WIP: reproducible optimizations

This commit is contained in:
Duncan Ogilvie 2021-08-23 16:18:39 +02:00
parent c768c59650
commit 2ce197a9b0
4 changed files with 15 additions and 4 deletions

View file

@ -29,6 +29,7 @@
#include <vtil/utility>
#include <functional>
#include <unordered_map>
#include <map>
#include <shared_mutex>
#include "../arch/identifier.hpp"
#include "instruction.hpp"
@ -74,7 +75,7 @@ namespace vtil
// Cache of explored blocks, mapping virtual instruction pointer to the basic block structure.
//
std::unordered_map<vip_t, basic_block*> explored_blocks;
std::map<vip_t, basic_block*> explored_blocks;
// Cache of paths from block A to block B.
//
@ -98,7 +99,7 @@ namespace vtil
// Convention of specialized calls, maps the vip of the VXCALL instruction onto the convention used.
//
std::unordered_map<vip_t, call_convention> spec_subroutine_conventions;
std::map<vip_t, call_convention> spec_subroutine_conventions;
// Misc. stats.
//

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@ -36,7 +36,7 @@
// Determine whether or not to use parallel transformations.
//
#ifndef VTIL_USE_PARALLEL_TRANSFORM
#define VTIL_USE_PARALLEL_TRANSFORM true
#define VTIL_USE_PARALLEL_TRANSFORM false
#endif
namespace vtil

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@ -48,11 +48,21 @@ namespace vtil::optimizer
//
cached_tracer local_tracer = {};
auto lbranch_info = aux::analyze_branch( blk, &local_tracer, {} );
auto log_branch_info = [](const auto& branch_info, const char* name) {
logger::log("\n%s, cc: %s, is_jcc: %d, is_vm_exit: %d\n", name, branch_info.cc, branch_info.is_jcc, branch_info.is_vm_exit);
for (const auto& dest : branch_info.destinations)
{
logger::log(" dest: %s\n", dest);
}
};
log_branch_info(lbranch_info, "lbranch_info");
ctracer.mtx.lock();
for ( auto& [k, v] : local_tracer.cache )
ctracer.cache[ k ] = v;
ctracer.mtx.unlock();
auto branch_info = aux::analyze_branch( blk, &ctracer, { .cross_block = true, .pack = true, .resolve_opaque = true } );
log_branch_info(branch_info, "branch_info");
// If branching to real, assert single next block.
//

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@ -36,7 +36,7 @@
// Determine whether we should log the details of the simplification process.
//
#ifndef VTIL_SYMEX_SIMPLIFY_VERBOSE
#define VTIL_SYMEX_SIMPLIFY_VERBOSE 0
#define VTIL_SYMEX_SIMPLIFY_VERBOSE 1
#endif
// [Configuration]