mirror of
https://github.com/angr/angr
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d46e56f891
* Fix signed division and remainder in the pcode engine OpBehaviorIntSdiv and OpBehaviorIntSrem used Claripy's `/` and `%`, which are unsigned bit-vector operations. For negative operands they therefore produced the same results as the unsigned INT_DIV and INT_REM behaviors. INT_SDIV now uses claripy.SDiv (truncation toward zero). INT_SREM is defined as in1 - SDiv(in1, in2) * in2, giving a remainder with the dividend's sign, which matches the p-code semantics documented in the class comments. For 64-bit -5 and 2, INT_SDIV now yields -2 (0xfffffffffffffffe) and INT_SREM yields -1 (0xffffffffffffffff) instead of large unsigned values. The arithmetic behavior test table enables both INT_SDIV and INT_SREM with the matching signed reference expressions, and a new concrete test checks mixed-sign combinations (-5/2, 5/-2, -5/-2, ...) that an unsigned implementation cannot satisfy. * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci * Use claripy.SMod for INT_SREM Per review, INT_SREM uses claripy.SMod directly instead of the equivalent in1 - claripy.SDiv(in1, in2) * in2. Verified identical to a truncated-toward-zero reference over 100k random 64-bit pairs, including the INT_MIN / -1 corner. * Address pcode signed arithmetic review comments * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
609 lines
20 KiB
Python
609 lines
20 KiB
Python
from __future__ import annotations
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import logging
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import operator
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import unittest
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from dataclasses import dataclass
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import claripy
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from pypcode import OpCode
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import angr
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from angr.engines import SimSuccessors
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from angr.engines.pcode.behavior import BehaviorFactory
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from angr.engines.pcode.emulate import PcodeEmulatorMixin
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from angr.sim_state import SimState
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log = logging.getLogger(__name__)
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@dataclass(eq=True)
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class MockAddrSpace:
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"""
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Mock AddrSpace
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"""
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name: str
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CONST_SPACE = MockAddrSpace("const")
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RAM_SPACE = MockAddrSpace("ram")
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REGISTER_SPACE = MockAddrSpace("register")
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UNIQUE_SPACE = MockAddrSpace("unique")
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@dataclass(eq=True)
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class MockVarnode:
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"""
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Mock Varnode
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"""
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space: MockAddrSpace
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offset: int
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size: int
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register_name: str = "<mock>"
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space_encoded_in_offset: MockAddrSpace | None = None
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def getRegisterName(self) -> str:
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return self.register_name
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def getSpaceFromConst(self) -> MockAddrSpace | None:
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return self.space_encoded_in_offset
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@dataclass(eq=True)
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class MockPcodeOp:
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"""
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Mock P-Code Op
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"""
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opcode: OpCode
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output: MockVarnode | None
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inputs: list[MockVarnode]
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BEHAVIORS = BehaviorFactory()
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@dataclass
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class MockIRSB:
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"""
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Mock IRSB
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"""
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_ops: list[MockPcodeOp]
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addr: int = 0
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behaviors: BehaviorFactory = BEHAVIORS
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jumpkind: str = "Ijk_Boring"
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OP = MockPcodeOp
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VN = MockVarnode
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class TestPcodeEmulatorMixin(unittest.TestCase):
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"""
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Test P-Code engine emulator mixin
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"""
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@staticmethod
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def _step_irsb(irsb, state=None):
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emulator = PcodeEmulatorMixin(angr.load_shellcode(b"\x90", arch="AMD64"))
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if state is None:
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state = SimState(arch=emulator.project.arch)
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emulator.state = state
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emulator.state.history.recent_bbl_addrs.append(0)
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emulator.successors = SimSuccessors(0, emulator.state)
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emulator.handle_pcode_block(irsb)
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emulator.successors.processed = True
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return emulator.successors
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def _test_branch_and_call_common(self, opcode: OpCode):
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target_addr = 0x12345678
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successors = self._step_irsb(
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MockIRSB(
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[
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OP(
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OpCode.IMARK,
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None,
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[VN(RAM_SPACE, 0, 1)],
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),
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OP(
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opcode,
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None,
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[VN(RAM_SPACE, target_addr, 1)],
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),
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]
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)
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)
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assert len(successors.all_successors) == 1
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state = successors.all_successors[0]
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assert state.solver.eval(state.regs.pc == target_addr)
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def test_branch(self):
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self._test_branch_and_call_common(OpCode.BRANCH)
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def test_call(self):
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self._test_branch_and_call_common(OpCode.CALL)
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def _test_branchind_and_callind_common(self, opcode: OpCode):
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target_addr = 0x12345678
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target_pointer_addr = 0x100000
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target_pointer_size = 8
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state = SimState(arch="AMD64")
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state.memory.store(target_pointer_addr, claripy.BVV(target_addr, 8 * target_pointer_size), endness="IEnd_LE")
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successors = self._step_irsb(
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MockIRSB(
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[
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OP(
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OpCode.IMARK,
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None,
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[VN(RAM_SPACE, 0, 1)],
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),
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OP(
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opcode,
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None,
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[VN(RAM_SPACE, target_pointer_addr, target_pointer_size)],
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),
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]
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),
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state,
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)
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assert len(successors.all_successors) == 1
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state = successors.all_successors[0]
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assert state.solver.eval(state.regs.pc == target_addr)
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def test_branchind(self):
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self._test_branchind_and_callind_common(OpCode.BRANCHIND)
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def test_callind(self):
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self._test_branchind_and_callind_common(OpCode.CALLIND)
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def _test_cbranch_common(self, cond: claripy.BVV):
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condition_addr = 0x100000
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target_addr = 0x12345678
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fallthru_addr = 1
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state = SimState(arch="AMD64")
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state.memory.store(condition_addr, cond)
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successors = self._step_irsb(
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MockIRSB(
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[
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OP(
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OpCode.IMARK,
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None,
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[VN(RAM_SPACE, 0, fallthru_addr)],
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),
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OP(
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OpCode.CBRANCH,
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None,
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[VN(RAM_SPACE, target_addr, 8), VN(RAM_SPACE, condition_addr, 1)],
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),
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]
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),
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state,
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)
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if cond.concrete:
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if state.solver.eval(cond):
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sat_pc, unsat_pc = target_addr, fallthru_addr
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else:
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sat_pc, unsat_pc = fallthru_addr, target_addr
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assert len(successors.successors) == 1
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state = successors.successors[0]
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assert state.solver.eval(state.regs.pc == sat_pc)
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assert len(successors.unsat_successors) == 1
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state = successors.unsat_successors[0]
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assert state.solver.eval(state.regs.pc == unsat_pc)
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else:
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assert len(successors.successors) == 2
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pcs = {state.solver.eval(state.regs.pc) for state in successors.successors}
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assert pcs == {target_addr, fallthru_addr}
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def test_cbranch_taken(self):
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self._test_cbranch_common(claripy.BVV(1, 8))
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self._test_cbranch_common(claripy.BVV(2, 8))
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def test_cbranch_not_taken(self):
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self._test_cbranch_common(claripy.BVV(0, 8))
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def test_cbranch_symbolic(self):
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self._test_cbranch_common(claripy.BVS("condition", 8))
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def _test_rel_cbranch_common(self, cond: claripy.BVV):
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condition_addr = 0x100000
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start_addr = 0
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target_addr = start_addr
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target_stmt = 1
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instruction_len = 1
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fallthru_addr = start_addr + instruction_len
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cbranch_idx = 2
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state = SimState(arch="AMD64")
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state.memory.store(condition_addr, cond)
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successors = self._step_irsb(
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MockIRSB(
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[
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# Op 0
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OP(
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OpCode.IMARK,
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None,
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[VN(RAM_SPACE, start_addr, instruction_len)],
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),
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# Op 1
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OP(
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OpCode.INT_ADD,
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VN(UNIQUE_SPACE, 0, 8),
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[VN(UNIQUE_SPACE, 0, 8), VN(CONST_SPACE, 1, 8)],
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),
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# Op 2
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OP(
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OpCode.CBRANCH,
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None,
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[VN(CONST_SPACE, target_stmt - cbranch_idx, 8), VN(RAM_SPACE, condition_addr, 1)],
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),
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]
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),
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state,
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)
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if cond.concrete:
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if state.solver.eval(cond):
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sat_pc, unsat_pc = target_addr, fallthru_addr
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sat_stmt, unsat_stmt = target_stmt, 0
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else:
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sat_pc, unsat_pc = fallthru_addr, target_addr
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sat_stmt, unsat_stmt = 0, target_stmt
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assert len(successors.successors) == 1
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state = successors.successors[0]
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assert state.solver.eval(state.regs.pc == sat_pc)
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assert state.scratch.statement_offset == sat_stmt
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assert len(successors.unsat_successors) == 1
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state = successors.unsat_successors[0]
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assert state.solver.eval(state.regs.pc == unsat_pc)
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assert state.scratch.statement_offset == unsat_stmt
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else:
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assert len(successors.successors) == 2
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pcs = {
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(state.solver.eval(state.regs.pc), state.scratch.statement_offset) for state in successors.successors
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}
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assert pcs == {(target_addr, target_stmt), (fallthru_addr, 0)}
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def test_rel_cbranch_taken(self):
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self._test_rel_cbranch_common(claripy.BVV(1, 8))
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self._test_rel_cbranch_common(claripy.BVV(2, 8))
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def test_rel_cbranch_not_taken(self):
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self._test_rel_cbranch_common(claripy.BVV(0, 8))
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def test_rel_cbranch_symbolic(self):
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self._test_cbranch_common(claripy.BVS("condition", 8))
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def test_load_store(self):
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addr = 0x133700000
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addr2 = 0x999900000
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value = claripy.BVV(0xFEDCBA9876543210, 64)
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state = SimState(arch="AMD64")
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state.memory.store(addr, value)
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state.regs.rax = addr
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# Load value from RAM[addr] and store it into RAM[addr2]
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successors = self._step_irsb(
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MockIRSB(
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[
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OP(
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OpCode.IMARK,
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None,
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[VN(RAM_SPACE, 0, 1)],
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),
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OP(
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OpCode.COPY,
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VN(UNIQUE_SPACE, 0, 8),
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[VN(CONST_SPACE, addr, 8)],
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),
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OP(
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OpCode.LOAD,
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VN(UNIQUE_SPACE, 8, 8),
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[VN(CONST_SPACE, 0xCACACACA, 0, space_encoded_in_offset=RAM_SPACE), VN(UNIQUE_SPACE, 0, 8)],
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),
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OP(
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OpCode.COPY,
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VN(UNIQUE_SPACE, 0, 8),
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[VN(CONST_SPACE, addr2, 8)],
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),
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OP(
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OpCode.STORE,
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None,
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[
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VN(CONST_SPACE, 0xCACACACA, 0, space_encoded_in_offset=RAM_SPACE),
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VN(UNIQUE_SPACE, 0, 8),
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VN(UNIQUE_SPACE, 8, 8),
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],
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),
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],
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),
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state,
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)
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new_state = successors.successors[0]
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assert new_state.solver.is_true(new_state.memory.load(addr2, 8) == value)
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def _test_single_arith_binary_op(self, opcode: OpCode):
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opcode_to_operation = {
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OpCode.BOOL_AND: operator.and_,
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OpCode.BOOL_OR: operator.or_,
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OpCode.BOOL_XOR: operator.xor,
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OpCode.INT_ADD: operator.add,
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OpCode.INT_AND: operator.and_,
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OpCode.INT_DIV: operator.floordiv,
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OpCode.INT_EQUAL: operator.eq,
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OpCode.INT_LEFT: operator.lshift,
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OpCode.INT_LESS: operator.lt,
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OpCode.INT_LESSEQUAL: operator.le,
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OpCode.INT_MULT: operator.mul,
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OpCode.INT_NOTEQUAL: operator.ne,
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OpCode.INT_OR: operator.or_,
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OpCode.INT_REM: operator.mod,
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OpCode.INT_RIGHT: claripy.LShR,
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OpCode.INT_SDIV: claripy.SDiv,
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OpCode.INT_SLESS: claripy.SLT,
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OpCode.INT_SLESSEQUAL: claripy.SLE,
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OpCode.INT_SREM: claripy.SMod,
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OpCode.INT_SRIGHT: operator.rshift,
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OpCode.INT_SUB: operator.sub,
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OpCode.INT_XOR: operator.xor,
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}
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operation = opcode_to_operation.get(opcode)
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assert operation is not None
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is_boolean = opcode in {OpCode.BOOL_AND, OpCode.BOOL_OR, OpCode.BOOL_XOR}
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is_comparison = opcode in {
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OpCode.INT_EQUAL,
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OpCode.INT_LESS,
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OpCode.INT_LESSEQUAL,
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OpCode.INT_NOTEQUAL,
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OpCode.INT_SLESS,
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OpCode.INT_SLESSEQUAL,
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}
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operand_size = 1 if is_boolean else 4
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result_addr = 0x100000
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result_size = 1 if is_comparison else operand_size
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x_addr, x = 0, claripy.BVS("x", operand_size * 8)
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y_addr, y = operand_size, claripy.BVS("y", operand_size * 8)
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state = SimState(arch="AMD64", remove_options={"SIMPLIFY_MEMORY_WRITES"})
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state.memory.store(x_addr, x, endness="Iend_LE")
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state.memory.store(y_addr, y, endness="Iend_LE")
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successors = self._step_irsb(
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MockIRSB(
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[
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OP(
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OpCode.IMARK,
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None,
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[VN(RAM_SPACE, 0, 1)],
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),
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OP(
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opcode,
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VN(RAM_SPACE, result_addr, operand_size),
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[VN(RAM_SPACE, x_addr, operand_size), VN(RAM_SPACE, y_addr, operand_size)],
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),
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]
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),
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state,
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)
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assert len(successors.all_successors) == 1
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state = successors.all_successors[0]
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assert state.solver.eval(state.regs.pc == 1)
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result = state.memory.load(result_addr, result_size, endness="Iend_LE")
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if is_boolean:
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booleanize = angr.engines.pcode.behavior.OpBehavior.booleanize
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expected_result = operation(booleanize(x), booleanize(y)).zero_extend(7)
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elif is_comparison:
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expected_result = claripy.If(operation(x, y), claripy.BVV(1, 1), claripy.BVV(0, 1)).zero_extend(7)
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else:
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expected_result = operation(x, y)
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solver = claripy.Solver()
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assert solver.is_true(result == expected_result)
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def test_arith_binary_ops(self):
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for opcode in [
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OpCode.BOOL_AND,
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OpCode.BOOL_OR,
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OpCode.BOOL_XOR,
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OpCode.INT_ADD,
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OpCode.INT_AND,
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OpCode.INT_DIV,
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OpCode.INT_EQUAL,
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OpCode.INT_LEFT,
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OpCode.INT_LESS,
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OpCode.INT_LESSEQUAL,
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OpCode.INT_MULT,
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OpCode.INT_NOTEQUAL,
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OpCode.INT_OR,
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OpCode.INT_REM,
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OpCode.INT_RIGHT,
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OpCode.INT_SDIV,
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OpCode.INT_SLESS,
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OpCode.INT_SLESSEQUAL,
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OpCode.INT_SREM,
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OpCode.INT_SRIGHT,
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OpCode.INT_SUB,
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OpCode.INT_XOR,
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]:
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with self.subTest(opcode):
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self._test_single_arith_binary_op(opcode)
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def _test_single_arith_unary_op(self, opcode: OpCode):
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opcode_to_operation = {
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OpCode.INT_NEGATE: operator.inv,
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OpCode.INT_2COMP: operator.neg,
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}
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operation = opcode_to_operation.get(opcode)
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assert operation is not None
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operand_size = 4
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result_size = operand_size
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result_addr = 0x100000
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x_addr, x = 0, claripy.BVS("x", operand_size * 8)
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state = SimState(arch="AMD64", remove_options={"SIMPLIFY_MEMORY_WRITES"})
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state.memory.store(x_addr, x, endness="Iend_LE")
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successors = self._step_irsb(
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MockIRSB(
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[
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OP(
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OpCode.IMARK,
|
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None,
|
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[VN(RAM_SPACE, 0, 1)],
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),
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OP(
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opcode,
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VN(RAM_SPACE, result_addr, operand_size),
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[VN(RAM_SPACE, x_addr, operand_size)],
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),
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]
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),
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state,
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)
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assert len(successors.all_successors) == 1
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state = successors.all_successors[0]
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assert state.solver.eval(state.regs.pc == 1)
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result = state.memory.load(result_addr, result_size, endness="Iend_LE")
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expected_result = operation(x)
|
|
|
|
assert claripy.Solver().is_true(result == expected_result)
|
|
|
|
def test_arith_unary_ops(self):
|
|
for opcode in [
|
|
OpCode.INT_NEGATE,
|
|
OpCode.INT_2COMP,
|
|
]:
|
|
with self.subTest(opcode):
|
|
self._test_single_arith_unary_op(opcode)
|
|
|
|
def _test_other_unary_common(self, opcode, input_value, expected_value):
|
|
operand_addr = 0x200000
|
|
operand_size = input_value.size() // 8
|
|
|
|
result_addr = 0x100000
|
|
result_size = expected_value.size() // 8
|
|
|
|
state = SimState(arch="AMD64", remove_options={"SIMPLIFY_MEMORY_WRITES"})
|
|
state.memory.store(operand_addr, input_value, endness="Iend_LE")
|
|
state.memory.store(result_addr, claripy.BVV(b"\xca" * result_size), endness="Iend_LE")
|
|
|
|
successors = self._step_irsb(
|
|
MockIRSB(
|
|
[
|
|
OP(
|
|
OpCode.IMARK,
|
|
None,
|
|
[VN(RAM_SPACE, 0, 1)],
|
|
),
|
|
OP(
|
|
opcode,
|
|
VN(RAM_SPACE, result_addr, result_size),
|
|
[VN(RAM_SPACE, operand_addr, operand_size)],
|
|
),
|
|
],
|
|
),
|
|
state,
|
|
)
|
|
|
|
assert len(successors.all_successors) == 1
|
|
state = successors.successors[0]
|
|
v = state.memory.load(result_addr, result_size, endness="Iend_LE")
|
|
assert state.solver.eval(v == expected_value)
|
|
|
|
def test_bool_negate(self):
|
|
# FIXME: Should values >1 be considered true? If some op only clears the 0th bit this may be incorrect
|
|
self._test_other_unary_common(OpCode.BOOL_NEGATE, claripy.BVV(0, 8), claripy.BVV(1, 8))
|
|
self._test_other_unary_common(OpCode.BOOL_NEGATE, claripy.BVV(1, 8), claripy.BVV(0, 8))
|
|
self._test_other_unary_common(OpCode.BOOL_NEGATE, claripy.BVV(0xFF, 8), claripy.BVV(0, 8))
|
|
|
|
def test_zext(self):
|
|
self._test_other_unary_common(OpCode.INT_ZEXT, claripy.BVV(0x7234, 16), claripy.BVV(0x7234, 16))
|
|
self._test_other_unary_common(OpCode.INT_ZEXT, claripy.BVV(0x7234, 16), claripy.BVV(0x0000_7234, 32))
|
|
self._test_other_unary_common(OpCode.INT_ZEXT, claripy.BVV(0x8234, 16), claripy.BVV(0x0000_8234, 32))
|
|
|
|
def test_sext(self):
|
|
self._test_other_unary_common(OpCode.INT_SEXT, claripy.BVV(0x7234, 16), claripy.BVV(0x7234, 16))
|
|
self._test_other_unary_common(OpCode.INT_SEXT, claripy.BVV(0x7234, 16), claripy.BVV(0x0000_7234, 32))
|
|
self._test_other_unary_common(OpCode.INT_SEXT, claripy.BVV(0x8234, 16), claripy.BVV(0xFFFF_8234, 32))
|
|
|
|
def test_popcount(self):
|
|
self._test_other_unary_common(OpCode.POPCOUNT, claripy.BVV(0, 32), claripy.BVV(0, 32))
|
|
self._test_other_unary_common(OpCode.POPCOUNT, claripy.BVV(0x12345678, 32), claripy.BVV(13, 32))
|
|
self._test_other_unary_common(OpCode.POPCOUNT, claripy.BVV(0xFFFFFFFF, 32), claripy.BVV(32, 32))
|
|
|
|
def test_lzcount(self):
|
|
self._test_other_unary_common(OpCode.LZCOUNT, claripy.BVV(0xFFFF, 16), claripy.BVV(0, 16))
|
|
self._test_other_unary_common(OpCode.LZCOUNT, claripy.BVV(0x7FFF, 16), claripy.BVV(1, 16))
|
|
self._test_other_unary_common(OpCode.LZCOUNT, claripy.BVV(0x3F0F, 16), claripy.BVV(2, 16))
|
|
self._test_other_unary_common(OpCode.LZCOUNT, claripy.BVV(0x0080, 16), claripy.BVV(8, 16))
|
|
self._test_other_unary_common(OpCode.LZCOUNT, claripy.BVV(0x0001, 16), claripy.BVV(15, 16))
|
|
self._test_other_unary_common(OpCode.LZCOUNT, claripy.BVV(0x0000, 16), claripy.BVV(16, 16))
|
|
|
|
# TODO: Add tests for the following ops:
|
|
# * = FIXME
|
|
# ! = Not Implemented
|
|
#
|
|
# ! OpCode.CPOOLREF
|
|
# OpCode.FLOAT_ABS
|
|
# OpCode.FLOAT_ADD
|
|
# OpCode.FLOAT_CEIL
|
|
# OpCode.FLOAT_DIV
|
|
# OpCode.FLOAT_EQUAL
|
|
# OpCode.FLOAT_FLOAT2FLOAT
|
|
# OpCode.FLOAT_FLOOR
|
|
# OpCode.FLOAT_INT2FLOAT
|
|
# OpCode.FLOAT_LESS
|
|
# OpCode.FLOAT_LESSEQUAL
|
|
# OpCode.FLOAT_MULT
|
|
# OpCode.FLOAT_NAN
|
|
# OpCode.FLOAT_NEG
|
|
# OpCode.FLOAT_NOTEQUAL
|
|
# OpCode.FLOAT_ROUND
|
|
# OpCode.FLOAT_SQRT
|
|
# OpCode.FLOAT_SUB
|
|
# OpCode.FLOAT_TRUNC
|
|
# OpCode.INT_CARRY
|
|
# OpCode.INT_SBORROW
|
|
# OpCode.INT_SCARRY
|
|
# ! OpCode.NEW
|
|
# OpCode.RETURN
|
|
|
|
|
|
if __name__ == "__main__":
|
|
log.setLevel(logging.DEBUG)
|
|
logging.getLogger("angr.engines.pcode").setLevel(logging.DEBUG)
|
|
unittest.main()
|