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* Enable ruff isort rule * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
64 lines
1.9 KiB
Python
64 lines
1.9 KiB
Python
#!/usr/bin/env python3
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# pylint: disable=missing-class-docstring,disable=no-self-use
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from __future__ import annotations
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__package__ = __package__ or "tests.analyses" # pylint:disable=redefined-builtin
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import os
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import unittest
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import angr
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from angr.analyses.propagator.vex_vars import VEXReg
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from tests.common import bin_location
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test_location = os.path.join(bin_location, "tests")
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class TestFCP(unittest.TestCase):
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def test_lwip_udpecho_bm(self):
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bin_path = os.path.join(test_location, "armel", "lwip_udpecho_bm.elf")
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p = angr.Project(bin_path, auto_load_libs=False)
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cfg = p.analyses.CFG()
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func = cfg.functions[0x23C9]
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prop = p.analyses.FastConstantPropagation(func)
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assert len(prop.replacements) > 0
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def test_register_propagation_across_calls(self):
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call_targets = [
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"syscall",
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"call _0", # Resolved
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"call rdi", # TOP
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"call qword ptr [0xBAD]", # Unresolved
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]
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for target in call_targets:
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p = angr.load_shellcode(
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f"""
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_0:
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mov rcx, 0x12345678
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mov rbp, 0xFEDCBA90
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_11:
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{target}
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mov rax, rcx
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mov rdi, rbp
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ret
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""",
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"AMD64",
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)
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cfg = p.analyses.CFG()
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prop = p.analyses.FastConstantPropagation(func=cfg.functions[0])
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regs_replaced = {
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p.arch.register_names[var.offset]: val
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for codeloc, replacements in prop.replacements.items()
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if codeloc.block_addr >= 0x11
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for var, val in replacements.items()
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if isinstance(var, VEXReg)
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}
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assert "rax" not in regs_replaced # caller saved
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assert regs_replaced["rdi"] == 0xFEDCBA90 # callee saved
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if __name__ == "__main__":
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unittest.main()
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