mirror of
https://github.com/capstone-engine/capstone
synced 2026-08-11 16:26:07 -04:00
Constify backend data (#1040)
* Constify string literals Use -Wwrite-strings to force string literals to be of type "const char[]", then fix up all warning fallout. * Constify common infrastructure Step one in allowing backend data to be readonly. Minimal changes to backends for now; just set all pointers in common structs that aren't modified to const. * Constify AArch64 backend Section size changes within libcapstone.so are -.rodata 602587 -.data.rel.ro 228416 -.data 1003746 +.rodata 769051 +.data.rel.ro 241120 +.data 824578 * Constify ARM backend Section size changes within libcapstone.so are -.rodata 769051 -.data.rel.ro 241120 -.data 824578 +.rodata 959835 +.data.rel.ro 245120 +.data 629506 * Constify Mips backend Section size changes within libcapstone.so are -.rodata 959835 -.data.rel.ro 245120 -.data 629506 +.rodata 1069851 +.data.rel.ro 256416 +.data 508194 * Constify PowerPC backend Section size changes within libcapstone.so are -.rodata 1069851 -.data.rel.ro 256416 -.data 508194 +.rodata 1142715 +.data.rel.ro 272224 +.data 419490 * Constify Sparc backend Section size changes within libcapstone.so are -.rodata 1142715 -.data.rel.ro 272224 -.data 419490 +.rodata 1175227 +.data.rel.ro 277536 +.data 381666 * Constify SystemZ backend Section size changes within libcapstone.so are -.rodata 1175227 -.data.rel.ro 277536 -.data 381666 +.rodata 1221883 +.data.rel.ro 278016 +.data 334498 * Constify X86 backend Section size changes within libcapstone.so are -.rodata 1221883 -.data.rel.ro 278016 -.data 334498 +.rodata 1533531 +.data.rel.ro 281184 +.data 19714 * Constify XCore backend Section size changes within libcapstone.so are -.rodata 1533531 -.data.rel.ro 281184 -.data 19714 +.rodata 1553026 +.data.rel.ro 281280 +.data 40
This commit is contained in:
Richard Henderson
Nguyen Anh Quynh
parent
8998a3a1d5
commit
22ead3e0bf
65 changed files with 1565 additions and 1565 deletions
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@ -5,14 +5,14 @@
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/// isPredicate - Set if this is one of the operands that made up of
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/// the predicate operand that controls an isPredicable() instruction.
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bool MCOperandInfo_isPredicate(MCOperandInfo *m)
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bool MCOperandInfo_isPredicate(const MCOperandInfo *m)
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{
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return m->Flags & (1 << MCOI_Predicate);
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}
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/// isOptionalDef - Set if this operand is a optional def.
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///
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bool MCOperandInfo_isOptionalDef(MCOperandInfo *m)
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bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m)
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{
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return m->Flags & (1 << MCOI_OptionalDef);
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}
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@ -130,7 +130,7 @@ typedef struct MCInstrDesc {
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uint64_t TSFlags; // Target Specific Flag values
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char ImplicitUses; // Registers implicitly read by this instr
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char ImplicitDefs; // Registers implicitly defined by this instr
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MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
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uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
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// A complex method to determine is a certain is deprecated or not, and return
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// the reason for deprecation.
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@ -138,8 +138,8 @@ typedef struct MCInstrDesc {
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unsigned char ComplexDeprecationInfo; // dummy field, just to satisfy initializer
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} MCInstrDesc;
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bool MCOperandInfo_isPredicate(MCOperandInfo *m);
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bool MCOperandInfo_isPredicate(const MCOperandInfo *m);
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bool MCOperandInfo_isOptionalDef(MCOperandInfo *m);
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bool MCOperandInfo_isOptionalDef(const MCOperandInfo *m);
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#endif
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@ -22,18 +22,18 @@
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/// defined below.
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typedef struct DiffListIterator {
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uint16_t Val;
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MCPhysReg *List;
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const MCPhysReg *List;
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} DiffListIterator;
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void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
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MCRegisterDesc *D, unsigned NR,
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const MCRegisterDesc *D, unsigned NR,
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unsigned RA, unsigned PC,
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MCRegisterClass *C, unsigned NC,
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const MCRegisterClass *C, unsigned NC,
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uint16_t (*RURoots)[2], unsigned NRU,
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MCPhysReg *DL,
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char *Strings,
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uint16_t *SubIndices, unsigned NumIndices,
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uint16_t *RET)
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const MCPhysReg *DL,
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const char *Strings,
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const uint16_t *SubIndices, unsigned NumIndices,
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const uint16_t *RET)
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{
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RI->Desc = D;
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RI->NumRegs = NR;
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@ -50,7 +50,7 @@ void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
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RI->RegEncodingTable = RET;
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}
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static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, MCPhysReg *DiffList)
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static void DiffListIterator_init(DiffListIterator *d, MCPhysReg InitVal, const MCPhysReg *DiffList)
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{
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d->Val = InitVal;
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d->List = DiffList;
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@ -83,7 +83,7 @@ static bool DiffListIterator_isValid(DiffListIterator *d)
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return (d->List != 0);
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}
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unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC)
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unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC)
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{
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DiffListIterator iter;
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@ -105,10 +105,10 @@ unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, un
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return 0;
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}
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unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
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unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx)
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{
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DiffListIterator iter;
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uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
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const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices;
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DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs);
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DiffListIterator_next(&iter);
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@ -123,7 +123,7 @@ unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx
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return 0;
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}
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MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
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const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
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{
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//assert(i < getNumRegClasses() && "Register Class ID out of range");
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if (i >= RI->NumClasses)
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@ -131,7 +131,7 @@ MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i)
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return &(RI->Classes[i]);
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}
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bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg)
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bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg)
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{
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unsigned InByte = Reg % 8;
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unsigned Byte = Reg / 8;
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@ -27,12 +27,12 @@
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/// An unsigned integer type large enough to represent all physical registers,
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/// but not necessarily virtual registers.
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typedef uint16_t MCPhysReg;
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typedef MCPhysReg* iterator;
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typedef const MCPhysReg* iterator;
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typedef struct MCRegisterClass {
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char *Name;
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const char *Name;
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iterator RegsBegin;
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uint8_t *RegSet;
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const uint8_t *RegSet;
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uint16_t RegsSize;
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uint16_t RegSetSize;
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uint16_t ID;
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@ -75,42 +75,42 @@ typedef struct MCRegisterDesc {
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/// virtual methods.
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///
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typedef struct MCRegisterInfo {
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MCRegisterDesc *Desc; // Pointer to the descriptor array
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const MCRegisterDesc *Desc; // Pointer to the descriptor array
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unsigned NumRegs; // Number of entries in the array
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unsigned RAReg; // Return address register
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unsigned PCReg; // Program counter register
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MCRegisterClass *Classes; // Pointer to the regclass array
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const MCRegisterClass *Classes; // Pointer to the regclass array
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unsigned NumClasses; // Number of entries in the array
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unsigned NumRegUnits; // Number of regunits.
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uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
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MCPhysReg *DiffLists; // Pointer to the difflists array
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char *RegStrings; // Pointer to the string table.
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uint16_t *SubRegIndices; // Pointer to the subreg lookup
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const MCPhysReg *DiffLists; // Pointer to the difflists array
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const char *RegStrings; // Pointer to the string table.
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const uint16_t *SubRegIndices; // Pointer to the subreg lookup
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// array.
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unsigned NumSubRegIndices; // Number of subreg indices.
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uint16_t *RegEncodingTable; // Pointer to array of register
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const uint16_t *RegEncodingTable; // Pointer to array of register
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// encodings.
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} MCRegisterInfo;
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void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
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MCRegisterDesc *D, unsigned NR, unsigned RA,
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const MCRegisterDesc *D, unsigned NR, unsigned RA,
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unsigned PC,
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MCRegisterClass *C, unsigned NC,
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const MCRegisterClass *C, unsigned NC,
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uint16_t (*RURoots)[2],
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unsigned NRU,
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MCPhysReg *DL,
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char *Strings,
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uint16_t *SubIndices,
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const MCPhysReg *DL,
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const char *Strings,
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const uint16_t *SubIndices,
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unsigned NumIndices,
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uint16_t *RET);
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const uint16_t *RET);
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unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC);
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unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);
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unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
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unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
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MCRegisterClass* MCRegisterInfo_getRegClass(MCRegisterInfo *RI, unsigned i);
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const MCRegisterClass* MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i);
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bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg);
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bool MCRegisterClass_contains(const MCRegisterClass *c, unsigned Reg);
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#endif
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2
Makefile
2
Makefile
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@ -37,7 +37,7 @@ ifneq (,$(findstring yes,$(CAPSTONE_X86_ATT_DISABLE)))
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CFLAGS += -DCAPSTONE_X86_ATT_DISABLE
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endif
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CFLAGS += -fPIC -Wall -Iinclude
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CFLAGS += -fPIC -Wall -Wwrite-strings -Iinclude
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ifeq ($(CAPSTONE_USE_SYS_DYN_MEM),yes)
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CFLAGS += -DCAPSTONE_USE_SYS_DYN_MEM
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@ -28,7 +28,7 @@ void SStream_Init(SStream *ss)
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ss->buffer[0] = '\0';
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}
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void SStream_concat0(SStream *ss, char *s)
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void SStream_concat0(SStream *ss, const char *s)
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{
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#ifndef CAPSTONE_DIET
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unsigned int len = (unsigned int) strlen(s);
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@ -13,7 +13,7 @@ void SStream_Init(SStream *ss);
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void SStream_concat(SStream *ss, const char *fmt, ...);
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void SStream_concat0(SStream *ss, char *s);
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void SStream_concat0(SStream *ss, const char *s);
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void printInt64Bang(SStream *O, int64_t val);
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@ -28,7 +28,7 @@
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#include "AArch64BaseInfo.h"
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char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid)
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const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
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{
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unsigned i;
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for (i = 0; i < N->NumPairs; ++i) {
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@ -44,7 +44,7 @@ char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Val
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// compare s1 with lower(s2)
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// return true if s1 == lower(f2), and false otherwise
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static bool compare_lower_str(char *s1, char *s2)
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static bool compare_lower_str(const char *s1, const char *s2)
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{
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bool res;
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char *lower = cs_strdup(s2), *c;
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@ -57,7 +57,7 @@ static bool compare_lower_str(char *s1, char *s2)
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return res;
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}
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uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid)
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uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid)
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{
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unsigned i;
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for (i = 0; i < N->NumPairs; ++i) {
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@ -71,7 +71,7 @@ uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Va
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return (uint32_t)-1;
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}
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bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value)
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bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value)
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{
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return Value < N->TooBigImm;
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}
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@ -98,7 +98,7 @@ static char *utostr(uint64_t X, bool isNeg)
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return result;
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}
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static A64NamedImmMapper_Mapping SysRegPairs[] = {
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static const A64NamedImmMapper_Mapping SysRegPairs[] = {
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{"pan", A64SysReg_PAN},
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{"uao", A64SysReg_UAO},
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{"osdtrrx_el1", A64SysReg_OSDTRRX_EL1},
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@ -622,12 +622,12 @@ static A64NamedImmMapper_Mapping SysRegPairs[] = {
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{"pmslatfr_el1", A64SysReg_PMSLATFR_EL1}
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};
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static A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
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static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
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{"cpm_ioacc_ctl_el3", A64SysReg_CPM_IOACC_CTL_EL3}
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};
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// result must be a big enough buffer: 128 bytes is more than enough
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void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
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void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
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{
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int dummy;
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uint32_t Op0, Op1, CRn, CRm, Op2;
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@ -697,7 +697,7 @@ void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, ch
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cs_mem_free(Op2S);
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}
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static A64NamedImmMapper_Mapping TLBIPairs[] = {
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static const A64NamedImmMapper_Mapping TLBIPairs[] = {
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{"ipas2e1is", A64TLBI_IPAS2E1IS},
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{"ipas2le1is", A64TLBI_IPAS2LE1IS},
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{"vmalle1is", A64TLBI_VMALLE1IS},
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@ -732,13 +732,13 @@ static A64NamedImmMapper_Mapping TLBIPairs[] = {
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{"vaale1", A64TLBI_VAALE1}
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};
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A64NamedImmMapper A64TLBI_TLBIMapper = {
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const A64NamedImmMapper A64TLBI_TLBIMapper = {
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TLBIPairs,
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ARR_SIZE(TLBIPairs),
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0,
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};
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static A64NamedImmMapper_Mapping ATPairs[] = {
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static const A64NamedImmMapper_Mapping ATPairs[] = {
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{"s1e1r", A64AT_S1E1R},
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{"s1e2r", A64AT_S1E2R},
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{"s1e3r", A64AT_S1E3R},
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@ -753,13 +753,13 @@ static A64NamedImmMapper_Mapping ATPairs[] = {
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{"s12e0w", A64AT_S12E0W}
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};
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A64NamedImmMapper A64AT_ATMapper = {
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const A64NamedImmMapper A64AT_ATMapper = {
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ATPairs,
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ARR_SIZE(ATPairs),
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0,
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};
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static A64NamedImmMapper_Mapping DBarrierPairs[] = {
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static const A64NamedImmMapper_Mapping DBarrierPairs[] = {
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{"oshld", A64DB_OSHLD},
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{"oshst", A64DB_OSHST},
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{"osh", A64DB_OSH},
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@ -774,13 +774,13 @@ static A64NamedImmMapper_Mapping DBarrierPairs[] = {
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{"sy", A64DB_SY}
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};
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A64NamedImmMapper A64DB_DBarrierMapper = {
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const A64NamedImmMapper A64DB_DBarrierMapper = {
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DBarrierPairs,
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ARR_SIZE(DBarrierPairs),
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16,
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};
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static A64NamedImmMapper_Mapping DCPairs[] = {
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static const A64NamedImmMapper_Mapping DCPairs[] = {
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{"zva", A64DC_ZVA},
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{"ivac", A64DC_IVAC},
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{"isw", A64DC_ISW},
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@ -791,35 +791,35 @@ static A64NamedImmMapper_Mapping DCPairs[] = {
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{"cisw", A64DC_CISW}
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};
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A64NamedImmMapper A64DC_DCMapper = {
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const A64NamedImmMapper A64DC_DCMapper = {
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DCPairs,
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ARR_SIZE(DCPairs),
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0,
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};
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static A64NamedImmMapper_Mapping ICPairs[] = {
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static const A64NamedImmMapper_Mapping ICPairs[] = {
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{"ialluis", A64IC_IALLUIS},
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{"iallu", A64IC_IALLU},
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{"ivau", A64IC_IVAU}
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};
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A64NamedImmMapper A64IC_ICMapper = {
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const A64NamedImmMapper A64IC_ICMapper = {
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ICPairs,
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ARR_SIZE(ICPairs),
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0,
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};
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static A64NamedImmMapper_Mapping ISBPairs[] = {
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static const A64NamedImmMapper_Mapping ISBPairs[] = {
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{"sy", A64DB_SY},
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};
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A64NamedImmMapper A64ISB_ISBMapper = {
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const A64NamedImmMapper A64ISB_ISBMapper = {
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ISBPairs,
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ARR_SIZE(ISBPairs),
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16,
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};
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static A64NamedImmMapper_Mapping PRFMPairs[] = {
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static const A64NamedImmMapper_Mapping PRFMPairs[] = {
|
||||
{"pldl1keep", A64PRFM_PLDL1KEEP},
|
||||
{"pldl1strm", A64PRFM_PLDL1STRM},
|
||||
{"pldl2keep", A64PRFM_PLDL2KEEP},
|
||||
|
|
@ -840,13 +840,13 @@ static A64NamedImmMapper_Mapping PRFMPairs[] = {
|
|||
{"pstl3strm", A64PRFM_PSTL3STRM}
|
||||
};
|
||||
|
||||
A64NamedImmMapper A64PRFM_PRFMMapper = {
|
||||
const A64NamedImmMapper A64PRFM_PRFMMapper = {
|
||||
PRFMPairs,
|
||||
ARR_SIZE(PRFMPairs),
|
||||
32,
|
||||
};
|
||||
|
||||
static A64NamedImmMapper_Mapping PStatePairs[] = {
|
||||
static const A64NamedImmMapper_Mapping PStatePairs[] = {
|
||||
{"spsel", A64PState_SPSel},
|
||||
{"daifset", A64PState_DAIFSet},
|
||||
{"daifclr", A64PState_DAIFClr},
|
||||
|
|
@ -854,13 +854,13 @@ static A64NamedImmMapper_Mapping PStatePairs[] = {
|
|||
{"uao", A64PState_UAO}
|
||||
};
|
||||
|
||||
A64NamedImmMapper A64PState_PStateMapper = {
|
||||
const A64NamedImmMapper A64PState_PStateMapper = {
|
||||
PStatePairs,
|
||||
ARR_SIZE(PStatePairs),
|
||||
0,
|
||||
};
|
||||
|
||||
static A64NamedImmMapper_Mapping MRSPairs[] = {
|
||||
static const A64NamedImmMapper_Mapping MRSPairs[] = {
|
||||
{"mdccsr_el0", A64SysReg_MDCCSR_EL0},
|
||||
{"dbgdtrrx_el0", A64SysReg_DBGDTRRX_EL0},
|
||||
{"mdrar_el1", A64SysReg_MDRAR_EL1},
|
||||
|
|
@ -966,13 +966,13 @@ static A64NamedImmMapper_Mapping MRSPairs[] = {
|
|||
{"pmbidr_el1", A64SysReg_PMBIDR_EL1}
|
||||
};
|
||||
|
||||
A64SysRegMapper AArch64_MRSMapper = {
|
||||
const A64SysRegMapper AArch64_MRSMapper = {
|
||||
NULL,
|
||||
MRSPairs,
|
||||
ARR_SIZE(MRSPairs),
|
||||
};
|
||||
|
||||
static A64NamedImmMapper_Mapping MSRPairs[] = {
|
||||
static const A64NamedImmMapper_Mapping MSRPairs[] = {
|
||||
{"dbgdtrtx_el0", A64SysReg_DBGDTRTX_EL0},
|
||||
{"oslar_el1", A64SysReg_OSLAR_EL1},
|
||||
{"pmswinc_el0", A64SysReg_PMSWINC_EL0},
|
||||
|
|
@ -990,7 +990,7 @@ static A64NamedImmMapper_Mapping MSRPairs[] = {
|
|||
{"icc_sgi0r_el1", A64SysReg_ICC_SGI0R_EL1}
|
||||
};
|
||||
|
||||
A64SysRegMapper AArch64_MSRMapper = {
|
||||
const A64SysRegMapper AArch64_MSRMapper = {
|
||||
NULL,
|
||||
MSRPairs,
|
||||
ARR_SIZE(MSRPairs),
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ typedef enum A64CC_CondCode { // Meaning (integer) Meaning (floating-point)
|
|||
A64CC_Invalid
|
||||
} A64CC_CondCode;
|
||||
|
||||
inline static char *getCondCodeName(A64CC_CondCode CC)
|
||||
inline static const char *getCondCodeName(A64CC_CondCode CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: return NULL; // never reach
|
||||
|
|
@ -139,33 +139,33 @@ inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code)
|
|||
/// might even be optimal to just reorder the tables for the common instructions
|
||||
/// rather than changing the algorithm.
|
||||
typedef struct A64NamedImmMapper_Mapping {
|
||||
char *Name;
|
||||
const char *Name;
|
||||
uint32_t Value;
|
||||
} A64NamedImmMapper_Mapping;
|
||||
|
||||
typedef struct A64NamedImmMapper {
|
||||
A64NamedImmMapper_Mapping *Pairs;
|
||||
const A64NamedImmMapper_Mapping *Pairs;
|
||||
size_t NumPairs;
|
||||
uint32_t TooBigImm;
|
||||
} A64NamedImmMapper;
|
||||
|
||||
typedef struct A64SysRegMapper {
|
||||
A64NamedImmMapper_Mapping *SysRegPairs;
|
||||
A64NamedImmMapper_Mapping *InstPairs;
|
||||
const A64NamedImmMapper_Mapping *SysRegPairs;
|
||||
const A64NamedImmMapper_Mapping *InstPairs;
|
||||
size_t NumInstPairs;
|
||||
} A64SysRegMapper;
|
||||
|
||||
extern A64SysRegMapper AArch64_MSRMapper;
|
||||
extern A64SysRegMapper AArch64_MRSMapper;
|
||||
extern const A64SysRegMapper AArch64_MSRMapper;
|
||||
extern const A64SysRegMapper AArch64_MRSMapper;
|
||||
|
||||
extern A64NamedImmMapper A64DB_DBarrierMapper;
|
||||
extern A64NamedImmMapper A64AT_ATMapper;
|
||||
extern A64NamedImmMapper A64DC_DCMapper;
|
||||
extern A64NamedImmMapper A64IC_ICMapper;
|
||||
extern A64NamedImmMapper A64ISB_ISBMapper;
|
||||
extern A64NamedImmMapper A64PRFM_PRFMMapper;
|
||||
extern A64NamedImmMapper A64PState_PStateMapper;
|
||||
extern A64NamedImmMapper A64TLBI_TLBIMapper;
|
||||
extern const A64NamedImmMapper A64DB_DBarrierMapper;
|
||||
extern const A64NamedImmMapper A64AT_ATMapper;
|
||||
extern const A64NamedImmMapper A64DC_DCMapper;
|
||||
extern const A64NamedImmMapper A64IC_ICMapper;
|
||||
extern const A64NamedImmMapper A64ISB_ISBMapper;
|
||||
extern const A64NamedImmMapper A64PRFM_PRFMMapper;
|
||||
extern const A64NamedImmMapper A64PState_PStateMapper;
|
||||
extern const A64NamedImmMapper A64TLBI_TLBIMapper;
|
||||
|
||||
enum {
|
||||
A64AT_Invalid = -1, // Op0 Op1 CRn CRm Op2
|
||||
|
|
@ -293,7 +293,7 @@ typedef enum A64Layout_VectorLayout {
|
|||
A64Layout_VL_D
|
||||
} A64Layout_VectorLayout;
|
||||
|
||||
inline static char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
|
||||
inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout)
|
||||
{
|
||||
switch (Layout) {
|
||||
case A64Layout_VL_8B: return ".8b";
|
||||
|
|
@ -1002,12 +1002,12 @@ enum A64TLBIValues {
|
|||
|
||||
bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm);
|
||||
|
||||
char *A64NamedImmMapper_toString(A64NamedImmMapper *N, uint32_t Value, bool *Valid);
|
||||
const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid);
|
||||
|
||||
uint32_t A64NamedImmMapper_fromString(A64NamedImmMapper *N, char *Name, bool *Valid);
|
||||
uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid);
|
||||
|
||||
bool A64NamedImmMapper_validImm(A64NamedImmMapper *N, uint32_t Value);
|
||||
bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value);
|
||||
|
||||
void A64SysRegMapper_toString(A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
|
||||
void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -38,143 +38,143 @@
|
|||
// Definitions are further down.
|
||||
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
|
||||
uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
|
||||
uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
|
||||
uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
|
||||
uint32_t insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder);
|
||||
const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder);
|
||||
uint64_t Addr, const void *Decoder);
|
||||
|
||||
static bool Check(DecodeStatus *Out, DecodeStatus In)
|
||||
{
|
||||
|
|
@ -280,7 +280,7 @@ static const unsigned FPR128DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
if (RegNo > 31)
|
||||
|
|
@ -293,7 +293,7 @@ static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
|
|||
|
||||
static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
if (RegNo > 15)
|
||||
return Fail;
|
||||
|
|
@ -313,7 +313,7 @@ static const unsigned FPR64DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -337,7 +337,7 @@ static const unsigned FPR32DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -361,7 +361,7 @@ static const unsigned FPR16DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -385,7 +385,7 @@ static const unsigned FPR8DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -409,7 +409,7 @@ static const unsigned GPR64DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -423,7 +423,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
|
|||
|
||||
static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -451,7 +451,7 @@ static const unsigned GPR32DecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -465,7 +465,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
|
|||
|
||||
static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -492,7 +492,7 @@ static const unsigned VectorDecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -516,7 +516,7 @@ static const unsigned QQDecoderTable[] = {
|
|||
};
|
||||
|
||||
static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -543,7 +543,7 @@ static const unsigned QQQDecoderTable[] = {
|
|||
};
|
||||
|
||||
static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -571,7 +571,7 @@ static const unsigned QQQQDecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
if (RegNo > 31)
|
||||
|
|
@ -594,7 +594,7 @@ static const unsigned DDDecoderTable[] = {
|
|||
};
|
||||
|
||||
static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -621,7 +621,7 @@ static const unsigned DDDDecoderTable[] = {
|
|||
};
|
||||
|
||||
static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -649,7 +649,7 @@ static const unsigned DDDDDecoderTable[] = {
|
|||
|
||||
static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Register;
|
||||
|
||||
|
|
@ -663,7 +663,7 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
|
|||
|
||||
static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
// scale{5} is asserted as 1 in tblgen.
|
||||
Imm |= 0x20;
|
||||
|
|
@ -673,14 +673,14 @@ static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
|
|||
|
||||
static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, 64 - Imm);
|
||||
return Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
int64_t ImmVal = Imm;
|
||||
|
||||
|
|
@ -693,7 +693,7 @@ static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, void *Decoder)
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, (Imm >> 1) & 1);
|
||||
MCOperand_CreateImm0(Inst, Imm & 1);
|
||||
|
|
@ -701,7 +701,7 @@ static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address, void *Decoder)
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
bool ValidNamed;
|
||||
char result[128];
|
||||
|
|
@ -716,7 +716,7 @@ static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
|
|||
|
||||
static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
bool ValidNamed;
|
||||
char result[128];
|
||||
|
|
@ -731,7 +731,7 @@ static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
|
|||
|
||||
static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
// This decoder exists to add the dummy Lane operand to the MCInst, which must
|
||||
// be 1 in assembly but has no other real manifestation.
|
||||
|
|
@ -768,77 +768,77 @@ static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm, 64);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm, 32);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm, 16);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftRImm(Inst, Imm, 8);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftLImm(Inst, Imm, 64);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftLImm(Inst, Imm, 32);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftLImm(Inst, Imm, 16);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
return DecodeVecShiftLImm(Inst, Imm, 8);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
|
|
@ -902,7 +902,7 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
|
|||
|
||||
static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned imm = fieldFromInstruction(insn, 5, 16);
|
||||
|
|
@ -938,7 +938,7 @@ static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
|
|||
|
||||
static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
|
|
@ -999,7 +999,7 @@ static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
|
|||
|
||||
static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
bool IsLoad;
|
||||
bool IsIndexed;
|
||||
|
|
@ -1188,7 +1188,7 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
|
|||
|
||||
static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
|
|
@ -1264,7 +1264,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
|
|||
|
||||
static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rt = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
|
|
@ -1393,7 +1393,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
|
|||
|
||||
static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd, Rn, Rm;
|
||||
unsigned extend = fieldFromInstruction(insn, 10, 6);
|
||||
|
|
@ -1453,7 +1453,7 @@ static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
|
|||
|
||||
static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
|
|
@ -1486,7 +1486,7 @@ static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
|
|||
|
||||
static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned cmode = fieldFromInstruction(insn, 12, 4);
|
||||
|
|
@ -1526,7 +1526,7 @@ static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
|
|||
|
||||
static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned cmode = fieldFromInstruction(insn, 12, 4);
|
||||
|
|
@ -1544,7 +1544,7 @@ static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
|
||||
|
|
@ -1562,7 +1562,7 @@ static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(insn, 5, 5);
|
||||
|
|
@ -1598,7 +1598,7 @@ static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
|
|||
|
||||
static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
int64_t imm = fieldFromInstruction(insn, 0, 26);
|
||||
|
||||
|
|
@ -1614,7 +1614,7 @@ static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
|
|||
|
||||
static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
|
||||
uint32_t insn, uint64_t Addr,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
uint32_t op1 = fieldFromInstruction(insn, 16, 3);
|
||||
uint32_t op2 = fieldFromInstruction(insn, 5, 3);
|
||||
|
|
@ -1631,7 +1631,7 @@ static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
|
||||
uint64_t Addr, void *Decoder)
|
||||
uint64_t Addr, const void *Decoder)
|
||||
{
|
||||
uint32_t Rt = fieldFromInstruction(insn, 0, 5);
|
||||
uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5;
|
||||
|
|
|
|||
|
|
@ -4798,7 +4798,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0,
|
||||
/* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0,
|
||||
/* 20 */ 'l', 'd', '1', 9, 0,
|
||||
|
|
@ -6550,12 +6550,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo, int AltIdx)
|
||||
static const char *getRegisterName(unsigned RegNo, int AltIdx)
|
||||
{
|
||||
// assert(RegNo && RegNo < 420 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrsNoRegAltName[] = {
|
||||
static const char AsmStrsNoRegAltName[] = {
|
||||
/* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
||||
/* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
||||
/* 26 */ 'b', '1', '0', 0,
|
||||
|
|
@ -6881,7 +6881,7 @@ static char *getRegisterName(unsigned RegNo, int AltIdx)
|
|||
301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411,
|
||||
};
|
||||
|
||||
static char AsmStrsvreg[] = {
|
||||
static const char AsmStrsvreg[] = {
|
||||
/* 0 */ 'v', '1', '0', 0,
|
||||
/* 4 */ 'v', '2', '0', 0,
|
||||
/* 8 */ 'v', '3', '0', 0,
|
||||
|
|
@ -6950,7 +6950,7 @@ static char *getRegisterName(unsigned RegNo, int AltIdx)
|
|||
};
|
||||
|
||||
const uint32_t *RegAsmOffset;
|
||||
char *AsmStrs;
|
||||
const char *AsmStrs;
|
||||
|
||||
switch(AltIdx) {
|
||||
default: // llvm_unreachable("Invalid register alt name index!");
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||
return (insn & fieldMask) >> startBit; \
|
||||
}
|
||||
|
||||
static uint8_t DecoderTable32[] = {
|
||||
static const uint8_t DecoderTable32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 2, 86, 4, // Skip to: 1117
|
||||
/* 7 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ...
|
||||
|
|
@ -9610,7 +9610,7 @@ static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
|
|||
|
||||
#define DecodeToMCInst(fname,fieldname, InsnType) \
|
||||
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
|
||||
uint64_t Address, void *Decoder) \
|
||||
uint64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
InsnType tmp; \
|
||||
switch (Idx) { \
|
||||
|
|
@ -12667,11 +12667,11 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||
}
|
||||
|
||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
|
||||
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
|
|
|
|||
|
|
@ -567,7 +567,7 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg AArch64RegDiffLists[] = {
|
||||
static const MCPhysReg AArch64RegDiffLists[] = {
|
||||
/* 0 */ 65185, 1, 1, 1, 0,
|
||||
/* 5 */ 65281, 1, 1, 1, 0,
|
||||
/* 10 */ 5, 29, 1, 1, 0,
|
||||
|
|
@ -627,7 +627,7 @@ static MCPhysReg AArch64RegDiffLists[] = {
|
|||
/* 625 */ 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t AArch64SubRegIdxLists[] = {
|
||||
static const uint16_t AArch64SubRegIdxLists[] = {
|
||||
/* 0 */ 2, 14, 7, 1, 0,
|
||||
/* 5 */ 15, 0,
|
||||
/* 7 */ 3, 14, 7, 1, 4, 18, 17, 16, 0,
|
||||
|
|
@ -638,7 +638,7 @@ static uint16_t AArch64SubRegIdxLists[] = {
|
|||
/* 86 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 13, 30, 32, 31, 29, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc AArch64RegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
|
||||
{ 3, 0, 0, 0, 0 },
|
||||
{ 1518, 266, 4, 5, 10001 },
|
||||
{ 1525, 266, 4, 5, 10001 },
|
||||
|
|
@ -1062,436 +1062,436 @@ static MCRegisterDesc AArch64RegDesc[] = { // Descriptors
|
|||
};
|
||||
|
||||
// FPR8 Register Class...
|
||||
static MCPhysReg FPR8[] = {
|
||||
static const MCPhysReg FPR8[] = {
|
||||
AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31,
|
||||
};
|
||||
|
||||
// FPR8 Bit set.
|
||||
static uint8_t FPR8Bits[] = {
|
||||
static const uint8_t FPR8Bits[] = {
|
||||
0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
|
||||
// FPR16 Register Class...
|
||||
static MCPhysReg FPR16[] = {
|
||||
static const MCPhysReg FPR16[] = {
|
||||
AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31,
|
||||
};
|
||||
|
||||
// FPR16 Bit set.
|
||||
static uint8_t FPR16Bits[] = {
|
||||
static const uint8_t FPR16Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
|
||||
// GPR32all Register Class...
|
||||
static MCPhysReg GPR32all[] = {
|
||||
static const MCPhysReg GPR32all[] = {
|
||||
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP,
|
||||
};
|
||||
|
||||
// GPR32all Bit set.
|
||||
static uint8_t GPR32allBits[] = {
|
||||
static const uint8_t GPR32allBits[] = {
|
||||
0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// FPR32 Register Class...
|
||||
static MCPhysReg FPR32[] = {
|
||||
static const MCPhysReg FPR32[] = {
|
||||
AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31,
|
||||
};
|
||||
|
||||
// FPR32 Bit set.
|
||||
static uint8_t FPR32Bits[] = {
|
||||
static const uint8_t FPR32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
|
||||
// GPR32 Register Class...
|
||||
static MCPhysReg GPR32[] = {
|
||||
static const MCPhysReg GPR32[] = {
|
||||
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR,
|
||||
};
|
||||
|
||||
// GPR32 Bit set.
|
||||
static uint8_t GPR32Bits[] = {
|
||||
static const uint8_t GPR32Bits[] = {
|
||||
0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// GPR32sp Register Class...
|
||||
static MCPhysReg GPR32sp[] = {
|
||||
static const MCPhysReg GPR32sp[] = {
|
||||
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP,
|
||||
};
|
||||
|
||||
// GPR32sp Bit set.
|
||||
static uint8_t GPR32spBits[] = {
|
||||
static const uint8_t GPR32spBits[] = {
|
||||
0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// GPR32common Register Class...
|
||||
static MCPhysReg GPR32common[] = {
|
||||
static const MCPhysReg GPR32common[] = {
|
||||
AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30,
|
||||
};
|
||||
|
||||
// GPR32common Bit set.
|
||||
static uint8_t GPR32commonBits[] = {
|
||||
static const uint8_t GPR32commonBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// CCR Register Class...
|
||||
static MCPhysReg CCR[] = {
|
||||
static const MCPhysReg CCR[] = {
|
||||
AArch64_NZCV,
|
||||
};
|
||||
|
||||
// CCR Bit set.
|
||||
static uint8_t CCRBits[] = {
|
||||
static const uint8_t CCRBits[] = {
|
||||
0x08,
|
||||
};
|
||||
|
||||
// GPR32sponly Register Class...
|
||||
static MCPhysReg GPR32sponly[] = {
|
||||
static const MCPhysReg GPR32sponly[] = {
|
||||
AArch64_WSP,
|
||||
};
|
||||
|
||||
// GPR32sponly Bit set.
|
||||
static uint8_t GPR32sponlyBits[] = {
|
||||
static const uint8_t GPR32sponlyBits[] = {
|
||||
0x20,
|
||||
};
|
||||
|
||||
// GPR64all Register Class...
|
||||
static MCPhysReg GPR64all[] = {
|
||||
static const MCPhysReg GPR64all[] = {
|
||||
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP,
|
||||
};
|
||||
|
||||
// GPR64all Bit set.
|
||||
static uint8_t GPR64allBits[] = {
|
||||
static const uint8_t GPR64allBits[] = {
|
||||
0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// FPR64 Register Class...
|
||||
static MCPhysReg FPR64[] = {
|
||||
static const MCPhysReg FPR64[] = {
|
||||
AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31,
|
||||
};
|
||||
|
||||
// FPR64 Bit set.
|
||||
static uint8_t FPR64Bits[] = {
|
||||
static const uint8_t FPR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
|
||||
// GPR64 Register Class...
|
||||
static MCPhysReg GPR64[] = {
|
||||
static const MCPhysReg GPR64[] = {
|
||||
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR,
|
||||
};
|
||||
|
||||
// GPR64 Bit set.
|
||||
static uint8_t GPR64Bits[] = {
|
||||
static const uint8_t GPR64Bits[] = {
|
||||
0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// GPR64sp Register Class...
|
||||
static MCPhysReg GPR64sp[] = {
|
||||
static const MCPhysReg GPR64sp[] = {
|
||||
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP,
|
||||
};
|
||||
|
||||
// GPR64sp Bit set.
|
||||
static uint8_t GPR64spBits[] = {
|
||||
static const uint8_t GPR64spBits[] = {
|
||||
0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// GPR64common Register Class...
|
||||
static MCPhysReg GPR64common[] = {
|
||||
static const MCPhysReg GPR64common[] = {
|
||||
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR,
|
||||
};
|
||||
|
||||
// GPR64common Bit set.
|
||||
static uint8_t GPR64commonBits[] = {
|
||||
static const uint8_t GPR64commonBits[] = {
|
||||
0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// tcGPR64 Register Class...
|
||||
static MCPhysReg tcGPR64[] = {
|
||||
static const MCPhysReg tcGPR64[] = {
|
||||
AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18,
|
||||
};
|
||||
|
||||
// tcGPR64 Bit set.
|
||||
static uint8_t tcGPR64Bits[] = {
|
||||
static const uint8_t tcGPR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GPR64sponly Register Class...
|
||||
static MCPhysReg GPR64sponly[] = {
|
||||
static const MCPhysReg GPR64sponly[] = {
|
||||
AArch64_SP,
|
||||
};
|
||||
|
||||
// GPR64sponly Bit set.
|
||||
static uint8_t GPR64sponlyBits[] = {
|
||||
static const uint8_t GPR64sponlyBits[] = {
|
||||
0x10,
|
||||
};
|
||||
|
||||
// DD Register Class...
|
||||
static MCPhysReg DD[] = {
|
||||
static const MCPhysReg DD[] = {
|
||||
AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0,
|
||||
};
|
||||
|
||||
// DD Bit set.
|
||||
static uint8_t DDBits[] = {
|
||||
static const uint8_t DDBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// FPR128 Register Class...
|
||||
static MCPhysReg FPR128[] = {
|
||||
static const MCPhysReg FPR128[] = {
|
||||
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31,
|
||||
};
|
||||
|
||||
// FPR128 Bit set.
|
||||
static uint8_t FPR128Bits[] = {
|
||||
static const uint8_t FPR128Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
|
||||
// FPR128_lo Register Class...
|
||||
static MCPhysReg FPR128_lo[] = {
|
||||
static const MCPhysReg FPR128_lo[] = {
|
||||
AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15,
|
||||
};
|
||||
|
||||
// FPR128_lo Bit set.
|
||||
static uint8_t FPR128_loBits[] = {
|
||||
static const uint8_t FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
|
||||
};
|
||||
|
||||
// DDD Register Class...
|
||||
static MCPhysReg DDD[] = {
|
||||
static const MCPhysReg DDD[] = {
|
||||
AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1,
|
||||
};
|
||||
|
||||
// DDD Bit set.
|
||||
static uint8_t DDDBits[] = {
|
||||
static const uint8_t DDDBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// DDDD Register Class...
|
||||
static MCPhysReg DDDD[] = {
|
||||
static const MCPhysReg DDDD[] = {
|
||||
AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2,
|
||||
};
|
||||
|
||||
// DDDD Bit set.
|
||||
static uint8_t DDDDBits[] = {
|
||||
static const uint8_t DDDDBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQ Register Class...
|
||||
static MCPhysReg QQ[] = {
|
||||
static const MCPhysReg QQ[] = {
|
||||
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0,
|
||||
};
|
||||
|
||||
// QQ Bit set.
|
||||
static uint8_t QQBits[] = {
|
||||
static const uint8_t QQBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQ_with_qsub0_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
|
||||
};
|
||||
|
||||
// QQ_with_qsub0_in_FPR128_lo Bit set.
|
||||
static uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQ_with_qsub1_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0,
|
||||
};
|
||||
|
||||
// QQ_with_qsub1_in_FPR128_lo Bit set.
|
||||
static uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15,
|
||||
};
|
||||
|
||||
// QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
|
||||
static uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// QQQ Register Class...
|
||||
static MCPhysReg QQQ[] = {
|
||||
static const MCPhysReg QQQ[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
|
||||
};
|
||||
|
||||
// QQQ Bit set.
|
||||
static uint8_t QQQBits[] = {
|
||||
static const uint8_t QQQBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub0_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub0_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub1_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub1_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub2_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub2_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15,
|
||||
};
|
||||
|
||||
// QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// QQQQ Register Class...
|
||||
static MCPhysReg QQQQ[] = {
|
||||
static const MCPhysReg QQQQ[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ Bit set.
|
||||
static uint8_t QQQQBits[] = {
|
||||
static const uint8_t QQQQBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub1_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub1_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub2_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub2_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub3_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub3_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
|
||||
static MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
|
||||
AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15,
|
||||
};
|
||||
|
||||
// QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
|
||||
static uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01,
|
||||
};
|
||||
|
||||
static MCRegisterClass AArch64MCRegisterClasses[] = {
|
||||
static const MCRegisterClass AArch64MCRegisterClasses[] = {
|
||||
{ "FPR8", FPR8, FPR8Bits, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 },
|
||||
{ "FPR16", FPR16, FPR16Bits, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 },
|
||||
{ "GPR32all", GPR32all, GPR32allBits, 33, sizeof(GPR32allBits), AArch64_GPR32allRegClassID, 4, 4, 1, 1 },
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
#include "AArch64GenInstrInfo.inc"
|
||||
|
||||
|
||||
static char *getRegisterName(unsigned RegNo, int AltIdx);
|
||||
static const char *getRegisterName(unsigned RegNo, int AltIdx);
|
||||
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
static bool printSysAlias(MCInst *MI, SStream *O);
|
||||
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
|
||||
|
|
@ -86,7 +86,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
|
|||
bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri);
|
||||
|
||||
if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) {
|
||||
char *AsmMnemonic = NULL;
|
||||
const char *AsmMnemonic = NULL;
|
||||
|
||||
switch (MCOperand_getImm(Op3)) {
|
||||
default:
|
||||
|
|
@ -134,7 +134,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
|
|||
// instruction. In all cases the immediate shift amount shift must be in
|
||||
// the range 0 to (reg.size -1).
|
||||
if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
|
||||
char *AsmMnemonic = NULL;
|
||||
const char *AsmMnemonic = NULL;
|
||||
int shift = 0;
|
||||
int immr = (int)MCOperand_getImm(Op2);
|
||||
int imms = (int)MCOperand_getImm(Op3);
|
||||
|
|
@ -323,7 +323,7 @@ static bool printSysAlias(MCInst *MI, SStream *O)
|
|||
// unsigned Opcode = MCInst_getOpcode(MI);
|
||||
//assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!");
|
||||
|
||||
char *Asm = NULL;
|
||||
const char *Asm = NULL;
|
||||
MCOperand *Op1 = MCInst_getOperand(MI, 0);
|
||||
MCOperand *Cn = MCInst_getOperand(MI, 1);
|
||||
MCOperand *Cm = MCInst_getOperand(MI, 2);
|
||||
|
|
@ -1011,7 +1011,7 @@ static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O)
|
|||
{
|
||||
unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
|
||||
bool Valid;
|
||||
char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid);
|
||||
const char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid);
|
||||
|
||||
if (Valid) {
|
||||
SStream_concat0(O, Name);
|
||||
|
|
@ -1126,7 +1126,7 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *Layout
|
|||
// If it's a D-reg, we need to promote it to the equivalent Q-reg before
|
||||
// printing (otherwise getRegisterName fails).
|
||||
if (GETREGCLASS_CONTAIN0(AArch64_FPR64RegClassID, Reg)) {
|
||||
MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
|
||||
const MCRegisterClass *FPR128RC = MCRegisterInfo_getRegClass(MRI, AArch64_FPR128RegClassID);
|
||||
Reg = MCRegisterInfo_getMatchingSuperReg(MRI, Reg, AArch64_dsub, FPR128RC);
|
||||
}
|
||||
|
||||
|
|
@ -1286,7 +1286,7 @@ static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
|
|||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
unsigned Opcode = MCInst_getOpcode(MI);
|
||||
bool Valid;
|
||||
char *Name;
|
||||
const char *Name;
|
||||
|
||||
if (Opcode == AArch64_ISB)
|
||||
Name = A64NamedImmMapper_toString(&A64ISB_ISBMapper, Val, &Valid);
|
||||
|
|
@ -1350,7 +1350,7 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
|
|||
{
|
||||
unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
|
||||
bool Valid;
|
||||
char *Name;
|
||||
const char *Name;
|
||||
|
||||
Name = A64NamedImmMapper_toString(&A64PState_PStateMapper, Val, &Valid);
|
||||
if (Valid) {
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "AArch64GenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ ARM64_REG_INVALID, NULL },
|
||||
|
||||
{ ARM64_REG_X29, "x29"},
|
||||
|
|
@ -292,7 +292,7 @@ const char *AArch64_reg_name(csh handle, unsigned int reg)
|
|||
#endif
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -14304,7 +14304,7 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
}
|
||||
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ ARM64_INS_INVALID, NULL },
|
||||
|
||||
{ ARM64_INS_ABS, "abs" },
|
||||
|
|
@ -14726,7 +14726,7 @@ static name_map insn_name_maps[] = {
|
|||
};
|
||||
|
||||
// map *S & alias instructions back to original id
|
||||
static name_map alias_insn_name_maps[] = {
|
||||
static const name_map alias_insn_name_maps[] = {
|
||||
{ ARM64_INS_ADC, "adcs" },
|
||||
{ ARM64_INS_AND, "ands" },
|
||||
{ ARM64_INS_ADD, "adds" },
|
||||
|
|
@ -14801,7 +14801,7 @@ const char *AArch64_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ ARM64_GRP_INVALID, NULL },
|
||||
{ ARM64_GRP_JUMP, "jump" },
|
||||
|
|
@ -14851,7 +14851,7 @@ arm64_reg AArch64_map_vregister(unsigned int r)
|
|||
// for some reasons different Arm64 can map different register number to
|
||||
// the same register. this function handles the issue for exposing Mips
|
||||
// operands by mapping internal registers to 'public' register.
|
||||
unsigned int map[] = { 0,
|
||||
static const unsigned int map[] = { 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0,
|
||||
|
|
|
|||
|
|
@ -35,12 +35,12 @@ typedef enum ARM_AM_AddrOpc {
|
|||
ARM_AM_add
|
||||
} ARM_AM_AddrOpc;
|
||||
|
||||
static inline char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
|
||||
static inline const char *ARM_AM_getAddrOpcStr(ARM_AM_AddrOpc Op)
|
||||
{
|
||||
return Op == ARM_AM_sub ? "-" : "";
|
||||
}
|
||||
|
||||
static inline char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
|
||||
static inline const char *ARM_AM_getShiftOpcStr(ARM_AM_ShiftOpc Op)
|
||||
{
|
||||
switch (Op) {
|
||||
default: return ""; //llvm_unreachable("Unknown shift opc!");
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ inline static ARMCC_CondCodes ARMCC_getOppositeCondition(ARMCC_CondCodes CC)
|
|||
}
|
||||
}
|
||||
|
||||
inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
|
||||
inline static const char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
|
||||
{
|
||||
switch (CC) {
|
||||
case ARMCC_EQ: return "eq";
|
||||
|
|
@ -92,7 +92,7 @@ inline static char *ARMCC_ARMCondCodeToString(ARMCC_CondCodes CC)
|
|||
}
|
||||
}
|
||||
|
||||
inline static char *ARM_PROC_IFlagsToString(unsigned val)
|
||||
inline static const char *ARM_PROC_IFlagsToString(unsigned val)
|
||||
{
|
||||
switch (val) {
|
||||
case ARM_CPSFLAG_F: return "f";
|
||||
|
|
@ -102,7 +102,7 @@ inline static char *ARM_PROC_IFlagsToString(unsigned val)
|
|||
}
|
||||
}
|
||||
|
||||
inline static char *ARM_PROC_IModToString(unsigned val)
|
||||
inline static const char *ARM_PROC_IModToString(unsigned val)
|
||||
{
|
||||
switch (val) {
|
||||
case ARM_CPSMODE_IE: return "ie";
|
||||
|
|
@ -111,7 +111,7 @@ inline static char *ARM_PROC_IModToString(unsigned val)
|
|||
}
|
||||
}
|
||||
|
||||
inline static char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
|
||||
inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
|
||||
{
|
||||
switch (val) {
|
||||
default: return "BUGBUG";
|
||||
|
|
@ -153,7 +153,7 @@ enum ARM_ISB_InstSyncBOpt {
|
|||
ARM_ISB_SY = 15
|
||||
};
|
||||
|
||||
inline static char *ARM_ISB_InstSyncBOptToString(unsigned val)
|
||||
inline static const char *ARM_ISB_InstSyncBOptToString(unsigned val)
|
||||
{
|
||||
switch (val) {
|
||||
default: // never reach
|
||||
|
|
@ -222,7 +222,7 @@ typedef enum ARMII_AddrMode {
|
|||
ARMII_AddrMode_i12 = 16
|
||||
} ARMII_AddrMode;
|
||||
|
||||
inline static char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
|
||||
inline static const char *ARMII_AddrModeToString(ARMII_AddrMode addrmode)
|
||||
{
|
||||
switch (addrmode) {
|
||||
case ARMII_AddrModeNone: return "AddrModeNone";
|
||||
|
|
|
|||
|
|
@ -554,7 +554,7 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
|
|||
// that as a post-pass.
|
||||
static void AddThumb1SBit(MCInst *MI, bool InITBlock)
|
||||
{
|
||||
MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
|
||||
const MCOperandInfo *OpInfo = ARMInsts[MCInst_getOpcode(MI)].OpInfo;
|
||||
unsigned short NumOps = ARMInsts[MCInst_getOpcode(MI)].NumOperands;
|
||||
unsigned i;
|
||||
|
||||
|
|
@ -578,7 +578,7 @@ static void AddThumb1SBit(MCInst *MI, bool InITBlock)
|
|||
static DecodeStatus AddThumbPredicate(cs_struct *ud, MCInst *MI)
|
||||
{
|
||||
DecodeStatus S = MCDisassembler_Success;
|
||||
MCOperandInfo *OpInfo;
|
||||
const MCOperandInfo *OpInfo;
|
||||
unsigned short NumOps;
|
||||
unsigned int i;
|
||||
unsigned CC;
|
||||
|
|
@ -658,7 +658,7 @@ static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
|
|||
{
|
||||
unsigned CC;
|
||||
unsigned short NumOps;
|
||||
MCOperandInfo *OpInfo;
|
||||
const MCOperandInfo *OpInfo;
|
||||
unsigned i;
|
||||
|
||||
CC = ITStatus_getITCC(&(ud->ITBlock));
|
||||
|
|
|
|||
|
|
@ -5600,7 +5600,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', '.', '3', '2', 9, 0,
|
||||
/* 12 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', '.', '3', '2', 9, 0,
|
||||
/* 26 */ 's', 'h', 'a', '1', 's', 'u', '1', '.', '3', '2', 9, 0,
|
||||
|
|
@ -8162,12 +8162,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 289 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
|
||||
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
||||
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
||||
|
|
@ -8394,12 +8394,12 @@ static char *getRegisterName(unsigned RegNo)
|
|||
}
|
||||
|
||||
// get registers with number only
|
||||
static char *getRegisterName2(unsigned RegNo)
|
||||
static const char *getRegisterName2(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 289 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
|
||||
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
||||
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||
return (insn & fieldMask) >> startBit; \
|
||||
}
|
||||
|
||||
static uint8_t DecoderTableARM32[] = {
|
||||
static const uint8_t DecoderTableARM32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 25, 3, // Inst{27-25} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 160, 11, // Skip to: 2983
|
||||
/* 7 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ...
|
||||
|
|
@ -1870,7 +1870,7 @@ static uint8_t DecoderTableARM32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableNEONData32[] = {
|
||||
static const uint8_t DecoderTableNEONData32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 207, 30, // Skip to: 7894
|
||||
/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
|
||||
|
|
@ -5413,7 +5413,7 @@ static uint8_t DecoderTableNEONData32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableNEONDup32[] = {
|
||||
static const uint8_t DecoderTableNEONDup32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 22, 6, // Inst{27-22} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 56, 105, 0, // Skip to: 112
|
||||
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
|
||||
|
|
@ -5506,7 +5506,7 @@ static uint8_t DecoderTableNEONDup32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableNEONLoadStore32[] = {
|
||||
static const uint8_t DecoderTableNEONLoadStore32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 17, 1, // Skip to: 280
|
||||
/* 7 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
|
||||
|
|
@ -6893,7 +6893,7 @@ static uint8_t DecoderTableNEONLoadStore32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableThumb16[] = {
|
||||
static const uint8_t DecoderTableThumb16[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 22
|
||||
/* 7 */ MCD_OPC_CheckPredicate, 19, 210, 3, // Skip to: 989
|
||||
|
|
@ -7130,7 +7130,7 @@ static uint8_t DecoderTableThumb16[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableThumb32[] = {
|
||||
static const uint8_t DecoderTableThumb32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 34
|
||||
/* 7 */ MCD_OPC_CheckPredicate, 26, 48, 0, // Skip to: 59
|
||||
|
|
@ -7147,7 +7147,7 @@ static uint8_t DecoderTableThumb32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableThumb216[] = {
|
||||
static const uint8_t DecoderTableThumb216[] = {
|
||||
/* 0 */ MCD_OPC_CheckPredicate, 22, 12, 0, // Skip to: 16
|
||||
/* 4 */ MCD_OPC_CheckField, 8, 8, 191, 1, 5, 0, // Skip to: 16
|
||||
/* 11 */ MCD_OPC_Decode, 163, 18, 230, 1, // Opcode: t2IT
|
||||
|
|
@ -7155,7 +7155,7 @@ static uint8_t DecoderTableThumb216[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableThumb232[] = {
|
||||
static const uint8_t DecoderTableThumb232[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 29, 25, 8, // Skip to: 2080
|
||||
/* 7 */ MCD_OPC_ExtractField, 24, 3, // Inst{26-24} ...
|
||||
|
|
@ -8727,7 +8727,7 @@ static uint8_t DecoderTableThumb232[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableThumbSBit16[] = {
|
||||
static const uint8_t DecoderTableThumbSBit16[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 16
|
||||
/* 7 */ MCD_OPC_CheckPredicate, 19, 49, 1, // Skip to: 316
|
||||
|
|
@ -8806,7 +8806,7 @@ static uint8_t DecoderTableThumbSBit16[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableVFP32[] = {
|
||||
static const uint8_t DecoderTableVFP32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 83, 1, // Skip to: 346
|
||||
/* 7 */ MCD_OPC_ExtractField, 24, 4, // Inst{27-24} ...
|
||||
|
|
@ -9435,7 +9435,7 @@ static uint8_t DecoderTableVFP32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableVFPV832[] = {
|
||||
static const uint8_t DecoderTableVFPV832[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 160, 0, // Skip to: 167
|
||||
/* 7 */ MCD_OPC_ExtractField, 6, 1, // Inst{6} ...
|
||||
|
|
@ -9657,7 +9657,7 @@ static uint8_t DecoderTableVFPV832[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTablev8Crypto32[] = {
|
||||
static const uint8_t DecoderTablev8Crypto32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 72
|
||||
/* 7 */ MCD_OPC_ExtractField, 23, 9, // Inst{31-23} ...
|
||||
|
|
@ -9758,7 +9758,7 @@ static uint8_t DecoderTablev8Crypto32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTablev8NEON32[] = {
|
||||
static const uint8_t DecoderTablev8NEON32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 8, 4, // Inst{11-8} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 127, 0, // Skip to: 134
|
||||
/* 7 */ MCD_OPC_ExtractField, 6, 2, // Inst{7-6} ...
|
||||
|
|
@ -10088,7 +10088,7 @@ static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
|
|||
|
||||
#define DecodeToMCInst(fname,fieldname, InsnType) \
|
||||
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
|
||||
uint64_t Address, void *Decoder) \
|
||||
uint64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
InsnType tmp; \
|
||||
switch (Idx) { \
|
||||
|
|
@ -13452,11 +13452,11 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||
}
|
||||
|
||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
|
||||
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
|
||||
{ \
|
||||
uint64_t Bits = ARM_getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
|
|
|
|||
|
|
@ -2830,367 +2830,367 @@ enum {
|
|||
#define ImplicitList14 0
|
||||
#define ImplicitList15 0
|
||||
|
||||
static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo11[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo15[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo16[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo23[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo24[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo26[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static MCOperandInfo OperandInfo30[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo31[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo35[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo36[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo39[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo42[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo44[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo45[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo46[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo47[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo48[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo49[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo53[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo54[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo58[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo59[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo63[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo64[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo69[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo73[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo74[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo75[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo80[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo81[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo85[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo86[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo87[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo88[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo89[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo90[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo92[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo93[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo94[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo95[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo96[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo100[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo102[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo103[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo104[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo106[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo107[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo108[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo111[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo112[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo119[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo121[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo122[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo123[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo124[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo125[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo126[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo127[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo130[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo131[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo132[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo133[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo134[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo135[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo136[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo137[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo138[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo140[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo141[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo143[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo144[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo145[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo146[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo147[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo148[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo149[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo151[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo152[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo153[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo154[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo155[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo156[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo157[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo158[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo159[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo160[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo162[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo163[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo164[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo165[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo166[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo167[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo168[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo169[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo170[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo171[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo174[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo175[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo176[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo177[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo179[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo180[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo181[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo182[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo183[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo184[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo185[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo186[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo187[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo188[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo190[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo194[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo199[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo200[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo203[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo204[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo205[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo207[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo208[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo209[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo210[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo211[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo214[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo217[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo221[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo222[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo223[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo226[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo229[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo230[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo259[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo260[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo263[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo267[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo274[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo278[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo283[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo291[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo296[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo298[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo299[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo308[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo309[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo310[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo316[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo324[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo326[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo328[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo329[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo331[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo336[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo337[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo338[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo339[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo340[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static MCOperandInfo OperandInfo341[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static MCOperandInfo OperandInfo342[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo343[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo358[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo359[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static MCOperandInfo OperandInfo360[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo11[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo15[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo16[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo23[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo24[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo26[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static const MCOperandInfo OperandInfo30[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo31[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo32[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo35[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo36[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo39[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo42[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo44[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo45[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo46[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo47[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo48[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo49[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo50[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo53[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo54[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo56[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo58[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo59[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo63[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo64[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo69[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo73[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo74[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo75[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo80[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo81[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo85[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo86[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo87[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo88[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo89[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo90[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo91[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo92[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo93[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo94[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo95[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo96[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo100[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo102[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo103[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo104[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo106[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo107[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo108[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo111[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo112[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo119[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo121[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo122[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo123[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo124[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo125[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo126[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo127[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo130[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo131[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo132[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo133[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo134[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo135[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo136[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo137[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo138[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo140[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo141[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo143[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo144[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo145[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo146[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo147[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo148[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo149[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo151[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo152[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo153[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo154[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo155[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo156[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo157[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo158[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo159[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo160[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo162[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo163[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo164[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo165[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo166[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo167[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo168[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo169[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo170[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo171[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo174[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo175[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo176[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo177[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo179[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo180[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo181[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo182[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo183[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo184[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo185[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo186[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo187[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo188[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo190[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo192[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo194[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo196[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo199[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo200[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo203[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo204[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo205[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo207[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo208[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo209[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo210[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo211[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo214[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo217[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo221[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo222[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo223[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo226[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo229[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo230[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo259[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo260[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo263[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo267[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo274[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo278[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo283[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo291[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo296[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo298[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo299[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo308[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo309[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo310[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo316[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo324[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo326[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo328[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo329[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo331[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo336[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo337[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo338[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo339[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo340[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static const MCOperandInfo OperandInfo341[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
|
||||
static const MCOperandInfo OperandInfo342[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo343[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
|
||||
static const MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
|
||||
static const MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo358[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo359[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
static const MCOperandInfo OperandInfo360[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
|
||||
|
||||
static MCInstrDesc ARMInsts[] = {
|
||||
static const MCInstrDesc ARMInsts[] = {
|
||||
{ 0, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #0 = PHI
|
||||
{ 1, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #1 = INLINEASM
|
||||
{ 2, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #2 = CFI_INSTRUCTION
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -210,7 +210,7 @@ static void printRegName(cs_struct *h, SStream *OS, unsigned RegNo)
|
|||
#endif
|
||||
}
|
||||
|
||||
static name_map insn_update_flgs[] = {
|
||||
static const name_map insn_update_flgs[] = {
|
||||
{ ARM_INS_CMN, "cmn" },
|
||||
{ ARM_INS_CMP, "cmp" },
|
||||
{ ARM_INS_TEQ, "teq" },
|
||||
|
|
@ -667,7 +667,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
|
|||
case ARM_STREXD:
|
||||
case ARM_LDAEXD:
|
||||
case ARM_STLEXD: {
|
||||
MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
|
||||
const MCRegisterClass* MRC = MCRegisterInfo_getRegClass(MRI, ARM_GPRRegClassID);
|
||||
bool isStore = Opcode == ARM_STREXD || Opcode == ARM_STLEXD;
|
||||
|
||||
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, isStore ? 1 : 0));
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "ARMGenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ ARM_REG_INVALID, NULL },
|
||||
{ ARM_REG_APSR, "apsr"},
|
||||
{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
|
||||
|
|
@ -127,7 +127,7 @@ static name_map reg_name_maps[] = {
|
|||
{ ARM_REG_S30, "s30"},
|
||||
{ ARM_REG_S31, "s31"},
|
||||
};
|
||||
static name_map reg_name_maps2[] = {
|
||||
static const name_map reg_name_maps2[] = {
|
||||
{ ARM_REG_INVALID, NULL },
|
||||
{ ARM_REG_APSR, "apsr"},
|
||||
{ ARM_REG_APSR_NZCV, "apsr_nzcv"},
|
||||
|
|
@ -266,7 +266,7 @@ const char *ARM_reg_name2(csh handle, unsigned int reg)
|
|||
#endif
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -13576,7 +13576,7 @@ void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ ARM_INS_INVALID, NULL },
|
||||
|
||||
{ ARM_INS_ADC, "adc" },
|
||||
|
|
@ -14031,7 +14031,7 @@ const char *ARM_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ ARM_GRP_INVALID, NULL },
|
||||
{ ARM_GRP_JUMP, "jump" },
|
||||
|
|
@ -14090,7 +14090,7 @@ const char *ARM_group_name(csh handle, unsigned int id)
|
|||
|
||||
// list all relative branch instructions
|
||||
// ie: insns[i].branch && !insns[i].indirect_branch
|
||||
static unsigned int insn_rel[] = {
|
||||
static const unsigned int insn_rel[] = {
|
||||
ARM_BL,
|
||||
ARM_BLX_pred,
|
||||
ARM_Bcc,
|
||||
|
|
@ -14107,7 +14107,7 @@ static unsigned int insn_rel[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static unsigned int insn_blx_rel_to_arm[] = {
|
||||
static const unsigned int insn_blx_rel_to_arm[] = {
|
||||
ARM_tBLXi,
|
||||
0
|
||||
};
|
||||
|
|
|
|||
|
|
@ -41,162 +41,162 @@
|
|||
// Forward declare these because the autogenerated code will reference them.
|
||||
// Definitions are further down.
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
// DecodeBranchTargetMM - Decode microMIPS branch offset, which is
|
||||
// shifted left by 1 bit.
|
||||
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
// DecodeJumpTargetMM - Decode microMIPS jump target, which is
|
||||
// shifted left by 1 bit.
|
||||
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMem(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCachePref(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeCOP3Mem(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeSimm16(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
// Decode the immediate field of an LSA instruction which
|
||||
// is off by one.
|
||||
static DecodeStatus DecodeLSAImm(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeInsSize(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeExtSize(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
/// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
|
||||
/// handle.
|
||||
static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
|
||||
uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
|
||||
uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
|
||||
|
||||
|
||||
#define GET_SUBTARGETINFO_ENUM
|
||||
|
|
@ -456,18 +456,18 @@ bool Mips64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst
|
|||
return status == MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
|
||||
static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
|
||||
{
|
||||
//MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
|
||||
//return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
|
||||
MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
|
||||
const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
|
||||
return rc->RegsBegin[RegNo];
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, MCRegisterInfo *);
|
||||
typedef DecodeStatus (*DecodeFN)(MCInst *, unsigned, uint64_t, const MCRegisterInfo *);
|
||||
// The size of the n field depends on the element size
|
||||
// The register class also depends on this.
|
||||
uint32_t tmp = fieldFromInstruction(insn, 17, 5);
|
||||
|
|
@ -520,7 +520,7 @@ static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
||||
// (otherwise we would have matched the ADDI instruction from the earlier
|
||||
|
|
@ -556,7 +556,7 @@ static DecodeStatus DecodeAddiGroupBranch_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
||||
// (otherwise we would have matched the ADDI instruction from the earlier
|
||||
|
|
@ -592,7 +592,7 @@ static DecodeStatus DecodeDaddiGroupBranch_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
||||
// (otherwise we would have matched the BLEZL instruction from the earlier
|
||||
|
|
@ -632,7 +632,7 @@ static DecodeStatus DecodeBlezlGroupBranch_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
||||
// (otherwise we would have matched the BGTZL instruction from the earlier
|
||||
|
|
@ -672,7 +672,7 @@ static DecodeStatus DecodeBgtzlGroupBranch_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
||||
// (otherwise we would have matched the BGTZ instruction from the earlier
|
||||
|
|
@ -718,7 +718,7 @@ static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
|
||||
// (otherwise we would have matched the BLEZL instruction from the earlier
|
||||
|
|
@ -758,13 +758,13 @@ static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI, uint32_t insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -777,7 +777,7 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -790,7 +790,7 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
if (Inst->csh->mode & CS_MODE_64)
|
||||
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
|
||||
|
|
@ -799,13 +799,13 @@ static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -818,7 +818,7 @@ static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -831,7 +831,7 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -844,7 +844,7 @@ static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -857,7 +857,7 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -870,7 +870,7 @@ static DecodeStatus DecodeCCRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -883,7 +883,7 @@ static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMem(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
||||
|
|
@ -904,7 +904,7 @@ static DecodeStatus DecodeMem(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCachePref(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Hint = fieldFromInstruction(Insn, 16, 5);
|
||||
|
|
@ -920,7 +920,7 @@ static DecodeStatus DecodeCachePref(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, MCRegisterInfo *Decoder)
|
||||
uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(fieldFromInstruction(Insn, 16, 10), 10);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
|
||||
|
|
@ -967,7 +967,7 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0x0fff, 12);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
||||
|
|
@ -987,7 +987,7 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
|
||||
|
|
@ -1004,7 +1004,7 @@ static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeFMem(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
||||
|
|
@ -1021,7 +1021,7 @@ static DecodeStatus DecodeFMem(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
||||
|
|
@ -1038,7 +1038,7 @@ static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Offset = SignExtend32(Insn & 0xffff, 16);
|
||||
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
|
||||
|
|
@ -1055,7 +1055,7 @@ static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int64_t Offset = SignExtend64((Insn >> 7) & 0x1ff, 9);
|
||||
unsigned Rt = fieldFromInstruction(Insn, 16, 5);
|
||||
|
|
@ -1077,7 +1077,7 @@ static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// Currently only hardware register 29 is supported.
|
||||
if (RegNo != 29)
|
||||
|
|
@ -1089,7 +1089,7 @@ static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1103,7 +1103,7 @@ static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1116,7 +1116,7 @@ static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1130,7 +1130,7 @@ static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1144,7 +1144,7 @@ static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1158,7 +1158,7 @@ static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1172,7 +1172,7 @@ static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1186,7 +1186,7 @@ static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1200,7 +1200,7 @@ static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1214,7 +1214,7 @@ static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
|
||||
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -1228,7 +1228,7 @@ static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTarget(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
uint64_t TargetAddress = (SignExtend32(Offset, 16) * 4) + Address + 4;
|
||||
MCOperand_CreateImm0(Inst, TargetAddress);
|
||||
|
|
@ -1237,7 +1237,7 @@ static DecodeStatus DecodeBranchTarget(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeJumpTarget(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
uint64_t TargetAddress = (fieldFromInstruction(Insn, 0, 26) << 2) | ((Address + 4) & ~0x0FFFFFFF);
|
||||
MCOperand_CreateImm0(Inst, TargetAddress);
|
||||
|
|
@ -1246,7 +1246,7 @@ static DecodeStatus DecodeJumpTarget(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int32_t BranchOffset = SignExtend32(Offset, 21) * 4;
|
||||
|
||||
|
|
@ -1256,7 +1256,7 @@ static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int32_t BranchOffset = SignExtend32(Offset, 26) * 4;
|
||||
|
||||
|
|
@ -1265,7 +1265,7 @@ static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
|
||||
unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int32_t BranchOffset = SignExtend32(Offset, 16) * 2;
|
||||
MCOperand_CreateImm0(Inst, BranchOffset);
|
||||
|
|
@ -1274,7 +1274,7 @@ static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
|
||||
MCOperand_CreateImm0(Inst, JumpOffset);
|
||||
|
|
@ -1283,14 +1283,14 @@ static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeSimm16(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeLSAImm(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// We add one to the immediate field as it was encoded as 'imm - 1'.
|
||||
MCOperand_CreateImm0(Inst, Insn + 1);
|
||||
|
|
@ -1298,7 +1298,7 @@ static DecodeStatus DecodeLSAImm(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeInsSize(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
// First we need to grab the pos(lsb) from MCInst.
|
||||
int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
|
||||
|
|
@ -1308,7 +1308,7 @@ static DecodeStatus DecodeInsSize(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeExtSize(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
int Size = (int) Insn + 1;
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
|
||||
|
|
@ -1316,14 +1316,14 @@ static DecodeStatus DecodeExtSize(MCInst *Inst,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
|
||||
unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
|
||||
unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
|
||||
return MCDisassembler_Success;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
|
||||
/// printInstruction - This method is automatically generated by tablegen
|
||||
/// from the instruction set description.
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
||||
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
|
||||
{
|
||||
static const uint32_t OpInfo[] = {
|
||||
0U, // PHI
|
||||
|
|
@ -3442,7 +3442,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'j', 'a', 'l', 'r', 'c', 32, 9, 0,
|
||||
/* 8 */ 'd', 'm', 'f', 'c', '0', 9, 0,
|
||||
/* 15 */ 'd', 'm', 't', 'c', '0', 9, 0,
|
||||
|
|
@ -4870,12 +4870,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 394 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'f', '1', '0', 0,
|
||||
/* 4 */ 'w', '1', '0', 0,
|
||||
/* 8 */ 'f', '2', '0', 0,
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||
|
||||
#if 0
|
||||
// TODO: properly handle this in the future with MIPS1/2 modes
|
||||
static uint8_t DecoderTableCOP3_32[] = {
|
||||
static const uint8_t DecoderTableCOP3_32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 51, 8, 0, // Skip to: 15
|
||||
/* 7 */ MCD_OPC_CheckPredicate, 1, 40, 0, // Skip to: 51
|
||||
|
|
@ -45,7 +45,7 @@ static uint8_t DecoderTableCOP3_32[] = {
|
|||
};
|
||||
#endif
|
||||
|
||||
static uint8_t DecoderTableMicroMips32[] = {
|
||||
static const uint8_t DecoderTableMicroMips32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 114, 3, // Skip to: 889
|
||||
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
|
||||
|
|
@ -413,7 +413,7 @@ static uint8_t DecoderTableMicroMips32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableMips32[] = {
|
||||
static const uint8_t DecoderTableMips32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 173, 3, // Skip to: 948
|
||||
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
|
||||
|
|
@ -3635,7 +3635,7 @@ static uint8_t DecoderTableMips32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableMips32r6_64r632[] = {
|
||||
static const uint8_t DecoderTableMips32r6_64r632[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 205, 1, // Skip to: 468
|
||||
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
|
||||
|
|
@ -4072,7 +4072,7 @@ static uint8_t DecoderTableMips32r6_64r632[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
|
||||
static const uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 22
|
||||
/* 7 */ MCD_OPC_CheckPredicate, 36, 30, 0, // Skip to: 41
|
||||
|
|
@ -4086,7 +4086,7 @@ static uint8_t DecoderTableMips32r6_64r6_GP6432[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTableMips6432[] = {
|
||||
static const uint8_t DecoderTableMips6432[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 112, 1, // Skip to: 375
|
||||
/* 7 */ MCD_OPC_ExtractField, 0, 6, // Inst{5-0} ...
|
||||
|
|
@ -4697,7 +4697,7 @@ static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
|
|||
|
||||
#define DecodeToMCInst(fname,fieldname, InsnType) \
|
||||
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
|
||||
uint64_t Address, void *Decoder) \
|
||||
uint64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
InsnType tmp; \
|
||||
switch (Idx) { \
|
||||
|
|
@ -6506,11 +6506,11 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||
}
|
||||
|
||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
|
||||
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
|
|
|
|||
|
|
@ -497,7 +497,7 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg MipsRegDiffLists[] = {
|
||||
static const MCPhysReg MipsRegDiffLists[] = {
|
||||
/* 0 */ 0, 0,
|
||||
/* 2 */ 4, 1, 1, 1, 1, 0,
|
||||
/* 8 */ 364, 65286, 1, 1, 1, 0,
|
||||
|
|
@ -590,14 +590,14 @@ static MCPhysReg MipsRegDiffLists[] = {
|
|||
/* 251 */ 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t MipsSubRegIdxLists[] = {
|
||||
static const uint16_t MipsSubRegIdxLists[] = {
|
||||
/* 0 */ 1, 0,
|
||||
/* 2 */ 3, 4, 5, 6, 7, 0,
|
||||
/* 8 */ 2, 9, 8, 0,
|
||||
/* 12 */ 9, 1, 8, 10, 11, 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
||||
{ 6, 0, 0, 0, 0 },
|
||||
{ 2007, 1, 82, 1, 4017 },
|
||||
{ 2010, 1, 1, 1, 4017 },
|
||||
|
|
@ -994,486 +994,486 @@ static MCRegisterDesc MipsRegDesc[] = { // Descriptors
|
|||
{ 977, 156, 1, 0, 2273 },
|
||||
};
|
||||
|
||||
static MCPhysReg OddSP[] = {
|
||||
static const MCPhysReg OddSP[] = {
|
||||
Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||
};
|
||||
|
||||
// OddSP Bit set.
|
||||
static uint8_t OddSPBits[] = {
|
||||
static const uint8_t OddSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||
};
|
||||
|
||||
// CCR Register Class...
|
||||
static MCPhysReg CCR[] = {
|
||||
static const MCPhysReg CCR[] = {
|
||||
Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
|
||||
};
|
||||
|
||||
// CCR Bit set.
|
||||
static uint8_t CCRBits[] = {
|
||||
static const uint8_t CCRBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// COP2 Register Class...
|
||||
static MCPhysReg COP2[] = {
|
||||
static const MCPhysReg COP2[] = {
|
||||
Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231,
|
||||
};
|
||||
|
||||
// COP2 Bit set.
|
||||
static uint8_t COP2Bits[] = {
|
||||
static const uint8_t COP2Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01,
|
||||
};
|
||||
|
||||
// COP3 Register Class...
|
||||
static MCPhysReg COP3[] = {
|
||||
static const MCPhysReg COP3[] = {
|
||||
Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331,
|
||||
};
|
||||
|
||||
// COP3 Bit set.
|
||||
static uint8_t COP3Bits[] = {
|
||||
static const uint8_t COP3Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// DSPR Register Class...
|
||||
static MCPhysReg DSPR[] = {
|
||||
static const MCPhysReg DSPR[] = {
|
||||
Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
|
||||
};
|
||||
|
||||
// DSPR Bit set.
|
||||
static uint8_t DSPRBits[] = {
|
||||
static const uint8_t DSPRBits[] = {
|
||||
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// FGR32 Register Class...
|
||||
static MCPhysReg FGR32[] = {
|
||||
static const MCPhysReg FGR32[] = {
|
||||
Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
|
||||
};
|
||||
|
||||
// FGR32 Bit set.
|
||||
static uint8_t FGR32Bits[] = {
|
||||
static const uint8_t FGR32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// FGRCC Register Class...
|
||||
static MCPhysReg FGRCC[] = {
|
||||
static const MCPhysReg FGRCC[] = {
|
||||
Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
|
||||
};
|
||||
|
||||
// FGRCC Bit set.
|
||||
static uint8_t FGRCCBits[] = {
|
||||
static const uint8_t FGRCCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// FGRH32 Register Class...
|
||||
static MCPhysReg FGRH32[] = {
|
||||
static const MCPhysReg FGRH32[] = {
|
||||
Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31,
|
||||
};
|
||||
|
||||
// FGRH32 Bit set.
|
||||
static uint8_t FGRH32Bits[] = {
|
||||
static const uint8_t FGRH32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// GPR32 Register Class...
|
||||
static MCPhysReg GPR32[] = {
|
||||
static const MCPhysReg GPR32[] = {
|
||||
Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
|
||||
};
|
||||
|
||||
// GPR32 Bit set.
|
||||
static uint8_t GPR32Bits[] = {
|
||||
static const uint8_t GPR32Bits[] = {
|
||||
0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// HWRegs Register Class...
|
||||
static MCPhysReg HWRegs[] = {
|
||||
static const MCPhysReg HWRegs[] = {
|
||||
Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31,
|
||||
};
|
||||
|
||||
// HWRegs Bit set.
|
||||
static uint8_t HWRegsBits[] = {
|
||||
static const uint8_t HWRegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||||
};
|
||||
|
||||
// OddSP_with_sub_hi Register Class...
|
||||
static MCPhysReg OddSP_with_sub_hi[] = {
|
||||
static const MCPhysReg OddSP_with_sub_hi[] = {
|
||||
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||
};
|
||||
|
||||
// OddSP_with_sub_hi Bit set.
|
||||
static uint8_t OddSP_with_sub_hiBits[] = {
|
||||
static const uint8_t OddSP_with_sub_hiBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||
};
|
||||
|
||||
// FGR32_and_OddSP Register Class...
|
||||
static MCPhysReg FGR32_and_OddSP[] = {
|
||||
static const MCPhysReg FGR32_and_OddSP[] = {
|
||||
Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31,
|
||||
};
|
||||
|
||||
// FGR32_and_OddSP Bit set.
|
||||
static uint8_t FGR32_and_OddSPBits[] = {
|
||||
static const uint8_t FGR32_and_OddSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
||||
};
|
||||
|
||||
// FGRH32_and_OddSP Register Class...
|
||||
static MCPhysReg FGRH32_and_OddSP[] = {
|
||||
static const MCPhysReg FGRH32_and_OddSP[] = {
|
||||
Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31,
|
||||
};
|
||||
|
||||
// FGRH32_and_OddSP Bit set.
|
||||
static uint8_t FGRH32_and_OddSPBits[] = {
|
||||
static const uint8_t FGRH32_and_OddSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
|
||||
};
|
||||
|
||||
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
|
||||
static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
|
||||
static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
|
||||
Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||
};
|
||||
|
||||
// OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
|
||||
static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
|
||||
static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||
};
|
||||
|
||||
// CPU16RegsPlusSP Register Class...
|
||||
static MCPhysReg CPU16RegsPlusSP[] = {
|
||||
static const MCPhysReg CPU16RegsPlusSP[] = {
|
||||
Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP,
|
||||
};
|
||||
|
||||
// CPU16RegsPlusSP Bit set.
|
||||
static uint8_t CPU16RegsPlusSPBits[] = {
|
||||
static const uint8_t CPU16RegsPlusSPBits[] = {
|
||||
0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||||
};
|
||||
|
||||
// CC Register Class...
|
||||
static MCPhysReg CC[] = {
|
||||
static const MCPhysReg CC[] = {
|
||||
Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7,
|
||||
};
|
||||
|
||||
// CC Bit set.
|
||||
static uint8_t CCBits[] = {
|
||||
static const uint8_t CCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x80, 0x7f,
|
||||
};
|
||||
|
||||
// CPU16Regs Register Class...
|
||||
static MCPhysReg CPU16Regs[] = {
|
||||
static const MCPhysReg CPU16Regs[] = {
|
||||
Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1,
|
||||
};
|
||||
|
||||
// CPU16Regs Bit set.
|
||||
static uint8_t CPU16RegsBits[] = {
|
||||
static const uint8_t CPU16RegsBits[] = {
|
||||
0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
|
||||
};
|
||||
|
||||
// FCC Register Class...
|
||||
static MCPhysReg FCC[] = {
|
||||
static const MCPhysReg FCC[] = {
|
||||
Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7,
|
||||
};
|
||||
|
||||
// FCC Bit set.
|
||||
static uint8_t FCCBits[] = {
|
||||
static const uint8_t FCCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
||||
};
|
||||
|
||||
// MSACtrl Register Class...
|
||||
static MCPhysReg MSACtrl[] = {
|
||||
static const MCPhysReg MSACtrl[] = {
|
||||
Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap,
|
||||
};
|
||||
|
||||
// MSACtrl Bit set.
|
||||
static uint8_t MSACtrlBits[] = {
|
||||
static const uint8_t MSACtrlBits[] = {
|
||||
0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
|
||||
static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
|
||||
static const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
|
||||
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
|
||||
};
|
||||
|
||||
// OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
|
||||
static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
|
||||
static const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
||||
};
|
||||
|
||||
// HI32DSP Register Class...
|
||||
static MCPhysReg HI32DSP[] = {
|
||||
static const MCPhysReg HI32DSP[] = {
|
||||
Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3,
|
||||
};
|
||||
|
||||
// HI32DSP Bit set.
|
||||
static uint8_t HI32DSPBits[] = {
|
||||
static const uint8_t HI32DSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
|
||||
};
|
||||
|
||||
// LO32DSP Register Class...
|
||||
static MCPhysReg LO32DSP[] = {
|
||||
static const MCPhysReg LO32DSP[] = {
|
||||
Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3,
|
||||
};
|
||||
|
||||
// LO32DSP Bit set.
|
||||
static uint8_t LO32DSPBits[] = {
|
||||
static const uint8_t LO32DSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
||||
};
|
||||
|
||||
// CPURAReg Register Class...
|
||||
static MCPhysReg CPURAReg[] = {
|
||||
static const MCPhysReg CPURAReg[] = {
|
||||
Mips_RA,
|
||||
};
|
||||
|
||||
// CPURAReg Bit set.
|
||||
static uint8_t CPURARegBits[] = {
|
||||
static const uint8_t CPURARegBits[] = {
|
||||
0x00, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// CPUSPReg Register Class...
|
||||
static MCPhysReg CPUSPReg[] = {
|
||||
static const MCPhysReg CPUSPReg[] = {
|
||||
Mips_SP,
|
||||
};
|
||||
|
||||
// CPUSPReg Bit set.
|
||||
static uint8_t CPUSPRegBits[] = {
|
||||
static const uint8_t CPUSPRegBits[] = {
|
||||
0x00, 0x00, 0x10,
|
||||
};
|
||||
|
||||
// DSPCC Register Class...
|
||||
static MCPhysReg DSPCC[] = {
|
||||
static const MCPhysReg DSPCC[] = {
|
||||
Mips_DSPCCond,
|
||||
};
|
||||
|
||||
// DSPCC Bit set.
|
||||
static uint8_t DSPCCBits[] = {
|
||||
static const uint8_t DSPCCBits[] = {
|
||||
0x04,
|
||||
};
|
||||
|
||||
// HI32 Register Class...
|
||||
static MCPhysReg HI32[] = {
|
||||
static const MCPhysReg HI32[] = {
|
||||
Mips_HI0,
|
||||
};
|
||||
|
||||
// HI32 Bit set.
|
||||
static uint8_t HI32Bits[] = {
|
||||
static const uint8_t HI32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||||
};
|
||||
|
||||
// LO32 Register Class...
|
||||
static MCPhysReg LO32[] = {
|
||||
static const MCPhysReg LO32[] = {
|
||||
Mips_LO0,
|
||||
};
|
||||
|
||||
// LO32 Bit set.
|
||||
static uint8_t LO32Bits[] = {
|
||||
static const uint8_t LO32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// FGR64 Register Class...
|
||||
static MCPhysReg FGR64[] = {
|
||||
static const MCPhysReg FGR64[] = {
|
||||
Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64,
|
||||
};
|
||||
|
||||
// FGR64 Bit set.
|
||||
static uint8_t FGR64Bits[] = {
|
||||
static const uint8_t FGR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
|
||||
};
|
||||
|
||||
// GPR64 Register Class...
|
||||
static MCPhysReg GPR64[] = {
|
||||
static const MCPhysReg GPR64[] = {
|
||||
Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64,
|
||||
};
|
||||
|
||||
// GPR64 Bit set.
|
||||
static uint8_t GPR64Bits[] = {
|
||||
static const uint8_t GPR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// AFGR64 Register Class...
|
||||
static MCPhysReg AFGR64[] = {
|
||||
static const MCPhysReg AFGR64[] = {
|
||||
Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15,
|
||||
};
|
||||
|
||||
// AFGR64 Bit set.
|
||||
static uint8_t AFGR64Bits[] = {
|
||||
static const uint8_t AFGR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// FGR64_and_OddSP Register Class...
|
||||
static MCPhysReg FGR64_and_OddSP[] = {
|
||||
static const MCPhysReg FGR64_and_OddSP[] = {
|
||||
Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
|
||||
};
|
||||
|
||||
// FGR64_and_OddSP Bit set.
|
||||
static uint8_t FGR64_and_OddSPBits[] = {
|
||||
static const uint8_t FGR64_and_OddSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
|
||||
static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
|
||||
static const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
|
||||
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
|
||||
static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
|
||||
static const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||||
};
|
||||
|
||||
// AFGR64_and_OddSP Register Class...
|
||||
static MCPhysReg AFGR64_and_OddSP[] = {
|
||||
static const MCPhysReg AFGR64_and_OddSP[] = {
|
||||
Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
|
||||
};
|
||||
|
||||
// AFGR64_and_OddSP Bit set.
|
||||
static uint8_t AFGR64_and_OddSPBits[] = {
|
||||
static const uint8_t AFGR64_and_OddSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPU16Regs Register Class...
|
||||
static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
|
||||
static const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
|
||||
Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPU16Regs Bit set.
|
||||
static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
|
||||
static const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
|
||||
};
|
||||
|
||||
// ACC64DSP Register Class...
|
||||
static MCPhysReg ACC64DSP[] = {
|
||||
static const MCPhysReg ACC64DSP[] = {
|
||||
Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3,
|
||||
};
|
||||
|
||||
// ACC64DSP Bit set.
|
||||
static uint8_t ACC64DSPBits[] = {
|
||||
static const uint8_t ACC64DSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x3c,
|
||||
};
|
||||
|
||||
// OCTEON_MPL Register Class...
|
||||
static MCPhysReg OCTEON_MPL[] = {
|
||||
static const MCPhysReg OCTEON_MPL[] = {
|
||||
Mips_MPL0, Mips_MPL1, Mips_MPL2,
|
||||
};
|
||||
|
||||
// OCTEON_MPL Bit set.
|
||||
static uint8_t OCTEON_MPLBits[] = {
|
||||
static const uint8_t OCTEON_MPLBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
|
||||
};
|
||||
|
||||
// OCTEON_P Register Class...
|
||||
static MCPhysReg OCTEON_P[] = {
|
||||
static const MCPhysReg OCTEON_P[] = {
|
||||
Mips_P0, Mips_P1, Mips_P2,
|
||||
};
|
||||
|
||||
// OCTEON_P Bit set.
|
||||
static uint8_t OCTEON_PBits[] = {
|
||||
static const uint8_t OCTEON_PBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
||||
};
|
||||
|
||||
// ACC64 Register Class...
|
||||
static MCPhysReg ACC64[] = {
|
||||
static const MCPhysReg ACC64[] = {
|
||||
Mips_AC0,
|
||||
};
|
||||
|
||||
// ACC64 Bit set.
|
||||
static uint8_t ACC64Bits[] = {
|
||||
static const uint8_t ACC64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x04,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPURAReg Register Class...
|
||||
static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
|
||||
static const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
|
||||
Mips_RA_64,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPURAReg Bit set.
|
||||
static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
|
||||
static const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPUSPReg Register Class...
|
||||
static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
|
||||
static const MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
|
||||
Mips_SP_64,
|
||||
};
|
||||
|
||||
// GPR64_with_sub_32_in_CPUSPReg Bit set.
|
||||
static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
|
||||
static const uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
||||
};
|
||||
|
||||
// HI64 Register Class...
|
||||
static MCPhysReg HI64[] = {
|
||||
static const MCPhysReg HI64[] = {
|
||||
Mips_HI0_64,
|
||||
};
|
||||
|
||||
// HI64 Bit set.
|
||||
static uint8_t HI64Bits[] = {
|
||||
static const uint8_t HI64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
|
||||
};
|
||||
|
||||
// LO64 Register Class...
|
||||
static MCPhysReg LO64[] = {
|
||||
static const MCPhysReg LO64[] = {
|
||||
Mips_LO0_64,
|
||||
};
|
||||
|
||||
// LO64 Bit set.
|
||||
static uint8_t LO64Bits[] = {
|
||||
static const uint8_t LO64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
||||
};
|
||||
|
||||
// MSA128B Register Class...
|
||||
static MCPhysReg MSA128B[] = {
|
||||
static const MCPhysReg MSA128B[] = {
|
||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||
};
|
||||
|
||||
// MSA128B Bit set.
|
||||
static uint8_t MSA128BBits[] = {
|
||||
static const uint8_t MSA128BBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// MSA128D Register Class...
|
||||
static MCPhysReg MSA128D[] = {
|
||||
static const MCPhysReg MSA128D[] = {
|
||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||
};
|
||||
|
||||
// MSA128D Bit set.
|
||||
static uint8_t MSA128DBits[] = {
|
||||
static const uint8_t MSA128DBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// MSA128H Register Class...
|
||||
static MCPhysReg MSA128H[] = {
|
||||
static const MCPhysReg MSA128H[] = {
|
||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||
};
|
||||
|
||||
// MSA128H Bit set.
|
||||
static uint8_t MSA128HBits[] = {
|
||||
static const uint8_t MSA128HBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// MSA128W Register Class...
|
||||
static MCPhysReg MSA128W[] = {
|
||||
static const MCPhysReg MSA128W[] = {
|
||||
Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
|
||||
};
|
||||
|
||||
// MSA128W Bit set.
|
||||
static uint8_t MSA128WBits[] = {
|
||||
static const uint8_t MSA128WBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// MSA128B_with_sub_64_in_OddSP Register Class...
|
||||
static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
|
||||
static const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
|
||||
Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31,
|
||||
};
|
||||
|
||||
// MSA128B_with_sub_64_in_OddSP Bit set.
|
||||
static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
|
||||
static const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
|
||||
};
|
||||
|
||||
// ACC128 Register Class...
|
||||
static MCPhysReg ACC128[] = {
|
||||
static const MCPhysReg ACC128[] = {
|
||||
Mips_AC0_64,
|
||||
};
|
||||
|
||||
// ACC128 Bit set.
|
||||
static uint8_t ACC128Bits[] = {
|
||||
static const uint8_t ACC128Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
};
|
||||
|
||||
static MCRegisterClass MipsMCRegisterClasses[] = {
|
||||
static const MCRegisterClass MipsMCRegisterClasses[] = {
|
||||
{ "OddSP", OddSP, OddSPBits, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 },
|
||||
{ "CCR", CCR, CCRBits, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 },
|
||||
{ "COP2", COP2, COP2Bits, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 },
|
||||
|
|
|
|||
|
|
@ -82,8 +82,8 @@ typedef enum Mips_CondCode {
|
|||
#define GET_INSTRINFO_ENUM
|
||||
#include "MipsGenInstrInfo.inc"
|
||||
|
||||
static char *getRegisterName(unsigned RegNo);
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
|
||||
|
||||
static void set_mem_access(MCInst *MI, bool status)
|
||||
{
|
||||
|
|
@ -108,7 +108,7 @@ static bool isReg(MCInst *MI, unsigned OpNo, unsigned R)
|
|||
MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == R);
|
||||
}
|
||||
|
||||
static char* MipsFCCToString(Mips_CondCode CC)
|
||||
static const char* MipsFCCToString(Mips_CondCode CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: return 0; // never reach
|
||||
|
|
@ -315,14 +315,14 @@ static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
|
|||
SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
|
||||
}
|
||||
|
||||
static char *printAlias1(char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
|
||||
static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
|
||||
{
|
||||
SStream_concat(OS, "%s\t", Str);
|
||||
printOperand(MI, OpNo, OS);
|
||||
return cs_strdup(Str);
|
||||
}
|
||||
|
||||
static char *printAlias2(char *Str, MCInst *MI,
|
||||
static char *printAlias2(const char *Str, MCInst *MI,
|
||||
unsigned OpNo0, unsigned OpNo1, SStream *OS)
|
||||
{
|
||||
char *tmp;
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "MipsGenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ MIPS_REG_INVALID, NULL },
|
||||
|
||||
//{ MIPS_REG_0, "0"},
|
||||
|
|
@ -208,7 +208,7 @@ const char *Mips_reg_name(csh handle, unsigned int reg)
|
|||
#endif
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -9243,7 +9243,7 @@ void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
}
|
||||
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ MIPS_INS_INVALID, NULL },
|
||||
|
||||
{ MIPS_INS_ABSQ_S, "absq_s" },
|
||||
|
|
@ -9849,7 +9849,7 @@ const char *Mips_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ MIPS_GRP_INVALID, NULL },
|
||||
{ MIPS_GRP_JUMP, "jump" },
|
||||
|
|
@ -9931,7 +9931,7 @@ mips_reg Mips_map_register(unsigned int r)
|
|||
// for some reasons different Mips modes can map different register number to
|
||||
// the same Mips register. this function handles the issue for exposing Mips
|
||||
// operands by mapping internal registers to 'public' register.
|
||||
unsigned int map[] = { 0,
|
||||
static const unsigned int map[] = { 0,
|
||||
MIPS_REG_AT, MIPS_REG_DSPCCOND, MIPS_REG_DSPCARRY, MIPS_REG_DSPEFI, MIPS_REG_DSPOUTFLAG,
|
||||
MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, MIPS_REG_FP, MIPS_REG_GP, MIPS_REG_2,
|
||||
MIPS_REG_1, MIPS_REG_0, MIPS_REG_6, MIPS_REG_4, MIPS_REG_5,
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/// printInstruction - This method is automatically generated by tablegen
|
||||
/// from the instruction set description.
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
||||
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
|
||||
{
|
||||
static const uint32_t OpInfo[] = {
|
||||
0U, // PHI
|
||||
|
|
@ -2563,7 +2563,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ '#', 'E', 'H', '_', 'S', 'j', 'L', 'j', '_', 'S', 'e', 't', 'u', 'p', 9, 0,
|
||||
/* 16 */ 'b', 'd', 'z', 'l', 'a', '+', 32, 0,
|
||||
/* 24 */ 'b', 'd', 'n', 'z', 'l', 'a', '+', 32, 0,
|
||||
|
|
@ -4043,11 +4043,11 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 279 && "Invalid register number!");
|
||||
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ '*', '*', 'R', 'O', 'U', 'N', 'D', 'I', 'N', 'G', 32, 'M', 'O', 'D', 'E', '*', '*', 0,
|
||||
/* 18 */ '*', '*', 'F', 'R', 'A', 'M', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
|
||||
/* 36 */ '*', '*', 'B', 'A', 'S', 'E', 32, 'P', 'O', 'I', 'N', 'T', 'E', 'R', '*', '*', 0,
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ static InsnType fname(InsnType insn, unsigned startBit, \
|
|||
// FieldFromInstruction(fieldFromInstruction_2, uint16_t)
|
||||
FieldFromInstruction(fieldFromInstruction_4, uint32_t)
|
||||
|
||||
static uint8_t DecoderTable32[] = {
|
||||
static const uint8_t DecoderTable32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 26, 6, // Inst{31-26} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 11
|
||||
/* 7 */ MCD_OPC_Decode, 161, 7, 0, // Opcode: TDI
|
||||
|
|
|
|||
|
|
@ -347,7 +347,7 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg PPCRegDiffLists[] = {
|
||||
static const MCPhysReg PPCRegDiffLists[] = {
|
||||
/* 0 */ 0, 0,
|
||||
/* 2 */ 2, 1, 1, 1, 1, 1, 1, 1, 0,
|
||||
/* 11 */ 65527, 14, 1, 1, 1, 0,
|
||||
|
|
@ -391,13 +391,13 @@ static MCPhysReg PPCRegDiffLists[] = {
|
|||
/* 124 */ 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t PPCSubRegIdxLists[] = {
|
||||
static const uint16_t PPCSubRegIdxLists[] = {
|
||||
/* 0 */ 1, 0,
|
||||
/* 2 */ 3, 2, 0,
|
||||
/* 5 */ 6, 5, 4, 7, 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc PPCRegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc PPCRegDesc[] = { // Descriptors
|
||||
{ 4, 0, 0, 0, 0 },
|
||||
{ 962, 1, 61, 1, 1985 },
|
||||
{ 1119, 1, 1, 1, 1985 },
|
||||
|
|
@ -681,216 +681,216 @@ static MCRegisterDesc PPCRegDesc[] = { // Descriptors
|
|||
|
||||
|
||||
// GPRC Register Class...
|
||||
static MCPhysReg GPRC[] = {
|
||||
static const MCPhysReg GPRC[] = {
|
||||
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP,
|
||||
};
|
||||
|
||||
// GPRC Bit set.
|
||||
static uint8_t GPRCBits[] = {
|
||||
static const uint8_t GPRCBits[] = {
|
||||
0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// GPRC_NOR0 Register Class...
|
||||
static MCPhysReg GPRC_NOR0[] = {
|
||||
static const MCPhysReg GPRC_NOR0[] = {
|
||||
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO,
|
||||
};
|
||||
|
||||
// GPRC_NOR0 Bit set.
|
||||
static uint8_t GPRC_NOR0Bits[] = {
|
||||
static const uint8_t GPRC_NOR0Bits[] = {
|
||||
0x22, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// GPRC_and_GPRC_NOR0 Register Class...
|
||||
static MCPhysReg GPRC_and_GPRC_NOR0[] = {
|
||||
static const MCPhysReg GPRC_and_GPRC_NOR0[] = {
|
||||
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP,
|
||||
};
|
||||
|
||||
// GPRC_and_GPRC_NOR0 Bit set.
|
||||
static uint8_t GPRC_and_GPRC_NOR0Bits[] = {
|
||||
static const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
|
||||
0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// CRBITRC Register Class...
|
||||
static MCPhysReg CRBITRC[] = {
|
||||
static const MCPhysReg CRBITRC[] = {
|
||||
PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
|
||||
};
|
||||
|
||||
// CRBITRC Bit set.
|
||||
static uint8_t CRBITRCBits[] = {
|
||||
static const uint8_t CRBITRCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// F4RC Register Class...
|
||||
static MCPhysReg F4RC[] = {
|
||||
static const MCPhysReg F4RC[] = {
|
||||
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14,
|
||||
};
|
||||
|
||||
// F4RC Bit set.
|
||||
static uint8_t F4RCBits[] = {
|
||||
static const uint8_t F4RCBits[] = {
|
||||
0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// CRRC Register Class...
|
||||
static MCPhysReg CRRC[] = {
|
||||
static const MCPhysReg CRRC[] = {
|
||||
PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4,
|
||||
};
|
||||
|
||||
// CRRC Bit set.
|
||||
static uint8_t CRRCBits[] = {
|
||||
static const uint8_t CRRCBits[] = {
|
||||
0x00, 0xf8, 0x07,
|
||||
};
|
||||
|
||||
// CARRYRC Register Class...
|
||||
static MCPhysReg CARRYRC[] = {
|
||||
static const MCPhysReg CARRYRC[] = {
|
||||
PPC_CARRY,
|
||||
};
|
||||
|
||||
// CARRYRC Bit set.
|
||||
static uint8_t CARRYRCBits[] = {
|
||||
static const uint8_t CARRYRCBits[] = {
|
||||
0x04,
|
||||
};
|
||||
|
||||
// CCRC Register Class...
|
||||
static MCPhysReg CCRC[] = {
|
||||
static const MCPhysReg CCRC[] = {
|
||||
PPC_CC,
|
||||
};
|
||||
|
||||
// CCRC Bit set.
|
||||
static uint8_t CCRCBits[] = {
|
||||
static const uint8_t CCRCBits[] = {
|
||||
0x08,
|
||||
};
|
||||
|
||||
// CTRRC Register Class...
|
||||
static MCPhysReg CTRRC[] = {
|
||||
static const MCPhysReg CTRRC[] = {
|
||||
PPC_CTR,
|
||||
};
|
||||
|
||||
// CTRRC Bit set.
|
||||
static uint8_t CTRRCBits[] = {
|
||||
static const uint8_t CTRRCBits[] = {
|
||||
0x10,
|
||||
};
|
||||
|
||||
// VRSAVERC Register Class...
|
||||
static MCPhysReg VRSAVERC[] = {
|
||||
static const MCPhysReg VRSAVERC[] = {
|
||||
PPC_VRSAVE,
|
||||
};
|
||||
|
||||
// VRSAVERC Bit set.
|
||||
static uint8_t VRSAVERCBits[] = {
|
||||
static const uint8_t VRSAVERCBits[] = {
|
||||
0x00, 0x01,
|
||||
};
|
||||
|
||||
// VSFRC Register Class...
|
||||
static MCPhysReg VSFRC[] = {
|
||||
static const MCPhysReg VSFRC[] = {
|
||||
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
|
||||
};
|
||||
|
||||
// VSFRC Bit set.
|
||||
static uint8_t VSFRCBits[] = {
|
||||
static const uint8_t VSFRCBits[] = {
|
||||
0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// G8RC Register Class...
|
||||
static MCPhysReg G8RC[] = {
|
||||
static const MCPhysReg G8RC[] = {
|
||||
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8,
|
||||
};
|
||||
|
||||
// G8RC Bit set.
|
||||
static uint8_t G8RCBits[] = {
|
||||
static const uint8_t G8RCBits[] = {
|
||||
0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// G8RC_NOX0 Register Class...
|
||||
static MCPhysReg G8RC_NOX0[] = {
|
||||
static const MCPhysReg G8RC_NOX0[] = {
|
||||
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8,
|
||||
};
|
||||
|
||||
// G8RC_NOX0 Bit set.
|
||||
static uint8_t G8RC_NOX0Bits[] = {
|
||||
static const uint8_t G8RC_NOX0Bits[] = {
|
||||
0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// G8RC_and_G8RC_NOX0 Register Class...
|
||||
static MCPhysReg G8RC_and_G8RC_NOX0[] = {
|
||||
static const MCPhysReg G8RC_and_G8RC_NOX0[] = {
|
||||
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8,
|
||||
};
|
||||
|
||||
// G8RC_and_G8RC_NOX0 Bit set.
|
||||
static uint8_t G8RC_and_G8RC_NOX0Bits[] = {
|
||||
static const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
|
||||
0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// F8RC Register Class...
|
||||
static MCPhysReg F8RC[] = {
|
||||
static const MCPhysReg F8RC[] = {
|
||||
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14,
|
||||
};
|
||||
|
||||
// F8RC Bit set.
|
||||
static uint8_t F8RCBits[] = {
|
||||
static const uint8_t F8RCBits[] = {
|
||||
0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
||||
};
|
||||
|
||||
// VFRC Register Class...
|
||||
static MCPhysReg VFRC[] = {
|
||||
static const MCPhysReg VFRC[] = {
|
||||
PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
|
||||
};
|
||||
|
||||
// VFRC Bit set.
|
||||
static uint8_t VFRCBits[] = {
|
||||
static const uint8_t VFRCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// CTRRC8 Register Class...
|
||||
static MCPhysReg CTRRC8[] = {
|
||||
static const MCPhysReg CTRRC8[] = {
|
||||
PPC_CTR8,
|
||||
};
|
||||
|
||||
// CTRRC8 Bit set.
|
||||
static uint8_t CTRRC8Bits[] = {
|
||||
static const uint8_t CTRRC8Bits[] = {
|
||||
0x00, 0x00, 0x08,
|
||||
};
|
||||
|
||||
// VSRC Register Class...
|
||||
static MCPhysReg VSRC[] = {
|
||||
static const MCPhysReg VSRC[] = {
|
||||
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20,
|
||||
};
|
||||
|
||||
// VSRC Bit set.
|
||||
static uint8_t VSRCBits[] = {
|
||||
static const uint8_t VSRCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// VRRC Register Class...
|
||||
static MCPhysReg VRRC[] = {
|
||||
static const MCPhysReg VRRC[] = {
|
||||
PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20,
|
||||
};
|
||||
|
||||
// VRRC Bit set.
|
||||
static uint8_t VRRCBits[] = {
|
||||
static const uint8_t VRRCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// VSHRC Register Class...
|
||||
static MCPhysReg VSHRC[] = {
|
||||
static const MCPhysReg VSHRC[] = {
|
||||
PPC_VSH2, PPC_VSH3, PPC_VSH4, PPC_VSH5, PPC_VSH0, PPC_VSH1, PPC_VSH6, PPC_VSH7, PPC_VSH8, PPC_VSH9, PPC_VSH10, PPC_VSH11, PPC_VSH12, PPC_VSH13, PPC_VSH14, PPC_VSH15, PPC_VSH16, PPC_VSH17, PPC_VSH18, PPC_VSH19, PPC_VSH31, PPC_VSH30, PPC_VSH29, PPC_VSH28, PPC_VSH27, PPC_VSH26, PPC_VSH25, PPC_VSH24, PPC_VSH23, PPC_VSH22, PPC_VSH21, PPC_VSH20,
|
||||
};
|
||||
|
||||
// VSHRC Bit set.
|
||||
static uint8_t VSHRCBits[] = {
|
||||
static const uint8_t VSHRCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
// VSLRC Register Class...
|
||||
static MCPhysReg VSLRC[] = {
|
||||
static const MCPhysReg VSLRC[] = {
|
||||
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14,
|
||||
};
|
||||
|
||||
// VSLRC Bit set.
|
||||
static uint8_t VSLRCBits[] = {
|
||||
static const uint8_t VSLRCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
||||
};
|
||||
|
||||
static MCRegisterClass PPCMCRegisterClasses[] = {
|
||||
static const MCRegisterClass PPCMCRegisterClasses[] = {
|
||||
{ "GPRC", GPRC, GPRCBits, 34, sizeof(GPRCBits), PPC_GPRCRegClassID, 4, 4, 1, 1 },
|
||||
{ "GPRC_NOR0", GPRC_NOR0, GPRC_NOR0Bits, 34, sizeof(GPRC_NOR0Bits), PPC_GPRC_NOR0RegClassID, 4, 4, 1, 1 },
|
||||
{ "GPRC_and_GPRC_NOR0", GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC_GPRC_and_GPRC_NOR0RegClassID, 4, 4, 1, 1 },
|
||||
|
|
|
|||
|
|
@ -30,11 +30,11 @@
|
|||
#include "PPCMapping.h"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char *getRegisterName(unsigned RegNo);
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
#endif
|
||||
|
||||
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
|
||||
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
|
||||
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
|
||||
static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
|
||||
static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info);
|
||||
|
|
@ -624,7 +624,7 @@ static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
|
|||
#ifndef CAPSTONE_DIET
|
||||
/// stripRegisterPrefix - This method strips the character prefix from a
|
||||
/// register name so that only the number is left. Used by for linux asm.
|
||||
static char *stripRegisterPrefix(char *RegName)
|
||||
static const char *stripRegisterPrefix(const char *RegName)
|
||||
{
|
||||
switch (RegName[0]) {
|
||||
case 'r':
|
||||
|
|
@ -648,7 +648,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
|
|||
if (MCOperand_isReg(Op)) {
|
||||
unsigned reg = MCOperand_getReg(Op);
|
||||
#ifndef CAPSTONE_DIET
|
||||
char *RegName = getRegisterName(reg);
|
||||
const char *RegName = getRegisterName(reg);
|
||||
#endif
|
||||
// map to public register
|
||||
reg = PPC_map_register(reg);
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "PPCGenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ PPC_REG_INVALID, NULL },
|
||||
|
||||
{ PPC_REG_CARRY, "ca" },
|
||||
|
|
@ -211,7 +211,7 @@ const char *PPC_reg_name(csh handle, unsigned int reg)
|
|||
#endif
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -6924,7 +6924,7 @@ void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ PPC_INS_INVALID, NULL },
|
||||
|
||||
{ PPC_INS_ADD, "add" },
|
||||
|
|
@ -7865,7 +7865,7 @@ static name_map insn_name_maps[] = {
|
|||
};
|
||||
|
||||
// special alias insn
|
||||
static name_map alias_insn_names[] = {
|
||||
static const name_map alias_insn_names[] = {
|
||||
{ 0, NULL }
|
||||
};
|
||||
#endif
|
||||
|
|
@ -7891,7 +7891,7 @@ const char *PPC_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ PPC_GRP_INVALID, NULL },
|
||||
{ PPC_GRP_JUMP, "jump" },
|
||||
|
|
@ -7930,7 +7930,7 @@ const char *PPC_group_name(csh handle, unsigned int id)
|
|||
// map internal raw register to 'public' register
|
||||
ppc_reg PPC_map_register(unsigned int r)
|
||||
{
|
||||
static unsigned int map[] = { 0,
|
||||
static const unsigned int map[] = { 0,
|
||||
0, PPC_REG_CARRY, PPC_REG_CC, PPC_REG_CTR, 0,
|
||||
PPC_REG_LR, 0, PPC_REG_VRSAVE, PPC_REG_R0, 0,
|
||||
PPC_REG_CR0, PPC_REG_CR1, PPC_REG_CR2, PPC_REG_CR3, PPC_REG_CR4,
|
||||
|
|
@ -7995,7 +7995,7 @@ ppc_reg PPC_map_register(unsigned int r)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct ppc_alias alias_insn_name_maps[] = {
|
||||
static const struct ppc_alias alias_insn_name_maps[] = {
|
||||
//{ PPC_INS_BTA, "bta" },
|
||||
{ PPC_INS_B, PPC_BC_LT, "blt" },
|
||||
{ PPC_INS_B, PPC_BC_LE, "ble" },
|
||||
|
|
@ -8117,7 +8117,7 @@ bool PPC_alias_insn(const char *name, struct ppc_alias *alias)
|
|||
}
|
||||
|
||||
// list all relative branch instructions
|
||||
static unsigned int insn_abs[] = {
|
||||
static const unsigned int insn_abs[] = {
|
||||
PPC_BA,
|
||||
PPC_BCCA,
|
||||
PPC_BCCLA,
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
#include "../../include/sparc.h"
|
||||
|
||||
inline static char *SPARCCondCodeToString(sparc_cc CC)
|
||||
inline static const char *SPARCCondCodeToString(sparc_cc CC)
|
||||
{
|
||||
switch (CC) {
|
||||
default: return NULL; // unreachable
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
|
||||
/// printInstruction - This method is automatically generated by tablegen
|
||||
/// from the instruction set description.
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
||||
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
|
||||
{
|
||||
static const uint32_t OpInfo[] = {
|
||||
0U, // PHI
|
||||
|
|
@ -514,7 +514,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
|
||||
/* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
|
||||
/* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
|
||||
|
|
@ -1090,12 +1090,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 119 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'f', '1', '0', 0,
|
||||
/* 4 */ 'f', '2', '0', 0,
|
||||
/* 8 */ 'f', '3', '0', 0,
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||
return (insn & fieldMask) >> startBit; \
|
||||
}
|
||||
|
||||
static uint8_t DecoderTableSparc32[] = {
|
||||
static const uint8_t DecoderTableSparc32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 13, 2, // Skip to: 532
|
||||
/* 7 */ MCD_OPC_ExtractField, 22, 3, // Inst{24-22} ...
|
||||
|
|
@ -1455,7 +1455,7 @@ static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
|
|||
|
||||
#define DecodeToMCInst(fname,fieldname, InsnType) \
|
||||
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
|
||||
uint64_t Address, void *Decoder) \
|
||||
uint64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
InsnType tmp; \
|
||||
switch (Idx) { \
|
||||
|
|
@ -1945,11 +1945,11 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||
}
|
||||
|
||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
|
||||
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
|
|
|
|||
|
|
@ -173,7 +173,7 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg SparcRegDiffLists[] = {
|
||||
static const MCPhysReg SparcRegDiffLists[] = {
|
||||
/* 0 */ 65126, 1, 1, 1, 0,
|
||||
/* 5 */ 32, 1, 0,
|
||||
/* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
|
||||
|
|
@ -240,13 +240,13 @@ static MCPhysReg SparcRegDiffLists[] = {
|
|||
/* 212 */ 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t SparcSubRegIdxLists[] = {
|
||||
static const uint16_t SparcSubRegIdxLists[] = {
|
||||
/* 0 */ 1, 3, 0,
|
||||
/* 3 */ 2, 4, 0,
|
||||
/* 6 */ 2, 1, 3, 4, 5, 6, 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc SparcRegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc SparcRegDesc[] = { // Descriptors
|
||||
{ 3, 0, 0, 0, 0 },
|
||||
{ 406, 4, 4, 2, 3393 },
|
||||
{ 410, 4, 4, 2, 3393 },
|
||||
|
|
@ -369,86 +369,86 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
|
|||
};
|
||||
|
||||
// FCCRegs Register Class...
|
||||
static MCPhysReg FCCRegs[] = {
|
||||
static const MCPhysReg FCCRegs[] = {
|
||||
SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3,
|
||||
};
|
||||
|
||||
// FCCRegs Bit set.
|
||||
static uint8_t FCCRegsBits[] = {
|
||||
static const uint8_t FCCRegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
||||
};
|
||||
|
||||
// FPRegs Register Class...
|
||||
static MCPhysReg FPRegs[] = {
|
||||
static const MCPhysReg FPRegs[] = {
|
||||
SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31,
|
||||
};
|
||||
|
||||
// FPRegs Bit set.
|
||||
static uint8_t FPRegsBits[] = {
|
||||
static const uint8_t FPRegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// IntRegs Register Class...
|
||||
static MCPhysReg IntRegs[] = {
|
||||
static const MCPhysReg IntRegs[] = {
|
||||
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
|
||||
};
|
||||
|
||||
// IntRegs Bit set.
|
||||
static uint8_t IntRegsBits[] = {
|
||||
static const uint8_t IntRegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// DFPRegs Register Class...
|
||||
static MCPhysReg DFPRegs[] = {
|
||||
static const MCPhysReg DFPRegs[] = {
|
||||
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31,
|
||||
};
|
||||
|
||||
// DFPRegs Bit set.
|
||||
static uint8_t DFPRegsBits[] = {
|
||||
static const uint8_t DFPRegsBits[] = {
|
||||
0xf8, 0xff, 0xff, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// I64Regs Register Class...
|
||||
static MCPhysReg I64Regs[] = {
|
||||
static const MCPhysReg I64Regs[] = {
|
||||
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
|
||||
};
|
||||
|
||||
// I64Regs Bit set.
|
||||
static uint8_t I64RegsBits[] = {
|
||||
static const uint8_t I64RegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// DFPRegs_with_sub_even Register Class...
|
||||
static MCPhysReg DFPRegs_with_sub_even[] = {
|
||||
static const MCPhysReg DFPRegs_with_sub_even[] = {
|
||||
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15,
|
||||
};
|
||||
|
||||
// DFPRegs_with_sub_even Bit set.
|
||||
static uint8_t DFPRegs_with_sub_evenBits[] = {
|
||||
static const uint8_t DFPRegs_with_sub_evenBits[] = {
|
||||
0xf8, 0xff, 0x07,
|
||||
};
|
||||
|
||||
// QFPRegs Register Class...
|
||||
static MCPhysReg QFPRegs[] = {
|
||||
static const MCPhysReg QFPRegs[] = {
|
||||
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15,
|
||||
};
|
||||
|
||||
// QFPRegs Bit set.
|
||||
static uint8_t QFPRegsBits[] = {
|
||||
static const uint8_t QFPRegsBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
||||
};
|
||||
|
||||
// QFPRegs_with_sub_even Register Class...
|
||||
static MCPhysReg QFPRegs_with_sub_even[] = {
|
||||
static const MCPhysReg QFPRegs_with_sub_even[] = {
|
||||
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7,
|
||||
};
|
||||
|
||||
// QFPRegs_with_sub_even Bit set.
|
||||
static uint8_t QFPRegs_with_sub_evenBits[] = {
|
||||
static const uint8_t QFPRegs_with_sub_evenBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
|
||||
};
|
||||
|
||||
static MCRegisterClass SparcMCRegisterClasses[] = {
|
||||
static const MCRegisterClass SparcMCRegisterClasses[] = {
|
||||
{ "FCCRegs", FCCRegs, FCCRegsBits, 4, sizeof(FCCRegsBits), SP_FCCRegsRegClassID, 0, 0, 1, 1 },
|
||||
{ "FPRegs", FPRegs, FPRegsBits, 32, sizeof(FPRegsBits), SP_FPRegsRegClassID, 4, 4, 1, 1 },
|
||||
{ "IntRegs", IntRegs, IntRegsBits, 32, sizeof(IntRegsBits), SP_IntRegsRegClassID, 4, 4, 1, 1 },
|
||||
|
|
|
|||
|
|
@ -38,8 +38,8 @@
|
|||
|
||||
#include "Sparc.h"
|
||||
|
||||
static char *getRegisterName(unsigned RegNo);
|
||||
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
|
||||
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
|
||||
static void printOperand(MCInst *MI, int opNum, SStream *O);
|
||||
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "SparcGenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ SPARC_REG_INVALID, NULL },
|
||||
|
||||
{ SPARC_REG_F0, "f0"},
|
||||
|
|
@ -121,7 +121,7 @@ const char *Sparc_reg_name(csh handle, unsigned int reg)
|
|||
#endif
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -2775,7 +2775,7 @@ static insn_map insns[] = {
|
|||
static struct hint_map {
|
||||
unsigned int id;
|
||||
uint8_t hints;
|
||||
} insn_hints[] = {
|
||||
} const insn_hints[] = {
|
||||
{ SP_BPGEZapn, SPARC_HINT_A | SPARC_HINT_PN },
|
||||
{ SP_BPGEZapt, SPARC_HINT_A | SPARC_HINT_PT },
|
||||
{ SP_BPGEZnapn, SPARC_HINT_PN },
|
||||
|
|
@ -2833,7 +2833,7 @@ void Sparc_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
}
|
||||
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ SPARC_INS_INVALID, NULL },
|
||||
|
||||
{ SPARC_INS_ADDCC, "addcc" },
|
||||
|
|
@ -3120,7 +3120,7 @@ static name_map insn_name_maps[] = {
|
|||
|
||||
#ifndef CAPSTONE_DIET
|
||||
// special alias insn
|
||||
static name_map alias_insn_names[] = {
|
||||
static const name_map alias_insn_names[] = {
|
||||
{ 0, NULL }
|
||||
};
|
||||
#endif
|
||||
|
|
@ -3146,7 +3146,7 @@ const char *Sparc_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ SPARC_GRP_INVALID, NULL },
|
||||
{ SPARC_GRP_JUMP, "jump" },
|
||||
|
|
@ -3182,7 +3182,7 @@ const char *Sparc_group_name(csh handle, unsigned int id)
|
|||
// map internal raw register to 'public' register
|
||||
sparc_reg Sparc_map_register(unsigned int r)
|
||||
{
|
||||
static unsigned int map[] = { 0,
|
||||
static const unsigned int map[] = { 0,
|
||||
SPARC_REG_ICC, SPARC_REG_Y, SPARC_REG_F0, SPARC_REG_F2, SPARC_REG_F4,
|
||||
SPARC_REG_F6, SPARC_REG_F8, SPARC_REG_F10, SPARC_REG_F12, SPARC_REG_F14,
|
||||
SPARC_REG_F16, SPARC_REG_F18, SPARC_REG_F20, SPARC_REG_F22, SPARC_REG_F24,
|
||||
|
|
@ -3229,7 +3229,7 @@ sparc_reg Sparc_map_insn(const char *name)
|
|||
|
||||
// NOTE: put strings in the order of string length since
|
||||
// we are going to compare with mnemonic to find out CC
|
||||
static name_map alias_icc_maps[] = {
|
||||
static const name_map alias_icc_maps[] = {
|
||||
{ SPARC_CC_ICC_LEU, "leu" },
|
||||
{ SPARC_CC_ICC_POS, "pos" },
|
||||
{ SPARC_CC_ICC_NEG, "neg" },
|
||||
|
|
@ -3248,7 +3248,7 @@ static name_map alias_icc_maps[] = {
|
|||
{ SPARC_CC_ICC_L, "l" },
|
||||
};
|
||||
|
||||
static name_map alias_fcc_maps[] = {
|
||||
static const name_map alias_fcc_maps[] = {
|
||||
{ SPARC_CC_FCC_UGE, "uge" },
|
||||
{ SPARC_CC_FCC_ULE, "ule" },
|
||||
{ SPARC_CC_FCC_UG, "ug" },
|
||||
|
|
@ -3286,7 +3286,7 @@ sparc_cc Sparc_map_FCC(const char *name)
|
|||
return (i != -1)? i : SPARC_CC_INVALID;
|
||||
}
|
||||
|
||||
static name_map hint_maps[] = {
|
||||
static const name_map hint_maps[] = {
|
||||
{ SPARC_HINT_A, ",a" },
|
||||
{ SPARC_HINT_A | SPARC_HINT_PN, ",a,pn" },
|
||||
{ SPARC_HINT_PN, ",pn" },
|
||||
|
|
|
|||
|
|
@ -302,7 +302,7 @@ bool SystemZ_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst
|
|||
{
|
||||
uint64_t Inst;
|
||||
uint8_t Bytes[6];
|
||||
uint8_t *Table;
|
||||
const uint8_t *Table;
|
||||
uint16_t I;
|
||||
|
||||
// The top 2 bits of the first byte specify the size.
|
||||
|
|
|
|||
|
|
@ -932,7 +932,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'l', 'a', 'a', 9, 0,
|
||||
/* 5 */ 'l', 'a', 9, 0,
|
||||
/* 9 */ 'l', 'e', 'd', 'b', 'r', 'a', 9, 0,
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||
return (insn & fieldMask) >> startBit; \
|
||||
}
|
||||
|
||||
static uint8_t DecoderTable16[] = {
|
||||
static const uint8_t DecoderTable16[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 8, 8, // Inst{15-8} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 134
|
||||
/* 7 */ MCD_OPC_ExtractField, 4, 4, // Inst{7-4} ...
|
||||
|
|
@ -97,7 +97,7 @@ static uint8_t DecoderTable16[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTable32[] = {
|
||||
static const uint8_t DecoderTable32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 24, 8, // Inst{31-24} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 64, 4, 0, // Skip to: 11
|
||||
/* 7 */ MCD_OPC_Decode, 216, 6, 7, // Opcode: STH
|
||||
|
|
@ -833,7 +833,7 @@ static uint8_t DecoderTable32[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTable48[] = {
|
||||
static const uint8_t DecoderTable48[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 40, 8, // Inst{47-40} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 192, 1, 238, 0, // Skip to: 246
|
||||
/* 8 */ MCD_OPC_ExtractField, 32, 4, // Inst{35-32} ...
|
||||
|
|
@ -1697,7 +1697,7 @@ static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
|
|||
|
||||
#define DecodeToMCInst(fname,fieldname, InsnType) \
|
||||
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
|
||||
uint64_t Address, void *Decoder) \
|
||||
uint64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
InsnType tmp; \
|
||||
switch (Idx) { \
|
||||
|
|
@ -2936,11 +2936,11 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||
}
|
||||
|
||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
|
||||
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
|
|
|
|||
|
|
@ -157,7 +157,7 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg SystemZRegDiffLists[] = {
|
||||
static const MCPhysReg SystemZRegDiffLists[] = {
|
||||
/* 0 */ 65193, 1, 1, 1, 0,
|
||||
/* 5 */ 65469, 1, 0,
|
||||
/* 8 */ 65519, 2, 0,
|
||||
|
|
@ -205,13 +205,13 @@ static MCPhysReg SystemZRegDiffLists[] = {
|
|||
/* 171 */ 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t SystemZSubRegIdxLists[] = {
|
||||
static const uint16_t SystemZSubRegIdxLists[] = {
|
||||
/* 0 */ 5, 1, 0,
|
||||
/* 3 */ 6, 1, 2, 3, 0,
|
||||
/* 8 */ 6, 5, 1, 2, 4, 3, 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc SystemZRegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
|
||||
{ 2, 0, 0, 0, 0 },
|
||||
{ 0, 4, 4, 2, 2737 },
|
||||
{ 13, 38, 33, 1, 2737 },
|
||||
|
|
@ -313,126 +313,126 @@ static MCRegisterDesc SystemZRegDesc[] = { // Descriptors
|
|||
};
|
||||
|
||||
// GRX32Bit Register Class...
|
||||
static MCPhysReg GRX32Bit[] = {
|
||||
static const MCPhysReg GRX32Bit[] = {
|
||||
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H,
|
||||
};
|
||||
|
||||
// GRX32Bit Bit set.
|
||||
static uint8_t GRX32BitBits[] = {
|
||||
static const uint8_t GRX32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// FP32Bit Register Class...
|
||||
static MCPhysReg FP32Bit[] = {
|
||||
static const MCPhysReg FP32Bit[] = {
|
||||
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
|
||||
};
|
||||
|
||||
// FP32Bit Bit set.
|
||||
static uint8_t FP32BitBits[] = {
|
||||
static const uint8_t FP32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GR32Bit Register Class...
|
||||
static MCPhysReg GR32Bit[] = {
|
||||
static const MCPhysReg GR32Bit[] = {
|
||||
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
|
||||
};
|
||||
|
||||
// GR32Bit Bit set.
|
||||
static uint8_t GR32BitBits[] = {
|
||||
static const uint8_t GR32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GRH32Bit Register Class...
|
||||
static MCPhysReg GRH32Bit[] = {
|
||||
static const MCPhysReg GRH32Bit[] = {
|
||||
SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H,
|
||||
};
|
||||
|
||||
// GRH32Bit Bit set.
|
||||
static uint8_t GRH32BitBits[] = {
|
||||
static const uint8_t GRH32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// ADDR32Bit Register Class...
|
||||
static MCPhysReg ADDR32Bit[] = {
|
||||
static const MCPhysReg ADDR32Bit[] = {
|
||||
SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
|
||||
};
|
||||
|
||||
// ADDR32Bit Bit set.
|
||||
static uint8_t ADDR32BitBits[] = {
|
||||
static const uint8_t ADDR32BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// CCRegs Register Class...
|
||||
static MCPhysReg CCRegs[] = {
|
||||
static const MCPhysReg CCRegs[] = {
|
||||
SystemZ_CC,
|
||||
};
|
||||
|
||||
// CCRegs Bit set.
|
||||
static uint8_t CCRegsBits[] = {
|
||||
static const uint8_t CCRegsBits[] = {
|
||||
0x02,
|
||||
};
|
||||
|
||||
// FP64Bit Register Class...
|
||||
static MCPhysReg FP64Bit[] = {
|
||||
static const MCPhysReg FP64Bit[] = {
|
||||
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
|
||||
};
|
||||
|
||||
// FP64Bit Bit set.
|
||||
static uint8_t FP64BitBits[] = {
|
||||
static const uint8_t FP64BitBits[] = {
|
||||
0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GR64Bit Register Class...
|
||||
static MCPhysReg GR64Bit[] = {
|
||||
static const MCPhysReg GR64Bit[] = {
|
||||
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
|
||||
};
|
||||
|
||||
// GR64Bit Bit set.
|
||||
static uint8_t GR64BitBits[] = {
|
||||
static const uint8_t GR64BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// ADDR64Bit Register Class...
|
||||
static MCPhysReg ADDR64Bit[] = {
|
||||
static const MCPhysReg ADDR64Bit[] = {
|
||||
SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
|
||||
};
|
||||
|
||||
// ADDR64Bit Bit set.
|
||||
static uint8_t ADDR64BitBits[] = {
|
||||
static const uint8_t ADDR64BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// FP128Bit Register Class...
|
||||
static MCPhysReg FP128Bit[] = {
|
||||
static const MCPhysReg FP128Bit[] = {
|
||||
SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q,
|
||||
};
|
||||
|
||||
// FP128Bit Bit set.
|
||||
static uint8_t FP128BitBits[] = {
|
||||
static const uint8_t FP128BitBits[] = {
|
||||
0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR128Bit Register Class...
|
||||
static MCPhysReg GR128Bit[] = {
|
||||
static const MCPhysReg GR128Bit[] = {
|
||||
SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
|
||||
};
|
||||
|
||||
// GR128Bit Bit set.
|
||||
static uint8_t GR128BitBits[] = {
|
||||
static const uint8_t GR128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// ADDR128Bit Register Class...
|
||||
static MCPhysReg ADDR128Bit[] = {
|
||||
static const MCPhysReg ADDR128Bit[] = {
|
||||
SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
|
||||
};
|
||||
|
||||
// ADDR128Bit Bit set.
|
||||
static uint8_t ADDR128BitBits[] = {
|
||||
static const uint8_t ADDR128BitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
static MCRegisterClass SystemZMCRegisterClasses[] = {
|
||||
static const MCRegisterClass SystemZMCRegisterClasses[] = {
|
||||
{ "GRX32Bit", GRX32Bit, GRX32BitBits, 32, sizeof(GRX32BitBits), SystemZ_GRX32BitRegClassID, 4, 4, 1, 1 },
|
||||
{ "FP32Bit", FP32Bit, FP32BitBits, 16, sizeof(FP32BitBits), SystemZ_FP32BitRegClassID, 4, 4, 1, 1 },
|
||||
{ "GR32Bit", GR32Bit, GR32BitBits, 16, sizeof(GR32BitBits), SystemZ_GR32BitRegClassID, 4, 4, 1, 1 },
|
||||
|
|
|
|||
|
|
@ -364,7 +364,7 @@ static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
|
|||
|
||||
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
|
||||
{
|
||||
static char *const CondNames[] = {
|
||||
static const char *const CondNames[] = {
|
||||
"o", "h", "nle", "l", "nhe", "lh", "ne",
|
||||
"e", "nlh", "he", "nl", "le", "nh", "no"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include "SystemZGenInstrInfo.inc"
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ SYSZ_REG_INVALID, NULL },
|
||||
|
||||
{ SYSZ_REG_0, "0"},
|
||||
|
|
@ -66,7 +66,7 @@ const char *SystemZ_reg_name(csh handle, unsigned int reg)
|
|||
#endif
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -4344,7 +4344,7 @@ void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ SYSZ_INS_INVALID, NULL },
|
||||
|
||||
{ SYSZ_INS_A, "a" },
|
||||
|
|
@ -5031,7 +5031,7 @@ static name_map insn_name_maps[] = {
|
|||
};
|
||||
|
||||
// special alias insn
|
||||
static name_map alias_insn_names[] = {
|
||||
static const name_map alias_insn_names[] = {
|
||||
{ 0, NULL }
|
||||
};
|
||||
#endif
|
||||
|
|
@ -5057,7 +5057,7 @@ const char *SystemZ_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ SYSZ_GRP_INVALID, NULL },
|
||||
{ SYSZ_GRP_JUMP, "jump" },
|
||||
|
|
@ -5091,7 +5091,7 @@ const char *SystemZ_group_name(csh handle, unsigned int id)
|
|||
// map internal raw register to 'public' register
|
||||
sysz_reg SystemZ_map_register(unsigned int r)
|
||||
{
|
||||
static unsigned int map[] = { 0,
|
||||
static const unsigned int map[] = { 0,
|
||||
SYSZ_REG_CC, SYSZ_REG_F0, SYSZ_REG_F1, SYSZ_REG_F2, SYSZ_REG_F3,
|
||||
SYSZ_REG_F4, SYSZ_REG_F5, SYSZ_REG_F6, SYSZ_REG_F7, SYSZ_REG_F8,
|
||||
SYSZ_REG_F9, SYSZ_REG_F10, SYSZ_REG_F11, SYSZ_REG_F12, SYSZ_REG_F13,
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ enum {
|
|||
static void translateRegister(MCInst *mcInst, Reg reg)
|
||||
{
|
||||
#define ENTRY(x) X86_##x,
|
||||
uint8_t llvmRegnums[] = {
|
||||
static const uint8_t llvmRegnums[] = {
|
||||
ALL_REGS
|
||||
0
|
||||
};
|
||||
|
|
|
|||
|
|
@ -12556,7 +12556,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 32, 9, 0,
|
||||
/* 18 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 32, 9, 0,
|
||||
/* 36 */ 'k', 'a', 'n', 'd', 'b', 32, 9, 0,
|
||||
|
|
@ -15387,12 +15387,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 234 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 's', 't', '(', '0', ')', 0,
|
||||
/* 6 */ 's', 't', '(', '1', ')', 0,
|
||||
/* 12 */ 's', 't', '(', '2', ')', 0,
|
||||
|
|
|
|||
|
|
@ -12556,7 +12556,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '3', '2', 'x', '4', 32, 9, 0,
|
||||
/* 18 */ 'v', 'b', 'r', 'o', 'a', 'd', 'c', 'a', 's', 't', 'i', '6', '4', 'x', '4', 32, 9, 0,
|
||||
/* 36 */ 'k', 'a', 'n', 'd', 'b', 32, 9, 0,
|
||||
|
|
@ -14782,12 +14782,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 234 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 's', 't', '(', '0', ')', 0,
|
||||
/* 6 */ 's', 't', '(', '1', ')', 0,
|
||||
/* 12 */ 's', 't', '(', '2', ')', 0,
|
||||
|
|
|
|||
|
|
@ -1689,7 +1689,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'x', 's', 'a', 'v', 'e', '6', '4', 9, 0,
|
||||
/* 9 */ 'x', 'r', 's', 't', 'o', 'r', '6', '4', 9, 0,
|
||||
/* 19 */ 'x', 's', 'a', 'v', 'e', 'o', 'p', 't', '6', '4', 9, 0,
|
||||
|
|
@ -2513,12 +2513,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 234 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 's', 't', '(', '0', ')', 0,
|
||||
/* 6 */ 's', 't', '(', '1', ')', 0,
|
||||
/* 12 */ 's', 't', '(', '2', ')', 0,
|
||||
|
|
|
|||
|
|
@ -1689,7 +1689,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'j', 'a', 9, 0,
|
||||
/* 4 */ 's', 'e', 't', 'a', 9, 0,
|
||||
/* 10 */ 'c', 'm', 'p', 'x', 'c', 'h', 'g', '1', '6', 'b', 9, 0,
|
||||
|
|
@ -2829,12 +2829,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 234 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 's', 't', '(', '0', ')', 0,
|
||||
/* 6 */ 's', 't', '(', '1', ')', 0,
|
||||
/* 12 */ 's', 't', '(', '2', ')', 0,
|
||||
|
|
|
|||
|
|
@ -339,7 +339,7 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg X86RegDiffLists[] = {
|
||||
static const MCPhysReg X86RegDiffLists[] = {
|
||||
/* 0 */ 0, 1, 0,
|
||||
/* 3 */ 2, 1, 0,
|
||||
/* 6 */ 5, 1, 0,
|
||||
|
|
@ -390,14 +390,14 @@ static MCPhysReg X86RegDiffLists[] = {
|
|||
/* 149 */ 65520, 65520, 65535, 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t X86SubRegIdxLists[] = {
|
||||
static const uint16_t X86SubRegIdxLists[] = {
|
||||
/* 0 */ 4, 3, 1, 0,
|
||||
/* 4 */ 4, 3, 1, 2, 0,
|
||||
/* 9 */ 4, 3, 0,
|
||||
/* 12 */ 6, 5, 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc X86RegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc X86RegDesc[] = { // Descriptors
|
||||
{ 5, 0, 0, 0, 0 },
|
||||
{ 812, 2, 90, 3, 2273 },
|
||||
{ 840, 2, 86, 3, 2273 },
|
||||
|
|
@ -635,792 +635,792 @@ static MCRegisterDesc X86RegDesc[] = { // Descriptors
|
|||
};
|
||||
|
||||
// GR8 Register Class...
|
||||
static MCPhysReg GR8[] = {
|
||||
static const MCPhysReg GR8[] = {
|
||||
X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH, X86_SIL, X86_DIL, X86_BPL, X86_SPL, X86_R8B, X86_R9B, X86_R10B, X86_R11B, X86_R14B, X86_R15B, X86_R12B, X86_R13B,
|
||||
};
|
||||
|
||||
// GR8 Bit set.
|
||||
static uint8_t GR8Bits[] = {
|
||||
static const uint8_t GR8Bits[] = {
|
||||
0xb6, 0xa6, 0x01, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR8_NOREX Register Class...
|
||||
static MCPhysReg GR8_NOREX[] = {
|
||||
static const MCPhysReg GR8_NOREX[] = {
|
||||
X86_AL, X86_CL, X86_DL, X86_AH, X86_CH, X86_DH, X86_BL, X86_BH,
|
||||
};
|
||||
|
||||
// GR8_NOREX Bit set.
|
||||
static uint8_t GR8_NOREXBits[] = {
|
||||
static const uint8_t GR8_NOREXBits[] = {
|
||||
0x36, 0x26, 0x01,
|
||||
};
|
||||
|
||||
// GR8_ABCD_H Register Class...
|
||||
static MCPhysReg GR8_ABCD_H[] = {
|
||||
static const MCPhysReg GR8_ABCD_H[] = {
|
||||
X86_AH, X86_CH, X86_DH, X86_BH,
|
||||
};
|
||||
|
||||
// GR8_ABCD_H Bit set.
|
||||
static uint8_t GR8_ABCD_HBits[] = {
|
||||
static const uint8_t GR8_ABCD_HBits[] = {
|
||||
0x12, 0x22,
|
||||
};
|
||||
|
||||
// GR8_ABCD_L Register Class...
|
||||
static MCPhysReg GR8_ABCD_L[] = {
|
||||
static const MCPhysReg GR8_ABCD_L[] = {
|
||||
X86_AL, X86_CL, X86_DL, X86_BL,
|
||||
};
|
||||
|
||||
// GR8_ABCD_L Bit set.
|
||||
static uint8_t GR8_ABCD_LBits[] = {
|
||||
static const uint8_t GR8_ABCD_LBits[] = {
|
||||
0x24, 0x04, 0x01,
|
||||
};
|
||||
|
||||
// GR16 Register Class...
|
||||
static MCPhysReg GR16[] = {
|
||||
static const MCPhysReg GR16[] = {
|
||||
X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP, X86_R8W, X86_R9W, X86_R10W, X86_R11W, X86_R14W, X86_R15W, X86_R12W, X86_R13W,
|
||||
};
|
||||
|
||||
// GR16 Bit set.
|
||||
static uint8_t GR16Bits[] = {
|
||||
static const uint8_t GR16Bits[] = {
|
||||
0x48, 0x51, 0x04, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR16_NOREX Register Class...
|
||||
static MCPhysReg GR16_NOREX[] = {
|
||||
static const MCPhysReg GR16_NOREX[] = {
|
||||
X86_AX, X86_CX, X86_DX, X86_SI, X86_DI, X86_BX, X86_BP, X86_SP,
|
||||
};
|
||||
|
||||
// GR16_NOREX Bit set.
|
||||
static uint8_t GR16_NOREXBits[] = {
|
||||
static const uint8_t GR16_NOREXBits[] = {
|
||||
0x48, 0x51, 0x04, 0x00, 0x00, 0xa0,
|
||||
};
|
||||
|
||||
// VK1 Register Class...
|
||||
static MCPhysReg VK1[] = {
|
||||
static const MCPhysReg VK1[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK1 Bit set.
|
||||
static uint8_t VK1Bits[] = {
|
||||
static const uint8_t VK1Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// VK16 Register Class...
|
||||
static MCPhysReg VK16[] = {
|
||||
static const MCPhysReg VK16[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK16 Bit set.
|
||||
static uint8_t VK16Bits[] = {
|
||||
static const uint8_t VK16Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// VK2 Register Class...
|
||||
static MCPhysReg VK2[] = {
|
||||
static const MCPhysReg VK2[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK2 Bit set.
|
||||
static uint8_t VK2Bits[] = {
|
||||
static const uint8_t VK2Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// VK4 Register Class...
|
||||
static MCPhysReg VK4[] = {
|
||||
static const MCPhysReg VK4[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK4 Bit set.
|
||||
static uint8_t VK4Bits[] = {
|
||||
static const uint8_t VK4Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// VK8 Register Class...
|
||||
static MCPhysReg VK8[] = {
|
||||
static const MCPhysReg VK8[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK8 Bit set.
|
||||
static uint8_t VK8Bits[] = {
|
||||
static const uint8_t VK8Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// VK16WM Register Class...
|
||||
static MCPhysReg VK16WM[] = {
|
||||
static const MCPhysReg VK16WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK16WM Bit set.
|
||||
static uint8_t VK16WMBits[] = {
|
||||
static const uint8_t VK16WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// VK1WM Register Class...
|
||||
static MCPhysReg VK1WM[] = {
|
||||
static const MCPhysReg VK1WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK1WM Bit set.
|
||||
static uint8_t VK1WMBits[] = {
|
||||
static const uint8_t VK1WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// VK2WM Register Class...
|
||||
static MCPhysReg VK2WM[] = {
|
||||
static const MCPhysReg VK2WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK2WM Bit set.
|
||||
static uint8_t VK2WMBits[] = {
|
||||
static const uint8_t VK2WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// VK4WM Register Class...
|
||||
static MCPhysReg VK4WM[] = {
|
||||
static const MCPhysReg VK4WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK4WM Bit set.
|
||||
static uint8_t VK4WMBits[] = {
|
||||
static const uint8_t VK4WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// VK8WM Register Class...
|
||||
static MCPhysReg VK8WM[] = {
|
||||
static const MCPhysReg VK8WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK8WM Bit set.
|
||||
static uint8_t VK8WMBits[] = {
|
||||
static const uint8_t VK8WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// SEGMENT_REG Register Class...
|
||||
static MCPhysReg SEGMENT_REG[] = {
|
||||
static const MCPhysReg SEGMENT_REG[] = {
|
||||
X86_CS, X86_DS, X86_SS, X86_ES, X86_FS, X86_GS,
|
||||
};
|
||||
|
||||
// SEGMENT_REG Bit set.
|
||||
static uint8_t SEGMENT_REGBits[] = {
|
||||
static const uint8_t SEGMENT_REGBits[] = {
|
||||
0x00, 0x08, 0x02, 0x10, 0x03, 0x00, 0x02,
|
||||
};
|
||||
|
||||
// GR16_ABCD Register Class...
|
||||
static MCPhysReg GR16_ABCD[] = {
|
||||
static const MCPhysReg GR16_ABCD[] = {
|
||||
X86_AX, X86_CX, X86_DX, X86_BX,
|
||||
};
|
||||
|
||||
// GR16_ABCD Bit set.
|
||||
static uint8_t GR16_ABCDBits[] = {
|
||||
static const uint8_t GR16_ABCDBits[] = {
|
||||
0x08, 0x11, 0x04,
|
||||
};
|
||||
|
||||
// FPCCR Register Class...
|
||||
static MCPhysReg FPCCR[] = {
|
||||
static const MCPhysReg FPCCR[] = {
|
||||
X86_FPSW,
|
||||
};
|
||||
|
||||
// FPCCR Bit set.
|
||||
static uint8_t FPCCRBits[] = {
|
||||
static const uint8_t FPCCRBits[] = {
|
||||
0x00, 0x00, 0x00, 0x80,
|
||||
};
|
||||
|
||||
// FR32X Register Class...
|
||||
static MCPhysReg FR32X[] = {
|
||||
static const MCPhysReg FR32X[] = {
|
||||
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
|
||||
};
|
||||
|
||||
// FR32X Bit set.
|
||||
static uint8_t FR32XBits[] = {
|
||||
static const uint8_t FR32XBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// FR32 Register Class...
|
||||
static MCPhysReg FR32[] = {
|
||||
static const MCPhysReg FR32[] = {
|
||||
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
|
||||
};
|
||||
|
||||
// FR32 Bit set.
|
||||
static uint8_t FR32Bits[] = {
|
||||
static const uint8_t FR32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GR32 Register Class...
|
||||
static MCPhysReg GR32[] = {
|
||||
static const MCPhysReg GR32[] = {
|
||||
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
|
||||
};
|
||||
|
||||
// GR32 Bit set.
|
||||
static uint8_t GR32Bits[] = {
|
||||
static const uint8_t GR32Bits[] = {
|
||||
0x00, 0x00, 0xf8, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR32_NOAX Register Class...
|
||||
static MCPhysReg GR32_NOAX[] = {
|
||||
static const MCPhysReg GR32_NOAX[] = {
|
||||
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
|
||||
};
|
||||
|
||||
// GR32_NOAX Bit set.
|
||||
static uint8_t GR32_NOAXBits[] = {
|
||||
static const uint8_t GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0xf0, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR32_NOSP Register Class...
|
||||
static MCPhysReg GR32_NOSP[] = {
|
||||
static const MCPhysReg GR32_NOSP[] = {
|
||||
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
|
||||
};
|
||||
|
||||
// GR32_NOSP Bit set.
|
||||
static uint8_t GR32_NOSPBits[] = {
|
||||
static const uint8_t GR32_NOSPBits[] = {
|
||||
0x00, 0x00, 0xf8, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_NOSP Register Class...
|
||||
static MCPhysReg GR32_NOAX_and_GR32_NOSP[] = {
|
||||
static const MCPhysReg GR32_NOAX_and_GR32_NOSP[] = {
|
||||
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_R8D, X86_R9D, X86_R10D, X86_R11D, X86_R14D, X86_R15D, X86_R12D, X86_R13D,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_NOSP Bit set.
|
||||
static uint8_t GR32_NOAX_and_GR32_NOSPBits[] = {
|
||||
static const uint8_t GR32_NOAX_and_GR32_NOSPBits[] = {
|
||||
0x00, 0x00, 0xf0, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// DEBUG_REG Register Class...
|
||||
static MCPhysReg DEBUG_REG[] = {
|
||||
static const MCPhysReg DEBUG_REG[] = {
|
||||
X86_DR0, X86_DR1, X86_DR2, X86_DR3, X86_DR4, X86_DR5, X86_DR6, X86_DR7,
|
||||
};
|
||||
|
||||
// DEBUG_REG Bit set.
|
||||
static uint8_t DEBUG_REGBits[] = {
|
||||
static const uint8_t DEBUG_REGBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR32_NOREX Register Class...
|
||||
static MCPhysReg GR32_NOREX[] = {
|
||||
static const MCPhysReg GR32_NOREX[] = {
|
||||
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP,
|
||||
};
|
||||
|
||||
// GR32_NOREX Bit set.
|
||||
static uint8_t GR32_NOREXBits[] = {
|
||||
static const uint8_t GR32_NOREXBits[] = {
|
||||
0x00, 0x00, 0xf8, 0x61,
|
||||
};
|
||||
|
||||
// VK32 Register Class...
|
||||
static MCPhysReg VK32[] = {
|
||||
static const MCPhysReg VK32[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK32 Bit set.
|
||||
static uint8_t VK32Bits[] = {
|
||||
static const uint8_t VK32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_NOREX Register Class...
|
||||
static MCPhysReg GR32_NOAX_and_GR32_NOREX[] = {
|
||||
static const MCPhysReg GR32_NOAX_and_GR32_NOREX[] = {
|
||||
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP, X86_ESP,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_NOREX Bit set.
|
||||
static uint8_t GR32_NOAX_and_GR32_NOREXBits[] = {
|
||||
static const uint8_t GR32_NOAX_and_GR32_NOREXBits[] = {
|
||||
0x00, 0x00, 0xf0, 0x61,
|
||||
};
|
||||
|
||||
// GR32_NOREX_NOSP Register Class...
|
||||
static MCPhysReg GR32_NOREX_NOSP[] = {
|
||||
static const MCPhysReg GR32_NOREX_NOSP[] = {
|
||||
X86_EAX, X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP,
|
||||
};
|
||||
|
||||
// GR32_NOREX_NOSP Bit set.
|
||||
static uint8_t GR32_NOREX_NOSPBits[] = {
|
||||
static const uint8_t GR32_NOREX_NOSPBits[] = {
|
||||
0x00, 0x00, 0xf8, 0x21,
|
||||
};
|
||||
|
||||
// RFP32 Register Class...
|
||||
static MCPhysReg RFP32[] = {
|
||||
static const MCPhysReg RFP32[] = {
|
||||
X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
|
||||
};
|
||||
|
||||
// RFP32 Bit set.
|
||||
static uint8_t RFP32Bits[] = {
|
||||
static const uint8_t RFP32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
|
||||
};
|
||||
|
||||
// VK32WM Register Class...
|
||||
static MCPhysReg VK32WM[] = {
|
||||
static const MCPhysReg VK32WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK32WM Bit set.
|
||||
static uint8_t VK32WMBits[] = {
|
||||
static const uint8_t VK32WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_NOREX_NOSP Register Class...
|
||||
static MCPhysReg GR32_NOAX_and_GR32_NOREX_NOSP[] = {
|
||||
static const MCPhysReg GR32_NOAX_and_GR32_NOREX_NOSP[] = {
|
||||
X86_ECX, X86_EDX, X86_ESI, X86_EDI, X86_EBX, X86_EBP,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_NOREX_NOSP Bit set.
|
||||
static uint8_t GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
|
||||
static const uint8_t GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
|
||||
0x00, 0x00, 0xf0, 0x21,
|
||||
};
|
||||
|
||||
// GR32_ABCD Register Class...
|
||||
static MCPhysReg GR32_ABCD[] = {
|
||||
static const MCPhysReg GR32_ABCD[] = {
|
||||
X86_EAX, X86_ECX, X86_EDX, X86_EBX,
|
||||
};
|
||||
|
||||
// GR32_ABCD Bit set.
|
||||
static uint8_t GR32_ABCDBits[] = {
|
||||
static const uint8_t GR32_ABCDBits[] = {
|
||||
0x00, 0x00, 0x68, 0x01,
|
||||
};
|
||||
|
||||
// GR32_ABCD_and_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR32_ABCD_and_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR32_ABCD_and_GR32_NOAX[] = {
|
||||
X86_ECX, X86_EDX, X86_EBX,
|
||||
};
|
||||
|
||||
// GR32_ABCD_and_GR32_NOAX Bit set.
|
||||
static uint8_t GR32_ABCD_and_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR32_ABCD_and_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x60, 0x01,
|
||||
};
|
||||
|
||||
// GR32_TC Register Class...
|
||||
static MCPhysReg GR32_TC[] = {
|
||||
static const MCPhysReg GR32_TC[] = {
|
||||
X86_EAX, X86_ECX, X86_EDX,
|
||||
};
|
||||
|
||||
// GR32_TC Bit set.
|
||||
static uint8_t GR32_TCBits[] = {
|
||||
static const uint8_t GR32_TCBits[] = {
|
||||
0x00, 0x00, 0x48, 0x01,
|
||||
};
|
||||
|
||||
// GR32_AD Register Class...
|
||||
static MCPhysReg GR32_AD[] = {
|
||||
static const MCPhysReg GR32_AD[] = {
|
||||
X86_EAX, X86_EDX,
|
||||
};
|
||||
|
||||
// GR32_AD Bit set.
|
||||
static uint8_t GR32_ADBits[] = {
|
||||
static const uint8_t GR32_ADBits[] = {
|
||||
0x00, 0x00, 0x08, 0x01,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_TC Register Class...
|
||||
static MCPhysReg GR32_NOAX_and_GR32_TC[] = {
|
||||
static const MCPhysReg GR32_NOAX_and_GR32_TC[] = {
|
||||
X86_ECX, X86_EDX,
|
||||
};
|
||||
|
||||
// GR32_NOAX_and_GR32_TC Bit set.
|
||||
static uint8_t GR32_NOAX_and_GR32_TCBits[] = {
|
||||
static const uint8_t GR32_NOAX_and_GR32_TCBits[] = {
|
||||
0x00, 0x00, 0x40, 0x01,
|
||||
};
|
||||
|
||||
// CCR Register Class...
|
||||
static MCPhysReg CCR[] = {
|
||||
static const MCPhysReg CCR[] = {
|
||||
X86_EFLAGS,
|
||||
};
|
||||
|
||||
// CCR Bit set.
|
||||
static uint8_t CCRBits[] = {
|
||||
static const uint8_t CCRBits[] = {
|
||||
0x00, 0x00, 0x00, 0x02,
|
||||
};
|
||||
|
||||
// GR32_AD_and_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR32_AD_and_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR32_AD_and_GR32_NOAX[] = {
|
||||
X86_EDX,
|
||||
};
|
||||
|
||||
// GR32_AD_and_GR32_NOAX Bit set.
|
||||
static uint8_t GR32_AD_and_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR32_AD_and_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x01,
|
||||
};
|
||||
|
||||
// RFP64 Register Class...
|
||||
static MCPhysReg RFP64[] = {
|
||||
static const MCPhysReg RFP64[] = {
|
||||
X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
|
||||
};
|
||||
|
||||
// RFP64 Bit set.
|
||||
static uint8_t RFP64Bits[] = {
|
||||
static const uint8_t RFP64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
|
||||
};
|
||||
|
||||
// FR64X Register Class...
|
||||
static MCPhysReg FR64X[] = {
|
||||
static const MCPhysReg FR64X[] = {
|
||||
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
|
||||
};
|
||||
|
||||
// FR64X Bit set.
|
||||
static uint8_t FR64XBits[] = {
|
||||
static const uint8_t FR64XBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GR64 Register Class...
|
||||
static MCPhysReg GR64[] = {
|
||||
static const MCPhysReg GR64[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP, X86_RIP,
|
||||
};
|
||||
|
||||
// GR64 Bit set.
|
||||
static uint8_t GR64Bits[] = {
|
||||
static const uint8_t GR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// CONTROL_REG Register Class...
|
||||
static MCPhysReg CONTROL_REG[] = {
|
||||
static const MCPhysReg CONTROL_REG[] = {
|
||||
X86_CR0, X86_CR1, X86_CR2, X86_CR3, X86_CR4, X86_CR5, X86_CR6, X86_CR7, X86_CR8, X86_CR9, X86_CR10, X86_CR11, X86_CR12, X86_CR13, X86_CR14, X86_CR15,
|
||||
};
|
||||
|
||||
// CONTROL_REG Bit set.
|
||||
static uint8_t CONTROL_REGBits[] = {
|
||||
static const uint8_t CONTROL_REGBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// FR64 Register Class...
|
||||
static MCPhysReg FR64[] = {
|
||||
static const MCPhysReg FR64[] = {
|
||||
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
|
||||
};
|
||||
|
||||
// FR64 Bit set.
|
||||
static uint8_t FR64Bits[] = {
|
||||
static const uint8_t FR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// GR64_with_sub_8bit Register Class...
|
||||
static MCPhysReg GR64_with_sub_8bit[] = {
|
||||
static const MCPhysReg GR64_with_sub_8bit[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP,
|
||||
};
|
||||
|
||||
// GR64_with_sub_8bit Bit set.
|
||||
static uint8_t GR64_with_sub_8bitBits[] = {
|
||||
static const uint8_t GR64_with_sub_8bitBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR64_NOSP Register Class...
|
||||
static MCPhysReg GR64_NOSP[] = {
|
||||
static const MCPhysReg GR64_NOSP[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP,
|
||||
};
|
||||
|
||||
// GR64_NOSP Bit set.
|
||||
static uint8_t GR64_NOSPBits[] = {
|
||||
static const uint8_t GR64_NOSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX[] = {
|
||||
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP, X86_RSP,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf0, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP[] = {
|
||||
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R10, X86_R11, X86_RBX, X86_R14, X86_R15, X86_R12, X86_R13, X86_RBP,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSPBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf0, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR64_NOREX Register Class...
|
||||
static MCPhysReg GR64_NOREX[] = {
|
||||
static const MCPhysReg GR64_NOREX[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP, X86_RIP,
|
||||
};
|
||||
|
||||
// GR64_NOREX Bit set.
|
||||
static uint8_t GR64_NOREXBits[] = {
|
||||
static const uint8_t GR64_NOREXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0x1b,
|
||||
};
|
||||
|
||||
// GR64_TC Register Class...
|
||||
static MCPhysReg GR64_TC[] = {
|
||||
static const MCPhysReg GR64_TC[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11, X86_RIP,
|
||||
};
|
||||
|
||||
// GR64_TC Bit set.
|
||||
static uint8_t GR64_TCBits[] = {
|
||||
static const uint8_t GR64_TCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xc8, 0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c,
|
||||
};
|
||||
|
||||
// GR64_NOSP_and_GR64_TC Register Class...
|
||||
static MCPhysReg GR64_NOSP_and_GR64_TC[] = {
|
||||
static const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11,
|
||||
};
|
||||
|
||||
// GR64_NOSP_and_GR64_TC Bit set.
|
||||
static uint8_t GR64_NOSP_and_GR64_TCBits[] = {
|
||||
static const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xc8, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c,
|
||||
};
|
||||
|
||||
// GR64_with_sub_16bit_in_GR16_NOREX Register Class...
|
||||
static MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
|
||||
static const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP,
|
||||
};
|
||||
|
||||
// GR64_with_sub_16bit_in_GR16_NOREX Bit set.
|
||||
static uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
|
||||
static const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0x19,
|
||||
};
|
||||
|
||||
// VK64 Register Class...
|
||||
static MCPhysReg VK64[] = {
|
||||
static const MCPhysReg VK64[] = {
|
||||
X86_K0, X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK64 Bit set.
|
||||
static uint8_t VK64Bits[] = {
|
||||
static const uint8_t VK64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// VR64 Register Class...
|
||||
static MCPhysReg VR64[] = {
|
||||
static const MCPhysReg VR64[] = {
|
||||
X86_MM0, X86_MM1, X86_MM2, X86_MM3, X86_MM4, X86_MM5, X86_MM6, X86_MM7,
|
||||
};
|
||||
|
||||
// VR64 Bit set.
|
||||
static uint8_t VR64Bits[] = {
|
||||
static const uint8_t VR64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// GR64_NOREX_NOSP Register Class...
|
||||
static MCPhysReg GR64_NOREX_NOSP[] = {
|
||||
static const MCPhysReg GR64_NOREX_NOSP[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP,
|
||||
};
|
||||
|
||||
// GR64_NOREX_NOSP Bit set.
|
||||
static uint8_t GR64_NOREX_NOSPBits[] = {
|
||||
static const uint8_t GR64_NOREX_NOSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf8, 0x09,
|
||||
};
|
||||
|
||||
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
|
||||
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_R8, X86_R9, X86_R11,
|
||||
};
|
||||
|
||||
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX Bit set.
|
||||
static uint8_t GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xc0, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
|
||||
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP, X86_RSP,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf0, 0x19,
|
||||
};
|
||||
|
||||
// VK64WM Register Class...
|
||||
static MCPhysReg VK64WM[] = {
|
||||
static const MCPhysReg VK64WM[] = {
|
||||
X86_K1, X86_K2, X86_K3, X86_K4, X86_K5, X86_K6, X86_K7,
|
||||
};
|
||||
|
||||
// VK64WM Bit set.
|
||||
static uint8_t VK64WMBits[] = {
|
||||
static const uint8_t VK64WMBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
||||
};
|
||||
|
||||
// GR64_NOREX_and_GR64_TC Register Class...
|
||||
static MCPhysReg GR64_NOREX_and_GR64_TC[] = {
|
||||
static const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RIP,
|
||||
};
|
||||
|
||||
// GR64_NOREX_and_GR64_TC Bit set.
|
||||
static uint8_t GR64_NOREX_and_GR64_TCBits[] = {
|
||||
static const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xc8, 0x0b,
|
||||
};
|
||||
|
||||
// GR64_TCW64 Register Class...
|
||||
static MCPhysReg GR64_TCW64[] = {
|
||||
static const MCPhysReg GR64_TCW64[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11,
|
||||
};
|
||||
|
||||
// GR64_TCW64 Bit set.
|
||||
static uint8_t GR64_TCW64Bits[] = {
|
||||
static const uint8_t GR64_TCW64Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP[] = {
|
||||
X86_RCX, X86_RDX, X86_RSI, X86_RDI, X86_RBX, X86_RBP,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSPBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xf0, 0x09,
|
||||
};
|
||||
|
||||
// GR64_NOREX_NOSP_and_GR64_TC Register Class...
|
||||
static MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
|
||||
static const MCPhysReg GR64_NOREX_NOSP_and_GR64_TC[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RSI, X86_RDI,
|
||||
};
|
||||
|
||||
// GR64_NOREX_NOSP_and_GR64_TC Bit set.
|
||||
static uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
|
||||
static const uint8_t GR64_NOREX_NOSP_and_GR64_TCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xc8, 0x09,
|
||||
};
|
||||
|
||||
// GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX[] = {
|
||||
X86_RCX, X86_RDX, X86_R8, X86_R9, X86_R11,
|
||||
};
|
||||
|
||||
// GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX Bit set.
|
||||
static uint8_t GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c,
|
||||
};
|
||||
|
||||
// GR64_ABCD Register Class...
|
||||
static MCPhysReg GR64_ABCD[] = {
|
||||
static const MCPhysReg GR64_ABCD[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX, X86_RBX,
|
||||
};
|
||||
|
||||
// GR64_ABCD Bit set.
|
||||
static uint8_t GR64_ABCDBits[] = {
|
||||
static const uint8_t GR64_ABCDBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
|
||||
};
|
||||
|
||||
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Register Class...
|
||||
static MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
|
||||
static const MCPhysReg GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX[] = {
|
||||
X86_RCX, X86_RDX, X86_RSI, X86_RDI,
|
||||
};
|
||||
|
||||
// GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX Bit set.
|
||||
static uint8_t GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
|
||||
static const uint8_t GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0xc0, 0x09,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX[] = {
|
||||
X86_RCX, X86_RDX, X86_RBX,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x60, 0x01,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_TC Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
|
||||
X86_RAX, X86_RCX, X86_RDX,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_TC Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_AD Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_AD[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_AD[] = {
|
||||
X86_RAX, X86_RDX,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_AD Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_ADBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_ADBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC[] = {
|
||||
X86_RCX, X86_RDX,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TCBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX Register Class...
|
||||
static MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX[] = {
|
||||
static const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX[] = {
|
||||
X86_RDX,
|
||||
};
|
||||
|
||||
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX Bit set.
|
||||
static uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXBits[] = {
|
||||
static const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAXBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
|
||||
};
|
||||
|
||||
// RST Register Class...
|
||||
static MCPhysReg RST[] = {
|
||||
static const MCPhysReg RST[] = {
|
||||
X86_ST0, X86_ST1, X86_ST2, X86_ST3, X86_ST4, X86_ST5, X86_ST6, X86_ST7,
|
||||
};
|
||||
|
||||
// RST Bit set.
|
||||
static uint8_t RSTBits[] = {
|
||||
static const uint8_t RSTBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
||||
};
|
||||
|
||||
// RFP80 Register Class...
|
||||
static MCPhysReg RFP80[] = {
|
||||
static const MCPhysReg RFP80[] = {
|
||||
X86_FP0, X86_FP1, X86_FP2, X86_FP3, X86_FP4, X86_FP5, X86_FP6,
|
||||
};
|
||||
|
||||
// RFP80 Bit set.
|
||||
static uint8_t RFP80Bits[] = {
|
||||
static const uint8_t RFP80Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
|
||||
};
|
||||
|
||||
// VR128X Register Class...
|
||||
static MCPhysReg VR128X[] = {
|
||||
static const MCPhysReg VR128X[] = {
|
||||
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15, X86_XMM16, X86_XMM17, X86_XMM18, X86_XMM19, X86_XMM20, X86_XMM21, X86_XMM22, X86_XMM23, X86_XMM24, X86_XMM25, X86_XMM26, X86_XMM27, X86_XMM28, X86_XMM29, X86_XMM30, X86_XMM31,
|
||||
};
|
||||
|
||||
// VR128X Bit set.
|
||||
static uint8_t VR128XBits[] = {
|
||||
static const uint8_t VR128XBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// VR128 Register Class...
|
||||
static MCPhysReg VR128[] = {
|
||||
static const MCPhysReg VR128[] = {
|
||||
X86_XMM0, X86_XMM1, X86_XMM2, X86_XMM3, X86_XMM4, X86_XMM5, X86_XMM6, X86_XMM7, X86_XMM8, X86_XMM9, X86_XMM10, X86_XMM11, X86_XMM12, X86_XMM13, X86_XMM14, X86_XMM15,
|
||||
};
|
||||
|
||||
// VR128 Bit set.
|
||||
static uint8_t VR128Bits[] = {
|
||||
static const uint8_t VR128Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// VR256X Register Class...
|
||||
static MCPhysReg VR256X[] = {
|
||||
static const MCPhysReg VR256X[] = {
|
||||
X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15, X86_YMM16, X86_YMM17, X86_YMM18, X86_YMM19, X86_YMM20, X86_YMM21, X86_YMM22, X86_YMM23, X86_YMM24, X86_YMM25, X86_YMM26, X86_YMM27, X86_YMM28, X86_YMM29, X86_YMM30, X86_YMM31,
|
||||
};
|
||||
|
||||
// VR256X Bit set.
|
||||
static uint8_t VR256XBits[] = {
|
||||
static const uint8_t VR256XBits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// VR256 Register Class...
|
||||
static MCPhysReg VR256[] = {
|
||||
static const MCPhysReg VR256[] = {
|
||||
X86_YMM0, X86_YMM1, X86_YMM2, X86_YMM3, X86_YMM4, X86_YMM5, X86_YMM6, X86_YMM7, X86_YMM8, X86_YMM9, X86_YMM10, X86_YMM11, X86_YMM12, X86_YMM13, X86_YMM14, X86_YMM15,
|
||||
};
|
||||
|
||||
// VR256 Bit set.
|
||||
static uint8_t VR256Bits[] = {
|
||||
static const uint8_t VR256Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// VR512 Register Class...
|
||||
static MCPhysReg VR512[] = {
|
||||
static const MCPhysReg VR512[] = {
|
||||
X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15, X86_ZMM16, X86_ZMM17, X86_ZMM18, X86_ZMM19, X86_ZMM20, X86_ZMM21, X86_ZMM22, X86_ZMM23, X86_ZMM24, X86_ZMM25, X86_ZMM26, X86_ZMM27, X86_ZMM28, X86_ZMM29, X86_ZMM30, X86_ZMM31,
|
||||
};
|
||||
|
||||
// VR512 Bit set.
|
||||
static uint8_t VR512Bits[] = {
|
||||
static const uint8_t VR512Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
|
||||
};
|
||||
|
||||
// VR512_with_sub_xmm_in_FR32 Register Class...
|
||||
static MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
|
||||
static const MCPhysReg VR512_with_sub_xmm_in_FR32[] = {
|
||||
X86_ZMM0, X86_ZMM1, X86_ZMM2, X86_ZMM3, X86_ZMM4, X86_ZMM5, X86_ZMM6, X86_ZMM7, X86_ZMM8, X86_ZMM9, X86_ZMM10, X86_ZMM11, X86_ZMM12, X86_ZMM13, X86_ZMM14, X86_ZMM15,
|
||||
};
|
||||
|
||||
// VR512_with_sub_xmm_in_FR32 Bit set.
|
||||
static uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
|
||||
static const uint8_t VR512_with_sub_xmm_in_FR32Bits[] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
|
||||
};
|
||||
|
||||
|
|
@ -1430,7 +1430,7 @@ static MCRegisterDesc X86RegDesc[] = { // Descriptors
|
|||
#define CAPSTONE_REGISTER_CLASS(x) x
|
||||
#endif
|
||||
|
||||
static MCRegisterClass X86MCRegisterClasses[] = {
|
||||
static const MCRegisterClass X86MCRegisterClasses[] = {
|
||||
{ CAPSTONE_REGISTER_CLASS("GR8"), GR8, GR8Bits, 20, sizeof(GR8Bits), X86_GR8RegClassID, 1, 1, 1, 1 },
|
||||
{ CAPSTONE_REGISTER_CLASS("GR8_NOREX"), GR8_NOREX, GR8_NOREXBits, 8, sizeof(GR8_NOREXBits), X86_GR8_NOREXRegClassID, 1, 1, 1, 1 },
|
||||
{ CAPSTONE_REGISTER_CLASS("GR8_ABCD_H"), GR8_ABCD_H, GR8_ABCD_HBits, 4, sizeof(GR8_ABCD_HBits), X86_GR8_ABCD_HRegClassID, 1, 1, 1, 1 },
|
||||
|
|
|
|||
|
|
@ -261,7 +261,7 @@ static void printRoundingControl(MCInst *MI, unsigned Op, SStream *O)
|
|||
|
||||
#endif
|
||||
|
||||
static char *getRegisterName(unsigned RegNo);
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
static void printRegName(SStream *OS, unsigned RegNo)
|
||||
{
|
||||
SStream_concat0(OS, getRegisterName(RegNo));
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#include "../../utils.h"
|
||||
|
||||
|
||||
uint64_t arch_masks[9] = {
|
||||
const uint64_t arch_masks[9] = {
|
||||
0, 0xff,
|
||||
0xffff,
|
||||
0,
|
||||
|
|
@ -20,7 +20,7 @@ uint64_t arch_masks[9] = {
|
|||
0xffffffffffffffff
|
||||
};
|
||||
|
||||
static x86_reg sib_base_map[] = {
|
||||
static const x86_reg sib_base_map[] = {
|
||||
X86_REG_INVALID,
|
||||
#define ENTRY(x) X86_REG_##x,
|
||||
ALL_SIB_BASES
|
||||
|
|
@ -39,7 +39,7 @@ enum {
|
|||
X86_REG_sib64 = 505
|
||||
};
|
||||
|
||||
static x86_reg sib_index_map[] = {
|
||||
static const x86_reg sib_index_map[] = {
|
||||
X86_REG_INVALID,
|
||||
#define ENTRY(x) X86_REG_##x,
|
||||
ALL_EA_BASES
|
||||
|
|
@ -49,7 +49,7 @@ static x86_reg sib_index_map[] = {
|
|||
#undef ENTRY
|
||||
};
|
||||
|
||||
static x86_reg segment_map[] = {
|
||||
static const x86_reg segment_map[] = {
|
||||
X86_REG_INVALID,
|
||||
X86_REG_CS,
|
||||
X86_REG_SS,
|
||||
|
|
@ -75,7 +75,7 @@ x86_reg x86_map_segment(int r)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ X86_REG_INVALID, NULL },
|
||||
|
||||
{ X86_REG_AH, "ah" },
|
||||
|
|
@ -315,7 +315,7 @@ static name_map reg_name_maps[] = {
|
|||
#endif
|
||||
|
||||
// register size in non-64bit mode
|
||||
uint8_t regsize_map_32 [] = {
|
||||
const uint8_t regsize_map_32 [] = {
|
||||
0, // { X86_REG_INVALID, NULL },
|
||||
1, // { X86_REG_AH, "ah" },
|
||||
1, // { X86_REG_AL, "al" },
|
||||
|
|
@ -553,7 +553,7 @@ uint8_t regsize_map_32 [] = {
|
|||
};
|
||||
|
||||
// register size in 64bit mode
|
||||
uint8_t regsize_map_64 [] = {
|
||||
const uint8_t regsize_map_64 [] = {
|
||||
0, // { X86_REG_INVALID, NULL },
|
||||
1, // { X86_REG_AH, "ah" },
|
||||
1, // { X86_REG_AL, "al" },
|
||||
|
|
@ -812,7 +812,7 @@ const char *X86_reg_name(csh handle, unsigned int reg)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ X86_INS_INVALID, NULL },
|
||||
|
||||
{ X86_INS_AAA, "aaa" },
|
||||
|
|
@ -2125,7 +2125,7 @@ const char *X86_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
// generic groups
|
||||
{ X86_GRP_INVALID, NULL },
|
||||
{ X86_GRP_JUMP, "jump" },
|
||||
|
|
@ -2204,7 +2204,7 @@ const char *X86_group_name(csh handle, unsigned int id)
|
|||
#endif
|
||||
|
||||
#ifndef CAPSTONE_X86_REDUCE
|
||||
static insn_map insns[] = { // full x86 instructions
|
||||
static const insn_map insns[] = { // full x86 instructions
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -37765,7 +37765,7 @@ static insn_map insns[] = { // full x86 instructions
|
|||
},
|
||||
};
|
||||
#else // X86 reduce (defined CAPSTONE_X86_REDUCE)
|
||||
static insn_map insns[] = { // reduce x86 instructions
|
||||
static const insn_map insns[] = { // reduce x86 instructions
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -47236,7 +47236,7 @@ struct insn_reg2 {
|
|||
x86_reg reg1, reg2;
|
||||
};
|
||||
|
||||
static struct insn_reg insn_regs_att[] = {
|
||||
static const struct insn_reg insn_regs_att[] = {
|
||||
{ X86_INSB, X86_REG_DX },
|
||||
{ X86_INSW, X86_REG_DX },
|
||||
{ X86_INSL, X86_REG_DX },
|
||||
|
|
@ -47348,7 +47348,7 @@ static struct insn_reg insn_regs_att[] = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static struct insn_reg insn_regs_intel[] = {
|
||||
static const struct insn_reg insn_regs_intel[] = {
|
||||
{ X86_OUTSB, X86_REG_DX },
|
||||
{ X86_OUTSW, X86_REG_DX },
|
||||
{ X86_OUTSL, X86_REG_DX },
|
||||
|
|
@ -47475,7 +47475,7 @@ static struct insn_reg insn_regs_intel[] = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static struct insn_reg2 insn_regs_intel2[] = {
|
||||
static const struct insn_reg2 insn_regs_intel2[] = {
|
||||
{ X86_IN8rr, X86_REG_AL, X86_REG_DX },
|
||||
{ X86_IN16rr, X86_REG_AX, X86_REG_DX },
|
||||
{ X86_IN32rr, X86_REG_EAX, X86_REG_DX },
|
||||
|
|
|
|||
|
|
@ -36,15 +36,15 @@ x86_reg X86_insn_reg_att(unsigned int id);
|
|||
bool X86_insn_reg_intel2(unsigned int id, x86_reg *reg1, x86_reg *reg2);
|
||||
bool X86_insn_reg_att2(unsigned int id, x86_reg *reg1, x86_reg *reg2);
|
||||
|
||||
extern uint64_t arch_masks[9];
|
||||
extern const uint64_t arch_masks[9];
|
||||
|
||||
// handle LOCK/REP/REPNE prefixes
|
||||
// return True if we patch mnemonic, like in MULPD case
|
||||
bool X86_lockrep(MCInst *MI, SStream *O);
|
||||
|
||||
// map registers to sizes
|
||||
extern uint8_t regsize_map_32[];
|
||||
extern uint8_t regsize_map_64[];
|
||||
extern const uint8_t regsize_map_32[];
|
||||
extern const uint8_t regsize_map_64[];
|
||||
|
||||
void op_addReg(MCInst *MI, int reg);
|
||||
void op_addImm(MCInst *MI, int v);
|
||||
|
|
|
|||
|
|
@ -54,86 +54,86 @@ static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *in
|
|||
return true;
|
||||
}
|
||||
|
||||
static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
|
||||
static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
|
||||
{
|
||||
MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
|
||||
const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
|
||||
return rc->RegsBegin[RegNo];
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address, void *Decoder);
|
||||
uint64_t Address, const void *Decoder);
|
||||
|
||||
#include "XCoreGenDisassemblerTables.inc"
|
||||
|
||||
|
|
@ -142,7 +142,7 @@ static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn
|
|||
#include "XCoreGenRegisterInfo.inc"
|
||||
|
||||
static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, void *Decoder)
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
|
||||
uint64_t Address, void *Decoder)
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
unsigned Reg;
|
||||
if (RegNo > 15)
|
||||
|
|
@ -169,9 +169,9 @@ static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, void *Decoder)
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
static unsigned Values[] = {
|
||||
static const unsigned Values[] = {
|
||||
32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
|
||||
};
|
||||
|
||||
|
|
@ -183,7 +183,7 @@ static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
|
||||
uint64_t Address, void *Decoder)
|
||||
uint64_t Address, const void *Decoder)
|
||||
{
|
||||
MCOperand_CreateImm0(Inst, -(int64_t)Val);
|
||||
return MCDisassembler_Success;
|
||||
|
|
@ -233,7 +233,7 @@ static DecodeStatus Decode3OpInstruction(unsigned Insn,
|
|||
#define GET_INSTRINFO_ENUM
|
||||
#include "XCoreGenInstrInfo.inc"
|
||||
static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
// Try and decode as a 3R instruction.
|
||||
unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
|
||||
|
|
@ -304,7 +304,7 @@ static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64
|
|||
}
|
||||
|
||||
static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
|
||||
|
|
@ -318,7 +318,7 @@ static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Ad
|
|||
}
|
||||
|
||||
static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
|
||||
|
|
@ -332,7 +332,7 @@ static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
|
||||
|
|
@ -346,7 +346,7 @@ static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t A
|
|||
}
|
||||
|
||||
static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
|
||||
|
|
@ -361,7 +361,7 @@ static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint6
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
|
||||
|
|
@ -375,7 +375,7 @@ static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t A
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
|
||||
|
|
@ -389,7 +389,7 @@ static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
|
||||
|
|
@ -404,7 +404,7 @@ static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
// Try and decode as a L3R / L2RUS instruction.
|
||||
unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
|
||||
|
|
@ -476,7 +476,7 @@ static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint6
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
|
||||
|
|
@ -490,7 +490,7 @@ static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t A
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2;
|
||||
DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
|
||||
|
|
@ -504,7 +504,7 @@ static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t
|
|||
}
|
||||
|
||||
static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
||||
|
|
@ -518,7 +518,7 @@ static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Ad
|
|||
}
|
||||
|
||||
static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
||||
|
|
@ -532,7 +532,7 @@ static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t
|
|||
}
|
||||
|
||||
static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
||||
|
|
@ -546,7 +546,7 @@ static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t
|
|||
}
|
||||
|
||||
static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
|
||||
|
|
@ -560,7 +560,7 @@ static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint6
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S =
|
||||
|
|
@ -575,7 +575,7 @@ static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t A
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S =
|
||||
|
|
@ -591,7 +591,7 @@ static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S =
|
||||
|
|
@ -606,7 +606,7 @@ static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
DecodeStatus S =
|
||||
|
|
@ -621,7 +621,7 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
|
||||
DecodeStatus S =
|
||||
|
|
@ -643,7 +643,7 @@ static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t A
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Opcode;
|
||||
|
||||
|
|
@ -662,7 +662,7 @@ static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3, Op4, Op5;
|
||||
DecodeStatus S =
|
||||
|
|
@ -683,7 +683,7 @@ static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t A
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
|
||||
|
|
@ -703,7 +703,7 @@ static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint
|
|||
}
|
||||
|
||||
static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
|
||||
void *Decoder)
|
||||
const void *Decoder)
|
||||
{
|
||||
unsigned Op1, Op2, Op3;
|
||||
unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
|
||||
|
|
|
|||
|
|
@ -266,7 +266,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
0U
|
||||
};
|
||||
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'l', 'd', 'a', 'p', 32, 'r', '1', '1', ',', 32, 0,
|
||||
/* 11 */ 'g', 'e', 't', 's', 'r', 32, 'r', '1', '1', ',', 32, 0,
|
||||
/* 23 */ 's', 'e', 't', 32, 'c', 'p', ',', 32, 0,
|
||||
|
|
@ -730,12 +730,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
|
|||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static char *getRegisterName(unsigned RegNo)
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
// assert(RegNo && RegNo < 17 && "Invalid register number!");
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static char AsmStrs[] = {
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'r', '1', '0', 0,
|
||||
/* 4 */ 'r', '0', 0,
|
||||
/* 7 */ 'r', '1', '1', 0,
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
|
|||
return (insn & fieldMask) >> startBit; \
|
||||
}
|
||||
|
||||
static uint8_t DecoderTable16[] = {
|
||||
static const uint8_t DecoderTable16[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 108, 0, // Skip to: 115
|
||||
/* 7 */ MCD_OPC_ExtractField, 0, 11, // Inst{10-0} ...
|
||||
|
|
@ -355,7 +355,7 @@ static uint8_t DecoderTable16[] = {
|
|||
0
|
||||
};
|
||||
|
||||
static uint8_t DecoderTable32[] = {
|
||||
static const uint8_t DecoderTable32[] = {
|
||||
/* 0 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
|
||||
/* 3 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 96
|
||||
/* 7 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ...
|
||||
|
|
@ -606,7 +606,7 @@ static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits)
|
|||
|
||||
#define DecodeToMCInst(fname,fieldname, InsnType) \
|
||||
static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
|
||||
uint64_t Address, void *Decoder) \
|
||||
uint64_t Address, const void *Decoder) \
|
||||
{ \
|
||||
InsnType tmp; \
|
||||
switch (Idx) { \
|
||||
|
|
@ -766,11 +766,11 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M
|
|||
}
|
||||
|
||||
#define DecodeInstruction(fname, fieldname, decoder, InsnType) \
|
||||
static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, MCRegisterInfo *MRI, int feature) \
|
||||
static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
|
||||
InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
|
||||
{ \
|
||||
uint64_t Bits = getFeatureBits(feature); \
|
||||
uint8_t *Ptr = DecodeTable; \
|
||||
const uint8_t *Ptr = DecodeTable; \
|
||||
uint32_t CurFieldValue = 0, ExpectedValue; \
|
||||
DecodeStatus S = MCDisassembler_Success; \
|
||||
unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
|
||||
|
|
|
|||
|
|
@ -54,15 +54,15 @@ enum {
|
|||
#ifdef GET_REGINFO_MC_DESC
|
||||
#undef GET_REGINFO_MC_DESC
|
||||
|
||||
static MCPhysReg XCoreRegDiffLists[] = {
|
||||
static const MCPhysReg XCoreRegDiffLists[] = {
|
||||
/* 0 */ 65535, 0,
|
||||
};
|
||||
|
||||
static uint16_t XCoreSubRegIdxLists[] = {
|
||||
static const uint16_t XCoreSubRegIdxLists[] = {
|
||||
/* 0 */ 0,
|
||||
};
|
||||
|
||||
static MCRegisterDesc XCoreRegDesc[] = { // Descriptors
|
||||
static const MCRegisterDesc XCoreRegDesc[] = { // Descriptors
|
||||
{ 3, 0, 0, 0, 0 },
|
||||
{ 38, 1, 1, 0, 1 },
|
||||
{ 41, 1, 1, 0, 1 },
|
||||
|
|
@ -83,26 +83,26 @@ static MCRegisterDesc XCoreRegDesc[] = { // Descriptors
|
|||
};
|
||||
|
||||
// RRegs Register Class...
|
||||
static MCPhysReg RRegs[] = {
|
||||
static const MCPhysReg RRegs[] = {
|
||||
XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11, XCore_CP, XCore_DP, XCore_SP, XCore_LR,
|
||||
};
|
||||
|
||||
// RRegs Bit set.
|
||||
static uint8_t RRegsBits[] = {
|
||||
static const uint8_t RRegsBits[] = {
|
||||
0xfe, 0xff, 0x01,
|
||||
};
|
||||
|
||||
// GRRegs Register Class...
|
||||
static MCPhysReg GRRegs[] = {
|
||||
static const MCPhysReg GRRegs[] = {
|
||||
XCore_R0, XCore_R1, XCore_R2, XCore_R3, XCore_R4, XCore_R5, XCore_R6, XCore_R7, XCore_R8, XCore_R9, XCore_R10, XCore_R11,
|
||||
};
|
||||
|
||||
// GRRegs Bit set.
|
||||
static uint8_t GRRegsBits[] = {
|
||||
static const uint8_t GRRegsBits[] = {
|
||||
0xe0, 0xff, 0x01,
|
||||
};
|
||||
|
||||
static MCRegisterClass XCoreMCRegisterClasses[] = {
|
||||
static const MCRegisterClass XCoreMCRegisterClasses[] = {
|
||||
{ "RRegs", RRegs, RRegsBits, 16, sizeof(RRegsBits), XCore_RRegsRegClassID, 4, 4, 1, 0 },
|
||||
{ "GRRegs", GRRegs, GRRegsBits, 12, sizeof(GRRegsBits), XCore_GRRegsRegClassID, 4, 4, 1, 1 },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@
|
|||
#include "../../MathExtras.h"
|
||||
#include "XCoreMapping.h"
|
||||
|
||||
static char *getRegisterName(unsigned RegNo);
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
|
||||
void XCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
#define GET_INSTRINFO_ENUM
|
||||
#include "XCoreGenInstrInfo.inc"
|
||||
|
||||
static name_map reg_name_maps[] = {
|
||||
static const name_map reg_name_maps[] = {
|
||||
{ XCORE_REG_INVALID, NULL },
|
||||
|
||||
{ XCORE_REG_CP, "cp" },
|
||||
|
|
@ -71,7 +71,7 @@ xcore_reg XCore_reg_id(char *name)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static insn_map insns[] = {
|
||||
static const insn_map insns[] = {
|
||||
// dummy item
|
||||
{
|
||||
0, 0,
|
||||
|
|
@ -1397,7 +1397,7 @@ void XCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map insn_name_maps[] = {
|
||||
static const name_map insn_name_maps[] = {
|
||||
{ XCORE_INS_INVALID, NULL },
|
||||
|
||||
{ XCORE_INS_ADD, "add" },
|
||||
|
|
@ -1523,7 +1523,7 @@ static name_map insn_name_maps[] = {
|
|||
};
|
||||
|
||||
// special alias insn
|
||||
static name_map alias_insn_names[] = {
|
||||
static const name_map alias_insn_names[] = {
|
||||
{ 0, NULL }
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1549,7 +1549,7 @@ const char *XCore_insn_name(csh handle, unsigned int id)
|
|||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
static const name_map group_name_maps[] = {
|
||||
{ XCORE_GRP_INVALID, NULL },
|
||||
{ XCORE_GRP_JUMP, "jump" },
|
||||
};
|
||||
|
|
@ -1570,7 +1570,7 @@ const char *XCore_group_name(csh handle, unsigned int id)
|
|||
// map internal raw register to 'public' register
|
||||
xcore_reg XCore_map_register(unsigned int r)
|
||||
{
|
||||
static unsigned int map[] = { 0,
|
||||
static const unsigned int map[] = { 0,
|
||||
};
|
||||
|
||||
if (r < ARR_SIZE(map))
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ typedef const char *(*GetName_t)(csh handle, unsigned int id);
|
|||
typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
|
||||
|
||||
// return register name, given register ID
|
||||
typedef char *(*GetRegisterName_t)(unsigned RegNo);
|
||||
typedef const char *(*GetRegisterName_t)(unsigned RegNo);
|
||||
|
||||
// for ARM only
|
||||
typedef struct ARM_ITStatus {
|
||||
|
|
@ -52,7 +52,7 @@ struct cs_struct {
|
|||
bool skipdata; // set this to True if we skip data when disassembling
|
||||
uint8_t skipdata_size; // how many bytes to skip
|
||||
cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
|
||||
uint8_t *regsize_map; // map to register size (x86-only for now)
|
||||
const uint8_t *regsize_map; // map to register size (x86-only for now)
|
||||
};
|
||||
|
||||
#define MAX_ARCH 8
|
||||
|
|
|
|||
8
utils.c
8
utils.c
|
|
@ -11,7 +11,7 @@
|
|||
#include "utils.h"
|
||||
|
||||
// create a cache for fast id lookup
|
||||
static unsigned short *make_id2insn(insn_map *insns, unsigned int size)
|
||||
static unsigned short *make_id2insn(const insn_map *insns, unsigned int size)
|
||||
{
|
||||
// NOTE: assume that the max id is always put at the end of insns array
|
||||
unsigned short max_id = insns[size - 1].id;
|
||||
|
|
@ -27,7 +27,7 @@ static unsigned short *make_id2insn(insn_map *insns, unsigned int size)
|
|||
|
||||
// look for @id in @insns, given its size in @max. first time call will update @cache.
|
||||
// return 0 if not found
|
||||
unsigned short insn_find(insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache)
|
||||
unsigned short insn_find(const insn_map *insns, unsigned int max, unsigned int id, unsigned short **cache)
|
||||
{
|
||||
if (id > insns[max - 1].id)
|
||||
return 0;
|
||||
|
|
@ -38,7 +38,7 @@ unsigned short insn_find(insn_map *insns, unsigned int max, unsigned int id, uns
|
|||
return (*cache)[id];
|
||||
}
|
||||
|
||||
int name2id(name_map* map, int max, const char *name)
|
||||
int name2id(const name_map* map, int max, const char *name)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -54,7 +54,7 @@ int name2id(name_map* map, int max, const char *name)
|
|||
|
||||
// count number of positive members in a list.
|
||||
// NOTE: list must be guaranteed to end in 0
|
||||
unsigned int count_positive(unsigned char *list)
|
||||
unsigned int count_positive(const unsigned char *list)
|
||||
{
|
||||
unsigned int c;
|
||||
|
||||
|
|
|
|||
8
utils.h
8
utils.h
|
|
@ -30,21 +30,21 @@ typedef struct insn_map {
|
|||
|
||||
// look for @id in @m, given its size in @max. first time call will update @cache.
|
||||
// return 0 if not found
|
||||
unsigned short insn_find(insn_map *m, unsigned int max, unsigned int id, unsigned short **cache);
|
||||
unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id, unsigned short **cache);
|
||||
|
||||
// map id to string
|
||||
typedef struct name_map {
|
||||
unsigned int id;
|
||||
char *name;
|
||||
const char *name;
|
||||
} name_map;
|
||||
|
||||
// map a name to its ID
|
||||
// return 0 if not found
|
||||
int name2id(name_map* map, int max, const char *name);
|
||||
int name2id(const name_map* map, int max, const char *name);
|
||||
|
||||
// count number of positive members in a list.
|
||||
// NOTE: list must be guaranteed to end in 0
|
||||
unsigned int count_positive(unsigned char *list);
|
||||
unsigned int count_positive(const unsigned char *list);
|
||||
|
||||
#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue