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https://github.com/capstone-engine/capstone
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Revert "Merges encoding branch (#1187)"
This reverts commit a1ed8fc6f6.
This commit is contained in:
Nguyen Anh Quynh
parent
a31b532864
commit
3f9978c809
8 changed files with 14 additions and 101 deletions
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@ -759,23 +759,12 @@ static void update_pub_insn(cs_insn *pub, InternalInstruction *inter, uint8_t *p
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pub->detail->x86.addr_size = inter->addressSize;
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pub->detail->x86.modrm = inter->orgModRM;
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pub->detail->x86.encoding.modrm_offset = (inter->modRMLocation != 0) ? (inter->modRMLocation - inter->startLocation) : 0;
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pub->detail->x86.sib = inter->sib;
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pub->detail->x86.disp = inter->displacement;
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pub->detail->x86.sib_index = x86_map_sib_index(inter->sibIndex);
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pub->detail->x86.sib_scale = inter->sibScale;
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pub->detail->x86.sib_base = x86_map_sib_base(inter->sibBase);
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pub->detail->x86.disp = inter->displacement;
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if (inter->consumedDisplacement) {
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pub->detail->x86.encoding.disp_offset = inter->displacementOffset;
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pub->detail->x86.encoding.disp_size = inter->displacementSize;
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}
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pub->detail->x86.encoding.imm_offset = inter->immediateOffset;
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if (/*pub->detail->x86.encoding.imm_size == 0 && */inter->immediateOffset != 0) {
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pub->detail->x86.encoding.imm_size = inter->immediateSize;
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}
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}
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void X86_init(MCRegisterInfo *MRI)
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@ -823,7 +812,6 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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memset(instr->flat_insn->detail->x86.prefix, 0, sizeof(instr->flat_insn->detail->x86.prefix));
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memset(instr->flat_insn->detail->x86.opcode, 0, sizeof(instr->flat_insn->detail->x86.opcode));
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memset(instr->flat_insn->detail->x86.operands, 0, sizeof(instr->flat_insn->detail->x86.operands));
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memset(&instr->flat_insn->detail->x86.encoding, 0, sizeof(instr->flat_insn->detail->x86.encoding));
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}
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if (handle->mode & CS_MODE_16)
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@ -1537,8 +1537,6 @@ static int readModRM(struct InternalInstruction *insn)
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if (insn->consumedModRM)
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return 0;
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insn->modRMLocation = insn->readerCursor;
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if (consumeByte(insn, &insn->modRM))
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return -1;
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@ -2046,7 +2044,7 @@ static int readOperands(struct InternalInstruction *insn)
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return -1;
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// Apply the AVX512 compressed displacement scaling factor.
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if (x86OperandSets[insn->spec->operands][index].encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8)
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insn->displacement *= (int64_t)1 << (x86OperandSets[insn->spec->operands][index].encoding - ENCODING_RM);
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insn->displacement *= 1 << (x86OperandSets[insn->spec->operands][index].encoding - ENCODING_RM);
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break;
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case ENCODING_CB:
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case ENCODING_CW:
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@ -2090,14 +2088,6 @@ static int readOperands(struct InternalInstruction *insn)
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case ENCODING_Ia:
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if (readImmediate(insn, insn->addressSize))
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return -1;
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/* Direct memory-offset (moffset) immediate will get mapped
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to memory operand later. We want the encoding info to
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reflect that as well. */
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insn->displacementOffset = insn->immediateOffset;
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insn->displacementSize = insn->immediateSize;
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insn->displacement = insn->immediates[insn->numImmediatesConsumed - 1];
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insn->immediateOffset = 0;
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insn->immediateSize = 0;
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break;
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case ENCODING_RB:
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if (readOpcodeRegister(insn, 1))
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@ -2366,7 +2356,6 @@ int decodeInstruction(struct InternalInstruction *insn,
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insn->reader = reader;
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insn->readerArg = readerArg;
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insn->startLocation = startLoc;
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insn->modRMLocation = 0;
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insn->readerCursor = startLoc;
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insn->mode = mode;
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@ -589,7 +589,7 @@ typedef struct InternalInstruction {
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uint8_t sib;
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/* The displacement, used for memory operands */
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bool consumedDisplacement;
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int64_t displacement;
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int32_t displacement;
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/* The value of the two-byte escape prefix (usually 0x0f) */
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uint8_t twoByteEscape;
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/* The value of the three-byte escape prefix (usually 0x38 or 0x3a) */
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@ -680,9 +680,6 @@ typedef struct InternalInstruction {
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all memory operands */
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uint8_t modRM;
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/* contains the location (for use with the reader) of the modRM byte */
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uint64_t modRMLocation;
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// special data to handle MOVcr, MOVdr, MOVrc, MOVrd
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uint8_t firstByte; // save the first byte in stream
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@ -552,7 +552,7 @@ class CsInsn(object):
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(self.prefix, self.opcode, self.rex, self.addr_size, \
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self.modrm, self.sib, self.disp, \
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self.sib_index, self.sib_scale, self.sib_base, self.sse_cc, \
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self.avx_cc, self.avx_sae, self.avx_rm, self.operands, self.encoding) = x86.get_arch_info(self._detail.arch.x86)
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self.avx_cc, self.avx_sae, self.avx_rm, self.operands) = x86.get_arch_info(self._detail.arch.x86)
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elif arch == CS_ARCH_MIPS:
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self.operands = mips.get_arch_info(self._detail.arch.mips)
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elif arch == CS_ARCH_PPC:
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@ -1,7 +1,7 @@
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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import ctypes
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from . import copy_ctypes, copy_ctypes_list
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from . import copy_ctypes_list
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from .x86_const import *
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# define the API
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@ -47,14 +47,6 @@ class X86Op(ctypes.Structure):
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def mem(self):
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return self.value.mem
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class CsX86Encoding(ctypes.Structure):
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_fields_ = (
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('modrm_offset', ctypes.c_uint8),
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('disp_offset', ctypes.c_uint8),
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('disp_size', ctypes.c_uint8),
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('imm_offset', ctypes.c_uint8),
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('imm_size', ctypes.c_uint8),
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)
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class CsX86(ctypes.Structure):
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_fields_ = (
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@ -74,13 +66,11 @@ class CsX86(ctypes.Structure):
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('avx_rm', ctypes.c_uint),
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('op_count', ctypes.c_uint8),
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('operands', X86Op * 8),
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('encoding', CsX86Encoding),
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)
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def get_arch_info(a):
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return (a.prefix[:], a.opcode[:], a.rex, a.addr_size, \
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a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, \
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a.sib_base, a.sse_cc, a.avx_cc, a.avx_sae, a.avx_rm, \
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copy_ctypes_list(a.operands[:a.op_count]), \
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copy_ctypes(a.encoding))
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copy_ctypes_list(a.operands[:a.op_count]))
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@ -7,9 +7,9 @@ from capstone.x86 import *
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from xprint import to_hex, to_x, to_x_32
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X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
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X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc"
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X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
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X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
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X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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all_tests = (
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(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", 0),
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@ -47,22 +47,10 @@ def print_insn_detail(mode, insn):
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# print modRM byte
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print("\tmodrm: 0x%x" % (insn.modrm))
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# print modRM offset
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if insn.modrm_offset != 0:
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print("\tmodrm_offset: 0x%x" % (insn.modrm_offset))
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# print displacement value
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print("\tdisp: 0x%s" % to_x_32(insn.disp))
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# print displacement offset (offset into instruction bytes)
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if insn.disp_offset != 0:
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print("\tdisp_offset: 0x%x" % (insn.disp_offset))
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# print displacement size
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if insn.disp_size != 0:
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print("\tdisp_size: 0x%x" % (insn.disp_size))
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# SIB is not available in 16-bit mode
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if (mode & CS_MODE_16 == 0):
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# print SIB byte
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@ -97,10 +85,6 @@ def print_insn_detail(mode, insn):
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for i in range(count):
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op = insn.op_find(X86_OP_IMM, i + 1)
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print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm)))
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if insn.imm_offset != 0:
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print("\timm_offset: 0x%x" % (insn.imm_offset))
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if insn.imm_size != 0:
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print("\timm_size: 0x%x" % (insn.imm_size))
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if len(insn.operands) > 0:
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print("\top_count: %u" % len(insn.operands))
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@ -203,19 +203,6 @@ typedef struct cs_x86_op {
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bool avx_zero_opmask;
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} cs_x86_op;
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typedef struct cs_x86_encoding {
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// ModR/M offset, or 0 when irrelevant
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uint8_t modrm_offset;
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// Displacement offset, or 0 when irrelevant.
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uint8_t disp_offset;
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uint8_t disp_size;
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// Immediate offset, or 0 when irrelevant.
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uint8_t imm_offset;
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uint8_t imm_size;
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} cs_x86_encoding;
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// Instruction structure
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typedef struct cs_x86 {
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// Instruction prefix, which can be up to 4 bytes.
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@ -272,8 +259,6 @@ typedef struct cs_x86 {
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uint8_t op_count;
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cs_x86_op operands[8]; // operands for this instruction.
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cs_x86_encoding encoding; // encoding information
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} cs_x86;
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//> X86 instructions
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@ -50,19 +50,7 @@ static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins)
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printf("\taddr_size: %u\n", x86->addr_size);
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printf("\tmodrm: 0x%x\n", x86->modrm);
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if (x86->encoding.modrm_offset != 0) {
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printf("\tmodrm_offset: 0x%x\n", x86->encoding.modrm_offset);
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}
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printf("\tdisp: 0x%x\n", x86->disp);
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if (x86->encoding.disp_offset != 0) {
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printf("\tdisp_offset: 0x%x\n", x86->encoding.disp_offset);
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}
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if (x86->encoding.disp_size != 0) {
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printf("\tdisp_size: 0x%x\n", x86->encoding.disp_size);
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}
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// SIB is not available in 16-bit mode
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if ((mode & CS_MODE_16) == 0) {
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@ -101,14 +89,6 @@ static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins)
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for (i = 1; i < count + 1; i++) {
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int index = cs_op_index(ud, ins, X86_OP_IMM, i);
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printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm);
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if (x86->encoding.imm_offset != 0) {
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printf("\timm_offset: 0x%x\n", x86->encoding.imm_offset);
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}
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if (x86->encoding.imm_size != 0) {
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printf("\timm_size: 0x%x\n", x86->encoding.imm_size);
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}
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}
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}
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@ -165,12 +145,12 @@ static void test()
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//#define X86_CODE32 "\xa1\x13\x48\x6d\x3a\x8b\x81\x23\x01\x00\x00\x8b\x84\x39\x23\x01\x00\x00"
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//#define X86_CODE32 "\xb4\xc6" // mov ah, 0x6c
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//#define X86_CODE32 "\x77\x04" // ja +6
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#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
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#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
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//#define X86_CODE64 "\xe9\x79\xff\xff\xff" // jmp 0xf7e
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#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc"
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#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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//#define X86_CODE16 "\x67\x00\x18"
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#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
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#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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//#define X86_CODE32 "\x0f\xa7\xc0" // xstorerng
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//#define X86_CODE32 "\x64\xa1\x18\x00\x00\x00" // mov eax, dword ptr fs:[18]
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//#define X86_CODE32 "\x64\xa3\x00\x00\x00\x00" // mov [fs:0x0], eax
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