From 4eeceba201e02fbcd0cf9dd3d41c86ad8c4a4604 Mon Sep 17 00:00:00 2001 From: billow Date: Fri, 22 May 2026 23:04:35 +0800 Subject: [PATCH] Add M68K ColdFire ISA support (#2927) * regenerate arch/M68K/M68KInstructionTable.inc * Add M68K ColdFire ISA support * Apply suggestions from code review Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com> * Clarify M68K EA validation and detail checks * Normalize M68K memory operand details * Update docs/cs_v6_release_guide.md --------- Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com> --- arch/M68K/M68KDisassembler.c | 1174 +- arch/M68K/M68KDisassembler.h | 103 +- arch/M68K/M68KInstPrinter.c | 201 +- arch/M68K/M68KInstructionTable.inc | 15996 ++++++++-------- bindings/python/capstone/__init__.py | 75 +- bindings/python/capstone/m68k.py | 86 +- bindings/python/capstone/m68k_const.py | 763 +- .../python/cstest_py/src/cstest_py/details.py | 63 +- .../M68KInstructionTblGen.c | 53 +- cs.c | 4 +- cstool/cstool.c | 14 + cstool/cstool_m68k.c | 40 + docs/cs_v6_release_guide.md | 5 +- include/capstone/capstone.h | 30 + include/capstone/m68k.h | 51 +- suite/cstest/include/test_detail_m68k.h | 11 +- suite/cstest/include/test_mapping.h | 26 + suite/cstest/src/test_case.c | 2 +- suite/cstest/src/test_detail_m68k.c | 18 + tests/details/m68k.yaml | 9126 ++++++--- 20 files changed, 16417 insertions(+), 11424 deletions(-) diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index a24290e32..c0a400df1 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -48,18 +48,6 @@ #include "M68KDisassembler.h" #include "M68KInstPrinter.h" -enum { - M68K_CPU_TYPE_INVALID, - M68K_CPU_TYPE_68000, - M68K_CPU_TYPE_68010, - M68K_CPU_TYPE_68EC020, - M68K_CPU_TYPE_68020, - M68K_CPU_TYPE_CPU32, - M68K_CPU_TYPE_68030, - M68K_CPU_TYPE_68040, - M68K_CPU_TYPE_68060 -}; - /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// static unsigned int m68k_read_disassembler_16(const m68k_info *info, @@ -360,6 +348,69 @@ static void get_with_index_address_mode(m68k_info *info, cs_m68k_op *op, } } +enum { + /* Raw effective-address encoding bits, used before get_ea_mode_op() + * consumes any extension words and fills cs_m68k_op.address_mode. */ + M68K_EA_REGISTER_MASK = 0x07, + M68K_EA_MODE_SHIFT = 3, + M68K_EA_FIELD_MASK = 0x3f, + M68K_EA_DATA_DIRECT_D0 = 0x00, + M68K_EA_ADDR_DIRECT_A7 = 0x0f, + M68K_EA_ADDR_INDIRECT_DISP_A7 = 0x2f, + M68K_EA_IMMEDIATE_FIELD = 0x3c, +}; + +enum { + M68K_EA_MODE_DATA_DIRECT = 0, + M68K_EA_MODE_ADDR_DIRECT = 1, + M68K_EA_MODE_ADDR_INDIRECT = 2, + M68K_EA_MODE_ADDR_INDIRECT_POST_INC = 3, + M68K_EA_MODE_ADDR_INDIRECT_PRE_DEC = 4, + M68K_EA_MODE_ADDR_INDIRECT_DISP = 5, + M68K_EA_MODE_ADDR_INDIRECT_INDEX = 6, + M68K_EA_MODE_EXTENDED = 7, +}; + +enum { + M68K_EA_EXT_ABSOLUTE_SHORT = 0, + M68K_EA_EXT_ABSOLUTE_LONG = 1, +}; + +static uint32_t m68k_ea_field(uint32_t ir) +{ + return ir & M68K_EA_FIELD_MASK; +} + +static uint32_t m68k_ea_mode(uint32_t ir) +{ + return m68k_ea_field(ir) >> M68K_EA_MODE_SHIFT; +} + +static uint32_t m68k_ea_register(uint32_t ir) +{ + return ir & M68K_EA_REGISTER_MASK; +} + +static bool m68k_ea_is_data_register_direct(uint32_t ir) +{ + return m68k_ea_mode(ir) == M68K_EA_MODE_DATA_DIRECT; +} + +static bool m68k_ea_is_register_direct(uint32_t ir) +{ + return m68k_ea_field(ir) <= M68K_EA_ADDR_DIRECT_A7; +} + +static bool m68k_ea_is_immediate(uint32_t ir) +{ + return m68k_ea_field(ir) == M68K_EA_IMMEDIATE_FIELD; +} + +static bool m68k_ea_is_data_register_direct_or_immediate(uint32_t ir) +{ + return m68k_ea_is_data_register_direct(ir) || m68k_ea_is_immediate(ir); +} + /* Make string of effective address mode */ static void get_ea_mode_op(m68k_info *info, cs_m68k_op *op, uint32_t instruction, uint32_t size) @@ -368,7 +419,7 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op *op, op->type = M68K_OP_MEM; - switch (instruction & 0x3f) { + switch (m68k_ea_field(instruction)) { case 0x00: case 0x01: case 0x02: @@ -407,7 +458,7 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op *op, case 0x17: /* address register indirect */ op->address_mode = M68K_AM_REGI_ADDR; - op->reg = M68K_REG_A0 + (instruction & 7); + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); break; case 0x18: @@ -420,7 +471,7 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op *op, case 0x1f: /* address register indirect with postincrement */ op->address_mode = M68K_AM_REGI_ADDR_POST_INC; - op->reg = M68K_REG_A0 + (instruction & 7); + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); break; case 0x20: @@ -433,7 +484,7 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op *op, case 0x27: /* address register indirect with predecrement */ op->address_mode = M68K_AM_REGI_ADDR_PRE_DEC; - op->reg = M68K_REG_A0 + (instruction & 7); + op->mem.base_reg = M68K_REG_A0 + (instruction & 7); break; case 0x28: @@ -466,13 +517,13 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op *op, case 0x38: /* absolute short address */ op->address_mode = M68K_AM_ABSOLUTE_DATA_SHORT; - op->imm = read_imm_16(info); + op->mem.address = read_imm_16(info); break; case 0x39: /* absolute long address */ op->address_mode = M68K_AM_ABSOLUTE_DATA_LONG; - op->imm = read_imm_32(info); + op->mem.address = read_imm_32(info); break; case 0x3a: { @@ -802,14 +853,16 @@ static void build_absolute_jump_with_immediate(m68k_info *info, int opcode, static void build_bcc(m68k_info *info, int size, int displacement) { - build_relative_branch(info, s_branch_lut[(info->ir >> 8) & 0xf], size, - displacement); + build_relative_branch(info, + s_branch_lut[M68K_IR_CONDITION_NIBBLE(info)], + size, displacement); } static void build_trap(m68k_info *info, int size, int immediate) { build_absolute_jump_with_immediate( - info, s_trap_lut[(info->ir >> 8) & 0xf], size, immediate); + info, s_trap_lut[M68K_IR_CONDITION_NIBBLE(info)], size, + immediate); } static void build_dbxx(m68k_info *info, int opcode, int size, int displacement) @@ -835,7 +888,8 @@ static void build_dbxx(m68k_info *info, int opcode, int size, int displacement) static void build_dbcc(m68k_info *info, int size, int displacement) { - build_dbxx(info, s_dbcc_lut[(info->ir >> 8) & 0xf], size, displacement); + build_dbxx(info, s_dbcc_lut[M68K_IR_CONDITION_NIBBLE(info)], size, + displacement); } static void build_d_d_ea(m68k_info *info, int opcode, int size) @@ -905,6 +959,100 @@ static void build_d(m68k_info *info, int opcode, int size) op->reg = M68K_REG_D0 + (info->ir & 7); } +static m68k_reg cf_reg_from_nibble(unsigned int reg) +{ + return (reg & 8) ? (m68k_reg)(M68K_REG_A0 + (reg & 7)) : + (m68k_reg)(M68K_REG_D0 + (reg & 7)); +} + +static m68k_reg cf_acc_reg(unsigned int acc) +{ + switch (acc & 3) { + case 0: + return M68K_REG_ACC0; + case 1: + return M68K_REG_ACC1; + case 2: + return M68K_REG_ACC2; + default: + return M68K_REG_ACC3; + } +} + +static void cf_build_reg_op(cs_m68k_op *op, m68k_reg reg) +{ + op->address_mode = M68K_AM_NONE; + op->type = M68K_OP_REG; + op->reg = reg; +} + +static void cf_build_direct_reg_op(cs_m68k_op *op, m68k_reg reg) +{ + op->type = M68K_OP_REG; + op->reg = reg; + op->address_mode = (reg >= M68K_REG_A0 && reg <= M68K_REG_A7) ? + M68K_AM_REG_DIRECT_ADDR : + M68K_AM_REG_DIRECT_DATA; +} + +static void cf_build_imm_op(cs_m68k_op *op, uint32_t imm) +{ + op->type = M68K_OP_IMM; + op->address_mode = M68K_AM_IMMEDIATE; + op->imm = imm; +} + +static void cf_build_shift_op(cs_m68k_op *op, uint32_t shift) +{ + op->type = M68K_OP_SHIFT; + op->address_mode = M68K_AM_NONE; + op->flags = shift == 0x0200 ? M68K_OP_FLAG_SHIFT_LEFT : + M68K_OP_FLAG_SHIFT_RIGHT; +} + +static void cf_build_mac_reg_op(cs_m68k_op *op, uint32_t reg, bool long_size) +{ + cf_build_direct_reg_op(op, cf_reg_from_nibble(reg)); + if (!long_size) + op->flags = (reg & 0x10) ? M68K_OP_FLAG_REG_UPPER : + M68K_OP_FLAG_REG_LOWER; +} + +static bool cf_mac_ea_is_valid(uint32_t ir) +{ + uint32_t mode = m68k_ea_mode(ir); + + /* ColdFire MAC/EMAC load forms accept (An), (An)+, -(An), and d16(An). */ + return mode >= M68K_EA_MODE_ADDR_INDIRECT && + mode <= M68K_EA_MODE_ADDR_INDIRECT_DISP; +} + +static bool cf_coproc_ea_is_valid(uint32_t ir) +{ + return m68k_ea_field(ir) <= M68K_EA_ADDR_INDIRECT_DISP_A7; +} + +static bool cf_alterable_memory_ea_is_valid(uint32_t ir) +{ + uint32_t mode = m68k_ea_mode(ir); + uint32_t reg = m68k_ea_register(ir); + + return (mode >= M68K_EA_MODE_ADDR_INDIRECT && + mode <= M68K_EA_MODE_ADDR_INDIRECT_INDEX) || + (mode == M68K_EA_MODE_EXTENDED && + reg <= M68K_EA_EXT_ABSOLUTE_LONG); +} + +static bool cf_sr_ccr_source_ea_is_valid(uint32_t ir) +{ + return m68k_ea_is_data_register_direct_or_immediate(ir); +} + +static bool cf_sr_ccr_destination_ea_is_valid(uint32_t ir) +{ + return m68k_ea_is_data_register_direct(ir); +} + static uint16_t reverse_bits(uint32_t v) { uint32_t r = v; // r will be reversed bits of v; first get LSB of v @@ -1068,15 +1216,12 @@ static void build_move16(m68k_info *info, const uint32_t data[2], const uint32_t m = modes[i]; op->type = M68K_OP_MEM; + op->address_mode = m; - if (m == M68K_AM_REGI_ADDR_POST_INC || - m == M68K_AM_REG_DIRECT_ADDR) { - op->address_mode = m; - op->reg = M68K_REG_A0 + d; - } else { - op->address_mode = m; - op->imm = d; - } + if (m == M68K_AM_REGI_ADDR_POST_INC || m == M68K_AM_REGI_ADDR) + op->mem.base_reg = M68K_REG_A0 + d; + else + op->mem.address = d; } } @@ -1130,7 +1275,7 @@ static void build_cpush_cinv(m68k_info *info, int op_offset) op1->type = M68K_OP_MEM; op1->address_mode = M68K_AM_REGI_ADDR; - op1->reg = M68K_REG_A0 + (info->ir & 7); + op1->mem.base_reg = M68K_REG_A0 + (info->ir & 7); } static void build_movep_re(m68k_info *info, int size) @@ -1241,14 +1386,578 @@ static void d68000_illegal(m68k_info *info) build_illegal(info, info->ir); } -static void d68000_1010(m68k_info *info) +static void dcf_1111(m68k_info *info) { - build_invalid(info, info->ir); + d68000_invalid(info); } -static void d68000_1111(m68k_info *info) +static void dcf_bitop_d(m68k_info *info, m68k_insn insn) { - build_invalid(info, info->ir); + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A_PLUS | CS_MODE_M68K_CF_ISA_C); + build_d(info, insn, 0); +} + +static void dcf_bitrev(m68k_info *info) +{ + dcf_bitop_d(info, M68K_INS_BITREV); +} + +static void dcf_byterev(m68k_info *info) +{ + dcf_bitop_d(info, M68K_INS_BYTEREV); +} + +static void dcf_ff1(m68k_info *info) +{ + dcf_bitop_d(info, M68K_INS_FF1); +} + +static uint32_t cf_mov3q_imm(uint32_t ir) +{ + uint32_t imm = (ir >> 9) & 7; + + return imm == 0 ? UINT32_MAX : imm; +} + +static void dcf_mov3q(m68k_info *info) +{ + cs_m68k *ext; + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + + ext = build_init_op(info, M68K_INS_MOV3Q, 2, 4); + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + cf_build_imm_op(op0, cf_mov3q_imm(info->ir)); + get_ea_mode_op(info, op1, info->ir, 4); +} + +static void cf_init_two_op(m68k_info *info, m68k_insn insn, cs_m68k_op **op0, + cs_m68k_op **op1) +{ + cs_m68k *ext = build_init_op(info, insn, 2, 4); + + *op0 = &ext->operands[0]; + *op1 = &ext->operands[1]; +} + +static m68k_reg cf_primary_acc_reg(const m68k_info *info) +{ + return m68k_has_feature(info, CS_MODE_M68K_CF_EMAC) ? M68K_REG_ACC0 : + M68K_REG_ACC; +} + +static m68k_reg cf_accext_reg(uint32_t ir) +{ + return (ir & 0x0400) ? M68K_REG_ACCEXT23 : M68K_REG_ACCEXT01; +} + +static void dcf_movclr_accn_reg(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVCLR, &op0, &op1); + cf_build_reg_op(op0, cf_acc_reg((info->ir >> 9) & 3)); + cf_build_direct_reg_op(op1, cf_reg_from_nibble(info->ir & 0xf)); +} + +static void dcf_move_acc_reg(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, cf_primary_acc_reg(info)); + cf_build_direct_reg_op(op1, cf_reg_from_nibble(info->ir & 0xf)); +} + +static void dcf_move_accn_reg(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, cf_acc_reg((info->ir >> 9) & 3)); + cf_build_direct_reg_op(op1, cf_reg_from_nibble(info->ir & 0xf)); +} + +static void dcf_move_acc_acc(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, cf_acc_reg(info->ir & 3)); + cf_build_reg_op(op1, cf_acc_reg((info->ir >> 9) & 3)); +} + +static void dcf_move_reg_acc(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_direct_reg_op(op0, cf_reg_from_nibble(info->ir & 0xf)); + cf_build_reg_op(op1, cf_primary_acc_reg(info)); +} + +static void dcf_move_reg_accn(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_direct_reg_op(op0, cf_reg_from_nibble(info->ir & 0xf)); + cf_build_reg_op(op1, cf_acc_reg((info->ir >> 9) & 3)); +} + +static void dcf_move_imm_acc(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_imm_op(op0, read_imm_32(info)); + cf_build_reg_op(op1, cf_primary_acc_reg(info)); +} + +static void dcf_move_imm_accn(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_imm_op(op0, read_imm_32(info)); + cf_build_reg_op(op1, cf_acc_reg((info->ir >> 9) & 3)); +} + +static void dcf_move_accext_reg(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, cf_accext_reg(info->ir)); + cf_build_direct_reg_op(op1, cf_reg_from_nibble(info->ir & 0xf)); +} + +static void dcf_move_reg_accext(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_direct_reg_op(op0, cf_reg_from_nibble(info->ir & 0xf)); + cf_build_reg_op(op1, cf_accext_reg(info->ir)); +} + +static void dcf_move_imm_accext(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_EMAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_imm_op(op0, read_imm_32(info)); + cf_build_reg_op(op1, cf_accext_reg(info->ir)); +} + +static void dcf_move_macsr_reg(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, M68K_REG_MACSR); + cf_build_direct_reg_op(op1, cf_reg_from_nibble(info->ir & 0xf)); +} + +static void dcf_move_reg_macsr(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_direct_reg_op(op0, cf_reg_from_nibble(info->ir & 0xf)); + cf_build_reg_op(op1, M68K_REG_MACSR); +} + +static void dcf_move_imm_macsr(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_imm_op(op0, read_imm_32(info)); + cf_build_reg_op(op1, M68K_REG_MACSR); +} + +static void dcf_move_mask_reg(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, M68K_REG_MASK); + cf_build_direct_reg_op(op1, cf_reg_from_nibble(info->ir & 0xf)); +} + +static void dcf_move_reg_mask(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_direct_reg_op(op0, cf_reg_from_nibble(info->ir & 0xf)); + cf_build_reg_op(op1, M68K_REG_MASK); +} + +static void dcf_move_imm_mask(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_imm_op(op0, read_imm_32(info)); + cf_build_reg_op(op1, M68K_REG_MASK); +} + +static void dcf_move_macsr_ccr(m68k_info *info) +{ + cs_m68k_op *op0; + cs_m68k_op *op1; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + cf_init_two_op(info, M68K_INS_MOVE, &op0, &op1); + cf_build_reg_op(op0, M68K_REG_MACSR); + cf_build_reg_op(op1, M68K_REG_CCR); +} + +static void dcf_mac_arith(m68k_info *info) +{ + uint16_t ext_word; + cs_m68k *ext; + cs_m68k_op *op0; + cs_m68k_op *op1; + cs_m68k_op *op; + uint32_t src0; + uint32_t src1; + uint32_t update; + uint32_t acc; + bool is_memory; + bool is_emac; + int size; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_MAC); + + is_memory = !m68k_ea_is_register_direct(info->ir); + if (is_memory && !cf_mac_ea_is_valid(info->ir)) { + d68000_invalid(info); + return; + } + + ext_word = (uint16_t)read_imm_16(info); + if (!is_memory && (ext_word & 0xf000)) { + d68000_invalid(info); + return; + } + + is_emac = m68k_has_feature(info, CS_MODE_M68K_CF_EMAC) != 0; + size = (ext_word & 0x0800) ? 4 : 2; + + ext = build_init_op(info, + (ext_word & 0x0100) ? M68K_INS_MSAC : M68K_INS_MAC, + is_memory ? 0 : 2, size); + op0 = &ext->operands[0]; + op1 = &ext->operands[1]; + + if (is_memory) { + src0 = ext_word & 0xf; + src1 = (ext_word >> 12) & 0xf; + if (!(ext_word & 0x0800)) { + if (ext_word & 0x40) + src0 |= 0x10; + if (ext_word & 0x80) + src1 |= 0x10; + } + } else { + src0 = info->ir & 0xf; + src1 = ((info->ir >> 9) & 7) | ((info->ir & 0x40) ? 8 : 0); + if (!(ext_word & 0x0800)) { + if (ext_word & 0x40) + src0 |= 0x10; + if (ext_word & 0x80) + src1 |= 0x10; + } + } + + cf_build_mac_reg_op(op0, src0, size == 4); + cf_build_mac_reg_op(op1, src1, size == 4); + ext->op_count = 2; + + if (ext_word & 0x0600) { + op = &ext->operands[ext->op_count++]; + cf_build_shift_op(op, ext_word & 0x0600); + } + + if (is_memory) { + op = &ext->operands[ext->op_count++]; + get_ea_mode_op(info, op, info->ir, size); + if (ext_word & 0x20) + op->flags |= M68K_OP_FLAG_MEM_UPDATE; + + update = ((info->ir >> 9) & 7) | ((info->ir & 0x40) ? 8 : 0); + op = &ext->operands[ext->op_count++]; + cf_build_direct_reg_op(op, cf_reg_from_nibble(update)); + } + + if (is_emac) { + if (is_memory) + acc = ((ext_word >> 3) & 0x2) | + ((~info->ir >> 7) & 0x1); + else + acc = ((info->ir & 0x80) ? 1 : 0) | + ((ext_word & 0x10) ? 2 : 0); + op = &ext->operands[ext->op_count++]; + cf_build_reg_op(op, cf_acc_reg(acc)); + } +} + +static void dcf_mvs_8(m68k_info *info) +{ + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + ext = build_init_op(info, M68K_INS_MVS, 2, 1); + get_ea_mode_op(info, &ext->operands[0], info->ir, 1); + cf_build_direct_reg_op(&ext->operands[1], + (m68k_reg)(M68K_REG_D0 + ((info->ir >> 9) & 7))); +} + +static void dcf_mvs_16(m68k_info *info) +{ + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + ext = build_init_op(info, M68K_INS_MVS, 2, 2); + get_ea_mode_op(info, &ext->operands[0], info->ir, 2); + cf_build_direct_reg_op(&ext->operands[1], + (m68k_reg)(M68K_REG_D0 + ((info->ir >> 9) & 7))); +} + +static void dcf_mvz_8(m68k_info *info) +{ + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + ext = build_init_op(info, M68K_INS_MVZ, 2, 1); + get_ea_mode_op(info, &ext->operands[0], info->ir, 1); + cf_build_direct_reg_op(&ext->operands[1], + (m68k_reg)(M68K_REG_D0 + ((info->ir >> 9) & 7))); +} + +static void dcf_mvz_16(m68k_info *info) +{ + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + ext = build_init_op(info, M68K_INS_MVZ, 2, 2); + get_ea_mode_op(info, &ext->operands[0], info->ir, 2); + cf_build_direct_reg_op(&ext->operands[1], + (m68k_reg)(M68K_REG_D0 + ((info->ir >> 9) & 7))); +} + +static void dcf_sats(m68k_info *info) +{ + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + build_d(info, M68K_INS_SATS, 4); +} + +static void dcf_strldsr(m68k_info *info) +{ + cs_m68k *ext; + cs_m68k_op *op; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A_PLUS | CS_MODE_M68K_CF_ISA_C); + + (void)read_imm_16(info); + ext = build_init_op(info, M68K_INS_STRLDSR, 1, 2); + op = &ext->operands[0]; + cf_build_imm_op(op, read_imm_16(info)); +} + +static void dcf_wddata(m68k_info *info) +{ + int size_bits = (info->ir >> 6) & 3; + int size; + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A); + + switch (size_bits) { + case 0: + size = 1; + break; + case 1: + size = 2; + break; + case 2: + size = 4; + break; + default: + d68000_invalid(info); + return; + } + + if (!cf_alterable_memory_ea_is_valid(info->ir)) { + d68000_invalid(info); + return; + } + + ext = build_init_op(info, M68K_INS_WDDATA, 1, size); + get_ea_mode_op(info, &ext->operands[0], info->ir, size); +} + +static void dcf_wdebug(m68k_info *info) +{ + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A); + + if (read_imm_16(info) != 3) { + d68000_invalid(info); + return; + } + + ext = build_init_op(info, M68K_INS_WDEBUG, 1, 4); + get_ea_mode_op(info, &ext->operands[0], info->ir, 4); +} + +static void dcf_intouch(m68k_info *info) +{ + cs_m68k *ext; + cs_m68k_op *op; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C); + + ext = build_init_op(info, M68K_INS_INTOUCH, 1, 0); + op = &ext->operands[0]; + op->type = M68K_OP_MEM; + op->address_mode = M68K_AM_REGI_ADDR; + op->mem.base_reg = M68K_REG_A0 + (info->ir & 7); +} + +static void dcf_build_coproc_branch(m68k_info *info, int opcode, + int displacement) +{ + cs_m68k_op *op; + cs_m68k *ext = build_init_op(info, opcode, 1, 0); + + op = &ext->operands[0]; + op->type = M68K_OP_BR_DISP; + op->address_mode = M68K_AM_BRANCH_DISPLACEMENT; + op->br_disp.disp = displacement; + op->br_disp.disp_size = 2; + + set_insn_group(info, M68K_GRP_JUMP); + set_insn_group(info, M68K_GRP_BRANCH_RELATIVE); +} + +static int cf_coproc_size(uint16_t ir) +{ + switch (ir & 0x00c0) { + case 0x0000: + return 1; + case 0x0040: + return 2; + case 0x0080: + return 4; + default: + return 0; + } +} + +static void dcf_cp0bcbusy(m68k_info *info) +{ + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A); + dcf_build_coproc_branch(info, M68K_INS_CP0BCBUSY, + make_int_16(read_imm_16(info))); +} + +static void dcf_cp1bcbusy(m68k_info *info) +{ + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A); + dcf_build_coproc_branch(info, M68K_INS_CP1BCBUSY, + make_int_16(read_imm_16(info))); +} + +static void dcf_coproc_ldst(m68k_info *info) +{ + uint16_t ext_word; + bool cp1; + bool store; + int size; + int opcode; + cs_m68k *ext; + + LIMIT_FEATURE(info, CS_MODE_M68K_CF_ISA_A); + + size = cf_coproc_size(info->ir); + if (!size || !cf_coproc_ea_is_valid(info->ir)) { + d68000_invalid(info); + return; + } + + cp1 = (info->ir & 0x0200) != 0; + store = (info->ir & 0x0100) != 0; + ext_word = (uint16_t)read_imm_16(info); + + if (!store && m68k_ea_field(info->ir) == M68K_EA_DATA_DIRECT_D0 && + (ext_word & 0xf1ff) == 0) { + opcode = cp1 ? M68K_INS_CP1NOP : M68K_INS_CP0NOP; + ext = build_init_op(info, opcode, 1, 0); + cf_build_imm_op(&ext->operands[0], ((ext_word >> 9) & 7) + 1); + return; + } + + opcode = cp1 ? (store ? M68K_INS_CP1ST : M68K_INS_CP1LD) : + (store ? M68K_INS_CP0ST : M68K_INS_CP0LD); + ext = build_init_op(info, opcode, 4, size); + + if (store) { + cf_build_direct_reg_op(&ext->operands[0], + cf_reg_from_nibble((ext_word >> 12) & + 0xf)); + get_ea_mode_op(info, &ext->operands[1], info->ir, size); + } else { + get_ea_mode_op(info, &ext->operands[0], info->ir, size); + cf_build_direct_reg_op(&ext->operands[1], + cf_reg_from_nibble((ext_word >> 12) & + 0xf)); + } + + cf_build_imm_op(&ext->operands[2], ((ext_word >> 9) & 7) + 1); + cf_build_imm_op(&ext->operands[3], ext_word & 0x1ff); } static void d68000_abcd_rr(m68k_info *info) @@ -1500,7 +2209,8 @@ static void d68000_bcc_16(m68k_info *info) static void d68020_bcc_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_B | + CS_MODE_M68K_CF_ISA_C); build_bcc(info, 4, read_imm_32(info)); } @@ -1526,7 +2236,7 @@ static void d68000_bclr_s(m68k_info *info) static void d68010_bkpt(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_absolute_jump_with_immediate(info, M68K_INS_BKPT, 0, info->ir & 7); } @@ -1534,32 +2244,32 @@ static void d68010_bkpt(m68k_info *info) static void d68020_bfchg(m68k_info *info) { /* Bit field ops are 68020+ only; CPU32 does NOT support them - * despite sharing TYPE_68020. */ - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + * despite sharing CS_MODE_M68K_020. */ + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFCHG, false); } static void d68020_bfclr(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFCLR, false); } static void d68020_bfexts(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFEXTS, true); } static void d68020_bfextu(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFEXTU, true); } static void d68020_bfffo(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFFFO, true); } @@ -1568,7 +2278,7 @@ static void d68020_bfins(m68k_info *info) cs_m68k *ext = &info->extension; cs_m68k_op temp; - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFINS, true); // a bit hacky but we need to flip the args on only this instruction @@ -1580,13 +2290,13 @@ static void d68020_bfins(m68k_info *info) static void d68020_bfset(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFSET, false); } static void d68020_bftst(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_bitfield_ins(info, M68K_INS_BFTST, false); } @@ -1603,7 +2313,8 @@ static void d68000_bra_16(m68k_info *info) static void d68020_bra_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_B | + CS_MODE_M68K_CF_ISA_C); build_relative_branch(info, M68K_INS_BRA, 4, read_imm_32(info)); } @@ -1630,7 +2341,8 @@ static void d68000_bsr_16(m68k_info *info) static void d68020_bsr_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_B | + CS_MODE_M68K_CF_ISA_C); build_relative_branch(info, M68K_INS_BSR, 4, read_imm_32(info)); } @@ -1647,7 +2359,7 @@ static void d68000_btst_s(m68k_info *info) static void d68020_callm(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_ONLY); + LIMIT_FEATURE(info, M68020_ONLY); build_imm_ea(info, M68K_INS_CALLM, 0, read_imm_8(info)); } @@ -1656,33 +2368,33 @@ static void d68020_cas_8(m68k_info *info) /* * MC68060 traps CAS/CAS2/CHK2/CMP2 for software emulation, but they remain * valid opcodes and must still disassemble successfully. - * CAS/CAS2 are NOT available on CPU32 despite its TYPE_68020 overlap. + * CAS/CAS2 are NOT available on CPU32 despite its CS_MODE_M68K_020 overlap. */ - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_d_d_ea(info, M68K_INS_CAS, 1); } static void d68020_cas_16(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_d_d_ea(info, M68K_INS_CAS, 2); } static void d68020_cas_32(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_d_d_ea(info, M68K_INS_CAS, 4); } static void d68020_cas2_16(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_cas2(info, 2); } static void d68020_cas2_32(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_cas2(info, 4); } @@ -1693,31 +2405,31 @@ static void d68000_chk_16(m68k_info *info) static void d68020_chk_32(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_er_1(info, M68K_INS_CHK, 4); } static void d68020_chk2_cmp2_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_chk2_cmp2(info, 1); } static void d68020_chk2_cmp2_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_chk2_cmp2(info, 2); } static void d68020_chk2_cmp2_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_chk2_cmp2(info, 4); } static void d68040_cinv(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); build_cpush_cinv(info, M68K_INS_CINVL); } @@ -1768,13 +2480,13 @@ static void d68000_cmpi_8(m68k_info *info) static void d68020_cmpi_pcdi_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); } static void d68020_cmpi_pcix_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 1, read_imm_8(info)); } @@ -1785,13 +2497,13 @@ static void d68000_cmpi_16(m68k_info *info) static void d68020_cmpi_pcdi_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); } static void d68020_cmpi_pcix_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 2, read_imm_16(info)); } @@ -1802,13 +2514,13 @@ static void d68000_cmpi_32(m68k_info *info) static void d68020_cmpi_pcdi_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); } static void d68020_cmpi_pcix_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_imm_ea(info, M68K_INS_CMPI, 4, read_imm_32(info)); } @@ -1839,11 +2551,12 @@ static void d68020_cpbcc_16(m68k_info *info) { cs_m68k_op *op0; cs_m68k *ext; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); int cpid = M68K_CPID(info); int cond = M68K_IR_CONDITION(info); if (cpid == M68K_CPID_MMU) { - if (cond >= M68K_PMMU_MAX_COND || (info->type & TYPE_CPU32)) { + if (cond >= M68K_PMMU_MAX_COND || + m68k_has_feature(info, CS_MODE_M68K_CPU32)) { d68000_invalid(info); return; } @@ -1878,11 +2591,12 @@ static void d68020_cpbcc_32(m68k_info *info) { cs_m68k *ext; cs_m68k_op *op0; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); int cpid = M68K_CPID(info); int cond = M68K_IR_CONDITION(info); if (cpid == M68K_CPID_MMU) { - if (cond >= M68K_PMMU_MAX_COND || (info->type & TYPE_CPU32)) { + if (cond >= M68K_PMMU_MAX_COND || + m68k_has_feature(info, CS_MODE_M68K_CPU32)) { d68000_invalid(info); return; } @@ -1913,9 +2627,10 @@ static void d68020_cpdbcc(m68k_info *info) cs_m68k_op *op1; uint32_t ext1, ext2; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); - if (M68K_CPID(info) == M68K_CPID_CACHE && (info->type & M68040_PLUS)) { + if (M68K_CPID(info) == M68K_CPID_CACHE && + m68k_has_feature(info, M68040_PLUS)) { if (M68K_IR_IS_CPUSH(info)) d68040_cpush(info); else @@ -2025,9 +2740,10 @@ static void d68020_cpgen(m68k_info *info) uint32_t next; int rm, src, dst, opmode; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); - if (M68K_CPID(info) == M68K_CPID_MMU && (info->type & TYPE_68030)) { + if (M68K_CPID(info) == M68K_CPID_MMU && + m68k_has_feature(info, CS_MODE_M68K_030)) { d68030_pmmu(info); return; } @@ -2044,11 +2760,8 @@ static void d68020_cpgen(m68k_info *info) * operations (type 0-1); fmove_fpcr/fmovem types are dispatched * separately and never reach the SD path. */ uint32_t peeked = peek_imm_16(info); - if (M68K_FEXT_TYPE(peeked) <= 1 && M68K_FEXT_SD_FLAG(peeked) && - !(info->type & M68040_PLUS)) { - d68000_invalid(info); - return; - } + if (M68K_FEXT_TYPE(peeked) <= 1 && M68K_FEXT_SD_FLAG(peeked)) + LIMIT_FEATURE(info, M68040_PLUS | CS_MODE_M68K_CF_FPU); next = read_imm_16(info); @@ -2270,15 +2983,18 @@ fpu_operands: ext->op_size.type = M68K_SIZE_TYPE_FPU; ext->op_size.fpu_size = M68K_FPU_SIZE_SINGLE; get_ea_mode_op(info, op0, info->ir, 4); - op0->simm = BitsToFloat(op0->imm); - op0->type = M68K_OP_FP_SINGLE; + if (op0->address_mode == M68K_AM_IMMEDIATE) { + op0->simm = BitsToFloat(op0->imm); + op0->type = M68K_OP_FP_SINGLE; + } break; case M68K_FPSRC_DOUBLE: ext->op_size.type = M68K_SIZE_TYPE_FPU; ext->op_size.fpu_size = M68K_FPU_SIZE_DOUBLE; get_ea_mode_op(info, op0, info->ir, 8); - op0->type = M68K_OP_FP_DOUBLE; + if (op0->address_mode == M68K_AM_IMMEDIATE) + op0->type = M68K_OP_FP_DOUBLE; break; case M68K_FPSRC_EXTENDED: @@ -2308,8 +3024,8 @@ fpu_operands: static void d68020_cprestore(m68k_info *info) { cs_m68k *ext; - LIMIT_CPU_TYPES(info, M68020_PLUS); - REQUIRE_CPID_FPU_OR_PMMU(info); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); + REQUIRE_CPID_FPU(info); ext = build_init_op(info, M68K_INS_FRESTORE, 1, 0); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); @@ -2318,8 +3034,8 @@ static void d68020_cprestore(m68k_info *info) static void d68020_cpsave(m68k_info *info) { cs_m68k *ext; - LIMIT_CPU_TYPES(info, M68020_PLUS); - REQUIRE_CPID_FPU_OR_PMMU(info); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); + REQUIRE_CPID_FPU(info); ext = build_init_op(info, M68K_INS_FSAVE, 1, 0); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); @@ -2327,7 +3043,7 @@ static void d68020_cpsave(m68k_info *info) static void d68040_pflush_or_cpsave(m68k_info *info) { - if (info->type & M68040_PLUS) { + if (m68k_has_feature(info, M68040_PLUS)) { d68040_pflush(info); return; } @@ -2336,11 +3052,11 @@ static void d68040_pflush_or_cpsave(m68k_info *info) static void d68040_ptest_or_cprestore(m68k_info *info) { - if (info->type & TYPE_68040) { + if (m68k_has_feature(info, CS_MODE_M68K_040)) { d68040_ptest(info); return; } - if (info->type & TYPE_68060) { + if (m68k_has_feature(info, CS_MODE_M68K_060)) { d68000_invalid(info); return; } @@ -2350,7 +3066,7 @@ static void d68040_ptest_or_cprestore(m68k_info *info) static void d68020_cpscc(m68k_info *info) { cs_m68k *ext; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); REQUIRE_CPID_FPU(info); ext = build_init_op(info, M68K_INS_FSF, 1, 1); info->inst->Opcode += M68K_FP_COND(read_imm_16(info)); @@ -2361,7 +3077,7 @@ static void d68020_cpscc(m68k_info *info) static void d68020_cptrapcc_0(m68k_info *info) { uint32_t extension1; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); REQUIRE_CPID_FPU(info); extension1 = read_imm_16(info); @@ -2375,7 +3091,7 @@ static void d68020_cptrapcc_16(m68k_info *info) uint32_t extension1, extension2; cs_m68k_op *op0; cs_m68k *ext; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); REQUIRE_CPID_FPU(info); extension1 = read_imm_16(info); @@ -2396,7 +3112,7 @@ static void d68020_cptrapcc_32(m68k_info *info) uint32_t extension1, extension2; cs_m68k *ext; cs_m68k_op *op0; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_FPU); REQUIRE_CPID_FPU(info); extension1 = read_imm_16(info); @@ -2414,7 +3130,12 @@ static void d68020_cptrapcc_32(m68k_info *info) static void d68040_cpush(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS | CS_MODE_M68K_CF_ISA_A); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + M68K_IR_CACHE_SCOPE(info) != 1) { + d68000_invalid(info); + return; + } build_cpush_cinv(info, M68K_INS_CPUSHL); } @@ -2441,12 +3162,14 @@ static void d68000_divu(m68k_info *info) static void d68020_divl(m68k_info *info) { uint32_t extension, insn_signed; + bool cf_remainder; cs_m68k *ext; cs_m68k_op *op0; cs_m68k_op *op1; uint32_t reg_0, reg_1; + m68k_insn opcode; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_DIV); extension = read_imm_16(info); insn_signed = 0; @@ -2454,23 +3177,28 @@ static void d68020_divl(m68k_info *info) if (BIT_B((extension))) insn_signed = 1; - ext = build_init_op(info, insn_signed ? M68K_INS_DIVS : M68K_INS_DIVU, - 2, 4); + reg_0 = extension & 7; + reg_1 = (extension >> 12) & 7; + cf_remainder = m68k_has_feature(info, CS_MODE_M68K_CF_DIV) && + !BIT_A(extension) && (reg_0 != reg_1); + if (cf_remainder) + opcode = insn_signed ? M68K_INS_REMS : M68K_INS_REMU; + else + opcode = insn_signed ? M68K_INS_DIVS : M68K_INS_DIVU; + + ext = build_init_op(info, opcode, 2, 4); op0 = &ext->operands[0]; op1 = &ext->operands[1]; get_ea_mode_op(info, op0, info->ir, 4); - reg_0 = extension & 7; - reg_1 = (extension >> 12) & 7; - op1->address_mode = M68K_AM_NONE; op1->type = M68K_OP_REG_PAIR; op1->reg_pair.reg_0 = reg_0 + M68K_REG_D0; op1->reg_pair.reg_1 = reg_1 + M68K_REG_D0; - if ((reg_0 == reg_1) || !BIT_A(extension)) { + if ((reg_0 == reg_1) || (!BIT_A(extension) && !cf_remainder)) { op1->type = M68K_OP_REG; op1->reg = M68K_REG_D0 + reg_1; } @@ -2567,7 +3295,7 @@ static void d68000_ext_32(m68k_info *info) static void d68020_extb_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_A); build_d(info, M68K_INS_EXTB, 4); } @@ -2597,7 +3325,7 @@ static void d68000_link_16(m68k_info *info) static void d68020_link_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_link(info, read_imm_32(info), 4); } @@ -2702,6 +3430,13 @@ static void d68000_move_to_ccr(m68k_info *info) cs_m68k_op *op1; cs_m68k *ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + (!m68k_has_feature(info, CS_MODE_M68K_CF_ISA_A) || + !cf_sr_ccr_source_ea_is_valid(info->ir))) { + d68000_invalid(info); + return; + } + op0 = &ext->operands[0]; op1 = &ext->operands[1]; @@ -2717,7 +3452,13 @@ static void d68010_move_fr_ccr(m68k_info *info) cs_m68k_op *op1; cs_m68k *ext; - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS | CS_MODE_M68K_CF_ISA_A); + + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + !cf_sr_ccr_destination_ea_is_valid(info->ir)) { + d68000_invalid(info); + return; + } ext = build_init_op(info, M68K_INS_MOVE, 2, 2); @@ -2736,6 +3477,13 @@ static void d68000_move_fr_sr(m68k_info *info) cs_m68k_op *op1; cs_m68k *ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + (!m68k_has_feature(info, CS_MODE_M68K_CF_ISA_A) || + !cf_sr_ccr_destination_ea_is_valid(info->ir))) { + d68000_invalid(info); + return; + } + op0 = &ext->operands[0]; op1 = &ext->operands[1]; @@ -2751,6 +3499,13 @@ static void d68000_move_to_sr(m68k_info *info) cs_m68k_op *op1; cs_m68k *ext = build_init_op(info, M68K_INS_MOVE, 2, 2); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + (!m68k_has_feature(info, CS_MODE_M68K_CF_ISA_A) || + !cf_sr_ccr_source_ea_is_valid(info->ir))) { + d68000_invalid(info); + return; + } + op0 = &ext->operands[0]; op1 = &ext->operands[1]; @@ -2766,6 +3521,12 @@ static void d68000_move_fr_usp(m68k_info *info) cs_m68k_op *op1; cs_m68k *ext = build_init_op(info, M68K_INS_MOVE, 2, 0); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + !m68k_has_feature(info, CS_MODE_M68K_CF_USP)) { + d68000_invalid(info); + return; + } + op0 = &ext->operands[0]; op1 = &ext->operands[1]; @@ -2782,6 +3543,12 @@ static void d68000_move_to_usp(m68k_info *info) cs_m68k_op *op1; cs_m68k *ext = build_init_op(info, M68K_INS_MOVE, 2, 0); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE) && + !m68k_has_feature(info, CS_MODE_M68K_CF_USP)) { + d68000_invalid(info); + return; + } + op0 = &ext->operands[0]; op1 = &ext->operands[1]; @@ -2800,7 +3567,7 @@ static void d68010_movec(m68k_info *info) cs_m68k_op *op0; cs_m68k_op *op1; - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS | CS_MODE_M68K_CF_ISA_A); extension = read_imm_16(info); reg = M68K_REG_INVALID; @@ -2930,20 +3697,20 @@ static void d68000_movep_er_32(m68k_info *info) static void d68010_moves_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_moves(info, 1); } static void d68010_moves_16(m68k_info *info) { //uint32_t extension; - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_moves(info, 2); } static void d68010_moves_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_moves(info, 4); } @@ -2971,7 +3738,7 @@ static void d68040_move16_pi_pi(m68k_info *info) uint32_t modes[] = { M68K_AM_REGI_ADDR_POST_INC, M68K_AM_REGI_ADDR_POST_INC }; - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); build_move16(info, data, modes); } @@ -2982,7 +3749,7 @@ static void d68040_move16_pi_al(m68k_info *info) uint32_t modes[] = { M68K_AM_REGI_ADDR_POST_INC, M68K_AM_ABSOLUTE_DATA_LONG }; - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); data[0] = info->ir & 7; data[1] = read_imm_32(info); @@ -2995,7 +3762,7 @@ static void d68040_move16_al_pi(m68k_info *info) uint32_t modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, M68K_AM_REGI_ADDR_POST_INC }; - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); data[0] = read_imm_32(info); data[1] = info->ir & 7; @@ -3005,10 +3772,9 @@ static void d68040_move16_al_pi(m68k_info *info) static void d68040_move16_ai_al(m68k_info *info) { uint32_t data[2]; - uint32_t modes[] = { M68K_AM_REG_DIRECT_ADDR, - M68K_AM_ABSOLUTE_DATA_LONG }; + uint32_t modes[] = { M68K_AM_REGI_ADDR, M68K_AM_ABSOLUTE_DATA_LONG }; - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); data[0] = info->ir & 7; data[1] = read_imm_32(info); @@ -3018,10 +3784,9 @@ static void d68040_move16_ai_al(m68k_info *info) static void d68040_move16_al_ai(m68k_info *info) { uint32_t data[2]; - uint32_t modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, - M68K_AM_REG_DIRECT_ADDR }; + uint32_t modes[] = { M68K_AM_ABSOLUTE_DATA_LONG, M68K_AM_REGI_ADDR }; - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); data[0] = read_imm_32(info); data[1] = info->ir & 7; @@ -3046,7 +3811,9 @@ static void d68020_mull(m68k_info *info) cs_m68k_op *op1; uint32_t reg_0, reg_1; - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_A | + CS_MODE_M68K_CF_ISA_B | + CS_MODE_M68K_CF_ISA_C); extension = read_imm_16(info); insn_signed = 0; @@ -3190,13 +3957,13 @@ static void d68000_ori_to_sr(m68k_info *info) static void d68020_pack_rr(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_rr(info, M68K_INS_PACK, 0, read_imm_16(info)); } static void d68020_pack_mm(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_mm(info, M68K_INS_PACK, 0, read_imm_16(info)); } @@ -3353,7 +4120,7 @@ static void d68000_roxl_ea(m68k_info *info) static void d68010_rtd(m68k_info *info) { set_insn_group(info, M68K_GRP_RET); - LIMIT_CPU_TYPES(info, M68010_PLUS); + LIMIT_FEATURE(info, M68010_PLUS); build_absolute_jump_with_immediate(info, M68K_INS_RTD, 0, read_imm_16(info)); } @@ -3371,7 +4138,7 @@ static void d68020_rtm(m68k_info *info) set_insn_group(info, M68K_GRP_RET); - LIMIT_CPU_TYPES(info, M68020_ONLY); + LIMIT_FEATURE(info, M68020_ONLY); build_absolute_jump_with_immediate(info, M68K_INS_RTM, 0, 0); @@ -3412,8 +4179,8 @@ static void d68000_sbcd_mm(m68k_info *info) static void d68000_scc(m68k_info *info) { - cs_m68k *ext = - build_init_op(info, s_scc_lut[(info->ir >> 8) & 0xf], 1, 1); + cs_m68k *ext = build_init_op( + info, s_scc_lut[M68K_IR_CONDITION_NIBBLE(info)], 1, 1); get_ea_mode_op(info, &ext->operands[0], info->ir, 1); } @@ -3435,7 +4202,7 @@ static void d68040_pflush(m68k_info *info) cs_m68k *ext; cs_m68k_op *op; - LIMIT_CPU_TYPES(info, M68040_PLUS); + LIMIT_FEATURE(info, M68040_PLUS); mode = (info->ir >> 3) & 3; @@ -3445,14 +4212,14 @@ static void d68040_pflush(m68k_info *info) op = &ext->operands[0]; op->address_mode = M68K_AM_REGI_ADDR; op->type = M68K_OP_MEM; - op->reg = M68K_REG_A0 + (info->ir & 7); + op->mem.base_reg = M68K_REG_A0 + (info->ir & 7); break; case 1: /* PFLUSH (An) */ ext = build_init_op(info, M68K_INS_PFLUSH, 1, 0); op = &ext->operands[0]; op->address_mode = M68K_AM_REGI_ADDR; op->type = M68K_OP_MEM; - op->reg = M68K_REG_A0 + (info->ir & 7); + op->mem.base_reg = M68K_REG_A0 + (info->ir & 7); break; case 2: /* PFLUSHAN */ build_init_op(info, M68K_INS_PFLUSHAN, 0, 0); @@ -3476,7 +4243,7 @@ static void d68040_ptest(m68k_info *info) cs_m68k_op *op; int insn; - LIMIT_CPU_TYPES(info, TYPE_68040); + LIMIT_FEATURE(info, CS_MODE_M68K_040); is_read = (info->ir >> 5) & 1; insn = is_read ? M68K_INS_PTESTR : M68K_INS_PTESTW; @@ -3485,7 +4252,7 @@ static void d68040_ptest(m68k_info *info) op = &ext->operands[0]; op->address_mode = M68K_AM_REGI_ADDR; op->type = M68K_OP_MEM; - op->reg = M68K_REG_A0 + (info->ir & 7); + op->mem.base_reg = M68K_REG_A0 + (info->ir & 7); } static void d68060_plpa(m68k_info *info) @@ -3499,7 +4266,7 @@ static void d68060_plpa(m68k_info *info) cs_m68k_op *op; int insn; - LIMIT_CPU_TYPES(info, TYPE_68060); + LIMIT_FEATURE(info, CS_MODE_M68K_060); is_read = (info->ir >> 6) & 1; insn = is_read ? M68K_INS_PLPAR : M68K_INS_PLPAW; @@ -3508,18 +4275,18 @@ static void d68060_plpa(m68k_info *info) op = &ext->operands[0]; op->address_mode = M68K_AM_REGI_ADDR; op->type = M68K_OP_MEM; - op->reg = M68K_REG_A0 + (info->ir & 7); + op->mem.base_reg = M68K_REG_A0 + (info->ir & 7); } static void d68060_halt(m68k_info *info) { - LIMIT_CPU_TYPES_UNDECODED(info, TYPE_68060); + LIMIT_FEATURE_UNDECODED(info, CS_MODE_M68K_060 | CS_MODE_M68K_CF_ISA_A); build_init_op(info, M68K_INS_HALT, 0, 0); } static void d68cpu32_bgnd(m68k_info *info) { - LIMIT_CPU_TYPES_UNDECODED(info, TYPE_CPU32); + LIMIT_FEATURE_UNDECODED(info, CS_MODE_M68K_CPU32); build_init_op(info, M68K_INS_BGND, 0, 0); } @@ -3533,7 +4300,7 @@ static void d68cpu32_tbl(m68k_info *info) cs_m68k_op *op0; cs_m68k_op *op1; - if (!(info->type & TYPE_CPU32)) { + if (!m68k_has_feature(info, CS_MODE_M68K_CPU32)) { d68020_cpgen(info); return; } @@ -3674,7 +4441,8 @@ static void d68030_pmmu(m68k_info *info) case 1: { int is_flush; - if (cmd == 0x2400 && (info->ir & 0x3f) == 0) { + if (cmd == 0x2400 && + m68k_ea_field(info->ir) == M68K_EA_DATA_DIRECT_D0) { read_imm_16(info); build_init_op(info, M68K_INS_PFLUSHA, 0, 0); break; @@ -3857,7 +4625,7 @@ static void d68030_pmmu(m68k_info *info) static void d68060_lpstop(m68k_info *info) { - if (!(info->type & (TYPE_CPU32 | TYPE_68060))) { + if (!m68k_has_feature(info, CS_MODE_M68K_CPU32 | CS_MODE_M68K_060)) { d68020_cpgen(info); return; } @@ -3866,7 +4634,7 @@ static void d68060_lpstop(m68k_info *info) * try TBL (CPU32) or fall through to cpgen. */ if (peek_imm_16(info) != 0x01c0) { - if (info->type & TYPE_CPU32) { + if (m68k_has_feature(info, CS_MODE_M68K_CPU32)) { d68cpu32_tbl(info); } else { d68020_cpgen(info); @@ -3991,7 +4759,7 @@ static void d68000_tas(m68k_info *info) static void d68060_pulse(m68k_info *info) { - LIMIT_CPU_TYPES(info, TYPE_68060); + LIMIT_FEATURE(info, CS_MODE_M68K_060 | CS_MODE_M68K_CF_ISA_A); build_init_op(info, M68K_INS_PULSE, 0, 0); } @@ -4003,7 +4771,17 @@ static void d68000_trap(m68k_info *info) static void d68020_trapcc_0(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_A); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE)) { + if (M68K_IR_CONDITION_NIBBLE(info) != M68K_CONDITION_FALSE) { + d68000_invalid(info); + return; + } + build_absolute_jump_with_immediate(info, M68K_INS_TPF, 0, 0); + info->extension.op_count = 0; + return; + } + build_trap(info, 0, 0); info->extension.op_count = 0; @@ -4011,13 +4789,33 @@ static void d68020_trapcc_0(m68k_info *info) static void d68020_trapcc_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_A); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE)) { + if (M68K_IR_CONDITION_NIBBLE(info) != M68K_CONDITION_FALSE) { + d68000_invalid(info); + return; + } + build_absolute_jump_with_immediate(info, M68K_INS_TPF, 2, + read_imm_16(info)); + return; + } + build_trap(info, 2, read_imm_16(info)); } static void d68020_trapcc_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS | CS_MODE_M68K_CF_ISA_A); + if (m68k_has_feature(info, CS_MODE_M68K_COLDFIRE)) { + if (M68K_IR_CONDITION_NIBBLE(info) != M68K_CONDITION_FALSE) { + d68000_invalid(info); + return; + } + build_absolute_jump_with_immediate(info, M68K_INS_TPF, 4, + read_imm_32(info)); + return; + } + build_trap(info, 4, read_imm_32(info)); } @@ -4033,19 +4831,19 @@ static void d68000_tst_8(m68k_info *info) static void d68020_tst_pcdi_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 1); } static void d68020_tst_pcix_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 1); } static void d68020_tst_i_8(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 1); } @@ -4056,25 +4854,25 @@ static void d68000_tst_16(m68k_info *info) static void d68020_tst_a_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_pcdi_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_pcix_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } static void d68020_tst_i_16(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 2); } @@ -4085,25 +4883,25 @@ static void d68000_tst_32(m68k_info *info) static void d68020_tst_a_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_pcdi_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_pcix_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } static void d68020_tst_i_32(m68k_info *info) { - LIMIT_CPU_TYPES(info, M68020_PLUS); + LIMIT_FEATURE(info, M68020_PLUS); build_ea(info, M68K_INS_TST, 4); } @@ -4120,13 +4918,13 @@ static void d68000_unlk(m68k_info *info) static void d68020_unpk_rr(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_rr(info, M68K_INS_UNPK, 0, read_imm_16(info)); } static void d68020_unpk_mm(m68k_info *info) { - LIMIT_CPU_TYPES_NOT_CPU32(info, M68020_PLUS); + LIMIT_FEATURE_EXCLUDING(info, M68020_PLUS, CS_MODE_M68K_CPU32); build_mm(info, M68K_INS_UNPK, 0, read_imm_16(info)); } @@ -4192,12 +4990,12 @@ static void update_am_reg_list(m68k_info *info, cs_m68k_op *op, int write) case M68K_AM_REGI_ADDR_POST_INC: case M68K_AM_REGI_ADDR_PRE_DEC: - add_reg_to_rw_list(info, op->reg, 1); + add_reg_to_rw_list(info, op->mem.base_reg, 1); break; case M68K_AM_REGI_ADDR: case M68K_AM_REGI_ADDR_DISP: - add_reg_to_rw_list(info, op->reg, 0); + add_reg_to_rw_list(info, op->mem.base_reg, 0); break; case M68K_AM_AREGI_INDEX_8_BIT_DISP: @@ -4283,51 +5081,16 @@ static void build_regs_read_write_counts(m68k_info *info) } static void m68k_setup_internals(m68k_info *info, MCInst *inst, uint32_t pc, - uint32_t cpu_type) + m68k_feature_mask features) { info->inst = inst; info->pc = pc; info->ir = 0; - info->type = cpu_type; - info->address_mask = 0xffffffff; - - switch (info->type) { - case M68K_CPU_TYPE_68000: - info->type = TYPE_68000; + info->features = features; + if (m68k_has_feature(info, M68010_LESS)) info->address_mask = 0x00ffffff; - break; - case M68K_CPU_TYPE_68010: - info->type = TYPE_68010; - info->address_mask = 0x00ffffff; - break; - case M68K_CPU_TYPE_68EC020: - info->type = TYPE_68020; - info->address_mask = 0x00ffffff; - break; - case M68K_CPU_TYPE_68020: - info->type = TYPE_68020; + else info->address_mask = 0xffffffff; - break; - case M68K_CPU_TYPE_CPU32: - info->type = TYPE_68020 | TYPE_CPU32; - info->address_mask = 0xffffffff; - break; - case M68K_CPU_TYPE_68030: - info->type = TYPE_68030; - info->address_mask = 0xffffffff; - break; - case M68K_CPU_TYPE_68040: - info->type = TYPE_68040; - info->address_mask = 0xffffffff; - break; - case M68K_CPU_TYPE_68060: - info->type = TYPE_68060; - info->address_mask = 0xffffffff; - break; - default: - info->address_mask = 0; - return; - } } /* ======================================================================== */ @@ -4370,7 +5133,7 @@ bool M68K_getInstruction(csh ud, const uint8_t *code, size_t code_len, SStream ss; #endif uint32_t sz = 0; - uint32_t cpu_type = M68K_CPU_TYPE_68000; + m68k_feature_mask features = 0; cs_struct *handle = instr->csh; m68k_info *info = (m68k_info *)handle->printer_info; @@ -4393,21 +5156,12 @@ bool M68K_getInstruction(csh ud, const uint8_t *code, size_t code_len, info->code_len = code_len; info->baseAddress = address; - if (handle->mode & CS_MODE_M68K_010) { - cpu_type = M68K_CPU_TYPE_68010; - } else if (handle->mode & CS_MODE_M68K_020) { - cpu_type = M68K_CPU_TYPE_68020; - } else if (handle->mode & CS_MODE_M68K_030) { - cpu_type = M68K_CPU_TYPE_68030; - } else if (handle->mode & CS_MODE_M68K_040) { - cpu_type = M68K_CPU_TYPE_68040; - } else if (handle->mode & CS_MODE_M68K_060) { - cpu_type = M68K_CPU_TYPE_68060; - } else if (handle->mode & CS_MODE_M68K_CPU32) { - cpu_type = M68K_CPU_TYPE_CPU32; - } + features = + (m68k_feature_mask)(handle->mode & CS_MODE_M68K_FEATURE_MASK); + if (!features) + features = CS_MODE_M68K_000; - m68k_setup_internals(info, instr, (uint32_t)address, cpu_type); + m68k_setup_internals(info, instr, (uint32_t)address, features); sz = m68k_disassemble(info, address); if (sz == 0) { diff --git a/arch/M68K/M68KDisassembler.h b/arch/M68K/M68KDisassembler.h index 158e85329..42db88955 100644 --- a/arch/M68K/M68KDisassembler.h +++ b/arch/M68K/M68KDisassembler.h @@ -44,31 +44,28 @@ #define BIT_1E(A) ((A) & 0x40000000) #define BIT_1F(A) ((A) & 0x80000000) -/* These are the CPU types understood by this disassembler */ -#define TYPE_68000 1 -#define TYPE_68010 2 -#define TYPE_68020 4 -#define TYPE_68030 8 -#define TYPE_68040 16 -#define TYPE_68060 32 -#define TYPE_CPU32 64 +/* These are the M68K feature masks understood by this disassembler. */ +#define M68000_ONLY CS_MODE_M68K_000 -#define M68000_ONLY TYPE_68000 - -#define M68010_ONLY TYPE_68010 -#define M68010_LESS (TYPE_68000 | TYPE_68010) +#define M68010_ONLY CS_MODE_M68K_010 +#define M68010_LESS (CS_MODE_M68K_000 | CS_MODE_M68K_010) #define M68010_PLUS \ - (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68060) + (CS_MODE_M68K_010 | CS_MODE_M68K_020 | CS_MODE_M68K_030 | \ + CS_MODE_M68K_040 | CS_MODE_M68K_060) -#define M68020_ONLY TYPE_68020 -#define M68020_LESS (TYPE_68010 | TYPE_68020) -#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68060) +#define M68020_ONLY CS_MODE_M68K_020 +#define M68020_LESS (CS_MODE_M68K_010 | CS_MODE_M68K_020) +#define M68020_PLUS \ + (CS_MODE_M68K_020 | CS_MODE_M68K_030 | CS_MODE_M68K_040 | \ + CS_MODE_M68K_060) -#define M68030_ONLY TYPE_68030 -#define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030) -#define M68030_PLUS (TYPE_68030 | TYPE_68040 | TYPE_68060) +#define M68030_ONLY CS_MODE_M68K_030 +#define M68030_LESS (CS_MODE_M68K_010 | CS_MODE_M68K_020 | CS_MODE_M68K_030) +#define M68030_PLUS (CS_MODE_M68K_030 | CS_MODE_M68K_040 | CS_MODE_M68K_060) -#define M68040_PLUS (TYPE_68040 | TYPE_68060) +#define M68040_PLUS (CS_MODE_M68K_040 | CS_MODE_M68K_060) + +typedef uint32_t m68k_feature_mask; /* Extension word formats */ #define EXT_8BIT_DISPLACEMENT(A) ((A) & 0xff) @@ -123,6 +120,10 @@ /* 6-bit coprocessor condition (bits 5:0 of IR). */ #define M68K_IR_CONDITION(info) ((info)->ir & 0x3f) +/* 4-bit condition selector used by Bcc/DBcc/Scc/TRAPcc. */ +#define M68K_IR_CONDITION_NIBBLE(info) (((info)->ir >> 8) & 0xf) +#define M68K_CONDITION_FALSE 1 + /* cinv/cpush: select cpush(1) vs cinv(0) -- bit 5 of IR. */ #define M68K_IR_IS_CPUSH(info) (((info)->ir >> 5) & 1) @@ -187,36 +188,36 @@ #define M68K_FPOP_FSSQRT_RAW 0x01 /* 0x41 & 0x3f */ #define M68K_FPOP_FDSQRT_RAW 0x05 /* 0x45 & 0x3f */ -/* ── CPU-type guard macros ─────────────────────────────────────────── +/* ── Feature guard macros ──────────────────────────────────────────── * These reference the `info` parameter available at each call site. - * They early-return from the calling function on type mismatch. */ + * They early-return from the calling function on guard mismatch. */ -#define LIMIT_CPU_TYPES(info, ALLOWED_CPU_TYPES) \ +#define LIMIT_FEATURE(info, FEATURES) \ do { \ - if (!(info->type & ALLOWED_CPU_TYPES)) { \ + if (!m68k_has_feature(info, FEATURES)) { \ d68000_invalid(info); \ return; \ } \ } while (0) -/* Like LIMIT_CPU_TYPES but also reverses the instruction word consumption, +/* Like LIMIT_FEATURE but also reverses the instruction word consumption, * so the invalid instruction produces size=0 (not decoded) instead of size=2. * Use for handlers that replace d68000_invalid in the dispatch table. */ -#define LIMIT_CPU_TYPES_UNDECODED(info, ALLOWED_CPU_TYPES) \ +#define LIMIT_FEATURE_UNDECODED(info, FEATURES) \ do { \ - if (!(info->type & ALLOWED_CPU_TYPES)) { \ + if (!m68k_has_feature(info, FEATURES)) { \ info->pc -= 2; \ d68000_invalid(info); \ return; \ } \ } while (0) -/* Like LIMIT_CPU_TYPES but also rejects CPU32. CPU32 shares TYPE_68020 but - * lacks some 68020 instructions (CAS, CAS2, CHK.L, PACK, UNPK). */ -#define LIMIT_CPU_TYPES_NOT_CPU32(info, ALLOWED_CPU_TYPES) \ +/* Like LIMIT_FEATURE but also rejects a feature subset. CPU32 implies 68020 + * but lacks some 68020 instructions (CAS, CAS2, CHK.L, PACK, UNPK). */ +#define LIMIT_FEATURE_EXCLUDING(info, FEATURES, EXCLUDED_FEATURES) \ do { \ - if (!(info->type & (ALLOWED_CPU_TYPES)) || \ - (info->type & TYPE_CPU32)) { \ + if (!m68k_has_feature(info, FEATURES) || \ + m68k_has_feature(info, EXCLUDED_FEATURES)) { \ d68000_invalid(info); \ return; \ } \ @@ -232,21 +233,6 @@ } \ } while (0) -/* Require CpID == MMU or CpID == FPU. - * CpID MMU is rejected on CPU32 (no PMMU). Used by cpSAVE/cpRESTORE. */ -#define REQUIRE_CPID_FPU_OR_PMMU(info) \ - do { \ - int _cpid = M68K_CPID(info); \ - if (_cpid == M68K_CPID_MMU && ((info)->type & TYPE_CPU32)) { \ - d68000_invalid(info); \ - return; \ - } \ - if (_cpid != M68K_CPID_MMU && _cpid != M68K_CPID_FPU) { \ - d68000_invalid(info); \ - return; \ - } \ - } while (0) - /* ── EA / immediate convenience aliases ───────────────────────────── * Shorthand wrappers around the sized get_ea_mode_str / get_imm_str * functions. These expand at the call site where 'info' is in scope. */ @@ -281,7 +267,7 @@ typedef struct m68k_info { MCInst *inst; unsigned int pc; /* program counter */ unsigned int ir; /* instruction register */ - unsigned int type; + m68k_feature_mask features; unsigned int address_mask; /* Address mask to simulate address lines */ cs_m68k extension; uint16_t regs_read @@ -294,6 +280,27 @@ typedef struct m68k_info { uint8_t groups_count; } m68k_info; +static inline bool m68k_has_feature(const m68k_info *info, + m68k_feature_mask features) +{ + m68k_feature_mask available = info->features; + + if (available & CS_MODE_M68K_CPU32) + available |= CS_MODE_M68K_020; + if (available & CS_MODE_M68K_CF_ISA_A_PLUS) + available |= CS_MODE_M68K_CF_ISA_A; + if (available & CS_MODE_M68K_CF_ISA_B) + available |= CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_ISA_A_PLUS; + if (available & CS_MODE_M68K_CF_ISA_C) + available |= CS_MODE_M68K_CF_ISA_A; + if (available & CS_MODE_M68K_CF_EMAC) + available |= CS_MODE_M68K_CF_MAC; + if (available & CS_MODE_M68K_CF_EMAC_B) + available |= CS_MODE_M68K_CF_EMAC | CS_MODE_M68K_CF_MAC; + + return (available & features) != 0; +} + bool M68K_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c index e1fd5d440..b419b309c 100644 --- a/arch/M68K/M68KInstPrinter.c +++ b/arch/M68K/M68KInstPrinter.c @@ -21,83 +21,101 @@ static const char s_spacing[] = " "; static const char *const s_reg_names[] = { - "invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6", - "d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6", - "a7", "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", - "fp7", "pc", "sr", "ccr", "sfc", "dfc", "usp", "vbr", - "cacr", "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0", - "dtt1", "mmusr", "urp", "srp", + "invalid", "d0", "d1", "d2", "d3", "d4", "d5", "d6", + "d7", "a0", "a1", "a2", "a3", "a4", "a5", "a6", + "a7", "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", + "fp7", "pc", "sr", "ccr", "sfc", "dfc", "usp", "vbr", + "cacr", "caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0", + "dtt1", "mmusr", "urp", "srp", - "fpcr", "fpsr", "fpiar", + "fpcr", "fpsr", "fpiar", - "tt0", "tt1", "crp", + "tt0", "tt1", "crp", "acc", "acc0", "acc1", "acc2", "acc3", + "accext01", "accext23", "macsr", "mask", }; static const char *const s_instruction_names[] = { - "invalid", "abcd", "add", "adda", "addi", "addq", - "addx", "and", "andi", "asl", "asr", "bhs", - "blo", "bhi", "bls", "bcc", "bcs", "bne", - "beq", "bvc", "bvs", "bpl", "bmi", "bge", - "blt", "bgt", "ble", "bra", "bsr", "bchg", - "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", - "bfextu", "bfffo", "bfins", "bfset", "bftst", "bkpt", - "callm", "cas", "cas2", "chk", "chk2", "clr", - "cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl", - "cinvp", "cinva", "cpushl", "cpushp", "cpusha", "dbt", - "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", - "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", - "dblt", "dbgt", "dble", "dbra", "divs", "divsl", - "divu", "divul", "eor", "eori", "exg", "ext", - "extb", "fabs", "fsabs", "fdabs", "facos", "fadd", - "fsadd", "fdadd", "fasin", "fatan", "fatanh", "fbf", - "fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl", - "fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult", - "fbule", "fbne", "fbt", "fbsf", "fbseq", "fbgt", - "fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle", - "fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne", - "fbst", "fcmp", "fcos", "fcosh", "fdbf", "fdbeq", - "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", - "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", - "fdbne", "fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", - "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", - "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne", "fdbst", - "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", - "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", - "flognp1", "fmod", "fmove", "fsmove", "fdmove", "fmovecr", - "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", - "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", - "fsgldiv", "fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", - "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", - "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq", - "fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", - "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", - "fsgl", "fsgle", "fsngle", "fsngl", "fsnle", "fsnlt", - "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", - "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", - "ftrapogt", "ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", - "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", - "ftrapne", "ftrapt", "ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", - "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", - "ftrapnle", "ftrapnlt", "ftrapnge", "ftrapngt", "ftrapsne", "ftrapst", - "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", - "lea", "link", "lpstop", "lsl", "lsr", "move", - "movea", "movec", "movem", "movep", "moveq", "moves", - "move16", "muls", "mulu", "nbcd", "neg", "negx", - "nop", "not", "or", "ori", "pack", "pea", - "pflush", "pflusha", "pflushan", "pflushn", "ploadr", "ploadw", - "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", - "pulse", "rems", "remu", "reset", "rol", "ror", - "roxl", "roxr", "rtd", "rte", "rtm", "rtr", - "rts", "sbcd", "st", "sf", "shi", "sls", - "scc", "shs", "scs", "slo", "sne", "seq", - "svc", "svs", "spl", "smi", "sge", "slt", - "sgt", "sle", "stop", "sub", "suba", "subi", - "subq", "subx", "swap", "tas", "trap", "trapv", - "trapt", "trapf", "traphi", "trapls", "trapcc", "traphs", - "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", - "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", - "tst", "unlk", "unpk", "bgnd", "tbls", "tblu", - "tblsn", "tblun", + "invalid", "abcd", "add", "adda", "addi", + "addq", "addx", "and", "andi", "asl", + "asr", "bhs", "blo", "bhi", "bls", + "bcc", "bcs", "bne", "beq", "bvc", + "bvs", "bpl", "bmi", "bge", "blt", + "bgt", "ble", "bra", "bsr", "bchg", + "bclr", "bset", "btst", "bitrev", "byterev", + "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", + "bfins", "bfset", "bftst", "bkpt", "callm", + "cas", "cas2", "chk", "chk2", "clr", + "cmp", "cmpa", "cmpi", "cmpm", "cmp2", + "cinvl", "cinvp", "cinva", "cpushl", "cpushp", + "cpusha", "dbt", "dbf", "dbhi", "dbls", + "dbcc", "dbcs", "dbne", "dbeq", "dbvc", + "dbvs", "dbpl", "dbmi", "dbge", "dblt", + "dbgt", "dble", "dbra", "divs", "divsl", + "divu", "divul", "eor", "eori", "exg", + "ext", "extb", "ff1", "fabs", "fsabs", + "fdabs", "facos", "fadd", "fsadd", "fdadd", + "fasin", "fatan", "fatanh", "fbf", "fbeq", + "fbogt", "fboge", "fbolt", "fbole", "fbogl", + "fbor", "fbun", "fbueq", "fbugt", "fbuge", + "fbult", "fbule", "fbne", "fbt", "fbsf", + "fbseq", "fbgt", "fbge", "fblt", "fble", + "fbgl", "fbgle", "fbngle", "fbngl", "fbnle", + "fbnlt", "fbnge", "fbngt", "fbsne", "fbst", + "fcmp", "fcos", "fcosh", "fdbf", "fdbeq", + "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", + "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", + "fdbult", "fdbule", "fdbne", "fdbt", "fdbsf", + "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", + "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", + "fdbnlt", "fdbnge", "fdbngt", "fdbsne", "fdbst", + "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", + "fgetexp", "fgetman", "fint", "fintrz", "flog10", + "flog2", "flogn", "flognp1", "fmod", "fmove", + "fsmove", "fdmove", "fmovecr", "fmovem", "fmul", + "fsmul", "fdmul", "fneg", "fsneg", "fdneg", + "fnop", "frem", "frestore", "fsave", "fscale", + "fsgldiv", "fsglmul", "fsin", "fsincos", "fsinh", + "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", + "fsogt", "fsoge", "fsolt", "fsole", "fsogl", + "fsor", "fsun", "fsueq", "fsugt", "fsuge", + "fsult", "fsule", "fsne", "fst", "fssf", + "fsseq", "fsgt", "fsge", "fslt", "fsle", + "fsgl", "fsgle", "fsngle", "fsngl", "fsnle", + "fsnlt", "fsnge", "fsngt", "fssne", "fsst", + "fsub", "fssub", "fdsub", "ftan", "ftanh", + "ftentox", "ftrapf", "ftrapeq", "ftrapogt", "ftrapoge", + "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", + "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", + "ftrapne", "ftrapt", "ftrapsf", "ftrapseq", "ftrapgt", + "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", + "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge", + "ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", + "halt", "illegal", "intouch", "jmp", "jsr", + "lea", "link", "lpstop", "lsl", "lsr", + "mac", "move", "movea", "movec", "movem", + "movep", "moveq", "moves", "move16", "mov3q", + "movclr", "msac", "muls", "mulu", "mvs", + "mvz", "nbcd", "neg", "negx", "nop", + "not", "or", "ori", "pack", "pea", + "pflush", "pflusha", "pflushan", "pflushn", "ploadr", + "ploadw", "plpar", "plpaw", "pmove", "pmovefd", + "ptestr", "ptestw", "pulse", "rems", "remu", + "reset", "rol", "ror", "roxl", "roxr", + "rtd", "rte", "rtm", "rtr", "rts", + "sats", "sbcd", "st", "sf", "shi", + "sls", "scc", "shs", "scs", "slo", + "sne", "seq", "svc", "svs", "spl", + "smi", "sge", "slt", "sgt", "sle", + "stop", "strldsr", "sub", "suba", "subi", + "subq", "subx", "swap", "tas", "trap", + "trapv", "trapt", "trapf", "traphi", "trapls", + "trapcc", "traphs", "trapcs", "traplo", "trapne", + "trapeq", "trapvc", "trapvs", "trappl", "trapmi", + "trapge", "traplt", "trapgt", "traple", "tst", + "unlk", "unpk", "wddata", "wdebug", "bgnd", + "tbls", "tblu", "tblsn", "tblun", "cp0bcbusy", + "cp0ld", "cp0nop", "cp0st", "cp1bcbusy", "cp1ld", + "cp1nop", "cp1st", "tpf", }; #endif @@ -154,6 +172,15 @@ static void registerPair(SStream *O, const cs_m68k_op *op) s_reg_names[op->reg_pair.reg_1]); } +static void printRegisterName(SStream *O, const cs_m68k_op *op) +{ + SStream_concat(O, "%s", getRegName(op->reg)); + if (op->flags & M68K_OP_FLAG_REG_LOWER) + SStream_concat0(O, "l"); + else if (op->flags & M68K_OP_FLAG_REG_UPPER) + SStream_concat0(O, "u"); +} + static void printScaleFactor(SStream *O, uint8_t scale, int threshold) { if (scale > threshold) @@ -221,26 +248,29 @@ static void printIndex8BitDisp(SStream *O, unsigned int pc, static void printRegAddrMode(SStream *O, unsigned int pc, const cs_m68k_op *op) { + m68k_reg base_reg = op->type == M68K_OP_MEM ? op->mem.base_reg : + op->reg; + switch (op->address_mode) { case M68K_AM_REG_DIRECT_DATA: - SStream_concat(O, "d%" PRId32, (op->reg - M68K_REG_D0)); + printRegisterName(O, op); break; case M68K_AM_REG_DIRECT_ADDR: - SStream_concat(O, "a%" PRId32, (op->reg - M68K_REG_A0)); + printRegisterName(O, op); break; case M68K_AM_REGI_ADDR: - SStream_concat(O, "(a%" PRId32 ")", (op->reg - M68K_REG_A0)); + SStream_concat(O, "(a%" PRId32 ")", (base_reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_POST_INC: - SStream_concat(O, "(a%" PRId32 ")+", (op->reg - M68K_REG_A0)); + SStream_concat(O, "(a%" PRId32 ")+", (base_reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_PRE_DEC: - SStream_concat(O, "-(a%" PRId32 ")", (op->reg - M68K_REG_A0)); + SStream_concat(O, "-(a%" PRId32 ")", (base_reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "%s$%" PRIx16 "(a%" PRId32 ")", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), - (op->mem.base_reg - M68K_REG_A0)); + (base_reg - M68K_REG_A0)); break; case M68K_AM_PCI_DISP: SStream_concat(O, "$%" PRIx32 "(pc)", pc + 2 + op->mem.disp); @@ -344,7 +374,13 @@ static void printAddressingMode(SStream *O, unsigned int pc, registerPair(O, op); break; case M68K_OP_REG: - SStream_concat(O, "%s", s_reg_names[op->reg]); + printRegisterName(O, op); + break; + case M68K_OP_SHIFT: + if (op->flags & M68K_OP_FLAG_SHIFT_LEFT) + SStream_concat0(O, "<<"); + else if (op->flags & M68K_OP_FLAG_SHIFT_RIGHT) + SStream_concat0(O, ">>"); break; default: break; @@ -361,10 +397,10 @@ static void printAddressingMode(SStream *O, unsigned int pc, printRegAddrMode(O, pc, op); break; case M68K_AM_ABSOLUTE_DATA_SHORT: - SStream_concat(O, "$%" PRIx32 ".w", (uint32_t)op->imm); + SStream_concat(O, "$%" PRIx32 ".w", (uint32_t)op->mem.address); break; case M68K_AM_ABSOLUTE_DATA_LONG: - SStream_concat(O, "$%" PRIx64 ".l", (uint64_t)op->imm); + SStream_concat(O, "$%" PRIx64 ".l", (uint64_t)op->mem.address); break; case M68K_AM_IMMEDIATE: printImmediate(O, inst, op); @@ -390,6 +426,8 @@ static void printAddressingMode(SStream *O, unsigned int pc, } printBitfield(O, op); + if (op->flags & M68K_OP_FLAG_MEM_UPDATE) + SStream_concat0(O, "&"); } static void printCAS2(SStream *O, unsigned int pc, const cs_m68k *ext) @@ -420,6 +458,7 @@ static void printCacheOp(SStream *O, unsigned int pc, const cs_m68k *ext) printAddressingMode(O, pc, ext, &ext->operands[i]); } } + #endif static void printOpSize(SStream *O, const cs_m68k *ext) diff --git a/arch/M68K/M68KInstructionTable.inc b/arch/M68K/M68KInstructionTable.inc index d289edb59..c06bfd0fd 100644 --- a/arch/M68K/M68KInstructionTable.inc +++ b/arch/M68K/M68KInstructionTable.inc @@ -192,14 +192,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, + { dcf_bitrev, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -704,14 +704,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, + { dcf_byterev, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -1216,14 +1216,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, + { dcf_ff1, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -16615,7 +16615,7 @@ static const instruction_struct g_instruction_table[] = { { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, - { d68000_move_fr_sr, 0x0, 0x0 }, + { dcf_strldsr, 0xffff, 0x46fc }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, { d68000_move_fr_sr, 0x0, 0x0 }, @@ -19584,14 +19584,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, + { dcf_sats, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -28928,259 +28928,259 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -29440,6 +29440,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -29448,251 +29456,243 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -29952,6 +29952,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -29960,251 +29968,243 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -30464,6 +30464,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -30472,251 +30480,243 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -30976,6 +30976,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -30984,251 +30992,243 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -31488,6 +31488,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -31496,259 +31504,246 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, @@ -31991,254 +31986,28 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_moveq, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -32247,12 +32016,243 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -32512,6 +32512,14 @@ static const instruction_struct g_instruction_table[] = { { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, { d68000_moveq, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -32520,251 +32528,243 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, + { dcf_mvs_8, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, - { d68000_invalid, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { dcf_mvs_16, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { dcf_mvz_8, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, + { dcf_mvz_16, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, @@ -40960,4102 +40960,4102 @@ static const instruction_struct g_instruction_table[] = { { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, { d68000_invalid, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - { d68000_1010, 0x0, 0x0 }, - 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dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_reg_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_acc, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_move_acc_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_accn, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_accn, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_reg_accn, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_move_acc_acc, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_accn, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_move_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_movclr_accn_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_move_reg_macsr, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_macsr, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_move_macsr_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_macsr_ccr, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_accext, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_move_reg_mask, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_mask, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_move_mask_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_move_reg_accext, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_imm_accext, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { dcf_mov3q, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_move_accext_reg, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { dcf_mac_arith, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, + { d68000_invalid, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, { d68000_cmp_8, 0x0, 0x0 }, @@ -61565,9 +61565,9 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -61696,22 +61696,22 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -61720,14 +61720,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -61754,28 +61754,28 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -61792,14 +61792,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -61821,137 +61821,137 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, @@ -62077,9 +62077,9 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -62208,22 +62208,22 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -62232,14 +62232,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -62266,28 +62266,28 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -62304,14 +62304,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -62333,137 +62333,137 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, { d68040_cinv, 0x0, 0x0 }, @@ -62504,14 +62504,14 @@ static const instruction_struct g_instruction_table[] = { { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, - { d68040_cpush, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, + { dcf_intouch, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, { d68040_cpush, 0x0, 0x0 }, @@ -62778,20 +62778,20 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68040_ptest, 0x0, 0x0 }, { d68040_ptest, 0x0, 0x0 }, { d68040_ptest, 0x0, 0x0 }, @@ -62816,14 +62816,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68040_ptest_or_cprestore, 0x0, 0x0 }, { d68040_ptest_or_cprestore, 0x0, 0x0 }, { d68040_ptest_or_cprestore, 0x0, 0x0 }, @@ -62845,17 +62845,17 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, @@ -62864,62 +62864,62 @@ static const instruction_struct g_instruction_table[] = { { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, @@ -62928,54 +62928,54 @@ static const instruction_struct g_instruction_table[] = { { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, { d68060_plpa, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, { d68040_move16_pi_al, 0x0, 0x0 }, @@ -63101,9 +63101,9 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -63232,22 +63232,22 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -63256,14 +63256,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -63290,28 +63290,28 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -63328,14 +63328,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -63357,137 +63357,137 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68060_lpstop, 0x0, 0x0 }, { d68cpu32_tbl, 0x0, 0x0 }, { d68cpu32_tbl, 0x0, 0x0 }, @@ -63613,9 +63613,9 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -63744,22 +63744,22 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -63768,14 +63768,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -63802,28 +63802,28 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -63840,14 +63840,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -63869,137 +63869,137 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, @@ -64125,9 +64125,9 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -64256,262 +64256,310 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_wddata, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_wdebug, 0xffff, 0x3 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, @@ -64528,102 +64576,54 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, @@ -64637,57 +64637,57 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -64704,6 +64704,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, + { dcf_cp0bcbusy, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, @@ -64760,46 +64768,54 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -64810,44 +64826,60 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -64861,169 +64893,185 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, @@ -65040,102 +65088,54 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpgen, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpdbcc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, - { d68020_cpscc, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, { d68020_cpscc, 0x0, 0x0 }, @@ -65149,57 +65149,57 @@ static const instruction_struct g_instruction_table[] = { { d68020_cptrapcc_16, 0x0, 0x0 }, { d68020_cptrapcc_32, 0x0, 0x0 }, { d68020_cptrapcc_0, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, - { d68020_cpbcc_16, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, @@ -65216,6 +65216,14 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, { d68020_cpbcc_16, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, + { dcf_cp1bcbusy, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, @@ -65272,46 +65280,54 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68020_cpbcc_32, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, @@ -65322,44 +65338,60 @@ static const instruction_struct g_instruction_table[] = { { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68020_cpsave, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, @@ -65373,168 +65405,136 @@ static const instruction_struct g_instruction_table[] = { { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68020_cprestore, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 }, - { d68000_1111, 0x0, 0x0 } + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_coproc_ldst, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 }, + { dcf_1111, 0x0, 0x0 } }; diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 608b6e3fa..8de658846 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -88,6 +88,24 @@ __all__ = [ "CS_MODE_M68K_040", "CS_MODE_M68K_060", "CS_MODE_M68K_CPU32", + "CS_MODE_M68K_CF_ISA_A", + "CS_MODE_M68K_CF_ISA_A_PLUS", + "CS_MODE_M68K_CF_ISA_B", + "CS_MODE_M68K_CF_ISA_C", + "CS_MODE_M68K_CF_USP", + "CS_MODE_M68K_CF_DIV", + "CS_MODE_M68K_CF_MAC", + "CS_MODE_M68K_CF_EMAC", + "CS_MODE_M68K_CF_EMAC_B", + "CS_MODE_M68K_CF_FPU", + "CS_MODE_M68K_COLDFIRE", + "CS_MODE_M68K_CFV1", + "CS_MODE_M68K_CFV2", + "CS_MODE_M68K_CFV3", + "CS_MODE_M68K_CFV4", + "CS_MODE_M68K_CFV4E", + "CS_MODE_M68K_CFV5", + "CS_MODE_M68K_FEATURE_MASK", "CS_MODE_M680X_6301", "CS_MODE_M680X_6309", "CS_MODE_M680X_6800", @@ -358,6 +376,56 @@ CS_MODE_M68K_030 = 1 << 4 # M68K 68030 mode CS_MODE_M68K_040 = 1 << 5 # M68K 68040 mode CS_MODE_M68K_060 = 1 << 6 # M68K 68060 mode CS_MODE_M68K_CPU32 = 1 << 7 +CS_MODE_M68K_CF_ISA_A = 1 << 8 +CS_MODE_M68K_CF_ISA_A_PLUS = 1 << 9 +CS_MODE_M68K_CF_ISA_B = 1 << 10 +CS_MODE_M68K_CF_ISA_C = 1 << 11 +CS_MODE_M68K_CF_USP = 1 << 12 +CS_MODE_M68K_CF_DIV = 1 << 13 +CS_MODE_M68K_CF_MAC = 1 << 14 +CS_MODE_M68K_CF_EMAC = 1 << 15 +CS_MODE_M68K_CF_EMAC_B = 1 << 16 +CS_MODE_M68K_CF_FPU = 1 << 17 +CS_MODE_M68K_COLDFIRE = ( + CS_MODE_M68K_CF_ISA_A + | CS_MODE_M68K_CF_ISA_A_PLUS + | CS_MODE_M68K_CF_ISA_B + | CS_MODE_M68K_CF_ISA_C + | CS_MODE_M68K_CF_USP + | CS_MODE_M68K_CF_DIV + | CS_MODE_M68K_CF_MAC + | CS_MODE_M68K_CF_EMAC + | CS_MODE_M68K_CF_EMAC_B + | CS_MODE_M68K_CF_FPU +) +CS_MODE_M68K_CFV1 = CS_MODE_M68K_CF_ISA_C | CS_MODE_M68K_CF_USP +CS_MODE_M68K_CFV2 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV +CS_MODE_M68K_CFV3 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV +CS_MODE_M68K_CFV4 = CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_DIV +CS_MODE_M68K_CFV4E = ( + CS_MODE_M68K_CF_ISA_B + | CS_MODE_M68K_CF_DIV + | CS_MODE_M68K_CF_USP + | CS_MODE_M68K_CF_EMAC + | CS_MODE_M68K_CF_FPU +) +CS_MODE_M68K_CFV5 = ( + CS_MODE_M68K_CF_ISA_C + | CS_MODE_M68K_CF_USP + | CS_MODE_M68K_CF_DIV + | CS_MODE_M68K_CF_EMAC + | CS_MODE_M68K_CF_EMAC_B +) +CS_MODE_M68K_FEATURE_MASK = ( + CS_MODE_M68K_000 + | CS_MODE_M68K_010 + | CS_MODE_M68K_020 + | CS_MODE_M68K_030 + | CS_MODE_M68K_040 + | CS_MODE_M68K_060 + | CS_MODE_M68K_CPU32 + | CS_MODE_M68K_COLDFIRE +) CS_MODE_BIG_ENDIAN = 1 << 31 # big-endian mode CS_MODE_MIPS16 = CS_MODE_16 # Generic mips16 CS_MODE_MIPS32 = CS_MODE_32 # Generic mips32 @@ -634,7 +702,7 @@ elif sys.platform in ("win32", "cygwin"): _lib = "capstone.dll" else: _lib = "libcapstone.so" - mode = getattr(os, 'RTLD_DEEPBIND', 0) + mode = getattr(os, "RTLD_DEEPBIND", 0) _found = False @@ -647,10 +715,7 @@ def _load_lib(path): # if we're on linux, try again with .so.5 extension if lib_file.endswith(".so"): if os.path.exists(lib_file + ".{}".format(CS_VERSION_MAJOR)): - return ctypes.CDLL( - lib_file + ".{}".format(CS_VERSION_MAJOR), - mode=mode - ) + return ctypes.CDLL(lib_file + ".{}".format(CS_VERSION_MAJOR), mode=mode) return None diff --git a/bindings/python/capstone/m68k.py b/bindings/python/capstone/m68k.py index f54884f24..86f4e6501 100644 --- a/bindings/python/capstone/m68k.py +++ b/bindings/python/capstone/m68k.py @@ -4,54 +4,61 @@ import ctypes from . import copy_ctypes_list from .m68k_const import * + # define the API class M68KOpMem(ctypes.Structure): _fields_ = ( - ('base_reg', ctypes.c_uint), - ('index_reg', ctypes.c_uint), - ('in_base_reg', ctypes.c_uint), - ('in_disp', ctypes.c_int), - ('out_disp', ctypes.c_int), - ('disp', ctypes.c_short), - ('scale', ctypes.c_ubyte), - ('bitfield', ctypes.c_ubyte), - ('width', ctypes.c_ubyte), - ('offset', ctypes.c_ubyte), - ('index_size', ctypes.c_ubyte), - ('in_disp_size', ctypes.c_ubyte), - ('out_disp_size', ctypes.c_ubyte), - ('disp_size', ctypes.c_ubyte), + ("base_reg", ctypes.c_uint), + ("index_reg", ctypes.c_uint), + ("in_base_reg", ctypes.c_uint), + ("in_disp", ctypes.c_int), + ("out_disp", ctypes.c_int), + ("disp", ctypes.c_short), + ("scale", ctypes.c_ubyte), + ("bitfield", ctypes.c_ubyte), + ("width", ctypes.c_ubyte), + ("offset", ctypes.c_ubyte), + ("index_size", ctypes.c_ubyte), + ("in_disp_size", ctypes.c_ubyte), + ("out_disp_size", ctypes.c_ubyte), + ("disp_size", ctypes.c_ubyte), + ("address", ctypes.c_uint64), ) + class M68KOpRegPair(ctypes.Structure): _fields_ = ( - ('reg_0', ctypes.c_uint), - ('reg_1', ctypes.c_uint), + ("reg_0", ctypes.c_uint), + ("reg_1", ctypes.c_uint), ) + class M68KOpValue(ctypes.Union): _fields_ = ( - ('imm', ctypes.c_int64), - ('dimm', ctypes.c_double), - ('simm', ctypes.c_float), - ('reg', ctypes.c_uint), - ('reg_pair', M68KOpRegPair), + ("imm", ctypes.c_int64), + ("dimm", ctypes.c_double), + ("simm", ctypes.c_float), + ("reg", ctypes.c_uint), + ("reg_pair", M68KOpRegPair), ) + class M68KOpBrDisp(ctypes.Structure): _fields_ = ( - ('disp', ctypes.c_int), - ('disp_size', ctypes.c_ubyte), + ("disp", ctypes.c_int), + ("disp_size", ctypes.c_ubyte), ) - + + class M68KOp(ctypes.Structure): _fields_ = ( - ('value', M68KOpValue), - ('mem', M68KOpMem), - ('br_disp', M68KOpBrDisp), - ('register_bits', ctypes.c_uint), - ('type', ctypes.c_uint), - ('address_mode', ctypes.c_uint), + ("value", M68KOpValue), + ("mem", M68KOpMem), + ("br_disp", M68KOpBrDisp), + ("register_bits", ctypes.c_uint), + ("type", ctypes.c_uint), + ("address_mode", ctypes.c_uint), + ("flags", ctypes.c_ubyte), ) @property @@ -69,7 +76,7 @@ class M68KOp(ctypes.Structure): @property def reg(self): return self.value.reg - + @property def reg_pair(self): return self.value.reg_pair @@ -82,22 +89,25 @@ class M68KOp(ctypes.Structure): def register_bits(self): return self.register_bits + class M68KOpSize(ctypes.Structure): _fields_ = ( - ('type', ctypes.c_uint), - ('size', ctypes.c_uint), + ("type", ctypes.c_uint), + ("size", ctypes.c_uint), ) def get(a): return copy_ctypes_list(type, size) + class CsM68K(ctypes.Structure): - M68K_OPERAND_COUNT = 4 + M68K_OPERAND_COUNT = 6 _fields_ = ( - ('operands', M68KOp * M68K_OPERAND_COUNT), - ('op_size', M68KOpSize), - ('op_count', ctypes.c_uint8), + ("operands", M68KOp * M68K_OPERAND_COUNT), + ("op_size", M68KOpSize), + ("op_count", ctypes.c_uint8), ) + def get_arch_info(a): - return (copy_ctypes_list(a.operands[:a.op_count]), a.op_size) + return (copy_ctypes_list(a.operands[: a.op_count]), a.op_size) diff --git a/bindings/python/capstone/m68k_const.py b/bindings/python/capstone/m68k_const.py index 7d2d6794a..309764ea3 100644 --- a/bindings/python/capstone/m68k_const.py +++ b/bindings/python/capstone/m68k_const.py @@ -1,6 +1,19 @@ -from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX +from . import ( + CS_OP_INVALID, + CS_OP_REG, + CS_OP_IMM, + CS_OP_FP, + CS_OP_PRED, + CS_OP_SPECIAL, + CS_OP_MEM, + CS_OP_MEM_REG, + CS_OP_MEM_IMM, + UINT16_MAX, + UINT8_MAX, +) + # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py] -M68K_OPERAND_COUNT = 4 +M68K_OPERAND_COUNT = 6 M68K_REG_INVALID = 0 M68K_REG_D0 = 1 @@ -49,7 +62,19 @@ M68K_REG_SRP = 43 M68K_REG_FPCR = 44 M68K_REG_FPSR = 45 M68K_REG_FPIAR = 46 -M68K_REG_ENDING = 47 +M68K_REG_TT0 = 47 +M68K_REG_TT1 = 48 +M68K_REG_CRP = 49 +M68K_REG_ACC = 50 +M68K_REG_ACC0 = 51 +M68K_REG_ACC1 = 52 +M68K_REG_ACC2 = 53 +M68K_REG_ACC3 = 54 +M68K_REG_ACCEXT01 = 55 +M68K_REG_ACCEXT23 = 56 +M68K_REG_MACSR = 57 +M68K_REG_MASK = 58 +M68K_REG_ENDING = 59 M68K_AM_NONE = 0 M68K_AM_REG_DIRECT_DATA = 1 @@ -74,12 +99,20 @@ M68K_AM_BRANCH_DISPLACEMENT = 19 M68K_OP_INVALID = CS_OP_INVALID M68K_OP_REG = CS_OP_REG M68K_OP_IMM = CS_OP_IMM -M68K_OP_FP_SINGLE = CS_OP_SPECIAL+0 -M68K_OP_FP_DOUBLE = CS_OP_SPECIAL+1 -M68K_OP_REG_BITS = CS_OP_SPECIAL+2 -M68K_OP_REG_PAIR = CS_OP_SPECIAL+3 -M68K_OP_BR_DISP = CS_OP_SPECIAL+4 +M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0 +M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1 +M68K_OP_REG_BITS = CS_OP_SPECIAL + 2 +M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3 +M68K_OP_BR_DISP = CS_OP_SPECIAL + 4 +M68K_OP_SHIFT = CS_OP_SPECIAL + 5 M68K_OP_MEM = CS_OP_MEM +M68K_OP_FLAG_NONE = 0 +M68K_OP_FLAG_REG_LOWER = 1 +M68K_OP_FLAG_REG_UPPER = 2 +M68K_OP_FLAG_SHIFT_LEFT = 4 +M68K_OP_FLAG_SHIFT_RIGHT = 8 +M68K_OP_FLAG_MEM_UPDATE = 16 +M68K_BF_REG_FLAG = 0x80 M68K_OP_BR_DISP_SIZE_INVALID = 0 M68K_OP_BR_DISP_SIZE_BYTE = 1 @@ -133,349 +166,377 @@ M68K_INS_BCHG = 29 M68K_INS_BCLR = 30 M68K_INS_BSET = 31 M68K_INS_BTST = 32 -M68K_INS_BFCHG = 33 -M68K_INS_BFCLR = 34 -M68K_INS_BFEXTS = 35 -M68K_INS_BFEXTU = 36 -M68K_INS_BFFFO = 37 -M68K_INS_BFINS = 38 -M68K_INS_BFSET = 39 -M68K_INS_BFTST = 40 -M68K_INS_BKPT = 41 -M68K_INS_CALLM = 42 -M68K_INS_CAS = 43 -M68K_INS_CAS2 = 44 -M68K_INS_CHK = 45 -M68K_INS_CHK2 = 46 -M68K_INS_CLR = 47 -M68K_INS_CMP = 48 -M68K_INS_CMPA = 49 -M68K_INS_CMPI = 50 -M68K_INS_CMPM = 51 -M68K_INS_CMP2 = 52 -M68K_INS_CINVL = 53 -M68K_INS_CINVP = 54 -M68K_INS_CINVA = 55 -M68K_INS_CPUSHL = 56 -M68K_INS_CPUSHP = 57 -M68K_INS_CPUSHA = 58 -M68K_INS_DBT = 59 -M68K_INS_DBF = 60 -M68K_INS_DBHI = 61 -M68K_INS_DBLS = 62 -M68K_INS_DBCC = 63 -M68K_INS_DBCS = 64 -M68K_INS_DBNE = 65 -M68K_INS_DBEQ = 66 -M68K_INS_DBVC = 67 -M68K_INS_DBVS = 68 -M68K_INS_DBPL = 69 -M68K_INS_DBMI = 70 -M68K_INS_DBGE = 71 -M68K_INS_DBLT = 72 -M68K_INS_DBGT = 73 -M68K_INS_DBLE = 74 -M68K_INS_DBRA = 75 -M68K_INS_DIVS = 76 -M68K_INS_DIVSL = 77 -M68K_INS_DIVU = 78 -M68K_INS_DIVUL = 79 -M68K_INS_EOR = 80 -M68K_INS_EORI = 81 -M68K_INS_EXG = 82 -M68K_INS_EXT = 83 -M68K_INS_EXTB = 84 -M68K_INS_FABS = 85 -M68K_INS_FSABS = 86 -M68K_INS_FDABS = 87 -M68K_INS_FACOS = 88 -M68K_INS_FADD = 89 -M68K_INS_FSADD = 90 -M68K_INS_FDADD = 91 -M68K_INS_FASIN = 92 -M68K_INS_FATAN = 93 -M68K_INS_FATANH = 94 -M68K_INS_FBF = 95 -M68K_INS_FBEQ = 96 -M68K_INS_FBOGT = 97 -M68K_INS_FBOGE = 98 -M68K_INS_FBOLT = 99 -M68K_INS_FBOLE = 100 -M68K_INS_FBOGL = 101 -M68K_INS_FBOR = 102 -M68K_INS_FBUN = 103 -M68K_INS_FBUEQ = 104 -M68K_INS_FBUGT = 105 -M68K_INS_FBUGE = 106 -M68K_INS_FBULT = 107 -M68K_INS_FBULE = 108 -M68K_INS_FBNE = 109 -M68K_INS_FBT = 110 -M68K_INS_FBSF = 111 -M68K_INS_FBSEQ = 112 -M68K_INS_FBGT = 113 -M68K_INS_FBGE = 114 -M68K_INS_FBLT = 115 -M68K_INS_FBLE = 116 -M68K_INS_FBGL = 117 -M68K_INS_FBGLE = 118 -M68K_INS_FBNGLE = 119 -M68K_INS_FBNGL = 120 -M68K_INS_FBNLE = 121 -M68K_INS_FBNLT = 122 -M68K_INS_FBNGE = 123 -M68K_INS_FBNGT = 124 -M68K_INS_FBSNE = 125 -M68K_INS_FBST = 126 -M68K_INS_FCMP = 127 -M68K_INS_FCOS = 128 -M68K_INS_FCOSH = 129 -M68K_INS_FDBF = 130 -M68K_INS_FDBEQ = 131 -M68K_INS_FDBOGT = 132 -M68K_INS_FDBOGE = 133 -M68K_INS_FDBOLT = 134 -M68K_INS_FDBOLE = 135 -M68K_INS_FDBOGL = 136 -M68K_INS_FDBOR = 137 -M68K_INS_FDBUN = 138 -M68K_INS_FDBUEQ = 139 -M68K_INS_FDBUGT = 140 -M68K_INS_FDBUGE = 141 -M68K_INS_FDBULT = 142 -M68K_INS_FDBULE = 143 -M68K_INS_FDBNE = 144 -M68K_INS_FDBT = 145 -M68K_INS_FDBSF = 146 -M68K_INS_FDBSEQ = 147 -M68K_INS_FDBGT = 148 -M68K_INS_FDBGE = 149 -M68K_INS_FDBLT = 150 -M68K_INS_FDBLE = 151 -M68K_INS_FDBGL = 152 -M68K_INS_FDBGLE = 153 -M68K_INS_FDBNGLE = 154 -M68K_INS_FDBNGL = 155 -M68K_INS_FDBNLE = 156 -M68K_INS_FDBNLT = 157 -M68K_INS_FDBNGE = 158 -M68K_INS_FDBNGT = 159 -M68K_INS_FDBSNE = 160 -M68K_INS_FDBST = 161 -M68K_INS_FDIV = 162 -M68K_INS_FSDIV = 163 -M68K_INS_FDDIV = 164 -M68K_INS_FETOX = 165 -M68K_INS_FETOXM1 = 166 -M68K_INS_FGETEXP = 167 -M68K_INS_FGETMAN = 168 -M68K_INS_FINT = 169 -M68K_INS_FINTRZ = 170 -M68K_INS_FLOG10 = 171 -M68K_INS_FLOG2 = 172 -M68K_INS_FLOGN = 173 -M68K_INS_FLOGNP1 = 174 -M68K_INS_FMOD = 175 -M68K_INS_FMOVE = 176 -M68K_INS_FSMOVE = 177 -M68K_INS_FDMOVE = 178 -M68K_INS_FMOVECR = 179 -M68K_INS_FMOVEM = 180 -M68K_INS_FMUL = 181 -M68K_INS_FSMUL = 182 -M68K_INS_FDMUL = 183 -M68K_INS_FNEG = 184 -M68K_INS_FSNEG = 185 -M68K_INS_FDNEG = 186 -M68K_INS_FNOP = 187 -M68K_INS_FREM = 188 -M68K_INS_FRESTORE = 189 -M68K_INS_FSAVE = 190 -M68K_INS_FSCALE = 191 -M68K_INS_FSGLDIV = 192 -M68K_INS_FSGLMUL = 193 -M68K_INS_FSIN = 194 -M68K_INS_FSINCOS = 195 -M68K_INS_FSINH = 196 -M68K_INS_FSQRT = 197 -M68K_INS_FSSQRT = 198 -M68K_INS_FDSQRT = 199 -M68K_INS_FSF = 200 -M68K_INS_FSBEQ = 201 -M68K_INS_FSOGT = 202 -M68K_INS_FSOGE = 203 -M68K_INS_FSOLT = 204 -M68K_INS_FSOLE = 205 -M68K_INS_FSOGL = 206 -M68K_INS_FSOR = 207 -M68K_INS_FSUN = 208 -M68K_INS_FSUEQ = 209 -M68K_INS_FSUGT = 210 -M68K_INS_FSUGE = 211 -M68K_INS_FSULT = 212 -M68K_INS_FSULE = 213 -M68K_INS_FSNE = 214 -M68K_INS_FST = 215 -M68K_INS_FSSF = 216 -M68K_INS_FSSEQ = 217 -M68K_INS_FSGT = 218 -M68K_INS_FSGE = 219 -M68K_INS_FSLT = 220 -M68K_INS_FSLE = 221 -M68K_INS_FSGL = 222 -M68K_INS_FSGLE = 223 -M68K_INS_FSNGLE = 224 -M68K_INS_FSNGL = 225 -M68K_INS_FSNLE = 226 -M68K_INS_FSNLT = 227 -M68K_INS_FSNGE = 228 -M68K_INS_FSNGT = 229 -M68K_INS_FSSNE = 230 -M68K_INS_FSST = 231 -M68K_INS_FSUB = 232 -M68K_INS_FSSUB = 233 -M68K_INS_FDSUB = 234 -M68K_INS_FTAN = 235 -M68K_INS_FTANH = 236 -M68K_INS_FTENTOX = 237 -M68K_INS_FTRAPF = 238 -M68K_INS_FTRAPEQ = 239 -M68K_INS_FTRAPOGT = 240 -M68K_INS_FTRAPOGE = 241 -M68K_INS_FTRAPOLT = 242 -M68K_INS_FTRAPOLE = 243 -M68K_INS_FTRAPOGL = 244 -M68K_INS_FTRAPOR = 245 -M68K_INS_FTRAPUN = 246 -M68K_INS_FTRAPUEQ = 247 -M68K_INS_FTRAPUGT = 248 -M68K_INS_FTRAPUGE = 249 -M68K_INS_FTRAPULT = 250 -M68K_INS_FTRAPULE = 251 -M68K_INS_FTRAPNE = 252 -M68K_INS_FTRAPT = 253 -M68K_INS_FTRAPSF = 254 -M68K_INS_FTRAPSEQ = 255 -M68K_INS_FTRAPGT = 256 -M68K_INS_FTRAPGE = 257 -M68K_INS_FTRAPLT = 258 -M68K_INS_FTRAPLE = 259 -M68K_INS_FTRAPGL = 260 -M68K_INS_FTRAPGLE = 261 -M68K_INS_FTRAPNGLE = 262 -M68K_INS_FTRAPNGL = 263 -M68K_INS_FTRAPNLE = 264 -M68K_INS_FTRAPNLT = 265 -M68K_INS_FTRAPNGE = 266 -M68K_INS_FTRAPNGT = 267 -M68K_INS_FTRAPSNE = 268 -M68K_INS_FTRAPST = 269 -M68K_INS_FTST = 270 -M68K_INS_FTWOTOX = 271 -M68K_INS_HALT = 272 -M68K_INS_ILLEGAL = 273 -M68K_INS_JMP = 274 -M68K_INS_JSR = 275 -M68K_INS_LEA = 276 -M68K_INS_LINK = 277 -M68K_INS_LPSTOP = 278 -M68K_INS_LSL = 279 -M68K_INS_LSR = 280 -M68K_INS_MOVE = 281 -M68K_INS_MOVEA = 282 -M68K_INS_MOVEC = 283 -M68K_INS_MOVEM = 284 -M68K_INS_MOVEP = 285 -M68K_INS_MOVEQ = 286 -M68K_INS_MOVES = 287 -M68K_INS_MOVE16 = 288 -M68K_INS_MULS = 289 -M68K_INS_MULU = 290 -M68K_INS_NBCD = 291 -M68K_INS_NEG = 292 -M68K_INS_NEGX = 293 -M68K_INS_NOP = 294 -M68K_INS_NOT = 295 -M68K_INS_OR = 296 -M68K_INS_ORI = 297 -M68K_INS_PACK = 298 -M68K_INS_PEA = 299 -M68K_INS_PFLUSH = 300 -M68K_INS_PFLUSHA = 301 -M68K_INS_PFLUSHAN = 302 -M68K_INS_PFLUSHN = 303 -M68K_INS_PLOADR = 304 -M68K_INS_PLOADW = 305 -M68K_INS_PLPAR = 306 -M68K_INS_PLPAW = 307 -M68K_INS_PMOVE = 308 -M68K_INS_PMOVEFD = 309 -M68K_INS_PTESTR = 310 -M68K_INS_PTESTW = 311 -M68K_INS_PULSE = 312 -M68K_INS_REMS = 313 -M68K_INS_REMU = 314 -M68K_INS_RESET = 315 -M68K_INS_ROL = 316 -M68K_INS_ROR = 317 -M68K_INS_ROXL = 318 -M68K_INS_ROXR = 319 -M68K_INS_RTD = 320 -M68K_INS_RTE = 321 -M68K_INS_RTM = 322 -M68K_INS_RTR = 323 -M68K_INS_RTS = 324 -M68K_INS_SBCD = 325 -M68K_INS_ST = 326 -M68K_INS_SF = 327 -M68K_INS_SHI = 328 -M68K_INS_SLS = 329 -M68K_INS_SCC = 330 -M68K_INS_SHS = 331 -M68K_INS_SCS = 332 -M68K_INS_SLO = 333 -M68K_INS_SNE = 334 -M68K_INS_SEQ = 335 -M68K_INS_SVC = 336 -M68K_INS_SVS = 337 -M68K_INS_SPL = 338 -M68K_INS_SMI = 339 -M68K_INS_SGE = 340 -M68K_INS_SLT = 341 -M68K_INS_SGT = 342 -M68K_INS_SLE = 343 -M68K_INS_STOP = 344 -M68K_INS_SUB = 345 -M68K_INS_SUBA = 346 -M68K_INS_SUBI = 347 -M68K_INS_SUBQ = 348 -M68K_INS_SUBX = 349 -M68K_INS_SWAP = 350 -M68K_INS_TAS = 351 -M68K_INS_TRAP = 352 -M68K_INS_TRAPV = 353 -M68K_INS_TRAPT = 354 -M68K_INS_TRAPF = 355 -M68K_INS_TRAPHI = 356 -M68K_INS_TRAPLS = 357 -M68K_INS_TRAPCC = 358 -M68K_INS_TRAPHS = 359 -M68K_INS_TRAPCS = 360 -M68K_INS_TRAPLO = 361 -M68K_INS_TRAPNE = 362 -M68K_INS_TRAPEQ = 363 -M68K_INS_TRAPVC = 364 -M68K_INS_TRAPVS = 365 -M68K_INS_TRAPPL = 366 -M68K_INS_TRAPMI = 367 -M68K_INS_TRAPGE = 368 -M68K_INS_TRAPLT = 369 -M68K_INS_TRAPGT = 370 -M68K_INS_TRAPLE = 371 -M68K_INS_TST = 372 -M68K_INS_UNLK = 373 -M68K_INS_UNPK = 374 -M68K_INS_ENDING = 375 +M68K_INS_BITREV = 33 +M68K_INS_BYTEREV = 34 +M68K_INS_BFCHG = 35 +M68K_INS_BFCLR = 36 +M68K_INS_BFEXTS = 37 +M68K_INS_BFEXTU = 38 +M68K_INS_BFFFO = 39 +M68K_INS_BFINS = 40 +M68K_INS_BFSET = 41 +M68K_INS_BFTST = 42 +M68K_INS_BKPT = 43 +M68K_INS_CALLM = 44 +M68K_INS_CAS = 45 +M68K_INS_CAS2 = 46 +M68K_INS_CHK = 47 +M68K_INS_CHK2 = 48 +M68K_INS_CLR = 49 +M68K_INS_CMP = 50 +M68K_INS_CMPA = 51 +M68K_INS_CMPI = 52 +M68K_INS_CMPM = 53 +M68K_INS_CMP2 = 54 +M68K_INS_CINVL = 55 +M68K_INS_CINVP = 56 +M68K_INS_CINVA = 57 +M68K_INS_CPUSHL = 58 +M68K_INS_CPUSHP = 59 +M68K_INS_CPUSHA = 60 +M68K_INS_DBT = 61 +M68K_INS_DBF = 62 +M68K_INS_DBHI = 63 +M68K_INS_DBLS = 64 +M68K_INS_DBCC = 65 +M68K_INS_DBCS = 66 +M68K_INS_DBNE = 67 +M68K_INS_DBEQ = 68 +M68K_INS_DBVC = 69 +M68K_INS_DBVS = 70 +M68K_INS_DBPL = 71 +M68K_INS_DBMI = 72 +M68K_INS_DBGE = 73 +M68K_INS_DBLT = 74 +M68K_INS_DBGT = 75 +M68K_INS_DBLE = 76 +M68K_INS_DBRA = 77 +M68K_INS_DIVS = 78 +M68K_INS_DIVSL = 79 +M68K_INS_DIVU = 80 +M68K_INS_DIVUL = 81 +M68K_INS_EOR = 82 +M68K_INS_EORI = 83 +M68K_INS_EXG = 84 +M68K_INS_EXT = 85 +M68K_INS_EXTB = 86 +M68K_INS_FF1 = 87 +M68K_INS_FABS = 88 +M68K_INS_FSABS = 89 +M68K_INS_FDABS = 90 +M68K_INS_FACOS = 91 +M68K_INS_FADD = 92 +M68K_INS_FSADD = 93 +M68K_INS_FDADD = 94 +M68K_INS_FASIN = 95 +M68K_INS_FATAN = 96 +M68K_INS_FATANH = 97 +M68K_INS_FBF = 98 +M68K_INS_FBEQ = 99 +M68K_INS_FBOGT = 100 +M68K_INS_FBOGE = 101 +M68K_INS_FBOLT = 102 +M68K_INS_FBOLE = 103 +M68K_INS_FBOGL = 104 +M68K_INS_FBOR = 105 +M68K_INS_FBUN = 106 +M68K_INS_FBUEQ = 107 +M68K_INS_FBUGT = 108 +M68K_INS_FBUGE = 109 +M68K_INS_FBULT = 110 +M68K_INS_FBULE = 111 +M68K_INS_FBNE = 112 +M68K_INS_FBT = 113 +M68K_INS_FBSF = 114 +M68K_INS_FBSEQ = 115 +M68K_INS_FBGT = 116 +M68K_INS_FBGE = 117 +M68K_INS_FBLT = 118 +M68K_INS_FBLE = 119 +M68K_INS_FBGL = 120 +M68K_INS_FBGLE = 121 +M68K_INS_FBNGLE = 122 +M68K_INS_FBNGL = 123 +M68K_INS_FBNLE = 124 +M68K_INS_FBNLT = 125 +M68K_INS_FBNGE = 126 +M68K_INS_FBNGT = 127 +M68K_INS_FBSNE = 128 +M68K_INS_FBST = 129 +M68K_INS_FCMP = 130 +M68K_INS_FCOS = 131 +M68K_INS_FCOSH = 132 +M68K_INS_FDBF = 133 +M68K_INS_FDBEQ = 134 +M68K_INS_FDBOGT = 135 +M68K_INS_FDBOGE = 136 +M68K_INS_FDBOLT = 137 +M68K_INS_FDBOLE = 138 +M68K_INS_FDBOGL = 139 +M68K_INS_FDBOR = 140 +M68K_INS_FDBUN = 141 +M68K_INS_FDBUEQ = 142 +M68K_INS_FDBUGT = 143 +M68K_INS_FDBUGE = 144 +M68K_INS_FDBULT = 145 +M68K_INS_FDBULE = 146 +M68K_INS_FDBNE = 147 +M68K_INS_FDBT = 148 +M68K_INS_FDBSF = 149 +M68K_INS_FDBSEQ = 150 +M68K_INS_FDBGT = 151 +M68K_INS_FDBGE = 152 +M68K_INS_FDBLT = 153 +M68K_INS_FDBLE = 154 +M68K_INS_FDBGL = 155 +M68K_INS_FDBGLE = 156 +M68K_INS_FDBNGLE = 157 +M68K_INS_FDBNGL = 158 +M68K_INS_FDBNLE = 159 +M68K_INS_FDBNLT = 160 +M68K_INS_FDBNGE = 161 +M68K_INS_FDBNGT = 162 +M68K_INS_FDBSNE = 163 +M68K_INS_FDBST = 164 +M68K_INS_FDIV = 165 +M68K_INS_FSDIV = 166 +M68K_INS_FDDIV = 167 +M68K_INS_FETOX = 168 +M68K_INS_FETOXM1 = 169 +M68K_INS_FGETEXP = 170 +M68K_INS_FGETMAN = 171 +M68K_INS_FINT = 172 +M68K_INS_FINTRZ = 173 +M68K_INS_FLOG10 = 174 +M68K_INS_FLOG2 = 175 +M68K_INS_FLOGN = 176 +M68K_INS_FLOGNP1 = 177 +M68K_INS_FMOD = 178 +M68K_INS_FMOVE = 179 +M68K_INS_FSMOVE = 180 +M68K_INS_FDMOVE = 181 +M68K_INS_FMOVECR = 182 +M68K_INS_FMOVEM = 183 +M68K_INS_FMUL = 184 +M68K_INS_FSMUL = 185 +M68K_INS_FDMUL = 186 +M68K_INS_FNEG = 187 +M68K_INS_FSNEG = 188 +M68K_INS_FDNEG = 189 +M68K_INS_FNOP = 190 +M68K_INS_FREM = 191 +M68K_INS_FRESTORE = 192 +M68K_INS_FSAVE = 193 +M68K_INS_FSCALE = 194 +M68K_INS_FSGLDIV = 195 +M68K_INS_FSGLMUL = 196 +M68K_INS_FSIN = 197 +M68K_INS_FSINCOS = 198 +M68K_INS_FSINH = 199 +M68K_INS_FSQRT = 200 +M68K_INS_FSSQRT = 201 +M68K_INS_FDSQRT = 202 +M68K_INS_FSF = 203 +M68K_INS_FSBEQ = 204 +M68K_INS_FSOGT = 205 +M68K_INS_FSOGE = 206 +M68K_INS_FSOLT = 207 +M68K_INS_FSOLE = 208 +M68K_INS_FSOGL = 209 +M68K_INS_FSOR = 210 +M68K_INS_FSUN = 211 +M68K_INS_FSUEQ = 212 +M68K_INS_FSUGT = 213 +M68K_INS_FSUGE = 214 +M68K_INS_FSULT = 215 +M68K_INS_FSULE = 216 +M68K_INS_FSNE = 217 +M68K_INS_FST = 218 +M68K_INS_FSSF = 219 +M68K_INS_FSSEQ = 220 +M68K_INS_FSGT = 221 +M68K_INS_FSGE = 222 +M68K_INS_FSLT = 223 +M68K_INS_FSLE = 224 +M68K_INS_FSGL = 225 +M68K_INS_FSGLE = 226 +M68K_INS_FSNGLE = 227 +M68K_INS_FSNGL = 228 +M68K_INS_FSNLE = 229 +M68K_INS_FSNLT = 230 +M68K_INS_FSNGE = 231 +M68K_INS_FSNGT = 232 +M68K_INS_FSSNE = 233 +M68K_INS_FSST = 234 +M68K_INS_FSUB = 235 +M68K_INS_FSSUB = 236 +M68K_INS_FDSUB = 237 +M68K_INS_FTAN = 238 +M68K_INS_FTANH = 239 +M68K_INS_FTENTOX = 240 +M68K_INS_FTRAPF = 241 +M68K_INS_FTRAPEQ = 242 +M68K_INS_FTRAPOGT = 243 +M68K_INS_FTRAPOGE = 244 +M68K_INS_FTRAPOLT = 245 +M68K_INS_FTRAPOLE = 246 +M68K_INS_FTRAPOGL = 247 +M68K_INS_FTRAPOR = 248 +M68K_INS_FTRAPUN = 249 +M68K_INS_FTRAPUEQ = 250 +M68K_INS_FTRAPUGT = 251 +M68K_INS_FTRAPUGE = 252 +M68K_INS_FTRAPULT = 253 +M68K_INS_FTRAPULE = 254 +M68K_INS_FTRAPNE = 255 +M68K_INS_FTRAPT = 256 +M68K_INS_FTRAPSF = 257 +M68K_INS_FTRAPSEQ = 258 +M68K_INS_FTRAPGT = 259 +M68K_INS_FTRAPGE = 260 +M68K_INS_FTRAPLT = 261 +M68K_INS_FTRAPLE = 262 +M68K_INS_FTRAPGL = 263 +M68K_INS_FTRAPGLE = 264 +M68K_INS_FTRAPNGLE = 265 +M68K_INS_FTRAPNGL = 266 +M68K_INS_FTRAPNLE = 267 +M68K_INS_FTRAPNLT = 268 +M68K_INS_FTRAPNGE = 269 +M68K_INS_FTRAPNGT = 270 +M68K_INS_FTRAPSNE = 271 +M68K_INS_FTRAPST = 272 +M68K_INS_FTST = 273 +M68K_INS_FTWOTOX = 274 +M68K_INS_HALT = 275 +M68K_INS_ILLEGAL = 276 +M68K_INS_INTOUCH = 277 +M68K_INS_JMP = 278 +M68K_INS_JSR = 279 +M68K_INS_LEA = 280 +M68K_INS_LINK = 281 +M68K_INS_LPSTOP = 282 +M68K_INS_LSL = 283 +M68K_INS_LSR = 284 +M68K_INS_MAC = 285 +M68K_INS_MOVE = 286 +M68K_INS_MOVEA = 287 +M68K_INS_MOVEC = 288 +M68K_INS_MOVEM = 289 +M68K_INS_MOVEP = 290 +M68K_INS_MOVEQ = 291 +M68K_INS_MOVES = 292 +M68K_INS_MOVE16 = 293 +M68K_INS_MOV3Q = 294 +M68K_INS_MOVCLR = 295 +M68K_INS_MSAC = 296 +M68K_INS_MULS = 297 +M68K_INS_MULU = 298 +M68K_INS_MVS = 299 +M68K_INS_MVZ = 300 +M68K_INS_NBCD = 301 +M68K_INS_NEG = 302 +M68K_INS_NEGX = 303 +M68K_INS_NOP = 304 +M68K_INS_NOT = 305 +M68K_INS_OR = 306 +M68K_INS_ORI = 307 +M68K_INS_PACK = 308 +M68K_INS_PEA = 309 +M68K_INS_PFLUSH = 310 +M68K_INS_PFLUSHA = 311 +M68K_INS_PFLUSHAN = 312 +M68K_INS_PFLUSHN = 313 +M68K_INS_PLOADR = 314 +M68K_INS_PLOADW = 315 +M68K_INS_PLPAR = 316 +M68K_INS_PLPAW = 317 +M68K_INS_PMOVE = 318 +M68K_INS_PMOVEFD = 319 +M68K_INS_PTESTR = 320 +M68K_INS_PTESTW = 321 +M68K_INS_PULSE = 322 +M68K_INS_REMS = 323 +M68K_INS_REMU = 324 +M68K_INS_RESET = 325 +M68K_INS_ROL = 326 +M68K_INS_ROR = 327 +M68K_INS_ROXL = 328 +M68K_INS_ROXR = 329 +M68K_INS_RTD = 330 +M68K_INS_RTE = 331 +M68K_INS_RTM = 332 +M68K_INS_RTR = 333 +M68K_INS_RTS = 334 +M68K_INS_SATS = 335 +M68K_INS_SBCD = 336 +M68K_INS_ST = 337 +M68K_INS_SF = 338 +M68K_INS_SHI = 339 +M68K_INS_SLS = 340 +M68K_INS_SCC = 341 +M68K_INS_SHS = 342 +M68K_INS_SCS = 343 +M68K_INS_SLO = 344 +M68K_INS_SNE = 345 +M68K_INS_SEQ = 346 +M68K_INS_SVC = 347 +M68K_INS_SVS = 348 +M68K_INS_SPL = 349 +M68K_INS_SMI = 350 +M68K_INS_SGE = 351 +M68K_INS_SLT = 352 +M68K_INS_SGT = 353 +M68K_INS_SLE = 354 +M68K_INS_STOP = 355 +M68K_INS_STRLDSR = 356 +M68K_INS_SUB = 357 +M68K_INS_SUBA = 358 +M68K_INS_SUBI = 359 +M68K_INS_SUBQ = 360 +M68K_INS_SUBX = 361 +M68K_INS_SWAP = 362 +M68K_INS_TAS = 363 +M68K_INS_TRAP = 364 +M68K_INS_TRAPV = 365 +M68K_INS_TRAPT = 366 +M68K_INS_TRAPF = 367 +M68K_INS_TRAPHI = 368 +M68K_INS_TRAPLS = 369 +M68K_INS_TRAPCC = 370 +M68K_INS_TRAPHS = 371 +M68K_INS_TRAPCS = 372 +M68K_INS_TRAPLO = 373 +M68K_INS_TRAPNE = 374 +M68K_INS_TRAPEQ = 375 +M68K_INS_TRAPVC = 376 +M68K_INS_TRAPVS = 377 +M68K_INS_TRAPPL = 378 +M68K_INS_TRAPMI = 379 +M68K_INS_TRAPGE = 380 +M68K_INS_TRAPLT = 381 +M68K_INS_TRAPGT = 382 +M68K_INS_TRAPLE = 383 +M68K_INS_TST = 384 +M68K_INS_UNLK = 385 +M68K_INS_UNPK = 386 +M68K_INS_WDDATA = 387 +M68K_INS_WDEBUG = 388 +M68K_INS_BGND = 389 +M68K_INS_TBLS = 390 +M68K_INS_TBLU = 391 +M68K_INS_TBLSN = 392 +M68K_INS_TBLUN = 393 +M68K_INS_CP0BCBUSY = 394 +M68K_INS_CP0LD = 395 +M68K_INS_CP0NOP = 396 +M68K_INS_CP0ST = 397 +M68K_INS_CP1BCBUSY = 398 +M68K_INS_CP1LD = 399 +M68K_INS_CP1NOP = 400 +M68K_INS_CP1ST = 401 +M68K_INS_TPF = 402 +M68K_INS_ENDING = 403 M68K_GRP_INVALID = 0 M68K_GRP_JUMP = 1 diff --git a/bindings/python/cstest_py/src/cstest_py/details.py b/bindings/python/cstest_py/src/cstest_py/details.py index 34a04a9b9..1998aafaa 100644 --- a/bindings/python/cstest_py/src/cstest_py/details.py +++ b/bindings/python/cstest_py/src/cstest_py/details.py @@ -69,13 +69,20 @@ from capstone.m68k_const import ( M68K_OP_FP_DOUBLE, M68K_OP_FP_SINGLE, M68K_OP_MEM, + M68K_OP_SHIFT, ) from capstone.mips_const import MIPS_OP_REG, MIPS_OP_IMM, MIPS_OP_MEM from capstone.mos65xx_const import MOS65XX_OP_REG, MOS65XX_OP_MEM, MOS65XX_OP_IMM from capstone.riscv import RISCV_OP_FP from capstone.riscv_const import RISCV_OP_CSR, RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG from capstone.sh_const import SH_OP_REG, SH_OP_MEM, SH_OP_IMM -from capstone.sparc_const import SPARC_OP_REG, SPARC_OP_IMM, SPARC_OP_MEM, SPARC_OP_ASI, SPARC_OP_MEMBAR_TAG +from capstone.sparc_const import ( + SPARC_OP_REG, + SPARC_OP_IMM, + SPARC_OP_MEM, + SPARC_OP_ASI, + SPARC_OP_MEMBAR_TAG, +) from capstone.systemz_const import SYSTEMZ_OP_REG, SYSTEMZ_OP_IMM, SYSTEMZ_OP_MEM from capstone.tms320c64x_const import ( TMS320C64X_OP_REG, @@ -401,10 +408,14 @@ def test_expected_x86(actual: CsInsn, expected: dict) -> bool: def test_expected_ppc(actual: CsInsn, expected: dict) -> bool: - if "bc" in expected and not compare_uint8(actual.bc.bo, expected["bc"].get("bo"), "bo"): + if "bc" in expected and not compare_uint8( + actual.bc.bo, expected["bc"].get("bo"), "bo" + ): return False - if "bc" in expected and not compare_uint8(actual.bc.bi, expected["bc"].get("bi"), "bi"): + if "bc" in expected and not compare_uint8( + actual.bc.bi, expected["bc"].get("bi"), "bi" + ): return False if "bc" in expected and not compare_enum( @@ -591,9 +602,7 @@ def test_expected_arm(actual: CsInsn, expected: dict) -> bool: if not compare_int8(aop.neon_lane, eop.get("neon_lane"), "neon_lane"): return False - if not compare_int32( - aop.vector_index, eop.get("vector_index"), "vector_index" - ): + if not compare_int32(aop.vector_index, eop.get("vector_index"), "vector_index"): return False if not compare_tbool(aop.subtracted, eop.get("subtracted"), "subtracted"): @@ -715,9 +724,7 @@ def test_expected_aarch64(actual: CsInsn, expected: dict) -> bool: if not compare_tbool(aop.is_vreg, eop.get("is_vreg"), "is_vreg"): return False - if not compare_int32( - aop.vector_index, eop.get("vector_index"), "vector_index" - ): + if not compare_int32(aop.vector_index, eop.get("vector_index"), "vector_index"): return False if not compare_tbool( @@ -760,32 +767,24 @@ def test_expected_aarch64(actual: CsInsn, expected: dict) -> bool: if not compare_fp(aop.value.fp, eop.get("fp"), "fp"): return False elif aop.type == AARCH64_OP_SYSREG: - if not compare_enum( - aop.sysop.sub_type, eop.get("sub_type"), "sub_type" - ): + if not compare_enum(aop.sysop.sub_type, eop.get("sub_type"), "sub_type"): return False if not compare_int32( aop.sysop.reg.raw_val, eop.get("sys_raw_val"), "sys_raw_val" ): return False elif aop.type == AARCH64_OP_SYSIMM: - if not compare_enum( - aop.sysop.sub_type, eop.get("sub_type"), "sub_type" - ): + if not compare_enum(aop.sysop.sub_type, eop.get("sub_type"), "sub_type"): return False if not compare_int32( aop.sysop.imm.raw_val, eop.get("sys_raw_val"), "sys_raw_val" ): return False # EXACTFPIMM operands - if not compare_fp( - aop.fp, eop.get("fp"), "fp" - ): + if not compare_fp(aop.fp, eop.get("fp"), "fp"): return False elif aop.type == AARCH64_OP_SYSALIAS: - if not compare_enum( - aop.sysop.sub_type, eop.get("sub_type"), "sub_type" - ): + if not compare_enum(aop.sysop.sub_type, eop.get("sub_type"), "sub_type"): return False if not compare_int32( aop.sysop.alias.raw_val, eop.get("sys_raw_val"), "sys_raw_val" @@ -1114,6 +1113,8 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool: return False if not compare_enum(aop.address_mode, eop.get("address_mode"), "address_mode"): return False + if not compare_bit_flags(aop.flags, eop.get("flags"), "flags"): + return False if aop.type == M68K_OP_REG: if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"): @@ -1148,6 +1149,9 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool: elif aop.type == M68K_OP_FP_SINGLE: if not compare_fp(aop.simm, eop.get("simm"), "simm"): return False + elif aop.type == M68K_OP_SHIFT: + # Shift direction is stored in aop.flags and compared above. + pass elif aop.type == M68K_OP_MEM: if "mem" not in eop: continue @@ -1185,9 +1189,7 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool: return False if not compare_int16(aop.mem.disp, eop["mem"].get("disp"), "disp"): return False - if not compare_int32( - aop.mem.in_disp, eop["mem"].get("in_disp"), "in_disp" - ): + if not compare_int32(aop.mem.in_disp, eop["mem"].get("in_disp"), "in_disp"): return False if not compare_int32( aop.mem.out_disp, eop["mem"].get("out_disp"), "out_disp" @@ -1203,6 +1205,10 @@ def test_expected_m68k(actual: CsInsn, expected: dict) -> bool: return False if not compare_uint8(aop.mem.offset, eop["mem"].get("offset"), "offset"): return False + if not compare_uint64( + aop.mem.address, eop["mem"].get("address"), "address" + ): + return False else: raise ValueError("Operand type not handled.") return True @@ -1351,7 +1357,9 @@ def test_expected_riscv(actual: CsInsn, expected: dict) -> bool: if not compare_fp(aop.dimm, eop.get("dimm"), "dimm"): return False elif aop.type == RISCV_OP_CSR: - if not compare_uint16(aop.csr, capstone.riscv.SYSREG_NAME_TO_VAL[eop.get("csr")], "csr"): + if not compare_uint16( + aop.csr, capstone.riscv.SYSREG_NAME_TO_VAL[eop.get("csr")], "csr" + ): return False else: raise ValueError("Operand type not handled.") @@ -1399,9 +1407,7 @@ def test_expected_SystemZ(actual: CsInsn, expected: dict) -> bool: len(actual.operands), len(expected.get("operands")), "operands_count" ): return False - elif not compare_enum( - actual.format, expected.get("format"), "format" - ): + elif not compare_enum(actual.format, expected.get("format"), "format"): return False for aop, eop in zip(actual.operands, expected["operands"]): @@ -1563,6 +1569,7 @@ def test_expected_wasm(actual: CsInsn, expected: dict) -> bool: raise ValueError("Operand type not handled.") return True + def test_expected_arc(actual: CsInsn, expected: dict) -> bool: if "operands" not in expected: return True diff --git a/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c b/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c index 5d726c926..82b211662 100644 --- a/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c +++ b/contrib/m68k_instruction_tbl_gen/M68KInstructionTblGen.c @@ -37,8 +37,7 @@ typedef struct { static opcode_struct g_opcode_info[] = { /* opcode handler mask match ea_mask mask2 match2*/ - { "d68000_1010", 0xf000, 0xa000, 0x000 }, - { "d68000_1111", 0xf000, 0xf000, 0x000 }, + { "dcf_1111", 0xf000, 0xf000, 0x000 }, { "d68000_abcd_rr", 0xf1f8, 0xc100, 0x000 }, { "d68000_abcd_mm", 0xf1f8, 0xc108, 0x000 }, { "d68000_add_er_8", 0xf1c0, 0xd000, 0xbff }, @@ -112,6 +111,8 @@ static opcode_struct g_opcode_info[] = { { "d68020_bsr_32", 0xffff, 0x61ff, 0x000 }, { "d68000_btst_r", 0xf1c0, 0x0100, 0xbff }, { "d68000_btst_s", 0xffc0, 0x0800, 0xbfb }, + { "dcf_bitrev", 0xfff8, 0x00c0, 0x000 }, + { "dcf_byterev", 0xfff8, 0x02c0, 0x000 }, { "d68020_callm", 0xffc0, 0x06c0, 0x27b, 0xff00, 0x0000 }, { "d68020_cas_8", 0xffc0, 0x0ac0, 0x3f8, 0xfe38, 0x0000 }, { "d68020_cas_16", 0xffc0, 0x0cc0, 0x3f8, 0xfe38, 0x0000 }, @@ -146,6 +147,20 @@ static opcode_struct g_opcode_info[] = { { "d68000_cmpm_8", 0xf1f8, 0xb108, 0x000 }, { "d68000_cmpm_16", 0xf1f8, 0xb148, 0x000 }, { "d68000_cmpm_32", 0xf1f8, 0xb188, 0x000 }, + { "dcf_cp0bcbusy", 0xfff8, 0xfcc0, 0x000 }, + { "dcf_cp1bcbusy", 0xfff8, 0xfec0, 0x000 }, + { "dcf_coproc_ldst", 0xffc0, 0xfc00, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfc40, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfc80, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfd00, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfd40, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfd80, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfe00, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfe40, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xfe80, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xff00, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xff40, 0xfc0 }, + { "dcf_coproc_ldst", 0xffc0, 0xff80, 0xfc0 }, { "d68020_cpbcc_16", 0xf1c0, 0xf080, 0x000 }, { "d68020_cpbcc_32", 0xf1c0, 0xf0c0, 0x000 }, { "d68020_cpdbcc", 0xf1f8, 0xf048, 0x000 }, @@ -176,7 +191,9 @@ static opcode_struct g_opcode_info[] = { { "d68020_extb_32", 0xfff8, 0x49c0, 0x000 }, { "d68000_ext_16", 0xfff8, 0x4880, 0x000 }, { "d68000_ext_32", 0xfff8, 0x48c0, 0x000 }, + { "dcf_ff1", 0xfff8, 0x04c0, 0x000 }, { "d68000_illegal", 0xffff, 0x4afc, 0x000 }, + { "dcf_intouch", 0xfff8, 0xf428, 0x000 }, { "d68000_jmp", 0xffc0, 0x4ec0, 0x27b }, { "d68000_jsr", 0xffc0, 0x4e80, 0x27b }, { "d68000_lea", 0xf1c0, 0x41c0, 0x27b }, @@ -208,6 +225,24 @@ static opcode_struct g_opcode_info[] = { { "d68000_move_to_usp", 0xfff8, 0x4e60, 0x000 }, { "d68000_move_fr_usp", 0xfff8, 0x4e68, 0x000 }, { "d68010_movec", 0xfffe, 0x4e7a, 0x000 }, + { "dcf_movclr_accn_reg", 0xf9f0, 0xa1c0, 0x000 }, + { "dcf_move_acc_reg", 0xfff0, 0xa180, 0x000 }, + { "dcf_move_accn_reg", 0xf9f0, 0xa180, 0x000 }, + { "dcf_move_acc_acc", 0xf9fc, 0xa110, 0x000 }, + { "dcf_move_reg_acc", 0xfff0, 0xa100, 0x000 }, + { "dcf_move_reg_accn", 0xf9f0, 0xa100, 0x000 }, + { "dcf_move_imm_acc", 0xffff, 0xa13c, 0x000 }, + { "dcf_move_imm_accn", 0xf9ff, 0xa13c, 0x000 }, + { "dcf_move_accext_reg", 0xfbf0, 0xab80, 0x000 }, + { "dcf_move_reg_accext", 0xfbc0, 0xab00, 0xc00 }, + { "dcf_move_imm_accext", 0xfbff, 0xab3c, 0x000 }, + { "dcf_move_macsr_reg", 0xfff0, 0xa980, 0x000 }, + { "dcf_move_reg_macsr", 0xfff0, 0xa900, 0x000 }, + { "dcf_move_imm_macsr", 0xffff, 0xa93c, 0x000 }, + { "dcf_move_mask_reg", 0xfff0, 0xad80, 0x000 }, + { "dcf_move_reg_mask", 0xfff0, 0xad00, 0x000 }, + { "dcf_move_imm_mask", 0xffff, 0xad3c, 0x000 }, + { "dcf_move_macsr_ccr", 0xffff, 0xa9c0, 0x000 }, { "d68000_movem_pd_16", 0xfff8, 0x48a0, 0x000 }, { "d68000_movem_pd_32", 0xfff8, 0x48e0, 0x000 }, { "d68000_movem_re_16", 0xffc0, 0x4880, 0x2f8 }, @@ -218,10 +253,17 @@ static opcode_struct g_opcode_info[] = { { "d68000_movep_er_32", 0xf1f8, 0x0148, 0x000 }, { "d68000_movep_re_16", 0xf1f8, 0x0188, 0x000 }, { "d68000_movep_re_32", 0xf1f8, 0x01c8, 0x000 }, + { "dcf_mov3q", 0xf1c0, 0xa140, 0xfff }, + { "dcf_mac_arith", 0xf000, 0xa000, 0xc00 }, + { "dcf_mac_arith", 0xf000, 0xa000, 0x3c0 }, { "d68010_moves_8", 0xffc0, 0x0e00, 0x3f8, 0x07ff, 0x0000 }, { "d68010_moves_16", 0xffc0, 0x0e40, 0x3f8, 0x07ff, 0x0000 }, { "d68010_moves_32", 0xffc0, 0x0e80, 0x3f8, 0x07ff, 0x0000 }, { "d68000_moveq", 0xf100, 0x7000, 0x000 }, + { "dcf_mvs_8", 0xf1c0, 0x7100, 0xbff }, + { "dcf_mvs_16", 0xf1c0, 0x7140, 0xfff }, + { "dcf_mvz_8", 0xf1c0, 0x7180, 0xbff }, + { "dcf_mvz_16", 0xf1c0, 0x71c0, 0xfff }, { "d68040_move16_pi_pi", 0xfff8, 0xf620, 0x000, 0x8fff, 0x8000 }, { "d68040_move16_pi_al", 0xfff8, 0xf600, 0x000 }, { "d68040_move16_al_pi", 0xfff8, 0xf608, 0x000 }, @@ -296,6 +338,7 @@ static opcode_struct g_opcode_info[] = { { "d68000_sbcd_mm", 0xf1f8, 0x8108, 0x000 }, { "d68000_scc", 0xf0c0, 0x50c0, 0xbf8 }, { "d68000_stop", 0xffff, 0x4e72, 0x000 }, + { "dcf_strldsr", 0xffff, 0x40e7, 0x000, 0xffff, 0x46fc }, { "d68060_lpstop", 0xffff, 0xf800, 0x000 }, { "d68cpu32_tbl", 0xffc0, 0xf800, 0x000 }, { "d68040_pflush", 0xffe0, 0xf500, 0x000 }, @@ -325,6 +368,7 @@ static opcode_struct g_opcode_info[] = { { "d68000_subx_mm_16", 0xf1f8, 0x9148, 0x000 }, { "d68000_subx_mm_32", 0xf1f8, 0x9188, 0x000 }, { "d68000_swap", 0xfff8, 0x4840, 0x000 }, + { "dcf_sats", 0xfff8, 0x4c80, 0x000 }, { "d68000_tas", 0xffc0, 0x4ac0, 0xbf8 }, { "d68000_trap", 0xfff0, 0x4e40, 0x000 }, { "d68020_trapcc_0", 0xf0ff, 0x50fc, 0x000 }, @@ -348,6 +392,11 @@ static opcode_struct g_opcode_info[] = { { "d68000_unlk", 0xfff8, 0x4e58, 0x000 }, { "d68020_unpk_rr", 0xf1f8, 0x8180, 0x000 }, { "d68020_unpk_mm", 0xf1f8, 0x8188, 0x000 }, + { "dcf_wddata", 0xffc0, 0xfb00, 0x3f8 }, + { "dcf_wddata", 0xffc0, 0xfb40, 0x3f8 }, + { "dcf_wddata", 0xffc0, 0xfb80, 0x3f8 }, + { "dcf_wdebug", 0xfff8, 0xfbd0, 0x000, 0xffff, 0x0003 }, + { "dcf_wdebug", 0xfff8, 0xfbe8, 0x000, 0xffff, 0x0003 }, { 0, 0, 0, 0 } }; diff --git a/cs.c b/cs.c index 9aafe2930..257e70f6c 100644 --- a/cs.c +++ b/cs.c @@ -166,9 +166,7 @@ typedef struct cs_arch_config { { \ M68K_global_init, \ M68K_option, \ - ~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_000 | CS_MODE_M68K_010 | \ - CS_MODE_M68K_020 | CS_MODE_M68K_030 | CS_MODE_M68K_040 | \ - CS_MODE_M68K_060 | CS_MODE_M68K_CPU32), \ + ~(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_FEATURE_MASK), \ } #define CS_ARCH_CONFIG_TMS320C64X \ { \ diff --git a/cstool/cstool.c b/cstool/cstool.c index d507453f1..9d8c44334 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -428,6 +428,20 @@ static struct { { "m68k40", "m68k, 68040", CS_ARCH_M68K, CS_MODE_M68K_040 }, { "m68k60", "m68k, 68060", CS_ARCH_M68K, CS_MODE_M68K_060 }, { "m68kcpu32", "m68k, cpu32", CS_ARCH_M68K, CS_MODE_M68K_CPU32 }, + { "m68kcf", "m68k, ColdFire all features", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_COLDFIRE }, + { "m68kcfv1", "m68k, ColdFire V1", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV1 }, + { "m68kcfv2", "m68k, ColdFire V2", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV2 }, + { "m68kcfv3", "m68k, ColdFire V3", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV3 }, + { "m68kcfv4", "m68k, ColdFire V4", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV4 }, + { "m68kcfv4e", "m68k, ColdFire V4e", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV4E }, + { "m68kcfv5", "m68k, ColdFire V5", CS_ARCH_M68K, + CS_MODE_BIG_ENDIAN | CS_MODE_M68K_CFV5 }, { "tms320c64x", "tms320c64x, big endian", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN }, diff --git a/cstool/cstool_m68k.c b/cstool/cstool_m68k.c index 0bfe9dddb..49588ce66 100644 --- a/cstool/cstool_m68k.c +++ b/cstool/cstool_m68k.c @@ -6,6 +6,7 @@ // // +#include #include #include #include "cstool.h" @@ -38,8 +39,38 @@ static const char *s_addressing_modes[] = { "Absolute Data Addressing - Short", "Absolute Data Addressing - Long", "Immediate value", + "Branch displacement", }; +static void print_operand_flags(unsigned int op_index, uint8_t flags) +{ + int need_sep = 0; + + if (!flags) + return; + + printf("\t\t\toperands[%u].flags: ", op_index); + if (flags & M68K_OP_FLAG_REG_LOWER) { + printf("REG_LOWER"); + need_sep = 1; + } + if (flags & M68K_OP_FLAG_REG_UPPER) { + printf("%sREG_UPPER", need_sep ? ", " : ""); + need_sep = 1; + } + if (flags & M68K_OP_FLAG_SHIFT_LEFT) { + printf("%sSHIFT_LEFT", need_sep ? ", " : ""); + need_sep = 1; + } + if (flags & M68K_OP_FLAG_SHIFT_RIGHT) { + printf("%sSHIFT_RIGHT", need_sep ? ", " : ""); + need_sep = 1; + } + if (flags & M68K_OP_FLAG_MEM_UPDATE) + printf("%sMEM_UPDATE", need_sep ? ", " : ""); + printf("\n"); +} + static void print_read_write_regs(cs_detail *detail, csh handle) { int i; @@ -96,6 +127,11 @@ void print_insn_detail_m68k(csh handle, cs_insn *ins) printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base_reg)); + if (op->address_mode == M68K_AM_ABSOLUTE_DATA_SHORT || + op->address_mode == M68K_AM_ABSOLUTE_DATA_LONG) + printf("\t\t\toperands[%u].mem.address: 0x%" PRIx64 + "\n", + i, op->mem.address); if (op->mem.index_reg != M68K_REG_INVALID) { printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, @@ -121,6 +157,10 @@ void print_insn_detail_m68k(csh handle, cs_insn *ins) printf("\t\toperands[%u].type: FP_DOUBLE\n", i); printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm); break; + case M68K_OP_SHIFT: + printf("\t\toperands[%u].type: SHIFT\n", i); + break; } + print_operand_flags(i, op->flags); } } diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index 290a88ec6..3c09682cf 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -281,8 +281,8 @@ Nonetheless, we hope this additional information is useful to you. **M68K** -- Architecture support added for `cpu32`, `M68060`. -- Enhanced bitfield instructions, PC-relative addressing, and immediate value type handling. +- Architecture support added for `cpu32`, `M68060`, and ColdFire variants (`CFV1`, `CFV2`, `CFV3`, `CFV4`, `CFV4E`, `CFV5`), including feature flags for USP, DIV, MAC/EMAC, and FPU instructions. +- Expanded operand details for bitfield instructions, PC-relative addressing, immediate value types, and memory addressing metadata. - Expanded integration tests and refactored invalid assembly edge cases. **UX** @@ -482,6 +482,7 @@ Such an instruction is ill-defined in LLVM and should be fixed upstream. | m68k_op_mem.in_disp, m68k_op_mem.out_disp | These fields are now signed instead of unsigned. | The M68K architecture uses sign extended displacements for effective address calculation. | | m68k_op_mem.disp_size | Defines if the .disp field was encoded as a byte (false) or word (true) | Necessary for accurate printing. | | m68k_op_mem.in_disp_size, m68k_op_mem.out_disp_size | Defines if the .in_disp and .out_disp fields respectively were encoded as words (false) or longs (true) | Necessary for accurate printing. | +| `M68K_OP_MEM` storage | Memory operands now store base registers in `m68k_op_mem.base_reg` and absolute addresses in `m68k_op_mem.address`; `op->reg` and `op->imm` are only used for register and immediate operands. | Keeps memory-addressing details in `m68k_op_mem` consistently. | ### Notes about AArch64, SystemZ and ARM renaming diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index ca061afc3..6aadd0ac2 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -164,6 +164,36 @@ typedef enum cs_mode { CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode CS_MODE_M68K_CPU32 = 1 << 7, + CS_MODE_M68K_CF_ISA_A = 1 << 8, ///< ColdFire ISA_A + CS_MODE_M68K_CF_ISA_A_PLUS = 1 << 9, ///< ColdFire ISA_A+ + CS_MODE_M68K_CF_ISA_B = 1 << 10, ///< ColdFire ISA_B + CS_MODE_M68K_CF_ISA_C = 1 << 11, ///< ColdFire ISA_C + CS_MODE_M68K_CF_USP = 1 << 12, ///< ColdFire USP instructions + CS_MODE_M68K_CF_DIV = 1 << 13, ///< ColdFire hardware divide + CS_MODE_M68K_CF_MAC = 1 << 14, ///< ColdFire MAC + CS_MODE_M68K_CF_EMAC = 1 << 15, ///< ColdFire EMAC + CS_MODE_M68K_CF_EMAC_B = 1 << 16, ///< ColdFire EMAC_B + CS_MODE_M68K_CF_FPU = 1 << 17, ///< ColdFire FPU + CS_MODE_M68K_COLDFIRE = CS_MODE_M68K_CF_ISA_A | + CS_MODE_M68K_CF_ISA_A_PLUS | + CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_ISA_C | + CS_MODE_M68K_CF_USP | CS_MODE_M68K_CF_DIV | + CS_MODE_M68K_CF_MAC | CS_MODE_M68K_CF_EMAC | + CS_MODE_M68K_CF_EMAC_B | CS_MODE_M68K_CF_FPU, + CS_MODE_M68K_CFV1 = CS_MODE_M68K_CF_ISA_C | CS_MODE_M68K_CF_USP, + CS_MODE_M68K_CFV2 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV, + CS_MODE_M68K_CFV3 = CS_MODE_M68K_CF_ISA_A | CS_MODE_M68K_CF_DIV, + CS_MODE_M68K_CFV4 = CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_DIV, + CS_MODE_M68K_CFV4E = CS_MODE_M68K_CF_ISA_B | CS_MODE_M68K_CF_DIV | + CS_MODE_M68K_CF_USP | CS_MODE_M68K_CF_EMAC | + CS_MODE_M68K_CF_FPU, + CS_MODE_M68K_CFV5 = CS_MODE_M68K_CF_ISA_C | CS_MODE_M68K_CF_USP | + CS_MODE_M68K_CF_DIV | CS_MODE_M68K_CF_EMAC | + CS_MODE_M68K_CF_EMAC_B, + CS_MODE_M68K_FEATURE_MASK = CS_MODE_M68K_000 | CS_MODE_M68K_010 | + CS_MODE_M68K_020 | CS_MODE_M68K_030 | + CS_MODE_M68K_040 | CS_MODE_M68K_060 | + CS_MODE_M68K_CPU32 | CS_MODE_M68K_COLDFIRE, CS_MODE_BIG_ENDIAN = 1U << 31, ///< big-endian mode CS_MODE_MIPS16 = CS_MODE_16, ///< Generic mips16 CS_MODE_MIPS32 = CS_MODE_32, ///< Generic mips32 diff --git a/include/capstone/m68k.h b/include/capstone/m68k.h index 82ee0c698..02b7a8eb5 100644 --- a/include/capstone/m68k.h +++ b/include/capstone/m68k.h @@ -15,7 +15,7 @@ extern "C" { #pragma warning(disable : 4201) #endif -#define M68K_OPERAND_COUNT 4 +#define M68K_OPERAND_COUNT 6 /// M68K registers and special registers typedef enum m68k_reg { @@ -76,6 +76,15 @@ typedef enum m68k_reg { M68K_REG_TT0, M68K_REG_TT1, M68K_REG_CRP, + M68K_REG_ACC, + M68K_REG_ACC0, + M68K_REG_ACC1, + M68K_REG_ACC2, + M68K_REG_ACC3, + M68K_REG_ACCEXT01, + M68K_REG_ACCEXT23, + M68K_REG_MACSR, + M68K_REG_MASK, M68K_REG_ENDING, // <-- mark the end of the list of registers } m68k_reg; @@ -126,9 +135,24 @@ typedef enum m68k_op_type { // Register pair in the same op (upper 4 bits for first reg, lower for second) M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3, M68K_OP_BR_DISP = CS_OP_SPECIAL + 4, ///< Branch displacement + /// Shift-direction pseudo operand. + /// Shift direction is set in cs_m68k_op.flags + M68K_OP_SHIFT = CS_OP_SPECIAL + 5, M68K_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand). } m68k_op_type; +/// Per-operand modifier flags. +typedef enum m68k_op_flags { + M68K_OP_FLAG_NONE = 0, + M68K_OP_FLAG_REG_LOWER = + 1 << 0, ///< Lower half of a ColdFire MAC word register operand + M68K_OP_FLAG_REG_UPPER = + 1 << 1, ///< Upper half of a ColdFire MAC word register operand + M68K_OP_FLAG_SHIFT_LEFT = 1 << 2, ///< ColdFire MAC left-shift operand + M68K_OP_FLAG_SHIFT_RIGHT = 1 << 3, ///< ColdFire MAC right-shift operand + M68K_OP_FLAG_MEM_UPDATE = 1 << 4, ///< ColdFire MAC memory update marker +} m68k_op_flags; + /// Instruction's operand referring to memory /// This is associated with M68K_OP_MEM operand type above typedef struct m68k_op_mem { @@ -146,6 +170,7 @@ typedef struct m68k_op_mem { uint8_t in_disp_size; ///< 0 = word, 1 = long uint8_t out_disp_size; ///< 0 = word, 1 = long uint8_t disp_size; ///< 0 = byte, 1 = word + uint64_t address; ///< absolute address for absolute MEM operands } m68k_op_mem; /// Bitfield offset/width helpers for m68k_op_mem. @@ -189,6 +214,7 @@ typedef struct cs_m68k_op { uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order) m68k_op_type type; m68k_address_mode address_mode; ///< M68K addressing mode for this op + uint8_t flags; ///< Operand modifier flags, see m68k_op_flags. } cs_m68k_op; /// Operation size of the CPU instructions @@ -270,6 +296,8 @@ typedef enum m68k_insn { M68K_INS_BCLR, M68K_INS_BSET, M68K_INS_BTST, + M68K_INS_BITREV, + M68K_INS_BYTEREV, M68K_INS_BFCHG, M68K_INS_BFCLR, M68K_INS_BFEXTS, @@ -322,6 +350,7 @@ typedef enum m68k_insn { M68K_INS_EXG, M68K_INS_EXT, M68K_INS_EXTB, + M68K_INS_FF1, M68K_INS_FABS, M68K_INS_FSABS, M68K_INS_FDABS, @@ -511,6 +540,7 @@ typedef enum m68k_insn { M68K_INS_FTWOTOX, M68K_INS_HALT, M68K_INS_ILLEGAL, + M68K_INS_INTOUCH, M68K_INS_JMP, M68K_INS_JSR, M68K_INS_LEA, @@ -518,6 +548,7 @@ typedef enum m68k_insn { M68K_INS_LPSTOP, M68K_INS_LSL, M68K_INS_LSR, + M68K_INS_MAC, M68K_INS_MOVE, M68K_INS_MOVEA, M68K_INS_MOVEC, @@ -526,8 +557,13 @@ typedef enum m68k_insn { M68K_INS_MOVEQ, M68K_INS_MOVES, M68K_INS_MOVE16, + M68K_INS_MOV3Q, + M68K_INS_MOVCLR, + M68K_INS_MSAC, M68K_INS_MULS, M68K_INS_MULU, + M68K_INS_MVS, + M68K_INS_MVZ, M68K_INS_NBCD, M68K_INS_NEG, M68K_INS_NEGX, @@ -562,6 +598,7 @@ typedef enum m68k_insn { M68K_INS_RTM, M68K_INS_RTR, M68K_INS_RTS, + M68K_INS_SATS, M68K_INS_SBCD, M68K_INS_ST, M68K_INS_SF, @@ -582,6 +619,7 @@ typedef enum m68k_insn { M68K_INS_SGT, M68K_INS_SLE, M68K_INS_STOP, + M68K_INS_STRLDSR, M68K_INS_SUB, M68K_INS_SUBA, M68K_INS_SUBI, @@ -612,11 +650,22 @@ typedef enum m68k_insn { M68K_INS_TST, M68K_INS_UNLK, M68K_INS_UNPK, + M68K_INS_WDDATA, + M68K_INS_WDEBUG, M68K_INS_BGND, M68K_INS_TBLS, M68K_INS_TBLU, M68K_INS_TBLSN, M68K_INS_TBLUN, + M68K_INS_CP0BCBUSY, + M68K_INS_CP0LD, + M68K_INS_CP0NOP, + M68K_INS_CP0ST, + M68K_INS_CP1BCBUSY, + M68K_INS_CP1LD, + M68K_INS_CP1NOP, + M68K_INS_CP1ST, + M68K_INS_TPF, M68K_INS_ENDING, // <-- mark the end of the list of instructions } m68k_insn; diff --git a/suite/cstest/include/test_detail_m68k.h b/suite/cstest/include/test_detail_m68k.h index 3d0e175a8..1f6640c96 100644 --- a/suite/cstest/include/test_detail_m68k.h +++ b/suite/cstest/include/test_detail_m68k.h @@ -23,6 +23,7 @@ typedef struct { uint8_t bitfield; uint8_t width; uint8_t offset; + uint64_t address; } TestDetailM68KOpMem; static const cyaml_schema_field_t test_detail_m68k_op_mem_mapping_schema[] = { @@ -51,6 +52,8 @@ static const cyaml_schema_field_t test_detail_m68k_op_mem_mapping_schema[] = { width), CYAML_FIELD_UINT("offset", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, offset), + CYAML_FIELD_UINT("address", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, + address), CYAML_FIELD_INT("in_disp_size", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, in_disp_size), @@ -80,9 +83,11 @@ typedef struct { float simm; TestDetailM68KOpMem *mem; + char **flags; + size_t flags_count; } TestDetailM68KOp; -static const cyaml_schema_value_t test_detail_m68k_op_sys_psr_schema = { +static const cyaml_schema_value_t test_detail_m68k_op_flag_schema = { CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED), }; @@ -111,6 +116,10 @@ static const cyaml_schema_field_t test_detail_m68k_op_mapping_schema[] = { CYAML_FIELD_FLOAT("simm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, simm), CYAML_FIELD_MAPPING_PTR("mem", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, mem, test_detail_m68k_op_mem_mapping_schema), + CYAML_FIELD_SEQUENCE("flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, + TestDetailM68KOp, flags, + &test_detail_m68k_op_flag_schema, 0, + CYAML_UNLIMITED), CYAML_FIELD_END }; diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index 993b86bda..6bbf73c18 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -103,7 +103,27 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_M68K_030", .val = CS_MODE_M68K_030 }, { .str = "CS_MODE_M68K_040", .val = CS_MODE_M68K_040 }, { .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 }, + { .str = "CS_MODE_M68K_CFV1", .val = CS_MODE_M68K_CFV1 }, + { .str = "CS_MODE_M68K_CFV2", .val = CS_MODE_M68K_CFV2 }, + { .str = "CS_MODE_M68K_CFV3", .val = CS_MODE_M68K_CFV3 }, + { .str = "CS_MODE_M68K_CFV4", .val = CS_MODE_M68K_CFV4 }, + { .str = "CS_MODE_M68K_CFV4E", .val = CS_MODE_M68K_CFV4E }, + { .str = "CS_MODE_M68K_CFV5", .val = CS_MODE_M68K_CFV5 }, + { .str = "CS_MODE_M68K_CF_DIV", .val = CS_MODE_M68K_CF_DIV }, + { .str = "CS_MODE_M68K_CF_EMAC", .val = CS_MODE_M68K_CF_EMAC }, + { .str = "CS_MODE_M68K_CF_EMAC_B", .val = CS_MODE_M68K_CF_EMAC_B }, + { .str = "CS_MODE_M68K_CF_FPU", .val = CS_MODE_M68K_CF_FPU }, + { .str = "CS_MODE_M68K_CF_ISA_A", .val = CS_MODE_M68K_CF_ISA_A }, + { .str = "CS_MODE_M68K_CF_ISA_A_PLUS", + .val = CS_MODE_M68K_CF_ISA_A_PLUS }, + { .str = "CS_MODE_M68K_CF_ISA_B", .val = CS_MODE_M68K_CF_ISA_B }, + { .str = "CS_MODE_M68K_CF_ISA_C", .val = CS_MODE_M68K_CF_ISA_C }, + { .str = "CS_MODE_M68K_CF_MAC", .val = CS_MODE_M68K_CF_MAC }, + { .str = "CS_MODE_M68K_CF_USP", .val = CS_MODE_M68K_CF_USP }, + { .str = "CS_MODE_M68K_COLDFIRE", .val = CS_MODE_M68K_COLDFIRE }, { .str = "CS_MODE_M68K_CPU32", .val = CS_MODE_M68K_CPU32 }, + { .str = "CS_MODE_M68K_FEATURE_MASK", + .val = CS_MODE_M68K_FEATURE_MASK }, { .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS }, { .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO }, { .str = "CS_MODE_MICRO32R3", .val = CS_MODE_MICRO32R3 }, @@ -918,6 +938,11 @@ static const cs_enum_id_map cs_enum_map[] = { .val = M68K_OP_BR_DISP_SIZE_LONG }, { .str = "M68K_OP_BR_DISP_SIZE_WORD", .val = M68K_OP_BR_DISP_SIZE_WORD }, + { .str = "M68K_OP_FLAG_MEM_UPDATE", .val = M68K_OP_FLAG_MEM_UPDATE }, + { .str = "M68K_OP_FLAG_REG_LOWER", .val = M68K_OP_FLAG_REG_LOWER }, + { .str = "M68K_OP_FLAG_REG_UPPER", .val = M68K_OP_FLAG_REG_UPPER }, + { .str = "M68K_OP_FLAG_SHIFT_LEFT", .val = M68K_OP_FLAG_SHIFT_LEFT }, + { .str = "M68K_OP_FLAG_SHIFT_RIGHT", .val = M68K_OP_FLAG_SHIFT_RIGHT }, { .str = "M68K_OP_FP_DOUBLE", .val = M68K_OP_FP_DOUBLE }, { .str = "M68K_OP_FP_SINGLE", .val = M68K_OP_FP_SINGLE }, { .str = "M68K_OP_IMM", .val = M68K_OP_IMM }, @@ -925,6 +950,7 @@ static const cs_enum_id_map cs_enum_map[] = { { .str = "M68K_OP_REG", .val = M68K_OP_REG }, { .str = "M68K_OP_REG_BITS", .val = M68K_OP_REG_BITS }, { .str = "M68K_OP_REG_PAIR", .val = M68K_OP_REG_PAIR }, + { .str = "M68K_OP_SHIFT", .val = M68K_OP_SHIFT }, { .str = "M68K_SIZE_TYPE_CPU", .val = M68K_SIZE_TYPE_CPU }, { .str = "M68K_SIZE_TYPE_FPU", .val = M68K_SIZE_TYPE_FPU }, { .str = "MIPS_INS_ADDIU", .val = MIPS_INS_ADDIU }, diff --git a/suite/cstest/src/test_case.c b/suite/cstest/src/test_case.c index 3f6063541..cb865c286 100644 --- a/suite/cstest/src/test_case.c +++ b/suite/cstest/src/test_case.c @@ -65,7 +65,7 @@ char *test_input_stringify(const TestInput *test_input, const char *prefix) cs_mem_free(byte_seq); return NULL; } - char opt_seq[128] = { 0 }; + char opt_seq[512] = { 0 }; str_append_no_realloc(opt_seq, sizeof(opt_seq), "["); for (size_t i = 0; i < test_input->options_count; ++i) { str_append_no_realloc(opt_seq, sizeof(opt_seq), diff --git a/suite/cstest/src/test_detail_m68k.c b/suite/cstest/src/test_detail_m68k.c index 8ada16314..79bad5000 100644 --- a/suite/cstest/src/test_detail_m68k.c +++ b/suite/cstest/src/test_detail_m68k.c @@ -29,6 +29,7 @@ TestDetailM68KOpMem *test_detail_m68k_op_mem_clone(TestDetailM68KOpMem *mem) clone->bitfield = mem->bitfield; clone->width = mem->width; clone->offset = mem->offset; + clone->address = mem->address; clone->in_disp_size = mem->in_disp_size; clone->out_disp_size = mem->out_disp_size; clone->disp_size = mem->disp_size; @@ -112,6 +113,11 @@ TestDetailM68KOp *test_detail_m68k_op_clone(TestDetailM68KOp *op) clone->br_disp = op->br_disp; clone->br_disp_size = op->br_disp_size; clone->register_bits = op->register_bits; + clone->flags_count = op->flags_count; + if (op->flags_count > 0) + clone->flags = cs_mem_calloc(sizeof(char *), op->flags_count); + for (size_t i = 0; i < clone->flags_count; ++i) + clone->flags[i] = op->flags[i] ? strdup(op->flags[i]) : NULL; clone->mem = op->mem ? test_detail_m68k_op_mem_clone(op->mem) : NULL; return clone; @@ -127,6 +133,9 @@ void test_detail_m68k_op_free(TestDetailM68KOp *op) cs_mem_free(op->reg_pair_0); cs_mem_free(op->reg_pair_1); cs_mem_free(op->address_mode); + for (size_t i = 0; i < op->flags_count; ++i) + cs_mem_free(op->flags[i]); + cs_mem_free(op->flags); test_detail_m68k_op_mem_free(op->mem); cs_mem_free(op); } @@ -147,6 +156,8 @@ bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected) TestDetailM68KOp *eop = expected->operands[i]; compare_enum_ret(op->type, eop->type, false); compare_enum_ret(op->address_mode, eop->address_mode, false); + compare_bit_flags_ret(op->flags, eop->flags, eop->flags_count, + false); switch (op->type) { default: fprintf(stderr, @@ -181,6 +192,9 @@ bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected) compare_uint8_ret(op->br_disp.disp_size, eop->br_disp_size, false); break; + case M68K_OP_SHIFT: + // Shift direction is stored in op->flags and compared above. + break; case M68K_OP_MEM: if (!eop->mem) { break; @@ -221,6 +235,10 @@ bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected) compare_uint8_ret(op->mem.offset, eop->mem->offset, false); } + if (eop->mem->address) { + compare_uint64_ret(op->mem.address, + eop->mem->address, false); + } compare_tbool_ret(op->mem.in_disp_size, eop->mem->in_disp_size, false); compare_tbool_ret(op->mem.out_disp_size, diff --git a/tests/details/m68k.yaml b/tests/details/m68k.yaml index abb46896e..a28582895 100644 --- a/tests/details/m68k.yaml +++ b/tests/details/m68k.yaml @@ -1,1184 +1,1044 @@ test_cases: - - - input: - bytes: [ 0xf6, 0x20, 0x90, 0x00 ] + - input: + bytes: [0xf6, 0x20, 0x90, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "move16 (a0)+, (a1)+" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC - - - input: - bytes: [ 0x06, 0xd0, 0x00, 0x01 ] + - asm_text: "move16 (a0)+, (a1)+" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR_POST_INC + - type: M68K_OP_MEM + mem: + base_reg: a1 + address_mode: M68K_AM_REGI_ADDR_POST_INC + - input: + bytes: [0x06, 0xd0, 0x00, 0x01] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "callm #$1, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x1 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a0] - regs_impl_read: [a0] - - - input: - bytes: [ 0x06, 0xd0 ] + - asm_text: "callm #$1, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x06, 0xd0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: [] - - - input: - bytes: [ 0x06, 0xd0 ] + - input: + bytes: [0x06, 0xd0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: [] - - - input: - bytes: [ 0x06, 0xc0 ] + - input: + bytes: [0x06, 0xc0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "rtm d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: d0 - groups: [ret, jump] - regs_write: [d0] - regs_impl_write: [d0] - - - input: - bytes: [ 0x06, 0xc0 ] + - asm_text: "rtm d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: d0 + groups: [ret, jump] + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x06, 0xc0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "dc.w $6c0" - - - input: - bytes: [ 0x06, 0xc0 ] + - asm_text: "dc.w $6c0" + - input: + bytes: [0x06, 0xc0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "dc.w $6c0" - - - input: - bytes: [ 0xf8, 0x00, 0x01, 0xc0, 0x20, 0x00 ] + - asm_text: "dc.w $6c0" + - input: + bytes: [0xf8, 0x00, 0x01, 0xc0, 0x20, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "lpstop #$2000" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x2000 - groups: [jump] - - - input: - bytes: [ 0xf8, 0x00, 0x01, 0xc0, 0x20, 0x00 ] + - asm_text: "lpstop #$2000" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x2000 + groups: [jump] + - input: + bytes: [0xf8, 0x00, 0x01, 0xc0, 0x20, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "lpstop #$2000" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x2000 - groups: [jump] - - - input: - bytes: [ 0xf8, 0x00, 0x01, 0xc0 ] + - asm_text: "lpstop #$2000" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x2000 + groups: [jump] + - input: + bytes: [0xf8, 0x00, 0x01, 0xc0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "dc.w $f800" - - - asm_text: "bset.b d0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_read: [d0] - regs_write: [d0] - regs_impl_read: [d0] - regs_impl_write: [d0] - - - input: - bytes: [ 0x4a, 0xcc ] + - asm_text: "dc.w $f800" + - asm_text: "bset.b d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x4a, 0xcc] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "pulse" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - - - input: - bytes: [ 0x4a, 0xcc ] + - asm_text: "pulse" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0x4a, 0xcc] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "dc.w $4acc" - - - input: - bytes: [ 0xf6, 0x20, 0x90, 0x00 ] + - asm_text: "dc.w $4acc" + - input: + bytes: [0xf6, 0x20, 0x90, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "move16 (a0)+, (a1)+" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC - regs_write: [a0, a1] - regs_impl_write: [a0, a1] - - - input: - bytes: [ 0xf4, 0xc8 ] + - asm_text: "move16 (a0)+, (a1)+" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR_POST_INC + - type: M68K_OP_MEM + mem: + base_reg: a1 + address_mode: M68K_AM_REGI_ADDR_POST_INC + regs_write: [a0, a1] + regs_impl_write: [a0, a1] + - input: + bytes: [0xf4, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cinvl bc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x3 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a0] - regs_impl_read: [a0] - - - input: - bytes: [ 0xf4, 0xc8 ] + - asm_text: "cinvl bc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x3 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf4, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "cinvl bc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x3 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a0] - regs_impl_read: [a0] - - - input: - bytes: [ 0xf4, 0xe8 ] + - asm_text: "cinvl bc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x3 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf4, 0xe8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cpushl bc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x3 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a0] - regs_impl_read: [a0] - - - input: - bytes: [ 0xf4, 0xe8 ] + - asm_text: "cpushl bc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x3 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf4, 0xe8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "cpushl bc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x3 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a0] - regs_impl_read: [a0] - - - input: - bytes: [ 0x0c, 0xd0, 0x00, 0x40 ] + - asm_text: "cpushl bc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x3 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x0c, 0xd0, 0x00, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas.w d0, d1, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d1 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [d0, a0] - regs_write: [d1] - regs_impl_read: [d0, a0] - regs_impl_write: [d1] - - - input: - bytes: [ 0x0c, 0xd0, 0x00, 0x40 ] + - asm_text: "cas.w d0, d1, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [d0, a0] + regs_write: [d1] + regs_impl_read: [d0, a0] + regs_impl_write: [d1] + - input: + bytes: [0x0c, 0xd0, 0x00, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "cas.w d0, d1, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d1 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [d0, a0] - regs_write: [d1] - regs_impl_read: [d0, a0] - regs_impl_write: [d1] - - - input: - bytes: [ 0x01, 0x88, 0x00, 0x10 ] + - asm_text: "cas.w d0, d1, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [d0, a0] + regs_write: [d1] + regs_impl_read: [d0, a0] + regs_impl_write: [d1] + - input: + bytes: [0x01, 0x88, 0x00, 0x10] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "movep.w d0, $10(a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG - reg: d0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_DISP - mem: - base_reg: a0 - disp: 0x10 - regs_read: [d0] - regs_impl_read: [d0] - - - input: - bytes: [ 0x01, 0x88, 0x00, 0x10 ] + - asm_text: "movep.w d0, $10(a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_DISP + mem: + base_reg: a0 + disp: 0x10 + regs_read: [d0, a0] + regs_impl_read: [d0, a0] + - input: + bytes: [0x01, 0x88, 0x00, 0x10] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "movep.w d0, $10(a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG - reg: d0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_DISP - mem: - base_reg: a0 - disp: 0x10 - regs_read: [d0] - regs_impl_read: [d0] - - - input: - bytes: [ 0x0c, 0xfc, 0x80, 0x80, 0x90, 0xc1 ] + - asm_text: "movep.w d0, $10(a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_DISP + mem: + base_reg: a0 + disp: 0x10 + regs_read: [d0, a0] + regs_impl_read: [d0, a0] + - input: + bytes: [0x0c, 0xfc, 0x80, 0x80, 0x90, 0xc1] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas2.w d0:d1,d2:d3,(a0):(a1)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d1 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d2 - reg_pair_1: d3 - - - type: M68K_OP_REG_PAIR - reg_pair_0: a0 - reg_pair_1: a1 - regs_read: [d0, d1] - regs_write: [d2, d3, a0, a1] - regs_impl_read: [d0, d1] - regs_impl_write: [d2, d3, a0, a1] - - - input: - bytes: [ 0x0c, 0xfc, 0x80, 0x80, 0x90, 0xc1 ] + - asm_text: "cas2.w d0:d1,d2:d3,(a0):(a1)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d1 + - type: M68K_OP_REG_PAIR + reg_pair_0: d2 + reg_pair_1: d3 + - type: M68K_OP_REG_PAIR + reg_pair_0: a0 + reg_pair_1: a1 + regs_read: [d0, d1] + regs_write: [d2, d3, a0, a1] + regs_impl_read: [d0, d1] + regs_impl_write: [d2, d3, a0, a1] + - input: + bytes: [0x0c, 0xfc, 0x80, 0x80, 0x90, 0xc1] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "cas2.w d0:d1,d2:d3,(a0):(a1)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d1 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d2 - reg_pair_1: d3 - - - type: M68K_OP_REG_PAIR - reg_pair_0: a0 - reg_pair_1: a1 - regs_read: [d0, d1] - regs_write: [d2, d3, a0, a1] - regs_impl_read: [d0, d1] - regs_impl_write: [d2, d3, a0, a1] - - - input: - bytes: [ 0x02, 0xd0, 0x08, 0x00 ] + - asm_text: "cas2.w d0:d1,d2:d3,(a0):(a1)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d1 + - type: M68K_OP_REG_PAIR + reg_pair_0: d2 + reg_pair_1: d3 + - type: M68K_OP_REG_PAIR + reg_pair_0: a0 + reg_pair_1: a1 + regs_read: [d0, d1] + regs_write: [d2, d3, a0, a1] + regs_impl_read: [d0, d1] + regs_impl_write: [d2, d3, a0, a1] + - input: + bytes: [0x02, 0xd0, 0x08, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "chk2.w (a0), d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: d0 - regs_read: [a0] - regs_write: [d0] - regs_impl_read: [a0] - regs_impl_write: [d0] - - - input: - bytes: [ 0x02, 0xd0, 0x08, 0x00 ] + - asm_text: "chk2.w (a0), d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d0 + regs_read: [a0] + regs_write: [d0] + regs_impl_read: [a0] + regs_impl_write: [d0] + - input: + bytes: [0x02, 0xd0, 0x08, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "chk2.w (a0), d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: d0 - regs_read: [a0] - regs_write: [d0] - regs_impl_read: [a0] - regs_impl_write: [d0] - - - input: - bytes: [ 0x02, 0xd0, 0x00, 0x00 ] + - asm_text: "chk2.w (a0), d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d0 + regs_read: [a0] + regs_write: [d0] + regs_impl_read: [a0] + regs_impl_write: [d0] + - input: + bytes: [0x02, 0xd0, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cmp2.w (a0), d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: d0 - regs_read: [a0] - regs_write: [d0] - regs_impl_read: [a0] - regs_impl_write: [d0] - - - input: - bytes: [ 0x02, 0xd0, 0x00, 0x00 ] + - asm_text: "cmp2.w (a0), d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d0 + regs_read: [a0] + regs_write: [d0] + regs_impl_read: [a0] + regs_impl_write: [d0] + - input: + bytes: [0x02, 0xd0, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "cmp2.w (a0), d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: d0 - regs_read: [a0] - regs_write: [d0] - regs_impl_read: [a0] - regs_impl_write: [d0] - - - input: - bytes: [ 0xf0, 0x10, 0xf0, 0x00 ] + - asm_text: "cmp2.w (a0), d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d0 + regs_read: [a0] + regs_write: [d0] + regs_impl_read: [a0] + regs_impl_write: [d0] + - input: + bytes: [0xf0, 0x10, 0xf0, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1000 expected: insns: - - - asm_text: "dc.w $f010" - - - asm_text: "dc.w $f000" - - - input: - bytes: [ 0x48, 0xaf, 0xff, 0xff, 0x7f, 0xff ] + - asm_text: "dc.w $f010" + - asm_text: "dc.w $f000" + - input: + bytes: [0x48, 0xaf, 0xff, 0xff, 0x7f, 0xff] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1004 expected: insns: - - - asm_text: "movem.w d0-d7/a0-a7, $7fff(a7)" - details: - regs_read: [ d0, d1, d2, d3, d4, d5, d6, d7, a0, a1, a2, a3, a4, a5, a6, a7 ] - m68k: - operands: - - - type: M68K_OP_REG_BITS - register_bits: 0xffff - - - type: M68K_OP_MEM - mem: - base_reg: a7 - disp: 0x7fff - disp_size: 1 - address_mode: M68K_AM_REGI_ADDR_DISP - - - input: - bytes: [ 0x11, 0xb0, 0x01, 0x37, 0x7f, 0xff, 0xff, 0xff, 0x12, 0x34, 0x56, 0x78, 0x01, 0x33, 0x10, 0x10, 0x10, 0x10, 0x32, 0x32, 0x32, 0x32 ] + - asm_text: "movem.w d0-d7/a0-a7, $7fff(a7)" + details: + regs_read: + [d0, d1, d2, d3, d4, d5, d6, d7, a0, a1, a2, a3, a4, a5, a6, a7] + m68k: + operands: + - type: M68K_OP_REG_BITS + register_bits: 0xffff + - type: M68K_OP_MEM + mem: + base_reg: a7 + disp: 0x7fff + disp_size: 1 + address_mode: M68K_AM_REGI_ADDR_DISP + - input: + bytes: + [ + 0x11, + 0xb0, + 0x01, + 0x37, + 0x7f, + 0xff, + 0xff, + 0xff, + 0x12, + 0x34, + 0x56, + 0x78, + 0x01, + 0x33, + 0x10, + 0x10, + 0x10, + 0x10, + 0x32, + 0x32, + 0x32, + 0x32, + ] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x100a expected: insns: - - - asm_text: "move.b ([$7fffffff, a0], d0.w, $12345678), ([$10101010, a0, d0.w], $32323232)" - details: - regs_read: [ d0, a0 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: a0 - index_reg: d0 - index_size: -1 - in_disp: 0x7fffffff - out_disp: 0x12345678 - in_disp_size: 1 - out_disp_size: 1 - address_mode: M68K_AM_MEMI_POST_INDEX - - - type: M68K_OP_MEM - mem: - base_reg: a0 - index_reg: d0 - index_size: -1 - in_disp: 0x10101010 - out_disp: 0x32323232 - in_disp_size: 1 - out_disp_size: 1 - address_mode: M68K_AM_MEMI_PRE_INDEX - - - input: - bytes: [ 0x4c, 0x00, 0x54, 0x04 ] + - asm_text: "move.b ([$7fffffff, a0], d0.w, $12345678), ([$10101010, a0, d0.w], $32323232)" + details: + regs_read: [d0, a0] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + index_reg: d0 + index_size: -1 + in_disp: 0x7fffffff + out_disp: 0x12345678 + in_disp_size: 1 + out_disp_size: 1 + address_mode: M68K_AM_MEMI_POST_INDEX + - type: M68K_OP_MEM + mem: + base_reg: a0 + index_reg: d0 + index_size: -1 + in_disp: 0x10101010 + out_disp: 0x32323232 + in_disp_size: 1 + out_disp_size: 1 + address_mode: M68K_AM_MEMI_PRE_INDEX + - input: + bytes: [0x4c, 0x00, 0x54, 0x04] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1020 expected: insns: - - - asm_text: "mulu.l d0, d4:d5" - details: - regs_read: [ d0 ] - regs_write: [ d4, d5 ] - m68k: - operands: - - - type: M68K_OP_REG - reg: d0 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d4 - reg_pair_1: d5 - - - input: - bytes: [ 0x48, 0xe7, 0xe0, 0x30 ] + - asm_text: "mulu.l d0, d4:d5" + details: + regs_read: [d0] + regs_write: [d4, d5] + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d4 + reg_pair_1: d5 + - input: + bytes: [0x48, 0xe7, 0xe0, 0x30] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1024 expected: insns: - - - asm_text: "movem.l d0-d2/a2-a3, -(a7)" - details: - regs_read: [ d0, d1, d2, a2, a3 ] - regs_write: [ a7 ] - m68k: - operands: - - - type: M68K_OP_REG_BITS - register_bits: 0xc07 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_PRE_DEC - - - input: - bytes: [ 0x4c, 0xdf, 0x0c, 0x07 ] + - asm_text: "movem.l d0-d2/a2-a3, -(a7)" + details: + regs_read: [d0, d1, d2, a2, a3] + regs_write: [a7] + m68k: + operands: + - type: M68K_OP_REG_BITS + register_bits: 0xc07 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_PRE_DEC + - input: + bytes: [0x4c, 0xdf, 0x0c, 0x07] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1028 expected: insns: - - - asm_text: "movem.l (a7)+, d0-d2/a2-a3" - details: - regs_write: [ a7, d0, d1, d2, a2, a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC - - - type: M68K_OP_REG_BITS - register_bits: 0xc07 - - - input: - bytes: [ 0xd4, 0x40 ] + - asm_text: "movem.l (a7)+, d0-d2/a2-a3" + details: + regs_write: [a7, d0, d1, d2, a2, a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a7 + address_mode: M68K_AM_REGI_ADDR_POST_INC + - type: M68K_OP_REG_BITS + register_bits: 0xc07 + - input: + bytes: [0xd4, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x102c expected: insns: - - - asm_text: "add.w d0, d2" - details: - regs_read: [ d0 ] - regs_write: [ d2 ] - m68k: - operands: - - - type: M68K_OP_REG - reg: d0 - - - type: M68K_OP_REG - reg: d2 - - - input: - bytes: [ 0x87, 0x5a ] + - asm_text: "add.w d0, d2" + details: + regs_read: [d0] + regs_write: [d2] + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d2 + - input: + bytes: [0x87, 0x5a] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x102e expected: insns: - - - asm_text: "or.w d3, (a2)+" - details: - regs_read: [ d3 ] - regs_write: [ a2 ] - m68k: - operands: - - - type: M68K_OP_REG - reg: d3 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC - - - input: - bytes: [ 0x4e, 0x71 ] + - asm_text: "or.w d3, (a2)+" + details: + regs_read: [d3] + regs_write: [a2] + m68k: + operands: + - type: M68K_OP_REG + reg: d3 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_POST_INC + - input: + bytes: [0x4e, 0x71] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1030 expected: insns: - - - asm_text: "nop" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - - - input: - bytes: [ 0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00 ] + - asm_text: "nop" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1032 expected: insns: - - - asm_text: "andi.l #$c0dec0de, $0(a4, d5.l * 4)" - details: - regs_read: [ d5, a4 ] - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xc0dec0de - - - type: M68K_OP_MEM - mem: - base_reg: a4 - index_reg: d5 - index_size: 1 - scale: 4 - disp: 0 - disp_size: -1 - address_mode: M68K_AM_AREGI_INDEX_8_BIT_DISP - - - input: - bytes: [ 0x1d, 0x80, 0x71, 0x12, 0x01, 0x23 ] + - asm_text: "andi.l #$c0dec0de, $0(a4, d5.l * 4)" + details: + regs_read: [d5, a4] + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xc0dec0de + - type: M68K_OP_MEM + mem: + base_reg: a4 + index_reg: d5 + index_size: 1 + scale: 4 + disp: 0 + disp_size: -1 + address_mode: M68K_AM_AREGI_INDEX_8_BIT_DISP + - input: + bytes: [0x1d, 0x80, 0x71, 0x12, 0x01, 0x23] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x103a expected: insns: - - - asm_text: "move.b d0, ([a6, d7.w], $123)" - details: - regs_read: [ d0, d7, a6 ] - m68k: - operands: - - - type: M68K_OP_REG - reg: d0 - - - type: M68K_OP_MEM - mem: - base_reg: a6 - index_reg: d7 - index_size: -1 - out_disp: 0x123 - out_disp_size: -1 - in_disp: 0 - address_mode: M68K_AM_MEMI_PRE_INDEX - - - input: - bytes: [ 0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56 ] + - asm_text: "move.b d0, ([a6, d7.w], $123)" + details: + regs_read: [d0, d7, a6] + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_MEM + mem: + base_reg: a6 + index_reg: d7 + index_size: -1 + out_disp: 0x123 + out_disp_size: -1 + in_disp: 0 + address_mode: M68K_AM_MEMI_PRE_INDEX + - input: + bytes: [0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1040 expected: insns: - - - asm_text: "fadd.s #3.141500, fp0" - details: - regs_write: [ fp0 ] - m68k: - operands: - - - type: M68K_OP_FP_SINGLE - simm: 3.1414999961853027 - - - type: M68K_OP_REG - reg: fp0 - - - input: - bytes: [ 0x54, 0xc5 ] + - asm_text: "fadd.s #3.141500, fp0" + details: + regs_write: [fp0] + m68k: + operands: + - type: M68K_OP_FP_SINGLE + simm: 3.1414999961853027 + - type: M68K_OP_REG + reg: fp0 + - input: + bytes: [0x54, 0xc5] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1048 expected: insns: - - - asm_text: "scc.b d5" - details: - regs_write: [ d5 ] - m68k: - operands: - - - type: M68K_OP_REG - reg: d5 - - - input: - bytes: [ 0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00 ] + - asm_text: "scc.b d5" + details: + regs_write: [d5] + m68k: + operands: + - type: M68K_OP_REG + reg: d5 + - input: + bytes: [0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x104a expected: insns: - - - asm_text: "fmove.s #1000.000000, fp0" - details: - regs_write: [ fp0 ] - m68k: - operands: - - - type: M68K_OP_FP_SINGLE - simm: 1000.000000 - - - type: M68K_OP_REG - reg: fp0 - - - input: - bytes: [ 0xf2, 0x00, 0x0a, 0x28 ] + - asm_text: "fmove.s #1000.000000, fp0" + details: + regs_write: [fp0] + m68k: + operands: + - type: M68K_OP_FP_SINGLE + simm: 1000.000000 + - type: M68K_OP_REG + reg: fp0 + - input: + bytes: [0xf2, 0x00, 0x0a, 0x28] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1052 expected: insns: - - - asm_text: "fsub fp2, fp4" - details: - regs_read: [ fp2 ] - regs_write: [ fp4 ] - m68k: - operands: - - - type: M68K_OP_REG - reg: fp2 - - - type: M68K_OP_REG - reg: fp4 - - - input: - bytes: [ 0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12 ] + - asm_text: "fsub fp2, fp4" + details: + regs_read: [fp2] + regs_write: [fp4] + m68k: + operands: + - type: M68K_OP_REG + reg: fp2 + - type: M68K_OP_REG + reg: fp4 + - input: + bytes: [0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1056 expected: insns: - - - asm_text: "jsr $12.l" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_ABSOLUTE_DATA_LONG - - - input: - bytes: [ 0x4e, 0x75 ] + - asm_text: "jsr $12.l" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_ABSOLUTE_DATA_LONG + mem: + address: 0x12 + - input: + bytes: [0x4e, 0x75] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x105c expected: insns: - - - asm_text: "rts" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - groups: [ret] - - - input: - bytes: [ 0x47, 0xf1, 0x21, 0x22, 0xff, 0xd6, 0xff, 0xa9 ] + - asm_text: "rts" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + groups: [ret] + - input: + bytes: [0x47, 0xf1, 0x21, 0x22, 0xff, 0xd6, 0xff, 0xa9] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x105e expected: insns: - - - asm_text: "lea.l ([-$2a, a1, d2.w], -$57), a3" - details: - regs_read: [ d2, a1 ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: a1 - index_reg: d2 - index_size: -1 - in_disp: -0x2a - in_disp_size: -1 - out_disp: -0x57 - out_disp_size: -1 - address_mode: M68K_AM_MEMI_PRE_INDEX - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xf1, 0x21, 0x12, 0xff, 0xa9 ] + - asm_text: "lea.l ([-$2a, a1, d2.w], -$57), a3" + details: + regs_read: [d2, a1] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a1 + index_reg: d2 + index_size: -1 + in_disp: -0x2a + in_disp_size: -1 + out_disp: -0x57 + out_disp_size: -1 + address_mode: M68K_AM_MEMI_PRE_INDEX + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xf1, 0x21, 0x12, 0xff, 0xa9] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1066 expected: insns: - - - asm_text: "lea.l ([a1, d2.w], -$57), a3" - details: - regs_read: [ d2, a1 ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: a1 - index_reg: d2 - index_size: -1 - in_disp: 0 - out_disp: -0x57 - out_disp_size: -1 - address_mode: M68K_AM_MEMI_PRE_INDEX - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xf1, 0x21, 0x21, 0xff, 0xd6 ] + - asm_text: "lea.l ([a1, d2.w], -$57), a3" + details: + regs_read: [d2, a1] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a1 + index_reg: d2 + index_size: -1 + in_disp: 0 + out_disp: -0x57 + out_disp_size: -1 + address_mode: M68K_AM_MEMI_PRE_INDEX + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xf1, 0x21, 0x21, 0xff, 0xd6] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x106c expected: insns: - - - asm_text: "lea.l ([-$2a, a1, d2.w]), a3" - details: - regs_read: [ d2, a1 ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: a1 - index_reg: d2 - index_size: -1 - in_disp: -0x2a - in_disp_size: -1 - out_disp: 0 - out_disp_size: -1 - address_mode: M68K_AM_MEMI_PRE_INDEX - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xf1, 0x21, 0x26, 0xff, 0xd6, 0xff, 0xa9 ] + - asm_text: "lea.l ([-$2a, a1, d2.w]), a3" + details: + regs_read: [d2, a1] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a1 + index_reg: d2 + index_size: -1 + in_disp: -0x2a + in_disp_size: -1 + out_disp: 0 + out_disp_size: -1 + address_mode: M68K_AM_MEMI_PRE_INDEX + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xf1, 0x21, 0x26, 0xff, 0xd6, 0xff, 0xa9] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1072 expected: insns: - - - asm_text: "lea.l ([-$2a, a1], d2.w, -$57), a3" - details: - regs_read: [ d2, a1 ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: a1 - index_reg: d2 - index_size: -1 - in_disp: -0x2a - in_disp_size: -1 - out_disp: -0x57 - out_disp_size: -1 - address_mode: M68K_AM_MEMI_POST_INDEX - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xf1, 0x21, 0x20, 0xff, 0xd6 ] + - asm_text: "lea.l ([-$2a, a1], d2.w, -$57), a3" + details: + regs_read: [d2, a1] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a1 + index_reg: d2 + index_size: -1 + in_disp: -0x2a + in_disp_size: -1 + out_disp: -0x57 + out_disp_size: -1 + address_mode: M68K_AM_MEMI_POST_INDEX + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xf1, 0x21, 0x20, 0xff, 0xd6] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x107a expected: insns: - - - asm_text: "lea.l -$2a(a1, d2.w), a3" - details: - regs_read: [ d2, a1 ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: a1 - index_reg: d2 - index_size: -1 - in_disp: -0x2a - out_disp: 0 - in_disp_size: -1 - out_disp_size: -1 - address_mode: M68K_AM_AREGI_INDEX_BASE_DISP - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xfb, 0x21, 0x20, 0xf9, 0xce ] + - asm_text: "lea.l -$2a(a1, d2.w), a3" + details: + regs_read: [d2, a1] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a1 + index_reg: d2 + index_size: -1 + in_disp: -0x2a + out_disp: 0 + in_disp_size: -1 + out_disp_size: -1 + address_mode: M68K_AM_AREGI_INDEX_BASE_DISP + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xfb, 0x21, 0x20, 0xf9, 0xce] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1080 expected: insns: - - - asm_text: "lea.l $a50(pc, d2.w), a3" - details: - regs_read: [ d2, pc ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: pc - index_reg: d2 - index_size: -1 - in_disp: -0x632 - out_disp: 0 - in_disp_size: -1 - address_mode: M68K_AM_PCI_INDEX_BASE_DISP - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xfb, 0x21, 0x30, 0xff, 0xff, 0xf9, 0xc8 ] + - asm_text: "lea.l $a50(pc, d2.w), a3" + details: + regs_read: [d2, pc] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: pc + index_reg: d2 + index_size: -1 + in_disp: -0x632 + out_disp: 0 + in_disp_size: -1 + address_mode: M68K_AM_PCI_INDEX_BASE_DISP + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xfb, 0x21, 0x30, 0xff, 0xff, 0xf9, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1086 expected: insns: - - - asm_text: "lea.l $a50(pc, d2.w), a3" - details: - regs_read: [ d2, pc ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: pc - index_reg: d2 - index_size: -1 - in_disp: -0x638 - out_disp: 0 - in_disp_size: 1 - address_mode: M68K_AM_PCI_INDEX_BASE_DISP - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xfb, 0x01, 0x70, 0xff, 0xff, 0xf9, 0xc0 ] + - asm_text: "lea.l $a50(pc, d2.w), a3" + details: + regs_read: [d2, pc] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: pc + index_reg: d2 + index_size: -1 + in_disp: -0x638 + out_disp: 0 + in_disp_size: 1 + address_mode: M68K_AM_PCI_INDEX_BASE_DISP + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xfb, 0x01, 0x70, 0xff, 0xff, 0xf9, 0xc0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x108e expected: insns: - - - asm_text: "lea.l $a50(pc), a3" - details: - regs_read: [ pc ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - base_reg: pc - index_size: -1 - in_disp: -0x640 - in_disp_size: 1 - address_mode: M68K_AM_PCI_INDEX_BASE_DISP - - - type: M68K_OP_REG - reg: a3 - - - input: - bytes: [ 0x47, 0xf0, 0x29, 0xa0, 0xff, 0xd6 ] + - asm_text: "lea.l $a50(pc), a3" + details: + regs_read: [pc] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: pc + index_size: -1 + in_disp: -0x640 + in_disp_size: 1 + address_mode: M68K_AM_PCI_INDEX_BASE_DISP + - type: M68K_OP_REG + reg: a3 + - input: + bytes: [0x47, 0xf0, 0x29, 0xa0, 0xff, 0xd6] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x1096 expected: insns: - - - asm_text: "lea.l -$2a(d2.l), a3" - details: - regs_read: [ d2 ] - regs_write: [ a3 ] - m68k: - operands: - - - type: M68K_OP_MEM - mem: - index_reg: d2 - index_size: 1 - disp: 0 - disp_size: -1 - address_mode: M68K_AM_AREGI_INDEX_BASE_DISP - - - type: M68K_OP_REG - reg: a3 + - asm_text: "lea.l -$2a(d2.l), a3" + details: + regs_read: [d2] + regs_write: [a3] + m68k: + operands: + - type: M68K_OP_MEM + mem: + index_reg: d2 + index_size: 1 + disp: 0 + disp_size: -1 + address_mode: M68K_AM_AREGI_INDEX_BASE_DISP + - type: M68K_OP_REG + reg: a3 # ========================================================================== # 68040/060 PFLUSH variants (Line-F 0xF5xx) @@ -1188,131 +1048,115 @@ test_cases: # --- PFLUSHN (An) : opcode = 0xF500 | reg (mask FFF8, match F500) --- # PFLUSHN flushes non-global ATC entries matching (An) - - - input: - bytes: [ 0xf5, 0x00 ] + - input: + bytes: [0xf5, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "pflushn (a0)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - input: - bytes: [ 0xf5, 0x03 ] + - asm_text: "pflushn (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf5, 0x03] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "pflushn (a3)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "pflushn (a3)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # --- PFLUSH (An) : opcode = 0xF508 | reg (mask FFF8, match F508) --- # PFLUSH flushes all ATC entries matching (An) - - - input: - bytes: [ 0xf5, 0x08 ] + - input: + bytes: [0xf5, 0x08] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "pflush (a0)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - input: - bytes: [ 0xf5, 0x0d ] + - asm_text: "pflush (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xf5, 0x0d] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "pflush (a5)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "pflush (a5)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # --- PFLUSHAN : opcode = 0xF510 (mask FFF8, match F510) --- # PFLUSHAN flushes all non-global ATC entries - - - input: - bytes: [ 0xf5, 0x10 ] + - input: + bytes: [0xf5, 0x10] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "pflushan" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - - - input: - bytes: [ 0xf5, 0x10 ] + - asm_text: "pflushan" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0xf5, 0x10] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "pflushan" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU + - asm_text: "pflushan" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU # --- PFLUSHA : opcode = 0xF518 (mask FFF8, match F518) --- # PFLUSHA flushes all ATC entries - - - input: - bytes: [ 0xf5, 0x18 ] + - input: + bytes: [0xf5, 0x18] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "pflusha" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - - - input: - bytes: [ 0xf5, 0x18 ] + - asm_text: "pflusha" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0xf5, 0x18] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "pflusha" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU + - asm_text: "pflusha" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU # ========================================================================== # 68040 PTEST instructions (Line-F 0xF5xx) @@ -1320,72 +1164,60 @@ test_cases: # ========================================================================== # --- PTESTW (An) : opcode = 0xF548 | reg (mask FFF8, match F548) --- - - - input: - bytes: [ 0xf5, 0x48 ] + - input: + bytes: [0xf5, 0x48] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "ptestw (a0)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - input: - bytes: [ 0xf5, 0x4f ] + - asm_text: "ptestw (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xf5, 0x4f] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "ptestw (a7)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "ptestw (a7)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # --- PTESTR (An) : opcode = 0xF568 | reg (mask FFF8, match F568) --- - - - input: - bytes: [ 0xf5, 0x68 ] + - input: + bytes: [0xf5, 0x68] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "ptestr (a0)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - input: - bytes: [ 0xf5, 0x6c ] + - asm_text: "ptestr (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xf5, 0x6c] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "ptestr (a4)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "ptestr (a4)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # ========================================================================== # 68060 PLPA instructions (Line-F 0xF5xx) @@ -1393,108 +1225,92 @@ test_cases: # ========================================================================== # --- PLPAW (An) : opcode = 0xF588 | reg (mask FFF8, match F588) --- - - - input: - bytes: [ 0xf5, 0x88 ] + - input: + bytes: [0xf5, 0x88] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "plpaw (a0)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - input: - bytes: [ 0xf5, 0x8e ] + - asm_text: "plpaw (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xf5, 0x8e] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "plpaw (a6)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "plpaw (a6)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # --- PLPAR (An) : opcode = 0xF5C8 | reg (mask FFF8, match F5C8) --- - - - input: - bytes: [ 0xf5, 0xc8 ] + - input: + bytes: [0xf5, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "plpar (a0)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - input: - bytes: [ 0xf5, 0xcf ] + - asm_text: "plpar (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xf5, 0xcf] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "plpar (a7)" - details: - m68k: - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "plpar (a7)" + details: + m68k: + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # ========================================================================== # HALT instruction (68060 + ColdFire) # Opcode = 0x4AC8 # ========================================================================== - - - input: - bytes: [ 0x4a, 0xc8 ] + - input: + bytes: [0x4a, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "halt" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU + - asm_text: "halt" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU # ========================================================================== # BGND instruction (CPU32 only) # Opcode = 0x4AFA (enter background debug mode) # ========================================================================== - - - input: - bytes: [ 0x4a, 0xfa ] + - input: + bytes: [0x4a, 0xfa] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "bgnd" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU + - asm_text: "bgnd" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU # ========================================================================== # CPU32 Table Lookup instructions (TBLS, TBLU, TBLSN, TBLUN) @@ -1515,141 +1331,121 @@ test_cases: # ========================================================================== # TBLU.W (A0),D0 : word=F810, ext=0140 - - - input: - bytes: [ 0xf8, 0x10, 0x01, 0x40 ] + - input: + bytes: [0xf8, 0x10, 0x01, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "tblu.w (a0), d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_read: [a0] - regs_write: [d0] - regs_impl_read: [a0] - regs_impl_write: [d0] + - asm_text: "tblu.w (a0), d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [a0] + regs_write: [d0] + regs_impl_read: [a0] + regs_impl_write: [d0] # TBLS.L (A2),D3 : word=F812, ext=3980 - - - input: - bytes: [ 0xf8, 0x12, 0x39, 0x80 ] + - input: + bytes: [0xf8, 0x12, 0x39, 0x80] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "tbls.l (a2), d3" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_fpu: M68K_FPU_SIZE_SINGLE - op_size_cpu: M68K_CPU_SIZE_LONG - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d3 - regs_read: [a2] - regs_write: [d3] - regs_impl_read: [a2] - regs_impl_write: [d3] + - asm_text: "tbls.l (a2), d3" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d3 + regs_read: [a2] + regs_write: [d3] + regs_impl_read: [a2] + regs_impl_write: [d3] # TBLUN.B (A1),D2 : word=F811, ext=2500 - - - input: - bytes: [ 0xf8, 0x11, 0x25, 0x00 ] + - input: + bytes: [0xf8, 0x11, 0x25, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "tblun.b (a1), d2" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d2 - regs_read: [a1] - regs_write: [d2] - regs_impl_read: [a1] - regs_impl_write: [d2] + - asm_text: "tblun.b (a1), d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d2 + regs_read: [a1] + regs_write: [d2] + regs_impl_read: [a1] + regs_impl_write: [d2] # TBLSN.W (A4),D5 : word=F814, ext=5D40 - - - input: - bytes: [ 0xf8, 0x14, 0x5d, 0x40 ] + - input: + bytes: [0xf8, 0x14, 0x5d, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "tblsn.w (a4), d5" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d5 - regs_read: [a4] - regs_write: [d5] - regs_impl_read: [a4] - regs_impl_write: [d5] + - asm_text: "tblsn.w (a4), d5" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d5 + regs_read: [a4] + regs_write: [d5] + regs_impl_read: [a4] + regs_impl_write: [d5] # TBLU.W D1:D2,D3 (register form) : word=F801, ext=3042 - - - input: - bytes: [ 0xf8, 0x01, 0x30, 0x42 ] + - input: + bytes: [0xf8, 0x01, 0x30, 0x42] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "tblu.w d1:d2, d3" + - asm_text: "tblu.w d1:d2, d3" # TBLS.B D4:D5,D6 (register form) : word=F804, ext=6805 - - - input: - bytes: [ 0xf8, 0x04, 0x68, 0x05 ] + - input: + bytes: [0xf8, 0x04, 0x68, 0x05] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "tbls.b d4:d5, d6" + - asm_text: "tbls.b d4:d5, d6" # ========================================================================== # 68030 PMMU coprocessor instructions (CpID=0, Line-F 0xF0xx) @@ -1657,360 +1453,307 @@ test_cases: # ========================================================================== # PMOVE (A0),TC : word=F010, ext=4000 (direction=0 → EA first: memory to register) - - - input: - bytes: [ 0xf0, 0x10, 0x40, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x40, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove (a0), tc" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: tc - regs_read: [a0] - regs_write: [tc] - regs_impl_read: [a0] - regs_impl_write: [tc] + - asm_text: "pmove (a0), tc" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: tc + regs_read: [a0] + regs_write: [tc] + regs_impl_read: [a0] + regs_impl_write: [tc] # --- PMOVE TC,(A0) : move Translation Control register to memory --- # Ext word: 0x4200 (direction=1 → reg first: register to EA) # From binutils: pmove, two(0xf000,0x4200), two(0xffc0,0xffff), "08%s" - - - input: - bytes: [ 0xf0, 0x10, 0x42, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x42, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove tc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: tc - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [tc, a0] - regs_impl_read: [tc, a0] + - asm_text: "pmove tc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: tc + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [tc, a0] + regs_impl_read: [tc, a0] # --- PMOVE (A1),SRP : move memory to Supervisor Root Pointer --- # SRP is register code 100 in bits 12-10 of ext word # Ext word 0x4800: direction=0 → EA first (memory to register) # First word: 0xF011 (F000 | EA for (A1) = 010_001) - - - input: - bytes: [ 0xf0, 0x11, 0x48, 0x00 ] + - input: + bytes: [0xf0, 0x11, 0x48, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove (a1), srp" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: srp - regs_read: [a1] - regs_write: [srp] - regs_impl_read: [a1] - regs_impl_write: [srp] + - asm_text: "pmove (a1), srp" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: srp + regs_read: [a1] + regs_write: [srp] + regs_impl_read: [a1] + regs_impl_write: [srp] # --- PMOVE (A2),CRP : move memory to CPU Root Pointer --- # CRP is register code 101 in bits 12-10 → ext = 0x4C00 # Ext word 0x4C00: direction=0 → EA first (memory to register) # First word: 0xF012 (F000 | EA for (A2) = 010_010) - - - input: - bytes: [ 0xf0, 0x12, 0x4c, 0x00 ] + - input: + bytes: [0xf0, 0x12, 0x4c, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove (a2), crp" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: crp - regs_read: [a2] - regs_write: [crp] - regs_impl_read: [a2] - regs_impl_write: [crp] + - asm_text: "pmove (a2), crp" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: crp + regs_read: [a2] + regs_write: [crp] + regs_impl_read: [a2] + regs_impl_write: [crp] # --- PMOVE (A0),MMUSR : move memory to MMU Status Register --- # MMUSR is register code 110 → ext = 0x6000 (direction=0 → EA first) # From binutils: pmove, two(0xf000,0x6000), two(0xffc0,0xffff), "*w18" - - - input: - bytes: [ 0xf0, 0x10, 0x60, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x60, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove (a0), mmusr" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: mmusr - regs_read: [a0] - regs_write: [mmusr] - regs_impl_read: [a0] - regs_impl_write: [mmusr] + - asm_text: "pmove (a0), mmusr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: mmusr + regs_read: [a0] + regs_write: [mmusr] + regs_impl_read: [a0] + regs_impl_write: [mmusr] # --- PMOVE (A0),TT0 : move memory to Transparent Translation Register 0 --- # From binutils: pmovefd, two(0xf000,0x0100), two(0xffc0,0xe3ff) # TT0 = register 010 → ext word bits 12-10 = 010 # Ext: 0x0800 (direction=0 → EA first: memory to register) - - - input: - bytes: [ 0xf0, 0x10, 0x08, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x08, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove (a0), tt0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: tt0 - regs_read: [a0] - regs_write: [tt0] - regs_impl_read: [a0] - regs_impl_write: [tt0] + - asm_text: "pmove (a0), tt0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: tt0 + regs_read: [a0] + regs_write: [tt0] + regs_impl_read: [a0] + regs_impl_write: [tt0] # --- PMOVE (A0),TT1 : move memory to Transparent Translation Register 1 --- # TT1 = register 011 → ext = 0x0C00 (direction=0 → EA first) - - - input: - bytes: [ 0xf0, 0x10, 0x0c, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x0c, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pmove (a0), tt1" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_REG - reg: tt1 - regs_read: [a0] - regs_write: [tt1] - regs_impl_read: [a0] - regs_impl_write: [tt1] + - asm_text: "pmove (a0), tt1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: tt1 + regs_read: [a0] + regs_write: [tt1] + regs_impl_read: [a0] + regs_impl_write: [tt1] # --- PFLUSH (68030 variant) --- # From binutils: pflush, two(0xf000,0x3800), two(0xffc0,0xfe1e) # Format: F000|EA, 001 FC mask 0 (An) # ext = 0x3800 (fc=0x00 → SFC register via pmmu_decode_fc, mask=0) - - - input: - bytes: [ 0xf0, 0x10, 0x38, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x38, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pflush sfc, #$0, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: sfc - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [sfc, a0] - regs_impl_read: [sfc, a0] + - asm_text: "pflush sfc, #$0, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: sfc + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [sfc, a0] + regs_impl_read: [sfc, a0] # --- PFLUSHA (68030 variant) --- # From binutils: pflusha, two(0xf000,0x2400), two(0xffff,0xffff) - - - input: - bytes: [ 0xf0, 0x00, 0x24, 0x00 ] + - input: + bytes: [0xf0, 0x00, 0x24, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "pflusha" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU + - asm_text: "pflusha" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU # --- PLOADW fc,(ea) (68030) --- # From binutils: ploadw, two(0xf000,0x2000), two(0xffc0,0xfffe), "f3&s" # PLOADW #1,(A0) : FC=#1 encoded as immediate in bits # ext = 0x2000 | (FC encoding) # For FC = SFC (function code source = 000): ext = 0x2000 - - - input: - bytes: [ 0xf0, 0x10, 0x20, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x20, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "ploadw sfc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: sfc - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [sfc, a0] - regs_impl_read: [sfc, a0] + - asm_text: "ploadw sfc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: sfc + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [sfc, a0] + regs_impl_read: [sfc, a0] # --- PLOADR fc,(ea) (68030) --- # From binutils: ploadr, two(0xf000,0x2200), two(0xffc0,0xfffe), "f3&s" # ext = 0x2200 | FC - - - input: - bytes: [ 0xf0, 0x10, 0x22, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x22, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "ploadr sfc, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: sfc - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [sfc, a0] - regs_impl_read: [sfc, a0] + - asm_text: "ploadr sfc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: sfc + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [sfc, a0] + regs_impl_read: [sfc, a0] # --- PTESTW fc,(ea),#level (68030) --- # From binutils: ptestw, two(0xf000,0x8000), two(0xffc0,0xe3fe), "f3&st8" # ext word = 0x8000 | (level<<10) | FC # PTESTW SFC,(A0),#7 : ext = 0x8000 | (7<<10) | 0 = 0x9C00 - - - input: - bytes: [ 0xf0, 0x10, 0x9c, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x9c, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "ptestw sfc, (a0), #$7" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: sfc - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x7 - regs_read: [sfc, a0] - regs_impl_read: [sfc, a0] + - asm_text: "ptestw sfc, (a0), #$7" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: sfc + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x7 + regs_read: [sfc, a0] + regs_impl_read: [sfc, a0] # --- PTESTR fc,(ea),#level (68030) --- # From binutils: ptestr, two(0xf000,0x8200), two(0xffc0,0xe3fe), "f3&st8" # ext word = 0x8200 | (level<<10) | FC # PTESTR SFC,(A0),#7 : ext = 0x8200 | (7<<10) | 0 = 0x9E00 - - - input: - bytes: [ 0xf0, 0x10, 0x9e, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x9e, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "ptestr sfc, (a0), #$7" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: sfc - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x7 - regs_read: [sfc, a0] - regs_impl_read: [sfc, a0] + - asm_text: "ptestr sfc, (a0), #$7" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: sfc + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x7 + regs_read: [sfc, a0] + regs_impl_read: [sfc, a0] # ========================================================================== # Variant-exclusion tests @@ -2018,1505 +1761,1258 @@ test_cases: # ========================================================================== # PFLUSH 040 encoding should be invalid on 68030 (it's a different format) - - - input: - bytes: [ 0xf5, 0x08 ] + - input: + bytes: [0xf5, 0x08] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "dc.w $f508" + - asm_text: "dc.w $f508" # PFLUSH 040 encoding should be invalid on 68000 - - - input: - bytes: [ 0xf5, 0x08 ] + - input: + bytes: [0xf5, 0x08] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f508" + - asm_text: "dc.w $f508" # PFLUSHA 040 encoding should be invalid on 68020 - - - input: - bytes: [ 0xf5, 0x18 ] + - input: + bytes: [0xf5, 0x18] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "dc.w $f518" + - asm_text: "dc.w $f518" # PTESTW is 68040 only, should be invalid on 68060 - - - input: - bytes: [ 0xf5, 0x48 ] + - input: + bytes: [0xf5, 0x48] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "dc.w $f548" + - asm_text: "dc.w $f548" # PTESTR is 68040 only, should be invalid on 68060 - - - input: - bytes: [ 0xf5, 0x68 ] + - input: + bytes: [0xf5, 0x68] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "dc.w $f568" + - asm_text: "dc.w $f568" # PLPAR/PLPAW are 68060 only, should be invalid on 68040 - - - input: - bytes: [ 0xf5, 0xc8 ] + - input: + bytes: [0xf5, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "dc.w $f5c8" - - - input: - bytes: [ 0xf5, 0x88 ] + - asm_text: "dc.w $f5c8" + - input: + bytes: [0xf5, 0x88] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "dc.w $f588" + - asm_text: "dc.w $f588" # HALT should be invalid on 68040 - - - input: - bytes: [ 0x4a, 0xc8 ] + - input: + bytes: [0x4a, 0xc8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: [] # BGND should be invalid on 68060 - - - input: - bytes: [ 0x4a, 0xfa ] + - input: + bytes: [0x4a, 0xfa] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: [] # BGND should be invalid on 68000 - - - input: - bytes: [ 0x4a, 0xfa ] + - input: + bytes: [0x4a, 0xfa] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: [] # TBLU encoding on 68060 should not decode as TBLU (CPU32 only) - - - input: - bytes: [ 0xf8, 0x10, 0x01, 0x40 ] + - input: + bytes: [0xf8, 0x10, 0x01, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "dc.w $f810" - - - asm_text: "bchg.b d0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_read: [d0] - regs_write: [d0] - regs_impl_read: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $f810" + - asm_text: "bchg.b d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] # 68030 PMOVE should not work on 68000 - - - input: - bytes: [ 0xf0, 0x10, 0x40, 0x00 ] + - input: + bytes: [0xf0, 0x10, 0x40, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f010" - - - asm_text: "negx.b d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $f010" + - asm_text: "negx.b d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # Regression: btst with immediate bit number and high-byte != 0 - - - input: - bytes: [ 0x08, 0x00, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x00, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "btst.b #$f0, d0" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_REG + - asm_text: "btst.b #$f0, d0" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_REG - - - input: - bytes: [ 0x08, 0x1e, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x1e, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "btst.b #$f0, (a6)+" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_POST_INC + - asm_text: "btst.b #$f0, (a6)+" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_POST_INC - - - input: - bytes: [ 0x08, 0x24, 0xff, 0xf8 ] + - input: + bytes: [0x08, 0x24, 0xff, 0xf8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "btst.b #$f8, -(a4)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf8 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_PRE_DEC + - asm_text: "btst.b #$f8, -(a4)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf8 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_PRE_DEC # Regression: bchg with immediate bit number - - - input: - bytes: [ 0x08, 0x51, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x51, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "bchg.b #$f0, (a1)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "bchg.b #$f0, (a1)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # Regression: bclr with immediate bit number - - - input: - bytes: [ 0x08, 0x91, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x91, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "bclr.b #$f0, (a1)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "bclr.b #$f0, (a1)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # Regression: bset with immediate bit number - - - input: - bytes: [ 0x08, 0xd1, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0xd1, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "bset.b #$f0, (a1)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR + - asm_text: "bset.b #$f0, (a1)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR # Regression: ori.b to ccr with high-byte != 0 - - - input: - bytes: [ 0x00, 0x3c, 0xff, 0xe8 ] + - input: + bytes: [0x00, 0x3c, 0xff, 0xe8] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "ori.b #$e8, ccr" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xe8 - - - type: M68K_OP_REG + - asm_text: "ori.b #$e8, ccr" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xe8 + - type: M68K_OP_REG # Regression: andi.b to ccr with high-byte != 0 - - - input: - bytes: [ 0x02, 0x3c, 0xff, 0x00 ] + - input: + bytes: [0x02, 0x3c, 0xff, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "andi.b #$0, ccr" - details: - m68k: - operands: - - - type: M68K_OP_IMM - - - type: M68K_OP_REG + - asm_text: "andi.b #$0, ccr" + details: + m68k: + operands: + - type: M68K_OP_IMM + - type: M68K_OP_REG # Regression: eori.b to ccr with high-byte != 0 - - - input: - bytes: [ 0x0a, 0x3c, 0xff, 0x00 ] + - input: + bytes: [0x0a, 0x3c, 0xff, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "eori.b #$0, ccr" - details: - m68k: - operands: - - - type: M68K_OP_IMM - - - type: M68K_OP_REG + - asm_text: "eori.b #$0, ccr" + details: + m68k: + operands: + - type: M68K_OP_IMM + - type: M68K_OP_REG # Regression: btst/bchg/bclr/bset should also work on 68040 - - - input: - bytes: [ 0x08, 0x00, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x00, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "btst.b #$f0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0xf0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "btst.b #$f0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] - - - input: - bytes: [ 0x08, 0x00, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x00, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_060] address: 0x0 expected: insns: - - - asm_text: "btst.b #$f0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0xf0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "btst.b #$f0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] - - - input: - bytes: [ 0x08, 0x00, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x00, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "btst.b #$f0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0xf0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "btst.b #$f0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # Regression: bchg/bclr/bset should also work on 68040 and CPU32 with high-byte immediate - - - input: - bytes: [ 0x08, 0x51, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x51, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "bchg.b #$f0, (a1)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM + - asm_text: "bchg.b #$f0, (a1)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM - - - input: - bytes: [ 0x08, 0x51, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x51, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "bchg.b #$f0, (a1)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a1] - regs_impl_read: [a1] + - asm_text: "bchg.b #$f0, (a1)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [a1] + regs_impl_read: [a1] - - - input: - bytes: [ 0x08, 0x91, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x91, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "bclr.b #$f0, (a1)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM + - asm_text: "bclr.b #$f0, (a1)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM - - - input: - bytes: [ 0x08, 0x91, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0x91, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "bclr.b #$f0, (a1)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a1] - regs_impl_read: [a1] + - asm_text: "bclr.b #$f0, (a1)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [a1] + regs_impl_read: [a1] - - - input: - bytes: [ 0x08, 0xd1, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0xd1, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "bset.b #$f0, (a1)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xf0 - - - type: M68K_OP_MEM + - asm_text: "bset.b #$f0, (a1)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xf0 + - type: M68K_OP_MEM - - - input: - bytes: [ 0x08, 0xd1, 0xff, 0xf0 ] + - input: + bytes: [0x08, 0xd1, 0xff, 0xf0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "bset.b #$f0, (a1)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0xf0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [a1] - regs_impl_read: [a1] + - asm_text: "bset.b #$f0, (a1)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [a1] + regs_impl_read: [a1] - - - input: - bytes: [ 0x02, 0x3c, 0xff, 0x1f ] + - input: + bytes: [0x02, 0x3c, 0xff, 0x1f] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "andi.b #$1f, ccr" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0x1f - - - type: M68K_OP_REG - reg: ccr + - asm_text: "andi.b #$1f, ccr" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x1f + - type: M68K_OP_REG + reg: ccr - - - input: - bytes: [ 0x0a, 0x3c, 0xff, 0xab ] + - input: + bytes: [0x0a, 0x3c, 0xff, 0xab] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "eori.b #$ab, ccr" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xab - - - type: M68K_OP_REG - reg: ccr + - asm_text: "eori.b #$ab, ccr" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xab + - type: M68K_OP_REG + reg: ccr # Regression: CAS.l should be invalid on CPU32 - - - input: - bytes: [ 0x0e, 0xee, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0e, 0xee, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $eee" - - - asm_text: "ori.b #$0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $eee" + - asm_text: "ori.b #$0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # CAS.l should still work on 68040 - - - input: - bytes: [ 0x0e, 0xee, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0e, 0xee, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas.l d0, d0, $0(a6)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_fpu: M68K_FPU_SIZE_SINGLE - op_size_cpu: M68K_CPU_SIZE_LONG - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_DISP - mem: - base_reg: a6 - disp_size: 1 - regs_read: [d0] - regs_write: [d0] - regs_impl_read: [d0] - regs_impl_write: [d0] + - asm_text: "cas.l d0, d0, $0(a6)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_DISP + mem: + base_reg: a6 + disp_size: 1 + regs_read: [d0, a6] + regs_write: [d0] + regs_impl_read: [d0, a6] + regs_impl_write: [d0] # Regression: CAS.b should be invalid on CPU32 - - - input: - bytes: [ 0x0a, 0xd0, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0a, 0xd0, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $ad0" - - - asm_text: "ori.b #$0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $ad0" + - asm_text: "ori.b #$0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # CAS.b should still work on 68040 - - - input: - bytes: [ 0x0a, 0xd0, 0x00, 0x00 ] + - input: + bytes: [0x0a, 0xd0, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas.b d0, d0, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [d0, a0] - regs_write: [d0] - regs_impl_read: [d0, a0] - regs_impl_write: [d0] + - asm_text: "cas.b d0, d0, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [d0, a0] + regs_write: [d0] + regs_impl_read: [d0, a0] + regs_impl_write: [d0] # Regression: CAS.w should be invalid on CPU32 - - - input: - bytes: [ 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0c, 0xd0, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $cd0" - - - asm_text: "ori.b #$0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $cd0" + - asm_text: "ori.b #$0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # CAS.w should still work on 68040 - - - input: - bytes: [ 0x0c, 0xd0, 0x00, 0x00 ] + - input: + bytes: [0x0c, 0xd0, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas.w d0, d0, (a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR - regs_read: [d0, a0] - regs_write: [d0] - regs_impl_read: [d0, a0] - regs_impl_write: [d0] + - asm_text: "cas.w d0, d0, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR + regs_read: [d0, a0] + regs_write: [d0] + regs_impl_read: [d0, a0] + regs_impl_write: [d0] # Regression: CAS2.w should be invalid on CPU32 - - - input: - bytes: [ 0x0c, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0c, 0xfc, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $cfc" - - - asm_text: "ori.b #$0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $cfc" + - asm_text: "ori.b #$0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # CAS2.w should still work on 68040 - - - input: - bytes: [ 0x0c, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0c, 0xfc, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas2.w d0:d0,d0:d0,(d0):(d0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d0 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d0 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d0 - regs_read: [d0] - regs_write: [d0] - regs_impl_read: [d0] - regs_impl_write: [d0] + - asm_text: "cas2.w d0:d0,d0:d0,(d0):(d0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] # Regression: CAS2.l should be invalid on CPU32 - - - input: - bytes: [ 0x0e, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0e, 0xfc, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $efc" - - - asm_text: "ori.b #$0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $efc" + - asm_text: "ori.b #$0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # CAS2.l should still work on 68040 - - - input: - bytes: [ 0x0e, 0xfc, 0x00, 0x00, 0x00, 0x00 ] + - input: + bytes: [0x0e, 0xfc, 0x00, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "cas2.l d0:d0,d0:d0,(d0):(d0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_fpu: M68K_FPU_SIZE_SINGLE - op_size_cpu: M68K_CPU_SIZE_LONG - operands: - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d0 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d0 - - - type: M68K_OP_REG_PAIR - reg_pair_0: d0 - reg_pair_1: d0 - regs_read: [d0] - regs_write: [d0] - regs_impl_read: [d0] - regs_impl_write: [d0] + - asm_text: "cas2.l d0:d0,d0:d0,(d0):(d0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d0 + reg_pair_1: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] # Bug 1: SBCD memory-to-memory should not read extra immediate - - - input: - bytes: [ 0x8f, 0x08 ] + - input: + bytes: [0x8f, 0x08] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "sbcd.b -(a0), -(a7)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REGI_ADDR_PRE_DEC - reg: a0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REGI_ADDR_PRE_DEC - reg: a7 - regs_read: [a0] - regs_write: [a7] - regs_impl_read: [a0] - regs_impl_write: [a7] + - asm_text: "sbcd.b -(a0), -(a7)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REGI_ADDR_PRE_DEC + reg: a0 + - type: M68K_OP_REG + address_mode: M68K_AM_REGI_ADDR_PRE_DEC + reg: a7 + regs_read: [a0] + regs_write: [a7] + regs_impl_read: [a0] + regs_impl_write: [a7] # Bug 2: PACK should be invalid on CPU32 - - - input: - bytes: [ 0x83, 0x40 ] + - input: + bytes: [0x83, 0x40] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $8340" + - asm_text: "dc.w $8340" # Bug 2: PACK should work on 68020 - - - input: - bytes: [ 0x83, 0x40, 0x00, 0x01 ] + - input: + bytes: [0x83, 0x40, 0x00, 0x01] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "pack d0, d1, #$1" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d1 - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x1 - regs_read: [d0] - regs_write: [d1] - regs_impl_read: [d0] - regs_impl_write: [d1] + - asm_text: "pack d0, d1, #$1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + regs_read: [d0] + regs_write: [d1] + regs_impl_read: [d0] + regs_impl_write: [d1] # Bug 2: UNPK should be invalid on CPU32 - - - input: - bytes: [ 0x83, 0x80 ] + - input: + bytes: [0x83, 0x80] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $8380" + - asm_text: "dc.w $8380" # Bug 2: UNPK should work on 68020 - - - input: - bytes: [ 0x83, 0x80, 0x00, 0x01 ] + - input: + bytes: [0x83, 0x80, 0x00, 0x01] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "unpk d0, d1, #$1" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d1 - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x1 - regs_read: [d0] - regs_write: [d1] - regs_impl_read: [d0] - regs_impl_write: [d1] + - asm_text: "unpk d0, d1, #$1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + regs_read: [d0] + regs_write: [d1] + regs_impl_read: [d0] + regs_impl_write: [d1] # Bug 3: CHK.L should be invalid on CPU32 - - - input: - bytes: [ 0x41, 0x00 ] + - input: + bytes: [0x41, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $4100" + - asm_text: "dc.w $4100" # Bug 3: CHK.L should work on 68020 - - - input: - bytes: [ 0x41, 0x00 ] + - input: + bytes: [0x41, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "chk.l d0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_fpu: M68K_FPU_SIZE_SINGLE - op_size_cpu: M68K_CPU_SIZE_LONG - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_read: [d0] - regs_write: [d0] - regs_impl_read: [d0] - regs_impl_write: [d0] + - asm_text: "chk.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] # Bug 4: CpID=2 cpgen should be invalid - - - input: - bytes: [ 0xf4, 0x00 ] + - input: + bytes: [0xf4, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "dc.w $f400" + - asm_text: "dc.w $f400" # Bug 4: CpID=2 cpbcc should be invalid - - - input: - bytes: [ 0xf4, 0x81 ] + - input: + bytes: [0xf4, 0x81] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "dc.w $f481" + - asm_text: "dc.w $f481" # Bug 7: move16 should be invalid on 68000 - - - input: - bytes: [ 0xf6, 0x20, 0x90, 0x00 ] + - input: + bytes: [0xf6, 0x20, 0x90, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f620" + - asm_text: "dc.w $f620" # Bug 12: fsdiv should be invalid on 68020 (pre-040 s/d FPU) - - - input: - bytes: [ 0xf2, 0x00, 0x00, 0x60, 0x00, 0x00 ] + - input: + bytes: [0xf2, 0x00, 0x00, 0x60, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "dc.w $f200" - - - asm_text: "ori.w #$0, -(a0)" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_WORD - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_MEM - address_mode: M68K_AM_REGI_ADDR_PRE_DEC - regs_write: [a0] - regs_impl_write: [a0] + - asm_text: "dc.w $f200" + - asm_text: "ori.w #$0, -(a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_MEM + address_mode: M68K_AM_REGI_ADDR_PRE_DEC + regs_write: [a0] + regs_impl_write: [a0] # Bug 12: fsdiv should work on 68040 - - - input: - bytes: [ 0xf2, 0x00, 0x00, 0x60 ] + - input: + bytes: [0xf2, 0x00, 0x00, 0x60] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040] address: 0x0 expected: insns: - - - asm_text: "fsdiv fp0, fp0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - operands: - - - type: M68K_OP_REG - reg: fp0 - - - type: M68K_OP_REG - reg: fp0 - regs_read: [fp0] - regs_write: [fp0] - regs_impl_read: [fp0] - regs_impl_write: [fp0] + - asm_text: "fsdiv fp0, fp0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp0 + - type: M68K_OP_REG + reg: fp0 + regs_read: [fp0] + regs_write: [fp0] + regs_impl_read: [fp0] + regs_impl_write: [fp0] # cpbcc CpID=1 condition >= 32 should be invalid - - - input: - bytes: [ 0xf2, 0xe0 ] + - input: + bytes: [0xf2, 0xe0] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "dc.w $f2e0" + - asm_text: "dc.w $f2e0" # cpbcc CpID=0 condition >= 16 should be invalid - - - input: - bytes: [ 0xf0, 0x90 ] + - input: + bytes: [0xf0, 0x90] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f090" + - asm_text: "dc.w $f090" # cpbcc CpID=0 should be invalid on 68000 (no coprocessor interface) - - - input: - bytes: [ 0xf0, 0x85 ] + - input: + bytes: [0xf0, 0x85] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f085" + - asm_text: "dc.w $f085" # cpbcc CpID=0 should be invalid on CPU32 - - - input: - bytes: [ 0xf0, 0x85 ] + - input: + bytes: [0xf0, 0x85] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $f085" + - asm_text: "dc.w $f085" # cpsave CpID=0 should be invalid on 68000 (no coprocessor interface) - - - input: - bytes: [ 0xf1, 0x10 ] + - input: + bytes: [0xf1, 0x10] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f110" + - asm_text: "dc.w $f110" # cpsave CpID=0 should be invalid on CPU32 - - - input: - bytes: [ 0xf1, 0x10 ] + - input: + bytes: [0xf1, 0x10] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $f110" + - asm_text: "dc.w $f110" # cprestore CpID=0 should be invalid on 68000 (no coprocessor interface) - - - input: - bytes: [ 0xf1, 0x50 ] + - input: + bytes: [0xf1, 0x50] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $f150" + - asm_text: "dc.w $f150" # cprestore CpID=0 should be invalid on CPU32 - - - input: - bytes: [ 0xf1, 0x50 ] + - input: + bytes: [0xf1, 0x50] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $f150" + - asm_text: "dc.w $f150" # Bug 13: TBL with bit 15 set should be invalid on CPU32 - - - input: - bytes: [ 0xf8, 0x00, 0x88, 0x00 ] + - input: + bytes: [0xf8, 0x00, 0x88, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $f800" - - - asm_text: "or.b d0, d4" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d4 - regs_read: [d0] - regs_write: [d4] - regs_impl_read: [d0] - regs_impl_write: [d4] + - asm_text: "dc.w $f800" + - asm_text: "or.b d0, d4" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d4 + regs_read: [d0] + regs_write: [d4] + regs_impl_read: [d0] + regs_impl_write: [d4] # Bug 13: TBL with bit 9 set should be invalid on CPU32 - - - input: - bytes: [ 0xf8, 0x00, 0x0a, 0x00, 0x00, 0x00 ] + - input: + bytes: [0xf8, 0x00, 0x0a, 0x00, 0x00, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $f800" - - - asm_text: "eori.b #$0, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $f800" + - asm_text: "eori.b #$0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # Bug 14: PMMU with invalid FC source should be invalid on 68030 - - - input: - bytes: [ 0xf0, 0x00, 0x24, 0x04 ] + - input: + bytes: [0xf0, 0x00, 0x24, 0x04] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_030] address: 0x0 expected: insns: - - - asm_text: "dc.w $f000" - - - asm_text: "move.l d4, d2" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_fpu: M68K_FPU_SIZE_SINGLE - op_size_cpu: M68K_CPU_SIZE_LONG - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d4 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d2 - regs_read: [d4] - regs_write: [d2] - regs_impl_read: [d4] - regs_impl_write: [d2] + - asm_text: "dc.w $f000" + - asm_text: "move.l d4, d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d4 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d2 + regs_read: [d4] + regs_write: [d2] + regs_impl_read: [d4] + regs_impl_write: [d2] # Bug 14: PMMU cpgen CpID=0 should be invalid on 68020 (not 68030) - - - input: - bytes: [ 0xf0, 0x00, 0x24, 0x00 ] + - input: + bytes: [0xf0, 0x00, 0x24, 0x00] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "dc.w $f000" - - - asm_text: "move.l d0, d2" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_fpu: M68K_FPU_SIZE_SINGLE - op_size_cpu: M68K_CPU_SIZE_LONG - operands: - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d2 - regs_read: [d0] - regs_write: [d2] - regs_impl_read: [d0] - regs_impl_write: [d2] + - asm_text: "dc.w $f000" + - asm_text: "move.l d0, d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d2 + regs_read: [d0] + regs_write: [d2] + regs_impl_read: [d0] + regs_impl_write: [d2] # Bug 15a: Bitfield instructions (bftst etc.) must be illegal on 68000 # Full encoding: e8f8 0800 009c = bftst $9c.w{d0:32} on 68020+ (Do=1 → offset is register d0) # On 68000, e8f8 has size bits=11 which is undefined → dc.w, remainder = btst - - - input: - bytes: [ 0xe8, 0xf8, 0x08, 0x00, 0x00, 0x9c ] + - input: + bytes: [0xe8, 0xf8, 0x08, 0x00, 0x00, 0x9c] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "dc.w $e8f8" - - - asm_text: "btst.b #$9c, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x9c - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $e8f8" + - asm_text: "btst.b #$9c, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x9c + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # Bug 15b: Bitfield instructions must be illegal on CPU32 # CPU32 has TYPE_68020|TYPE_CPU32, so LIMIT_CPU_TYPES_NOT_CPU32 rejects it - - - input: - bytes: [ 0xe8, 0xf8, 0x08, 0x00, 0x00, 0x9c ] + - input: + bytes: [0xe8, 0xf8, 0x08, 0x00, 0x00, 0x9c] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CPU32] address: 0x0 expected: insns: - - - asm_text: "dc.w $e8f8" - - - asm_text: "btst.b #$9c, d0" - details: - m68k: - op_size_type: M68K_SIZE_TYPE_CPU - op_size_cpu: M68K_CPU_SIZE_BYTE - operands: - - - type: M68K_OP_IMM - address_mode: M68K_AM_IMMEDIATE - imm: 0x9c - - - type: M68K_OP_REG - address_mode: M68K_AM_REG_DIRECT_DATA - reg: d0 - regs_write: [d0] - regs_impl_write: [d0] + - asm_text: "dc.w $e8f8" + - asm_text: "btst.b #$9c, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x9c + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] # Bug 15c: Bitfield instructions valid on 68020 — full 3-word encoding - - - input: - bytes: [ 0xe8, 0xf8, 0x08, 0x00, 0x00, 0x9c ] + - input: + bytes: [0xe8, 0xf8, 0x08, 0x00, 0x00, 0x9c] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "bftst $9c.w{d0:32}" - details: - m68k: - operands: - - - type: M68K_OP_MEM - mem: - bitfield: 1 - offset: 0x80 - width: 32 - address_mode: M68K_AM_ABSOLUTE_DATA_SHORT + - asm_text: "bftst $9c.w{d0:32}" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + bitfield: 1 + address: 0x9c + offset: 0x80 + width: 32 + address_mode: M68K_AM_ABSOLUTE_DATA_SHORT # Bug 15d: Bitfield with static offset and width - - - input: - bytes: [ 0xe8, 0xf8, 0x05, 0x05, 0x00, 0x9c ] + - input: + bytes: [0xe8, 0xf8, 0x05, 0x05, 0x00, 0x9c] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "bftst $9c.w{20:5}" - details: - m68k: - operands: - - - type: M68K_OP_MEM - mem: - bitfield: 1 - offset: 20 - width: 5 - address_mode: M68K_AM_ABSOLUTE_DATA_SHORT + - asm_text: "bftst $9c.w{20:5}" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + bitfield: 1 + address: 0x9c + offset: 20 + width: 5 + address_mode: M68K_AM_ABSOLUTE_DATA_SHORT # Bug 15e: Bitfield with both register-encoded offset and width - - - input: - bytes: [ 0xe8, 0xf8, 0x08, 0x60, 0x00, 0x9c ] + - input: + bytes: [0xe8, 0xf8, 0x08, 0x60, 0x00, 0x9c] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_020] address: 0x0 expected: insns: - - - asm_text: "bftst $9c.w{d1:d0}" - details: - m68k: - operands: - - - type: M68K_OP_MEM - mem: - bitfield: 1 - offset: 0x81 - width: 0x80 - address_mode: M68K_AM_ABSOLUTE_DATA_SHORT + - asm_text: "bftst $9c.w{d1:d0}" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + bitfield: 1 + address: 0x9c + offset: 0x81 + width: 0x80 + address_mode: M68K_AM_ABSOLUTE_DATA_SHORT # Bug 16: btst PC-relative displacement (case 0x3a) must account for # extra words consumed before the displacement word. @@ -3524,28 +3020,24 @@ test_cases: # btst #$e8, d16(PC) where d16=0x0a54, read at PC=0x1054 # Target: 0x1054 + 0x0a54 = 0x1aa8 # Printer: pc + 2 + disp = 0x1050 + 2 + disp => disp must be 0xa56 - - - input: - bytes: [ 0x08, 0x3a, 0x00, 0xe8, 0x0a, 0x54 ] + - input: + bytes: [0x08, 0x3a, 0x00, 0xe8, 0x0a, 0x54] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x1050 expected: insns: - - - asm_text: "btst.b #$e8, $1aa8(pc)" - details: - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0xe8 - - - type: M68K_OP_MEM - mem: - disp: 0xa56 - disp_size: 1 - address_mode: M68K_AM_PCI_DISP + - asm_text: "btst.b #$e8, $1aa8(pc)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0xe8 + - type: M68K_OP_MEM + mem: + disp: 0xa56 + disp_size: 1 + address_mode: M68K_AM_PCI_DISP # Bug 17: btst PC-relative indexed (case 0x3b) must account for # extra words consumed before the extension word. @@ -3554,51 +3046,4375 @@ test_cases: # Extension read at PC=0x3404 # Target: 0x3404 + 0x39 = 0x343d # Printer: pc + 2 + disp = 0x3400 + 2 + disp => disp must be 0x3b - - - input: - bytes: [ 0x08, 0x3b, 0x00, 0x38, 0x00, 0x39 ] + - input: + bytes: [0x08, 0x3b, 0x00, 0x38, 0x00, 0x39] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x3400 expected: insns: - - - asm_text: "btst.b #$38, $343d(pc, d0.w)" - details: - regs_read: [ d0, pc ] - m68k: - operands: - - - type: M68K_OP_IMM - imm: 0x38 - - - type: M68K_OP_MEM - mem: - base_reg: pc - index_reg: d0 - index_size: -1 - disp: 0x3b - address_mode: M68K_AM_PCI_INDEX_8_BIT_DISP + - asm_text: "btst.b #$38, $343d(pc, d0.w)" + details: + regs_read: [d0, pc] + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x38 + - type: M68K_OP_MEM + mem: + base_reg: pc + index_reg: d0 + index_size: -1 + disp: 0x3b + address_mode: M68K_AM_PCI_INDEX_8_BIT_DISP # P2-7: roxr.b with register count — d1 as shift count register, d3 as dest # Encoding 0xe233: roxr.b d1,d3 - - - input: - bytes: [ 0xe2, 0x33 ] + - input: + bytes: [0xe2, 0x33] arch: "m68k" - options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000 ] + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_000] address: 0x0 expected: insns: - - - asm_text: "roxr.b d1, d3" - details: - m68k: - operands: - - - type: M68K_OP_REG - reg: d1 - - - type: M68K_OP_REG - reg: d3 + - asm_text: "roxr.b d1, d3" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d1 + - type: M68K_OP_REG + reg: d3 + # ColdFire coverage grouped by ColdFire PRM instruction-set summary category. + # Categories follow Chapter 3, "Instruction Set Summary". + + # ColdFire: Data Movement + - input: + bytes: [0xa5, 0x54] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mov3q.l #$2, (a4)" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x2 + - type: M68K_OP_MEM + mem: + base_reg: a4 + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0x71, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvs.b d0, d0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d0 + - input: + bytes: [0x71, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvs.w d0, d0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d0 + - input: + bytes: [0x71, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvz.b d0, d0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d0 + - input: + bytes: [0x71, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvz.w d0, d0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d0 + - input: + bytes: [0x73, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvs.b d0, d1" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d1 + regs_read: [d0] + regs_write: [d1] + regs_impl_read: [d0] + regs_impl_write: [d1] + - input: + bytes: [0xf2, 0x00, 0x05, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsmove fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x44] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdmove fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xa1, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mov3q.l #$ffffffff, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xffffffff + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x73, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvs.b (a0), d1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + regs_read: [a0] + regs_write: [d1] + regs_impl_read: [a0] + regs_impl_write: [d1] + - input: + bytes: [0x73, 0xd0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "mvz.w (a0), d1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + regs_read: [a0] + regs_write: [d1] + regs_impl_read: [a0] + regs_impl_write: [d1] + - input: + bytes: [0xa1, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l d0, acc" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: acc + regs_read: [d0] + regs_write: [acc] + regs_impl_read: [d0] + regs_impl_write: [acc] + - input: + bytes: [0xa1, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l acc, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: acc + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [acc] + regs_write: [d0] + regs_impl_read: [acc] + regs_impl_write: [d0] + - input: + bytes: [0xa1, 0x3c, 0x12, 0x34, 0x56, 0x78] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l #$12345678, acc" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x12345678 + - type: M68K_OP_REG + reg: acc + regs_write: [acc] + regs_impl_write: [acc] + - input: + bytes: [0xa9, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l d0, macsr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: macsr + regs_read: [d0] + regs_write: [macsr] + regs_impl_read: [d0] + regs_impl_write: [macsr] + - input: + bytes: [0xa9, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l macsr, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: macsr + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [macsr] + regs_write: [d0] + regs_impl_read: [macsr] + regs_impl_write: [d0] + - input: + bytes: [0xa9, 0x3c, 0x00, 0x00, 0x00, 0x07] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l #$7, macsr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x7 + - type: M68K_OP_REG + reg: macsr + regs_write: [macsr] + regs_impl_write: [macsr] + - input: + bytes: [0xad, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l d0, mask" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: mask + regs_read: [d0] + regs_write: [mask] + regs_impl_read: [d0] + regs_impl_write: [mask] + - input: + bytes: [0xad, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l mask, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: mask + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [mask] + regs_write: [d0] + regs_impl_read: [mask] + regs_impl_write: [d0] + - input: + bytes: [0xad, 0x3c, 0x00, 0x00, 0x00, 0x07] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l #$7, mask" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x7 + - type: M68K_OP_REG + reg: mask + regs_write: [mask] + regs_impl_write: [mask] + - input: + bytes: [0xa1, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "movclr.l acc0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: acc0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [acc0] + regs_write: [d0] + regs_impl_read: [acc0] + regs_impl_write: [d0] + - input: + bytes: [0xab, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l d0, accext01" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: accext01 + regs_read: [d0] + regs_write: [accext01] + regs_impl_read: [d0] + regs_impl_write: [accext01] + - input: + bytes: [0xab, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l accext01, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: accext01 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [accext01] + regs_write: [d0] + regs_impl_read: [accext01] + regs_impl_write: [d0] + - input: + bytes: [0xab, 0x3c, 0x00, 0x00, 0x00, 0x07] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l #$7, accext01" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x7 + - type: M68K_OP_REG + reg: accext01 + regs_write: [accext01] + regs_impl_write: [accext01] + - input: + bytes: [0xaf, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC_B] + address: 0x0 + expected: + insns: + - asm_text: "move.l d0, accext23" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: accext23 + regs_read: [d0] + regs_write: [accext23] + regs_impl_read: [d0] + regs_impl_write: [accext23] + - input: + bytes: [0xf2, 0x00, 0x40, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.l d0, fp0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: fp0 + regs_read: [d0] + regs_write: [fp0] + regs_impl_read: [d0] + regs_impl_write: [fp0] + - input: + bytes: [0xf2, 0x00, 0x60, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.l fp0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: fp0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [fp0] + regs_write: [d0] + regs_impl_read: [fp0] + regs_impl_write: [d0] + - input: + bytes: [0xf2, 0x3c, 0x44, 0x80, 0x3f, 0x80, 0x00, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.s #1.000000, fp1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_FPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_FP_SINGLE + address_mode: M68K_AM_IMMEDIATE + simm: 1.000000 + - type: M68K_OP_REG + reg: fp1 + regs_write: [fp1] + regs_impl_write: [fp1] + - input: + bytes: + [0xf2, 0x3c, 0x54, 0x80, 0x40, 0x09, 0x21, 0xfb, 0x54, 0x44, 0x2d, 0x18] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.d #3.141593, fp1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_FPU + op_size_fpu: M68K_FPU_SIZE_DOUBLE + operands: + - type: M68K_OP_FP_DOUBLE + address_mode: M68K_AM_IMMEDIATE + dimm: 3.141592653589793 + - type: M68K_OP_REG + reg: fp1 + regs_write: [fp1] + regs_impl_write: [fp1] + - input: + bytes: [0xf2, 0x10, 0x50, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.w (a0), fp0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: fp0 + regs_read: [a0] + regs_write: [fp0] + regs_impl_read: [a0] + regs_impl_write: [fp0] + - input: + bytes: [0xf2, 0x10, 0x64, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.s fp0, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_FPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: fp0 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [fp0, a0] + regs_impl_read: [fp0, a0] + - input: + bytes: [0xf2, 0x00, 0x5f, 0x0f] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmovecr #$f, fp6" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0xf + - type: M68K_OP_REG + reg: fp6 + regs_write: [fp6] + regs_impl_write: [fp6] + - input: + bytes: [0xf2, 0x00, 0x90, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.l d0, fpcr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: fpcr + regs_read: [d0] + regs_write: [fpcr] + regs_impl_read: [d0] + regs_impl_write: [fpcr] + - input: + bytes: [0xf2, 0x00, 0xb0, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.l fpcr, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: fpcr + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [fpcr] + regs_write: [d0] + regs_impl_read: [fpcr] + regs_impl_write: [d0] + - input: + bytes: [0xf2, 0x00, 0x88, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.l d0, fpsr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: fpsr + regs_read: [d0] + regs_write: [fpsr] + regs_impl_read: [d0] + regs_impl_write: [fpsr] + - input: + bytes: [0xf2, 0x00, 0xa4, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmove.l fpiar, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: fpiar + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [fpiar] + regs_write: [d0] + regs_impl_read: [fpiar] + regs_impl_write: [d0] + - input: + bytes: [0xf2, 0x10, 0xc0, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmovem (a0), fp0-fp1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG_BITS + register_bits: 196608 + regs_read: [a0] + regs_write: [fp0, fp1] + regs_impl_read: [a0] + regs_impl_write: [fp0, fp1] + - input: + bytes: [0xf2, 0x10, 0xe0, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmovem fp0-fp1, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG_BITS + register_bits: 196608 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [fp0, fp1, a0] + regs_impl_read: [fp0, fp1, a0] + - input: + bytes: [0xf2, 0x18, 0xd0, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmovem (a0)+, fp6-fp7" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR_POST_INC + - type: M68K_OP_REG_BITS + register_bits: 12582912 + regs_write: [a0, fp6, fp7] + regs_impl_write: [a0, fp6, fp7] + - input: + bytes: [0xf2, 0x20, 0xe0, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmovem fp0-fp1, -(a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG_BITS + register_bits: 196608 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR_PRE_DEC + regs_read: [fp0, fp1] + regs_write: [a0] + regs_impl_read: [fp0, fp1] + regs_impl_write: [a0] + - input: + bytes: [0xf2, 0x10, 0xc8, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmovem (a0), d1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d1 + regs_read: [a0] + regs_write: [d1] + regs_impl_read: [a0] + regs_impl_write: [d1] + - input: + bytes: [0x20, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "move.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x20, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "movea.l d0, a0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + reg: a0 + regs_read: [d0] + regs_write: [a0] + regs_impl_read: [d0] + regs_impl_write: [a0] + - input: + bytes: [0x70, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "moveq #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x48, 0xd0, 0x00, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "movem.l d0-d1, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG_BITS + register_bits: 3 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [d0, d1, a0] + regs_impl_read: [d0, d1, a0] + - input: + bytes: [0x41, 0xd0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "lea.l (a0), a0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + reg: a0 + regs_read: [a0] + regs_write: [a0] + regs_impl_read: [a0] + regs_impl_write: [a0] + - input: + bytes: [0x4e, 0x50, 0x00, 0x04] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "link.w a0, #$4" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + reg: a0 + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x4 + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x48, 0x50] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: pea.l (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x4e, 0x58] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: unlk a0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + reg: a0 + regs_write: [a0] + regs_impl_write: [a0] + + # ColdFire: Program Control + - input: + bytes: [0x51, 0xfc] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "tpf" + details: + m68k: + operands: [] + - input: + bytes: [0x51, 0xfa, 0x12, 0x34] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "tpf.w #$1234" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x1234 + - input: + bytes: [0x51, 0xfb, 0x12, 0x34, 0x56, 0x78] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "tpf.l #$12345678" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x12345678 + - input: + bytes: [0x60, 0xff, 0x00, 0x00, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: bra.l $12 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_BR_DISP + address_mode: M68K_AM_BRANCH_DISPLACEMENT + br_disp: 16 + br_disp_size: 4 + groups: [jump, branch_relative] + - input: + bytes: [0x61, 0xff, 0x00, 0x00, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: bsr.l $12 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_BR_DISP + address_mode: M68K_AM_BRANCH_DISPLACEMENT + br_disp: 16 + br_disp_size: 4 + groups: [jump, branch_relative] + - input: + bytes: [0x66, 0xff, 0x00, 0x00, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: bne.l $12 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_BR_DISP + address_mode: M68K_AM_BRANCH_DISPLACEMENT + br_disp: 16 + br_disp_size: 4 + groups: [jump, branch_relative] + - input: + bytes: [0xf2, 0x80, 0x00, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: fnop + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0xf2, 0x80, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: fbf.w $12 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_BR_DISP + address_mode: M68K_AM_BRANCH_DISPLACEMENT + br_disp: 16 + br_disp_size: 2 + groups: [jump, branch_relative] + - input: + bytes: [0xf2, 0xc0, 0x00, 0x00, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: fbf.l $12 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_BR_DISP + address_mode: M68K_AM_BRANCH_DISPLACEMENT + br_disp: 16 + br_disp_size: 4 + groups: [jump, branch_relative] + - input: + bytes: [0xf2, 0x48, 0x00, 0x00, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdbf d0, $14" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_BR_DISP + address_mode: M68K_AM_BRANCH_DISPLACEMENT + br_disp: 18 + br_disp_size: 2 + groups: [jump, branch_relative] + regs_read: [d0] + regs_impl_read: [d0] + - input: + bytes: [0xf2, 0x50, 0x00, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: fsf.b (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf2, 0x7c, 0x00, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: ftrapf + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0xf2, 0x7a, 0x00, 0x00, 0x12, 0x34] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "ftrapf.w #$1234" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1234 + - input: + bytes: [0xf2, 0x7b, 0x00, 0x00, 0x12, 0x34, 0x56, 0x78] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "ftrapf.w #$12345678" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x12345678 + - input: + bytes: [0xf2, 0x00, 0x05, 0x3a] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "ftst fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0x50, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: st.b d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x4e, 0xd0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: jmp (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + groups: [jump] + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x4e, 0x90] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: jsr (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + groups: [jump] + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x4e, 0x71] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: nop + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + - input: + bytes: [0x4e, 0x75] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: rts + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + groups: [ret] + - input: + bytes: [0x4a, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: tas.b d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x4a, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: tst.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + + # ColdFire: Integer Arithmetic + - input: + bytes: [0x4c, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "sats.l d0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - input: + bytes: [0xa0, 0x01, 0x00, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w d1l, d0l, acc0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d1 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: d0 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: acc0 + - input: + bytes: [0xa0, 0x01, 0x02, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w d1l, d0u, <<, acc0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d1 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: d0 + flags: [M68K_OP_FLAG_REG_UPPER] + - type: M68K_OP_SHIFT + flags: [M68K_OP_FLAG_SHIFT_LEFT] + - type: M68K_OP_REG + reg: acc0 + - input: + bytes: [0xa6, 0x02, 0x08, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.l d2, d3, acc0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d2 + - type: M68K_OP_REG + reg: d3 + - type: M68K_OP_REG + reg: acc0 + - input: + bytes: [0xa2, 0x93, 0xa0, 0x89] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w a1l, a2u, (a3), d1, acc0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: a1 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: a2 + flags: [M68K_OP_FLAG_REG_UPPER] + - type: M68K_OP_MEM + mem: + base_reg: a3 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d1 + - type: M68K_OP_REG + reg: acc0 + - input: + bytes: [0xa2, 0x93, 0xa0, 0xa9] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w a1l, a2u, (a3)&, d1, acc0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: a1 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: a2 + flags: [M68K_OP_FLAG_REG_UPPER] + - type: M68K_OP_MEM + mem: + base_reg: a3 + flags: [M68K_OP_FLAG_MEM_UPDATE] + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d1 + - type: M68K_OP_REG + reg: acc0 + - input: + bytes: [0xa2, 0x93, 0xa2, 0x89] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w a1l, a2u, <<, (a3), d1, acc0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: a1 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: a2 + flags: [M68K_OP_FLAG_REG_UPPER] + - type: M68K_OP_SHIFT + flags: [M68K_OP_FLAG_SHIFT_LEFT] + - type: M68K_OP_MEM + mem: + base_reg: a3 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: d1 + - type: M68K_OP_REG + reg: acc0 + - input: + bytes: [0x4c, 0x40, 0x28, 0x02] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_DIV] + address: 0x0 + expected: + insns: + - asm_text: "divs.l d0, d2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d2 + regs_read: [d0] + regs_write: [d2] + regs_impl_read: [d0] + regs_impl_write: [d2] + - input: + bytes: [0xa0, 0x01, 0x00, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w d1l, d0l" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d1 + flags: [M68K_OP_FLAG_REG_LOWER] + - type: M68K_OP_REG + reg: d0 + flags: [M68K_OP_FLAG_REG_LOWER] + - input: + bytes: [0xa6, 0x82, 0x08, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.l d2, d3, acc1" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d2 + - type: M68K_OP_REG + reg: d3 + - type: M68K_OP_REG + reg: acc1 + - input: + bytes: [0x4c, 0x40, 0x24, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_DIV] + address: 0x0 + expected: + insns: + - asm_text: "divu.l d0, d1:d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d1 + reg_pair_1: d2 + regs_read: [d0] + regs_write: [d1, d2] + regs_impl_read: [d0] + regs_impl_write: [d1, d2] + - input: + bytes: [0x4c, 0x40, 0x2c, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_DIV] + address: 0x0 + expected: + insns: + - asm_text: "divs.l d0, d1:d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d1 + reg_pair_1: d2 + regs_read: [d0] + regs_write: [d1, d2] + regs_impl_read: [d0] + regs_impl_write: [d1, d2] + - input: + bytes: [0xa0, 0x01, 0x01, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "msac.w d1l, d0l, acc0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + flags: [M68K_OP_FLAG_REG_LOWER] + reg: d1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + flags: [M68K_OP_FLAG_REG_LOWER] + reg: d0 + - type: M68K_OP_REG + reg: acc0 + regs_read: [d1] + regs_write: [d0, acc0] + regs_impl_read: [d1] + regs_impl_write: [d0, acc0] + - input: + bytes: [0xa6, 0x02, 0x09, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "msac.l d2, d3, acc0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d2 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d3 + - type: M68K_OP_REG + reg: acc0 + regs_read: [d2] + regs_write: [d3, acc0] + regs_impl_read: [d2] + regs_impl_write: [d3, acc0] + - input: + bytes: [0xa0, 0x02, 0x06, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w d2l, d0l, >>, acc0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + flags: [M68K_OP_FLAG_REG_LOWER] + reg: d2 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + flags: [M68K_OP_FLAG_REG_LOWER] + reg: d0 + - type: M68K_OP_SHIFT + flags: [M68K_OP_FLAG_SHIFT_RIGHT] + - type: M68K_OP_REG + reg: acc0 + regs_read: [d2] + regs_write: [d0, acc0] + regs_impl_read: [d2] + regs_impl_write: [d0, acc0] + - input: + bytes: [0xa2, 0x93, 0xa3, 0x89] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "msac.w a1l, a2u, <<, (a3), d1, acc0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + flags: [M68K_OP_FLAG_REG_LOWER] + reg: a1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + flags: [M68K_OP_FLAG_REG_UPPER] + reg: a2 + - type: M68K_OP_SHIFT + flags: [M68K_OP_FLAG_SHIFT_LEFT] + - type: M68K_OP_MEM + mem: + base_reg: a3 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + - type: M68K_OP_REG + reg: acc0 + regs_read: [a1, a3] + regs_write: [a2, d1, acc0] + regs_impl_read: [a1, a3] + regs_impl_write: [a2, d1, acc0] + - input: + bytes: [0xa2, 0x93, 0xa4, 0x89] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_EMAC] + address: 0x0 + expected: + insns: + - asm_text: "mac.w a1l, a2u, >>, (a3), d1, acc0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + flags: [M68K_OP_FLAG_REG_LOWER] + reg: a1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + flags: [M68K_OP_FLAG_REG_UPPER] + reg: a2 + - type: M68K_OP_SHIFT + flags: [M68K_OP_FLAG_SHIFT_RIGHT] + - type: M68K_OP_MEM + mem: + base_reg: a3 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d1 + - type: M68K_OP_REG + reg: acc0 + regs_read: [a1, a3] + regs_write: [a2, d1, acc0] + regs_impl_read: [a1, a3] + regs_impl_write: [a2, d1, acc0] + - input: + bytes: [0xd0, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "add.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xd1, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "adda.l d0, a0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + reg: a0 + regs_read: [d0] + regs_write: [a0] + regs_impl_read: [d0] + regs_impl_write: [a0] + - input: + bytes: [0x06, 0x80, 0x00, 0x00, 0x00, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "addi.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x52, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "addq.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xd1, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "addx.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x42, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: clr.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xb0, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cmp.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xb1, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cmpa.l d0, a0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + reg: a0 + regs_read: [d0] + regs_write: [a0] + regs_impl_read: [d0] + regs_impl_write: [a0] + - input: + bytes: [0x0c, 0x80, 0x00, 0x00, 0x00, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cmpi.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x48, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: ext.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x49, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: extb.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xc1, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "muls.w d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xc0, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "mulu.w d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x44, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: neg.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x40, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: negx.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x4c, 0x40, 0x20, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_DIV] + address: 0x0 + expected: + insns: + - asm_text: "remu.l d0, d1:d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d1 + reg_pair_1: d2 + regs_read: [d0] + regs_write: [d1, d2] + regs_impl_read: [d0] + regs_impl_write: [d1, d2] + - input: + bytes: [0x4c, 0x40, 0x28, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_DIV] + address: 0x0 + expected: + insns: + - asm_text: "rems.l d0, d1:d2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG_PAIR + reg_pair_0: d1 + reg_pair_1: d2 + regs_read: [d0] + regs_write: [d1, d2] + regs_impl_read: [d0] + regs_impl_write: [d1, d2] + - input: + bytes: [0x90, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "sub.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x91, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "suba.l d0, a0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_ADDR + reg: a0 + regs_read: [d0] + regs_write: [a0] + regs_impl_read: [d0] + regs_impl_write: [a0] + - input: + bytes: [0x04, 0x80, 0x00, 0x00, 0x00, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "subi.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x53, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "subq.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x91, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "subx.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + + # ColdFire: Floating-Point Arithmetic + - input: + bytes: [0xf2, 0x00, 0x0a, 0x28] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsub fp2, fp4" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp2 + - type: M68K_OP_REG + reg: fp4 + regs_read: [fp2] + regs_write: [fp4] + regs_impl_read: [fp2] + regs_impl_write: [fp4] + - input: + bytes: [0xf2, 0x00, 0x05, 0x62] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsadd fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x66] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdadd fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x68] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fssub fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x6c] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdsub fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x63] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsmul fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x67] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdmul fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x60] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsdiv fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x64] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fddiv fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x5a] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsneg fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x5e] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdneg fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x58] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsabs fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x5c] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdabs fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x41] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fssqrt fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x45] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdsqrt fp1, fp2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fint fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x02] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsinh fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fintrz fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x04] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsqrt fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x06] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "flognp1 fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x08] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fetoxm1 fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x09] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fatanh fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x0a] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fatan fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x0c] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fasin fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x0e] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsin fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x0f] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "ftan fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fetox fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x11] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "ftwotox fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x12] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "ftentox fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x14] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "flogn fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x15] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "flog10 fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x16] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "flog2 fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x19] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fcosh fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x1c] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "facos fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x1d] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fcos fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x1e] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fgetexp fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x1f] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fgetman fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x20] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fdiv fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x21] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmod fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x22] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fadd fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x23] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fmul fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x24] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsgldiv fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x25] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "frem fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x26] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fscale fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x27] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fsglmul fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x38] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fcmp fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x18] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fabs fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + - input: + bytes: [0xf2, 0x00, 0x05, 0x1a] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: "fneg fp1, fp2" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: fp1 + - type: M68K_OP_REG + reg: fp2 + regs_read: [fp1] + regs_write: [fp2] + regs_impl_read: [fp1] + regs_impl_write: [fp2] + + # ColdFire: Logical + - input: + bytes: [0xc0, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "and.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x02, 0x80, 0x00, 0x00, 0x00, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "andi.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xb1, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "eor.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x0a, 0x80, 0x00, 0x00, 0x00, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "eori.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x46, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: not.l d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x80, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "or.l d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x00, 0x80, 0x00, 0x00, 0x00, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "ori.l #$1, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x1 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + + # ColdFire: Shift + - input: + bytes: [0xe1, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "asl.l #$8, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x8 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xe0, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "asr.l #$8, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x8 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xe1, 0x88] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "lsl.l #$8, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x8 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0xe0, 0x88] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "lsr.l #$8, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x8 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x48, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: swap d0 + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_write: [d0] + regs_impl_write: [d0] + + # ColdFire: Bit Manipulation + - input: + bytes: [0x00, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A_PLUS] + address: 0x0 + expected: + insns: + - asm_text: "bitrev d0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - input: + bytes: [0x02, 0xc1] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A_PLUS] + address: 0x0 + expected: + insns: + - asm_text: "byterev d1" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d1 + - input: + bytes: [0x04, 0xc2] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A_PLUS] + address: 0x0 + expected: + insns: + - asm_text: "ff1 d2" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d2 + - input: + bytes: [0x01, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "bchg.b d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x01, 0x80] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "bclr.b d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x01, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "bset.b d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + - input: + bytes: [0x01, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "btst.b d0, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_BYTE + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [d0] + regs_write: [d0] + regs_impl_read: [d0] + regs_impl_write: [d0] + + # ColdFire: System Control + - input: + bytes: [0xa9, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_MAC] + address: 0x0 + expected: + insns: + - asm_text: "move.l macsr, ccr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_REG + reg: macsr + - type: M68K_OP_REG + reg: ccr + regs_read: [macsr] + regs_write: [ccr] + regs_impl_read: [macsr] + regs_impl_write: [ccr] + - input: + bytes: [0x4a, 0xc8] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "halt" + details: + m68k: + operands: [] + - input: + bytes: [0x40, 0xe7, 0x46, 0xfc, 0x04, 0xd2] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A_PLUS] + address: 0x0 + expected: + insns: + - asm_text: "strldsr.w #$4d2" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x4d2 + - input: + bytes: [0xfb, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "wddata.b (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xfb, 0xd0, 0x00, 0x03] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "wdebug.l (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0x42, 0xc3] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "move.w ccr, d3" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: ccr + - type: M68K_OP_REG + reg: d3 + - input: + bytes: [0x4e, 0x68] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_USP] + address: 0x0 + expected: + insns: + - asm_text: "move usp, a0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: usp + - type: M68K_OP_REG + reg: a0 + - input: + bytes: [0x4e, 0x60] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_USP] + address: 0x0 + expected: + insns: + - asm_text: "move a0, usp" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: a0 + - type: M68K_OP_REG + reg: usp + - input: + bytes: [0x4a, 0xcc] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "pulse" + details: + m68k: + operands: [] + - input: + bytes: [0x4e, 0x7b, 0x00, 0x02] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "movec d0, cacr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: cacr + regs_read: [d0] + regs_write: [cacr] + regs_impl_read: [d0] + regs_impl_write: [cacr] + - input: + bytes: [0x4e, 0x7a, 0x10, 0x02] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "movec cacr, d1" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_REG + reg: cacr + - type: M68K_OP_REG + reg: d1 + regs_read: [cacr] + regs_write: [d1] + regs_impl_read: [cacr] + regs_impl_write: [d1] + - input: + bytes: [0xfb, 0x50] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: wddata.w (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xfb, 0x90] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: wddata.l (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_fpu: M68K_FPU_SIZE_SINGLE + op_size_cpu: M68K_CPU_SIZE_LONG + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf3, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: fsave (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0xf3, 0x50] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_FPU] + address: 0x0 + expected: + insns: + - asm_text: frestore (a0) + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + - input: + bytes: [0x44, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "move.w d0, ccr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: ccr + regs_read: [d0] + regs_write: [ccr] + regs_impl_read: [d0] + regs_impl_write: [ccr] + - input: + bytes: [0x40, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "move.w sr, d0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + reg: sr + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + regs_read: [sr] + regs_write: [d0] + regs_impl_read: [sr] + regs_impl_write: [d0] + - input: + bytes: [0x46, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "move.w d0, sr" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + op_size_cpu: M68K_CPU_SIZE_WORD + operands: + - type: M68K_OP_REG + address_mode: M68K_AM_REG_DIRECT_DATA + reg: d0 + - type: M68K_OP_REG + reg: sr + regs_read: [d0] + regs_write: [sr] + regs_impl_read: [d0] + regs_impl_write: [sr] + - input: + bytes: [0x4a, 0xfc] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "illegal #$4afc" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x4afc + - input: + bytes: [0x4e, 0x73] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: rte + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + groups: [iret] + - input: + bytes: [0x4e, 0x72, 0x27, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "stop #$2700" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x2700 + groups: [jump] + - input: + bytes: [0x4e, 0x40] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "trap #$0" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + groups: [jump] + + # ColdFire: Cache Maintenance + - input: + bytes: [0xf4, 0x28] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_B] + address: 0x0 + expected: + insns: + - asm_text: "intouch (a0)" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - input: + bytes: [0xf4, 0xe8] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cpushl bc, (a0)" + details: + m68k: + op_size_type: M68K_SIZE_TYPE_CPU + operands: + - type: M68K_OP_IMM + address_mode: M68K_AM_IMMEDIATE + imm: 0x3 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + regs_read: [a0] + regs_impl_read: [a0] + + # Additional ColdFire decoder coverage not listed in the CFPRM instruction-set summary. + # Source: existing Capstone/binutils mcfisa_a coprocessor encodings. + # ColdFire: Coprocessor Extensions + - input: + bytes: [0xfc, 0xc0, 0x00, 0x50] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0bcbusy $52" + details: + m68k: + operands: + - type: M68K_OP_BR_DISP + br_disp: 0x50 + br_disp_size: 2 + address_mode: M68K_AM_BRANCH_DISPLACEMENT + - input: + bytes: [0xfc, 0x80, 0x21, 0x23] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0ld.l d0, d2, #$1, #$123" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d2 + - type: M68K_OP_IMM + imm: 0x1 + - type: M68K_OP_IMM + imm: 0x123 + - input: + bytes: [0xfc, 0x50, 0xa4, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0ld.w (a0), a2, #$3, #$1" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_REG + reg: a2 + - type: M68K_OP_IMM + imm: 0x3 + - type: M68K_OP_IMM + imm: 0x1 + - input: + bytes: [0xfc, 0x18, 0xaa, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0ld.b (a0)+, a2, #$6, #$1" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR_POST_INC + - type: M68K_OP_REG + reg: a2 + - type: M68K_OP_IMM + imm: 0x6 + - type: M68K_OP_IMM + imm: 0x1 + - input: + bytes: [0xfc, 0xa8, 0xae, 0x01, 0x00, 0x10] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0ld.l $10(a0), a2, #$8, #$1" + details: + m68k: + operands: + - type: M68K_OP_MEM + mem: + base_reg: a0 + disp: 0x10 + disp_size: 1 + address_mode: M68K_AM_REGI_ADDR_DISP + - type: M68K_OP_REG + reg: a2 + - type: M68K_OP_IMM + imm: 0x8 + - type: M68K_OP_IMM + imm: 0x1 + - input: + bytes: [0xfd, 0x80, 0x21, 0x23] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0st.l d2, d0, #$1, #$123" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d2 + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_IMM + imm: 0x1 + - type: M68K_OP_IMM + imm: 0x123 + - input: + bytes: [0xfd, 0x50, 0xa4, 0x01] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0st.w a2, (a0), #$3, #$1" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: a2 + - type: M68K_OP_MEM + mem: + base_reg: a0 + address_mode: M68K_AM_REGI_ADDR + - type: M68K_OP_IMM + imm: 0x3 + - type: M68K_OP_IMM + imm: 0x1 + - input: + bytes: [0xfc, 0x00, 0x0e, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0nop #$8" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x8 + - input: + bytes: [0xfc, 0x80, 0x04, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0nop #$3" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x3 + - input: + bytes: [0xfc, 0x80, 0x14, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp0ld.l d0, d1, #$3, #$0" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d1 + - type: M68K_OP_IMM + imm: 0x3 + - type: M68K_OP_IMM + imm: 0x0 + - input: + bytes: [0xfe, 0xc0, 0x00, 0x50] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp1bcbusy $52" + details: + m68k: + operands: + - type: M68K_OP_BR_DISP + br_disp: 0x50 + br_disp_size: 2 + address_mode: M68K_AM_BRANCH_DISPLACEMENT + - input: + bytes: [0xfe, 0x80, 0x21, 0x23] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp1ld.l d0, d2, #$1, #$123" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_REG + reg: d2 + - type: M68K_OP_IMM + imm: 0x1 + - type: M68K_OP_IMM + imm: 0x123 + - input: + bytes: [0xff, 0x80, 0x21, 0x23] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp1st.l d2, d0, #$1, #$123" + details: + m68k: + operands: + - type: M68K_OP_REG + reg: d2 + - type: M68K_OP_REG + reg: d0 + - type: M68K_OP_IMM + imm: 0x1 + - type: M68K_OP_IMM + imm: 0x123 + - input: + bytes: [0xfe, 0x00, 0x0e, 0x00] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "cp1nop #$8" + details: + m68k: + operands: + - type: M68K_OP_IMM + imm: 0x8 + + # ColdFire: Feature Gating / Negative Cases + - input: + bytes: [0x00, 0xc0] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "dc.w $c0" + - input: + bytes: [0x4e, 0x68] + arch: "m68k" + options: [CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_CF_ISA_A] + address: 0x0 + expected: + insns: + - asm_text: "dc.w $4e68"