diff --git a/ChangeLog b/ChangeLog index a7841a4ae..cff73987f 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,103 @@ This file details the changelog of Capstone. +----------------------------- +Version 6.0.0-Alpha10: July 21th, 2026 + +## API changes and additions + +- Enum names of the Alpha architecture are now correctly all upper case. + Because of an old Auto-Sync bug all the enum names were prefixed with `Alpha` instead of `ALPHA` + and some contained lower case letters. + Sadly, I just recently recognized that Alpha was effected by that bug. + + While this change is very annoying for everybody using the Alpha module, + it must be done before the Beta release. + Please excuse the inconvenience! + + A simple command to replace almost all of these occurrences in your code base is: + ``` + find . -type f -regex ".*\.\(c\|h\)$" -exec sed -i -E "s|Alpha_([A-Z0-9_]+)|ALPHA_\1|g" {} + + ``` + Author: @Rot127 + +- RISC-V got a v5 compatibility macro for its header. + With its recent module update `CS_MODE_RISCVC` was renamed to `CS_MODE_RISCV_C` to be + more consistent with the other `CS_MODE_` enums. + This could break builds against a `v5` code base which only has `CS_MODE_RISCVC`. + + Now you can simply define `CAPSTONE_RISCV_COMPAT_HEADER` before including `capstone.h` + and `CS_MODE_RISCVC` will be defined as alias for `CS_MODE_RISCV_C` + + ``` + #define CAPSTONE_RISCV_COMPAT_HEADER + #include + ``` + Author: @moste00 + +- Prevent literal displacement truncation for AArch64 memory operands. + There are AArch64 displacements which are 64bit in size. But `aarch64_op_mem.disp` was an `int32_t`. + It was promoted to an `int64_t`. + Author: @amaanmujawar + +- Fixed several decoding bugs in the Alpha module. + See https://github.com/capstone-engine/capstone/pull/2967 for details. + Author: @mattst88 + +- The RISC-V details now also include the FP rounding mode `cs_riscv.rounding_mode`. + Author: @moste00 + +- AArch64: Add `CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM` flag to print shifted `MOVN` and + `MOVZ` instructions in their explicit forms instead of using the equivalent `MOV` aliases. + + Example output from `cstool`: + ``` + > cstool aarch64 0xe402a012 + mov w4, #-0x170001 + + > cstool aarch64+explicitwideimm 0xe402a012 + movn w4, #0x17, lsl #16 + + > cstool aarch64+explicitwideimm 0xe402a052 + movz w4, #0x17, lsl #16 + ``` + Author: @amaanmujawar + +- M68K: Fixed EA decoding error and added ColdFire EMAC_B dual-acc MAC. + Author: @b1llow + +## What's Changed +* Add CI job for building and testing on 32bit big endian by @trufae in https://github.com/capstone-engine/capstone/pull/2941 +* Fixed CONTRIBUTING.md not listing all Architectures by @rectrap in https://github.com/capstone-engine/capstone/pull/2952 +* Find writeback registers by @slate5 in https://github.com/capstone-engine/capstone/pull/2960 +* m68k: fix off-by-one bounds check in M68K_insn_name by @jmestwa-coder in https://github.com/capstone-engine/capstone/pull/2964 +* Fix OOB reads/writes - CVE-2026-55893 & CVE-2026-55894 by @Rot127 in https://github.com/capstone-engine/capstone/pull/2968 +* Alpha: fix decoder bugs and add test coverage by @mattst88 in https://github.com/capstone-engine/capstone/pull/2967 +* Fix crash due to invalid register by @moste00 in https://github.com/capstone-engine/capstone/pull/2966 +* Fix naming convention for Alpha enums by @Rot127 in https://github.com/capstone-engine/capstone/pull/2971 +* Add frm operands to float/double instructions by @moste00 in https://github.com/capstone-engine/capstone/pull/2972 +* Apply clang-format by @Rot127 in https://github.com/capstone-engine/capstone/pull/2975 +* Fix AArch64 predicate-as-counter register printed in hex by @yufengzjj in https://github.com/capstone-engine/capstone/pull/2976 +* SH: fix signed shift overflow in sh_disassemble dsp decode by @jmestwa-coder in https://github.com/capstone-engine/capstone/pull/2983 +* Guard operand append past MAX_MC_OPS in MCInst.c by @Samin061 in https://github.com/capstone-engine/capstone/pull/2985 +* M68K: Handle EA decoding error case and add ColdFire EMAC_B dual-acc MAC by @b1llow in https://github.com/capstone-engine/capstone/pull/2987 +* Xtensa: fix swapped isIntN arguments in decodeOffset_16_16Operand by @jmestwa-coder in https://github.com/capstone-engine/capstone/pull/2986 +* Don't build cstool arch specific details printing, if not requested. by @Rot127 in https://github.com/capstone-engine/capstone/pull/2888 +* Add overflow check to cs_kern_os_calloc by @Rot127 in https://github.com/capstone-engine/capstone/pull/2980 +* M68K: Fix FPU condition and FMOVEM decoding by @b1llow in https://github.com/capstone-engine/capstone/pull/2993 +* AArch64: enh Add option for explicit shifted wide immediates by @amaanmujawar in https://github.com/capstone-engine/capstone/pull/2995 +* Add compat behaviour for RISCV for RISCVC/RISCV_C constant by @moste00 in https://github.com/capstone-engine/capstone/pull/2996 +* AArch64: fix LDR literal detail operand truncation by @amaanmujawar in https://github.com/capstone-engine/capstone/pull/2984 + +## New Contributors +* @rectrap made their first contribution in https://github.com/capstone-engine/capstone/pull/2952 +* @jmestwa-coder made their first contribution in https://github.com/capstone-engine/capstone/pull/2964 +* @mattst88 made their first contribution in https://github.com/capstone-engine/capstone/pull/2967 +* @yufengzjj made their first contribution in https://github.com/capstone-engine/capstone/pull/2976 +* @Samin061 made their first contribution in https://github.com/capstone-engine/capstone/pull/2985 +* @amaanmujawar made their first contribution in https://github.com/capstone-engine/capstone/pull/2995 + +**Full Changelog**: https://github.com/capstone-engine/capstone/compare/6.0.0-Alpha9...6.0.0-Alpha10 + ----------------------------- Version 6.0.0-Alpha9: May 28th, 2026 diff --git a/arch/Alpha/AlphaGenCSMappingInsn.inc b/arch/Alpha/AlphaGenCSMappingInsn.inc index 70bbdc493..766648f0a 100644 --- a/arch/Alpha/AlphaGenCSMappingInsn.inc +++ b/arch/Alpha/AlphaGenCSMappingInsn.inc @@ -1888,7 +1888,7 @@ }, { /* adds/su $RA,$RB,$RC */ - ALPHA_ADDS /* 267 */, ALPHA_INS_ADDSsSU, + ALPHA_ADDS /* 267 */, ALPHA_INS_ADDSSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -1896,7 +1896,7 @@ }, { /* addt/su $RA,$RB,$RC */ - ALPHA_ADDT /* 268 */, ALPHA_INS_ADDTsSU, + ALPHA_ADDT /* 268 */, ALPHA_INS_ADDTSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2224,7 +2224,7 @@ }, { /* cmpteq/su $RA,$RB,$RC */ - ALPHA_CMPTEQ /* 309 */, ALPHA_INS_CMPTEQsSU, + ALPHA_CMPTEQ /* 309 */, ALPHA_INS_CMPTEQSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2232,7 +2232,7 @@ }, { /* cmptle/su $RA,$RB,$RC */ - ALPHA_CMPTLE /* 310 */, ALPHA_INS_CMPTLEsSU, + ALPHA_CMPTLE /* 310 */, ALPHA_INS_CMPTLESSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2240,7 +2240,7 @@ }, { /* cmptlt/su $RA,$RB,$RC */ - ALPHA_CMPTLT /* 311 */, ALPHA_INS_CMPTLTsSU, + ALPHA_CMPTLT /* 311 */, ALPHA_INS_CMPTLTSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2248,7 +2248,7 @@ }, { /* cmptun/su $RA,$RB,$RC */ - ALPHA_CMPTUN /* 312 */, ALPHA_INS_CMPTUNsSU, + ALPHA_CMPTUN /* 312 */, ALPHA_INS_CMPTUNSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2416,7 +2416,7 @@ }, { /* cvtqs/sui $RB,$RC */ - ALPHA_CVTQS /* 333 */, ALPHA_INS_CVTQSsSUI, + ALPHA_CVTQS /* 333 */, ALPHA_INS_CVTQSSSUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2424,7 +2424,7 @@ }, { /* cvtqt/sui $RB,$RC */ - ALPHA_CVTQT /* 334 */, ALPHA_INS_CVTQTsSUI, + ALPHA_CVTQT /* 334 */, ALPHA_INS_CVTQTSSUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2432,7 +2432,7 @@ }, { /* cvtst/s $RB,$RC */ - ALPHA_CVTST /* 335 */, ALPHA_INS_CVTSTsS, + ALPHA_CVTST /* 335 */, ALPHA_INS_CVTSTSS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2440,7 +2440,7 @@ }, { /* cvttq/svc $RB,$RC */ - ALPHA_CVTTQ /* 336 */, ALPHA_INS_CVTTQsSVC, + ALPHA_CVTTQ /* 336 */, ALPHA_INS_CVTTQSSVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2448,7 +2448,7 @@ }, { /* cvtts/sui $RB,$RC */ - ALPHA_CVTTS /* 337 */, ALPHA_INS_CVTTSsSUI, + ALPHA_CVTTS /* 337 */, ALPHA_INS_CVTTSSSUI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2456,7 +2456,7 @@ }, { /* divs/su $RA,$RB,$RC */ - ALPHA_DIVS /* 338 */, ALPHA_INS_DIVSsSU, + ALPHA_DIVS /* 338 */, ALPHA_INS_DIVSSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -2464,7 +2464,7 @@ }, { /* divt/su $RA,$RB,$RC */ - ALPHA_DIVT /* 339 */, ALPHA_INS_DIVTsSU, + ALPHA_DIVT /* 339 */, ALPHA_INS_DIVTSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -3280,7 +3280,7 @@ }, { /* muls/su $RA,$RB,$RC */ - ALPHA_MULS /* 441 */, ALPHA_INS_MULSsSU, + ALPHA_MULS /* 441 */, ALPHA_INS_MULSSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -3288,7 +3288,7 @@ }, { /* mult/su $RA,$RB,$RC */ - ALPHA_MULT /* 442 */, ALPHA_INS_MULTsSU, + ALPHA_MULT /* 442 */, ALPHA_INS_MULTSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -3512,7 +3512,7 @@ }, { /* sqrts/su $RB,$RC */ - ALPHA_SQRTS /* 470 */, ALPHA_INS_SQRTSsSU, + ALPHA_SQRTS /* 470 */, ALPHA_INS_SQRTSSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -3520,7 +3520,7 @@ }, { /* sqrtt/su $RB,$RC */ - ALPHA_SQRTT /* 471 */, ALPHA_INS_SQRTTsSU, + ALPHA_SQRTT /* 471 */, ALPHA_INS_SQRTTSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -3712,7 +3712,7 @@ }, { /* subs/su $RA,$RB,$RC */ - ALPHA_SUBS /* 495 */, ALPHA_INS_SUBSsSU, + ALPHA_SUBS /* 495 */, ALPHA_INS_SUBSSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, @@ -3720,7 +3720,7 @@ }, { /* subt/su $RA,$RB,$RC */ - ALPHA_SUBT /* 496 */, ALPHA_INS_SUBTsSU, + ALPHA_SUBT /* 496 */, ALPHA_INS_SUBTSSU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0, {{ 0 }}, diff --git a/arch/Alpha/AlphaGenCSMappingInsnName.inc b/arch/Alpha/AlphaGenCSMappingInsnName.inc index f808562c4..c2ea2b16c 100644 --- a/arch/Alpha/AlphaGenCSMappingInsnName.inc +++ b/arch/Alpha/AlphaGenCSMappingInsnName.inc @@ -14,8 +14,8 @@ "invalid", // ALPHA_INS_INVALID "addl", // ALPHA_INS_ADDL "addq", // ALPHA_INS_ADDQ - "adds/su", // ALPHA_INS_ADDSsSU - "addt/su", // ALPHA_INS_ADDTsSU + "adds/su", // ALPHA_INS_ADDSSSU + "addt/su", // ALPHA_INS_ADDTSSU "and", // ALPHA_INS_AND "beq", // ALPHA_INS_BEQ "bge", // ALPHA_INS_BGE @@ -41,10 +41,10 @@ "cmpeq", // ALPHA_INS_CMPEQ "cmple", // ALPHA_INS_CMPLE "cmplt", // ALPHA_INS_CMPLT - "cmpteq/su", // ALPHA_INS_CMPTEQsSU - "cmptle/su", // ALPHA_INS_CMPTLEsSU - "cmptlt/su", // ALPHA_INS_CMPTLTsSU - "cmptun/su", // ALPHA_INS_CMPTUNsSU + "cmpteq/su", // ALPHA_INS_CMPTEQSSU + "cmptle/su", // ALPHA_INS_CMPTLESSU + "cmptlt/su", // ALPHA_INS_CMPTLTSSU + "cmptun/su", // ALPHA_INS_CMPTUNSSU "cmpule", // ALPHA_INS_CMPULE "cmpult", // ALPHA_INS_CMPULT "call_pal", // ALPHA_INS_CALL_PAL @@ -55,13 +55,13 @@ "ctlz", // ALPHA_INS_CTLZ "ctpop", // ALPHA_INS_CTPOP "cttz", // ALPHA_INS_CTTZ - "cvtqs/sui", // ALPHA_INS_CVTQSsSUI - "cvtqt/sui", // ALPHA_INS_CVTQTsSUI - "cvtst/s", // ALPHA_INS_CVTSTsS - "cvttq/svc", // ALPHA_INS_CVTTQsSVC - "cvtts/sui", // ALPHA_INS_CVTTSsSUI - "divs/su", // ALPHA_INS_DIVSsSU - "divt/su", // ALPHA_INS_DIVTsSU + "cvtqs/sui", // ALPHA_INS_CVTQSSSUI + "cvtqt/sui", // ALPHA_INS_CVTQTSSUI + "cvtst/s", // ALPHA_INS_CVTSTSS + "cvttq/svc", // ALPHA_INS_CVTTQSSVC + "cvtts/sui", // ALPHA_INS_CVTTSSSUI + "divs/su", // ALPHA_INS_DIVSSSU + "divt/su", // ALPHA_INS_DIVTSSU "ecb", // ALPHA_INS_ECB "eqv", // ALPHA_INS_EQV "excb", // ALPHA_INS_EXCB @@ -121,8 +121,8 @@ "mskwl", // ALPHA_INS_MSKWL "mull", // ALPHA_INS_MULL "mulq", // ALPHA_INS_MULQ - "muls/su", // ALPHA_INS_MULSsSU - "mult/su", // ALPHA_INS_MULTsSU + "muls/su", // ALPHA_INS_MULSSSU + "mult/su", // ALPHA_INS_MULTSSU "ornot", // ALPHA_INS_ORNOT "rc", // ALPHA_INS_RC "ret", // ALPHA_INS_RET @@ -139,8 +139,8 @@ "sextb", // ALPHA_INS_SEXTB "sextw", // ALPHA_INS_SEXTW "sll", // ALPHA_INS_SLL - "sqrts/su", // ALPHA_INS_SQRTSsSU - "sqrtt/su", // ALPHA_INS_SQRTTsSU + "sqrts/su", // ALPHA_INS_SQRTSSSU + "sqrtt/su", // ALPHA_INS_SQRTTSSU "sra", // ALPHA_INS_SRA "srl", // ALPHA_INS_SRL "stb", // ALPHA_INS_STB @@ -154,8 +154,8 @@ "stw", // ALPHA_INS_STW "subl", // ALPHA_INS_SUBL "subq", // ALPHA_INS_SUBQ - "subs/su", // ALPHA_INS_SUBSsSU - "subt/su", // ALPHA_INS_SUBTsSU + "subs/su", // ALPHA_INS_SUBSSSU + "subt/su", // ALPHA_INS_SUBTSSU "trapb", // ALPHA_INS_TRAPB "umulh", // ALPHA_INS_UMULH "wh64", // ALPHA_INS_WH64 diff --git a/arch/Alpha/AlphaGenCSMappingInsnOp.inc b/arch/Alpha/AlphaGenCSMappingInsnOp.inc index 5cc3a46aa..602f68b20 100644 --- a/arch/Alpha/AlphaGenCSMappingInsnOp.inc +++ b/arch/Alpha/AlphaGenCSMappingInsnOp.inc @@ -830,14 +830,14 @@ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_ADDS (267) - ALPHA_INS_ADDSsSU - adds/su $RA,$RB,$RC */ +{ /* ALPHA_ADDS (267) - ALPHA_INS_ADDSSSU - adds/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_ADDT (268) - ALPHA_INS_ADDTsSU - addt/su $RA,$RB,$RC */ +{ /* ALPHA_ADDT (268) - ALPHA_INS_ADDTSSU - addt/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ @@ -1128,28 +1128,28 @@ { CS_OP_IMM, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* L */ { 0 } }}, -{ /* ALPHA_CMPTEQ (309) - ALPHA_INS_CMPTEQsSU - cmpteq/su $RA,$RB,$RC */ +{ /* ALPHA_CMPTEQ (309) - ALPHA_INS_CMPTEQSSU - cmpteq/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CMPTLE (310) - ALPHA_INS_CMPTLEsSU - cmptle/su $RA,$RB,$RC */ +{ /* ALPHA_CMPTLE (310) - ALPHA_INS_CMPTLESSU - cmptle/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CMPTLT (311) - ALPHA_INS_CMPTLTsSU - cmptlt/su $RA,$RB,$RC */ +{ /* ALPHA_CMPTLT (311) - ALPHA_INS_CMPTLTSSU - cmptlt/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CMPTUN (312) - ALPHA_INS_CMPTUNsSU - cmptun/su $RA,$RB,$RC */ +{ /* ALPHA_CMPTUN (312) - ALPHA_INS_CMPTUNSSU - cmptun/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ @@ -1291,44 +1291,44 @@ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CVTQS (333) - ALPHA_INS_CVTQSsSUI - cvtqs/sui $RB,$RC */ +{ /* ALPHA_CVTQS (333) - ALPHA_INS_CVTQSSSUI - cvtqs/sui $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CVTQT (334) - ALPHA_INS_CVTQTsSUI - cvtqt/sui $RB,$RC */ +{ /* ALPHA_CVTQT (334) - ALPHA_INS_CVTQTSSUI - cvtqt/sui $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CVTST (335) - ALPHA_INS_CVTSTsS - cvtst/s $RB,$RC */ +{ /* ALPHA_CVTST (335) - ALPHA_INS_CVTSTSS - cvtst/s $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CVTTQ (336) - ALPHA_INS_CVTTQsSVC - cvttq/svc $RB,$RC */ +{ /* ALPHA_CVTTQ (336) - ALPHA_INS_CVTTQSSVC - cvttq/svc $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_CVTTS (337) - ALPHA_INS_CVTTSsSUI - cvtts/sui $RB,$RC */ +{ /* ALPHA_CVTTS (337) - ALPHA_INS_CVTTSSSUI - cvtts/sui $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_DIVS (338) - ALPHA_INS_DIVSsSU - divs/su $RA,$RB,$RC */ +{ /* ALPHA_DIVS (338) - ALPHA_INS_DIVSSSU - divs/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_DIVT (339) - ALPHA_INS_DIVTsSU - divt/su $RA,$RB,$RC */ +{ /* ALPHA_DIVT (339) - ALPHA_INS_DIVTSSU - divt/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ @@ -2034,14 +2034,14 @@ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_MULS (441) - ALPHA_INS_MULSsSU - muls/su $RA,$RB,$RC */ +{ /* ALPHA_MULS (441) - ALPHA_INS_MULSSSU - muls/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_MULT (442) - ALPHA_INS_MULTsSU - mult/su $RA,$RB,$RC */ +{ /* ALPHA_MULT (442) - ALPHA_INS_MULTSSU - mult/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ @@ -2227,13 +2227,13 @@ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_SQRTS (470) - ALPHA_INS_SQRTSsSU - sqrts/su $RB,$RC */ +{ /* ALPHA_SQRTS (470) - ALPHA_INS_SQRTSSSU - sqrts/su $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_SQRTT (471) - ALPHA_INS_SQRTTsSU - sqrtt/su $RB,$RC */ +{ /* ALPHA_SQRTT (471) - ALPHA_INS_SQRTTSSU - sqrtt/su $RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RB */ @@ -2402,14 +2402,14 @@ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_i64, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_SUBS (495) - ALPHA_INS_SUBSsSU - subs/su $RA,$RB,$RC */ +{ /* ALPHA_SUBS (495) - ALPHA_INS_SUBSSSU - subs/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RA */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f32, CS_DATA_TYPE_LAST }, }, /* RB */ { 0 } }}, -{ /* ALPHA_SUBT (496) - ALPHA_INS_SUBTsSU - subt/su $RA,$RB,$RC */ +{ /* ALPHA_SUBT (496) - ALPHA_INS_SUBTSSU - subt/su $RA,$RB,$RC */ { { CS_OP_REG, CS_AC_WRITE, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RC */ { CS_OP_REG, CS_AC_READ, { CS_DATA_TYPE_f64, CS_DATA_TYPE_LAST }, }, /* RA */ diff --git a/bindings/python/capstone/alpha_const.py b/bindings/python/capstone/alpha_const.py index 3402a12a6..9b0c4e456 100644 --- a/bindings/python/capstone/alpha_const.py +++ b/bindings/python/capstone/alpha_const.py @@ -80,8 +80,8 @@ ALPHA_REG_ENDING = 65 ALPHA_INS_INVALID = 0 ALPHA_INS_ADDL = 1 ALPHA_INS_ADDQ = 2 -ALPHA_INS_ADDSsSU = 3 -ALPHA_INS_ADDTsSU = 4 +ALPHA_INS_ADDSSSU = 3 +ALPHA_INS_ADDTSSU = 4 ALPHA_INS_AND = 5 ALPHA_INS_BEQ = 6 ALPHA_INS_BGE = 7 @@ -107,128 +107,129 @@ ALPHA_INS_CMPBGE = 26 ALPHA_INS_CMPEQ = 27 ALPHA_INS_CMPLE = 28 ALPHA_INS_CMPLT = 29 -ALPHA_INS_CMPTEQsSU = 30 -ALPHA_INS_CMPTLEsSU = 31 -ALPHA_INS_CMPTLTsSU = 32 -ALPHA_INS_CMPTUNsSU = 33 +ALPHA_INS_CMPTEQSSU = 30 +ALPHA_INS_CMPTLESSU = 31 +ALPHA_INS_CMPTLTSSU = 32 +ALPHA_INS_CMPTUNSSU = 33 ALPHA_INS_CMPULE = 34 ALPHA_INS_CMPULT = 35 -ALPHA_INS_COND_BRANCH = 36 -ALPHA_INS_CPYSE = 37 -ALPHA_INS_CPYSN = 38 -ALPHA_INS_CPYS = 39 -ALPHA_INS_CTLZ = 40 -ALPHA_INS_CTPOP = 41 -ALPHA_INS_CTTZ = 42 -ALPHA_INS_CVTQSsSUI = 43 -ALPHA_INS_CVTQTsSUI = 44 -ALPHA_INS_CVTSTsS = 45 -ALPHA_INS_CVTTQsSVC = 46 -ALPHA_INS_CVTTSsSUI = 47 -ALPHA_INS_DIVSsSU = 48 -ALPHA_INS_DIVTsSU = 49 -ALPHA_INS_ECB = 50 -ALPHA_INS_EQV = 51 -ALPHA_INS_EXCB = 52 -ALPHA_INS_EXTBL = 53 -ALPHA_INS_EXTLH = 54 -ALPHA_INS_EXTLL = 55 -ALPHA_INS_EXTQH = 56 -ALPHA_INS_EXTQL = 57 -ALPHA_INS_EXTWH = 58 -ALPHA_INS_EXTWL = 59 -ALPHA_INS_FBEQ = 60 -ALPHA_INS_FBGE = 61 -ALPHA_INS_FBGT = 62 -ALPHA_INS_FBLE = 63 -ALPHA_INS_FBLT = 64 -ALPHA_INS_FBNE = 65 -ALPHA_INS_FCMOVEQ = 66 -ALPHA_INS_FCMOVGE = 67 -ALPHA_INS_FCMOVGT = 68 -ALPHA_INS_FCMOVLE = 69 -ALPHA_INS_FCMOVLT = 70 -ALPHA_INS_FCMOVNE = 71 -ALPHA_INS_FETCH = 72 -ALPHA_INS_FETCH_M = 73 -ALPHA_INS_FTOIS = 74 -ALPHA_INS_FTOIT = 75 -ALPHA_INS_INSBL = 76 -ALPHA_INS_INSLH = 77 -ALPHA_INS_INSLL = 78 -ALPHA_INS_INSQH = 79 -ALPHA_INS_INSQL = 80 -ALPHA_INS_INSWH = 81 -ALPHA_INS_INSWL = 82 -ALPHA_INS_ITOFS = 83 -ALPHA_INS_ITOFT = 84 -ALPHA_INS_JMP = 85 -ALPHA_INS_JSR = 86 -ALPHA_INS_JSR_COROUTINE = 87 -ALPHA_INS_LDA = 88 -ALPHA_INS_LDAH = 89 -ALPHA_INS_LDBU = 90 -ALPHA_INS_LDL = 91 -ALPHA_INS_LDL_L = 92 -ALPHA_INS_LDQ = 93 -ALPHA_INS_LDQ_L = 94 -ALPHA_INS_LDQ_U = 95 -ALPHA_INS_LDS = 96 -ALPHA_INS_LDT = 97 -ALPHA_INS_LDWU = 98 -ALPHA_INS_MB = 99 -ALPHA_INS_MSKBL = 100 -ALPHA_INS_MSKLH = 101 -ALPHA_INS_MSKLL = 102 -ALPHA_INS_MSKQH = 103 -ALPHA_INS_MSKQL = 104 -ALPHA_INS_MSKWH = 105 -ALPHA_INS_MSKWL = 106 -ALPHA_INS_MULL = 107 -ALPHA_INS_MULQ = 108 -ALPHA_INS_MULSsSU = 109 -ALPHA_INS_MULTsSU = 110 -ALPHA_INS_ORNOT = 111 -ALPHA_INS_RC = 112 -ALPHA_INS_RET = 113 -ALPHA_INS_RPCC = 114 -ALPHA_INS_RS = 115 -ALPHA_INS_S4ADDL = 116 -ALPHA_INS_S4ADDQ = 117 -ALPHA_INS_S4SUBL = 118 -ALPHA_INS_S4SUBQ = 119 -ALPHA_INS_S8ADDL = 120 -ALPHA_INS_S8ADDQ = 121 -ALPHA_INS_S8SUBL = 122 -ALPHA_INS_S8SUBQ = 123 -ALPHA_INS_SEXTB = 124 -ALPHA_INS_SEXTW = 125 -ALPHA_INS_SLL = 126 -ALPHA_INS_SQRTSsSU = 127 -ALPHA_INS_SQRTTsSU = 128 -ALPHA_INS_SRA = 129 -ALPHA_INS_SRL = 130 -ALPHA_INS_STB = 131 -ALPHA_INS_STL = 132 -ALPHA_INS_STL_C = 133 -ALPHA_INS_STQ = 134 -ALPHA_INS_STQ_C = 135 -ALPHA_INS_STQ_U = 136 -ALPHA_INS_STS = 137 -ALPHA_INS_STT = 138 -ALPHA_INS_STW = 139 -ALPHA_INS_SUBL = 140 -ALPHA_INS_SUBQ = 141 -ALPHA_INS_SUBSsSU = 142 -ALPHA_INS_SUBTsSU = 143 -ALPHA_INS_TRAPB = 144 -ALPHA_INS_UMULH = 145 -ALPHA_INS_WH64 = 146 -ALPHA_INS_WH64EN = 147 -ALPHA_INS_WMB = 148 -ALPHA_INS_XOR = 149 -ALPHA_INS_ZAPNOT = 150 -ALPHA_INS_ENDING = 151 +ALPHA_INS_CALL_PAL = 36 +ALPHA_INS_COND_BRANCH = 37 +ALPHA_INS_CPYSE = 38 +ALPHA_INS_CPYSN = 39 +ALPHA_INS_CPYS = 40 +ALPHA_INS_CTLZ = 41 +ALPHA_INS_CTPOP = 42 +ALPHA_INS_CTTZ = 43 +ALPHA_INS_CVTQSSSUI = 44 +ALPHA_INS_CVTQTSSUI = 45 +ALPHA_INS_CVTSTSS = 46 +ALPHA_INS_CVTTQSSVC = 47 +ALPHA_INS_CVTTSSSUI = 48 +ALPHA_INS_DIVSSSU = 49 +ALPHA_INS_DIVTSSU = 50 +ALPHA_INS_ECB = 51 +ALPHA_INS_EQV = 52 +ALPHA_INS_EXCB = 53 +ALPHA_INS_EXTBL = 54 +ALPHA_INS_EXTLH = 55 +ALPHA_INS_EXTLL = 56 +ALPHA_INS_EXTQH = 57 +ALPHA_INS_EXTQL = 58 +ALPHA_INS_EXTWH = 59 +ALPHA_INS_EXTWL = 60 +ALPHA_INS_FBEQ = 61 +ALPHA_INS_FBGE = 62 +ALPHA_INS_FBGT = 63 +ALPHA_INS_FBLE = 64 +ALPHA_INS_FBLT = 65 +ALPHA_INS_FBNE = 66 +ALPHA_INS_FCMOVEQ = 67 +ALPHA_INS_FCMOVGE = 68 +ALPHA_INS_FCMOVGT = 69 +ALPHA_INS_FCMOVLE = 70 +ALPHA_INS_FCMOVLT = 71 +ALPHA_INS_FCMOVNE = 72 +ALPHA_INS_FETCH = 73 +ALPHA_INS_FETCH_M = 74 +ALPHA_INS_FTOIS = 75 +ALPHA_INS_FTOIT = 76 +ALPHA_INS_INSBL = 77 +ALPHA_INS_INSLH = 78 +ALPHA_INS_INSLL = 79 +ALPHA_INS_INSQH = 80 +ALPHA_INS_INSQL = 81 +ALPHA_INS_INSWH = 82 +ALPHA_INS_INSWL = 83 +ALPHA_INS_ITOFS = 84 +ALPHA_INS_ITOFT = 85 +ALPHA_INS_JMP = 86 +ALPHA_INS_JSR = 87 +ALPHA_INS_JSR_COROUTINE = 88 +ALPHA_INS_LDA = 89 +ALPHA_INS_LDAH = 90 +ALPHA_INS_LDBU = 91 +ALPHA_INS_LDL = 92 +ALPHA_INS_LDL_L = 93 +ALPHA_INS_LDQ = 94 +ALPHA_INS_LDQ_L = 95 +ALPHA_INS_LDQ_U = 96 +ALPHA_INS_LDS = 97 +ALPHA_INS_LDT = 98 +ALPHA_INS_LDWU = 99 +ALPHA_INS_MB = 100 +ALPHA_INS_MSKBL = 101 +ALPHA_INS_MSKLH = 102 +ALPHA_INS_MSKLL = 103 +ALPHA_INS_MSKQH = 104 +ALPHA_INS_MSKQL = 105 +ALPHA_INS_MSKWH = 106 +ALPHA_INS_MSKWL = 107 +ALPHA_INS_MULL = 108 +ALPHA_INS_MULQ = 109 +ALPHA_INS_MULSSSU = 110 +ALPHA_INS_MULTSSU = 111 +ALPHA_INS_ORNOT = 112 +ALPHA_INS_RC = 113 +ALPHA_INS_RET = 114 +ALPHA_INS_RPCC = 115 +ALPHA_INS_RS = 116 +ALPHA_INS_S4ADDL = 117 +ALPHA_INS_S4ADDQ = 118 +ALPHA_INS_S4SUBL = 119 +ALPHA_INS_S4SUBQ = 120 +ALPHA_INS_S8ADDL = 121 +ALPHA_INS_S8ADDQ = 122 +ALPHA_INS_S8SUBL = 123 +ALPHA_INS_S8SUBQ = 124 +ALPHA_INS_SEXTB = 125 +ALPHA_INS_SEXTW = 126 +ALPHA_INS_SLL = 127 +ALPHA_INS_SQRTSSSU = 128 +ALPHA_INS_SQRTTSSU = 129 +ALPHA_INS_SRA = 130 +ALPHA_INS_SRL = 131 +ALPHA_INS_STB = 132 +ALPHA_INS_STL = 133 +ALPHA_INS_STL_C = 134 +ALPHA_INS_STQ = 135 +ALPHA_INS_STQ_C = 136 +ALPHA_INS_STQ_U = 137 +ALPHA_INS_STS = 138 +ALPHA_INS_STT = 139 +ALPHA_INS_STW = 140 +ALPHA_INS_SUBL = 141 +ALPHA_INS_SUBQ = 142 +ALPHA_INS_SUBSSSU = 143 +ALPHA_INS_SUBTSSU = 144 +ALPHA_INS_TRAPB = 145 +ALPHA_INS_UMULH = 146 +ALPHA_INS_WH64 = 147 +ALPHA_INS_WH64EN = 148 +ALPHA_INS_WMB = 149 +ALPHA_INS_XOR = 150 +ALPHA_INS_ZAPNOT = 151 +ALPHA_INS_ENDING = 152 # Group of Alpha instructions diff --git a/bindings/python/capstone/m68k_const.py b/bindings/python/capstone/m68k_const.py index 309764ea3..4f283a8fb 100644 --- a/bindings/python/capstone/m68k_const.py +++ b/bindings/python/capstone/m68k_const.py @@ -1,17 +1,4 @@ -from . import ( - CS_OP_INVALID, - CS_OP_REG, - CS_OP_IMM, - CS_OP_FP, - CS_OP_PRED, - CS_OP_SPECIAL, - CS_OP_MEM, - CS_OP_MEM_REG, - CS_OP_MEM_IMM, - UINT16_MAX, - UINT8_MAX, -) - +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py] M68K_OPERAND_COUNT = 6 @@ -99,19 +86,20 @@ M68K_AM_BRANCH_DISPLACEMENT = 19 M68K_OP_INVALID = CS_OP_INVALID M68K_OP_REG = CS_OP_REG M68K_OP_IMM = CS_OP_IMM -M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0 -M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1 -M68K_OP_REG_BITS = CS_OP_SPECIAL + 2 -M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3 -M68K_OP_BR_DISP = CS_OP_SPECIAL + 4 -M68K_OP_SHIFT = CS_OP_SPECIAL + 5 +M68K_OP_FP_SINGLE = CS_OP_SPECIAL+0 +M68K_OP_FP_DOUBLE = CS_OP_SPECIAL+1 +M68K_OP_REG_BITS = CS_OP_SPECIAL+2 +M68K_OP_REG_PAIR = CS_OP_SPECIAL+3 +M68K_OP_BR_DISP = CS_OP_SPECIAL+4 +M68K_OP_SHIFT = CS_OP_SPECIAL+5 M68K_OP_MEM = CS_OP_MEM + M68K_OP_FLAG_NONE = 0 -M68K_OP_FLAG_REG_LOWER = 1 -M68K_OP_FLAG_REG_UPPER = 2 -M68K_OP_FLAG_SHIFT_LEFT = 4 -M68K_OP_FLAG_SHIFT_RIGHT = 8 -M68K_OP_FLAG_MEM_UPDATE = 16 +M68K_OP_FLAG_REG_LOWER = 1<<0 +M68K_OP_FLAG_REG_UPPER = 1<<1 +M68K_OP_FLAG_SHIFT_LEFT = 1<<2 +M68K_OP_FLAG_SHIFT_RIGHT = 1<<3 +M68K_OP_FLAG_MEM_UPDATE = 1<<4 M68K_BF_REG_FLAG = 0x80 M68K_OP_BR_DISP_SIZE_INVALID = 0 @@ -536,7 +524,11 @@ M68K_INS_CP1LD = 399 M68K_INS_CP1NOP = 400 M68K_INS_CP1ST = 401 M68K_INS_TPF = 402 -M68K_INS_ENDING = 403 +M68K_INS_MAAAC = 403 +M68K_INS_MASAC = 404 +M68K_INS_MSAAC = 405 +M68K_INS_MSSAC = 406 +M68K_INS_ENDING = 407 M68K_GRP_INVALID = 0 M68K_GRP_JUMP = 1 diff --git a/include/capstone/alpha.h b/include/capstone/alpha.h index 91b108542..52f0735c9 100644 --- a/include/capstone/alpha.h +++ b/include/capstone/alpha.h @@ -130,8 +130,8 @@ typedef enum alpha_insn { ALPHA_INS_INVALID, ALPHA_INS_ADDL, ALPHA_INS_ADDQ, - ALPHA_INS_ADDSsSU, - ALPHA_INS_ADDTsSU, + ALPHA_INS_ADDSSSU, + ALPHA_INS_ADDTSSU, ALPHA_INS_AND, ALPHA_INS_BEQ, ALPHA_INS_BGE, @@ -157,10 +157,10 @@ typedef enum alpha_insn { ALPHA_INS_CMPEQ, ALPHA_INS_CMPLE, ALPHA_INS_CMPLT, - ALPHA_INS_CMPTEQsSU, - ALPHA_INS_CMPTLEsSU, - ALPHA_INS_CMPTLTsSU, - ALPHA_INS_CMPTUNsSU, + ALPHA_INS_CMPTEQSSU, + ALPHA_INS_CMPTLESSU, + ALPHA_INS_CMPTLTSSU, + ALPHA_INS_CMPTUNSSU, ALPHA_INS_CMPULE, ALPHA_INS_CMPULT, ALPHA_INS_CALL_PAL, @@ -171,13 +171,13 @@ typedef enum alpha_insn { ALPHA_INS_CTLZ, ALPHA_INS_CTPOP, ALPHA_INS_CTTZ, - ALPHA_INS_CVTQSsSUI, - ALPHA_INS_CVTQTsSUI, - ALPHA_INS_CVTSTsS, - ALPHA_INS_CVTTQsSVC, - ALPHA_INS_CVTTSsSUI, - ALPHA_INS_DIVSsSU, - ALPHA_INS_DIVTsSU, + ALPHA_INS_CVTQSSSUI, + ALPHA_INS_CVTQTSSUI, + ALPHA_INS_CVTSTSS, + ALPHA_INS_CVTTQSSVC, + ALPHA_INS_CVTTSSSUI, + ALPHA_INS_DIVSSSU, + ALPHA_INS_DIVTSSU, ALPHA_INS_ECB, ALPHA_INS_EQV, ALPHA_INS_EXCB, @@ -237,8 +237,8 @@ typedef enum alpha_insn { ALPHA_INS_MSKWL, ALPHA_INS_MULL, ALPHA_INS_MULQ, - ALPHA_INS_MULSsSU, - ALPHA_INS_MULTsSU, + ALPHA_INS_MULSSSU, + ALPHA_INS_MULTSSU, ALPHA_INS_ORNOT, ALPHA_INS_RC, ALPHA_INS_RET, @@ -255,8 +255,8 @@ typedef enum alpha_insn { ALPHA_INS_SEXTB, ALPHA_INS_SEXTW, ALPHA_INS_SLL, - ALPHA_INS_SQRTSsSU, - ALPHA_INS_SQRTTsSU, + ALPHA_INS_SQRTSSSU, + ALPHA_INS_SQRTTSSU, ALPHA_INS_SRA, ALPHA_INS_SRL, ALPHA_INS_STB, @@ -270,8 +270,8 @@ typedef enum alpha_insn { ALPHA_INS_STW, ALPHA_INS_SUBL, ALPHA_INS_SUBQ, - ALPHA_INS_SUBSsSU, - ALPHA_INS_SUBTsSU, + ALPHA_INS_SUBSSSU, + ALPHA_INS_SUBTSSU, ALPHA_INS_TRAPB, ALPHA_INS_UMULH, ALPHA_INS_WH64, diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 8ff3a0d79..b0a996b51 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -71,6 +71,7 @@ extern "C" { #define CS_VERSION_ALPHA 0xa000 #define CS_VERSION_ALPHA9 (CS_VERSION_ALPHA | 9) #define CS_VERSION_ALPHA10 (CS_VERSION_ALPHA | 10) +#define CS_VERSION_ALPHA11 (CS_VERSION_ALPHA | 11) #define CS_VERSION_BETA 0xb000 #define CS_VERSION_BETA1 (CS_VERSION_BETA | 1) diff --git a/include/capstone/m68k.h b/include/capstone/m68k.h index 36c13e742..a510a82ff 100644 --- a/include/capstone/m68k.h +++ b/include/capstone/m68k.h @@ -144,10 +144,10 @@ typedef enum m68k_op_type { /// Per-operand modifier flags. typedef enum m68k_op_flags { M68K_OP_FLAG_NONE = 0, - M68K_OP_FLAG_REG_LOWER = - 1 << 0, ///< Lower half of a ColdFire MAC word register operand - M68K_OP_FLAG_REG_UPPER = - 1 << 1, ///< Upper half of a ColdFire MAC word register operand + /// Lower half of a ColdFire MAC word register operand + M68K_OP_FLAG_REG_LOWER = 1 << 0, + /// Upper half of a ColdFire MAC word register operand + M68K_OP_FLAG_REG_UPPER = 1 << 1, M68K_OP_FLAG_SHIFT_LEFT = 1 << 2, ///< ColdFire MAC left-shift operand M68K_OP_FLAG_SHIFT_RIGHT = 1 << 3, ///< ColdFire MAC right-shift operand M68K_OP_FLAG_MEM_UPDATE = 1 << 4, ///< ColdFire MAC memory update marker diff --git a/pkgconfig.mk b/pkgconfig.mk index 5e6da92b9..ed0da9ef8 100644 --- a/pkgconfig.mk +++ b/pkgconfig.mk @@ -9,4 +9,4 @@ PKG_MINOR = 0 PKG_EXTRA = 0 # version tag. Examples: rc1, b2, post1 - or just comment out for no tag -PKG_TAG = alpha9 +PKG_TAG = alpha10