merge next to master

2026-08-11 16:26:07 -04:00 · 2018-07-20 12:36:50 +08:00 · 2018-07-20 12:36:50 +08:00 · 76c1c3c4e9
commit 76c1c3c4e9
parent d64cfab1d8 9783ea8585
392 changed files with 507131 additions and 238448 deletions
--- a/.appveyor.yml
+++ b/.appveyor.yml
@ -1,4 +1,4 @@
-version: 3.0.4-{build}
+version: 4.0-{build}

 os:
  - Visual Studio 2015
--- a/.gitignore
+++ b/.gitignore
@ -1,3 +1,5 @@
+.DS_Store
+
 # Object files
 *.o
 *.ko
@ -36,6 +38,7 @@ bindings/ocaml/*.mli
 bindings/ocaml/test
 bindings/ocaml/test_arm
 bindings/ocaml/test_arm64
+bindings/ocaml/test_basic
 bindings/ocaml/test_mips
 bindings/ocaml/test_x86
 bindings/ocaml/test_detail
@ -43,10 +46,11 @@ bindings/ocaml/test_ppc
 bindings/ocaml/test_sparc
 bindings/ocaml/test_systemz
 bindings/ocaml/test_xcore
+bindings/ocaml/test_m680x


 # test binaries
-tests/test
+tests/test_basic
 tests/test_detail
 tests/test_iter
 tests/test_arm
@ -59,18 +63,15 @@ tests/test_sparc
 tests/test_systemz
 tests/test_xcore
 tests/*.static
-tests/test_basic
 tests/test_customized_mnem
-
-tests/test_m680x
 tests/test_m68k
 tests/test_tms320c64x
+tests/test_m680x
 tests/test_evm

 # regress binaries
 suite/regress/invalid_read_in_print_operand

-
 # vim tmp file
 *.swp
 *~
@ -88,6 +89,7 @@ ProjectUpgradeLog.log
 Debug/
 Release/
 ipch/
+build*/
 *.sdf
 *.opensdf
 *.suo
--- a/.travis.yml
+++ b/.travis.yml
@ -1,26 +1,16 @@
 language: cpp
 sudo: false
-env:
-  global:
-    - LD_LIBRARY_PATH=$TRAVIS_BUILD_DIR/tests/:$TRAVIS_BUILD_DIR:$LD_LIBRARY_PATH
+before_install:
+        - export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
 script:
-  - ./make.sh
-  - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./make.sh install; fi
-  - make check
-  - cd bindings/python && make check
+        - ./make.sh
+        - make check
+        - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then cp libcapstone.so.* bindings/python/libcapstone.so; fi
+        - if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then cp libcapstone.*.dylib bindings/python/libcapstone.dylib; fi
+        - cd bindings/python && make check
 compiler:
-  - clang
-  - gcc
+        - clang
+        - gcc
 os:
-  - linux
-  - osx
-matrix:
-  include:
-    - if: branch = master
-      os: osx
-      script: brew update && brew install --HEAD capstone && brew test capstone
-      compiler: gcc
-    - if: branch = master
-      os: osx
-      script: brew update && brew install --HEAD capstone && brew test capstone
-      compiler: clang
+        - linux
+        - osx
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -1,13 +1,26 @@
 cmake_minimum_required(VERSION 2.6)
 project(capstone)

-set(VERSION_MAJOR 3)
+set(VERSION_MAJOR 4)
 set(VERSION_MINOR 0)
-set(VERSION_PATCH 5)
+set(VERSION_PATCH 0)
+
+if(POLICY CMP0042)
+  # http://www.cmake.org/cmake/help/v3.0/policy/CMP0042.html
+  cmake_policy(SET CMP0042 NEW)
+endif(POLICY CMP0042)
+
+if (POLICY CMP0048)
+  # use old policy to honor version set using VERSION_* variables to preserve backwards
+  # compatibility. change OLD to NEW when minimum cmake version is updated to 3.* and
+  # set VERSION using project(capstone VERSION 4.0.0).
+  # http://www.cmake.org/cmake/help/v3.0/policy/CMP0048.html
+  cmake_policy (SET CMP0048 OLD)
+endif()

 # to configure the options specify them in in the command line or change them in the cmake UI.
 # Don't edit the makefile!
-option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" OFF)
+option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ON)
 option(CAPSTONE_BUILD_STATIC "Build static library" ON)
 option(CAPSTONE_BUILD_SHARED "Build shared library" ON)
 option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
@ -15,14 +28,27 @@ option(CAPSTONE_BUILD_TESTS "Build tests" ON)
 option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON)
 option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)

-option(CAPSTONE_ARM_SUPPORT "ARM support" ON)
-option(CAPSTONE_ARM64_SUPPORT "ARM64 support" ON)
-option(CAPSTONE_MIPS_SUPPORT "MIPS support" ON)
-option(CAPSTONE_PPC_SUPPORT "PowerPC support" ON)
-option(CAPSTONE_SPARC_SUPPORT "Sparc support" ON)
-option(CAPSTONE_SYSZ_SUPPORT "SystemZ support" ON)
-option(CAPSTONE_XCORE_SUPPORT "XCore support" ON)
-option(CAPSTONE_X86_SUPPORT "x86 support" ON)
+set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM)
+set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM)
+
+list(LENGTH SUPPORTED_ARCHITECTURES count)
+math(EXPR count "${count}-1")
+# create options controlling whether support for a particular architecture is needed
+foreach(i RANGE ${count})
+  list(GET SUPPORTED_ARCHITECTURES ${i} supported_architecture)
+  list(GET SUPPORTED_ARCHITECTURE_LABELS ${i} supported_architecture_label)
+  option("CAPSTONE_${supported_architecture}_SUPPORT" "${supported_architecture_label} support" ON)
+endforeach(i)
+
+# propagate achitecture support variables to preprocessor
+foreach(supported_architecture ${SUPPORTED_ARCHITECTURES})
+  set(option_name "CAPSTONE_${supported_architecture}_SUPPORT")
+  if(${option_name})
+    message("Enabling ${option_name}")
+    add_definitions("-D${option_name}")
+  endif()
+endforeach(supported_architecture)
+
 option(CAPSTONE_X86_REDUCE "x86 with reduce instruction sets to minimize library" OFF)
 option(CAPSTONE_X86_ATT_DISABLE "Disable x86 AT&T syntax" OFF)
 option(CAPSTONE_OSXKERNEL_SUPPORT "Support to embed Capstone into OS X Kernel extensions" OFF)
@ -32,6 +58,8 @@ if (MSVC)
    set(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} /MTd")
 endif ()

+enable_testing()
+
 if (CAPSTONE_BUILD_DIET)
    add_definitions(-DCAPSTONE_DIET)
 endif ()
@ -56,33 +84,37 @@ set(SOURCES_ENGINE
    MCRegisterInfo.c
    SStream.c
    utils.c
-    )
-
+)
 set(HEADERS_ENGINE
-    include/capstone.h
-    utils.h
-    MCRegisterInfo.h
+    cs_priv.h
+    LEB128.h
+    MathExtras.h
+    MCDisassembler.h
+    MCFixedLenDisassembler.h
    MCInst.h
    MCInstrDesc.h
+    MCRegisterInfo.h
    SStream.h
-    cs_priv.h
-    include/platform.h
+    utils.h
    )

 set(HEADERS_COMMON
-    include/arm64.h
-    include/arm.h
-    include/capstone.h
-    include/mips.h
-    include/ppc.h
-    include/x86.h
-    include/sparc.h
-    include/systemz.h
-    include/xcore.h
-    include/platform.h
+    include/capstone/arm64.h
+    include/capstone/arm.h
+    include/capstone/capstone.h
+    include/capstone/evm.h
+    include/capstone/mips.h
+    include/capstone/ppc.h
+    include/capstone/x86.h
+    include/capstone/sparc.h
+    include/capstone/systemz.h
+    include/capstone/xcore.h
+    include/capstone/m68k.h
+    include/capstone/tms320c64x.h
+    include/capstone/m680x.h
+    include/capstone/platform.h
    )

-
 set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)

 ## architecture support
@ -93,6 +125,20 @@ if (CAPSTONE_ARM_SUPPORT)
        arch/ARM/ARMInstPrinter.c
        arch/ARM/ARMMapping.c
        arch/ARM/ARMModule.c
+    )
+    set(HEADERS_ARM
+        arch/ARM/ARMAddressingModes.h
+        arch/ARM/ARMBaseInfo.h
+        arch/ARM/ARMDisassembler.h
+        arch/ARM/ARMGenAsmWriter.inc
+        arch/ARM/ARMGenDisassemblerTables.inc
+        arch/ARM/ARMGenInstrInfo.inc
+        arch/ARM/ARMGenRegisterInfo.inc
+        arch/ARM/ARMGenSubtargetInfo.inc
+        arch/ARM/ARMInstPrinter.h
+        arch/ARM/ARMMapping.h
+        arch/ARM/ARMMappingInsn.inc
+        arch/ARM/ARMMappingInsnOp.inc
        )
    set(HEADERS_ARM
        arch/ARM/ARMAddressingModes.h
@ -117,6 +163,19 @@ if (CAPSTONE_ARM64_SUPPORT)
        arch/AArch64/AArch64InstPrinter.c
        arch/AArch64/AArch64Mapping.c
        arch/AArch64/AArch64Module.c
+    )
+    set(HEADERS_ARM64
+        arch/AArch64/AArch64AddressingModes.h
+        arch/AArch64/AArch64BaseInfo.h
+        arch/AArch64/AArch64Disassembler.h
+        arch/AArch64/AArch64GenAsmWriter.inc
+        arch/AArch64/AArch64GenDisassemblerTables.inc
+        arch/AArch64/AArch64GenInstrInfo.inc
+        arch/AArch64/AArch64GenRegisterInfo.inc
+        arch/AArch64/AArch64GenSubtargetInfo.inc
+        arch/AArch64/AArch64InstPrinter.h
+        arch/AArch64/AArch64Mapping.h
+        arch/AArch64/AArch64MappingInsn.inc
        )
    set(HEADERS_ARM64
        arch/AArch64/AArch64AddressingModes.h
@ -140,6 +199,17 @@ if (CAPSTONE_MIPS_SUPPORT)
        arch/Mips/MipsInstPrinter.c
        arch/Mips/MipsMapping.c
        arch/Mips/MipsModule.c
+    )
+    set(HEADERS_MIPS
+        arch/Mips/MipsDisassembler.h
+        arch/Mips/MipsGenAsmWriter.inc
+        arch/Mips/MipsGenDisassemblerTables.inc
+        arch/Mips/MipsGenInstrInfo.inc
+        arch/Mips/MipsGenRegisterInfo.inc
+        arch/Mips/MipsGenSubtargetInfo.inc
+        arch/Mips/MipsInstPrinter.h
+        arch/Mips/MipsMapping.h
+        arch/Mips/MipsMappingInsn.inc
        )
    set(HEADERS_MIPS
        arch/Mips/MipsDisassembler.h
@ -161,6 +231,18 @@ if (CAPSTONE_PPC_SUPPORT)
        arch/PowerPC/PPCInstPrinter.c
        arch/PowerPC/PPCMapping.c
        arch/PowerPC/PPCModule.c
+    )
+    set(HEADERS_PPC
+        arch/PowerPC/PPCDisassembler.h
+        arch/PowerPC/PPCGenAsmWriter.inc
+        arch/PowerPC/PPCGenDisassemblerTables.inc
+        arch/PowerPC/PPCGenInstrInfo.inc
+        arch/PowerPC/PPCGenRegisterInfo.inc
+        arch/PowerPC/PPCGenSubtargetInfo.inc
+        arch/PowerPC/PPCInstPrinter.h
+        arch/PowerPC/PPCMapping.h
+        arch/PowerPC/PPCMappingInsn.inc
+        arch/PowerPC/PPCPredicates.h
        )
    set(HEADERS_PPC
        arch/PowerPC/PPCDisassembler.h
@ -184,6 +266,27 @@ if (CAPSTONE_X86_SUPPORT)
        arch/X86/X86IntelInstPrinter.c
        arch/X86/X86Mapping.c
        arch/X86/X86Module.c
+    )
+    set(HEADERS_X86
+        arch/X86/X86BaseInfo.h
+        arch/X86/X86Disassembler.h
+        arch/X86/X86DisassemblerDecoder.h
+        arch/X86/X86DisassemblerDecoderCommon.h
+        arch/X86/X86GenAsmWriter.inc
+        arch/X86/X86GenAsmWriter1.inc
+        arch/X86/X86GenAsmWriter1_reduce.inc
+        arch/X86/X86GenAsmWriter_reduce.inc
+        arch/X86/X86GenDisassemblerTables.inc
+        arch/X86/X86GenDisassemblerTables_reduce.inc
+        arch/X86/X86GenInstrInfo.inc
+        arch/X86/X86GenInstrInfo_reduce.inc
+        arch/X86/X86GenRegisterInfo.inc
+        arch/X86/X86InstPrinter.h
+        arch/X86/X86Mapping.h
+        arch/X86/X86MappingInsn.inc
+        arch/X86/X86MappingInsnOp.inc
+        arch/X86/X86MappingInsnOp_reduce.inc
+        arch/X86/X86MappingInsn_reduce.inc
        )
    set(HEADERS_X86
        arch/X86/X86BaseInfo.h
@ -205,7 +308,7 @@ if (CAPSTONE_X86_SUPPORT)
    if (NOT CAPSTONE_BUILD_DIET)
        set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
    endif ()
-    set(TEST_SOURCES ${TEST_SOURCES} test_x86.c)
+    set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c)
 endif ()

 if (CAPSTONE_SPARC_SUPPORT)
@ -226,6 +329,7 @@ if (CAPSTONE_SPARC_SUPPORT)
        arch/Sparc/SparcGenSubtargetInfo.inc
        arch/Sparc/SparcInstPrinter.h
        arch/Sparc/SparcMapping.h
+        arch/Sparc/SparcMappingInsn.inc
        )
    set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c)
 endif ()
@ -247,8 +351,9 @@ if (CAPSTONE_SYSZ_SUPPORT)
        arch/SystemZ/SystemZGenRegisterInfo.inc
        arch/SystemZ/SystemZGenSubtargetInfo.inc
        arch/SystemZ/SystemZInstPrinter.h
-        arch/SystemZ/SystemZMCTargetDesc.h
        arch/SystemZ/SystemZMapping.h
+        arch/SystemZ/SystemZMappingInsn.inc
+        arch/SystemZ/SystemZMCTargetDesc.h
        )
    set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c)
 endif ()
@ -269,10 +374,76 @@ if (CAPSTONE_XCORE_SUPPORT)
        arch/XCore/XCoreGenRegisterInfo.inc
        arch/XCore/XCoreInstPrinter.h
        arch/XCore/XCoreMapping.h
+        arch/XCore/XCoreMappingInsn.inc
        )
    set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c)
 endif ()

+if (CAPSTONE_M68K_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_M68K)
+    set(SOURCES_M68K
+		arch/M68K/M68KDisassembler.c
+		arch/M68K/M68KInstPrinter.c
+		arch/M68K/M68KModule.c
+    )
+    set(HEADERS_M68K
+		arch/M68K/M68KDisassembler.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c)
+endif ()
+
+if (CAPSTONE_TMS320C64X_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_TMS320C64X)
+    set(SOURCES_TMS320C64X
+        arch/TMS320C64x/TMS320C64xDisassembler.c
+        arch/TMS320C64x/TMS320C64xInstPrinter.c
+        arch/TMS320C64x/TMS320C64xMapping.c
+        arch/TMS320C64x/TMS320C64xModule.c
+        )
+    set(HEADERS_TMS320C64X
+        arch/TMS320C64x/TMS320C64xDisassembler.h
+        arch/TMS320C64x/TMS320C64xGenAsmWriter.inc
+        arch/TMS320C64x/TMS320C64xGenDisassemblerTables.inc
+        arch/TMS320C64x/TMS320C64xGenInstrInfo.inc
+        arch/TMS320C64x/TMS320C64xGenRegisterInfo.inc
+        arch/TMS320C64x/TMS320C64xInstPrinter.h
+        arch/TMS320C64x/TMS320C64xMapping.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c)
+endif ()
+
+if (CAPSTONE_M680X_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_M680X)
+    set(SOURCES_M680X
+		arch/M680X/M680XDisassembler.c
+		arch/M680X/M680XInstPrinter.c
+		arch/M680X/M680XModule.c
+    )
+    set(HEADERS_M680X
+		arch/M680X/M680XInstPrinter.h
+		arch/M680X/M680XDisassembler.h
+		arch/M680X/M680XDisassemblerInternals.h
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c)
+endif ()
+
+if (CAPSTONE_EVM_SUPPORT)
+    add_definitions(-DCAPSTONE_HAS_EVM)
+    set(SOURCES_EVM
+        arch/EVM/EVMDisassembler.c
+        arch/EVM/EVMInstPrinter.c
+        arch/EVM/EVMMapping.c
+        arch/EVM/EVMModule.c
+    )
+    set(HEADERS_EVM
+        arch/EVM/EVMDisassembler.h
+        arch/EVM/EVMInstPrinter.h
+        arch/EVM/EVMMapping.h
+        arch/EVM/EVMMappingInsn.inc
+        )
+    set(TEST_SOURCES ${TEST_SOURCES} test_evm.c)
+endif ()
+
 if (CAPSTONE_OSXKERNEL_SUPPORT)
    add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
 endif ()
@ -287,6 +458,10 @@ set(ALL_SOURCES
    ${SOURCES_SPARC}
    ${SOURCES_SYSZ}
    ${SOURCES_XCORE}
+    ${SOURCES_M68K}
+    ${SOURCES_TMS320C64X}
+    ${SOURCES_M680X}
+    ${SOURCES_EVM}
    )

 set(ALL_HEADERS
@ -300,6 +475,10 @@ set(ALL_HEADERS
    ${HEADERS_SPARC}
    ${HEADERS_SYSZ}
    ${HEADERS_XCORE}
+    ${HEADERS_M68K}
+    ${HEADERS_TMS320C64X}
+    ${HEADERS_M680X}
+    ${HEADERS_EVM}
    )

 include_directories("${PROJECT_SOURCE_DIR}/include")
@ -318,14 +497,14 @@ endif ()
 # Force static runtime libraries
 if (CAPSTONE_BUILD_STATIC_RUNTIME)
    FOREACH(flag
-        CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
-        CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
-        CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
-        CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
-        if (MSVC)
-            STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
-            SET("${flag}" "${${flag}} /EHsc")
-        endif (MSVC)
+	CMAKE_C_FLAGS_RELEASE CMAKE_C_FLAGS_RELWITHDEBINFO
+	CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_DEBUG_INIT
+	CMAKE_CXX_FLAGS_RELEASE  CMAKE_CXX_FLAGS_RELWITHDEBINFO
+	CMAKE_CXX_FLAGS_DEBUG  CMAKE_CXX_FLAGS_DEBUG_INIT)
+	if (MSVC)
+	    STRING(REPLACE "/MD"  "/MT" "${flag}" "${${flag}}")
+	    SET("${flag}" "${${flag}} /EHsc")
+	endif (MSVC)
    ENDFOREACH()
 endif ()

@ -353,12 +532,14 @@ if (CAPSTONE_BUILD_TESTS)
        STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC})
        add_executable(${TBIN} "tests/${TSRC}")
        target_link_libraries(${TBIN} ${default-target})
+        add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN})
    endforeach ()
    if (CAPSTONE_ARM_SUPPORT)
        set(ARM_REGRESS_TEST test_arm_regression.c)
        STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST})
        add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}")
        target_link_libraries(${ARM_REGRESS_BIN} ${default-target})
+        add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN})
    endif()
    # fuzz target built with the tests
    add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c)
@ -374,6 +555,10 @@ source_group("Source\\Sparc" FILES ${SOURCES_SPARC})
 source_group("Source\\SystemZ" FILES ${SOURCES_SYSZ})
 source_group("Source\\X86" FILES ${SOURCES_X86})
 source_group("Source\\XCore" FILES ${SOURCES_XCORE})
+source_group("Source\\M68K" FILES ${SOURCES_M68K})
+source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X})
+source_group("Source\\M680X" FILES ${SOURCES_M680X})
+source_group("Source\\EVM" FILES ${SOURCES_EVM})

 source_group("Include\\Common" FILES ${HEADERS_COMMON})
 source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@ -385,6 +570,10 @@ source_group("Include\\Sparc" FILES ${HEADERS_SPARC})
 source_group("Include\\SystemZ" FILES ${HEADERS_SYSZ})
 source_group("Include\\X86" FILES ${HEADERS_X86})
 source_group("Include\\XCore" FILES ${HEADERS_XCORE})
+source_group("Include\\M68K" FILES ${HEADERS_M68K})
+source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X})
+source_group("Include\\M680X" FILES ${HEADERS_MC680X})
+source_group("Include\\EVM" FILES ${HEADERS_EVM})

 ### test library 64bit routine:
 get_property(LIB64 GLOBAL PROPERTY FIND_LIBRARY_USE_LIB64_PATHS)
--- a/COMPILE.TXT
+++ b/COMPILE.TXT
@ -7,6 +7,8 @@ To compile using CMake, see COMPILE_CMAKE.TXT.

 To compile using XCode on MacOSX, see xcode/README.md.

+To compile for Windows CE (a.k.a, Windows Embedded Compact), see windowsce/COMPILE.md.
+
                        *-*-*-*-*-*

 Capstone requires no prerequisite packages, so it is easy to compile & install.
@ -15,11 +17,12 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.

 (0) Tailor Capstone to your need.

-  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
-  SystemZ, XCore & X86), if you just need several selected archs, choose which
-  ones you want to compile in by editing "config.mk" before going to next steps.
+  Out of 12 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
+  Sparc, SystemZ, XCore, X86, M680X, TMS320C64x & EVM), if you just need several
+  selected archs, choose the ones you want to compile in by editing "config.mk"
+  before going to next steps.

-  By default, all 8 architectures are compiled.
+  By default, all 12 architectures are compiled.

  The other way of customize Capstone without having to edit config.mk is to
  pass the desired options on the commandline to ./make.sh. Currently,
@ -84,10 +87,14 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
 	/usr/include/capstone/x86.h
 	/usr/include/capstone/arm.h
 	/usr/include/capstone/arm64.h
+	/usr/include/capstone/evm.h
+	/usr/include/capstone/m68k.h
+	/usr/include/capstone/m680x.h
 	/usr/include/capstone/mips.h
 	/usr/include/capstone/ppc.h
 	/usr/include/capstone/sparc.h
 	/usr/include/capstone/systemz.h
+	/usr/include/capstone/tms320c64x.h
 	/usr/include/capstone/xcore.h
 	/usr/include/capstone/platform.h
 	/usr/lib/libcapstone.so (for Linux/*nix), or /usr/lib/libcapstone.dylib (OSX)
@ -139,9 +146,9 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
  To cross-compile for Android (smartphone/tablet), Android NDK is required.
  NOTE: Only ARM and ARM64 are currently supported.

-       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
-       or
-       $ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64
+	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm
+  or
+	$ NDK=/android/android-ndk-r10e ./make.sh cross-android arm64

  Resulted files libcapstone.so, libcapstone.a & tests/test* can then
  be used on Android devices.
--- a/COMPILE_CMAKE.TXT
+++ b/COMPILE_CMAKE.TXT
@ -16,20 +16,25 @@ Get CMake for free from http://www.cmake.org.

 (0) Tailor Capstone to your need.

-  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
-  SystemZ, X86 & XCore), if you just need several selected archs, run "cmake"
-  with the unwanted archs disabled (set to 0) as followings.
+  Out of 12 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
+  Sparc, SystemZ, X86, XCore, M680X, TMS320C64x & EVM), if you just need several selected archs,
+  run "cmake" with the unwanted archs disabled (set to 0) as followings.

  - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM.
  - CAPSTONE_ARM64_SUPPORT: support ARM64. Run cmake with -DCAPSTONE_ARM64_SUPPORT=0 to remove ARM64.
+  - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
+  - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K.
  - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips.
  - CAPSTONE_PPC_SUPPORT: support PPC. Run cmake with -DCAPSTONE_PPC_SUPPORT=0 to remove PPC.
  - CAPSTONE_SPARC_SUPPORT: support Sparc. Run cmake with -DCAPSTONE_SPARC_SUPPORT=0 to remove Sparc.
  - CAPSTONE_SYSZ_SUPPORT: support SystemZ. Run cmake with -DCAPSTONE_SYSZ_SUPPORT=0 to remove SystemZ.
  - CAPSTONE_XCORE_SUPPORT: support XCore. Run cmake with -DCAPSTONE_XCORE_SUPPORT=0 to remove XCore.
  - CAPSTONE_X86_SUPPORT: support X86. Run cmake with -DCAPSTONE_X86_SUPPORT=0 to remove X86.
+  - CAPSTONE_X86_TMS320C64X: support TMS320C64X. Run cmake with -DCAPSTONE_TMS320C64X_SUPPORT=0 to remove TMS320C64X.
+  - CAPSTONE_X86_M680X: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X.
+  - CAPSTONE_X86_EVM: support EVM. Run cmake with -DCAPSTONE_EVM_SUPPORT=0 to remove EVM.

-  By default, all 8 architectures are compiled in.
+  By default, all 10 architectures are compiled in.


  Besides, Capstone also allows some more customization via following macros.
--- a/COMPILE_MSVC.TXT
+++ b/COMPILE_MSVC.TXT
@ -19,9 +19,9 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.

 (0) Tailor Capstone to your need.

-  Out of 8 archtitectures supported by Capstone (Arm, Arm64, Mips, PPC, Sparc,
-  SystemZ, X86 & XCore), if you just need several selected archs, choose the ones
-  you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
+  Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC,
+  Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose
+  the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln",
  then directly editing the projects "capstone_static" & "capstone_dll" for static
  and dynamic libraries, respectively. This must be done before going to the next
  steps.
@ -32,6 +32,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.

  - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support.
  - CAPSTONE_HAS_ARM64: support ARM64. Delete this to remove ARM64 support.
+  - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support.
  - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support.
  - CAPSTONE_HAS_PPC: support PPC. Delete this to remove PPC support.
  - CAPSTONE_HAS_SPARC: support Sparc. Delete this to remove Sparc support.
@ -39,7 +40,7 @@ versions, and Windows Driver Kit 8.1 Update 1 or newer versions are required.
  - CAPSTONE_HAS_X86: support X86. Delete this to remove X86 support.
  - CAPSTONE_HAS_XCORE: support XCore. Delete this to remove XCore support.

-  By default, all 8 architectures are compiled in.
+  By default, all 9 architectures are compiled in.


  Besides, Capstone also allows some more customization via following macros.
--- a/CREDITS.TXT
+++ b/CREDITS.TXT
@ -49,7 +49,7 @@ Axel "0vercl0k" Souchet (@0vercl0k) & Alex Ionescu: port to MSVC.
 Daniel Pistelli: Cmake support.
 Peter Hlavaty: integrate Capstone for Windows kernel drivers.
 Guillaume Jeanne: Ocaml binding.
-Martin Tofall, Obsidium Software: Optimize X86 performance & size.
+Martin Tofall, Obsidium Software: Optimize X86 performance & size + x86 encoding features.
 David Martínez Moreno & Hilko Bengen: Debian package.
 Félix Cloutier: Xcode project.
 Benoit Lecocq: OpenBSD package.
@ -64,3 +64,16 @@ Andrew Dutcher: better Python setup.
 Ruben Boonen: PowerShell binding.
 David Zimmer: VB6 binding.
 Philippe Antoine: Integration with oss-fuzz and various fixes.
+Bui Dinh Cuong: Explicit registers accessed for Arm64.
+Vincent Bénony: Explicit registers accessed for X86.
+Adel Gadllah, Francisco Alonso & Stefan Cornelius: RPM package.
+Felix Gröbert (Google): fuzz testing harness.
+Daniel Collin & Nicolas Planel: M68K architecture.
+Pranith Kumar: Explicit registers accessed for Arm64.
+Xipiter LLC: Capstone logo redesigned.
+Satoshi Tanda: Support Windows kernel driver.
+Koutheir Attouchi: Support for Windows CE.
+Fotis Loukos: TMS320C64x architecture.
+Wolfgang Schwotzer: M680X architecture.
+Philippe Antoine: Integration with oss-fuzz and various fixes.
+Stephen Eckels (stevemk14ebr): x86 encoding features
--- a/101
+++ b/101
@ -1,5 +1,106 @@
 This file details the changelog of Capstone.

+[ Arm ]
+
+- Fix a bug where Arm.Operand is wrongly calculated for the second and
+  following operands
+- Fix a bug where Arm.OpInfo.memBarrier and Arm.OpInfo.op is wrongly
+  calculated
+
+[ Bindings ]
+
+- Java; add Capstone.strerror() and CsInsn.regsAccess().
+
+---------------------------------
+Version 3.0.2: March 11th, 2015
+
+
+[ Library ]
+
+- On *nix, only export symbols that are part of the API (instead of all
+  the internal symbols).
+
+
+[ X86 ]
+
+- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding.
+- Fix implicit registers read/written & instruction groups of some instructions.
+- More flexible on the order of prefixes, so better handle some tricky
+  instructions.
+- REPNE prefix can go with STOS & MOVS instructions.
+- Fix a compilation bug for X86_REDUCE mode.
+- Fix operand size of instructions with operand PTR []
+
+
+[ Arm ]
+
+- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode).
+- Fix a bug on handling the If-Then block.
+
+
+[ Mips ]
+
+- Sanity check for the input size for MIPS64 mode.
+
+
+[ MSVC ]
+
+- Compile capstone.dll with static runtime MSVCR built in.
+
+
+[ Python binding ]
+
+- Fix a compiling issue of Cython binding with gcc 4.9.
+
+---------------------------------
+Version 3.0.1: February 03rd, 2015
+
+[ X86 ]
+
+- Properly handle LOCK, REP, REPE & REPNE prefixes.
+- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
+- Print LJUMP/LCALL without * as prefix for Intel syntax.
+- Handle REX prefix properly for segment/MMX related instructions (x86_64).
+- Instruction with length > 15 is consider invalid.
+- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP,
+  FSTP, FSTPNCE, NOP.
+- Handle some tricky code for some X86_64 instructions with REX prefix.
+- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
+- MOV32ms & MOV32sm should reference word rather than dword.
+
+
+[ Arm64 ]
+
+- BL & BLR instructions do not read SP register.
+- Print absolute (rather than relative) address for instructions B, BL,
+  CBNZ, ADR.
+
+
+[ Arm ]
+
+- Instructions ADC & SBC do not update flags.
+- BL & BLX do not read SP, but PC register.
+- Alias LDR instruction with operands [sp], 4 to POP.
+- Print immediate operand of MVN instruction in positive hexadecimal form.
+
+
+[ PowerPC ]
+
+- Fix some compilation bugs when DIET mode is enable.
+- Populate SLWI/SRWI instruction details with SH operand.
+
+
+[ Python binding ]
+
+- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes.
+- Fixed a memory leak for Cython disasm functions when we immaturely quit
+  the enumeration of disassembled instructions.
+- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable
+  at the same time.
+- Fix a memory leaking bug when when we stop enumeration over the disassembled
+  instructions prematurely.
+- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).
+
 ---------------------------------
 Version 3.0.5: July 1xth, 2018

--- a/HACK.TXT
+++ b/HACK.TXT
@ -5,6 +5,8 @@ Capstone source is organized as followings.
 ├── arch            <- code handling disasm engine for each arch
 │   ├── AArch64     <- ARM64 (aka ARMv8) engine
 │   ├── ARM         <- ARM engine
+│   ├── M680X       <- M680X engine
+│   ├── M68K        <- M68K engine
 │   ├── Mips        <- Mips engine
 │   ├── PowerPC     <- PowerPC engine
 │   ├── Sparc       <- Sparc engine
--- a/LEB128.h
+++ b/LEB128.h
@ -13,14 +13,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_SUPPORT_LEB128_H
 #define CS_LLVM_SUPPORT_LEB128_H

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
+#include "include/capstone/capstone.h"

 /// Utility function to decode a ULEB128 value.
 static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
@ -29,7 +27,7 @@ static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n)
 	uint64_t Value = 0;
 	unsigned Shift = 0;
 	do {
-		Value += (*p & 0x7f) << Shift;
+		Value += (uint64_t)(*p & 0x7f) << Shift;
 		Shift += 7;
 	} while (*p++ >= 128);
 	if (n)
--- a/MCDisassembler.h
+++ b/MCDisassembler.h
@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_MCDISASSEMBLER_H
 #define CS_MCDISASSEMBLER_H
--- a/MCFixedLenDisassembler.h
+++ b/MCFixedLenDisassembler.h
@ -10,7 +10,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
 #define CS_LLVM_MC_MCFIXEDLENDISASSEMBLER_H
--- a/MCInst.c
+++ b/MCInst.c
@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #if defined(CAPSTONE_HAS_OSXKERNEL)
 #include <Availability.h>
@ -29,6 +29,9 @@ void MCInst_Init(MCInst *inst)
 	inst->has_imm = false;
 	inst->op1_size = 0;
 	inst->writeback = false;
+	inst->ac_idx = 0;
+	inst->popcode_adjust = 0;
+	inst->assembly[0] = '\0';
 }

 void MCInst_clear(MCInst *inst)
--- a/MCInst.h
+++ b/MCInst.h
@ -14,15 +14,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_MCINST_H
 #define CS_MCINST_H

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-#include "include/capstone.h"
+#include "include/capstone/capstone.h"

 typedef struct MCInst MCInst;
 typedef struct cs_struct cs_struct;
@ -106,6 +103,11 @@ struct MCInst {
 	uint8_t x86_prefix[4];
 	uint8_t imm_size;	// immediate size for X86_OP_IMM operand
 	bool writeback;	// writeback for ARM
+	// operand access index for list of registers sharing the same access right (for ARM)
+	uint8_t ac_idx;
+	uint8_t popcode_adjust;   // Pseudo X86 instruction adjust
+	char assembly[8];	// for special instruction, so that we dont need printer
+	unsigned char evm_data[32];	// for EVM PUSH operand
 };

 void MCInst_Init(MCInst *inst);
--- a/MCInstrDesc.c
+++ b/MCInstrDesc.c
@ -1,5 +1,5 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #include "MCInstrDesc.h"

--- a/MCInstrDesc.h
+++ b/MCInstrDesc.h
@ -13,15 +13,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_MC_MCINSTRDESC_H
 #define CS_LLVM_MC_MCINSTRDESC_H

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-#include "include/platform.h"
+#include "capstone/platform.h"

 //===----------------------------------------------------------------------===//
 // Machine Operand Flags and Description
@ -113,6 +110,8 @@ enum {
 	MCID_ExtraSrcRegAllocReq,
 	MCID_ExtraDefRegAllocReq,
 	MCID_RegSequence,
+	MCID_ExtractSubreg,
+	MCID_InsertSubreg
 };

 /// MCInstrDesc - Describe properties that are true of each instruction in the
--- a/MCRegisterInfo.c
+++ b/MCRegisterInfo.c
@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #include "MCRegisterInfo.h"

--- a/MCRegisterInfo.h
+++ b/MCRegisterInfo.h
@ -14,15 +14,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_MC_MCREGISTERINFO_H
 #define CS_LLVM_MC_MCREGISTERINFO_H

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-#include "include/platform.h"
+#include "capstone/platform.h"

 /// An unsigned integer type large enough to represent all physical registers,
 /// but not necessarily virtual registers.
@ -30,9 +27,9 @@ typedef uint16_t MCPhysReg;
 typedef const MCPhysReg* iterator;

 typedef struct MCRegisterClass {
-	const char *Name;
 	iterator RegsBegin;
 	const uint8_t *RegSet;
+	uint32_t NameIdx;
 	uint16_t RegsSize;
 	uint16_t RegSetSize;
 	uint16_t ID;
@ -60,6 +57,10 @@ typedef struct MCRegisterDesc {
 	// RegUnits - Points to the list of register units. The low 4 bits holds the
 	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
 	uint32_t RegUnits;
+
+	/// Index into list with lane mask sequences. The sequence contains a lanemask
+	/// for every register unit.
+	uint16_t RegUnitLaneMasks;
 } MCRegisterDesc;

 /// MCRegisterInfo base class - We assume that the target defines a static
@ -104,7 +105,6 @@ void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI,
 		unsigned NumIndices,
 		const uint16_t *RET);

-
 unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC);

 unsigned MCRegisterInfo_getSubReg(const MCRegisterInfo *RI, unsigned Reg, unsigned Idx);
--- a/208
+++ b/208
@ -65,7 +65,7 @@ else
 BLDIR = $(abspath $(BUILDDIR))
 OBJDIR = $(BLDIR)/obj
 endif
-INCDIR = $(DESTDIR)$(PREFIX)/include
+INCDIR ?= $(PREFIX)/include

 UNAME_S := $(shell uname -s)

@ -83,10 +83,10 @@ LIBDATADIR = $(LIBDIR)

 ifndef USE_GENERIC_LIBDATADIR
 ifeq ($(UNAME_S), FreeBSD)
-LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+LIBDATADIR = $(PREFIX)/libdata
 endif
 ifeq ($(UNAME_S), DragonFly)
-LIBDATADIR = $(DESTDIR)$(PREFIX)/libdata
+LIBDATADIR = $(PREFIX)/libdata
 endif
 endif

@ -98,105 +98,77 @@ LIBNAME = capstone


 DEP_ARM =
-DEP_ARM += arch/ARM/ARMGenAsmWriter.inc
-DEP_ARM += arch/ARM/ARMGenDisassemblerTables.inc
-DEP_ARM += arch/ARM/ARMGenInstrInfo.inc
-DEP_ARM += arch/ARM/ARMGenRegisterInfo.inc
-DEP_ARM += arch/ARM/ARMGenSubtargetInfo.inc
+DEP_ARM += $(wildcard arch/ARM/ARM*.inc)

 LIBOBJ_ARM =
 ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_ARM
-	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMDisassembler.o
-	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMInstPrinter.o
-	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMMapping.o
-	LIBOBJ_ARM += $(OBJDIR)/arch/ARM/ARMModule.o
+	LIBSRC_ARM += $(wildcard arch/ARM/ARM*.c)
+	LIBOBJ_ARM += $(LIBSRC_ARM:%.c=$(OBJDIR)/%.o)
 endif

 DEP_ARM64 =
-DEP_ARM64 += arch/AArch64/AArch64GenAsmWriter.inc
-DEP_ARM64 += arch/AArch64/AArch64GenInstrInfo.inc
-DEP_ARM64 += arch/AArch64/AArch64GenSubtargetInfo.inc
-DEP_ARM64 += arch/AArch64/AArch64GenDisassemblerTables.inc
-DEP_ARM64 += arch/AArch64/AArch64GenRegisterInfo.inc
+DEP_ARM64 += $(wildcard arch/AArch64/AArch64*.inc)

 LIBOBJ_ARM64 =
 ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_ARM64
-	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64BaseInfo.o
-	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Disassembler.o
-	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64InstPrinter.o
-	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Mapping.o
-	LIBOBJ_ARM64 += $(OBJDIR)/arch/AArch64/AArch64Module.o
+	LIBSRC_ARM64 += $(wildcard arch/AArch64/AArch64*.c)
+	LIBOBJ_ARM64 += $(LIBSRC_ARM64:%.c=$(OBJDIR)/%.o)
 endif


+DEP_M68K =
+DEP_M68K += $(wildcard arch/M68K/M68K*.h)
+
+LIBOBJ_M68K =
+ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_M68K
+	LIBSRC_M68K += $(wildcard arch/M68K/M68K*.c)
+	LIBOBJ_M68K += $(LIBSRC_M68K:%.c=$(OBJDIR)/%.o)
+endif
+
 DEP_MIPS =
-DEP_MIPS += arch/Mips/MipsGenAsmWriter.inc
-DEP_MIPS += arch/Mips/MipsGenDisassemblerTables.inc
-DEP_MIPS += arch/Mips/MipsGenInstrInfo.inc
-DEP_MIPS += arch/Mips/MipsGenRegisterInfo.inc
-DEP_MIPS += arch/Mips/MipsGenSubtargetInfo.inc
+DEP_MIPS += $(wildcard arch/Mips/Mips*.inc)

 LIBOBJ_MIPS =
 ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_MIPS
-	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsDisassembler.o
-	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsInstPrinter.o
-	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsMapping.o
-	LIBOBJ_MIPS += $(OBJDIR)/arch/Mips/MipsModule.o
+	LIBSRC_MIPS += $(wildcard arch/Mips/Mips*.c)
+	LIBOBJ_MIPS += $(LIBSRC_MIPS:%.c=$(OBJDIR)/%.o)
 endif


 DEP_PPC =
-DEP_PPC += arch/PowerPC/PPCGenAsmWriter.inc
-DEP_PPC += arch/PowerPC/PPCGenInstrInfo.inc
-DEP_PPC += arch/PowerPC/PPCGenSubtargetInfo.inc
-DEP_PPC += arch/PowerPC/PPCGenDisassemblerTables.inc
-DEP_PPC += arch/PowerPC/PPCGenRegisterInfo.inc
+DEP_PPC += $(wildcard arch/PowerPC/PPC*.inc)

 LIBOBJ_PPC =
 ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_POWERPC
-	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCDisassembler.o
-	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCInstPrinter.o
-	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCMapping.o
-	LIBOBJ_PPC += $(OBJDIR)/arch/PowerPC/PPCModule.o
+	LIBSRC_PPC += $(wildcard arch/PowerPC/PPC*.c)
+	LIBOBJ_PPC += $(LIBSRC_PPC:%.c=$(OBJDIR)/%.o)
 endif


 DEP_SPARC =
-DEP_SPARC += arch/Sparc/SparcGenAsmWriter.inc
-DEP_SPARC += arch/Sparc/SparcGenInstrInfo.inc
-DEP_SPARC += arch/Sparc/SparcGenSubtargetInfo.inc
-DEP_SPARC += arch/Sparc/SparcGenDisassemblerTables.inc
-DEP_SPARC += arch/Sparc/SparcGenRegisterInfo.inc
+DEP_SPARC += $(wildcard arch/Sparc/Sparc*.inc)

 LIBOBJ_SPARC =
 ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_SPARC
-	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcDisassembler.o
-	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcInstPrinter.o
-	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcMapping.o
-	LIBOBJ_SPARC += $(OBJDIR)/arch/Sparc/SparcModule.o
+	LIBSRC_SPARC += $(wildcard arch/Sparc/Sparc*.c)
+	LIBOBJ_SPARC += $(LIBSRC_SPARC:%.c=$(OBJDIR)/%.o)
 endif


 DEP_SYSZ =
-DEP_SYSZ += arch/SystemZ/SystemZGenAsmWriter.inc
-DEP_SYSZ += arch/SystemZ/SystemZGenInstrInfo.inc
-DEP_SYSZ += arch/SystemZ/SystemZGenSubtargetInfo.inc
-DEP_SYSZ += arch/SystemZ/SystemZGenDisassemblerTables.inc
-DEP_SYSZ += arch/SystemZ/SystemZGenRegisterInfo.inc
+DEP_SYSZ += $(wildcard arch/SystemZ/SystemZ*.inc)

 LIBOBJ_SYSZ =
 ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_SYSZ
-	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZDisassembler.o
-	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZInstPrinter.o
-	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMapping.o
-	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZModule.o
-	LIBOBJ_SYSZ += $(OBJDIR)/arch/SystemZ/SystemZMCTargetDesc.o
+	LIBSRC_SYSZ += $(wildcard arch/SystemZ/SystemZ*.c)
+	LIBOBJ_SYSZ += $(LIBSRC_SYSZ:%.c=$(OBJDIR)/%.o)
 endif


@ -213,6 +185,9 @@ DEP_X86 += arch/X86/X86GenAsmWriter1$(X86_REDUCE).inc
 DEP_X86 += arch/X86/X86GenDisassemblerTables$(X86_REDUCE).inc
 DEP_X86 += arch/X86/X86GenInstrInfo$(X86_REDUCE).inc
 DEP_X86 += arch/X86/X86GenRegisterInfo.inc
+DEP_X86 += arch/X86/X86MappingInsn$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86MappingInsnOp$(X86_REDUCE).inc
+DEP_X86 += arch/X86/X86ImmSize.inc

 LIBOBJ_X86 =
 ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
@ -232,32 +207,68 @@ endif


 DEP_XCORE =
-DEP_XCORE += arch/XCore/XCoreGenAsmWriter.inc
-DEP_XCORE += arch/XCore/XCoreGenInstrInfo.inc
-DEP_XCORE += arch/XCore/XCoreGenDisassemblerTables.inc
-DEP_XCORE += arch/XCore/XCoreGenRegisterInfo.inc
+DEP_XCORE += $(wildcard arch/XCore/XCore*.inc)

 LIBOBJ_XCORE =
 ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
 	CFLAGS += -DCAPSTONE_HAS_XCORE
-	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreDisassembler.o
-	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreInstPrinter.o
-	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreMapping.o
-	LIBOBJ_XCORE += $(OBJDIR)/arch/XCore/XCoreModule.o
+	LIBSRC_XCORE += $(wildcard arch/XCore/XCore*.c)
+	LIBOBJ_XCORE += $(LIBSRC_XCORE:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_TMS320C64X =
+DEP_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.inc)
+
+LIBOBJ_TMS320C64X =
+ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_TMS320C64X
+	LIBSRC_TMS320C64X += $(wildcard arch/TMS320C64x/TMS320C64x*.c)
+	LIBOBJ_TMS320C64X += $(LIBSRC_TMS320C64X:%.c=$(OBJDIR)/%.o)
+endif
+
+DEP_M680X =
+DEP_M680X += $(wildcard arch/M680X/*.inc)
+DEP_M680X += $(wildcard arch/M680X/M680X*.h)
+
+LIBOBJ_M680X =
+ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_M680X
+	LIBSRC_M680X += $(wildcard arch/M680X/*.c)
+	LIBOBJ_M680X += $(LIBSRC_M680X:%.c=$(OBJDIR)/%.o)
+endif
+
+
+DEP_EVM =
+DEP_EVM += $(wildcard arch/EVM/EVM*.inc)
+
+LIBOBJ_EVM =
+ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
+	CFLAGS += -DCAPSTONE_HAS_EVM
+	LIBSRC_EVM += $(wildcard arch/EVM/EVM*.c)
+	LIBOBJ_EVM += $(LIBSRC_EVM:%.c=$(OBJDIR)/%.o)
 endif


 LIBOBJ =
 LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o
-LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE)
+LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_ARM64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM)
 LIBOBJ += $(OBJDIR)/MCInst.o


+ifeq ($(PKG_EXTRA),)
+PKGCFGDIR = $(LIBDATADIR)/pkgconfig
+else
 PKGCFGDIR ?= $(LIBDATADIR)/pkgconfig
-API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
+ifeq ($(PKGCFGDIR),)
+PKGCFGDIR = $(LIBDATADIR)/pkgconfig
+endif
+endif
+
+API_MAJOR=$(shell echo `grep -e CS_API_MAJOR include/capstone/capstone.h | grep -v = | awk '{print $$3}'` | awk '{print $$1}')
 VERSION_EXT =

-IS_APPLE := $(shell $(CC) -dM -E - < /dev/null | grep -cm 1 -e __apple_build_version__ -e __APPLE_CC__)
+IS_APPLE := $(shell $(CC) -dM -E - < /dev/null 2> /dev/null | grep __apple_build_version__ | wc -l | tr -d " ")
 ifeq ($(IS_APPLE),1)
 # on MacOS, compile in Universal format by default
 MACOS_UNIVERSAL ?= yes
@ -282,7 +293,7 @@ CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
 LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
 $(LIBNAME)_LDFLAGS += -shared
 # Cygwin?
-IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l)
+IS_CYGWIN := $(shell $(CC) -dumpmachine 2>/dev/null | grep -i cygwin | wc -l)
 ifeq ($(IS_CYGWIN),1)
 EXT = dll
 AR_EXT = lib
@ -291,7 +302,7 @@ CFLAGS := $(CFLAGS:-fPIC=)
 # On Windows we need the shared library to be executable
 else
 # mingw?
-IS_MINGW := $(shell $(CC) --version | grep -i mingw | wc -l)
+IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i mingw | wc -l)
 ifeq ($(IS_MINGW),1)
 EXT = dll
 AR_EXT = lib
@ -310,11 +321,11 @@ endif

 ifeq ($(CAPSTONE_SHARED),yes)
 ifeq ($(IS_MINGW),1)
-LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
 else ifeq ($(IS_CYGWIN),1)
-LIBRARY = $(BLDIR)/$(LIBNAME).$(EXT)
+LIBRARY = $(BLDIR)/$(LIBNAME).$(VERSION_EXT)
 else	# *nix
-LIBRARY = $(BLDIR)/lib$(LIBNAME).$(EXT)
+LIBRARY = $(BLDIR)/lib$(LIBNAME).$(VERSION_EXT)
 CFLAGS += -fvisibility=hidden
 endif
 endif
@ -354,16 +365,20 @@ else
 endif
 endif

-$(LIBOBJ): *.h include/*.h config.mk
+$(LIBOBJ): config.mk *.h include/capstone/*.h

 $(LIBOBJ_ARM): $(DEP_ARM)
 $(LIBOBJ_ARM64): $(DEP_ARM64)
+$(LIBOBJ_M68K): $(DEP_M68K)
 $(LIBOBJ_MIPS): $(DEP_MIPS)
 $(LIBOBJ_PPC): $(DEP_PPC)
 $(LIBOBJ_SPARC): $(DEP_SPARC)
 $(LIBOBJ_SYSZ): $(DEP_SYSZ)
 $(LIBOBJ_X86): $(DEP_X86)
 $(LIBOBJ_XCORE): $(DEP_XCORE)
+$(LIBOBJ_TMS320C64X): $(DEP_TMS320C64X)
+$(LIBOBJ_M680X): $(DEP_M680X)
+$(LIBOBJ_EVM): $(DEP_EVM)

 ifeq ($(CAPSTONE_STATIC),yes)
 $(ARCHIVE): $(LIBOBJ)
@ -385,23 +400,23 @@ else
 endif

 install: $(PKGCFGF) $(ARCHIVE) $(LIBRARY)
-	mkdir -p $(LIBDIR)
-	$(call install-library,$(LIBDIR))
+	mkdir -p $(DESTDIR)$(LIBDIR)
+	$(call install-library,$(DESTDIR)$(LIBDIR))
 ifeq ($(CAPSTONE_STATIC),yes)
-	$(INSTALL_DATA) $(ARCHIVE) $(LIBDIR)
+	$(INSTALL_DATA) $(ARCHIVE) $(DESTDIR)$(LIBDIR)
 endif
-	mkdir -p $(INCDIR)/$(LIBNAME)
-	$(INSTALL_DATA) include/*.h $(INCDIR)/$(LIBNAME)
-	mkdir -p $(PKGCFGDIR)
-	$(INSTALL_DATA) $(PKGCFGF) $(PKGCFGDIR)/
-	mkdir -p $(BINDIR)
-	$(INSTALL_LIB) cstool/cstool $(BINDIR)
+	mkdir -p $(DESTDIR)$(INCDIR)/$(LIBNAME)
+	$(INSTALL_DATA) include/capstone/*.h $(DESTDIR)$(INCDIR)/$(LIBNAME)
+	mkdir -p $(DESTDIR)$(PKGCFGDIR)
+	$(INSTALL_DATA) $(PKGCFGF) $(DESTDIR)$(PKGCFGDIR)
+	mkdir -p $(DESTDIR)$(BINDIR)
+	$(INSTALL_LIB) cstool/cstool $(DESTDIR)$(BINDIR)

 uninstall:
-	rm -rf $(INCDIR)/$(LIBNAME)
-	rm -f $(LIBDIR)/lib$(LIBNAME).*
-	rm -f $(PKGCFGDIR)/$(LIBNAME).pc
-	rm -f $(BINDIR)/cstool
+	rm -rf $(DESTDIR)$(INCDIR)/$(LIBNAME)
+	rm -f $(DESTDIR)$(LIBDIR)/lib$(LIBNAME).*
+	rm -f $(DESTDIR)$(PKGCFGDIR)/$(LIBNAME).pc
+	rm -f $(DESTDIR)$(BINDIR)/cstool

 clean:
 	rm -f $(LIBOBJ)
@ -437,12 +452,12 @@ dist:
 	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip


-TESTS = test_basic test_detail test_arm test_arm64 test_mips test_ppc test_sparc
-TESTS += test_systemz test_x86 test_xcore test_iter
+TESTS = test_basic test_detail test_arm test_arm64 test_m68k test_mips test_ppc test_sparc
+TESTS += test_systemz test_x86 test_xcore test_iter test_evm
 TESTS += test_basic.static test_detail.static test_arm.static test_arm64.static
-TESTS += test_mips.static test_ppc.static test_sparc.static
-TESTS += test_systemz.static test_x86.static test_xcore.static
-TESTS += test_skipdata test_skipdata.static test_iter.static
+TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
+TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
+TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static
 check: $(TESTS)
 test_%:
 	./tests/$@ > /dev/null && echo OK || echo FAILED
@ -462,7 +477,7 @@ define install-library
 	$(INSTALL_LIB) $(LIBRARY) $1
 	$(if $(VERSION_EXT),
 		cd $1 && \
-		mv lib$(LIBNAME).$(EXT) lib$(LIBNAME).$(VERSION_EXT) && \
+		rm -f lib$(LIBNAME).$(EXT) && \
 		ln -s lib$(LIBNAME).$(VERSION_EXT) lib$(LIBNAME).$(EXT))
 endef
 else
@ -483,11 +498,12 @@ endef


 define generate-pkgcfg
+	mkdir -p $(BLDIR)
 	echo 'Name: capstone' > $(PKGCFGF)
 	echo 'Description: Capstone disassembly engine' >> $(PKGCFGF)
 	echo 'Version: $(PKG_VERSION)' >> $(PKGCFGF)
 	echo 'libdir=$(LIBDIR)' >> $(PKGCFGF)
-	echo 'includedir=$(INCDIR)/capstone' >> $(PKGCFGF)
+	echo 'includedir=$(INCDIR)' >> $(PKGCFGF)
 	echo 'archive=$${libdir}/libcapstone.a' >> $(PKGCFGF)
 	echo 'Libs: -L$${libdir} -lcapstone' >> $(PKGCFGF)
 	echo 'Cflags: -I$${includedir}' >> $(PKGCFGF)
--- a/MathExtras.h
+++ b/MathExtras.h
@ -12,17 +12,15 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_SUPPORT_MATHEXTRAS_H
 #define CS_LLVM_SUPPORT_MATHEXTRAS_H

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
-#ifdef _MSC_VER
-# include <intrin.h>
+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+#include "windowsce/intrin.h"
+#elif defined(_MSC_VER)
+#include <intrin.h>
 #endif

 #ifndef __cplusplus
--- a/README.md
+++ b/README.md
@ -1,11 +1,17 @@
+Capstone Engine
+===============
+
+[![Build Status](https://travis-ci.org/aquynh/capstone.svg?branch=next)](https://travis-ci.org/aquynh/capstone)
+[![Build status](https://ci.appveyor.com/api/projects/status/a4wvbn89wu3pinas/branch/next?svg=true)](https://ci.appveyor.com/project/aquynh/capstone/branch/next)
+
 Capstone is a disassembly framework with the target of becoming the ultimate
 disasm engine for binary analysis and reversing in the security community.

 Created by Nguyen Anh Quynh, then developed and maintained by a small community,
 Capstone offers some unparalleled features:

- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
-  SystemZ, XCore and X86 (including X86_64).
+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Ethereum VM, M68K,
+  Mips, PPC, Sparc, SystemZ, TMS320C64X, M680X, XCore and X86 (including X86_64).

 - Having clean/simple/lightweight/intuitive architecture-neutral API.

@ -14,13 +20,13 @@ Capstone offers some unparalleled features:
 - Provide semantics of the disassembled instruction, such as list of implicit
  registers read & written.

- Implemented in pure C language, with lightweight bindings for Visual Basic, PHP,
-  PowerShell, Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml,
-  Lua, Rust, Delphi, Free Pascal & Vala ready either in main code, or provided
+- Implemented in pure C language, with lightweight bindings for Visual Basic, PHP, PowerShell,
+  Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua,
+  Rust, Delphi, Free Pascal & Vala ready either in main code, or provided
  externally by the community).

 - Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
-  Linux, *BSD, Solaris, etc.
+  Linux, \*BSD, Solaris, etc.

 - Thread-safe by design.

@ -34,22 +40,26 @@ Capstone offers some unparalleled features:
 Further information is available at http://www.capstone-engine.org


-[Compile]
+Compile
+-------

 See COMPILE.TXT file for how to compile and install Capstone.


-[Documentation]
+Documentation
+-------------

 See docs/README for how to customize & program your own tools with Capstone.


-[Hack]
+Hack
+----

 See HACK.TXT file for the structure of the source code.


-[License]
+License
+-------

 This project is released under the BSD license. If you redistribute the binary
 or source code of Capstone, please attach file LICENSE.TXT with your products.
--- a/SStream.c
+++ b/SStream.c
@ -1,9 +1,6 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
 #include <stdarg.h>
 #if defined(CAPSTONE_HAS_OSXKERNEL)
 #include <Availability.h>
@ -15,7 +12,7 @@
 #endif
 #include <string.h>

-#include <platform.h>
+#include <capstone/platform.h>

 #include "SStream.h"
 #include "cs_priv.h"
@ -64,11 +61,12 @@ void printInt64Bang(SStream *O, int64_t val)
 		else
 			SStream_concat(O, "#%"PRIu64, val);
 	} else {
-		if (val <- HEX_THRESHOLD)
+		if (val <- HEX_THRESHOLD) {
 			if (val == LONG_MIN)
-				SStream_concat(O, "#-0x%"PRIx64, val);
+				SStream_concat(O, "#-0x%"PRIx64, (uint64_t)val);
 			else
-				SStream_concat(O, "#-0x%"PRIx64, -val);
+				SStream_concat(O, "#-0x%"PRIx64, (uint64_t)-val);
+		}
 		else
 			SStream_concat(O, "#-%"PRIu64, -val);
 	}
@ -91,11 +89,12 @@ void printInt64(SStream *O, int64_t val)
 		else
 			SStream_concat(O, "%"PRIu64, val);
 	} else {
-		if (val <- HEX_THRESHOLD)
+		if (val <- HEX_THRESHOLD) {
 			if (val == LONG_MIN)
-				SStream_concat(O, "-0x%"PRIx64, val);
+				SStream_concat(O, "-0x%"PRIx64, (uint64_t)val);
 			else
-				SStream_concat(O, "-0x%"PRIx64, -val);
+				SStream_concat(O, "-0x%"PRIx64, (uint64_t)-val);
+		}
 		else
 			SStream_concat(O, "-%"PRIu64, -val);
 	}
@ -110,7 +109,7 @@ void printInt32BangDec(SStream *O, int32_t val)
 		if (val == INT_MIN)
 			SStream_concat(O, "#-%u", val);
 		else
-			SStream_concat(O, "#-%u", -val);
+			SStream_concat(O, "#-%u", (uint32_t)-val);
 }

 void printInt32Bang(SStream *O, int32_t val)
@ -121,11 +120,12 @@ void printInt32Bang(SStream *O, int32_t val)
 		else
 			SStream_concat(O, "#%u", val);
 	} else {
-		if (val <- HEX_THRESHOLD)
+		if (val <- HEX_THRESHOLD) {
 			if (val == INT_MIN)
-				SStream_concat(O, "#-0x%x", val);
+				SStream_concat(O, "#-0x%x", (uint32_t)val);
 			else
-				SStream_concat(O, "#-0x%x", -val);
+				SStream_concat(O, "#-0x%x", (uint32_t)-val);
+		}
 		else
 			SStream_concat(O, "#-%u", -val);
 	}
@ -139,11 +139,12 @@ void printInt32(SStream *O, int32_t val)
 		else
 			SStream_concat(O, "%u", val);
 	} else {
-		if (val <- HEX_THRESHOLD)
+		if (val <- HEX_THRESHOLD) {
 			if (val == INT_MIN)
-				SStream_concat(O, "-0x%x", val);
+				SStream_concat(O, "-0x%x", (uint32_t)val);
 			else
-				SStream_concat(O, "-0x%x", -val);
+				SStream_concat(O, "-0x%x", (uint32_t)-val);
+			}
 		else
 			SStream_concat(O, "-%u", -val);
 	}
--- a/SStream.h
+++ b/SStream.h
@ -1,9 +1,11 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_SSTREAM_H_
 #define CS_SSTREAM_H_

+#include "include/capstone/platform.h"
+
 typedef struct SStream {
 	char buffer[512];
 	int index;
--- a/arch/AArch64/AArch64AddressingModes.h
+++ b/arch/AArch64/AArch64AddressingModes.h
@ -15,7 +15,7 @@
 #define CS_AARCH64_ADDRESSINGMODES_H

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #include "../../MathExtras.h"

@ -198,7 +198,7 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm)
 	// where B = NOT(b);

 	FPUnion.I = 0;
-	FPUnion.I |= ((uint32_t) Sign) << 31;
+	FPUnion.I |= ((uint32_t)Sign) << 31;
 	FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
 	FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
 	FPUnion.I |= (Exp & 0x3) << 23;
--- a/arch/AArch64/AArch64BaseInfo.c
+++ b/arch/AArch64/AArch64BaseInfo.c
@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifdef CAPSTONE_HAS_ARM64

@ -627,17 +627,16 @@ static const A64NamedImmMapper_Mapping CycloneSysRegPairs[] = {
 };

 // result must be a big enough buffer: 128 bytes is more than enough
-void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result)
+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result)
 {
 	int dummy;
 	uint32_t Op0, Op1, CRn, CRm, Op2;
-	char *Op1S, *CRnS, *CRmS, *Op2S;
+	char *Op0S, *Op1S, *CRnS, *CRmS, *Op2S;
 	unsigned i;

 	// First search the registers shared by all
 	for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) {
 		if (SysRegPairs[i].Value == Bits) {
-			*Valid = true;
 			strcpy(result, SysRegPairs[i].Name);
 			return;
 		}
@ -648,7 +647,6 @@ void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Val
 	if (true) {
 		for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) {
 			if (CycloneSysRegPairs[i].Value == Bits) {
-				*Valid = true;
 				strcpy(result, CycloneSysRegPairs[i].Name);
 				return;
 			}
@ -659,7 +657,6 @@ void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Val
 	// write-only).
 	for (i = 0; i < S->NumInstPairs; ++i) {
 		if (S->InstPairs[i].Value == Bits) {
-			*Valid = true;
 			strcpy(result, S->InstPairs[i].Name);
 			return;
 		}
@ -671,17 +668,7 @@ void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Val
 	CRm = (Bits >> 3) & 0xf;
 	Op2 = Bits & 0x7;

-	// Only combinations matching: 11 xxx 1x11 xxxx xxx are valid for a generic
-	// name.
-	if (Op0 != 3 || (CRn != 11 && CRn != 15)) {
-		*Valid = false;
-		return;
-	}
-
-	//assert(Op0 == 3 && (CRn == 11 || CRn == 15) && "Invalid generic sysreg");
-
-	*Valid = true;
-
+	Op0S = utostr(Op0, false);
 	Op1S = utostr(Op1, false);
 	CRnS = utostr(CRn, false);
 	CRmS = utostr(CRm, false);
@ -691,6 +678,7 @@ void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Val
 	dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S);
 	(void)dummy;

+	cs_mem_free(Op0S);
 	cs_mem_free(Op1S);
 	cs_mem_free(CRnS);
 	cs_mem_free(CRmS);
--- a/arch/AArch64/AArch64BaseInfo.h
+++ b/arch/AArch64/AArch64BaseInfo.h
@ -15,15 +15,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_AARCH64_BASEINFO_H
 #define CS_LLVM_AARCH64_BASEINFO_H

 #include <ctype.h>
-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
 #include <string.h>

 #ifndef __cplusplus
@ -1008,6 +1005,6 @@ uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bo

 bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value);

-void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, bool *Valid, char *result);
+void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result);

 #endif
--- a/arch/AArch64/AArch64Disassembler.c
+++ b/arch/AArch64/AArch64Disassembler.c
@ -14,7 +14,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifdef CAPSTONE_HAS_ARM64

@ -233,16 +233,16 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
 	}

 	if (MI->flat_insn->detail) {
-		memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm64)+sizeof(cs_arm64));
 		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
 			MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
 	}

 	if (MODE_IS_BIG_ENDIAN(ud->mode))
 		insn = (code[3] << 0) | (code[2] << 8) |
-			(code[1] <<  16) | (((uint32_t) code[0]) << 24);
+			(code[1] <<  16) | ((uint32_t) code[0] << 24);
 	else
-		insn = (((uint32_t) code[3]) << 24) | (code[2] << 16) |
+		insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
 			(code[1] <<  8) | (code[0] <<  0);

 	// Calling the auto-generated decoder function.
@ -703,30 +703,20 @@ static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
 static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
 		uint64_t Address, const void *Decoder)
 {
-	bool ValidNamed;
-	char result[128];
-
-	Imm |= 0x8000;
 	MCOperand_CreateImm0(Inst, Imm);

-	A64SysRegMapper_toString(&AArch64_MRSMapper, Imm, &ValidNamed, result);
-
-	return ValidNamed ? Success : Fail;
+	// Every system register in the encoding space is valid with the syntax
+	// S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
+	return Success;
 }

 static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
 		uint64_t Address,
 		const void *Decoder)
 {
-	bool ValidNamed;
-	char result[128];
-
-	Imm |= 0x8000;
 	MCOperand_CreateImm0(Inst, Imm);

-	A64SysRegMapper_toString(&AArch64_MSRMapper, Imm, &ValidNamed, result);
-
-	return ValidNamed ? Success : Fail;
+	return Success;
 }

 static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
@ -1269,7 +1259,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
 	unsigned Rt = fieldFromInstruction(insn, 0, 5);
 	unsigned Rn = fieldFromInstruction(insn, 5, 5);
 	unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
-	int64_t offset = fieldFromInstruction(insn, 15, 7);
+	int32_t offset = fieldFromInstruction(insn, 15, 7);
 	bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
 	unsigned Opcode = MCInst_getOpcode(Inst);
 	bool NeedsDisjointWritebackTransfer = false;
--- a/arch/AArch64/AArch64Disassembler.h
+++ b/arch/AArch64/AArch64Disassembler.h
@ -1,14 +1,10 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_AARCH64_DISASSEMBLER_H
 #define CS_AARCH64_DISASSEMBLER_H

-#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
-#include <stdint.h>
-#endif
-
-#include "../../include/capstone.h"
+#include "capstone/capstone.h"
 #include "../../MCRegisterInfo.h"
 #include "../../MCInst.h"

--- a/arch/AArch64/AArch64GenAsmWriter.inc
+++ b/arch/AArch64/AArch64GenAsmWriter.inc
@ -7,7 +7,7 @@
 \*===----------------------------------------------------------------------===*/

 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 /// printInstruction - This method is automatically generated by tablegen
 /// from the instruction set description.
@ -34,6 +34,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
    0U,	// STACKMAP
    0U,	// PATCHPOINT
    0U,	// LOAD_STACK_GUARD
+    0U,	// STATEPOINT
+    0U,	// FRAME_ALLOC
    6182U,	// ABSv16i8
    553920550U,	// ABSv1i64
    1074272294U,	// ABSv2i32
@ -2426,6 +2428,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
    0U,	// STACKMAP
    0U,	// PATCHPOINT
    0U,	// LOAD_STACK_GUARD
+    0U,	// STATEPOINT
+    0U,	// FRAME_ALLOC
    0U,	// ABSv16i8
    0U,	// ABSv1i64
    0U,	// ABSv2i32
@ -6848,7 +6852,7 @@ static const char *getRegisterName(unsigned RegNo, int AltIdx)
  /* 1774 */ 'n', 'z', 'c', 'v', 0,
  };

-  static const uint32_t RegAsmOffsetNoRegAltName[] = {
+  static const uint16_t RegAsmOffsetNoRegAltName[] = {
    1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, 
    1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, 
    313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, 
@ -6916,7 +6920,7 @@ static const char *getRegisterName(unsigned RegNo, int AltIdx)
  /* 115 */ 'v', '9', 0,
  };

-  static const uint32_t RegAsmOffsetvreg[] = {
+  static const uint16_t RegAsmOffsetvreg[] = {
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 
    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 
@ -6949,7 +6953,7 @@ static const char *getRegisterName(unsigned RegNo, int AltIdx)
    107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 
  };

-  const uint32_t *RegAsmOffset;
+  const uint16_t *RegAsmOffset;
  const char *AsmStrs;

  switch(AltIdx) {
@ -6964,10 +6968,10 @@ static const char *getRegisterName(unsigned RegNo, int AltIdx)
    break;
  }
  //int i;
-  //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/4; i++)
+  //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/2; i++)
  //     printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1);
  //printf("*************************\n");
-  //for (i = 0; i < sizeof(RegAsmOffsetvreg)/4; i++)
+  //for (i = 0; i < sizeof(RegAsmOffsetvreg)/2; i++)
  //     printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1);
  //printf("-------------------------\n");
  return AsmStrs+RegAsmOffset[RegNo-1];
--- a/arch/AArch64/AArch64GenDisassemblerTables.inc
+++ b/arch/AArch64/AArch64GenDisassemblerTables.inc
--- a/arch/AArch64/AArch64GenInstrInfo.inc
+++ b/arch/AArch64/AArch64GenInstrInfo.inc
--- a/arch/AArch64/AArch64GenRegisterInfo.inc
+++ b/arch/AArch64/AArch64GenRegisterInfo.inc
@ -7,7 +7,7 @@
 \*===----------------------------------------------------------------------===*/

 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */


 #ifdef GET_REGINFO_ENUM
@ -481,7 +481,7 @@ enum {
  AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 39,
  AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 40,
  AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 41,
-  AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 42
+  AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 42,
 };

 // Register alternate name indices
@ -561,7 +561,7 @@ enum {
 \*===----------------------------------------------------------------------===*/

 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */


 #ifdef GET_REGINFO_MC_DESC
@ -638,427 +638,427 @@ static const uint16_t AArch64SubRegIdxLists[] = {
  /* 86 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 13, 30, 32, 31, 29, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0,
 };

-static const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
-  { 3, 0, 0, 0, 0 },
-  { 1518, 266, 4, 5, 10001 },
-  { 1525, 266, 4, 5, 10001 },
-  { 1536, 4, 4, 4, 10001 },
-  { 1522, 3, 4, 5, 3152 },
-  { 1521, 4, 625, 4, 3152 },
-  { 1528, 4, 3, 4, 3184 },
-  { 1532, 625, 4, 5, 3184 },
-  { 146, 4, 101, 4, 9969 },
-  { 335, 4, 146, 4, 9969 },
-  { 480, 4, 206, 4, 9969 },
-  { 625, 4, 68, 4, 9969 },
-  { 768, 4, 68, 4, 9969 },
-  { 911, 4, 68, 4, 9969 },
-  { 1054, 4, 68, 4, 9969 },
-  { 1197, 4, 68, 4, 9969 },
-  { 1340, 4, 68, 4, 9969 },
-  { 1479, 4, 68, 4, 9969 },
-  { 0, 4, 68, 4, 9969 },
-  { 191, 4, 68, 4, 9969 },
-  { 378, 4, 68, 4, 9969 },
-  { 521, 4, 68, 4, 9969 },
-  { 664, 4, 68, 4, 9969 },
-  { 807, 4, 68, 4, 9969 },
-  { 950, 4, 68, 4, 9969 },
-  { 1093, 4, 68, 4, 9969 },
-  { 1236, 4, 68, 4, 9969 },
-  { 1379, 4, 68, 4, 9969 },
-  { 46, 4, 68, 4, 9969 },
-  { 239, 4, 68, 4, 9969 },
-  { 428, 4, 68, 4, 9969 },
-  { 573, 4, 68, 4, 9969 },
-  { 716, 4, 68, 4, 9969 },
-  { 859, 4, 68, 4, 9969 },
-  { 1002, 4, 68, 4, 9969 },
-  { 1145, 4, 68, 4, 9969 },
-  { 1288, 4, 68, 4, 9969 },
-  { 1431, 4, 68, 4, 9969 },
-  { 98, 4, 68, 4, 9969 },
-  { 291, 4, 68, 4, 9969 },
-  { 161, 426, 104, 1, 9697 },
-  { 349, 426, 149, 1, 9697 },
-  { 493, 426, 209, 1, 9697 },
-  { 637, 426, 71, 1, 9697 },
-  { 780, 426, 71, 1, 9697 },
-  { 923, 426, 71, 1, 9697 },
-  { 1066, 426, 71, 1, 9697 },
-  { 1209, 426, 71, 1, 9697 },
-  { 1352, 426, 71, 1, 9697 },
-  { 1491, 426, 71, 1, 9697 },
-  { 13, 426, 71, 1, 9697 },
-  { 205, 426, 71, 1, 9697 },
-  { 393, 426, 71, 1, 9697 },
-  { 537, 426, 71, 1, 9697 },
-  { 680, 426, 71, 1, 9697 },
-  { 823, 426, 71, 1, 9697 },
-  { 966, 426, 71, 1, 9697 },
-  { 1109, 426, 71, 1, 9697 },
-  { 1252, 426, 71, 1, 9697 },
-  { 1395, 426, 71, 1, 9697 },
-  { 62, 426, 71, 1, 9697 },
-  { 255, 426, 71, 1, 9697 },
-  { 444, 426, 71, 1, 9697 },
-  { 589, 426, 71, 1, 9697 },
-  { 732, 426, 71, 1, 9697 },
-  { 875, 426, 71, 1, 9697 },
-  { 1018, 426, 71, 1, 9697 },
-  { 1161, 426, 71, 1, 9697 },
-  { 1304, 426, 71, 1, 9697 },
-  { 1447, 426, 71, 1, 9697 },
-  { 114, 426, 71, 1, 9697 },
-  { 307, 426, 71, 1, 9697 },
-  { 164, 428, 102, 3, 6705 },
-  { 352, 428, 147, 3, 6705 },
-  { 496, 428, 207, 3, 6705 },
-  { 640, 428, 69, 3, 6705 },
-  { 783, 428, 69, 3, 6705 },
-  { 926, 428, 69, 3, 6705 },
-  { 1069, 428, 69, 3, 6705 },
-  { 1212, 428, 69, 3, 6705 },
-  { 1355, 428, 69, 3, 6705 },
-  { 1494, 428, 69, 3, 6705 },
-  { 17, 428, 69, 3, 6705 },
-  { 209, 428, 69, 3, 6705 },
-  { 397, 428, 69, 3, 6705 },
-  { 541, 428, 69, 3, 6705 },
-  { 684, 428, 69, 3, 6705 },
-  { 827, 428, 69, 3, 6705 },
-  { 970, 428, 69, 3, 6705 },
-  { 1113, 428, 69, 3, 6705 },
-  { 1256, 428, 69, 3, 6705 },
-  { 1399, 428, 69, 3, 6705 },
-  { 66, 428, 69, 3, 6705 },
-  { 259, 428, 69, 3, 6705 },
-  { 448, 428, 69, 3, 6705 },
-  { 593, 428, 69, 3, 6705 },
-  { 736, 428, 69, 3, 6705 },
-  { 879, 428, 69, 3, 6705 },
-  { 1022, 428, 69, 3, 6705 },
-  { 1165, 428, 69, 3, 6705 },
-  { 1308, 428, 69, 3, 6705 },
-  { 1451, 428, 69, 3, 6705 },
-  { 118, 428, 69, 3, 6705 },
-  { 311, 428, 69, 3, 6705 },
-  { 179, 439, 124, 0, 4801 },
-  { 366, 439, 169, 0, 4801 },
-  { 509, 439, 229, 0, 4801 },
-  { 652, 439, 91, 0, 4801 },
-  { 795, 439, 91, 0, 4801 },
-  { 938, 439, 91, 0, 4801 },
-  { 1081, 439, 91, 0, 4801 },
-  { 1224, 439, 91, 0, 4801 },
-  { 1367, 439, 91, 0, 4801 },
-  { 1506, 439, 91, 0, 4801 },
-  { 30, 439, 91, 0, 4801 },
-  { 223, 439, 91, 0, 4801 },
-  { 412, 439, 91, 0, 4801 },
-  { 557, 439, 91, 0, 4801 },
-  { 700, 439, 91, 0, 4801 },
-  { 843, 439, 91, 0, 4801 },
-  { 986, 439, 91, 0, 4801 },
-  { 1129, 439, 91, 0, 4801 },
-  { 1272, 439, 91, 0, 4801 },
-  { 1415, 439, 91, 0, 4801 },
-  { 82, 439, 91, 0, 4801 },
-  { 275, 439, 91, 0, 4801 },
-  { 464, 439, 91, 0, 4801 },
-  { 609, 439, 91, 0, 4801 },
-  { 752, 439, 91, 0, 4801 },
-  { 895, 439, 91, 0, 4801 },
-  { 1038, 439, 91, 0, 4801 },
-  { 1181, 439, 91, 0, 4801 },
-  { 1324, 439, 91, 0, 4801 },
-  { 1467, 439, 91, 0, 4801 },
-  { 134, 439, 91, 0, 4801 },
-  { 327, 439, 91, 0, 4801 },
-  { 182, 427, 103, 2, 4769 },
-  { 369, 427, 148, 2, 4769 },
-  { 512, 427, 208, 2, 4769 },
-  { 655, 427, 70, 2, 4769 },
-  { 798, 427, 70, 2, 4769 },
-  { 941, 427, 70, 2, 4769 },
-  { 1084, 427, 70, 2, 4769 },
-  { 1227, 427, 70, 2, 4769 },
-  { 1370, 427, 70, 2, 4769 },
-  { 1509, 427, 70, 2, 4769 },
-  { 34, 427, 70, 2, 4769 },
-  { 227, 427, 70, 2, 4769 },
-  { 416, 427, 70, 2, 4769 },
-  { 561, 427, 70, 2, 4769 },
-  { 704, 427, 70, 2, 4769 },
-  { 847, 427, 70, 2, 4769 },
-  { 990, 427, 70, 2, 4769 },
-  { 1133, 427, 70, 2, 4769 },
-  { 1276, 427, 70, 2, 4769 },
-  { 1419, 427, 70, 2, 4769 },
-  { 86, 427, 70, 2, 4769 },
-  { 279, 427, 70, 2, 4769 },
-  { 468, 427, 70, 2, 4769 },
-  { 613, 427, 70, 2, 4769 },
-  { 756, 427, 70, 2, 4769 },
-  { 899, 427, 70, 2, 4769 },
-  { 1042, 427, 70, 2, 4769 },
-  { 1185, 427, 70, 2, 4769 },
-  { 1328, 427, 70, 2, 4769 },
-  { 1471, 427, 70, 2, 4769 },
-  { 138, 427, 70, 2, 4769 },
-  { 331, 427, 70, 2, 4769 },
-  { 185, 4, 256, 4, 4769 },
-  { 372, 4, 256, 4, 4769 },
-  { 515, 4, 256, 4, 4769 },
-  { 658, 4, 256, 4, 4769 },
-  { 801, 4, 256, 4, 4769 },
-  { 944, 4, 256, 4, 4769 },
-  { 1087, 4, 256, 4, 4769 },
-  { 1230, 4, 256, 4, 4769 },
-  { 1373, 4, 256, 4, 4769 },
-  { 1512, 4, 256, 4, 4769 },
-  { 38, 4, 256, 4, 4769 },
-  { 231, 4, 256, 4, 4769 },
-  { 420, 4, 256, 4, 4769 },
-  { 565, 4, 256, 4, 4769 },
-  { 708, 4, 256, 4, 4769 },
-  { 851, 4, 256, 4, 4769 },
-  { 994, 4, 256, 4, 4769 },
-  { 1137, 4, 256, 4, 4769 },
-  { 1280, 4, 256, 4, 4769 },
-  { 1423, 4, 256, 4, 4769 },
-  { 90, 4, 256, 4, 4769 },
-  { 283, 4, 256, 4, 4769 },
-  { 472, 4, 256, 4, 4769 },
-  { 617, 4, 256, 4, 4769 },
-  { 760, 4, 256, 4, 4769 },
-  { 903, 4, 256, 4, 4769 },
-  { 1046, 4, 256, 4, 4769 },
-  { 1189, 4, 256, 4, 4769 },
-  { 1332, 4, 256, 4, 4769 },
-  { 1475, 4, 294, 4, 4673 },
-  { 142, 4, 294, 4, 4673 },
-  { 188, 621, 4, 5, 4737 },
-  { 375, 621, 4, 5, 4737 },
-  { 518, 621, 4, 5, 4737 },
-  { 661, 621, 4, 5, 4737 },
-  { 804, 621, 4, 5, 4737 },
-  { 947, 621, 4, 5, 4737 },
-  { 1090, 621, 4, 5, 4737 },
-  { 1233, 621, 4, 5, 4737 },
-  { 1376, 621, 4, 5, 4737 },
-  { 1515, 621, 4, 5, 4737 },
-  { 42, 621, 4, 5, 4737 },
-  { 235, 621, 4, 5, 4737 },
-  { 424, 621, 4, 5, 4737 },
-  { 569, 621, 4, 5, 4737 },
-  { 712, 621, 4, 5, 4737 },
-  { 855, 621, 4, 5, 4737 },
-  { 998, 621, 4, 5, 4737 },
-  { 1141, 621, 4, 5, 4737 },
-  { 1284, 621, 4, 5, 4737 },
-  { 1427, 621, 4, 5, 4737 },
-  { 94, 621, 4, 5, 4737 },
-  { 287, 621, 4, 5, 4737 },
-  { 476, 621, 4, 5, 4737 },
-  { 621, 621, 4, 5, 4737 },
-  { 764, 621, 4, 5, 4737 },
-  { 907, 621, 4, 5, 4737 },
-  { 1050, 621, 4, 5, 4737 },
-  { 1193, 621, 4, 5, 4737 },
-  { 1336, 621, 4, 5, 4737 },
-  { 346, 430, 179, 7, 1041 },
-  { 490, 430, 243, 7, 1041 },
-  { 634, 430, 134, 7, 1041 },
-  { 777, 430, 134, 7, 1041 },
-  { 920, 430, 134, 7, 1041 },
-  { 1063, 430, 134, 7, 1041 },
-  { 1206, 430, 134, 7, 1041 },
-  { 1349, 430, 134, 7, 1041 },
-  { 1488, 430, 134, 7, 1041 },
-  { 10, 430, 134, 7, 1041 },
-  { 201, 430, 134, 7, 1041 },
-  { 389, 430, 134, 7, 1041 },
-  { 533, 430, 134, 7, 1041 },
-  { 676, 430, 134, 7, 1041 },
-  { 819, 430, 134, 7, 1041 },
-  { 962, 430, 134, 7, 1041 },
-  { 1105, 430, 134, 7, 1041 },
-  { 1248, 430, 134, 7, 1041 },
-  { 1391, 430, 134, 7, 1041 },
-  { 58, 430, 134, 7, 1041 },
-  { 251, 430, 134, 7, 1041 },
-  { 440, 430, 134, 7, 1041 },
-  { 585, 430, 134, 7, 1041 },
-  { 728, 430, 134, 7, 1041 },
-  { 871, 430, 134, 7, 1041 },
-  { 1014, 430, 134, 7, 1041 },
-  { 1157, 430, 134, 7, 1041 },
-  { 1300, 430, 134, 7, 1041 },
-  { 1443, 430, 134, 7, 1041 },
-  { 110, 430, 134, 7, 1041 },
-  { 303, 430, 134, 7, 1041 },
-  { 157, 421, 134, 7, 4080 },
-  { 628, 562, 264, 31, 81 },
-  { 771, 562, 264, 31, 81 },
-  { 914, 562, 264, 31, 81 },
-  { 1057, 562, 264, 31, 81 },
-  { 1200, 562, 264, 31, 81 },
-  { 1343, 562, 264, 31, 81 },
-  { 1482, 562, 264, 31, 81 },
-  { 4, 562, 264, 31, 81 },
-  { 195, 562, 264, 31, 81 },
-  { 382, 562, 264, 31, 81 },
-  { 525, 562, 264, 31, 81 },
-  { 668, 562, 264, 31, 81 },
-  { 811, 562, 264, 31, 81 },
-  { 954, 562, 264, 31, 81 },
-  { 1097, 562, 264, 31, 81 },
-  { 1240, 562, 264, 31, 81 },
-  { 1383, 562, 264, 31, 81 },
-  { 50, 562, 264, 31, 81 },
-  { 243, 562, 264, 31, 81 },
-  { 432, 562, 264, 31, 81 },
-  { 577, 562, 264, 31, 81 },
-  { 720, 562, 264, 31, 81 },
-  { 863, 562, 264, 31, 81 },
-  { 1006, 562, 264, 31, 81 },
-  { 1149, 562, 264, 31, 81 },
-  { 1292, 562, 264, 31, 81 },
-  { 1435, 562, 264, 31, 81 },
-  { 102, 562, 264, 31, 81 },
-  { 295, 562, 264, 31, 81 },
-  { 149, 584, 264, 31, 160 },
-  { 338, 397, 264, 31, 368 },
-  { 483, 540, 264, 31, 3216 },
-  { 487, 32, 258, 16, 305 },
-  { 631, 32, 191, 16, 305 },
-  { 774, 32, 191, 16, 305 },
-  { 917, 32, 191, 16, 305 },
-  { 1060, 32, 191, 16, 305 },
-  { 1203, 32, 191, 16, 305 },
-  { 1346, 32, 191, 16, 305 },
-  { 1485, 32, 191, 16, 305 },
-  { 7, 32, 191, 16, 305 },
-  { 198, 32, 191, 16, 305 },
-  { 385, 32, 191, 16, 305 },
-  { 529, 32, 191, 16, 305 },
-  { 672, 32, 191, 16, 305 },
-  { 815, 32, 191, 16, 305 },
-  { 958, 32, 191, 16, 305 },
-  { 1101, 32, 191, 16, 305 },
-  { 1244, 32, 191, 16, 305 },
-  { 1387, 32, 191, 16, 305 },
-  { 54, 32, 191, 16, 305 },
-  { 247, 32, 191, 16, 305 },
-  { 436, 32, 191, 16, 305 },
-  { 581, 32, 191, 16, 305 },
-  { 724, 32, 191, 16, 305 },
-  { 867, 32, 191, 16, 305 },
-  { 1010, 32, 191, 16, 305 },
-  { 1153, 32, 191, 16, 305 },
-  { 1296, 32, 191, 16, 305 },
-  { 1439, 32, 191, 16, 305 },
-  { 106, 32, 191, 16, 305 },
-  { 299, 32, 191, 16, 305 },
-  { 153, 47, 191, 16, 448 },
-  { 342, 608, 191, 16, 3824 },
-  { 363, 268, 185, 53, 993 },
-  { 506, 268, 249, 53, 993 },
-  { 649, 268, 140, 53, 993 },
-  { 792, 268, 140, 53, 993 },
-  { 935, 268, 140, 53, 993 },
-  { 1078, 268, 140, 53, 993 },
-  { 1221, 268, 140, 53, 993 },
-  { 1364, 268, 140, 53, 993 },
-  { 1503, 268, 140, 53, 993 },
-  { 27, 268, 140, 53, 993 },
-  { 219, 268, 140, 53, 993 },
-  { 408, 268, 140, 53, 993 },
-  { 553, 268, 140, 53, 993 },
-  { 696, 268, 140, 53, 993 },
-  { 839, 268, 140, 53, 993 },
-  { 982, 268, 140, 53, 993 },
-  { 1125, 268, 140, 53, 993 },
-  { 1268, 268, 140, 53, 993 },
-  { 1411, 268, 140, 53, 993 },
-  { 78, 268, 140, 53, 993 },
-  { 271, 268, 140, 53, 993 },
-  { 460, 268, 140, 53, 993 },
-  { 605, 268, 140, 53, 993 },
-  { 748, 268, 140, 53, 993 },
-  { 891, 268, 140, 53, 993 },
-  { 1034, 268, 140, 53, 993 },
-  { 1177, 268, 140, 53, 993 },
-  { 1320, 268, 140, 53, 993 },
-  { 1463, 268, 140, 53, 993 },
-  { 130, 268, 140, 53, 993 },
-  { 323, 268, 140, 53, 993 },
-  { 175, 280, 140, 53, 4080 },
-  { 643, 476, 4, 86, 1 },
-  { 786, 476, 4, 86, 1 },
-  { 929, 476, 4, 86, 1 },
-  { 1072, 476, 4, 86, 1 },
-  { 1215, 476, 4, 86, 1 },
-  { 1358, 476, 4, 86, 1 },
-  { 1497, 476, 4, 86, 1 },
-  { 21, 476, 4, 86, 1 },
-  { 213, 476, 4, 86, 1 },
-  { 401, 476, 4, 86, 1 },
-  { 545, 476, 4, 86, 1 },
-  { 688, 476, 4, 86, 1 },
-  { 831, 476, 4, 86, 1 },
-  { 974, 476, 4, 86, 1 },
-  { 1117, 476, 4, 86, 1 },
-  { 1260, 476, 4, 86, 1 },
-  { 1403, 476, 4, 86, 1 },
-  { 70, 476, 4, 86, 1 },
-  { 263, 476, 4, 86, 1 },
-  { 452, 476, 4, 86, 1 },
-  { 597, 476, 4, 86, 1 },
-  { 740, 476, 4, 86, 1 },
-  { 883, 476, 4, 86, 1 },
-  { 1026, 476, 4, 86, 1 },
-  { 1169, 476, 4, 86, 1 },
-  { 1312, 476, 4, 86, 1 },
-  { 1455, 476, 4, 86, 1 },
-  { 122, 476, 4, 86, 1 },
-  { 315, 476, 4, 86, 1 },
-  { 167, 508, 4, 86, 160 },
-  { 355, 365, 4, 86, 368 },
-  { 499, 444, 4, 86, 3216 },
-  { 503, 302, 261, 65, 241 },
-  { 646, 302, 88, 65, 241 },
-  { 789, 302, 88, 65, 241 },
-  { 932, 302, 88, 65, 241 },
-  { 1075, 302, 88, 65, 241 },
-  { 1218, 302, 88, 65, 241 },
-  { 1361, 302, 88, 65, 241 },
-  { 1500, 302, 88, 65, 241 },
-  { 24, 302, 88, 65, 241 },
-  { 216, 302, 88, 65, 241 },
-  { 404, 302, 88, 65, 241 },
-  { 549, 302, 88, 65, 241 },
-  { 692, 302, 88, 65, 241 },
-  { 835, 302, 88, 65, 241 },
-  { 978, 302, 88, 65, 241 },
-  { 1121, 302, 88, 65, 241 },
-  { 1264, 302, 88, 65, 241 },
-  { 1407, 302, 88, 65, 241 },
-  { 74, 302, 88, 65, 241 },
-  { 267, 302, 88, 65, 241 },
-  { 456, 302, 88, 65, 241 },
-  { 601, 302, 88, 65, 241 },
-  { 744, 302, 88, 65, 241 },
-  { 887, 302, 88, 65, 241 },
-  { 1030, 302, 88, 65, 241 },
-  { 1173, 302, 88, 65, 241 },
-  { 1316, 302, 88, 65, 241 },
-  { 1459, 302, 88, 65, 241 },
-  { 126, 302, 88, 65, 241 },
-  { 319, 302, 88, 65, 241 },
-  { 171, 323, 88, 65, 448 },
-  { 359, 344, 88, 65, 3824 },
+static MCRegisterDesc AArch64RegDesc[] = { // Descriptors
+  { 3, 0, 0, 0, 0, 0 },
+  { 1518, 266, 4, 5, 10001, 26 },
+  { 1525, 266, 4, 5, 10001, 26 },
+  { 1536, 4, 4, 4, 10001, 0 },
+  { 1522, 3, 4, 5, 3152, 26 },
+  { 1521, 4, 625, 4, 3152, 0 },
+  { 1528, 4, 3, 4, 3184, 0 },
+  { 1532, 625, 4, 5, 3184, 26 },
+  { 146, 4, 101, 4, 9969, 0 },
+  { 335, 4, 146, 4, 9969, 0 },
+  { 480, 4, 206, 4, 9969, 0 },
+  { 625, 4, 68, 4, 9969, 0 },
+  { 768, 4, 68, 4, 9969, 0 },
+  { 911, 4, 68, 4, 9969, 0 },
+  { 1054, 4, 68, 4, 9969, 0 },
+  { 1197, 4, 68, 4, 9969, 0 },
+  { 1340, 4, 68, 4, 9969, 0 },
+  { 1479, 4, 68, 4, 9969, 0 },
+  { 0, 4, 68, 4, 9969, 0 },
+  { 191, 4, 68, 4, 9969, 0 },
+  { 378, 4, 68, 4, 9969, 0 },
+  { 521, 4, 68, 4, 9969, 0 },
+  { 664, 4, 68, 4, 9969, 0 },
+  { 807, 4, 68, 4, 9969, 0 },
+  { 950, 4, 68, 4, 9969, 0 },
+  { 1093, 4, 68, 4, 9969, 0 },
+  { 1236, 4, 68, 4, 9969, 0 },
+  { 1379, 4, 68, 4, 9969, 0 },
+  { 46, 4, 68, 4, 9969, 0 },
+  { 239, 4, 68, 4, 9969, 0 },
+  { 428, 4, 68, 4, 9969, 0 },
+  { 573, 4, 68, 4, 9969, 0 },
+  { 716, 4, 68, 4, 9969, 0 },
+  { 859, 4, 68, 4, 9969, 0 },
+  { 1002, 4, 68, 4, 9969, 0 },
+  { 1145, 4, 68, 4, 9969, 0 },
+  { 1288, 4, 68, 4, 9969, 0 },
+  { 1431, 4, 68, 4, 9969, 0 },
+  { 98, 4, 68, 4, 9969, 0 },
+  { 291, 4, 68, 4, 9969, 0 },
+  { 161, 426, 104, 1, 9697, 3 },
+  { 349, 426, 149, 1, 9697, 3 },
+  { 493, 426, 209, 1, 9697, 3 },
+  { 637, 426, 71, 1, 9697, 3 },
+  { 780, 426, 71, 1, 9697, 3 },
+  { 923, 426, 71, 1, 9697, 3 },
+  { 1066, 426, 71, 1, 9697, 3 },
+  { 1209, 426, 71, 1, 9697, 3 },
+  { 1352, 426, 71, 1, 9697, 3 },
+  { 1491, 426, 71, 1, 9697, 3 },
+  { 13, 426, 71, 1, 9697, 3 },
+  { 205, 426, 71, 1, 9697, 3 },
+  { 393, 426, 71, 1, 9697, 3 },
+  { 537, 426, 71, 1, 9697, 3 },
+  { 680, 426, 71, 1, 9697, 3 },
+  { 823, 426, 71, 1, 9697, 3 },
+  { 966, 426, 71, 1, 9697, 3 },
+  { 1109, 426, 71, 1, 9697, 3 },
+  { 1252, 426, 71, 1, 9697, 3 },
+  { 1395, 426, 71, 1, 9697, 3 },
+  { 62, 426, 71, 1, 9697, 3 },
+  { 255, 426, 71, 1, 9697, 3 },
+  { 444, 426, 71, 1, 9697, 3 },
+  { 589, 426, 71, 1, 9697, 3 },
+  { 732, 426, 71, 1, 9697, 3 },
+  { 875, 426, 71, 1, 9697, 3 },
+  { 1018, 426, 71, 1, 9697, 3 },
+  { 1161, 426, 71, 1, 9697, 3 },
+  { 1304, 426, 71, 1, 9697, 3 },
+  { 1447, 426, 71, 1, 9697, 3 },
+  { 114, 426, 71, 1, 9697, 3 },
+  { 307, 426, 71, 1, 9697, 3 },
+  { 164, 428, 102, 3, 6705, 3 },
+  { 352, 428, 147, 3, 6705, 3 },
+  { 496, 428, 207, 3, 6705, 3 },
+  { 640, 428, 69, 3, 6705, 3 },
+  { 783, 428, 69, 3, 6705, 3 },
+  { 926, 428, 69, 3, 6705, 3 },
+  { 1069, 428, 69, 3, 6705, 3 },
+  { 1212, 428, 69, 3, 6705, 3 },
+  { 1355, 428, 69, 3, 6705, 3 },
+  { 1494, 428, 69, 3, 6705, 3 },
+  { 17, 428, 69, 3, 6705, 3 },
+  { 209, 428, 69, 3, 6705, 3 },
+  { 397, 428, 69, 3, 6705, 3 },
+  { 541, 428, 69, 3, 6705, 3 },
+  { 684, 428, 69, 3, 6705, 3 },
+  { 827, 428, 69, 3, 6705, 3 },
+  { 970, 428, 69, 3, 6705, 3 },
+  { 1113, 428, 69, 3, 6705, 3 },
+  { 1256, 428, 69, 3, 6705, 3 },
+  { 1399, 428, 69, 3, 6705, 3 },
+  { 66, 428, 69, 3, 6705, 3 },
+  { 259, 428, 69, 3, 6705, 3 },
+  { 448, 428, 69, 3, 6705, 3 },
+  { 593, 428, 69, 3, 6705, 3 },
+  { 736, 428, 69, 3, 6705, 3 },
+  { 879, 428, 69, 3, 6705, 3 },
+  { 1022, 428, 69, 3, 6705, 3 },
+  { 1165, 428, 69, 3, 6705, 3 },
+  { 1308, 428, 69, 3, 6705, 3 },
+  { 1451, 428, 69, 3, 6705, 3 },
+  { 118, 428, 69, 3, 6705, 3 },
+  { 311, 428, 69, 3, 6705, 3 },
+  { 179, 439, 124, 0, 4801, 3 },
+  { 366, 439, 169, 0, 4801, 3 },
+  { 509, 439, 229, 0, 4801, 3 },
+  { 652, 439, 91, 0, 4801, 3 },
+  { 795, 439, 91, 0, 4801, 3 },
+  { 938, 439, 91, 0, 4801, 3 },
+  { 1081, 439, 91, 0, 4801, 3 },
+  { 1224, 439, 91, 0, 4801, 3 },
+  { 1367, 439, 91, 0, 4801, 3 },
+  { 1506, 439, 91, 0, 4801, 3 },
+  { 30, 439, 91, 0, 4801, 3 },
+  { 223, 439, 91, 0, 4801, 3 },
+  { 412, 439, 91, 0, 4801, 3 },
+  { 557, 439, 91, 0, 4801, 3 },
+  { 700, 439, 91, 0, 4801, 3 },
+  { 843, 439, 91, 0, 4801, 3 },
+  { 986, 439, 91, 0, 4801, 3 },
+  { 1129, 439, 91, 0, 4801, 3 },
+  { 1272, 439, 91, 0, 4801, 3 },
+  { 1415, 439, 91, 0, 4801, 3 },
+  { 82, 439, 91, 0, 4801, 3 },
+  { 275, 439, 91, 0, 4801, 3 },
+  { 464, 439, 91, 0, 4801, 3 },
+  { 609, 439, 91, 0, 4801, 3 },
+  { 752, 439, 91, 0, 4801, 3 },
+  { 895, 439, 91, 0, 4801, 3 },
+  { 1038, 439, 91, 0, 4801, 3 },
+  { 1181, 439, 91, 0, 4801, 3 },
+  { 1324, 439, 91, 0, 4801, 3 },
+  { 1467, 439, 91, 0, 4801, 3 },
+  { 134, 439, 91, 0, 4801, 3 },
+  { 327, 439, 91, 0, 4801, 3 },
+  { 182, 427, 103, 2, 4769, 3 },
+  { 369, 427, 148, 2, 4769, 3 },
+  { 512, 427, 208, 2, 4769, 3 },
+  { 655, 427, 70, 2, 4769, 3 },
+  { 798, 427, 70, 2, 4769, 3 },
+  { 941, 427, 70, 2, 4769, 3 },
+  { 1084, 427, 70, 2, 4769, 3 },
+  { 1227, 427, 70, 2, 4769, 3 },
+  { 1370, 427, 70, 2, 4769, 3 },
+  { 1509, 427, 70, 2, 4769, 3 },
+  { 34, 427, 70, 2, 4769, 3 },
+  { 227, 427, 70, 2, 4769, 3 },
+  { 416, 427, 70, 2, 4769, 3 },
+  { 561, 427, 70, 2, 4769, 3 },
+  { 704, 427, 70, 2, 4769, 3 },
+  { 847, 427, 70, 2, 4769, 3 },
+  { 990, 427, 70, 2, 4769, 3 },
+  { 1133, 427, 70, 2, 4769, 3 },
+  { 1276, 427, 70, 2, 4769, 3 },
+  { 1419, 427, 70, 2, 4769, 3 },
+  { 86, 427, 70, 2, 4769, 3 },
+  { 279, 427, 70, 2, 4769, 3 },
+  { 468, 427, 70, 2, 4769, 3 },
+  { 613, 427, 70, 2, 4769, 3 },
+  { 756, 427, 70, 2, 4769, 3 },
+  { 899, 427, 70, 2, 4769, 3 },
+  { 1042, 427, 70, 2, 4769, 3 },
+  { 1185, 427, 70, 2, 4769, 3 },
+  { 1328, 427, 70, 2, 4769, 3 },
+  { 1471, 427, 70, 2, 4769, 3 },
+  { 138, 427, 70, 2, 4769, 3 },
+  { 331, 427, 70, 2, 4769, 3 },
+  { 185, 4, 256, 4, 4769, 0 },
+  { 372, 4, 256, 4, 4769, 0 },
+  { 515, 4, 256, 4, 4769, 0 },
+  { 658, 4, 256, 4, 4769, 0 },
+  { 801, 4, 256, 4, 4769, 0 },
+  { 944, 4, 256, 4, 4769, 0 },
+  { 1087, 4, 256, 4, 4769, 0 },
+  { 1230, 4, 256, 4, 4769, 0 },
+  { 1373, 4, 256, 4, 4769, 0 },
+  { 1512, 4, 256, 4, 4769, 0 },
+  { 38, 4, 256, 4, 4769, 0 },
+  { 231, 4, 256, 4, 4769, 0 },
+  { 420, 4, 256, 4, 4769, 0 },
+  { 565, 4, 256, 4, 4769, 0 },
+  { 708, 4, 256, 4, 4769, 0 },
+  { 851, 4, 256, 4, 4769, 0 },
+  { 994, 4, 256, 4, 4769, 0 },
+  { 1137, 4, 256, 4, 4769, 0 },
+  { 1280, 4, 256, 4, 4769, 0 },
+  { 1423, 4, 256, 4, 4769, 0 },
+  { 90, 4, 256, 4, 4769, 0 },
+  { 283, 4, 256, 4, 4769, 0 },
+  { 472, 4, 256, 4, 4769, 0 },
+  { 617, 4, 256, 4, 4769, 0 },
+  { 760, 4, 256, 4, 4769, 0 },
+  { 903, 4, 256, 4, 4769, 0 },
+  { 1046, 4, 256, 4, 4769, 0 },
+  { 1189, 4, 256, 4, 4769, 0 },
+  { 1332, 4, 256, 4, 4769, 0 },
+  { 1475, 4, 294, 4, 4673, 0 },
+  { 142, 4, 294, 4, 4673, 0 },
+  { 188, 621, 4, 5, 4737, 26 },
+  { 375, 621, 4, 5, 4737, 26 },
+  { 518, 621, 4, 5, 4737, 26 },
+  { 661, 621, 4, 5, 4737, 26 },
+  { 804, 621, 4, 5, 4737, 26 },
+  { 947, 621, 4, 5, 4737, 26 },
+  { 1090, 621, 4, 5, 4737, 26 },
+  { 1233, 621, 4, 5, 4737, 26 },
+  { 1376, 621, 4, 5, 4737, 26 },
+  { 1515, 621, 4, 5, 4737, 26 },
+  { 42, 621, 4, 5, 4737, 26 },
+  { 235, 621, 4, 5, 4737, 26 },
+  { 424, 621, 4, 5, 4737, 26 },
+  { 569, 621, 4, 5, 4737, 26 },
+  { 712, 621, 4, 5, 4737, 26 },
+  { 855, 621, 4, 5, 4737, 26 },
+  { 998, 621, 4, 5, 4737, 26 },
+  { 1141, 621, 4, 5, 4737, 26 },
+  { 1284, 621, 4, 5, 4737, 26 },
+  { 1427, 621, 4, 5, 4737, 26 },
+  { 94, 621, 4, 5, 4737, 26 },
+  { 287, 621, 4, 5, 4737, 26 },
+  { 476, 621, 4, 5, 4737, 26 },
+  { 621, 621, 4, 5, 4737, 26 },
+  { 764, 621, 4, 5, 4737, 26 },
+  { 907, 621, 4, 5, 4737, 26 },
+  { 1050, 621, 4, 5, 4737, 26 },
+  { 1193, 621, 4, 5, 4737, 26 },
+  { 1336, 621, 4, 5, 4737, 26 },
+  { 346, 430, 179, 7, 1041, 30 },
+  { 490, 430, 243, 7, 1041, 30 },
+  { 634, 430, 134, 7, 1041, 30 },
+  { 777, 430, 134, 7, 1041, 30 },
+  { 920, 430, 134, 7, 1041, 30 },
+  { 1063, 430, 134, 7, 1041, 30 },
+  { 1206, 430, 134, 7, 1041, 30 },
+  { 1349, 430, 134, 7, 1041, 30 },
+  { 1488, 430, 134, 7, 1041, 30 },
+  { 10, 430, 134, 7, 1041, 30 },
+  { 201, 430, 134, 7, 1041, 30 },
+  { 389, 430, 134, 7, 1041, 30 },
+  { 533, 430, 134, 7, 1041, 30 },
+  { 676, 430, 134, 7, 1041, 30 },
+  { 819, 430, 134, 7, 1041, 30 },
+  { 962, 430, 134, 7, 1041, 30 },
+  { 1105, 430, 134, 7, 1041, 30 },
+  { 1248, 430, 134, 7, 1041, 30 },
+  { 1391, 430, 134, 7, 1041, 30 },
+  { 58, 430, 134, 7, 1041, 30 },
+  { 251, 430, 134, 7, 1041, 30 },
+  { 440, 430, 134, 7, 1041, 30 },
+  { 585, 430, 134, 7, 1041, 30 },
+  { 728, 430, 134, 7, 1041, 30 },
+  { 871, 430, 134, 7, 1041, 30 },
+  { 1014, 430, 134, 7, 1041, 30 },
+  { 1157, 430, 134, 7, 1041, 30 },
+  { 1300, 430, 134, 7, 1041, 30 },
+  { 1443, 430, 134, 7, 1041, 30 },
+  { 110, 430, 134, 7, 1041, 30 },
+  { 303, 430, 134, 7, 1041, 30 },
+  { 157, 421, 134, 7, 4080, 2 },
+  { 628, 562, 264, 31, 81, 37 },
+  { 771, 562, 264, 31, 81, 37 },
+  { 914, 562, 264, 31, 81, 37 },
+  { 1057, 562, 264, 31, 81, 37 },
+  { 1200, 562, 264, 31, 81, 37 },
+  { 1343, 562, 264, 31, 81, 37 },
+  { 1482, 562, 264, 31, 81, 37 },
+  { 4, 562, 264, 31, 81, 37 },
+  { 195, 562, 264, 31, 81, 37 },
+  { 382, 562, 264, 31, 81, 37 },
+  { 525, 562, 264, 31, 81, 37 },
+  { 668, 562, 264, 31, 81, 37 },
+  { 811, 562, 264, 31, 81, 37 },
+  { 954, 562, 264, 31, 81, 37 },
+  { 1097, 562, 264, 31, 81, 37 },
+  { 1240, 562, 264, 31, 81, 37 },
+  { 1383, 562, 264, 31, 81, 37 },
+  { 50, 562, 264, 31, 81, 37 },
+  { 243, 562, 264, 31, 81, 37 },
+  { 432, 562, 264, 31, 81, 37 },
+  { 577, 562, 264, 31, 81, 37 },
+  { 720, 562, 264, 31, 81, 37 },
+  { 863, 562, 264, 31, 81, 37 },
+  { 1006, 562, 264, 31, 81, 37 },
+  { 1149, 562, 264, 31, 81, 37 },
+  { 1292, 562, 264, 31, 81, 37 },
+  { 1435, 562, 264, 31, 81, 37 },
+  { 102, 562, 264, 31, 81, 37 },
+  { 295, 562, 264, 31, 81, 37 },
+  { 149, 584, 264, 31, 160, 42 },
+  { 338, 397, 264, 31, 368, 28 },
+  { 483, 540, 264, 31, 3216, 5 },
+  { 487, 32, 258, 16, 305, 43 },
+  { 631, 32, 191, 16, 305, 43 },
+  { 774, 32, 191, 16, 305, 43 },
+  { 917, 32, 191, 16, 305, 43 },
+  { 1060, 32, 191, 16, 305, 43 },
+  { 1203, 32, 191, 16, 305, 43 },
+  { 1346, 32, 191, 16, 305, 43 },
+  { 1485, 32, 191, 16, 305, 43 },
+  { 7, 32, 191, 16, 305, 43 },
+  { 198, 32, 191, 16, 305, 43 },
+  { 385, 32, 191, 16, 305, 43 },
+  { 529, 32, 191, 16, 305, 43 },
+  { 672, 32, 191, 16, 305, 43 },
+  { 815, 32, 191, 16, 305, 43 },
+  { 958, 32, 191, 16, 305, 43 },
+  { 1101, 32, 191, 16, 305, 43 },
+  { 1244, 32, 191, 16, 305, 43 },
+  { 1387, 32, 191, 16, 305, 43 },
+  { 54, 32, 191, 16, 305, 43 },
+  { 247, 32, 191, 16, 305, 43 },
+  { 436, 32, 191, 16, 305, 43 },
+  { 581, 32, 191, 16, 305, 43 },
+  { 724, 32, 191, 16, 305, 43 },
+  { 867, 32, 191, 16, 305, 43 },
+  { 1010, 32, 191, 16, 305, 43 },
+  { 1153, 32, 191, 16, 305, 43 },
+  { 1296, 32, 191, 16, 305, 43 },
+  { 1439, 32, 191, 16, 305, 43 },
+  { 106, 32, 191, 16, 305, 43 },
+  { 299, 32, 191, 16, 305, 43 },
+  { 153, 47, 191, 16, 448, 33 },
+  { 342, 608, 191, 16, 3824, 10 },
+  { 363, 268, 185, 53, 993, 49 },
+  { 506, 268, 249, 53, 993, 49 },
+  { 649, 268, 140, 53, 993, 49 },
+  { 792, 268, 140, 53, 993, 49 },
+  { 935, 268, 140, 53, 993, 49 },
+  { 1078, 268, 140, 53, 993, 49 },
+  { 1221, 268, 140, 53, 993, 49 },
+  { 1364, 268, 140, 53, 993, 49 },
+  { 1503, 268, 140, 53, 993, 49 },
+  { 27, 268, 140, 53, 993, 49 },
+  { 219, 268, 140, 53, 993, 49 },
+  { 408, 268, 140, 53, 993, 49 },
+  { 553, 268, 140, 53, 993, 49 },
+  { 696, 268, 140, 53, 993, 49 },
+  { 839, 268, 140, 53, 993, 49 },
+  { 982, 268, 140, 53, 993, 49 },
+  { 1125, 268, 140, 53, 993, 49 },
+  { 1268, 268, 140, 53, 993, 49 },
+  { 1411, 268, 140, 53, 993, 49 },
+  { 78, 268, 140, 53, 993, 49 },
+  { 271, 268, 140, 53, 993, 49 },
+  { 460, 268, 140, 53, 993, 49 },
+  { 605, 268, 140, 53, 993, 49 },
+  { 748, 268, 140, 53, 993, 49 },
+  { 891, 268, 140, 53, 993, 49 },
+  { 1034, 268, 140, 53, 993, 49 },
+  { 1177, 268, 140, 53, 993, 49 },
+  { 1320, 268, 140, 53, 993, 49 },
+  { 1463, 268, 140, 53, 993, 49 },
+  { 130, 268, 140, 53, 993, 49 },
+  { 323, 268, 140, 53, 993, 49 },
+  { 175, 280, 140, 53, 4080, 14 },
+  { 643, 476, 4, 86, 1, 56 },
+  { 786, 476, 4, 86, 1, 56 },
+  { 929, 476, 4, 86, 1, 56 },
+  { 1072, 476, 4, 86, 1, 56 },
+  { 1215, 476, 4, 86, 1, 56 },
+  { 1358, 476, 4, 86, 1, 56 },
+  { 1497, 476, 4, 86, 1, 56 },
+  { 21, 476, 4, 86, 1, 56 },
+  { 213, 476, 4, 86, 1, 56 },
+  { 401, 476, 4, 86, 1, 56 },
+  { 545, 476, 4, 86, 1, 56 },
+  { 688, 476, 4, 86, 1, 56 },
+  { 831, 476, 4, 86, 1, 56 },
+  { 974, 476, 4, 86, 1, 56 },
+  { 1117, 476, 4, 86, 1, 56 },
+  { 1260, 476, 4, 86, 1, 56 },
+  { 1403, 476, 4, 86, 1, 56 },
+  { 70, 476, 4, 86, 1, 56 },
+  { 263, 476, 4, 86, 1, 56 },
+  { 452, 476, 4, 86, 1, 56 },
+  { 597, 476, 4, 86, 1, 56 },
+  { 740, 476, 4, 86, 1, 56 },
+  { 883, 476, 4, 86, 1, 56 },
+  { 1026, 476, 4, 86, 1, 56 },
+  { 1169, 476, 4, 86, 1, 56 },
+  { 1312, 476, 4, 86, 1, 56 },
+  { 1455, 476, 4, 86, 1, 56 },
+  { 122, 476, 4, 86, 1, 56 },
+  { 315, 476, 4, 86, 1, 56 },
+  { 167, 508, 4, 86, 160, 61 },
+  { 355, 365, 4, 86, 368, 47 },
+  { 499, 444, 4, 86, 3216, 17 },
+  { 503, 302, 261, 65, 241, 62 },
+  { 646, 302, 88, 65, 241, 62 },
+  { 789, 302, 88, 65, 241, 62 },
+  { 932, 302, 88, 65, 241, 62 },
+  { 1075, 302, 88, 65, 241, 62 },
+  { 1218, 302, 88, 65, 241, 62 },
+  { 1361, 302, 88, 65, 241, 62 },
+  { 1500, 302, 88, 65, 241, 62 },
+  { 24, 302, 88, 65, 241, 62 },
+  { 216, 302, 88, 65, 241, 62 },
+  { 404, 302, 88, 65, 241, 62 },
+  { 549, 302, 88, 65, 241, 62 },
+  { 692, 302, 88, 65, 241, 62 },
+  { 835, 302, 88, 65, 241, 62 },
+  { 978, 302, 88, 65, 241, 62 },
+  { 1121, 302, 88, 65, 241, 62 },
+  { 1264, 302, 88, 65, 241, 62 },
+  { 1407, 302, 88, 65, 241, 62 },
+  { 74, 302, 88, 65, 241, 62 },
+  { 267, 302, 88, 65, 241, 62 },
+  { 456, 302, 88, 65, 241, 62 },
+  { 601, 302, 88, 65, 241, 62 },
+  { 744, 302, 88, 65, 241, 62 },
+  { 887, 302, 88, 65, 241, 62 },
+  { 1030, 302, 88, 65, 241, 62 },
+  { 1173, 302, 88, 65, 241, 62 },
+  { 1316, 302, 88, 65, 241, 62 },
+  { 1459, 302, 88, 65, 241, 62 },
+  { 126, 302, 88, 65, 241, 62 },
+  { 319, 302, 88, 65, 241, 62 },
+  { 171, 323, 88, 65, 448, 52 },
+  { 359, 344, 88, 65, 3824, 22 },
 };

  // FPR8 Register Class...
@ -1491,50 +1491,50 @@ static const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
  };

-static const MCRegisterClass AArch64MCRegisterClasses[] = {
-  { "FPR8", FPR8, FPR8Bits, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 },
-  { "FPR16", FPR16, FPR16Bits, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 },
-  { "GPR32all", GPR32all, GPR32allBits, 33, sizeof(GPR32allBits), AArch64_GPR32allRegClassID, 4, 4, 1, 1 },
-  { "FPR32", FPR32, FPR32Bits, 32, sizeof(FPR32Bits), AArch64_FPR32RegClassID, 4, 4, 1, 1 },
-  { "GPR32", GPR32, GPR32Bits, 32, sizeof(GPR32Bits), AArch64_GPR32RegClassID, 4, 4, 1, 1 },
-  { "GPR32sp", GPR32sp, GPR32spBits, 32, sizeof(GPR32spBits), AArch64_GPR32spRegClassID, 4, 4, 1, 1 },
-  { "GPR32common", GPR32common, GPR32commonBits, 31, sizeof(GPR32commonBits), AArch64_GPR32commonRegClassID, 4, 4, 1, 1 },
-  { "CCR", CCR, CCRBits, 1, sizeof(CCRBits), AArch64_CCRRegClassID, 4, 4, -1, 0 },
-  { "GPR32sponly", GPR32sponly, GPR32sponlyBits, 1, sizeof(GPR32sponlyBits), AArch64_GPR32sponlyRegClassID, 4, 4, 1, 1 },
-  { "GPR64all", GPR64all, GPR64allBits, 33, sizeof(GPR64allBits), AArch64_GPR64allRegClassID, 8, 8, 1, 1 },
-  { "FPR64", FPR64, FPR64Bits, 32, sizeof(FPR64Bits), AArch64_FPR64RegClassID, 8, 8, 1, 1 },
-  { "GPR64", GPR64, GPR64Bits, 32, sizeof(GPR64Bits), AArch64_GPR64RegClassID, 8, 8, 1, 1 },
-  { "GPR64sp", GPR64sp, GPR64spBits, 32, sizeof(GPR64spBits), AArch64_GPR64spRegClassID, 8, 8, 1, 1 },
-  { "GPR64common", GPR64common, GPR64commonBits, 31, sizeof(GPR64commonBits), AArch64_GPR64commonRegClassID, 8, 8, 1, 1 },
-  { "tcGPR64", tcGPR64, tcGPR64Bits, 19, sizeof(tcGPR64Bits), AArch64_tcGPR64RegClassID, 8, 8, 1, 1 },
-  { "GPR64sponly", GPR64sponly, GPR64sponlyBits, 1, sizeof(GPR64sponlyBits), AArch64_GPR64sponlyRegClassID, 8, 8, 1, 1 },
-  { "DD", DD, DDBits, 32, sizeof(DDBits), AArch64_DDRegClassID, 16, 8, 1, 1 },
-  { "FPR128", FPR128, FPR128Bits, 32, sizeof(FPR128Bits), AArch64_FPR128RegClassID, 16, 16, 1, 1 },
-  { "FPR128_lo", FPR128_lo, FPR128_loBits, 16, sizeof(FPR128_loBits), AArch64_FPR128_loRegClassID, 16, 16, 1, 1 },
-  { "DDD", DDD, DDDBits, 32, sizeof(DDDBits), AArch64_DDDRegClassID, 24, 8, 1, 1 },
-  { "DDDD", DDDD, DDDDBits, 32, sizeof(DDDDBits), AArch64_DDDDRegClassID, 32, 8, 1, 1 },
-  { "QQ", QQ, QQBits, 32, sizeof(QQBits), AArch64_QQRegClassID, 32, 16, 1, 1 },
-  { "QQ_with_qsub0_in_FPR128_lo", QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_loRegClassID, 32, 16, 1, 1 },
-  { "QQ_with_qsub1_in_FPR128_lo", QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
-  { "QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo", QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
-  { "QQQ", QQQ, QQQBits, 32, sizeof(QQQBits), AArch64_QQQRegClassID, 48, 16, 1, 1 },
-  { "QQQ_with_qsub0_in_FPR128_lo", QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 16, 1, 1 },
-  { "QQQ_with_qsub1_in_FPR128_lo", QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
-  { "QQQ_with_qsub2_in_FPR128_lo", QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
-  { "QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo", QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
-  { "QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo", QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
-  { "QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo", QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
-  { "QQQQ", QQQQ, QQQQBits, 32, sizeof(QQQQBits), AArch64_QQQQRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub0_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub1_in_FPR128_lo", QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub2_in_FPR128_lo", QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo", QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
-  { "QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo", QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+static MCRegisterClass AArch64MCRegisterClasses[] = {
+  { FPR8, FPR8Bits, 39, 32, sizeof(FPR8Bits), AArch64_FPR8RegClassID, 1, 1, 1, 1 },
+  { FPR16, FPR16Bits, 26, 32, sizeof(FPR16Bits), AArch64_FPR16RegClassID, 2, 2, 1, 1 },
+  { GPR32all, GPR32allBits, 58, 33, sizeof(GPR32allBits), AArch64_GPR32allRegClassID, 4, 4, 1, 1 },
+  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64_FPR32RegClassID, 4, 4, 1, 1 },
+  { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64_GPR32RegClassID, 4, 4, 1, 1 },
+  { GPR32sp, GPR32spBits, 739, 32, sizeof(GPR32spBits), AArch64_GPR32spRegClassID, 4, 4, 1, 1 },
+  { GPR32common, GPR32commonBits, 76, 31, sizeof(GPR32commonBits), AArch64_GPR32commonRegClassID, 4, 4, 1, 1 },
+  { CCR, CCRBits, 54, 1, sizeof(CCRBits), AArch64_CCRRegClassID, 4, 4, -1, 0 },
+  { GPR32sponly, GPR32sponlyBits, 755, 1, sizeof(GPR32sponlyBits), AArch64_GPR32sponlyRegClassID, 4, 4, 1, 1 },
+  { GPR64all, GPR64allBits, 67, 33, sizeof(GPR64allBits), AArch64_GPR64allRegClassID, 8, 8, 1, 1 },
+  { FPR64, FPR64Bits, 12, 32, sizeof(FPR64Bits), AArch64_FPR64RegClassID, 8, 8, 1, 1 },
+  { GPR64, GPR64Bits, 20, 32, sizeof(GPR64Bits), AArch64_GPR64RegClassID, 8, 8, 1, 1 },
+  { GPR64sp, GPR64spBits, 747, 32, sizeof(GPR64spBits), AArch64_GPR64spRegClassID, 8, 8, 1, 1 },
+  { GPR64common, GPR64commonBits, 88, 31, sizeof(GPR64commonBits), AArch64_GPR64commonRegClassID, 8, 8, 1, 1 },
+  { tcGPR64, tcGPR64Bits, 18, 19, sizeof(tcGPR64Bits), AArch64_tcGPR64RegClassID, 8, 8, 1, 1 },
+  { GPR64sponly, GPR64sponlyBits, 767, 1, sizeof(GPR64sponlyBits), AArch64_GPR64sponlyRegClassID, 8, 8, 1, 1 },
+  { DD, DDBits, 46, 32, sizeof(DDBits), AArch64_DDRegClassID, 16, 8, 1, 1 },
+  { FPR128, FPR128Bits, 32, 32, sizeof(FPR128Bits), AArch64_FPR128RegClassID, 16, 16, 1, 1 },
+  { FPR128_lo, FPR128_loBits, 119, 16, sizeof(FPR128_loBits), AArch64_FPR128_loRegClassID, 16, 16, 1, 1 },
+  { DDD, DDDBits, 45, 32, sizeof(DDDBits), AArch64_DDDRegClassID, 24, 8, 1, 1 },
+  { DDDD, DDDDBits, 44, 32, sizeof(DDDDBits), AArch64_DDDDRegClassID, 32, 8, 1, 1 },
+  { QQ, QQBits, 51, 32, sizeof(QQBits), AArch64_QQRegClassID, 32, 16, 1, 1 },
+  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 102, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_loRegClassID, 32, 16, 1, 1 },
+  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 164, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
+  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 251, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
+  { QQQ, QQQBits, 50, 32, sizeof(QQQBits), AArch64_QQQRegClassID, 48, 16, 1, 1 },
+  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 101, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 16, 1, 1 },
+  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 163, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
+  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 343, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
+  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 191, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
+  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 493, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
+  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 433, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
+  { QQQQ, QQQQBits, 49, 32, sizeof(QQQQBits), AArch64_QQQQRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 100, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 162, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 342, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 586, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 129, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 371, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 677, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 309, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 615, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
+  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 553, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
 };

 #endif // GET_REGINFO_MC_DESC
--- a/arch/AArch64/AArch64GenSubtargetInfo.inc
+++ b/arch/AArch64/AArch64GenSubtargetInfo.inc
@ -7,7 +7,7 @@
 \*===----------------------------------------------------------------------===*/

 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */


 #ifdef GET_SUBTARGETINFO_ENUM
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@ -12,11 +12,11 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */

 #ifdef CAPSTONE_HAS_ARM64

-#include <platform.h>
+#include <capstone/platform.h>
 #include <stdio.h>
 #include <stdlib.h>

@ -45,14 +45,34 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
 static void printShifter(MCInst *MI, unsigned OpNum, SStream *O);

+static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index)
+{
+#ifndef CAPSTONE_DIET
+	uint8_t *arr = AArch64_get_op_access(h, id);
+
+	if (arr[index] == CS_AC_IGNORE)
+		return 0;
+
+	return arr[index];
+#else
+	return 0;
+#endif
+}
+
 static void set_mem_access(MCInst *MI, bool status)
 {
+	MI->csh->doing_mem = status;
+
 	if (MI->csh->detail != CS_OPT_ON)
 		return;

-	MI->csh->doing_mem = status;
-
 	if (status) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_MEM;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base = ARM64_REG_INVALID;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = ARM64_REG_INVALID;
@ -116,9 +136,20 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 						getRegisterName(getWRegFromXReg(MCOperand_getReg(Op1)), AArch64_NoRegAltName));

 				if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+					uint8_t access;
+					access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+					MI->ac_idx++;
+#endif
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
 					MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+					access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+					MI->ac_idx++;
+#endif
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = getWRegFromXReg(MCOperand_getReg(Op1));
 					MI->flat_insn->detail->arm64.op_count++;
@ -170,12 +201,28 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 				MCInst_setOpcodePub(MI, AArch64_map_insn(AsmMnemonic));

 				if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+					uint8_t access;
+					access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+					MI->ac_idx++;
+#endif
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
 					MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+					access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+					MI->ac_idx++;
+#endif
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
 					MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+					access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+					MI->ac_idx++;
+#endif
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = shift;
 					MI->flat_insn->detail->arm64.op_count++;
@ -197,15 +244,36 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 			MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz"));

 			if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
 				MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
 				MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (Is64Bit ? 64 : 32) - (int)MCOperand_getImm(Op2);
 				MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) + 1;
 				MI->flat_insn->detail->arm64.op_count++;
@ -225,15 +293,36 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 		MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfx" : "ubfx"));

 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
 			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op1);
 			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op2);
 			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op3) - MCOperand_getImm(Op2) + 1;
 			MI->flat_insn->detail->arm64.op_count++;
@ -263,15 +352,36 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 			MCInst_setOpcodePub(MI, AArch64_map_insn("bfi"));

 			if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
 				MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
 				MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
 				MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
 				MI->flat_insn->detail->arm64.op_count++;
@ -292,15 +402,36 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
 		MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil"));

 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0);
 			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op2);
 			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB;
 			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width;
 			MI->flat_insn->detail->arm64.op_count++;
@ -565,6 +696,12 @@ static bool printSysAlias(MCInst *MI, SStream *O)
 		MCInst_setOpcodePub(MI, insn_id);
 		SStream_concat0(O, Asm);
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = op_ic + op_dc + op_at + op_tlbi;
 			MI->flat_insn->detail->arm64.op_count++;
@ -574,6 +711,12 @@ static bool printSysAlias(MCInst *MI, SStream *O)
 			unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 4));
 			SStream_concat(O, ", %s", getRegisterName(Reg, AArch64_NoRegAltName));
 			if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
 				MI->flat_insn->detail->arm64.op_count++;
@ -600,6 +743,12 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
 					MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.index = Reg;
 				}
 			} else {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
 				MI->flat_insn->detail->arm64.op_count++;
@ -611,12 +760,23 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
 		if (MI->Opcode == AArch64_ADR) {
 			imm += MI->address;
 			printUInt64Bang(O, imm);
-		} else
-			printUInt64Bang(O, imm);
+		} else {
+			if (MI->csh->doing_mem)
+				printInt64Bang(O, imm);
+			else
+				printUInt64Bang(O, imm);
+		}
+
 		if (MI->csh->detail) {
 			if (MI->csh->doing_mem) {
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
 			} else {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
 				MI->flat_insn->detail->arm64.op_count++;
@ -630,6 +790,12 @@ static void printHexImm(MCInst *MI, unsigned OpNo, SStream *O)
 	MCOperand *Op = MCInst_getOperand(MI, OpNo);
 	SStream_concat(O, "#%#llx", MCOperand_getImm(Op));
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
 		MI->flat_insn->detail->arm64.op_count++;
@ -646,6 +812,12 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNo,
 		if (Reg == AArch64_XZR) {
 			printInt32Bang(O, Imm);
 			if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Imm;
 				MI->flat_insn->detail->arm64.op_count++;
@ -653,6 +825,12 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNo,
 		} else {
 			SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
 			if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
 				MI->flat_insn->detail->arm64.op_count++;
@ -674,6 +852,12 @@ static void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O)
 	unsigned Reg = MCOperand_getReg(Op);
 	SStream_concat0(O, getRegisterName(Reg, AArch64_vreg));
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
 		MI->flat_insn->detail->arm64.op_count++;
@ -686,6 +870,12 @@ static void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O)
 	//assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
 	SStream_concat(O, "c%u", MCOperand_getImm(Op));
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_CIMM;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = MCOperand_getImm(Op);
 		MI->flat_insn->detail->arm64.op_count++;
@ -703,6 +893,12 @@ static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O)
 		printInt32Bang(O, Val);

 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
 			MI->flat_insn->detail->arm64.op_count++;
@ -721,6 +917,12 @@ static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O)
 	printUInt32Bang(O, (int)Val);

 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
 		MI->flat_insn->detail->arm64.op_count++;
@ -749,8 +951,14 @@ static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O)
 	}

 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
-		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int64_t)Val;
 		MI->flat_insn->detail->arm64.op_count++;
 	}
 }
@ -796,6 +1004,12 @@ static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O)
 {
 	SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName));
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
 		MI->flat_insn->detail->arm64.op_count++;
@ -882,6 +1096,12 @@ static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O)

 	SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName));
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg;
 		MI->flat_insn->detail->arm64.op_count++;
@ -976,6 +1196,12 @@ static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
 		if (MI->csh->doing_mem) {
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
 		} else {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
 			MI->flat_insn->detail->arm64.op_count++;
@ -994,9 +1220,15 @@ static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStrea
 			if (MI->csh->doing_mem) {
 				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
 			} else {
-			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
-			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
-			MI->flat_insn->detail->arm64.op_count++;
+#ifndef CAPSTONE_DIET
+				uint8_t access;
+				access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+				MI->ac_idx++;
+#endif
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
+				MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)val;
+				MI->flat_insn->detail->arm64.op_count++;
 			}
 		}
 	}
@ -1024,6 +1256,12 @@ static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O)
 	} else {
 		printInt32Bang(O, prfop);
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop;
 			MI->flat_insn->detail->arm64.op_count++;
@ -1044,6 +1282,12 @@ static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O)
 	SStream_concat(O, "#%.8f", FPImm);
 #endif
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_FP;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].fp = FPImm;
 		MI->flat_insn->detail->arm64.op_count++;
@ -1135,6 +1379,12 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *Layout
 		if (i + 1 != NumRegs)
 			SStream_concat0(O, ", ");
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg);
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas;
@ -1251,6 +1501,12 @@ static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
 		uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address;
 		printUInt64Bang(O, imm);
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
 			MI->flat_insn->detail->arm64.op_count++;
@ -1270,6 +1526,12 @@ static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O)
 		printUInt64Bang(O, imm);

 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
 			MI->flat_insn->detail->arm64.op_count++;
@ -1293,6 +1555,12 @@ static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
 	if (Valid) {
 		SStream_concat0(O, Name);
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_BARRIER;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].barrier = Val;
 			MI->flat_insn->detail->arm64.op_count++;
@ -1300,6 +1568,12 @@ static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
 	} else {
 		printUInt32Bang(O, Val);
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
 			MI->flat_insn->detail->arm64.op_count++;
@ -1310,36 +1584,42 @@ static void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
 static void printMRSSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
 {
 	unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
-	bool Valid;
 	char Name[128];

-	A64SysRegMapper_toString(&AArch64_MRSMapper, Val, &Valid, Name);
+	A64SysRegMapper_toString(&AArch64_MRSMapper, Val, Name);

-	if (Valid) {
-		SStream_concat0(O, Name);
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
-			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
-			MI->flat_insn->detail->arm64.op_count++;
-		}
+	SStream_concat0(O, Name);
+	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS;
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
+		MI->flat_insn->detail->arm64.op_count++;
 	}
 }

 static void printMSRSystemRegister(MCInst *MI, unsigned OpNo, SStream *O)
 {
 	unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
-	bool Valid;
 	char Name[128];

-	A64SysRegMapper_toString(&AArch64_MSRMapper, Val, &Valid, Name);
+	A64SysRegMapper_toString(&AArch64_MSRMapper, Val, Name);

-	if (Valid) {
-		SStream_concat0(O, Name);
-		if (MI->csh->detail) {
-			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MSR;
-			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
-			MI->flat_insn->detail->arm64.op_count++;
-		}
+	SStream_concat0(O, Name);
+	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		uint8_t access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MSR;
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val;
+		MI->flat_insn->detail->arm64.op_count++;
 	}
 }

@ -1353,12 +1633,26 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNo, SStream *O)
 	if (Valid) {
 		SStream_concat0(O, Name);
 		if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+			uint8_t access;
+			access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+			MI->ac_idx++;
+#endif
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PSTATE;
 			MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].pstate = Val;
 			MI->flat_insn->detail->arm64.op_count++;
 		}
 	} else {
+#ifndef CAPSTONE_DIET
+		unsigned char access;
+#endif
 		printInt32Bang(O, Val);
+#ifndef CAPSTONE_DIET
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
 		MI->flat_insn->detail->arm64.op_count++;
@ -1371,6 +1665,12 @@ static void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O)
 	uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal);
 	SStream_concat(O, "#%#016llx", Val);
 	if (MI->csh->detail) {
+#ifndef CAPSTONE_DIET
+		unsigned char access;
+		access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx);
+		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access;
+		MI->ac_idx++;
+#endif
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
 		MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val;
 		MI->flat_insn->detail->arm64.op_count++;
@ -1386,9 +1686,253 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst
 	if (((cs_struct *)handle)->detail != CS_OPT_ON)
 		return;

-	// check if this insn requests write-back
-	if (strrchr(insn_asm, '!') != NULL)
-		flat_insn->detail->arm64.writeback = true;
+	if (mci->csh->detail) {
+		unsigned opcode = MCInst_getOpcode(mci);
+		switch (opcode) {
+			default:
+				break;
+			case AArch64_LD1Fourv16b_POST:
+			case AArch64_LD1Fourv1d_POST:
+			case AArch64_LD1Fourv2d_POST:
+			case AArch64_LD1Fourv2s_POST:
+			case AArch64_LD1Fourv4h_POST:
+			case AArch64_LD1Fourv4s_POST:
+			case AArch64_LD1Fourv8b_POST:
+			case AArch64_LD1Fourv8h_POST:
+			case AArch64_LD1Onev16b_POST:
+			case AArch64_LD1Onev1d_POST:
+			case AArch64_LD1Onev2d_POST:
+			case AArch64_LD1Onev2s_POST:
+			case AArch64_LD1Onev4h_POST:
+			case AArch64_LD1Onev4s_POST:
+			case AArch64_LD1Onev8b_POST:
+			case AArch64_LD1Onev8h_POST:
+			case AArch64_LD1Rv16b_POST:
+			case AArch64_LD1Rv1d_POST:
+			case AArch64_LD1Rv2d_POST:
+			case AArch64_LD1Rv2s_POST:
+			case AArch64_LD1Rv4h_POST:
+			case AArch64_LD1Rv4s_POST:
+			case AArch64_LD1Rv8b_POST:
+			case AArch64_LD1Rv8h_POST:
+			case AArch64_LD1Threev16b_POST:
+			case AArch64_LD1Threev1d_POST:
+			case AArch64_LD1Threev2d_POST:
+			case AArch64_LD1Threev2s_POST:
+			case AArch64_LD1Threev4h_POST:
+			case AArch64_LD1Threev4s_POST:
+			case AArch64_LD1Threev8b_POST:
+			case AArch64_LD1Threev8h_POST:
+			case AArch64_LD1Twov16b_POST:
+			case AArch64_LD1Twov1d_POST:
+			case AArch64_LD1Twov2d_POST:
+			case AArch64_LD1Twov2s_POST:
+			case AArch64_LD1Twov4h_POST:
+			case AArch64_LD1Twov4s_POST:
+			case AArch64_LD1Twov8b_POST:
+			case AArch64_LD1Twov8h_POST:
+			case AArch64_LD1i16_POST:
+			case AArch64_LD1i32_POST:
+			case AArch64_LD1i64_POST:
+			case AArch64_LD1i8_POST:
+			case AArch64_LD2Rv16b_POST:
+			case AArch64_LD2Rv1d_POST:
+			case AArch64_LD2Rv2d_POST:
+			case AArch64_LD2Rv2s_POST:
+			case AArch64_LD2Rv4h_POST:
+			case AArch64_LD2Rv4s_POST:
+			case AArch64_LD2Rv8b_POST:
+			case AArch64_LD2Rv8h_POST:
+			case AArch64_LD2Twov16b_POST:
+			case AArch64_LD2Twov2d_POST:
+			case AArch64_LD2Twov2s_POST:
+			case AArch64_LD2Twov4h_POST:
+			case AArch64_LD2Twov4s_POST:
+			case AArch64_LD2Twov8b_POST:
+			case AArch64_LD2Twov8h_POST:
+			case AArch64_LD2i16_POST:
+			case AArch64_LD2i32_POST:
+			case AArch64_LD2i64_POST:
+			case AArch64_LD2i8_POST:
+			case AArch64_LD3Rv16b_POST:
+			case AArch64_LD3Rv1d_POST:
+			case AArch64_LD3Rv2d_POST:
+			case AArch64_LD3Rv2s_POST:
+			case AArch64_LD3Rv4h_POST:
+			case AArch64_LD3Rv4s_POST:
+			case AArch64_LD3Rv8b_POST:
+			case AArch64_LD3Rv8h_POST:
+			case AArch64_LD3Threev16b_POST:
+			case AArch64_LD3Threev2d_POST:
+			case AArch64_LD3Threev2s_POST:
+			case AArch64_LD3Threev4h_POST:
+			case AArch64_LD3Threev4s_POST:
+			case AArch64_LD3Threev8b_POST:
+			case AArch64_LD3Threev8h_POST:
+			case AArch64_LD3i16_POST:
+			case AArch64_LD3i32_POST:
+			case AArch64_LD3i64_POST:
+			case AArch64_LD3i8_POST:
+			case AArch64_LD4Fourv16b_POST:
+			case AArch64_LD4Fourv2d_POST:
+			case AArch64_LD4Fourv2s_POST:
+			case AArch64_LD4Fourv4h_POST:
+			case AArch64_LD4Fourv4s_POST:
+			case AArch64_LD4Fourv8b_POST:
+			case AArch64_LD4Fourv8h_POST:
+			case AArch64_LD4Rv16b_POST:
+			case AArch64_LD4Rv1d_POST:
+			case AArch64_LD4Rv2d_POST:
+			case AArch64_LD4Rv2s_POST:
+			case AArch64_LD4Rv4h_POST:
+			case AArch64_LD4Rv4s_POST:
+			case AArch64_LD4Rv8b_POST:
+			case AArch64_LD4Rv8h_POST:
+			case AArch64_LD4i16_POST:
+			case AArch64_LD4i32_POST:
+			case AArch64_LD4i64_POST:
+			case AArch64_LD4i8_POST:
+			case AArch64_LDPDpost:
+			case AArch64_LDPDpre:
+			case AArch64_LDPQpost:
+			case AArch64_LDPQpre:
+			case AArch64_LDPSWpost:
+			case AArch64_LDPSWpre:
+			case AArch64_LDPSpost:
+			case AArch64_LDPSpre:
+			case AArch64_LDPWpost:
+			case AArch64_LDPWpre:
+			case AArch64_LDPXpost:
+			case AArch64_LDPXpre:
+			case AArch64_LDRBBpost:
+			case AArch64_LDRBBpre:
+			case AArch64_LDRBpost:
+			case AArch64_LDRBpre:
+			case AArch64_LDRDpost:
+			case AArch64_LDRDpre:
+			case AArch64_LDRHHpost:
+			case AArch64_LDRHHpre:
+			case AArch64_LDRHpost:
+			case AArch64_LDRHpre:
+			case AArch64_LDRQpost:
+			case AArch64_LDRQpre:
+			case AArch64_LDRSBWpost:
+			case AArch64_LDRSBWpre:
+			case AArch64_LDRSBXpost:
+			case AArch64_LDRSBXpre:
+			case AArch64_LDRSHWpost:
+			case AArch64_LDRSHWpre:
+			case AArch64_LDRSHXpost:
+			case AArch64_LDRSHXpre:
+			case AArch64_LDRSWpost:
+			case AArch64_LDRSWpre:
+			case AArch64_LDRSpost:
+			case AArch64_LDRSpre:
+			case AArch64_LDRWpost:
+			case AArch64_LDRWpre:
+			case AArch64_LDRXpost:
+			case AArch64_LDRXpre:
+			case AArch64_ST1Fourv16b_POST:
+			case AArch64_ST1Fourv1d_POST:
+			case AArch64_ST1Fourv2d_POST:
+			case AArch64_ST1Fourv2s_POST:
+			case AArch64_ST1Fourv4h_POST:
+			case AArch64_ST1Fourv4s_POST:
+			case AArch64_ST1Fourv8b_POST:
+			case AArch64_ST1Fourv8h_POST:
+			case AArch64_ST1Onev16b_POST:
+			case AArch64_ST1Onev1d_POST:
+			case AArch64_ST1Onev2d_POST:
+			case AArch64_ST1Onev2s_POST:
+			case AArch64_ST1Onev4h_POST:
+			case AArch64_ST1Onev4s_POST:
+			case AArch64_ST1Onev8b_POST:
+			case AArch64_ST1Onev8h_POST:
+			case AArch64_ST1Threev16b_POST:
+			case AArch64_ST1Threev1d_POST:
+			case AArch64_ST1Threev2d_POST:
+			case AArch64_ST1Threev2s_POST:
+			case AArch64_ST1Threev4h_POST:
+			case AArch64_ST1Threev4s_POST:
+			case AArch64_ST1Threev8b_POST:
+			case AArch64_ST1Threev8h_POST:
+			case AArch64_ST1Twov16b_POST:
+			case AArch64_ST1Twov1d_POST:
+			case AArch64_ST1Twov2d_POST:
+			case AArch64_ST1Twov2s_POST:
+			case AArch64_ST1Twov4h_POST:
+			case AArch64_ST1Twov4s_POST:
+			case AArch64_ST1Twov8b_POST:
+			case AArch64_ST1Twov8h_POST:
+			case AArch64_ST1i16_POST:
+			case AArch64_ST1i32_POST:
+			case AArch64_ST1i64_POST:
+			case AArch64_ST1i8_POST:
+			case AArch64_ST2Twov16b_POST:
+			case AArch64_ST2Twov2d_POST:
+			case AArch64_ST2Twov2s_POST:
+			case AArch64_ST2Twov4h_POST:
+			case AArch64_ST2Twov4s_POST:
+			case AArch64_ST2Twov8b_POST:
+			case AArch64_ST2Twov8h_POST:
+			case AArch64_ST2i16_POST:
+			case AArch64_ST2i32_POST:
+			case AArch64_ST2i64_POST:
+			case AArch64_ST2i8_POST:
+			case AArch64_ST3Threev16b_POST:
+			case AArch64_ST3Threev2d_POST:
+			case AArch64_ST3Threev2s_POST:
+			case AArch64_ST3Threev4h_POST:
+			case AArch64_ST3Threev4s_POST:
+			case AArch64_ST3Threev8b_POST:
+			case AArch64_ST3Threev8h_POST:
+			case AArch64_ST3i16_POST:
+			case AArch64_ST3i32_POST:
+			case AArch64_ST3i64_POST:
+			case AArch64_ST3i8_POST:
+			case AArch64_ST4Fourv16b_POST:
+			case AArch64_ST4Fourv2d_POST:
+			case AArch64_ST4Fourv2s_POST:
+			case AArch64_ST4Fourv4h_POST:
+			case AArch64_ST4Fourv4s_POST:
+			case AArch64_ST4Fourv8b_POST:
+			case AArch64_ST4Fourv8h_POST:
+			case AArch64_ST4i16_POST:
+			case AArch64_ST4i32_POST:
+			case AArch64_ST4i64_POST:
+			case AArch64_ST4i8_POST:
+			case AArch64_STPDpost:
+			case AArch64_STPDpre:
+			case AArch64_STPQpost:
+			case AArch64_STPQpre:
+			case AArch64_STPSpost:
+			case AArch64_STPSpre:
+			case AArch64_STPWpost:
+			case AArch64_STPWpre:
+			case AArch64_STPXpost:
+			case AArch64_STPXpre:
+			case AArch64_STRBBpost:
+			case AArch64_STRBBpre:
+			case AArch64_STRBpost:
+			case AArch64_STRBpre:
+			case AArch64_STRDpost:
+			case AArch64_STRDpre:
+			case AArch64_STRHHpost:
+			case AArch64_STRHHpre:
+			case AArch64_STRHpost:
+			case AArch64_STRHpre:
+			case AArch64_STRQpost:
+			case AArch64_STRQpre:
+			case AArch64_STRSpost:
+			case AArch64_STRSpre:
+			case AArch64_STRWpost:
+			case AArch64_STRWpre:
+			case AArch64_STRXpost:
+			case AArch64_STRXpre:
+				flat_insn->detail->arm64.writeback = true;
+				break;
+		}
+	}
 }

 #endif
--- a/arch/AArch64/AArch64InstPrinter.h
+++ b/arch/AArch64/AArch64InstPrinter.h
@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_AARCH64INSTPRINTER_H
 #define CS_LLVM_AARCH64INSTPRINTER_H
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
--- a/arch/AArch64/AArch64Mapping.h
+++ b/arch/AArch64/AArch64Mapping.h
@ -1,10 +1,10 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_ARM64_MAP_H
 #define CS_ARM64_MAP_H

-#include "../../include/capstone.h"
+#include "capstone/capstone.h"

 // return name of regiser in friendly string
 const char *AArch64_reg_name(csh handle, unsigned int reg);
@ -32,4 +32,10 @@ void arm64_op_addFP(MCInst *MI, float fp);

 void arm64_op_addImm(MCInst *MI, int64_t imm);

+uint8_t *AArch64_get_op_access(cs_struct *h, unsigned int id);
+
+void AArch64_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+
 #endif
--- a/arch/AArch64/AArch64MappingInsn.inc
+++ b/arch/AArch64/AArch64MappingInsn.inc
--- a/arch/AArch64/AArch64MappingInsnOp.inc
+++ b/arch/AArch64/AArch64MappingInsnOp.inc
--- a/arch/AArch64/AArch64Module.c
+++ b/arch/AArch64/AArch64Module.c
@ -25,6 +25,9 @@ cs_err AArch64_global_init(cs_struct *ud)
 	ud->insn_name = AArch64_insn_name;
 	ud->group_name = AArch64_group_name;
 	ud->post_printer = AArch64_post_printer;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = AArch64_reg_access;
+#endif

 	return CS_ERR_OK;
 }
--- a/arch/AArch64/ARMMappingInsnOp.inc
+++ b/arch/AArch64/ARMMappingInsnOp.inc
--- a/arch/ARM/ARMAddressingModes.h
+++ b/arch/ARM/ARMAddressingModes.h
@ -12,12 +12,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
 #define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H

-#include "../../include/platform.h"
+#include "capstone/platform.h"
 #include "../../MathExtras.h"

 /// ARM_AM - ARM Addressing Mode Stuff
--- a/arch/ARM/ARMBaseInfo.h
+++ b/arch/ARM/ARMBaseInfo.h
@ -15,12 +15,12 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_ARMBASEINFO_H
 #define CS_ARMBASEINFO_H

-#include "../../include/arm.h"
+#include "capstone/arm.h"

 // Defines symbolic names for ARM registers.  This defines a mapping from
 // register name to register number.
--- a/arch/ARM/ARMDisassembler.c
+++ b/arch/ARM/ARMDisassembler.c
@ -8,14 +8,14 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifdef CAPSTONE_HAS_ARM

 #include <stdio.h>
 #include <string.h>
 #include <stdlib.h>
-#include <platform.h>
+#include <capstone/platform.h>

 #include "ARMAddressingModes.h"
 #include "ARMBaseInfo.h"
@ -161,8 +161,6 @@ static DecodeStatus DecodePredicateOperand(MCInst *Inst, unsigned Val,
 		uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
 		uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val,
 		uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSPRRegListOperand(MCInst *Inst, unsigned Val,
@ -251,6 +249,8 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Insn,
 		uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Insn,
 		uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDoubleRegLoad(MCInst *Inst, unsigned Insn,
 		uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeDoubleRegStore(MCInst *Inst, unsigned Insn,
@ -443,11 +443,31 @@ void ARM_init(MCRegisterInfo *MRI)
 			0);
 }

+// Post-decoding checks
+static DecodeStatus checkDecodedInstruction(MCInst *MI,
+		uint32_t Insn,
+		DecodeStatus Result)
+{
+	switch (MCInst_getOpcode(MI)) {
+		case ARM_HVC: {
+			  // HVC is undefined if condition = 0xf otherwise upredictable
+			  // if condition != 0xe
+			  uint32_t Cond = (Insn >> 28) & 0xF;
+			  if (Cond == 0xF)
+				  return MCDisassembler_Fail;
+			  if (Cond != 0xE)
+				  return MCDisassembler_SoftFail;
+			  return Result;
+		  }
+		default:
+			   return Result;
+	}
+}
+
 static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
 		uint16_t *Size, uint64_t Address)
 {
 	uint32_t insn, i;
-	uint8_t bytes[4];
 	DecodeStatus result;

 	if (code_len < 4)
@ -455,28 +475,30 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
 		return MCDisassembler_Fail;

 	if (MI->flat_insn->detail) {
-		memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
-		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
+		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
 			MI->flat_insn->detail->arm.operands[i].vector_index = -1;
+			MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
+		}
 	}

-	memcpy(bytes, code, 4);
-
 	if (MODE_IS_BIG_ENDIAN(ud->mode))
-		insn = (bytes[3] << 0) |
-			(bytes[2] << 8) |
-			(bytes[1] <<  16) |
-			(((uint32_t) bytes[0]) << 24);
+		insn = (code[3] << 0) |
+			(code[2] << 8) |
+			(code[1] <<  16) |
+			((uint32_t) code[0] << 24);
 	else
-		insn = (((uint32_t) bytes[3]) << 24) |
-			(bytes[2] << 16) |
-			(bytes[1] <<  8) |
-			(bytes[0] <<  0);
+		insn = ((uint32_t) code[3] << 24) |
+			(code[2] << 16) |
+			(code[1] <<  8) |
+			(code[0] <<  0);

 	// Calling the auto-generated decoder function.
 	result = decodeInstruction_4(DecoderTableARM32, MI, insn, Address, NULL, ud->mode);
 	if (result != MCDisassembler_Fail) {
-		*Size = 4;
+		result = checkDecodedInstruction(MI, insn, result);
+		if (result != MCDisassembler_Fail)
+			*Size = 4;
 		return result;
 	}

@ -683,7 +705,6 @@ static void UpdateThumbVFPPredicate(cs_struct *ud, MCInst *MI)
 static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t *code, size_t code_len,
 		uint16_t *Size, uint64_t Address)
 {
-	uint8_t bytes[4];
 	uint16_t insn16;
 	DecodeStatus result;
 	bool InITBlock;
@ -697,17 +718,17 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
 		return MCDisassembler_Fail;

 	if (MI->flat_insn->detail) {
-		memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
-		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm)+sizeof(cs_arm));
+		for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++) {
 			MI->flat_insn->detail->arm.operands[i].vector_index = -1;
+			MI->flat_insn->detail->arm.operands[i].neon_lane = -1;
+		}
 	}

-	memcpy(bytes, code, 2);
-
 	if (MODE_IS_BIG_ENDIAN(ud->mode))
-		insn16 = (bytes[0] << 8) | bytes[1];
+		insn16 = (code[0] << 8) | code[1];
 	else
-		insn16 = (bytes[1] << 8) | bytes[0];
+		insn16 = (code[1] << 8) | code[0];

 	result = decodeInstruction_2(DecoderTableThumb16, MI, insn16, Address, NULL, ud->mode);
 	if (result != MCDisassembler_Fail) {
@ -755,18 +776,16 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
 		// not enough data
 		return MCDisassembler_Fail;

-	memcpy(bytes, code, 4);
-
 	if (MODE_IS_BIG_ENDIAN(ud->mode))
-		insn32 = (bytes[3] <<  0) |
-			(bytes[2] <<  8) |
-			(bytes[1] << 16) |
-			(((uint32_t) bytes[0]) << 24);
+		insn32 = (code[3] <<  0) |
+			(code[2] <<  8) |
+			(code[1] << 16) |
+			((uint32_t) code[0] << 24);
 	else
-		insn32 = (bytes[3] <<  8) |
-			(bytes[2] <<  0) |
-			(((uint32_t) bytes[1]) << 24) |
-			(bytes[0] << 16);
+		insn32 = (code[3] <<  8) |
+			(code[2] <<  0) |
+			((uint32_t) code[1] << 24) |
+			(code[0] << 16);

 	MCInst_clear(MI);
 	result = decodeInstruction_4(DecoderTableThumb32, MI, insn32, Address, NULL, ud->mode);
@ -1046,12 +1065,18 @@ static const uint16_t DPRDecoderTable[] = {
 static DecodeStatus DecodeDPRRegisterClass(MCInst *Inst, unsigned RegNo,
 		uint64_t Address, const void *Decoder)
 {
-	unsigned Register = 0;
+	unsigned Register;
+
+	//uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
+	//bool hasD16 = featureBits & ARM_FeatureD16;
+
+	//if (RegNo > 31 || (hasD16 && RegNo > 15))	// FIXME
 	if (RegNo > 31)
 		return MCDisassembler_Fail;

 	Register = DPRDecoderTable[RegNo];
 	MCOperand_CreateReg0(Inst, Register);
+
 	return MCDisassembler_Success;
 }

@ -1146,16 +1171,6 @@ static DecodeStatus DecodeCCOutOperand(MCInst *Inst, unsigned Val,
 	return MCDisassembler_Success;
 }

-static DecodeStatus DecodeSOImmOperand(MCInst *Inst, unsigned Val,
-		uint64_t Address, const void *Decoder)
-{
-	uint32_t imm = Val & 0xFF;
-	uint32_t rot = (Val & 0xF00) >> 7;
-	uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
-	MCOperand_CreateImm0(Inst, rot_imm);
-	return MCDisassembler_Success;
-}
-
 static DecodeStatus DecodeSORegImmOperand(MCInst *Inst, unsigned Val,
 		uint64_t Address, const void *Decoder)
 {
@ -3337,6 +3352,9 @@ static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
 	unsigned addrmode;
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
+	uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
+	bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
+	bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);

 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
@ -3373,11 +3391,10 @@ static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,
 			case ARM_t2LDRSHs:
 				return MCDisassembler_Fail;
 			case ARM_t2LDRHs:
-				// FIXME: this instruction is only available with MP extensions,
-				// this should be checked first but we don't have access to the
-				// feature bits here.
 				MCInst_setOpcode(Inst, ARM_t2PLDWs);
 				break;
+			case ARM_t2LDRSBs:
+				MCInst_setOpcode(Inst, ARM_t2PLIs);
 			default:
 				break;
 		}
@ -3385,8 +3402,14 @@ static DecodeStatus DecodeT2LoadShift(MCInst *Inst, unsigned Insn,

 	switch (MCInst_getOpcode(Inst)) {
 		case ARM_t2PLDs:
-		case ARM_t2PLDWs:
+			break;
 		case ARM_t2PLIs:
+			if (!hasV7Ops)
+				return MCDisassembler_Fail;
+			break;
+		case ARM_t2PLDWs:
+			if (!hasV7Ops || !hasMP)
+				return MCDisassembler_Fail;
 			break;
 		default:
 			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@ -3411,9 +3434,14 @@ static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned U = fieldFromInstruction_4(Insn, 9, 1);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 8);
+	unsigned add = fieldFromInstruction_4(Insn, 9, 1);
+
+	uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
+	bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
+	bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
+
 	imm |= (U << 8);
 	imm |= (Rn << 9);
-
 	if (Rn == 15) {
 		switch (MCInst_getOpcode(Inst)) {
 			case ARM_t2LDRi8:
@ -3447,6 +3475,13 @@ static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,
 		switch (MCInst_getOpcode(Inst)) {
 			case ARM_t2LDRSHi8:
 				return MCDisassembler_Fail;
+			case ARM_t2LDRHi8:
+				if (!add)
+					MCInst_setOpcode(Inst, ARM_t2PLDWi8);
+				break;
+			case ARM_t2LDRSBi8:
+				MCInst_setOpcode(Inst, ARM_t2PLIi8);
+				break;
 			default:
 				break;
 		}
@ -3454,8 +3489,14 @@ static DecodeStatus DecodeT2LoadImm8(MCInst *Inst, unsigned Insn,

 	switch (MCInst_getOpcode(Inst)) {
 		case ARM_t2PLDi8:
+			break;
 		case ARM_t2PLIi8:
+			if (!hasV7Ops)
+				return MCDisassembler_Fail;
+			break;
 		case ARM_t2PLDWi8:
+			if (!hasV7Ops || !hasMP)
+				return MCDisassembler_Fail;
 			break;
 		default:
 			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@ -3475,6 +3516,10 @@ static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
 	unsigned Rn = fieldFromInstruction_4(Insn, 16, 4);
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned imm = fieldFromInstruction_4(Insn, 0, 12);
+	uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
+	bool hasMP = ((featureBits & ARM_FeatureMP) != 0);
+	bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);
+
 	imm |= (Rn << 13);

 	if (Rn == 15) {
@ -3511,7 +3556,10 @@ static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,
 			case ARM_t2LDRSHi12:
 				return MCDisassembler_Fail;
 			case ARM_t2LDRHi12:
-				MCInst_setOpcode(Inst, ARM_t2PLDi12);
+				MCInst_setOpcode(Inst, ARM_t2PLDWi12);
+				break;
+			case ARM_t2LDRSBi12:
+				MCInst_setOpcode(Inst, ARM_t2PLIi12);
 				break;
 			default:
 				break;
@ -3520,8 +3568,14 @@ static DecodeStatus DecodeT2LoadImm12(MCInst *Inst, unsigned Insn,

 	switch (MCInst_getOpcode(Inst)) {
 		case ARM_t2PLDi12:
-		case ARM_t2PLDWi12:
+			break;
 		case ARM_t2PLIi12:
+			if (!hasV7Ops)
+				return MCDisassembler_Fail;
+			break;
+		case ARM_t2PLDWi12:
+			if (!hasV7Ops || !hasMP)
+				return MCDisassembler_Fail;
 			break;
 		default:
 			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@ -3581,6 +3635,8 @@ static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,
 	unsigned Rt = fieldFromInstruction_4(Insn, 12, 4);
 	unsigned U = fieldFromInstruction_4(Insn, 23, 1);
 	int imm = fieldFromInstruction_4(Insn, 0, 12);
+	uint64_t featureBits = ARM_getFeatureBits(Inst->csh->mode);
+	bool hasV7Ops = ((featureBits & ARM_HasV7Ops) != 0);

 	if (Rt == 15) {
 		switch (MCInst_getOpcode(Inst)) {
@ -3600,7 +3656,10 @@ static DecodeStatus DecodeT2LoadLabel(MCInst *Inst, unsigned Insn,

 	switch(MCInst_getOpcode(Inst)) {
 		case ARM_t2PLDpci:
+			break;
 		case ARM_t2PLIpci:
+			if (!hasV7Ops)
+				return MCDisassembler_Fail;
 			break;
 		default:
 			if (!Check(&S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@ -4053,6 +4112,7 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val,
 static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
 		uint64_t Address, const void *Decoder)
 {
+	DecodeStatus S = MCDisassembler_Success;
 	uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode);
 	if (FeatureBits & ARM_FeatureMClass) {
 		unsigned ValLow = Val & 0xff;
@ -4082,17 +4142,25 @@ static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
 				return MCDisassembler_Fail;
 		}

-		// The ARMv7-M architecture has an additional 2-bit mask value in the MSR
-		// instruction (bits {11,10}). The mask is used only with apsr, iapsr,
-		// eapsr and xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates
-		// if the NZCVQ bits should be moved by the instruction. Bit mask{0}
-		// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
-		// only if the processor includes the DSP extension.
-		if ((FeatureBits & ARM_HasV7Ops) && MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
-			unsigned Mask = (Val >> 10) & 3;
-			if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
-					(!(FeatureBits & ARM_FeatureDSPThumb2) && Mask == 1))
-				return MCDisassembler_Fail;
+		if (MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
+			unsigned Mask = fieldFromInstruction_4(Val, 10, 2);
+			if (!(FeatureBits & ARM_HasV7Ops)) {
+				// The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
+				// unpredictable.
+				if (Mask != 2)
+					S = MCDisassembler_SoftFail;
+			}
+			else {
+				// The ARMv7-M architecture stores an additional 2-bit mask value in
+				// MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
+				// xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
+				// the NZCVQ bits should be moved by the instruction. Bit mask{0}
+				// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
+				// only if the processor includes the DSP extension.
+				if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
+						(!(FeatureBits & ARM_FeatureDSPThumb2) && (Mask & 1)))
+					S = MCDisassembler_SoftFail;
+			}
 		}
 	} else {
 		// A/R class
@ -4100,6 +4168,30 @@ static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
 			return MCDisassembler_Fail;
 	}

+	MCOperand_CreateImm0(Inst, Val);
+	return S;
+}
+
+static DecodeStatus DecodeBankedReg(MCInst *Inst, unsigned Val,
+		uint64_t Address, const void *Decoder)
+{
+
+	unsigned R = fieldFromInstruction_4(Val, 5, 1);
+	unsigned SysM = fieldFromInstruction_4(Val, 0, 5);
+
+	// The table of encodings for these banked registers comes from B9.2.3 of the
+	// ARM ARM. There are patterns, but nothing regular enough to make this logic
+	// neater. So by fiat, these values are UNPREDICTABLE:
+	if (!R) {
+		if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
+				SysM == 0x1a || SysM == 0x1b)
+			return MCDisassembler_SoftFail;
+	} else {
+		if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
+				SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
+			return MCDisassembler_SoftFail;
+	}
+
 	MCOperand_CreateImm0(Inst, Val);
 	return MCDisassembler_Success;
 }
@ -4961,8 +5053,10 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst *Inst, uint32_t Val,
 	DecodeStatus S = MCDisassembler_Success;

 	// Shift of "asr #32" is not allowed in Thumb2 mode.
-	if (Val == 0x20) S = MCDisassembler_SoftFail;
+	if (Val == 0x20)
+		S = MCDisassembler_Fail;
 	MCOperand_CreateImm0(Inst, Val);
+
 	return S;
 }

--- a/arch/ARM/ARMDisassembler.h
+++ b/arch/ARM/ARMDisassembler.h
@ -1,10 +1,10 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_ARMDISASSEMBLER_H
 #define CS_ARMDISASSEMBLER_H

-#include "../../include/capstone.h"
+#include "capstone/capstone.h"
 #include "../../MCRegisterInfo.h"

 void ARM_init(MCRegisterInfo *MRI);
--- a/arch/ARM/ARMGenAsmWriter.inc
+++ b/arch/ARM/ARMGenAsmWriter.inc
--- a/arch/ARM/ARMGenDisassemblerTables.inc
+++ b/arch/ARM/ARMGenDisassemblerTables.inc
--- a/arch/ARM/ARMGenInstrInfo.inc
+++ b/arch/ARM/ARMGenInstrInfo.inc
--- a/arch/ARM/ARMGenRegisterInfo.inc
+++ b/arch/ARM/ARMGenRegisterInfo.inc
--- a/arch/ARM/ARMGenSubtargetInfo.inc
+++ b/arch/ARM/ARMGenSubtargetInfo.inc
@ -7,68 +7,66 @@
 \*===----------------------------------------------------------------------===*/

 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */


 #ifdef GET_SUBTARGETINFO_ENUM
 #undef GET_SUBTARGETINFO_ENUM

-#define ARM_FeatureAAPCS (1ULL << 0)
-#define ARM_FeatureAClass (1ULL << 1)
-#define ARM_FeatureAPCS (1ULL << 2)
-#define ARM_FeatureAvoidMOVsShOp (1ULL << 3)
-#define ARM_FeatureAvoidPartialCPSR (1ULL << 4)
-#define ARM_FeatureCRC (1ULL << 5)
-#define ARM_FeatureCrypto (1ULL << 6)
-#define ARM_FeatureD16 (1ULL << 7)
-#define ARM_FeatureDB (1ULL << 8)
-#define ARM_FeatureDSPThumb2 (1ULL << 9)
-#define ARM_FeatureFP16 (1ULL << 10)
-#define ARM_FeatureFPARMv8 (1ULL << 11)
-#define ARM_FeatureHWDiv (1ULL << 12)
-#define ARM_FeatureHWDivARM (1ULL << 13)
-#define ARM_FeatureHasRAS (1ULL << 14)
-#define ARM_FeatureHasSlowFPVMLx (1ULL << 15)
-#define ARM_FeatureMClass (1ULL << 16)
-#define ARM_FeatureMP (1ULL << 17)
-#define ARM_FeatureNEON (1ULL << 18)
-#define ARM_FeatureNEONForFP (1ULL << 19)
-#define ARM_FeatureNaClTrap (1ULL << 20)
-#define ARM_FeatureNoARM (1ULL << 21)
-#define ARM_FeaturePerfMon (1ULL << 22)
-#define ARM_FeaturePref32BitThumb (1ULL << 23)
-#define ARM_FeatureRClass (1ULL << 24)
-#define ARM_FeatureSlowFPBrcc (1ULL << 25)
-#define ARM_FeatureT2XtPk (1ULL << 26)
-#define ARM_FeatureThumb2 (1ULL << 27)
-#define ARM_FeatureTrustZone (1ULL << 28)
-#define ARM_FeatureVFP2 (1ULL << 29)
-#define ARM_FeatureVFP3 (1ULL << 30)
-#define ARM_FeatureVFP4 (1ULL << 31)
-#define ARM_FeatureVFPOnlySP (1ULL << 32)
-#define ARM_FeatureVMLxForwarding (1ULL << 33)
-#define ARM_FeatureVirtualization (1ULL << 34)
-#define ARM_FeatureZCZeroing (1ULL << 35)
-#define ARM_HasV4TOps (1ULL << 36)
-#define ARM_HasV5TEOps (1ULL << 37)
-#define ARM_HasV5TOps (1ULL << 38)
-#define ARM_HasV6MOps (1ULL << 39)
-#define ARM_HasV6Ops (1ULL << 40)
-#define ARM_HasV6T2Ops (1ULL << 41)
-#define ARM_HasV7Ops (1ULL << 42)
-#define ARM_HasV8Ops (1ULL << 43)
-#define ARM_ModeThumb (1ULL << 44)
-#define ARM_ProcA5 (1ULL << 45)
-#define ARM_ProcA7 (1ULL << 46)
-#define ARM_ProcA8 (1ULL << 47)
-#define ARM_ProcA9 (1ULL << 48)
-#define ARM_ProcA12 (1ULL << 49)
-#define ARM_ProcA15 (1ULL << 50)
-#define ARM_ProcA53 (1ULL << 51)
-#define ARM_ProcA57 (1ULL << 52)
-#define ARM_ProcKrait (1ULL << 53)
-#define ARM_ProcR5 (1ULL << 54)
-#define ARM_ProcSwift (1ULL << 55)
+#define ARM_FeatureAClass (1ULL << 0)
+#define ARM_FeatureAvoidMOVsShOp (1ULL << 1)
+#define ARM_FeatureAvoidPartialCPSR (1ULL << 2)
+#define ARM_FeatureCRC (1ULL << 3)
+#define ARM_FeatureCrypto (1ULL << 4)
+#define ARM_FeatureD16 (1ULL << 5)
+#define ARM_FeatureDB (1ULL << 6)
+#define ARM_FeatureDSPThumb2 (1ULL << 7)
+#define ARM_FeatureFP16 (1ULL << 8)
+#define ARM_FeatureFPARMv8 (1ULL << 9)
+#define ARM_FeatureHWDiv (1ULL << 10)
+#define ARM_FeatureHWDivARM (1ULL << 11)
+#define ARM_FeatureHasRAS (1ULL << 12)
+#define ARM_FeatureHasSlowFPVMLx (1ULL << 13)
+#define ARM_FeatureMClass (1ULL << 14)
+#define ARM_FeatureMP (1ULL << 15)
+#define ARM_FeatureNEON (1ULL << 16)
+#define ARM_FeatureNEONForFP (1ULL << 17)
+#define ARM_FeatureNaClTrap (1ULL << 18)
+#define ARM_FeatureNoARM (1ULL << 19)
+#define ARM_FeaturePerfMon (1ULL << 20)
+#define ARM_FeaturePref32BitThumb (1ULL << 21)
+#define ARM_FeatureRClass (1ULL << 22)
+#define ARM_FeatureSlowFPBrcc (1ULL << 23)
+#define ARM_FeatureT2XtPk (1ULL << 24)
+#define ARM_FeatureThumb2 (1ULL << 25)
+#define ARM_FeatureTrustZone (1ULL << 26)
+#define ARM_FeatureVFP2 (1ULL << 27)
+#define ARM_FeatureVFP3 (1ULL << 28)
+#define ARM_FeatureVFP4 (1ULL << 29)
+#define ARM_FeatureVFPOnlySP (1ULL << 30)
+#define ARM_FeatureVMLxForwarding (1ULL << 31)
+#define ARM_FeatureVirtualization (1ULL << 32)
+#define ARM_FeatureZCZeroing (1ULL << 33)
+#define ARM_HasV4TOps (1ULL << 34)
+#define ARM_HasV5TEOps (1ULL << 35)
+#define ARM_HasV5TOps (1ULL << 36)
+#define ARM_HasV6MOps (1ULL << 37)
+#define ARM_HasV6Ops (1ULL << 38)
+#define ARM_HasV6T2Ops (1ULL << 39)
+#define ARM_HasV7Ops (1ULL << 40)
+#define ARM_HasV8Ops (1ULL << 41)
+#define ARM_ModeThumb (1ULL << 42)
+#define ARM_ProcA5 (1ULL << 43)
+#define ARM_ProcA7 (1ULL << 44)
+#define ARM_ProcA8 (1ULL << 45)
+#define ARM_ProcA9 (1ULL << 46)
+#define ARM_ProcA12 (1ULL << 47)
+#define ARM_ProcA15 (1ULL << 48)
+#define ARM_ProcA17 (1ULL << 49)
+#define ARM_ProcA53 (1ULL << 50)
+#define ARM_ProcA57 (1ULL << 51)
+#define ARM_ProcKrait (1ULL << 52)
+#define ARM_ProcR5 (1ULL << 53)
+#define ARM_ProcSwift (1ULL << 54)

 #endif // GET_SUBTARGETINFO_ENUM
-
--- a/arch/ARM/ARMInstPrinter.c
+++ b/arch/ARM/ARMInstPrinter.c
--- a/arch/ARM/ARMInstPrinter.h
+++ b/arch/ARM/ARMInstPrinter.h
@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_ARMINSTPRINTER_H
 #define CS_ARMINSTPRINTER_H
--- a/arch/ARM/ARMMapping.c
+++ b/arch/ARM/ARMMapping.c
--- a/arch/ARM/ARMMapping.h
+++ b/arch/ARM/ARMMapping.h
@ -1,10 +1,10 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_ARM_MAP_H
 #define CS_ARM_MAP_H

-#include "../../include/capstone.h"
+#include "../../include/capstone/capstone.h"
 #include "../../utils.h"

 // return name of regiser in friendly string
@ -23,4 +23,10 @@ bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);

 bool ARM_blx_to_arm_mode(cs_struct *h, unsigned int insn_id);

+uint8_t *ARM_get_op_access(cs_struct *h, unsigned int id);
+
+void ARM_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+
 #endif
--- a/arch/ARM/ARMMappingInsn.inc
+++ b/arch/ARM/ARMMappingInsn.inc
--- a/arch/ARM/ARMMappingInsnOp.inc
+++ b/arch/ARM/ARMMappingInsnOp.inc
--- a/arch/ARM/ARMModule.c
+++ b/arch/ARM/ARMModule.c
@ -25,6 +25,9 @@ cs_err ARM_global_init(cs_struct *ud)
 	ud->insn_name = ARM_insn_name;
 	ud->group_name = ARM_group_name;
 	ud->post_printer = ARM_post_printer;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = ARM_reg_access;
+#endif

 	if (ud->mode & CS_MODE_THUMB)
 		ud->disasm = Thumb_getInstruction;
--- a/arch/EVM/EVMDisassembler.c
+++ b/arch/EVM/EVMDisassembler.c
@ -0,0 +1,379 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include <string.h>
+#include <stddef.h> // offsetof macro
+                    // alternatively #include "../../utils.h" like everyone else
+
+#include "EVMDisassembler.h"
+#include "EVMMapping.h"
+
+static short opcodes[256] = {
+	EVM_INS_STOP,
+	EVM_INS_ADD,
+	EVM_INS_MUL,
+	EVM_INS_SUB,
+	EVM_INS_DIV,
+	EVM_INS_SDIV,
+	EVM_INS_MOD,
+	EVM_INS_SMOD,
+	EVM_INS_ADDMOD,
+	EVM_INS_MULMOD,
+	EVM_INS_EXP,
+	EVM_INS_SIGNEXTEND,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_LT,
+	EVM_INS_GT,
+	EVM_INS_SLT,
+	EVM_INS_SGT,
+	EVM_INS_EQ,
+	EVM_INS_ISZERO,
+	EVM_INS_AND,
+	EVM_INS_OR,
+	EVM_INS_XOR,
+	EVM_INS_NOT,
+	EVM_INS_BYTE,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_SHA3,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_ADDRESS,
+	EVM_INS_BALANCE,
+	EVM_INS_ORIGIN,
+	EVM_INS_CALLER,
+	EVM_INS_CALLVALUE,
+	EVM_INS_CALLDATALOAD,
+	EVM_INS_CALLDATASIZE,
+	EVM_INS_CALLDATACOPY,
+	EVM_INS_CODESIZE,
+	EVM_INS_CODECOPY,
+	EVM_INS_GASPRICE,
+	EVM_INS_EXTCODESIZE,
+	EVM_INS_EXTCODECOPY,
+	EVM_INS_RETURNDATASIZE,
+	EVM_INS_RETURNDATACOPY,
+	-1,
+	EVM_INS_BLOCKHASH,
+	EVM_INS_COINBASE,
+	EVM_INS_TIMESTAMP,
+	EVM_INS_NUMBER,
+	EVM_INS_DIFFICULTY,
+	EVM_INS_GASLIMIT,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_POP,
+	EVM_INS_MLOAD,
+	EVM_INS_MSTORE,
+	EVM_INS_MSTORE8,
+	EVM_INS_SLOAD,
+	EVM_INS_SSTORE,
+	EVM_INS_JUMP,
+	EVM_INS_JUMPI,
+	EVM_INS_PC,
+	EVM_INS_MSIZE,
+	EVM_INS_GAS,
+	EVM_INS_JUMPDEST,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_PUSH1,
+	EVM_INS_PUSH2,
+	EVM_INS_PUSH3,
+	EVM_INS_PUSH4,
+	EVM_INS_PUSH5,
+	EVM_INS_PUSH6,
+	EVM_INS_PUSH7,
+	EVM_INS_PUSH8,
+	EVM_INS_PUSH9,
+	EVM_INS_PUSH10,
+	EVM_INS_PUSH11,
+	EVM_INS_PUSH12,
+	EVM_INS_PUSH13,
+	EVM_INS_PUSH14,
+	EVM_INS_PUSH15,
+	EVM_INS_PUSH16,
+	EVM_INS_PUSH17,
+	EVM_INS_PUSH18,
+	EVM_INS_PUSH19,
+	EVM_INS_PUSH20,
+	EVM_INS_PUSH21,
+	EVM_INS_PUSH22,
+	EVM_INS_PUSH23,
+	EVM_INS_PUSH24,
+	EVM_INS_PUSH25,
+	EVM_INS_PUSH26,
+	EVM_INS_PUSH27,
+	EVM_INS_PUSH28,
+	EVM_INS_PUSH29,
+	EVM_INS_PUSH30,
+	EVM_INS_PUSH31,
+	EVM_INS_PUSH32,
+	EVM_INS_DUP1,
+	EVM_INS_DUP2,
+	EVM_INS_DUP3,
+	EVM_INS_DUP4,
+	EVM_INS_DUP5,
+	EVM_INS_DUP6,
+	EVM_INS_DUP7,
+	EVM_INS_DUP8,
+	EVM_INS_DUP9,
+	EVM_INS_DUP10,
+	EVM_INS_DUP11,
+	EVM_INS_DUP12,
+	EVM_INS_DUP13,
+	EVM_INS_DUP14,
+	EVM_INS_DUP15,
+	EVM_INS_DUP16,
+	EVM_INS_SWAP1,
+	EVM_INS_SWAP2,
+	EVM_INS_SWAP3,
+	EVM_INS_SWAP4,
+	EVM_INS_SWAP5,
+	EVM_INS_SWAP6,
+	EVM_INS_SWAP7,
+	EVM_INS_SWAP8,
+	EVM_INS_SWAP9,
+	EVM_INS_SWAP10,
+	EVM_INS_SWAP11,
+	EVM_INS_SWAP12,
+	EVM_INS_SWAP13,
+	EVM_INS_SWAP14,
+	EVM_INS_SWAP15,
+	EVM_INS_SWAP16,
+	EVM_INS_LOG0,
+	EVM_INS_LOG1,
+	EVM_INS_LOG2,
+	EVM_INS_LOG3,
+	EVM_INS_LOG4,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_CREATE,
+	EVM_INS_CALL,
+	EVM_INS_CALLCODE,
+	EVM_INS_RETURN,
+	EVM_INS_DELEGATECALL,
+	EVM_INS_CALLBLACKBOX,
+	-1,
+	-1,
+	-1,
+	-1,
+	EVM_INS_STATICCALL,
+	-1,
+	-1,
+	EVM_INS_REVERT,
+	-1,
+	EVM_INS_SUICIDE,
+};
+
+bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+	MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
+{
+	unsigned char opcode;
+
+	if (code_len == 0)
+		return false;
+
+	opcode = code[0];
+	if (opcodes[opcode] == -1) {
+		// invalid opcode
+		return false;
+	}
+
+	// valid opcode
+	MI->address = address;
+	MI->OpcodePub = MI->Opcode = opcode;
+
+	if (opcode >= EVM_INS_PUSH1 && opcode <= EVM_INS_PUSH32) {
+		unsigned char len = (opcode - EVM_INS_PUSH1 + 1);
+		if (code_len < 1 + len) {
+			// not enough data
+			return false;
+		}
+
+		*size = 1 + len;
+		memcpy(MI->evm_data, code + 1, len);
+	} else
+		*size = 1;
+
+	if (MI->flat_insn->detail) {
+		memset(MI->flat_insn->detail, 0, offsetof(cs_detail, evm)+sizeof(cs_evm));
+		EVM_get_insn_id((cs_struct *)ud, MI->flat_insn, opcode);
+
+		if (MI->flat_insn->detail->evm.pop) {
+			MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_READ;
+			MI->flat_insn->detail->groups_count++;
+		}
+
+		if (MI->flat_insn->detail->evm.push) {
+			MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STACK_WRITE;
+			MI->flat_insn->detail->groups_count++;
+		}
+
+		// setup groups
+		switch(opcode) {
+			default:
+				break;
+			case EVM_INS_ADD:
+			case EVM_INS_MUL:
+			case EVM_INS_SUB:
+			case EVM_INS_DIV:
+			case EVM_INS_SDIV:
+			case EVM_INS_MOD:
+			case EVM_INS_SMOD:
+			case EVM_INS_ADDMOD:
+			case EVM_INS_MULMOD:
+			case EVM_INS_EXP:
+			case EVM_INS_SIGNEXTEND:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MATH;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_MSTORE:
+			case EVM_INS_MSTORE8:
+			case EVM_INS_CALLDATACOPY:
+			case EVM_INS_CODECOPY:
+			case EVM_INS_EXTCODECOPY:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_WRITE;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_MLOAD:
+			case EVM_INS_CREATE:
+			case EVM_INS_CALL:
+			case EVM_INS_CALLCODE:
+			case EVM_INS_RETURN:
+			case EVM_INS_DELEGATECALL:
+			case EVM_INS_REVERT:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_MEM_READ;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_SSTORE:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_WRITE;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_SLOAD:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_STORE_READ;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_JUMP:
+			case EVM_INS_JUMPI:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_JUMP;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+			case EVM_INS_STOP:
+			case EVM_INS_SUICIDE:
+				MI->flat_insn->detail->groups[MI->flat_insn->detail->groups_count] = EVM_GRP_HALT;
+				MI->flat_insn->detail->groups_count++;
+				break;
+
+		}
+	}
+
+	return true;
+}
--- a/arch/EVM/EVMDisassembler.h
+++ b/arch/EVM/EVMDisassembler.h
@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifndef CS_EVMDISASSEMBLER_H
+#define CS_EVMDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool EVM_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+		MCInst *instr, uint16_t *size, uint64_t address, void *info);
+
+#endif
--- a/arch/EVM/EVMInstPrinter.c
+++ b/arch/EVM/EVMInstPrinter.c
@ -0,0 +1,20 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include "EVMInstPrinter.h"
+#include "EVMMapping.h"
+
+
+void EVM_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
+{
+	SStream_concat(O, EVM_insn_name((csh)MI->csh, MI->Opcode));
+
+	if (MI->Opcode >= EVM_INS_PUSH1 && MI->Opcode <= EVM_INS_PUSH32) {
+		unsigned int i;
+
+		SStream_concat0(O, "\t");
+		for (i = 0; i < MI->Opcode - EVM_INS_PUSH1 + 1; i++) {
+			SStream_concat(O, "%02x", MI->evm_data[i]);
+		}
+	}
+}
--- a/arch/EVM/EVMInstPrinter.h
+++ b/arch/EVM/EVMInstPrinter.h
@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifndef CS_EVMINSTPRINTER_H
+#define CS_EVMINSTPRINTER_H
+
+
+#include "capstone/capstone.h"
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../cs_priv.h"
+
+struct SStream;
+
+void EVM_printInst(MCInst *MI, struct SStream *O, void *Info);
+
+#endif
--- a/arch/EVM/EVMMapping.c
+++ b/arch/EVM/EVMMapping.c
@ -0,0 +1,344 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifdef CAPSTONE_HAS_EVM
+
+#include <string.h>
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "EVMMapping.h"
+
+#ifndef CAPSTONE_DIET
+static cs_evm insns[256] = {
+#include "EVMMappingInsn.inc"
+};
+#endif
+
+// look for @id in @insns, given its size in @max.
+// return -1 if not found
+static int evm_insn_find(cs_evm *insns, unsigned int max, unsigned int id)
+{
+	if (id >= max)
+		return -1;
+
+	if (insns[id].fee == 0xffffffff)
+		// unused opcode
+		return -1;
+
+	return (int)id;
+}
+
+// fill in details
+void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
+{
+	insn->id = id;
+#ifndef CAPSTONE_DIET
+	if (evm_insn_find(insns, ARR_SIZE(insns), id) > 0) {
+		if (h->detail) {
+			memcpy(&insn->detail->evm, &insns[id], sizeof(insns[id]));
+		}
+	}
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map insn_name_maps[] = {
+	{ EVM_INS_STOP, "stop" },
+	{ EVM_INS_ADD, "add" },
+	{ EVM_INS_MUL, "mul" },
+	{ EVM_INS_SUB, "sub" },
+	{ EVM_INS_DIV, "div" },
+	{ EVM_INS_SDIV, "sdiv" },
+	{ EVM_INS_MOD, "mod" },
+	{ EVM_INS_SMOD, "smod" },
+	{ EVM_INS_ADDMOD, "addmod" },
+	{ EVM_INS_MULMOD, "mulmod" },
+	{ EVM_INS_EXP, "exp" },
+	{ EVM_INS_SIGNEXTEND, "signextend" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_LT, "lt" },
+	{ EVM_INS_GT, "gt" },
+	{ EVM_INS_SLT, "slt" },
+	{ EVM_INS_SGT, "sgt" },
+	{ EVM_INS_EQ, "eq" },
+	{ EVM_INS_ISZERO, "iszero" },
+	{ EVM_INS_AND, "and" },
+	{ EVM_INS_OR, "or" },
+	{ EVM_INS_XOR, "xor" },
+	{ EVM_INS_NOT, "not" },
+	{ EVM_INS_BYTE, "byte" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_SHA3, "sha3" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_ADDRESS, "address" },
+	{ EVM_INS_BALANCE, "balance" },
+	{ EVM_INS_ORIGIN, "origin" },
+	{ EVM_INS_CALLER, "caller" },
+	{ EVM_INS_CALLVALUE, "callvalue" },
+	{ EVM_INS_CALLDATALOAD, "calldataload" },
+	{ EVM_INS_CALLDATASIZE, "calldatasize" },
+	{ EVM_INS_CALLDATACOPY, "calldatacopy" },
+	{ EVM_INS_CODESIZE, "codesize" },
+	{ EVM_INS_CODECOPY, "codecopy" },
+	{ EVM_INS_GASPRICE, "gasprice" },
+	{ EVM_INS_EXTCODESIZE, "extcodesize" },
+	{ EVM_INS_EXTCODECOPY, "extcodecopy" },
+	{ EVM_INS_RETURNDATASIZE, "returndatasize" },
+	{ EVM_INS_RETURNDATACOPY, "returndatacopy" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_BLOCKHASH, "blockhash" },
+	{ EVM_INS_COINBASE, "coinbase" },
+	{ EVM_INS_TIMESTAMP, "timestamp" },
+	{ EVM_INS_NUMBER, "number" },
+	{ EVM_INS_DIFFICULTY, "difficulty" },
+	{ EVM_INS_GASLIMIT, "gaslimit" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_POP, "pop" },
+	{ EVM_INS_MLOAD, "mload" },
+	{ EVM_INS_MSTORE, "mstore" },
+	{ EVM_INS_MSTORE8, "mstore8" },
+	{ EVM_INS_SLOAD, "sload" },
+	{ EVM_INS_SSTORE, "sstore" },
+	{ EVM_INS_JUMP, "jump" },
+	{ EVM_INS_JUMPI, "jumpi" },
+	{ EVM_INS_PC, "pc" },
+	{ EVM_INS_MSIZE, "msize" },
+	{ EVM_INS_GAS, "gas" },
+	{ EVM_INS_JUMPDEST, "jumpdest" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_PUSH1, "push1" },
+	{ EVM_INS_PUSH2, "push2" },
+	{ EVM_INS_PUSH3, "push3" },
+	{ EVM_INS_PUSH4, "push4" },
+	{ EVM_INS_PUSH5, "push5" },
+	{ EVM_INS_PUSH6, "push6" },
+	{ EVM_INS_PUSH7, "push7" },
+	{ EVM_INS_PUSH8, "push8" },
+	{ EVM_INS_PUSH9, "push9" },
+	{ EVM_INS_PUSH10, "push10" },
+	{ EVM_INS_PUSH11, "push11" },
+	{ EVM_INS_PUSH12, "push12" },
+	{ EVM_INS_PUSH13, "push13" },
+	{ EVM_INS_PUSH14, "push14" },
+	{ EVM_INS_PUSH15, "push15" },
+	{ EVM_INS_PUSH16, "push16" },
+	{ EVM_INS_PUSH17, "push17" },
+	{ EVM_INS_PUSH18, "push18" },
+	{ EVM_INS_PUSH19, "push19" },
+	{ EVM_INS_PUSH20, "push20" },
+	{ EVM_INS_PUSH21, "push21" },
+	{ EVM_INS_PUSH22, "push22" },
+	{ EVM_INS_PUSH23, "push23" },
+	{ EVM_INS_PUSH24, "push24" },
+	{ EVM_INS_PUSH25, "push25" },
+	{ EVM_INS_PUSH26, "push26" },
+	{ EVM_INS_PUSH27, "push27" },
+	{ EVM_INS_PUSH28, "push28" },
+	{ EVM_INS_PUSH29, "push29" },
+	{ EVM_INS_PUSH30, "push30" },
+	{ EVM_INS_PUSH31, "push31" },
+	{ EVM_INS_PUSH32, "push32" },
+	{ EVM_INS_DUP1, "dup1" },
+	{ EVM_INS_DUP2, "dup2" },
+	{ EVM_INS_DUP3, "dup3" },
+	{ EVM_INS_DUP4, "dup4" },
+	{ EVM_INS_DUP5, "dup5" },
+	{ EVM_INS_DUP6, "dup6" },
+	{ EVM_INS_DUP7, "dup7" },
+	{ EVM_INS_DUP8, "dup8" },
+	{ EVM_INS_DUP9, "dup9" },
+	{ EVM_INS_DUP10, "dup10" },
+	{ EVM_INS_DUP11, "dup11" },
+	{ EVM_INS_DUP12, "dup12" },
+	{ EVM_INS_DUP13, "dup13" },
+	{ EVM_INS_DUP14, "dup14" },
+	{ EVM_INS_DUP15, "dup15" },
+	{ EVM_INS_DUP16, "dup16" },
+	{ EVM_INS_SWAP1, "swap1" },
+	{ EVM_INS_SWAP2, "swap2" },
+	{ EVM_INS_SWAP3, "swap3" },
+	{ EVM_INS_SWAP4, "swap4" },
+	{ EVM_INS_SWAP5, "swap5" },
+	{ EVM_INS_SWAP6, "swap6" },
+	{ EVM_INS_SWAP7, "swap7" },
+	{ EVM_INS_SWAP8, "swap8" },
+	{ EVM_INS_SWAP9, "swap9" },
+	{ EVM_INS_SWAP10, "swap10" },
+	{ EVM_INS_SWAP11, "swap11" },
+	{ EVM_INS_SWAP12, "swap12" },
+	{ EVM_INS_SWAP13, "swap13" },
+	{ EVM_INS_SWAP14, "swap14" },
+	{ EVM_INS_SWAP15, "swap15" },
+	{ EVM_INS_SWAP16, "swap16" },
+	{ EVM_INS_LOG0, "log0" },
+	{ EVM_INS_LOG1, "log1" },
+	{ EVM_INS_LOG2, "log2" },
+	{ EVM_INS_LOG3, "log3" },
+	{ EVM_INS_LOG4, "log4" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_CREATE, "create" },
+	{ EVM_INS_CALL, "call" },
+	{ EVM_INS_CALLCODE, "callcode" },
+	{ EVM_INS_RETURN, "return" },
+	{ EVM_INS_DELEGATECALL, "delegatecall" },
+	{ EVM_INS_CALLBLACKBOX, "callblackbox" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_STATICCALL, "staticcall" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_REVERT, "revert" },
+	{ EVM_INS_INVALID, NULL },
+	{ EVM_INS_SUICIDE, "suicide" },
+};
+#endif
+
+const char *EVM_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	if (id >= ARR_SIZE(insn_name_maps))
+		return NULL;
+	else
+		return insn_name_maps[id].name;
+#else
+	return NULL;
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	// generic groups
+	{ EVM_GRP_INVALID, NULL },
+	{ EVM_GRP_JUMP,	"jump" },
+	// special groups
+	{ EVM_GRP_MATH,	"math" },
+	{ EVM_GRP_STACK_WRITE, "stack_write" },
+	{ EVM_GRP_STACK_READ, "stack_read" },
+	{ EVM_GRP_MEM_WRITE, "mem_write" },
+	{ EVM_GRP_MEM_READ, "mem_read" },
+	{ EVM_GRP_STORE_WRITE, "store_write" },
+	{ EVM_GRP_STORE_READ, "store_read" },
+	{ EVM_GRP_HALT, "halt" },
+};
+#endif
+
+const char *EVM_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+#endif
--- a/arch/EVM/EVMMapping.h
+++ b/arch/EVM/EVMMapping.h
@ -0,0 +1,8 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#include <capstone/capstone.h>
+
+void EVM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+const char *EVM_insn_name(csh handle, unsigned int id);
+const char *EVM_group_name(csh handle, unsigned int id);
--- a/arch/EVM/EVMMappingInsn.inc
+++ b/arch/EVM/EVMMappingInsn.inc
@ -0,0 +1,259 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+{ 0, 0, 0 }, // STOP
+{ 2, 1, 3 }, // ADD
+{ 2, 1, 5 }, // MUL
+{ 2, 1, 3 }, // SUB
+{ 2, 1, 5 }, // DIV
+{ 2, 1, 5 }, // SDIV
+{ 2, 1, 5 }, // MOD
+{ 2, 1, 5 }, // SMOD
+{ 3, 1, 8 }, // ADDMOD
+{ 3, 1, 8 }, // MULMOD
+{ 2, 1, 10 }, // EXP
+{ 2, 1, 5 }, // SIGNEXTEND
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 1, 3 }, // LT
+{ 2, 1, 3 }, // GT
+{ 2, 1, 3 }, // SLT
+{ 2, 1, 3 }, // SGT
+{ 2, 1, 3 }, // EQ
+{ 1, 1, 3 }, // ISZERO
+{ 2, 1, 3 }, // AND
+{ 2, 1, 3 }, // OR
+{ 2, 1, 3 }, // XOR
+{ 1, 1, 3 }, // NOT
+{ 2, 1, 3 }, // BYTE
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 1, 30 }, // SHA3
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 1, 2 }, // ADDRESS
+{ 1, 1, 20 }, // BALANCE
+{ 0, 1, 2 }, // ORIGIN
+{ 0, 1, 2 }, // CALLER
+{ 0, 1, 2 }, // CALLVALUE
+{ 1, 1, 3 }, // CALLDATALOAD
+{ 0, 1, 2 }, // CALLDATASIZE
+{ 3, 0, 3 }, // CALLDATACOPY
+{ 0, 1, 2 }, // CODESIZE
+{ 3, 0, 3 }, // CODECOPY
+{ 0, 1, 2 }, // GASPRICE
+{ 1, 1, 20 }, // EXTCODESIZE
+{ 4, 0, 20 }, // EXTCODECOPY
+{ 0, 1, 2 }, // RETURNDATASIZE
+{ 3, 0, 3 }, // RETURNDATACOPY
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 1, 20 }, // BLOCKHASH
+{ 0, 1, 2 }, // COINBASE
+{ 0, 1, 2 }, // TIMESTAMP
+{ 0, 1, 2 }, // NUMBER
+{ 0, 1, 2 }, // DIFFICULTY
+{ 0, 1, 2 }, // GASLIMIT
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 0, 2 }, // POP
+{ 1, 1, 3 }, // MLOAD
+{ 2, 0, 3 }, // MSTORE
+{ 2, 0, 3 }, // MSTORE8
+{ 1, 1, 50 }, // SLOAD
+{ 2, 0, 0 }, // SSTORE
+{ 1, 0, 8 }, // JUMP
+{ 2, 0, 10 }, // JUMPI
+{ 0, 1, 2 }, // GETPC
+{ 0, 1, 2 }, // MSIZE
+{ 0, 1, 2 }, // GAS
+{ 0, 0, 1 }, // JUMPDEST
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 1, 3 }, // PUSH1
+{ 0, 1, 3 }, // PUSH2
+{ 0, 1, 3 }, // PUSH3
+{ 0, 1, 3 }, // PUSH4
+{ 0, 1, 3 }, // PUSH5
+{ 0, 1, 3 }, // PUSH6
+{ 0, 1, 3 }, // PUSH7
+{ 0, 1, 3 }, // PUSH8
+{ 0, 1, 3 }, // PUSH9
+{ 0, 1, 3 }, // PUSH10
+{ 0, 1, 3 }, // PUSH11
+{ 0, 1, 3 }, // PUSH12
+{ 0, 1, 3 }, // PUSH13
+{ 0, 1, 3 }, // PUSH14
+{ 0, 1, 3 }, // PUSH15
+{ 0, 1, 3 }, // PUSH16
+{ 0, 1, 3 }, // PUSH17
+{ 0, 1, 3 }, // PUSH18
+{ 0, 1, 3 }, // PUSH19
+{ 0, 1, 3 }, // PUSH20
+{ 0, 1, 3 }, // PUSH21
+{ 0, 1, 3 }, // PUSH22
+{ 0, 1, 3 }, // PUSH23
+{ 0, 1, 3 }, // PUSH24
+{ 0, 1, 3 }, // PUSH25
+{ 0, 1, 3 }, // PUSH26
+{ 0, 1, 3 }, // PUSH27
+{ 0, 1, 3 }, // PUSH28
+{ 0, 1, 3 }, // PUSH29
+{ 0, 1, 3 }, // PUSH30
+{ 0, 1, 3 }, // PUSH31
+{ 0, 1, 3 }, // PUSH32
+{ 1, 2, 3 }, // DUP1
+{ 2, 3, 3 }, // DUP2
+{ 3, 4, 3 }, // DUP3
+{ 4, 5, 3 }, // DUP4
+{ 5, 6, 3 }, // DUP5
+{ 6, 7, 3 }, // DUP6
+{ 7, 8, 3 }, // DUP7
+{ 8, 9, 3 }, // DUP8
+{ 9, 10, 3 }, // DUP9
+{ 10, 11, 3 }, // DUP10
+{ 11, 12, 3 }, // DUP11
+{ 12, 13, 3 }, // DUP12
+{ 13, 14, 3 }, // DUP13
+{ 14, 15, 3 }, // DUP14
+{ 15, 16, 3 }, // DUP15
+{ 16, 17, 3 }, // DUP16
+{ 2, 2, 3 }, // SWAP1
+{ 3, 3, 3 }, // SWAP2
+{ 4, 4, 3 }, // SWAP3
+{ 5, 5, 3 }, // SWAP4
+{ 6, 6, 3 }, // SWAP5
+{ 7, 7, 3 }, // SWAP6
+{ 8, 8, 3 }, // SWAP7
+{ 9, 9, 3 }, // SWAP8
+{ 10, 10, 3 }, // SWAP9
+{ 11, 11, 3 }, // SWAP10
+{ 12, 12, 3 }, // SWAP11
+{ 13, 13, 3 }, // SWAP12
+{ 14, 14, 3 }, // SWAP13
+{ 15, 15, 3 }, // SWAP14
+{ 16, 16, 3 }, // SWAP15
+{ 17, 17, 3 }, // SWAP16
+{ 2, 0, 375 }, // LOG0
+{ 3, 0, 750 }, // LOG1
+{ 4, 0, 1125 }, // LOG2
+{ 5, 0, 1500 }, // LOG3
+{ 6, 0, 1875 }, // LOG4
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 3, 1, 32000 }, // CREATE
+{ 7, 1, 40 }, // CALL
+{ 7, 1, 40 }, // CALLCODE
+{ 2, 0, 0 }, // RETURN
+{ 6, 1, 40 }, // DELEGATECALL
+{ 7, 1, 40 }, // CALLBLACKBOX
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 6, 1, 40 }, // STATICCALL
+{ 0, 0, 0xffffffff }, // unused
+{ 0, 0, 0xffffffff }, // unused
+{ 2, 0, 0 }, // REVERT
+{ 0, 0, 0xffffffff }, // unused
+{ 1, 0, 0 }, // SUICIDE
--- a/arch/EVM/EVMModule.c
+++ b/arch/EVM/EVMModule.c
@ -0,0 +1,33 @@
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh, 2018 */
+
+#ifdef CAPSTONE_HAS_EVM
+
+#include "../../cs_priv.h"
+#include "EVMDisassembler.h"
+#include "EVMInstPrinter.h"
+#include "EVMMapping.h"
+#include "EVMModule.h"
+
+cs_err EVM_global_init(cs_struct *ud)
+{
+	// verify if requested mode is valid
+	if (ud->mode)
+		return CS_ERR_MODE;
+
+	ud->printer = EVM_printInst;
+	ud->printer_info = NULL;
+	ud->insn_id = EVM_get_insn_id;
+	ud->insn_name = EVM_insn_name;
+	ud->group_name = EVM_group_name;
+	ud->disasm = EVM_getInstruction;
+
+	return CS_ERR_OK;
+}
+
+cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	return CS_ERR_OK;
+}
+
+#endif
--- a/arch/EVM/EVMModule.h
+++ b/arch/EVM/EVMModule.h
@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_EVM_MODULE_H
+#define CS_EVM_MODULE_H
+
+#include "../../utils.h"
+
+cs_err EVM_global_init(cs_struct *ud);
+cs_err EVM_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif
--- a/arch/M680X/M680XDisassembler.c
+++ b/arch/M680X/M680XDisassembler.c
--- a/arch/M680X/M680XDisassembler.h
+++ b/arch/M680X/M680XDisassembler.h
@ -0,0 +1,17 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XDISASSEMBLER_H
+#define CS_M680XDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+bool M680X_getInstruction(csh ud, const uint8_t *code, size_t code_len,
+	MCInst *instr, uint16_t *size, uint64_t address, void *info);
+void M680X_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
+void M680X_reg_access(const cs_insn *insn,
+	cs_regs regs_read, uint8_t *regs_read_count,
+	cs_regs regs_write, uint8_t *regs_write_count);
+
+#endif
+
--- a/arch/M680X/M680XDisassemblerInternals.h
+++ b/arch/M680X/M680XDisassemblerInternals.h
@ -0,0 +1,57 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XDISASSEMBLERINTERNALS_H
+#define CS_M680XDISASSEMBLERINTERNALS_H
+
+#include "../../MCInst.h"
+#include "../../include/capstone/m680x.h"
+
+typedef enum e_cpu_type {
+	M680X_CPU_TYPE_INVALID,
+	M680X_CPU_TYPE_6301,	// M680X Hitachi HD6301,HD6303 mode
+	M680X_CPU_TYPE_6309,	// M680X Hitachi HD6309 mode
+	M680X_CPU_TYPE_6800,	// M680X Motorola 6800,6802 mode
+	M680X_CPU_TYPE_6801,	// M680X Motorola 6801,6803 mode
+	M680X_CPU_TYPE_6805,	// M680X Motorola/Freescale M68HC05 mode
+	M680X_CPU_TYPE_6808,	// M680X Motorola/Freescale M68HC08 mode
+	M680X_CPU_TYPE_6809,	// M680X Motorola 6809 mode
+	M680X_CPU_TYPE_6811,	// M680X Motorola/Freescale M68HC11 mode
+	M680X_CPU_TYPE_CPU12,	// M680X Motorola/Freescale CPU12 mode
+	// used on M68HC12/HCS12
+	M680X_CPU_TYPE_HCS08,	// M680X Freescale HCS08 mode
+	M680X_CPU_TYPE_ENDING,
+} e_cpu_type;
+
+struct inst_page1;
+struct inst_pageX;
+
+typedef struct {
+	const struct inst_page1 *inst_page1_table;
+	const struct inst_pageX *inst_overlay_table[2];
+	size_t overlay_table_size[2];
+	uint8_t pageX_prefix[3];
+	const struct inst_pageX *inst_pageX_table[3];
+	size_t pageX_table_size[3];
+	const uint8_t *reg_byte_size;
+	const bool *tfr_reg_valid;
+	m680x_insn insn_cc_not_modified[2];
+} cpu_tables;
+
+/* Private, For internal use only */
+typedef struct m680x_info {
+	const uint8_t *code;	// code buffer
+	uint32_t size;		// byte size of code
+	uint16_t offset;	// address offset of first byte in code buffer
+	e_cpu_type cpu_type;	// The CPU type to be used for disassembling
+	cs_m680x m680x;		// M680X specific properties
+	const cpu_tables *cpu;
+	m680x_insn insn;	// Instruction ID
+	uint8_t insn_size;	// byte size of instruction
+} m680x_info;
+
+extern cs_err M680X_disassembler_init(cs_struct *ud);
+extern cs_err M680X_instprinter_init(cs_struct *ud);
+
+#endif
+
--- a/arch/M680X/M680XInstPrinter.c
+++ b/arch/M680X/M680XInstPrinter.c
@ -0,0 +1,365 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef CAPSTONE_HAS_M680X
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <capstone/platform.h>
+
+#include "../../MCInst.h"
+#include "../../SStream.h"
+#include "../../MCRegisterInfo.h"
+#include "../../utils.h"
+#include "M680XInstPrinter.h"
+#include "M680XDisassembler.h"
+#include "M680XDisassemblerInternals.h"
+
+#ifndef CAPSTONE_DIET
+static const char s_reg_names[][10] = {
+	"<invalid>", "A", "B", "E", "F", "0", "D", "W", "CC", "DP", "MD",
+	"HX", "H", "X", "Y", "S", "U", "V", "Q", "PC", "TMP2", "TMP3",
+};
+
+static const char s_instruction_names[][6] = {
+	"INVLD", "ABA", "ABX", "ABY", "ADC", "ADCA", "ADCB", "ADCD", "ADCR",
+	"ADD", "ADDA", "ADDB", "ADDD", "ADDE", "ADDF", "ADDR", "ADDW",
+	"AIM", "AIS", "AIX", "AND", "ANDA", "ANDB", "ANDCC", "ANDD", "ANDR",
+	"ASL", "ASLA", "ASLB", "ASLD",
+	"ASR", "ASRA", "ASRB", "ASRD", "ASRX",
+	"BAND",
+	"BCC", "BCLR", "BCS", "BEOR", "BEQ", "BGE", "BGND", "BGT", "BHCC",
+	"BHCS", "BHI",
+	"BIAND", "BIEOR", "BIH", "BIL",
+	"BIOR", "BIT", "BITA", "BITB", "BITD", "BITMD", "BLE", "BLS", "BLT",
+	"BMC",
+	"BMI", "BMS",
+	"BNE", "BOR", "BPL", "BRCLR", "BRSET", "BRA", "BRN", "BSET", "BSR",
+	"BVC", "BVS",
+	"CALL", "CBA", "CBEQ", "CBEQA", "CBEQX", "CLC", "CLI",
+	"CLR", "CLRA", "CLRB", "CLRD", "CLRE", "CLRF", "CLRH", "CLRW", "CLRX",
+	"CLV", "CMP",
+	"CMPA", "CMPB", "CMPD", "CMPE", "CMPF", "CMPR", "CMPS", "CMPU", "CMPW",
+	"CMPX", "CMPY",
+	"COM", "COMA", "COMB", "COMD", "COME", "COMF", "COMW", "COMX", "CPD",
+	"CPHX", "CPS", "CPX", "CPY",
+	"CWAI", "DAA", "DBEQ", "DBNE", "DBNZ", "DBNZA", "DBNZX",
+	"DEC", "DECA", "DECB", "DECD", "DECE", "DECF", "DECW",
+	"DECX", "DES", "DEX", "DEY",
+	"DIV", "DIVD", "DIVQ", "EDIV", "EDIVS", "EIM", "EMACS", "EMAXD",
+	"EMAXM", "EMIND", "EMINM", "EMUL", "EMULS",
+	"EOR", "EORA", "EORB", "EORD", "EORR", "ETBL",
+	"EXG", "FDIV", "IBEQ", "IBNE", "IDIV", "IDIVS", "ILLGL",
+	"INC", "INCA", "INCB", "INCD", "INCE", "INCF", "INCW", "INCX",
+	"INS", "INX", "INY",
+	"JMP", "JSR",
+	"LBCC", "LBCS", "LBEQ", "LBGE", "LBGT", "LBHI", "LBLE", "LBLS", "LBLT",
+	"LBMI", "LBNE", "LBPL", "LBRA", "LBRN", "LBSR", "LBVC", "LBVS",
+	"LDA", "LDAA", "LDAB", "LDB", "LDBT", "LDD", "LDE", "LDF", "LDHX",
+	"LDMD",
+	"LDQ", "LDS", "LDU", "LDW", "LDX", "LDY",
+	"LEAS", "LEAU", "LEAX", "LEAY",
+	"LSL", "LSLA", "LSLB", "LSLD", "LSLX",
+	"LSR", "LSRA", "LSRB", "LSRD", "LSRW", "LSRX",
+	"MAXA", "MAXM", "MEM", "MINA", "MINM", "MOV", "MOVB", "MOVW", "MUL",
+	"MULD",
+	"NEG", "NEGA", "NEGB", "NEGD", "NEGX",
+	"NOP", "NSA", "OIM", "ORA", "ORAA", "ORAB", "ORB", "ORCC", "ORD", "ORR",
+	"PSHA", "PSHB", "PSHC", "PSHD", "PSHH", "PSHS", "PSHSW", "PSHU",
+	"PSHUW", "PSHX", "PSHY",
+	"PULA", "PULB", "PULC", "PULD", "PULH", "PULS", "PULSW", "PULU",
+	"PULUW", "PULX", "PULY", "REV", "REVW",
+	"ROL", "ROLA", "ROLB", "ROLD", "ROLW", "ROLX",
+	"ROR", "RORA", "RORB", "RORD", "RORW", "RORX",
+	"RSP", "RTC", "RTI", "RTS", "SBA", "SBC", "SBCA", "SBCB", "SBCD",
+	"SBCR",
+	"SEC", "SEI", "SEV", "SEX", "SEXW", "SLP", "STA", "STAA", "STAB", "STB",
+	"STBT", "STD", "STE", "STF", "STOP", "STHX",
+	"STQ", "STS", "STU", "STW", "STX", "STY",
+	"SUB", "SUBA", "SUBB", "SUBD", "SUBE", "SUBF", "SUBR", "SUBW",
+	"SWI", "SWI2", "SWI3",
+	"SYNC", "TAB", "TAP", "TAX", "TBA", "TBEQ", "TBL", "TBNE", "TEST",
+	"TFM", "TFR",
+	"TIM", "TPA",
+	"TST", "TSTA", "TSTB", "TSTD", "TSTE", "TSTF", "TSTW", "TSTX",
+	"TSX", "TSY", "TXA", "TXS", "TYS", "WAI", "WAIT", "WAV", "WAVR",
+	"XGDX", "XGDY",
+};
+
+static name_map s_group_names[] = {
+	{ M680X_GRP_INVALID, "<invalid>" },
+	{ M680X_GRP_JUMP,  "JUMP" },
+	{ M680X_GRP_CALL,  "CALL" },
+	{ M680X_GRP_RET, "RETURN" },
+	{ M680X_GRP_INT, "INTERRUPT" },
+	{ M680X_GRP_IRET,  "INTERRUPT_RETURN" },
+	{ M680X_GRP_PRIV,  "PRIVILEGED" },
+	{ M680X_GRP_BRAREL,  "BRANCH_RELATIVE" },
+};
+#endif
+
+static void printRegName(cs_struct *handle, SStream *OS, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+	SStream_concat(OS, handle->reg_name((csh)handle, reg));
+#endif
+}
+
+static void printInstructionName(cs_struct *handle, SStream *OS,
+	unsigned int insn)
+{
+#ifndef CAPSTONE_DIET
+	SStream_concat(OS, handle->insn_name((csh)handle, insn));
+#endif
+}
+
+static uint32_t get_unsigned(int32_t value, int byte_size)
+{
+	switch (byte_size) {
+	case 1:
+		return (uint32_t)(value & 0xff);
+
+	case 2:
+		return (uint32_t)(value & 0xffff);
+
+	default:
+	case 4:
+		return (uint32_t)value;
+	}
+}
+
+static void printIncDec(bool isPost, SStream *O, m680x_info *info,
+	cs_m680x_op *op)
+{
+	static const char s_inc_dec[][3] = { "--", "-", "", "+", "++" };
+
+	if (!op->idx.inc_dec)
+		return;
+
+	if ((!isPost && !(op->idx.flags & M680X_IDX_POST_INC_DEC)) ||
+		(isPost && (op->idx.flags & M680X_IDX_POST_INC_DEC))) {
+		const char *prePostfix = "";
+
+		if (info->cpu_type == M680X_CPU_TYPE_CPU12)
+			prePostfix = (op->idx.inc_dec < 0) ? "-" : "+";
+		else if (op->idx.inc_dec >= -2 && (op->idx.inc_dec <= 2)) {
+			prePostfix = (char *)s_inc_dec[op->idx.inc_dec + 2];
+		}
+
+		SStream_concat(O, prePostfix);
+	}
+}
+
+static void printOperand(MCInst *MI, SStream *O, m680x_info *info,
+	cs_m680x_op *op)
+{
+	switch (op->type) {
+	case M680X_OP_REGISTER:
+		printRegName(MI->csh, O, op->reg);
+		break;
+
+	case M680X_OP_CONSTANT:
+		SStream_concat(O, "%u", op->const_val);
+		break;
+
+	case M680X_OP_IMMEDIATE:
+		if (MI->csh->imm_unsigned)
+			SStream_concat(O, "#%u",
+				get_unsigned(op->imm, op->size));
+		else
+			SStream_concat(O, "#%d", op->imm);
+
+		break;
+
+	case M680X_OP_INDEXED:
+		if (op->idx.flags & M680X_IDX_INDIRECT)
+			SStream_concat(O, "[");
+
+		if (op->idx.offset_reg != M680X_REG_INVALID)
+			printRegName(MI->csh, O, op->idx.offset_reg);
+		else if (op->idx.offset_bits > 0) {
+			if (op->idx.base_reg == M680X_REG_PC)
+				SStream_concat(O, "$%04X", op->idx.offset_addr);
+			else
+				SStream_concat(O, "%d", op->idx.offset);
+		}
+		else if (op->idx.inc_dec != 0 &&
+			info->cpu_type == M680X_CPU_TYPE_CPU12)
+			SStream_concat(O, "%d", abs(op->idx.inc_dec));
+
+		if (!(op->idx.flags & M680X_IDX_NO_COMMA))
+			SStream_concat(O, ",");
+
+		printIncDec(false, O, info, op);
+
+		printRegName(MI->csh, O, op->idx.base_reg);
+
+		if (op->idx.base_reg == M680X_REG_PC &&
+			(op->idx.offset_bits > 0))
+			SStream_concat(O, "R");
+
+		printIncDec(true, O, info, op);
+
+		if (op->idx.flags & M680X_IDX_INDIRECT)
+			SStream_concat(O, "]");
+
+		break;
+
+	case M680X_OP_RELATIVE:
+		SStream_concat(O, "$%04X", op->rel.address);
+		break;
+
+	case M680X_OP_DIRECT:
+		SStream_concat(O, "$%02X", op->direct_addr);
+		break;
+
+	case M680X_OP_EXTENDED:
+		if (op->ext.indirect)
+			SStream_concat(O, "[$%04X]", op->ext.address);
+		else {
+			if (op->ext.address < 256) {
+				SStream_concat(O, ">$%04X", op->ext.address);
+			}
+			else {
+				SStream_concat(O, "$%04X", op->ext.address);
+			}
+		}
+
+		break;
+
+	default:
+		SStream_concat(O, "<invalid_operand>");
+		break;
+	}
+}
+
+static const char *getDelimiter(m680x_info *info, cs_m680x *m680x)
+{
+	bool indexed = false;
+	int count = 0;
+	int i;
+
+	if (info->insn == M680X_INS_TFM)
+		return ",";
+
+	if (m680x->op_count > 1) {
+		for (i  = 0; i < m680x->op_count; ++i) {
+			if (m680x->operands[i].type == M680X_OP_INDEXED)
+				indexed = true;
+
+			if (m680x->operands[i].type != M680X_OP_REGISTER)
+				count++;
+		}
+	}
+
+	return (indexed && (count >= 1)) ? ";" : ",";
+};
+
+void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo)
+{
+	m680x_info *info = (m680x_info *)PrinterInfo;
+	cs_m680x *m680x = &info->m680x;
+	cs_detail *detail = MI->flat_insn->detail;
+	int suppress_operands = 0;
+	const char *delimiter = getDelimiter(info, m680x);
+	int i;
+
+	if (detail != NULL)
+		memcpy(&detail->m680x, m680x, sizeof(cs_m680x));
+
+	if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) {
+		if (m680x->op_count)
+			SStream_concat(O, "FCB $%02X", m680x->operands[0].imm);
+		else
+			SStream_concat(O, "FCB $<unknown>");
+
+		return;
+	}
+
+	printInstructionName(MI->csh, O, info->insn);
+	SStream_concat(O, " ");
+
+	if ((m680x->flags & M680X_FIRST_OP_IN_MNEM) != 0)
+		suppress_operands++;
+
+	if ((m680x->flags & M680X_SECOND_OP_IN_MNEM) != 0)
+		suppress_operands++;
+
+	for (i  = 0; i < m680x->op_count; ++i) {
+		if (i >= suppress_operands) {
+			printOperand(MI, O, info, &m680x->operands[i]);
+
+			if ((i + 1) != m680x->op_count)
+				SStream_concat(O, delimiter);
+		}
+	}
+}
+
+const char *M680X_reg_name(csh handle, unsigned int reg)
+{
+#ifndef CAPSTONE_DIET
+
+	if (reg >= M680X_REG_ENDING)
+		return NULL;
+
+	return s_reg_names[(int)reg];
+#else
+	return NULL;
+#endif
+}
+
+const char *M680X_insn_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+
+	if (id >= ARR_SIZE(s_instruction_names))
+		return NULL;
+	else
+		return s_instruction_names[(int)id];
+
+#else
+	return NULL;
+#endif
+}
+
+const char *M680X_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(s_group_names, ARR_SIZE(s_group_names), id);
+#else
+	return NULL;
+#endif
+}
+
+cs_err M680X_instprinter_init(cs_struct *ud)
+{
+#ifndef CAPSTONE_DIET
+
+	if (M680X_REG_ENDING != ARR_SIZE(s_reg_names)) {
+		fprintf(stderr, "Internal error: Size mismatch in enum "
+			"m680x_reg and s_reg_names\n");
+
+		return CS_ERR_MODE;
+	}
+
+	if (M680X_INS_ENDING != ARR_SIZE(s_instruction_names)) {
+		fprintf(stderr, "Internal error: Size mismatch in enum "
+			"m680x_insn and s_instruction_names\n");
+
+		return CS_ERR_MODE;
+	}
+
+	if (M680X_GRP_ENDING != ARR_SIZE(s_group_names)) {
+		fprintf(stderr, "Internal error: Size mismatch in enum "
+			"m680x_group_type and s_group_names\n");
+
+		return CS_ERR_MODE;
+	}
+
+#endif
+
+	return CS_ERR_OK;
+}
+
+#endif
+
--- a/arch/M680X/M680XInstPrinter.h
+++ b/arch/M680X/M680XInstPrinter.h
@ -0,0 +1,25 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifndef CS_M680XINSTPRINTER_H
+#define CS_M680XINSTPRINTER_H
+
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+struct SStream;
+
+void M680X_init(MCRegisterInfo *MRI);
+
+void M680X_printInst(MCInst *MI, struct SStream *O, void *Info);
+const char *M680X_reg_name(csh handle, unsigned int reg);
+const char *M680X_insn_name(csh handle, unsigned int id);
+const char *M680X_group_name(csh handle, unsigned int id);
+void M680X_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm,
+	MCInst *mci);
+
+#endif
+
+
--- a/arch/M680X/M680XModule.c
+++ b/arch/M680X/M680XModule.c
@ -0,0 +1,77 @@
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef CAPSTONE_HAS_M680X
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "M680XDisassembler.h"
+#include "M680XDisassemblerInternals.h"
+#include "M680XInstPrinter.h"
+#include "M680XModule.h"
+
+cs_err M680X_global_init(cs_struct *ud)
+{
+	m680x_info *info;
+	cs_err errcode;
+
+	/* Do some validation checks */
+	errcode = M680X_disassembler_init(ud);
+
+	if (errcode != CS_ERR_OK)
+		return errcode;
+
+	errcode =  M680X_instprinter_init(ud);
+
+	if (errcode != CS_ERR_OK)
+		return errcode;
+
+	// verify if requested mode is valid
+	if (ud->mode & ~(CS_MODE_M680X_6800 | CS_MODE_M680X_6801 |
+			CS_MODE_M680X_6805 | CS_MODE_M680X_6808 |
+			CS_MODE_M680X_6809 | CS_MODE_M680X_6811 |
+			CS_MODE_M680X_6301 | CS_MODE_M680X_6309 |
+			CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08)) {
+		// At least one mode is not supported by M680X
+		return CS_ERR_MODE;
+	}
+
+	if (!(ud->mode & (CS_MODE_M680X_6800 | CS_MODE_M680X_6801 |
+				CS_MODE_M680X_6805 | CS_MODE_M680X_6808 |
+				CS_MODE_M680X_6809 | CS_MODE_M680X_6811 |
+				CS_MODE_M680X_6301 | CS_MODE_M680X_6309 |
+				CS_MODE_M680X_CPU12 | CS_MODE_M680X_HCS08))) {
+		// At least the cpu type has to be selected. No default.
+		return CS_ERR_MODE;
+	}
+
+	info = cs_mem_malloc(sizeof(m680x_info));
+
+	if (!info)
+		return CS_ERR_MEM;
+
+	ud->printer = M680X_printInst;
+	ud->printer_info = info;
+	ud->getinsn_info = NULL;
+	ud->disasm = M680X_getInstruction;
+	ud->reg_name = M680X_reg_name;
+	ud->insn_id = M680X_get_insn_id;
+	ud->insn_name = M680X_insn_name;
+	ud->group_name = M680X_group_name;
+	ud->skipdata_size = 1;
+	ud->post_printer = NULL;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = M680X_reg_access;
+#endif
+
+	return CS_ERR_OK;
+}
+
+cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	//TODO
+	return CS_ERR_OK;
+}
+
+#endif
+
--- a/arch/M680X/M680XModule.h
+++ b/arch/M680X/M680XModule.h
@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_M680X_MODULE_H
+#define CS_M680X_MODULE_H
+
+#include "../../utils.h"
+
+cs_err M680X_global_init(cs_struct *ud);
+cs_err M680X_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif
--- a/arch/M680X/cpu12.inc
+++ b/arch/M680X/cpu12.inc
@ -0,0 +1,335 @@
+
+// CPU12 instructions on PAGE1
+static const inst_page1 g_cpu12_inst_page1_table[256] = {
+	// 0x0x
+	{ M680X_INS_BGND, inh_hid, inh_hid },
+	{ M680X_INS_MEM, inh_hid, inh_hid },
+	{ M680X_INS_INY, inh_hid, inh_hid },
+	{ M680X_INS_DEY, inh_hid, inh_hid },
+	{ M680X_INS_DBEQ, loop_hid, inh_hid }, // or DBNE/IBEQ/IBNE/TBEQ/TBNE
+	{ M680X_INS_JMP, idx12_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_INX, inh_hid, inh_hid },
+	{ M680X_INS_DEX, inh_hid, inh_hid },
+	{ M680X_INS_RTC, inh_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_BSET, idx12_hid, imm8_hid },
+	{ M680X_INS_BCLR, idx12_hid, imm8_hid },
+	{ M680X_INS_BRSET, idx12_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, idx12_hid, imm8rel_hid },
+	// 0x1x
+	{ M680X_INS_ANDCC, imm8_hid, inh_hid },
+	{ M680X_INS_EDIV, inh_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_EMUL, inh_hid, inh_hid },
+	{ M680X_INS_ORCC, imm8_hid, inh_hid },
+	{ M680X_INS_JSR, idx12_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LEAY, idx12_hid, inh_hid },
+	{ M680X_INS_LEAX, idx12_hid, inh_hid },
+	{ M680X_INS_LEAS, idx12_hid, inh_hid },
+	{ M680X_INS_BSET, ext_hid, imm8_hid },
+	{ M680X_INS_BCLR, ext_hid, imm8_hid },
+	{ M680X_INS_BRSET, ext_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, ext_hid, imm8rel_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x
+	{ M680X_INS_PULX, inh_hid, inh_hid },
+	{ M680X_INS_PULY, inh_hid, inh_hid },
+	{ M680X_INS_PULA, inh_hid, inh_hid },
+	{ M680X_INS_PULB, inh_hid, inh_hid },
+	{ M680X_INS_PSHX, inh_hid, inh_hid },
+	{ M680X_INS_PSHY, inh_hid, inh_hid },
+	{ M680X_INS_PSHA, inh_hid, inh_hid },
+	{ M680X_INS_PSHB, inh_hid, inh_hid },
+	{ M680X_INS_PULC, inh_hid, inh_hid },
+	{ M680X_INS_PSHC, inh_hid, inh_hid },
+	{ M680X_INS_PULD, inh_hid, inh_hid },
+	{ M680X_INS_PSHD, inh_hid, inh_hid },
+	{ M680X_INS_WAVR, inh_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_WAI, inh_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_ASLA, inh_hid, inh_hid },
+	{ M680X_INS_LSRD, inh_hid, inh_hid },
+	{ M680X_INS_CALL, ext_hid, index_hid },
+	{ M680X_INS_CALL, idx12_hid, index_hid },
+	{ M680X_INS_BSET, dir_hid, imm8_hid },
+	{ M680X_INS_BCLR, dir_hid, imm8_hid },
+	{ M680X_INS_BRSET, dir_hid, imm8rel_hid },
+	{ M680X_INS_BRCLR, dir_hid, imm8rel_hid },
+	// 0x5x
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_ASLB, inh_hid, inh_hid },
+	{ M680X_INS_ASLD, inh_hid, inh_hid },
+	{ M680X_INS_STAA, dir_hid, inh_hid },
+	{ M680X_INS_STAB, dir_hid, inh_hid },
+	{ M680X_INS_STD, dir_hid, inh_hid },
+	{ M680X_INS_STY, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	{ M680X_INS_STS, dir_hid, inh_hid },
+	// 0x6x
+	{ M680X_INS_NEG, idx12_hid, inh_hid },
+	{ M680X_INS_COM, idx12_hid, inh_hid },
+	{ M680X_INS_INC, idx12_hid, inh_hid },
+	{ M680X_INS_DEC, idx12_hid, inh_hid },
+	{ M680X_INS_LSR, idx12_hid, inh_hid },
+	{ M680X_INS_ROL, idx12_hid, inh_hid },
+	{ M680X_INS_ROR, idx12_hid, inh_hid },
+	{ M680X_INS_ASR, idx12_hid, inh_hid },
+	{ M680X_INS_ASL, idx12_hid, inh_hid },
+	{ M680X_INS_CLR, idx12_hid, inh_hid },
+	{ M680X_INS_STAA, idx12_hid, inh_hid },
+	{ M680X_INS_STAB, idx12_hid, inh_hid },
+	{ M680X_INS_STD, idx12_hid, inh_hid },
+	{ M680X_INS_STY, idx12_hid, inh_hid },
+	{ M680X_INS_STX, idx12_hid, inh_hid },
+	{ M680X_INS_STS, idx12_hid, inh_hid },
+	// 0x7x
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_ASL, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	{ M680X_INS_STAA, ext_hid, inh_hid },
+	{ M680X_INS_STAB, ext_hid, inh_hid },
+	{ M680X_INS_STD, ext_hid, inh_hid },
+	{ M680X_INS_STY, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	{ M680X_INS_STS, ext_hid, inh_hid },
+	// 0x8x
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_SUBD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDAA, imm8_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORAA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CPD, imm16_hid, inh_hid },
+	{ M680X_INS_CPY, imm16_hid, inh_hid },
+	{ M680X_INS_CPX, imm16_hid, inh_hid },
+	{ M680X_INS_CPS, imm16_hid, inh_hid },
+	// 0x9x
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_SUBD, dir_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDAA, dir_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORAA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CPD, dir_hid, inh_hid },
+	{ M680X_INS_CPY, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_CPS, dir_hid, inh_hid },
+	// 0xAx
+	{ M680X_INS_SUBA, idx12_hid, inh_hid },
+	{ M680X_INS_CMPA, idx12_hid, inh_hid },
+	{ M680X_INS_SBCA, idx12_hid, inh_hid },
+	{ M680X_INS_SUBD, idx12_hid, inh_hid },
+	{ M680X_INS_ANDA, idx12_hid, inh_hid },
+	{ M680X_INS_BITA, idx12_hid, inh_hid },
+	{ M680X_INS_LDAA, idx12_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_EORA, idx12_hid, inh_hid },
+	{ M680X_INS_ADCA, idx12_hid, inh_hid },
+	{ M680X_INS_ORAA, idx12_hid, inh_hid },
+	{ M680X_INS_ADDA, idx12_hid, inh_hid },
+	{ M680X_INS_CPD, idx12_hid, inh_hid },
+	{ M680X_INS_CPY, idx12_hid, inh_hid },
+	{ M680X_INS_CPX, idx12_hid, inh_hid },
+	{ M680X_INS_CPS, idx12_hid, inh_hid },
+	// 0xBx
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_SUBD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_TFR, rr12_hid, inh_hid }, // or EXG
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CPD, ext_hid, inh_hid },
+	{ M680X_INS_CPY, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_CPS, ext_hid, inh_hid },
+	// 0xCx
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDAB, imm8_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORAB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_LDD, imm16_hid, inh_hid },
+	{ M680X_INS_LDY, imm16_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ADDD, dir_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDAB, dir_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORAB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_LDD, dir_hid, inh_hid },
+	{ M680X_INS_LDY, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_LDS, dir_hid, inh_hid },
+	// 0xEx
+	{ M680X_INS_SUBB, idx12_hid, inh_hid },
+	{ M680X_INS_CMPB, idx12_hid, inh_hid },
+	{ M680X_INS_SBCB, idx12_hid, inh_hid },
+	{ M680X_INS_ADDD, idx12_hid, inh_hid },
+	{ M680X_INS_ANDB, idx12_hid, inh_hid },
+	{ M680X_INS_BITB, idx12_hid, inh_hid },
+	{ M680X_INS_LDAB, idx12_hid, inh_hid },
+	{ M680X_INS_TST, idx12_hid, inh_hid },
+	{ M680X_INS_EORB, idx12_hid, inh_hid },
+	{ M680X_INS_ADCB, idx12_hid, inh_hid },
+	{ M680X_INS_ORAB, idx12_hid, inh_hid },
+	{ M680X_INS_ADDB, idx12_hid, inh_hid },
+	{ M680X_INS_LDD, idx12_hid, inh_hid },
+	{ M680X_INS_LDY, idx12_hid, inh_hid },
+	{ M680X_INS_LDX, idx12_hid, inh_hid },
+	{ M680X_INS_LDS, idx12_hid, inh_hid },
+	// 0xFx
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_ADDD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_LDD, ext_hid, inh_hid },
+	{ M680X_INS_LDY, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_LDS, ext_hid, inh_hid },
+};
+
+// CPU12 instructions on PAGE2
+static const inst_pageX g_cpu12_inst_page2_table[] = {
+	{ 0x00, M680X_INS_MOVW, imm16i12x_hid, inh_hid },
+	{ 0x01, M680X_INS_MOVW, exti12x_hid, inh_hid },
+	{ 0x02, M680X_INS_MOVW, idx12_hid, idx12_hid },
+	{ 0x03, M680X_INS_MOVW, imm16_hid,  ext_hid },
+	{ 0x04, M680X_INS_MOVW, ext_hid, ext_hid },
+	{ 0x05, M680X_INS_MOVW, idx12_hid, ext_hid },
+	{ 0x06, M680X_INS_ABA, inh_hid, inh_hid },
+	{ 0x07, M680X_INS_DAA, inh_hid, inh_hid },
+	{ 0x08, M680X_INS_MOVB, imm8i12x_hid, inh_hid },
+	{ 0x09, M680X_INS_MOVB, exti12x_hid, inh_hid },
+	{ 0x0a, M680X_INS_MOVB, idx12_hid, idx12_hid },
+	{ 0x0b, M680X_INS_MOVB, imm8_hid, ext_hid },
+	{ 0x0c, M680X_INS_MOVB, ext_hid, ext_hid },
+	{ 0x0d, M680X_INS_MOVB, idx12_hid, ext_hid },
+	{ 0x0e, M680X_INS_TAB, inh_hid, inh_hid },
+	{ 0x0f, M680X_INS_TBA, inh_hid, inh_hid },
+	{ 0x10, M680X_INS_IDIV, inh_hid, inh_hid },
+	{ 0x11, M680X_INS_FDIV, inh_hid, inh_hid },
+	{ 0x12, M680X_INS_EMACS, ext_hid, inh_hid },
+	{ 0x13, M680X_INS_EMULS, inh_hid, inh_hid },
+	{ 0x14, M680X_INS_EDIVS, inh_hid, inh_hid },
+	{ 0x15, M680X_INS_IDIVS, inh_hid, inh_hid },
+	{ 0x16, M680X_INS_SBA, inh_hid, inh_hid },
+	{ 0x17, M680X_INS_CBA, inh_hid, inh_hid },
+	{ 0x18, M680X_INS_MAXA, idx12_hid, inh_hid },
+	{ 0x19, M680X_INS_MINA, idx12_hid, inh_hid },
+	{ 0x1a, M680X_INS_EMAXD, idx12_hid, inh_hid },
+	{ 0x1b, M680X_INS_EMIND, idx12_hid, inh_hid },
+	{ 0x1c, M680X_INS_MAXM, idx12_hid, inh_hid },
+	{ 0x1d, M680X_INS_MINM, idx12_hid, inh_hid },
+	{ 0x1e, M680X_INS_EMAXM, idx12_hid, inh_hid },
+	{ 0x1f, M680X_INS_EMINM, idx12_hid, inh_hid },
+	{ 0x20, M680X_INS_LBRA, rel16_hid, inh_hid },
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	{ 0x3a, M680X_INS_REV, inh_hid, inh_hid },
+	{ 0x3b, M680X_INS_REVW, inh_hid, inh_hid },
+	{ 0x3c, M680X_INS_WAV, inh_hid, inh_hid },
+	{ 0x3d, M680X_INS_TBL, idx12s_hid, inh_hid },
+	{ 0x3e, M680X_INS_STOP, inh_hid, inh_hid },
+	{ 0x3f, M680X_INS_ETBL, idx12s_hid, inh_hid },
+};
+
--- a/arch/M680X/hcs08.inc
+++ b/arch/M680X/hcs08.inc
@ -0,0 +1,60 @@
+
+// Additional instructions only supported on HCS08
+static const inst_pageX g_hcs08_inst_overlay_table[] = {
+	{ 0x32, M680X_INS_LDHX, ext_hid, inh_hid },
+	{ 0x3e, M680X_INS_CPHX, ext_hid, inh_hid },
+	{ 0x82, M680X_INS_BGND, inh_hid, inh_hid },
+	{ 0x96, M680X_INS_STHX, ext_hid, inh_hid },
+};
+
+// HCS08 PAGE2 instructions (prefix 0x9E)
+static const inst_pageX g_hcs08_inst_page2_table[] = {
+	{ 0x60, M680X_INS_NEG, idxS_hid, inh_hid },
+	{ 0x61, M680X_INS_CBEQ, idxS_hid,rel8_hid },
+	{ 0x63, M680X_INS_COM, idxS_hid, inh_hid },
+	{ 0x64, M680X_INS_LSR, idxS_hid, inh_hid },
+	{ 0x66, M680X_INS_ROR, idxS_hid, inh_hid },
+	{ 0x67, M680X_INS_ASR, idxS_hid, inh_hid },
+	{ 0x68, M680X_INS_LSL, idxS_hid, inh_hid },
+	{ 0x69, M680X_INS_ROL, idxS_hid, inh_hid },
+	{ 0x6a, M680X_INS_DEC, idxS_hid, inh_hid },
+	{ 0x6b, M680X_INS_DBNZ, idxS_hid,rel8_hid },
+	{ 0x6c, M680X_INS_INC, idxS_hid, inh_hid },
+	{ 0x6d, M680X_INS_TST, idxS_hid, inh_hid },
+	{ 0x6f, M680X_INS_CLR, idxS_hid, inh_hid },
+	{ 0xae, M680X_INS_LDHX, idxX0_hid, inh_hid },
+	{ 0xbe, M680X_INS_LDHX, idxX16_hid, inh_hid },
+	{ 0xce, M680X_INS_LDHX, idxX_hid, inh_hid },
+	{ 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid },
+	{ 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid },
+	{ 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid },
+	{ 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid },
+	{ 0xd4, M680X_INS_AND, idxS16_hid, inh_hid },
+	{ 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid },
+	{ 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid },
+	{ 0xd7, M680X_INS_STA, idxS16_hid, inh_hid },
+	{ 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid },
+	{ 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid },
+	{ 0xda, M680X_INS_ORA, idxS16_hid, inh_hid },
+	{ 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid },
+	{ 0xde, M680X_INS_LDX, idxS16_hid, inh_hid },
+	{ 0xdf, M680X_INS_STX, idxS16_hid, inh_hid },
+	{ 0xe0, M680X_INS_SUB, idxS_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMP, idxS_hid, inh_hid },
+	{ 0xe2, M680X_INS_SBC, idxS_hid, inh_hid },
+	{ 0xe3, M680X_INS_CPX, idxS_hid, inh_hid },
+	{ 0xe4, M680X_INS_AND, idxS_hid, inh_hid },
+	{ 0xe5, M680X_INS_BIT, idxS_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDA, idxS_hid, inh_hid },
+	{ 0xe7, M680X_INS_STA, idxS_hid, inh_hid },
+	{ 0xe8, M680X_INS_EOR, idxS_hid, inh_hid },
+	{ 0xe9, M680X_INS_ADC, idxS_hid, inh_hid },
+	{ 0xea, M680X_INS_ORA, idxS_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADD, idxS_hid, inh_hid },
+	{ 0xee, M680X_INS_LDX, idxS_hid, inh_hid },
+	{ 0xef, M680X_INS_STX, idxS_hid, inh_hid },
+	{ 0xf3, M680X_INS_CPHX, idxS_hid, inh_hid },
+	{ 0xfe, M680X_INS_LDHX, idxS_hid, inh_hid },
+	{ 0xff, M680X_INS_STHX, idxS_hid, inh_hid },
+};
+
--- a/arch/M680X/hd6301.inc
+++ b/arch/M680X/hd6301.inc
@ -0,0 +1,15 @@
+
+// Additional instructions only supported on HD6301/3
+static const inst_pageX g_hd6301_inst_overlay_table[] = {
+	{ 0x18, M680X_INS_XGDX, inh_hid, inh_hid },
+	{ 0x1a, M680X_INS_SLP, inh_hid, inh_hid },
+	{ 0x61, M680X_INS_AIM, imm8_hid, idxX_hid },
+	{ 0x62, M680X_INS_OIM, imm8_hid, idxX_hid },
+	{ 0x65, M680X_INS_EIM, imm8_hid, idxX_hid },
+	{ 0x6B, M680X_INS_TIM, imm8_hid, idxX_hid },
+	{ 0x71, M680X_INS_AIM, imm8_hid, dir_hid },
+	{ 0x72, M680X_INS_OIM, imm8_hid, dir_hid },
+	{ 0x75, M680X_INS_EIM, imm8_hid, dir_hid },
+	{ 0x7B, M680X_INS_TIM, imm8_hid, dir_hid },
+};
+
--- a/arch/M680X/hd6309.inc
+++ b/arch/M680X/hd6309.inc
@ -0,0 +1,259 @@
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// Additional instructions only supported on HD6309 PAGE1
+static const inst_pageX g_hd6309_inst_overlay_table[] = {
+	{ 0x01, M680X_INS_OIM, imm8_hid, dir_hid },
+	{ 0x02, M680X_INS_AIM, imm8_hid, dir_hid },
+	{ 0x05, M680X_INS_EIM, imm8_hid, dir_hid },
+	{ 0x0B, M680X_INS_TIM, imm8_hid, dir_hid },
+	{ 0x14, M680X_INS_SEXW, inh_hid, inh_hid },
+	{ 0x61, M680X_INS_OIM, imm8_hid, idx09_hid },
+	{ 0x62, M680X_INS_AIM, imm8_hid, idx09_hid },
+	{ 0x65, M680X_INS_EIM, imm8_hid, idx09_hid },
+	{ 0x6B, M680X_INS_TIM, imm8_hid, idx09_hid },
+	{ 0x71, M680X_INS_OIM, imm8_hid, ext_hid },
+	{ 0x72, M680X_INS_AIM, imm8_hid, ext_hid },
+	{ 0x75, M680X_INS_EIM, imm8_hid, ext_hid },
+	{ 0x7B, M680X_INS_TIM, imm8_hid, ext_hid },
+	{ 0xCD, M680X_INS_LDQ, imm32_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// HD6309 PAGE2 instructions (with prefix 0x10)
+static const inst_pageX g_hd6309_inst_page2_table[] = {
+	// 0x2x, relative long branch instructions
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	// 0x3x
+	{ 0x30, M680X_INS_ADDR, rr09_hid, inh_hid },
+	{ 0x31, M680X_INS_ADCR, rr09_hid, inh_hid },
+	{ 0x32, M680X_INS_SUBR, rr09_hid, inh_hid },
+	{ 0x33, M680X_INS_SBCR, rr09_hid, inh_hid },
+	{ 0x34, M680X_INS_ANDR, rr09_hid, inh_hid },
+	{ 0x35, M680X_INS_ORR, rr09_hid, inh_hid },
+	{ 0x36, M680X_INS_EORR, rr09_hid, inh_hid },
+	{ 0x37, M680X_INS_CMPR, rr09_hid, inh_hid },
+	{ 0x38, M680X_INS_PSHSW, inh_hid, inh_hid },
+	{ 0x39, M680X_INS_PULSW, inh_hid, inh_hid },
+	{ 0x3a, M680X_INS_PSHUW, inh_hid, inh_hid },
+	{ 0x3b, M680X_INS_PULUW, inh_hid, inh_hid },
+	{ 0x3f, M680X_INS_SWI2, inh_hid, inh_hid },
+	// 0x4x, Register D instructions
+	{ 0x40, M680X_INS_NEGD, inh_hid, inh_hid },
+	{ 0x43, M680X_INS_COMD, inh_hid, inh_hid },
+	{ 0x44, M680X_INS_LSRD, inh_hid, inh_hid },
+	{ 0x46, M680X_INS_RORD, inh_hid, inh_hid },
+	{ 0x47, M680X_INS_ASRD, inh_hid, inh_hid },
+	{ 0x48, M680X_INS_LSLD, inh_hid, inh_hid },
+	{ 0x49, M680X_INS_ROLD, inh_hid, inh_hid },
+	{ 0x4a, M680X_INS_DECD, inh_hid, inh_hid },
+	{ 0x4c, M680X_INS_INCD, inh_hid, inh_hid },
+	{ 0x4d, M680X_INS_TSTD, inh_hid, inh_hid },
+	{ 0x4f, M680X_INS_CLRD, inh_hid, inh_hid },
+	// 0x5x, Register W instructions
+	{ 0x53, M680X_INS_COMW, inh_hid, inh_hid },
+	{ 0x54, M680X_INS_LSRW, inh_hid, inh_hid },
+	{ 0x56, M680X_INS_RORW, inh_hid, inh_hid },
+	{ 0x59, M680X_INS_ROLW, inh_hid, inh_hid },
+	{ 0x5a, M680X_INS_DECW, inh_hid, inh_hid },
+	{ 0x5c, M680X_INS_INCW, inh_hid, inh_hid },
+	{ 0x5d, M680X_INS_TSTW, inh_hid, inh_hid },
+	{ 0x5f, M680X_INS_CLRW, inh_hid, inh_hid },
+	// 0x8x, immediate instructionY with register D,W,Y
+	{ 0x80, M680X_INS_SUBW, imm16_hid, inh_hid },
+	{ 0x81, M680X_INS_CMPW, imm16_hid, inh_hid },
+	{ 0x82, M680X_INS_SBCD, imm16_hid, inh_hid },
+	{ 0x83, M680X_INS_CMPD, imm16_hid, inh_hid },
+	{ 0x84, M680X_INS_ANDD, imm16_hid, inh_hid },
+	{ 0x85, M680X_INS_BITD, imm16_hid, inh_hid },
+	{ 0x86, M680X_INS_LDW, imm16_hid, inh_hid },
+	{ 0x88, M680X_INS_EORD, imm16_hid, inh_hid },
+	{ 0x89, M680X_INS_ADCD, imm16_hid, inh_hid },
+	{ 0x8a, M680X_INS_ORD, imm16_hid, inh_hid },
+	{ 0x8b, M680X_INS_ADDW, imm16_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid },
+	{ 0x8e, M680X_INS_LDY, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register D,W,Y
+	{ 0x90, M680X_INS_SUBW, dir_hid, inh_hid },
+	{ 0x91, M680X_INS_CMPW, dir_hid, inh_hid },
+	{ 0x92, M680X_INS_SBCD, dir_hid, inh_hid },
+	{ 0x93, M680X_INS_CMPD, dir_hid, inh_hid },
+	{ 0x94, M680X_INS_ANDD, dir_hid, inh_hid },
+	{ 0x95, M680X_INS_BITD, dir_hid, inh_hid },
+	{ 0x96, M680X_INS_LDW, dir_hid, inh_hid },
+	{ 0x97, M680X_INS_STW, dir_hid, inh_hid },
+	{ 0x98, M680X_INS_EORD, dir_hid, inh_hid },
+	{ 0x99, M680X_INS_ADCD, dir_hid, inh_hid },
+	{ 0x9a, M680X_INS_ORD, dir_hid, inh_hid },
+	{ 0x9b, M680X_INS_ADDW, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPY, dir_hid, inh_hid },
+	{ 0x9e, M680X_INS_LDY, dir_hid, inh_hid },
+	{ 0x9f, M680X_INS_STY, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register D,W,Y
+	{ 0xa0, M680X_INS_SUBW, idx09_hid, inh_hid },
+	{ 0xa1, M680X_INS_CMPW, idx09_hid, inh_hid },
+	{ 0xa2, M680X_INS_SBCD, idx09_hid, inh_hid },
+	{ 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid },
+	{ 0xa4, M680X_INS_ANDD, idx09_hid, inh_hid },
+	{ 0xa5, M680X_INS_BITD, idx09_hid, inh_hid },
+	{ 0xa6, M680X_INS_LDW, idx09_hid, inh_hid },
+	{ 0xa7, M680X_INS_STW, idx09_hid, inh_hid },
+	{ 0xa8, M680X_INS_EORD, idx09_hid, inh_hid },
+	{ 0xa9, M680X_INS_ADCD, idx09_hid, inh_hid },
+	{ 0xaa, M680X_INS_ORD, idx09_hid, inh_hid },
+	{ 0xab, M680X_INS_ADDW, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPY, idx09_hid, inh_hid },
+	{ 0xae, M680X_INS_LDY, idx09_hid, inh_hid },
+	{ 0xaf, M680X_INS_STY, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register D,W,Y
+	{ 0xb0, M680X_INS_SUBW, ext_hid, inh_hid },
+	{ 0xb1, M680X_INS_CMPW, ext_hid, inh_hid },
+	{ 0xb2, M680X_INS_SBCD, ext_hid, inh_hid },
+	{ 0xb3, M680X_INS_CMPD, ext_hid, inh_hid },
+	{ 0xb4, M680X_INS_ANDD, ext_hid, inh_hid },
+	{ 0xb5, M680X_INS_BITD, ext_hid, inh_hid },
+	{ 0xb6, M680X_INS_LDW, ext_hid, inh_hid },
+	{ 0xb7, M680X_INS_STW, ext_hid, inh_hid },
+	{ 0xb8, M680X_INS_EORD, ext_hid, inh_hid },
+	{ 0xb9, M680X_INS_ADCD, ext_hid, inh_hid },
+	{ 0xba, M680X_INS_ORD, ext_hid, inh_hid },
+	{ 0xbb, M680X_INS_ADDW, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPY, ext_hid, inh_hid },
+	{ 0xbe, M680X_INS_LDY, ext_hid, inh_hid },
+	{ 0xbf, M680X_INS_STY, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register S
+	{ 0xce, M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx, direct instructions with register S,Q
+	{ 0xdc, M680X_INS_LDQ, dir_hid, inh_hid },
+	{ 0xdd, M680X_INS_STQ, dir_hid, inh_hid },
+	{ 0xde, M680X_INS_LDS, dir_hid, inh_hid },
+	{ 0xdf, M680X_INS_STS, dir_hid, inh_hid },
+	// 0xEx, indexed instructions with register S,Q
+	{ 0xec, M680X_INS_LDQ, idx09_hid, inh_hid },
+	{ 0xed, M680X_INS_STQ, idx09_hid, inh_hid },
+	{ 0xee, M680X_INS_LDS, idx09_hid, inh_hid },
+	{ 0xef, M680X_INS_STS, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register S,Q
+	{ 0xfc, M680X_INS_LDQ, ext_hid, inh_hid },
+	{ 0xfd, M680X_INS_STQ, ext_hid, inh_hid },
+	{ 0xfe, M680X_INS_LDS, ext_hid, inh_hid },
+	{ 0xff, M680X_INS_STS, ext_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// HD6309 PAGE3 instructions (with prefix 0x11)
+static const inst_pageX g_hd6309_inst_page3_table[] = {
+	{ 0x30, M680X_INS_BAND, bitmv_hid, inh_hid },
+	{ 0x31, M680X_INS_BIAND, bitmv_hid, inh_hid },
+	{ 0x32, M680X_INS_BOR, bitmv_hid, inh_hid },
+	{ 0x33, M680X_INS_BIOR, bitmv_hid, inh_hid },
+	{ 0x34, M680X_INS_BEOR, bitmv_hid, inh_hid },
+	{ 0x35, M680X_INS_BIEOR, bitmv_hid, inh_hid },
+	{ 0x36, M680X_INS_LDBT, bitmv_hid, inh_hid },
+	{ 0x37, M680X_INS_STBT, bitmv_hid, inh_hid },
+	{ 0x38, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x39, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x3a, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x3b, M680X_INS_TFM, tfm_hid, inh_hid },
+	{ 0x3c, M680X_INS_BITMD, imm8_hid, inh_hid },
+	{ 0x3d, M680X_INS_LDMD, imm8_hid, inh_hid },
+	{ 0x3f, M680X_INS_SWI3, inh_hid, inh_hid },
+	// 0x4x, Register E instructions
+	{ 0x43, M680X_INS_COME, inh_hid, inh_hid },
+	{ 0x4a, M680X_INS_DECE, inh_hid, inh_hid },
+	{ 0x4c, M680X_INS_INCE, inh_hid, inh_hid },
+	{ 0x4d, M680X_INS_TSTE, inh_hid, inh_hid },
+	{ 0x4f, M680X_INS_CLRE, inh_hid, inh_hid },
+	// 0x5x, Register F instructions
+	{ 0x53, M680X_INS_COMF, inh_hid, inh_hid },
+	{ 0x5a, M680X_INS_DECF, inh_hid, inh_hid },
+	{ 0x5c, M680X_INS_INCF, inh_hid, inh_hid },
+	{ 0x5d, M680X_INS_TSTF, inh_hid, inh_hid },
+	{ 0x5f, M680X_INS_CLRF, inh_hid, inh_hid },
+	// 0x8x, immediate instructions with register U,S,E
+	{ 0x80, M680X_INS_SUBE, imm8_hid, inh_hid },
+	{ 0x81, M680X_INS_CMPE, imm8_hid, inh_hid },
+	{ 0x83, M680X_INS_CMPU, imm16_hid, inh_hid },
+	{ 0x86, M680X_INS_LDE, imm8_hid, inh_hid },
+	{ 0x8b, M680X_INS_ADDE, imm8_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid },
+	{ 0x8d, M680X_INS_DIVD, imm8_hid, inh_hid },
+	{ 0x8e, M680X_INS_DIVQ, imm16_hid, inh_hid },
+	{ 0x8f, M680X_INS_MULD, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register U,S,E,Q
+	{ 0x90, M680X_INS_SUBE, dir_hid, inh_hid },
+	{ 0x91, M680X_INS_CMPE, dir_hid, inh_hid },
+	{ 0x93, M680X_INS_CMPU, dir_hid, inh_hid },
+	{ 0x96, M680X_INS_LDE, dir_hid, inh_hid },
+	{ 0x97, M680X_INS_STE, dir_hid, inh_hid },
+	{ 0x9b, M680X_INS_ADDE, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPS, dir_hid, inh_hid },
+	{ 0x9d, M680X_INS_DIVD, dir_hid, inh_hid },
+	{ 0x9e, M680X_INS_DIVQ, dir_hid, inh_hid },
+	{ 0x9f, M680X_INS_MULD, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register U,S,D,Q
+	{ 0xa0, M680X_INS_SUBE, idx09_hid, inh_hid },
+	{ 0xa1, M680X_INS_CMPE, idx09_hid, inh_hid },
+	{ 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid },
+	{ 0xa6, M680X_INS_LDE, idx09_hid, inh_hid },
+	{ 0xa7, M680X_INS_STE, idx09_hid, inh_hid },
+	{ 0xab, M680X_INS_ADDE, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPS, idx09_hid, inh_hid },
+	{ 0xad, M680X_INS_DIVD, idx09_hid, inh_hid },
+	{ 0xae, M680X_INS_DIVQ, idx09_hid, inh_hid },
+	{ 0xaf, M680X_INS_MULD, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register U,S,D,Q
+	{ 0xb0, M680X_INS_SUBE, ext_hid, inh_hid },
+	{ 0xb1, M680X_INS_CMPE, ext_hid, inh_hid },
+	{ 0xb3, M680X_INS_CMPU, ext_hid, inh_hid },
+	{ 0xb6, M680X_INS_LDE, ext_hid, inh_hid },
+	{ 0xb7, M680X_INS_STE, ext_hid, inh_hid },
+	{ 0xbb, M680X_INS_ADDE, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPS, ext_hid, inh_hid },
+	{ 0xbd, M680X_INS_DIVD, ext_hid, inh_hid },
+	{ 0xbe, M680X_INS_DIVQ, ext_hid, inh_hid },
+	{ 0xbf, M680X_INS_MULD, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register F
+	{ 0xc0, M680X_INS_SUBF, imm8_hid, inh_hid },
+	{ 0xc1, M680X_INS_CMPF, imm8_hid, inh_hid },
+	{ 0xc6, M680X_INS_LDF, imm8_hid, inh_hid },
+	{ 0xcb, M680X_INS_ADDF, imm8_hid, inh_hid },
+	// 0xDx, direct instructions with register F
+	{ 0xd0, M680X_INS_SUBF, dir_hid, inh_hid },
+	{ 0xd1, M680X_INS_CMPF, dir_hid, inh_hid },
+	{ 0xd6, M680X_INS_LDF, dir_hid, inh_hid },
+	{ 0xd7, M680X_INS_STF, dir_hid, inh_hid },
+	{ 0xdb, M680X_INS_ADDF, dir_hid, inh_hid },
+	// 0xEx, indexed instructions with register F
+	{ 0xe0, M680X_INS_SUBF, idx09_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMPF, idx09_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDF, idx09_hid, inh_hid },
+	{ 0xe7, M680X_INS_STF, idx09_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADDF, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register F
+	{ 0xf0, M680X_INS_SUBF, ext_hid, inh_hid },
+	{ 0xf1, M680X_INS_CMPF, ext_hid, inh_hid },
+	{ 0xf6, M680X_INS_LDF, ext_hid, inh_hid },
+	{ 0xf7, M680X_INS_STF, ext_hid, inh_hid },
+	{ 0xfb, M680X_INS_ADDF, ext_hid, inh_hid },
+};
+
--- a/arch/M680X/insn_props.inc
+++ b/arch/M680X/insn_props.inc
@ -0,0 +1,367 @@
+
+// These temporary defines keep the following table short and handy.
+#define NOG M680X_GRP_INVALID
+#define NOR M680X_REG_INVALID
+
+static const insn_props g_insn_props[] = {
+	{ NOG, uuuu, NOR, NOR, false, false }, // INVLD
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // ABA
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_X, false, false }, // ABX
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_Y, false, false }, // ABY
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADCA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADCB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADCD
+	{ NOG, rmmm, NOR, NOR, true, false }, // ADCR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADD
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADDA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADDB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADDD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // ADDE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // ADDF
+	{ NOG, rmmm, NOR, NOR, true, false }, // ADDR
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // ADDW
+	{ NOG, rmmm, NOR, NOR, true, false }, // AIM
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // AIS
+	{ NOG, mrrr, M680X_REG_HX, NOR, false, false }, // AIX
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // AND
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ANDA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ANDB
+	{ NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ANDCC
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ANDD
+	{ NOG, rmmm, NOR, NOR, true, false }, // ANDR
+	{ NOG, mrrr, NOR, NOR, true, false }, // ASL
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASLA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASLB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASLD
+	{ NOG, mrrr, NOR, NOR, true, false }, // ASR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ASRA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ASRB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ASRD
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // ASRX
+	{ NOG, mrrr, NOR, NOR, false, false }, // BAND
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCC
+	{ NOG, mrrr, NOR, NOR, true, false }, // BCLR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BCS
+	{ NOG, mrrr, NOR, NOR, false, false }, // BEOR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BEQ
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGE
+	{ NOG, uuuu, NOR, NOR, false, false }, // BGND
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BGT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHCS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BHI
+	{ NOG, mrrr, NOR, NOR, false, false }, // BIAND
+	{ NOG, mrrr, NOR, NOR, false, false }, // BIEOR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIH
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BIL
+	{ NOG, mrrr, NOR, NOR, false, false }, // BIOR
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // BIT
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // BITA
+	{ NOG, rrrr, M680X_REG_B, NOR, true, false }, // BITB
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // BITD
+	{ NOG, rrrr, M680X_REG_MD, NOR, true, false }, // BITMD
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BLT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMI
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BMS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BNE
+	{ NOG, mrrr, NOR, NOR, false, false }, // BOR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BPL
+	{ M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRCLR
+	{ M680X_GRP_JUMP, rruu, NOR, NOR, false, false }, // BRSET
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRA
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BRN never branches
+	{ NOG, mrrr, NOR, NOR, true, false }, // BSET
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // BSR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // BVS
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // CALL
+	{ NOG, rrrr, M680X_REG_B, M680X_REG_A, true, false }, // CBA
+	{ M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQ
+	{ M680X_GRP_JUMP, rruu, M680X_REG_A, NOR, false, false }, // CBEQA
+	{ M680X_GRP_JUMP, rruu, M680X_REG_X, NOR, false, false }, // CBEQX
+	{ NOG, uuuu, NOR, NOR, true, false }, // CLC
+	{ NOG, uuuu, NOR, NOR, true, false }, // CLI
+	{ NOG, wrrr, NOR, NOR, true, false }, // CLR
+	{ NOG, wrrr, M680X_REG_A, NOR, true, false }, // CLRA
+	{ NOG, wrrr, M680X_REG_B, NOR, true, false }, // CLRB
+	{ NOG, wrrr, M680X_REG_D, NOR, true, false }, // CLRD
+	{ NOG, wrrr, M680X_REG_E, NOR, true, false }, // CLRE
+	{ NOG, wrrr, M680X_REG_F, NOR, true, false }, // CLRF
+	{ NOG, wrrr, M680X_REG_H, NOR, true, false }, // CLRH
+	{ NOG, wrrr, M680X_REG_W, NOR, true, false }, // CLRW
+	{ NOG, wrrr, M680X_REG_X, NOR, true, false }, // CLRX
+	{ NOG, uuuu, NOR, NOR, true, false }, // CLV
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMP
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // CMPA
+	{ NOG, rrrr, M680X_REG_B, NOR, true, false }, // CMPB
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // CMPD
+	{ NOG, rrrr, M680X_REG_E, NOR, true, false }, // CMPE
+	{ NOG, rrrr, M680X_REG_F, NOR, true, false }, // CMPF
+	{ NOG, rrrr, NOR, NOR, true, false }, // CMPR
+	{ NOG, rrrr, M680X_REG_S, NOR, true, false }, // CMPS
+	{ NOG, rrrr, M680X_REG_U, NOR, true, false }, // CMPU
+	{ NOG, rrrr, M680X_REG_W, NOR, true, false }, // CMPW
+	{ NOG, rrrr, M680X_REG_X, NOR, true, false }, // CMPX
+	{ NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CMPY
+	{ NOG, mrrr, NOR, NOR, true, false }, // COM
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // COMA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // COMB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // COMD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // COME
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // COMF
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // COMW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // COMX
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // CPD
+	{ NOG, rrrr, M680X_REG_HX, NOR, true, false }, // CPHX
+	{ NOG, rrrr, M680X_REG_S, NOR, true, false }, // CPS
+	{ NOG, rrrr, M680X_REG_X, NOR, true, false }, // CPX
+	{ NOG, rrrr, M680X_REG_Y, NOR, true, false }, // CPY
+	{ NOG, mrrr, NOR, NOR, true, true }, // CWAI
+	{ NOG, mrrr, NOR, NOR, true, true }, // DAA
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBEQ
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNE
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // DBNZ
+	{ M680X_GRP_JUMP, muuu, M680X_REG_A, NOR, false, false }, // DBNZA
+	{ M680X_GRP_JUMP, muuu, M680X_REG_X, NOR, false, false }, // DBNZX
+	{ NOG, mrrr, NOR, NOR, true, false }, // DEC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // DECA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // DECB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // DECD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // DECE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // DECF
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // DECW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // DECX
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // DES
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // DEX
+	{ NOG, mrrr, M680X_REG_Y, NOR, true, false }, // DEY
+	{ NOG, mmrr, NOR, NOR, true, true }, // DIV
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // DIVD
+	{ NOG, mrrr, M680X_REG_Q, NOR, true, false }, // DIVQ
+	{ NOG, mmrr, NOR, NOR, true, true }, // EDIV
+	{ NOG, mmrr, NOR, NOR, true, true }, // EDIVS
+	{ NOG, rmmm, NOR, NOR, true, false }, // EIM
+	{ NOG, mrrr, NOR, NOR, true, true }, // EMACS
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMAXD
+	{ NOG, mrrr, NOR, NOR, true, true }, // EMAXM
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // EMIND
+	{ NOG, mrrr, NOR, NOR, true, true }, // EMINM
+	{ NOG, mmrr, NOR, NOR, true, true }, // EMUL
+	{ NOG, mmrr, NOR, NOR, true, true }, // EMULS
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // EOR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // EORA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // EORB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // EORD
+	{ NOG, rmmm, NOR, NOR, true, false }, // EORR
+	{ NOG, rmmm, NOR, NOR, true, true }, // ETBL
+	{ NOG, mmmm, NOR, NOR, false, false }, // EXG
+	{ NOG, mmmm, NOR, NOR, true, true }, // FDIV
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBEQ
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // IBNE
+	{ NOG, mmmm, NOR, NOR, true, true }, // IDIV
+	{ NOG, mmmm, NOR, NOR, true, true }, // IDIVS
+	{ NOG, uuuu, NOR, NOR, false, false }, // ILLGL
+	{ NOG, mrrr, NOR, NOR, true, false }, // INC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // INCA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // INCB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // INCD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // INCE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // INCF
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // INCW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // INCX
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // INS
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // INX
+	{ NOG, mrrr, M680X_REG_Y, NOR, true, false }, // INY
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // JMP
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // JSR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBCS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBEQ
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBGT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBHI
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLS
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBLT
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBMI
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBNE
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBPL
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRA
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBRN never branches
+	{ M680X_GRP_CALL, uuuu, NOR, NOR, false, true }, // LBSR
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVC
+	{ M680X_GRP_JUMP, uuuu, NOR, NOR, false, false }, // LBVS
+	{ NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDA
+	{ NOG, wrrr, M680X_REG_A, NOR, true, false }, // LDAA
+	{ NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDAB
+	{ NOG, wrrr, M680X_REG_B, NOR, true, false }, // LDB
+	{ NOG, mrrr, NOR, NOR, false, false }, // LDBT
+	{ NOG, wrrr, M680X_REG_D, NOR, true, false }, // LDD
+	{ NOG, wrrr, M680X_REG_E, NOR, true, false }, // LDE
+	{ NOG, wrrr, M680X_REG_F, NOR, true, false }, // LDF
+	{ NOG, wrrr, M680X_REG_HX, NOR, true, false }, // LDHX
+	{ NOG, mrrr, M680X_REG_MD, NOR, false, false }, // LDMD
+	{ NOG, wrrr, M680X_REG_Q, NOR, true, false }, // LDQ
+	{ NOG, wrrr, M680X_REG_S, NOR, true, false }, // LDS
+	{ NOG, wrrr, M680X_REG_U, NOR, true, false }, // LDU
+	{ NOG, wrrr, M680X_REG_W, NOR, true, false }, // LDW
+	{ NOG, wrrr, M680X_REG_X, NOR, true, false }, // LDX
+	{ NOG, wrrr, M680X_REG_Y, NOR, true, false }, // LDY
+	{ NOG, wrrr, M680X_REG_S, NOR, false, false }, // LEAS
+	{ NOG, wrrr, M680X_REG_U, NOR, false, false }, // LEAU
+	{ NOG, wrrr, M680X_REG_X, NOR, false, false }, // LEAX
+	{ NOG, wrrr, M680X_REG_Y, NOR, false, false }, // LEAY
+	{ NOG, mrrr, NOR, NOR, true, false }, // LSL
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSLA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSLB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSLD
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSLX
+	{ NOG, mrrr, NOR, NOR, true, false }, // LSR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // LSRA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // LSRB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // LSRD
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // LSRW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // LSRX
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // MAXA
+	{ NOG, mrrr, NOR, NOR, true, true }, // MAXM
+	{ NOG, mmrr, NOR, NOR, true, true }, // MEM
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // MINA
+	{ NOG, mrrr, NOR, NOR, true, true }, // MINM
+	{ NOG, rwww, NOR, NOR, true, false }, // MOV
+	{ NOG, rwww, NOR, NOR, false, false }, // MOVB
+	{ NOG, rwww, NOR, NOR, false, false }, // MOVW
+	{ NOG, mmmm, NOR, NOR, true, true }, // MUL
+	{ NOG, mwrr, M680X_REG_D, NOR, true, true }, // MULD
+	{ NOG, mrrr, NOR, NOR, true, false }, // NEG
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // NEGA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // NEGB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // NEGD
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // NEGX
+	{ NOG, uuuu, NOR, NOR, false, false }, // NOP
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // NSA
+	{ NOG, rmmm, NOR, NOR, true, false }, // OIM
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORA
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ORAA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORAB
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ORB
+	{ NOG, mrrr, M680X_REG_CC, NOR, true, false }, // ORCC
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ORD
+	{ NOG, rmmm, NOR, NOR, true, false }, // ORR
+	{ NOG, rmmm, M680X_REG_A, NOR, false, true }, // PSHA
+	{ NOG, rmmm, M680X_REG_B, NOR, false, true }, // PSHB
+	{ NOG, rmmm, M680X_REG_CC, NOR, false, true }, // PSHC
+	{ NOG, rmmm, M680X_REG_D, NOR, false, true }, // PSHD
+	{ NOG, rmmm, M680X_REG_H, NOR, false, true }, // PSHH
+	{ NOG, mrrr, M680X_REG_S, NOR, false, false }, // PSHS
+	{ NOG, mrrr, M680X_REG_S, M680X_REG_W, false, false }, // PSHSW
+	{ NOG, mrrr, M680X_REG_U, NOR, false, false }, // PSHU
+	{ NOG, mrrr, M680X_REG_U, M680X_REG_W, false, false }, // PSHUW
+	{ NOG, rmmm, M680X_REG_X, NOR, false, true }, // PSHX
+	{ NOG, rmmm, M680X_REG_Y, NOR, false, true }, // PSHY
+	{ NOG, wmmm, M680X_REG_A, NOR, false, true }, // PULA
+	{ NOG, wmmm, M680X_REG_B, NOR, false, true }, // PULB
+	{ NOG, wmmm, M680X_REG_CC, NOR, false, true }, // PULC
+	{ NOG, wmmm, M680X_REG_D, NOR, false, true }, // PULD
+	{ NOG, wmmm, M680X_REG_H, NOR, false, true }, // PULH
+	{ NOG, mwww, M680X_REG_S, NOR, false, false }, // PULS
+	{ NOG, mwww, M680X_REG_S, M680X_REG_W, false, false }, // PULSW
+	{ NOG, mwww, M680X_REG_U, NOR, false, false }, // PULU
+	{ NOG, mwww, M680X_REG_U, M680X_REG_W, false, false }, // PULUW
+	{ NOG, wmmm, M680X_REG_X, NOR, false, true }, // PULX
+	{ NOG, wmmm, M680X_REG_Y, NOR, false, true }, // PULY
+	{ NOG, mmrr, NOR, NOR, true, true }, // REV
+	{ NOG, mmmm, NOR, NOR, true, true }, // REVW
+	{ NOG, mrrr, NOR, NOR, true, false }, // ROL
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // ROLA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // ROLB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // ROLD
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // ROLW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // ROLX
+	{ NOG, mrrr, NOR, NOR, true, false }, // ROR
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // RORA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // RORB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // RORD
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // RORW
+	{ NOG, mrrr, M680X_REG_X, NOR, true, false }, // RORX
+	{ NOG, wrrr, M680X_REG_S, NOR, false, false }, // RSP
+	{ M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTC
+	{ M680X_GRP_IRET, mwww, NOR, NOR, false, true }, // RTI
+	{ M680X_GRP_RET, mwww, NOR, NOR, false, true }, // RTS
+	{ NOG, rmmm, M680X_REG_B, M680X_REG_A, true, false }, // SBA
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBC
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SBCA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // SBCB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // SBCD
+	{ NOG, rmmm, NOR, NOR, true, false }, // SBCR
+	{ NOG, uuuu, NOR, NOR, true, false }, // SEC
+	{ NOG, uuuu, NOR, NOR, true, false }, // SEI
+	{ NOG, uuuu, NOR, NOR, true, false }, // SEV
+	{ NOG, wrrr, NOR, NOR, true, true }, // SEX
+	{ NOG, rwww, M680X_REG_W, NOR, true, true }, // SEXW
+	{ NOG, uuuu, NOR, NOR, false, false }, // SLP
+	{ NOG, rwww, M680X_REG_A, NOR, true, false }, // STA
+	{ NOG, rwww, M680X_REG_A, NOR, true, false }, // STAA
+	{ NOG, rwww, M680X_REG_B, NOR, true, false }, // STAB
+	{ NOG, rwww, M680X_REG_B, NOR, true, false }, // STB
+	{ NOG, rrrm, NOR, NOR, false, false }, // STBT
+	{ NOG, rwww, M680X_REG_D, NOR, true, false }, // STD
+	{ NOG, rwww, M680X_REG_E, NOR, true, false }, // STE
+	{ NOG, rwww, M680X_REG_F, NOR, true, false }, // STF
+	{ NOG, uuuu, NOR, NOR, false, false }, // STOP
+	{ NOG, rwww, M680X_REG_HX, NOR, true, false }, // STHX
+	{ NOG, rwww, M680X_REG_Q, NOR, true, false }, // STQ
+	{ NOG, rwww, M680X_REG_S, NOR, true, false }, // STS
+	{ NOG, rwww, M680X_REG_U, NOR, true, false }, // STU
+	{ NOG, rwww, M680X_REG_W, NOR, true, false }, // STW
+	{ NOG, rwww, M680X_REG_X, NOR, true, false }, // STX
+	{ NOG, rwww, M680X_REG_Y, NOR, true, false }, // STY
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUB
+	{ NOG, mrrr, M680X_REG_A, NOR, true, false }, // SUBA
+	{ NOG, mrrr, M680X_REG_B, NOR, true, false }, // SUBB
+	{ NOG, mrrr, M680X_REG_D, NOR, true, false }, // SUBD
+	{ NOG, mrrr, M680X_REG_E, NOR, true, false }, // SUBE
+	{ NOG, mrrr, M680X_REG_F, NOR, true, false }, // SUBF
+	{ NOG, rmmm, NOR, NOR, true, false }, // SUBR
+	{ NOG, mrrr, M680X_REG_W, NOR, true, false }, // SUBW
+	{ M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI
+	{ M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI2
+	{ M680X_GRP_INT, mmrr, NOR, NOR, true, true }, // SWI3
+	{ NOG, uuuu, NOR, NOR, false, false }, // SYNC
+	{ NOG, rwww, M680X_REG_A, M680X_REG_B, true, false }, // TAB
+	{ NOG, rwww, M680X_REG_A, M680X_REG_CC, false, false }, // TAP
+	{ NOG, rwww, M680X_REG_A, M680X_REG_X, false, false }, // TAX
+	{ NOG, rwww, M680X_REG_B, M680X_REG_A, true, false }, // TBA
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBEQ
+	{ NOG, rmmm, NOR, NOR, true, true }, // TBL
+	{ M680X_GRP_JUMP, muuu, NOR, NOR, false, false }, // TBNE
+	{ NOG, uuuu, NOR, NOR, false, false }, // TEST
+	{ NOG, rwww, NOR, NOR, false, false }, // TFM
+	{ NOG, rwww, NOR, NOR, false, false }, // TFR
+	{ NOG, rrrr, NOR, NOR, true, false }, // TIM
+	{ NOG, rwww, M680X_REG_CC, M680X_REG_A, false, false }, // TPA
+	{ NOG, rrrr, NOR, NOR, true, false }, // TST
+	{ NOG, rrrr, M680X_REG_A, NOR, true, false }, // TSTA
+	{ NOG, rrrr, M680X_REG_B, NOR, true, false }, // TSTB
+	{ NOG, rrrr, M680X_REG_D, NOR, true, false }, // TSTD
+	{ NOG, rrrr, M680X_REG_E, NOR, true, false }, // TSTE
+	{ NOG, rrrr, M680X_REG_F, NOR, true, false }, // TSTF
+	{ NOG, rrrr, M680X_REG_W, NOR, true, false }, // TSTW
+	{ NOG, rrrr, M680X_REG_X, NOR, true, false }, // TSTX
+	{ NOG, rwww, M680X_REG_S, M680X_REG_HX, false, false }, // TSX
+	{ NOG, rwww, M680X_REG_S, M680X_REG_Y, false, false }, // TSY
+	{ NOG, rwww, M680X_REG_X, M680X_REG_A, false, false }, // TXA
+	{ NOG, rwww, M680X_REG_HX, M680X_REG_S, false, false }, // TXS
+	{ NOG, rwww, M680X_REG_Y, M680X_REG_S, false, false }, // TYS
+	{ NOG, mrrr, NOR, NOR, true, true }, // WAI
+	{ NOG, uuuu, NOR, NOR, true, false }, // WAIT
+	{ NOG, uuuu, NOR, NOR, true, true }, // WAV
+	{ NOG, uuuu, NOR, NOR, true, true }, // WAVR
+	{ NOG, mmmm, M680X_REG_D, M680X_REG_X, false, false }, // XGDX
+	{ NOG, mmmm, M680X_REG_D, M680X_REG_Y, false, false }, // XGDY
+};
+#undef NOR
+#undef NOG
+
--- a/arch/M680X/m6800.inc
+++ b/arch/M680X/m6800.inc
@ -0,0 +1,277 @@
+
+// M6800/2 instructions
+static const inst_page1 g_m6800_inst_page1_table[256] = {
+	// 0x0x, inherent instructions
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TAP, inh_hid, inh_hid },
+	{ M680X_INS_TPA, inh_hid, inh_hid },
+	{ M680X_INS_INX, inh_hid, inh_hid },
+	{ M680X_INS_DEX, inh_hid, inh_hid },
+	{ M680X_INS_CLV, inh_hid, inh_hid },
+	{ M680X_INS_SEV, inh_hid, inh_hid },
+	{ M680X_INS_CLC, inh_hid, inh_hid },
+	{ M680X_INS_SEC, inh_hid, inh_hid },
+	{ M680X_INS_CLI, inh_hid, inh_hid },
+	{ M680X_INS_SEI, inh_hid, inh_hid },
+	// 0x1x, inherent instructions
+	{ M680X_INS_SBA, inh_hid, inh_hid },
+	{ M680X_INS_CBA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TAB, inh_hid, inh_hid },
+	{ M680X_INS_TBA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_DAA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ABA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x, inherent instructions
+	{ M680X_INS_TSX, inh_hid, inh_hid },
+	{ M680X_INS_INS, inh_hid, inh_hid },
+	{ M680X_INS_PULA, inh_hid, inh_hid },
+	{ M680X_INS_PULB, inh_hid, inh_hid },
+	{ M680X_INS_DES, inh_hid, inh_hid },
+	{ M680X_INS_TXS, inh_hid, inh_hid },
+	{ M680X_INS_PSHA, inh_hid, inh_hid },
+	{ M680X_INS_PSHB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_WAI, inh_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x, Register A instructions
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_ASLA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	// 0x5x, Register B instructions
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_ASLB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	// 0x6x, indexed instructions
+	{ M680X_INS_NEG, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idxX_hid, inh_hid },
+	{ M680X_INS_LSR, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idxX_hid, inh_hid },
+	{ M680X_INS_ASR, idxX_hid, inh_hid },
+	{ M680X_INS_ASL, idxX_hid, inh_hid },
+	{ M680X_INS_ROL, idxX_hid, inh_hid },
+	{ M680X_INS_DEC, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idxX_hid, inh_hid },
+	{ M680X_INS_TST, idxX_hid, inh_hid },
+	{ M680X_INS_JMP, idxX_hid, inh_hid },
+	{ M680X_INS_CLR, idxX_hid, inh_hid },
+	// 0x7x, extended instructions
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_ASL, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	// 0x8x, immediate instructions with Register A,X,S
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDAA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORAA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CPX, imm16_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_LDS, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0x9x, direct instructions with register A,X,S
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDAA, dir_hid, inh_hid },
+	{ M680X_INS_STAA, dir_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORAA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDS, dir_hid, inh_hid },
+	{ M680X_INS_STS, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with Register A,X
+	{ M680X_INS_SUBA, idxX_hid, inh_hid },
+	{ M680X_INS_CMPA, idxX_hid, inh_hid },
+	{ M680X_INS_SBCA, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, idxX_hid, inh_hid },
+	{ M680X_INS_BITA, idxX_hid, inh_hid },
+	{ M680X_INS_LDAA, idxX_hid, inh_hid },
+	{ M680X_INS_STAA, idxX_hid, inh_hid },
+	{ M680X_INS_EORA, idxX_hid, inh_hid },
+	{ M680X_INS_ADCA, idxX_hid, inh_hid },
+	{ M680X_INS_ORAA, idxX_hid, inh_hid },
+	{ M680X_INS_ADDA, idxX_hid, inh_hid },
+	{ M680X_INS_CPX, idxX_hid, inh_hid },
+	{ M680X_INS_JSR, idxX_hid, inh_hid },
+	{ M680X_INS_LDS, idxX_hid, inh_hid },
+	{ M680X_INS_STS, idxX_hid, inh_hid },
+	// 0xBx, extended instructions with register A,X,S
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDAA, ext_hid, inh_hid },
+	{ M680X_INS_STAA, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORAA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_LDS, ext_hid, inh_hid },
+	{ M680X_INS_STS, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register B,X
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDAB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORAB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0xDx direct instructions with register B,X
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDAB, dir_hid, inh_hid },
+	{ M680X_INS_STAB, dir_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORAB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	// 0xEx, indexed instruction with register B,X
+	{ M680X_INS_SUBB, idxX_hid, inh_hid },
+	{ M680X_INS_CMPB, idxX_hid, inh_hid },
+	{ M680X_INS_SBCB, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, idxX_hid, inh_hid },
+	{ M680X_INS_BITB, idxX_hid, inh_hid },
+	{ M680X_INS_LDAB, idxX_hid, inh_hid },
+	{ M680X_INS_STAB, idxX_hid, inh_hid },
+	{ M680X_INS_EORB, idxX_hid, inh_hid },
+	{ M680X_INS_ADCB, idxX_hid, inh_hid },
+	{ M680X_INS_ORAB, idxX_hid, inh_hid },
+	{ M680X_INS_ADDB, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, idxX_hid, inh_hid },
+	{ M680X_INS_STX, idxX_hid, inh_hid },
+	// 0xFx, extended instructions with register B,U
+	{ M680X_INS_SUBB, ext_hid, inh_hid },
+	{ M680X_INS_CMPB, ext_hid, inh_hid },
+	{ M680X_INS_SBCB, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDB, ext_hid, inh_hid },
+	{ M680X_INS_BITB, ext_hid, inh_hid },
+	{ M680X_INS_LDAB, ext_hid, inh_hid },
+	{ M680X_INS_STAB, ext_hid, inh_hid },
+	{ M680X_INS_EORB, ext_hid, inh_hid },
+	{ M680X_INS_ADCB, ext_hid, inh_hid },
+	{ M680X_INS_ORAB, ext_hid, inh_hid },
+	{ M680X_INS_ADDB, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+};
+
--- a/arch/M680X/m6801.inc
+++ b/arch/M680X/m6801.inc
@ -0,0 +1,39 @@
+
+// Additional instructions only supported on M6801/3
+static const inst_pageX g_m6801_inst_overlay_table[] = {
+	// 0x0x, inherent instructions
+	{ 0x04, M680X_INS_LSRD, inh_hid, inh_hid },
+	{ 0x05, M680X_INS_ASLD, inh_hid, inh_hid },
+	// 0x2x, relative branch instructions
+	{ 0x21, M680X_INS_BRN, rel8_hid, inh_hid },
+	// 0x3x, inherent instructions
+	{ 0x38, M680X_INS_PULX, inh_hid, inh_hid },
+	{ 0x3A, M680X_INS_ABX, inh_hid, inh_hid },
+	{ 0x3C, M680X_INS_PSHX, inh_hid, inh_hid },
+	{ 0x3D, M680X_INS_MUL, inh_hid, inh_hid  },
+	// 0x8x, immediate instructions with Register D
+	{ 0x83, M680X_INS_SUBD, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register D
+	{ 0x93, M680X_INS_SUBD, dir_hid, inh_hid },
+	{ 0x9D, M680X_INS_JSR, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with Register D
+	{ 0xA3, M680X_INS_SUBD, idxX_hid, inh_hid },
+	// 0xBx, extended instructions with register D
+	{ 0xB3, M680X_INS_SUBD, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register D
+	{ 0xC3, M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ 0xCC, M680X_INS_LDD, imm16_hid, inh_hid },
+	// 0xDx direct instructions with register D
+	{ 0xD3, M680X_INS_ADDD, dir_hid, inh_hid },
+	{ 0xDC, M680X_INS_LDD, dir_hid, inh_hid },
+	{ 0xDD, M680X_INS_STD, dir_hid, inh_hid },
+	// 0xEx, indexed instruction with register D
+	{ 0xE3, M680X_INS_ADDD, idxX_hid, inh_hid },
+	{ 0xEC, M680X_INS_LDD, idxX_hid, inh_hid },
+	{ 0xED, M680X_INS_STD, idxX_hid, inh_hid },
+	// 0xFx, extended instructions with register D
+	{ 0xF3, M680X_INS_ADDD, ext_hid, inh_hid },
+	{ 0xFC, M680X_INS_LDD, ext_hid, inh_hid },
+	{ 0xFD, M680X_INS_STD, ext_hid, inh_hid },
+};
+
--- a/arch/M680X/m6805.inc
+++ b/arch/M680X/m6805.inc
@ -0,0 +1,277 @@
+
+// M68HC05 instructions
+static const inst_page1 g_m6805_inst_page1_table[256] = {
+	// 0x0x, bit manipulation instructions
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRSET, opidxdr_hid, inh_hid },
+	{ M680X_INS_BRCLR, opidxdr_hid, inh_hid },
+	// 0x1x, bit set/clear instructions
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	{ M680X_INS_BCLR, opidx_hid, dir_hid },
+	{ M680X_INS_BSET, opidx_hid, dir_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BHCC, rel8_hid, inh_hid },
+	{ M680X_INS_BHCS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BMC, rel8_hid, inh_hid },
+	{ M680X_INS_BMS, rel8_hid, inh_hid },
+	{ M680X_INS_BIL, rel8_hid, inh_hid },
+	{ M680X_INS_BIH, rel8_hid, inh_hid },
+	// 0x3x, direct instructions
+	{ M680X_INS_NEG, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, dir_hid, inh_hid },
+	{ M680X_INS_LSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, dir_hid, inh_hid },
+	{ M680X_INS_ASR, dir_hid, inh_hid },
+	{ M680X_INS_LSL, dir_hid, inh_hid },
+	{ M680X_INS_ROL, dir_hid, inh_hid },
+	{ M680X_INS_DEC, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, dir_hid, inh_hid },
+	{ M680X_INS_TST, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLR, dir_hid, inh_hid },
+	// 0x4x, inherent instructions
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_LSLA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	// 0x5x, inherent instructions
+	{ M680X_INS_NEGX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMX, inh_hid, inh_hid },
+	{ M680X_INS_LSRX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORX, inh_hid, inh_hid },
+	{ M680X_INS_ASRX, inh_hid, inh_hid },
+	{ M680X_INS_LSLX, inh_hid, inh_hid },
+	{ M680X_INS_ROLX, inh_hid, inh_hid },
+	{ M680X_INS_DECX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCX, inh_hid, inh_hid },
+	{ M680X_INS_TSTX, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRX, inh_hid, inh_hid },
+	// 0x6x, indexed, 1 byte offset instructions
+	{ M680X_INS_NEG, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idxX_hid, inh_hid },
+	{ M680X_INS_LSR, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idxX_hid, inh_hid },
+	{ M680X_INS_ASR, idxX_hid, inh_hid },
+	{ M680X_INS_LSL, idxX_hid, inh_hid },
+	{ M680X_INS_ROL, idxX_hid, inh_hid },
+	{ M680X_INS_DEC, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idxX_hid, inh_hid },
+	{ M680X_INS_TST, idxX_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLR, idxX_hid, inh_hid },
+	// 0x7x, indexed, no offset instructions
+	{ M680X_INS_NEG, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idxX0_hid, inh_hid },
+	{ M680X_INS_LSR, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idxX0_hid, inh_hid },
+	{ M680X_INS_ASR, idxX0_hid, inh_hid },
+	{ M680X_INS_LSL, idxX0_hid, inh_hid },
+	{ M680X_INS_ROL, idxX0_hid, inh_hid },
+	{ M680X_INS_DEC, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idxX0_hid, inh_hid },
+	{ M680X_INS_TST, idxX0_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLR, idxX0_hid, inh_hid },
+	// 0x8x, inherent instructions
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_STOP, inh_hid, inh_hid },
+	{ M680X_INS_WAIT, inh_hid, inh_hid },
+	// 0x9x, inherent instructions
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TAX, inh_hid, inh_hid },
+	{ M680X_INS_CLC, inh_hid, inh_hid },
+	{ M680X_INS_SEC, inh_hid, inh_hid },
+	{ M680X_INS_CLI, inh_hid, inh_hid },
+	{ M680X_INS_SEI, inh_hid, inh_hid },
+	{ M680X_INS_RSP, inh_hid, inh_hid },
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_TXA, inh_hid, inh_hid },
+	// 0xAx, immediate instructions with reg. A
+	{ M680X_INS_SUB, imm8_hid, inh_hid },
+	{ M680X_INS_CMP, imm8_hid, inh_hid },
+	{ M680X_INS_SBC, imm8_hid, inh_hid },
+	{ M680X_INS_CPX, imm8_hid, inh_hid },
+	{ M680X_INS_AND, imm8_hid, inh_hid },
+	{ M680X_INS_BIT, imm8_hid, inh_hid },
+	{ M680X_INS_LDA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EOR, imm8_hid, inh_hid },
+	{ M680X_INS_ADC, imm8_hid, inh_hid },
+	{ M680X_INS_ORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADD, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_LDX, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0xBx, direct instructions with reg. A
+	{ M680X_INS_SUB, dir_hid, inh_hid },
+	{ M680X_INS_CMP, dir_hid, inh_hid },
+	{ M680X_INS_SBC, dir_hid, inh_hid },
+	{ M680X_INS_CPX, dir_hid, inh_hid },
+	{ M680X_INS_AND, dir_hid, inh_hid },
+	{ M680X_INS_BIT, dir_hid, inh_hid },
+	{ M680X_INS_LDA, dir_hid, inh_hid },
+	{ M680X_INS_STA, dir_hid, inh_hid },
+	{ M680X_INS_EOR, dir_hid, inh_hid },
+	{ M680X_INS_ADC, dir_hid, inh_hid },
+	{ M680X_INS_ORA, dir_hid, inh_hid },
+	{ M680X_INS_ADD, dir_hid, inh_hid },
+	{ M680X_INS_JMP, dir_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	// 0xCx, extended instructions with reg. A
+	{ M680X_INS_SUB, ext_hid, inh_hid },
+	{ M680X_INS_CMP, ext_hid, inh_hid },
+	{ M680X_INS_SBC, ext_hid, inh_hid },
+	{ M680X_INS_CPX, ext_hid, inh_hid },
+	{ M680X_INS_AND, ext_hid, inh_hid },
+	{ M680X_INS_BIT, ext_hid, inh_hid },
+	{ M680X_INS_LDA, ext_hid, inh_hid },
+	{ M680X_INS_STA, ext_hid, inh_hid },
+	{ M680X_INS_EOR, ext_hid, inh_hid },
+	{ M680X_INS_ADC, ext_hid, inh_hid },
+	{ M680X_INS_ORA, ext_hid, inh_hid },
+	{ M680X_INS_ADD, ext_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	// 0xDx, indexed with 2 byte offset instructions with reg. A
+	{ M680X_INS_SUB, idxX16_hid, inh_hid },
+	{ M680X_INS_CMP, idxX16_hid, inh_hid },
+	{ M680X_INS_SBC, idxX16_hid, inh_hid },
+	{ M680X_INS_CPX, idxX16_hid, inh_hid },
+	{ M680X_INS_AND, idxX16_hid, inh_hid },
+	{ M680X_INS_BIT, idxX16_hid, inh_hid },
+	{ M680X_INS_LDA, idxX16_hid, inh_hid },
+	{ M680X_INS_STA, idxX16_hid, inh_hid },
+	{ M680X_INS_EOR, idxX16_hid, inh_hid },
+	{ M680X_INS_ADC, idxX16_hid, inh_hid },
+	{ M680X_INS_ORA, idxX16_hid, inh_hid },
+	{ M680X_INS_ADD, idxX16_hid, inh_hid },
+	{ M680X_INS_JMP, idxX16_hid, inh_hid },
+	{ M680X_INS_JSR, idxX16_hid, inh_hid },
+	{ M680X_INS_LDX, idxX16_hid, inh_hid },
+	{ M680X_INS_STX, idxX16_hid, inh_hid },
+	// 0xEx, indexed with 1 byte offset instructions with reg. A
+	{ M680X_INS_SUB, idxX_hid, inh_hid },
+	{ M680X_INS_CMP, idxX_hid, inh_hid },
+	{ M680X_INS_SBC, idxX_hid, inh_hid },
+	{ M680X_INS_CPX, idxX_hid, inh_hid },
+	{ M680X_INS_AND, idxX_hid, inh_hid },
+	{ M680X_INS_BIT, idxX_hid, inh_hid },
+	{ M680X_INS_LDA, idxX_hid, inh_hid },
+	{ M680X_INS_STA, idxX_hid, inh_hid },
+	{ M680X_INS_EOR, idxX_hid, inh_hid },
+	{ M680X_INS_ADC, idxX_hid, inh_hid },
+	{ M680X_INS_ORA, idxX_hid, inh_hid },
+	{ M680X_INS_ADD, idxX_hid, inh_hid },
+	{ M680X_INS_JMP, idxX_hid, inh_hid },
+	{ M680X_INS_JSR, idxX_hid, inh_hid },
+	{ M680X_INS_LDX, idxX_hid, inh_hid },
+	{ M680X_INS_STX, idxX_hid, inh_hid },
+	// 0xFx, indexed without offset instructions with reg. A
+	{ M680X_INS_SUB, idxX0_hid, inh_hid },
+	{ M680X_INS_CMP, idxX0_hid, inh_hid },
+	{ M680X_INS_SBC, idxX0_hid, inh_hid },
+	{ M680X_INS_CPX, idxX0_hid, inh_hid },
+	{ M680X_INS_AND, idxX0_hid, inh_hid },
+	{ M680X_INS_BIT, idxX0_hid, inh_hid },
+	{ M680X_INS_LDA, idxX0_hid, inh_hid },
+	{ M680X_INS_STA, idxX0_hid, inh_hid },
+	{ M680X_INS_EOR, idxX0_hid, inh_hid },
+	{ M680X_INS_ADC, idxX0_hid, inh_hid },
+	{ M680X_INS_ORA, idxX0_hid, inh_hid },
+	{ M680X_INS_ADD, idxX0_hid, inh_hid },
+	{ M680X_INS_JMP, idxX0_hid, inh_hid },
+	{ M680X_INS_JSR, idxX0_hid, inh_hid },
+	{ M680X_INS_LDX, idxX0_hid, inh_hid },
+	{ M680X_INS_STX, idxX0_hid, inh_hid },
+};
+
--- a/arch/M680X/m6808.inc
+++ b/arch/M680X/m6808.inc
@ -0,0 +1,91 @@
+
+// Additional instructions only supported on M68HC08
+static const inst_pageX g_m6808_inst_overlay_table[] = {
+	{ 0x31, M680X_INS_CBEQ, dir_hid, rel8_hid },
+	{ 0x35, M680X_INS_STHX, dir_hid, inh_hid },
+	{ 0x3b, M680X_INS_DBNZ, dir_hid, rel8_hid },
+	{ 0x41, M680X_INS_CBEQA, imm8rel_hid, inh_hid },
+	{ 0x45, M680X_INS_LDHX, imm16_hid, inh_hid },
+	{ 0x4b, M680X_INS_DBNZA, rel8_hid, inh_hid },
+	{ 0x4e, M680X_INS_MOV, dir_hid, dir_hid },
+	{ 0x51, M680X_INS_CBEQX, imm8rel_hid, inh_hid },
+	{ 0x52, M680X_INS_DIV, inh_hid, inh_hid },
+	{ 0x55, M680X_INS_LDHX, dir_hid, inh_hid },
+	{ 0x5b, M680X_INS_DBNZX, rel8_hid, inh_hid },
+	{ 0x5e, M680X_INS_MOV, dir_hid, idxX0p_hid },
+	{ 0x61, M680X_INS_CBEQ, idxXp_hid, rel8_hid },
+	{ 0x62, M680X_INS_NSA, inh_hid, inh_hid },
+	{ 0x65, M680X_INS_CPHX, imm16_hid, inh_hid },
+	{ 0x6b, M680X_INS_DBNZ, idxX_hid, rel8_hid },
+	{ 0x6e, M680X_INS_MOV, imm8_hid, dir_hid },
+	{ 0x71, M680X_INS_CBEQ, idxX0p_hid, rel8_hid },
+	{ 0x72, M680X_INS_DAA, inh_hid, inh_hid },
+	{ 0x75, M680X_INS_CPHX, dir_hid, inh_hid },
+	{ 0x7b, M680X_INS_DBNZ, idxX0_hid, rel8_hid },
+	{ 0x7e, M680X_INS_MOV, idxX0p_hid, dir_hid },
+	{ 0x84, M680X_INS_TAP, inh_hid, inh_hid },
+	{ 0x85, M680X_INS_TPA, inh_hid, inh_hid },
+	{ 0x86, M680X_INS_PULA, inh_hid, inh_hid },
+	{ 0x87, M680X_INS_PSHA, inh_hid, inh_hid },
+	{ 0x88, M680X_INS_PULX, inh_hid, inh_hid },
+	{ 0x89, M680X_INS_PSHX, inh_hid, inh_hid },
+	{ 0x8a, M680X_INS_PULH, inh_hid, inh_hid },
+	{ 0x8b, M680X_INS_PSHH, inh_hid, inh_hid },
+	{ 0x8c, M680X_INS_CLRH, inh_hid, inh_hid },
+	{ 0x90, M680X_INS_BGE, rel8_hid, inh_hid },
+	{ 0x91, M680X_INS_BLT, rel8_hid, inh_hid },
+	{ 0x92, M680X_INS_BGT, rel8_hid, inh_hid },
+	{ 0x93, M680X_INS_BLE, rel8_hid, inh_hid },
+	{ 0x94, M680X_INS_TXS, inh_hid, inh_hid },
+	{ 0x95, M680X_INS_TSX, inh_hid, inh_hid },
+	{ 0x97, M680X_INS_TAX, inh_hid, inh_hid },
+	{ 0x9f, M680X_INS_TXA, inh_hid, inh_hid },
+	{ 0xa7, M680X_INS_AIS, imm8_hid, inh_hid },
+	{ 0xaf, M680X_INS_AIX, imm8_hid, inh_hid },
+};
+
+// M68HC08 PAGE2 instructions (prefix 0x9E)
+static const inst_pageX g_m6808_inst_page2_table[] = {
+	{ 0x60, M680X_INS_NEG, idxS_hid, inh_hid },
+	{ 0x61, M680X_INS_CBEQ, idxS_hid, rel8_hid },
+	{ 0x63, M680X_INS_COM, idxS_hid, inh_hid },
+	{ 0x64, M680X_INS_LSR, idxS_hid, inh_hid },
+	{ 0x66, M680X_INS_ROR, idxS_hid, inh_hid },
+	{ 0x67, M680X_INS_ASR, idxS_hid, inh_hid },
+	{ 0x68, M680X_INS_LSL, idxS_hid, inh_hid },
+	{ 0x69, M680X_INS_ROL, idxS_hid, inh_hid },
+	{ 0x6a, M680X_INS_DEC, idxS_hid, inh_hid },
+	{ 0x6b, M680X_INS_DBNZ, idxS_hid, rel8_hid },
+	{ 0x6c, M680X_INS_INC, idxS_hid, inh_hid },
+	{ 0x6d, M680X_INS_TST, idxS_hid, inh_hid },
+	{ 0x6f, M680X_INS_CLR, idxS_hid, inh_hid },
+	{ 0xd0, M680X_INS_SUB, idxS16_hid, inh_hid },
+	{ 0xd1, M680X_INS_CMP, idxS16_hid, inh_hid },
+	{ 0xd2, M680X_INS_SBC, idxS16_hid, inh_hid },
+	{ 0xd3, M680X_INS_CPX, idxS16_hid, inh_hid },
+	{ 0xd4, M680X_INS_AND, idxS16_hid, inh_hid },
+	{ 0xd5, M680X_INS_BIT, idxS16_hid, inh_hid },
+	{ 0xd6, M680X_INS_LDA, idxS16_hid, inh_hid },
+	{ 0xd7, M680X_INS_STA, idxS16_hid, inh_hid },
+	{ 0xd8, M680X_INS_EOR, idxS16_hid, inh_hid },
+	{ 0xd9, M680X_INS_ADC, idxS16_hid, inh_hid },
+	{ 0xda, M680X_INS_ORA, idxS16_hid, inh_hid },
+	{ 0xdb, M680X_INS_ADD, idxS16_hid, inh_hid },
+	{ 0xde, M680X_INS_LDX, idxS16_hid, inh_hid },
+	{ 0xdf, M680X_INS_STX, idxS16_hid, inh_hid },
+	{ 0xe0, M680X_INS_SUB, idxS_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMP, idxS_hid, inh_hid },
+	{ 0xe2, M680X_INS_SBC, idxS_hid, inh_hid },
+	{ 0xe3, M680X_INS_CPX, idxS_hid, inh_hid },
+	{ 0xe4, M680X_INS_AND, idxS_hid, inh_hid },
+	{ 0xe5, M680X_INS_BIT, idxS_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDA, idxS_hid, inh_hid },
+	{ 0xe7, M680X_INS_STA, idxS_hid, inh_hid },
+	{ 0xe8, M680X_INS_EOR, idxS_hid, inh_hid },
+	{ 0xe9, M680X_INS_ADC, idxS_hid, inh_hid },
+	{ 0xea, M680X_INS_ORA, idxS_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADD, idxS_hid, inh_hid },
+	{ 0xee, M680X_INS_LDX, idxS_hid, inh_hid },
+	{ 0xef, M680X_INS_STX, idxS_hid, inh_hid },
+};
+
--- a/arch/M680X/m6809.inc
+++ b/arch/M680X/m6809.inc
@ -0,0 +1,352 @@
+
+// M6809/HD6309 PAGE1 instructions
+static const inst_page1 g_m6809_inst_page1_table[256] = {
+	// 0x0x, direct instructions
+	{ M680X_INS_NEG, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, dir_hid, inh_hid },
+	{ M680X_INS_LSR, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, dir_hid, inh_hid },
+	{ M680X_INS_ASR, dir_hid, inh_hid },
+	{ M680X_INS_LSL, dir_hid, inh_hid },
+	{ M680X_INS_ROL, dir_hid, inh_hid },
+	{ M680X_INS_DEC, dir_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, dir_hid, inh_hid },
+	{ M680X_INS_TST, dir_hid, inh_hid },
+	{ M680X_INS_JMP, dir_hid, inh_hid },
+	{ M680X_INS_CLR, dir_hid, inh_hid },
+	// 0x1x, misc instructions
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE2
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid }, // PAGE3
+	{ M680X_INS_NOP, inh_hid, inh_hid },
+	{ M680X_INS_SYNC, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LBRA, rel16_hid, inh_hid },
+	{ M680X_INS_LBSR, rel16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_DAA, inh_hid, inh_hid },
+	{ M680X_INS_ORCC, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ANDCC, imm8_hid, inh_hid },
+	{ M680X_INS_SEX, inh_hid, inh_hid },
+	{ M680X_INS_EXG, rr09_hid, inh_hid },
+	{ M680X_INS_TFR, rr09_hid, inh_hid },
+	// 0x2x, relative branch instructions
+	{ M680X_INS_BRA, rel8_hid, inh_hid },
+	{ M680X_INS_BRN, rel8_hid, inh_hid },
+	{ M680X_INS_BHI, rel8_hid, inh_hid },
+	{ M680X_INS_BLS, rel8_hid, inh_hid },
+	{ M680X_INS_BCC, rel8_hid, inh_hid },
+	{ M680X_INS_BCS, rel8_hid, inh_hid },
+	{ M680X_INS_BNE, rel8_hid, inh_hid },
+	{ M680X_INS_BEQ, rel8_hid, inh_hid },
+	{ M680X_INS_BVC, rel8_hid, inh_hid },
+	{ M680X_INS_BVS, rel8_hid, inh_hid },
+	{ M680X_INS_BPL, rel8_hid, inh_hid },
+	{ M680X_INS_BMI, rel8_hid, inh_hid },
+	{ M680X_INS_BGE, rel8_hid, inh_hid },
+	{ M680X_INS_BLT, rel8_hid, inh_hid },
+	{ M680X_INS_BGT, rel8_hid, inh_hid },
+	{ M680X_INS_BLE, rel8_hid, inh_hid },
+	// 0x3x, misc instructions
+	{ M680X_INS_LEAX, idx09_hid, inh_hid },
+	{ M680X_INS_LEAY, idx09_hid, inh_hid },
+	{ M680X_INS_LEAS, idx09_hid, inh_hid },
+	{ M680X_INS_LEAU, idx09_hid, inh_hid },
+	{ M680X_INS_PSHS, rbits_hid, inh_hid },
+	{ M680X_INS_PULS, rbits_hid, inh_hid },
+	{ M680X_INS_PSHU, rbits_hid, inh_hid },
+	{ M680X_INS_PULU, rbits_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RTS, inh_hid, inh_hid },
+	{ M680X_INS_ABX, inh_hid, inh_hid },
+	{ M680X_INS_RTI, inh_hid, inh_hid },
+	{ M680X_INS_CWAI, imm8_hid, inh_hid },
+	{ M680X_INS_MUL, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_SWI, inh_hid, inh_hid },
+	// 0x4x, Register A instructions
+	{ M680X_INS_NEGA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMA, inh_hid, inh_hid },
+	{ M680X_INS_LSRA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORA, inh_hid, inh_hid },
+	{ M680X_INS_ASRA, inh_hid, inh_hid },
+	{ M680X_INS_LSLA, inh_hid, inh_hid },
+	{ M680X_INS_ROLA, inh_hid, inh_hid },
+	{ M680X_INS_DECA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCA, inh_hid, inh_hid },
+	{ M680X_INS_TSTA, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRA, inh_hid, inh_hid },
+	// 0x5x, Register B instructions
+	{ M680X_INS_NEGB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COMB, inh_hid, inh_hid },
+	{ M680X_INS_LSRB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_RORB, inh_hid, inh_hid },
+	{ M680X_INS_ASRB, inh_hid, inh_hid },
+	{ M680X_INS_LSLB, inh_hid, inh_hid },
+	{ M680X_INS_ROLB, inh_hid, inh_hid },
+	{ M680X_INS_DECB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INCB, inh_hid, inh_hid },
+	{ M680X_INS_TSTB, inh_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_CLRB, inh_hid, inh_hid },
+	// 0x6x, indexed instructions
+	{ M680X_INS_NEG, idx09_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, idx09_hid, inh_hid },
+	{ M680X_INS_LSR, idx09_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, idx09_hid, inh_hid },
+	{ M680X_INS_ASR, idx09_hid, inh_hid },
+	{ M680X_INS_LSL, idx09_hid, inh_hid },
+	{ M680X_INS_ROL, idx09_hid, inh_hid },
+	{ M680X_INS_DEC, idx09_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, idx09_hid, inh_hid },
+	{ M680X_INS_TST, idx09_hid, inh_hid },
+	{ M680X_INS_JMP, idx09_hid, inh_hid },
+	{ M680X_INS_CLR, idx09_hid, inh_hid },
+	// 0x7x, extended instructions
+	{ M680X_INS_NEG, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_COM, ext_hid, inh_hid },
+	{ M680X_INS_LSR, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_ROR, ext_hid, inh_hid },
+	{ M680X_INS_ASR, ext_hid, inh_hid },
+	{ M680X_INS_LSL, ext_hid, inh_hid },
+	{ M680X_INS_ROL, ext_hid, inh_hid },
+	{ M680X_INS_DEC, ext_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_INC, ext_hid, inh_hid },
+	{ M680X_INS_TST, ext_hid, inh_hid },
+	{ M680X_INS_JMP, ext_hid, inh_hid },
+	{ M680X_INS_CLR, ext_hid, inh_hid },
+	// 0x8x, immediate instructions with Register A,D,X
+	{ M680X_INS_SUBA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPA, imm8_hid, inh_hid },
+	{ M680X_INS_SBCA, imm8_hid, inh_hid },
+	{ M680X_INS_SUBD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDA, imm8_hid, inh_hid },
+	{ M680X_INS_BITA, imm8_hid, inh_hid },
+	{ M680X_INS_LDA, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADCA, imm8_hid, inh_hid },
+	{ M680X_INS_ORA, imm8_hid, inh_hid },
+	{ M680X_INS_ADDA, imm8_hid, inh_hid },
+	{ M680X_INS_CMPX, imm16_hid, inh_hid },
+	{ M680X_INS_BSR, rel8_hid, inh_hid },
+	{ M680X_INS_LDX, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0x9x, direct instructions with register A,D,X
+	{ M680X_INS_SUBA, dir_hid, inh_hid },
+	{ M680X_INS_CMPA, dir_hid, inh_hid },
+	{ M680X_INS_SBCA, dir_hid, inh_hid },
+	{ M680X_INS_SUBD, dir_hid, inh_hid },
+	{ M680X_INS_ANDA, dir_hid, inh_hid },
+	{ M680X_INS_BITA, dir_hid, inh_hid },
+	{ M680X_INS_LDA, dir_hid, inh_hid },
+	{ M680X_INS_STA, dir_hid, inh_hid },
+	{ M680X_INS_EORA, dir_hid, inh_hid },
+	{ M680X_INS_ADCA, dir_hid, inh_hid },
+	{ M680X_INS_ORA, dir_hid, inh_hid },
+	{ M680X_INS_ADDA, dir_hid, inh_hid },
+	{ M680X_INS_CMPX, dir_hid, inh_hid },
+	{ M680X_INS_JSR, dir_hid, inh_hid },
+	{ M680X_INS_LDX, dir_hid, inh_hid },
+	{ M680X_INS_STX, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with Register A,D,X
+	{ M680X_INS_SUBA, idx09_hid, inh_hid },
+	{ M680X_INS_CMPA, idx09_hid, inh_hid },
+	{ M680X_INS_SBCA, idx09_hid, inh_hid },
+	{ M680X_INS_SUBD, idx09_hid, inh_hid },
+	{ M680X_INS_ANDA, idx09_hid, inh_hid },
+	{ M680X_INS_BITA, idx09_hid, inh_hid },
+	{ M680X_INS_LDA, idx09_hid, inh_hid },
+	{ M680X_INS_STA, idx09_hid, inh_hid },
+	{ M680X_INS_EORA, idx09_hid, inh_hid },
+	{ M680X_INS_ADCA, idx09_hid, inh_hid },
+	{ M680X_INS_ORA, idx09_hid, inh_hid },
+	{ M680X_INS_ADDA, idx09_hid, inh_hid },
+	{ M680X_INS_CMPX, idx09_hid, inh_hid },
+	{ M680X_INS_JSR, idx09_hid, inh_hid },
+	{ M680X_INS_LDX, idx09_hid, inh_hid },
+	{ M680X_INS_STX, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register A,D,X
+	{ M680X_INS_SUBA, ext_hid, inh_hid },
+	{ M680X_INS_CMPA, ext_hid, inh_hid },
+	{ M680X_INS_SBCA, ext_hid, inh_hid },
+	{ M680X_INS_SUBD, ext_hid, inh_hid },
+	{ M680X_INS_ANDA, ext_hid, inh_hid },
+	{ M680X_INS_BITA, ext_hid, inh_hid },
+	{ M680X_INS_LDA, ext_hid, inh_hid },
+	{ M680X_INS_STA, ext_hid, inh_hid },
+	{ M680X_INS_EORA, ext_hid, inh_hid },
+	{ M680X_INS_ADCA, ext_hid, inh_hid },
+	{ M680X_INS_ORA, ext_hid, inh_hid },
+	{ M680X_INS_ADDA, ext_hid, inh_hid },
+	{ M680X_INS_CMPX, ext_hid, inh_hid },
+	{ M680X_INS_JSR, ext_hid, inh_hid },
+	{ M680X_INS_LDX, ext_hid, inh_hid },
+	{ M680X_INS_STX, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register B,D,U
+	{ M680X_INS_SUBB, imm8_hid, inh_hid },
+	{ M680X_INS_CMPB, imm8_hid, inh_hid },
+	{ M680X_INS_SBCB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDD, imm16_hid, inh_hid },
+	{ M680X_INS_ANDB, imm8_hid, inh_hid },
+	{ M680X_INS_BITB, imm8_hid, inh_hid },
+	{ M680X_INS_LDB, imm8_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_EORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADCB, imm8_hid, inh_hid },
+	{ M680X_INS_ORB, imm8_hid, inh_hid },
+	{ M680X_INS_ADDB, imm8_hid, inh_hid },
+	{ M680X_INS_LDD, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	{ M680X_INS_LDU, imm16_hid, inh_hid },
+	{ M680X_INS_ILLGL, illgl_hid, inh_hid },
+	// 0xDx direct instructions with register B,D,U
+	{ M680X_INS_SUBB, dir_hid, inh_hid },
+	{ M680X_INS_CMPB, dir_hid, inh_hid },
+	{ M680X_INS_SBCB, dir_hid, inh_hid },
+	{ M680X_INS_ADDD, dir_hid, inh_hid },
+	{ M680X_INS_ANDB, dir_hid, inh_hid },
+	{ M680X_INS_BITB, dir_hid, inh_hid },
+	{ M680X_INS_LDB, dir_hid, inh_hid },
+	{ M680X_INS_STB, dir_hid, inh_hid },
+	{ M680X_INS_EORB, dir_hid, inh_hid },
+	{ M680X_INS_ADCB, dir_hid, inh_hid },
+	{ M680X_INS_ORB, dir_hid, inh_hid },
+	{ M680X_INS_ADDB, dir_hid, inh_hid },
+	{ M680X_INS_LDD, dir_hid, inh_hid },
+	{ M680X_INS_STD, dir_hid, inh_hid },
+	{ M680X_INS_LDU, dir_hid, inh_hid },
+	{ M680X_INS_STU, dir_hid, inh_hid },
+	// 0xEx, indexed instruction with register B,D,U
+	{ M680X_INS_SUBB, idx09_hid, inh_hid },
+	{ M680X_INS_CMPB, idx09_hid, inh_hid },
+	{ M680X_INS_SBCB, idx09_hid, inh_hid },
+	{ M680X_INS_ADDD, idx09_hid, inh_hid },
+	{ M680X_INS_ANDB, idx09_hid, inh_hid },
+	{ M680X_INS_BITB, idx09_hid, inh_hid },
+	{ M680X_INS_LDB, idx09_hid, inh_hid },
+	{ M680X_INS_STB, idx09_hid, inh_hid },
+	{ M680X_INS_EORB, idx09_hid, inh_hid },
+	{ M680X_INS_ADCB, idx09_hid, inh_hid },
+	{ M680X_INS_ORB, idx09_hid, inh_hid },
+	{ M680X_INS_ADDB, idx09_hid, inh_hid },
+	{ M680X_INS_LDD, idx09_hid, inh_hid },
+	{ M680X_INS_STD, idx09_hid, inh_hid },
+	{ M680X_INS_LDU, idx09_hid, inh_hid },
+	{ M680X_INS_STU, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register B,D,U
+	{ M680X_INS_SUBB, ext_hid, inh_hid },
+	{ M680X_INS_CMPB, ext_hid, inh_hid },
+	{ M680X_INS_SBCB, ext_hid, inh_hid },
+	{ M680X_INS_ADDD, ext_hid, inh_hid },
+	{ M680X_INS_ANDB, ext_hid, inh_hid },
+	{ M680X_INS_BITB, ext_hid, inh_hid },
+	{ M680X_INS_LDB, ext_hid, inh_hid },
+	{ M680X_INS_STB, ext_hid, inh_hid },
+	{ M680X_INS_EORB, ext_hid, inh_hid },
+	{ M680X_INS_ADCB, ext_hid, inh_hid },
+	{ M680X_INS_ORB, ext_hid, inh_hid },
+	{ M680X_INS_ADDB, ext_hid, inh_hid },
+	{ M680X_INS_LDD, ext_hid, inh_hid },
+	{ M680X_INS_STD, ext_hid, inh_hid },
+	{ M680X_INS_LDU, ext_hid, inh_hid },
+	{ M680X_INS_STU, ext_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// M6809 PAGE2 instructions (with prefix 0x10)
+static const inst_pageX g_m6809_inst_page2_table[] = {
+	// 0x2x, relative long branch instructions
+	{ 0x21, M680X_INS_LBRN, rel16_hid, inh_hid },
+	{ 0x22, M680X_INS_LBHI, rel16_hid, inh_hid },
+	{ 0x23, M680X_INS_LBLS, rel16_hid, inh_hid },
+	{ 0x24, M680X_INS_LBCC, rel16_hid, inh_hid },
+	{ 0x25, M680X_INS_LBCS, rel16_hid, inh_hid },
+	{ 0x26, M680X_INS_LBNE, rel16_hid, inh_hid },
+	{ 0x27, M680X_INS_LBEQ, rel16_hid, inh_hid },
+	{ 0x28, M680X_INS_LBVC, rel16_hid, inh_hid },
+	{ 0x29, M680X_INS_LBVS, rel16_hid, inh_hid },
+	{ 0x2a, M680X_INS_LBPL, rel16_hid, inh_hid },
+	{ 0x2b, M680X_INS_LBMI, rel16_hid, inh_hid },
+	{ 0x2c, M680X_INS_LBGE, rel16_hid, inh_hid },
+	{ 0x2d, M680X_INS_LBLT, rel16_hid, inh_hid },
+	{ 0x2e, M680X_INS_LBGT, rel16_hid, inh_hid },
+	{ 0x2f, M680X_INS_LBLE, rel16_hid, inh_hid },
+	// 0x3x
+	{ 0x3f, M680X_INS_SWI2, inh_hid, inh_hid },
+	// 0x8x, immediate instructions with register D,Y
+	{ 0x83, M680X_INS_CMPD, imm16_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPY, imm16_hid, inh_hid },
+	{ 0x8e, M680X_INS_LDY, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register D,Y
+	{ 0x93, M680X_INS_CMPD, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPY, dir_hid, inh_hid },
+	{ 0x9e, M680X_INS_LDY, dir_hid, inh_hid },
+	{ 0x9f, M680X_INS_STY, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register D,Y
+	{ 0xa3, M680X_INS_CMPD, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPY, idx09_hid, inh_hid },
+	{ 0xae, M680X_INS_LDY, idx09_hid, inh_hid },
+	{ 0xaf, M680X_INS_STY, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register D,Y
+	{ 0xb3, M680X_INS_CMPD, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPY, ext_hid, inh_hid },
+	{ 0xbe, M680X_INS_LDY, ext_hid, inh_hid },
+	{ 0xbf, M680X_INS_STY, ext_hid, inh_hid },
+	// 0xCx, immediate instructions with register S
+	{ 0xce, M680X_INS_LDS, imm16_hid, inh_hid },
+	// 0xDx, direct instructions with register S
+	{ 0xde, M680X_INS_LDS, dir_hid, inh_hid },
+	{ 0xdf, M680X_INS_STS, dir_hid, inh_hid },
+	// 0xEx, indexed instructions with register S
+	{ 0xee, M680X_INS_LDS, idx09_hid, inh_hid },
+	{ 0xef, M680X_INS_STS, idx09_hid, inh_hid },
+	// 0xFx, extended instructions with register S
+	{ 0xfe, M680X_INS_LDS, ext_hid, inh_hid },
+	{ 0xff, M680X_INS_STS, ext_hid, inh_hid },
+};
+
+// The following array has to be sorted by increasing
+// opcodes. Otherwise the binary_search will fail.
+//
+// M6809 PAGE3 instructions (with prefix 0x11)
+static const inst_pageX g_m6809_inst_page3_table[] = {
+	{ 0x3f, M680X_INS_SWI3, inh_hid, inh_hid },
+	// 0x8x, immediate instructions with register U,S
+	{ 0x83, M680X_INS_CMPU, imm16_hid, inh_hid },
+	{ 0x8c, M680X_INS_CMPS, imm16_hid, inh_hid },
+	// 0x9x, direct instructions with register U,S
+	{ 0x93, M680X_INS_CMPU, dir_hid, inh_hid },
+	{ 0x9c, M680X_INS_CMPS, dir_hid, inh_hid },
+	// 0xAx, indexed instructions with register U,S
+	{ 0xa3, M680X_INS_CMPU, idx09_hid, inh_hid },
+	{ 0xac, M680X_INS_CMPS, idx09_hid, inh_hid },
+	// 0xBx, extended instructions with register U,S
+	{ 0xb3, M680X_INS_CMPU, ext_hid, inh_hid },
+	{ 0xbc, M680X_INS_CMPS, ext_hid, inh_hid },
+};
+
--- a/arch/M680X/m6811.inc
+++ b/arch/M680X/m6811.inc
@ -0,0 +1,105 @@
+
+// Additional instructions only supported on M68HC11
+static const inst_pageX g_m6811_inst_overlay_table[] = {
+	{ 0x00, M680X_INS_TEST, inh_hid, inh_hid },
+	{ 0x02, M680X_INS_IDIV, inh_hid, inh_hid },
+	{ 0x03, M680X_INS_FDIV, inh_hid, inh_hid },
+	{ 0x12, M680X_INS_BRSET, dir_hid, imm8rel_hid },
+	{ 0x13, M680X_INS_BRCLR, dir_hid, imm8rel_hid },
+	{ 0x14, M680X_INS_BSET, dir_hid, imm8_hid },
+	{ 0x15, M680X_INS_BCLR, dir_hid, imm8_hid },
+	{ 0x1c, M680X_INS_BSET, idxX_hid, imm8_hid },
+	{ 0x1d, M680X_INS_BCLR, idxX_hid, imm8_hid },
+	{ 0x1e, M680X_INS_BRSET, idxX_hid, imm8rel_hid },
+	{ 0x1f, M680X_INS_BRCLR, idxX_hid, imm8rel_hid },
+	{ 0x8f, M680X_INS_XGDX, inh_hid, inh_hid },
+	{ 0xcf, M680X_INS_STOP, inh_hid, inh_hid },
+};
+
+// M68HC11 PAGE2 instructions
+static const inst_pageX g_m6811_inst_page2_table[] = {
+	{ 0x08, M680X_INS_INY, inh_hid, inh_hid },
+	{ 0x09, M680X_INS_DEY, inh_hid, inh_hid },
+	{ 0x1c, M680X_INS_BSET, idxY_hid, imm8_hid },
+	{ 0x1d, M680X_INS_BCLR, idxY_hid, imm8_hid },
+	{ 0x1e, M680X_INS_BRSET, idxY_hid, imm8rel_hid },
+	{ 0x1f, M680X_INS_BRCLR, idxY_hid, imm8rel_hid },
+	{ 0x30, M680X_INS_TSY, inh_hid, inh_hid },
+	{ 0x35, M680X_INS_TYS, inh_hid, inh_hid },
+	{ 0x38, M680X_INS_PULY, inh_hid, inh_hid },
+	{ 0x3a, M680X_INS_ABY, inh_hid, inh_hid },
+	{ 0x3c, M680X_INS_PSHY, inh_hid, inh_hid },
+	{ 0x60, M680X_INS_NEG, idxY_hid, inh_hid },
+	{ 0x63, M680X_INS_COM, idxY_hid, inh_hid },
+	{ 0x64, M680X_INS_LSR, idxY_hid, inh_hid },
+	{ 0x66, M680X_INS_ROR, idxY_hid, inh_hid },
+	{ 0x67, M680X_INS_ASR, idxY_hid, inh_hid },
+	{ 0x68, M680X_INS_ASL, idxY_hid, inh_hid },
+	{ 0x69, M680X_INS_ROL, idxY_hid, inh_hid },
+	{ 0x6a, M680X_INS_DEC, idxY_hid, inh_hid },
+	{ 0x6c, M680X_INS_INC, idxY_hid, inh_hid },
+	{ 0x6d, M680X_INS_TST, idxY_hid, inh_hid },
+	{ 0x6e, M680X_INS_JMP, idxY_hid, inh_hid },
+	{ 0x6f, M680X_INS_CLR, idxY_hid, inh_hid },
+	{ 0x8c, M680X_INS_CPY, imm16_hid, inh_hid },
+	{ 0x8f, M680X_INS_XGDY, inh_hid, inh_hid },
+	{ 0x9c, M680X_INS_CPY, dir_hid, inh_hid },
+	{ 0xa0, M680X_INS_SUBA, idxY_hid, inh_hid },
+	{ 0xa1, M680X_INS_CMPA, idxY_hid, inh_hid },
+	{ 0xa2, M680X_INS_SBCA, idxY_hid, inh_hid },
+	{ 0xa3, M680X_INS_SUBD, idxY_hid, inh_hid },
+	{ 0xa4, M680X_INS_ANDA, idxY_hid, inh_hid },
+	{ 0xa5, M680X_INS_BITA, idxY_hid, inh_hid },
+	{ 0xa6, M680X_INS_LDAA, idxY_hid, inh_hid },
+	{ 0xa7, M680X_INS_STAA, idxY_hid, inh_hid },
+	{ 0xa8, M680X_INS_EORA, idxY_hid, inh_hid },
+	{ 0xa9, M680X_INS_ADCA, idxY_hid, inh_hid },
+	{ 0xaa, M680X_INS_ORAA, idxY_hid, inh_hid },
+	{ 0xab, M680X_INS_ADDA, idxY_hid, inh_hid },
+	{ 0xac, M680X_INS_CPY, idxY_hid, inh_hid },
+	{ 0xad, M680X_INS_JSR, idxY_hid, inh_hid },
+	{ 0xae, M680X_INS_LDS, idxY_hid, inh_hid },
+	{ 0xaf, M680X_INS_STS, idxY_hid, inh_hid },
+	{ 0xbc, M680X_INS_CPY, ext_hid, inh_hid },
+	{ 0xce, M680X_INS_LDY, imm16_hid, inh_hid },
+	{ 0xde, M680X_INS_LDY, dir_hid, inh_hid },
+	{ 0xdf, M680X_INS_STY, dir_hid, inh_hid },
+	{ 0xe0, M680X_INS_SUBB, idxY_hid, inh_hid },
+	{ 0xe1, M680X_INS_CMPB, idxY_hid, inh_hid },
+	{ 0xe2, M680X_INS_SBCB, idxY_hid, inh_hid },
+	{ 0xe3, M680X_INS_ADDD, idxY_hid, inh_hid },
+	{ 0xe4, M680X_INS_ANDB, idxY_hid, inh_hid },
+	{ 0xe5, M680X_INS_BITB, idxY_hid, inh_hid },
+	{ 0xe6, M680X_INS_LDAB, idxY_hid, inh_hid },
+	{ 0xe7, M680X_INS_STAB, idxY_hid, inh_hid },
+	{ 0xe8, M680X_INS_EORB, idxY_hid, inh_hid },
+	{ 0xe9, M680X_INS_ADCB, idxY_hid, inh_hid },
+	{ 0xea, M680X_INS_ORAB, idxY_hid, inh_hid },
+	{ 0xeb, M680X_INS_ADDB, idxY_hid, inh_hid },
+	{ 0xec, M680X_INS_LDD, idxY_hid, inh_hid },
+	{ 0xed, M680X_INS_STD, idxY_hid, inh_hid },
+	{ 0xee, M680X_INS_LDY, idxY_hid, inh_hid },
+	{ 0xef, M680X_INS_STY, idxY_hid, inh_hid },
+	{ 0xfe, M680X_INS_LDY, ext_hid, inh_hid },
+	{ 0xff, M680X_INS_STY, ext_hid, inh_hid },
+};
+
+// M68HC11 PAGE3 instructions
+static const inst_pageX g_m6811_inst_page3_table[] = {
+	{ 0x83, M680X_INS_CPD, imm16_hid, inh_hid },
+	{ 0x93, M680X_INS_CPD, dir_hid, inh_hid },
+	{ 0xa3, M680X_INS_CPD, idxX_hid, inh_hid },
+	{ 0xac, M680X_INS_CPY, idxX_hid, inh_hid },
+	{ 0xb3, M680X_INS_CPD, ext_hid, inh_hid },
+	{ 0xee, M680X_INS_LDY, idxX_hid, inh_hid },
+	{ 0xef, M680X_INS_STY, idxX_hid, inh_hid },
+};
+
+// M68HC11 PAGE4 instructions
+static const inst_pageX g_m6811_inst_page4_table[] = {
+	{ 0xa3, M680X_INS_CPD, idxY_hid, inh_hid },
+	{ 0xac, M680X_INS_CPX, idxY_hid, inh_hid },
+	{ 0xee, M680X_INS_LDX, idxY_hid, inh_hid },
+	{ 0xef, M680X_INS_STX, idxY_hid, inh_hid },
+};
+
--- a/arch/M68K/M68KDisassembler.c
+++ b/arch/M68K/M68KDisassembler.c
--- a/arch/M68K/M68KDisassembler.h
+++ b/arch/M68K/M68KDisassembler.h
@ -0,0 +1,30 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
+
+#ifndef CS_M68KDISASSEMBLER_H
+#define CS_M68KDISASSEMBLER_H
+
+#include "../../MCInst.h"
+
+/* Private, For internal use only */
+typedef struct m68k_info {
+	const uint8_t *code;
+	size_t code_len;
+	uint64_t baseAddress;
+	MCInst *inst;
+	unsigned int pc;        /* program counter */
+	unsigned int ir;        /* instruction register */
+	unsigned int type;
+	unsigned int address_mask; /* Address mask to simulate address lines */
+	cs_m68k extension;
+	uint16_t regs_read[20]; // list of implicit registers read by this insn
+	uint8_t regs_read_count; // number of implicit registers read by this insn
+	uint16_t regs_write[20]; // list of implicit registers modified by this insn
+	uint8_t regs_write_count; // number of implicit registers modified by this insn
+	uint8_t groups[8];
+	uint8_t groups_count;
+} m68k_info;
+
+bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info);
+
+#endif
--- a/arch/M68K/M68KInstPrinter.c
+++ b/arch/M68K/M68KInstPrinter.c
@ -0,0 +1,377 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
+
+#ifdef _MSC_VER
+// Disable security warnings for strcat & sprintf
+#ifndef _CRT_SECURE_NO_WARNINGS
+#define _CRT_SECURE_NO_WARNINGS
+#endif
+
+//Banned API Usage : strcat / sprintf is a Banned API as listed in dontuse.h for
+//security purposes.
+#pragma warning(disable:28719)
+#endif
+
+#include <stdio.h>	// DEBUG
+#include <stdlib.h>
+#include <string.h>
+
+#include "M68KDisassembler.h"
+
+#include "../../cs_priv.h"
+#include "../../utils.h"
+
+#include "../../MCInst.h"
+#include "../../MCInstrDesc.h"
+#include "../../MCRegisterInfo.h"
+
+#ifndef CAPSTONE_DIET
+static const char* s_spacing = " ";
+
+static const char* s_reg_names[] = {
+	"invalid",
+	"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+	"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+	"fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
+	"pc",
+	"sr", "ccr", "sfc", "dfc", "usp", "vbr", "cacr",
+	"caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
+	"dtt1", "mmusr", "urp", "srp",
+
+	"fpcr", "fpsr", "fpiar",
+};
+
+static const char* s_instruction_names[] = {
+	"invalid",
+	"abcd", "add", "adda", "addi", "addq", "addx", "and", "andi", "asl", "asr", "bhs", "blo", "bhi", "bls", "bcc", "bcs", "bne", "beq", "bvc",
+	"bvs", "bpl", "bmi", "bge", "blt", "bgt", "ble", "bra", "bsr", "bchg", "bclr", "bset", "btst", "bfchg", "bfclr", "bfexts", "bfextu", "bfffo", "bfins",
+	"bfset", "bftst", "bkpt", "callm", "cas", "cas2", "chk", "chk2", "clr", "cmp", "cmpa", "cmpi", "cmpm", "cmp2", "cinvl", "cinvp", "cinva", "cpushl", "cpushp",
+	"cpusha", "dbt", "dbf", "dbhi", "dbls", "dbcc", "dbcs", "dbne", "dbeq", "dbvc", "dbvs", "dbpl", "dbmi", "dbge", "dblt", "dbgt", "dble", "dbra",
+	"divs", "divsl", "divu", "divul", "eor", "eori", "exg", "ext", "extb", "fabs", "fsabs", "fdabs", "facos", "fadd", "fsadd", "fdadd", "fasin",
+	"fatan", "fatanh", "fbf", "fbeq", "fbogt", "fboge", "fbolt", "fbole", "fbogl", "fbor", "fbun", "fbueq", "fbugt", "fbuge", "fbult", "fbule", "fbne", "fbt",
+	"fbsf", "fbseq", "fbgt", "fbge", "fblt", "fble", "fbgl", "fbgle", "fbngle", "fbngl", "fbnle", "fbnlt", "fbnge", "fbngt", "fbsne", "fbst", "fcmp", "fcos",
+	"fcosh", "fdbf", "fdbeq", "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", "fdbne",
+	"fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne",
+	"fdbst", "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", "flognp1", "fmod", "fmove",
+	"fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv",
+	"fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq",
+	"fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", "fsgl", "fsgle", "fsngle",
+	"fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt",
+	"ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt",
+	"ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
+	"ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec",
+	"movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha",
+	"pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror",
+	"roxl", "roxr", "rtd", "rte", "rtm", "rtr", "rts", "sbcd", "st", "sf", "shi", "sls", "scc", "shs", "scs", "slo", "sne", "seq", "svc", "svs", "spl", "smi",
+	"sge", "slt", "sgt", "sle", "stop", "sub", "suba", "subi", "subq", "subx", "swap", "tas", "trap", "trapv", "trapt", "trapf", "traphi", "trapls",
+	"trapcc", "traphs", "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", "tst", "unlk", "unpk",
+};
+#endif
+
+
+#ifndef CAPSTONE_DIET
+const char* getRegName(m68k_reg reg)
+{
+	return s_reg_names[(int)reg];
+}
+
+static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix)
+{
+	unsigned int first = 0;
+	unsigned int run_length = 0;
+	int i;
+
+	for (i = 0; i < 8; ++i) {
+		if (data & (1 << i)) {
+			first = i;
+			run_length = 0;
+
+			while (i < 7 && (data & (1 << (i + 1)))) {
+				i++;
+				run_length++;
+			}
+
+			if (buffer[0] != 0)
+				strcat(buffer, "/");
+
+			sprintf(buffer + strlen(buffer), "%s%d", prefix, first);
+			if (run_length > 0)
+				sprintf(buffer + strlen(buffer), "-%s%d", prefix, first + run_length);
+		}
+	}
+}
+
+static void registerBits(SStream* O, const cs_m68k_op* op)
+{
+	char buffer[128];
+	unsigned int data = op->register_bits;
+
+	buffer[0] = 0;
+
+	printRegbitsRange(buffer, data & 0xff, "d");
+	printRegbitsRange(buffer, (data >> 8) & 0xff, "a");
+	printRegbitsRange(buffer, (data >> 16) & 0xff, "fp");
+
+	SStream_concat(O, "%s", buffer);
+}
+
+static void registerPair(SStream* O, const cs_m68k_op* op)
+{
+	SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + op->reg_pair.reg_0],
+			s_reg_names[M68K_REG_D0 + op->reg_pair.reg_1]);
+}
+
+void printAddressingMode(SStream* O, unsigned int pc, const cs_m68k* inst, const cs_m68k_op* op)
+{
+	switch (op->address_mode) {
+		case M68K_AM_NONE:
+			switch (op->type) {
+				case M68K_OP_REG_BITS:
+					registerBits(O, op);
+					break;
+				case M68K_OP_REG_PAIR:
+					registerPair(O, op);
+					break;
+				case M68K_OP_REG:
+					SStream_concat(O, "%s", s_reg_names[op->reg]);
+					break;
+				default:
+					break;
+			}
+			break;
+
+		case M68K_AM_REG_DIRECT_DATA: SStream_concat(O, "d%d", (op->reg - M68K_REG_D0)); break;
+		case M68K_AM_REG_DIRECT_ADDR: SStream_concat(O, "a%d", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR: SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR_POST_INC: SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR_PRE_DEC: SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); break;
+		case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); break;
+		case M68K_AM_PCI_DISP: SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp); break;
+		case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break;
+		case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break;
+		case M68K_AM_IMMEDIATE:
+			 if (inst->op_size.type == M68K_SIZE_TYPE_FPU) {
+#if defined(_KERNEL_MODE)
+				 // Issue #681: Windows kernel does not support formatting float point
+				 SStream_concat(O, "#<float_point_unsupported>");
+				 break;
+#else
+				 if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE)
+					 SStream_concat(O, "#%f", op->simm);
+				 else if (inst->op_size.fpu_size == M68K_FPU_SIZE_DOUBLE)
+					 SStream_concat(O, "#%f", op->dimm);
+				 else
+					 SStream_concat(O, "#<unsupported>");
+				 break;
+#endif
+			 }
+			 SStream_concat(O, "#$%x", op->imm);
+			 break;
+		case M68K_AM_PCI_INDEX_8_BIT_DISP:
+			SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			break;
+		case M68K_AM_AREGI_INDEX_8_BIT_DISP:
+			SStream_concat(O, "%s$%x(%s,%s%s.%c)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			break;
+		case M68K_AM_PCI_INDEX_BASE_DISP:
+		case M68K_AM_AREGI_INDEX_BASE_DISP:
+
+			if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
+				SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
+			} else {
+				if (op->mem.in_disp > 0)
+					SStream_concat(O, "$%x", op->mem.in_disp);
+			}
+
+			SStream_concat(O, "(");
+
+			if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) {
+			    SStream_concat(O, "pc,%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			} else {
+				if (op->mem.base_reg != M68K_REG_INVALID)
+					SStream_concat(O, "a%d,%s", op->mem.base_reg - M68K_REG_A0, s_spacing);
+				SStream_concat(O, "%s.%c", getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+			}
+
+			if (op->mem.scale > 0)
+			    SStream_concat(O, "%s*%s%d)", s_spacing, s_spacing, op->mem.scale);
+			else
+			    SStream_concat(O, ")");
+			break;
+			// It's ok to just use PCMI here as is as we set base_reg to PC in the disassembler. While this is not strictly correct it makes the code
+			// easier and that is what actually happens when the code is executed anyway.
+
+		case M68K_AM_PC_MEMI_POST_INDEX:
+		case M68K_AM_PC_MEMI_PRE_INDEX:
+		case M68K_AM_MEMI_PRE_INDEX:
+		case M68K_AM_MEMI_POST_INDEX:
+			SStream_concat(O, "([");
+
+			if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) {
+				SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp);
+			} else {
+				if (op->mem.in_disp > 0)
+					SStream_concat(O, "$%x", op->mem.in_disp);
+			}
+
+			if (op->mem.base_reg != M68K_REG_INVALID) {
+				if (op->mem.in_disp > 0)
+					SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg));
+				else
+					SStream_concat(O, "%s", getRegName(op->mem.base_reg));
+			}
+
+			if (op->address_mode == M68K_AM_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_POST_INDEX)
+			    SStream_concat(O, "]");
+
+			if (op->mem.index_reg != M68K_REG_INVALID)
+			    SStream_concat(O, ",%s%s.%c", s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
+
+			if (op->mem.scale > 0)
+			    SStream_concat(O, "%s*%s%d", s_spacing, s_spacing, op->mem.scale);
+
+			if (op->address_mode == M68K_AM_MEMI_PRE_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX)
+			    SStream_concat(O, "]");
+
+			if (op->mem.out_disp > 0)
+			    SStream_concat(O, ",%s$%x", s_spacing, op->mem.out_disp);
+
+			SStream_concat(O, ")");
+			break;
+		case M68K_AM_BRANCH_DISPLACEMENT:
+			SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp);
+		default:
+			break;
+	}
+
+	if (op->mem.bitfield)
+		SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width);
+}
+#endif
+
+#define m68k_sizeof_array(array) (int)(sizeof(array)/sizeof(array[0]))
+#define m68k_min(a, b) (a < b) ? a : b
+
+void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo)
+{
+#ifndef CAPSTONE_DIET
+	m68k_info *info = (m68k_info *)PrinterInfo;
+	cs_m68k *ext = &info->extension;
+	cs_detail *detail = NULL;
+	int i = 0;
+
+	detail = MI->flat_insn->detail;
+	if (detail) {
+		int regs_read_count = m68k_min(m68k_sizeof_array(detail->regs_read), info->regs_read_count);
+		int regs_write_count = m68k_min(m68k_sizeof_array(detail->regs_write), info->regs_write_count);
+		int groups_count = m68k_min(m68k_sizeof_array(detail->groups), info->groups_count);
+
+		memcpy(&detail->m68k, ext, sizeof(cs_m68k));
+
+		memcpy(&detail->regs_read, &info->regs_read, regs_read_count * sizeof(uint16_t));
+		detail->regs_read_count = regs_read_count;
+
+		memcpy(&detail->regs_write, &info->regs_write, regs_write_count * sizeof(uint16_t));
+		detail->regs_write_count = regs_write_count;
+
+		memcpy(&detail->groups, &info->groups, groups_count);
+		detail->groups_count = groups_count;
+	}
+
+	if (MI->Opcode == M68K_INS_INVALID) {
+		if (ext->op_count)
+			SStream_concat(O, "dc.w $%x", ext->operands[0].imm);
+		else
+			SStream_concat(O, "dc.w $<unknown>");
+		return;
+	}
+
+	SStream_concat0(O, (char*)s_instruction_names[MI->Opcode]);
+
+	switch (ext->op_size.type) {
+		case M68K_SIZE_TYPE_INVALID :
+			break;
+
+		case M68K_SIZE_TYPE_CPU :
+			switch (ext->op_size.cpu_size) {
+				case M68K_CPU_SIZE_BYTE: SStream_concat0(O, ".b"); break;
+				case M68K_CPU_SIZE_WORD: SStream_concat0(O, ".w"); break;
+				case M68K_CPU_SIZE_LONG: SStream_concat0(O, ".l"); break;
+				case M68K_CPU_SIZE_NONE: break;
+			}
+			break;
+
+		case M68K_SIZE_TYPE_FPU :
+			switch (ext->op_size.fpu_size) {
+				case M68K_FPU_SIZE_SINGLE: SStream_concat0(O, ".s"); break;
+				case M68K_FPU_SIZE_DOUBLE: SStream_concat0(O, ".d"); break;
+				case M68K_FPU_SIZE_EXTENDED: SStream_concat0(O, ".x"); break;
+				case M68K_FPU_SIZE_NONE: break;
+			}
+			break;
+	}
+
+	SStream_concat0(O, " ");
+
+	// this one is a bit spacial so we do special things
+
+	if (MI->Opcode == M68K_INS_CAS2) {
+		int reg_value_0, reg_value_1;
+		printAddressingMode(O, info->pc, ext, &ext->operands[0]); SStream_concat0(O, ",");
+		printAddressingMode(O, info->pc, ext, &ext->operands[1]); SStream_concat0(O, ",");
+		reg_value_0 = ext->operands[2].register_bits >> 4;
+		reg_value_1 = ext->operands[2].register_bits & 0xf;
+		SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]);
+		return;
+	}
+
+	for (i  = 0; i < ext->op_count; ++i) {
+		printAddressingMode(O, info->pc, ext, &ext->operands[i]);
+		if ((i + 1) != ext->op_count)
+			SStream_concat(O, ",%s", s_spacing);
+	}
+#endif
+}
+
+const char* M68K_reg_name(csh handle, unsigned int reg)
+{
+#ifdef CAPSTONE_DIET
+	return NULL;
+#else
+	return s_reg_names[(int)reg];
+#endif
+}
+
+void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id)
+{
+	insn->id = id; // These id's matches for 68k
+}
+
+const char* M68K_insn_name(csh handle, unsigned int id)
+{
+#ifdef CAPSTONE_DIET
+	return NULL;
+#else
+	return s_instruction_names[id];
+#endif
+}
+
+#ifndef CAPSTONE_DIET
+static name_map group_name_maps[] = {
+	{ M68K_GRP_INVALID , NULL },
+	{ M68K_GRP_JUMP, "jump" },
+	{ M68K_GRP_RET , "ret" },
+	{ M68K_GRP_IRET, "iret" },
+	{ M68K_GRP_BRANCH_RELATIVE, "branch_relative" },
+};
+#endif
+
+const char *M68K_group_name(csh handle, unsigned int id)
+{
+#ifndef CAPSTONE_DIET
+	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
+#else
+	return NULL;
+#endif
+}
+
--- a/arch/M68K/M68KInstPrinter.h
+++ b/arch/M68K/M68KInstPrinter.h
@ -0,0 +1,23 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
+
+#ifndef CS_M68KINSTPRINTER_H
+#define CS_M68KINSTPRINTER_H
+
+#include "capstone/capstone.h"
+#include "../../MCRegisterInfo.h"
+#include "../../MCInst.h"
+
+struct SStream;
+
+void M68K_init(MCRegisterInfo *MRI);
+
+void M68K_printInst(MCInst* MI, struct SStream* O, void* Info);
+const char* M68K_reg_name(csh handle, unsigned int reg);
+void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id);
+const char *M68K_insn_name(csh handle, unsigned int id);
+const char* M68K_group_name(csh handle, unsigned int id);
+void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci);
+
+#endif
+
--- a/arch/M68K/M68KModule.c
+++ b/arch/M68K/M68KModule.c
@ -0,0 +1,42 @@
+/* Capstone Disassembly Engine */
+/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
+
+#ifdef CAPSTONE_HAS_M68K
+
+#include "../../utils.h"
+#include "../../MCRegisterInfo.h"
+#include "M68KDisassembler.h"
+#include "M68KInstPrinter.h"
+#include "M68KModule.h"
+
+cs_err M68K_global_init(cs_struct *ud)
+{
+	m68k_info *info;
+
+	info = cs_mem_malloc(sizeof(m68k_info));
+	if (!info) {
+		return CS_ERR_MEM;
+	}
+
+	ud->printer = M68K_printInst;
+	ud->printer_info = info;
+	ud->getinsn_info = NULL;
+	ud->disasm = M68K_getInstruction;
+	ud->skipdata_size = 2;
+	ud->post_printer = NULL;
+
+	ud->reg_name = M68K_reg_name;
+	ud->insn_id = M68K_get_insn_id;
+	ud->insn_name = M68K_insn_name;
+	ud->group_name = M68K_group_name;
+
+	return CS_ERR_OK;
+}
+
+cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value)
+{
+	return CS_ERR_OK;
+}
+
+#endif
+
--- a/arch/M68K/M68KModule.h
+++ b/arch/M68K/M68KModule.h
@ -0,0 +1,12 @@
+/* Capstone Disassembly Engine */
+/* By Travis Finkenauer <tmfinken@gmail.com>, 2018 */
+
+#ifndef CS_M68K_MODULE_H
+#define CS_M68K_MODULE_H
+
+#include "../../utils.h"
+
+cs_err M68K_global_init(cs_struct *ud);
+cs_err M68K_option(cs_struct *handle, cs_opt_type type, size_t value);
+
+#endif
--- a/arch/Mips/MipsDisassembler.c
+++ b/arch/Mips/MipsDisassembler.c
@ -12,14 +12,14 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifdef CAPSTONE_HAS_MIPS

 #include <stdio.h>
 #include <string.h>

-#include <platform.h>
+#include "capstone/platform.h"

 #include "../../utils.h"

@ -46,6 +46,15 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);

+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder);
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder);

@ -118,6 +127,16 @@ static DecodeStatus DecodeBranchTarget21(MCInst *Inst,
 static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
 		unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder);

+// DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+
+// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
+// shifted left by 1 bit.
+static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder);
+
 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
 // shifted left by 1 bit.
 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
@ -131,12 +150,33 @@ static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
 static DecodeStatus DecodeMem(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);

-static DecodeStatus DecodeCachePref(MCInst *Inst,
-		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);
+static DecodeStatus DecodeCacheOp(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSyncI(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);

 static DecodeStatus DecodeMSA128Mem(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);

+static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
 static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);

@ -146,15 +186,30 @@ static DecodeStatus DecodeMemMMImm16(MCInst *Inst,
 static DecodeStatus DecodeFMem(MCInst *Inst, unsigned Insn,
 		uint64_t Address, const MCRegisterInfo *Decoder);

-static DecodeStatus DecodeCOP2Mem(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const MCRegisterInfo *Decoder);
+static DecodeStatus DecodeFMem2(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder);

-static DecodeStatus DecodeCOP3Mem(MCInst *Inst, unsigned Insn,
-		uint64_t Address, const MCRegisterInfo *Decoder);
+static DecodeStatus DecodeFMem3(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder);

 static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);

+static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeLiSimm7(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm4(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder);
+
 static DecodeStatus DecodeSimm16(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);

@ -175,6 +230,18 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
 static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder);

+static DecodeStatus DecodeSimm9SP(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeANDI16Imm(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeUImm5lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder);
+
 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
 /// handle.
 static DecodeStatus DecodeINSVE_DF_4(MCInst *MI,
@ -198,6 +265,14 @@ static DecodeStatus DecodeBgtzGroupBranch_4(MCInst *MI,
 static DecodeStatus DecodeBlezGroupBranch_4(MCInst *MI,
 		uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);

+static DecodeStatus DecodeRegListOperand(MCInst *Inst,
+		uint32_t insn, uint64_t Address, const MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeRegListOperand16(MCInst *Inst,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);
+
+static DecodeStatus DecodeMovePRegPair(MCInst *Inst,
+		uint32_t insn, uint64_t Address, MCRegisterInfo *Decoder);

 #define GET_SUBTARGETINFO_ENUM
 #include "MipsGenSubtargetInfo.inc"
@ -265,19 +340,22 @@ static uint64_t getFeatureBits(int mode)
 void Mips_init(MCRegisterInfo *MRI)
 {
 	// InitMCRegisterInfo(MipsRegDesc, 394, RA, PC,
-	// 		MipsMCRegisterClasses, 48,
+	// 		MipsMCRegisterClasses, 62,
 	// 		MipsRegUnitRoots,
 	// 		273,
 	// 		MipsRegDiffLists,
+	// 		MipsLaneMaskLists,
 	// 		MipsRegStrings,
+	// 		MipsRegClassStrings,
 	// 		MipsSubRegIdxLists,
 	// 		12,
 	// 		MipsSubRegIdxRanges,
 	// 		MipsRegEncodingTable);

+
 	MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, 394,
 			0, 0,
-			MipsMCRegisterClasses, 48,
+			MipsMCRegisterClasses, 62,
 			0, 0,
 			MipsRegDiffLists,
 			0,
@ -285,36 +363,44 @@ void Mips_init(MCRegisterInfo *MRI)
 			0);
 }

+/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
+/// according to the given endianess.
+static void readInstruction16(unsigned char *code, uint32_t *insn,
+		bool isBigEndian)
+{
+	// We want to read exactly 2 Bytes of data.
+	if (isBigEndian)
+		*insn = (code[0] << 8) | code[1];
+	else
+		*insn = (code[1] << 8) | code[0];
+}
+
 /// readInstruction - read four bytes from the MemoryObject
 /// and return 32 bit word sorted according to the given endianess
-static DecodeStatus readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
+static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips)
 {
+	// High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
+	// always precede the low 16 bits in the instruction stream (that is, they
+	// are placed at lower addresses in the instruction stream).
+	//
+	// microMIPS byte ordering:
+	//   Big-endian:    0 | 1 | 2 | 3
+	//   Little-endian: 1 | 0 | 3 | 2
+
 	// We want to read exactly 4 Bytes of data.
 	if (isBigEndian) {
 		// Encoded as a big-endian 32-bit word in the stream.
-		*insn = (code[3] <<  0) |
-			(code[2] <<  8) |
-			(code[1] << 16) |
-			(((uint32_t) code[0]) << 24);
+		*insn =
+			(code[3] << 0) | (code[2] << 8) | (code[1] << 16) | ((uint32_t) code[0] << 24);
 	} else {
-		// Encoded as a small-endian 32-bit word in the stream.
-		// Little-endian byte ordering:
-		//   mips32r2:   4 | 3 | 2 | 1
-		//   microMIPS:  2 | 1 | 4 | 3
 		if (isMicroMips) {
-			*insn = (code[2] <<  0) |
-				(code[3] <<  8) |
-				(code[0] << 16) |
-				(((uint32_t) code[1]) << 24);
+			*insn = (code[2] << 0) | (code[3] << 8) | (code[0] << 16) |
+				((uint32_t) code[1] << 24);
 		} else {
-			*insn = (code[0] <<  0) |
-				(code[1] <<  8) |
-				(code[2] << 16) |
-				(((uint32_t) code[3]) << 24);
+			*insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) |
+				((uint32_t) code[3] << 24);
 		}
 	}
-
-	return MCDisassembler_Success;
 }

 static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
@ -325,20 +411,31 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 	uint32_t Insn;
 	DecodeStatus Result;

-	if (code_len < 4)
-		// not enough data
-		return MCDisassembler_Fail;
-
 	if (instr->flat_insn->detail) {
-		memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
+		memset(instr->flat_insn->detail, 0, offsetof(cs_detail, mips)+sizeof(cs_mips));
 	}

-	Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian,
-			mode & CS_MODE_MICRO);
-	if (Result == MCDisassembler_Fail)
-		return MCDisassembler_Fail;
-
 	if (mode & CS_MODE_MICRO) {
+		if (code_len < 2)
+			// not enough data
+			return MCDisassembler_Fail;
+
+		readInstruction16((unsigned char*)code, &Insn, isBigEndian);
+
+		// Calling the auto-generated decoder function.
+		Result = decodeInstruction(DecoderTableMicroMips16, instr, Insn, Address, MRI, mode);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 2;
+			return Result;
+		}
+
+		if (code_len < 4)
+			// not enough data
+			return MCDisassembler_Fail;
+
+		readInstruction32((unsigned char*)code, &Insn, isBigEndian, true);
+
+		//DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
 		// Calling the auto-generated decoder function.
 		Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, MRI, mode);
 		if (Result != MCDisassembler_Fail) {
@ -348,9 +445,13 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 		return MCDisassembler_Fail;
 	}

-#if 0
-	// TODO: properly handle this in the future with MIPS1/2 modes
-	if (((mode & CS_MODE_32) == 0) && ((mode & CS_MODE_MIPS3) == 0)) {	// COP3
+	if (code_len < 4)
+		// not enough data
+		return MCDisassembler_Fail;
+
+	readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
+
+	if ((mode & CS_MODE_MIPS2) && ((mode & CS_MODE_MIPS3) == 0)) {
 		// DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
 		Result = decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, MRI, mode);
 		if (Result != MCDisassembler_Fail) {
@ -358,9 +459,8 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 			return Result;
 		}
 	}
-#endif

-	if (((mode & CS_MODE_MIPS32R6) != 0) && ((mode & CS_MODE_MIPSGP64) != 0)) {
+	if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) {
 		// DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
 		Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
 				Address, MRI, mode);
@ -370,7 +470,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 		}
 	}

-	if ((mode & CS_MODE_MIPS32R6) != 0) {
+	if (mode & CS_MODE_MIPS32R6) {
 		// DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
 		Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn,
 				Address, MRI, mode);
@ -380,6 +480,17 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
 		}
 	}

+	if (mode & CS_MODE_MIPS64) {
+		// DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
+		Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
+				Address, MRI, mode);
+		if (Result != MCDisassembler_Fail) {
+			*Size = 4;
+			return Result;
+		}
+	}
+
+	// DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
 	// Calling the auto-generated decoder function.
 	Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
 	if (Result != MCDisassembler_Fail) {
@ -403,63 +514,8 @@ bool Mips_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *i
 	return status == MCDisassembler_Success;
 }

-static DecodeStatus Mips64Disassembler_getInstruction(int mode, MCInst *instr,
-		const uint8_t *code, size_t code_len,
-		uint16_t *Size,
-		uint64_t Address, bool isBigEndian, MCRegisterInfo *MRI)
-{
-	uint32_t Insn;
-	DecodeStatus Result;
-
-	if (code_len < 4)
-		// not enough data
-		return MCDisassembler_Fail;
-
-	if (instr->flat_insn->detail) {
-		memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
-	}
-
-	Result = readInstruction32((unsigned char*)code, &Insn, isBigEndian, false);
-	if (Result == MCDisassembler_Fail)
-		return MCDisassembler_Fail;
-
-	if (instr->flat_insn->detail) {
-		memset(instr->flat_insn->detail, 0, sizeof(cs_detail));
-	}
-
-	// Calling the auto-generated decoder function.
-	Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, MRI, mode);
-	if (Result != MCDisassembler_Fail) {
-		*Size = 4;
-		return Result;
-	}
-
-	// If we fail to decode in Mips64 decoder space we can try in Mips32
-	Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, MRI, mode);
-	if (Result != MCDisassembler_Fail) {
-		*Size = 4;
-		return Result;
-	}
-
-	return MCDisassembler_Fail;
-}
-
-bool Mips64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr,
-		uint16_t *size, uint64_t address, void *info)
-{
-	cs_struct *handle = (cs_struct *)(uintptr_t)ud;
-
-	DecodeStatus status = Mips64Disassembler_getInstruction(handle->mode, instr,
-			code, code_len, size, address,
-			MODE_IS_BIG_ENDIAN(handle->mode), (MCRegisterInfo *)info);
-
-	return status == MCDisassembler_Success;
-}
-
 static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
 {
-	//MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
-	//return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
 	const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
 	return rc->RegsBegin[RegNo];
 }
@ -492,9 +548,6 @@ static DecodeStatus DecodeINSVE_DF_4(MCInst *MI, uint32_t insn,
 	if (NSize == 0 || RegDecoder == NULL)
 		return MCDisassembler_Fail;

-	if (RegDecoder == NULL)
-		return MCDisassembler_Fail;
-
 	// $wd
 	tmp = fieldFromInstruction(insn, 6, 5);
 	if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail)
@ -776,6 +829,45 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst,
 	return MCDisassembler_Success;
 }

+static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 7)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, Mips_GPRMM16RegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 7)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, Mips_GPRMM16ZeroRegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst,
+		unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Reg;
+
+	if (RegNo > 7)
+		return MCDisassembler_Fail;
+
+	Reg = getReg(Decoder, Mips_GPRMM16MovePRegClassID, RegNo);
+	MCOperand_CreateReg0(Inst, Reg);
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
 {
@ -792,7 +884,8 @@ static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst,
 static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
 		unsigned RegNo, uint64_t Address, const MCRegisterInfo *Decoder)
 {
-	if (Inst->csh->mode & CS_MODE_64)
+	// if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
+	if (Inst->csh->mode & CS_MODE_MIPS64)
 		return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);

 	return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
@ -888,11 +981,12 @@ static DecodeStatus DecodeMem(MCInst *Inst,
 	int Offset = SignExtend32(Insn & 0xffff, 16);
 	unsigned Reg = fieldFromInstruction(Insn, 16, 5);
 	unsigned Base = fieldFromInstruction(Insn, 21, 5);
+	int opcode = MCInst_getOpcode(Inst);

 	Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
 	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);

-	if (MCInst_getOpcode(Inst) == Mips_SC){
+	if (opcode == Mips_SC || opcode == Mips_SCD) {
 		MCOperand_CreateReg0(Inst, Reg);
 	}

@ -903,8 +997,8 @@ static DecodeStatus DecodeMem(MCInst *Inst,
 	return MCDisassembler_Success;
 }

-static DecodeStatus DecodeCachePref(MCInst *Inst,
-		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+static DecodeStatus DecodeCacheOp(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
 {
 	int Offset = SignExtend32(Insn & 0xffff, 16);
 	unsigned Hint = fieldFromInstruction(Insn, 16, 5);
@ -919,6 +1013,52 @@ static DecodeStatus DecodeCachePref(MCInst *Inst,
 	return MCDisassembler_Success;
 }

+static DecodeStatus DecodeCacheOpMM(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int Offset = SignExtend32(Insn & 0xfff, 12);
+	unsigned Base = fieldFromInstruction(Insn, 16, 5);
+	unsigned Hint = fieldFromInstruction(Insn, 21, 5);
+
+	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+	MCOperand_CreateReg0(Inst, Base);
+	MCOperand_CreateImm0(Inst, Offset);
+	MCOperand_CreateImm0(Inst, Hint);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeCacheOpR6(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int Offset = fieldFromInstruction(Insn, 7, 9);
+	unsigned Hint = fieldFromInstruction(Insn, 16, 5);
+	unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+	MCOperand_CreateReg0(Inst, Base);
+	MCOperand_CreateImm0(Inst, Offset);
+	MCOperand_CreateImm0(Inst, Hint);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSyncI(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int Offset = SignExtend32(Insn & 0xffff, 16);
+	unsigned Base = fieldFromInstruction(Insn, 21, 5);
+
+	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+	MCOperand_CreateReg0(Inst, Base);
+	MCOperand_CreateImm0(Inst, Offset);
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
 		uint64_t Address, const MCRegisterInfo *Decoder)
 {
@ -966,6 +1106,101 @@ static DecodeStatus DecodeMSA128Mem(MCInst *Inst, unsigned Insn,
 	return MCDisassembler_Success;
 }

+static DecodeStatus DecodeMemMMImm4(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Offset = Insn & 0xf;
+	unsigned Reg = fieldFromInstruction(Insn, 7, 3);
+	unsigned Base = fieldFromInstruction(Insn, 4, 3);
+
+	switch (MCInst_getOpcode(Inst)) {
+		case Mips_LBU16_MM:
+		case Mips_LHU16_MM:
+		case Mips_LW16_MM:
+			if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
+					== MCDisassembler_Fail)
+				return MCDisassembler_Fail;
+			break;
+		case Mips_SB16_MM:
+		case Mips_SH16_MM:
+		case Mips_SW16_MM:
+			if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
+					== MCDisassembler_Fail)
+				return MCDisassembler_Fail;
+			break;
+	}
+
+	if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
+			== MCDisassembler_Fail)
+		return MCDisassembler_Fail;
+
+	switch (MCInst_getOpcode(Inst)) {
+		case Mips_LBU16_MM:
+			if (Offset == 0xf)
+				MCOperand_CreateImm0(Inst, -1);
+			else
+				MCOperand_CreateImm0(Inst, Offset);
+			break;
+		case Mips_SB16_MM:
+			MCOperand_CreateImm0(Inst, Offset);
+			break;
+		case Mips_LHU16_MM:
+		case Mips_SH16_MM:
+			MCOperand_CreateImm0(Inst, Offset << 1);
+			break;
+		case Mips_LW16_MM:
+		case Mips_SW16_MM:
+			MCOperand_CreateImm0(Inst, Offset << 2);
+			break;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Offset = Insn & 0x1F;
+	unsigned Reg = fieldFromInstruction(Insn, 5, 5);
+
+	Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+
+	MCOperand_CreateReg0(Inst, Reg);
+	MCOperand_CreateReg0(Inst, Mips_SP);
+	MCOperand_CreateImm0(Inst, Offset << 2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Offset = Insn & 0x7F;
+	unsigned Reg = fieldFromInstruction(Insn, 7, 3);
+
+	Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
+
+	MCOperand_CreateReg0(Inst, Reg);
+	MCOperand_CreateReg0(Inst, Mips_GP);
+	MCOperand_CreateImm0(Inst, Offset << 2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int Offset = SignExtend32(Insn & 0xf, 4);
+
+	if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == MCDisassembler_Fail)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateReg0(Inst, Mips_SP);
+	MCOperand_CreateImm0(Inst, Offset * 4);
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
 {
@ -976,12 +1211,26 @@ static DecodeStatus DecodeMemMMImm12(MCInst *Inst,
 	Reg = getReg(Decoder, Mips_GPR32RegClassID, Reg);
 	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);

-	if (MCInst_getOpcode(Inst) == Mips_SC_MM)
-		MCOperand_CreateReg0(Inst, Reg);
+	switch (MCInst_getOpcode(Inst)) {
+		case Mips_SWM32_MM:
+		case Mips_LWM32_MM:
+			if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
+					== MCDisassembler_Fail)
+				return MCDisassembler_Fail;
+			MCOperand_CreateReg0(Inst, Base);
+			MCOperand_CreateImm0(Inst, Offset);
+			break;
+		case Mips_SC_MM:
+			MCOperand_CreateReg0(Inst, Reg);
+			// fallthrough
+		default:
+			MCOperand_CreateReg0(Inst, Reg);
+			if (MCInst_getOpcode(Inst) == Mips_LWP_MM || MCInst_getOpcode(Inst) == Mips_SWP_MM)
+				MCOperand_CreateReg0(Inst, Reg + 1);

-	MCOperand_CreateReg0(Inst, Reg);
-	MCOperand_CreateReg0(Inst, Base);
-	MCOperand_CreateImm0(Inst, Offset);
+			MCOperand_CreateReg0(Inst, Base);
+			MCOperand_CreateImm0(Inst, Offset);
+	}

 	return MCDisassembler_Success;
 }
@ -1020,8 +1269,8 @@ static DecodeStatus DecodeFMem(MCInst *Inst,
 	return MCDisassembler_Success;
 }

-static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
-		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+static DecodeStatus DecodeFMem2(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
 {
 	int Offset = SignExtend32(Insn & 0xffff, 16);
 	unsigned Reg = fieldFromInstruction(Insn, 16, 5);
@ -1037,8 +1286,8 @@ static DecodeStatus DecodeCOP2Mem(MCInst *Inst,
 	return MCDisassembler_Success;
 }

-static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
-		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
+static DecodeStatus DecodeFMem3(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
 {
 	int Offset = SignExtend32(Insn & 0xffff, 16);
 	unsigned Reg = fieldFromInstruction(Insn, 16, 5);
@ -1054,6 +1303,23 @@ static DecodeStatus DecodeCOP3Mem(MCInst *Inst,
 	return MCDisassembler_Success;
 }

+static DecodeStatus DecodeFMemCop2R6(MCInst *Inst,
+		unsigned Insn, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int Offset = SignExtend32(Insn & 0x07ff, 11);
+	unsigned Reg = fieldFromInstruction(Insn, 16, 5);
+	unsigned Base = fieldFromInstruction(Insn, 11, 5);
+
+	Reg = getReg(Decoder, Mips_COP2RegClassID, Reg);
+	Base = getReg(Decoder, Mips_GPR32RegClassID, Base);
+
+	MCOperand_CreateReg0(Inst, Reg);
+	MCOperand_CreateReg0(Inst, Base);
+	MCOperand_CreateImm0(Inst, Offset);
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
 {
@ -1264,6 +1530,22 @@ static DecodeStatus DecodeBranchTarget26(MCInst *Inst,
 	return MCDisassembler_Success;
 }

+static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int32_t BranchOffset = SignExtend32(Offset, 7) * 2;
+	MCOperand_CreateImm0(Inst, BranchOffset);
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst,
+		unsigned Offset, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int32_t BranchOffset = SignExtend32(Offset, 10) * 2;
+	MCOperand_CreateImm0(Inst, BranchOffset);
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeBranchTargetMM(MCInst *Inst,
 		unsigned Offset, uint64_t Address, const MCRegisterInfo *Decoder)
 {
@ -1282,10 +1564,51 @@ static DecodeStatus DecodeJumpTargetMM(MCInst *Inst,
 	return MCDisassembler_Success;
 }

+static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	if (Value == 0)
+		MCOperand_CreateImm0(Inst, 1);
+	else if (Value == 0x7)
+		MCOperand_CreateImm0(Inst, -1);
+	else
+		MCOperand_CreateImm0(Inst, Value << 2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeUImm6Lsl2(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	MCOperand_CreateImm0(Inst, Value << 2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeLiSimm7(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	if (Value == 0x7F)
+		MCOperand_CreateImm0(Inst, -1);
+	else
+		MCOperand_CreateImm0(Inst, Value);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm4(MCInst *Inst,
+		unsigned Value, uint64_t Address, MCRegisterInfo *Decoder)
+{
+	MCOperand_CreateImm0(Inst, SignExtend32(Value, 4));
+
+	return MCDisassembler_Success;
+}
+
 static DecodeStatus DecodeSimm16(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
 {
 	MCOperand_CreateImm0(Inst, SignExtend32(Insn, 16));
+
 	return MCDisassembler_Success;
 }

@ -1294,6 +1617,7 @@ static DecodeStatus DecodeLSAImm(MCInst *Inst,
 {
 	// We add one to the immediate field as it was encoded as 'imm - 1'.
 	MCOperand_CreateImm0(Inst, Insn + 1);
+
 	return MCDisassembler_Success;
 }

@ -1304,14 +1628,17 @@ static DecodeStatus DecodeInsSize(MCInst *Inst,
 	int Pos = (int)MCOperand_getImm(MCInst_getOperand(Inst, 2));
 	int Size = (int) Insn - Pos + 1;
 	MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
+
 	return MCDisassembler_Success;
 }

 static DecodeStatus DecodeExtSize(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
 {
-	int Size = (int) Insn  + 1;
+	int Size = (int)Insn  + 1;
+
 	MCOperand_CreateImm0(Inst, SignExtend32(Size, 16));
+
 	return MCDisassembler_Success;
 }

@ -1319,6 +1646,7 @@ static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
 {
 	MCOperand_CreateImm0(Inst, SignExtend32(Insn, 19) * 4);
+
 	return MCDisassembler_Success;
 }

@ -1326,6 +1654,139 @@ static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst,
 		unsigned Insn, uint64_t Address, const MCRegisterInfo *Decoder)
 {
 	MCOperand_CreateImm0(Inst, SignExtend32(Insn, 18) * 8);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm9SP(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	int32_t DecodedValue;
+
+	switch (Insn) {
+		case 0: DecodedValue = 256; break;
+		case 1: DecodedValue = 257; break;
+		case 510: DecodedValue = -258; break;
+		case 511: DecodedValue = -257; break;
+		default: DecodedValue = SignExtend32(Insn, 9); break;
+	}
+	MCOperand_CreateImm0(Inst, DecodedValue * 4);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeANDI16Imm(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	// Insn must be >= 0, since it is unsigned that condition is always true.
+	// assert(Insn < 16);
+	int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
+		255, 32768, 65535};
+
+	if (Insn >= 16)
+		return MCDisassembler_Fail;
+
+	MCOperand_CreateImm0(Inst, DecodedValues[Insn]);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeUImm5lsl2(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	MCOperand_CreateImm0(Inst, Insn << 2);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Insn,
+		uint64_t Address, const MCRegisterInfo *Decoder)
+{
+	unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5,
+		Mips_S6, Mips_FP};
+	unsigned RegNum;
+	unsigned int i;
+
+	unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
+	// Empty register lists are not allowed.
+	if (RegLst == 0)
+		return MCDisassembler_Fail;
+
+	RegNum = RegLst & 0xf;
+	for (i = 0; i < MIN(RegNum, ARR_SIZE(Regs)); i++)
+		MCOperand_CreateReg0(Inst, Regs[i]);
+
+	if (RegLst & 0x10)
+		MCOperand_CreateReg0(Inst, Mips_RA);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeRegListOperand16(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned Regs[] = {Mips_S0, Mips_S1, Mips_S2, Mips_S3};
+	unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
+	unsigned RegNum = RegLst & 0x3;
+	unsigned int i;
+
+	for (i = 0; i <= RegNum; i++)
+		MCOperand_CreateReg0(Inst, Regs[i]);
+
+	MCOperand_CreateReg0(Inst, Mips_RA);
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
+
+	switch (RegPair) {
+		default:
+			return MCDisassembler_Fail;
+		case 0:
+			MCOperand_CreateReg0(Inst, Mips_A1);
+			MCOperand_CreateReg0(Inst, Mips_A2);
+			break;
+		case 1:
+			MCOperand_CreateReg0(Inst, Mips_A1);
+			MCOperand_CreateReg0(Inst, Mips_A3);
+			break;
+		case 2:
+			MCOperand_CreateReg0(Inst, Mips_A2);
+			MCOperand_CreateReg0(Inst, Mips_A3);
+			break;
+		case 3:
+			MCOperand_CreateReg0(Inst, Mips_A0);
+			MCOperand_CreateReg0(Inst, Mips_S5);
+			break;
+		case 4:
+			MCOperand_CreateReg0(Inst, Mips_A0);
+			MCOperand_CreateReg0(Inst, Mips_S6);
+			break;
+		case 5:
+			MCOperand_CreateReg0(Inst, Mips_A0);
+			MCOperand_CreateReg0(Inst, Mips_A1);
+			break;
+		case 6:
+			MCOperand_CreateReg0(Inst, Mips_A0);
+			MCOperand_CreateReg0(Inst, Mips_A2);
+			break;
+		case 7:
+			MCOperand_CreateReg0(Inst, Mips_A0);
+			MCOperand_CreateReg0(Inst, Mips_A3);
+			break;
+	}
+
+	return MCDisassembler_Success;
+}
+
+static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, unsigned Insn,
+		uint64_t Address, MCRegisterInfo *Decoder)
+{
+	MCOperand_CreateImm0(Inst, SignExtend32(Insn, 23) * 4);
 	return MCDisassembler_Success;
 }

--- a/arch/Mips/MipsDisassembler.h
+++ b/arch/Mips/MipsDisassembler.h
@ -1,12 +1,10 @@
 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_MIPSDISASSEMBLER_H
 #define CS_MIPSDISASSEMBLER_H

-#include "../../include/capstone.h"
-
-#include "../../include/capstone.h"
+#include "capstone/capstone.h"
 #include "../../MCRegisterInfo.h"

 void Mips_init(MCRegisterInfo *MRI);
@ -14,7 +12,4 @@ void Mips_init(MCRegisterInfo *MRI);
 bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
 		MCInst *instr, uint16_t *size, uint64_t address, void *info);

-bool Mips64_getInstruction(csh handle, const uint8_t *code, size_t code_len,
-		MCInst *instr, uint16_t *size, uint64_t address, void *info);
-
 #endif
--- a/arch/Mips/MipsGenAsmWriter.inc
+++ b/arch/Mips/MipsGenAsmWriter.inc
--- a/arch/Mips/MipsGenDisassemblerTables.inc
+++ b/arch/Mips/MipsGenDisassemblerTables.inc
--- a/arch/Mips/MipsGenInstrInfo.inc
+++ b/arch/Mips/MipsGenInstrInfo.inc
--- a/arch/Mips/MipsGenRegisterInfo.inc
+++ b/arch/Mips/MipsGenRegisterInfo.inc
--- a/arch/Mips/MipsGenSubtargetInfo.inc
+++ b/arch/Mips/MipsGenSubtargetInfo.inc
@ -7,7 +7,7 @@
 \*===----------------------------------------------------------------------===*/

 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */


 #ifdef GET_SUBTARGETINFO_ENUM
@ -16,35 +16,35 @@
 #define Mips_FeatureCnMips (1ULL << 0)
 #define Mips_FeatureDSP (1ULL << 1)
 #define Mips_FeatureDSPR2 (1ULL << 2)
-#define Mips_FeatureEABI (1ULL << 3)
-#define Mips_FeatureFP64Bit (1ULL << 4)
-#define Mips_FeatureFPXX (1ULL << 5)
-#define Mips_FeatureGP64Bit (1ULL << 6)
-#define Mips_FeatureMSA (1ULL << 7)
-#define Mips_FeatureMicroMips (1ULL << 8)
-#define Mips_FeatureMips1 (1ULL << 9)
-#define Mips_FeatureMips2 (1ULL << 10)
-#define Mips_FeatureMips3 (1ULL << 11)
-#define Mips_FeatureMips3_32 (1ULL << 12)
-#define Mips_FeatureMips3_32r2 (1ULL << 13)
-#define Mips_FeatureMips4 (1ULL << 14)
-#define Mips_FeatureMips4_32 (1ULL << 15)
-#define Mips_FeatureMips4_32r2 (1ULL << 16)
-#define Mips_FeatureMips5 (1ULL << 17)
-#define Mips_FeatureMips5_32r2 (1ULL << 18)
-#define Mips_FeatureMips16 (1ULL << 19)
-#define Mips_FeatureMips32 (1ULL << 20)
-#define Mips_FeatureMips32r2 (1ULL << 21)
-#define Mips_FeatureMips32r6 (1ULL << 22)
-#define Mips_FeatureMips64 (1ULL << 23)
-#define Mips_FeatureMips64r2 (1ULL << 24)
-#define Mips_FeatureMips64r6 (1ULL << 25)
-#define Mips_FeatureN32 (1ULL << 26)
-#define Mips_FeatureN64 (1ULL << 27)
-#define Mips_FeatureNaN2008 (1ULL << 28)
-#define Mips_FeatureNoABICalls (1ULL << 29)
-#define Mips_FeatureNoOddSPReg (1ULL << 30)
-#define Mips_FeatureO32 (1ULL << 31)
+#define Mips_FeatureFP64Bit (1ULL << 3)
+#define Mips_FeatureFPXX (1ULL << 4)
+#define Mips_FeatureGP64Bit (1ULL << 5)
+#define Mips_FeatureMSA (1ULL << 6)
+#define Mips_FeatureMicroMips (1ULL << 7)
+#define Mips_FeatureMips1 (1ULL << 8)
+#define Mips_FeatureMips2 (1ULL << 9)
+#define Mips_FeatureMips3 (1ULL << 10)
+#define Mips_FeatureMips3_32 (1ULL << 11)
+#define Mips_FeatureMips3_32r2 (1ULL << 12)
+#define Mips_FeatureMips4 (1ULL << 13)
+#define Mips_FeatureMips4_32 (1ULL << 14)
+#define Mips_FeatureMips4_32r2 (1ULL << 15)
+#define Mips_FeatureMips5 (1ULL << 16)
+#define Mips_FeatureMips5_32r2 (1ULL << 17)
+#define Mips_FeatureMips16 (1ULL << 18)
+#define Mips_FeatureMips32 (1ULL << 19)
+#define Mips_FeatureMips32r2 (1ULL << 20)
+#define Mips_FeatureMips32r3 (1ULL << 21)
+#define Mips_FeatureMips32r5 (1ULL << 22)
+#define Mips_FeatureMips32r6 (1ULL << 23)
+#define Mips_FeatureMips64 (1ULL << 24)
+#define Mips_FeatureMips64r2 (1ULL << 25)
+#define Mips_FeatureMips64r3 (1ULL << 26)
+#define Mips_FeatureMips64r5 (1ULL << 27)
+#define Mips_FeatureMips64r6 (1ULL << 28)
+#define Mips_FeatureNaN2008 (1ULL << 29)
+#define Mips_FeatureNoABICalls (1ULL << 30)
+#define Mips_FeatureNoOddSPReg (1ULL << 31)
 #define Mips_FeatureSingleFloat (1ULL << 32)
 #define Mips_FeatureVFPU (1ULL << 33)

--- a/arch/Mips/MipsInstPrinter.c
+++ b/arch/Mips/MipsInstPrinter.c
@ -12,11 +12,11 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifdef CAPSTONE_HAS_MIPS

-#include <platform.h>
+#include <capstone/platform.h>
 #include <stdlib.h>
 #include <stdio.h>	// debug
 #include <string.h>
@ -261,6 +261,20 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O)
 	// Load/Store memory operands -- imm($reg)
 	// If PIC target the target is loaded as the
 	// pattern lw $25,%call16($28)
+
+	// opNum can be invalid if instruction had reglist as operand.
+	// MemOperand is always last operand of instruction (base + offset).
+	switch (MCInst_getOpcode(MI)) {
+		default:
+			break;
+		case Mips_SWM32_MM:
+		case Mips_LWM32_MM:
+		case Mips_SWM16_MM:
+		case Mips_LWM16_MM:
+			opNum = MCInst_getNumOperands(MI) - 2;
+			break;
+	}
+
 	set_mem_access(MI, true);
 	printOperand(MI, opNum + 1, O);
 	SStream_concat0(O, "(");
@ -286,6 +300,11 @@ static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
 	SStream_concat0(O, MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
 }

+static void printRegisterPair(MCInst *MI, int opNum, SStream *O)
+{
+	printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, opNum)));
+}
+
 static char *printAlias1(const char *Str, MCInst *MI, unsigned OpNo, SStream *OS)
 {
 	SStream_concat(OS, "%s\t", Str);
@ -312,6 +331,7 @@ static char *printAlias(MCInst *MI, SStream *OS)
 {
 	switch (MCInst_getOpcode(MI)) {
 		case Mips_BEQ:
+		case Mips_BEQ_MM:
 			// beq $zero, $zero, $L2 => b $L2
 			// beq $r0, $zero, $L2 => beqz $r0, $L2
 			if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
@ -319,11 +339,6 @@ static char *printAlias(MCInst *MI, SStream *OS)
 			if (isReg(MI, 1, Mips_ZERO))
 				return printAlias2("beqz", MI, 0, 2, OS);
 			return NULL;
-		case Mips_BEQL:
-			// beql $r0, $zero, $L2 => beqzl $r0, $L2
-			if (isReg(MI, 0, Mips_ZERO) && isReg(MI, 1, Mips_ZERO))
-				return printAlias2("beqzl", MI, 0, 2, OS);
-			return NULL;
 		case Mips_BEQ64:
 			// beq $r0, $zero, $L2 => beqz $r0, $L2
 			if (isReg(MI, 1, Mips_ZERO_64))
@ -334,11 +349,6 @@ static char *printAlias(MCInst *MI, SStream *OS)
 			if (isReg(MI, 1, Mips_ZERO))
 				return printAlias2("bnez", MI, 0, 2, OS);
 			return NULL;
-		case Mips_BNEL:
-			// bnel $r0, $zero, $L2 => bnezl $r0, $L2
-			if (isReg(MI, 1, Mips_ZERO))
-				return printAlias2("bnezl", MI, 0, 2, OS);
-			return NULL;
 		case Mips_BNE64:
 			// bne $r0, $zero, $L2 => bnez $r0, $L2
 			if (isReg(MI, 1, Mips_ZERO_64))
@ -389,6 +399,25 @@ static char *printAlias(MCInst *MI, SStream *OS)
 	}
 }

+static void printRegisterList(MCInst *MI, int opNum, SStream *O)
+{
+	int i, e, reg;
+
+	// - 2 because register List is always first operand of instruction and it is
+	// always followed by memory operand (base + offset).
+	for (i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
+		if (i != opNum)
+			SStream_concat0(O, ", ");
+		reg = MCOperand_getReg(MCInst_getOperand(MI, i));
+		printRegName(O, reg);
+		if (MI->csh->detail) {
+			MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_REG;
+			MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].reg = reg;
+			MI->flat_insn->detail->mips.op_count++;
+		}
+	}
+}
+
 #define PRINT_ALIAS_INSTR
 #include "MipsGenAsmWriter.inc"

--- a/arch/Mips/MipsInstPrinter.h
+++ b/arch/Mips/MipsInstPrinter.h
@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//

 /* Capstone Disassembly Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */

 #ifndef CS_MIPSINSTPRINTER_H
 #define CS_MIPSINSTPRINTER_H
--- a/Show more
+++ b/Show more