From 9daa1ffbac35f553c4b2c0428af0b5cfdd6850d7 Mon Sep 17 00:00:00 2001 From: R3v0LT <87137964+R33v0LT@users.noreply.github.com> Date: Tue, 26 Mar 2024 08:58:56 +0300 Subject: [PATCH] Add HPPA(PA-RISC) architecture (#2265) * Refactor HPPA * Add full HPPA 1.1 instructions support * Add HPPA 1.1 cs tests * Fix HPPA dissassembler * Add HPPA 2.0 instructions * Add HPPA tests * Fix HPPA disasm & printer * Update HPPA tests * Remove unused code * Add implicit register access info & Refactor HPPA main files * Add python bindings/tests and cstests * Fix HPPA disasm wrong decoding * Rewrite invalid test cases * Update HPPA python constants * Make HPPA python test executable * Change HPPA python tests sequence to match c tests * Refactor HPPA main files * Write target instead of offset in details * Add HPPA detail function support in cstest * Rewrite targets in branch tests * Make correct string modifier addition * Add hppa test calls * Add zero operands check * Remove MCOperand array * Change immediate values printing * Add HPPA 2.0 wide support * Fix invalid break instruction decode Remove unused code * Add HPPA to fuzzing tests * Add HPPA to options * Add HPPA to docs * Refactor HPPA * Fix invalid branch insn decoding * Add HPPA to labeler * clang-format hppa files * Document internal structures and minor refactoring * Add missing default statements * Fix invalid default statement --- .github/labeler.yml | 7 + .gitignore | 2 + CMakeLists.txt | 27 +- COMPILE.TXT | 1 + COMPILE_CMAKE.TXT | 3 +- COMPILE_MSVC.TXT | 1 + CREDITS.TXT | 2 +- HACK.TXT | 1 + MCInst.c | 1 + MCInst.h | 1 + Makefile | 18 +- Mapping.c | 1 + Mapping.h | 4 + MathExtras.h | 18 + arch/HPPA/HPPAConstants.h | 74 + arch/HPPA/HPPADisassembler.c | 3837 ++++++++++++++++++++++++ arch/HPPA/HPPADisassembler.h | 13 + arch/HPPA/HPPAInstPrinter.c | 837 ++++++ arch/HPPA/HPPAInstPrinter.h | 25 + arch/HPPA/HPPAMapping.c | 440 +++ arch/HPPA/HPPAMapping.h | 19 + arch/HPPA/HPPAModule.c | 34 + arch/HPPA/HPPAModule.h | 12 + bindings/Makefile | 4 + bindings/const_generator.py | 3 +- bindings/python/Makefile | 2 +- bindings/python/capstone/__init__.py | 16 +- bindings/python/capstone/hppa.py | 72 + bindings/python/capstone/hppa_const.py | 453 +++ bindings/python/setup_cython.py | 2 +- bindings/python/test_all.py | 3 +- bindings/python/test_basic.py | 8 + bindings/python/test_detail.py | 8 + bindings/python/test_hppa.py | 75 + bindings/python/test_iter.py | 9 +- cmake.sh | 3 + config.mk | 2 +- cs.c | 32 +- cstool/cstool.c | 22 + cstool/cstool.h | 1 + cstool/cstool_hppa.c | 87 + include/capstone/capstone.h | 6 + include/capstone/hppa.h | 543 ++++ nmake.bat | 1 + suite/MC/HPPA/alu11.s.cs | 433 +++ suite/MC/HPPA/arith_imm11.s.cs | 97 + suite/MC/HPPA/assist20.s.cs | 32 + suite/MC/HPPA/branch11.s.cs | 9 + suite/MC/HPPA/branch20.s.cs | 43 + suite/MC/HPPA/computation20.s.cs | 63 + suite/MC/HPPA/copr_dw11.s.cs | 41 + suite/MC/HPPA/float11.s.cs | 89 + suite/MC/HPPA/float20.s.cs | 57 + suite/MC/HPPA/index_mem11.s.cs | 88 + suite/MC/HPPA/longimm20.s.cs | 4 + suite/MC/HPPA/mem_mgmt11.s.cs | 25 + suite/MC/HPPA/memory_reference20.s.cs | 99 + suite/MC/HPPA/multimedia20.s.cs | 14 + suite/MC/HPPA/no_grp11.s.cs | 109 + suite/MC/HPPA/sfu11.s.cs | 5 + suite/MC/HPPA/shexdep11.s.cs | 225 ++ suite/MC/HPPA/sysctrl20.s.cs | 49 + suite/MC/HPPA/system_op11.s.cs | 14 + suite/capstone_get_setup.c | 3 + suite/cstest/include/factory.h | 1 + suite/cstest/src/capstone_test.c | 3 + suite/cstest/src/hppa_detail.c | 96 + suite/cstest/src/main.c | 7 + suite/test_c.sh | 3 +- suite/test_corpus.py | 7 + suite/test_corpus3.py | 6 + suite/test_python.sh | 3 +- tests/Makefile | 4 + tests/test_all.sh | 3 +- tests/test_alpha.c | 2 +- tests/test_basic.c | 36 + tests/test_detail.c | 36 + tests/test_hppa.c | 186 ++ tests/test_iter.c | 37 + 79 files changed, 8639 insertions(+), 20 deletions(-) create mode 100644 arch/HPPA/HPPAConstants.h create mode 100644 arch/HPPA/HPPADisassembler.c create mode 100644 arch/HPPA/HPPADisassembler.h create mode 100644 arch/HPPA/HPPAInstPrinter.c create mode 100644 arch/HPPA/HPPAInstPrinter.h create mode 100644 arch/HPPA/HPPAMapping.c create mode 100644 arch/HPPA/HPPAMapping.h create mode 100644 arch/HPPA/HPPAModule.c create mode 100644 arch/HPPA/HPPAModule.h create mode 100644 bindings/python/capstone/hppa.py create mode 100644 bindings/python/capstone/hppa_const.py create mode 100755 bindings/python/test_hppa.py create mode 100644 cstool/cstool_hppa.c create mode 100644 include/capstone/hppa.h create mode 100644 suite/MC/HPPA/alu11.s.cs create mode 100644 suite/MC/HPPA/arith_imm11.s.cs create mode 100644 suite/MC/HPPA/assist20.s.cs create mode 100644 suite/MC/HPPA/branch11.s.cs create mode 100644 suite/MC/HPPA/branch20.s.cs create mode 100644 suite/MC/HPPA/computation20.s.cs create mode 100644 suite/MC/HPPA/copr_dw11.s.cs create mode 100644 suite/MC/HPPA/float11.s.cs create mode 100644 suite/MC/HPPA/float20.s.cs create mode 100644 suite/MC/HPPA/index_mem11.s.cs create mode 100644 suite/MC/HPPA/longimm20.s.cs create mode 100644 suite/MC/HPPA/mem_mgmt11.s.cs create mode 100644 suite/MC/HPPA/memory_reference20.s.cs create mode 100644 suite/MC/HPPA/multimedia20.s.cs create mode 100644 suite/MC/HPPA/no_grp11.s.cs create mode 100644 suite/MC/HPPA/sfu11.s.cs create mode 100644 suite/MC/HPPA/shexdep11.s.cs create mode 100644 suite/MC/HPPA/sysctrl20.s.cs create mode 100644 suite/MC/HPPA/system_op11.s.cs create mode 100644 suite/cstest/src/hppa_detail.c create mode 100644 tests/test_hppa.c diff --git a/.github/labeler.yml b/.github/labeler.yml index 9ae8548cb..a7c03cea9 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -57,6 +57,13 @@ EVM: - include/capstone/evm.h - tests/test_evm.c +HPPA: + - arch/HPPA/* + - cstool/cstool_hppa.c + - include/capstone/hppa.h + - suite/MC/HPPA/* + - tests/test_hppa.c + M680X: - arch/M680X/* - cstool/cstool_m680x.c diff --git a/.gitignore b/.gitignore index 2ffc794f2..34dbd05bb 100644 --- a/.gitignore +++ b/.gitignore @@ -75,6 +75,8 @@ tests/test_bpf tests/test_sh tests/test_riscv tests/test_sh +tests/test_alpha +tests/test_hppa # regress binaries suite/regress/invalid_read_in_print_operand diff --git a/CMakeLists.txt b/CMakeLists.txt index 3f0e9dcc1..2a01ae8b6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -64,8 +64,8 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN) set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64") endif() -set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA) -set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha) +set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA) +set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA) list(LENGTH SUPPORTED_ARCHITECTURES count) math(EXPR count "${count}-1") @@ -169,6 +169,7 @@ set(HEADERS_COMMON include/capstone/platform.h include/capstone/sh.h include/capstone/alpha.h + include/capstone/hppa.h ) set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) @@ -617,6 +618,24 @@ if (CAPSTONE_ALPHA_SUPPORT) set(TEST_SOURCES ${TEST_SOURCES} test_alpha.c) endif () +if(CAPSTONE_HPPA_SUPPORT) + add_definitions(-DCAPSTONE_HAS_HPPA) + set(SOURCES_HPPA + arch/HPPA/HPPADisassembler.c + arch/HPPA/HPPAInstPrinter.c + arch/HPPA/HPPAMapping.c + arch/HPPA/HPPAModule.c + ) + set(HEADERS_HPPA + arch/HPPA/HPPAConstants.h + arch/HPPA/HPPADisassembler.h + arch/HPPA/HPPAInstPrinter.h + arch/HPPA/HPPAMapping.h + arch/HPPA/HPPAModule.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_hppa.c) +endif() + if (CAPSTONE_OSXKERNEL_SUPPORT) add_definitions(-DCAPSTONE_HAS_OSXKERNEL) endif() @@ -642,6 +661,7 @@ set(ALL_SOURCES ${SOURCES_SH} ${SOURCES_TRICORE} ${SOURCES_ALPHA} + ${SOURCES_HPPA} ) set(ALL_HEADERS @@ -666,6 +686,7 @@ set(ALL_HEADERS ${HEADERS_SH} ${HEADERS_TRICORE} ${HEADERS_ALPHA} + ${HEADERS_HPPA} ) ## properties @@ -730,6 +751,7 @@ source_group("Source\\RISCV" FILES ${SOURCES_RISCV}) source_group("Source\\SH" FILES ${SOURCES_SH}) source_group("Source\\TriCore" FILES ${SOURCES_TRICORE}) source_group("Source\\Alpha" FILES ${SOURCES_ALPHA}) +source_group("Source\\HPPA" FILES ${SOURCES_HPPA}) source_group("Include\\Common" FILES ${HEADERS_COMMON}) source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) @@ -752,6 +774,7 @@ source_group("Include\\RISCV" FILES ${HEADERS_RISCV}) source_group("Include\\SH" FILES ${HEADERS_SH}) source_group("Include\\TriCore" FILES ${HEADERS_TRICORE}) source_group("Include\\Alpha" FILES ${HEADERS_ALPHA}) +source_group("Include\\HPPA" FILES ${HEADERS_HPPA}) ## installation if(CAPSTONE_INSTALL) diff --git a/COMPILE.TXT b/COMPILE.TXT index 17e89afc3..5d914ffc6 100644 --- a/COMPILE.TXT +++ b/COMPILE.TXT @@ -89,6 +89,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. /usr/include/capstone/bpf.h /usr/include/capstone/capstone.h /usr/include/capstone/evm.h + /usr/include/capstone/hppa.h /usr/include/capstone/m680x.h /usr/include/capstone/m68k.h /usr/include/capstone/mips.h diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index d36bd792e..dfe491f96 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -22,6 +22,7 @@ Get CMake for free from http://www.cmake.org. - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64. - CAPSTONE_ALPHA_SUPPORT: support Alpha. Run cmake with -DCAPSTONE_ALPHA_SUPPORT=0 to remove Alpha. + - CAPSTONE_HPPA_SUPPORT: support HPPA. Run cmake with -DCAPSTONE_HPPA_SUPPORT=0 to remove HPPA. - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K. - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. @@ -117,7 +118,7 @@ Get CMake for free from http://www.cmake.org. Will just target the x86 architecture. The list of available architectures is: ARM, AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX, - WASM, BPF, RISCV, Alpha. + WASM, BPF, RISCV, Alpha, HPPA. (4) You can also create an installation image with cmake, by using the 'install' target. Use: diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT index c9d41ae39..6b0d4e14b 100644 --- a/COMPILE_MSVC.TXT +++ b/COMPILE_MSVC.TXT @@ -33,6 +33,7 @@ or newer versions are required. - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. - CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support. - CAPSTONE_HAS_ALPHA: support Alpha. Delete this to remove Alpha support. + - CAPSTONE_HAS_HPPA: support HPPA. Delete this to remove HPPA support. - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support. - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support. diff --git a/CREDITS.TXT b/CREDITS.TXT index e520e7081..81b94a8c0 100644 --- a/CREDITS.TXT +++ b/CREDITS.TXT @@ -88,4 +88,4 @@ fanfuqiang & citypw & porto703 : RISCV architecture. Josh "blacktop" Maine: Arm64 architecture improvements. Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support) Billow & Sidneyp : TriCore architecture. -Dmitry Sibirtsev: Alpha architecture. \ No newline at end of file +Dmitry Sibirtsev: Alpha & HPPA architecture. \ No newline at end of file diff --git a/HACK.TXT b/HACK.TXT index a6b0dd69b..5858f61cd 100644 --- a/HACK.TXT +++ b/HACK.TXT @@ -10,6 +10,7 @@ Capstone source is organized as followings. │   ├── ARM <- ARM engine │   ├── BPF <- Berkeley Packet Filter engine │   ├── EVM <- Ethereum engine +│   ├── HPPA <- HPPA engine │   ├── M680X <- M680X engine │   ├── M68K <- M68K engine │   ├── Mips <- Mips engine diff --git a/MCInst.c b/MCInst.c index a0ca8ec6b..aed26086a 100644 --- a/MCInst.c +++ b/MCInst.c @@ -36,6 +36,7 @@ void MCInst_Init(MCInst *inst) inst->tied_op_idx[i] = -1; inst->isAliasInstr = false; inst->fillDetailOps = false; + memset(&inst->hppa_ext, 0, sizeof(inst->hppa_ext)); } void MCInst_clear(MCInst *inst) diff --git a/MCInst.h b/MCInst.h index 69c2bb946..25f8f5c46 100644 --- a/MCInst.h +++ b/MCInst.h @@ -131,6 +131,7 @@ struct MCInst { uint8_t xAcquireRelease; // X86 xacquire/xrelease bool isAliasInstr; // Flag if this MCInst is an alias. bool fillDetailOps; // If set, detail->operands gets filled. + hppa_ext hppa_ext; ///< for HPPA operand. Contains info about modifiers and their effect on the instruction }; void MCInst_Init(MCInst *inst); diff --git a/Makefile b/Makefile index 78f6ab3f5..7a526abd1 100644 --- a/Makefile +++ b/Makefile @@ -335,11 +335,22 @@ ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) LIBOBJ_ALPHA += $(LIBSRC_ALPHA:%.c=$(OBJDIR)/%.o) endif +DEP_HPPA = +DEP_HPPA += $(wildcard arch/HPPA/HPPA*.inc) + +LIBOBJ_HPPA = +ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_HPPA + LIBSRC_HPPA += $(wildcard arch/HPPA/HPPA*.c) + LIBOBJ_HPPA += $(LIBSRC_HPPA:%.c=$(OBJDIR)/%.o) +endif + + LIBOBJ = LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH) LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF) -LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) +LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) ifeq ($(PKG_EXTRA),) @@ -476,6 +487,7 @@ $(LIBOBJ_MOS65XX): $(DEP_MOS65XX) $(LIBOBJ_BPF): $(DEP_BPF) $(LIBOBJ_TRICORE): $(DEP_TRICORE) $(LIBOBJ_ALPHA): $(DEP_ALPHA) +$(LIBOBJ_HPPA): $(DEP_HPPA) ifeq ($(CAPSTONE_STATIC),yes) $(ARCHIVE): $(LIBOBJ) @@ -561,13 +573,13 @@ dist: git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip -TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore +TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore test_hppa TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static -TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static +TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static test_hppa.static check: $(TESTS) diff --git a/Mapping.c b/Mapping.c index 80741a7b2..580db8445 100644 --- a/Mapping.c +++ b/Mapping.c @@ -334,6 +334,7 @@ DEFINE_get_detail_op(ppc, PPC); DEFINE_get_detail_op(tricore, TriCore); DEFINE_get_detail_op(aarch64, AArch64); DEFINE_get_detail_op(alpha, Alpha); +DEFINE_get_detail_op(hppa, HPPA); /// Returns true if for this architecture the /// alias operands should be filled. diff --git a/Mapping.h b/Mapping.h index 29cc3b9b5..9b5de0afe 100644 --- a/Mapping.h +++ b/Mapping.h @@ -124,6 +124,7 @@ DECL_get_detail_op(ppc, PPC); DECL_get_detail_op(tricore, TriCore); DECL_get_detail_op(aarch64, AArch64); DECL_get_detail_op(alpha, Alpha); +DECL_get_detail_op(hppa, HPPA); /// Increments the detail->arch.op_count by one. #define DEFINE_inc_detail_op_count(arch, ARCH) \ @@ -149,6 +150,8 @@ DEFINE_inc_detail_op_count(aarch64, AArch64); DEFINE_dec_detail_op_count(aarch64, AArch64); DEFINE_inc_detail_op_count(alpha, Alpha); DEFINE_dec_detail_op_count(alpha, Alpha); +DEFINE_inc_detail_op_count(hppa, HPPA); +DEFINE_dec_detail_op_count(hppa, HPPA); /// Returns true if a memory operand is currently edited. static inline bool doing_mem(const MCInst *MI) @@ -175,6 +178,7 @@ DEFINE_get_arch_detail(ppc, PPC); DEFINE_get_arch_detail(tricore, TriCore); DEFINE_get_arch_detail(aarch64, AArch64); DEFINE_get_arch_detail(alpha, Alpha); +DEFINE_get_arch_detail(hppa, HPPA); static inline bool detail_is_set(const MCInst *MI) { diff --git a/MathExtras.h b/MathExtras.h index e0f37a5ba..eb3b98971 100644 --- a/MathExtras.h +++ b/MathExtras.h @@ -430,6 +430,12 @@ static inline int64_t SignExtend64(uint64_t X, unsigned B) { return (int64_t)(X << (64 - B)) >> (64 - B); } +/// \brief Removes the rightmost bit of x and extends the field to the left with that +/// bit to form a 64-bit quantity. The field is of size len +static inline int64_t LowSignExtend64(uint64_t x, unsigned len) { + return (x >> 1) - ((x & 1) << (len - 1)); +} + /// \brief One extend number X starting at bit B and returns it as int32_t. /// Requires 0 < B <= 32. static inline int32_t OneExtend32(uint32_t X, unsigned B) { @@ -467,4 +473,16 @@ static inline unsigned int countLeadingZeros(int x) return count; } +/// \brief Get specified field from 32-bit instruction. Returns bits from the segment [from, to] +static inline uint32_t get_insn_field(uint32_t insn, uint8_t from, uint8_t to) +{ + return insn >> (31 - to) & ((1 << (to - from + 1)) - 1); +} + +/// \brief Get specified bit from 32-bit instruction +static inline uint32_t get_insn_bit(uint32_t insn, uint8_t bit) +{ + return get_insn_field(insn, bit, bit); +} + #endif diff --git a/arch/HPPA/HPPAConstants.h b/arch/HPPA/HPPAConstants.h new file mode 100644 index 000000000..d2ebb61b7 --- /dev/null +++ b/arch/HPPA/HPPAConstants.h @@ -0,0 +1,74 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +/* This file defines constants and macros used for parsing a HPPA instruction */ + +#ifndef CS_HPPA_CONSTANTS_H +#define CS_HPPA_CONSTANTS_H + +#define HPPA_OP_TYPE(byte) (byte) >> 2 +#define MODE_IS_HPPA_20(mode) (((mode)&CS_MODE_HPPA_20) != 0) +#define MODE_IS_HPPA_20W(mode) (((mode) & (1 << 3)) != 0) + +///> HPPA opcode types +#define HPPA_OP_TYPE_SYSOP 0x00 +#define HPPA_OP_TYPE_MEMMGMT 0x01 +#define HPPA_OP_TYPE_ALU 0x02 +#define HPPA_OP_TYPE_IDXMEM 0x03 +#define HPPA_OP_TYPE_SPOP 0x04 +#define HPPA_OP_TYPE_DIAG 0x05 +#define HPPA_OP_TYPE_FMPYADD 0x06 +#define HPPA_OP_TYPE_LDIL 0x08 +#define HPPA_OP_TYPE_COPRW 0x09 +#define HPPA_OP_TYPE_ADDIL 0x0a +#define HPPA_OP_TYPE_COPRDW 0x0b +#define HPPA_OP_TYPE_COPR 0x0c +#define HPPA_OP_TYPE_LDO 0x0d +#define HPPA_OP_TYPE_FLOAT 0x0e +#define HPPA_OP_TYPE_PRDSPEC 0x0f +#define HPPA_OP_TYPE_LDB 0x10 +#define HPPA_OP_TYPE_LDH 0x11 +#define HPPA_OP_TYPE_LDW 0x12 +#define HPPA_OP_TYPE_LDWM 0x13 +#define HPPA_OP_TYPE_LOADDW 0x14 +#define HPPA_OP_TYPE_FLDW 0x16 +#define HPPA_OP_TYPE_LOADW 0x17 +#define HPPA_OP_TYPE_STB 0x18 +#define HPPA_OP_TYPE_STH 0x19 +#define HPPA_OP_TYPE_STW 0x1a +#define HPPA_OP_TYPE_STWM 0x1b +#define HPPA_OP_TYPE_STOREDW 0x1c +#define HPPA_OP_TYPE_FSTW 0x1e +#define HPPA_OP_TYPE_STOREW 0x1f +#define HPPA_OP_TYPE_CMPBT 0x20 +#define HPPA_OP_TYPE_CMPIBT 0x21 +#define HPPA_OP_TYPE_CMPBF 0x22 +#define HPPA_OP_TYPE_CMPIBF 0x23 +#define HPPA_OP_TYPE_CMPICLR 0x24 +#define HPPA_OP_TYPE_SUBI 0x25 +#define HPPA_OP_TYPE_FMPYSUB 0x26 +#define HPPA_OP_TYPE_CMPBDWT 0x27 +#define HPPA_OP_TYPE_ADDBT 0x28 +#define HPPA_OP_TYPE_ADDIBT 0x29 +#define HPPA_OP_TYPE_ADDBF 0x2a +#define HPPA_OP_TYPE_ADDIBF 0x2b +#define HPPA_OP_TYPE_ADDIT 0x2c +#define HPPA_OP_TYPE_ADDI 0x2d +#define HPPA_OP_TYPE_FPFUSED 0x2e +#define HPPA_OP_TYPE_CMPBDWF 0x2f +#define HPPA_OP_TYPE_BBS 0x30 +#define HPPA_OP_TYPE_BB 0x31 +#define HPPA_OP_TYPE_MOVB 0x32 +#define HPPA_OP_TYPE_MOVIB 0x33 +#define HPPA_OP_TYPE_SHEXDEP0 0x34 +#define HPPA_OP_TYPE_SHEXDEP1 0x35 +#define HPPA_OP_TYPE_SHEXDEP2 0x36 +#define HPPA_OP_TYPE_BE 0x38 +#define HPPA_OP_TYPE_BLE 0x39 +#define HPPA_OP_TYPE_BRANCH 0x3a +#define HPPA_OP_TYPE_CMPIBDW 0x3b +#define HPPA_OP_TYPE_SHEXDEP3 0x3c +#define HPPA_OP_TYPE_SHEXDEP4 0x3d +#define HPPA_OP_TYPE_MULTMED 0x3e + +#endif // CS_HPPA_CONSTANTS_H \ No newline at end of file diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c new file mode 100644 index 000000000..b962f2d52 --- /dev/null +++ b/arch/HPPA/HPPADisassembler.c @@ -0,0 +1,3837 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include +#include // offsetof macro +#include +#include "HPPADisassembler.h" +#include "HPPAConstants.h" + +#include "../../Mapping.h" +#include "../../MathExtras.h" +#include "../../utils.h" + +#define CMPLT_HAS_MODIFY_BIT(CMPLT) (((CMPLT)&1) == 1) + +#define HPPA_EXT_REF(MI) (&MI->hppa_ext) + +static const char *const compare_cond_names[] = { + "", "=", "<", "<=", "<<", "<<=", "sv", "od", + "tr", "<>", ">=", ">", ">>=", ">>", "nsv", "ev" +}; +static const char *const compare_cond_64_names[] = { + "*", "*=", "*<", "*<=", "*<<", "*<<=", "*sv", "*od", + "*tr", "*<>", "*>=", "*>", "*>>=", "*>>", "*nsv", "*ev" +}; +static const char *const cmpib_cond_64_names[] = { "*<<", "*=", "*<", "*<=", + "*>>=", "*<>", "*>=", "*>" }; +static const char *const add_cond_names[] = { + "", "=", "<", "<=", "nuv", "znv", "sv", "od", + "tr", "<>", ">=", ">", "uv", "vnz", "nsv", "ev" +}; +static const char *const add_cond_64_names[] = { + "*", "*=", "*<", "*<=", "*nuv", "*znv", "*sv", "*od", + "*tr", "*<>", "*>=", "*>", "*uv", "*vnz", "*nsv", "*ev" +}; +static const char *const wide_add_cond_names[] = { + "*", "=", "<", "<=", "nuv", "*=", "*<", "*<=", + "tr", "<>", ">=", ">", "uv", "*<>", "*>=", "*>" +}; +static const char *const logical_cond_names[] = { + "", "=", "<", "<=", "", "", "", "od", + "tr", "<>", ">=", ">", "", "", "", "ev" +}; +static const char *const logical_cond_64_names[] = { + "*", "*=", "*<", "*<=", "", "", "", "*od", + "*tr", "*<>", "*>=", "*>", "", "", "", "*ev" +}; +static const char *const unit_cond_names[] = { "", "swz", "sbz", "shz", + "sdc", "swc", "sbc", "shc", + "tr", "nwz", "nbz", "nhz", + "ndc", "nwc", "nbc", "nhc" }; +static const char *const unit_cond_64_names[] = { + "*", "*swz", "*sbz", "*shz", "*sdc", "*swc", "*sbc", "*shc", + "*tr", "*nwz", "*nbz", "*nhz", "*ndc", "*nwc", "*nbc", "*nhc" +}; +static const char *const shift_cond_names[] = { "", "=", "<", "od", + "tr", "<>", ">=", "ev" }; +static const char *const shift_cond_64_names[] = { "*", "*=", "*<", "*od", + "*tr", "*<>", "*>=", "*ev" }; +static const char *const index_compl_names[] = { "", "m", "s", "sm" }; +static const char *const short_ldst_compl_names[] = { "", "ma", "", "mb" }; +static const char *const short_bytes_compl_names[] = { "", "b,m", "e", "e,m" }; +static const char *const float_format_names[] = { "sgl", "dbl", "", "quad" }; +static const char *const float_cond_names[] = { + "", "acc", "rej", "", "", "acc8", "rej8", "", "", "acc6", "", + "", "", "acc4", "", "", "", "acc2", "", "", "", "", + "", "", "", "", "", "", "", "", "", "" +}; +static const char *const fcnv_fixed_names[] = { "w", "dw", "", "qw" }; +static const char *const fcnv_ufixed_names[] = { "uw", "udw", "", "uqw" }; +static const char *const float_comp_names[] = { + "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", + "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", + "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", + "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" +}; +static const char *const signed_unsigned_names[] = { "u", "s" }; +static const char *const saturation_names[] = { "us", "ss", "", "" }; +static const char *const add_compl_names[] = { "", "", "l", "tsv" }; + +#define CREATE_GR_REG(MI, gr) MCOperand_CreateReg0(MI, gr + HPPA_REG_GR0) +#define CREATE_SR_REG(MI, sr) MCOperand_CreateReg0(MI, sr + HPPA_REG_SR0) +#define CREATE_CR_REG(MI, cr) MCOperand_CreateReg0(MI, cr + HPPA_REG_CR0) +#define CREATE_FPR_REG(MI, fpr) MCOperand_CreateReg0(MI, fpr + HPPA_REG_FPR0) +#define CREATE_FPE_REG(MI, fpe) MCOperand_CreateReg0(MI, fpe + HPPA_REG_FPE0) +#define CREATE_SP_FPR_REG(MI, fpr) \ + MCOperand_CreateReg0(MI, fpr + HPPA_REG_SP_FPR0) + +static void create_float_reg_spec(MCInst *MI, uint32_t reg, uint32_t fpe_flag) +{ + if (fpe_flag == 1) { + CREATE_FPE_REG(MI, reg); + } else { + CREATE_FPR_REG(MI, reg); + } +} + +/* Get at various relevant fields of an instruction word. */ + +#define MASK_5 0x1f +#define MASK_10 0x3ff +#define MASK_11 0x7ff +#define MASK_14 0x3fff +#define MASK_16 0xffff +#define MASK_21 0x1fffff + +/* Routines to extract various sized constants out of hppa + instructions. */ + +/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */ +static int extract_3(unsigned word) +{ + return get_insn_field(word, 18, 18) << 2 | get_insn_field(word, 16, 17); +} + +static int extract_5_load(unsigned word) +{ + return LowSignExtend64(word >> 16 & MASK_5, 5); +} + +/* Extract the immediate field from a st{bhw}s instruction. */ + +static int extract_5_store(unsigned word) +{ + return LowSignExtend64(word & MASK_5, 5); +} + +/* Extract an 11 bit immediate field. */ + +static int extract_11(unsigned word) +{ + return LowSignExtend64(word & MASK_11, 11); +} + +/* Extract a 14 bit immediate field. */ + +static int extract_14(unsigned word) +{ + return LowSignExtend64(word & MASK_14, 14); +} + +/* Extract a 16 bit immediate field. */ + +static int extract_16(unsigned word, bool wide) +{ + int m15, m0, m1; + + m0 = get_insn_bit(word, 16); + m1 = get_insn_bit(word, 17); + m15 = get_insn_bit(word, 31); + word = (word >> 1) & 0x1fff; + if (wide) { + word = word | (m15 << 15) | ((m15 ^ m0) << 14) | + ((m15 ^ m1) << 13); + } else { + word = word | (m15 << 15) | (m15 << 14) | (m15 << 13); + } + return SignExtend32(word, 16); +} + +/* Extract a 21 bit constant. */ + +static int extract_21(unsigned word) +{ + int val; + + word &= MASK_21; + word <<= 11; + val = get_insn_field(word, 20, 20); + val <<= 11; + val |= get_insn_field(word, 9, 19); + val <<= 2; + val |= get_insn_field(word, 5, 6); + val <<= 5; + val |= get_insn_field(word, 0, 4); + val <<= 2; + val |= get_insn_field(word, 7, 8); + return SignExtend32(val, 21) << 11; +} + +/* Extract a 12 bit constant from branch instructions. */ + +static int extract_12(unsigned word) +{ + return SignExtend32(get_insn_field(word, 19, 28) | + get_insn_field(word, 29, 29) << 10 | + (word & 0x1) << 11, + 12) + << 2; +} + +/* Extract a 17 bit constant from branch instructions, returning the + 19 bit signed value. */ + +static int extract_17(unsigned word) +{ + return SignExtend32(get_insn_field(word, 19, 28) | + get_insn_field(word, 29, 29) << 10 | + get_insn_field(word, 11, 15) << 11 | + (word & 0x1) << 16, + 17) + << 2; +} + +static int extract_22(unsigned word) +{ + return SignExtend32(get_insn_field(word, 19, 28) | + get_insn_field(word, 29, 29) << 10 | + get_insn_field(word, 11, 15) << 11 | + get_insn_field(word, 6, 10) << 16 | + (word & 0x1) << 21, + 22) + << 2; +} + +static void push_str_modifier(hppa_ext *hppa, const char *modifier) +{ + if (strcmp(modifier, "")) { + hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; + assert(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); + mod->type = HPPA_MOD_STR; + assert(strlen(modifier) <= HPPA_STR_MODIFIER_LEN); + strcpy(mod->str_mod, modifier); + } +} + +static void push_int_modifier(hppa_ext *hppa, uint64_t modifier) +{ + hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; + assert(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); + mod->type = HPPA_MOD_INT; + mod->int_mod = modifier; +} + +static void fill_sysop_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext8 = get_insn_field(insn, 19, 26); + uint32_t ext5 = get_insn_field(insn, 11, 15); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext8) { + case 0xa5: + MCInst_setOpcode(MI, HPPA_INS_MFIA); + return; + case 0xc6: + MCInst_setOpcode(MI, HPPA_INS_MTSARCM); + return; + case 0x65: + push_str_modifier(HPPA_EXT_REF(MI), "r"); + // fallthrough + case 0x60: + MCInst_setOpcode(MI, HPPA_INS_RFI); + return; + default: + break; + } + } + + switch (ext8) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_BREAK); + break; + case 0x20: + if (ext5 == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_SYNC); + } else if (ext5 == 0x10) { + MCInst_setOpcode(MI, HPPA_INS_SYNCDMA); + } + break; + case 0x60: + MCInst_setOpcode(MI, HPPA_INS_RFI); + break; + case 0x65: + MCInst_setOpcode(MI, HPPA_INS_RFIR); + break; + case 0x6b: + MCInst_setOpcode(MI, HPPA_INS_SSM); + break; + case 0x73: + MCInst_setOpcode(MI, HPPA_INS_RSM); + break; + case 0xc3: + MCInst_setOpcode(MI, HPPA_INS_MTSM); + break; + case 0x85: + MCInst_setOpcode(MI, HPPA_INS_LDSID); + break; + case 0xc1: + MCInst_setOpcode(MI, HPPA_INS_MTSP); + break; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_MFSP); + break; + case 0xc2: + MCInst_setOpcode(MI, HPPA_INS_MTCTL); + break; + case 0x45: + MCInst_setOpcode(MI, HPPA_INS_MFCTL); + if (get_insn_bit(insn, 17) == 1 && + MODE_IS_HPPA_20(MI->csh->mode)) { + push_str_modifier(HPPA_EXT_REF(MI), "w"); + } + break; + default: + break; + } +} + +static bool decode_sysop(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext8 = get_insn_field(insn, 19, 26); + uint32_t ext5 = get_insn_field(insn, 11, 15); + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t s = extract_3(insn); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext8) { + case 0xa5: + if (ext5 != 0) { + return false; + } + CREATE_GR_REG(MI, t); + return true; + case 0xc6: + CREATE_GR_REG(MI, r2); + return true; + default: + break; + } + } + + switch (ext8) { + case 0x00: + MCOperand_CreateImm0(MI, t); + MCOperand_CreateImm0(MI, get_insn_field(insn, 6, 18)); + return true; + case 0x20: + if (ext5 != 0x00 && ext5 != 0x10) { + return false; + } + // fallthrough + case 0x60: + case 0x65: + return true; + case 0x6b: + case 0x73: + MCOperand_CreateImm0(MI, get_insn_field(insn, 9, 15)); + CREATE_GR_REG(MI, t); + return true; + case 0xc3: + CREATE_GR_REG(MI, r2); + return true; + case 0x85: + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, t); + return true; + case 0xc1: + CREATE_GR_REG(MI, r2); + CREATE_SR_REG(MI, s); + return true; + case 0x25: + if (ext5 != 0) { + return false; + } + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, t); + return true; + case 0xc2: + CREATE_GR_REG(MI, r2); + CREATE_CR_REG(MI, r1); + return true; + case 0x45: + if (ext5 != 0) { + return false; + } + if (get_insn_bit(insn, 17) == 1 && MODE_IS_HPPA_20(ud->mode) && + r1 != 11) { + return false; + } + CREATE_CR_REG(MI, r1); + CREATE_GR_REG(MI, t); + return true; + default: + return false; + } +} + +static void fill_memmgmt_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x20: + MCInst_setOpcode(MI, HPPA_INS_IITLBT); + return; + case 0x18: + MCInst_setOpcode(MI, HPPA_INS_PITLB); + push_str_modifier(HPPA_EXT_REF(MI), "l"); + return; + case 0x60: + MCInst_setOpcode(MI, HPPA_INS_IDTLBT); + return; + case 0x58: + MCInst_setOpcode(MI, HPPA_INS_PDTLB); + push_str_modifier(HPPA_EXT_REF(MI), "l"); + return; + case 0x4f: + MCInst_setOpcode(MI, HPPA_INS_FIC); + return; + case 0x46: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBE); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBEI); + }; + push_str_modifier(HPPA_EXT_REF(MI), "r"); + return; + case 0x47: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBE); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBEI); + }; + push_str_modifier(HPPA_EXT_REF(MI), "w"); + return; + default: + break; + } + } + + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_IITLBP); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_IITLBA); + break; + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_PITLB); + break; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_PITLBE); + break; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_FIC); + break; + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_FICE); + break; + case 0x40: + MCInst_setOpcode(MI, HPPA_INS_IDTLBP); + break; + case 0x41: + MCInst_setOpcode(MI, HPPA_INS_IDTLBA); + break; + case 0x48: + MCInst_setOpcode(MI, HPPA_INS_PDTLB); + break; + case 0x49: + MCInst_setOpcode(MI, HPPA_INS_PDTLBE); + break; + case 0x4a: + MCInst_setOpcode(MI, HPPA_INS_FDC); + break; + case 0x4b: + MCInst_setOpcode(MI, HPPA_INS_FDCE); + break; + case 0x4e: + MCInst_setOpcode(MI, HPPA_INS_PDC); + break; + case 0x46: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBER); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBERI); + }; + break; + case 0x47: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBEW); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBEWI); + }; + break; + case 0x4d: + MCInst_setOpcode(MI, HPPA_INS_LPA); + break; + case 0x4c: + MCInst_setOpcode(MI, HPPA_INS_LCI); + break; + default: + break; + } +} + +static void fill_memmgmt_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint8_t cmplt = get_insn_bit(insn, 26); + uint32_t ext = get_insn_field(insn, 19, 25); + if (MODE_IS_HPPA_20(mode)) { + switch (ext) { + case 0x18: + case 0x58: + case 0x4f: + goto success; + default: + break; + } + } + + switch (ext) { + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4e: + case 0x4d: + break; + default: + return; + } +success: + if (CMPLT_HAS_MODIFY_BIT(cmplt)) { + hppa_ext->b_writeble = true; + } + push_str_modifier(hppa_ext, index_compl_names[cmplt]); +} + +static bool decode_memmgmt(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 25); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t s3 = extract_3(insn); + uint32_t s2 = get_insn_field(insn, 16, 17); + uint32_t t = get_insn_field(insn, 27, 31); + if (ext > 0x20 && get_insn_bit(insn, 18) == 1 && + (ext != 0x46 && ext != 0x47)) { + if (MODE_IS_HPPA_20(ud->mode)) { + if (ext != 0x4a) { + return false; + } + } else { + return false; + } + } + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x20: + case 0x60: + CREATE_GR_REG(MI, r); + CREATE_GR_REG(MI, b); + goto success; + case 0x58: + case 0x4f: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + goto success; + case 0x18: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s3); + CREATE_GR_REG(MI, b); + goto success; + case 0x4a: + if (get_insn_bit(insn, 18) == 1) { + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + } else { + CREATE_GR_REG(MI, r); + } + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + goto success; + default: + break; + } + } + + switch (ext) { + case 0x00: + case 0x01: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s3); + CREATE_GR_REG(MI, b); + break; + case 0x40: + case 0x41: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4e: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + break; + case 0x46: + case 0x47: + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + if (get_insn_bit(insn, 18) == 0) { + CREATE_GR_REG(MI, r); + } else { + MCOperand_CreateImm0(MI, r); + } + CREATE_GR_REG(MI, t); + break; + case 0x4d: + case 0x4c: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } +success: + fill_memmgmt_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode); + return true; +} + +static void fill_alu_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 20, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x28: + case 0x38: + case 0x1c: + case 0x3c: + MCInst_setOpcode(MI, HPPA_INS_ADD); + return; + case 0x19: + case 0x29: + case 0x39: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x1b: + case 0x2b: + case 0x3b: + MCInst_setOpcode(MI, HPPA_INS_SHLADD); + return; + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + MCInst_setOpcode(MI, HPPA_INS_SUB); + return; + case 0x22: + MCInst_setOpcode(MI, HPPA_INS_CMPCLR); + return; + case 0x27: + MCInst_setOpcode(MI, HPPA_INS_UADDCM); + return; + case 0x2f: + MCInst_setOpcode(MI, HPPA_INS_DCOR); + return; + case 0x0f: + case 0x0d: + case 0x0c: + MCInst_setOpcode(MI, HPPA_INS_HADD); + return; + case 0x07: + case 0x05: + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_HSUB); + return; + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_HAVG); + return; + case 0x1d: + case 0x1e: + case 0x1f: + MCInst_setOpcode(MI, HPPA_INS_HSHLADD); + return; + case 0x15: + case 0x16: + case 0x17: + MCInst_setOpcode(MI, HPPA_INS_HSHRADD); + return; + default: + break; + } + } + + switch (ext) { + case 0x18: + MCInst_setOpcode(MI, HPPA_INS_ADD); + break; + case 0x38: + MCInst_setOpcode(MI, HPPA_INS_ADDO); + break; + case 0x1c: + MCInst_setOpcode(MI, HPPA_INS_ADDC); + break; + case 0x3c: + MCInst_setOpcode(MI, HPPA_INS_ADDCO); + break; + case 0x19: + MCInst_setOpcode(MI, HPPA_INS_SH1ADD); + break; + case 0x39: + MCInst_setOpcode(MI, HPPA_INS_SH1ADDO); + break; + case 0x1a: + MCInst_setOpcode(MI, HPPA_INS_SH2ADD); + break; + case 0x3a: + MCInst_setOpcode(MI, HPPA_INS_SH2ADDO); + break; + case 0x1b: + MCInst_setOpcode(MI, HPPA_INS_SH3ADD); + break; + case 0x3b: + MCInst_setOpcode(MI, HPPA_INS_SH3ADDO); + break; + case 0x10: + MCInst_setOpcode(MI, HPPA_INS_SUB); + break; + case 0x30: + MCInst_setOpcode(MI, HPPA_INS_SUBO); + break; + case 0x13: + MCInst_setOpcode(MI, HPPA_INS_SUBT); + break; + case 0x33: + MCInst_setOpcode(MI, HPPA_INS_SUBTO); + break; + case 0x14: + MCInst_setOpcode(MI, HPPA_INS_SUBB); + break; + case 0x34: + MCInst_setOpcode(MI, HPPA_INS_SUBBO); + break; + case 0x11: + MCInst_setOpcode(MI, HPPA_INS_DS); + break; + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_ANDCM); + break; + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_AND); + break; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_OR); + break; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_XOR); + break; + case 0x0e: + MCInst_setOpcode(MI, HPPA_INS_UXOR); + break; + case 0x22: + MCInst_setOpcode(MI, HPPA_INS_COMCLR); + break; + case 0x26: + MCInst_setOpcode(MI, HPPA_INS_UADDCM); + break; + case 0x27: + MCInst_setOpcode(MI, HPPA_INS_UADDCMT); + break; + case 0x28: + MCInst_setOpcode(MI, HPPA_INS_ADDL); + break; + case 0x29: + MCInst_setOpcode(MI, HPPA_INS_SH1ADDL); + break; + case 0x2a: + MCInst_setOpcode(MI, HPPA_INS_SH2ADDL); + break; + case 0x2b: + MCInst_setOpcode(MI, HPPA_INS_SH3ADDL); + break; + case 0x2e: + MCInst_setOpcode(MI, HPPA_INS_DCOR); + break; + case 0x2f: + MCInst_setOpcode(MI, HPPA_INS_IDCOR); + break; + default: + break; + } +} + +static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = (get_insn_field(insn, 19, 19) << 3) | + get_insn_field(insn, 16, 18); + uint32_t ext = get_insn_field(insn, 20, 25); + if (MODE_IS_HPPA_20(mode)) { + uint32_t e1 = get_insn_field(insn, 20, 21); + uint32_t e2 = get_insn_bit(insn, 23); + uint32_t e3 = get_insn_field(insn, 24, 25); + uint32_t d = get_insn_bit(insn, 26); + switch (ext) { + case 0x18: + case 0x28: + case 0x38: + case 0x1c: + case 0x3c: + if (e2 == 1) { + if (d == 1) { + push_str_modifier(hppa_ext, "dc"); + } else { + push_str_modifier(hppa_ext, "c"); + } + } + // fallthrough + case 0x19: + case 0x29: + case 0x39: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x1b: + case 0x2b: + case 0x3b: + push_str_modifier(hppa_ext, add_compl_names[e1]); + if (d == 1) { + push_str_modifier(hppa_ext, + add_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + add_cond_names[cond]); + } + return; + case 0x10: + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + if (e2 == 1) { + if (d == 1) { + push_str_modifier(hppa_ext, "db"); + } else { + push_str_modifier(hppa_ext, "b"); + } + } + if (e1 == 3) { + push_str_modifier(hppa_ext, "tsv"); + } + if (e3 == 3) { + push_str_modifier(hppa_ext, "tc"); + } + // fallthrough + case 0x22: + if (d == 1) { + push_str_modifier(hppa_ext, + compare_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + compare_cond_names[cond]); + } + return; + case 0x00: + case 0x08: + case 0x09: + case 0x0a: + if (d == 1) { + push_str_modifier(hppa_ext, + logical_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + logical_cond_names[cond]); + } + return; + case 0x27: + push_str_modifier(hppa_ext, "tc"); + goto unit_cond; + case 0x2f: + push_str_modifier(hppa_ext, "i"); + // fallthough + case 0x26: + case 0x0e: + case 0x2e: +unit_cond: + if (d == 1) { + push_str_modifier(hppa_ext, + unit_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + unit_cond_names[cond]); + } + return; + case 0x0d: + case 0x0c: + case 0x05: + case 0x04: + push_str_modifier(hppa_ext, saturation_names[e3]); + return; + default: + break; + } + } + + switch (ext) { + case 0x18: + case 0x38: + case 0x1c: + case 0x3c: + case 0x19: + case 0x39: + case 0x1a: + case 0x3a: + case 0x3b: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + push_str_modifier(hppa_ext, add_cond_names[cond]); + break; + case 0x10: + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + case 0x11: + case 0x22: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + case 0x00: + case 0x08: + case 0x09: + case 0x0a: + push_str_modifier(hppa_ext, logical_cond_names[cond]); + break; + case 0x0e: + case 0x26: + case 0x27: + case 0x2e: + case 0x2f: + push_str_modifier(hppa_ext, unit_cond_names[cond]); + break; + default: + break; + } +} + +static bool decode_alu(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 20, 25); + uint32_t r1 = get_insn_field(insn, 11, 15); + uint32_t r2 = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x19: + case 0x29: + case 0x39: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x1b: + case 0x2b: + case 0x3b: + case 0x1d: + case 0x1e: + case 0x1f: + case 0x15: + case 0x16: + case 0x17: + case 0x0f: + case 0x0d: + case 0x0c: + case 0x07: + case 0x05: + case 0x04: + case 0x0b: + CREATE_GR_REG(MI, r1); + if (ext > 0x10) { + MCOperand_CreateImm0( + MI, get_insn_field(insn, 24, 25)); + } + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + goto success; + default: + break; + } + } + switch (ext) { + case 0x18: + case 0x38: + case 0x1c: + case 0x3c: + case 0x19: + case 0x39: + case 0x1a: + case 0x3a: + case 0x1b: + case 0x3b: + case 0x10: + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + case 0x11: + case 0x00: + case 0x08: + case 0x09: + case 0x0a: + case 0x0e: + case 0x22: + case 0x26: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + CREATE_GR_REG(MI, r1); + // fallthrough + case 0x2e: + case 0x2f: + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } +success: + fill_alu_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode); + return true; +} + +static void fill_idxmem_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 22, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_LDB); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_LDH); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_LDW); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_LDD); + return; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_LDDA); + return; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_LDCD); + return; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_LDWA); + return; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_LDCW); + return; + default: + break; + } + if (get_insn_bit(insn, 19) == 1) { + switch (ext) { + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_STB); + return; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_STH); + return; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_STW); + return; + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_STD); + return; + case 0x0c: + MCInst_setOpcode(MI, HPPA_INS_STBY); + return; + case 0x0d: + MCInst_setOpcode(MI, HPPA_INS_STDBY); + return; + case 0x0e: + MCInst_setOpcode(MI, HPPA_INS_STWA); + return; + case 0x0f: + MCInst_setOpcode(MI, HPPA_INS_STDA); + return; + default: + break; + } + } + } + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_LDBX); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_LDHX); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_LDWX); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_LDCWX); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_LDWAX); + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_LDBS); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_LDHS); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_LDWS); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_LDCWS); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_LDWAS); + break; + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_STBS); + break; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_STHS); + break; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_STWS); + break; + case 0x0c: + MCInst_setOpcode(MI, HPPA_INS_STBYS); + break; + case 0x0e: + MCInst_setOpcode(MI, HPPA_INS_STWAS); + break; + default: + break; + } + } +} + +static void fill_idxmem_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode, + uint32_t im5) +{ + uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26); + uint32_t cc = get_insn_field(insn, 20, 21); + uint32_t ext = get_insn_field(insn, 22, 25); + if (CMPLT_HAS_MODIFY_BIT(cmplt)) { + hppa_ext->b_writeble = true; + } + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + push_str_modifier(hppa_ext, index_compl_names[cmplt]); + if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + case 0x05: + case 0x07: + push_str_modifier(hppa_ext, index_compl_names[cmplt]); + if (cc == 1) { + push_str_modifier(hppa_ext, "co"); + } + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + if (cmplt == 1 && im5 == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier( + hppa_ext, + short_ldst_compl_names[cmplt]); + } + if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + case 0x05: + case 0x07: + if (cmplt == 1 && im5 == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier( + hppa_ext, + short_ldst_compl_names[cmplt]); + } + if (cc == 1) { + push_str_modifier(hppa_ext, "co"); + } + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0e: + case 0x0f: + if (cmplt == 1 && im5 == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier( + hppa_ext, + short_ldst_compl_names[cmplt]); + } + if (cc == 1) { + push_str_modifier(hppa_ext, "bc"); + } else if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + case 0x0c: + case 0x0d: + push_str_modifier(hppa_ext, + short_bytes_compl_names[cmplt]); + if (cc == 1) { + push_str_modifier(hppa_ext, "bc"); + } else if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + default: + break; + } + } +} + +static bool decode_idxmem(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 22, 25); + uint32_t im5; + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t s = get_insn_field(insn, 16, 17); + if (MODE_IS_HPPA_20(ud->mode)) { + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x03: + case 0x05: + case 0x04: + CREATE_GR_REG(MI, r); + if (ext != 0x04) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), + ud->mode, -1); + return true; + default: + break; + } + } else { + switch (ext) { + case 0x03: + case 0x05: + case 0x04: + im5 = extract_5_load(insn); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x04) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), + ud->mode, im5); + return true; + case 0x0b: + case 0x0d: + case 0x0f: + im5 = extract_5_store(insn); + CREATE_GR_REG(MI, r); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x0f) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), + ud->mode, im5); + return true; + default: + break; + } + } + } + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x07: + case 0x06: + CREATE_GR_REG(MI, r); + if (ext != 0x06) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1); + return true; + } else { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x07: + case 0x06: + im5 = extract_5_load(insn); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x06) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0c: + case 0x0e: + im5 = extract_5_store(insn); + CREATE_GR_REG(MI, r); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x0e) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + break; + default: + return false; + } + if (MODE_IS_HPPA_20(ud->mode)) { + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, im5); + } else { + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1); + } + return true; + } +} + +static void fill_ldst_dw_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t ext = get_insn_bit(insn, 30); + if (opcode == 0x14) { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_LDD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FLDD); + } + } else { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_STD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FSTD); + } + } +} + +static void fill_ldst_dw_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im) +{ + uint32_t cmplt = (get_insn_bit(insn, 29) << 1) | get_insn_bit(insn, 28); + if (cmplt == 1 && im == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]); + } +} + +static bool decode_ldst_dw(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + im &= ~7; + uint32_t ext = get_insn_bit(insn, 30); + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t s = get_insn_field(insn, 16, 17); + if (opcode == HPPA_OP_TYPE_LOADDW) { + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + if (ext == 0) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + } else { + if (ext == 0) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + } + fill_ldst_dw_mods(insn, HPPA_EXT_REF(MI), im); + return true; +} + +static void fill_ldst_w_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t ext = get_insn_bit(insn, 29); + if (opcode == 0x17) { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_FLDW); + } else { + MCInst_setOpcode(MI, HPPA_INS_LDW); + } + } else { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_FSTW); + } else { + MCInst_setOpcode(MI, HPPA_INS_STW); + } + } +} + +static void fill_ldst_w_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im) +{ + if (im >= 0) { + push_str_modifier(hppa_ext, "mb"); + } else { + push_str_modifier(hppa_ext, "ma"); + } +} + +static bool decode_ldst_w(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t ext = get_insn_bit(insn, 29); + uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + im &= ~3; + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t s = get_insn_field(insn, 16, 17); + if (opcode == 0x17) { + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + if (ext == 1) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + } else { + if (ext == 1) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + } + if (ext == 1) { + fill_ldst_w_mods(insn, HPPA_EXT_REF(MI), im); + } + return true; +} + +static void fill_arith_imm_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (opcode) { + case 0x2d: + case 0x2c: + MCInst_setOpcode(MI, HPPA_INS_ADDI); + return; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_SUBI); + return; + default: + break; + } + } + if (get_insn_bit(insn, 20) == 0) { + switch (opcode) { + case 0x2d: + MCInst_setOpcode(MI, HPPA_INS_ADDI); + break; + case 0x2c: + MCInst_setOpcode(MI, HPPA_INS_ADDIT); + break; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_SUBI); + break; + default: + break; + } + } else { + switch (opcode) { + case 0x2d: + MCInst_setOpcode(MI, HPPA_INS_ADDIO); + break; + case 0x2c: + MCInst_setOpcode(MI, HPPA_INS_ADDITO); + break; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_SUBIO); + break; + default: + break; + } + } +} + +static void fill_arith_imm_insn_mods(uint32_t insn, hppa_ext *hppa_ext, + cs_mode mode) +{ + uint32_t opcode = insn >> 26; + uint32_t cond = (get_insn_bit(insn, 19) << 3) | + get_insn_field(insn, 16, 18); + uint32_t cmplt = get_insn_bit(insn, 20); + if (MODE_IS_HPPA_20(mode)) { + if (cmplt == 1) { + push_str_modifier(hppa_ext, "tsv"); + } + if (opcode == 0x2c) { + push_str_modifier(hppa_ext, "tc"); + } + } + switch (opcode) { + case 0x2d: + case 0x2c: + push_str_modifier(hppa_ext, add_cond_names[cond]); + break; + case 0x25: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + default: + break; + } +} + +static bool decode_arith_imm(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + MCOperand_CreateImm0(MI, extract_11(insn)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + fill_arith_imm_insn_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_shexdep0_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t d = get_insn_bit(insn, 22); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x01: + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_SHRPD); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_SHRPW); + return; + case 0x06: + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_EXTRW); + return; + case 0x00: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_SHRPW); + } else { + MCInst_setOpcode(MI, HPPA_INS_SHRPD); + } + return; + case 0x04: + case 0x05: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_EXTRW); + } else { + MCInst_setOpcode(MI, HPPA_INS_EXTRD); + } + return; + default: + break; + } + } + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_VSHD); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_SHD); + break; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_VEXTRU); + break; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_VEXTRS); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_EXTRU); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_EXTRS); + break; + default: + break; + } +} + +static void fill_shexdep0_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = get_insn_field(insn, 16, 18); + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t d = get_insn_bit(insn, 22); + + if (ext >= 0x04 && MODE_IS_HPPA_20(mode)) { + push_str_modifier(hppa_ext, signed_unsigned_names[ext & 1]); + } + + if (MODE_IS_HPPA_20(mode)) { + switch (ext) { + case 0x00: + case 0x04: + case 0x05: + if (d == 0) { + break; + } + // fallthrough + case 0x01: + case 0x03: + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); + return; + default: + break; + } + } + push_str_modifier(hppa_ext, shift_cond_names[cond]); +} + +static bool decode_shexdep0(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t cp = get_insn_bit(insn, 20); + uint32_t cpos = get_insn_field(insn, 22, 26); + uint32_t sa = 63 - ((cp << 5) | cpos); + uint32_t r1 = get_insn_field(insn, 11, 15); + uint32_t r2 = get_insn_field(insn, 6, 10); + uint32_t clen_t = get_insn_field(insn, 27, 31); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x01: + case 0x00: + case 0x03: + case 0x02: + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, r2); + if (ext <= 0x01) { + CREATE_CR_REG(MI, 11); + HPPA_EXT_REF(MI)->is_alternative = true; + } else { + MCOperand_CreateImm0(MI, sa); + } + CREATE_GR_REG(MI, clen_t); + break; + case 0x06: + case 0x07: + case 0x04: + case 0x05: + CREATE_GR_REG(MI, r2); + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, cpos); + } else { + CREATE_CR_REG(MI, 11); + HPPA_EXT_REF(MI)->is_alternative = true; + } + MCOperand_CreateImm0(MI, 32 - clen_t); + CREATE_GR_REG(MI, r1); + break; + default: + return false; + } + } else { + switch (ext) { + case 0x00: + case 0x02: + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, r2); + if (ext == 0x02) { + MCOperand_CreateImm0(MI, 31 - cpos); + } + CREATE_GR_REG(MI, clen_t); + break; + case 0x04: + case 0x05: + case 0x06: + case 0x07: + CREATE_GR_REG(MI, r2); + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, cpos); + } + MCOperand_CreateImm0(MI, 32 - clen_t); + CREATE_GR_REG(MI, r1); + break; + default: + return false; + } + } + fill_shexdep0_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_shexdep1_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t d = get_insn_bit(insn, 22); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x02: + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_DEPW); + break; + case 0x06: + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_DEPWI); + break; + case 0x00: + case 0x01: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_DEPW); + } else { + MCInst_setOpcode(MI, HPPA_INS_DEPD); + } + break; + case 0x04: + case 0x05: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_DEPWI); + } else { + MCInst_setOpcode(MI, HPPA_INS_DEPDI); + } + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_ZVDEP); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_VDEP); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_ZDEP); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_DEP); + break; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_ZVDEPI); + break; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_VDEPI); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_ZDEPI); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_DEPI); + break; + default: + break; + } + } +} + +static void fill_shexdep1_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = get_insn_field(insn, 16, 18); + uint32_t cmplt = get_insn_bit(insn, 21); + uint32_t ext = get_insn_field(insn, 19, 21); + if (MODE_IS_HPPA_20(mode)) { + if (cmplt == 0) { + push_str_modifier(hppa_ext, "z"); + } + switch (ext) { + case 0x00: + case 0x01: + case 0x04: + case 0x05: + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); + return; + default: + break; + } + } + push_str_modifier(hppa_ext, shift_cond_names[cond]); +} + +static bool decode_shexdep1(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t cl = get_insn_bit(insn, 23); + uint32_t clen = get_insn_field(insn, 27, 31); + uint32_t len = (cl + 1) * 32 - clen; + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t t = get_insn_field(insn, 6, 10); + uint32_t cpos = get_insn_field(insn, 22, 26); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x02: + case 0x03: + case 0x06: + case 0x07: + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + } else { + CREATE_GR_REG(MI, r); + } + MCOperand_CreateImm0(MI, 31 - cpos); + MCOperand_CreateImm0(MI, 32 - clen); + CREATE_GR_REG(MI, t); + break; + case 0x00: + case 0x01: + case 0x04: + case 0x05: + if (ext >= 0x04) { + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + } else { + CREATE_GR_REG(MI, r); + } + CREATE_CR_REG(MI, 11); + HPPA_EXT_REF(MI)->is_alternative = true; + MCOperand_CreateImm0(MI, len); + CREATE_GR_REG(MI, t); + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + CREATE_GR_REG(MI, r); + if (ext >= 0x02) { + MCOperand_CreateImm0(MI, 31 - cpos); + } + MCOperand_CreateImm0(MI, 32 - clen); + CREATE_GR_REG(MI, t); + break; + case 0x04: + case 0x05: + case 0x06: + case 0x07: + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, 31 - cpos); + } + MCOperand_CreateImm0(MI, 32 - clen); + CREATE_GR_REG(MI, t); + break; + default: + break; + } + } + fill_shexdep1_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_shexdep2_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t cmplt = get_insn_bit(insn, 21); + uint32_t cond = get_insn_field(insn, 16, 18); + push_str_modifier(hppa_ext, signed_unsigned_names[cmplt]); + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); +} + +static bool decode_shexdep2(MCInst *MI, uint32_t insn) +{ + uint32_t pos = (get_insn_bit(insn, 20) << 5) | + get_insn_field(insn, 22, 26); + uint32_t cl = get_insn_bit(insn, 19); + uint32_t clen = get_insn_field(insn, 27, 31); + uint32_t len = (cl + 1) * 32 - clen; + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + MCOperand_CreateImm0(MI, pos); + MCOperand_CreateImm0(MI, len); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + fill_shexdep2_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_shexdep3_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t cmplt = get_insn_bit(insn, 21); + uint32_t cond = get_insn_field(insn, 16, 18); + if (cmplt == 0) { + push_str_modifier(hppa_ext, "z"); + } + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); +} + +static bool decode_shexdep3(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + if (opcode == HPPA_OP_TYPE_SHEXDEP3) { + MCInst_setOpcode(MI, HPPA_INS_DEPD); + } else { + MCInst_setOpcode(MI, HPPA_INS_DEPDI); + } + uint32_t pos = 63 - ((get_insn_bit(insn, 20) << 5) | + get_insn_field(insn, 22, 26)); + uint32_t cl = get_insn_bit(insn, 19); + uint32_t clen = get_insn_field(insn, 27, 31); + uint32_t len = (cl + 1) * 32 - clen; + if (opcode == HPPA_OP_TYPE_SHEXDEP3) { + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + } else { + MCOperand_CreateImm0( + MI, LowSignExtend64(get_insn_field(insn, 11, 15), 5)); + } + MCOperand_CreateImm0(MI, pos); + MCOperand_CreateImm0(MI, len); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + fill_shexdep3_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_multmed_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t bit_16 = get_insn_bit(insn, 16); + uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | + get_insn_field(insn, 20, 21); + if (bit_16 == 0) { + MCInst_setOpcode(MI, HPPA_INS_PERMH); + return; + } + switch (ext) { + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_HSHL); + break; + case 0x0a: + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_HSHR); + break; + case 0x00: + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_MIXW); + break; + case 0x01: + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_MIXH); + break; + default: + break; + } +} + +static void fill_multmed_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t bit_16 = get_insn_bit(insn, 16); + uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | + get_insn_field(insn, 20, 21); + uint32_t eb = get_insn_field(insn, 20, 21); + uint32_t ea = get_insn_field(insn, 17, 18); + if (bit_16 == 0) { + char c[5]; + snprintf(c, sizeof(c), "%d%d%d%d", get_insn_field(insn, 17, 18), + get_insn_field(insn, 20, 21), + get_insn_field(insn, 22, 23), + get_insn_field(insn, 24, 25)); + push_str_modifier(hppa_ext, c); + return; + } + switch (ext) { + case 0x0a: + case 0x0b: + if (eb >= 2) { + push_str_modifier(hppa_ext, + signed_unsigned_names[eb - 2]); + } + break; + case 0x00: + case 0x08: + case 0x01: + case 0x09: + if (ea == 2) { + push_str_modifier(hppa_ext, "l"); + } else if (ea == 0) { + push_str_modifier(hppa_ext, "r"); + } + break; + default: + break; + } +} + +static bool decode_multmed(MCInst *MI, uint32_t insn) +{ + uint32_t bit_16 = get_insn_bit(insn, 16); + uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | + get_insn_field(insn, 20, 21); + uint32_t r1 = get_insn_field(insn, 11, 15); + uint32_t r2 = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t sa = get_insn_field(insn, 22, 25); + if (bit_16 == 0) { + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + goto success; + } + switch (ext) { + case 0x02: + case 0x0a: + case 0x0b: + if (ext >= 0x0a) { + CREATE_GR_REG(MI, r2); + } else { + CREATE_GR_REG(MI, r1); + } + MCOperand_CreateImm0(MI, sa); + CREATE_GR_REG(MI, t); + break; + case 0x00: + case 0x08: + case 0x01: + case 0x09: + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } +success: + fill_multmed_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_branch_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 16, 18); + uint32_t bit_19 = get_insn_bit(insn, 19); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (insn == 0xe8004005) { + MCInst_setOpcode(MI, HPPA_INS_CLRBTS); + return; + } else if (insn == 0xe8004001) { + MCInst_setOpcode(MI, HPPA_INS_PUSHNOM); + return; + } + + switch (ext) { + case 0x00: + case 0x01: + case 0x04: + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_B); + return; + case 0x06: + if (bit_19 == 0) { + MCInst_setOpcode(MI, HPPA_INS_BV); + } else { + MCInst_setOpcode(MI, HPPA_INS_BVE); + } + return; + case 0x07: + if (bit_19 == 1) { + MCInst_setOpcode(MI, HPPA_INS_BVE); + } + return; + case 0x02: + if (get_insn_field(insn, 19, 29) == 0 && + get_insn_bit(insn, 31) == 0) { + MCInst_setOpcode(MI, HPPA_INS_BLR); + return; + } + if (get_insn_field(insn, 19, 31) == 1) { + MCInst_setOpcode(MI, HPPA_INS_PUSHBTS); + return; + } + if (bit_19 == 0 && + get_insn_field(insn, 29, 31) == 0x5) { + MCInst_setOpcode(MI, HPPA_INS_POPBTS); + return; + } + return; + default: + return; + } + } + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_BL); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_GATE); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_BLR); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_BV); + break; + default: + break; + } +} + +static void fill_branch_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t ext = get_insn_field(insn, 16, 18); + uint32_t n = get_insn_bit(insn, 30); + uint32_t p = get_insn_bit(insn, 31); + if (MODE_IS_HPPA_20(mode)) { + switch (ext) { + case 0x00: + case 0x05: + push_str_modifier(hppa_ext, "l"); + // fallthrough + case 0x02: + break; + case 0x01: + push_str_modifier(hppa_ext, "gate"); + break; + case 0x04: + push_str_modifier(hppa_ext, "l"); + push_str_modifier(hppa_ext, "push"); + break; + case 0x06: + case 0x07: + if (get_insn_bit(insn, 19) == 0) { + break; + } + if (ext == 7) { + push_str_modifier(hppa_ext, "l"); + hppa_ext->is_alternative = true; + if (p == 1) { + push_str_modifier(hppa_ext, "push"); + } + } else { + if (p == 1) { + push_str_modifier(hppa_ext, "pop"); + } + } + break; + default: + return; + } + } + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } +} + +static bool decode_branch(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 16, 18); + uint32_t t = get_insn_field(insn, 6, 10); + uint32_t i = get_insn_field(insn, 20, 28); + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t bit_19 = get_insn_bit(insn, 19); + if (MODE_IS_HPPA_20(ud->mode)) { + if (insn == 0xe8004005 || insn == 0xe8004001) { + return true; + } + + switch (ext) { + case 0x01: + case 0x00: + MCOperand_CreateImm0(MI, extract_17(insn)); + CREATE_GR_REG(MI, t); + break; + case 0x04: + case 0x05: + MCOperand_CreateImm0(MI, extract_22(insn)); + CREATE_GR_REG(MI, t); + break; + case 0x02: + if (bit_19 == 1) { + return false; + } + if (get_insn_field(insn, 20, 31) == 1 && t == 0) { + CREATE_GR_REG(MI, r); + break; + } + if (r == 0 && t == 0 && + get_insn_field(insn, 29, 31) == 0x5) { + MCOperand_CreateImm0(MI, i); + break; + } + if (get_insn_bit(insn, 31) == 0 && + get_insn_field(insn, 19, 29) == 0) { + CREATE_GR_REG(MI, r); + CREATE_GR_REG(MI, t); + break; + } + return false; + case 0x06: + if (bit_19 == 0) { + CREATE_GR_REG(MI, r); + } + CREATE_GR_REG(MI, t); + break; + case 0x07: + if (bit_19 == 1) { + CREATE_GR_REG(MI, t); + CREATE_GR_REG(MI, 2); + break; + } + // fallthrough + default: + return false; + } + fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; + } else { + switch (ext) { + case 0x00: + case 0x01: + MCOperand_CreateImm0(MI, extract_17(insn)); + CREATE_GR_REG(MI, t); + break; + case 0x02: + case 0x06: + CREATE_GR_REG(MI, r); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } + fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; + } +} + +static void fill_corpdw_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = (get_insn_field(insn, 19, 19) << 1) | + get_insn_field(insn, 22, 22); + uint32_t opcode = insn >> 26; + uint32_t uid = get_insn_field(insn, 23, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (opcode == 0x09) { + switch (ext) { + case 0x00: + case 0x02: + if (uid <= 0x01) { + MCInst_setOpcode(MI, HPPA_INS_FLDW); + } else { + MCInst_setOpcode(MI, HPPA_INS_CLDW); + } + return; + case 0x01: + case 0x03: + if (uid <= 0x01) { + MCInst_setOpcode(MI, HPPA_INS_FSTW); + } else { + MCInst_setOpcode(MI, HPPA_INS_CSTW); + } + return; + default: + break; + } + } else { + switch (ext) { + case 0x00: + case 0x02: + if (uid == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FLDD); + } else { + MCInst_setOpcode(MI, HPPA_INS_CLDD); + } + return; + case 0x01: + case 0x03: + if (uid == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FSTD); + } else { + MCInst_setOpcode(MI, HPPA_INS_CSTD); + } + return; + default: + break; + } + } + } + if (opcode == 0x09) { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_CLDWX); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_CSTWX); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_CLDWS); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_CSTWS); + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_CLDDX); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_CSTDX); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_CLDDS); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_CSTDS); + break; + default: + break; + } + } +} + +static inline bool coprdw_has_uid_mod(uint32_t opcode, uint32_t uid) +{ + return !((opcode == HPPA_OP_TYPE_COPRW && uid <= 0x01) || + (opcode == HPPA_OP_TYPE_COPRDW && uid == 0x00)); +} + +static void fill_corpdw_mods(uint32_t insn, uint32_t im, hppa_ext *hppa_ext, + cs_mode mode) +{ + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26); + uint32_t cc = get_insn_field(insn, 20, 21); + uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22); + uint32_t opcode = insn >> 26; + + if (coprdw_has_uid_mod(opcode, uid)) { + push_int_modifier(hppa_ext, uid); + } + if (CMPLT_HAS_MODIFY_BIT(cmplt)) { + hppa_ext->b_writeble = true; + } + + switch (ext) { + case 0x00: + case 0x01: + push_str_modifier(hppa_ext, index_compl_names[cmplt]); + break; + case 0x02: + case 0x03: + if (MODE_IS_HPPA_20(mode)) { + if (cmplt == 1 && im == 0) { + push_str_modifier(hppa_ext, "o"); + break; + } + } + push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]); + break; + default: + break; + } + if ((ext & 1) == 1 && cc == 1) { + push_str_modifier(hppa_ext, "bc"); + } + if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } +} + +static bool decode_corpdw(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22); + uint32_t x = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t s = get_insn_field(insn, 16, 17); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t opcode = MCInst_getOpcode(MI); + switch (ext) { + case 0x00: + case 0x02: + if (ext == 0x02) { + x = LowSignExtend64(x, 5); + MCOperand_CreateImm0(MI, x); + } else { + CREATE_GR_REG(MI, x); + } + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + if (opcode == HPPA_INS_FLDW || opcode == HPPA_INS_FLDD) { + CREATE_FPR_REG(MI, t); + } else { + CREATE_GR_REG(MI, t); + } + break; + case 0x01: + case 0x03: + if (opcode == HPPA_INS_FSTW || opcode == HPPA_INS_FSTD) { + CREATE_FPR_REG(MI, t); + } else { + CREATE_GR_REG(MI, t); + } + if (ext == 0x03) { + x = LowSignExtend64(x, 5); + MCOperand_CreateImm0(MI, x); + } else { + CREATE_GR_REG(MI, x); + } + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + break; + default: + break; + } + fill_corpdw_mods(insn, x, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_spop_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 21, 22); + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_SPOP0); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_SPOP1); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_SPOP2); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_SPOP3); + break; + default: + break; + } +} + +static void fill_spop_mods(uint32_t insn, uint32_t ext, hppa_ext *hppa_ext) +{ + uint32_t sfu = get_insn_field(insn, 23, 25); + uint32_t n = get_insn_field(insn, 26, 26); + uint32_t sop; + + push_int_modifier(hppa_ext, sfu); + switch (ext) { + case 0x00: + sop = (get_insn_field(insn, 6, 20) << 5) | + get_insn_field(insn, 27, 31); + break; + case 0x01: + sop = get_insn_field(insn, 6, 20); + break; + case 0x02: + sop = (get_insn_field(insn, 11, 20) << 5) | + get_insn_field(insn, 27, 31); + break; + case 0x03: + sop = (get_insn_field(insn, 16, 20) << 5) | + get_insn_field(insn, 27, 31); + break; + default: + break; + } + push_int_modifier(hppa_ext, sop); + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } +} + +static bool decode_spop(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 21, 22); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + switch (ext) { + case 0x00: + break; + case 0x01: + CREATE_GR_REG(MI, t); + break; + case 0x02: + CREATE_GR_REG(MI, r1); + break; + case 0x03: + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, r1); + break; + default: + return false; + } + fill_spop_mods(insn, ext, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_copr_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t subop; + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FID); + return; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_FNEG); + return; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_FNEGABS); + return; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop != 4) { + MCInst_setOpcode(MI, HPPA_INS_FCNV); + return; + } + } else if (class == 2) { + if (get_insn_bit(insn, 26) == 0) { + MCInst_setOpcode(MI, HPPA_INS_FCMP); + } else { + MCInst_setOpcode(MI, HPPA_INS_FTEST); + } + return; + } + } + } + + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_COPR); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCPY); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FABS); + return; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_FSQRT); + return; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_FRND); + return; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FCNVFF); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FCNVXF); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCNVFX); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FCNVFXT); + return; + default: + break; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FCMP); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FTEST); + return; + default: + break; + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FADD); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FSUB); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FMPY); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FDIV); + return; + default: + break; + } + } + } else if (uid == 2) { + subop = get_insn_field(insn, 18, 22); + switch (subop) { + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_PMDIS); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_PMENB); + return; + default: + break; + } + } + MCInst_setOpcode(MI, HPPA_INS_COPR); +} + +static void fill_copr_mods(uint32_t insn, uint32_t uid, uint32_t class, + hppa_ext *hppa_ext, uint32_t subop, cs_mode mode) +{ + uint32_t n = get_insn_field(insn, 26, 26); + uint32_t sf = get_insn_field(insn, 19, 20); + uint32_t df = get_insn_field(insn, 17, 18); + if (MODE_IS_HPPA_20(mode)) { + if (uid == 0) { + if (class == 0) { + switch (subop) { + case 0x00: + return; + default: + break; + } + } else if (class == 1) { + switch (subop) { + case 0x00: + push_str_modifier( + hppa_ext, + float_format_names[sf]); + push_str_modifier( + hppa_ext, + float_format_names[df]); + return; + case 0x01: + push_str_modifier(hppa_ext, + fcnv_fixed_names[sf]); + push_str_modifier( + hppa_ext, + float_format_names[df]); + return; + case 0x03: + push_str_modifier(hppa_ext, "t"); + // fallthrough + case 0x02: + push_str_modifier( + hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + fcnv_fixed_names[df]); + return; + case 0x05: + push_str_modifier( + hppa_ext, + fcnv_ufixed_names[sf]); + push_str_modifier( + hppa_ext, + float_format_names[df]); + return; + case 0x07: + push_str_modifier(hppa_ext, "t"); + // fallthrough + case 0x06: + push_str_modifier( + hppa_ext, + float_format_names[sf]); + push_str_modifier( + hppa_ext, + fcnv_ufixed_names[df]); + return; + default: + break; + } + } + } + } + + if (uid == 0) { + if (class == 0) { + switch (subop) { + case 0x00: + push_int_modifier(hppa_ext, 0); + push_int_modifier(hppa_ext, 0); + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + break; + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + push_str_modifier(hppa_ext, + float_format_names[sf]); + break; + default: + break; + } + } else if (class == 1) { + push_str_modifier(hppa_ext, float_format_names[sf]); + push_str_modifier(hppa_ext, float_format_names[df]); + } else if (class == 2) { + uint32_t cond = get_insn_field(insn, 27, 31); + if (n == 1 && subop == 1) { + push_str_modifier(hppa_ext, + float_cond_names[cond]); + } + if (n == 0) { + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + float_comp_names[cond]); + } + } else if (class == 3) { + push_str_modifier(hppa_ext, float_format_names[sf]); + } + } else if (uid == 2) { + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + } else { + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t sop = (get_insn_field(insn, 6, 22) << 5) | + get_insn_field(insn, 27, 31); + push_int_modifier(hppa_ext, uid); + push_int_modifier(hppa_ext, sop); + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + } +} + +static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t subop; + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t t = get_insn_field(insn, 27, 31); + if (MODE_IS_HPPA_20(ud->mode)) { + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + if (subop == 0x01) { + return false; + } + if (subop >= 0x02) { + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop == 0x04) { + return false; + } + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + } else if (class == 2) { + uint32_t n = get_insn_bit(insn, 26); + subop = get_insn_field(insn, 16, 18); + if (n == 0) { + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + if (subop != 0) { + MCOperand_CreateImm0(MI, + subop - 1); + HPPA_EXT_REF(MI) + ->is_alternative = true; + } + } else { + if (subop != 1) { + MCOperand_CreateImm0( + MI, (subop ^ 1) - 1); + HPPA_EXT_REF(MI) + ->is_alternative = true; + } + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + if (subop >= 4) { + return false; + } + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + CREATE_FPR_REG(MI, t); + } + fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), + subop, ud->mode); + return true; + } + } + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x02: + case 0x03: + case 0x04: + case 0x05: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + // fallthough + case 0x00: + break; + default: + return false; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + switch (subop) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + break; + default: + return false; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + // fallthough + case 0x01: + break; + default: + return false; + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + CREATE_FPR_REG(MI, t); + break; + default: + return false; + } + } + fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } else if (uid == 2) { + subop = get_insn_field(insn, 18, 22); + switch (subop) { + case 0x01: + case 0x03: + break; + default: + return false; + } + } + fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), -1, ud->mode); + return true; +} + +static void fill_float_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t subop; + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_FNEG); + return; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_FNEGABS); + return; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop == 0x04) { + return; + } + MCInst_setOpcode(MI, HPPA_INS_FCNV); + return; + } else if (class == 2) { + MCInst_setOpcode(MI, HPPA_INS_FCMP); + return; + } + } + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCPY); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FABS); + break; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_FSQRT); + break; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_FRND); + break; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FCNVFF); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FCNVXF); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCNVFX); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FCNVFXT); + break; + default: + break; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + if (subop == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FCMP); + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + uint32_t fixed = get_insn_field(insn, 23, 23); + if (fixed == 0) { + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FADD); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FSUB); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FMPY); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FDIV); + break; + default: + break; + } + } else { + if (subop == 0x02) { + MCInst_setOpcode(MI, HPPA_INS_XMPYU); + } + } + } +} + +static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext, + uint32_t subop, cs_mode mode) +{ + uint32_t sf = get_insn_field(insn, 19, 20); + uint32_t df = get_insn_field(insn, 17, 18); + + if (MODE_IS_HPPA_20(mode)) { + if (class == 1) { + switch (subop) { + case 0x00: + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + float_format_names[df]); + return; + case 0x01: + push_str_modifier(hppa_ext, + fcnv_fixed_names[sf]); + push_str_modifier(hppa_ext, + float_format_names[df]); + return; + case 0x03: + push_str_modifier(hppa_ext, "t"); + // fallthough + case 0x02: + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + fcnv_fixed_names[df]); + return; + case 0x05: + push_str_modifier(hppa_ext, + fcnv_ufixed_names[sf]); + push_str_modifier(hppa_ext, + float_format_names[df]); + return; + case 0x07: + push_str_modifier(hppa_ext, "t"); + // fallthrough + case 0x06: + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + fcnv_ufixed_names[df]); + return; + default: + return; + } + } + } + + if (class == 0) { + uint32_t fmt = get_insn_field(insn, 19, 20); + push_str_modifier(hppa_ext, float_format_names[fmt]); + } else if (class == 1) { + push_str_modifier(hppa_ext, float_format_names[sf]); + push_str_modifier(hppa_ext, float_format_names[df]); + } else if (class == 2) { + uint32_t fmt = get_insn_field(insn, 20, 20); + uint32_t cond = get_insn_field(insn, 27, 31); + push_str_modifier(hppa_ext, float_format_names[fmt]); + push_str_modifier(hppa_ext, float_cond_names[cond]); + } else if (class == 3) { + if (get_insn_field(insn, 23, 23) == 0) { + uint32_t fmt = get_insn_field(insn, 20, 20); + push_str_modifier(hppa_ext, float_format_names[fmt]); + } + } +} + +static bool decode_float(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t subop; + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r1_fpe = get_insn_bit(insn, 24); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t r2_fpe = get_insn_bit(insn, 19); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t t_fpe = get_insn_bit(insn, 25); + if (MODE_IS_HPPA_20(ud->mode)) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + if (subop >= 0x02) { + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), + subop, ud->mode); + return true; + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop == 0x04) { + return false; + } + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + if (subop != 0) { + MCOperand_CreateImm0(MI, subop - 1); + } + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } + } + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x02: + case 0x03: + case 0x04: + case 0x05: + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + default: + return false; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + if (subop <= 0x03) { + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + default: + return false; + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + uint32_t fixed = get_insn_field(insn, 23, 23); + if ((fixed == 0 && subop <= 0x03) || + (fixed == 1 && subop == 0x02)) { + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } + return false; + } + return false; +} + +static void fill_fpfused_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t subop = get_insn_bit(insn, 26); + if (subop == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FMPYFADD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FMPYNFADD); + } +} + +static void fill_fpfused_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t fmt = get_insn_bit(insn, 20); + push_str_modifier(hppa_ext, float_format_names[fmt]); +} + +static bool decode_fpfused(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r1_fpe = get_insn_bit(insn, 24); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t r2_fpe = get_insn_bit(insn, 19); + uint32_t ra = (get_insn_field(insn, 16, 18) << 2) | + get_insn_field(insn, 21, 22); + uint32_t ra_fpe = get_insn_bit(insn, 23); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t t_fpe = get_insn_bit(insn, 25); + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + create_float_reg_spec(MI, ra, ra_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_fpfused_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_action_and_branch_insn_name(MCInst *MI, uint32_t opcode) +{ + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPBDWT: + case HPPA_OP_TYPE_CMPBDWF: + MCInst_setOpcode(MI, HPPA_INS_CMPB); + return; + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + case HPPA_OP_TYPE_CMPIBDW: + MCInst_setOpcode(MI, HPPA_INS_CMPIB); + return; + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + MCInst_setOpcode(MI, HPPA_INS_ADDB); + return; + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + MCInst_setOpcode(MI, HPPA_INS_ADDIB); + return; + case HPPA_OP_TYPE_BBS: + MCInst_setOpcode(MI, HPPA_INS_BB); + return; + default: + break; + } + } + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + MCInst_setOpcode(MI, HPPA_INS_COMBT); + break; + case HPPA_OP_TYPE_CMPBF: + MCInst_setOpcode(MI, HPPA_INS_COMBF); + break; + case HPPA_OP_TYPE_CMPIBT: + MCInst_setOpcode(MI, HPPA_INS_COMIBT); + break; + case HPPA_OP_TYPE_CMPIBF: + MCInst_setOpcode(MI, HPPA_INS_COMIBF); + break; + case HPPA_OP_TYPE_ADDBT: + MCInst_setOpcode(MI, HPPA_INS_ADDBT); + break; + case HPPA_OP_TYPE_ADDBF: + MCInst_setOpcode(MI, HPPA_INS_ADDBF); + break; + case HPPA_OP_TYPE_ADDIBT: + MCInst_setOpcode(MI, HPPA_INS_ADDIBT); + break; + case HPPA_OP_TYPE_ADDIBF: + MCInst_setOpcode(MI, HPPA_INS_ADDIBF); + break; + case HPPA_OP_TYPE_MOVB: + MCInst_setOpcode(MI, HPPA_INS_MOVB); + break; + case HPPA_OP_TYPE_MOVIB: + MCInst_setOpcode(MI, HPPA_INS_MOVIB); + break; + case HPPA_OP_TYPE_BBS: + MCInst_setOpcode(MI, HPPA_INS_BVB); + break; + case HPPA_OP_TYPE_BB: + MCInst_setOpcode(MI, HPPA_INS_BB); + break; + default: + break; + } +} + +static void fill_action_and_branch_mods(uint32_t insn, uint32_t opcode, + hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = get_insn_field(insn, 16, 18); + uint32_t n = get_insn_bit(insn, 30); + uint32_t d = get_insn_bit(insn, 18); + + if (MODE_IS_HPPA_20(mode)) { + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPIBT: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPIBF: + push_str_modifier(hppa_ext, + compare_cond_names[cond + 8]); + break; + case HPPA_OP_TYPE_CMPBDWT: + push_str_modifier(hppa_ext, + compare_cond_64_names[cond]); + break; + case HPPA_OP_TYPE_CMPBDWF: + push_str_modifier(hppa_ext, + compare_cond_64_names[cond + 8]); + break; + case HPPA_OP_TYPE_CMPIBDW: + push_str_modifier(hppa_ext, cmpib_cond_64_names[cond]); + break; + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDIBT: + if (MODE_IS_HPPA_20W(mode)) { + push_str_modifier(hppa_ext, + wide_add_cond_names[cond]); + } else { + push_str_modifier(hppa_ext, + add_cond_names[cond]); + } + break; + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_ADDIBF: + if (MODE_IS_HPPA_20W(mode)) { + push_str_modifier( + hppa_ext, + wide_add_cond_names[cond + 8]); + } else { + push_str_modifier(hppa_ext, + add_cond_names[cond + 8]); + } + break; + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + if (d == 0) { + push_str_modifier(hppa_ext, + shift_cond_names[cond]); + } else { + push_str_modifier(hppa_ext, + shift_cond_64_names[cond]); + } + break; + case HPPA_OP_TYPE_MOVB: + case HPPA_OP_TYPE_MOVIB: + push_str_modifier(hppa_ext, shift_cond_names[cond]); + break; + default: + break; + } + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + return; + } + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + push_str_modifier(hppa_ext, add_cond_names[cond]); + break; + case HPPA_OP_TYPE_MOVB: + case HPPA_OP_TYPE_MOVIB: + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + push_str_modifier(hppa_ext, shift_cond_names[cond]); + break; + default: + break; + } + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } +} + +static bool fill_action_and_branch(const cs_struct *ud, MCInst *MI, + uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r2 = get_insn_field(insn, 11, 15); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPBDWT: + case HPPA_OP_TYPE_CMPBDWF: + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_MOVB: + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, r1); + MCOperand_CreateImm0(MI, extract_12(insn)); + break; + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + case HPPA_OP_TYPE_CMPIBDW: + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + case HPPA_OP_TYPE_MOVIB: + MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5)); + CREATE_GR_REG(MI, r1); + MCOperand_CreateImm0(MI, extract_12(insn)); + break; + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + CREATE_GR_REG(MI, r2); + if ((opcode & 1) == 1) { + MCOperand_CreateImm0(MI, r1); + } else { + CREATE_CR_REG(MI, 11); + } + MCOperand_CreateImm0(MI, extract_12(insn)); + break; + default: + return false; + } + fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), + ud->mode); + return true; + } + if ((opcode & 1) == 0 || opcode == HPPA_OP_TYPE_BB) { + CREATE_GR_REG(MI, r2); + } else { + MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5)); + } + if (opcode == HPPA_OP_TYPE_BB) { + MCOperand_CreateImm0(MI, r1); + } else if (opcode != HPPA_OP_TYPE_BBS) { + CREATE_GR_REG(MI, r1); + } + MCOperand_CreateImm0(MI, extract_12(insn)); + fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_load_insn_name(MCInst *MI, uint32_t opcode) +{ + switch (opcode) { + case HPPA_OP_TYPE_LDB: + MCInst_setOpcode(MI, HPPA_INS_LDB); + break; + case HPPA_OP_TYPE_LDH: + MCInst_setOpcode(MI, HPPA_INS_LDH); + break; + case HPPA_OP_TYPE_LDW: + MCInst_setOpcode(MI, HPPA_INS_LDW); + break; + case HPPA_OP_TYPE_LDWM: + if (MODE_IS_HPPA_20(MI->csh->mode)) { + MCInst_setOpcode(MI, HPPA_INS_LDW); + } else { + MCInst_setOpcode(MI, HPPA_INS_LDWM); + } + break; + default: + break; + } +} + +static void fill_store_insn_name(MCInst *MI, uint32_t opcode) +{ + switch (opcode) { + case HPPA_OP_TYPE_STB: + MCInst_setOpcode(MI, HPPA_INS_STB); + break; + case HPPA_OP_TYPE_STH: + MCInst_setOpcode(MI, HPPA_INS_STH); + break; + case HPPA_OP_TYPE_STW: + MCInst_setOpcode(MI, HPPA_INS_STW); + break; + case HPPA_OP_TYPE_STWM: + if (MODE_IS_HPPA_20(MI->csh->mode)) { + MCInst_setOpcode(MI, HPPA_INS_STW); + } else { + MCInst_setOpcode(MI, HPPA_INS_STWM); + } + break; + default: + break; + } +} + +static bool decode_cmpclr(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t cond = (get_insn_bit(insn, 19) << 3) | + get_insn_field(insn, 16, 18); + uint32_t d = get_insn_bit(insn, 20); + if (MODE_IS_HPPA_20(ud->mode)) { + MCInst_setOpcode(MI, HPPA_INS_CMPICLR); + } else { + MCInst_setOpcode(MI, HPPA_INS_COMICLR); + } + + MCOperand_CreateImm0(MI, + LowSignExtend64(get_insn_field(insn, 21, 31), 11)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + + if (d == 0) { + push_str_modifier(HPPA_EXT_REF(MI), compare_cond_names[cond]); + } else { + push_str_modifier(HPPA_EXT_REF(MI), + compare_cond_64_names[cond]); + } + return true; +} + +static bool decode_be(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t n = get_insn_bit(insn, 30); + bool mode = MODE_IS_HPPA_20(ud->mode); + if (opcode == HPPA_OP_TYPE_BLE) { + if (!mode) { + MCInst_setOpcode(MI, HPPA_INS_BLE); + } else { + MCInst_setOpcode(MI, HPPA_INS_BE); + push_str_modifier(HPPA_EXT_REF(MI), "l"); + HPPA_EXT_REF(MI)->is_alternative = true; + } + } else { + MCInst_setOpcode(MI, HPPA_INS_BE); + } + + MCOperand_CreateImm0(MI, extract_17(insn)); + CREATE_SR_REG(MI, extract_3(insn)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + if (opcode == HPPA_OP_TYPE_BLE && mode) { + CREATE_SR_REG(MI, 0); + CREATE_GR_REG(MI, 31); + } + if (n == 1) { + push_str_modifier(HPPA_EXT_REF(MI), "n"); + } + return true; +} + +static bool decode_float_ldst(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t a = get_insn_bit(insn, 29); + uint32_t disp = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + disp &= ~3; + + if (opcode == HPPA_OP_TYPE_FLDW) { + MCInst_setOpcode(MI, HPPA_INS_FLDW); + MCOperand_CreateImm0(MI, disp); + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15)); + } else { + MCInst_setOpcode(MI, HPPA_INS_FSTW); + CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15)); + MCOperand_CreateImm0(MI, disp); + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + } + + if (a == 0) { + push_str_modifier(HPPA_EXT_REF(MI), "ma"); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "mb"); + } + return true; +} + +static bool decode_fmpy(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t rm1 = get_insn_field(insn, 6, 10); + uint32_t rm2 = get_insn_field(insn, 11, 15); + uint32_t ta = get_insn_field(insn, 16, 20); + uint32_t ra = get_insn_field(insn, 21, 25); + uint32_t tm = get_insn_field(insn, 27, 31); + uint32_t fmt = get_insn_field(insn, 26, 26); + + if (opcode == HPPA_OP_TYPE_FMPYADD) { + MCInst_setOpcode(MI, HPPA_INS_FMPYADD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FMPYSUB); + } + + if (fmt == 0) { + push_str_modifier(HPPA_EXT_REF(MI), "dbl"); + CREATE_FPR_REG(MI, rm1); + CREATE_FPR_REG(MI, rm2); + CREATE_FPR_REG(MI, tm); + CREATE_FPR_REG(MI, ra); + CREATE_FPR_REG(MI, ta); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "sgl"); + CREATE_SP_FPR_REG(MI, rm1); + CREATE_SP_FPR_REG(MI, rm2); + CREATE_SP_FPR_REG(MI, tm); + CREATE_SP_FPR_REG(MI, ra); + CREATE_SP_FPR_REG(MI, ta); + } + + return true; +} + +static bool decode_load(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + if (MODE_IS_HPPA_20(ud->mode)) { + uint32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + if (opcode == HPPA_OP_TYPE_LDWM) { + if (d < 0) { + push_str_modifier(HPPA_EXT_REF(MI), "mb"); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "ma"); + } + } + MCOperand_CreateImm0(MI, d); + } else { + MCOperand_CreateImm0(MI, extract_14(insn)); + } + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + return true; +} + +static bool decode_store(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + if (MODE_IS_HPPA_20(ud->mode)) { + uint32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + if (opcode == HPPA_OP_TYPE_STWM) { + if (d < 0) { + push_str_modifier(HPPA_EXT_REF(MI), "mb"); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "ma"); + } + } + MCOperand_CreateImm0(MI, d); + } else { + MCOperand_CreateImm0(MI, extract_14(insn)); + } + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + return true; +} + +static bool getInstruction(const cs_struct *ud, const uint8_t *code, + size_t code_len, MCInst *MI) +{ + if (code_len < 4) + return false; + + MCInst_clear(MI); + + uint32_t full_insn = readBytes32(MI, code); + uint8_t opcode = full_insn >> 26; + + if (MODE_IS_HPPA_20(ud->mode)) { + switch (opcode) { + case HPPA_OP_TYPE_LOADDW: + case HPPA_OP_TYPE_STOREDW: + fill_ldst_dw_insn_name(MI, full_insn); + return decode_ldst_dw(ud, MI, full_insn); + case HPPA_OP_TYPE_LOADW: + case HPPA_OP_TYPE_STOREW: + fill_ldst_w_insn_name(MI, full_insn); + return decode_ldst_w(ud, MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP2: + MCInst_setOpcode(MI, HPPA_INS_EXTRD); + return decode_shexdep2(MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP3: + case HPPA_OP_TYPE_SHEXDEP4: + return decode_shexdep3(ud, MI, full_insn); + case HPPA_OP_TYPE_MULTMED: + fill_multmed_insn_name(MI, full_insn); + return decode_multmed(MI, full_insn); + case HPPA_OP_TYPE_FPFUSED: + fill_fpfused_insn_name(MI, full_insn); + return decode_fpfused(ud, MI, full_insn); + case HPPA_OP_TYPE_FLDW: + case HPPA_OP_TYPE_FSTW: + return decode_float_ldst(ud, MI, full_insn); + case HPPA_OP_TYPE_CMPBDWT: + case HPPA_OP_TYPE_CMPBDWF: + case HPPA_OP_TYPE_CMPIBDW: + fill_action_and_branch_insn_name(MI, opcode); + return fill_action_and_branch(ud, MI, full_insn); + default: + break; + } + } + + switch (opcode) { + case HPPA_OP_TYPE_SYSOP: + fill_sysop_insn_name(MI, full_insn); + return decode_sysop(ud, MI, full_insn); + case HPPA_OP_TYPE_MEMMGMT: + fill_memmgmt_insn_name(MI, full_insn); + return decode_memmgmt(ud, MI, full_insn); + case HPPA_OP_TYPE_ALU: + fill_alu_insn_name(MI, full_insn); + return decode_alu(ud, MI, full_insn); + case HPPA_OP_TYPE_IDXMEM: + fill_idxmem_insn_name(MI, full_insn); + return decode_idxmem(ud, MI, full_insn); + case HPPA_OP_TYPE_ADDIT: + case HPPA_OP_TYPE_ADDI: + case HPPA_OP_TYPE_SUBI: + fill_arith_imm_insn_name(MI, full_insn); + return decode_arith_imm(ud, MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP0: + fill_shexdep0_insn_name(MI, full_insn); + return decode_shexdep0(ud, MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP1: + fill_shexdep1_insn_name(MI, full_insn); + return decode_shexdep1(ud, MI, full_insn); + case HPPA_OP_TYPE_BRANCH: + fill_branch_insn_name(MI, full_insn); + return decode_branch(ud, MI, full_insn); + case HPPA_OP_TYPE_COPRW: + case HPPA_OP_TYPE_COPRDW: + fill_corpdw_insn_name(MI, full_insn); + return decode_corpdw(ud, MI, full_insn); + case HPPA_OP_TYPE_SPOP: + fill_spop_insn_name(MI, full_insn); + return decode_spop(ud, MI, full_insn); + case HPPA_OP_TYPE_COPR: + fill_copr_insn_name(MI, full_insn); + return decode_copr(ud, MI, full_insn); + case HPPA_OP_TYPE_FLOAT: + fill_float_insn_name(MI, full_insn); + return decode_float(ud, MI, full_insn); + case HPPA_OP_TYPE_DIAG: + MCInst_setOpcode(MI, HPPA_INS_DIAG); + MCOperand_CreateImm0(MI, get_insn_field(full_insn, 6, 31)); + return true; + case HPPA_OP_TYPE_FMPYADD: + case HPPA_OP_TYPE_FMPYSUB: + return decode_fmpy(ud, MI, full_insn); + case HPPA_OP_TYPE_LDIL: + case HPPA_OP_TYPE_ADDIL: + if (opcode == HPPA_OP_TYPE_LDIL) { + MCInst_setOpcode(MI, HPPA_INS_LDIL); + } else { + MCInst_setOpcode(MI, HPPA_INS_ADDIL); + } + MCOperand_CreateImm0(MI, extract_21(full_insn)); + CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10)); + return true; + case HPPA_OP_TYPE_LDO: + MCInst_setOpcode(MI, HPPA_INS_LDO); + if (MODE_IS_HPPA_20(ud->mode)) { + MCOperand_CreateImm0( + MI, extract_16(full_insn, + MODE_IS_HPPA_20W(ud->mode))); + } else { + MCOperand_CreateImm0(MI, extract_14(full_insn)); + } + CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(full_insn, 11, 15)); + return true; + case HPPA_OP_TYPE_LDB: + case HPPA_OP_TYPE_LDH: + case HPPA_OP_TYPE_LDW: + case HPPA_OP_TYPE_LDWM: + fill_load_insn_name(MI, opcode); + return decode_load(ud, MI, full_insn); + case HPPA_OP_TYPE_STB: + case HPPA_OP_TYPE_STH: + case HPPA_OP_TYPE_STW: + case HPPA_OP_TYPE_STWM: + fill_store_insn_name(MI, opcode); + return decode_store(ud, MI, full_insn); + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_MOVB: + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + case HPPA_OP_TYPE_MOVIB: + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + fill_action_and_branch_insn_name(MI, opcode); + return fill_action_and_branch(ud, MI, full_insn); + case HPPA_OP_TYPE_CMPICLR: + return decode_cmpclr(ud, MI, full_insn); + case HPPA_OP_TYPE_BE: + case HPPA_OP_TYPE_BLE: + return decode_be(ud, MI, full_insn); + default: + return false; + } +} + +void init_details(MCInst *MI) +{ + cs_detail *detail = get_detail(MI); + if (detail) { + memset(detail, 0, offsetof(cs_detail, hppa) + sizeof(cs_hppa)); + } +} + +bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) +{ + cs_struct *cs = (cs_struct *)ud; + init_details(instr); + if (!getInstruction(cs, code, code_len, instr)) { + *size = 0; + return false; + } + *size = 4; + return true; +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPADisassembler.h b/arch/HPPA/HPPADisassembler.h new file mode 100644 index 000000000..f4d12e213 --- /dev/null +++ b/arch/HPPA/HPPADisassembler.h @@ -0,0 +1,13 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPA_DISASSEMBLER_H +#define CS_HPPA_DISASSEMBLER_H + +#include "../../MCInst.h" + +bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAInstPrinter.c b/arch/HPPA/HPPAInstPrinter.c new file mode 100644 index 000000000..56a2ff638 --- /dev/null +++ b/arch/HPPA/HPPAInstPrinter.c @@ -0,0 +1,837 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include +#include "../../Mapping.h" +#include "../../utils.h" + +#include "HPPAInstPrinter.h" +#include "HPPAMapping.h" + +static const struct pa_insn pa_insns[] = { + { HPPA_INS_LDI, HPPA_GRP_LONG_IMM }, + { HPPA_INS_CMPIB, HPPA_GRP_BRANCH }, + { HPPA_INS_COMIB, HPPA_GRP_BRANCH }, + { HPPA_INS_CMPB, HPPA_GRP_BRANCH }, + { HPPA_INS_COMB, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDB, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDIB, HPPA_GRP_BRANCH }, + { HPPA_INS_NOP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_COPY, HPPA_GRP_COMPUTATION }, + { HPPA_INS_MTSAR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LDD, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDW, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDH, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDB, HPPA_GRP_MEM_REF }, + { HPPA_INS_STD, HPPA_GRP_MEM_REF }, + { HPPA_INS_STW, HPPA_GRP_MEM_REF }, + { HPPA_INS_STH, HPPA_GRP_MEM_REF }, + { HPPA_INS_STB, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWM, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWM, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDHX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDBX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWA, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCW, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWA, HPPA_GRP_MEM_REF }, + { HPPA_INS_STBY, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDDA, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCD, HPPA_GRP_MEM_REF }, + { HPPA_INS_STDA, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWAX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCWX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDHS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDBS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWAS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCWS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STHS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STBS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWAS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STDBY, HPPA_GRP_MEM_REF }, + { HPPA_INS_STBYS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDO, HPPA_GRP_LONG_IMM }, + { HPPA_INS_LDIL, HPPA_GRP_LONG_IMM }, + { HPPA_INS_ADDIL, HPPA_GRP_LONG_IMM }, + { HPPA_INS_B, HPPA_GRP_BRANCH }, + { HPPA_INS_BL, HPPA_GRP_BRANCH }, + { HPPA_INS_GATE, HPPA_GRP_BRANCH }, + { HPPA_INS_BLR, HPPA_GRP_BRANCH }, + { HPPA_INS_BV, HPPA_GRP_BRANCH }, + { HPPA_INS_BVE, HPPA_GRP_BRANCH }, + { HPPA_INS_BE, HPPA_GRP_BRANCH }, + { HPPA_INS_BLE, HPPA_GRP_BRANCH }, + { HPPA_INS_MOVB, HPPA_GRP_BRANCH }, + { HPPA_INS_MOVIB, HPPA_GRP_BRANCH }, + { HPPA_INS_COMBT, HPPA_GRP_BRANCH }, + { HPPA_INS_COMBF, HPPA_GRP_BRANCH }, + { HPPA_INS_COMIBT, HPPA_GRP_BRANCH }, + { HPPA_INS_COMIBF, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDBT, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDBF, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDIBT, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDIBF, HPPA_GRP_BRANCH }, + { HPPA_INS_BB, HPPA_GRP_BRANCH }, + { HPPA_INS_BVB, HPPA_GRP_BRANCH }, + { HPPA_INS_CLRBTS, HPPA_GRP_BRANCH }, + { HPPA_INS_POPBTS, HPPA_GRP_BRANCH }, + { HPPA_INS_PUSHNOM, HPPA_GRP_BRANCH }, + { HPPA_INS_PUSHBTS, HPPA_GRP_BRANCH }, + { HPPA_INS_CMPCLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_COMCLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_OR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_XOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_AND, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ANDCM, HPPA_GRP_COMPUTATION }, + { HPPA_INS_UXOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_UADDCM, HPPA_GRP_COMPUTATION }, + { HPPA_INS_UADDCMT, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DCOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_IDCOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDIO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDIT, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDITO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDC, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDCO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUB, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBB, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBBO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBT, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBTO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DS, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBIO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_CMPICLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_COMICLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SHLADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH1ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH1ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH1ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH2ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH2ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH2ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH3ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH3ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH3ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_HADD, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HAVG, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHL, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHLADD, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHR, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHRADD, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSUB, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_MIXH, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_MIXW, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_PERMH, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_SHRPD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SHRPW, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VSHD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SHD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRW, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VEXTRU, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VEXTRS, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRU, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRS, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPDI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPW, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPWI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZVDEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VDEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZDEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZVDEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VDEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZDEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_BREAK, HPPA_GRP_SYSCTRL }, + { HPPA_INS_RFI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_RFIR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SSM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_RSM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTSM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LDSID, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTSP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTCTL, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTSARCM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFIA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFSP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFCTL, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SYNC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SYNCDMA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBEI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBER, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBERI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBEW, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBEWI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LPA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LCI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PDTLB, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PITLB, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PDTLBE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PITLBE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IDTLBA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IITLBA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IDTLBP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IITLBP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PDC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FDC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FIC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FDCE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FICE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_DIAG, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IDTLBT, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IITLBT, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTCPU, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFCPU, HPPA_GRP_SYSCTRL }, + { HPPA_INS_TOCEN, HPPA_GRP_SYSCTRL }, + { HPPA_INS_TOCDIS, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SHDWGR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_GRSHDW, HPPA_GRP_SYSCTRL }, + { HPPA_INS_GFW, HPPA_GRP_SYSCTRL }, + { HPPA_INS_GFR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FLDW, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDD, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTW, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTD, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDWX, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDDX, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTWX, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTDX, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTQX, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDWS, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDDS, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTWS, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTDS, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTQS, HPPA_GRP_FLOAT }, + { HPPA_INS_FADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FSUB, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPY, HPPA_GRP_FLOAT }, + { HPPA_INS_FDIV, HPPA_GRP_FLOAT }, + { HPPA_INS_FSQRT, HPPA_GRP_FLOAT }, + { HPPA_INS_FABS, HPPA_GRP_FLOAT }, + { HPPA_INS_FREM, HPPA_GRP_FLOAT }, + { HPPA_INS_FRND, HPPA_GRP_FLOAT }, + { HPPA_INS_FCPY, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVFF, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVXF, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVFX, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVFXT, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYFADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYNFADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FNEG, HPPA_GRP_FLOAT }, + { HPPA_INS_FNEGABS, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNV, HPPA_GRP_FLOAT }, + { HPPA_INS_FCMP, HPPA_GRP_FLOAT }, + { HPPA_INS_XMPYU, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYSUB, HPPA_GRP_FLOAT }, + { HPPA_INS_FTEST, HPPA_GRP_FLOAT }, + { HPPA_INS_FID, HPPA_GRP_FLOAT }, + { HPPA_INS_PMDIS, HPPA_GRP_PERFMON }, + { HPPA_INS_PMENB, HPPA_GRP_PERFMON }, + { HPPA_INS_SPOP0, HPPA_GRP_ASSIST }, + { HPPA_INS_SPOP1, HPPA_GRP_ASSIST }, + { HPPA_INS_SPOP2, HPPA_GRP_ASSIST }, + { HPPA_INS_SPOP3, HPPA_GRP_ASSIST }, + { HPPA_INS_COPR, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDW, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDD, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTW, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTD, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDWX, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDDX, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTWX, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTDX, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDWS, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDDS, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTWS, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTDS, HPPA_GRP_ASSIST }, + { HPPA_INS_CALL, HPPA_GRP_INVALID }, + { HPPA_INS_RET, HPPA_GRP_INVALID }, +}; + +static void set_op_imm(cs_hppa *hppa, uint64_t val) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_IMM; + op->imm = val; +} + +static void set_op_reg(cs_hppa *hppa, uint64_t val, cs_ac_type access) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_REG; + op->reg = val; + op->access = access; +} + +static void set_op_idx_reg(cs_hppa *hppa, uint64_t reg) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_IDX_REG; + op->reg = reg; + op->access = CS_AC_READ; +} + +static void set_op_disp(cs_hppa *hppa, uint64_t val) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_DISP; + op->imm = val; +} + +static void set_op_target(cs_hppa *hppa, uint64_t val) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_TARGET; + op->imm = val; +} + +static void set_op_mem(cs_hppa *hppa, uint32_t base, uint32_t space, + cs_ac_type base_access) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_MEM; + op->mem.base = base; + op->mem.space = space; + op->mem.base_access = base_access; +} +/* HPPA instruction formats (access) + i - imm arguments + R - read access register + W - write access register + w - read + write access register + r - index register (read only) + T - offset (pc relative) + o - displacement (imm) + x - [r] or [o] defined by the operand kind + b - base register (may be writable in some cases) +*/ +static const struct pa_insn_fmt pa_formats[] = { + { HPPA_INS_LDI, "iW", false }, + + { HPPA_INS_CMPIB, "iRT", false }, + { HPPA_INS_COMIB, "iRT", false }, + + { HPPA_INS_CMPB, "RRT", false }, + { HPPA_INS_COMB, "RRT", false }, + + { HPPA_INS_ADDB, "RwT", false }, + + { HPPA_INS_ADDIB, "iwT", false }, + + { HPPA_INS_NOP, "", false }, + { HPPA_INS_COPY, "RW", false }, + { HPPA_INS_MTSAR, "R", false }, + + { HPPA_INS_LDD, "x(Rb)W", false }, + { HPPA_INS_LDW, "x(Rb)W", false }, + { HPPA_INS_LDH, "x(Rb)W", false }, + { HPPA_INS_LDB, "x(Rb)W", false }, + { HPPA_INS_STD, "Ro(Rb)", false }, + { HPPA_INS_STW, "Ro(Rb)", false }, + { HPPA_INS_STH, "Ro(Rb)", false }, + { HPPA_INS_STB, "Ro(Rb)", false }, + { HPPA_INS_LDWM, "o(Rw)W", false }, + { HPPA_INS_STWM, "Ro(Rw)", false }, + { HPPA_INS_LDWX, "r(Rb)W", false }, + { HPPA_INS_LDHX, "r(Rb)W", false }, + { HPPA_INS_LDBX, "r(Rb)W", false }, + { HPPA_INS_LDWA, "x(R)W", false }, + { HPPA_INS_LDCW, "x(Rb)W", false }, + { HPPA_INS_STWA, "Ro(b)", false }, + { HPPA_INS_STBY, "Ro(Rb)", false }, + { HPPA_INS_LDDA, "x(b)W", false }, + { HPPA_INS_LDCD, "x(Rb)W", false }, + { HPPA_INS_STDA, "Ro(b)", false }, + { HPPA_INS_LDWAX, "r(b)W", false }, + { HPPA_INS_LDCWX, "r(Rb)W", false }, + { HPPA_INS_LDWS, "o(Rb)W", false }, + { HPPA_INS_LDHS, "o(Rb)W", false }, + { HPPA_INS_LDBS, "o(Rb)W", false }, + { HPPA_INS_LDWAS, "o(b)W", false }, + { HPPA_INS_LDCWS, "o(Rb)W", false }, + { HPPA_INS_STWS, "Ro(Rb)", false }, + { HPPA_INS_STHS, "Ro(Rb)", false }, + { HPPA_INS_STBS, "Ro(Rb)", false }, + { HPPA_INS_STWAS, "Ro(b)", false }, + { HPPA_INS_STDBY, "Ro(Rb)", false }, + { HPPA_INS_STBYS, "Ro(Rb)", false }, + + { HPPA_INS_LDO, "o(R)W", false }, + { HPPA_INS_LDIL, "iW", false }, + { HPPA_INS_ADDIL, "iR", false }, + + { HPPA_INS_B, "TW", false }, + { HPPA_INS_BL, "TW", false }, + { HPPA_INS_GATE, "TW", false }, + { HPPA_INS_BLR, "RW", false }, + { HPPA_INS_BV, "x(R)", false }, + { HPPA_INS_BVE, "(b)", false }, + { HPPA_INS_BVE, "(b)W", true }, + { HPPA_INS_BE, "o(RR)", false }, + { HPPA_INS_BE, "o(RR)WW", true }, + { HPPA_INS_BLE, "o(RR)", false }, + { HPPA_INS_MOVB, "RWT", false }, + { HPPA_INS_MOVIB, "iWT", false }, + { HPPA_INS_COMBT, "RRT", false }, + { HPPA_INS_COMBF, "RRT", false }, + { HPPA_INS_COMIBT, "iRT", false }, + { HPPA_INS_COMIBF, "iRT", false }, + { HPPA_INS_ADDBT, "RwT", false }, + { HPPA_INS_ADDBF, "RwT", false }, + { HPPA_INS_ADDIBT, "iwT", false }, + { HPPA_INS_ADDIBF, "iwT", false }, + { HPPA_INS_BB, "RiT", false }, + { HPPA_INS_BVB, "RT", false }, + { HPPA_INS_CLRBTS, "", false }, + { HPPA_INS_POPBTS, "i", false }, + { HPPA_INS_PUSHNOM, "", false }, + { HPPA_INS_PUSHBTS, "R", false }, + + { HPPA_INS_CMPCLR, "RRW", false }, + { HPPA_INS_COMCLR, "RRW", false }, + { HPPA_INS_OR, "RRW", false }, + { HPPA_INS_XOR, "RRW", false }, + { HPPA_INS_AND, "RRW", false }, + { HPPA_INS_ANDCM, "RRW", false }, + { HPPA_INS_UXOR, "RRW", false }, + { HPPA_INS_UADDCM, "RRW", false }, + { HPPA_INS_UADDCMT, "RRW", false }, + { HPPA_INS_DCOR, "RW", false }, + { HPPA_INS_IDCOR, "RW", false }, + { HPPA_INS_ADDI, "iRW", false }, + { HPPA_INS_ADDIO, "iRW", false }, + { HPPA_INS_ADDIT, "iRW", false }, + { HPPA_INS_ADDITO, "iRW", false }, + { HPPA_INS_ADD, "RRW", false }, + { HPPA_INS_ADDL, "RRW", false }, + { HPPA_INS_ADDO, "RRW", false }, + { HPPA_INS_ADDC, "RRW", false }, + { HPPA_INS_ADDCO, "RRW", false }, + { HPPA_INS_SUB, "RRW", false }, + { HPPA_INS_SUBO, "RRW", false }, + { HPPA_INS_SUBB, "RRW", false }, + { HPPA_INS_SUBBO, "RRW", false }, + { HPPA_INS_SUBT, "RRW", false }, + { HPPA_INS_SUBTO, "RRW", false }, + { HPPA_INS_DS, "RRW", false }, + { HPPA_INS_SUBI, "iRW", false }, + { HPPA_INS_SUBIO, "iRW", false }, + { HPPA_INS_CMPICLR, "iRW", false }, + { HPPA_INS_COMICLR, "iRW", false }, + { HPPA_INS_SHLADD, "RiRW", false }, + { HPPA_INS_SH1ADD, "RRW", false }, + { HPPA_INS_SH1ADDL, "RRW", false }, + { HPPA_INS_SH1ADDO, "RRW", false }, + { HPPA_INS_SH2ADD, "RRW", false }, + { HPPA_INS_SH2ADDL, "RRW", false }, + { HPPA_INS_SH2ADDO, "RRW", false }, + { HPPA_INS_SH3ADD, "RRW", false }, + { HPPA_INS_SH3ADDL, "RRW", false }, + { HPPA_INS_SH3ADDO, "RRW", false }, + + { HPPA_INS_HADD, "RRW", false }, + { HPPA_INS_HAVG, "RRW", false }, + { HPPA_INS_HSHL, "RiW", false }, + { HPPA_INS_HSHLADD, "RiRW", false }, + { HPPA_INS_HSHR, "RiW", false }, + { HPPA_INS_HSHRADD, "RiRW", false }, + { HPPA_INS_HSUB, "RRW", false }, + { HPPA_INS_MIXH, "RRW", false }, + { HPPA_INS_MIXW, "RRW", false }, + { HPPA_INS_PERMH, "RW", false }, + + { HPPA_INS_SHRPD, "RRiW", false }, + { HPPA_INS_SHRPD, "RRRW", true }, + { HPPA_INS_SHRPW, "RRiW", false }, + { HPPA_INS_SHRPW, "RRRW", true }, + { HPPA_INS_VSHD, "RRW", false }, + { HPPA_INS_SHD, "RRiW", false }, + { HPPA_INS_EXTRD, "RiiW", false }, + { HPPA_INS_EXTRD, "RRiW", true }, + { HPPA_INS_EXTRW, "RiiW", false }, + { HPPA_INS_EXTRW, "RRiW", true }, + { HPPA_INS_VEXTRU, "RiW", false }, + { HPPA_INS_VEXTRS, "RiW", false }, + { HPPA_INS_EXTRU, "RiiW", false }, + { HPPA_INS_EXTRS, "RiiW", false }, + { HPPA_INS_DEPD, "RiiW", false }, + { HPPA_INS_DEPDI, "iiiW", false }, + { HPPA_INS_DEPW, "RiiW", false }, + { HPPA_INS_DEPW, "RRiW", true }, + { HPPA_INS_DEPWI, "iiiW", false }, + { HPPA_INS_DEPWI, "iRiW", true }, + { HPPA_INS_ZVDEP, "RiW", false }, + { HPPA_INS_VDEP, "RiW", false }, + { HPPA_INS_ZDEP, "RiiW", false }, + { HPPA_INS_DEP, "RiiW", false }, + { HPPA_INS_ZVDEPI, "iiW", false }, + { HPPA_INS_VDEPI, "iiW", false }, + { HPPA_INS_ZDEPI, "iiiW", false }, + { HPPA_INS_DEPI, "iiiW", false }, + + { HPPA_INS_BREAK, "ii", false }, + { HPPA_INS_RFI, "", false }, + { HPPA_INS_RFIR, "", false }, + { HPPA_INS_SSM, "iW", false }, + { HPPA_INS_RSM, "iW", false }, + { HPPA_INS_MTSM, "R", false }, + { HPPA_INS_LDSID, "(RR)W", false }, + { HPPA_INS_MTSP, "RW", false }, + { HPPA_INS_MTCTL, "RW", false }, + { HPPA_INS_MTSARCM, "R", false }, + { HPPA_INS_MFIA, "W", false }, + { HPPA_INS_MFSP, "RW", false }, + { HPPA_INS_MFCTL, "RW", false }, + { HPPA_INS_SYNC, "", false }, + { HPPA_INS_SYNCDMA, "", false }, + { HPPA_INS_PROBE, "(RR)RW", false }, + { HPPA_INS_PROBEI, "(RR)iW", false }, + { HPPA_INS_PROBER, "(RR)RW", false }, + { HPPA_INS_PROBERI, "(RR)iW", false }, + { HPPA_INS_PROBEW, "(RR)RW", false }, + { HPPA_INS_PROBEWI, "(RR)iW", false }, + { HPPA_INS_LPA, "r(Rb)W", false }, + { HPPA_INS_LCI, "r(RR)W", false }, + { HPPA_INS_PDTLB, "r(Rb)", false }, + { HPPA_INS_PITLB, "r(Rb)", false }, + { HPPA_INS_PDTLBE, "r(Rb)", false }, + { HPPA_INS_PITLBE, "r(Rb)", false }, + { HPPA_INS_IDTLBA, "R(RR)", false }, + { HPPA_INS_IITLBA, "R(RR)", false }, + { HPPA_INS_IDTLBP, "R(RR)", false }, + { HPPA_INS_IITLBP, "R(RR)", false }, + { HPPA_INS_PDC, "r(Rb)", false }, + { HPPA_INS_FDC, "x(Rb)", false }, + { HPPA_INS_FIC, "r(Rb)", false }, + { HPPA_INS_FDCE, "r(Rb)", false }, + { HPPA_INS_FICE, "r(Rb)", false }, + { HPPA_INS_DIAG, "i", false }, + { HPPA_INS_IDTLBT, "RR", false }, + { HPPA_INS_IITLBT, "RR", false }, + + { HPPA_INS_FLDW, "x(Rb)W", false }, + { HPPA_INS_FLDD, "x(Rb)W", false }, + { HPPA_INS_FSTW, "Rx(Rb)", false }, + { HPPA_INS_FSTD, "Rx(Rb)", false }, + { HPPA_INS_FLDWX, "r(Rb)W", false }, + { HPPA_INS_FLDDX, "r(Rb)W", false }, + { HPPA_INS_FSTWX, "Rr(Rb)", false }, + { HPPA_INS_FSTDX, "Rr(Rb)", false }, + { HPPA_INS_FSTQX, "", false }, + { HPPA_INS_FLDWS, "o(Rb)W", false }, + { HPPA_INS_FLDDS, "o(Rb)W", false }, + { HPPA_INS_FSTWS, "Ro(Rb)", false }, + { HPPA_INS_FSTDS, "Ro(Rb)", false }, + { HPPA_INS_FSTQS, "Ro(Rb)", false }, + { HPPA_INS_FADD, "RRW", false }, + { HPPA_INS_FSUB, "RRW", false }, + { HPPA_INS_FMPY, "RRW", false }, + { HPPA_INS_FDIV, "RRW", false }, + { HPPA_INS_FSQRT, "RW", false }, + { HPPA_INS_FABS, "RW", false }, + { HPPA_INS_FREM, "", false }, + { HPPA_INS_FRND, "RW", false }, + { HPPA_INS_FCPY, "RW", false }, + { HPPA_INS_FCNVFF, "RW", false }, + { HPPA_INS_FCNVXF, "RW", false }, + { HPPA_INS_FCNVFX, "RW", false }, + { HPPA_INS_FCNVFXT, "RW", false }, + { HPPA_INS_FMPYFADD, "RRRW", false }, + { HPPA_INS_FMPYNFADD, "RRRW", false }, + { HPPA_INS_FNEG, "RW", false }, + { HPPA_INS_FNEGABS, "RW", false }, + { HPPA_INS_FCNV, "RW", false }, + { HPPA_INS_FCMP, "RR", false }, + { HPPA_INS_FCMP, "RRi", true }, + { HPPA_INS_XMPYU, "RRW", false }, + { HPPA_INS_FMPYADD, "RRWRw", false }, + { HPPA_INS_FMPYSUB, "RRWRw", false }, + { HPPA_INS_FTEST, "", false }, + { HPPA_INS_FTEST, "i", true }, + { HPPA_INS_FID, "", false }, + + { HPPA_INS_PMDIS, "", false }, + { HPPA_INS_PMENB, "", false }, + + { HPPA_INS_SPOP0, "", false }, + { HPPA_INS_SPOP1, "W", false }, + { HPPA_INS_SPOP2, "R", false }, + { HPPA_INS_SPOP3, "RR", false }, + { HPPA_INS_COPR, "", false }, + { HPPA_INS_CLDW, "x(Rb)W", false }, + { HPPA_INS_CLDD, "o(Rb)W", false }, + { HPPA_INS_CSTW, "Rx(Rb)", false }, + { HPPA_INS_CSTD, "Rx(Rb)", false }, + { HPPA_INS_CLDWX, "r(Rb)W", false }, + { HPPA_INS_CLDDX, "r(Rb)W", false }, + { HPPA_INS_CSTWX, "Rr(Rb)", false }, + { HPPA_INS_CSTDX, "Rr(Rb)", false }, + { HPPA_INS_CLDWS, "o(Rb)W", false }, + { HPPA_INS_CLDDS, "o(Rb)W", false }, + { HPPA_INS_CSTWS, "Ro(Rb)", false }, + { HPPA_INS_CSTDS, "Ro(Rb)", false }, + + { HPPA_INS_CALL, "", false }, + { HPPA_INS_RET, "", false }, +}; + +static void print_operand(MCInst *MI, SStream *O, const cs_hppa_op *op) +{ + switch (op->type) { + case HPPA_OP_INVALID: + SStream_concat(O, "invalid"); + break; + case HPPA_OP_REG: + SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg)); + break; + case HPPA_OP_IMM: + printInt32(O, op->imm); + break; + case HPPA_OP_DISP: + printInt32(O, op->imm); + break; + case HPPA_OP_IDX_REG: + SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg)); + break; + case HPPA_OP_MEM: + SStream_concat(O, "("); + if (op->mem.space != HPPA_OP_INVALID && + op->mem.space != HPPA_REG_SR0) { + SStream_concat(O, HPPA_reg_name((csh)MI->csh, + op->mem.space)); + SStream_concat(O, ","); + } + SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->mem.base)); + SStream_concat(O, ")"); + break; + case HPPA_OP_TARGET: + printUInt64(O, MI->address + op->imm); + break; + } +} + +#define NUMFMTS ARR_SIZE(pa_formats) + +static void fill_operands(MCInst *MI, cs_hppa *hppa) +{ + hppa->op_count = 0; + unsigned mc_op_count = MCInst_getNumOperands(MI); + if (mc_op_count == 0) + return; + + hppa_ext *hppa_ext = &MI->hppa_ext; + uint32_t opcode = MCInst_getOpcode(MI); + + for (int i = 0; i < NUMFMTS; ++i) { + const struct pa_insn_fmt *pa_fmt = &pa_formats[i]; + if (opcode != pa_fmt->insn_id || + hppa_ext->is_alternative != pa_fmt->is_alternative) { + continue; + } + const char *fmt = pa_fmt->format; + uint8_t idx = 0; + uint32_t space_regs[2] = { HPPA_REG_INVALID, HPPA_REG_INVALID }; + uint8_t space_reg_idx = 0; + cs_ac_type base_access = CS_AC_INVALID; + MCOperand *op = NULL; + while (*fmt) { + op = MCInst_getOperand(MI, idx++); + switch (*fmt++) { + case 'i': + if (MCOperand_isReg(op)) { + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_READ); + } else { + set_op_imm(hppa, MCOperand_getImm(op)); + } + break; + case 'o': + set_op_disp(hppa, MCOperand_getImm(op)); + break; + + case 'R': + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_READ); + break; + + case 'W': + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_WRITE); + break; + + case 'w': + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_READ_WRTE); + break; + + case 'r': + set_op_idx_reg(hppa, MCOperand_getReg(op)); + break; + + case 'T': + set_op_target(hppa, MCOperand_getImm(op) + 8); + break; + + case 'x': + if (MCOperand_isReg(op)) { + set_op_idx_reg(hppa, + MCOperand_getReg(op)); + } else { + set_op_disp(hppa, MCOperand_getImm(op)); + } + break; + + case '(': + while (*fmt != ')') { + if (space_reg_idx > 0) { + op = MCInst_getOperand(MI, + idx++); + } + assert(space_reg_idx < + ARR_SIZE(space_regs)); + space_regs[space_reg_idx] = + MCOperand_getReg(op); + if (*fmt == 'R') { + base_access = CS_AC_READ; + } else if (*fmt == 'W') { + base_access = CS_AC_WRITE; + } else if (*fmt == 'b') { + base_access = CS_AC_READ; + if (hppa_ext->b_writeble) + base_access |= + CS_AC_WRITE; + } + fmt++; + space_reg_idx++; + } + + if (space_regs[1] == HPPA_REG_INVALID) + set_op_mem(hppa, space_regs[0], + space_regs[1], base_access); + else + set_op_mem(hppa, space_regs[1], + space_regs[0], base_access); + fmt++; + break; + + default: + printf("Unknown: %c\n", *(fmt - 1)); + break; + } + } + break; + } +} + +static void print_modifiers(MCInst *MI, SStream *O) +{ + hppa_ext *hppa_ext = &MI->hppa_ext; + for (uint8_t i = 0; i < hppa_ext->mod_num; ++i) { + SStream_concat(O, ","); + if (hppa_ext->modifiers[i].type == HPPA_MOD_STR) + SStream_concat(O, hppa_ext->modifiers[i].str_mod); + else + SStream_concat(O, "%d", hppa_ext->modifiers[i].int_mod); + } +} + +static void add_groups(MCInst *MI) +{ + unsigned int opcode = MCInst_getOpcode(MI); + for (unsigned i = 0; i < ARR_SIZE(pa_insns); ++i) { + if (pa_insns[i].insn != opcode) { + continue; + } + add_group(MI, pa_insns[i].grp); + } +} + +static void update_regs_access(MCInst *MI, unsigned int opcode) +{ + if (opcode == HPPA_INS_INVALID) + return; + + hppa_ext *hppa_ext = &MI->hppa_ext; + switch (opcode) { + default: + break; + case HPPA_INS_BLE: + map_add_implicit_write(MI, HPPA_REG_GR31); + map_add_implicit_write(MI, HPPA_REG_SR0); + break; + case HPPA_INS_BVB: + map_add_implicit_read(MI, HPPA_REG_CR11); + break; + case HPPA_INS_RFI: + if (hppa_ext->mod_num == 0) { + break; + } + // fallthrough + case HPPA_INS_RFIR: + map_add_implicit_write(MI, HPPA_REG_GR1); + map_add_implicit_write(MI, HPPA_REG_GR8); + map_add_implicit_write(MI, HPPA_REG_GR9); + map_add_implicit_write(MI, HPPA_REG_GR16); + map_add_implicit_write(MI, HPPA_REG_GR17); + map_add_implicit_write(MI, HPPA_REG_GR24); + map_add_implicit_write(MI, HPPA_REG_GR25); + break; + case HPPA_INS_VDEP: + case HPPA_INS_VDEPI: + case HPPA_INS_VEXTRS: + case HPPA_INS_VEXTRU: + case HPPA_INS_VSHD: + case HPPA_INS_ZVDEPI: + map_add_implicit_read(MI, HPPA_REG_CR11); + break; + case HPPA_INS_ADDIL: + map_add_implicit_write(MI, HPPA_REG_GR1); + break; + } +} + +void HPPA_printInst(MCInst *MI, SStream *O, void *Info) +{ + cs_hppa hppa; + + /* set pubOpcode as instruction id */ + MCInst_setOpcodePub(MI, MCInst_getOpcode(MI)); + + SStream_concat(O, HPPA_insn_name((csh)MI->csh, MCInst_getOpcode(MI))); + print_modifiers(MI, O); + SStream_concat(O, " "); + fill_operands(MI, &hppa); + for (int i = 0; i < hppa.op_count; i++) { + cs_hppa_op *op = &hppa.operands[i]; + print_operand(MI, O, op); + if (op->type != HPPA_OP_IDX_REG && op->type != HPPA_OP_DISP && + i != hppa.op_count - 1) { + SStream_concat(O, ","); + } + } + + if (detail_is_set(MI)) { + cs_hppa *hppa_detail = HPPA_get_detail(MI); + *hppa_detail = hppa; + add_groups(MI); +#ifndef CAPSTONE_DIET + update_regs_access(MI, MCInst_getOpcode(MI)); +#endif + } +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAInstPrinter.h b/arch/HPPA/HPPAInstPrinter.h new file mode 100644 index 000000000..8bf1c673b --- /dev/null +++ b/arch/HPPA/HPPAInstPrinter.h @@ -0,0 +1,25 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPAINSTPRINTER_H +#define CS_HPPAINSTPRINTER_H + +#include + +#include "../../MCInst.h" +#include "../../SStream.h" + +struct pa_insn { + hppa_insn insn; + hppa_insn_group grp; +}; + +struct pa_insn_fmt { + hppa_insn insn_id; + const char *format; + bool is_alternative; ///< true if some completer affects the instruction format +}; + +void HPPA_printInst(MCInst *MI, SStream *O, void *Info); + +#endif diff --git a/arch/HPPA/HPPAMapping.c b/arch/HPPA/HPPAMapping.c new file mode 100644 index 000000000..75f03dc2d --- /dev/null +++ b/arch/HPPA/HPPAMapping.c @@ -0,0 +1,440 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include +#include + +#include "HPPAMapping.h" +#include "HPPAConstants.h" +#include "../../Mapping.h" +#include "../../utils.h" + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + { HPPA_GRP_INVALID, NULL }, + + { HPPA_GRP_COMPUTATION, "computation" }, + { HPPA_GRP_MULTIMEDIA, "multimedia" }, + { HPPA_GRP_MEM_REF, "memory_reference" }, + { HPPA_GRP_LONG_IMM, "long_imm" }, + { HPPA_GRP_BRANCH, "branch" }, + { HPPA_GRP_SYSCTRL, "system_control" }, + { HPPA_GRP_ASSIST, "assist" }, + { HPPA_GRP_FLOAT, "float" }, +}; +#endif + +const char *HPPA_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map insn_name_maps[HPPA_INS_ENDING] = { + { HPPA_INS_INVALID, NULL }, + + { HPPA_INS_ADD, "add" }, + { HPPA_INS_ADDI, "addi" }, + { HPPA_INS_ADDIO, "addio" }, + { HPPA_INS_ADDIT, "addit" }, + { HPPA_INS_ADDITO, "addito" }, + { HPPA_INS_ADDB, "addb" }, + { HPPA_INS_ADDBT, "addbt" }, + { HPPA_INS_ADDBF, "addbf" }, + { HPPA_INS_ADDIB, "addib" }, + { HPPA_INS_ADDIBT, "addibt" }, + { HPPA_INS_ADDIBF, "addibf" }, + { HPPA_INS_ADDIL, "addil" }, + { HPPA_INS_ADDC, "addc" }, + { HPPA_INS_ADDCO, "addco" }, + { HPPA_INS_ADDL, "addl" }, + { HPPA_INS_ADDO, "addo" }, + { HPPA_INS_AND, "and" }, + { HPPA_INS_ANDCM, "andcm" }, + { HPPA_INS_B, "b" }, + { HPPA_INS_BB, "bb" }, + { HPPA_INS_BE, "be" }, + { HPPA_INS_BL, "bl" }, + { HPPA_INS_BLE, "ble" }, + { HPPA_INS_BLR, "blr" }, + { HPPA_INS_BREAK, "break" }, + { HPPA_INS_BV, "bv" }, + { HPPA_INS_BVB, "bvb" }, + { HPPA_INS_BVE, "bve" }, + { HPPA_INS_CALL, "call" }, + { HPPA_INS_CLDD, "cldd" }, + { HPPA_INS_CLDDS, "cldds" }, + { HPPA_INS_CLDDX, "clddx" }, + { HPPA_INS_CLDW, "cldw" }, + { HPPA_INS_CLDWS, "cldws" }, + { HPPA_INS_CLDWX, "cldwx" }, + { HPPA_INS_CLRBTS, "clrbts" }, + { HPPA_INS_CMPB, "cmpb" }, + { HPPA_INS_CMPCLR, "cmpclr" }, + { HPPA_INS_CMPIB, "cmpib" }, + { HPPA_INS_CMPICLR, "cmpiclr" }, + { HPPA_INS_COMB, "comb" }, + { HPPA_INS_COMBT, "combt" }, + { HPPA_INS_COMBF, "combf" }, + { HPPA_INS_COMCLR, "comclr" }, + { HPPA_INS_COMIB, "comib" }, + { HPPA_INS_COMIBT, "comibt" }, + { HPPA_INS_COMIBF, "comibf" }, + { HPPA_INS_COMICLR, "comiclr" }, + { HPPA_INS_COPR, "copr" }, + { HPPA_INS_COPY, "copy" }, + { HPPA_INS_CSTD, "cstd" }, + { HPPA_INS_CSTDS, "cstds" }, + { HPPA_INS_CSTDX, "cstdx" }, + { HPPA_INS_CSTW, "cstw" }, + { HPPA_INS_CSTWS, "cstws" }, + { HPPA_INS_CSTWX, "cstwx" }, + { HPPA_INS_DCOR, "dcor" }, + { HPPA_INS_DEP, "dep" }, + { HPPA_INS_DEPI, "depi" }, + { HPPA_INS_DEPD, "depd" }, + { HPPA_INS_DEPDI, "depdi" }, + { HPPA_INS_DEPW, "depw" }, + { HPPA_INS_DEPWI, "depwi" }, + { HPPA_INS_DIAG, "diag" }, + { HPPA_INS_DS, "ds" }, + { HPPA_INS_EXTRD, "extrd" }, + { HPPA_INS_EXTRS, "extrs" }, + { HPPA_INS_EXTRU, "extru" }, + { HPPA_INS_EXTRW, "extrw" }, + { HPPA_INS_FABS, "fabs" }, + { HPPA_INS_FADD, "fadd" }, + { HPPA_INS_FCMP, "fcmp" }, + { HPPA_INS_FCNV, "fcnv" }, + { HPPA_INS_FCNVFF, "fcnvff" }, + { HPPA_INS_FCNVFX, "fcnvfx" }, + { HPPA_INS_FCNVFXT, "fcnvfxt" }, + { HPPA_INS_FCNVXF, "fcnvxf" }, + { HPPA_INS_FCPY, "fcpy" }, + { HPPA_INS_FDC, "fdc" }, + { HPPA_INS_FDCE, "fdce" }, + { HPPA_INS_FDIV, "fdiv" }, + { HPPA_INS_FIC, "fic" }, + { HPPA_INS_FICE, "fice" }, + { HPPA_INS_FID, "fid" }, + { HPPA_INS_FLDD, "fldd" }, + { HPPA_INS_FLDDS, "fldds" }, + { HPPA_INS_FLDDX, "flddx" }, + { HPPA_INS_FLDW, "fldw" }, + { HPPA_INS_FLDWS, "fldws" }, + { HPPA_INS_FLDWX, "fldwx" }, + { HPPA_INS_FMPY, "fmpy" }, + { HPPA_INS_FMPYADD, "fmpyadd" }, + { HPPA_INS_FMPYFADD, "fmpyfadd" }, + { HPPA_INS_FMPYNFADD, "fmpynfadd" }, + { HPPA_INS_FMPYSUB, "fmpysub" }, + { HPPA_INS_FNEG, "fneg" }, + { HPPA_INS_FNEGABS, "fnegabs" }, + { HPPA_INS_FREM, "frem" }, + { HPPA_INS_FRND, "frnd" }, + { HPPA_INS_FSQRT, "fsqrt" }, + { HPPA_INS_FSTD, "fstd" }, + { HPPA_INS_FSTDS, "fstds" }, + { HPPA_INS_FSTDX, "fstdx" }, + { HPPA_INS_FSTW, "fstw" }, + { HPPA_INS_FSTWS, "fstws" }, + { HPPA_INS_FSTWX, "fstwx" }, + { HPPA_INS_FSTQS, "fstqs" }, + { HPPA_INS_FSTQX, "fstqx" }, + { HPPA_INS_FSUB, "fsub" }, + { HPPA_INS_FTEST, "ftest" }, + { HPPA_INS_GATE, "gate" }, + { HPPA_INS_GFR, "gfr" }, + { HPPA_INS_GFW, "gfw" }, + { HPPA_INS_GRSHDW, "grshdw" }, + { HPPA_INS_HADD, "hadd" }, + { HPPA_INS_HAVG, "havg" }, + { HPPA_INS_HSHL, "hshl" }, + { HPPA_INS_HSHLADD, "hshladd" }, + { HPPA_INS_HSHR, "hshr" }, + { HPPA_INS_HSHRADD, "hshradd" }, + { HPPA_INS_HSUB, "hsub" }, + { HPPA_INS_IDTLBA, "idtlba" }, + { HPPA_INS_IDTLBP, "idtlbp" }, + { HPPA_INS_IDTLBT, "idtlbt" }, + { HPPA_INS_IDCOR, "idcor" }, + { HPPA_INS_IITLBA, "iitlba" }, + { HPPA_INS_IITLBP, "iitlbp" }, + { HPPA_INS_IITLBT, "iitlbt" }, + { HPPA_INS_LCI, "lci" }, + { HPPA_INS_LDB, "ldb" }, + { HPPA_INS_LDBS, "ldbs" }, + { HPPA_INS_LDBX, "ldbx" }, + { HPPA_INS_LDCD, "ldcd" }, + { HPPA_INS_LDCW, "ldcw" }, + { HPPA_INS_LDCWS, "ldcws" }, + { HPPA_INS_LDCWX, "ldcwx" }, + { HPPA_INS_LDD, "ldd" }, + { HPPA_INS_LDDA, "ldda" }, + { HPPA_INS_LDH, "ldh" }, + { HPPA_INS_LDHS, "ldhs" }, + { HPPA_INS_LDHX, "ldhx" }, + { HPPA_INS_LDI, "ldi" }, + { HPPA_INS_LDIL, "ldil" }, + { HPPA_INS_LDO, "ldo" }, + { HPPA_INS_LDSID, "ldsid" }, + { HPPA_INS_LDW, "ldw" }, + { HPPA_INS_LDWA, "ldwa" }, + { HPPA_INS_LDWAS, "ldwas" }, + { HPPA_INS_LDWAX, "ldwax" }, + { HPPA_INS_LDWM, "ldwm" }, + { HPPA_INS_LDWS, "ldws" }, + { HPPA_INS_LDWX, "ldwx" }, + { HPPA_INS_LPA, "lpa" }, + { HPPA_INS_MFCPU, "mfcpu" }, + { HPPA_INS_MFCTL, "mfctl" }, + { HPPA_INS_MFIA, "mfia" }, + { HPPA_INS_MFSP, "mfsp" }, + { HPPA_INS_MIXH, "mixh" }, + { HPPA_INS_MIXW, "mixw" }, + { HPPA_INS_MOVB, "movb" }, + { HPPA_INS_MOVIB, "movib" }, + { HPPA_INS_MTCPU, "mtcpu" }, + { HPPA_INS_MTCTL, "mtctl" }, + { HPPA_INS_MTSAR, "mtsar" }, + { HPPA_INS_MTSARCM, "mtsarcm" }, + { HPPA_INS_MTSM, "mtsm" }, + { HPPA_INS_MTSP, "mtsp" }, + { HPPA_INS_NOP, "nop" }, + { HPPA_INS_OR, "or" }, + { HPPA_INS_PDC, "pdc" }, + { HPPA_INS_PDTLB, "pdtlb" }, + { HPPA_INS_PDTLBE, "pdtlbe" }, + { HPPA_INS_PERMH, "permh" }, + { HPPA_INS_PITLB, "pitlb" }, + { HPPA_INS_PITLBE, "pitlbe" }, + { HPPA_INS_PMDIS, "pmdis" }, + { HPPA_INS_PMENB, "pmenb" }, + { HPPA_INS_POPBTS, "popbts" }, + { HPPA_INS_PROBE, "probe" }, + { HPPA_INS_PROBEI, "probei" }, + { HPPA_INS_PROBER, "prober" }, + { HPPA_INS_PROBERI, "proberi" }, + { HPPA_INS_PROBEW, "probew" }, + { HPPA_INS_PROBEWI, "probewi" }, + { HPPA_INS_PUSHBTS, "pushbts" }, + { HPPA_INS_PUSHNOM, "pushnom" }, + { HPPA_INS_RET, "ret" }, + { HPPA_INS_RFI, "rfi" }, + { HPPA_INS_RFIR, "rfir" }, + { HPPA_INS_RSM, "rsm" }, + { HPPA_INS_SHDWGR, "shdwgr" }, + { HPPA_INS_SHLADD, "shladd" }, + { HPPA_INS_SH1ADD, "sh1add" }, + { HPPA_INS_SH1ADDL, "sh1addl" }, + { HPPA_INS_SH1ADDO, "sh1addo" }, + { HPPA_INS_SH2ADD, "sh2add" }, + { HPPA_INS_SH2ADDL, "sh2addl" }, + { HPPA_INS_SH2ADDO, "sh2addo" }, + { HPPA_INS_SH3ADD, "sh3add" }, + { HPPA_INS_SH3ADDL, "sh3addl" }, + { HPPA_INS_SH3ADDO, "sh3addo" }, + { HPPA_INS_SHD, "shd" }, + { HPPA_INS_SHRPD, "shrpd" }, + { HPPA_INS_SHRPW, "shrpw" }, + { HPPA_INS_SPOP0, "spop0" }, + { HPPA_INS_SPOP1, "spop1" }, + { HPPA_INS_SPOP2, "spop2" }, + { HPPA_INS_SPOP3, "spop3" }, + { HPPA_INS_SSM, "ssm" }, + { HPPA_INS_STB, "stb" }, + { HPPA_INS_STBS, "stbs" }, + { HPPA_INS_STBY, "stby" }, + { HPPA_INS_STBYS, "stbys" }, + { HPPA_INS_STD, "std" }, + { HPPA_INS_STDA, "stda" }, + { HPPA_INS_STDBY, "stdby" }, + { HPPA_INS_STH, "sth" }, + { HPPA_INS_STHS, "sths" }, + { HPPA_INS_STW, "stw" }, + { HPPA_INS_STWA, "stwa" }, + { HPPA_INS_STWAS, "stwas" }, + { HPPA_INS_STWS, "stws" }, + { HPPA_INS_STWM, "stwm" }, + { HPPA_INS_SUB, "sub" }, + { HPPA_INS_SUBB, "subb" }, + { HPPA_INS_SUBBO, "subbo" }, + { HPPA_INS_SUBI, "subi" }, + { HPPA_INS_SUBIO, "subio" }, + { HPPA_INS_SUBO, "subo" }, + { HPPA_INS_SUBT, "subt" }, + { HPPA_INS_SUBTO, "subto" }, + { HPPA_INS_SYNC, "sync" }, + { HPPA_INS_SYNCDMA, "syncdma" }, + { HPPA_INS_TOCDIS, "tocdis" }, + { HPPA_INS_TOCEN, "tocen" }, + { HPPA_INS_UADDCM, "uaddcm" }, + { HPPA_INS_UADDCMT, "uaddcmt" }, + { HPPA_INS_UXOR, "uxor" }, + { HPPA_INS_VDEP, "vdep" }, + { HPPA_INS_VDEPI, "vdepi" }, + { HPPA_INS_VEXTRS, "vextrs" }, + { HPPA_INS_VEXTRU, "vextru" }, + { HPPA_INS_VSHD, "vshd" }, + { HPPA_INS_XMPYU, "xmpyu" }, + { HPPA_INS_XOR, "xor" }, + { HPPA_INS_ZDEP, "zdep" }, + { HPPA_INS_ZDEPI, "zdepi" }, + { HPPA_INS_ZVDEP, "zvdep" }, + { HPPA_INS_ZVDEPI, "zvdepi" }, +}; +#endif + +const char *HPPA_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(insn_name_maps, ARR_SIZE(insn_name_maps), id); +#else + return NULL; +#endif +} + +/* Integer register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const reg_names[] = { + "flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "dp", "ret0", "ret1", "sp", "r31" +}; + +/* Floating point register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const fp_reg_names[] = { + "fpsr", "fpe2", "fpe4", "fpe6", "fr4", "fr5", "fr6", "fr7", + "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", + "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31" +}; + +static const char *const control_reg[] = { + "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", + "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", "iva", "eiem", + "itmr", "pcsq", "pcoq", "iir", "isr", "ior", "ipsw", "eirr", + "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7" +}; + +static const char *const space_reg[] = { "sr0", "sr1", "sr2", "sr3", + "sr4", "sr5", "sr6", "sr7" }; + +static const char *const fpe_reg[] = { + "fpe1", "fpe3", "fpe5", "fpe7", "fr4R", "fr5R", "fr6R", "fr7R", + "fr8R", "fr9R", "fr10R", "fr11R", "fr12R", "fr13R", "fr14R", "fr15R", + "fr16R", "fr17R", "fr18R", "fr19R", "fr20R", "fr21R", "fr22R", "fr23R", + "fr24R", "fr25R", "fr26R", "fr27R", "fr28R", "fr29R", "fr30R", "fr31R" +}; + +static const char *const sp_fp_reg[] = { + "fr16L", "fr17L", "fr18L", "fr19L", "fr20L", "fr21L", "fr22L", "fr23L", + "fr24L", "fr25L", "fr26L", "fr27L", "fr28L", "fr29L", "fr30L", "fr31L", + "fr16R", "fr17R", "fr18R", "fr19R", "fr20R", "fr21R", "fr22R", "fr23R", + "fr24R", "fr25R", "fr26R", "fr27R", "fr28R", "fr29R", "fr30R", "fr31R" +}; + +const char *HPPA_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= HPPA_REG_GR0 && reg <= HPPA_REG_GR31) + return reg_names[reg - HPPA_REG_GR0]; + else if (reg >= HPPA_REG_FPR0 && reg <= HPPA_REG_FPR31) + return fp_reg_names[reg - HPPA_REG_FPR0]; + else if (reg >= HPPA_REG_SR0 && reg <= HPPA_REG_SR7) + return space_reg[reg - HPPA_REG_SR0]; + else if (reg >= HPPA_REG_CR0 && reg <= HPPA_REG_CR31) + return control_reg[reg - HPPA_REG_CR0]; + else if (reg >= HPPA_REG_FPE0 && reg <= HPPA_REG_FPE31) + return fpe_reg[reg - HPPA_REG_FPE0]; + else if (reg >= HPPA_REG_SP_FPR0 && reg <= HPPA_REG_SP_FPR31) + return sp_fp_reg[reg - HPPA_REG_SP_FPR0]; + return NULL; +#else + return NULL; +#endif +} + +void HPPA_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int opcode) +{ + insn->id = opcode; +} + +static void sort_and_uniq(cs_regs arr, uint8_t n, uint8_t *new_n) +{ + /* arr is always a tiny (usually n < 3) array, + * a simple O(n^2) sort is efficient enough. */ + int i; + int j; + int iMin; + int tmp; + + /* a modified selection sort for sorting and making unique */ + for (j = 0; j < n; j++) { + /* arr[iMin] will be min(arr[j .. n-1]) */ + iMin = j; + for (i = j + 1; i < n; i++) { + if (arr[i] < arr[iMin]) + iMin = i; + } + if (j != 0 && arr[iMin] == arr[j - 1]) { // duplicate ele found + arr[iMin] = arr[n - 1]; + --n; + } else { + tmp = arr[iMin]; + arr[iMin] = arr[j]; + arr[j] = tmp; + } + } + + *new_n = n; +} + +void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) +{ + uint8_t read_count = 0; + uint8_t write_count = 0; + const cs_hppa *hppa = &(insn->detail->hppa); + + for (unsigned i = 0; i < hppa->op_count; ++i) { + const cs_hppa_op *op = &(hppa->operands[i]); + switch (op->type) { + case HPPA_OP_REG: + case HPPA_OP_IDX_REG: + if (op->access & CS_AC_READ) { + regs_read[read_count++] = op->reg; + } + if (op->access & CS_AC_WRITE) { + regs_write[write_count++] = op->reg; + } + break; + case HPPA_OP_MEM: + if (op->mem.space != HPPA_OP_INVALID) + regs_read[read_count++] = op->mem.space; + if (op->mem.base_access & CS_AC_READ) { + regs_read[read_count++] = op->mem.base; + } + if (op->mem.base_access & CS_AC_WRITE) { + regs_write[write_count++] = op->mem.base; + } + break; + default: + break; + } + } + + sort_and_uniq(regs_read, read_count, regs_read_count); + sort_and_uniq(regs_write, write_count, regs_write_count); +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAMapping.h b/arch/HPPA/HPPAMapping.h new file mode 100644 index 000000000..6b62fe3a3 --- /dev/null +++ b/arch/HPPA/HPPAMapping.h @@ -0,0 +1,19 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPAMAPPING_H +#define CS_HPPAMAPPING_H + +#include + +#include "../../cs_priv.h" + +const char *HPPA_group_name(csh handle, unsigned int id); +const char *HPPA_insn_name(csh handle, unsigned int id); +const char *HPPA_reg_name(csh handle, unsigned int reg); +void HPPA_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); +void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAModule.c b/arch/HPPA/HPPAModule.c new file mode 100644 index 000000000..ad4c9663e --- /dev/null +++ b/arch/HPPA/HPPAModule.c @@ -0,0 +1,34 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include "HPPADisassembler.h" +#include "HPPAInstPrinter.h" +#include "HPPAMapping.h" +#include "HPPAModule.h" + +cs_err HPPA_global_init(cs_struct *ud) +{ + ud->printer = HPPA_printInst; + ud->reg_name = HPPA_reg_name; + ud->insn_id = HPPA_get_insn_id; + ud->insn_name = HPPA_insn_name; + ud->group_name = HPPA_group_name; +#ifndef CAPSTONE_DIET + ud->reg_access = HPPA_reg_access; +#endif + ud->disasm = HPPA_getInstruction; + + return CS_ERR_OK; +} + +cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_MODE) + handle->mode = (cs_mode)value; + + return CS_ERR_OK; +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAModule.h b/arch/HPPA/HPPAModule.h new file mode 100644 index 000000000..c1949ec1b --- /dev/null +++ b/arch/HPPA/HPPAModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPA_MODULE_H +#define CS_HPPA_MODULE_H + +#include "../../utils.h" + +cs_err HPPA_global_init(cs_struct *ud); +cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/bindings/Makefile b/bindings/Makefile index c730917d4..85e570500 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -24,6 +24,7 @@ TEST_TRICORE = $(TMPDIR)/test_tricore TEST_SH = $(TMPDIR)/test_sh TEST_TMS320C64X = $(TMPDIR)/test_tms320c64x TEST_ALPHA = $(TMPDIR)/test_alpha +TEST_HPPA = $(TMPDIR)/test_hppa PYTHON3 ?= python3 @@ -66,6 +67,7 @@ expected: ../tests/test_tricore > $(TEST_TRICORE)_e ../tests/test_tms320c64x > $(TEST_TMS320C64X)_e ../tests/test_alpha > $(TEST_ALPHA)_e + ../tests/test_hppa > $(TEST_HPPA)_e python: FORCE cd python && $(MAKE) @@ -91,6 +93,7 @@ python: FORCE $(PYTHON3) python/test_tricore.py > $(TEST_TRICORE)_o $(PYTHON3) python/test_tms320c64x.py > $(TEST_TMS320C64X)_o $(PYTHON3) python/test_alpha.py > $(TEST_ALPHA)_o + $(PYTHON3) python/test_hppa.py > $(TEST_HPPA)_o $(MAKE) test_diff java: FORCE @@ -131,6 +134,7 @@ test_diff: FORCE $(DIFF) $(TEST_TRICORE)_e $(TEST_TRICORE)_o $(DIFF) $(TEST_TMS320C64X)_e $(TEST_TMS320C64X)_o $(DIFF) $(TEST_ALPHA)_e $(TEST_ALPHA)_o + $(DIFF) $(TEST_HPPA)_e $(TEST_HPPA)_o clean: rm -rf $(TMPDIR) diff --git a/bindings/const_generator.py b/bindings/const_generator.py index 2171c7b78..70bd94ef3 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -5,7 +5,7 @@ import sys, re INCL_DIR = '../include/capstone/' -include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h' ] +include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h' ] template = { 'java': { @@ -54,6 +54,7 @@ template = { 'sh.h': 'sh', 'tricore.h': ['TRICORE', 'TriCore'], 'alpha.h': ['ALPHA', 'Alpha'], + 'hppa.h': 'hppa', 'comment_open': '#', 'comment_close': '', }, diff --git a/bindings/python/Makefile b/bindings/python/Makefile index a1e6f7bf1..10b9af313 100644 --- a/bindings/python/Makefile +++ b/bindings/python/Makefile @@ -71,7 +71,7 @@ clean: TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py test_mips.py TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py -TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py +TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py test_hppa.py TESTS += test_lite.py test_iter.py test_customized_mnem.py test_alpha.py check: diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 729fb5829..8e1174e39 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -42,6 +42,7 @@ __all__ = [ 'CS_ARCH_SH', 'CS_ARCH_TRICORE', 'CS_ARCH_ALPHA', + 'CS_ARCH_HPPA', 'CS_ARCH_ALL', 'CS_MODE_LITTLE_ENDIAN', @@ -106,6 +107,9 @@ __all__ = [ 'CS_MODE_TRICORE_160', 'CS_MODE_TRICORE_161', 'CS_MODE_TRICORE_162', + 'CS_MODE_HPPA_11', + 'CS_MODE_HPPA_20', + 'CS_MODE_HPPA_20W', 'CS_OPT_SYNTAX', 'CS_OPT_SYNTAX_DEFAULT', @@ -219,7 +223,8 @@ CS_ARCH_RISCV = 15 CS_ARCH_SH = 16 CS_ARCH_TRICORE = 17 CS_ARCH_ALPHA = 18 -CS_ARCH_MAX = 19 +CS_ARCH_HPPA = 19 +CS_ARCH_MAX = 20 CS_ARCH_ALL = 0xFFFF # disasm mode @@ -285,6 +290,9 @@ CS_MODE_TRICORE_131 = 1 << 4 # Tricore 1.3.1 CS_MODE_TRICORE_160 = 1 << 5 # Tricore 1.6 CS_MODE_TRICORE_161 = 1 << 6 # Tricore 1.6.1 CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2 +CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1 +CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0 +CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide # Capstone option type CS_OPT_INVALID = 0 # No option specified @@ -443,7 +451,7 @@ def copy_ctypes_list(src): return [copy_ctypes(n) for n in src] # Weird import placement because these modules are needed by the below code but need the above functions -from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha +from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha, hppa class _cs_arch(ctypes.Union): _fields_ = ( @@ -466,6 +474,7 @@ class _cs_arch(ctypes.Union): ('sh', sh.CsSH), ('tricore', tricore.CsTriCore), ('alpha', alpha.CsAlpha), + ('hppa', hppa.CsHPPA), ) class _cs_detail(ctypes.Structure): @@ -817,6 +826,8 @@ class CsInsn(object): (self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore) elif arch == CS_ARCH_ALPHA: (self.operands) = alpha.get_arch_info(self._raw.detail.contents.arch.alpha) + elif arch == CS_ARCH_HPPA: + (self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa) def __getattr__(self, name): @@ -1310,6 +1321,7 @@ def debug(): "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX, 'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE, 'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA, + 'hppa': CS_ARCH_HPPA } all_archs = "" diff --git a/bindings/python/capstone/hppa.py b/bindings/python/capstone/hppa.py new file mode 100644 index 000000000..3bc1077de --- /dev/null +++ b/bindings/python/capstone/hppa.py @@ -0,0 +1,72 @@ +# Capstone Python bindings, by Dmitry Sibirtsev + +import ctypes +from . import copy_ctypes_list +from .hppa_const import * + + + +class HPPAOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint), + ('space', ctypes.c_uint), + ('base_access', ctypes.c_uint8), + ) + +class HPPAModifierValue(ctypes.Union): + _fields_ = ( + ('str_mod', ctypes.c_char_p), + ('int_mod', ctypes.c_uint32) + ) + +class HPPAModifier(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_int), + ('value', HPPAModifierValue) + ) + +class HPPAExt(ctypes.Structure): + _fields_ = ( + ('modifiers', HPPAModifier * 5), + ('mod_num', ctypes.c_uint8), + ('b_writable', ctypes.c_bool), + ('cmplt', ctypes.c_bool) + ) + +class HPPAOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', HPPAOpMem) + ) + + +class HPPAOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint8), + ('value', HPPAOpValue), + ('access', ctypes.c_uint8) + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +# Instruction structure +class CsHPPA(ctypes.Structure): + _fields_ = ( + ('op_count', ctypes.c_uint8), + ('operands', HPPAOp * 5) + ) + +def get_arch_info(a): + return (copy_ctypes_list(a.operands[:a.op_count])) diff --git a/bindings/python/capstone/hppa_const.py b/bindings/python/capstone/hppa_const.py new file mode 100644 index 000000000..060ce987c --- /dev/null +++ b/bindings/python/capstone/hppa_const.py @@ -0,0 +1,453 @@ +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py] +HPPA_MAX_OPS = 5 +HPPA_STR_MODIFIER_LEN = 8 +HPPA_MAX_MODIFIERS_LEN = 5 + +HPPA_OP_INVALID = 0 +HPPA_OP_REG = 1 +HPPA_OP_IMM = 2 +HPPA_OP_IDX_REG = 3 +HPPA_OP_DISP = 4 +HPPA_OP_MEM = 5 +HPPA_OP_TARGET = 6 + +# HPPA registers + +HPPA_REG_INVALID = 0 +HPPA_REG_GR0 = 1 +HPPA_REG_GR1 = 2 +HPPA_REG_GR2 = 3 +HPPA_REG_GR3 = 4 +HPPA_REG_GR4 = 5 +HPPA_REG_GR5 = 6 +HPPA_REG_GR6 = 7 +HPPA_REG_GR7 = 8 +HPPA_REG_GR8 = 9 +HPPA_REG_GR9 = 10 +HPPA_REG_GR10 = 11 +HPPA_REG_GR11 = 12 +HPPA_REG_GR12 = 13 +HPPA_REG_GR13 = 14 +HPPA_REG_GR14 = 15 +HPPA_REG_GR15 = 16 +HPPA_REG_GR16 = 17 +HPPA_REG_GR17 = 18 +HPPA_REG_GR18 = 19 +HPPA_REG_GR19 = 20 +HPPA_REG_GR20 = 21 +HPPA_REG_GR21 = 22 +HPPA_REG_GR22 = 23 +HPPA_REG_GR23 = 24 +HPPA_REG_GR24 = 25 +HPPA_REG_GR25 = 26 +HPPA_REG_GR26 = 27 +HPPA_REG_GR27 = 28 +HPPA_REG_GR28 = 29 +HPPA_REG_GR29 = 30 +HPPA_REG_GR30 = 31 +HPPA_REG_GR31 = 32 +HPPA_REG_FPR0 = 33 +HPPA_REG_FPR1 = 34 +HPPA_REG_FPR2 = 35 +HPPA_REG_FPR3 = 36 +HPPA_REG_FPR4 = 37 +HPPA_REG_FPR5 = 38 +HPPA_REG_FPR6 = 39 +HPPA_REG_FPR7 = 40 +HPPA_REG_FPR8 = 41 +HPPA_REG_FPR9 = 42 +HPPA_REG_FPR10 = 43 +HPPA_REG_FPR11 = 44 +HPPA_REG_FPR12 = 45 +HPPA_REG_FPR13 = 46 +HPPA_REG_FPR14 = 47 +HPPA_REG_FPR15 = 48 +HPPA_REG_FPR16 = 49 +HPPA_REG_FPR17 = 50 +HPPA_REG_FPR18 = 51 +HPPA_REG_FPR19 = 52 +HPPA_REG_FPR20 = 53 +HPPA_REG_FPR21 = 54 +HPPA_REG_FPR22 = 55 +HPPA_REG_FPR23 = 56 +HPPA_REG_FPR24 = 57 +HPPA_REG_FPR25 = 58 +HPPA_REG_FPR26 = 59 +HPPA_REG_FPR27 = 60 +HPPA_REG_FPR28 = 61 +HPPA_REG_FPR29 = 62 +HPPA_REG_FPR30 = 63 +HPPA_REG_FPR31 = 64 +HPPA_REG_SR0 = 65 +HPPA_REG_SR1 = 66 +HPPA_REG_SR2 = 67 +HPPA_REG_SR3 = 68 +HPPA_REG_SR4 = 69 +HPPA_REG_SR5 = 70 +HPPA_REG_SR6 = 71 +HPPA_REG_SR7 = 72 +HPPA_REG_CR0 = 73 +HPPA_REG_CR1 = 74 +HPPA_REG_CR2 = 75 +HPPA_REG_CR3 = 76 +HPPA_REG_CR4 = 77 +HPPA_REG_CR5 = 78 +HPPA_REG_CR6 = 79 +HPPA_REG_CR7 = 80 +HPPA_REG_CR8 = 81 +HPPA_REG_CR9 = 82 +HPPA_REG_CR10 = 83 +HPPA_REG_CR11 = 84 +HPPA_REG_CR12 = 85 +HPPA_REG_CR13 = 86 +HPPA_REG_CR14 = 87 +HPPA_REG_CR15 = 88 +HPPA_REG_CR16 = 89 +HPPA_REG_CR17 = 90 +HPPA_REG_CR18 = 91 +HPPA_REG_CR19 = 92 +HPPA_REG_CR20 = 93 +HPPA_REG_CR21 = 94 +HPPA_REG_CR22 = 95 +HPPA_REG_CR23 = 96 +HPPA_REG_CR24 = 97 +HPPA_REG_CR25 = 98 +HPPA_REG_CR26 = 99 +HPPA_REG_CR27 = 100 +HPPA_REG_CR28 = 101 +HPPA_REG_CR29 = 102 +HPPA_REG_CR30 = 103 +HPPA_REG_CR31 = 104 +HPPA_REG_FPE0 = 105 +HPPA_REG_FPE1 = 106 +HPPA_REG_FPE2 = 107 +HPPA_REG_FPE3 = 108 +HPPA_REG_FPE4 = 109 +HPPA_REG_FPE5 = 110 +HPPA_REG_FPE6 = 111 +HPPA_REG_FPE7 = 112 +HPPA_REG_FPE8 = 113 +HPPA_REG_FPE9 = 114 +HPPA_REG_FPE10 = 115 +HPPA_REG_FPE11 = 116 +HPPA_REG_FPE12 = 117 +HPPA_REG_FPE13 = 118 +HPPA_REG_FPE14 = 119 +HPPA_REG_FPE15 = 120 +HPPA_REG_FPE16 = 121 +HPPA_REG_FPE17 = 122 +HPPA_REG_FPE18 = 123 +HPPA_REG_FPE19 = 124 +HPPA_REG_FPE20 = 125 +HPPA_REG_FPE21 = 126 +HPPA_REG_FPE22 = 127 +HPPA_REG_FPE23 = 128 +HPPA_REG_FPE24 = 129 +HPPA_REG_FPE25 = 130 +HPPA_REG_FPE26 = 131 +HPPA_REG_FPE27 = 132 +HPPA_REG_FPE28 = 133 +HPPA_REG_FPE29 = 134 +HPPA_REG_FPE30 = 135 +HPPA_REG_FPE31 = 136 +HPPA_REG_SP_FPR0 = 137 +HPPA_REG_SP_FPR1 = 138 +HPPA_REG_SP_FPR2 = 139 +HPPA_REG_SP_FPR3 = 140 +HPPA_REG_SP_FPR4 = 141 +HPPA_REG_SP_FPR5 = 142 +HPPA_REG_SP_FPR6 = 143 +HPPA_REG_SP_FPR7 = 144 +HPPA_REG_SP_FPR8 = 145 +HPPA_REG_SP_FPR9 = 146 +HPPA_REG_SP_FPR10 = 147 +HPPA_REG_SP_FPR11 = 148 +HPPA_REG_SP_FPR12 = 149 +HPPA_REG_SP_FPR13 = 150 +HPPA_REG_SP_FPR14 = 151 +HPPA_REG_SP_FPR15 = 152 +HPPA_REG_SP_FPR16 = 153 +HPPA_REG_SP_FPR17 = 154 +HPPA_REG_SP_FPR18 = 155 +HPPA_REG_SP_FPR19 = 156 +HPPA_REG_SP_FPR20 = 157 +HPPA_REG_SP_FPR21 = 158 +HPPA_REG_SP_FPR22 = 159 +HPPA_REG_SP_FPR23 = 160 +HPPA_REG_SP_FPR24 = 161 +HPPA_REG_SP_FPR25 = 162 +HPPA_REG_SP_FPR26 = 163 +HPPA_REG_SP_FPR27 = 164 +HPPA_REG_SP_FPR28 = 165 +HPPA_REG_SP_FPR29 = 166 +HPPA_REG_SP_FPR30 = 167 +HPPA_REG_SP_FPR31 = 168 +HPPA_REG_ENDING = 169 + +HPPA_INS_INVALID = 0 +HPPA_INS_ADD = 1 +HPPA_INS_ADDI = 2 +HPPA_INS_ADDIO = 3 +HPPA_INS_ADDIT = 4 +HPPA_INS_ADDITO = 5 +HPPA_INS_ADDB = 6 +HPPA_INS_ADDBT = 7 +HPPA_INS_ADDBF = 8 +HPPA_INS_ADDIB = 9 +HPPA_INS_ADDIBT = 10 +HPPA_INS_ADDIBF = 11 +HPPA_INS_ADDIL = 12 +HPPA_INS_ADDC = 13 +HPPA_INS_ADDCO = 14 +HPPA_INS_ADDL = 15 +HPPA_INS_ADDO = 16 +HPPA_INS_AND = 17 +HPPA_INS_ANDCM = 18 +HPPA_INS_B = 19 +HPPA_INS_BB = 20 +HPPA_INS_BE = 21 +HPPA_INS_BL = 22 +HPPA_INS_BLE = 23 +HPPA_INS_BLR = 24 +HPPA_INS_BREAK = 25 +HPPA_INS_BV = 26 +HPPA_INS_BVB = 27 +HPPA_INS_BVE = 28 +HPPA_INS_CALL = 29 +HPPA_INS_CLDD = 30 +HPPA_INS_CLDDS = 31 +HPPA_INS_CLDDX = 32 +HPPA_INS_CLDW = 33 +HPPA_INS_CLDWS = 34 +HPPA_INS_CLDWX = 35 +HPPA_INS_CLRBTS = 36 +HPPA_INS_CMPB = 37 +HPPA_INS_CMPCLR = 38 +HPPA_INS_CMPIB = 39 +HPPA_INS_CMPICLR = 40 +HPPA_INS_COMB = 41 +HPPA_INS_COMBT = 42 +HPPA_INS_COMBF = 43 +HPPA_INS_COMCLR = 44 +HPPA_INS_COMIB = 45 +HPPA_INS_COMIBT = 46 +HPPA_INS_COMIBF = 47 +HPPA_INS_COMICLR = 48 +HPPA_INS_COPR = 49 +HPPA_INS_COPY = 50 +HPPA_INS_CSTD = 51 +HPPA_INS_CSTDS = 52 +HPPA_INS_CSTDX = 53 +HPPA_INS_CSTW = 54 +HPPA_INS_CSTWS = 55 +HPPA_INS_CSTWX = 56 +HPPA_INS_DCOR = 57 +HPPA_INS_DEP = 58 +HPPA_INS_DEPI = 59 +HPPA_INS_DEPD = 60 +HPPA_INS_DEPDI = 61 +HPPA_INS_DEPW = 62 +HPPA_INS_DEPWI = 63 +HPPA_INS_DIAG = 64 +HPPA_INS_DS = 65 +HPPA_INS_EXTRD = 66 +HPPA_INS_EXTRS = 67 +HPPA_INS_EXTRU = 68 +HPPA_INS_EXTRW = 69 +HPPA_INS_FABS = 70 +HPPA_INS_FADD = 71 +HPPA_INS_FCMP = 72 +HPPA_INS_FCNV = 73 +HPPA_INS_FCNVFF = 74 +HPPA_INS_FCNVFX = 75 +HPPA_INS_FCNVFXT = 76 +HPPA_INS_FCNVXF = 77 +HPPA_INS_FCPY = 78 +HPPA_INS_FDC = 79 +HPPA_INS_FDCE = 80 +HPPA_INS_FDIV = 81 +HPPA_INS_FIC = 82 +HPPA_INS_FICE = 83 +HPPA_INS_FID = 84 +HPPA_INS_FLDD = 85 +HPPA_INS_FLDDS = 86 +HPPA_INS_FLDDX = 87 +HPPA_INS_FLDW = 88 +HPPA_INS_FLDWS = 89 +HPPA_INS_FLDWX = 90 +HPPA_INS_FMPY = 91 +HPPA_INS_FMPYADD = 92 +HPPA_INS_FMPYFADD = 93 +HPPA_INS_FMPYNFADD = 94 +HPPA_INS_FMPYSUB = 95 +HPPA_INS_FNEG = 96 +HPPA_INS_FNEGABS = 97 +HPPA_INS_FREM = 98 +HPPA_INS_FRND = 99 +HPPA_INS_FSQRT = 100 +HPPA_INS_FSTD = 101 +HPPA_INS_FSTDS = 102 +HPPA_INS_FSTDX = 103 +HPPA_INS_FSTW = 104 +HPPA_INS_FSTWS = 105 +HPPA_INS_FSTWX = 106 +HPPA_INS_FSTQS = 107 +HPPA_INS_FSTQX = 108 +HPPA_INS_FSUB = 109 +HPPA_INS_FTEST = 110 +HPPA_INS_GATE = 111 +HPPA_INS_GFR = 112 +HPPA_INS_GFW = 113 +HPPA_INS_GRSHDW = 114 +HPPA_INS_HADD = 115 +HPPA_INS_HAVG = 116 +HPPA_INS_HSHL = 117 +HPPA_INS_HSHLADD = 118 +HPPA_INS_HSHR = 119 +HPPA_INS_HSHRADD = 120 +HPPA_INS_HSUB = 121 +HPPA_INS_IDTLBA = 122 +HPPA_INS_IDTLBP = 123 +HPPA_INS_IDTLBT = 124 +HPPA_INS_IDCOR = 125 +HPPA_INS_IITLBA = 126 +HPPA_INS_IITLBP = 127 +HPPA_INS_IITLBT = 128 +HPPA_INS_LCI = 129 +HPPA_INS_LDB = 130 +HPPA_INS_LDBS = 131 +HPPA_INS_LDBX = 132 +HPPA_INS_LDCD = 133 +HPPA_INS_LDCW = 134 +HPPA_INS_LDCWS = 135 +HPPA_INS_LDCWX = 136 +HPPA_INS_LDD = 137 +HPPA_INS_LDDA = 138 +HPPA_INS_LDH = 139 +HPPA_INS_LDHS = 140 +HPPA_INS_LDHX = 141 +HPPA_INS_LDI = 142 +HPPA_INS_LDIL = 143 +HPPA_INS_LDO = 144 +HPPA_INS_LDSID = 145 +HPPA_INS_LDW = 146 +HPPA_INS_LDWA = 147 +HPPA_INS_LDWAS = 148 +HPPA_INS_LDWAX = 149 +HPPA_INS_LDWM = 150 +HPPA_INS_LDWS = 151 +HPPA_INS_LDWX = 152 +HPPA_INS_LPA = 153 +HPPA_INS_MFCPU = 154 +HPPA_INS_MFCTL = 155 +HPPA_INS_MFIA = 156 +HPPA_INS_MFSP = 157 +HPPA_INS_MIXH = 158 +HPPA_INS_MIXW = 159 +HPPA_INS_MOVB = 160 +HPPA_INS_MOVIB = 161 +HPPA_INS_MTCPU = 162 +HPPA_INS_MTCTL = 163 +HPPA_INS_MTSAR = 164 +HPPA_INS_MTSARCM = 165 +HPPA_INS_MTSM = 166 +HPPA_INS_MTSP = 167 +HPPA_INS_NOP = 168 +HPPA_INS_OR = 169 +HPPA_INS_PDC = 170 +HPPA_INS_PDTLB = 171 +HPPA_INS_PDTLBE = 172 +HPPA_INS_PERMH = 173 +HPPA_INS_PITLB = 174 +HPPA_INS_PITLBE = 175 +HPPA_INS_PMDIS = 176 +HPPA_INS_PMENB = 177 +HPPA_INS_POPBTS = 178 +HPPA_INS_PROBE = 179 +HPPA_INS_PROBEI = 180 +HPPA_INS_PROBER = 181 +HPPA_INS_PROBERI = 182 +HPPA_INS_PROBEW = 183 +HPPA_INS_PROBEWI = 184 +HPPA_INS_PUSHBTS = 185 +HPPA_INS_PUSHNOM = 186 +HPPA_INS_RET = 187 +HPPA_INS_RFI = 188 +HPPA_INS_RFIR = 189 +HPPA_INS_RSM = 190 +HPPA_INS_SHDWGR = 191 +HPPA_INS_SHLADD = 192 +HPPA_INS_SH1ADD = 193 +HPPA_INS_SH1ADDL = 194 +HPPA_INS_SH1ADDO = 195 +HPPA_INS_SH2ADD = 196 +HPPA_INS_SH2ADDL = 197 +HPPA_INS_SH2ADDO = 198 +HPPA_INS_SH3ADD = 199 +HPPA_INS_SH3ADDL = 200 +HPPA_INS_SH3ADDO = 201 +HPPA_INS_SHD = 202 +HPPA_INS_SHRPD = 203 +HPPA_INS_SHRPW = 204 +HPPA_INS_SPOP0 = 205 +HPPA_INS_SPOP1 = 206 +HPPA_INS_SPOP2 = 207 +HPPA_INS_SPOP3 = 208 +HPPA_INS_SSM = 209 +HPPA_INS_STB = 210 +HPPA_INS_STBS = 211 +HPPA_INS_STBY = 212 +HPPA_INS_STBYS = 213 +HPPA_INS_STD = 214 +HPPA_INS_STDA = 215 +HPPA_INS_STDBY = 216 +HPPA_INS_STH = 217 +HPPA_INS_STHS = 218 +HPPA_INS_STW = 219 +HPPA_INS_STWA = 220 +HPPA_INS_STWAS = 221 +HPPA_INS_STWS = 222 +HPPA_INS_STWM = 223 +HPPA_INS_SUB = 224 +HPPA_INS_SUBB = 225 +HPPA_INS_SUBBO = 226 +HPPA_INS_SUBI = 227 +HPPA_INS_SUBIO = 228 +HPPA_INS_SUBO = 229 +HPPA_INS_SUBT = 230 +HPPA_INS_SUBTO = 231 +HPPA_INS_SYNC = 232 +HPPA_INS_SYNCDMA = 233 +HPPA_INS_TOCDIS = 234 +HPPA_INS_TOCEN = 235 +HPPA_INS_UADDCM = 236 +HPPA_INS_UADDCMT = 237 +HPPA_INS_UXOR = 238 +HPPA_INS_VDEP = 239 +HPPA_INS_VDEPI = 240 +HPPA_INS_VEXTRS = 241 +HPPA_INS_VEXTRU = 242 +HPPA_INS_VSHD = 243 +HPPA_INS_XMPYU = 244 +HPPA_INS_XOR = 245 +HPPA_INS_ZDEP = 246 +HPPA_INS_ZDEPI = 247 +HPPA_INS_ZVDEP = 248 +HPPA_INS_ZVDEPI = 249 +HPPA_INS_ENDING = 250 + +HPPA_MOD_STR = 0 +HPPA_MOD_INT = 1 + +HPPA_GRP_INVALID = 0 +HPPA_GRP_COMPUTATION = 128 +HPPA_GRP_MULTIMEDIA = 129 +HPPA_GRP_MEM_REF = 130 +HPPA_GRP_LONG_IMM = 131 +HPPA_GRP_BRANCH = 132 +HPPA_GRP_SYSCTRL = 133 +HPPA_GRP_ASSIST = 134 +HPPA_GRP_FLOAT = 135 +HPPA_GRP_PERFMON = 136 +HPPA_GRP_ENDING = 137 diff --git a/bindings/python/setup_cython.py b/bindings/python/setup_cython.py index 9d4de46ca..18323b563 100644 --- a/bindings/python/setup_cython.py +++ b/bindings/python/setup_cython.py @@ -69,7 +69,7 @@ else: compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR] link_args = ['-L' + LIBS_DIR] -ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const', 'alpha', 'alpha_const' ] +ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const', 'alpha', 'alpha_const', 'hppa', 'hppa_const' ] ext_modules = [Extension("capstone.ccapstone", ["pyx/ccapstone.pyx"], diff --git a/bindings/python/test_all.py b/bindings/python/test_all.py index 2e70de6fd..95b4c7732 100755 --- a/bindings/python/test_all.py +++ b/bindings/python/test_all.py @@ -2,7 +2,7 @@ import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \ test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \ - test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha + test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha, test_hppa test_basic.test_class() test_arm.test_class() @@ -23,3 +23,4 @@ test_customized_mnem.test() test_xcore.test_class() test_riscv.test_class() test_alpha.test_class() +test_hppa.test_class() diff --git a/bindings/python/test_basic.py b/bindings/python/test_basic.py index fce582ad1..025715abb 100755 --- a/bindings/python/test_basic.py +++ b/bindings/python/test_basic.py @@ -42,6 +42,10 @@ RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xf RISCV_CODE64 = b"\x13\x04\xa8\x7a" ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' all_tests = ( @@ -79,6 +83,10 @@ all_tests = ( (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "RISCV64", None), (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), ) # ## Test cs_disasm_quick() diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py index fc8cbeae8..56555871c 100755 --- a/bindings/python/test_detail.py +++ b/bindings/python/test_detail.py @@ -32,6 +32,10 @@ MOS65XX_CODE = b"\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80" EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' all_tests = ( (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), @@ -61,6 +65,10 @@ all_tests = ( (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None), (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), ) diff --git a/bindings/python/test_hppa.py b/bindings/python/test_hppa.py new file mode 100755 index 000000000..75fcd0c29 --- /dev/null +++ b/bindings/python/test_hppa.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python3 + +# Capstone Python bindings, by Dmitry Sibirtsev + +from __future__ import print_function +from capstone import * +from capstone.hppa import * +from xprint import to_x, to_hex + +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' + +all_tests = ( + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)"), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)"), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)"), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == HPPA_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == HPPA_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == HPPA_OP_IDX_REG: + print("\t\toperands[%u].type: IDX_REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == HPPA_OP_DISP: + print("\t\toperands[%u].type: DISP = 0x%s" % (c, to_x(i.imm))) + if i.type == HPPA_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.space != HPPA_OP_INVALID: + print("\t\t\toperands[%u].mem.space: REG = %s" % (c, insn.reg_name(i.mem.space))) + print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base))) + if i.type == HPPA_OP_TARGET: + if i.imm >= 0x8000000000000000: + print("TARGET = -0x%lx" % i.imm) + else: + print("TARGET = 0x%lx" % i.imm) + c += 1 + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print() + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/bindings/python/test_iter.py b/bindings/python/test_iter.py index d966367cc..abdac0678 100755 --- a/bindings/python/test_iter.py +++ b/bindings/python/test_iter.py @@ -30,7 +30,10 @@ M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' - +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' all_tests = ( (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), @@ -60,6 +63,10 @@ all_tests = ( (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), ) # ## Test class Cs diff --git a/cmake.sh b/cmake.sh index da942fd8e..9e19c12d0 100755 --- a/cmake.sh +++ b/cmake.sh @@ -60,6 +60,9 @@ case $1 in RISCV) ARCH=RISCV ;; + HPPA) + ARCH=HPPA + ;; *) ;; esac diff --git a/config.mk b/config.mk index 65ba9a0fc..5b7a3d14e 100644 --- a/config.mk +++ b/config.mk @@ -4,7 +4,7 @@ ################################################################################ # Specify which archs you want to compile in. By default, we build all archs. -CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha +CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa ################################################################################ diff --git a/cs.c b/cs.c index 2e456830c..25476df9f 100644 --- a/cs.c +++ b/cs.c @@ -71,6 +71,7 @@ #include "arch/SH/SHModule.h" #include "arch/TriCore/TriCoreModule.h" #include "arch/Alpha/AlphaModule.h" +#include "arch/HPPA/HPPAModule.h" typedef struct cs_arch_config { // constructor initialization @@ -309,6 +310,16 @@ static const cs_arch_config arch_configs[MAX_ARCH] = { #else { NULL, NULL, 0 }, #endif +#ifdef CAPSTONE_HAS_HPPA + { + HPPA_global_init, + HPPA_option, + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11 + | CS_MODE_HPPA_20 | CS_MODE_HPPA_20W), + }, +#else + { NULL, NULL, 0 }, +#endif }; // bitmask of enabled architectures @@ -370,6 +381,9 @@ static const uint32_t all_arch = 0 #ifdef CAPSTONE_HAS_ALPHA | (1 << CS_ARCH_ALPHA) #endif +#ifdef CAPSTONE_HAS_HPPA + | (1 << CS_ARCH_HPPA) +#endif ; #endif @@ -603,7 +617,7 @@ bool CAPSTONE_API cs_support(int query) (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) | (1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) | (1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) | - (1 << CS_ARCH_ALPHA)); + (1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA)); if ((unsigned int)query < CS_ARCH_MAX) return all_arch & (1 << query); @@ -939,6 +953,9 @@ static uint8_t skipdata_size(cs_struct *handle) case CS_ARCH_ALPHA: // Alpha alignment is 4. return 4; + case CS_ARCH_HPPA: + // Hppa alignment is 4. + return 4; } } @@ -1683,6 +1700,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) if (insn->detail->alpha.operands[i].type == (alpha_op_type)op_type) count++; break; + case CS_ARCH_HPPA: + for (i = 0; i < insn->detail->hppa.op_count; i++) + if (insn->detail->hppa.operands[i].type == (hppa_op_type)op_type) + count++; + break; } return count; @@ -1874,6 +1896,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, return i; } break; + case CS_ARCH_HPPA: + for (i = 0; i < insn->detail->hppa.op_count; i++) { + if (insn->detail->hppa.operands[i].type == (hppa_op_type)op_type) + count++; + if (count == post) + return i; + } + break; } return -1; diff --git a/cstool/cstool.c b/cstool/cstool.c index 243c7b176..88bc94a17 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -116,6 +116,12 @@ static struct { { "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, { "alpha", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN }, { "alphabe", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN }, + { "hppa11", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN }, + { "hppa11be", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN }, + { "hppa20", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN }, + { "hppa20be", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN }, + { "hppa20w", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN }, + { "hppa20wbe", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN }, { NULL } }; @@ -215,6 +221,15 @@ static void usage(char *prog) printf(" alphabe alpha + big endian\n"); } + if (cs_support(CS_ARCH_HPPA)) { + printf(" hppa11 hppa V1.1 + little endian\n"); + printf(" hppa11be hppa V1.1 + big endian\n"); + printf(" hppa20 hppa V2.0 + little endian\n"); + printf(" hppa20be hppa V2.0 + big endian\n"); + printf(" hppa20w hppa V2.0 wide + little endian\n"); + printf(" hppa20wbe hppa V2.0 wide + big endian\n"); + } + if (cs_support(CS_ARCH_MIPS)) { printf(" mips mips32 + little endian\n"); printf(" mipsbe mips32 + big endian\n"); @@ -402,6 +417,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) case CS_ARCH_ALPHA: print_insn_detail_alpha(handle, ins); break; + case CS_ARCH_HPPA: + print_insn_detail_hppa(handle, ins); + break; default: break; } @@ -541,6 +559,10 @@ int main(int argc, char **argv) if (cs_support(CS_ARCH_ALPHA)) { printf("alpha=1 "); } + + if (cs_support(CS_ARCH_HPPA)) { + printf("hppa=1 "); + } printf("\n"); return 0; diff --git a/cstool/cstool.h b/cstool/cstool.h index 076c7b604..dfcf03bfa 100644 --- a/cstool/cstool.h +++ b/cstool/cstool.h @@ -20,5 +20,6 @@ void print_insn_detail_bpf(csh handle, cs_insn *ins); void print_insn_detail_sh(csh handle, cs_insn *ins); void print_insn_detail_tricore(csh handle, cs_insn *ins); void print_insn_detail_alpha(csh handle, cs_insn *ins); +void print_insn_detail_hppa(csh handle, cs_insn *ins); #endif //CAPSTONE_CSTOOL_CSTOOL_H_ diff --git a/cstool/cstool_hppa.c b/cstool/cstool_hppa.c new file mode 100644 index 000000000..f41b84318 --- /dev/null +++ b/cstool/cstool_hppa.c @@ -0,0 +1,87 @@ +#include + +#include +#include +#include "cstool.h" +#include "limits.h" + +void print_insn_detail_hppa(csh handle, cs_insn *ins) +{ + cs_hppa *hppa; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + if (ins->detail == NULL) + return; + + hppa = &ins->detail->hppa; + + printf("\top_count: %u\n", hppa->op_count); + for (unsigned i = 0; i < hppa->op_count; i++) { + cs_hppa_op *op = &(hppa->operands[i]); + uint64_t target_addr; + switch (op->type) { + case HPPA_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_IMM: + if (op->imm < 0) + printf("\t\toperands[%u].type: IMM = -0x%" PRIx64 + "\n", + i, -(op->imm)); + else + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 + "\n", + i, op->imm); + break; + case HPPA_OP_IDX_REG: + printf("\t\toperands[%u].type: IDX_REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_DISP: + if (op->imm < 0) + printf("\t\toperands[%u].type: DISP = -0x%" PRIx64 + "\n", + i, -(op->imm)); + else + printf("\t\toperands[%u].type: DISP = 0x%" PRIx64 + "\n", + i, op->imm); + break; + case HPPA_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.space != HPPA_OP_INVALID) { + printf("\t\t\toperands[%u].mem.space: REG = %s\n", + i, cs_reg_name(handle, op->mem.space)); + } + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, + cs_reg_name(handle, op->mem.base)); + break; + case HPPA_OP_TARGET: + printf("\t\toperands[%u].type: ", i); + target_addr = ins->address + op->imm; + printf("TARGET = 0x%" PRIx64 "\n", target_addr); + break; + } + } + + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for (unsigned i = 0; i < regs_read_count; i++) + printf(" %s", + cs_reg_name(handle, regs_read[i])); + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for (unsigned i = 0; i < regs_write_count; i++) + printf(" %s", + cs_reg_name(handle, regs_write[i])); + printf("\n"); + } + } +} \ No newline at end of file diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index a73137542..4fed66ef0 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -151,6 +151,7 @@ typedef enum cs_arch { CS_ARCH_SH, ///< SH architecture CS_ARCH_TRICORE, ///< TriCore architecture CS_ARCH_ALPHA, ///< Alpha architecture + CS_ARCH_HPPA, ///< HPPA architecture CS_ARCH_MAX, CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support() } cs_arch; @@ -230,6 +231,9 @@ typedef enum cs_mode { CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6 CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1 CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2 + CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1 + CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0 + CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide } cs_mode; typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); @@ -372,6 +376,7 @@ typedef struct cs_opt_skipdata { #include "sh.h" #include "tricore.h" #include "alpha.h" +#include "hppa.h" #define MAX_IMPL_W_REGS 47 #define MAX_IMPL_R_REGS 20 @@ -417,6 +422,7 @@ typedef struct cs_detail { cs_sh sh; ///< SH architecture cs_tricore tricore; ///< TriCore architecture cs_alpha alpha; ///< Alpha architecture + cs_hppa hppa; ///< HPPA architecture }; } cs_detail; diff --git a/include/capstone/hppa.h b/include/capstone/hppa.h new file mode 100644 index 000000000..1fa66be63 --- /dev/null +++ b/include/capstone/hppa.h @@ -0,0 +1,543 @@ +#ifndef CAPSTONE_HPPA_H +#define CAPSTONE_HPPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "cs_operand.h" +#include "platform.h" + +#define HPPA_MAX_OPS 5 +#define HPPA_STR_MODIFIER_LEN 8 +#define HPPA_MAX_MODIFIERS_LEN 5 + +/// Operand type for instruction's operands +typedef enum hppa_op_type { + HPPA_OP_INVALID = 0, + + HPPA_OP_REG, + HPPA_OP_IMM, + HPPA_OP_IDX_REG, + HPPA_OP_DISP, + HPPA_OP_MEM, + HPPA_OP_TARGET, + +} hppa_op_type; + +//> HPPA registers +typedef enum hppa_reg { + HPPA_REG_INVALID = 0, + + ///> General registers + HPPA_REG_GR0, + HPPA_REG_GR1, + HPPA_REG_GR2, + HPPA_REG_GR3, + HPPA_REG_GR4, + HPPA_REG_GR5, + HPPA_REG_GR6, + HPPA_REG_GR7, + HPPA_REG_GR8, + HPPA_REG_GR9, + HPPA_REG_GR10, + HPPA_REG_GR11, + HPPA_REG_GR12, + HPPA_REG_GR13, + HPPA_REG_GR14, + HPPA_REG_GR15, + HPPA_REG_GR16, + HPPA_REG_GR17, + HPPA_REG_GR18, + HPPA_REG_GR19, + HPPA_REG_GR20, + HPPA_REG_GR21, + HPPA_REG_GR22, + HPPA_REG_GR23, + HPPA_REG_GR24, + HPPA_REG_GR25, + HPPA_REG_GR26, + HPPA_REG_GR27, + HPPA_REG_GR28, + HPPA_REG_GR29, + HPPA_REG_GR30, + HPPA_REG_GR31, + + ///> Floating-point registers + HPPA_REG_FPR0, + HPPA_REG_FPR1, + HPPA_REG_FPR2, + HPPA_REG_FPR3, + HPPA_REG_FPR4, + HPPA_REG_FPR5, + HPPA_REG_FPR6, + HPPA_REG_FPR7, + HPPA_REG_FPR8, + HPPA_REG_FPR9, + HPPA_REG_FPR10, + HPPA_REG_FPR11, + HPPA_REG_FPR12, + HPPA_REG_FPR13, + HPPA_REG_FPR14, + HPPA_REG_FPR15, + HPPA_REG_FPR16, + HPPA_REG_FPR17, + HPPA_REG_FPR18, + HPPA_REG_FPR19, + HPPA_REG_FPR20, + HPPA_REG_FPR21, + HPPA_REG_FPR22, + HPPA_REG_FPR23, + HPPA_REG_FPR24, + HPPA_REG_FPR25, + HPPA_REG_FPR26, + HPPA_REG_FPR27, + HPPA_REG_FPR28, + HPPA_REG_FPR29, + HPPA_REG_FPR30, + HPPA_REG_FPR31, + + ///> Space registers + HPPA_REG_SR0, + HPPA_REG_SR1, + HPPA_REG_SR2, + HPPA_REG_SR3, + HPPA_REG_SR4, + HPPA_REG_SR5, + HPPA_REG_SR6, + HPPA_REG_SR7, + + ///> Control registers + HPPA_REG_CR0, + HPPA_REG_CR1, + HPPA_REG_CR2, + HPPA_REG_CR3, + HPPA_REG_CR4, + HPPA_REG_CR5, + HPPA_REG_CR6, + HPPA_REG_CR7, + HPPA_REG_CR8, + HPPA_REG_CR9, + HPPA_REG_CR10, + HPPA_REG_CR11, + HPPA_REG_CR12, + HPPA_REG_CR13, + HPPA_REG_CR14, + HPPA_REG_CR15, + HPPA_REG_CR16, + HPPA_REG_CR17, + HPPA_REG_CR18, + HPPA_REG_CR19, + HPPA_REG_CR20, + HPPA_REG_CR21, + HPPA_REG_CR22, + HPPA_REG_CR23, + HPPA_REG_CR24, + HPPA_REG_CR25, + HPPA_REG_CR26, + HPPA_REG_CR27, + HPPA_REG_CR28, + HPPA_REG_CR29, + HPPA_REG_CR30, + HPPA_REG_CR31, + + ///> Special floating point exception registers + HPPA_REG_FPE0, + HPPA_REG_FPE1, + HPPA_REG_FPE2, + HPPA_REG_FPE3, + HPPA_REG_FPE4, + HPPA_REG_FPE5, + HPPA_REG_FPE6, + HPPA_REG_FPE7, + HPPA_REG_FPE8, + HPPA_REG_FPE9, + HPPA_REG_FPE10, + HPPA_REG_FPE11, + HPPA_REG_FPE12, + HPPA_REG_FPE13, + HPPA_REG_FPE14, + HPPA_REG_FPE15, + HPPA_REG_FPE16, + HPPA_REG_FPE17, + HPPA_REG_FPE18, + HPPA_REG_FPE19, + HPPA_REG_FPE20, + HPPA_REG_FPE21, + HPPA_REG_FPE22, + HPPA_REG_FPE23, + HPPA_REG_FPE24, + HPPA_REG_FPE25, + HPPA_REG_FPE26, + HPPA_REG_FPE27, + HPPA_REG_FPE28, + HPPA_REG_FPE29, + HPPA_REG_FPE30, + HPPA_REG_FPE31, + + ///> Single-precision floating point registers + HPPA_REG_SP_FPR0, + HPPA_REG_SP_FPR1, + HPPA_REG_SP_FPR2, + HPPA_REG_SP_FPR3, + HPPA_REG_SP_FPR4, + HPPA_REG_SP_FPR5, + HPPA_REG_SP_FPR6, + HPPA_REG_SP_FPR7, + HPPA_REG_SP_FPR8, + HPPA_REG_SP_FPR9, + HPPA_REG_SP_FPR10, + HPPA_REG_SP_FPR11, + HPPA_REG_SP_FPR12, + HPPA_REG_SP_FPR13, + HPPA_REG_SP_FPR14, + HPPA_REG_SP_FPR15, + HPPA_REG_SP_FPR16, + HPPA_REG_SP_FPR17, + HPPA_REG_SP_FPR18, + HPPA_REG_SP_FPR19, + HPPA_REG_SP_FPR20, + HPPA_REG_SP_FPR21, + HPPA_REG_SP_FPR22, + HPPA_REG_SP_FPR23, + HPPA_REG_SP_FPR24, + HPPA_REG_SP_FPR25, + HPPA_REG_SP_FPR26, + HPPA_REG_SP_FPR27, + HPPA_REG_SP_FPR28, + HPPA_REG_SP_FPR29, + HPPA_REG_SP_FPR30, + HPPA_REG_SP_FPR31, + + HPPA_REG_ENDING, +} hppa_reg; + +/// HPPA instruction +typedef enum hppa_insn { + HPPA_INS_INVALID = 0, + + HPPA_INS_ADD, + HPPA_INS_ADDI, + HPPA_INS_ADDIO, + HPPA_INS_ADDIT, + HPPA_INS_ADDITO, + HPPA_INS_ADDB, + HPPA_INS_ADDBT, + HPPA_INS_ADDBF, + HPPA_INS_ADDIB, + HPPA_INS_ADDIBT, + HPPA_INS_ADDIBF, + HPPA_INS_ADDIL, + HPPA_INS_ADDC, + HPPA_INS_ADDCO, + HPPA_INS_ADDL, + HPPA_INS_ADDO, + HPPA_INS_AND, + HPPA_INS_ANDCM, + HPPA_INS_B, + HPPA_INS_BB, + HPPA_INS_BE, + HPPA_INS_BL, + HPPA_INS_BLE, + HPPA_INS_BLR, + HPPA_INS_BREAK, + HPPA_INS_BV, + HPPA_INS_BVB, + HPPA_INS_BVE, + HPPA_INS_CALL, + HPPA_INS_CLDD, + HPPA_INS_CLDDS, + HPPA_INS_CLDDX, + HPPA_INS_CLDW, + HPPA_INS_CLDWS, + HPPA_INS_CLDWX, + HPPA_INS_CLRBTS, + HPPA_INS_CMPB, + HPPA_INS_CMPCLR, + HPPA_INS_CMPIB, + HPPA_INS_CMPICLR, + HPPA_INS_COMB, + HPPA_INS_COMBT, + HPPA_INS_COMBF, + HPPA_INS_COMCLR, + HPPA_INS_COMIB, + HPPA_INS_COMIBT, + HPPA_INS_COMIBF, + HPPA_INS_COMICLR, + HPPA_INS_COPR, + HPPA_INS_COPY, + HPPA_INS_CSTD, + HPPA_INS_CSTDS, + HPPA_INS_CSTDX, + HPPA_INS_CSTW, + HPPA_INS_CSTWS, + HPPA_INS_CSTWX, + HPPA_INS_DCOR, + HPPA_INS_DEP, + HPPA_INS_DEPI, + HPPA_INS_DEPD, + HPPA_INS_DEPDI, + HPPA_INS_DEPW, + HPPA_INS_DEPWI, + HPPA_INS_DIAG, + HPPA_INS_DS, + HPPA_INS_EXTRD, + HPPA_INS_EXTRS, + HPPA_INS_EXTRU, + HPPA_INS_EXTRW, + HPPA_INS_FABS, + HPPA_INS_FADD, + HPPA_INS_FCMP, + HPPA_INS_FCNV, + HPPA_INS_FCNVFF, + HPPA_INS_FCNVFX, + HPPA_INS_FCNVFXT, + HPPA_INS_FCNVXF, + HPPA_INS_FCPY, + HPPA_INS_FDC, + HPPA_INS_FDCE, + HPPA_INS_FDIV, + HPPA_INS_FIC, + HPPA_INS_FICE, + HPPA_INS_FID, + HPPA_INS_FLDD, + HPPA_INS_FLDDS, + HPPA_INS_FLDDX, + HPPA_INS_FLDW, + HPPA_INS_FLDWS, + HPPA_INS_FLDWX, + HPPA_INS_FMPY, + HPPA_INS_FMPYADD, + HPPA_INS_FMPYFADD, + HPPA_INS_FMPYNFADD, + HPPA_INS_FMPYSUB, + HPPA_INS_FNEG, + HPPA_INS_FNEGABS, + HPPA_INS_FREM, + HPPA_INS_FRND, + HPPA_INS_FSQRT, + HPPA_INS_FSTD, + HPPA_INS_FSTDS, + HPPA_INS_FSTDX, + HPPA_INS_FSTW, + HPPA_INS_FSTWS, + HPPA_INS_FSTWX, + HPPA_INS_FSTQS, + HPPA_INS_FSTQX, + HPPA_INS_FSUB, + HPPA_INS_FTEST, + HPPA_INS_GATE, + HPPA_INS_GFR, + HPPA_INS_GFW, + HPPA_INS_GRSHDW, + HPPA_INS_HADD, + HPPA_INS_HAVG, + HPPA_INS_HSHL, + HPPA_INS_HSHLADD, + HPPA_INS_HSHR, + HPPA_INS_HSHRADD, + HPPA_INS_HSUB, + HPPA_INS_IDTLBA, + HPPA_INS_IDTLBP, + HPPA_INS_IDTLBT, + HPPA_INS_IDCOR, + HPPA_INS_IITLBA, + HPPA_INS_IITLBP, + HPPA_INS_IITLBT, + HPPA_INS_LCI, + HPPA_INS_LDB, + HPPA_INS_LDBS, + HPPA_INS_LDBX, + HPPA_INS_LDCD, + HPPA_INS_LDCW, + HPPA_INS_LDCWS, + HPPA_INS_LDCWX, + HPPA_INS_LDD, + HPPA_INS_LDDA, + HPPA_INS_LDH, + HPPA_INS_LDHS, + HPPA_INS_LDHX, + HPPA_INS_LDI, + HPPA_INS_LDIL, + HPPA_INS_LDO, + HPPA_INS_LDSID, + HPPA_INS_LDW, + HPPA_INS_LDWA, + HPPA_INS_LDWAS, + HPPA_INS_LDWAX, + HPPA_INS_LDWM, + HPPA_INS_LDWS, + HPPA_INS_LDWX, + HPPA_INS_LPA, + HPPA_INS_MFCPU, + HPPA_INS_MFCTL, + HPPA_INS_MFIA, + HPPA_INS_MFSP, + HPPA_INS_MIXH, + HPPA_INS_MIXW, + HPPA_INS_MOVB, + HPPA_INS_MOVIB, + HPPA_INS_MTCPU, + HPPA_INS_MTCTL, + HPPA_INS_MTSAR, + HPPA_INS_MTSARCM, + HPPA_INS_MTSM, + HPPA_INS_MTSP, + HPPA_INS_NOP, + HPPA_INS_OR, + HPPA_INS_PDC, + HPPA_INS_PDTLB, + HPPA_INS_PDTLBE, + HPPA_INS_PERMH, + HPPA_INS_PITLB, + HPPA_INS_PITLBE, + HPPA_INS_PMDIS, + HPPA_INS_PMENB, + HPPA_INS_POPBTS, + HPPA_INS_PROBE, + HPPA_INS_PROBEI, + HPPA_INS_PROBER, + HPPA_INS_PROBERI, + HPPA_INS_PROBEW, + HPPA_INS_PROBEWI, + HPPA_INS_PUSHBTS, + HPPA_INS_PUSHNOM, + HPPA_INS_RET, + HPPA_INS_RFI, + HPPA_INS_RFIR, + HPPA_INS_RSM, + HPPA_INS_SHDWGR, + HPPA_INS_SHLADD, + HPPA_INS_SH1ADD, + HPPA_INS_SH1ADDL, + HPPA_INS_SH1ADDO, + HPPA_INS_SH2ADD, + HPPA_INS_SH2ADDL, + HPPA_INS_SH2ADDO, + HPPA_INS_SH3ADD, + HPPA_INS_SH3ADDL, + HPPA_INS_SH3ADDO, + HPPA_INS_SHD, + HPPA_INS_SHRPD, + HPPA_INS_SHRPW, + HPPA_INS_SPOP0, + HPPA_INS_SPOP1, + HPPA_INS_SPOP2, + HPPA_INS_SPOP3, + HPPA_INS_SSM, + HPPA_INS_STB, + HPPA_INS_STBS, + HPPA_INS_STBY, + HPPA_INS_STBYS, + HPPA_INS_STD, + HPPA_INS_STDA, + HPPA_INS_STDBY, + HPPA_INS_STH, + HPPA_INS_STHS, + HPPA_INS_STW, + HPPA_INS_STWA, + HPPA_INS_STWAS, + HPPA_INS_STWS, + HPPA_INS_STWM, + HPPA_INS_SUB, + HPPA_INS_SUBB, + HPPA_INS_SUBBO, + HPPA_INS_SUBI, + HPPA_INS_SUBIO, + HPPA_INS_SUBO, + HPPA_INS_SUBT, + HPPA_INS_SUBTO, + HPPA_INS_SYNC, + HPPA_INS_SYNCDMA, + HPPA_INS_TOCDIS, + HPPA_INS_TOCEN, + HPPA_INS_UADDCM, + HPPA_INS_UADDCMT, + HPPA_INS_UXOR, + HPPA_INS_VDEP, + HPPA_INS_VDEPI, + HPPA_INS_VEXTRS, + HPPA_INS_VEXTRU, + HPPA_INS_VSHD, + HPPA_INS_XMPYU, + HPPA_INS_XOR, + HPPA_INS_ZDEP, + HPPA_INS_ZDEPI, + HPPA_INS_ZVDEP, + HPPA_INS_ZVDEPI, + + HPPA_INS_ENDING +} hppa_insn; + +/// HPPA space select operand +typedef struct hppa_mem { + hppa_reg base; + hppa_reg space; + cs_ac_type base_access; +} hppa_mem; + +// Instruction operand +typedef struct cs_hppa_op { + hppa_op_type type; ///< operand type + union { + hppa_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + hppa_mem mem; + }; + cs_ac_type access; +} cs_hppa_op; + +// Instruction structure +typedef struct cs_hppa { + // Number of operands of this instruction, + // or 0 when instruction has no operand. + uint8_t op_count; + cs_hppa_op operands[HPPA_MAX_OPS]; ///< operands for hppa instruction. +} cs_hppa; + +/// HPPA modifiers type. Can be string (most of them) or int (uid, sop) +typedef enum hppa_modifier_type { + HPPA_MOD_STR = 0, + HPPA_MOD_INT = 1 +} hppa_modifier_type; + +/// hppa string/integer modifier +typedef struct hppa_modifier { + hppa_modifier_type type; + union { + char str_mod[HPPA_STR_MODIFIER_LEN]; + uint32_t int_mod; + }; + +} hppa_modifier; + +// Additional instruction info +typedef struct hppa_ext { + hppa_modifier modifiers[HPPA_MAX_MODIFIERS_LEN]; ///< instruction modifiers array + uint8_t mod_num; ///< number of modifiers of current instruction + bool b_writeble; ///< true if some load/store modifier has modify base register bit + bool is_alternative; ///< true if some modifier affects instruction format +} hppa_ext; + +// Group of HPPA instructions +typedef enum hppa_insn_group { + HPPA_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + HPPA_GRP_COMPUTATION = 128, + HPPA_GRP_MULTIMEDIA, + HPPA_GRP_MEM_REF, + HPPA_GRP_LONG_IMM, + HPPA_GRP_BRANCH, + HPPA_GRP_SYSCTRL, + HPPA_GRP_ASSIST, + HPPA_GRP_FLOAT, + HPPA_GRP_PERFMON, + + HPPA_GRP_ENDING, +} hppa_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/nmake.bat b/nmake.bat index 0f03bce88..42d64158d 100644 --- a/nmake.bat +++ b/nmake.bat @@ -23,6 +23,7 @@ if "%1"=="WASM" set %arch%=WASM if "%1"=="BPF" set %arch%=BPF if "%1"=="RISCV" set %arch%=RISCV if "%1"=="ALPHA" set %arch%=ALPHA +if "%1"=="HPPA" set %arch%=HPPA if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON" diff --git a/suite/MC/HPPA/alu11.s.cs b/suite/MC/HPPA/alu11.s.cs new file mode 100644 index 000000000..2eee717ec --- /dev/null +++ b/suite/MC/HPPA/alu11.s.cs @@ -0,0 +1,433 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x08,0x41,0x06,0x03 = add r1,rp,r3 +0x08,0x41,0x26,0x03 = add,= r1,rp,r3 +0x08,0x41,0x46,0x03 = add,< r1,rp,r3 +0x08,0x41,0x66,0x03 = add,<= r1,rp,r3 +0x08,0x41,0x86,0x03 = add,nuv r1,rp,r3 +0x08,0x41,0xa6,0x03 = add,znv r1,rp,r3 +0x08,0x41,0xc6,0x03 = add,sv r1,rp,r3 +0x08,0x41,0xe6,0x03 = add,od r1,rp,r3 +0x08,0x41,0x16,0x03 = add,tr r1,rp,r3 +0x08,0x41,0x36,0x03 = add,<> r1,rp,r3 +0x08,0x41,0x56,0x03 = add,>= r1,rp,r3 +0x08,0x41,0x76,0x03 = add,> r1,rp,r3 +0x08,0x41,0x96,0x03 = add,uv r1,rp,r3 +0x08,0x41,0xb6,0x03 = add,vnz r1,rp,r3 +0x08,0x41,0xd6,0x03 = add,nsv r1,rp,r3 +0x08,0x41,0xf6,0x03 = add,ev r1,rp,r3 +0x08,0x41,0x0e,0x03 = addo r1,rp,r3 +0x08,0x41,0x2e,0x03 = addo,= r1,rp,r3 +0x08,0x41,0x4e,0x03 = addo,< r1,rp,r3 +0x08,0x41,0x6e,0x03 = addo,<= r1,rp,r3 +0x08,0x41,0x8e,0x03 = addo,nuv r1,rp,r3 +0x08,0x41,0xae,0x03 = addo,znv r1,rp,r3 +0x08,0x41,0xce,0x03 = addo,sv r1,rp,r3 +0x08,0x41,0xee,0x03 = addo,od r1,rp,r3 +0x08,0x41,0x1e,0x03 = addo,tr r1,rp,r3 +0x08,0x41,0x3e,0x03 = addo,<> r1,rp,r3 +0x08,0x41,0x5e,0x03 = addo,>= r1,rp,r3 +0x08,0x41,0x7e,0x03 = addo,> r1,rp,r3 +0x08,0x41,0x9e,0x03 = addo,uv r1,rp,r3 +0x08,0x41,0xbe,0x03 = addo,vnz r1,rp,r3 +0x08,0x41,0xde,0x03 = addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0x03 = addo,ev r1,rp,r3 +0x08,0x41,0x07,0x03 = addc r1,rp,r3 +0x08,0x41,0x27,0x03 = addc,= r1,rp,r3 +0x08,0x41,0x47,0x03 = addc,< r1,rp,r3 +0x08,0x41,0x67,0x03 = addc,<= r1,rp,r3 +0x08,0x41,0x87,0x03 = addc,nuv r1,rp,r3 +0x08,0x41,0xa7,0x03 = addc,znv r1,rp,r3 +0x08,0x41,0xc7,0x03 = addc,sv r1,rp,r3 +0x08,0x41,0xe7,0x03 = addc,od r1,rp,r3 +0x08,0x41,0x17,0x03 = addc,tr r1,rp,r3 +0x08,0x41,0x37,0x03 = addc,<> r1,rp,r3 +0x08,0x41,0x57,0x03 = addc,>= r1,rp,r3 +0x08,0x41,0x77,0x03 = addc,> r1,rp,r3 +0x08,0x41,0x97,0x03 = addc,uv r1,rp,r3 +0x08,0x41,0xb7,0x03 = addc,vnz r1,rp,r3 +0x08,0x41,0xd7,0x03 = addc,nsv r1,rp,r3 +0x08,0x41,0xf7,0x03 = addc,ev r1,rp,r3 +0x08,0x41,0x0f,0x03 = addco r1,rp,r3 +0x08,0x41,0x2f,0x03 = addco,= r1,rp,r3 +0x08,0x41,0x4f,0x03 = addco,< r1,rp,r3 +0x08,0x41,0x6f,0x03 = addco,<= r1,rp,r3 +0x08,0x41,0x8f,0x03 = addco,nuv r1,rp,r3 +0x08,0x41,0xaf,0x03 = addco,znv r1,rp,r3 +0x08,0x41,0xcf,0x03 = addco,sv r1,rp,r3 +0x08,0x41,0xef,0x03 = addco,od r1,rp,r3 +0x08,0x41,0x1f,0x03 = addco,tr r1,rp,r3 +0x08,0x41,0x3f,0x03 = addco,<> r1,rp,r3 +0x08,0x41,0x5f,0x03 = addco,>= r1,rp,r3 +0x08,0x41,0x7f,0x03 = addco,> r1,rp,r3 +0x08,0x41,0x9f,0x03 = addco,uv r1,rp,r3 +0x08,0x41,0xbf,0x03 = addco,vnz r1,rp,r3 +0x08,0x41,0xdf,0x03 = addco,nsv r1,rp,r3 +0x08,0x41,0xff,0x03 = addco,ev r1,rp,r3 +0x08,0x41,0x06,0x43 = sh1add r1,rp,r3 +0x08,0x41,0x26,0x43 = sh1add,= r1,rp,r3 +0x08,0x41,0x46,0x43 = sh1add,< r1,rp,r3 +0x08,0x41,0x66,0x43 = sh1add,<= r1,rp,r3 +0x08,0x41,0x86,0x43 = sh1add,nuv r1,rp,r3 +0x08,0x41,0xa6,0x43 = sh1add,znv r1,rp,r3 +0x08,0x41,0xc6,0x43 = sh1add,sv r1,rp,r3 +0x08,0x41,0xe6,0x43 = sh1add,od r1,rp,r3 +0x08,0x41,0x16,0x43 = sh1add,tr r1,rp,r3 +0x08,0x41,0x36,0x43 = sh1add,<> r1,rp,r3 +0x08,0x41,0x56,0x43 = sh1add,>= r1,rp,r3 +0x08,0x41,0x76,0x43 = sh1add,> r1,rp,r3 +0x08,0x41,0x96,0x43 = sh1add,uv r1,rp,r3 +0x08,0x41,0xb6,0x43 = sh1add,vnz r1,rp,r3 +0x08,0x41,0xd6,0x43 = sh1add,nsv r1,rp,r3 +0x08,0x41,0xf6,0x43 = sh1add,ev r1,rp,r3 +0x08,0x41,0x0e,0x43 = sh1addo r1,rp,r3 +0x08,0x41,0x2e,0x43 = sh1addo,= r1,rp,r3 +0x08,0x41,0x4e,0x43 = sh1addo,< r1,rp,r3 +0x08,0x41,0x6e,0x43 = sh1addo,<= r1,rp,r3 +0x08,0x41,0x8e,0x43 = sh1addo,nuv r1,rp,r3 +0x08,0x41,0xae,0x43 = sh1addo,znv r1,rp,r3 +0x08,0x41,0xce,0x43 = sh1addo,sv r1,rp,r3 +0x08,0x41,0xee,0x43 = sh1addo,od r1,rp,r3 +0x08,0x41,0x1e,0x43 = sh1addo,tr r1,rp,r3 +0x08,0x41,0x3e,0x43 = sh1addo,<> r1,rp,r3 +0x08,0x41,0x5e,0x43 = sh1addo,>= r1,rp,r3 +0x08,0x41,0x7e,0x43 = sh1addo,> r1,rp,r3 +0x08,0x41,0x9e,0x43 = sh1addo,uv r1,rp,r3 +0x08,0x41,0xbe,0x43 = sh1addo,vnz r1,rp,r3 +0x08,0x41,0xde,0x43 = sh1addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0x43 = sh1addo,ev r1,rp,r3 +0x08,0x41,0x06,0x83 = sh2add r1,rp,r3 +0x08,0x41,0x26,0x83 = sh2add,= r1,rp,r3 +0x08,0x41,0x46,0x83 = sh2add,< r1,rp,r3 +0x08,0x41,0x66,0x83 = sh2add,<= r1,rp,r3 +0x08,0x41,0x86,0x83 = sh2add,nuv r1,rp,r3 +0x08,0x41,0xa6,0x83 = sh2add,znv r1,rp,r3 +0x08,0x41,0xc6,0x83 = sh2add,sv r1,rp,r3 +0x08,0x41,0xe6,0x83 = sh2add,od r1,rp,r3 +0x08,0x41,0x16,0x83 = sh2add,tr r1,rp,r3 +0x08,0x41,0x36,0x83 = sh2add,<> r1,rp,r3 +0x08,0x41,0x56,0x83 = sh2add,>= r1,rp,r3 +0x08,0x41,0x76,0x83 = sh2add,> r1,rp,r3 +0x08,0x41,0x96,0x83 = sh2add,uv r1,rp,r3 +0x08,0x41,0xb6,0x83 = sh2add,vnz r1,rp,r3 +0x08,0x41,0xd6,0x83 = sh2add,nsv r1,rp,r3 +0x08,0x41,0xf6,0x83 = sh2add,ev r1,rp,r3 +0x08,0x41,0x0e,0x83 = sh2addo r1,rp,r3 +0x08,0x41,0x2e,0x83 = sh2addo,= r1,rp,r3 +0x08,0x41,0x4e,0x83 = sh2addo,< r1,rp,r3 +0x08,0x41,0x6e,0x83 = sh2addo,<= r1,rp,r3 +0x08,0x41,0x8e,0x83 = sh2addo,nuv r1,rp,r3 +0x08,0x41,0xae,0x83 = sh2addo,znv r1,rp,r3 +0x08,0x41,0xce,0x83 = sh2addo,sv r1,rp,r3 +0x08,0x41,0xee,0x83 = sh2addo,od r1,rp,r3 +0x08,0x41,0x1e,0x83 = sh2addo,tr r1,rp,r3 +0x08,0x41,0x3e,0x83 = sh2addo,<> r1,rp,r3 +0x08,0x41,0x5e,0x83 = sh2addo,>= r1,rp,r3 +0x08,0x41,0x7e,0x83 = sh2addo,> r1,rp,r3 +0x08,0x41,0x9e,0x83 = sh2addo,uv r1,rp,r3 +0x08,0x41,0xbe,0x83 = sh2addo,vnz r1,rp,r3 +0x08,0x41,0xde,0x83 = sh2addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0x83 = sh2addo,ev r1,rp,r3 +0x08,0x41,0x06,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x26,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x46,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x66,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x86,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xa6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xc6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xe6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x16,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x36,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x56,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x76,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x96,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xb6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xd6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xf6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x0e,0xc3 = sh3addo r1,rp,r3 +0x08,0x41,0x2e,0xc3 = sh3addo,= r1,rp,r3 +0x08,0x41,0x4e,0xc3 = sh3addo,< r1,rp,r3 +0x08,0x41,0x6e,0xc3 = sh3addo,<= r1,rp,r3 +0x08,0x41,0x8e,0xc3 = sh3addo,nuv r1,rp,r3 +0x08,0x41,0xae,0xc3 = sh3addo,znv r1,rp,r3 +0x08,0x41,0xce,0xc3 = sh3addo,sv r1,rp,r3 +0x08,0x41,0xee,0xc3 = sh3addo,od r1,rp,r3 +0x08,0x41,0x1e,0xc3 = sh3addo,tr r1,rp,r3 +0x08,0x41,0x3e,0xc3 = sh3addo,<> r1,rp,r3 +0x08,0x41,0x5e,0xc3 = sh3addo,>= r1,rp,r3 +0x08,0x41,0x7e,0xc3 = sh3addo,> r1,rp,r3 +0x08,0x41,0x9e,0xc3 = sh3addo,uv r1,rp,r3 +0x08,0x41,0xbe,0xc3 = sh3addo,vnz r1,rp,r3 +0x08,0x41,0xde,0xc3 = sh3addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0xc3 = sh3addo,ev r1,rp,r3 +0x08,0x41,0x04,0x03 = sub r1,rp,r3 +0x08,0x41,0x24,0x03 = sub,= r1,rp,r3 +0x08,0x41,0x44,0x03 = sub,< r1,rp,r3 +0x08,0x41,0x64,0x03 = sub,<= r1,rp,r3 +0x08,0x41,0x84,0x03 = sub,<< r1,rp,r3 +0x08,0x41,0xa4,0x03 = sub,<<= r1,rp,r3 +0x08,0x41,0xc4,0x03 = sub,sv r1,rp,r3 +0x08,0x41,0xe4,0x03 = sub,od r1,rp,r3 +0x08,0x41,0x14,0x03 = sub,tr r1,rp,r3 +0x08,0x41,0x34,0x03 = sub,<> r1,rp,r3 +0x08,0x41,0x54,0x03 = sub,>= r1,rp,r3 +0x08,0x41,0x74,0x03 = sub,> r1,rp,r3 +0x08,0x41,0x94,0x03 = sub,>>= r1,rp,r3 +0x08,0x41,0xb4,0x03 = sub,>> r1,rp,r3 +0x08,0x41,0xd4,0x03 = sub,nsv r1,rp,r3 +0x08,0x41,0xf4,0x03 = sub,ev r1,rp,r3 +0x08,0x41,0x0c,0x03 = subo r1,rp,r3 +0x08,0x41,0x2c,0x03 = subo,= r1,rp,r3 +0x08,0x41,0x4c,0x03 = subo,< r1,rp,r3 +0x08,0x41,0x6c,0x03 = subo,<= r1,rp,r3 +0x08,0x41,0x8c,0x03 = subo,<< r1,rp,r3 +0x08,0x41,0xac,0x03 = subo,<<= r1,rp,r3 +0x08,0x41,0xcc,0x03 = subo,sv r1,rp,r3 +0x08,0x41,0xec,0x03 = subo,od r1,rp,r3 +0x08,0x41,0x1c,0x03 = subo,tr r1,rp,r3 +0x08,0x41,0x3c,0x03 = subo,<> r1,rp,r3 +0x08,0x41,0x5c,0x03 = subo,>= r1,rp,r3 +0x08,0x41,0x7c,0x03 = subo,> r1,rp,r3 +0x08,0x41,0x9c,0x03 = subo,>>= r1,rp,r3 +0x08,0x41,0xbc,0x03 = subo,>> r1,rp,r3 +0x08,0x41,0xdc,0x03 = subo,nsv r1,rp,r3 +0x08,0x41,0xfc,0x03 = subo,ev r1,rp,r3 +0x08,0x41,0x04,0xc3 = subt r1,rp,r3 +0x08,0x41,0x24,0xc3 = subt,= r1,rp,r3 +0x08,0x41,0x44,0xc3 = subt,< r1,rp,r3 +0x08,0x41,0x64,0xc3 = subt,<= r1,rp,r3 +0x08,0x41,0x84,0xc3 = subt,<< r1,rp,r3 +0x08,0x41,0xa4,0xc3 = subt,<<= r1,rp,r3 +0x08,0x41,0xc4,0xc3 = subt,sv r1,rp,r3 +0x08,0x41,0xe4,0xc3 = subt,od r1,rp,r3 +0x08,0x41,0x14,0xc3 = subt,tr r1,rp,r3 +0x08,0x41,0x34,0xc3 = subt,<> r1,rp,r3 +0x08,0x41,0x54,0xc3 = subt,>= r1,rp,r3 +0x08,0x41,0x74,0xc3 = subt,> r1,rp,r3 +0x08,0x41,0x94,0xc3 = subt,>>= r1,rp,r3 +0x08,0x41,0xb4,0xc3 = subt,>> r1,rp,r3 +0x08,0x41,0xd4,0xc3 = subt,nsv r1,rp,r3 +0x08,0x41,0xf4,0xc3 = subt,ev r1,rp,r3 +0x08,0x41,0x0c,0xc3 = subto r1,rp,r3 +0x08,0x41,0x2c,0xc3 = subto,= r1,rp,r3 +0x08,0x41,0x4c,0xc3 = subto,< r1,rp,r3 +0x08,0x41,0x6c,0xc3 = subto,<= r1,rp,r3 +0x08,0x41,0x8c,0xc3 = subto,<< r1,rp,r3 +0x08,0x41,0xac,0xc3 = subto,<<= r1,rp,r3 +0x08,0x41,0xcc,0xc3 = subto,sv r1,rp,r3 +0x08,0x41,0xec,0xc3 = subto,od r1,rp,r3 +0x08,0x41,0x1c,0xc3 = subto,tr r1,rp,r3 +0x08,0x41,0x3c,0xc3 = subto,<> r1,rp,r3 +0x08,0x41,0x5c,0xc3 = subto,>= r1,rp,r3 +0x08,0x41,0x7c,0xc3 = subto,> r1,rp,r3 +0x08,0x41,0x9c,0xc3 = subto,>>= r1,rp,r3 +0x08,0x41,0xbc,0xc3 = subto,>> r1,rp,r3 +0x08,0x41,0xdc,0xc3 = subto,nsv r1,rp,r3 +0x08,0x41,0xfc,0xc3 = subto,ev r1,rp,r3 +0x08,0x41,0x05,0x03 = subb r1,rp,r3 +0x08,0x41,0x25,0x03 = subb,= r1,rp,r3 +0x08,0x41,0x45,0x03 = subb,< r1,rp,r3 +0x08,0x41,0x65,0x03 = subb,<= r1,rp,r3 +0x08,0x41,0x85,0x03 = subb,<< r1,rp,r3 +0x08,0x41,0xa5,0x03 = subb,<<= r1,rp,r3 +0x08,0x41,0xc5,0x03 = subb,sv r1,rp,r3 +0x08,0x41,0xe5,0x03 = subb,od r1,rp,r3 +0x08,0x41,0x15,0x03 = subb,tr r1,rp,r3 +0x08,0x41,0x35,0x03 = subb,<> r1,rp,r3 +0x08,0x41,0x55,0x03 = subb,>= r1,rp,r3 +0x08,0x41,0x75,0x03 = subb,> r1,rp,r3 +0x08,0x41,0x95,0x03 = subb,>>= r1,rp,r3 +0x08,0x41,0xb5,0x03 = subb,>> r1,rp,r3 +0x08,0x41,0xd5,0x03 = subb,nsv r1,rp,r3 +0x08,0x41,0xf5,0x03 = subb,ev r1,rp,r3 +0x08,0x41,0x0d,0x03 = subbo r1,rp,r3 +0x08,0x41,0x2d,0x03 = subbo,= r1,rp,r3 +0x08,0x41,0x4d,0x03 = subbo,< r1,rp,r3 +0x08,0x41,0x6d,0x03 = subbo,<= r1,rp,r3 +0x08,0x41,0x8d,0x03 = subbo,<< r1,rp,r3 +0x08,0x41,0xad,0x03 = subbo,<<= r1,rp,r3 +0x08,0x41,0xcd,0x03 = subbo,sv r1,rp,r3 +0x08,0x41,0xed,0x03 = subbo,od r1,rp,r3 +0x08,0x41,0x1d,0x03 = subbo,tr r1,rp,r3 +0x08,0x41,0x3d,0x03 = subbo,<> r1,rp,r3 +0x08,0x41,0x5d,0x03 = subbo,>= r1,rp,r3 +0x08,0x41,0x7d,0x03 = subbo,> r1,rp,r3 +0x08,0x41,0x9d,0x03 = subbo,>>= r1,rp,r3 +0x08,0x41,0xbd,0x03 = subbo,>> r1,rp,r3 +0x08,0x41,0xdd,0x03 = subbo,nsv r1,rp,r3 +0x08,0x41,0xfd,0x03 = subbo,ev r1,rp,r3 +0x08,0x41,0x04,0x43 = ds r1,rp,r3 +0x08,0x41,0x24,0x43 = ds,= r1,rp,r3 +0x08,0x41,0x44,0x43 = ds,< r1,rp,r3 +0x08,0x41,0x64,0x43 = ds,<= r1,rp,r3 +0x08,0x41,0x84,0x43 = ds,<< r1,rp,r3 +0x08,0x41,0xa4,0x43 = ds,<<= r1,rp,r3 +0x08,0x41,0xc4,0x43 = ds,sv r1,rp,r3 +0x08,0x41,0xe4,0x43 = ds,od r1,rp,r3 +0x08,0x41,0x14,0x43 = ds,tr r1,rp,r3 +0x08,0x41,0x34,0x43 = ds,<> r1,rp,r3 +0x08,0x41,0x54,0x43 = ds,>= r1,rp,r3 +0x08,0x41,0x74,0x43 = ds,> r1,rp,r3 +0x08,0x41,0x94,0x43 = ds,>>= r1,rp,r3 +0x08,0x41,0xb4,0x43 = ds,>> r1,rp,r3 +0x08,0x41,0xd4,0x43 = ds,nsv r1,rp,r3 +0x08,0x41,0xf4,0x43 = ds,ev r1,rp,r3 +0x08,0x41,0x00,0x03 = andcm r1,rp,r3 +0x08,0x41,0x20,0x03 = andcm,= r1,rp,r3 +0x08,0x41,0x40,0x03 = andcm,< r1,rp,r3 +0x08,0x41,0x60,0x03 = andcm,<= r1,rp,r3 +0x08,0x41,0xe0,0x03 = andcm,od r1,rp,r3 +0x08,0x41,0x10,0x03 = andcm,tr r1,rp,r3 +0x08,0x41,0x30,0x03 = andcm,<> r1,rp,r3 +0x08,0x41,0x50,0x03 = andcm,>= r1,rp,r3 +0x08,0x41,0x70,0x03 = andcm,> r1,rp,r3 +0x08,0x41,0xf0,0x03 = andcm,ev r1,rp,r3 +0x08,0x41,0x02,0x03 = and r1,rp,r3 +0x08,0x41,0x22,0x03 = and,= r1,rp,r3 +0x08,0x41,0x42,0x03 = and,< r1,rp,r3 +0x08,0x41,0x62,0x03 = and,<= r1,rp,r3 +0x08,0x41,0xe2,0x03 = and,od r1,rp,r3 +0x08,0x41,0x12,0x03 = and,tr r1,rp,r3 +0x08,0x41,0x32,0x03 = and,<> r1,rp,r3 +0x08,0x41,0x52,0x03 = and,>= r1,rp,r3 +0x08,0x41,0x72,0x03 = and,> r1,rp,r3 +0x08,0x41,0xf2,0x03 = and,ev r1,rp,r3 +0x08,0x41,0x02,0x43 = or r1,rp,r3 +0x08,0x41,0x22,0x43 = or,= r1,rp,r3 +0x08,0x41,0x42,0x43 = or,< r1,rp,r3 +0x08,0x41,0x62,0x43 = or,<= r1,rp,r3 +0x08,0x41,0xe2,0x43 = or,od r1,rp,r3 +0x08,0x41,0x12,0x43 = or,tr r1,rp,r3 +0x08,0x41,0x32,0x43 = or,<> r1,rp,r3 +0x08,0x41,0x52,0x43 = or,>= r1,rp,r3 +0x08,0x41,0x72,0x43 = or,> r1,rp,r3 +0x08,0x41,0xf2,0x43 = or,ev r1,rp,r3 +0x08,0x41,0x02,0x83 = xor r1,rp,r3 +0x08,0x41,0x22,0x83 = xor,= r1,rp,r3 +0x08,0x41,0x42,0x83 = xor,< r1,rp,r3 +0x08,0x41,0x62,0x83 = xor,<= r1,rp,r3 +0x08,0x41,0xe2,0x83 = xor,od r1,rp,r3 +0x08,0x41,0x12,0x83 = xor,tr r1,rp,r3 +0x08,0x41,0x32,0x83 = xor,<> r1,rp,r3 +0x08,0x41,0x52,0x83 = xor,>= r1,rp,r3 +0x08,0x41,0x72,0x83 = xor,> r1,rp,r3 +0x08,0x41,0xf2,0x83 = xor,ev r1,rp,r3 +0x08,0x41,0x03,0x83 = uxor r1,rp,r3 +0x08,0x41,0x23,0x83 = uxor,swz r1,rp,r3 +0x08,0x41,0x43,0x83 = uxor,sbz r1,rp,r3 +0x08,0x41,0x63,0x83 = uxor,shz r1,rp,r3 +0x08,0x41,0x13,0x83 = uxor,tr r1,rp,r3 +0x08,0x41,0x33,0x83 = uxor,nwz r1,rp,r3 +0x08,0x41,0x53,0x83 = uxor,nbz r1,rp,r3 +0x08,0x41,0x73,0x83 = uxor,nhz r1,rp,r3 +0x08,0x41,0x08,0x83 = comclr r1,rp,r3 +0x08,0x41,0x28,0x83 = comclr,= r1,rp,r3 +0x08,0x41,0x48,0x83 = comclr,< r1,rp,r3 +0x08,0x41,0x68,0x83 = comclr,<= r1,rp,r3 +0x08,0x41,0x88,0x83 = comclr,<< r1,rp,r3 +0x08,0x41,0xa8,0x83 = comclr,<<= r1,rp,r3 +0x08,0x41,0xc8,0x83 = comclr,sv r1,rp,r3 +0x08,0x41,0xe8,0x83 = comclr,od r1,rp,r3 +0x08,0x41,0x18,0x83 = comclr,tr r1,rp,r3 +0x08,0x41,0x38,0x83 = comclr,<> r1,rp,r3 +0x08,0x41,0x58,0x83 = comclr,>= r1,rp,r3 +0x08,0x41,0x78,0x83 = comclr,> r1,rp,r3 +0x08,0x41,0x98,0x83 = comclr,>>= r1,rp,r3 +0x08,0x41,0xb8,0x83 = comclr,>> r1,rp,r3 +0x08,0x41,0xd8,0x83 = comclr,nsv r1,rp,r3 +0x08,0x41,0xf8,0x83 = comclr,ev r1,rp,r3 +0x08,0x41,0x09,0x83 = uaddcm r1,rp,r3 +0x08,0x41,0x29,0x83 = uaddcm,swz r1,rp,r3 +0x08,0x41,0x49,0x83 = uaddcm,sbz r1,rp,r3 +0x08,0x41,0x69,0x83 = uaddcm,shz r1,rp,r3 +0x08,0x41,0x19,0x83 = uaddcm,tr r1,rp,r3 +0x08,0x41,0x39,0x83 = uaddcm,nwz r1,rp,r3 +0x08,0x41,0x59,0x83 = uaddcm,nbz r1,rp,r3 +0x08,0x41,0x79,0x83 = uaddcm,nhz r1,rp,r3 +0x08,0x41,0x09,0xc3 = uaddcmt r1,rp,r3 +0x08,0x41,0x29,0xc3 = uaddcmt,swz r1,rp,r3 +0x08,0x41,0x49,0xc3 = uaddcmt,sbz r1,rp,r3 +0x08,0x41,0x69,0xc3 = uaddcmt,shz r1,rp,r3 +0x08,0x41,0x19,0xc3 = uaddcmt,tr r1,rp,r3 +0x08,0x41,0x39,0xc3 = uaddcmt,nwz r1,rp,r3 +0x08,0x41,0x59,0xc3 = uaddcmt,nbz r1,rp,r3 +0x08,0x41,0x79,0xc3 = uaddcmt,nhz r1,rp,r3 +0x08,0x41,0x0a,0x03 = addl r1,rp,r3 +0x08,0x41,0x2a,0x03 = addl,= r1,rp,r3 +0x08,0x41,0x4a,0x03 = addl,< r1,rp,r3 +0x08,0x41,0x6a,0x03 = addl,<= r1,rp,r3 +0x08,0x41,0x8a,0x03 = addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0x03 = addl,znv r1,rp,r3 +0x08,0x41,0xca,0x03 = addl,sv r1,rp,r3 +0x08,0x41,0xea,0x03 = addl,od r1,rp,r3 +0x08,0x41,0x1a,0x03 = addl,tr r1,rp,r3 +0x08,0x41,0x3a,0x03 = addl,<> r1,rp,r3 +0x08,0x41,0x5a,0x03 = addl,>= r1,rp,r3 +0x08,0x41,0x7a,0x03 = addl,> r1,rp,r3 +0x08,0x41,0x9a,0x03 = addl,uv r1,rp,r3 +0x08,0x41,0xba,0x03 = addl,vnz r1,rp,r3 +0x08,0x41,0xda,0x03 = addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0x03 = addl,ev r1,rp,r3 +0x08,0x41,0x0a,0x43 = sh1addl r1,rp,r3 +0x08,0x41,0x2a,0x43 = sh1addl,= r1,rp,r3 +0x08,0x41,0x4a,0x43 = sh1addl,< r1,rp,r3 +0x08,0x41,0x6a,0x43 = sh1addl,<= r1,rp,r3 +0x08,0x41,0x8a,0x43 = sh1addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0x43 = sh1addl,znv r1,rp,r3 +0x08,0x41,0xca,0x43 = sh1addl,sv r1,rp,r3 +0x08,0x41,0xea,0x43 = sh1addl,od r1,rp,r3 +0x08,0x41,0x1a,0x43 = sh1addl,tr r1,rp,r3 +0x08,0x41,0x3a,0x43 = sh1addl,<> r1,rp,r3 +0x08,0x41,0x5a,0x43 = sh1addl,>= r1,rp,r3 +0x08,0x41,0x7a,0x43 = sh1addl,> r1,rp,r3 +0x08,0x41,0x9a,0x43 = sh1addl,uv r1,rp,r3 +0x08,0x41,0xba,0x43 = sh1addl,vnz r1,rp,r3 +0x08,0x41,0xda,0x43 = sh1addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0x43 = sh1addl,ev r1,rp,r3 +0x08,0x41,0x0a,0x83 = sh2addl r1,rp,r3 +0x08,0x41,0x2a,0x83 = sh2addl,= r1,rp,r3 +0x08,0x41,0x4a,0x83 = sh2addl,< r1,rp,r3 +0x08,0x41,0x6a,0x83 = sh2addl,<= r1,rp,r3 +0x08,0x41,0x8a,0x83 = sh2addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0x83 = sh2addl,znv r1,rp,r3 +0x08,0x41,0xca,0x83 = sh2addl,sv r1,rp,r3 +0x08,0x41,0xea,0x83 = sh2addl,od r1,rp,r3 +0x08,0x41,0x1a,0x83 = sh2addl,tr r1,rp,r3 +0x08,0x41,0x3a,0x83 = sh2addl,<> r1,rp,r3 +0x08,0x41,0x5a,0x83 = sh2addl,>= r1,rp,r3 +0x08,0x41,0x7a,0x83 = sh2addl,> r1,rp,r3 +0x08,0x41,0x9a,0x83 = sh2addl,uv r1,rp,r3 +0x08,0x41,0xba,0x83 = sh2addl,vnz r1,rp,r3 +0x08,0x41,0xda,0x83 = sh2addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0x83 = sh2addl,ev r1,rp,r3 +0x08,0x41,0x0a,0xc3 = sh3addl r1,rp,r3 +0x08,0x41,0x2a,0xc3 = sh3addl,= r1,rp,r3 +0x08,0x41,0x4a,0xc3 = sh3addl,< r1,rp,r3 +0x08,0x41,0x6a,0xc3 = sh3addl,<= r1,rp,r3 +0x08,0x41,0x8a,0xc3 = sh3addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0xc3 = sh3addl,znv r1,rp,r3 +0x08,0x41,0xca,0xc3 = sh3addl,sv r1,rp,r3 +0x08,0x41,0xea,0xc3 = sh3addl,od r1,rp,r3 +0x08,0x41,0x1a,0xc3 = sh3addl,tr r1,rp,r3 +0x08,0x41,0x3a,0xc3 = sh3addl,<> r1,rp,r3 +0x08,0x41,0x5a,0xc3 = sh3addl,>= r1,rp,r3 +0x08,0x41,0x7a,0xc3 = sh3addl,> r1,rp,r3 +0x08,0x41,0x9a,0xc3 = sh3addl,uv r1,rp,r3 +0x08,0x41,0xba,0xc3 = sh3addl,vnz r1,rp,r3 +0x08,0x41,0xda,0xc3 = sh3addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0xc3 = sh3addl,ev r1,rp,r3 +0x08,0x20,0x0b,0x82 = dcor r1,rp +0x08,0x20,0x2b,0x82 = dcor,swz r1,rp +0x08,0x20,0x4b,0x82 = dcor,sbz r1,rp +0x08,0x20,0x6b,0x82 = dcor,shz r1,rp +0x08,0x20,0x1b,0x82 = dcor,tr r1,rp +0x08,0x20,0x3b,0x82 = dcor,nwz r1,rp +0x08,0x20,0x5b,0x82 = dcor,nbz r1,rp +0x08,0x20,0x7b,0x82 = dcor,nhz r1,rp +0x08,0x20,0x0b,0xc2 = idcor r1,rp +0x08,0x20,0x2b,0xc2 = idcor,swz r1,rp +0x08,0x20,0x4b,0xc2 = idcor,sbz r1,rp +0x08,0x20,0x6b,0xc2 = idcor,shz r1,rp +0x08,0x20,0x1b,0xc2 = idcor,tr r1,rp +0x08,0x20,0x3b,0xc2 = idcor,nwz r1,rp +0x08,0x20,0x5b,0xc2 = idcor,nbz r1,rp +0x08,0x20,0x7b,0xc2 = idcor,nhz r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/arith_imm11.s.cs b/suite/MC/HPPA/arith_imm11.s.cs new file mode 100644 index 000000000..e2721e87d --- /dev/null +++ b/suite/MC/HPPA/arith_imm11.s.cs @@ -0,0 +1,97 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0xb4,0x22,0x00,0x1e = addi 0xf,r1,rp +0xb4,0x22,0x20,0x1e = addi,= 0xf,r1,rp +0xb4,0x22,0x40,0x1e = addi,< 0xf,r1,rp +0xb4,0x22,0x60,0x1e = addi,<= 0xf,r1,rp +0xb4,0x22,0x80,0x1e = addi,nuv 0xf,r1,rp +0xb4,0x22,0xa0,0x1e = addi,znv 0xf,r1,rp +0xb4,0x22,0xc0,0x1e = addi,sv 0xf,r1,rp +0xb4,0x22,0xe0,0x1e = addi,od 0xf,r1,rp +0xb4,0x22,0x10,0x1e = addi,tr 0xf,r1,rp +0xb4,0x22,0x30,0x1e = addi,<> 0xf,r1,rp +0xb4,0x22,0x50,0x1e = addi,>= 0xf,r1,rp +0xb4,0x22,0x70,0x1e = addi,> 0xf,r1,rp +0xb4,0x22,0x90,0x1e = addi,uv 0xf,r1,rp +0xb4,0x22,0xb0,0x1e = addi,vnz 0xf,r1,rp +0xb4,0x22,0xd0,0x1e = addi,nsv 0xf,r1,rp +0xb4,0x22,0xf0,0x1e = addi,ev 0xf,r1,rp +0xb0,0x22,0x00,0x1e = addit 0xf,r1,rp +0xb0,0x22,0x20,0x1e = addit,= 0xf,r1,rp +0xb0,0x22,0x40,0x1e = addit,< 0xf,r1,rp +0xb0,0x22,0x60,0x1e = addit,<= 0xf,r1,rp +0xb0,0x22,0x80,0x1e = addit,nuv 0xf,r1,rp +0xb0,0x22,0xa0,0x1e = addit,znv 0xf,r1,rp +0xb0,0x22,0xc0,0x1e = addit,sv 0xf,r1,rp +0xb0,0x22,0xe0,0x1e = addit,od 0xf,r1,rp +0xb0,0x22,0x10,0x1e = addit,tr 0xf,r1,rp +0xb0,0x22,0x30,0x1e = addit,<> 0xf,r1,rp +0xb0,0x22,0x50,0x1e = addit,>= 0xf,r1,rp +0xb0,0x22,0x70,0x1e = addit,> 0xf,r1,rp +0xb0,0x22,0x90,0x1e = addit,uv 0xf,r1,rp +0xb0,0x22,0xb0,0x1e = addit,vnz 0xf,r1,rp +0xb0,0x22,0xd0,0x1e = addit,nsv 0xf,r1,rp +0xb0,0x22,0xf0,0x1e = addit,ev 0xf,r1,rp +0x94,0x22,0x00,0x1e = subi 0xf,r1,rp +0x94,0x22,0x20,0x1e = subi,= 0xf,r1,rp +0x94,0x22,0x40,0x1e = subi,< 0xf,r1,rp +0x94,0x22,0x60,0x1e = subi,<= 0xf,r1,rp +0x94,0x22,0x80,0x1e = subi,<< 0xf,r1,rp +0x94,0x22,0xa0,0x1e = subi,<<= 0xf,r1,rp +0x94,0x22,0xc0,0x1e = subi,sv 0xf,r1,rp +0x94,0x22,0xe0,0x1e = subi,od 0xf,r1,rp +0x94,0x22,0x10,0x1e = subi,tr 0xf,r1,rp +0x94,0x22,0x30,0x1e = subi,<> 0xf,r1,rp +0x94,0x22,0x50,0x1e = subi,>= 0xf,r1,rp +0x94,0x22,0x70,0x1e = subi,> 0xf,r1,rp +0x94,0x22,0x90,0x1e = subi,>>= 0xf,r1,rp +0x94,0x22,0xb0,0x1e = subi,>> 0xf,r1,rp +0x94,0x22,0xd0,0x1e = subi,nsv 0xf,r1,rp +0x94,0x22,0xf0,0x1e = subi,ev 0xf,r1,rp +0xb4,0x22,0x08,0x1e = addio 0xf,r1,rp +0xb4,0x22,0x28,0x1e = addio,= 0xf,r1,rp +0xb4,0x22,0x48,0x1e = addio,< 0xf,r1,rp +0xb4,0x22,0x68,0x1e = addio,<= 0xf,r1,rp +0xb4,0x22,0x88,0x1e = addio,nuv 0xf,r1,rp +0xb4,0x22,0xa8,0x1e = addio,znv 0xf,r1,rp +0xb4,0x22,0xc8,0x1e = addio,sv 0xf,r1,rp +0xb4,0x22,0xe8,0x1e = addio,od 0xf,r1,rp +0xb4,0x22,0x18,0x1e = addio,tr 0xf,r1,rp +0xb4,0x22,0x38,0x1e = addio,<> 0xf,r1,rp +0xb4,0x22,0x58,0x1e = addio,>= 0xf,r1,rp +0xb4,0x22,0x78,0x1e = addio,> 0xf,r1,rp +0xb4,0x22,0x98,0x1e = addio,uv 0xf,r1,rp +0xb4,0x22,0xb8,0x1e = addio,vnz 0xf,r1,rp +0xb4,0x22,0xd8,0x1e = addio,nsv 0xf,r1,rp +0xb4,0x22,0xf8,0x1e = addio,ev 0xf,r1,rp +0xb0,0x22,0x08,0x1e = addito 0xf,r1,rp +0xb0,0x22,0x28,0x1e = addito,= 0xf,r1,rp +0xb0,0x22,0x48,0x1e = addito,< 0xf,r1,rp +0xb0,0x22,0x68,0x1e = addito,<= 0xf,r1,rp +0xb0,0x22,0x88,0x1e = addito,nuv 0xf,r1,rp +0xb0,0x22,0xa8,0x1e = addito,znv 0xf,r1,rp +0xb0,0x22,0xc8,0x1e = addito,sv 0xf,r1,rp +0xb0,0x22,0xe8,0x1e = addito,od 0xf,r1,rp +0xb0,0x22,0x18,0x1e = addito,tr 0xf,r1,rp +0xb0,0x22,0x38,0x1e = addito,<> 0xf,r1,rp +0xb0,0x22,0x58,0x1e = addito,>= 0xf,r1,rp +0xb0,0x22,0x78,0x1e = addito,> 0xf,r1,rp +0xb0,0x22,0x98,0x1e = addito,uv 0xf,r1,rp +0xb0,0x22,0xb8,0x1e = addito,vnz 0xf,r1,rp +0xb0,0x22,0xd8,0x1e = addito,nsv 0xf,r1,rp +0xb0,0x22,0xf8,0x1e = addito,ev 0xf,r1,rp +0x94,0x22,0x08,0x1e = subio 0xf,r1,rp +0x94,0x22,0x28,0x1e = subio,= 0xf,r1,rp +0x94,0x22,0x48,0x1e = subio,< 0xf,r1,rp +0x94,0x22,0x68,0x1e = subio,<= 0xf,r1,rp +0x94,0x22,0x88,0x1e = subio,<< 0xf,r1,rp +0x94,0x22,0xa8,0x1e = subio,<<= 0xf,r1,rp +0x94,0x22,0xc8,0x1e = subio,sv 0xf,r1,rp +0x94,0x22,0xe8,0x1e = subio,od 0xf,r1,rp +0x94,0x22,0x18,0x1e = subio,tr 0xf,r1,rp +0x94,0x22,0x38,0x1e = subio,<> 0xf,r1,rp +0x94,0x22,0x58,0x1e = subio,>= 0xf,r1,rp +0x94,0x22,0x78,0x1e = subio,> 0xf,r1,rp +0x94,0x22,0x98,0x1e = subio,>>= 0xf,r1,rp +0x94,0x22,0xb8,0x1e = subio,>> 0xf,r1,rp +0x94,0x22,0xd8,0x1e = subio,nsv 0xf,r1,rp +0x94,0x22,0xf8,0x1e = subio,ev 0xf,r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/assist20.s.cs b/suite/MC/HPPA/assist20.s.cs new file mode 100644 index 000000000..e19fc2783 --- /dev/null +++ b/suite/MC/HPPA/assist20.s.cs @@ -0,0 +1,32 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x10,0x00,0x00,0x61 = spop0,1,1,n +0x10,0x00,0x0a,0x61 = spop1,1,1,n r1 +0x10,0x20,0x04,0x61 = spop2,1,1,n r1 +0x10,0x41,0x06,0x61 = spop3,1,1,n r1,rp +0x30,0x00,0x01,0x61 = copr,5,1,n +0x2c,0x5e,0x59,0x41 = cldd,5,sl 0xf(sr1,rp),r1 +0x2c,0x5e,0x79,0x61 = cldd,5,mb,sl 0xf(sr1,rp),r1 +0x2c,0x5e,0x59,0x61 = cldd,5,ma,sl 0xf(sr1,rp),r1 +0x2c,0x41,0x49,0x43 = cldd,5,sl 2(sr1,rp),r3 +0x2c,0x41,0x69,0x43 = cldd,5,s,sl 2(sr1,rp),r3 +0x2c,0x41,0x69,0x63 = cldd,5,sm,sl 2(sr1,rp),r3 +0x2c,0x41,0x49,0x63 = cldd,5,m,sl 2(sr1,rp),r3 +0x24,0x5e,0x59,0x41 = cldw,5,sl 0xf(sr1,rp),r1 +0x24,0x5e,0x79,0x61 = cldw,5,mb,sl 0xf(sr1,rp),r1 +0x24,0x5e,0x59,0x61 = cldw,5,ma,sl 0xf(sr1,rp),r1 +0x24,0x41,0x49,0x43 = cldw,5,sl r1(sr1,rp),r3 +0x24,0x41,0x69,0x43 = cldw,5,s,sl r1(sr1,rp),r3 +0x24,0x41,0x69,0x63 = cldw,5,sm,sl r1(sr1,rp),r3 +0x24,0x41,0x49,0x63 = cldw,5,m,sl r1(sr1,rp),r3 +0x2c,0x5e,0x17,0x41 = cstd,5,bc r1,0xf(rp) +0x2c,0x5e,0x37,0x61 = cstd,5,mb,bc r1,0xf(rp) +0x2c,0x5e,0x17,0x61 = cstd,5,ma,bc r1,0xf(rp) +0x2c,0x43,0x07,0x41 = cstd,5,bc r1,r3(rp) +0x2c,0x43,0x27,0x41 = cstd,5,s,bc r1,r3(rp) +0x2c,0x43,0x27,0x61 = cstd,5,sm,bc r1,r3(rp) +0x24,0x5e,0x17,0x41 = cstw,5,bc r1,0xf(rp) +0x24,0x5e,0x37,0x61 = cstw,5,mb,bc r1,0xf(rp) +0x24,0x5e,0x17,0x61 = cstw,5,ma,bc r1,0xf(rp) +0x24,0x43,0x07,0x41 = cstw,5,bc r1,r3(rp) +0x24,0x43,0x27,0x41 = cstw,5,s,bc r1,r3(rp) +0x24,0x43,0x27,0x61 = cstw,5,sm,bc r1,r3(rp) \ No newline at end of file diff --git a/suite/MC/HPPA/branch11.s.cs b/suite/MC/HPPA/branch11.s.cs new file mode 100644 index 000000000..af58e2bcf --- /dev/null +++ b/suite/MC/HPPA/branch11.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0xe8,0x3f,0x1f,0x75 = bl 0xffffffffffffffc0,r1 +0xe8,0x3f,0x1f,0x6f = bl,n 0xffffffffffffffbc,r1 +0xe8,0x41,0x40,0x00 = blr r1,rp +0xe8,0x41,0x40,0x02 = blr,n r1,rp +0xe8,0x41,0xc0,0x00 = bv r1(rp) +0xe8,0x41,0xc0,0x02 = bv,n r1(rp) +0xe8,0x5f,0x3f,0x45 = gate 0xffffffffffffffa8,rp +0xe8,0x5f,0x3f,0x3f = gate,n 0xffffffffffffffa4,rp \ No newline at end of file diff --git a/suite/MC/HPPA/branch20.s.cs b/suite/MC/HPPA/branch20.s.cs new file mode 100644 index 000000000..3127b0048 --- /dev/null +++ b/suite/MC/HPPA/branch20.s.cs @@ -0,0 +1,43 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0xeb,0xff,0xb8,0x9d = b,l 0xfffffffffffffc54,r31 +0xeb,0xff,0xb8,0x97 = b,l,n 0xfffffffffffffc50,r31 +0xeb,0x9f,0x38,0x8d = b,gate 0xfffffffffffffc4c,ret0 +0xeb,0x9f,0x38,0x87 = b,gate,n 0xfffffffffffffc48,ret0 +0xeb,0xff,0x98,0x7d = b,l,push 0xfffffffffffffc44,r31 +0xeb,0xff,0x98,0x77 = b,l,push,n 0xfffffffffffffc40,r31 +0xe8,0x41,0x40,0x00 = blr r1,rp +0xe8,0x41,0x40,0x02 = blr,n r1,rp +0xe8,0x41,0xc0,0x00 = bv r1(rp) +0xe8,0x41,0xc0,0x02 = bv,n r1(rp) +0xe0,0x20,0x40,0x00 = be 0(sr1,r1) +0xe0,0x20,0x40,0x02 = be,n 0(sr1,r1) +0xe4,0x20,0x40,0x00 = be,l 0(sr1,r1),sr0,r31 +0xe4,0x20,0x40,0x02 = be,l,n 0(sr1,r1),sr0,r31 +0xe8,0x40,0xd0,0x00 = bve (rp) +0xe8,0x40,0xd0,0x02 = bve,n (rp) +0xe8,0x40,0xd0,0x01 = bve,pop (rp) +0xe8,0x40,0xd0,0x03 = bve,pop,n (rp) +0xe8,0x20,0xf0,0x00 = bve,l (r1),rp +0xe8,0x20,0xf0,0x02 = bve,l,n (r1),rp +0xe8,0x20,0xf0,0x01 = bve,l,push (r1),rp +0xe8,0x20,0xf0,0x03 = bve,l,push,n (r1),rp +0xa0,0x41,0x17,0xed = addb r1,rp,0xfffffffffffffbfc +0xa0,0x41,0x37,0xe5 = addb,= r1,rp,0xfffffffffffffbf8 +0xa0,0x41,0x37,0xdf = addb,=,n r1,rp,0xfffffffffffffbf4 +0xa4,0x5e,0x17,0xd5 = addib 0xf,rp,0xfffffffffffffbf0 +0xa4,0x5e,0x37,0xcd = addib,= 0xf,rp,0xfffffffffffffbec +0xa4,0x5e,0x37,0xc7 = addib,=,n 0xf,rp,0xfffffffffffffbe8 +0xc5,0xe1,0xd7,0xbd = bb,>= r1,0xf,0xfffffffffffffbe4 +0xc5,0xe1,0xd7,0xb7 = bb,>=,n r1,0xf,0xfffffffffffffbe0 +0x80,0x41,0x17,0xad = cmpb r1,rp,0xfffffffffffffbdc +0x80,0x41,0x37,0xa5 = cmpb,= r1,rp,0xfffffffffffffbd8 +0x80,0x41,0x37,0x9f = cmpb,=,n r1,rp,0xfffffffffffffbd4 +0x84,0x5e,0x17,0x95 = cmpib 0xf,rp,0xfffffffffffffbd0 +0x84,0x5e,0x37,0x8d = cmpib,= 0xf,rp,0xfffffffffffffbcc +0x84,0x5e,0x37,0x87 = cmpib,=,n 0xf,rp,0xfffffffffffffbc8 +0xc8,0x41,0x17,0x7d = movb r1,rp,0xfffffffffffffbc4 +0xc8,0x41,0x37,0x75 = movb,= r1,rp,0xfffffffffffffbc0 +0xc8,0x41,0x37,0x6f = movb,=,n r1,rp,0xfffffffffffffbbc +0xcc,0x5e,0x17,0x65 = movib 0xf,rp,0xfffffffffffffbb8 +0xcc,0x5e,0x37,0x5d = movib,= 0xf,rp,0xfffffffffffffbb4 +0xcc,0x5e,0x37,0x57 = movib,=,n 0xf,rp,0xfffffffffffffbb0 \ No newline at end of file diff --git a/suite/MC/HPPA/computation20.s.cs b/suite/MC/HPPA/computation20.s.cs new file mode 100644 index 000000000..e1cf5a8f7 --- /dev/null +++ b/suite/MC/HPPA/computation20.s.cs @@ -0,0 +1,63 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x08,0x41,0x66,0x03 = add,<= r1,rp,r3 +0x08,0x41,0x07,0x03 = add,c r1,rp,r3 +0x08,0x41,0x57,0x03 = add,c,>= r1,rp,r3 +0x08,0x41,0x07,0x23 = add,dc,* r1,rp,r3 +0x08,0x41,0x27,0x23 = add,dc,*= r1,rp,r3 +0x08,0x41,0x0a,0x03 = add,l r1,rp,r3 +0x08,0x41,0x4a,0x03 = add,l,< r1,rp,r3 +0x08,0x41,0x0e,0x03 = add,tsv r1,rp,r3 +0x08,0x41,0x7e,0x03 = add,tsv,> r1,rp,r3 +0x08,0x41,0x0f,0x03 = add,c,tsv r1,rp,r3 +0x08,0x41,0x3f,0x03 = add,c,tsv,<> r1,rp,r3 +0x08,0x41,0x0f,0x23 = add,dc,tsv,* r1,rp,r3 +0x08,0x41,0x5f,0x23 = add,dc,tsv,*>= r1,rp,r3 +0x08,0x41,0x06,0xc3 = shladd r1,3,rp,r3 +0x08,0x41,0x0a,0xc3 = shladd,l r1,3,rp,r3 +0x08,0x41,0x0e,0xc3 = shladd,tsv r1,3,rp,r3 +0x08,0x41,0xce,0xc3 = shladd,tsv,sv r1,3,rp,r3 +0x08,0x41,0x04,0x03 = sub r1,rp,r3 +0x08,0x41,0x04,0xc3 = sub,tc r1,rp,r3 +0x08,0x41,0x05,0x03 = sub,b r1,rp,r3 +0x08,0x41,0x0c,0x03 = sub,tsv r1,rp,r3 +0x08,0x41,0x0c,0xc3 = sub,tsv,tc r1,rp,r3 +0x08,0x41,0x0d,0x03 = sub,b,tsv r1,rp,r3 +0x08,0x41,0x6d,0x23 = sub,db,tsv,*<= r1,rp,r3 +0x08,0x41,0x02,0x43 = or r1,rp,r3 +0x08,0x41,0x22,0x43 = or,= r1,rp,r3 +0x08,0x41,0x02,0x83 = xor r1,rp,r3 +0x08,0x41,0x62,0x83 = xor,<= r1,rp,r3 +0x08,0x41,0x02,0x03 = and r1,rp,r3 +0x08,0x41,0x62,0x03 = and,<= r1,rp,r3 +0x08,0x41,0x00,0x03 = andcm r1,rp,r3 +0x08,0x41,0x60,0x03 = andcm,<= r1,rp,r3 +0x08,0x41,0x09,0x83 = uaddcm r1,rp,r3 +0x08,0x41,0x49,0x83 = uaddcm,sbz r1,rp,r3 +0x08,0x41,0x09,0xc3 = uaddcm,tc r1,rp,r3 +0x08,0x41,0x03,0x83 = uxor r1,rp,r3 +0x08,0x41,0x43,0x83 = uxor,sbz r1,rp,r3 +0x08,0x41,0x04,0x43 = ds r1,rp,r3 +0x08,0x41,0xa4,0x43 = ds,<<= r1,rp,r3 +0x08,0x41,0x08,0x83 = cmpclr r1,rp,r3 +0x08,0x41,0x98,0x83 = cmpclr,>>= r1,rp,r3 +0x08,0x20,0x0b,0x82 = dcor r1,rp +0x08,0x20,0x0b,0xc2 = dcor,i r1,rp +0x08,0x20,0x4b,0xc2 = dcor,i,sbz r1,rp +0xb4,0x22,0x01,0xbc = addi 0xde,r1,rp +0xb4,0x22,0x09,0xbc = addi,tsv 0xde,r1,rp +0xb0,0x22,0x01,0xbc = addi,tc 0xde,r1,rp +0xb0,0x22,0x09,0xbc = addi,tsv,tc 0xde,r1,rp +0xb0,0x22,0x69,0xbc = addi,tsv,tc,<= 0xde,r1,rp +0x94,0x22,0x01,0xbc = subi 0xde,r1,rp +0x94,0x22,0x09,0xbc = subi,tsv 0xde,r1,rp +0x94,0x22,0x29,0xbc = subi,tsv,= 0xde,r1,rp +0x90,0x43,0x01,0xbc = cmpiclr 0xde,rp,r3 +0x90,0x43,0x91,0xbc = cmpiclr,>>= 0xde,rp,r3 +0xd0,0x41,0x0f,0x83 = shrpd,* r1,rp,3,r3 +0xd0,0x41,0x4f,0x83 = shrpd,*< r1,rp,3,r3 +0xd0,0x41,0x0b,0x83 = shrpw r1,rp,3,r3 +0xd0,0x41,0x4b,0x83 = shrpw,< r1,rp,3,r3 +0xd0,0x22,0x16,0x1c = extrd,s,* r1,sar,4,rp +0xd8,0x22,0x07,0xdc = extrd,s,* r1,0x1e,4,rp +0xd8,0x22,0x03,0xdc = extrd,u,* r1,0x1e,4,rp +0xd8,0x22,0xc3,0xdc = extrd,u,*>= r1,0x1e,4,rp \ No newline at end of file diff --git a/suite/MC/HPPA/copr_dw11.s.cs b/suite/MC/HPPA/copr_dw11.s.cs new file mode 100644 index 000000000..5187667a5 --- /dev/null +++ b/suite/MC/HPPA/copr_dw11.s.cs @@ -0,0 +1,41 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x24,0x41,0x40,0xc3 = cldwx,3 r1(sr1,rp),r3 +0x24,0x41,0x60,0xc3 = cldwx,3,s r1(sr1,rp),r3 +0x24,0x41,0x40,0xe3 = cldwx,3,m r1(sr1,rp),r3 +0x24,0x41,0x60,0xe3 = cldwx,3,sm r1(sr1,rp),r3 +0x24,0x41,0x68,0xe3 = cldwx,3,sm,sl r1(sr1,rp),r3 +0x2c,0x41,0x40,0xc3 = clddx,3 r1(sr1,rp),r3 +0x2c,0x41,0x60,0xc3 = clddx,3,s r1(sr1,rp),r3 +0x2c,0x41,0x40,0xe3 = clddx,3,m r1(sr1,rp),r3 +0x2c,0x41,0x60,0xe3 = clddx,3,sm r1(sr1,rp),r3 +0x2c,0x41,0x68,0xe3 = clddx,3,sm,sl r1(sr1,rp),r3 +0x24,0x62,0x42,0xc1 = cstwx,3 r1,rp(sr1,r3) +0x24,0x62,0x62,0xc1 = cstwx,3,s r1,rp(sr1,r3) +0x24,0x62,0x42,0xe1 = cstwx,3,m r1,rp(sr1,r3) +0x24,0x62,0x46,0xe1 = cstwx,3,m,bc r1,rp(sr1,r3) +0x24,0x62,0x62,0xe1 = cstwx,3,sm r1,rp(sr1,r3) +0x24,0x62,0x6a,0xe1 = cstwx,3,sm,sl r1,rp(sr1,r3) +0x2c,0x62,0x42,0xc1 = cstdx,3 r1,rp(sr1,r3) +0x2c,0x62,0x62,0xc1 = cstdx,3,s r1,rp(sr1,r3) +0x2c,0x62,0x42,0xe1 = cstdx,3,m r1,rp(sr1,r3) +0x2c,0x62,0x46,0xe1 = cstdx,3,m,bc r1,rp(sr1,r3) +0x2c,0x62,0x62,0xe1 = cstdx,3,sm r1,rp(sr1,r3) +0x2c,0x62,0x6a,0xe1 = cstdx,3,sm,sl r1,rp(sr1,r3) +0x24,0x3e,0x50,0xc2 = cldws,3 0xf(sr1,r1),rp +0x24,0x3e,0x50,0xe2 = cldws,3,ma 0xf(sr1,r1),rp +0x24,0x3e,0x70,0xe2 = cldws,3,mb 0xf(sr1,r1),rp +0x24,0x3e,0x78,0xe2 = cldws,3,mb,sl 0xf(sr1,r1),rp +0x2c,0x3e,0x50,0xc2 = cldds,3 0xf(sr1,r1),rp +0x2c,0x3e,0x50,0xe2 = cldds,3,ma 0xf(sr1,r1),rp +0x2c,0x3e,0x70,0xe2 = cldds,3,mb 0xf(sr1,r1),rp +0x2c,0x3e,0x78,0xe2 = cldds,3,mb,sl 0xf(sr1,r1),rp +0x24,0x5e,0x52,0xc1 = cstws,3 r1,0xf(sr1,rp) +0x24,0x5e,0x52,0xe1 = cstws,3,ma r1,0xf(sr1,rp) +0x24,0x5e,0x56,0xe1 = cstws,3,ma,bc r1,0xf(sr1,rp) +0x24,0x5e,0x72,0xe1 = cstws,3,mb r1,0xf(sr1,rp) +0x24,0x5e,0x7a,0xe1 = cstws,3,mb,sl r1,0xf(sr1,rp) +0x2c,0x5e,0x52,0xc1 = cstds,3 r1,0xf(sr1,rp) +0x2c,0x5e,0x52,0xe1 = cstds,3,ma r1,0xf(sr1,rp) +0x2c,0x5e,0x56,0xe1 = cstds,3,ma,bc r1,0xf(sr1,rp) +0x2c,0x5e,0x72,0xe1 = cstds,3,mb r1,0xf(sr1,rp) +0x2c,0x5e,0x7a,0xe1 = cstds,3,mb,sl r1,0xf(sr1,rp) \ No newline at end of file diff --git a/suite/MC/HPPA/float11.s.cs b/suite/MC/HPPA/float11.s.cs new file mode 100644 index 000000000..45c5e5431 --- /dev/null +++ b/suite/MC/HPPA/float11.s.cs @@ -0,0 +1,89 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x30,0x00,0x00,0x20 = copr,0,0,n +0x30,0x00,0x00,0x62 = copr,1,2,n +0x30,0x20,0x40,0x02 = fcpy,sgl fpe2,fpe4 +0x30,0x20,0x48,0x02 = fcpy,dbl fpe2,fpe4 +0x30,0x20,0x58,0x02 = fcpy,quad fpe2,fpe4 +0x30,0x20,0x60,0x02 = fabs,sgl fpe2,fpe4 +0x30,0x20,0x68,0x02 = fabs,dbl fpe2,fpe4 +0x30,0x20,0x78,0x02 = fabs,quad fpe2,fpe4 +0x30,0x20,0x80,0x02 = fsqrt,sgl fpe2,fpe4 +0x30,0x20,0x88,0x02 = fsqrt,dbl fpe2,fpe4 +0x30,0x20,0x98,0x02 = fsqrt,quad fpe2,fpe4 +0x30,0x20,0xa0,0x02 = frnd,sgl fpe2,fpe4 +0x30,0x20,0xa8,0x02 = frnd,dbl fpe2,fpe4 +0x30,0x20,0xb8,0x02 = frnd,quad fpe2,fpe4 +0x30,0x20,0x22,0x02 = fcnvff,sgl,dbl fpe2,fpe4 +0x30,0x20,0x62,0x02 = fcnvff,sgl,quad fpe2,fpe4 +0x30,0x20,0x0a,0x02 = fcnvff,dbl,sgl fpe2,fpe4 +0x30,0x20,0x6a,0x02 = fcnvff,dbl,quad fpe2,fpe4 +0x30,0x20,0x02,0x02 = fcnvff,sgl,sgl fpe2,fpe4 +0x30,0x20,0x2a,0x02 = fcnvff,dbl,dbl fpe2,fpe4 +0x30,0x20,0x7a,0x02 = fcnvff,quad,quad fpe2,fpe4 +0x30,0x20,0xa2,0x02 = fcnvxf,sgl,dbl fpe2,fpe4 +0x30,0x20,0xe2,0x02 = fcnvxf,sgl,quad fpe2,fpe4 +0x30,0x20,0x8a,0x02 = fcnvxf,dbl,sgl fpe2,fpe4 +0x30,0x20,0xea,0x02 = fcnvxf,dbl,quad fpe2,fpe4 +0x30,0x20,0x82,0x02 = fcnvxf,sgl,sgl fpe2,fpe4 +0x30,0x20,0xaa,0x02 = fcnvxf,dbl,dbl fpe2,fpe4 +0x30,0x20,0xfa,0x02 = fcnvxf,quad,quad fpe2,fpe4 +0x30,0x21,0x22,0x02 = fcnvfx,sgl,dbl fpe2,fpe4 +0x30,0x21,0x62,0x02 = fcnvfx,sgl,quad fpe2,fpe4 +0x30,0x21,0x0a,0x02 = fcnvfx,dbl,sgl fpe2,fpe4 +0x30,0x21,0x6a,0x02 = fcnvfx,dbl,quad fpe2,fpe4 +0x30,0x21,0x02,0x02 = fcnvfx,sgl,sgl fpe2,fpe4 +0x30,0x21,0x2a,0x02 = fcnvfx,dbl,dbl fpe2,fpe4 +0x30,0x21,0x7a,0x02 = fcnvfx,quad,quad fpe2,fpe4 +0x30,0x21,0xa2,0x02 = fcnvfxt,sgl,dbl fpe2,fpe4 +0x30,0x21,0xe2,0x02 = fcnvfxt,sgl,quad fpe2,fpe4 +0x30,0x21,0x8a,0x02 = fcnvfxt,dbl,sgl fpe2,fpe4 +0x30,0x21,0xea,0x02 = fcnvfxt,dbl,quad fpe2,fpe4 +0x30,0x21,0x82,0x02 = fcnvfxt,sgl,sgl fpe2,fpe4 +0x30,0x21,0xaa,0x02 = fcnvfxt,dbl,dbl fpe2,fpe4 +0x30,0x21,0xfa,0x02 = fcnvfxt,quad,quad fpe2,fpe4 +0x30,0x22,0x04,0x00 = fcmp,sgl,false? fpe2,fpe4 +0x30,0x22,0x04,0x01 = fcmp,sgl,false fpe2,fpe4 +0x30,0x22,0x04,0x02 = fcmp,sgl,? fpe2,fpe4 +0x30,0x22,0x04,0x03 = fcmp,sgl,!<=> fpe2,fpe4 +0x30,0x22,0x04,0x04 = fcmp,sgl,= fpe2,fpe4 +0x30,0x22,0x04,0x05 = fcmp,sgl,=t fpe2,fpe4 +0x30,0x22,0x04,0x06 = fcmp,sgl,?= fpe2,fpe4 +0x30,0x22,0x04,0x07 = fcmp,sgl,!<> fpe2,fpe4 +0x30,0x22,0x04,0x08 = fcmp,sgl,!?>= fpe2,fpe4 +0x30,0x22,0x04,0x09 = fcmp,sgl,< fpe2,fpe4 +0x30,0x22,0x04,0x0a = fcmp,sgl,?< fpe2,fpe4 +0x30,0x22,0x04,0x0b = fcmp,sgl,!>= fpe2,fpe4 +0x30,0x22,0x04,0x0c = fcmp,sgl,!?> fpe2,fpe4 +0x30,0x22,0x04,0x0d = fcmp,sgl,<= fpe2,fpe4 +0x30,0x22,0x04,0x0e = fcmp,sgl,?<= fpe2,fpe4 +0x30,0x22,0x04,0x0f = fcmp,sgl,!> fpe2,fpe4 +0x30,0x22,0x04,0x10 = fcmp,sgl,!?<= fpe2,fpe4 +0x30,0x22,0x04,0x11 = fcmp,sgl,> fpe2,fpe4 +0x30,0x22,0x04,0x12 = fcmp,sgl,?> fpe2,fpe4 +0x30,0x22,0x04,0x13 = fcmp,sgl,!<= fpe2,fpe4 +0x30,0x22,0x04,0x14 = fcmp,sgl,!?< fpe2,fpe4 +0x30,0x22,0x04,0x15 = fcmp,sgl,>= fpe2,fpe4 +0x30,0x22,0x04,0x16 = fcmp,sgl,?>= fpe2,fpe4 +0x30,0x22,0x04,0x17 = fcmp,sgl,!< fpe2,fpe4 +0x30,0x22,0x04,0x18 = fcmp,sgl,!?= fpe2,fpe4 +0x30,0x22,0x04,0x19 = fcmp,sgl,<> fpe2,fpe4 +0x30,0x22,0x04,0x1a = fcmp,sgl,!= fpe2,fpe4 +0x30,0x22,0x04,0x1b = fcmp,sgl,!=t fpe2,fpe4 +0x30,0x22,0x04,0x1c = fcmp,sgl,!? fpe2,fpe4 +0x30,0x22,0x04,0x1d = fcmp,sgl,<=> fpe2,fpe4 +0x30,0x22,0x04,0x1e = fcmp,sgl,true? fpe2,fpe4 +0x30,0x22,0x04,0x1f = fcmp,sgl,true fpe2,fpe4 +0x30,0x00,0x24,0x20 = ftest +0x30,0x22,0x06,0x03 = fadd,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x0e,0x03 = fadd,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x1e,0x03 = fadd,quad fpe2,fpe4,fpe6 +0x30,0x22,0x26,0x03 = fsub,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x2e,0x03 = fsub,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x3e,0x03 = fsub,quad fpe2,fpe4,fpe6 +0x30,0x22,0x46,0x03 = fmpy,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x4e,0x03 = fmpy,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x5e,0x03 = fmpy,quad fpe2,fpe4,fpe6 +0x30,0x22,0x66,0x03 = fdiv,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x6e,0x03 = fdiv,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x7e,0x03 = fdiv,quad fpe2,fpe4,fpe6 +0x38,0x22,0x47,0x03 = xmpyu fpe2,fpe4,fpe6 \ No newline at end of file diff --git a/suite/MC/HPPA/float20.s.cs b/suite/MC/HPPA/float20.s.cs new file mode 100644 index 000000000..c0c7f20f8 --- /dev/null +++ b/suite/MC/HPPA/float20.s.cs @@ -0,0 +1,57 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x24,0x2a,0x10,0x14 = fldw 5(r1),fr20 +0x24,0x2a,0x30,0x34 = fldw,mb 5(r1),fr20 +0x24,0x2a,0x10,0x34 = fldw,ma 5(r1),fr20 +0x24,0x22,0x00,0x14 = fldw rp(r1),fr20 +0x24,0x22,0x20,0x14 = fldw,s rp(r1),fr20 +0x24,0x22,0x20,0x34 = fldw,sm rp(r1),fr20 +0x24,0x22,0x00,0x34 = fldw,m rp(r1),fr20 +0x2c,0x2a,0x10,0x14 = fldd 5(r1),fr20 +0x2c,0x2a,0x30,0x34 = fldd,mb 5(r1),fr20 +0x2c,0x2a,0x10,0x34 = fldd,ma 5(r1),fr20 +0x2c,0x22,0x00,0x14 = fldd rp(r1),fr20 +0x2c,0x22,0x20,0x14 = fldd,s rp(r1),fr20 +0x2c,0x22,0x20,0x34 = fldd,sm rp(r1),fr20 +0x2c,0x22,0x00,0x34 = fldd,m rp(r1),fr20 +0x24,0x5e,0x12,0x14 = fstw fr20,0xf(rp) +0x24,0x5e,0x32,0x34 = fstw,mb fr20,0xf(rp) +0x24,0x5e,0x12,0x34 = fstw,ma fr20,0xf(rp) +0x24,0x41,0x06,0x14 = fstw,bc fr20,r1(rp) +0x24,0x41,0x26,0x14 = fstw,s,bc fr20,r1(rp) +0x24,0x41,0x26,0x34 = fstw,sm,bc fr20,r1(rp) +0x24,0x41,0x06,0x34 = fstw,m,bc fr20,r1(rp) +0x2c,0x5e,0x12,0x14 = fstd fr20,0xf(rp) +0x2c,0x5e,0x32,0x34 = fstd,mb fr20,0xf(rp) +0x2c,0x5e,0x12,0x34 = fstd,ma fr20,0xf(rp) +0x2c,0x41,0x06,0x14 = fstd,bc fr20,r1(rp) +0x2c,0x41,0x26,0x14 = fstd,s,bc fr20,r1(rp) +0x2c,0x41,0x26,0x34 = fstd,sm,bc fr20,r1(rp) +0x2c,0x41,0x06,0x34 = fstd,m,bc fr20,r1(rp) +0x30,0x00,0x00,0x00 = fid +0x32,0x80,0x40,0x15 = fcpy,sgl fr20,fr21 +0x32,0x80,0x60,0x15 = fabs,sgl fr20,fr21 +0x32,0x80,0x80,0x15 = fsqrt,sgl fr20,fr21 +0x32,0x80,0xa0,0x15 = frnd,sgl fr20,fr21 +0x32,0x80,0xc0,0x15 = fneg,sgl fr20,fr21 +0x32,0x80,0xe0,0x15 = fnegabs,sgl fr20,fr21 +0x32,0x80,0x22,0x15 = fcnv,sgl,dbl fr20,fr21 +0x32,0x80,0xa2,0x15 = fcnv,w,dbl fr20,fr21 +0x32,0x95,0x04,0x04 = fcmp,sgl,= fr20,fr21 +0x32,0x95,0x44,0x04 = fcmp,sgl,= fr20,fr21,1 +0x30,0x00,0x64,0x20 = ftest 1 +0x30,0x00,0x24,0x21 = ftest,acc +0x30,0x00,0x24,0x25 = ftest,acc8 +0x30,0x00,0x24,0x29 = ftest,acc6 +0x30,0x00,0x24,0x2d = ftest,acc4 +0x30,0x00,0x24,0x31 = ftest,acc2 +0x30,0x00,0x24,0x22 = ftest,rej +0x30,0x00,0x24,0x26 = ftest,rej8 +0x32,0x95,0x06,0x16 = fadd,sgl fr20,fr21,fr22 +0x32,0x95,0x26,0x16 = fsub,sgl fr20,fr21,fr22 +0x32,0x95,0x46,0x16 = fmpy,sgl fr20,fr21,fr22 +0x32,0x95,0x66,0x16 = fdiv,sgl fr20,fr21,fr22 +0x3a,0x95,0x47,0x16 = xmpyu fr20,fr21,fr22 +0x18,0x85,0x41,0xe6 = fmpyadd,sgl fr20L,fr21L,fr22L,fr23L,fr24L +0x98,0x85,0x41,0xe6 = fmpysub,sgl fr20L,fr21L,fr22L,fr23L,fr24L +0xba,0x95,0xa4,0x17 = fmpyfadd,sgl fr20,fr21,fr22,fr23 +0xba,0x95,0xa4,0x37 = fmpynfadd,sgl fr20,fr21,fr22,fr23 \ No newline at end of file diff --git a/suite/MC/HPPA/index_mem11.s.cs b/suite/MC/HPPA/index_mem11.s.cs new file mode 100644 index 000000000..9c6f44fa6 --- /dev/null +++ b/suite/MC/HPPA/index_mem11.s.cs @@ -0,0 +1,88 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x0c,0x20,0x40,0x02 = ldbx flags(sr1,r1),rp +0x0c,0x20,0x60,0x02 = ldbx,s flags(sr1,r1),rp +0x0c,0x20,0x40,0x22 = ldbx,m flags(sr1,r1),rp +0x0c,0x20,0x60,0x22 = ldbx,sm flags(sr1,r1),rp +0x0c,0x20,0x68,0x02 = ldbx,s,sl flags(sr1,r1),rp +0x0c,0x20,0x48,0x22 = ldbx,m,sl flags(sr1,r1),rp +0x0c,0x20,0x68,0x22 = ldbx,sm,sl flags(sr1,r1),rp +0x0c,0x20,0x40,0x42 = ldhx flags(sr1,r1),rp +0x0c,0x20,0x60,0x42 = ldhx,s flags(sr1,r1),rp +0x0c,0x20,0x40,0x62 = ldhx,m flags(sr1,r1),rp +0x0c,0x20,0x60,0x62 = ldhx,sm flags(sr1,r1),rp +0x0c,0x20,0x68,0x42 = ldhx,s,sl flags(sr1,r1),rp +0x0c,0x20,0x48,0x62 = ldhx,m,sl flags(sr1,r1),rp +0x0c,0x20,0x68,0x62 = ldhx,sm,sl flags(sr1,r1),rp +0x0c,0x20,0x40,0x82 = ldwx flags(sr1,r1),rp +0x0c,0x20,0x60,0x82 = ldwx,s flags(sr1,r1),rp +0x0c,0x20,0x40,0xa2 = ldwx,m flags(sr1,r1),rp +0x0c,0x20,0x60,0xa2 = ldwx,sm flags(sr1,r1),rp +0x0c,0x20,0x68,0x82 = ldwx,s,sl flags(sr1,r1),rp +0x0c,0x20,0x48,0xa2 = ldwx,m,sl flags(sr1,r1),rp +0x0c,0x20,0x68,0xa2 = ldwx,sm,sl flags(sr1,r1),rp +0x0c,0x20,0x01,0x82 = ldwax flags(r1),rp +0x0c,0x20,0x21,0x82 = ldwax,s flags(r1),rp +0x0c,0x20,0x01,0xa2 = ldwax,m flags(r1),rp +0x0c,0x20,0x21,0xa2 = ldwax,sm flags(r1),rp +0x0c,0x20,0x29,0x82 = ldwax,s,sl flags(r1),rp +0x0c,0x20,0x09,0xa2 = ldwax,m,sl flags(r1),rp +0x0c,0x20,0x29,0xa2 = ldwax,sm,sl flags(r1),rp +0x0c,0x20,0x41,0xc2 = ldcwx flags(sr1,r1),rp +0x0c,0x20,0x61,0xc2 = ldcwx,s flags(sr1,r1),rp +0x0c,0x20,0x41,0xe2 = ldcwx,m flags(sr1,r1),rp +0x0c,0x20,0x61,0xe2 = ldcwx,sm flags(sr1,r1),rp +0x0c,0x20,0x65,0xc2 = ldcwx,s,co flags(sr1,r1),rp +0x0c,0x20,0x45,0xe2 = ldcwx,m,co flags(sr1,r1),rp +0x0c,0x20,0x65,0xe2 = ldcwx,sm,co flags(sr1,r1),rp +0x0c,0x3e,0x50,0x02 = ldbs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x22 = ldbs,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x70,0x22 = ldbs,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x58,0x22 = ldbs,ma,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x78,0x22 = ldbs,mb,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x42 = ldhs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x62 = ldhs,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x70,0x62 = ldhs,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x58,0x62 = ldhs,ma,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x78,0x62 = ldhs,mb,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x82 = ldws 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0xa2 = ldws,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x70,0xa2 = ldws,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x58,0xa2 = ldws,ma,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x78,0xa2 = ldws,mb,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x11,0x82 = ldwas 0xf(r1),rp +0x0c,0x3e,0x11,0xa2 = ldwas,ma 0xf(r1),rp +0x0c,0x3e,0x31,0xa2 = ldwas,mb 0xf(r1),rp +0x0c,0x3e,0x19,0xa2 = ldwas,ma,sl 0xf(r1),rp +0x0c,0x3e,0x39,0xa2 = ldwas,mb,sl 0xf(r1),rp +0x0c,0x3e,0x51,0xc2 = ldcws 0xf(sr1,r1),rp +0x0c,0x3e,0x51,0xe2 = ldcws,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x71,0xe2 = ldcws,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x55,0xe2 = ldcws,ma,co 0xf(sr1,r1),rp +0x0c,0x3e,0x75,0xe2 = ldcws,mb,co 0xf(sr1,r1),rp +0x0c,0x41,0x52,0x1e = stbs r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x3e = stbs,ma r1,0xf(sr1,rp) +0x0c,0x41,0x72,0x3e = stbs,mb r1,0xf(sr1,rp) +0x0c,0x41,0x56,0x3e = stbs,ma,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7a,0x3e = stbs,mb,sl r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x5e = sths r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x7e = sths,ma r1,0xf(sr1,rp) +0x0c,0x41,0x72,0x7e = sths,mb r1,0xf(sr1,rp) +0x0c,0x41,0x56,0x7e = sths,ma,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7a,0x7e = sths,mb,sl r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x9e = stws r1,0xf(sr1,rp) +0x0c,0x41,0x52,0xbe = stws,ma r1,0xf(sr1,rp) +0x0c,0x41,0x72,0xbe = stws,mb r1,0xf(sr1,rp) +0x0c,0x41,0x56,0xbe = stws,ma,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7a,0xbe = stws,mb,sl r1,0xf(sr1,rp) +0x0c,0x41,0x53,0x1e = stbys r1,0xf(sr1,rp) +0x0c,0x41,0x53,0x1e = stbys r1,0xf(sr1,rp) +0x0c,0x41,0x73,0x1e = stbys,e r1,0xf(sr1,rp) +0x0c,0x41,0x53,0x3e = stbys,b,m r1,0xf(sr1,rp) +0x0c,0x41,0x73,0x3e = stbys,e,m r1,0xf(sr1,rp) +0x0c,0x41,0x57,0x3e = stbys,b,m,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7b,0x3e = stbys,e,m,sl r1,0xf(sr1,rp) +0x0c,0x41,0x13,0x9e = stwas r1,0xf(rp) +0x0c,0x41,0x33,0xbe = stwas,mb r1,0xf(rp) +0x0c,0x41,0x13,0xbe = stwas,ma r1,0xf(rp) +0x0c,0x41,0x37,0xbe = stwas,mb,bc r1,0xf(rp) +0x0c,0x41,0x1b,0xbe = stwas,ma,sl r1,0xf(rp) \ No newline at end of file diff --git a/suite/MC/HPPA/longimm20.s.cs b/suite/MC/HPPA/longimm20.s.cs new file mode 100644 index 000000000..b7dce2bad --- /dev/null +++ b/suite/MC/HPPA/longimm20.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x34,0x22,0x3f,0xf1 = ldo -8(r1),rp +0x23,0x98,0xc5,0x4f = ldil -0x55810000,ret0 +0x2b,0x98,0xc5,0x4f = addil -0x55810000,ret0 \ No newline at end of file diff --git a/suite/MC/HPPA/mem_mgmt11.s.cs b/suite/MC/HPPA/mem_mgmt11.s.cs new file mode 100644 index 000000000..054ea8662 --- /dev/null +++ b/suite/MC/HPPA/mem_mgmt11.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x04,0x41,0x40,0x40 = iitlba r1,(sr1,rp) +0x04,0x41,0x40,0x00 = iitlbp r1,(sr1,rp) +0x04,0x41,0x42,0x00 = pitlb r1(sr1,rp) +0x04,0x41,0x42,0x40 = pitlbe r1(sr1,rp) +0x04,0x41,0x42,0x80 = fic r1(sr1,rp) +0x04,0x41,0x42,0xa0 = fic,m r1(sr1,rp) +0x04,0x41,0x42,0xc0 = fice r1(sr1,rp) +0x04,0x41,0x42,0xe0 = fice,m r1(sr1,rp) +0x04,0x41,0x50,0x40 = idtlba r1,(sr1,rp) +0x04,0x41,0x50,0x00 = idtlbp r1,(sr1,rp) +0x04,0x41,0x52,0x00 = pdtlb r1(sr1,rp) +0x04,0x41,0x52,0x40 = pdtlbe r1(sr1,rp) +0x04,0x41,0x52,0x80 = fdc r1(sr1,rp) +0x04,0x41,0x52,0xa0 = fdc,m r1(sr1,rp) +0x04,0x41,0x52,0xc0 = fdce r1(sr1,rp) +0x04,0x41,0x52,0xe0 = fdce,m r1(sr1,rp) +0x04,0x41,0x53,0x80 = pdc r1(sr1,rp) +0x04,0x41,0x53,0xa0 = pdc,m r1(sr1,rp) +0x04,0x22,0x51,0x83 = prober (sr1,r1),rp,r3 +0x04,0x30,0x71,0x83 = proberi (sr1,r1),0x10,r3 +0x04,0x22,0x51,0xc3 = probew (sr1,r1),rp,r3 +0x04,0x30,0x71,0xc3 = probewi (sr1,r1),0x10,r3 +0x04,0x41,0x53,0x43 = lpa r1(sr1,rp),r3 +0x04,0x41,0x53,0x03 = lci r1(sr1,rp),r3 \ No newline at end of file diff --git a/suite/MC/HPPA/memory_reference20.s.cs b/suite/MC/HPPA/memory_reference20.s.cs new file mode 100644 index 000000000..29ebc8dfe --- /dev/null +++ b/suite/MC/HPPA/memory_reference20.s.cs @@ -0,0 +1,99 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x0c,0x41,0x40,0x03 = ldb r1(sr1,rp),r3 +0x0c,0x41,0x60,0x03 = ldb,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0x23 = ldb,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0x23 = ldb,m r1(sr1,rp),r3 +0x0c,0x51,0x50,0x03 = ldb -8(sr1,rp),r3 +0x0c,0x51,0x50,0x23 = ldb,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0x23 = ldb,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0x03 = ldb,sl 8(sr1,rp),r3 +0x0c,0x41,0x40,0x43 = ldh r1(sr1,rp),r3 +0x0c,0x41,0x60,0x43 = ldh,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0x63 = ldh,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0x63 = ldh,m r1(sr1,rp),r3 +0x44,0x43,0x41,0xbc = ldh 0xde(sr1,rp),r3 +0x0c,0x51,0x50,0x63 = ldh,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0x63 = ldh,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0x43 = ldh,sl 8(sr1,rp),r3 +0x0c,0x41,0x40,0x83 = ldw r1(sr1,rp),r3 +0x0c,0x41,0x60,0x83 = ldw,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0xa3 = ldw,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0xa3 = ldw,m r1(sr1,rp),r3 +0x48,0x43,0x41,0xbc = ldw 0xde(sr1,rp),r3 +0x0c,0x51,0x50,0xa3 = ldw,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0xa3 = ldw,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0x83 = ldw,sl 8(sr1,rp),r3 +0x0c,0x41,0x40,0xc3 = ldd r1(sr1,rp),r3 +0x0c,0x41,0x60,0xc3 = ldd,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0xe3 = ldd,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0xe3 = ldd,m r1(sr1,rp),r3 +0x0c,0x51,0x50,0xc3 = ldd -8(sr1,rp),r3 +0x0c,0x51,0x50,0xe3 = ldd,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0xe3 = ldd,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0xc3 = ldd,sl 8(sr1,rp),r3 +0x60,0x21,0xbf,0xb1 = stb r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0x31 = stb,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0x31 = stb,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0x20 = stb,o r1,0(sr2,r1) +0x64,0x21,0xbf,0xb1 = sth r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0x71 = sth,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0x71 = sth,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0x60 = sth,o r1,0(sr2,r1) +0x68,0x21,0xbf,0xb1 = stw r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0xb1 = stw,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0xb1 = stw,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0xa0 = stw,o r1,0(sr2,r1) +0x70,0x21,0xbf,0xb1 = std r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0xf1 = std,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0xf1 = std,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0xe0 = std,o r1,0(sr2,r1) +0x0c,0x41,0x01,0x83 = ldwa r1(rp),r3 +0x0c,0x41,0x21,0x83 = ldwa,s r1(rp),r3 +0x0c,0x41,0x21,0xa3 = ldwa,sm r1(rp),r3 +0x0c,0x41,0x01,0xa3 = ldwa,m r1(rp),r3 +0x0c,0x51,0x11,0x83 = ldwa -8(rp),r3 +0x0c,0x51,0x11,0xa3 = ldwa,ma -8(rp),r3 +0x0c,0x51,0x31,0xa3 = ldwa,mb -8(rp),r3 +0x0c,0x50,0x19,0x83 = ldwa,sl 8(rp),r3 +0x0c,0x40,0x11,0xa3 = ldwa,o 0(rp),r3 +0x0c,0x41,0x01,0x03 = ldda r1(rp),r3 +0x0c,0x41,0x21,0x03 = ldda,s r1(rp),r3 +0x0c,0x41,0x21,0x23 = ldda,sm r1(rp),r3 +0x0c,0x41,0x01,0x23 = ldda,m r1(rp),r3 +0x0c,0x51,0x11,0x03 = ldda -8(rp),r3 +0x0c,0x51,0x11,0x23 = ldda,ma -8(rp),r3 +0x0c,0x51,0x31,0x23 = ldda,mb -8(rp),r3 +0x0c,0x50,0x19,0x03 = ldda,sl 8(rp),r3 +0x0c,0x40,0x11,0x23 = ldda,o 0(rp),r3 +0x0c,0x21,0x13,0x91 = stwa r1,-8(r1) +0x0c,0x21,0x13,0xb1 = stwa,ma r1,-8(r1) +0x0c,0x21,0x33,0xb1 = stwa,mb r1,-8(r1) +0x0c,0x21,0x13,0xa0 = stwa,o r1,0(r1) +0x0c,0x21,0x13,0xd1 = stda r1,-8(r1) +0x0c,0x21,0x13,0xf1 = stda,ma r1,-8(r1) +0x0c,0x21,0x33,0xf1 = stda,mb r1,-8(r1) +0x0c,0x21,0x13,0xe0 = stda,o r1,0(r1) +0x0c,0x41,0x41,0xc3 = ldcw r1(sr1,rp),r3 +0x0c,0x41,0x61,0xc3 = ldcw,s r1(sr1,rp),r3 +0x0c,0x41,0x61,0xe3 = ldcw,sm r1(sr1,rp),r3 +0x0c,0x41,0x41,0xe3 = ldcw,m r1(sr1,rp),r3 +0x0c,0x51,0x51,0xc3 = ldcw -8(sr1,rp),r3 +0x0c,0x51,0x51,0xe3 = ldcw,ma -8(sr1,rp),r3 +0x0c,0x51,0x71,0xe3 = ldcw,mb -8(sr1,rp),r3 +0x0c,0x40,0x55,0xc3 = ldcw,co 0(sr1,rp),r3 +0x0c,0x41,0x41,0x43 = ldcd r1(sr1,rp),r3 +0x0c,0x41,0x61,0x43 = ldcd,s r1(sr1,rp),r3 +0x0c,0x41,0x61,0x63 = ldcd,sm r1(sr1,rp),r3 +0x0c,0x41,0x41,0x63 = ldcd,m r1(sr1,rp),r3 +0x0c,0x51,0x51,0x43 = ldcd -8(sr1,rp),r3 +0x0c,0x51,0x51,0x63 = ldcd,ma -8(sr1,rp),r3 +0x0c,0x51,0x71,0x63 = ldcd,mb -8(sr1,rp),r3 +0x0c,0x40,0x55,0x43 = ldcd,co 0(sr1,rp),r3 +0x0c,0x41,0x53,0x11 = stby r1,-8(sr1,rp) +0x0c,0x41,0x53,0x31 = stby,b,m r1,-8(sr1,rp) +0x0c,0x41,0x73,0x11 = stby,e r1,-8(sr1,rp) +0x0c,0x41,0x73,0x31 = stby,e,m r1,-8(sr1,rp) +0x0c,0x41,0x53,0x51 = stdby r1,-8(sr1,rp) +0x0c,0x41,0x53,0x71 = stdby,b,m r1,-8(sr1,rp) +0x0c,0x41,0x73,0x51 = stdby,e r1,-8(sr1,rp) +0x0c,0x41,0x73,0x71 = stdby,e,m r1,-8(sr1,rp) \ No newline at end of file diff --git a/suite/MC/HPPA/multimedia20.s.cs b/suite/MC/HPPA/multimedia20.s.cs new file mode 100644 index 000000000..e83873364 --- /dev/null +++ b/suite/MC/HPPA/multimedia20.s.cs @@ -0,0 +1,14 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x08,0x41,0x03,0xc3 = hadd r1,rp,r3 +0x08,0x41,0x03,0x43 = hadd,ss r1,rp,r3 +0x08,0x41,0x03,0x03 = hadd,us r1,rp,r3 +0x08,0x41,0x01,0xc3 = hsub r1,rp,r3 +0x08,0x41,0x01,0x43 = hsub,ss r1,rp,r3 +0x08,0x41,0x01,0x03 = hsub,us r1,rp,r3 +0x08,0x41,0x02,0xc3 = havg r1,rp,r3 +0x08,0x41,0x07,0xc3 = hshladd r1,3,rp,r3 +0x08,0x41,0x05,0xc3 = hshradd r1,3,rp,r3 +0xf8,0x01,0x88,0xc2 = hshl r1,3,rp +0xf8,0x20,0xcc,0xc2 = hshr,s r1,3,rp +0xf8,0x21,0x00,0x02 = permh,0000 r1,rp +0xf8,0x21,0x06,0xc2 = permh,0123 r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/no_grp11.s.cs b/suite/MC/HPPA/no_grp11.s.cs new file mode 100644 index 000000000..508f27132 --- /dev/null +++ b/suite/MC/HPPA/no_grp11.s.cs @@ -0,0 +1,109 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x14,0x00,0x00,0x01 = diag 1 +0x18,0x22,0x29,0x03 = fmpyadd,dbl fpe2,fpe4,fpe6,fr4,fr5 +0x20,0x39,0x00,0x00 = ldil 0x32000,r1 +0x28,0x39,0x00,0x00 = addil 0x32000,r1 +0x34,0x22,0x00,0x1e = ldo 0xf(r1),rp +0x0c,0x3e,0x50,0x02 = ldbs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x42 = ldhs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x82 = ldws 0xf(sr1,r1),rp +0x4c,0x22,0x40,0x1e = ldwm 0xf(sr1,r1),rp +0x0c,0x41,0x12,0x1e = stbs r1,0xf(rp) +0x0c,0x41,0x12,0x5e = sths r1,0xf(rp) +0x0c,0x41,0x12,0x9e = stws r1,0xf(rp) +0x6c,0x41,0x00,0x1e = stwm r1,0xf(rp) +0x80,0x41,0x1f,0x0d = combt r1,rp,0xffffffffffffff8c +0x80,0x41,0x3f,0x05 = combt,= r1,rp,0xffffffffffffff88 +0x80,0x41,0x5e,0xfd = combt,< r1,rp,0xffffffffffffff84 +0x80,0x41,0x7e,0xf5 = combt,<= r1,rp,0xffffffffffffff80 +0x80,0x41,0x9e,0xed = combt,<< r1,rp,0xffffffffffffff7c +0x80,0x41,0xbe,0xe5 = combt,<<= r1,rp,0xffffffffffffff78 +0x80,0x41,0xde,0xdd = combt,sv r1,rp,0xffffffffffffff74 +0x80,0x41,0xfe,0xd5 = combt,od r1,rp,0xffffffffffffff70 +0x84,0x5e,0x1e,0xcd = comibt 0xf,rp,0xffffffffffffff6c +0x84,0x5e,0x3e,0xc5 = comibt,= 0xf,rp,0xffffffffffffff68 +0x84,0x5e,0x5e,0xbd = comibt,< 0xf,rp,0xffffffffffffff64 +0x84,0x5e,0x7e,0xb5 = comibt,<= 0xf,rp,0xffffffffffffff60 +0x84,0x5e,0x9e,0xad = comibt,<< 0xf,rp,0xffffffffffffff5c +0x84,0x5e,0xbe,0xa5 = comibt,<<= 0xf,rp,0xffffffffffffff58 +0x84,0x5e,0xde,0x9d = comibt,sv 0xf,rp,0xffffffffffffff54 +0x84,0x5e,0xfe,0x95 = comibt,od 0xf,rp,0xffffffffffffff50 +0x88,0x41,0x1e,0x8d = combf r1,rp,0xffffffffffffff4c +0x88,0x41,0x3e,0x85 = combf,= r1,rp,0xffffffffffffff48 +0x88,0x41,0x5e,0x7d = combf,< r1,rp,0xffffffffffffff44 +0x88,0x41,0x7e,0x75 = combf,<= r1,rp,0xffffffffffffff40 +0x88,0x41,0x9e,0x6d = combf,<< r1,rp,0xffffffffffffff3c +0x88,0x41,0xbe,0x65 = combf,<<= r1,rp,0xffffffffffffff38 +0x88,0x41,0xde,0x5d = combf,sv r1,rp,0xffffffffffffff34 +0x88,0x41,0xfe,0x55 = combf,od r1,rp,0xffffffffffffff30 +0x8c,0x5e,0x1e,0x4d = comibf 0xf,rp,0xffffffffffffff2c +0x8c,0x5e,0x3e,0x45 = comibf,= 0xf,rp,0xffffffffffffff28 +0x8c,0x5e,0x5e,0x3d = comibf,< 0xf,rp,0xffffffffffffff24 +0x8c,0x5e,0x7e,0x35 = comibf,<= 0xf,rp,0xffffffffffffff20 +0x8c,0x5e,0x9e,0x2d = comibf,<< 0xf,rp,0xffffffffffffff1c +0x8c,0x5e,0xbe,0x25 = comibf,<<= 0xf,rp,0xffffffffffffff18 +0x8c,0x5e,0xde,0x1d = comibf,sv 0xf,rp,0xffffffffffffff14 +0x8c,0x5e,0xfe,0x15 = comibf,od 0xf,rp,0xffffffffffffff10 +0x90,0x41,0x00,0x1e = comiclr 0xf,rp,r1 +0x90,0x41,0x20,0x1e = comiclr,= 0xf,rp,r1 +0x90,0x41,0x40,0x1e = comiclr,< 0xf,rp,r1 +0x90,0x41,0x60,0x1e = comiclr,<= 0xf,rp,r1 +0x90,0x41,0x80,0x1e = comiclr,<< 0xf,rp,r1 +0x90,0x41,0xa0,0x1e = comiclr,<<= 0xf,rp,r1 +0x90,0x41,0xc0,0x1e = comiclr,sv 0xf,rp,r1 +0x90,0x41,0xe0,0x1e = comiclr,od 0xf,rp,r1 +0x98,0x22,0x29,0x03 = fmpysub,dbl fpe2,fpe4,fpe6,fr4,fr5 +0xa0,0x41,0x1d,0xc5 = addbt r1,rp,0xfffffffffffffee8 +0xa0,0x41,0x3d,0xbd = addbt,= r1,rp,0xfffffffffffffee4 +0xa0,0x41,0x5d,0xb5 = addbt,< r1,rp,0xfffffffffffffee0 +0xa0,0x41,0x7d,0xad = addbt,<= r1,rp,0xfffffffffffffedc +0xa0,0x41,0x9d,0xa7 = addbt,nuv,n r1,rp,0xfffffffffffffed8 +0xa0,0x41,0xbd,0x9f = addbt,znv,n r1,rp,0xfffffffffffffed4 +0xa0,0x41,0xdd,0x95 = addbt,sv r1,rp,0xfffffffffffffed0 +0xa0,0x41,0xfd,0x8d = addbt,od r1,rp,0xfffffffffffffecc +0xa4,0x5e,0x1d,0x85 = addibt 0xf,rp,0xfffffffffffffec8 +0xa4,0x5e,0x3d,0x7d = addibt,= 0xf,rp,0xfffffffffffffec4 +0xa4,0x5e,0x5d,0x75 = addibt,< 0xf,rp,0xfffffffffffffec0 +0xa4,0x5e,0x7d,0x6d = addibt,<= 0xf,rp,0xfffffffffffffebc +0xa4,0x5e,0x9d,0x67 = addibt,nuv,n 0xf,rp,0xfffffffffffffeb8 +0xa4,0x5e,0xbd,0x5f = addibt,znv,n 0xf,rp,0xfffffffffffffeb4 +0xa4,0x5e,0xdd,0x55 = addibt,sv 0xf,rp,0xfffffffffffffeb0 +0xa4,0x5e,0xfd,0x4d = addibt,od 0xf,rp,0xfffffffffffffeac +0xa8,0x41,0x1d,0x45 = addbf r1,rp,0xfffffffffffffea8 +0xa8,0x41,0x3d,0x3d = addbf,= r1,rp,0xfffffffffffffea4 +0xa8,0x41,0x5d,0x35 = addbf,< r1,rp,0xfffffffffffffea0 +0xa8,0x41,0x7d,0x2d = addbf,<= r1,rp,0xfffffffffffffe9c +0xa8,0x41,0x9d,0x27 = addbf,nuv,n r1,rp,0xfffffffffffffe98 +0xa8,0x41,0xbd,0x1f = addbf,znv,n r1,rp,0xfffffffffffffe94 +0xa8,0x41,0xdd,0x15 = addbf,sv r1,rp,0xfffffffffffffe90 +0xa8,0x41,0xfd,0x0d = addbf,od r1,rp,0xfffffffffffffe8c +0xac,0x5e,0x1d,0x05 = addibf 0xf,rp,0xfffffffffffffe88 +0xac,0x5e,0x3c,0xfd = addibf,= 0xf,rp,0xfffffffffffffe84 +0xac,0x5e,0x5c,0xf5 = addibf,< 0xf,rp,0xfffffffffffffe80 +0xac,0x5e,0x7c,0xed = addibf,<= 0xf,rp,0xfffffffffffffe7c +0xac,0x5e,0x9c,0xe7 = addibf,nuv,n 0xf,rp,0xfffffffffffffe78 +0xac,0x5e,0xbc,0xdf = addibf,znv,n 0xf,rp,0xfffffffffffffe74 +0xac,0x5e,0xdc,0xd5 = addibf,sv 0xf,rp,0xfffffffffffffe70 +0xac,0x5e,0xfc,0xcd = addibf,od 0xf,rp,0xfffffffffffffe6c +0xc0,0x01,0x5c,0xc7 = bvb,<,n r1,0xfffffffffffffe68 +0xc0,0x01,0xdc,0xbf = bvb,>=,n r1,0xfffffffffffffe64 +0xc4,0x61,0x5c,0xb7 = bb,<,n r1,3,0xfffffffffffffe60 +0xc4,0x61,0xdc,0xaf = bb,>=,n r1,3,0xfffffffffffffe5c +0xc8,0x41,0x1c,0xa7 = movb,n r1,rp,0xfffffffffffffe58 +0xc8,0x41,0x3c,0x9d = movb,= r1,rp,0xfffffffffffffe54 +0xc8,0x41,0x5c,0x95 = movb,< r1,rp,0xfffffffffffffe50 +0xc8,0x41,0x7c,0x8d = movb,od r1,rp,0xfffffffffffffe4c +0xc8,0x41,0x9c,0x85 = movb,tr r1,rp,0xfffffffffffffe48 +0xc8,0x41,0xbc,0x7d = movb,<> r1,rp,0xfffffffffffffe44 +0xc8,0x41,0xdc,0x75 = movb,>= r1,rp,0xfffffffffffffe40 +0xc8,0x41,0xfc,0x6d = movb,ev r1,rp,0xfffffffffffffe3c +0xcc,0x5e,0x1c,0x67 = movib,n 0xf,rp,0xfffffffffffffe38 +0xcc,0x5e,0x3c,0x5d = movib,= 0xf,rp,0xfffffffffffffe34 +0xcc,0x5e,0x5c,0x55 = movib,< 0xf,rp,0xfffffffffffffe30 +0xcc,0x5e,0x7c,0x4d = movib,od 0xf,rp,0xfffffffffffffe2c +0xcc,0x5e,0x9c,0x45 = movib,tr 0xf,rp,0xfffffffffffffe28 +0xcc,0x5e,0xbc,0x3d = movib,<> 0xf,rp,0xfffffffffffffe24 +0xcc,0x5e,0xdc,0x35 = movib,>= 0xf,rp,0xfffffffffffffe20 +0xcc,0x5e,0xfc,0x2d = movib,ev 0xf,rp,0xfffffffffffffe1c +0xe0,0x20,0x42,0x02 = be,n 0x100(sr1,r1) +0xe4,0x20,0x42,0x02 = ble,n 0x100(sr1,r1) \ No newline at end of file diff --git a/suite/MC/HPPA/sfu11.s.cs b/suite/MC/HPPA/sfu11.s.cs new file mode 100644 index 000000000..93cd5efe0 --- /dev/null +++ b/suite/MC/HPPA/sfu11.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x10,0x00,0x00,0xa3 = spop0,2,3,n +0x10,0x00,0x1a,0xa1 = spop1,2,3,n r1 +0x10,0x20,0x04,0xa3 = spop2,2,3,n r1 +0x10,0x41,0x06,0xa3 = spop3,2,3,n r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/shexdep11.s.cs b/suite/MC/HPPA/shexdep11.s.cs new file mode 100644 index 000000000..f62164d49 --- /dev/null +++ b/suite/MC/HPPA/shexdep11.s.cs @@ -0,0 +1,225 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0xd0,0x41,0x00,0x03 = vshd r1,rp,r3 +0xd0,0x41,0x20,0x03 = vshd,= r1,rp,r3 +0xd0,0x41,0x40,0x03 = vshd,< r1,rp,r3 +0xd0,0x41,0x60,0x03 = vshd,od r1,rp,r3 +0xd0,0x41,0x80,0x03 = vshd,tr r1,rp,r3 +0xd0,0x41,0xa0,0x03 = vshd,<> r1,rp,r3 +0xd0,0x41,0xc0,0x03 = vshd,>= r1,rp,r3 +0xd0,0x41,0xe0,0x03 = vshd,ev r1,rp,r3 +0xd0,0x41,0x0a,0x03 = shd r1,rp,0xf,r3 +0xd0,0x41,0x2a,0x03 = shd,= r1,rp,0xf,r3 +0xd0,0x41,0x4a,0x03 = shd,< r1,rp,0xf,r3 +0xd0,0x41,0x6a,0x03 = shd,od r1,rp,0xf,r3 +0xd0,0x41,0x8a,0x03 = shd,tr r1,rp,0xf,r3 +0xd0,0x41,0xaa,0x03 = shd,<> r1,rp,0xf,r3 +0xd0,0x41,0xca,0x03 = shd,>= r1,rp,0xf,r3 +0xd0,0x41,0xea,0x03 = shd,ev r1,rp,0xf,r3 +0xd0,0x23,0x10,0x11 = vextru r1,0xf,r3 +0xd0,0x23,0x30,0x11 = vextru,= r1,0xf,r3 +0xd0,0x23,0x50,0x11 = vextru,< r1,0xf,r3 +0xd0,0x23,0x70,0x11 = vextru,od r1,0xf,r3 +0xd0,0x23,0x90,0x11 = vextru,tr r1,0xf,r3 +0xd0,0x23,0xb0,0x11 = vextru,<> r1,0xf,r3 +0xd0,0x23,0xd0,0x11 = vextru,>= r1,0xf,r3 +0xd0,0x23,0xf0,0x11 = vextru,ev r1,0xf,r3 +0xd0,0x23,0x14,0x11 = vextrs r1,0xf,r3 +0xd0,0x23,0x34,0x11 = vextrs,= r1,0xf,r3 +0xd0,0x23,0x54,0x11 = vextrs,< r1,0xf,r3 +0xd0,0x23,0x74,0x11 = vextrs,od r1,0xf,r3 +0xd0,0x23,0x94,0x11 = vextrs,tr r1,0xf,r3 +0xd0,0x23,0xb4,0x11 = vextrs,<> r1,0xf,r3 +0xd0,0x23,0xd4,0x11 = vextrs,>= r1,0xf,r3 +0xd0,0x23,0xf4,0x11 = vextrs,ev r1,0xf,r3 +0xd0,0x23,0x19,0xd1 = extru r1,0xe,0xf,r3 +0xd0,0x23,0x39,0xd1 = extru,= r1,0xe,0xf,r3 +0xd0,0x23,0x59,0xd1 = extru,< r1,0xe,0xf,r3 +0xd0,0x23,0x79,0xd1 = extru,od r1,0xe,0xf,r3 +0xd0,0x23,0x99,0xd1 = extru,tr r1,0xe,0xf,r3 +0xd0,0x23,0xb9,0xd1 = extru,<> r1,0xe,0xf,r3 +0xd0,0x23,0xd9,0xd1 = extru,>= r1,0xe,0xf,r3 +0xd0,0x23,0xf9,0xd1 = extru,ev r1,0xe,0xf,r3 +0xd0,0x23,0x1d,0xd1 = extrs r1,0xe,0xf,r3 +0xd0,0x23,0x3d,0xd1 = extrs,= r1,0xe,0xf,r3 +0xd0,0x23,0x5d,0xd1 = extrs,< r1,0xe,0xf,r3 +0xd0,0x23,0x7d,0xd1 = extrs,od r1,0xe,0xf,r3 +0xd0,0x23,0x9d,0xd1 = extrs,tr r1,0xe,0xf,r3 +0xd0,0x23,0xbd,0xd1 = extrs,<> r1,0xe,0xf,r3 +0xd0,0x23,0xdd,0xd1 = extrs,>= r1,0xe,0xf,r3 +0xd0,0x23,0xfd,0xd1 = extrs,ev r1,0xe,0xf,r3 +0xd4,0x61,0x00,0x11 = zvdep r1,0xf,r3 +0xd4,0x61,0x20,0x11 = zvdep,= r1,0xf,r3 +0xd4,0x61,0x40,0x11 = zvdep,< r1,0xf,r3 +0xd4,0x61,0x60,0x11 = zvdep,od r1,0xf,r3 +0xd4,0x61,0x80,0x11 = zvdep,tr r1,0xf,r3 +0xd4,0x61,0xa0,0x11 = zvdep,<> r1,0xf,r3 +0xd4,0x61,0xc0,0x11 = zvdep,>= r1,0xf,r3 +0xd4,0x61,0xe0,0x11 = zvdep,ev r1,0xf,r3 +0xd4,0x61,0x04,0x11 = vdep r1,0xf,r3 +0xd4,0x61,0x24,0x11 = vdep,= r1,0xf,r3 +0xd4,0x61,0x44,0x11 = vdep,< r1,0xf,r3 +0xd4,0x61,0x64,0x11 = vdep,od r1,0xf,r3 +0xd4,0x61,0x84,0x11 = vdep,tr r1,0xf,r3 +0xd4,0x61,0xa4,0x11 = vdep,<> r1,0xf,r3 +0xd4,0x61,0xc4,0x11 = vdep,>= r1,0xf,r3 +0xd4,0x61,0xe4,0x11 = vdep,ev r1,0xf,r3 +0xd4,0x61,0x0a,0x31 = zdep r1,0xe,0xf,r3 +0xd4,0x61,0x2a,0x31 = zdep,= r1,0xe,0xf,r3 +0xd4,0x61,0x4a,0x31 = zdep,< r1,0xe,0xf,r3 +0xd4,0x61,0x6a,0x31 = zdep,od r1,0xe,0xf,r3 +0xd4,0x61,0x8a,0x31 = zdep,tr r1,0xe,0xf,r3 +0xd4,0x61,0xaa,0x31 = zdep,<> r1,0xe,0xf,r3 +0xd4,0x61,0xca,0x31 = zdep,>= r1,0xe,0xf,r3 +0xd4,0x61,0xea,0x31 = zdep,ev r1,0xe,0xf,r3 +0xd4,0x61,0x0e,0x31 = dep r1,0xe,0xf,r3 +0xd4,0x61,0x2e,0x31 = dep,= r1,0xe,0xf,r3 +0xd4,0x61,0x4e,0x31 = dep,< r1,0xe,0xf,r3 +0xd4,0x61,0x6e,0x31 = dep,od r1,0xe,0xf,r3 +0xd4,0x61,0x8e,0x31 = dep,tr r1,0xe,0xf,r3 +0xd4,0x61,0xae,0x31 = dep,<> r1,0xe,0xf,r3 +0xd4,0x61,0xce,0x31 = dep,>= r1,0xe,0xf,r3 +0xd4,0x61,0xee,0x31 = dep,ev r1,0xe,0xf,r3 +0xd4,0x7c,0x10,0x11 = zvdepi 0xe,0xf,r3 +0xd4,0x7c,0x30,0x11 = zvdepi,= 0xe,0xf,r3 +0xd4,0x7c,0x50,0x11 = zvdepi,< 0xe,0xf,r3 +0xd4,0x7c,0x70,0x11 = zvdepi,od 0xe,0xf,r3 +0xd4,0x7c,0x90,0x11 = zvdepi,tr 0xe,0xf,r3 +0xd4,0x7c,0xb0,0x11 = zvdepi,<> 0xe,0xf,r3 +0xd4,0x7c,0xd0,0x11 = zvdepi,>= 0xe,0xf,r3 +0xd4,0x7c,0xf0,0x11 = zvdepi,ev 0xe,0xf,r3 +0xd4,0x7c,0x14,0x11 = vdepi 0xe,0xf,r3 +0xd4,0x7c,0x34,0x11 = vdepi,= 0xe,0xf,r3 +0xd4,0x7c,0x54,0x11 = vdepi,< 0xe,0xf,r3 +0xd4,0x7c,0x74,0x11 = vdepi,od 0xe,0xf,r3 +0xd4,0x7c,0x94,0x11 = vdepi,tr 0xe,0xf,r3 +0xd4,0x7c,0xb4,0x11 = vdepi,<> 0xe,0xf,r3 +0xd4,0x7c,0xd4,0x11 = vdepi,>= 0xe,0xf,r3 +0xd4,0x7c,0xf4,0x11 = vdepi,ev 0xe,0xf,r3 +0xd4,0x66,0x1b,0xbf = zdepi 3,2,1,r3 +0xd4,0x66,0x3b,0xbf = zdepi,= 3,2,1,r3 +0xd4,0x66,0x5b,0xbf = zdepi,< 3,2,1,r3 +0xd4,0x66,0x7b,0xbf = zdepi,od 3,2,1,r3 +0xd4,0x66,0x9b,0xbf = zdepi,tr 3,2,1,r3 +0xd4,0x66,0xbb,0xbf = zdepi,<> 3,2,1,r3 +0xd4,0x66,0xdb,0xbf = zdepi,>= 3,2,1,r3 +0xd4,0x66,0xfb,0xbf = zdepi,ev 3,2,1,r3 +0xd4,0x66,0x1f,0xbf = depi 3,2,1,r3 +0xd4,0x66,0x3f,0xbf = depi,= 3,2,1,r3 +0xd4,0x66,0x5f,0xbf = depi,< 3,2,1,r3 +0xd4,0x66,0x7f,0xbf = depi,od 3,2,1,r3 +0xd4,0x66,0x9f,0xbf = depi,tr 3,2,1,r3 +0xd4,0x66,0xbf,0xbf = depi,<> 3,2,1,r3 +0xd4,0x66,0xdf,0xbf = depi,>= 3,2,1,r3 +0xd4,0x66,0xff,0xbf = depi,ev 3,2,1,r3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/suite/MC/HPPA/sysctrl20.s.cs b/suite/MC/HPPA/sysctrl20.s.cs new file mode 100644 index 000000000..f6cd850e3 --- /dev/null +++ b/suite/MC/HPPA/sysctrl20.s.cs @@ -0,0 +1,49 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x00,0x20,0x50,0xa2 = ldsid (sr1,r1),rp +0x00,0x01,0x58,0x20 = mtsp r1,sr1 +0x00,0x00,0x44,0xa1 = mfsp sr1,r1 +0x00,0x41,0x18,0x40 = mtctl r1,cr2 +0x00,0x20,0x08,0xa2 = mfctl cr1,rp +0x01,0x60,0x48,0xa1 = mfctl,w sar,r1 +0x01,0x61,0x18,0xc0 = mtsarcm r1 +0x00,0x00,0x14,0xa1 = mfia r1 +0x00,0x0f,0x0d,0x61 = ssm 0xf,r1 +0x00,0x0f,0x0e,0x61 = rsm 0xf,r1 +0x00,0x01,0x18,0x60 = mtsm r1 +0x00,0x00,0x0c,0x00 = rfi +0x00,0x00,0x0c,0xa0 = rfi,r +0x03,0xff,0xc0,0x1f = break 0x1f,0x1ffe +0x00,0x00,0x04,0x00 = sync +0x00,0x10,0x04,0x00 = syncdma +0x04,0x22,0x51,0x83 = probe,r (sr1,r1),rp,r3 +0x04,0x22,0x51,0xc3 = probe,w (sr1,r1),rp,r3 +0x04,0x22,0x51,0x83 = probe,r (sr1,r1),rp,r3 +0x04,0x2f,0x71,0x83 = probei,r (sr1,r1),0xf,r3 +0x04,0x2f,0x71,0xc3 = probei,w (sr1,r1),0xf,r3 +0x04,0x2f,0x71,0x83 = probei,r (sr1,r1),0xf,r3 +0x04,0x41,0x53,0x43 = lpa r1(sr1,rp),r3 +0x04,0x41,0x53,0x63 = lpa,m r1(sr1,rp),r3 +0x04,0x41,0x53,0x03 = lci r1(sr1,rp),r3 +0x04,0x41,0x12,0x00 = pdtlb r1(rp) +0x04,0x41,0x16,0x00 = pdtlb,l r1(rp) +0x04,0x41,0x16,0x20 = pdtlb,l,m r1(rp) +0x04,0x41,0x42,0x00 = pitlb r1(sr1,rp) +0x04,0x41,0x46,0x00 = pitlb,l r1(sr1,rp) +0x04,0x41,0x46,0x20 = pitlb,l,m r1(sr1,rp) +0x04,0x41,0x12,0x40 = pdtlbe r1(rp) +0x04,0x41,0x12,0x60 = pdtlbe,m r1(rp) +0x04,0x41,0x42,0x40 = pitlbe r1(sr1,rp) +0x04,0x41,0x42,0x60 = pitlbe,m r1(sr1,rp) +0x04,0x41,0x18,0x00 = idtlbt r1,rp +0x04,0x41,0x08,0x00 = iitlbt r1,rp +0x04,0x41,0x13,0x80 = pdc r1(rp) +0x04,0x41,0x13,0xa0 = pdc,m r1(rp) +0x04,0x41,0x52,0x80 = fdc r1(sr1,rp) +0x04,0x41,0x52,0xa0 = fdc,m r1(sr1,rp) +0x04,0x5e,0x72,0x80 = fdc 0xf(sr1,rp) +0x04,0x41,0x42,0x80 = fic r1(sr1,rp) +0x04,0x41,0x52,0xc0 = fdce r1(sr1,rp) +0x04,0x41,0x52,0xe0 = fdce,m r1(sr1,rp) +0x04,0x41,0x42,0xc0 = fice r1(sr1,rp) +0x04,0x41,0x42,0xe0 = fice,m r1(sr1,rp) +0x14,0x00,0xde,0xad = diag 0xdead \ No newline at end of file diff --git a/suite/MC/HPPA/system_op11.s.cs b/suite/MC/HPPA/system_op11.s.cs new file mode 100644 index 000000000..99b362fa5 --- /dev/null +++ b/suite/MC/HPPA/system_op11.s.cs @@ -0,0 +1,14 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x00,0x00,0x20,0x01 = break 1,1 +0x00,0x00,0x04,0x00 = sync +0x00,0x10,0x04,0x00 = syncdma +0x00,0x00,0x0c,0x00 = rfi +0x00,0x00,0x0c,0xa0 = rfir +0x00,0x1e,0x0d,0x61 = ssm 0x1e,r1 +0x00,0x1e,0x0e,0x61 = rsm 0x1e,r1 +0x00,0x01,0x18,0x60 = mtsm r1 +0x00,0x20,0x50,0xa2 = ldsid (sr1,r1),rp +0x00,0x00,0x58,0x20 = mtsp flags,sr1 +0x00,0x00,0x44,0xa0 = mfsp sr1,flags +0x00,0x00,0x18,0x40 = mtctl flags,rctr +0x00,0x00,0x18,0x40 = mtctl flags,rctr \ No newline at end of file diff --git a/suite/capstone_get_setup.c b/suite/capstone_get_setup.c index 2d3f6a6bb..d3154ad28 100644 --- a/suite/capstone_get_setup.c +++ b/suite/capstone_get_setup.c @@ -76,6 +76,9 @@ int main() if (cs_support(CS_ARCH_ALPHA)) { printf("alpha=1 "); } + if (cs_support(CS_ARCH_HPPA)) { + printf("hppa=1 "); + } printf("\n"); return 0; diff --git a/suite/cstest/include/factory.h b/suite/cstest/include/factory.h index 09906b8c8..0752ff077 100644 --- a/suite/cstest/include/factory.h +++ b/suite/cstest/include/factory.h @@ -25,5 +25,6 @@ char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_alpha(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_hppa(csh *handle, cs_mode mode, cs_insn *ins); #endif /* FACTORY_H */ diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c index 16027af0d..1cb8ae5cf 100644 --- a/suite/cstest/src/capstone_test.c +++ b/suite/cstest/src/capstone_test.c @@ -198,6 +198,9 @@ int set_function(int arch) case CS_ARCH_ALPHA: function = get_detail_alpha; break; + case CS_ARCH_HPPA: + function = get_detail_hppa; + break; default: return -1; } diff --git a/suite/cstest/src/hppa_detail.c b/suite/cstest/src/hppa_detail.c new file mode 100644 index 000000000..38bc762c0 --- /dev/null +++ b/suite/cstest/src/hppa_detail.c @@ -0,0 +1,96 @@ +/* Capstone testing regression */ +/* By Dmitry Sibirtsev , 2023 */ + +#include "factory.h" + +char *get_detail_hppa(csh *p_handle, cs_mode mode, cs_insn *ins) +{ + cs_hppa *hppa; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + char *result; + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + csh handle = *p_handle; + + hppa = &(ins->detail->hppa); + + if (hppa->op_count) + add_str(&result, "\top_count: %u\n", hppa->op_count); + + for (i = 0; i < hppa->op_count; i++) { + cs_hppa_op *op = &(hppa->operands[i]); + switch ((int)op->type) { + default: + break; + case HPPA_OP_REG: + add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_IMM: + add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", + i, op->imm); + break; + case HPPA_OP_IDX_REG: + add_str(&result, + "\t\toperands[%u].type: IDX_REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_DISP: + add_str(&result, "\t\toperands[%u].type: DISP = 0x%x\n", + i, op->imm); + break; + case HPPA_OP_MEM: + add_str(&result, "\t\toperands[%u].type: MEM\n", i); + if (op->mem.space != HPPA_OP_INVALID) { + add_str(&result, + "\t\t\toperands[%u].mem.space: REG = %s\n", + i, cs_reg_name(handle, op->mem.space)); + } + add_str(&result, + "\t\t\toperands[%u].mem.base: REG = %s\n", i, + cs_reg_name(handle, op->mem.base)); + break; + case HPPA_OP_TARGET: + add_str(&result, "\t\toperands[%u].type: ", i); + if (op->imm >= 0x8000000000000000) + add_str(&result, "TARGET = -0x%lx\n", -op->imm); + else + add_str(&result, "TARGET = 0x%lx\n", op->imm); + break; + } + + // Print out all registers accessed by this instruction (either implicit or + // explicit) + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, "\tRegisters read:"); + for (i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_read[i])); + } + add_str(&result, "\n"); + } + + if (regs_write_count) { + add_str(&result, "\tRegisters modified:"); + for (i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_write[i])); + } + add_str(&result, "\n"); + } + } + } + + return result; +} diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c index a4a681f2f..0a02449ec 100644 --- a/suite/cstest/src/main.c +++ b/suite/cstest/src/main.c @@ -22,6 +22,7 @@ static single_dict arches[] = { {"CS_ARCH_RISCV", CS_ARCH_RISCV}, {"CS_ARCH_TRICORE", CS_ARCH_TRICORE}, {"CS_ARCH_ALPHA", CS_ARCH_ALPHA}, + {"CS_ARCH_HPPA", CS_ARCH_HPPA}, }; static single_dict modes[] = { @@ -71,6 +72,9 @@ static single_dict arches[] = { {"CS_MODE_TRICORE_160", CS_MODE_TRICORE_160}, {"CS_MODE_TRICORE_161", CS_MODE_TRICORE_161}, {"CS_MODE_TRICORE_162", CS_MODE_TRICORE_162}, + {"CS_MODE_HPPA_20", CS_MODE_HPPA_20}, + {"CS_MODE_HPPA_20W", CS_MODE_HPPA_20W}, + {"CS_MODE_HPPA_11", CS_MODE_HPPA_11}, }; static double_dict options[] = { @@ -127,6 +131,9 @@ static single_dict arches[] = { {"CS_MODE_TRICORE_161", CS_OPT_MODE, CS_MODE_TRICORE_161}, {"CS_MODE_TRICORE_162", CS_OPT_MODE, CS_MODE_TRICORE_162}, {"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON}, + {"CS_MODE_HPPA_20", CS_OPT_MODE, CS_MODE_HPPA_20}, + {"CS_MODE_HPPA_20W", CS_OPT_MODE, CS_MODE_HPPA_20W}, + {"CS_MODE_HPPA_11", CS_OPT_MODE, CS_MODE_HPPA_11}, }; static int counter; diff --git a/suite/test_c.sh b/suite/test_c.sh index eacbf3b95..3ba937650 100755 --- a/suite/test_c.sh +++ b/suite/test_c.sh @@ -24,4 +24,5 @@ ../tests/test_winkernel > /tmp/$1 ../tests/test_x86 > /tmp/$1 ../tests/test_xcore > /tmp/$1 -../tests/test_alpha > /tmp/$1 \ No newline at end of file +../tests/test_alpha > /tmp/$1 +../tests/test_hppa > /tmp/$1 \ No newline at end of file diff --git a/suite/test_corpus.py b/suite/test_corpus.py index c74c97193..8d7daf40b 100755 --- a/suite/test_corpus.py +++ b/suite/test_corpus.py @@ -34,6 +34,7 @@ def test_file(fname): "CS_ARCH_RISCV": CS_ARCH_RISCV, "CS_ARCH_TRICORE": CS_ARCH_TRICORE, "CS_ARCH_ALPHA": CS_ARCH_ALPHA, + "CS_ARCH_HPPA": CS_ARCH_HPPA, } modes = { @@ -71,6 +72,10 @@ def test_file(fname): "CS_MODE_TRICORE_161": CS_MODE_TRICORE_161, "CS_MODE_TRICORE_162": CS_MODE_TRICORE_162, "CS_MODE_BIG_ENDIAN+CS_MODE_QPX": CS_MODE_BIG_ENDIAN+CS_MODE_QPX, + "CS_MODE_HPPA_11": CS_MODE_HPPA_11, + "CS_MODE_HPPA_20": CS_MODE_HPPA_20, + "CS_MODE_HPPA_20W": CS_MODE_HPPA_20W, + } mc_modes = { @@ -118,6 +123,8 @@ def test_file(fname): ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54, ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55, ("CS_ARCH_ALPHA", "CS_MODE_BIG_ENDIAN"): 56, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58, } #if not option in ('', 'None'): diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py index b3d10f483..f7a2f2937 100755 --- a/suite/test_corpus3.py +++ b/suite/test_corpus3.py @@ -44,6 +44,7 @@ def test_file(fname): "CS_ARCH_RISCV": CS_ARCH_RISCV, "CS_ARCH_TRICORE": CS_ARCH_TRICORE, "CS_ARCH_ALPHA": CS_ARCH_ALPHA, + "CS_ARCH_HPPA": CS_ARCH_HPPA, } modes = { @@ -81,6 +82,9 @@ def test_file(fname): "CS_MODE_TRICORE_161": CS_MODE_TRICORE_161, "CS_MODE_TRICORE_162": CS_MODE_TRICORE_162, "CS_MODE_BIG_ENDIAN+CS_MODE_QPX": CS_MODE_BIG_ENDIAN+CS_MODE_QPX, + "CS_MODE_HPPA_11": CS_MODE_HPPA_11, + "CS_MODE_HPPA_20": CS_MODE_HPPA_20, + "CS_MODE_HPPA_20W": CS_MODE_HPPA_20W, } mc_modes = { @@ -128,6 +132,8 @@ def test_file(fname): ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54, ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55, ("CS_ARCH_ALPHA", "CS_MODE_BIG_ENDIAN"): 56, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58, } # if not option in ('', 'None'): diff --git a/suite/test_python.sh b/suite/test_python.sh index e95aa31a8..5445eb227 100755 --- a/suite/test_python.sh +++ b/suite/test_python.sh @@ -11,4 +11,5 @@ ../bindings/python/test_ppc.py >> /tmp/$1 ../bindings/python/test_sparc.py >> /tmp/$1 ../bindings/python/test_x86.py >> /tmp/$1 -../bindings/python/test_alpha.py >> /tmp/$1 \ No newline at end of file +../bindings/python/test_alpha.py >> /tmp/$1 +../bindings/python/test_hppa.py >> /tmp/$1 \ No newline at end of file diff --git a/tests/Makefile b/tests/Makefile index f01ff6fc9..9d44f09cb 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -141,6 +141,10 @@ ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_ALPHA SOURCES += test_alpha.c endif +ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_HPPA +SOURCES += test_hppa.c +endif OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) diff --git a/tests/test_all.sh b/tests/test_all.sh index 905d84e5a..1ff49959b 100644 --- a/tests/test_all.sh +++ b/tests/test_all.sh @@ -19,4 +19,5 @@ ./test_winkernel ./test_x86 ./test_xcore -./test_alpha \ No newline at end of file +./test_alpha +./test_hppa \ No newline at end of file diff --git a/tests/test_alpha.c b/tests/test_alpha.c index 7edc559bd..0206f25f6 100644 --- a/tests/test_alpha.c +++ b/tests/test_alpha.c @@ -1,5 +1,5 @@ /* Capstone Disassembler Engine */ -/* By Dmitry Sibirtsev , 2013-2019 */ +/* By Dmitry Sibirtsev , 2023 */ #include diff --git a/tests/test_basic.c b/tests/test_basic.c index db57f0002..dbd37a9ff 100644 --- a/tests/test_basic.c +++ b/tests/test_basic.c @@ -94,6 +94,12 @@ static void test() #ifdef CAPSTONE_HAS_ALPHA #define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" #define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" +#endif +#ifdef CAPSTONE_HAS_HPPA +#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" #endif struct platform { @@ -383,6 +389,36 @@ static void test() sizeof(ALPHA_CODE) - 1, "Alpha (Big-endian)" }, +#endif +#ifdef CAPSTONE_HAS_HPPA + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)" + }, #endif }; diff --git a/tests/test_detail.c b/tests/test_detail.c index 07a2ee5f8..ab8de7e1f 100644 --- a/tests/test_detail.c +++ b/tests/test_detail.c @@ -81,6 +81,12 @@ static void test() #ifdef CAPSTONE_HAS_ALPHA #define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" #define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" +#endif +#ifdef CAPSTONE_HAS_HPPA +#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" #endif struct platform platforms[] = { @@ -300,6 +306,36 @@ static void test() sizeof(ALPHA_CODE) - 1, "Alpha (Big-endian)" }, +#endif +#ifdef CAPSTONE_HAS_HPPA + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)" + }, #endif }; diff --git a/tests/test_hppa.c b/tests/test_hppa.c new file mode 100644 index 000000000..15a017904 --- /dev/null +++ b/tests/test_hppa.c @@ -0,0 +1,186 @@ +/* Capstone Disassembler Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + char *comment; +}; + +static csh handle; + +static void print_string_hex(char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_hppa *hppa; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + hppa = &(ins->detail->hppa); + if (hppa->op_count) + printf("\top_count: %u\n", hppa->op_count); + + for (i = 0; i < hppa->op_count; i++) { + cs_hppa_op *op = &(hppa->operands[i]); + switch ((int)op->type) { + default: + break; + case HPPA_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", + i, op->imm); + break; + case HPPA_OP_IDX_REG: + printf("\t\toperands[%u].type: IDX_REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_DISP: + printf("\t\toperands[%u].type: DISP = 0x%" PRIx64 "\n", + i, op->imm); + break; + case HPPA_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.space != HPPA_OP_INVALID) { + printf("\t\t\toperands[%u].mem.space: REG = %s\n", + i, cs_reg_name(handle, op->mem.space)); + } + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, + cs_reg_name(handle, op->mem.base)); + break; + case HPPA_OP_TARGET: + printf("\t\toperands[%u].type: ", i); + if (op->imm >= 0x8000000000000000) + printf("TARGET = -0x%" PRIx64 "\n", -op->imm); + else + printf("TARGET = 0x%" PRIx64 "\n", op->imm); + break; + } + } + + printf("\n"); +} + +static void test() +{ +#define HPPA_20_CODE_BE \ + "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE \ + "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE \ + "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE \ + "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" + + struct platform platforms[] = { + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char *)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)", + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char *)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)", + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char *)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)", + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char *)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { + cs_err err = + cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", + err); + continue; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, + address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, + platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", + insn[j].address, insn[j].mnemonic, + insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", + insn[j - 1].address + insn[j - 1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, + platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/tests/test_iter.c b/tests/test_iter.c index 0647cbffc..172d2c6a3 100644 --- a/tests/test_iter.c +++ b/tests/test_iter.c @@ -84,6 +84,13 @@ static void test() #define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" #endif +#ifdef CAPSTONE_HAS_HPPA +#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" +#endif + struct platform platforms[] = { #ifdef CAPSTONE_HAS_X86 { @@ -282,6 +289,36 @@ struct platform platforms[] = { sizeof(ALPHA_CODE) - 1, "Alpha (Big-endian)" }, +#endif +#ifdef CAPSTONE_HAS_HPPA + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)" + }, #endif };