diff --git a/include/capstone.h b/include/capstone.h
index 9d7ee157b..183f29d88 100644
--- a/include/capstone.h
+++ b/include/capstone.h
@@ -73,22 +73,22 @@ typedef enum cs_arch {
 
 // Mode type
 typedef enum cs_mode {
-	CS_MODE_LITTLE_ENDIAN = 0,	// little endian mode (default mode)
+	CS_MODE_LITTLE_ENDIAN = 0,	// little-endian mode (default mode)
 	CS_MODE_ARM = 0,	// 32-bit ARM
-	CS_MODE_16 = 1 << 1,	// 16-bit mode
-	CS_MODE_32 = 1 << 2,	// 32-bit mode.
-	CS_MODE_64 = 1 << 3,	// 64-bit mode.
+	CS_MODE_16 = 1 << 1,	// 16-bit mode (X86)
+	CS_MODE_32 = 1 << 2,	// 32-bit mode (X86)
+	CS_MODE_64 = 1 << 3,	// 64-bit mode (X86, PPC)
 	CS_MODE_THUMB = 1 << 4,	// ARM's Thumb mode, including Thumb-2
 	CS_MODE_MCLASS = 1 << 5,	// ARM's Cortex-M series
 	CS_MODE_V8 = 1 << 6,	// ARMv8 A32 encodings for ARM
-	CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS architecture)
+	CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS)
 	CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
 	CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
-	CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS arch)
-	CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc architecture)
-	CS_MODE_BIG_ENDIAN = 1 << 31,	// big endian mode
-	CS_MODE_MIPS32 = CS_MODE_32,	// Mips32 ISA
-	CS_MODE_MIPS64 = CS_MODE_64,	// Mips64 ISA.
+	CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS)
+	CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc)
+	CS_MODE_BIG_ENDIAN = 1 << 31,	// big-endian mode
+	CS_MODE_MIPS32 = CS_MODE_32,	// Mips32 ISA (Mips)
+	CS_MODE_MIPS64 = CS_MODE_64,	// Mips64 ISA (Mips)
 } cs_mode;
 
 typedef void* (*cs_malloc_t)(size_t size);