From cd282ef59324e28f1d59bbe12a0b2af535cc617f Mon Sep 17 00:00:00 2001
From: Rot127 <45763064+Rot127@users.noreply.github.com>
Date: Mon, 3 Mar 2025 03:59:24 +0000
Subject: [PATCH] Update operand type enums of all arch modules to the one in
 `capstone.h` (#2633)

* Set all operand types to the main CS_OP_ types from capstone.h.

* Add test cases from issue.
---
 bindings/java/capstone/M680x_const.java      | 17 ++++-----
 bindings/java/capstone/M68k_const.java       | 19 +++++-----
 bindings/java/capstone/Mips_const.java       |  9 ++---
 bindings/java/capstone/Sparc_const.java      |  9 ++---
 bindings/java/capstone/TMS320C64x_const.java | 11 +++---
 bindings/java/capstone/Wasm_const.java       | 19 +++++-----
 bindings/java/capstone/X86_const.java        |  9 ++---
 bindings/java/capstone/Xcore_const.java      |  9 ++---
 bindings/ocaml/m680x_const.ml                | 17 ++++-----
 bindings/ocaml/m68k_const.ml                 | 19 +++++-----
 bindings/ocaml/mips_const.ml                 |  9 ++---
 bindings/ocaml/sparc_const.ml                |  9 ++---
 bindings/ocaml/tms320c64x_const.ml           | 11 +++---
 bindings/ocaml/wasm_const.ml                 | 19 +++++-----
 bindings/ocaml/x86_const.ml                  |  9 ++---
 bindings/ocaml/xcore_const.ml                |  9 ++---
 bindings/python/capstone/bpf_const.py        | 17 ++++-----
 bindings/python/capstone/hppa_const.py       | 15 ++++----
 bindings/python/capstone/m680x_const.py      | 17 ++++-----
 bindings/python/capstone/m68k_const.py       | 19 +++++-----
 bindings/python/capstone/mips_const.py       |  9 ++---
 bindings/python/capstone/mos65xx_const.py    |  9 ++---
 bindings/python/capstone/riscv_const.py      |  9 ++---
 bindings/python/capstone/sh_const.py         |  9 ++---
 bindings/python/capstone/sparc_const.py      |  9 ++---
 bindings/python/capstone/tms320c64x_const.py | 11 +++---
 bindings/python/capstone/wasm_const.py       | 19 +++++-----
 bindings/python/capstone/x86_const.py        |  9 ++---
 bindings/python/capstone/xcore_const.py      |  9 ++---
 bindings/python/capstone/xtensa_const.py     |  2 +-
 include/capstone/bpf.h                       | 18 ++++-----
 include/capstone/hppa.h                      | 16 ++++----
 include/capstone/m680x.h                     | 17 +++++----
 include/capstone/m68k.h                      | 19 +++++-----
 include/capstone/mips.h                      |  9 +++--
 include/capstone/mos65xx.h                   |  9 +++--
 include/capstone/riscv.h                     |  9 +++--
 include/capstone/sh.h                        |  9 +++--
 include/capstone/sparc.h                     |  9 +++--
 include/capstone/tms320c64x.h                | 11 +++---
 include/capstone/wasm.h                      | 19 +++++-----
 include/capstone/x86.h                       |  9 +++--
 include/capstone/xcore.h                     |  9 +++--
 include/capstone/xtensa.h                    |  2 +-
 suite/cstest/include/test_mapping.h          | 21 +++++++++++
 tests/issues/issues.yaml                     | 39 +++++++++++++++++++-
 46 files changed, 315 insertions(+), 277 deletions(-)

diff --git a/bindings/java/capstone/M680x_const.java b/bindings/java/capstone/M680x_const.java
index 29eca2838..656971478 100644
--- a/bindings/java/capstone/M680x_const.java
+++ b/bindings/java/capstone/M680x_const.java
@@ -27,15 +27,14 @@ public class M680x_const {
 	public static final int M680X_REG_TMP2 = 20;
 	public static final int M680X_REG_TMP3 = 21;
 	public static final int M680X_REG_ENDING = 22;
-
-	public static final int M680X_OP_INVALID = 0;
-	public static final int M680X_OP_REGISTER = 1;
-	public static final int M680X_OP_IMMEDIATE = 2;
-	public static final int M680X_OP_INDEXED = 3;
-	public static final int M680X_OP_EXTENDED = 4;
-	public static final int M680X_OP_DIRECT = 5;
-	public static final int M680X_OP_RELATIVE = 6;
-	public static final int M680X_OP_CONSTANT = 7;
+	public static final int M680X_OP_INVALID = CS_OP_INVALID;
+	public static final int M680X_OP_REGISTER = CS_OP_REG;
+	public static final int M680X_OP_IMMEDIATE = CS_OP_IMM;
+	public static final int M680X_OP_INDEXED = CS_OP_SPECIAL+0;
+	public static final int M680X_OP_EXTENDED = CS_OP_SPECIAL+1;
+	public static final int M680X_OP_DIRECT = CS_OP_SPECIAL+2;
+	public static final int M680X_OP_RELATIVE = CS_OP_SPECIAL+3;
+	public static final int M680X_OP_CONSTANT = CS_OP_SPECIAL+4;
 
 	public static final int M680X_OFFSET_NONE = 0;
 	public static final int M680X_OFFSET_BITS_5 = 5;
diff --git a/bindings/java/capstone/M68k_const.java b/bindings/java/capstone/M68k_const.java
index 74cd8f9b9..d965b8928 100644
--- a/bindings/java/capstone/M68k_const.java
+++ b/bindings/java/capstone/M68k_const.java
@@ -73,16 +73,15 @@ public class M68k_const {
 	public static final int M68K_AM_ABSOLUTE_DATA_LONG = 17;
 	public static final int M68K_AM_IMMEDIATE = 18;
 	public static final int M68K_AM_BRANCH_DISPLACEMENT = 19;
-
-	public static final int M68K_OP_INVALID = 0;
-	public static final int M68K_OP_REG = 1;
-	public static final int M68K_OP_IMM = 2;
-	public static final int M68K_OP_MEM = 3;
-	public static final int M68K_OP_FP_SINGLE = 4;
-	public static final int M68K_OP_FP_DOUBLE = 5;
-	public static final int M68K_OP_REG_BITS = 6;
-	public static final int M68K_OP_REG_PAIR = 7;
-	public static final int M68K_OP_BR_DISP = 8;
+	public static final int M68K_OP_INVALID = CS_OP_INVALID;
+	public static final int M68K_OP_REG = CS_OP_REG;
+	public static final int M68K_OP_IMM = CS_OP_IMM;
+	public static final int M68K_OP_FP_SINGLE = CS_OP_SPECIAL+0;
+	public static final int M68K_OP_FP_DOUBLE = CS_OP_SPECIAL+1;
+	public static final int M68K_OP_REG_BITS = CS_OP_SPECIAL+2;
+	public static final int M68K_OP_REG_PAIR = CS_OP_SPECIAL+3;
+	public static final int M68K_OP_BR_DISP = CS_OP_SPECIAL+4;
+	public static final int M68K_OP_MEM = CS_OP_MEM;
 
 	public static final int M68K_OP_BR_DISP_SIZE_INVALID = 0;
 	public static final int M68K_OP_BR_DISP_SIZE_BYTE = 1;
diff --git a/bindings/java/capstone/Mips_const.java b/bindings/java/capstone/Mips_const.java
index 21c2c3696..b0321f88a 100644
--- a/bindings/java/capstone/Mips_const.java
+++ b/bindings/java/capstone/Mips_const.java
@@ -2,11 +2,10 @@
 package capstone;
 
 public class Mips_const {
-
-	public static final int MIPS_OP_INVALID = 0;
-	public static final int MIPS_OP_REG = 1;
-	public static final int MIPS_OP_IMM = 2;
-	public static final int MIPS_OP_MEM = 3;
+	public static final int MIPS_OP_INVALID = CS_OP_INVALID;
+	public static final int MIPS_OP_REG = CS_OP_REG;
+	public static final int MIPS_OP_IMM = CS_OP_IMM;
+	public static final int MIPS_OP_MEM = CS_OP_MEM;
 
 	public static final int MIPS_REG_INVALID = 0;
 	public static final int MIPS_REG_AT = 1;
diff --git a/bindings/java/capstone/Sparc_const.java b/bindings/java/capstone/Sparc_const.java
index fabd63571..8d2fe56a3 100644
--- a/bindings/java/capstone/Sparc_const.java
+++ b/bindings/java/capstone/Sparc_const.java
@@ -43,11 +43,10 @@ public class Sparc_const {
 	public static final int SPARC_HINT_PN = 1<<2;
 	public static final int SPARC_HINT_A_PN = SPARC_HINT_A|SPARC_HINT_PN;
 	public static final int SPARC_HINT_A_PT = SPARC_HINT_A|SPARC_HINT_PT;
-
-	public static final int SPARC_OP_INVALID = 0;
-	public static final int SPARC_OP_REG = 1;
-	public static final int SPARC_OP_IMM = 2;
-	public static final int SPARC_OP_MEM = 3;
+	public static final int SPARC_OP_INVALID = CS_OP_INVALID;
+	public static final int SPARC_OP_REG = CS_OP_REG;
+	public static final int SPARC_OP_IMM = CS_OP_IMM;
+	public static final int SPARC_OP_MEM = CS_OP_MEM;
 
 	public static final int SPARC_REG_INVALID = 0;
 	public static final int SPARC_REG_F0 = 1;
diff --git a/bindings/java/capstone/TMS320C64x_const.java b/bindings/java/capstone/TMS320C64x_const.java
index 6e48b41ce..dbbecd3b8 100644
--- a/bindings/java/capstone/TMS320C64x_const.java
+++ b/bindings/java/capstone/TMS320C64x_const.java
@@ -2,12 +2,11 @@
 package capstone;
 
 public class TMS320C64x_const {
-
-	public static final int TMS320C64X_OP_INVALID = 0;
-	public static final int TMS320C64X_OP_REG = 1;
-	public static final int TMS320C64X_OP_IMM = 2;
-	public static final int TMS320C64X_OP_MEM = 3;
-	public static final int TMS320C64X_OP_REGPAIR = 64;
+	public static final int TMS320C64X_OP_INVALID = CS_OP_INVALID;
+	public static final int TMS320C64X_OP_REG = CS_OP_REG;
+	public static final int TMS320C64X_OP_IMM = CS_OP_IMM;
+	public static final int TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL+0;
+	public static final int TMS320C64X_OP_MEM = CS_OP_MEM;
 
 	public static final int TMS320C64X_MEM_DISP_INVALID = 0;
 	public static final int TMS320C64X_MEM_DISP_CONSTANT = 1;
diff --git a/bindings/java/capstone/Wasm_const.java b/bindings/java/capstone/Wasm_const.java
index 4b28c672b..4bfa2486c 100644
--- a/bindings/java/capstone/Wasm_const.java
+++ b/bindings/java/capstone/Wasm_const.java
@@ -2,16 +2,15 @@
 package capstone;
 
 public class Wasm_const {
-
-	public static final int WASM_OP_INVALID = 0;
-	public static final int WASM_OP_NONE = 1;
-	public static final int WASM_OP_INT7 = 2;
-	public static final int WASM_OP_VARUINT32 = 3;
-	public static final int WASM_OP_VARUINT64 = 4;
-	public static final int WASM_OP_UINT32 = 5;
-	public static final int WASM_OP_UINT64 = 6;
-	public static final int WASM_OP_IMM = 7;
-	public static final int WASM_OP_BRTABLE = 8;
+	public static final int WASM_OP_INVALID = CS_OP_INVALID;
+	public static final int WASM_OP_IMM = CS_OP_IMM;
+	public static final int WASM_OP_NONE = CS_OP_SPECIAL+0;
+	public static final int WASM_OP_INT7 = CS_OP_SPECIAL+1;
+	public static final int WASM_OP_VARUINT32 = CS_OP_SPECIAL+2;
+	public static final int WASM_OP_VARUINT64 = CS_OP_SPECIAL+3;
+	public static final int WASM_OP_UINT32 = CS_OP_SPECIAL+4;
+	public static final int WASM_OP_UINT64 = CS_OP_SPECIAL+5;
+	public static final int WASM_OP_BRTABLE = CS_OP_SPECIAL+6;
 	public static final int WASM_INS_UNREACHABLE = 0x0;
 	public static final int WASM_INS_NOP = 0x1;
 	public static final int WASM_INS_BLOCK = 0x2;
diff --git a/bindings/java/capstone/X86_const.java b/bindings/java/capstone/X86_const.java
index 6f7561f05..32e645fd8 100644
--- a/bindings/java/capstone/X86_const.java
+++ b/bindings/java/capstone/X86_const.java
@@ -329,11 +329,10 @@ public class X86_const {
 	public static final int X86_FPU_FLAGS_TEST_C1 = 1<<17;
 	public static final int X86_FPU_FLAGS_TEST_C2 = 1<<18;
 	public static final int X86_FPU_FLAGS_TEST_C3 = 1<<19;
-
-	public static final int X86_OP_INVALID = 0;
-	public static final int X86_OP_REG = 1;
-	public static final int X86_OP_IMM = 2;
-	public static final int X86_OP_MEM = 3;
+	public static final int X86_OP_INVALID = CS_OP_INVALID;
+	public static final int X86_OP_REG = CS_OP_REG;
+	public static final int X86_OP_IMM = CS_OP_IMM;
+	public static final int X86_OP_MEM = CS_OP_MEM;
 
 	public static final int X86_XOP_CC_INVALID = 0;
 	public static final int X86_XOP_CC_LT = 1;
diff --git a/bindings/java/capstone/Xcore_const.java b/bindings/java/capstone/Xcore_const.java
index 848e142df..695012d6e 100644
--- a/bindings/java/capstone/Xcore_const.java
+++ b/bindings/java/capstone/Xcore_const.java
@@ -2,11 +2,10 @@
 package capstone;
 
 public class Xcore_const {
-
-	public static final int XCORE_OP_INVALID = 0;
-	public static final int XCORE_OP_REG = 1;
-	public static final int XCORE_OP_IMM = 2;
-	public static final int XCORE_OP_MEM = 3;
+	public static final int XCORE_OP_INVALID = CS_OP_INVALID;
+	public static final int XCORE_OP_REG = CS_OP_REG;
+	public static final int XCORE_OP_IMM = CS_OP_IMM;
+	public static final int XCORE_OP_MEM = CS_OP_MEM;
 
 	public static final int XCORE_REG_INVALID = 0;
 	public static final int XCORE_REG_CP = 1;
diff --git a/bindings/ocaml/m680x_const.ml b/bindings/ocaml/m680x_const.ml
index 5e887109f..f9df6285e 100644
--- a/bindings/ocaml/m680x_const.ml
+++ b/bindings/ocaml/m680x_const.ml
@@ -24,15 +24,14 @@ let _M680X_REG_PC = 19;;
 let _M680X_REG_TMP2 = 20;;
 let _M680X_REG_TMP3 = 21;;
 let _M680X_REG_ENDING = 22;;
-
-let _M680X_OP_INVALID = 0;;
-let _M680X_OP_REGISTER = 1;;
-let _M680X_OP_IMMEDIATE = 2;;
-let _M680X_OP_INDEXED = 3;;
-let _M680X_OP_EXTENDED = 4;;
-let _M680X_OP_DIRECT = 5;;
-let _M680X_OP_RELATIVE = 6;;
-let _M680X_OP_CONSTANT = 7;;
+let _M680X_OP_INVALID = _CS_OP_INVALID;;
+let _M680X_OP_REGISTER = _CS_OP_REG;;
+let _M680X_OP_IMMEDIATE = _CS_OP_IMM;;
+let _M680X_OP_INDEXED = _CS_OP_SPECIAL+0;;
+let _M680X_OP_EXTENDED = _CS_OP_SPECIAL+1;;
+let _M680X_OP_DIRECT = _CS_OP_SPECIAL+2;;
+let _M680X_OP_RELATIVE = _CS_OP_SPECIAL+3;;
+let _M680X_OP_CONSTANT = _CS_OP_SPECIAL+4;;
 
 let _M680X_OFFSET_NONE = 0;;
 let _M680X_OFFSET_BITS_5 = 5;;
diff --git a/bindings/ocaml/m68k_const.ml b/bindings/ocaml/m68k_const.ml
index f060d4ff5..d9ff737b3 100644
--- a/bindings/ocaml/m68k_const.ml
+++ b/bindings/ocaml/m68k_const.ml
@@ -70,16 +70,15 @@ let _M68K_AM_ABSOLUTE_DATA_SHORT = 16;;
 let _M68K_AM_ABSOLUTE_DATA_LONG = 17;;
 let _M68K_AM_IMMEDIATE = 18;;
 let _M68K_AM_BRANCH_DISPLACEMENT = 19;;
-
-let _M68K_OP_INVALID = 0;;
-let _M68K_OP_REG = 1;;
-let _M68K_OP_IMM = 2;;
-let _M68K_OP_MEM = 3;;
-let _M68K_OP_FP_SINGLE = 4;;
-let _M68K_OP_FP_DOUBLE = 5;;
-let _M68K_OP_REG_BITS = 6;;
-let _M68K_OP_REG_PAIR = 7;;
-let _M68K_OP_BR_DISP = 8;;
+let _M68K_OP_INVALID = _CS_OP_INVALID;;
+let _M68K_OP_REG = _CS_OP_REG;;
+let _M68K_OP_IMM = _CS_OP_IMM;;
+let _M68K_OP_FP_SINGLE = _CS_OP_SPECIAL+0;;
+let _M68K_OP_FP_DOUBLE = _CS_OP_SPECIAL+1;;
+let _M68K_OP_REG_BITS = _CS_OP_SPECIAL+2;;
+let _M68K_OP_REG_PAIR = _CS_OP_SPECIAL+3;;
+let _M68K_OP_BR_DISP = _CS_OP_SPECIAL+4;;
+let _M68K_OP_MEM = _CS_OP_MEM;;
 
 let _M68K_OP_BR_DISP_SIZE_INVALID = 0;;
 let _M68K_OP_BR_DISP_SIZE_BYTE = 1;;
diff --git a/bindings/ocaml/mips_const.ml b/bindings/ocaml/mips_const.ml
index 1f6ae1616..cdbbb1318 100644
--- a/bindings/ocaml/mips_const.ml
+++ b/bindings/ocaml/mips_const.ml
@@ -1,9 +1,8 @@
 (* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.ml] *)
-
-let _MIPS_OP_INVALID = 0;;
-let _MIPS_OP_REG = 1;;
-let _MIPS_OP_IMM = 2;;
-let _MIPS_OP_MEM = 3;;
+let _MIPS_OP_INVALID = _CS_OP_INVALID;;
+let _MIPS_OP_REG = _CS_OP_REG;;
+let _MIPS_OP_IMM = _CS_OP_IMM;;
+let _MIPS_OP_MEM = _CS_OP_MEM;;
 
 let _MIPS_REG_INVALID = 0;;
 let _MIPS_REG_AT = 1;;
diff --git a/bindings/ocaml/sparc_const.ml b/bindings/ocaml/sparc_const.ml
index fd8c7cea8..272b5d5cd 100644
--- a/bindings/ocaml/sparc_const.ml
+++ b/bindings/ocaml/sparc_const.ml
@@ -40,11 +40,10 @@ let _SPARC_HINT_PT = 1 lsl 1;;
 let _SPARC_HINT_PN = 1 lsl 2;;
 let _SPARC_HINT_A_PN = _SPARC_HINT_A lor SPARC_HINT_PN;;
 let _SPARC_HINT_A_PT = _SPARC_HINT_A lor SPARC_HINT_PT;;
-
-let _SPARC_OP_INVALID = 0;;
-let _SPARC_OP_REG = 1;;
-let _SPARC_OP_IMM = 2;;
-let _SPARC_OP_MEM = 3;;
+let _SPARC_OP_INVALID = _CS_OP_INVALID;;
+let _SPARC_OP_REG = _CS_OP_REG;;
+let _SPARC_OP_IMM = _CS_OP_IMM;;
+let _SPARC_OP_MEM = _CS_OP_MEM;;
 
 let _SPARC_REG_INVALID = 0;;
 let _SPARC_REG_F0 = 1;;
diff --git a/bindings/ocaml/tms320c64x_const.ml b/bindings/ocaml/tms320c64x_const.ml
index 53a4440e8..797297a3c 100644
--- a/bindings/ocaml/tms320c64x_const.ml
+++ b/bindings/ocaml/tms320c64x_const.ml
@@ -1,10 +1,9 @@
 (* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.ml] *)
-
-let _TMS320C64X_OP_INVALID = 0;;
-let _TMS320C64X_OP_REG = 1;;
-let _TMS320C64X_OP_IMM = 2;;
-let _TMS320C64X_OP_MEM = 3;;
-let _TMS320C64X_OP_REGPAIR = 64;;
+let _TMS320C64X_OP_INVALID = _CS_OP_INVALID;;
+let _TMS320C64X_OP_REG = _CS_OP_REG;;
+let _TMS320C64X_OP_IMM = _CS_OP_IMM;;
+let _TMS320C64X_OP_REGPAIR = _CS_OP_SPECIAL+0;;
+let _TMS320C64X_OP_MEM = _CS_OP_MEM;;
 
 let _TMS320C64X_MEM_DISP_INVALID = 0;;
 let _TMS320C64X_MEM_DISP_CONSTANT = 1;;
diff --git a/bindings/ocaml/wasm_const.ml b/bindings/ocaml/wasm_const.ml
index 760917dc1..5aa2d6ad1 100644
--- a/bindings/ocaml/wasm_const.ml
+++ b/bindings/ocaml/wasm_const.ml
@@ -1,14 +1,13 @@
 (* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.ml] *)
-
-let _WASM_OP_INVALID = 0;;
-let _WASM_OP_NONE = 1;;
-let _WASM_OP_INT7 = 2;;
-let _WASM_OP_VARUINT32 = 3;;
-let _WASM_OP_VARUINT64 = 4;;
-let _WASM_OP_UINT32 = 5;;
-let _WASM_OP_UINT64 = 6;;
-let _WASM_OP_IMM = 7;;
-let _WASM_OP_BRTABLE = 8;;
+let _WASM_OP_INVALID = _CS_OP_INVALID;;
+let _WASM_OP_IMM = _CS_OP_IMM;;
+let _WASM_OP_NONE = _CS_OP_SPECIAL+0;;
+let _WASM_OP_INT7 = _CS_OP_SPECIAL+1;;
+let _WASM_OP_VARUINT32 = _CS_OP_SPECIAL+2;;
+let _WASM_OP_VARUINT64 = _CS_OP_SPECIAL+3;;
+let _WASM_OP_UINT32 = _CS_OP_SPECIAL+4;;
+let _WASM_OP_UINT64 = _CS_OP_SPECIAL+5;;
+let _WASM_OP_BRTABLE = _CS_OP_SPECIAL+6;;
 let _WASM_INS_UNREACHABLE = 0x0;;
 let _WASM_INS_NOP = 0x1;;
 let _WASM_INS_BLOCK = 0x2;;
diff --git a/bindings/ocaml/x86_const.ml b/bindings/ocaml/x86_const.ml
index 97c27aaa8..92bf37230 100644
--- a/bindings/ocaml/x86_const.ml
+++ b/bindings/ocaml/x86_const.ml
@@ -326,11 +326,10 @@ let _X86_FPU_FLAGS_TEST_C0 = 1 lsl 16;;
 let _X86_FPU_FLAGS_TEST_C1 = 1 lsl 17;;
 let _X86_FPU_FLAGS_TEST_C2 = 1 lsl 18;;
 let _X86_FPU_FLAGS_TEST_C3 = 1 lsl 19;;
-
-let _X86_OP_INVALID = 0;;
-let _X86_OP_REG = 1;;
-let _X86_OP_IMM = 2;;
-let _X86_OP_MEM = 3;;
+let _X86_OP_INVALID = _CS_OP_INVALID;;
+let _X86_OP_REG = _CS_OP_REG;;
+let _X86_OP_IMM = _CS_OP_IMM;;
+let _X86_OP_MEM = _CS_OP_MEM;;
 
 let _X86_XOP_CC_INVALID = 0;;
 let _X86_XOP_CC_LT = 1;;
diff --git a/bindings/ocaml/xcore_const.ml b/bindings/ocaml/xcore_const.ml
index f32dd4ae4..7255f462e 100644
--- a/bindings/ocaml/xcore_const.ml
+++ b/bindings/ocaml/xcore_const.ml
@@ -1,9 +1,8 @@
 (* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.ml] *)
-
-let _XCORE_OP_INVALID = 0;;
-let _XCORE_OP_REG = 1;;
-let _XCORE_OP_IMM = 2;;
-let _XCORE_OP_MEM = 3;;
+let _XCORE_OP_INVALID = _CS_OP_INVALID;;
+let _XCORE_OP_REG = _CS_OP_REG;;
+let _XCORE_OP_IMM = _CS_OP_IMM;;
+let _XCORE_OP_MEM = _CS_OP_MEM;;
 
 let _XCORE_REG_INVALID = 0;;
 let _XCORE_REG_CP = 1;;
diff --git a/bindings/python/capstone/bpf_const.py b/bindings/python/capstone/bpf_const.py
index c01ee7aa2..8e9f1cff3 100644
--- a/bindings/python/capstone/bpf_const.py
+++ b/bindings/python/capstone/bpf_const.py
@@ -1,14 +1,13 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py]
-
-BPF_OP_INVALID = 0
-BPF_OP_REG = 1
-BPF_OP_IMM = 2
-BPF_OP_OFF = 3
-BPF_OP_MEM = 4
-BPF_OP_MMEM = 5
-BPF_OP_MSH = 6
-BPF_OP_EXT = 7
+BPF_OP_INVALID = CS_OP_INVALID
+BPF_OP_REG = CS_OP_REG
+BPF_OP_IMM = CS_OP_IMM
+BPF_OP_OFF = CS_OP_SPECIAL+0
+BPF_OP_MSH = CS_OP_SPECIAL+1
+BPF_OP_EXT = CS_OP_SPECIAL+2
+BPF_OP_MMEM = CS_OP_MEM|(CS_OP_SPECIAL+3)
+BPF_OP_MEM = CS_OP_MEM
 
 BPF_REG_INVALID = 0
 BPF_REG_A = 1
diff --git a/bindings/python/capstone/hppa_const.py b/bindings/python/capstone/hppa_const.py
index 789a99a97..75ef50792 100644
--- a/bindings/python/capstone/hppa_const.py
+++ b/bindings/python/capstone/hppa_const.py
@@ -2,14 +2,13 @@ from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_S
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py]
 HPPA_STR_MODIFIER_LEN = 8
 HPPA_MAX_MODIFIERS_LEN = 5
-
-HPPA_OP_INVALID = 0
-HPPA_OP_REG = 1
-HPPA_OP_IMM = 2
-HPPA_OP_IDX_REG = 3
-HPPA_OP_DISP = 4
-HPPA_OP_MEM = 5
-HPPA_OP_TARGET = 6
+HPPA_OP_INVALID = CS_OP_INVALID
+HPPA_OP_REG = CS_OP_REG
+HPPA_OP_IMM = CS_OP_IMM
+HPPA_OP_IDX_REG = CS_OP_SPECIAL+0
+HPPA_OP_DISP = CS_OP_SPECIAL+1
+HPPA_OP_TARGET = CS_OP_SPECIAL+2
+HPPA_OP_MEM = CS_OP_MEM
 
 # HPPA registers
 
diff --git a/bindings/python/capstone/m680x_const.py b/bindings/python/capstone/m680x_const.py
index f543517cc..92884ff99 100644
--- a/bindings/python/capstone/m680x_const.py
+++ b/bindings/python/capstone/m680x_const.py
@@ -25,15 +25,14 @@ M680X_REG_PC = 19
 M680X_REG_TMP2 = 20
 M680X_REG_TMP3 = 21
 M680X_REG_ENDING = 22
-
-M680X_OP_INVALID = 0
-M680X_OP_REGISTER = 1
-M680X_OP_IMMEDIATE = 2
-M680X_OP_INDEXED = 3
-M680X_OP_EXTENDED = 4
-M680X_OP_DIRECT = 5
-M680X_OP_RELATIVE = 6
-M680X_OP_CONSTANT = 7
+M680X_OP_INVALID = CS_OP_INVALID
+M680X_OP_REGISTER = CS_OP_REG
+M680X_OP_IMMEDIATE = CS_OP_IMM
+M680X_OP_INDEXED = CS_OP_SPECIAL+0
+M680X_OP_EXTENDED = CS_OP_SPECIAL+1
+M680X_OP_DIRECT = CS_OP_SPECIAL+2
+M680X_OP_RELATIVE = CS_OP_SPECIAL+3
+M680X_OP_CONSTANT = CS_OP_SPECIAL+4
 
 M680X_OFFSET_NONE = 0
 M680X_OFFSET_BITS_5 = 5
diff --git a/bindings/python/capstone/m68k_const.py b/bindings/python/capstone/m68k_const.py
index de702afe9..7d2d6794a 100644
--- a/bindings/python/capstone/m68k_const.py
+++ b/bindings/python/capstone/m68k_const.py
@@ -71,16 +71,15 @@ M68K_AM_ABSOLUTE_DATA_SHORT = 16
 M68K_AM_ABSOLUTE_DATA_LONG = 17
 M68K_AM_IMMEDIATE = 18
 M68K_AM_BRANCH_DISPLACEMENT = 19
-
-M68K_OP_INVALID = 0
-M68K_OP_REG = 1
-M68K_OP_IMM = 2
-M68K_OP_MEM = 3
-M68K_OP_FP_SINGLE = 4
-M68K_OP_FP_DOUBLE = 5
-M68K_OP_REG_BITS = 6
-M68K_OP_REG_PAIR = 7
-M68K_OP_BR_DISP = 8
+M68K_OP_INVALID = CS_OP_INVALID
+M68K_OP_REG = CS_OP_REG
+M68K_OP_IMM = CS_OP_IMM
+M68K_OP_FP_SINGLE = CS_OP_SPECIAL+0
+M68K_OP_FP_DOUBLE = CS_OP_SPECIAL+1
+M68K_OP_REG_BITS = CS_OP_SPECIAL+2
+M68K_OP_REG_PAIR = CS_OP_SPECIAL+3
+M68K_OP_BR_DISP = CS_OP_SPECIAL+4
+M68K_OP_MEM = CS_OP_MEM
 
 M68K_OP_BR_DISP_SIZE_INVALID = 0
 M68K_OP_BR_DISP_SIZE_BYTE = 1
diff --git a/bindings/python/capstone/mips_const.py b/bindings/python/capstone/mips_const.py
index 43e3318f9..724fdaa7a 100644
--- a/bindings/python/capstone/mips_const.py
+++ b/bindings/python/capstone/mips_const.py
@@ -1,10 +1,9 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
-
-MIPS_OP_INVALID = 0
-MIPS_OP_REG = 1
-MIPS_OP_IMM = 2
-MIPS_OP_MEM = 3
+MIPS_OP_INVALID = CS_OP_INVALID
+MIPS_OP_REG = CS_OP_REG
+MIPS_OP_IMM = CS_OP_IMM
+MIPS_OP_MEM = CS_OP_MEM
 
 MIPS_REG_INVALID = 0
 MIPS_REG_AT = 1
diff --git a/bindings/python/capstone/mos65xx_const.py b/bindings/python/capstone/mos65xx_const.py
index bd1e914a7..759bd3095 100644
--- a/bindings/python/capstone/mos65xx_const.py
+++ b/bindings/python/capstone/mos65xx_const.py
@@ -146,8 +146,7 @@ MOS65XX_GRP_INT = 4
 MOS65XX_GRP_IRET = 5
 MOS65XX_GRP_BRANCH_RELATIVE = 6
 MOS65XX_GRP_ENDING = 7
-
-MOS65XX_OP_INVALID = 0
-MOS65XX_OP_REG = 1
-MOS65XX_OP_IMM = 2
-MOS65XX_OP_MEM = 3
+MOS65XX_OP_INVALID = CS_OP_INVALID
+MOS65XX_OP_REG = CS_OP_REG
+MOS65XX_OP_IMM = CS_OP_IMM
+MOS65XX_OP_MEM = CS_OP_MEM
diff --git a/bindings/python/capstone/riscv_const.py b/bindings/python/capstone/riscv_const.py
index 16aa8b634..b06510217 100644
--- a/bindings/python/capstone/riscv_const.py
+++ b/bindings/python/capstone/riscv_const.py
@@ -2,11 +2,10 @@ from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_S
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
 
 # Operand type for instruction's operands
-
-RISCV_OP_INVALID = 0
-RISCV_OP_REG = 1
-RISCV_OP_IMM = 2
-RISCV_OP_MEM = 3
+RISCV_OP_INVALID = CS_OP_INVALID
+RISCV_OP_REG = CS_OP_REG
+RISCV_OP_IMM = CS_OP_IMM
+RISCV_OP_MEM = CS_OP_MEM
 
 # RISCV registers
 
diff --git a/bindings/python/capstone/sh_const.py b/bindings/python/capstone/sh_const.py
index d604f5c1b..c24b3304d 100644
--- a/bindings/python/capstone/sh_const.py
+++ b/bindings/python/capstone/sh_const.py
@@ -124,11 +124,10 @@ SH_REG_DSP_RSVD = 119
 SH_REG_DSP_RSVE = 120
 SH_REG_DSP_RSVF = 121
 SH_REG_ENDING = 122
-
-SH_OP_INVALID = 0
-SH_OP_REG = 1
-SH_OP_IMM = 2
-SH_OP_MEM = 3
+SH_OP_INVALID = CS_OP_INVALID
+SH_OP_REG = CS_OP_REG
+SH_OP_IMM = CS_OP_IMM
+SH_OP_MEM = CS_OP_MEM
 
 SH_OP_MEM_INVALID = 0
 SH_OP_MEM_REG_IND = 1
diff --git a/bindings/python/capstone/sparc_const.py b/bindings/python/capstone/sparc_const.py
index 5f757bf14..c31d83b5a 100644
--- a/bindings/python/capstone/sparc_const.py
+++ b/bindings/python/capstone/sparc_const.py
@@ -41,11 +41,10 @@ SPARC_HINT_PT = 1<<1
 SPARC_HINT_PN = 1<<2
 SPARC_HINT_A_PN = SPARC_HINT_A|SPARC_HINT_PN
 SPARC_HINT_A_PT = SPARC_HINT_A|SPARC_HINT_PT
-
-SPARC_OP_INVALID = 0
-SPARC_OP_REG = 1
-SPARC_OP_IMM = 2
-SPARC_OP_MEM = 3
+SPARC_OP_INVALID = CS_OP_INVALID
+SPARC_OP_REG = CS_OP_REG
+SPARC_OP_IMM = CS_OP_IMM
+SPARC_OP_MEM = CS_OP_MEM
 
 SPARC_REG_INVALID = 0
 SPARC_REG_F0 = 1
diff --git a/bindings/python/capstone/tms320c64x_const.py b/bindings/python/capstone/tms320c64x_const.py
index 0ca24b315..47bce4ba1 100644
--- a/bindings/python/capstone/tms320c64x_const.py
+++ b/bindings/python/capstone/tms320c64x_const.py
@@ -1,11 +1,10 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py]
-
-TMS320C64X_OP_INVALID = 0
-TMS320C64X_OP_REG = 1
-TMS320C64X_OP_IMM = 2
-TMS320C64X_OP_MEM = 3
-TMS320C64X_OP_REGPAIR = 64
+TMS320C64X_OP_INVALID = CS_OP_INVALID
+TMS320C64X_OP_REG = CS_OP_REG
+TMS320C64X_OP_IMM = CS_OP_IMM
+TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL+0
+TMS320C64X_OP_MEM = CS_OP_MEM
 
 TMS320C64X_MEM_DISP_INVALID = 0
 TMS320C64X_MEM_DISP_CONSTANT = 1
diff --git a/bindings/python/capstone/wasm_const.py b/bindings/python/capstone/wasm_const.py
index c2d08d493..b4507e882 100644
--- a/bindings/python/capstone/wasm_const.py
+++ b/bindings/python/capstone/wasm_const.py
@@ -1,15 +1,14 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [wasm_const.py]
-
-WASM_OP_INVALID = 0
-WASM_OP_NONE = 1
-WASM_OP_INT7 = 2
-WASM_OP_VARUINT32 = 3
-WASM_OP_VARUINT64 = 4
-WASM_OP_UINT32 = 5
-WASM_OP_UINT64 = 6
-WASM_OP_IMM = 7
-WASM_OP_BRTABLE = 8
+WASM_OP_INVALID = CS_OP_INVALID
+WASM_OP_IMM = CS_OP_IMM
+WASM_OP_NONE = CS_OP_SPECIAL+0
+WASM_OP_INT7 = CS_OP_SPECIAL+1
+WASM_OP_VARUINT32 = CS_OP_SPECIAL+2
+WASM_OP_VARUINT64 = CS_OP_SPECIAL+3
+WASM_OP_UINT32 = CS_OP_SPECIAL+4
+WASM_OP_UINT64 = CS_OP_SPECIAL+5
+WASM_OP_BRTABLE = CS_OP_SPECIAL+6
 WASM_INS_UNREACHABLE = 0x0
 WASM_INS_NOP = 0x1
 WASM_INS_BLOCK = 0x2
diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py
index ef3e3acce..e0fa1892a 100644
--- a/bindings/python/capstone/x86_const.py
+++ b/bindings/python/capstone/x86_const.py
@@ -327,11 +327,10 @@ X86_FPU_FLAGS_TEST_C0 = 1<<16
 X86_FPU_FLAGS_TEST_C1 = 1<<17
 X86_FPU_FLAGS_TEST_C2 = 1<<18
 X86_FPU_FLAGS_TEST_C3 = 1<<19
-
-X86_OP_INVALID = 0
-X86_OP_REG = 1
-X86_OP_IMM = 2
-X86_OP_MEM = 3
+X86_OP_INVALID = CS_OP_INVALID
+X86_OP_REG = CS_OP_REG
+X86_OP_IMM = CS_OP_IMM
+X86_OP_MEM = CS_OP_MEM
 
 X86_XOP_CC_INVALID = 0
 X86_XOP_CC_LT = 1
diff --git a/bindings/python/capstone/xcore_const.py b/bindings/python/capstone/xcore_const.py
index 3d32f65d2..5bc1b56fe 100644
--- a/bindings/python/capstone/xcore_const.py
+++ b/bindings/python/capstone/xcore_const.py
@@ -1,10 +1,9 @@
 from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
 # For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [xcore_const.py]
-
-XCORE_OP_INVALID = 0
-XCORE_OP_REG = 1
-XCORE_OP_IMM = 2
-XCORE_OP_MEM = 3
+XCORE_OP_INVALID = CS_OP_INVALID
+XCORE_OP_REG = CS_OP_REG
+XCORE_OP_IMM = CS_OP_IMM
+XCORE_OP_MEM = CS_OP_MEM
 
 XCORE_REG_INVALID = 0
 XCORE_REG_CP = 1
diff --git a/bindings/python/capstone/xtensa_const.py b/bindings/python/capstone/xtensa_const.py
index 05b5af6f1..fefdf7052 100644
--- a/bindings/python/capstone/xtensa_const.py
+++ b/bindings/python/capstone/xtensa_const.py
@@ -1644,4 +1644,4 @@ XTENSA_OP_IMM = CS_OP_IMM
 XTENSA_OP_MEM = CS_OP_MEM
 XTENSA_OP_MEM_REG = CS_OP_MEM_REG
 XTENSA_OP_MEM_IMM = CS_OP_MEM_IMM
-XTENSA_OP_L32R = 14
+XTENSA_OP_L32R = CS_OP_SPECIAL+0
diff --git a/include/capstone/bpf.h b/include/capstone/bpf.h
index 713c67778..45914c778 100644
--- a/include/capstone/bpf.h
+++ b/include/capstone/bpf.h
@@ -11,6 +11,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable : 4201)
@@ -19,15 +20,14 @@ extern "C" {
 #define NUM_BPF_OPS 3
 /// Operand type for instruction's operands
 typedef enum bpf_op_type {
-	BPF_OP_INVALID = 0,
-
-	BPF_OP_REG,
-	BPF_OP_IMM,
-	BPF_OP_OFF,
-	BPF_OP_MEM,
-	BPF_OP_MMEM, ///< M[k] in cBPF
-	BPF_OP_MSH,  ///< corresponds to cBPF's BPF_MSH mode
-	BPF_OP_EXT,  ///< cBPF's extension (not eBPF)
+	BPF_OP_INVALID = CS_OP_INVALID,
+	BPF_OP_REG = CS_OP_REG,
+	BPF_OP_IMM = CS_OP_IMM,
+	BPF_OP_OFF = CS_OP_SPECIAL + 0,
+	BPF_OP_MSH = CS_OP_SPECIAL + 1,  ///< corresponds to cBPF's BPF_MSH mode
+	BPF_OP_EXT = CS_OP_SPECIAL + 2,  ///< cBPF's extension (not eBPF)
+	BPF_OP_MMEM = CS_OP_MEM | (CS_OP_SPECIAL + 3), ///< M[k] in cBPF
+	BPF_OP_MEM = CS_OP_MEM,
 } bpf_op_type;
 
 /// BPF registers
diff --git a/include/capstone/hppa.h b/include/capstone/hppa.h
index 097126d91..319e2a45e 100644
--- a/include/capstone/hppa.h
+++ b/include/capstone/hppa.h
@@ -14,15 +14,13 @@ extern "C" {
 
 /// Operand type for instruction's operands
 typedef enum hppa_op_type {
-	HPPA_OP_INVALID = 0,
-
-	HPPA_OP_REG,
-	HPPA_OP_IMM,
-	HPPA_OP_IDX_REG,
-	HPPA_OP_DISP,
-	HPPA_OP_MEM,
-	HPPA_OP_TARGET,
-
+	HPPA_OP_INVALID = CS_OP_INVALID,
+	HPPA_OP_REG = CS_OP_REG,
+	HPPA_OP_IMM = CS_OP_IMM,
+	HPPA_OP_IDX_REG = CS_OP_SPECIAL + 0,
+	HPPA_OP_DISP = CS_OP_SPECIAL + 1,
+	HPPA_OP_TARGET = CS_OP_SPECIAL + 2,
+	HPPA_OP_MEM = CS_OP_MEM,
 } hppa_op_type;
 
 //> HPPA registers
diff --git a/include/capstone/m680x.h b/include/capstone/m680x.h
index 07533cce9..3ef32802a 100644
--- a/include/capstone/m680x.h
+++ b/include/capstone/m680x.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -53,14 +54,14 @@ typedef enum m680x_reg {
 
 /// Operand type for instruction's operands
 typedef enum m680x_op_type {
-	M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	M680X_OP_REGISTER,    ///< = Register operand.
-	M680X_OP_IMMEDIATE,   ///< = Immediate operand.
-	M680X_OP_INDEXED,     ///< = Indexed addressing operand.
-	M680X_OP_EXTENDED,    ///< = Extended addressing operand.
-	M680X_OP_DIRECT,      ///< = Direct addressing operand.
-	M680X_OP_RELATIVE,    ///< = Relative addressing operand.
-	M680X_OP_CONSTANT,    ///< = constant operand (Displayed as number only).
+	M680X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	M680X_OP_REGISTER = CS_OP_REG,    ///< = Register operand.
+	M680X_OP_IMMEDIATE = CS_OP_IMM,   ///< = Immediate operand.
+	M680X_OP_INDEXED = CS_OP_SPECIAL + 0,     ///< = Indexed addressing operand.
+	M680X_OP_EXTENDED = CS_OP_SPECIAL + 1,    ///< = Extended addressing operand.
+	M680X_OP_DIRECT = CS_OP_SPECIAL + 2,      ///< = Direct addressing operand.
+	M680X_OP_RELATIVE = CS_OP_SPECIAL + 3,    ///< = Relative addressing operand.
+	M680X_OP_CONSTANT = CS_OP_SPECIAL + 4,    ///< = constant operand (Displayed as number only).
 				///< Used e.g. for a bit index or page number.
 } m680x_op_type;
 
diff --git a/include/capstone/m68k.h b/include/capstone/m68k.h
index 35918d38a..12f198c18 100644
--- a/include/capstone/m68k.h
+++ b/include/capstone/m68k.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -110,15 +111,15 @@ typedef enum m68k_address_mode {
 
 /// Operand type for instruction's operands
 typedef enum m68k_op_type {
-	M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	M68K_OP_REG,         ///< = CS_OP_REG (Register operand).
-	M68K_OP_IMM,         ///< = CS_OP_IMM (Immediate operand).
-	M68K_OP_MEM,         ///< = CS_OP_MEM (Memory operand).
-	M68K_OP_FP_SINGLE,   ///< single precision Floating-Point operand
-	M68K_OP_FP_DOUBLE,   ///< double precision Floating-Point operand
-	M68K_OP_REG_BITS,    ///< Register bits move
-	M68K_OP_REG_PAIR,    ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
-	M68K_OP_BR_DISP,     ///< Branch displacement
+	M68K_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	M68K_OP_REG = CS_OP_REG,         ///< = CS_OP_REG (Register operand).
+	M68K_OP_IMM = CS_OP_IMM,         ///< = CS_OP_IMM (Immediate operand).
+	M68K_OP_FP_SINGLE = CS_OP_SPECIAL + 0,   ///< single precision Floating-Point operand
+	M68K_OP_FP_DOUBLE = CS_OP_SPECIAL + 1,   ///< double precision Floating-Point operand
+	M68K_OP_REG_BITS = CS_OP_SPECIAL + 2,    ///< Register bits move
+	M68K_OP_REG_PAIR = CS_OP_SPECIAL + 3,    ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
+	M68K_OP_BR_DISP = CS_OP_SPECIAL + 4,     ///< Branch displacement
+	M68K_OP_MEM = CS_OP_MEM,         ///< = CS_OP_MEM (Memory operand).
 } m68k_op_type;
 
 /// Instruction's operand referring to memory
diff --git a/include/capstone/mips.h b/include/capstone/mips.h
index 95b2da132..05c6bc924 100644
--- a/include/capstone/mips.h
+++ b/include/capstone/mips.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 // GCC MIPS toolchain has a default macro called "mips" which breaks
 // compilation
@@ -20,10 +21,10 @@ extern "C" {
 
 /// Operand type for instruction's operands
 typedef enum mips_op_type {
-	MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	MIPS_OP_REG, ///< = CS_OP_REG (Register operand).
-	MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	MIPS_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	MIPS_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	MIPS_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	MIPS_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } mips_op_type;
 
 /// MIPS registers
diff --git a/include/capstone/mos65xx.h b/include/capstone/mos65xx.h
index e942c9618..abd48efb2 100644
--- a/include/capstone/mos65xx.h
+++ b/include/capstone/mos65xx.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 /// MOS65XX registers and special registers
 typedef enum mos65xx_reg {
@@ -170,10 +171,10 @@ typedef enum mos65xx_group_type {
 
 /// Operand type for instruction's operands
 typedef enum mos65xx_op_type {
-	MOS65XX_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	MOS65XX_OP_REG, ///< = CS_OP_REG (Register operand).
-	MOS65XX_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	MOS65XX_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	MOS65XX_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	MOS65XX_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	MOS65XX_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	MOS65XX_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } mos65xx_op_type;
 
 /// Instruction operand
diff --git a/include/capstone/riscv.h b/include/capstone/riscv.h
index 09b8fedd3..9b748d926 100644
--- a/include/capstone/riscv.h
+++ b/include/capstone/riscv.h
@@ -14,6 +14,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 // GCC MIPS toolchain has a default macro called "mips" which breaks
 // compilation
@@ -25,10 +26,10 @@ extern "C" {
 
 //> Operand type for instruction's operands
 typedef enum riscv_op_type {
-	RISCV_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
-	RISCV_OP_REG, // = CS_OP_REG (Register operand).
-	RISCV_OP_IMM, // = CS_OP_IMM (Immediate operand).
-	RISCV_OP_MEM, // = CS_OP_MEM (Memory operand).
+	RISCV_OP_INVALID = CS_OP_INVALID, // = CS_OP_INVALID (Uninitialized).
+	RISCV_OP_REG = CS_OP_REG, // = CS_OP_REG (Register operand).
+	RISCV_OP_IMM = CS_OP_IMM, // = CS_OP_IMM (Immediate operand).
+	RISCV_OP_MEM = CS_OP_MEM, // = CS_OP_MEM (Memory operand).
 } riscv_op_type;
 
 // Instruction's operand referring to memory
diff --git a/include/capstone/sh.h b/include/capstone/sh.h
index 7f81313f1..2bebf4dce 100644
--- a/include/capstone/sh.h
+++ b/include/capstone/sh.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -157,10 +158,10 @@ typedef enum {
 } sh_reg;
 
 typedef enum {
-	SH_OP_INVALID = 0,  ///< = CS_OP_INVALID (Uninitialized).
-	SH_OP_REG, ///< = CS_OP_REG (Register operand).
-	SH_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	SH_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	SH_OP_INVALID = CS_OP_INVALID,  ///< = CS_OP_INVALID (Uninitialized).
+	SH_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	SH_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	SH_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } sh_op_type;	
 
 typedef enum {
diff --git a/include/capstone/sparc.h b/include/capstone/sparc.h
index f09b5ca7e..fd06fc10b 100644
--- a/include/capstone/sparc.h
+++ b/include/capstone/sparc.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 // GCC SPARC toolchain has a default macro called "sparc" which breaks
 // compilation
@@ -70,10 +71,10 @@ typedef enum sparc_hint {
 
 /// Operand type for instruction's operands
 typedef enum sparc_op_type {
-	SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	SPARC_OP_REG, ///< = CS_OP_REG (Register operand).
-	SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	SPARC_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	SPARC_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	SPARC_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	SPARC_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } sparc_op_type;
 
 /// SPARC registers
diff --git a/include/capstone/tms320c64x.h b/include/capstone/tms320c64x.h
index 5e7f1b3bc..04d0c1e9a 100644
--- a/include/capstone/tms320c64x.h
+++ b/include/capstone/tms320c64x.h
@@ -10,17 +10,18 @@ extern "C" {
 
 #include <stdint.h>
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
 #endif
 
 typedef enum tms320c64x_op_type {
-	TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
-	TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
-	TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
+	TMS320C64X_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	TMS320C64X_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	TMS320C64X_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	TMS320C64X_OP_REGPAIR = CS_OP_SPECIAL + 0, ///< Register pair for double word ops
+	TMS320C64X_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } tms320c64x_op_type;
 
 typedef enum tms320c64x_mem_disp {
diff --git a/include/capstone/wasm.h b/include/capstone/wasm.h
index a2ac20c38..dc81b3198 100644
--- a/include/capstone/wasm.h
+++ b/include/capstone/wasm.h
@@ -9,21 +9,22 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
 #endif
 
 typedef enum wasm_op_type {
-	WASM_OP_INVALID = 0,
-	WASM_OP_NONE,
-	WASM_OP_INT7,
-	WASM_OP_VARUINT32,
-	WASM_OP_VARUINT64,
-	WASM_OP_UINT32,
-	WASM_OP_UINT64,
-	WASM_OP_IMM,
-	WASM_OP_BRTABLE,
+	WASM_OP_INVALID = CS_OP_INVALID,
+	WASM_OP_IMM = CS_OP_IMM,
+	WASM_OP_NONE = CS_OP_SPECIAL + 0,
+	WASM_OP_INT7 = CS_OP_SPECIAL + 1,
+	WASM_OP_VARUINT32 = CS_OP_SPECIAL + 2,
+	WASM_OP_VARUINT64 = CS_OP_SPECIAL + 3,
+	WASM_OP_UINT32 = CS_OP_SPECIAL + 4,
+	WASM_OP_UINT64 = CS_OP_SPECIAL + 5,
+	WASM_OP_BRTABLE = CS_OP_SPECIAL + 6,
 } wasm_op_type;
 
 typedef struct cs_wasm_brtable {
diff --git a/include/capstone/x86.h b/include/capstone/x86.h
index 1761cc4e0..17e7cc2c0 100644
--- a/include/capstone/x86.h
+++ b/include/capstone/x86.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 /// Calculate relative address for X86-64, given cs_insn structure
 #define X86_REL_ADDR(insn) (((insn).detail->x86.operands[0].type == X86_OP_IMM) \
@@ -157,10 +158,10 @@ typedef enum x86_reg {
 
 /// Operand type for instruction's operands
 typedef enum x86_op_type {
-	X86_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	X86_OP_REG, ///< = CS_OP_REG (Register operand).
-	X86_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	X86_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	X86_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	X86_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	X86_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	X86_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } x86_op_type;
 
 /// XOP Code Condition type
diff --git a/include/capstone/xcore.h b/include/capstone/xcore.h
index 6db1f2468..c56d61810 100644
--- a/include/capstone/xcore.h
+++ b/include/capstone/xcore.h
@@ -9,6 +9,7 @@ extern "C" {
 #endif
 
 #include "platform.h"
+#include "cs_operand.h"
 
 #ifdef _MSC_VER
 #pragma warning(disable:4201)
@@ -16,10 +17,10 @@ extern "C" {
 
 /// Operand type for instruction's operands
 typedef enum xcore_op_type {
-	XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
-	XCORE_OP_REG, ///< = CS_OP_REG (Register operand).
-	XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
-	XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	XCORE_OP_INVALID = CS_OP_INVALID, ///< = CS_OP_INVALID (Uninitialized).
+	XCORE_OP_REG = CS_OP_REG, ///< = CS_OP_REG (Register operand).
+	XCORE_OP_IMM = CS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	XCORE_OP_MEM = CS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
 } xcore_op_type;
 
 /// XCore registers
diff --git a/include/capstone/xtensa.h b/include/capstone/xtensa.h
index ee34de4a8..6b2f2f6e1 100644
--- a/include/capstone/xtensa.h
+++ b/include/capstone/xtensa.h
@@ -1693,7 +1693,7 @@ typedef enum cs_xtensa_op_type {
 	XTENSA_OP_MEM = CS_OP_MEM,	   ///< = (Memory operand).
 	XTENSA_OP_MEM_REG = CS_OP_MEM_REG, ///< = (Memory Register operand).
 	XTENSA_OP_MEM_IMM = CS_OP_MEM_IMM, ///< = (Memory Immediate operand).
-	XTENSA_OP_L32R,			   ///< = (L32R Target)
+	XTENSA_OP_L32R = CS_OP_SPECIAL + 0,			   ///< = (L32R Target)
 } cs_xtensa_op_type;
 
 typedef struct cs_xtensa_op_mem {
diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h
index 877429798..d7e6fe739 100644
--- a/suite/cstest/include/test_mapping.h
+++ b/suite/cstest/include/test_mapping.h
@@ -488,6 +488,27 @@ static const cs_enum_id_map cs_enum_map[] = {
 	{ .str = "CS_AC_READ", .val = CS_AC_READ },
 	{ .str = "CS_AC_READ_WRITE", .val = CS_AC_READ_WRITE },
 	{ .str = "CS_AC_WRITE", .val = CS_AC_WRITE },
+	{ .str = "CS_OP_BOUND", .val = CS_OP_BOUND },
+	{ .str = "CS_OP_FP", .val = CS_OP_FP },
+	{ .str = "CS_OP_IMM", .val = CS_OP_IMM },
+	{ .str = "CS_OP_INVALID", .val = CS_OP_INVALID },
+	{ .str = "CS_OP_MEM", .val = CS_OP_MEM },
+	{ .str = "CS_OP_MEM_IMM", .val = CS_OP_MEM_IMM },
+	{ .str = "CS_OP_MEM_REG", .val = CS_OP_MEM_REG },
+	{ .str = "CS_OP_PRED", .val = CS_OP_PRED },
+	{ .str = "CS_OP_REG", .val = CS_OP_REG },
+	{ .str = "CS_OP_RESERVED_10", .val = CS_OP_RESERVED_10 },
+	{ .str = "CS_OP_RESERVED_11", .val = CS_OP_RESERVED_11 },
+	{ .str = "CS_OP_RESERVED_12", .val = CS_OP_RESERVED_12 },
+	{ .str = "CS_OP_RESERVED_13", .val = CS_OP_RESERVED_13 },
+	{ .str = "CS_OP_RESERVED_14", .val = CS_OP_RESERVED_14 },
+	{ .str = "CS_OP_RESERVED_15", .val = CS_OP_RESERVED_15 },
+	{ .str = "CS_OP_RESERVED_5", .val = CS_OP_RESERVED_5 },
+	{ .str = "CS_OP_RESERVED_6", .val = CS_OP_RESERVED_6 },
+	{ .str = "CS_OP_RESERVED_7", .val = CS_OP_RESERVED_7 },
+	{ .str = "CS_OP_RESERVED_8", .val = CS_OP_RESERVED_8 },
+	{ .str = "CS_OP_RESERVED_9", .val = CS_OP_RESERVED_9 },
+	{ .str = "CS_OP_SPECIAL", .val = CS_OP_SPECIAL },
 	{ .str = "EVM_GRP_HALT", .val = EVM_GRP_HALT },
 	{ .str = "EVM_GRP_JUMP", .val = EVM_GRP_JUMP },
 	{ .str = "EVM_GRP_MATH", .val = EVM_GRP_MATH },
diff --git a/tests/issues/issues.yaml b/tests/issues/issues.yaml
index 6d817f4e8..cdac2171b 100644
--- a/tests/issues/issues.yaml
+++ b/tests/issues/issues.yaml
@@ -5658,6 +5658,44 @@ test_cases:
                 imm: 0
                 access: CS_AC_READ
           regs_read: [ ra ]
+  - input:
+      name: "RISCV - #2632 - Memory operand type was 3 instead of 0x80"
+      bytes: [ 0x0c, 0xc2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_OPT_DETAIL, CS_MODE_RISCV32, CS_MODE_RISCVC ]
+      address: 0x0
+    expected:
+      insns:
+      - asm_text: "c.sw	a1, 0(a2)"
+        details:
+          riscv:
+            operands:
+              - type: CS_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              - type: CS_OP_MEM
+                mem_base: a2
+                access: CS_AC_WRITE
+  -
+    input:
+      name: "x86 - issue #2632 - Memory operand type was 3 instead of 0x80"
+      bytes: [ 0x4c, 0x89, 0x65, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov	qword ptr [rbp - 0x38], r12"
+        details:
+          x86:
+            operands:
+              -
+                type: CS_OP_MEM
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
 
   - input:
       name: "mipsel64r6 lapc as alias of addiupc with details & real"
@@ -5802,4 +5840,3 @@ test_cases:
               - type: MIPS_OP_IMM
                 imm: 0
                 access: CS_AC_READ
-