From d650f67eb2a4e5a70c062925bd3fc1d21ecfe5b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Petar=20Andri=C4=87?= Date: Wed, 13 May 2026 18:33:27 +0200 Subject: [PATCH] RISCV: the Ventana vendor is missing in the API (#2917) * RISCV: the Ventana vendor was missing in the API * Update docs --- arch/RISCV/RISCVDisassemblerExtension.c | 3 +++ bindings/python/capstone/__init__.py | 4 ++++ cs.c | 7 ++++--- cstool/cstool.c | 5 +++++ docs/cs_v6_release_guide.md | 1 + include/capstone/capstone.h | 1 + suite/auto-sync/src/autosync/mcupdater.json | 3 ++- suite/cstest/include/test_mapping.h | 2 ++ ..._riscv64_xventanacondops_syntax_no_alias_text.txt.yaml | 8 ++++---- 9 files changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/RISCV/RISCVDisassemblerExtension.c b/arch/RISCV/RISCVDisassemblerExtension.c index 406cd764e..bdecdf385 100644 --- a/arch/RISCV/RISCVDisassemblerExtension.c +++ b/arch/RISCV/RISCVDisassemblerExtension.c @@ -69,6 +69,9 @@ bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature) case RISCV_FeatureVendorXTHeadVdot: return mode & CS_MODE_RISCV_THEAD; + case RISCV_FeatureVendorXVentanaCondOps: + return mode & CS_MODE_RISCV_VENTANA; + case RISCV_FeatureStdExtZba: return mode & CS_MODE_RISCV_ZBA; case RISCV_FeatureStdExtZbb: diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 76e6793b5..608b6e3fa 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -146,6 +146,8 @@ __all__ = [ "CS_MODE_RISCV_XSFVFWMACCQQQ", "CS_MODE_RISCV_XSFVQMACCDOD", "CS_MODE_RISCV_XSFVQMACCQOQ", + "CS_MODE_RISCV_VENTANA", + "CS_MODE_RISCV_XVENTANACONDOPS", "CS_MODE_RISCV_BITMANIP", "CS_MODE_RISCV_ZBA", "CS_MODE_RISCV_ZBB", @@ -449,6 +451,8 @@ CS_MODE_RISCV_ZBKB = 1 << 17 CS_MODE_RISCV_ZBKC = 1 << 18 CS_MODE_RISCV_ZBKX = 1 << 19 CS_MODE_RISCV_ZBS = 1 << 20 +CS_MODE_RISCV_VENTANA = 1 << 21 +CS_MODE_RISCV_XVENTANACONDOPS = CS_MODE_RISCV_VENTANA CS_MODE_MOS65XX_6502 = 1 << 1 # MOS65XXX MOS 6502 CS_MODE_MOS65XX_65C02 = 1 << 2 # MOS65XXX WDC 65c02 CS_MODE_MOS65XX_W65C02 = 1 << 3 # MOS65XXX WDC W65c02 diff --git a/cs.c b/cs.c index f8d669113..9aafe2930 100644 --- a/cs.c +++ b/cs.c @@ -223,9 +223,10 @@ typedef struct cs_arch_config { CS_MODE_RISCV_ZCMP_ZCMT_ZCE | CS_MODE_RISCV_ZICFISS | \ CS_MODE_RISCV_E | CS_MODE_RISCV_A | CS_MODE_RISCV_COREV | \ CS_MODE_RISCV_SIFIVE | CS_MODE_RISCV_THEAD | \ - CS_MODE_RISCV_ZBA | CS_MODE_RISCV_ZBB | CS_MODE_RISCV_ZBC | \ - CS_MODE_RISCV_ZBKB | CS_MODE_RISCV_ZBKC | \ - CS_MODE_RISCV_ZBKX | CS_MODE_RISCV_ZBS), \ + CS_MODE_RISCV_VENTANA | CS_MODE_RISCV_ZBA | \ + CS_MODE_RISCV_ZBB | CS_MODE_RISCV_ZBC | CS_MODE_RISCV_ZBKB | \ + CS_MODE_RISCV_ZBKC | CS_MODE_RISCV_ZBKX | \ + CS_MODE_RISCV_ZBS), \ } #define CS_ARCH_CONFIG_SH \ { \ diff --git a/cstool/cstool.c b/cstool/cstool.c index 6b2b569b8..d507453f1 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -228,6 +228,11 @@ static struct { { CS_ARCH_RISCV, CS_ARCH_MAX }, 0, CS_MODE_RISCV_SIFIVE }, + { "+ventana", + "Enables the RISCV ventana extension", + { CS_ARCH_RISCV, CS_ARCH_MAX }, + 0, + CS_MODE_RISCV_VENTANA }, { "+bitmanip", "Enables the RISCV bit manipulation extension", { CS_ARCH_RISCV, CS_ARCH_MAX }, diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index b89338233..290a88ec6 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -233,6 +233,7 @@ Nonetheless, we hope this additional information is useful to you. * `CS_MODE_RISCV_ZBKC = 1 << 18` * `CS_MODE_RISCV_ZBKX = 1 << 19` * `CS_MODE_RISCV_ZBS = 1 << 20` + * `CS_MODE_RISCV_VENTANA = 1 << 21` - Added two syntax options for alias control: * `CS_OPT_SYNTAX_NO_ALIAS_TEXT`: RISC-V assigns readable aliases to special cases of more flexible instructions, for example: `ret` is a `jalr`, a more general instruction that takes an arbitrary register as jump destination and a link register. `ret` is the special case where those 2 arguments are restricted to `ra` and `x0` respectively. diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index 8a3766729..ca061afc3 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -231,6 +231,7 @@ typedef enum cs_mode { CS_MODE_RISCV_ZBKC = 1 << 18, CS_MODE_RISCV_ZBKX = 1 << 19, CS_MODE_RISCV_ZBS = 1 << 20, + CS_MODE_RISCV_VENTANA = 1 << 21, CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502 CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02 CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02 diff --git a/suite/auto-sync/src/autosync/mcupdater.json b/suite/auto-sync/src/autosync/mcupdater.json index 198d5be60..fddca440a 100644 --- a/suite/auto-sync/src/autosync/mcupdater.json +++ b/suite/auto-sync/src/autosync/mcupdater.json @@ -223,8 +223,9 @@ "xtheadcmo": ["CS_MODE_RISCV_XTHEADCMO"], "xtheadcondmov": ["CS_MODE_RISCV_XTHEADCONDMOV"], "xtheadsync": ["CS_MODE_RISCV_XTHEADSYNC"], - "xtheadvdot": ["CS_MODE_RISCV_XTHEADVDOT"] + "xtheadvdot": ["CS_MODE_RISCV_XTHEADVDOT"], + "xventanacondops": ["CS_MODE_RISCV_XVENTANACONDOPS"] } } } diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h index 8634e0d05..993b86bda 100644 --- a/suite/cstest/include/test_mapping.h +++ b/suite/cstest/include/test_mapping.h @@ -182,6 +182,8 @@ static const cs_enum_id_map test_mode_map[] = { { .str = "CS_MODE_RISCV_XTHEADMEMPAIR", .val = CS_MODE_RISCV_THEAD }, { .str = "CS_MODE_RISCV_XTHEADSYNC", .val = CS_MODE_RISCV_THEAD }, { .str = "CS_MODE_RISCV_XTHEADVDOT", .val = CS_MODE_RISCV_THEAD }, + { .str = "CS_MODE_RISCV_XVENTANACONDOPS", + .val = CS_MODE_RISCV_VENTANA }, { .str = "CS_MODE_RISCV_ZBA", .val = CS_MODE_RISCV_ZBA }, { .str = "CS_MODE_RISCV_ZBB", .val = CS_MODE_RISCV_ZBB }, { .str = "CS_MODE_RISCV_ZBC", .val = CS_MODE_RISCV_ZBC }, diff --git a/tests/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.yaml b/tests/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.yaml index 2afc649db..47fdc5d9b 100644 --- a/tests/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.yaml +++ b/tests/MC/RISCV/XVentanaCondOps_valid_riscv64_xventanacondops_syntax_no_alias_text.txt.yaml @@ -3,7 +3,7 @@ test_cases: input: bytes: [ 0x7b, 0x60, 0x00, 0x00 ] arch: "CS_ARCH_RISCV" - options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] + options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] expected: insns: - @@ -13,7 +13,7 @@ test_cases: input: bytes: [ 0x7b, 0x70, 0x00, 0x00 ] arch: "CS_ARCH_RISCV" - options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] + options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] expected: insns: - @@ -23,7 +23,7 @@ test_cases: input: bytes: [ 0xfb, 0x60, 0x31, 0x00 ] arch: "CS_ARCH_RISCV" - options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] + options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] expected: insns: - @@ -33,7 +33,7 @@ test_cases: input: bytes: [ 0xfb, 0x70, 0x31, 0x00 ] arch: "CS_ARCH_RISCV" - options: [ "CS_MODE_RISCV64", "xventanacondops", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] + options: [ "CS_MODE_RISCV64", "CS_MODE_RISCV_XVENTANACONDOPS", "CS_OPT_SYNTAX_NO_ALIAS_TEXT" ] expected: insns: -