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Rebased #2570 (#2614)

Browse source 
* Add ARC files

* Added ARC files for successful compilation

* Refactor ARC files

* Add ARC c/cs tests

* Add ARC python test/bindings

* Add ARC to CI/CD

* Avoid omitting parameter names

* Update cs files

* Fix ARC bugs

* Update ARC python bindings

* Refactor and update ARC test files

* Add detail flag to arc test

* Fix ARC test problems

* Fix ARCMapping compile error

* Replace __CHAR_BIT__ to CHAR_BIT

* Add credits and ARC info

* Update ARC to match the latest next

* Python formatting

* Remove asserts on 'Unknown condition code passed'

* Add ARC to some more documentation

* Add ARC to Targets constants

* Add ARC support to llvm-tblgen

* Replace asserts & add Expr handling

* Check DecodeGPR32RegisterClass return value

* Fix fieldFromInstruction patch

* Refactor ARC

* Reformat python files

* Fix incorrect import

* Update inc files and insn names

* Update python files

* Disable AArch64 Linux wheel build due to https://github.com/capstone-engine/capstone/issues/2615.

---------

Co-authored-by: R33v0LT <sibirtsevdl@gmail.com>
This commit is contained in:
Rot127 2025-01-28 14:34:24 +00:00 • committed by GitHub
parent c831cd5ef5
commit d7ef910bc6
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GPG key ID: B5690EEEBB952194
75 changed files with 21579 additions and 27 deletions
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7
.github/labeler.yml vendored
View file

@ -48,6 +48,13 @@ Alpha:
- tests/MC/Alpha/**
- tests/details/alpha.yaml
ARC:
- arch/ARC/*
- cstool/cstool_arc.c
- include/capstone/arc.h
- suite/MC/ARC/*
- tests/test_arc.c
BPF:
- arch/BPF/**
- cstool/cstool_bpf.c

4
.github/workflows/auto-sync.yml vendored
View file

@ -55,7 +55,7 @@ jobs:
cd vendor/llvm_root
mkdir build
cd build
cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=ARC ../llvm
cmake --build . --target llvm-tblgen --config Debug
cd ../../../
@ -74,6 +74,7 @@ jobs:
run: |
./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen
./src/autosync/ASUpdater.py -d -a Alpha -s IncGen
./src/autosync/ASUpdater.py -d -a ARC -s IncGen
./src/autosync/ASUpdater.py -d -a ARM -s IncGen
./src/autosync/ASUpdater.py -d -a PPC -s IncGen
./src/autosync/ASUpdater.py -d -a LoongArch -s IncGen
@ -93,6 +94,7 @@ jobs:
- name: CppTranslator - Test translation
run: |
./src/autosync/ASUpdater.py --ci -d -a AArch64 -s Translate
./src/autosync/ASUpdater.py --ci -d -a ARC -s Translate
./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate
./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate

24
.github/workflows/build-wheels-publish.yml vendored
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@ -52,9 +52,11 @@ jobs:
# x86_64 - musllinux
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' }
# aarch64 - manylinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' }
# Disabled for now due to: https://github.com/capstone-engine/capstone/issues/2615
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-manylinux* cp313-manylinux*', cibw_skip: '' }
# aarch64 - musllinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' }
# Disabled for now due to: https://github.com/capstone-engine/capstone/issues/2615
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp38-musllinux* cp313-musllinux*', cibw_skip: '' }
# macos - x86_64
- { os: macos-13, arch: x86_64, cibw_build: 'cp38* cp313*', cibw_skip: '' }
# macos - arm64
@ -162,15 +164,17 @@ jobs:
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp311-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp312-musllinux*', cibw_skip: '' }
# aarch64 - manylinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-manylinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-manylinux*', cibw_skip: '' }
# Disabled for now due to: https://github.com/capstone-engine/capstone/issues/2615
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-manylinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-manylinux*', cibw_skip: '' }
# aarch64 - musllinux
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-musllinux*', cibw_skip: '' }
- { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-musllinux*', cibw_skip: '' }
# Disabled for now due to: https://github.com/capstone-engine/capstone/issues/2615
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp39-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp310-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp311-musllinux*', cibw_skip: '' }
# - { os: ubuntu-latest, arch: aarch64, cibw_build: 'cp312-musllinux*', cibw_skip: '' }
# macos - x86_64
- { os: macos-13, arch: x86_64, cibw_build: 'cp*', cibw_skip: '*36* *37* *38* *313*' }
# macos - arm64

1
.gitignore vendored
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@ -79,6 +79,7 @@ tests/test_riscv
tests/test_sh
tests/test_alpha
tests/test_hppa
tests/test_arc
# regress binaries
suite/regress/invalid_read_in_print_operand

1
BUILDING.md
View file

@ -44,6 +44,7 @@ By default all are enabled.
- `CAPSTONE_ARM_SUPPORT`: Support ARM.
- `CAPSTONE_AARCH64_SUPPORT`: Support AARCH64.
- `CAPSTONE_ALPHA_SUPPORT`: Support Alpha.
- `CAPSTONE_ARC_SUPPORT`: Support ARC.
- `CAPSTONE_HPPA_SUPPORT`: Support HPPA.
- `CAPSTONE_LOONGARCH_SUPPORT`: Support LoongArch.
- `CAPSTONE_M680X_SUPPORT`: Support M680X.

25
CMakeLists.txt
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@ -105,8 +105,8 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
endif()
set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH XTENSA)
set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch Xtensa)
set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSTEMZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA LOONGARCH XTENSA ARC)
set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA LoongArch Xtensa ARC)
# If building for OSX it's best to allow CMake to handle building both architectures
if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
@ -232,6 +232,7 @@ set(HEADERS_COMMON
include/capstone/hppa.h
include/capstone/loongarch.h
include/capstone/xtensa.h
include/capstone/arc.h
)
## architecture support
@ -716,6 +717,22 @@ if(CAPSTONE_XTENSA_SUPPORT)
)
endif()
if (CAPSTONE_ARC_SUPPORT)
add_definitions(-DCAPSTONE_HAS_ARC)
set(SOURCES_ARC
arch/ARC/ARCDisassembler.c
arch/ARC/ARCInstPrinter.c
arch/ARC/ARCMapping.c
arch/ARC/ARCModule.c
)
set(HEADERS_ARC
arch/ARC/ARCInstPrinter.h
arch/ARC/ARCMapping.h
arch/ARC/ARCModule.h
arch/ARC/ARCLinkage.h
)
endif ()
if (CAPSTONE_OSXKERNEL_SUPPORT)
add_definitions(-DCAPSTONE_HAS_OSXKERNEL)
endif()
@ -744,6 +761,7 @@ set(ALL_SOURCES
${SOURCES_HPPA}
${SOURCES_LOONGARCH}
${SOURCES_XTENSA}
${SOURCES_ARC}
)
set(ALL_HEADERS
@ -771,6 +789,7 @@ set(ALL_HEADERS
${HEADERS_HPPA}
${HEADERS_LOONGARCH}
${HEADERS_XTENSA}
${HEADERS_ARC}
)
## properties
@ -839,6 +858,7 @@ source_group("Source\\Alpha" FILES ${SOURCES_ALPHA})
source_group("Source\\HPPA" FILES ${SOURCES_HPPA})
source_group("Source\\LoongArch" FILES ${SOURCES_LOONGARCH})
source_group("Source\\Xtensa" FILES ${SOURCES_XTENSA})
source_group("Source\\ARC" FILES ${SOURCES_ARC})
source_group("Include\\Common" FILES ${HEADERS_COMMON})
source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
@ -864,6 +884,7 @@ source_group("Include\\Alpha" FILES ${HEADERS_ALPHA})
source_group("Include\\HPPA" FILES ${HEADERS_HPPA})
source_group("Include\\LoongArch" FILES ${HEADERS_LOONGARCH})
source_group("Include\\Xtensa" FILES ${HEADERS_XTENSA})
source_group("Include\\ARC" FILES ${HEADERS_ARC})
## installation
if(CAPSTONE_INSTALL)

1
COMPILE_MAKE.TXT
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@ -94,6 +94,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install.
/usr/include/capstone/arm.h
/usr/include/capstone/arm64.h
/usr/include/capstone/alpha.h
/usr/include/capstone/arc.h
/usr/include/capstone/bpf.h
/usr/include/capstone/capstone.h
/usr/include/capstone/evm.h

2
CREDITS.TXT
View file

@ -88,6 +88,6 @@ fanfuqiang & citypw & porto703 : RISCV architecture.
Josh "blacktop" Maine: Arm64 architecture improvements.
Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support)
Billow & Sidneyp: TriCore architecture.
Dmitry Sibirtsev: Alpha & HPPA architecture.
Dmitry Sibirtsev: Alpha, HPPA, ARC architecture.
Jiajie Chen & Yanglin Xun: LoongArch architecture.
Billow: Xtensa architecture.

13
Makefile
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@ -365,11 +365,21 @@ ifneq (,$(findstring xtensa,$(CAPSTONE_ARCHS)))
LIBOBJ_XTENSA += $(LIBSRC_XTENSA:%.c=$(OBJDIR)/%.o)
endif
DEP_ARC =
DEP_ARC += $(wildcard arch/ARC/ARC*.inc)
LIBOBJ_ARC =
ifneq (,$(findstring arc,$(CAPSTONE_ARCHS)))
CFLAGS += -DCAPSTONE_HAS_ARC
LIBSRC_ARC += $(wildcard arch/ARC/ARC*.c)
LIBOBJ_ARC += $(LIBSRC_ARC:%.c=$(OBJDIR)/%.o)
endif
LIBOBJ =
LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o
LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH)
LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF)
LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH) $(LIBOBJ_XTENSA)
LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) $(LIBOBJ_LOONGARCH) $(LIBOBJ_XTENSA) $(LIBOBJ_ARC)
ifeq ($(PKG_EXTRA),)
@ -503,6 +513,7 @@ $(LIBOBJ_ALPHA): $(DEP_ALPHA)
$(LIBOBJ_HPPA): $(DEP_HPPA)
$(LIBOBJ_LOONGARCH): $(DEP_LOONGARCH)
$(LIBOBJ_XTENSA): $(DEP_XTENSA)
$(LIBOBJ_ARC): $(DEP_ARC)
ifeq ($(CAPSTONE_STATIC),yes)
$(ARCHIVE): $(LIBOBJ)

1
Mapping.c
View file

@ -354,6 +354,7 @@ DEFINE_get_detail_op(riscv, RISCV);
DEFINE_get_detail_op(systemz, SystemZ);
DEFINE_get_detail_op(xtensa, Xtensa);
DEFINE_get_detail_op(bpf, BPF);
DEFINE_get_detail_op(arc, ARC);
/// Returns true if for this architecture the
/// alias operands should be filled.

5
Mapping.h
View file

@ -146,6 +146,7 @@ DECL_get_detail_op(riscv, RISCV);
DECL_get_detail_op(systemz, SystemZ);
DECL_get_detail_op(xtensa, Xtensa);
DECL_get_detail_op(bpf, BPF);
DECL_get_detail_op(arc, ARC);
/// Increments the detail->arch.op_count by one.
#define DEFINE_inc_detail_op_count(arch, ARCH) \
@ -185,6 +186,8 @@ DEFINE_inc_detail_op_count(xtensa, Xtensa);
DEFINE_dec_detail_op_count(xtensa, Xtensa);
DEFINE_inc_detail_op_count(bpf, BPF);
DEFINE_dec_detail_op_count(bpf, BPF);
DEFINE_inc_detail_op_count(arc, ARC);
DEFINE_dec_detail_op_count(arc, ARC);
/// Returns true if a memory operand is currently edited.
static inline bool doing_mem(const MCInst *MI)
@ -215,6 +218,7 @@ DEFINE_get_arch_detail(hppa, HPPA);
DEFINE_get_arch_detail(loongarch, LoongArch);
DEFINE_get_arch_detail(mips, Mips);
DEFINE_get_arch_detail(riscv, RISCV);
DEFINE_get_arch_detail(arc, ARC);
DEFINE_get_arch_detail(systemz, SystemZ);
DEFINE_get_arch_detail(xtensa, Xtensa);
DEFINE_get_arch_detail(bpf, BPF);
@ -235,6 +239,7 @@ DEFINE_check_safe_inc(RISCV, RISCV);
DEFINE_check_safe_inc(SystemZ, SYSTEMZ);
DEFINE_check_safe_inc(Mips, MIPS);
DEFINE_check_safe_inc(BPF, BPF);
DEFINE_check_safe_inc(ARC, ARC);
static inline bool detail_is_set(const MCInst *MI)
{

8
MathExtras.h
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@ -493,4 +493,12 @@ static inline uint32_t get_insn_bit(uint32_t insn, uint8_t bit)
return get_insn_field(insn, bit, bit);
}
/// \brief Create a bitmask with the N right-most bits set to 1, and all other
/// bits set to 0. Only unsigned types are allowed.
static inline uint32_t maskTrailingOnes32(uint32_t N)
{
const unsigned Bits = CHAR_BIT * sizeof(uint32_t);
return N == 0 ? 0 : (((uint32_t) -1) >> (Bits - N));
}
#endif

2
README.md
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@ -16,7 +16,7 @@ disasm engine for binary analysis and reversing in the security community.
Created by Nguyen Anh Quynh, then developed and maintained by a small community,
Capstone offers some unparalleled features:
- Support multiple hardware architectures: ARM, AArch64, Alpha, BPF, Ethereum VM,
- Support multiple hardware architectures: ARM, AArch64, Alpha, ARC, BPF, Ethereum VM,
LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH,
Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64), Xtensa.

473
arch/ARC/ARCDisassembler.c Normal file
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@ -0,0 +1,473 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCDisassembler.cpp - Disassembler for ARC ---------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file is part of the ARC Disassembler.
///
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../MCDisassembler.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MathExtras.h"
#include "../../utils.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "arc-disassembler"
/// A disassembler class for ARC.
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
size_t BytesLen, uint64_t Address,
SStream *CStream);
// end anonymous namespace
static bool readInstruction32(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint32_t *Insn)
{
*Size = 4;
// Read 2 16-bit values, but swap hi/lo parts.
*Insn = (Bytes[0] << 16) | (Bytes[1] << 24) | (Bytes[2] << 0) |
(Bytes[3] << 8);
return true;
}
static bool readInstruction64(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint64_t *Insn)
{
*Size = 8;
*Insn = ((uint64_t)Bytes[0] << 16) | ((uint64_t)Bytes[1] << 24) |
((uint64_t)Bytes[2] << 0) | ((uint64_t)Bytes[3] << 8) |
((uint64_t)Bytes[4] << 48) | ((uint64_t)Bytes[5] << 56) |
((uint64_t)Bytes[6] << 32) | ((uint64_t)Bytes[7] << 40);
return true;
}
static bool readInstruction48(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint64_t *Insn)
{
*Size = 6;
*Insn = ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
((uint64_t)Bytes[2] << 32) | ((uint64_t)Bytes[3] << 40) |
((uint64_t)Bytes[4] << 16) | ((uint64_t)Bytes[5] << 24);
return true;
}
static bool readInstruction16(const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, uint64_t *Size, uint32_t *Insn)
{
*Size = 2;
*Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
return true;
}
#define DECLARE_DecodeSignedOperand(B) \
static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void *Decoder);
DECLARE_DecodeSignedOperand(11);
DECLARE_DecodeSignedOperand(9);
DECLARE_DecodeSignedOperand(10);
DECLARE_DecodeSignedOperand(12);
#define DECLARE_DecodeFromCyclicRange(B) \
static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void *Decoder);
DECLARE_DecodeFromCyclicRange(3);
#define DECLARE_DecodeBranchTargetS(B) \
static DecodeStatus CONCAT(DecodeBranchTargetS, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder);
DECLARE_DecodeBranchTargetS(8);
DECLARE_DecodeBranchTargetS(10);
DECLARE_DecodeBranchTargetS(7);
DECLARE_DecodeBranchTargetS(13);
DECLARE_DecodeBranchTargetS(21);
DECLARE_DecodeBranchTargetS(25);
DECLARE_DecodeBranchTargetS(9);
static DecodeStatus DecodeMEMrs9(MCInst *, unsigned, uint64_t,
const void *);
static DecodeStatus DecodeLdLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeStLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeLdRLImmInstruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeSOPwithRS12(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeSOPwithRU6(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeCCRU6Instruction(MCInst *, uint64_t, uint64_t,
const void *);
static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t, uint64_t,
const void *);
#define GET_REGINFO_ENUM
#include "ARCGenRegisterInfo.inc"
static const uint16_t GPR32DecoderTable[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6,
ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13,
ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20,
ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP,
ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK
};
static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo >= 32) {
;
return MCDisassembler_Fail;
}
unsigned Reg = GPR32DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, (Reg));
return MCDisassembler_Success;
}
static DecodeStatus DecodeGBR32ShortRegister(MCInst *Inst, unsigned RegNo,
uint64_t Address,
const void *Decoder)
{
// Enumerates registers from ranges [r0-r3],[r12-r15].
if (RegNo > 3)
RegNo += 8; // 4 for r12, etc...
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
}
#include "ARCGenDisassemblerTables.inc"
static unsigned decodeCField(unsigned Insn)
{
return fieldFromInstruction_4(Insn, 6, 6);
}
static unsigned decodeBField(unsigned Insn)
{
return (fieldFromInstruction_4(Insn, 12, 3) << 3) |
fieldFromInstruction_4(Insn, 24, 3);
}
static unsigned decodeAField(unsigned Insn)
{
return fieldFromInstruction_4(Insn, 0, 6);
}
static DecodeStatus DecodeMEMrs9(MCInst *Inst, unsigned Insn, uint64_t Address,
const void *Decoder)
{
// We have the 9-bit immediate in the low bits, 6-bit register in high bits.
unsigned S9 = Insn & 0x1ff;
unsigned R = (Insn & (0x7fff & ~0x1ff)) >> 9;
if (DecodeGPR32RegisterClass(Inst, R, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, (SignExtend32((S9), 9)));
return MCDisassembler_Success;
}
static void DecodeSymbolicOperandOff(MCInst *Inst, uint64_t Address,
uint64_t Offset, const void *Decoder)
{
uint64_t NextAddress = Address + Offset;
MCOperand_CreateImm0(Inst, (NextAddress));
}
#define DEFINE_DecodeBranchTargetS(B) \
static DecodeStatus CONCAT(DecodeBranchTargetS, \
B)(MCInst * Inst, unsigned InsnS, \
uint64_t Address, const void *Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
DecodeSymbolicOperandOff(Inst, Address, \
SignExtend32((InsnS), B), Decoder); \
return MCDisassembler_Success; \
}
DEFINE_DecodeBranchTargetS(8);
DEFINE_DecodeBranchTargetS(10);
DEFINE_DecodeBranchTargetS(7);
DEFINE_DecodeBranchTargetS(13);
DEFINE_DecodeBranchTargetS(21);
DEFINE_DecodeBranchTargetS(25);
DEFINE_DecodeBranchTargetS(9);
#define DEFINE_DecodeSignedOperand(B) \
static DecodeStatus CONCAT(DecodeSignedOperand, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void * Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
MCOperand_CreateImm0( \
Inst, SignExtend32(maskTrailingOnes32(B) & \
InsnS, B) \
); \
return MCDisassembler_Success; \
}
DEFINE_DecodeSignedOperand(11);
DEFINE_DecodeSignedOperand(9);
DEFINE_DecodeSignedOperand(10);
DEFINE_DecodeSignedOperand(12);
#define DEFINE_DecodeFromCyclicRange(B) \
static DecodeStatus CONCAT(DecodeFromCyclicRange, B)( \
MCInst * Inst, unsigned InsnS, uint64_t Address, \
const void * Decoder) \
{ \
CS_ASSERT(B > 0 && "field is empty"); \
const unsigned max = (1u << B) - 1; \
MCOperand_CreateImm0(Inst, (InsnS < max ? (int)(InsnS) : -1)); \
return MCDisassembler_Success; \
}
DEFINE_DecodeFromCyclicRange(3);
static DecodeStatus DecodeStLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned SrcC, DstB, LImm;
DstB = decodeBField(Insn);
if (DstB != 62) {
return MCDisassembler_Fail;
}
SrcC = decodeCField(Insn);
if (DecodeGPR32RegisterClass(Inst, SrcC, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
LImm = (Insn >> 32);
MCOperand_CreateImm0(Inst, (LImm));
MCOperand_CreateImm0(Inst, (0));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLdLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstA, SrcB, LImm;
;
SrcB = decodeBField(Insn);
if (SrcB != 62) {
;
return MCDisassembler_Fail;
}
DstA = decodeAField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
LImm = (Insn >> 32);
MCOperand_CreateImm0(Inst, (LImm));
MCOperand_CreateImm0(Inst, (0));
return MCDisassembler_Success;
}
static DecodeStatus DecodeLdRLImmInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstA, SrcB;
;
DstA = decodeAField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstA, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
SrcB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, SrcB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
if (decodeCField(Insn) != 62) {
;
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, ((uint32_t)(Insn >> 32)));
return MCDisassembler_Success;
}
static DecodeStatus DecodeRegisterOrImm(MCInst *Inst, uint64_t Address,
const void *Decoder, uint64_t RegNum,
uint64_t Value)
{
if (30 == RegNum) {
MCOperand_CreateImm0(Inst, (Value));
return MCDisassembler_Success;
}
return DecodeGPR32RegisterClass(Inst, RegNum, Address, Decoder);
}
static DecodeStatus DecodeMoveHRegInstruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
;
uint64_t H = fieldFromInstruction_8(Insn, 5, 3) |
(fieldFromInstruction_8(Insn, 0, 2) << 3);
uint64_t G = fieldFromInstruction_8(Insn, 8, 3) |
(fieldFromInstruction_8(Insn, 3, 2) << 3);
if (MCDisassembler_Success != DecodeRegisterOrImm(Inst, Address,
Decoder, G, 0))
return MCDisassembler_Fail;
return DecodeRegisterOrImm(Inst, Address, Decoder, H, Insn >> 16u);
}
static DecodeStatus DecodeCCRU6Instruction(MCInst *Inst, uint64_t Insn,
uint64_t Address,
const void *Decoder)
{
unsigned DstB;
;
DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t U6Field = fieldFromInstruction_8(Insn, 6, 6);
MCOperand_CreateImm0(Inst, (U6Field));
uint64_t CCField = fieldFromInstruction_8(Insn, 0, 4);
MCOperand_CreateImm0(Inst, (CCField));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSOPwithRU6(MCInst *Inst, uint64_t Insn,
uint64_t Address, const void *Decoder)
{
unsigned DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t U6 = fieldFromInstruction_8(Insn, 6, 6);
MCOperand_CreateImm0(Inst, (U6));
return MCDisassembler_Success;
}
static DecodeStatus DecodeSOPwithRS12(MCInst *Inst, uint64_t Insn,
uint64_t Address, const void *Decoder)
{
unsigned DstB = decodeBField(Insn);
if (DecodeGPR32RegisterClass(Inst, DstB, Address, Decoder) == MCDisassembler_Fail) {
return MCDisassembler_Fail;
}
uint64_t Lower = fieldFromInstruction_8(Insn, 6, 6);
uint64_t Upper = fieldFromInstruction_8(Insn, 0, 5);
uint64_t Sign = fieldFromInstruction_8(Insn, 5, 1) ? -1 : 1;
uint64_t Result = Sign * ((Upper << 6) + Lower);
MCOperand_CreateImm0(Inst, (Result));
return MCDisassembler_Success;
}
static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t *Bytes,
size_t BytesLen, uint64_t Address, SStream *cStream)
{
DecodeStatus Result;
if (BytesLen < 2) {
*Size = 0;
return MCDisassembler_Fail;
}
uint8_t DecodeByte = (Bytes[1] & 0xF7) >> 3;
// 0x00 -> 0x07 are 32-bit instructions.
// 0x08 -> 0x1F are 16-bit instructions.
if (DecodeByte < 0x08) {
// 32-bit instruction.
if (BytesLen < 4) {
// Did we decode garbage?
*Size = 0;
return MCDisassembler_Fail;
}
if (BytesLen >= 8) {
// Attempt to decode 64-bit instruction.
uint64_t Insn64;
if (!readInstruction64(Bytes, BytesLen, Address, Size, &Insn64))
return MCDisassembler_Fail;
Result = decodeInstruction_8(DecoderTable64, Instr,
Insn64, Address, NULL);
if (MCDisassembler_Success == Result) {
;
return Result;
};
}
uint32_t Insn32;
if (!readInstruction32(Bytes, BytesLen, Address, Size, &Insn32)) {
return MCDisassembler_Fail;
}
// Calling the auto-generated decoder function.
return decodeInstruction_4(DecoderTable32, Instr, Insn32,
Address, NULL);
} else {
if (BytesLen >= 6) {
// Attempt to treat as instr. with limm data.
uint64_t Insn48;
if (!readInstruction48(Bytes, BytesLen, Address, Size, &Insn48))
return MCDisassembler_Fail;
Result = decodeInstruction_8(DecoderTable48, Instr,
Insn48, Address, NULL);
if (MCDisassembler_Success == Result) {
;
return Result;
};
}
uint32_t Insn16;
if (!readInstruction16(Bytes, BytesLen, Address, Size, &Insn16))
return MCDisassembler_Fail;
// Calling the auto-generated decoder function.
return decodeInstruction_2(DecoderTable16, Instr, Insn16,
Address, NULL);
}
}
DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes,
size_t BytesLen, uint64_t Address,
SStream *CS)
{
return getInstruction(MI, Size, Bytes, BytesLen, Address, CS);
}
#endif

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arch/ARC/ARCGenCSInsnEnum.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_INS_INVALID,
ARC_INS_h,
ARC_INS_PBR,
ARC_INS_ERROR_FLS,
ARC_INS_ERROR_FFS,
ARC_INS_PLDFI,
ARC_INS_STB_FAR,
ARC_INS_STH_FAR,
ARC_INS_ST_FAR,
ARC_INS_ADC,
ARC_INS_ADC_F,
ARC_INS_ADD_S,
ARC_INS_ADD,
ARC_INS_ADD_F,
ARC_INS_AND,
ARC_INS_AND_F,
ARC_INS_ASL_S,
ARC_INS_ASL,
ARC_INS_ASL_F,
ARC_INS_ASR_S,
ARC_INS_ASR,
ARC_INS_ASR_F,
ARC_INS_BCLR_S,
ARC_INS_BEQ_S,
ARC_INS_BGE_S,
ARC_INS_BGT_S,
ARC_INS_BHI_S,
ARC_INS_BHS_S,
ARC_INS_BL,
ARC_INS_BLE_S,
ARC_INS_BLO_S,
ARC_INS_BLS_S,
ARC_INS_BLT_S,
ARC_INS_BL_S,
ARC_INS_BMSK_S,
ARC_INS_BNE_S,
ARC_INS_B,
ARC_INS_BREQ_S,
ARC_INS_BRNE_S,
ARC_INS_BR,
ARC_INS_BSET_S,
ARC_INS_BTST_S,
ARC_INS_B_S,
ARC_INS_CMP_S,
ARC_INS_CMP,
ARC_INS_LD_S,
ARC_INS_MOV_S,
ARC_INS_EI_S,
ARC_INS_ENTER_S,
ARC_INS_FFS_F,
ARC_INS_FFS,
ARC_INS_FLS_F,
ARC_INS_FLS,
ARC_INS_ABS_S,
ARC_INS_ADD1_S,
ARC_INS_ADD2_S,
ARC_INS_ADD3_S,
ARC_INS_AND_S,
ARC_INS_BIC_S,
ARC_INS_BRK_S,
ARC_INS_EXTB_S,
ARC_INS_EXTH_S,
ARC_INS_JEQ_S,
ARC_INS_JL_S,
ARC_INS_JL_S_D,
ARC_INS_JNE_S,
ARC_INS_J_S,
ARC_INS_J_S_D,
ARC_INS_LSR_S,
ARC_INS_MPYUW_S,
ARC_INS_MPYW_S,
ARC_INS_MPY_S,
ARC_INS_NEG_S,
ARC_INS_NOP_S,
ARC_INS_NOT_S,
ARC_INS_OR_S,
ARC_INS_SEXB_S,
ARC_INS_SEXH_S,
ARC_INS_SUB_S,
ARC_INS_SUB_S_NE,
ARC_INS_SWI_S,
ARC_INS_TRAP_S,
ARC_INS_TST_S,
ARC_INS_UNIMP_S,
ARC_INS_XOR_S,
ARC_INS_LDB_S,
ARC_INS_LDH_S,
ARC_INS_J,
ARC_INS_JL,
ARC_INS_JLI_S,
ARC_INS_LDB_AB,
ARC_INS_LDB_AW,
ARC_INS_LDB_DI_AB,
ARC_INS_LDB_DI_AW,
ARC_INS_LDB_DI,
ARC_INS_LDB_X_AB,
ARC_INS_LDB_X_AW,
ARC_INS_LDB_X_DI_AB,
ARC_INS_LDB_X_DI_AW,
ARC_INS_LDB_X_DI,
ARC_INS_LDB_X,
ARC_INS_LDB,
ARC_INS_LDH_AB,
ARC_INS_LDH_AW,
ARC_INS_LDH_DI_AB,
ARC_INS_LDH_DI_AW,
ARC_INS_LDH_DI,
ARC_INS_LDH_S_X,
ARC_INS_LDH_X_AB,
ARC_INS_LDH_X_AW,
ARC_INS_LDH_X_DI_AB,
ARC_INS_LDH_X_DI_AW,
ARC_INS_LDH_X_DI,
ARC_INS_LDH_X,
ARC_INS_LDH,
ARC_INS_LDI_S,
ARC_INS_LD_AB,
ARC_INS_LD_AW,
ARC_INS_LD_DI_AB,
ARC_INS_LD_DI_AW,
ARC_INS_LD_DI,
ARC_INS_LD_S_AS,
ARC_INS_LD,
ARC_INS_LEAVE_S,
ARC_INS_LR,
ARC_INS_LSR,
ARC_INS_LSR_F,
ARC_INS_MAX,
ARC_INS_MAX_F,
ARC_INS_MIN,
ARC_INS_MIN_F,
ARC_INS_MOV_S_NE,
ARC_INS_MOV,
ARC_INS_MOV_F,
ARC_INS_MPYMU,
ARC_INS_MPYMU_F,
ARC_INS_MPYM,
ARC_INS_MPYM_F,
ARC_INS_MPY,
ARC_INS_MPY_F,
ARC_INS_NORMH_F,
ARC_INS_NORMH,
ARC_INS_NORM_F,
ARC_INS_NORM,
ARC_INS_OR,
ARC_INS_OR_F,
ARC_INS_POP_S,
ARC_INS_PUSH_S,
ARC_INS_ROR,
ARC_INS_ROR_F,
ARC_INS_RSUB,
ARC_INS_RSUB_F,
ARC_INS_SBC,
ARC_INS_SBC_F,
ARC_INS_SETEQ,
ARC_INS_SETEQ_F,
ARC_INS_SEXB_F,
ARC_INS_SEXB,
ARC_INS_SEXH_F,
ARC_INS_SEXH,
ARC_INS_STB_S,
ARC_INS_ST_S,
ARC_INS_STB_AB,
ARC_INS_STB_AW,
ARC_INS_STB_DI_AB,
ARC_INS_STB_DI_AW,
ARC_INS_STB_DI,
ARC_INS_STB,
ARC_INS_STH_AB,
ARC_INS_STH_AW,
ARC_INS_STH_DI_AB,
ARC_INS_STH_DI_AW,
ARC_INS_STH_DI,
ARC_INS_STH_S,
ARC_INS_STH,
ARC_INS_ST_AB,
ARC_INS_ST_AW,
ARC_INS_ST_DI_AB,
ARC_INS_ST_DI_AW,
ARC_INS_ST_DI,
ARC_INS_ST,
ARC_INS_SUB1,
ARC_INS_SUB1_F,
ARC_INS_SUB2,
ARC_INS_SUB2_F,
ARC_INS_SUB3,
ARC_INS_SUB3_F,
ARC_INS_SUB,
ARC_INS_SUB_F,
ARC_INS_XOR,
ARC_INS_XOR_F,

5494
arch/ARC/ARCGenCSMappingInsn.inc Normal file
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arch/ARC/ARCGenCSMappingInsnName.inc Normal file
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
"invalid", // ARC_INS_INVALID
"h", // ARC_INS_h
"pbr", // ARC_INS_PBR
"error_fls", // ARC_INS_ERROR_FLS
"error_ffs", // ARC_INS_ERROR_FFS
"pldfi", // ARC_INS_PLDFI
"STB_FAR", // ARC_INS_STB_FAR
"STH_FAR", // ARC_INS_STH_FAR
"ST_FAR", // ARC_INS_ST_FAR
"adc", // ARC_INS_ADC
"adc_f", // ARC_INS_ADC_F
"add_s", // ARC_INS_ADD_S
"add", // ARC_INS_ADD
"add_f", // ARC_INS_ADD_F
"and", // ARC_INS_AND
"and_f", // ARC_INS_AND_F
"asl_s", // ARC_INS_ASL_S
"asl", // ARC_INS_ASL
"asl_f", // ARC_INS_ASL_F
"asr_s", // ARC_INS_ASR_S
"asr", // ARC_INS_ASR
"asr_f", // ARC_INS_ASR_F
"bclr_s", // ARC_INS_BCLR_S
"beq_s", // ARC_INS_BEQ_S
"bge_s", // ARC_INS_BGE_S
"bgt_s", // ARC_INS_BGT_S
"bhi_s", // ARC_INS_BHI_S
"bhs_s", // ARC_INS_BHS_S
"bl", // ARC_INS_BL
"ble_s", // ARC_INS_BLE_S
"blo_s", // ARC_INS_BLO_S
"bls_s", // ARC_INS_BLS_S
"blt_s", // ARC_INS_BLT_S
"bl_s", // ARC_INS_BL_S
"bmsk_s", // ARC_INS_BMSK_S
"bne_s", // ARC_INS_BNE_S
"b", // ARC_INS_B
"breq_s", // ARC_INS_BREQ_S
"brne_s", // ARC_INS_BRNE_S
"br", // ARC_INS_BR
"bset_s", // ARC_INS_BSET_S
"btst_s", // ARC_INS_BTST_S
"b_s", // ARC_INS_B_S
"cmp_s", // ARC_INS_CMP_S
"cmp", // ARC_INS_CMP
"ld_s", // ARC_INS_LD_S
"mov_s", // ARC_INS_MOV_S
"ei_s", // ARC_INS_EI_S
"enter_s", // ARC_INS_ENTER_S
"ffs_f", // ARC_INS_FFS_F
"ffs", // ARC_INS_FFS
"fls_f", // ARC_INS_FLS_F
"fls", // ARC_INS_FLS
"abs_s", // ARC_INS_ABS_S
"add1_s", // ARC_INS_ADD1_S
"add2_s", // ARC_INS_ADD2_S
"add3_s", // ARC_INS_ADD3_S
"and_s", // ARC_INS_AND_S
"bic_s", // ARC_INS_BIC_S
"brk_s", // ARC_INS_BRK_S
"extb_s", // ARC_INS_EXTB_S
"exth_s", // ARC_INS_EXTH_S
"jeq_s", // ARC_INS_JEQ_S
"jl_s", // ARC_INS_JL_S
"jl_s_d", // ARC_INS_JL_S_D
"jne_s", // ARC_INS_JNE_S
"j_s", // ARC_INS_J_S
"j_s_d", // ARC_INS_J_S_D
"lsr_s", // ARC_INS_LSR_S
"mpyuw_s", // ARC_INS_MPYUW_S
"mpyw_s", // ARC_INS_MPYW_S
"mpy_s", // ARC_INS_MPY_S
"neg_s", // ARC_INS_NEG_S
"nop_s", // ARC_INS_NOP_S
"not_s", // ARC_INS_NOT_S
"or_s", // ARC_INS_OR_S
"sexb_s", // ARC_INS_SEXB_S
"sexh_s", // ARC_INS_SEXH_S
"sub_s", // ARC_INS_SUB_S
"sub_s_ne", // ARC_INS_SUB_S_NE
"swi_s", // ARC_INS_SWI_S
"trap_s", // ARC_INS_TRAP_S
"tst_s", // ARC_INS_TST_S
"unimp_s", // ARC_INS_UNIMP_S
"xor_s", // ARC_INS_XOR_S
"ldb_s", // ARC_INS_LDB_S
"ldh_s", // ARC_INS_LDH_S
"j", // ARC_INS_J
"jl", // ARC_INS_JL
"jli_s", // ARC_INS_JLI_S
"ldb_ab", // ARC_INS_LDB_AB
"ldb_aw", // ARC_INS_LDB_AW
"ldb_di_ab", // ARC_INS_LDB_DI_AB
"ldb_di_aw", // ARC_INS_LDB_DI_AW
"ldb_di", // ARC_INS_LDB_DI
"ldb_x_ab", // ARC_INS_LDB_X_AB
"ldb_x_aw", // ARC_INS_LDB_X_AW
"ldb_x_di_ab", // ARC_INS_LDB_X_DI_AB
"ldb_x_di_aw", // ARC_INS_LDB_X_DI_AW
"ldb_x_di", // ARC_INS_LDB_X_DI
"ldb_x", // ARC_INS_LDB_X
"ldb", // ARC_INS_LDB
"ldh_ab", // ARC_INS_LDH_AB
"ldh_aw", // ARC_INS_LDH_AW
"ldh_di_ab", // ARC_INS_LDH_DI_AB
"ldh_di_aw", // ARC_INS_LDH_DI_AW
"ldh_di", // ARC_INS_LDH_DI
"ldh_s_x", // ARC_INS_LDH_S_X
"ldh_x_ab", // ARC_INS_LDH_X_AB
"ldh_x_aw", // ARC_INS_LDH_X_AW
"ldh_x_di_ab", // ARC_INS_LDH_X_DI_AB
"ldh_x_di_aw", // ARC_INS_LDH_X_DI_AW
"ldh_x_di", // ARC_INS_LDH_X_DI
"ldh_x", // ARC_INS_LDH_X
"ldh", // ARC_INS_LDH
"ldi_s", // ARC_INS_LDI_S
"ld_ab", // ARC_INS_LD_AB
"ld_aw", // ARC_INS_LD_AW
"ld_di_ab", // ARC_INS_LD_DI_AB
"ld_di_aw", // ARC_INS_LD_DI_AW
"ld_di", // ARC_INS_LD_DI
"ld_s_as", // ARC_INS_LD_S_AS
"ld", // ARC_INS_LD
"leave_s", // ARC_INS_LEAVE_S
"lr", // ARC_INS_LR
"lsr", // ARC_INS_LSR
"lsr_f", // ARC_INS_LSR_F
"max", // ARC_INS_MAX
"max_f", // ARC_INS_MAX_F
"min", // ARC_INS_MIN
"min_f", // ARC_INS_MIN_F
"mov_s_ne", // ARC_INS_MOV_S_NE
"mov", // ARC_INS_MOV
"mov_f", // ARC_INS_MOV_F
"mpymu", // ARC_INS_MPYMU
"mpymu_f", // ARC_INS_MPYMU_F
"mpym", // ARC_INS_MPYM
"mpym_f", // ARC_INS_MPYM_F
"mpy", // ARC_INS_MPY
"mpy_f", // ARC_INS_MPY_F
"normh_f", // ARC_INS_NORMH_F
"normh", // ARC_INS_NORMH
"norm_f", // ARC_INS_NORM_F
"norm", // ARC_INS_NORM
"or", // ARC_INS_OR
"or_f", // ARC_INS_OR_F
"pop_s", // ARC_INS_POP_S
"push_s", // ARC_INS_PUSH_S
"ror", // ARC_INS_ROR
"ror_f", // ARC_INS_ROR_F
"rsub", // ARC_INS_RSUB
"rsub_f", // ARC_INS_RSUB_F
"sbc", // ARC_INS_SBC
"sbc_f", // ARC_INS_SBC_F
"seteq", // ARC_INS_SETEQ
"seteq_f", // ARC_INS_SETEQ_F
"sexb_f", // ARC_INS_SEXB_F
"sexb", // ARC_INS_SEXB
"sexh_f", // ARC_INS_SEXH_F
"sexh", // ARC_INS_SEXH
"stb_s", // ARC_INS_STB_S
"st_s", // ARC_INS_ST_S
"stb_ab", // ARC_INS_STB_AB
"stb_aw", // ARC_INS_STB_AW
"stb_di_ab", // ARC_INS_STB_DI_AB
"stb_di_aw", // ARC_INS_STB_DI_AW
"stb_di", // ARC_INS_STB_DI
"stb", // ARC_INS_STB
"sth_ab", // ARC_INS_STH_AB
"sth_aw", // ARC_INS_STH_AW
"sth_di_ab", // ARC_INS_STH_DI_AB
"sth_di_aw", // ARC_INS_STH_DI_AW
"sth_di", // ARC_INS_STH_DI
"sth_s", // ARC_INS_STH_S
"sth", // ARC_INS_STH
"st_ab", // ARC_INS_ST_AB
"st_aw", // ARC_INS_ST_AW
"st_di_ab", // ARC_INS_ST_DI_AB
"st_di_aw", // ARC_INS_ST_DI_AW
"st_di", // ARC_INS_ST_DI
"st", // ARC_INS_ST
"sub1", // ARC_INS_SUB1
"sub1_f", // ARC_INS_SUB1_F
"sub2", // ARC_INS_SUB2
"sub2_f", // ARC_INS_SUB2_F
"sub3", // ARC_INS_SUB3
"sub3_f", // ARC_INS_SUB3_F
"sub", // ARC_INS_SUB
"sub_f", // ARC_INS_SUB_F
"xor", // ARC_INS_XOR
"xor_f", // ARC_INS_XOR_F

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_OP_GROUP_Operand = 0,
ARC_OP_GROUP_PredicateOperand = 1,
ARC_OP_GROUP_MemOperandRI = 2,
ARC_OP_GROUP_BRCCPredicateOperand = 3,
ARC_OP_GROUP_CCOperand = 4,
ARC_OP_GROUP_U6 = 5,

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
ARC_REG_INVALID = 0,
ARC_REG_BLINK = 1,
ARC_REG_FP = 2,
ARC_REG_GP = 3,
ARC_REG_ILINK = 4,
ARC_REG_SP = 5,
ARC_REG_R0 = 6,
ARC_REG_R1 = 7,
ARC_REG_R2 = 8,
ARC_REG_R3 = 9,
ARC_REG_R4 = 10,
ARC_REG_R5 = 11,
ARC_REG_R6 = 12,
ARC_REG_R7 = 13,
ARC_REG_R8 = 14,
ARC_REG_R9 = 15,
ARC_REG_R10 = 16,
ARC_REG_R11 = 17,
ARC_REG_R12 = 18,
ARC_REG_R13 = 19,
ARC_REG_R14 = 20,
ARC_REG_R15 = 21,
ARC_REG_R16 = 22,
ARC_REG_R17 = 23,
ARC_REG_R18 = 24,
ARC_REG_R19 = 25,
ARC_REG_R20 = 26,
ARC_REG_R21 = 27,
ARC_REG_R22 = 28,
ARC_REG_R23 = 29,
ARC_REG_R24 = 30,
ARC_REG_R25 = 31,
ARC_REG_R30 = 32,
ARC_REG_R32 = 33,
ARC_REG_R33 = 34,
ARC_REG_R34 = 35,
ARC_REG_R35 = 36,
ARC_REG_R36 = 37,
ARC_REG_R37 = 38,
ARC_REG_R38 = 39,
ARC_REG_R39 = 40,
ARC_REG_R40 = 41,
ARC_REG_R41 = 42,
ARC_REG_R42 = 43,
ARC_REG_R43 = 44,
ARC_REG_R44 = 45,
ARC_REG_R45 = 46,
ARC_REG_R46 = 47,
ARC_REG_R47 = 48,
ARC_REG_R48 = 49,
ARC_REG_R49 = 50,
ARC_REG_R50 = 51,
ARC_REG_R51 = 52,
ARC_REG_R52 = 53,
ARC_REG_R53 = 54,
ARC_REG_R54 = 55,
ARC_REG_R55 = 56,
ARC_REG_R56 = 57,
ARC_REG_R57 = 58,
ARC_REG_R58 = 59,
ARC_REG_R59 = 60,
ARC_REG_R60 = 61,
ARC_REG_R61 = 62,
ARC_REG_R62 = 63,
ARC_REG_R63 = 64,
ARC_REG_STATUS32 = 65,
ARC_REG_ENDING, // 66

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#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
ARC_NoRegister,
ARC_BLINK = 1,
ARC_FP = 2,
ARC_GP = 3,
ARC_ILINK = 4,
ARC_SP = 5,
ARC_R0 = 6,
ARC_R1 = 7,
ARC_R2 = 8,
ARC_R3 = 9,
ARC_R4 = 10,
ARC_R5 = 11,
ARC_R6 = 12,
ARC_R7 = 13,
ARC_R8 = 14,
ARC_R9 = 15,
ARC_R10 = 16,
ARC_R11 = 17,
ARC_R12 = 18,
ARC_R13 = 19,
ARC_R14 = 20,
ARC_R15 = 21,
ARC_R16 = 22,
ARC_R17 = 23,
ARC_R18 = 24,
ARC_R19 = 25,
ARC_R20 = 26,
ARC_R21 = 27,
ARC_R22 = 28,
ARC_R23 = 29,
ARC_R24 = 30,
ARC_R25 = 31,
ARC_R30 = 32,
ARC_R32 = 33,
ARC_R33 = 34,
ARC_R34 = 35,
ARC_R35 = 36,
ARC_R36 = 37,
ARC_R37 = 38,
ARC_R38 = 39,
ARC_R39 = 40,
ARC_R40 = 41,
ARC_R41 = 42,
ARC_R42 = 43,
ARC_R43 = 44,
ARC_R44 = 45,
ARC_R45 = 46,
ARC_R46 = 47,
ARC_R47 = 48,
ARC_R48 = 49,
ARC_R49 = 50,
ARC_R50 = 51,
ARC_R51 = 52,
ARC_R52 = 53,
ARC_R53 = 54,
ARC_R54 = 55,
ARC_R55 = 56,
ARC_R56 = 57,
ARC_R57 = 58,
ARC_R58 = 59,
ARC_R59 = 60,
ARC_R60 = 61,
ARC_R61 = 62,
ARC_R62 = 63,
ARC_R63 = 64,
ARC_STATUS32 = 65,
NUM_TARGET_REGS // 66
};
// Register classes
enum {
ARC_SREGRegClassID = 0,
ARC_GPR_SRegClassID = 1,
ARC_GPR32RegClassID = 2,
ARC_GPR32_and_GPR_SRegClassID = 3,
};
#endif // GET_REGINFO_ENUM
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg ARCRegDiffLists[] = {
/* 0 */ 0,
};
static const uint16_t ARCSubRegIdxLists[] = {
/* 0 */ 0,
};
static const MCRegisterDesc ARCRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 235, 0, 0, 0, 0, 0 },
{ 247, 0, 0, 0, 1, 0 },
{ 250, 0, 0, 0, 2, 0 },
{ 241, 0, 0, 0, 3, 0 },
{ 253, 0, 0, 0, 4, 0 },
{ 24, 0, 0, 0, 5, 0 },
{ 47, 0, 0, 0, 6, 0 },
{ 83, 0, 0, 0, 7, 0 },
{ 110, 0, 0, 0, 8, 0 },
{ 133, 0, 0, 0, 9, 0 },
{ 156, 0, 0, 0, 10, 0 },
{ 175, 0, 0, 0, 11, 0 },
{ 194, 0, 0, 0, 12, 0 },
{ 213, 0, 0, 0, 13, 0 },
{ 232, 0, 0, 0, 14, 0 },
{ 0, 0, 0, 0, 15, 0 },
{ 27, 0, 0, 0, 16, 0 },
{ 50, 0, 0, 0, 17, 0 },
{ 86, 0, 0, 0, 18, 0 },
{ 113, 0, 0, 0, 19, 0 },
{ 136, 0, 0, 0, 20, 0 },
{ 159, 0, 0, 0, 21, 0 },
{ 178, 0, 0, 0, 22, 0 },
{ 197, 0, 0, 0, 23, 0 },
{ 216, 0, 0, 0, 24, 0 },
{ 4, 0, 0, 0, 25, 0 },
{ 31, 0, 0, 0, 26, 0 },
{ 54, 0, 0, 0, 27, 0 },
{ 90, 0, 0, 0, 28, 0 },
{ 117, 0, 0, 0, 29, 0 },
{ 140, 0, 0, 0, 30, 0 },
{ 8, 0, 0, 0, 31, 0 },
{ 58, 0, 0, 0, 32, 0 },
{ 94, 0, 0, 0, 33, 0 },
{ 121, 0, 0, 0, 34, 0 },
{ 144, 0, 0, 0, 35, 0 },
{ 163, 0, 0, 0, 36, 0 },
{ 182, 0, 0, 0, 37, 0 },
{ 201, 0, 0, 0, 38, 0 },
{ 220, 0, 0, 0, 39, 0 },
{ 12, 0, 0, 0, 40, 0 },
{ 35, 0, 0, 0, 41, 0 },
{ 71, 0, 0, 0, 42, 0 },
{ 98, 0, 0, 0, 43, 0 },
{ 125, 0, 0, 0, 44, 0 },
{ 148, 0, 0, 0, 45, 0 },
{ 167, 0, 0, 0, 46, 0 },
{ 186, 0, 0, 0, 47, 0 },
{ 205, 0, 0, 0, 48, 0 },
{ 224, 0, 0, 0, 49, 0 },
{ 16, 0, 0, 0, 50, 0 },
{ 39, 0, 0, 0, 51, 0 },
{ 75, 0, 0, 0, 52, 0 },
{ 102, 0, 0, 0, 53, 0 },
{ 129, 0, 0, 0, 54, 0 },
{ 152, 0, 0, 0, 55, 0 },
{ 171, 0, 0, 0, 56, 0 },
{ 190, 0, 0, 0, 57, 0 },
{ 209, 0, 0, 0, 58, 0 },
{ 228, 0, 0, 0, 59, 0 },
{ 20, 0, 0, 0, 60, 0 },
{ 43, 0, 0, 0, 61, 0 },
{ 79, 0, 0, 0, 62, 0 },
{ 106, 0, 0, 0, 63, 0 },
{ 62, 0, 0, 0, 64, 0 },
};
// SREG Register Class...
static const MCPhysReg SREG[] = {
ARC_STATUS32,
};
// SREG Bit set.
static const uint8_t SREGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
};
// GPR_S Register Class...
static const MCPhysReg GPR_S[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
};
// GPR_S Bit set.
static const uint8_t GPR_SBits[] = {
0xc0, 0x03, 0x3c,
};
// GPR32 Register Class...
static const MCPhysReg GPR32[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6, ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13, ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20, ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP, ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK, ARC_R32, ARC_R33, ARC_R34, ARC_R35, ARC_R36, ARC_R37, ARC_R38, ARC_R39, ARC_R40, ARC_R41, ARC_R42, ARC_R43, ARC_R44, ARC_R45, ARC_R46, ARC_R47, ARC_R48, ARC_R49, ARC_R50, ARC_R51, ARC_R52, ARC_R53, ARC_R54, ARC_R55, ARC_R56, ARC_R57, ARC_R58, ARC_R59, ARC_R60, ARC_R61, ARC_R62, ARC_R63,
};
// GPR32 Bit set.
static const uint8_t GPR32Bits[] = {
0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
};
// GPR32_and_GPR_S Register Class...
static const MCPhysReg GPR32_and_GPR_S[] = {
ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
};
// GPR32_and_GPR_S Bit set.
static const uint8_t GPR32_and_GPR_SBits[] = {
0xc0, 0x03, 0x3c,
};
static const MCRegisterClass ARCMCRegisterClasses[] = {
{ SREG, SREGBits, sizeof(SREGBits) },
{ GPR_S, GPR_SBits, sizeof(GPR_SBits) },
{ GPR32, GPR32Bits, sizeof(GPR32Bits) },
{ GPR32_and_GPR_S, GPR32_and_GPR_SBits, sizeof(GPR32_and_GPR_SBits) },
};
static const uint16_t ARCRegEncodingTable[] = {
0,
31,
27,
26,
29,
28,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
30,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
10,
};
#endif // GET_REGINFO_MC_DESC

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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
ARC_FeatureNORM = 0,
ARC_NumSubtargetFeatures = 1
};
#endif // GET_SUBTARGETINFO_ENUM

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInfo.h - Additional ARC Info --------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone helper functions and enum definitions for
// the ARC target useful for the compiler back-end and the MC libraries.
// As such, it deliberately does not include references to LLVM core
// code gen types, passes, etc..
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
#define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H
// Enums corresponding to ARC condition codes
// CS namespace begin: ARCCC
typedef enum ARCCondCode {
ARCCC_AL = 0x0,
ARCCC_EQ = 0x1,
ARCCC_NE = 0x2,
ARCCC_P = 0x3,
ARCCC_N = 0x4,
ARCCC_LO = 0x5,
ARCCC_HS = 0x6,
ARCCC_VS = 0x7,
ARCCC_VC = 0x8,
ARCCC_GT = 0x9,
ARCCC_GE = 0xa,
ARCCC_LT = 0xb,
ARCCC_LE = 0xc,
ARCCC_HI = 0xd,
ARCCC_LS = 0xe,
ARCCC_PNZ = 0xf,
ARCCC_Z = 0x11, // Low 4-bits = EQ
ARCCC_NZ = 0x12 // Low 4-bits = NE
} ARCCC_CondCode;
typedef enum BRCondCode {
ARCCC_BREQ = 0x0,
ARCCC_BRNE = 0x1,
ARCCC_BRLT = 0x2,
ARCCC_BRGE = 0x3,
ARCCC_BRLO = 0x4,
ARCCC_BRHS = 0x5
} ARCCC_BRCondCode;
// CS namespace end: ARCCC
// end namespace ARCCC
// end namespace llvm
#endif

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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInstPrinter.cpp - ARC MCInst to assembly syntax -------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARC MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../SStream.h"
#include "../../MCInst.h"
#include "../../MCInstPrinter.h"
#include "ARCInfo.h"
#include "ARCInstPrinter.h"
#include "ARCLinkage.h"
#include "ARCMapping.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
#include "ARCGenAsmWriter.inc"
static const char *ARCBRCondCodeToString(ARCCC_BRCondCode BRCC)
{
switch (BRCC) {
case ARCCC_BREQ:
return "eq";
case ARCCC_BRNE:
return "ne";
case ARCCC_BRLT:
return "lt";
case ARCCC_BRGE:
return "ge";
case ARCCC_BRLO:
return "lo";
case ARCCC_BRHS:
return "hs";
}
// CS_ASSERT(0 && "Unknown condition code passed");
return "";
}
static const char *ARCCondCodeToString(ARCCC_CondCode CC)
{
switch (CC) {
case ARCCC_EQ:
return "eq";
case ARCCC_NE:
return "ne";
case ARCCC_P:
return "p";
case ARCCC_N:
return "n";
case ARCCC_HS:
return "hs";
case ARCCC_LO:
return "lo";
case ARCCC_GT:
return "gt";
case ARCCC_GE:
return "ge";
case ARCCC_VS:
return "vs";
case ARCCC_VC:
return "vc";
case ARCCC_LT:
return "lt";
case ARCCC_LE:
return "le";
case ARCCC_HI:
return "hi";
case ARCCC_LS:
return "ls";
case ARCCC_PNZ:
return "pnz";
case ARCCC_AL:
return "al";
case ARCCC_NZ:
return "nz";
case ARCCC_Z:
return "z";
}
// CS_ASSERT(0 && "Unknown condition code passed");
return "";
}
static void printRegName(SStream *OS, MCRegister Reg)
{
SStream_concat0(OS, getRegisterName(Reg));
}
static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
{
printInstruction(MI, Address, O);
}
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_Operand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isReg(Op)) {
printRegName(O, MCOperand_getReg(Op));
} else if (MCOperand_isImm(Op)) {
SStream_concat(O, "%" PRId64, MCOperand_getImm(Op));
} else if (MCOperand_isExpr(Op)) {
printExpr(O, MCOperand_getExpr(Op));
}
}
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
{
printOperand(MI, OpNum, O);
}
static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_MemOperandRI, OpNum);
MCOperand *base = MCInst_getOperand(MI, (OpNum));
MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1));
CS_ASSERT((MCOperand_isReg(base) && "Base should be register."));
CS_ASSERT((MCOperand_isImm(offset) && "Offset should be immediate."));
printRegName(O, MCOperand_getReg(base));
SStream_concat(O, "%s", ",");
printInt64(O, MCOperand_getImm(offset));
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_PredicateOperand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
SStream_concat0(
O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(Op)));
}
static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum);
MCOperand *Op = MCInst_getOperand(MI, (OpNum));
CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate."));
SStream_concat0(O, ARCBRCondCodeToString(
(ARCCC_BRCondCode)MCOperand_getImm(Op)));
}
static void printCCOperand(MCInst *MI, int OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_CCOperand, OpNum);
SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm(
MCInst_getOperand(MI, (OpNum)))));
}
static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
unsigned Value = MCOperand_getImm(MO);
unsigned Value2 = Value >> ShiftBy;
if (Value2 > 0x3F || (Value2 << ShiftBy != Value)) {
CS_ASSERT((false && "instruction has wrong format"));
}
}
printOperand(MI, OpNum, O);
}
static void printU6(MCInst *MI, int OpNum, SStream *O)
{
add_cs_detail(MI, ARC_OP_GROUP_U6, OpNum);
printU6ShiftedBy(0, MI, OpNum, O);
}
void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
printInst(MI, Address, Annot, O);
}
const char *ARC_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}
#endif

58
arch/ARC/ARCInstPrinter.h Normal file
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@ -0,0 +1,58 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- ARCInstPrinter.h - Convert ARC MCInst to assembly syntax -*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
///
/// \file
/// This file contains the declaration of the ARCInstPrinter class,
/// which is used to print ARC MCInst to a .s file.
///
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
#define LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../SStream.h"
#include "../../MCInst.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
// Autogenerated by tblgen.
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
static void printRegName(SStream *OS, MCRegister Reg);
static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
static void printCCOperand(MCInst *MI, int OpNum, SStream *O);
static void printU6(MCInst *MI, int OpNum, SStream *O);
static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O);
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O);
static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, SStream *O);
;
// end namespace llvm
#endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H

23
arch/ARC/ARCLinkage.h Normal file
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@ -0,0 +1,23 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_LINKAGE_H
#define CS_ARC_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
const char *ARC_LLVM_getRegisterName(unsigned RegNo);
void ARC_LLVM_printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O);
DecodeStatus ARC_LLVM_getInstruction(MCInst *MI, uint64_t *Size,
const uint8_t *Bytes,
size_t BytesLen, uint64_t Address,
SStream *CS);
#endif // CS_ARC_LINKAGE_H

288
arch/ARC/ARCMapping.c Normal file
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@ -0,0 +1,288 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifdef CAPSTONE_HAS_ARC
#include <stdio.h>
#include <string.h>
#include <capstone/capstone.h>
#include <capstone/arc.h>
#include "../../Mapping.h"
#include "../../MCDisassembler.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"
#include "ARCMapping.h"
#include "ARCLinkage.h"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "ARCGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "ARCGenInstrInfo.inc"
void ARC_init_mri(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(MRI, ARCRegDesc,
sizeof(ARCRegDesc), 0, 0,
ARCMCRegisterClasses,
ARR_SIZE(ARCMCRegisterClasses),
0, 0, ARCRegDiffLists, 0,
ARCSubRegIdxLists,
ARR_SIZE(ARCSubRegIdxLists), 0);
}
const char *ARC_reg_name(csh handle, unsigned int reg)
{
return ARC_LLVM_getRegisterName(reg);
}
void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Not used by ARC. Information is set after disassembly.
}
static const char *const insn_name_maps[] = {
#include "ARCGenCSMappingInsnName.inc"
};
const char *ARC_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{ ARC_GRP_INVALID, NULL },
{ ARC_GRP_JUMP, "jump" },
{ ARC_GRP_CALL, "call" },
{ ARC_GRP_RET, "return" },
{ ARC_GRP_BRANCH_RELATIVE, "branch_relative" },
};
#endif
const char *ARC_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_arc *arc = &(insn->detail->arc);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < arc->op_count; i++) {
cs_arc_op *op = &(arc->operands[i]);
switch ((int)op->type) {
case ARC_OP_REG:
if ((op->access & CS_AC_READ) &&
!arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) &&
!arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
const insn_map arc_insns[] = {
#include "ARCGenCSMappingInsn.inc"
};
void ARC_set_instr_map_data(MCInst *MI)
{
map_cs_id(MI, arc_insns, ARR_SIZE(arc_insns));
map_implicit_reads(MI, arc_insns);
map_implicit_writes(MI, arc_insns);
map_groups(MI, arc_insns);
}
bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
uint64_t temp_size;
ARC_init_cs_detail(instr);
bool Result = ARC_LLVM_getInstruction(instr, &temp_size, code,
code_len, address, info) !=
MCDisassembler_Fail;
ARC_set_instr_map_data(instr);
*size = temp_size;
return Result;
}
void ARC_printer(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
MI->MRI = MRI;
ARC_LLVM_printInst(MI, MI->address, "", O);
}
void ARC_setup_op(cs_arc_op *op)
{
memset(op, 0, sizeof(cs_arc_op));
op->type = ARC_OP_INVALID;
}
void ARC_init_cs_detail(MCInst *MI)
{
if (!detail_is_set(MI)) {
return;
}
unsigned int i;
memset(get_detail(MI), 0,
offsetof(cs_detail, arc) + sizeof(cs_arc));
for (i = 0; i < ARR_SIZE(ARC_get_detail(MI)->operands);
i++)
ARC_setup_op(
&ARC_get_detail(MI)->operands[i]);
}
static const map_insn_ops insn_operands[] = {
#include "ARCGenCSMappingInsnOp.inc"
};
void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
arc_op_type ImmType, int64_t Imm)
{
if (!detail_is_set(MI))
return;
ARC_check_safe_inc(MI);
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_IMM);
CS_ASSERT(ImmType == ARC_OP_IMM);
ARC_get_detail_op(MI, 0)->type = ImmType;
ARC_get_detail_op(MI, 0)->imm = Imm;
ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
ARC_inc_op_count(MI);
}
void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg)
{
if (!detail_is_set(MI))
return;
ARC_check_safe_inc(MI);
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
ARC_get_detail_op(MI, 0)->type = ARC_OP_REG;
ARC_get_detail_op(MI, 0)->reg = Reg;
ARC_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
ARC_inc_op_count(MI);
}
void ARC_add_cs_detail(MCInst *MI, int op_group,
va_list args)
{
if (!detail_is_set(MI))
return;
unsigned OpNum = va_arg(args, unsigned);
cs_op_type op_type = map_get_op_type(MI, OpNum);
cs_op_type base_op_type = op_type;
cs_op_type offset_op_type;
// Fill cs_detail
switch (op_group) {
default:
printf("ERROR: Operand group %d not handled!\n", op_group);
CS_ASSERT_RET(0);
case ARC_OP_GROUP_Operand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else if (op_type == CS_OP_REG) {
ARC_set_detail_op_reg(MI, OpNum,
MCInst_getOpVal(MI, OpNum));
} else {
// Expression
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCOperand_getImm(MCInst_getOperand(MI, OpNum)));
}
break;
case ARC_OP_GROUP_PredicateOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_MemOperandRI:
if (base_op_type == CS_OP_REG) {
ARC_set_detail_op_reg(MI, OpNum,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
offset_op_type = map_get_op_type(MI, OpNum+1);
if (offset_op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum+1, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum+1));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_BRCCPredicateOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_CCOperand:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
case ARC_OP_GROUP_U6:
if (op_type == CS_OP_IMM) {
ARC_set_detail_op_imm(MI, OpNum, ARC_OP_IMM,
MCInst_getOpVal(MI, OpNum));
} else
CS_ASSERT(0 && "Op type not handled.");
break;
}
}
#endif

55
arch/ARC/ARCMapping.h Normal file
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@ -0,0 +1,55 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_MAP_H
#define CS_ARC_MAP_H
#include "../../Mapping.h"
#include "../../include/capstone/capstone.h"
#include "../../utils.h"
typedef enum {
#include "ARCGenCSOpGroup.inc"
} arc_op_group;
void ARC_init_mri(MCRegisterInfo *MRI);
// return name of register in friendly string
const char *ARC_reg_name(csh handle, unsigned int reg);
void ARC_printer(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
// given internal insn id, return public instruction ID
void ARC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *ARC_insn_name(csh handle, unsigned int id);
const char *ARC_group_name(csh handle, unsigned int id);
void ARC_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
// cs_detail related functions
void ARC_init_cs_detail(MCInst *MI);
void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum,
arc_op_type ImmType, int64_t Imm);
void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group,
va_list args);
static inline void add_cs_detail(MCInst *MI,
int /* arc_op_group */ op_group, ...)
{
if (!detail_is_set(MI))
return;
va_list args;
va_start(args, op_group);
ARC_add_cs_detail(MI, op_group, args);
va_end(args);
}
#endif

52
arch/ARC/ARCModule.c Normal file
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@ -0,0 +1,52 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifdef CAPSTONE_HAS_ARC
#include <capstone/capstone.h>
#include "ARCModule.h"
#include "../../MCRegisterInfo.h"
#include "../../cs_priv.h"
#include "ARCMapping.h"
cs_err ARC_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
ARC_init_mri(mri);
ud->printer = ARC_printer;
ud->printer_info = mri;
ud->reg_name = ARC_reg_name;
ud->insn_id = ARC_get_insn_id;
ud->insn_name = ARC_insn_name;
ud->group_name = ARC_group_name;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = ARC_reg_access;
#endif
ud->disasm = ARC_getInstruction;
return CS_ERR_OK;
}
cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch (type) {
case CS_OPT_MODE:
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
handle->syntax |= (int)value;
break;
default:
break;
}
return CS_ERR_OK;
}
#endif

12
arch/ARC/ARCModule.h Normal file
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@ -0,0 +1,12 @@
/* Capstone Disassembly Engine */
/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2024 */
#ifndef CS_ARC_MODULE_H
#define CS_ARC_MODULE_H
#include "../../utils.h"
cs_err ARC_global_init(cs_struct *ud);
cs_err ARC_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif

3
bindings/const_generator.py
View file

@ -8,7 +8,7 @@ INCL_DIR = '../include/capstone/'
include = ['arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h',
'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h', 'riscv.h', 'sh.h', 'tricore.h',
'alpha.h', 'hppa.h', 'loongarch.h', 'xtensa.h']
'alpha.h', 'hppa.h', 'loongarch.h', 'arc.h', 'xtensa.h']
template = {
'java': {
@ -63,6 +63,7 @@ template = {
'hppa.h': 'hppa',
'loongarch.h': 'loongarch',
'xtensa.h': 'xtensa',
'arc.h': 'arc',
'comment_open': '#',
'comment_close': '',
},

12
bindings/python/capstone/__init__.py
View file

@ -42,6 +42,7 @@ __all__ = [
'CS_ARCH_HPPA',
'CS_ARCH_LOONGARCH',
'CS_ARCH_XTENSA',
'CS_ARCH_ARC',
'CS_ARCH_ALL',
'CS_MODE_LITTLE_ENDIAN',
@ -270,7 +271,8 @@ CS_ARCH_ALPHA = 18
CS_ARCH_HPPA = 19
CS_ARCH_LOONGARCH = 20
CS_ARCH_XTENSA = 21
CS_ARCH_MAX = 21
CS_ARCH_ARC = 22
CS_ARCH_MAX = 22
CS_ARCH_ALL = 0xFFFF
# disasm mode
@ -563,7 +565,7 @@ def copy_ctypes_list(src):
# Weird import placement because these modules are needed by the below code but need the above functions
from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, \
riscv, sh, tricore, alpha, hppa, loongarch, xtensa
riscv, sh, tricore, alpha, hppa, loongarch, arc, xtensa
class _cs_arch(ctypes.Union):
@ -590,6 +592,7 @@ class _cs_arch(ctypes.Union):
('hppa', hppa.CsHPPA),
('loongarch', loongarch.CsLoongArch),
('xtensa', xtensa.CsXtensa),
('arc', arc.CsARC),
)
@ -974,6 +977,8 @@ class CsInsn(object):
(self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa)
elif arch == CS_ARCH_LOONGARCH:
(self.format, self.operands) = loongarch.get_arch_info(self._raw.detail.contents.arch.loongarch)
elif arch == CS_ARCH_ARC:
(self.operands) = arc.get_arch_info(self._raw.detail.contents.arch.arc)
elif arch == CS_ARCH_XTENSA:
(self.operands) = xtensa.get_arch_info(self._raw.detail.contents.arch.xtensa)
@ -1450,7 +1455,8 @@ def debug():
"m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA
'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH, 'xtensa': CS_ARCH_XTENSA,
'arc': CS_ARCH_ARC
}
all_archs = ""

39
bindings/python/capstone/arc.py Normal file
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@ -0,0 +1,39 @@
# Capstone Python bindings, by R33v0LT <sibirtsevdl@gmail.com>
import ctypes
from . import copy_ctypes_list
from .arc_const import *
class ARCOpValue(ctypes.Union):
_fields_ = (
('reg', ctypes.c_uint),
('imm', ctypes.c_int64)
)
class ARCOp(ctypes.Structure):
_fields_ = (
('type', ctypes.c_int),
('value', ARCOpValue),
('access', ctypes.c_uint)
)
@property
def imm(self):
return self.value.imm
@property
def reg(self):
return self.value.reg
# Instruction structure
class CsARC(ctypes.Structure):
_fields_ = (
('op_count', ctypes.c_uint8),
('operands', ARCOp * 8),
)
def get_arch_info(a):
return (copy_ctypes_list(a.operands[:a.op_count]))

274
bindings/python/capstone/arc_const.py Normal file
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@ -0,0 +1,274 @@
from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX, UINT8_MAX
# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arc_const.py]
ARC_OP_INVALID = CS_OP_INVALID
ARC_OP_REG = CS_OP_REG
ARC_OP_IMM = CS_OP_IMM
ARC_REG_INVALID = 0
ARC_REG_BLINK = 1
ARC_REG_FP = 2
ARC_REG_GP = 3
ARC_REG_ILINK = 4
ARC_REG_SP = 5
ARC_REG_R0 = 6
ARC_REG_R1 = 7
ARC_REG_R2 = 8
ARC_REG_R3 = 9
ARC_REG_R4 = 10
ARC_REG_R5 = 11
ARC_REG_R6 = 12
ARC_REG_R7 = 13
ARC_REG_R8 = 14
ARC_REG_R9 = 15
ARC_REG_R10 = 16
ARC_REG_R11 = 17
ARC_REG_R12 = 18
ARC_REG_R13 = 19
ARC_REG_R14 = 20
ARC_REG_R15 = 21
ARC_REG_R16 = 22
ARC_REG_R17 = 23
ARC_REG_R18 = 24
ARC_REG_R19 = 25
ARC_REG_R20 = 26
ARC_REG_R21 = 27
ARC_REG_R22 = 28
ARC_REG_R23 = 29
ARC_REG_R24 = 30
ARC_REG_R25 = 31
ARC_REG_R30 = 32
ARC_REG_R32 = 33
ARC_REG_R33 = 34
ARC_REG_R34 = 35
ARC_REG_R35 = 36
ARC_REG_R36 = 37
ARC_REG_R37 = 38
ARC_REG_R38 = 39
ARC_REG_R39 = 40
ARC_REG_R40 = 41
ARC_REG_R41 = 42
ARC_REG_R42 = 43
ARC_REG_R43 = 44
ARC_REG_R44 = 45
ARC_REG_R45 = 46
ARC_REG_R46 = 47
ARC_REG_R47 = 48
ARC_REG_R48 = 49
ARC_REG_R49 = 50
ARC_REG_R50 = 51
ARC_REG_R51 = 52
ARC_REG_R52 = 53
ARC_REG_R53 = 54
ARC_REG_R54 = 55
ARC_REG_R55 = 56
ARC_REG_R56 = 57
ARC_REG_R57 = 58
ARC_REG_R58 = 59
ARC_REG_R59 = 60
ARC_REG_R60 = 61
ARC_REG_R61 = 62
ARC_REG_R62 = 63
ARC_REG_R63 = 64
ARC_REG_STATUS32 = 65
ARC_REG_ENDING = 66
ARC_INS_INVALID = 0
ARC_INS_h = 1
ARC_INS_PBR = 2
ARC_INS_ERROR_FLS = 3
ARC_INS_ERROR_FFS = 4
ARC_INS_PLDFI = 5
ARC_INS_STB_FAR = 6
ARC_INS_STH_FAR = 7
ARC_INS_ST_FAR = 8
ARC_INS_ADC = 9
ARC_INS_ADC_F = 10
ARC_INS_ADD_S = 11
ARC_INS_ADD = 12
ARC_INS_ADD_F = 13
ARC_INS_AND = 14
ARC_INS_AND_F = 15
ARC_INS_ASL_S = 16
ARC_INS_ASL = 17
ARC_INS_ASL_F = 18
ARC_INS_ASR_S = 19
ARC_INS_ASR = 20
ARC_INS_ASR_F = 21
ARC_INS_BCLR_S = 22
ARC_INS_BEQ_S = 23
ARC_INS_BGE_S = 24
ARC_INS_BGT_S = 25
ARC_INS_BHI_S = 26
ARC_INS_BHS_S = 27
ARC_INS_BL = 28
ARC_INS_BLE_S = 29
ARC_INS_BLO_S = 30
ARC_INS_BLS_S = 31
ARC_INS_BLT_S = 32
ARC_INS_BL_S = 33
ARC_INS_BMSK_S = 34
ARC_INS_BNE_S = 35
ARC_INS_B = 36
ARC_INS_BREQ_S = 37
ARC_INS_BRNE_S = 38
ARC_INS_BR = 39
ARC_INS_BSET_S = 40
ARC_INS_BTST_S = 41
ARC_INS_B_S = 42
ARC_INS_CMP_S = 43
ARC_INS_CMP = 44
ARC_INS_LD_S = 45
ARC_INS_MOV_S = 46
ARC_INS_EI_S = 47
ARC_INS_ENTER_S = 48
ARC_INS_FFS_F = 49
ARC_INS_FFS = 50
ARC_INS_FLS_F = 51
ARC_INS_FLS = 52
ARC_INS_ABS_S = 53
ARC_INS_ADD1_S = 54
ARC_INS_ADD2_S = 55
ARC_INS_ADD3_S = 56
ARC_INS_AND_S = 57
ARC_INS_BIC_S = 58
ARC_INS_BRK_S = 59
ARC_INS_EXTB_S = 60
ARC_INS_EXTH_S = 61
ARC_INS_JEQ_S = 62
ARC_INS_JL_S = 63
ARC_INS_JL_S_D = 64
ARC_INS_JNE_S = 65
ARC_INS_J_S = 66
ARC_INS_J_S_D = 67
ARC_INS_LSR_S = 68
ARC_INS_MPYUW_S = 69
ARC_INS_MPYW_S = 70
ARC_INS_MPY_S = 71
ARC_INS_NEG_S = 72
ARC_INS_NOP_S = 73
ARC_INS_NOT_S = 74
ARC_INS_OR_S = 75
ARC_INS_SEXB_S = 76
ARC_INS_SEXH_S = 77
ARC_INS_SUB_S = 78
ARC_INS_SUB_S_NE = 79
ARC_INS_SWI_S = 80
ARC_INS_TRAP_S = 81
ARC_INS_TST_S = 82
ARC_INS_UNIMP_S = 83
ARC_INS_XOR_S = 84
ARC_INS_LDB_S = 85
ARC_INS_LDH_S = 86
ARC_INS_J = 87
ARC_INS_JL = 88
ARC_INS_JLI_S = 89
ARC_INS_LDB_AB = 90
ARC_INS_LDB_AW = 91
ARC_INS_LDB_DI_AB = 92
ARC_INS_LDB_DI_AW = 93
ARC_INS_LDB_DI = 94
ARC_INS_LDB_X_AB = 95
ARC_INS_LDB_X_AW = 96
ARC_INS_LDB_X_DI_AB = 97
ARC_INS_LDB_X_DI_AW = 98
ARC_INS_LDB_X_DI = 99
ARC_INS_LDB_X = 100
ARC_INS_LDB = 101
ARC_INS_LDH_AB = 102
ARC_INS_LDH_AW = 103
ARC_INS_LDH_DI_AB = 104
ARC_INS_LDH_DI_AW = 105
ARC_INS_LDH_DI = 106
ARC_INS_LDH_S_X = 107
ARC_INS_LDH_X_AB = 108
ARC_INS_LDH_X_AW = 109
ARC_INS_LDH_X_DI_AB = 110
ARC_INS_LDH_X_DI_AW = 111
ARC_INS_LDH_X_DI = 112
ARC_INS_LDH_X = 113
ARC_INS_LDH = 114
ARC_INS_LDI_S = 115
ARC_INS_LD_AB = 116
ARC_INS_LD_AW = 117
ARC_INS_LD_DI_AB = 118
ARC_INS_LD_DI_AW = 119
ARC_INS_LD_DI = 120
ARC_INS_LD_S_AS = 121
ARC_INS_LD = 122
ARC_INS_LEAVE_S = 123
ARC_INS_LR = 124
ARC_INS_LSR = 125
ARC_INS_LSR_F = 126
ARC_INS_MAX = 127
ARC_INS_MAX_F = 128
ARC_INS_MIN = 129
ARC_INS_MIN_F = 130
ARC_INS_MOV_S_NE = 131
ARC_INS_MOV = 132
ARC_INS_MOV_F = 133
ARC_INS_MPYMU = 134
ARC_INS_MPYMU_F = 135
ARC_INS_MPYM = 136
ARC_INS_MPYM_F = 137
ARC_INS_MPY = 138
ARC_INS_MPY_F = 139
ARC_INS_NORMH_F = 140
ARC_INS_NORMH = 141
ARC_INS_NORM_F = 142
ARC_INS_NORM = 143
ARC_INS_OR = 144
ARC_INS_OR_F = 145
ARC_INS_POP_S = 146
ARC_INS_PUSH_S = 147
ARC_INS_ROR = 148
ARC_INS_ROR_F = 149
ARC_INS_RSUB = 150
ARC_INS_RSUB_F = 151
ARC_INS_SBC = 152
ARC_INS_SBC_F = 153
ARC_INS_SETEQ = 154
ARC_INS_SETEQ_F = 155
ARC_INS_SEXB_F = 156
ARC_INS_SEXB = 157
ARC_INS_SEXH_F = 158
ARC_INS_SEXH = 159
ARC_INS_STB_S = 160
ARC_INS_ST_S = 161
ARC_INS_STB_AB = 162
ARC_INS_STB_AW = 163
ARC_INS_STB_DI_AB = 164
ARC_INS_STB_DI_AW = 165
ARC_INS_STB_DI = 166
ARC_INS_STB = 167
ARC_INS_STH_AB = 168
ARC_INS_STH_AW = 169
ARC_INS_STH_DI_AB = 170
ARC_INS_STH_DI_AW = 171
ARC_INS_STH_DI = 172
ARC_INS_STH_S = 173
ARC_INS_STH = 174
ARC_INS_ST_AB = 175
ARC_INS_ST_AW = 176
ARC_INS_ST_DI_AB = 177
ARC_INS_ST_DI_AW = 178
ARC_INS_ST_DI = 179
ARC_INS_ST = 180
ARC_INS_SUB1 = 181
ARC_INS_SUB1_F = 182
ARC_INS_SUB2 = 183
ARC_INS_SUB2_F = 184
ARC_INS_SUB3 = 185
ARC_INS_SUB3_F = 186
ARC_INS_SUB = 187
ARC_INS_SUB_F = 188
ARC_INS_XOR = 189
ARC_INS_XOR_F = 190
# Group of ARC instructions
ARC_GRP_INVALID = 0
ARC_GRP_JUMP = 1
ARC_GRP_CALL = 2
ARC_GRP_RET = 3
ARC_GRP_BRANCH_RELATIVE = 4
ARC_GRP_ENDING = 5

4
bindings/python/cstest_py/src/cstest_py/compare.py
View file

@ -28,6 +28,7 @@ from capstone import tricore_const
from capstone import alpha_const
from capstone import hppa_const
from capstone import loongarch_const
from capstone import arc_const
def cs_const_getattr(identifier: str):
@ -95,6 +96,9 @@ def cs_const_getattr(identifier: str):
if attr is not None:
return attr
attr = getattr(loongarch_const, identifier, None)
if attr is not None:
return attr
attr = getattr(arc_const, identifier, None)
if attr is not None:
return attr
raise ValueError(f"Python capstone doesn't have the constant: {identifier}")

31
bindings/python/cstest_py/src/cstest_py/details.py
View file

@ -32,6 +32,11 @@ from capstone.loongarch_const import (
LOONGARCH_OP_MEM,
)
from capstone.arc_const import (
ARC_OP_REG,
ARC_OP_IMM,
)
from capstone.m680x_const import (
M680X_OP_REGISTER,
M680X_OP_IMMEDIATE,
@ -270,6 +275,8 @@ def compare_details(insn: CsInsn, expected: dict) -> bool:
return test_expected_x86(actual, expected["x86"])
elif "m68k" in expected:
return test_expected_m68k(actual, expected["m68k"])
elif "arc" in expected:
return test_expected_arc(actual, expected["arc"])
return True
@ -1528,3 +1535,27 @@ def test_expected_wasm(actual: CsInsn, expected: dict) -> bool:
else:
raise ValueError("Operand type not handled.")
return True
def test_expected_arc(actual: CsInsn, expected: dict) -> bool:
if "operands" not in expected:
return True
elif not compare_uint32(
len(actual.operands), len(expected.get("operands")), "operands_count"
):
return False
for aop, eop in zip(actual.operands, expected["operands"]):
if not compare_enum(aop.type, eop.get("type"), "type"):
return False
if not compare_enum(aop.access, eop.get("access"), "access"):
return False
if aop.type == ARC_OP_REG:
if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
return False
elif aop.type == ARC_OP_IMM:
if not compare_int32(aop.imm, eop.get("imm"), "imm"):
return False
else:
raise ValueError("Operand type not handled.")
return True

2
bindings/python/tests/test_iter.py
View file

@ -33,6 +33,7 @@ HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18
HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
ARC_CODE = b"\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
@ -66,6 +67,7 @@ all_tests = (
(CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None),
(CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None),
(CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None),
(CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, ARC_CODE, "ARC", None),
)
# ## Test class Cs

3
bindings/python/tests/test_lite.py
View file

@ -27,6 +27,8 @@ SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x
XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
ARC_CODE = b"\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
@ -54,6 +56,7 @@ all_tests = (
(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
(CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, ARC_CODE, "ARC", None),
)

3
cmake.sh
View file

@ -66,6 +66,9 @@ case $1 in
LOONGARCH)
ARCH=LOONGARCH
;;
ARC)
ARCH=ARC
;;
*)
;;
esac

2
config.mk
View file

@ -4,7 +4,7 @@
################################################################################
# Specify which archs you want to compile in. By default, we build all archs.
CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa loongarch xtensa
CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa loongarch xtensa arc
################################################################################

51
cs.c
View file

@ -72,6 +72,7 @@
#include "arch/HPPA/HPPAModule.h"
#include "arch/LoongArch/LoongArchModule.h"
#include "arch/Xtensa/XtensaModule.h"
#include "arch/ARC/ARCModule.h"
typedef struct cs_arch_config {
// constructor initialization
@ -266,6 +267,13 @@ typedef struct cs_arch_config {
CS_MODE_XTENSA_ESP8266), \
}
#define CS_ARCH_CONFIG_ARC \
{ \
ARC_global_init, \
ARC_option, \
~(CS_MODE_LITTLE_ENDIAN), \
}
#ifdef CAPSTONE_USE_ARCH_REGISTRATION
static cs_arch_config arch_configs[MAX_ARCH];
static uint32_t all_arch;
@ -382,7 +390,12 @@ static const cs_arch_config arch_configs[MAX_ARCH] = {
{ NULL, NULL, 0 },
#endif
#ifdef CAPSTONE_HAS_XTENSA
CS_ARCH_CONFIG_XTENSA
CS_ARCH_CONFIG_XTENSA,
#else
{ NULL, NULL, 0 },
#endif
#ifdef CAPSTONE_HAS_ARC
CS_ARCH_CONFIG_ARC,
#else
{ NULL, NULL, 0 },
#endif
@ -456,7 +469,10 @@ static const uint32_t all_arch = 0
#ifdef CAPSTONE_HAS_XTENSA
| (1 << CS_ARCH_XTENSA)
#endif
;
#ifdef CAPSTONE_HAS_ARC
| (1 << CS_ARCH_ARC)
#endif
;
#endif
@ -683,12 +699,21 @@ void CAPSTONE_API cs_arch_register_loongarch(void)
#endif
}
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_arc(void)
{
#if defined(CAPSTONE_USE_ARCH_REGISTRATION) && defined(CAPSTONE_HAS_ARC)
CS_ARCH_REGISTER(ARC);
#endif
}
CAPSTONE_EXPORT
bool CAPSTONE_API cs_support(int query)
{
if (query == CS_ARCH_ALL)
return all_arch ==
((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) |
((1 << CS_ARCH_ARM) | (1 << CS_ARCH_AARCH64) |
(1 << CS_ARCH_MIPS) | (1 << CS_ARCH_X86) |
(1 << CS_ARCH_PPC) | (1 << CS_ARCH_SPARC) |
(1 << CS_ARCH_SYSTEMZ) | (1 << CS_ARCH_XCORE) |
@ -698,7 +723,8 @@ bool CAPSTONE_API cs_support(int query)
(1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) |
(1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) |
(1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA) |
(1 << CS_ARCH_LOONGARCH) | (1 << CS_ARCH_XTENSA));
(1 << CS_ARCH_LOONGARCH) | (1 << CS_ARCH_XTENSA) |
(1 << CS_ARCH_ARC));
if ((unsigned int)query < CS_ARCH_MAX)
return all_arch & (1 << query);
@ -1010,6 +1036,10 @@ static uint8_t skipdata_size(cs_struct *handle)
case CS_ARCH_LOONGARCH:
// LoongArch alignment is 4.
return 4;
case CS_ARCH_ARC:
// ARC instruction's length can be 2, 4, 6 or 8 bytes,
// therefore, skip 2 bytes
return 2;
}
}
@ -1764,6 +1794,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type)
if (insn->detail->loongarch.operands[i].type == (loongarch_op_type)op_type)
count++;
break;
case CS_ARCH_ARC:
for (i = 0; i < insn->detail->arc.op_count; i++)
if (insn->detail->arc.operands[i].type == (arc_op_type)op_type)
count++;
break;
}
return count;
@ -1971,6 +2006,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type,
return i;
}
break;
case CS_ARCH_ARC:
for (i = 0; i < insn->detail->arc.op_count; i++) {
if (insn->detail->arc.operands[i].type == (arc_op_type)op_type)
count++;
if (count == post)
return i;
}
break;
}
return -1;

11
cstool/cstool.c
View file

@ -240,6 +240,9 @@ static struct {
{ "esp32", "Xtensa ESP32", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32 },
{ "esp32s2", "Xtensa ESP32S2", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S2 },
{ "esp8266", "Xtensa ESP8266", CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP8266 },
{ "arc", "ARC Little-Endian", CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN },
{ NULL }
};
@ -325,6 +328,7 @@ static const char *get_arch_name(cs_arch arch)
case CS_ARCH_ALPHA: return "Alpha";
case CS_ARCH_HPPA: return "HPPA";
case CS_ARCH_LOONGARCH: return "LoongArch";
case CS_ARCH_ARC: return "ARC";
default: return NULL;
}
}
@ -444,6 +448,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
case CS_ARCH_XTENSA:
print_insn_detail_xtensa(handle, ins);
break;
case CS_ARCH_ARC:
print_insn_detail_arc(handle, ins);
break;
default: break;
}
@ -634,6 +641,10 @@ int main(int argc, char **argv)
printf("xtensa=1 ");
}
if (cs_support(CS_ARCH_ARC)) {
printf("arc=1 ");
}
printf("\n");
return 0;
case 'h':

1
cstool/cstool.h
View file

@ -23,5 +23,6 @@ void print_insn_detail_alpha(csh handle, cs_insn *ins);
void print_insn_detail_hppa(csh handle, cs_insn *ins);
void print_insn_detail_loongarch(csh handle, cs_insn *ins);
void print_insn_detail_xtensa(csh handle, cs_insn *ins);
void print_insn_detail_arc(csh handle, cs_insn *ins);
#endif //CAPSTONE_CSTOOL_CSTOOL_H_

74
cstool/cstool_arc.c Normal file
View file

@ -0,0 +1,74 @@
#include <stdio.h>
#include <capstone/capstone.h>
#include "cstool.h"
void print_insn_detail_arc(csh handle, cs_insn *ins)
{
cs_arc *arc;
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
uint8_t access;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
arc = &(ins->detail->arc);
if (arc->op_count)
printf("\top_count: %u\n", arc->op_count);
for (i = 0; i < arc->op_count; i++) {
cs_arc_op *op = &(arc->operands[i]);
switch ((int)op->type) {
default:
break;
case ARC_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
break;
case ARC_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%lx\n", i,
(long)op->imm);
break;
}
access = op->access;
switch (access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ | CS_AC_WRITE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
}
if (ins->detail->writeback)
printf("\tWrite-back: True\n");
/* print all registers that are involved in this instruction */
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for (i = 0; i < regs_read_count; i++)
printf(" %s",
cs_reg_name(handle, regs_read[i]));
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for (i = 0; i < regs_write_count; i++)
printf(" %s",
cs_reg_name(handle, regs_write[i]));
printf("\n");
}
}
}

344
include/capstone/arc.h Normal file
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@ -0,0 +1,344 @@
#ifndef CAPSTONE_ARC_H
#define CAPSTONE_ARC_H
#ifdef __cplusplus
extern "C" {
#endif
#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
#include <stdint.h>
#endif
#include "platform.h"
#include "cs_operand.h"
/// Operand type for instruction's operands
typedef enum arc_op_type {
ARC_OP_INVALID = CS_OP_INVALID, ///< Invalid
ARC_OP_REG = CS_OP_REG, ///< Register operand
ARC_OP_IMM = CS_OP_IMM, ///< Immediate operand
} arc_op_type;
/// Instruction operand
typedef struct cs_arc_op {
arc_op_type type; //< operand type
union {
unsigned int reg; /// register value for REG operand
int64_t imm; /// immediate value for IMM operand
};
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
enum cs_ac_type access;
} cs_arc_op;
#define NUM_ARC_OPS 8
/// Instruction structure
typedef struct cs_arc {
/// Number of operands of this instruction,
/// or 0 when instruction has no operand.
uint8_t op_count;
cs_arc_op operands[NUM_ARC_OPS]; ///< operands for this instruction.
} cs_arc;
/// ARC registers
typedef enum arc_reg {
// generated content <ARCGenCSRegEnum.inc> begin
// clang-format off
ARC_REG_INVALID = 0,
ARC_REG_BLINK = 1,
ARC_REG_FP = 2,
ARC_REG_GP = 3,
ARC_REG_ILINK = 4,
ARC_REG_SP = 5,
ARC_REG_R0 = 6,
ARC_REG_R1 = 7,
ARC_REG_R2 = 8,
ARC_REG_R3 = 9,
ARC_REG_R4 = 10,
ARC_REG_R5 = 11,
ARC_REG_R6 = 12,
ARC_REG_R7 = 13,
ARC_REG_R8 = 14,
ARC_REG_R9 = 15,
ARC_REG_R10 = 16,
ARC_REG_R11 = 17,
ARC_REG_R12 = 18,
ARC_REG_R13 = 19,
ARC_REG_R14 = 20,
ARC_REG_R15 = 21,
ARC_REG_R16 = 22,
ARC_REG_R17 = 23,
ARC_REG_R18 = 24,
ARC_REG_R19 = 25,
ARC_REG_R20 = 26,
ARC_REG_R21 = 27,
ARC_REG_R22 = 28,
ARC_REG_R23 = 29,
ARC_REG_R24 = 30,
ARC_REG_R25 = 31,
ARC_REG_R30 = 32,
ARC_REG_R32 = 33,
ARC_REG_R33 = 34,
ARC_REG_R34 = 35,
ARC_REG_R35 = 36,
ARC_REG_R36 = 37,
ARC_REG_R37 = 38,
ARC_REG_R38 = 39,
ARC_REG_R39 = 40,
ARC_REG_R40 = 41,
ARC_REG_R41 = 42,
ARC_REG_R42 = 43,
ARC_REG_R43 = 44,
ARC_REG_R44 = 45,
ARC_REG_R45 = 46,
ARC_REG_R46 = 47,
ARC_REG_R47 = 48,
ARC_REG_R48 = 49,
ARC_REG_R49 = 50,
ARC_REG_R50 = 51,
ARC_REG_R51 = 52,
ARC_REG_R52 = 53,
ARC_REG_R53 = 54,
ARC_REG_R54 = 55,
ARC_REG_R55 = 56,
ARC_REG_R56 = 57,
ARC_REG_R57 = 58,
ARC_REG_R58 = 59,
ARC_REG_R59 = 60,
ARC_REG_R60 = 61,
ARC_REG_R61 = 62,
ARC_REG_R62 = 63,
ARC_REG_R63 = 64,
ARC_REG_STATUS32 = 65,
ARC_REG_ENDING, // 66
// clang-format on
// generated content <ARCGenCSRegEnum.inc> end
} arc_reg;
/// ARC instruction
typedef enum arc_insn {
// generated content <ARCGenCSInsnEnum.inc> begin
// clang-format off
ARC_INS_INVALID,
ARC_INS_h,
ARC_INS_PBR,
ARC_INS_ERROR_FLS,
ARC_INS_ERROR_FFS,
ARC_INS_PLDFI,
ARC_INS_STB_FAR,
ARC_INS_STH_FAR,
ARC_INS_ST_FAR,
ARC_INS_ADC,
ARC_INS_ADC_F,
ARC_INS_ADD_S,
ARC_INS_ADD,
ARC_INS_ADD_F,
ARC_INS_AND,
ARC_INS_AND_F,
ARC_INS_ASL_S,
ARC_INS_ASL,
ARC_INS_ASL_F,
ARC_INS_ASR_S,
ARC_INS_ASR,
ARC_INS_ASR_F,
ARC_INS_BCLR_S,
ARC_INS_BEQ_S,
ARC_INS_BGE_S,
ARC_INS_BGT_S,
ARC_INS_BHI_S,
ARC_INS_BHS_S,
ARC_INS_BL,
ARC_INS_BLE_S,
ARC_INS_BLO_S,
ARC_INS_BLS_S,
ARC_INS_BLT_S,
ARC_INS_BL_S,
ARC_INS_BMSK_S,
ARC_INS_BNE_S,
ARC_INS_B,
ARC_INS_BREQ_S,
ARC_INS_BRNE_S,
ARC_INS_BR,
ARC_INS_BSET_S,
ARC_INS_BTST_S,
ARC_INS_B_S,
ARC_INS_CMP_S,
ARC_INS_CMP,
ARC_INS_LD_S,
ARC_INS_MOV_S,
ARC_INS_EI_S,
ARC_INS_ENTER_S,
ARC_INS_FFS_F,
ARC_INS_FFS,
ARC_INS_FLS_F,
ARC_INS_FLS,
ARC_INS_ABS_S,
ARC_INS_ADD1_S,
ARC_INS_ADD2_S,
ARC_INS_ADD3_S,
ARC_INS_AND_S,
ARC_INS_BIC_S,
ARC_INS_BRK_S,
ARC_INS_EXTB_S,
ARC_INS_EXTH_S,
ARC_INS_JEQ_S,
ARC_INS_JL_S,
ARC_INS_JL_S_D,
ARC_INS_JNE_S,
ARC_INS_J_S,
ARC_INS_J_S_D,
ARC_INS_LSR_S,
ARC_INS_MPYUW_S,
ARC_INS_MPYW_S,
ARC_INS_MPY_S,
ARC_INS_NEG_S,
ARC_INS_NOP_S,
ARC_INS_NOT_S,
ARC_INS_OR_S,
ARC_INS_SEXB_S,
ARC_INS_SEXH_S,
ARC_INS_SUB_S,
ARC_INS_SUB_S_NE,
ARC_INS_SWI_S,
ARC_INS_TRAP_S,
ARC_INS_TST_S,
ARC_INS_UNIMP_S,
ARC_INS_XOR_S,
ARC_INS_LDB_S,
ARC_INS_LDH_S,
ARC_INS_J,
ARC_INS_JL,
ARC_INS_JLI_S,
ARC_INS_LDB_AB,
ARC_INS_LDB_AW,
ARC_INS_LDB_DI_AB,
ARC_INS_LDB_DI_AW,
ARC_INS_LDB_DI,
ARC_INS_LDB_X_AB,
ARC_INS_LDB_X_AW,
ARC_INS_LDB_X_DI_AB,
ARC_INS_LDB_X_DI_AW,
ARC_INS_LDB_X_DI,
ARC_INS_LDB_X,
ARC_INS_LDB,
ARC_INS_LDH_AB,
ARC_INS_LDH_AW,
ARC_INS_LDH_DI_AB,
ARC_INS_LDH_DI_AW,
ARC_INS_LDH_DI,
ARC_INS_LDH_S_X,
ARC_INS_LDH_X_AB,
ARC_INS_LDH_X_AW,
ARC_INS_LDH_X_DI_AB,
ARC_INS_LDH_X_DI_AW,
ARC_INS_LDH_X_DI,
ARC_INS_LDH_X,
ARC_INS_LDH,
ARC_INS_LDI_S,
ARC_INS_LD_AB,
ARC_INS_LD_AW,
ARC_INS_LD_DI_AB,
ARC_INS_LD_DI_AW,
ARC_INS_LD_DI,
ARC_INS_LD_S_AS,
ARC_INS_LD,
ARC_INS_LEAVE_S,
ARC_INS_LR,
ARC_INS_LSR,
ARC_INS_LSR_F,
ARC_INS_MAX,
ARC_INS_MAX_F,
ARC_INS_MIN,
ARC_INS_MIN_F,
ARC_INS_MOV_S_NE,
ARC_INS_MOV,
ARC_INS_MOV_F,
ARC_INS_MPYMU,
ARC_INS_MPYMU_F,
ARC_INS_MPYM,
ARC_INS_MPYM_F,
ARC_INS_MPY,
ARC_INS_MPY_F,
ARC_INS_NORMH_F,
ARC_INS_NORMH,
ARC_INS_NORM_F,
ARC_INS_NORM,
ARC_INS_OR,
ARC_INS_OR_F,
ARC_INS_POP_S,
ARC_INS_PUSH_S,
ARC_INS_ROR,
ARC_INS_ROR_F,
ARC_INS_RSUB,
ARC_INS_RSUB_F,
ARC_INS_SBC,
ARC_INS_SBC_F,
ARC_INS_SETEQ,
ARC_INS_SETEQ_F,
ARC_INS_SEXB_F,
ARC_INS_SEXB,
ARC_INS_SEXH_F,
ARC_INS_SEXH,
ARC_INS_STB_S,
ARC_INS_ST_S,
ARC_INS_STB_AB,
ARC_INS_STB_AW,
ARC_INS_STB_DI_AB,
ARC_INS_STB_DI_AW,
ARC_INS_STB_DI,
ARC_INS_STB,
ARC_INS_STH_AB,
ARC_INS_STH_AW,
ARC_INS_STH_DI_AB,
ARC_INS_STH_DI_AW,
ARC_INS_STH_DI,
ARC_INS_STH_S,
ARC_INS_STH,
ARC_INS_ST_AB,
ARC_INS_ST_AW,
ARC_INS_ST_DI_AB,
ARC_INS_ST_DI_AW,
ARC_INS_ST_DI,
ARC_INS_ST,
ARC_INS_SUB1,
ARC_INS_SUB1_F,
ARC_INS_SUB2,
ARC_INS_SUB2_F,
ARC_INS_SUB3,
ARC_INS_SUB3_F,
ARC_INS_SUB,
ARC_INS_SUB_F,
ARC_INS_XOR,
ARC_INS_XOR_F,
// clang-format on
// generated content <ARCGenCSInsnEnum.inc> end
} arc_insn;
//> Group of ARC instructions
typedef enum arc_insn_group {
ARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
/// Generic groups
/// all jump instructions (conditional+direct+indirect jumps)
ARC_GRP_JUMP, ///< = CS_GRP_JUMP
/// all call instructions
ARC_GRP_CALL, ///< = CS_GRP_CALL
/// all return instructions
ARC_GRP_RET, ///< = CS_GRP_RET
/// all relative branching instructions
ARC_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
ARC_GRP_ENDING,
} arc_insn_group;
#ifdef __cplusplus
}
#endif
#endif

6
include/capstone/capstone.h
View file

@ -103,6 +103,7 @@ typedef enum cs_arch {
CS_ARCH_HPPA, ///< HPPA architecture
CS_ARCH_LOONGARCH, ///< LoongArch architecture
CS_ARCH_XTENSA, ///< Xtensa architecture
CS_ARCH_ARC, ///< ARC architecture
CS_ARCH_MAX,
CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
} cs_arch;
@ -359,6 +360,7 @@ typedef struct cs_opt_skipdata {
/// BPF: 8 bytes.
/// TriCore: 2 bytes.
/// LoongArch: 4 bytes.
/// ARC: 2 bytes.
cs_skipdata_cb_t callback; // default value is NULL
/// User-defined data to be passed to @callback function pointer.
@ -392,6 +394,7 @@ typedef struct cs_opt_skipdata {
#include "hppa.h"
#include "loongarch.h"
#include "xtensa.h"
#include "arc.h"
#define MAX_IMPL_W_REGS 47
#define MAX_IMPL_R_REGS 20
@ -449,6 +452,7 @@ typedef struct cs_detail {
cs_hppa hppa; ///< HPPA architecture
cs_loongarch loongarch; ///< LoongArch architecture
cs_xtensa xtensa; ///< Xtensa architecture
cs_arc arc; ///< ARC architecture
};
} cs_detail;
@ -600,6 +604,8 @@ CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_alpha(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_loongarch(void);
CAPSTONE_EXPORT
void CAPSTONE_API cs_arch_register_arc(void);
/**
This API can be used to either ask for archs supported by this library,

141
suite/MC/ARC/alu_arc.s.cs Normal file
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@ -0,0 +1,141 @@
# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
0x0,0x20,0x0,0x0 = add %r0, %r0, %r0
0x0,0x20,0x4,0x0 = add %r4, %r0, %r0
0x0,0x20,0x4,0x80 = add.f %r4, %r0, %r0
0x0,0x20,0xc2,0x0 = add %r2, %r0, %r3
0x0,0x20,0x2,0x1 = add %r2, %r0, %r4
0x0,0x27,0x2,0x1 = add %r2, %r7, %r4
0xc0,0x20,0x61,0x0 = add.eq %r0, %r0, 1
0xc0,0x26,0x2b,0x4 = add.lt %r6, %r6, 16
0xc0,0x27,0xec,0x17 = add.le %r15, %r15, 31
0xc0,0x20,0x69,0x0 = add.gt %r0, %r0, 1
0xc0,0x26,0x2a,0x4 = add.ge %r6, %r6, 16
0xc0,0x27,0xe3,0x17 = add.p %r15, %r15, 31
0xc0,0x20,0x64,0x0 = add.n %r0, %r0, 1
0xc0,0x26,0x27,0x4 = add.vs %r6, %r6, 16
0xc0,0x27,0xef,0x17 = add.pnz %r15, %r15, 31
0xc0,0x20,0x61,0x80 = add.eq.f %r0, %r0, 1
0xc0,0x26,0x2b,0x84 = add.lt.f %r6, %r6, 16
0xc0,0x27,0xec,0x97 = add.le.f %r15, %r15, 31
0xc0,0x20,0x69,0x80 = add.gt.f %r0, %r0, 1
0xc0,0x26,0x2a,0x84 = add.ge.f %r6, %r6, 16
0xc0,0x27,0xe3,0x97 = add.p.f %r15, %r15, 31
0xc0,0x20,0x64,0x80 = add.n.f %r0, %r0, 1
0xc0,0x26,0x27,0x84 = add.vs.f %r6, %r6, 16
0xc0,0x27,0xef,0x97 = add.pnz.f %r15, %r15, 31
0x4,0x27,0x2,0x1 = and %r2, %r7, %r4
0x4,0x27,0x2,0x81 = and.f %r2, %r7, %r4
0x44,0x27,0x2,0x1 = and %r2, %r7, 4
0x84,0x21,0xc3,0xf = and %r1, %r1, 255
0x84,0x21,0xc3,0x8f = and.f %r1, %r1, 255
0xc4,0x20,0x21,0x0 = and.eq %r0, %r0, 0
0xc4,0x26,0x2b,0x4 = and.lt %r6, %r6, 16
0xc4,0x27,0xec,0x17 = and.le %r15, %r15, 31
0xc4,0x20,0x29,0x0 = and.gt %r0, %r0, 0
0xc4,0x26,0x2a,0x4 = and.ge %r6, %r6, 16
0xc4,0x27,0xe3,0x17 = and.p %r15, %r15, 31
0xc4,0x20,0x24,0x0 = and.n %r0, %r0, 0
0xc4,0x26,0x27,0x4 = and.vs %r6, %r6, 16
0xc4,0x27,0xef,0x17 = and.pnz %r15, %r15, 31
0xc4,0x20,0x21,0x80 = and.eq.f %r0, %r0, 0
0xc4,0x26,0x2b,0x84 = and.lt.f %r6, %r6, 16
0xc4,0x27,0xec,0x97 = and.le.f %r15, %r15, 31
0xc4,0x20,0x29,0x80 = and.gt.f %r0, %r0, 0
0xc4,0x26,0x2a,0x84 = and.ge.f %r6, %r6, 16
0xc4,0x27,0xe3,0x97 = and.p.f %r15, %r15, 31
0xc4,0x20,0x24,0x80 = and.n.f %r0, %r0, 0
0xc4,0x26,0x27,0x84 = and.vs.f %r6, %r6, 16
0xc4,0x27,0xef,0x97 = and.pnz.f %r15, %r15, 31
0x40,0x29,0x81,0x0 = asl %r1, %r1, 2
0x0,0x28,0x0,0x0 = asl %r0, %r0, %r0
0x0,0x28,0x0,0x80 = asl.f %r0, %r0, %r0
0x42,0x2a,0xc1,0x7 = asr %r1, %r2, 31
0x42,0x2a,0xc1,0x87 = asr.f %r1, %r2, 31
0x42,0x2b,0xc1,0x1 = asr %r1, %r3, 7
0x2,0x29,0x81,0x0 = asr %r1, %r1, %r2
0x8,0x22,0x40,0x0 = max %r0, %r2, %r1
0x48,0x21,0xc0,0x3 = max %r0, %r1, 15
0x8,0x22,0x80,0xf,0x0,0x0,0xa0,0xf = max %r0, %r2, 4000
0x88,0x22,0xc3,0xf = max %r2, %r2, 255
0x5,0x20,0x92,0x2f,0x0,0x0,0x0,0xf0 = or %r18, %r16, 61440
0x5,0x20,0x92,0xaf,0x0,0x0,0x0,0xf0 = or.f %r18, %r16, 61440
0x5,0x21,0x81,0x3 = or %r1, %r1, %r14
0x5,0x26,0x41,0x10 = or %r1, %r14, %r1
0x85,0x21,0x2,0x0 = or %r1, %r1, 128
0x2,0x23,0x9c,0x3f,0x0,0x0,0x5c,0x0 = sub %sp, %fp, 92
0x2,0x27,0x2,0x1 = sub %r2, %r7, %r4
0x2,0x27,0x2,0x81 = sub.f %r2, %r7, %r4
0x2,0x26,0x0,0x20 = sub %r0, %r22, %r0
0x17,0x23,0x43,0x30 = sub1 %r3, %fp, %r1
0x58,0x23,0x43,0x34 = sub2 %r3, %fp, 17
0x99,0x23,0xff,0x3f = sub3 %fp, %fp, -1
0x99,0x23,0xff,0xbf = sub3.f %fp, %fp, -1
0xce,0x20,0xe2,0x7 = rsub.ne %r0, %r0, 31
0xce,0x20,0x61,0x0 = rsub.eq %r0, %r0, 1
0xce,0x26,0x2b,0x4 = rsub.lt %r6, %r6, 16
0xce,0x27,0xec,0x17 = rsub.le %r15, %r15, 31
0xce,0x20,0x69,0x0 = rsub.gt %r0, %r0, 1
0xce,0x26,0x2a,0x4 = rsub.ge %r6, %r6, 16
0xce,0x27,0xe3,0x17 = rsub.p %r15, %r15, 31
0xce,0x20,0x64,0x0 = rsub.n %r0, %r0, 1
0xce,0x26,0x27,0x4 = rsub.vs %r6, %r6, 16
0xce,0x27,0xef,0x17 = rsub.pnz %r15, %r15, 31
0xce,0x20,0xe2,0x87 = rsub.ne.f %r0, %r0, 31
0xce,0x20,0x61,0x80 = rsub.eq.f %r0, %r0, 1
0xce,0x26,0x2b,0x84 = rsub.lt.f %r6, %r6, 16
0xce,0x27,0xec,0x97 = rsub.le.f %r15, %r15, 31
0xce,0x20,0x69,0x80 = rsub.gt.f %r0, %r0, 1
0xce,0x26,0x2a,0x84 = rsub.ge.f %r6, %r6, 16
0xce,0x27,0xe3,0x97 = rsub.p.f %r15, %r15, 31
0xce,0x20,0x64,0x80 = rsub.n.f %r0, %r0, 1
0xce,0x26,0x27,0x84 = rsub.vs.f %r6, %r6, 16
0xce,0x27,0xef,0x97 = rsub.pnz.f %r15, %r15, 31
0x1,0x20,0x0,0x0 = adc %r0, %r0, %r0
0x1,0x20,0x4,0x0 = adc %r4, %r0, %r0
0x1,0x20,0x4,0x80 = adc.f %r4, %r0, %r0
0x1,0x20,0xc2,0x0 = adc %r2, %r0, %r3
0x1,0x20,0x2,0x1 = adc %r2, %r0, %r4
0x1,0x27,0x2,0x1 = adc %r2, %r7, %r4
0xc1,0x20,0x61,0x0 = adc.eq %r0, %r0, 1
0xc1,0x26,0x2b,0x4 = adc.lt %r6, %r6, 16
0xc1,0x27,0xec,0x17 = adc.le %r15, %r15, 31
0xc1,0x20,0x69,0x0 = adc.gt %r0, %r0, 1
0xc1,0x26,0x2a,0x4 = adc.ge %r6, %r6, 16
0xc1,0x27,0xe3,0x17 = adc.p %r15, %r15, 31
0xc1,0x20,0x64,0x0 = adc.n %r0, %r0, 1
0xc1,0x26,0x27,0x4 = adc.vs %r6, %r6, 16
0xc1,0x27,0xef,0x17 = adc.pnz %r15, %r15, 31
0xc1,0x20,0x61,0x80 = adc.eq.f %r0, %r0, 1
0xc1,0x26,0x2b,0x84 = adc.lt.f %r6, %r6, 16
0xc1,0x27,0xec,0x97 = adc.le.f %r15, %r15, 31
0xc1,0x20,0x69,0x80 = adc.gt.f %r0, %r0, 1
0xc1,0x26,0x2a,0x84 = adc.ge.f %r6, %r6, 16
0xc1,0x27,0xe3,0x97 = adc.p.f %r15, %r15, 31
0xc1,0x20,0x64,0x80 = adc.n.f %r0, %r0, 1
0xc1,0x26,0x27,0x84 = adc.vs.f %r6, %r6, 16
0xc1,0x27,0xef,0x97 = adc.pnz.f %r15, %r15, 31
0x3,0x20,0x0,0x0 = sbc %r0, %r0, %r0
0x3,0x20,0x4,0x0 = sbc %r4, %r0, %r0
0x3,0x20,0x4,0x80 = sbc.f %r4, %r0, %r0
0x3,0x20,0xc2,0x0 = sbc %r2, %r0, %r3
0x3,0x20,0x2,0x1 = sbc %r2, %r0, %r4
0x3,0x27,0x2,0x1 = sbc %r2, %r7, %r4
0xc3,0x20,0x61,0x0 = sbc.eq %r0, %r0, 1
0xc3,0x26,0x2b,0x4 = sbc.lt %r6, %r6, 16
0xc3,0x27,0xec,0x17 = sbc.le %r15, %r15, 31
0xc3,0x20,0x69,0x0 = sbc.gt %r0, %r0, 1
0xc3,0x26,0x2a,0x4 = sbc.ge %r6, %r6, 16
0xc3,0x27,0xe3,0x17 = sbc.p %r15, %r15, 31
0xc3,0x20,0x64,0x0 = sbc.n %r0, %r0, 1
0xc3,0x26,0x27,0x4 = sbc.vs %r6, %r6, 16
0xc3,0x27,0xef,0x17 = sbc.pnz %r15, %r15, 31
0xc3,0x20,0x61,0x80 = sbc.eq.f %r0, %r0, 1
0xc3,0x26,0x2b,0x84 = sbc.lt.f %r6, %r6, 16
0xc3,0x27,0xec,0x97 = sbc.le.f %r15, %r15, 31
0xc3,0x20,0x69,0x80 = sbc.gt.f %r0, %r0, 1
0xc3,0x26,0x2a,0x84 = sbc.ge.f %r6, %r6, 16
0xc3,0x27,0xe3,0x97 = sbc.p.f %r15, %r15, 31
0xc3,0x20,0x64,0x80 = sbc.n.f %r0, %r0, 1
0xc3,0x26,0x27,0x84 = sbc.vs.f %r6, %r6, 16
0xc3,0x27,0xef,0x97 = sbc.pnz.f %r15, %r15, 31

12
suite/MC/ARC/br_arc.s.cs Normal file
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@ -0,0 +1,12 @@
# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
0x3d,0xa,0x12,0x0 = brlt %r2, 0, 60
0x91,0xa,0x4,0x91 = brlo %r10, %r4, -112
0x2d,0xa,0x40,0x0 = breq %r2, %r1, 44
0xf1,0x8,0x11,0x80 = brne %r0, 0, -16
0x27,0xa,0x5,0x2 = brhs %r2, %r8, 38
0x30,0x1,0x2,0x0 = bne 304
0xc,0x1,0x1,0x0 = beq 268
0xa0,0x1,0xd,0x0 = bhi 416
0xbd,0x7,0xcf,0xff = b -68
0x0,0x0,0x9e,0x0 = b 4096

128
suite/MC/ARC/compact_arc.s.cs Normal file
View file

@ -0,0 +1,128 @@
# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
0x31,0x78 = abs_s %r0, %r1
0x58,0x61 = add_s %r0, %r1, %r2
0x63,0x70 = add_s %r0, %r0, %fp
0x67,0x77 = add_s %fp, %fp, -1
0x67,0x76 = add_s %fp, %fp, 6
0xc3,0x70,0x22,0x11,0x44,0x33 = add_s %r0, %r0, 287454020
0xc7,0x74,0x22,0x11,0x44,0x33 = add_s 0, 287454020, 4
0x90,0xc0 = add_s %r0, %sp, 64
0x40,0xe0 = add_s %r0, %r0, 64
0x7,0x69 = add_s %r0, %r1, 7
0xb0,0xc0 = add_s %sp, %sp, 64
0xff,0xcf = add_s %r0, %gp, -4
0xc,0x49 = add_s %r0, %r1, 4
0x8c,0x48 = add_s %r1, %r0, 4
0x34,0x78 = add1_s %r0, %r0, %r1
0x35,0x78 = add2_s %r0, %r0, %r1
0x36,0x78 = add3_s %r0, %r0, %r1
0x24,0x78 = and_s %r0, %r0, %r1
0x3b,0x78 = asl_s %r0, %r1
0x34,0x68 = asl_s %r1, %r0, 4
0x38,0x78 = asl_s %r0, %r0, %r1
0x10,0xb8 = asl_s %r0, %r0, 16
0x3c,0x78 = asr_s %r0, %r1
0x3c,0x68 = asr_s %r1, %r0, 4
0x3a,0x78 = asr_s %r0, %r0, %r1
0x50,0xb8 = asr_s %r0, %r0, 16
0x80,0xf0 = b_s 256
0xfe,0xf1 = b_s -4
0xfe,0xf3 = beq_s -4
0xfe,0xf5 = bne_s -4
0x3e,0xf6 = bgt_s -4
0x7e,0xf6 = bge_s -4
0xbe,0xf6 = blt_s -4
0xfe,0xf6 = ble_s -4
0x3e,0xf7 = bhi_s -4
0x7e,0xf7 = bhs_s -4
0xbe,0xf7 = blo_s -4
0xfe,0xf7 = bls_s -4
0xb8,0xb8 = bclr_s %r0, %r0, 24
0x26,0x78 = bic_s %r0, %r0, %r1
0xc0,0xff = bl_s -256
0xd8,0xb8 = bmsk_s %r0, %r0, 24
0xc0,0xe8 = brne_s %r0, 0, -128
0x40,0xe8 = breq_s %r0, 0, -128
0xff,0x7f = brk_s
0x98,0xb8 = bset_s %r0, %r0, 24
0xf8,0xb8 = btst_s %r0, 24
0x93,0x70 = cmp_s %r0, %sp
0x97,0x77 = cmp_s %sp, -1
0xc0,0xe2 = cmp_s %r2, 64
0x0,0x5e = ei_s 512
0xe0,0xc1 = enter_s 16
0x2f,0x78 = extb_s %r0, %r1
0x30,0x78 = exth_s %r0, %r1
0x0,0x78 = j_s [%r0]
0xe0,0x7e = j_s [%blink]
0x20,0x78 = j_s.d [%r0]
0xe0,0x7f = j_s.d [%blink]
0xe0,0x7c = jeq_s [%blink]
0xe0,0x7d = jne_s [%blink]
0x40,0x78 = jl_s [%r0]
0x60,0x78 = jl_s.d [%r0]
0x0,0x5a = jli_s 512
0x40,0x61 = ld_s %r0, [%r1, %r2]
0x10,0xc0 = ld_s %r0, [%sp, 64]
0x80,0xd0 = ld_s %r0, [%pcl, 512]
0x30,0x80 = ld_s %r1, [%r0, 64]
0x0,0xc9 = ld_s %r0, [%gp, -1024]
0x48,0x61 = ldb_s %r0, [%r1, %r2]
0x30,0xc0 = ldb_s %r0, [%sp, 64]
0x30,0x88 = ldb_s %r1, [%r0, 16]
0x0,0xcb = ldb_s %r0, [%gp, -256]
0x50,0x61 = ldh_s %r0, [%r1, %r2]
0x30,0x90 = ldh_s %r1, [%r0, 32]
0x0,0xcd = ldh_s %r0, [%gp, -512]
0x30,0x98 = ldh_s.x %r1, [%r0, 32]
0x36,0x40 = ld_s %r0, [%r17, 8]
0x36,0x41 = ld_s %r1, [%r17, 8]
0x36,0x42 = ld_s %r2, [%r17, 8]
0x36,0x43 = ld_s %r3, [%r17, 8]
0x40,0x49 = ld_s.as %r0, [%r1, %r2]
0x0,0x54 = ld_s %r1, [%gp, -1024]
0x88,0x50 = ldi_s %r0, [64]
0xc0,0xc1 = leave_s 16
0x3d,0x78 = lsr_s %r0, %r1
0x39,0x78 = lsr_s %r0, %r0, %r1
0x30,0xb8 = lsr_s %r0, %r0, 16
0x2e,0x77 = mov_s %r17, -1
0xcf,0x75 = mov_s 0, 5
0x3e,0x70 = mov_s.ne %r0, %r17
0xdf,0x70,0x0,0x0,0x0,0x4 = mov_s.ne %r0, 1024
0x80,0xd8 = mov_s %r0, 128
0x32,0x40 = mov_s %r16, %r17
0xd3,0x40,0x0,0x0,0x0,0x4 = mov_s %r16, 1024
0x3a,0x46 = mov_s 0, %r17
0xdb,0x46,0x0,0x0,0x0,0x4 = mov_s 0, 1024
0x2c,0x78 = mpy_s %r0, %r0, %r1
0x2a,0x78 = mpyuw_s %r0, %r0, %r1
0x29,0x78 = mpyw_s %r0, %r0, %r1
0x33,0x78 = neg_s %r0, %r1
0xe0,0x78 = nop_s
0x32,0x78 = not_s %r0, %r1
0x25,0x78 = or_s %r0, %r0, %r1
0xe1,0xc0 = pop_s %r0
0xd1,0xc0 = pop_s %blink
0xc1,0xc0 = push_s %r0
0xf1,0xc0 = push_s %blink
0x2d,0x78 = sexb_s %r0, %r1
0x2e,0x78 = sexh_s %r0, %r1
0x50,0xc0 = st_s %r0, [%sp, 64]
0x30,0xa0 = st_s %r1, [%r0, 64]
0x10,0x54 = st_s %r0, [%gp, -1024]
0x70,0xc0 = stb_s %r0, [%sp, 64]
0x30,0xa8 = stb_s %r1, [%r0, 16]
0x30,0xb0 = sth_s %r1, [%r0, 32]
0x2c,0x68 = sub_s %r1, %r0, 4
0xc0,0x78 = sub_s.ne %r0, %r0, %r0
0x22,0x78 = sub_s %r0, %r0, %r1
0x70,0xb8 = sub_s %r0, %r0, 16
0xb0,0xc1 = sub_s %sp, %sp, 64
0x50,0x49 = sub_s %r0, %r1, %r2
0xe0,0x7a = swi_s
0x1e,0x7c = trap_s 32
0x2b,0x78 = tst_s %r0, %r1
0xe0,0x79 = unimp_s
0x27,0x78 = xor_s %r0, %r0, %r1

38
suite/MC/ARC/ldst_arc.s.cs Normal file
View file

@ -0,0 +1,38 @@
# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
0x0,0x10,0x0,0x0 = ld %r0, [%r0,0]
0x0,0x10,0x0,0x1 = ldh %r0, [%r0,0]
0x0,0x10,0x80,0x0 = ldb %r0, [%r0,0]
0xc,0x10,0x1,0x0 = ld %r1, [%r0,12]
0xf4,0x13,0xe,0xb0 = ld %r14, [%fp,-12]
0xf4,0x10,0x3,0x80 = ld %r3, [%r0,-12]
0xf4,0x10,0x0,0x0 = ld %r0, [%r0,244]
0xf4,0x10,0x0,0x80 = ld %r0, [%r0,-12]
0x0,0x11,0x43,0x1 = ldh.x %r3, [%r1,0]
0x2,0x11,0x42,0x1 = ldh.x %r2, [%r1,2]
0x7c,0x13,0x42,0xb1 = ldh.x %r2, [%fp,-132]
0x30,0x20,0x80,0xf,0x0,0x0,0x0,0xfa = ld %r0, [%r0,64000]
0x0,0x16,0x6,0x70,0x0,0x0,0xb0,0xf9 = ld %r6, [63920]
0x23,0x1c,0x82,0x30 = stb %r2, [%sp,35]
0x0,0x1e,0xc0,0x71,0x0,0x0,0xb0,0xf9 = st %r7, [63920]
0x1,0x10,0x81,0x4 = ldb.ab %r1, [%r0,1]
0x1,0x18,0x92,0x0 = stb.ab %r2, [%r0,1]
0xc,0x10,0x3,0x5 = ldh.ab %r3, [%r0,12]
0x12,0x18,0x14,0x1 = sth.ab %r4, [%r0,18]
0x80,0x12,0x5,0x4 = ld.ab %r5, [%r2,128]
0x40,0x1a,0x90,0x1 = st.ab %r6, [%r2,64]
0x1,0x10,0x87,0x2 = ldb.aw %r7, [%r0,1]
0x1,0x18,0xa,0x2 = stb.aw %r8, [%r0,1]
0xc,0x10,0x3,0x3 = ldh.aw %r3, [%r0,12]
0x12,0x18,0xcc,0x0 = sth.aw %r3, [%r0,18]
0x80,0x12,0x6,0x2 = ld.aw %r6, [%r2,128]
0x40,0x1a,0x88,0x1 = st.aw %r6, [%r2,64]
0x8,0x10,0xc0,0x1a = ldb.x.di.aw %r0, [%r8,8]
0x40,0x19,0x32,0x10 = stb.di.ab %r0, [%r9,64]
0x6a,0x20,0x40,0x8 = lr %r0, [33]
0x6a,0x27,0x40,0x8 = lr %r7, [33]
0x6a,0x27,0x40,0x18 = lr %r15, [33]
0x6a,0x26,0x40,0x28 = lr %r22, [33]
0xaa,0x20,0x60,0x8 = lr %r0, [-33]
0xaa,0x20,0x41,0x8 = lr %r0, [97]
0xaa,0x20,0x61,0x8 = lr %r0, [-97]

51
suite/MC/ARC/misc_arc.c.cs Normal file
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@ -0,0 +1,51 @@
# CS_ARCH_ARC, CS_MODE_LITTLE_ENDIAN, None
0x8a,0x20,0xff,0xf = mov %r0, -1
0xa,0x24,0x80,0xf,0x0,0x0,0xff,0x7f = mov %r4, 32767
0xca,0x22,0x81,0x1 = mov.eq %r2, %r6
0xa,0x25,0x80,0x10 = mov %r13, %r2
0x4a,0x21,0x0,0x5 = mov %r1, 20
0xca,0x20,0x21,0x8 = mov.eq %r0, 32
0xca,0x20,0x22,0x0 = mov.ne %r0, 0
0xca,0x20,0x21,0x0 = mov.eq %r0, 0
0xca,0x26,0x2b,0x4 = mov.lt %r6, 16
0xca,0x27,0xec,0x17 = mov.le %r15, 31
0xca,0x20,0x29,0x0 = mov.gt %r0, 0
0xca,0x26,0x2a,0x4 = mov.ge %r6, 16
0xca,0x27,0xe3,0x17 = mov.p %r15, 31
0xca,0x20,0x24,0x0 = mov.n %r0, 0
0xca,0x26,0x27,0x4 = mov.vs %r6, 16
0xca,0x27,0xef,0x17 = mov.pnz %r15, 31
0x4a,0x20,0x0,0x80 = mov.f %r0, 0
0x4a,0x26,0x0,0x84 = mov.f %r6, 16
0x4a,0x27,0xc0,0x97 = mov.f %r15, 31
0xca,0x20,0x21,0x80 = mov.eq.f %r0, 0
0xca,0x26,0x2b,0x84 = mov.lt.f %r6, 16
0xca,0x27,0xec,0x97 = mov.le.f %r15, 31
0xca,0x20,0x29,0x80 = mov.gt.f %r0, 0
0xca,0x26,0x2a,0x84 = mov.ge.f %r6, 16
0xca,0x27,0xe3,0x97 = mov.p.f %r15, 31
0xca,0x20,0x24,0x80 = mov.n.f %r0, 0
0xca,0x26,0x27,0x84 = mov.vs.f %r6, 16
0xca,0x27,0xef,0x97 = mov.pnz.f %r15, 31
0xfc,0x1c,0xc8,0xb6 = st.aw %fp, [%sp,-4]
0x4,0x14,0x1b,0x34 = ld.ab %fp, [%sp,4]
0x16,0x8,0xcf,0xff = bl -2028
0xc,0x25,0x80,0x92 = cmp %r13, %r10
0x4c,0x26,0x0,0x90 = cmp %r14, 0
0x4c,0x27,0x40,0xa0 = cmp %r23, 1
0x22,0x20,0x40,0x5 = jl [%r21]
0x22,0x20,0x80,0xf,0x0,0x0,0x39,0x30 = jl 12345
0x20,0x20,0xc0,0x0 = j [%r3]
0x20,0x20,0x80,0xf,0x0,0x0,0x39,0x30 = j 12345
0x38,0x23,0x43,0x30 = seteq %r3, %fp, %r1
0x78,0x23,0x43,0x34 = seteq %r3, %fp, 17
0xb8,0x23,0xff,0x3f = seteq %fp, %fp, -1
0x2f,0x28,0x13,0x0 = fls %r0, %r0
0x2f,0x28,0x13,0x80 = fls.f %r0, %r0
0x2f,0x28,0x12,0x0 = ffs %r0, %r0
0x2f,0x28,0x12,0x80 = ffs.f %r0, %r0
0x2f,0x2f,0xd2,0x13 = ffs %r15, %r15
0x2f,0x2f,0xd2,0x93 = ffs.f %r15, %r15
0x2f,0x2e,0xc1,0x27 = norm %r22, %blink
0x2f,0x2f,0x88,0x4 = normh %r7, %r18

4
suite/auto-sync/src/autosync/Targets.py
View file

@ -12,6 +12,7 @@ TARGETS_LLVM_NAMING = [
"Mips",
"Xtensa",
"TriCore",
"ARC",
]
# Names of the target architecture as they are used in code and pretty much everywhere else.
@ -25,6 +26,7 @@ ARCH_LLVM_NAMING = [
"Mips",
"Xtensa",
"TriCore",
"ARC",
]
# Maps the target full name to the name used in code (and pretty much everywhere else).
@ -38,6 +40,7 @@ TARGET_TO_IN_CODE_NAME = {
"Mips": "Mips",
"Xtensa": "Xtensa",
"TriCore": "TriCore",
"ARC": "ARC",
"ARCH": "ARCH", # For testing
}
@ -52,5 +55,6 @@ TARGET_TO_DIR_NAME = {
"Mips": "Mips",
"Xtensa": "Xtensa",
"TriCore": "TriCore",
"ARC": "ARC",
"ARCH": "ARCH", # For testing
}

4
suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py
View file

@ -50,6 +50,7 @@ from autosync.cpptranslator.patches.IsPredicate import IsPredicate
from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm
from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough
from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable
from autosync.cpptranslator.patches.BadConditionCode import BadConditionCode
from autosync.cpptranslator.patches.LLVM_DEBUG import LLVM_DEBUG
from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction
from autosync.cpptranslator.patches.MethodTypeQualifier import MethodTypeQualifier
@ -154,6 +155,7 @@ class Translator:
Assert.__name__: 0, # ◁─────────┐ The llvm_unreachable calls are replaced with asserts.
LLVMUnreachable.__name__: 1, # ─┘ Those assert should stay.
LLVMFallThrough.__name__: 0,
BadConditionCode.__name__: 0,
LLVM_DEBUG.__name__: 0,
DeclarationInConditionalClause.__name__: 0,
StreamOperations.__name__: 0,
@ -289,6 +291,8 @@ class Translator:
patch = Assert(p)
case LLVMFallThrough.__name__:
patch = LLVMFallThrough(p)
case BadConditionCode.__name__:
patch = BadConditionCode(p)
case DeclarationInConditionalClause.__name__:
patch = DeclarationInConditionalClause(p)
case OutStreamParam.__name__:

15
suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py
View file

@ -78,6 +78,7 @@ from autosync.cpptranslator.patches.TemplateRefs import TemplateRefs
from autosync.cpptranslator.patches.UseMarkup import UseMarkup
from autosync.cpptranslator.patches.UsingDeclaration import UsingDeclaration
from autosync.cpptranslator.TemplateCollector import TemplateCollector
from autosync.cpptranslator.patches.BadConditionCode import BadConditionCode
from autosync.Helper import get_path
from autosync.cpptranslator.patches.isUInt import IsUInt
@ -296,6 +297,13 @@ public:
b"fieldFromInstruction_4(Val, 0, 4)",
)
syntax = b"static unsigned function(unsigned Insn) { return fieldFromInstruction(Insn, 6, 6); }"
self.check_patching_result(
patch,
syntax,
b"fieldFromInstruction_4(Insn, 6, 6)",
)
def test_getnumoperands(self):
patch = GetNumOperands(0)
syntax = b"MI.getNumOperands();"
@ -612,3 +620,10 @@ public:
patch = IsUInt(0)
syntax = b"isUInt<RegUnitBits>(FirstRU);"
self.check_patching_result(patch, syntax, b"isUIntN(RegUnitBits, FirstRU)")
def test_badconditioncode(self):
patch = BadConditionCode(0)
syntax = b"return BadConditionCode(BRCC)"
self.check_patching_result(
patch, syntax, b'CS_ASSERT(0 && "Unknown condition code passed");'
)

26
suite/auto-sync/src/autosync/cpptranslator/arch_config.json
View file

@ -264,5 +264,31 @@
"files_for_template_search": [],
"templates_with_arg_deduction": [],
"manually_edited_files": []
},
"ARC": {
"files_to_translate": [
{
"in": "{LLVM_ROOT}/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp",
"out": "ARCDisassembler.c"
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp",
"out": "ARCInstPrinter.c"
},{
"in": "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h",
"out": "ARCInstPrinter.h"
},
{
"in": "{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInfo.h",
"out": "ARCInfo.h"
}
],
"files_for_template_search": [
"{CPP_INC_OUT_DIR}/ARCGenDisassemblerTables.inc",
"{CPP_INC_OUT_DIR}/ARCGenAsmWriter.inc",
"{LLVM_ROOT}/llvm/lib/Target/ARC/Disassembler/ARCDisassembler.cpp",
"{LLVM_ROOT}/llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.cpp"
],
"templates_with_arg_deduction": [],
"manually_edited_files": []
}
}

32
suite/auto-sync/src/autosync/cpptranslator/patches/BadConditionCode.py Normal file
View file

@ -0,0 +1,32 @@
# Copyright © 2024 Dmitry Sibitsev <sibirtsevdl@gmail.com>
# SPDX-License-Identifier: BSD-3
from tree_sitter import Node
from autosync.cpptranslator.patches.Patch import Patch
class BadConditionCode(Patch):
"""
Patch return BadConditionCode
to CS_ASSERT(0 && "Unknown condition code passed")
"""
def __init__(self, priority: int):
super().__init__(priority)
def get_search_pattern(self) -> str:
return (
"(return_statement "
" (call_expression "
' (identifier) @fcn_name (#eq? @fcn_name "BadConditionCode")'
" (argument_list)"
" )"
") @bad_condition_code"
)
def get_main_capture_name(self) -> str:
return "bad_condition_code"
def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes:
return b'CS_ASSERT(0 && "Unknown condition code passed");'

10
suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py
View file

@ -47,14 +47,20 @@ class FieldFromInstr(Patch):
else:
# Get the Val/Inst parameter.
# Its type determines the instruction width.
inst_param: Node = param_list_caller.named_children[1]
if len(param_list_caller.named_children) == 1:
# If function just return fieldFromInstruction(...)
inst_param: Node = param_list_caller.named_children[0]
else:
inst_param = param_list_caller.named_children[1]
inst_param_text = get_text(src, inst_param.start_byte, inst_param.end_byte)
# Search for the 'Inst' parameter and determine its type
# and with it the width of the instruction.
inst_type = inst_param_text.split(b" ")[0]
if inst_type:
if inst_type in [b"unsigned", b"uint32_t"]:
if inst_type in [b"uint64_t"]:
inst_width = b"8"
elif inst_type in [b"unsigned", b"uint32_t"]:
inst_width = b"4"
elif inst_type in [b"uint16_t"]:
inst_width = b"2"

29
suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py
View file

@ -70,6 +70,8 @@ class Includes(Patch):
return res + get_SystemZ_includes(filename) + get_general_macros()
case "Xtensa":
return res + get_Xtensa_includes(filename) + get_general_macros()
case "ARC":
return res + get_ARC_includes(filename) + get_general_macros()
case "TEST_ARCH":
return res + b"test_output"
case _:
@ -416,6 +418,33 @@ def get_Xtensa_includes(filename: str) -> bytes:
return b""
def get_ARC_includes(filename: str) -> bytes:
match filename:
case "ARCDisassembler.cpp":
return (
b'#include "../../MCInst.h"\n'
+ b'#include "../../SStream.h"\n'
+ b'#include "../../MCDisassembler.h"\n'
+ b'#include "../../MCFixedLenDisassembler.h"\n'
+ b'#include "../../MathExtras.h"\n'
+ b'#include "../../utils.h"\n'
)
case "ARCInstPrinter.cpp":
return (
b'#include "../../SStream.h"\n'
+ b'#include "../../MCInst.h"\n'
+ b'#include "../../MCInstPrinter.h"\n'
+ b'#include "ARCInfo.h"\n'
+ b'#include "ARCInstPrinter.h"\n'
+ b'#include "ARCLinkage.h"\n'
+ b'#include "ARCMapping.h"\n'
)
case "ARCInstPrinter.h":
return b'#include "../../SStream.h"\n' + b'#include "../../MCInst.h"\n'
log.fatal(f"No includes given for ARC source file: {filename}")
exit(1)
def get_general_macros():
return (
b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n"

3
suite/capstone_get_setup.c
View file

@ -85,6 +85,9 @@ int main()
if (cs_support(CS_ARCH_XTENSA)) {
printf("xtensa=1 ");
}
if (cs_support(CS_ARCH_ARC)) {
printf("arc=1 ");
}
printf("\n");
return 0;

5
suite/cstest/include/test_detail.h
View file

@ -32,6 +32,7 @@
#include "test_detail_x86.h"
#include "test_detail_m68k.h"
#include "test_detail_xtensa.h"
#include "test_detail_arc.h"
#include "test_compare.h"
#include <capstone/capstone.h>
#include <cyaml/cyaml.h>
@ -61,6 +62,7 @@ typedef struct {
TestDetailX86 *x86;
TestDetailM68K *m68k;
TestDetailXtensa *xtensa;
TestDetailARC *arc;
char **regs_read;
uint8_t regs_read_count;
@ -150,6 +152,9 @@ static const cyaml_schema_field_t test_detail_mapping_schema[] = {
CYAML_FIELD_MAPPING_PTR(
"xtensa", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
xtensa, test_detail_xtensa_mapping_schema),
CYAML_FIELD_MAPPING_PTR(
"arc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
arc, test_detail_arc_mapping_schema),
CYAML_FIELD_SEQUENCE("regs_read",
CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetail, regs_read, &single_string_schema, 0, 255),

60
suite/cstest/include/test_detail_arc.h Normal file
View file

@ -0,0 +1,60 @@
// Copyright © 2024 Sibirtsev Dmitry <sibirtsevdl@gmail.com>
// SPDX-License-Identifier: BSD-3
#ifndef TEST_DETAIL_ARC_H
#define TEST_DETAIL_ARC_H
#include "test_compare.h"
#include <cyaml/cyaml.h>
#include <capstone/capstone.h>
typedef struct {
char *type;
char *access;
char *reg;
int64_t imm;
} TestDetailARCOp;
static const cyaml_schema_field_t test_detail_arc_op_mapping_schema[] = {
CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetailARCOp, type, 0, CYAML_UNLIMITED),
CYAML_FIELD_STRING_PTR("access",
CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetailARCOp, access, 0, CYAML_UNLIMITED),
CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetailARCOp, reg, 0, CYAML_UNLIMITED),
CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailARCOp, imm),
CYAML_FIELD_END
};
static const cyaml_schema_value_t test_detail_arc_op_schema = {
CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailARCOp,
test_detail_arc_op_mapping_schema),
};
typedef struct {
TestDetailARCOp **operands;
uint32_t operands_count;
} TestDetailARC;
static const cyaml_schema_field_t test_detail_arc_mapping_schema[] = {
CYAML_FIELD_SEQUENCE(
"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
TestDetailARC, operands, &test_detail_arc_op_schema, 0,
CYAML_UNLIMITED), // 0-MAX options
CYAML_FIELD_END
};
TestDetailARC *test_detail_arc_new();
TestDetailARC *test_detail_arc_clone(const TestDetailARC *detail);
void test_detail_arc_free(TestDetailARC *detail);
TestDetailARCOp *test_detail_arc_op_new();
TestDetailARCOp *test_detail_arc_op_clone(const TestDetailARCOp *detail);
void test_detail_arc_op_free(TestDetailARCOp *detail);
bool test_expected_arc(csh *handle, const cs_arc *actual,
const TestDetailARC *expected);
#endif // TEST_DETAIL_ARC_H

8
suite/cstest/include/test_mapping.h
View file

@ -18,6 +18,7 @@ static const cs_enum_id_map test_arch_map[] = {
{ .str = "AArch64", .val = CS_ARCH_AARCH64 },
{ .str = "CS_ARCH_AARCH64", .val = CS_ARCH_AARCH64 },
{ .str = "CS_ARCH_ALPHA", .val = CS_ARCH_ALPHA },
{ .str = "CS_ARCH_ARC", .val = CS_ARCH_ARC },
{ .str = "CS_ARCH_ARM", .val = CS_ARCH_ARM },
{ .str = "CS_ARCH_BPF", .val = CS_ARCH_BPF },
{ .str = "CS_ARCH_EVM", .val = CS_ARCH_EVM },
@ -40,6 +41,7 @@ static const cs_enum_id_map test_arch_map[] = {
{ .str = "CS_ARCH_XTENSA", .val = CS_ARCH_XTENSA },
{ .str = "aarch64", .val = CS_ARCH_AARCH64 },
{ .str = "alpha", .val = CS_ARCH_ALPHA },
{ .str = "arc", .val = CS_ARCH_ARC },
{ .str = "arm", .val = CS_ARCH_ARM },
{ .str = "bpf", .val = CS_ARCH_BPF },
{ .str = "evm", .val = CS_ARCH_EVM },
@ -314,6 +316,8 @@ static const cs_enum_id_map cs_enum_map[] = {
{ .str = "AArch64CC_VS", .val = AArch64CC_VS },
{ .str = "ALPHA_OP_IMM", .val = ALPHA_OP_IMM },
{ .str = "ALPHA_OP_REG", .val = ALPHA_OP_REG },
{ .str = "ARC_OP_IMM", .val = ARC_OP_IMM },
{ .str = "ARC_OP_REG", .val = ARC_OP_REG },
{ .str = "ARMCC_AL", .val = ARMCC_AL },
{ .str = "ARMCC_EQ", .val = ARMCC_EQ },
{ .str = "ARMCC_GE", .val = ARMCC_GE },
@ -462,6 +466,10 @@ static const cs_enum_id_map cs_enum_map[] = {
{ .str = "Alpha_GRP_CALL", .val = Alpha_GRP_CALL },
{ .str = "Alpha_GRP_ENDING", .val = Alpha_GRP_ENDING },
{ .str = "Alpha_GRP_JUMP", .val = Alpha_GRP_JUMP },
{ .str = "ARC_GRP_JUMP", .val = ARC_GRP_JUMP },
{ .str = "ARC_GRP_CALL", .val = ARC_GRP_CALL },
{ .str = "ARC_GRP_RET", .val = ARC_GRP_RET },
{ .str = "ARC_GRP_BRANCH_RELATIVE", .val = ARC_GRP_BRANCH_RELATIVE },
{ .str = "BPF_EXT_LEN", .val = BPF_EXT_LEN },
{ .str = "BPF_GRP_ALU", .val = BPF_GRP_ALU },
{ .str = "BPF_GRP_CALL", .val = BPF_GRP_CALL },

11
suite/cstest/src/test_detail.c
View file

@ -130,6 +130,9 @@ TestDetail *test_detail_clone(TestDetail *detail)
if (detail->xtensa) {
clone->xtensa = test_detail_xtensa_clone(detail->xtensa);
}
if (detail->arc) {
clone->arc = test_detail_arc_clone(detail->arc);
}
return clone;
}
@ -230,7 +233,11 @@ void test_detail_free(TestDetail *detail)
}
if (detail->xtensa) {
test_detail_xtensa_free(detail->xtensa);
}
if (detail->arc) {
test_detail_arc_free(detail->arc);
}
cs_mem_free(detail);
}
@ -413,5 +420,9 @@ bool test_expected_detail(csh *handle, const cs_insn *insn,
return test_expected_xtensa(handle, &actual->xtensa,
expected->xtensa);
}
if (expected->arc) {
return test_expected_arc(handle, &actual->arc,
expected->arc);
}
return true;
}

99
suite/cstest/src/test_detail_arc.c Normal file
View file

@ -0,0 +1,99 @@
// Copyright © 2024 Sibirtsev Dmitry <sibirtsevdl@gmail.com>
// SPDX-License-Identifier: BSD-3
#include "test_compare.h"
#include "test_detail_arc.h"
#include <capstone/capstone.h>
#include <stdio.h>
#include <string.h>
TestDetailARC *test_detail_arc_new()
{
return cs_mem_calloc(sizeof(TestDetailARC), 1);
}
void test_detail_arc_free(TestDetailARC *detail)
{
if (!detail) {
return;
}
for (size_t i = 0; i < detail->operands_count; ++i) {
test_detail_arc_op_free(detail->operands[i]);
}
cs_mem_free(detail->operands);
cs_mem_free(detail);
}
TestDetailARC *test_detail_arc_clone(const TestDetailARC *detail)
{
TestDetailARC *clone = test_detail_arc_new();
clone->operands_count = detail->operands_count;
if (detail->operands_count > 0) {
clone->operands = cs_mem_calloc(sizeof(TestDetailARCOp *),
detail->operands_count);
}
for (size_t i = 0; i < detail->operands_count; ++i) {
clone->operands[i] =
test_detail_arc_op_clone(detail->operands[i]);
}
return clone;
}
TestDetailARCOp *test_detail_arc_op_new()
{
return cs_mem_calloc(sizeof(TestDetailARCOp), 1);
}
TestDetailARCOp *test_detail_arc_op_clone(const TestDetailARCOp *op)
{
TestDetailARCOp *clone = test_detail_arc_op_new();
clone->type = op->type ? strdup(op->type) : NULL;
clone->access = op->access ? strdup(op->access) : NULL;
clone->reg = op->reg ? strdup(op->reg) : NULL;
clone->imm = op->imm;
return clone;
}
void test_detail_arc_op_free(TestDetailARCOp *op)
{
if (!op) {
return;
}
cs_mem_free(op->type);
cs_mem_free(op->access);
cs_mem_free(op->reg);
cs_mem_free(op);
}
bool test_expected_arc(csh *handle, const cs_arc *actual,
const TestDetailARC *expected)
{
assert(handle && actual && expected);
compare_uint8_ret(actual->op_count, expected->operands_count, false);
for (size_t i = 0; i < actual->op_count; ++i) {
const cs_arc_op *op = &actual->operands[i];
TestDetailARCOp *eop = expected->operands[i];
compare_enum_ret(op->type, eop->type, false);
compare_enum_ret(op->access, eop->access, false);
switch (op->type) {
default:
fprintf(stderr,
"arc op type %" PRId32 " not handled.\n",
op->type);
return false;
case ARC_OP_REG:
compare_reg_ret(*handle, op->reg, eop->reg, false);
break;
case ARC_OP_IMM:
compare_int64_ret(op->imm, eop->imm, false);
break;
}
}
return true;
}

2
suite/test_corpus3.py
View file

@ -45,6 +45,7 @@ def test_file(fname):
"CS_ARCH_TRICORE": CS_ARCH_TRICORE,
"CS_ARCH_ALPHA": CS_ARCH_ALPHA,
"CS_ARCH_HPPA": CS_ARCH_HPPA,
"CS_ARCH_ARC": CS_ARCH_ARC,
}
modes = {
@ -136,6 +137,7 @@ def test_file(fname):
("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57,
("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58,
("CS_ARCH_TRICORE", "CS_MODE_TRICORE_180"): 59,
("CS_ARCH_ARC", "CS_MODE_LITTLE_ENDIAN"): 60,
}
# if not option in ('', 'None'):

1390
tests/MC/ARC/alu_arc.s.yaml Normal file
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100
tests/MC/ARC/br_arc.s.yaml Normal file
View file

@ -0,0 +1,100 @@
test_cases:
-
input:
bytes: [ 0x3d, 0x0a, 0x12, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "brlt %r2, 0, 60"
-
input:
bytes: [ 0x91, 0x0a, 0x04, 0x91 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "brlo %r10, %r4, -112"
-
input:
bytes: [ 0x2d, 0x0a, 0x40, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "breq %r2, %r1, 44"
-
input:
bytes: [ 0xf1, 0x08, 0x11, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "brne %r0, 0, -16"
-
input:
bytes: [ 0x27, 0x0a, 0x05, 0x02 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "brhs %r2, %r8, 38"
-
input:
bytes: [ 0x30, 0x01, 0x02, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "bne 304"
-
input:
bytes: [ 0x0c, 0x01, 0x01, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "beq 268"
-
input:
bytes: [ 0xa0, 0x01, 0x0d, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "bhi 416"
-
input:
bytes: [ 0xbd, 0x07, 0xcf, 0xff ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "b -68"
-
input:
bytes: [ 0x00, 0x00, 0x9e, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "b 4096"

1260
tests/MC/ARC/compact_arc.s.yaml Normal file
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File diff suppressed because it is too large Load diff

360
tests/MC/ARC/ldst_arc.s.yaml Normal file
View file

@ -0,0 +1,360 @@
test_cases:
-
input:
bytes: [ 0x00, 0x10, 0x00, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r0, [%r0,0]"
-
input:
bytes: [ 0x00, 0x10, 0x00, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldh %r0, [%r0,0]"
-
input:
bytes: [ 0x00, 0x10, 0x80, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldb %r0, [%r0,0]"
-
input:
bytes: [ 0x0c, 0x10, 0x01, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r1, [%r0,12]"
-
input:
bytes: [ 0xf4, 0x13, 0x0e, 0xb0 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r14, [%fp,-12]"
-
input:
bytes: [ 0xf4, 0x10, 0x03, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r3, [%r0,-12]"
-
input:
bytes: [ 0xf4, 0x10, 0x00, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r0, [%r0,244]"
-
input:
bytes: [ 0xf4, 0x10, 0x00, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r0, [%r0,-12]"
-
input:
bytes: [ 0x00, 0x11, 0x43, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldh.x %r3, [%r1,0]"
-
input:
bytes: [ 0x02, 0x11, 0x42, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldh.x %r2, [%r1,2]"
-
input:
bytes: [ 0x7c, 0x13, 0x42, 0xb1 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldh.x %r2, [%fp,-132]"
-
input:
bytes: [ 0x30, 0x20, 0x80, 0x0f, 0x00, 0x00, 0x00, 0xfa ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r0, [%r0,64000]"
-
input:
bytes: [ 0x00, 0x16, 0x06, 0x70, 0x00, 0x00, 0xb0, 0xf9 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld %r6, [63920]"
-
input:
bytes: [ 0x23, 0x1c, 0x82, 0x30 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stb %r2, [%sp,35]"
-
input:
bytes: [ 0x00, 0x1e, 0xc0, 0x71, 0x00, 0x00, 0xb0, 0xf9 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "st %r7, [63920]"
-
input:
bytes: [ 0x01, 0x10, 0x81, 0x04 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldb.ab %r1, [%r0,1]"
-
input:
bytes: [ 0x01, 0x18, 0x92, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stb.ab %r2, [%r0,1]"
-
input:
bytes: [ 0x0C, 0x10, 0x03, 0x05 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldh.ab %r3, [%r0,12]"
-
input:
bytes: [ 0x12, 0x18, 0x14, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "sth.ab %r4, [%r0,18]"
-
input:
bytes: [ 0x80, 0x12, 0x05, 0x04 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld.ab %r5, [%r2,128]"
-
input:
bytes: [ 0x40, 0x1A, 0x90, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "st.ab %r6, [%r2,64]"
-
input:
bytes: [ 0x01, 0x10, 0x87, 0x02 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldb.aw %r7, [%r0,1]"
-
input:
bytes: [ 0x01, 0x18, 0x0A, 0x02 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stb.aw %r8, [%r0,1]"
-
input:
bytes: [ 0x0C, 0x10, 0x03, 0x03 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldh.aw %r3, [%r0,12]"
-
input:
bytes: [ 0x12, 0x18, 0xCC, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "sth.aw %r3, [%r0,18]"
-
input:
bytes: [ 0x80, 0x12, 0x06, 0x02 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld.aw %r6, [%r2,128]"
-
input:
bytes: [ 0x40, 0x1A, 0x88, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "st.aw %r6, [%r2,64]"
-
input:
bytes: [ 0x08, 0x10, 0xC0, 0x1A ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ldb.x.di.aw %r0, [%r8,8]"
-
input:
bytes: [ 0x40, 0x19, 0x32, 0x10 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "stb.di.ab %r0, [%r9,64]"
-
input:
bytes: [ 0x6a, 0x20, 0x40, 0x08 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r0, [33]"
-
input:
bytes: [ 0x6a, 0x27, 0x40, 0x08 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r7, [33]"
-
input:
bytes: [ 0x6a, 0x27, 0x40, 0x18 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r15, [33]"
-
input:
bytes: [ 0x6a, 0x26, 0x40, 0x28 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r22, [33]"
-
input:
bytes: [ 0xaa, 0x20, 0x60, 0x08 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r0, [-33]"
-
input:
bytes: [ 0xaa, 0x20, 0x41, 0x08 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r0, [97]"
-
input:
bytes: [ 0xaa, 0x20, 0x61, 0x08 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "lr %r0, [-97]"

490
tests/MC/ARC/misc_arc.s.yaml Normal file
View file

@ -0,0 +1,490 @@
test_cases:
-
input:
bytes: [ 0x8a, 0x20, 0xff, 0x0f ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov %r0, -1"
-
input:
bytes: [ 0x0a, 0x24, 0x80, 0x0f, 0x00, 0x00, 0xff, 0x7f ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov %r4, 32767"
-
input:
bytes: [ 0xca, 0x22, 0x81, 0x01 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.eq %r2, %r6"
-
input:
bytes: [ 0x0a, 0x25, 0x80, 0x10 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov %r13, %r2"
-
input:
bytes: [ 0x4a, 0x21, 0x00, 0x05 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov %r1, 20"
-
input:
bytes: [ 0xca, 0x20, 0x21, 0x08 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.eq %r0, 32"
-
input:
bytes: [ 0xca, 0x20, 0x22, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.ne %r0, 0"
-
input:
bytes: [ 0xca, 0x20, 0x21, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.eq %r0, 0"
-
input:
bytes: [ 0xca, 0x26, 0x2b, 0x04 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.lt %r6, 16"
-
input:
bytes: [ 0xca, 0x27, 0xec, 0x17 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.le %r15, 31"
-
input:
bytes: [ 0xca, 0x20, 0x29, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.gt %r0, 0"
-
input:
bytes: [ 0xca, 0x26, 0x2a, 0x04 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.ge %r6, 16"
-
input:
bytes: [ 0xca, 0x27, 0xe3, 0x17 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.p %r15, 31"
-
input:
bytes: [ 0xca, 0x20, 0x24, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.n %r0, 0"
-
input:
bytes: [ 0xca, 0x26, 0x27, 0x04 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.vs %r6, 16"
-
input:
bytes: [ 0xca, 0x27, 0xef, 0x17 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.pnz %r15, 31"
-
input:
bytes: [ 0x4a, 0x20, 0x00, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.f %r0, 0"
-
input:
bytes: [ 0x4a, 0x26, 0x00, 0x84 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.f %r6, 16"
-
input:
bytes: [ 0x4a, 0x27, 0xc0, 0x97 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.f %r15, 31"
-
input:
bytes: [ 0xca, 0x20, 0x21, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.eq.f %r0, 0"
-
input:
bytes: [ 0xca, 0x26, 0x2b, 0x84 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.lt.f %r6, 16"
-
input:
bytes: [ 0xca, 0x27, 0xec, 0x97 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.le.f %r15, 31"
-
input:
bytes: [ 0xca, 0x20, 0x29, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.gt.f %r0, 0"
-
input:
bytes: [ 0xca, 0x26, 0x2a, 0x84 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.ge.f %r6, 16"
-
input:
bytes: [ 0xca, 0x27, 0xe3, 0x97 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.p.f %r15, 31"
-
input:
bytes: [ 0xca, 0x20, 0x24, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.n.f %r0, 0"
-
input:
bytes: [ 0xca, 0x26, 0x27, 0x84 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.vs.f %r6, 16"
-
input:
bytes: [ 0xca, 0x27, 0xef, 0x97 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "mov.pnz.f %r15, 31"
-
input:
bytes: [ 0xfc, 0x1c, 0xc8, 0xb6 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "st.aw %fp, [%sp,-4]"
-
input:
bytes: [ 0x04, 0x14, 0x1b, 0x34 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ld.ab %fp, [%sp,4]"
-
input:
bytes: [ 0x16, 0x08, 0xcf, 0xff ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "bl -2028"
-
input:
bytes: [ 0x0c, 0x25, 0x80, 0x92 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "cmp %r13, %r10"
-
input:
bytes: [ 0x4c, 0x26, 0x00, 0x90 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "cmp %r14, 0"
-
input:
bytes: [ 0x4c, 0x27, 0x40, 0xa0 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "cmp %r23, 1"
-
input:
bytes: [ 0x22, 0x20, 0x40, 0x05 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "jl [%r21]"
-
input:
bytes: [ 0x22, 0x20, 0x80, 0x0f, 0x00, 0x00, 0x39, 0x30 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "jl 12345"
-
input:
bytes: [ 0x20, 0x20, 0xc0, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "j [%r3]"
-
input:
bytes: [ 0x20, 0x20, 0x80, 0x0f, 0x00, 0x00, 0x39, 0x30 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "j 12345"
-
input:
bytes: [ 0x38, 0x23, 0x43, 0x30 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "seteq %r3, %fp, %r1"
-
input:
bytes: [ 0x78, 0x23, 0x43, 0x34 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "seteq %r3, %fp, 17"
-
input:
bytes: [ 0xb8, 0x23, 0xff, 0x3f, ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "seteq %fp, %fp, -1"
-
input:
bytes: [ 0x2f, 0x28, 0x13, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "fls %r0, %r0"
-
input:
bytes: [ 0x2f, 0x28, 0x13, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "fls.f %r0, %r0"
-
input:
bytes: [ 0x2f, 0x28, 0x12, 0x00 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ffs %r0, %r0"
-
input:
bytes: [ 0x2f, 0x28, 0x12, 0x80 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ffs.f %r0, %r0"
-
input:
bytes: [ 0x2f, 0x2f, 0xd2, 0x13 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ffs %r15, %r15"
-
input:
bytes: [ 0x2f, 0x2f, 0xd2, 0x93 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "ffs.f %r15, %r15"
-
input:
bytes: [ 0x2f, 0x2e, 0xc1, 0x27 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "norm %r22, %blink"
-
input:
bytes: [ 0x2f, 0x2f, 0x88, 0x04 ]
arch: "CS_ARCH_ARC"
options: [ "CS_MODE_LITTLE_ENDIAN" ]
expected:
insns:
-
asm_text: "normh %r7, %r18"

204
tests/details/arc.yaml Normal file
View file

@ -0,0 +1,204 @@
test_cases:
-
input:
bytes: [ 0x04, 0x11, 0x00, 0x00, 0x04, 0x11, 0x00, 0x02, 0x04, 0x11, 0x00, 0x04, 0x04, 0x11, 0x00, 0x01, 0x04, 0x11, 0x00, 0x03, 0x04, 0x11, 0x00, 0x05, 0x04, 0x11, 0x80, 0x00, 0x04, 0x11, 0x80, 0x02, 0x04, 0x11, 0x80, 0x04, 0x2d, 0x0a, 0x40, 0x00, 0xca, 0x22, 0x81, 0x01 ]
arch: "arc"
options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN ]
address: 0x0
expected:
insns:
-
asm_text: "ld %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ld.aw %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ld.ab %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ldh %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ldh.aw %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ldh.ab %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ldb %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ldb.aw %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "ldb.ab %r0, [%r1,4]"
details:
arc:
operands:
-
type: ARC_OP_REG
reg: "%r0"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 4
access: CS_AC_READ
-
asm_text: "breq %r2, %r1, 80"
details:
arc:
operands:
-
type: ARC_OP_IMM
imm: 0
access: CS_AC_READ
-
type: ARC_OP_REG
reg: "%r2"
access: CS_AC_READ
-
type: ARC_OP_REG
reg: "%r1"
access: CS_AC_READ
-
type: ARC_OP_IMM
imm: 0x50
access: CS_AC_READ
regs_read: [ "%r2", "%r1" ]
groups: [ jump, branch_relative ]
-
asm_text: "mov.eq %r2, %r6"
details:
arc:
operands:
-
type: ARC_OP_IMM
imm: 1
access: CS_AC_READ
-
type: ARC_OP_REG
reg: "%r2"
access: CS_AC_WRITE
-
type: ARC_OP_REG
reg: "%r6"
access: CS_AC_READ
regs_read: [ "status32", "%r6" ]
regs_write: [ "%r2" ]

13
tests/integration/test_iter.c
View file

@ -91,6 +91,10 @@ static void test()
#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c"
#endif
#ifdef CAPSTONE_HAS_ARC
#define ARC_CODE "\x04\x11\x00\x00\x04\x11\x00\x02\x04\x11\x00\x04\x04\x11\x00\x01\x04\x11\x00\x03\x04\x11\x00\x05\x04\x11\x80\x00\x04\x11\x80\x02\x04\x11\x80\x04"
#endif
struct platform platforms[] = {
#ifdef CAPSTONE_HAS_X86
{
@ -319,6 +323,15 @@ struct platform platforms[] = {
sizeof(HPPA_11_CODE) - 1,
"HPPA 1.1 (Little-endian)"
},
#endif
#ifdef CAPSTONE_HAS_ARC
{
CS_ARCH_ARC,
CS_MODE_LITTLE_ENDIAN,
(unsigned char*)ARC_CODE,
sizeof(ARC_CODE) - 1,
"ARC"
},
#endif
};