From f407e942492418781e2a4789ea4d22a1a5c9a277 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Wed, 10 Apr 2019 14:17:08 +0800 Subject: [PATCH] arm64: sync with LLVM 7.0.1 --- CMakeLists.txt | 24 +- MCRegisterInfo.h | 7 + SStream.c | 9 + SStream.h | 2 + arch/AArch64/AArch64AddressingModes.h | 307 +- arch/AArch64/AArch64BaseInfo.c | 188 +- arch/AArch64/AArch64BaseInfo.h | 247 +- arch/AArch64/AArch64Disassembler.c | 782 +- arch/AArch64/AArch64Disassembler.h | 2 + arch/AArch64/AArch64GenAsmWriter.inc | 25983 ++++++++---- arch/AArch64/AArch64GenDisassemblerTables.inc | 32573 ++++++++++------ arch/AArch64/AArch64GenInstrInfo.inc | 11863 ++++-- arch/AArch64/AArch64GenRegisterInfo.inc | 3316 +- arch/AArch64/AArch64GenRegisterName.inc | 686 + arch/AArch64/AArch64GenRegisterV.inc | 660 + arch/AArch64/AArch64GenSubtargetInfo.inc | 93 +- arch/AArch64/AArch64GenSystemOperands.inc | 2049 + .../AArch64/AArch64GenSystemOperands_enum.inc | 19 + arch/AArch64/AArch64InstPrinter.c | 1200 +- arch/AArch64/AArch64Mapping.c | 795 +- arch/AArch64/AArch64Mapping.h | 6 +- arch/AArch64/AArch64MappingInsn.inc | 16827 +++++++- arch/AArch64/AArch64MappingInsnName.inc | 943 + arch/AArch64/AArch64MappingInsnOp.inc | 19078 +++++++-- arch/AArch64/ARMMappingInsnOp.inc | 6657 ---- arch/ARM/ARMGenSystemRegister.inc | 6 +- arch/ARM/ARMMapping.c | 31 - arch/ARM/ARMMapping.h | 9 - bindings/java/TestArm64.java | 2 - bindings/java/capstone/Arm64.java | 4 +- bindings/java/capstone/Arm64_const.java | 2954 +- bindings/ocaml/arm64.ml | 1 - bindings/ocaml/arm64_const.ml | 2954 +- bindings/ocaml/ocaml.c | 9 +- bindings/python/capstone/arm64.py | 1 - bindings/python/capstone/arm64_const.py | 2954 +- bindings/python/test_arm64.py | 3 - cstool/cstool_arm64.c | 3 - include/capstone/arm64.h | 6411 +-- suite/cstest/issues.cs | 16 + suite/cstest/src/arm64_detail.c | 22 +- tests/test_arm64.c | 3 - utils.c | 30 + utils.h | 9 + 44 files changed, 98673 insertions(+), 41065 deletions(-) create mode 100644 arch/AArch64/AArch64GenRegisterName.inc create mode 100644 arch/AArch64/AArch64GenRegisterV.inc create mode 100644 arch/AArch64/AArch64GenSystemOperands.inc create mode 100644 arch/AArch64/AArch64GenSystemOperands_enum.inc create mode 100644 arch/AArch64/AArch64MappingInsnName.inc delete mode 100644 arch/AArch64/ARMMappingInsnOp.inc diff --git a/CMakeLists.txt b/CMakeLists.txt index f15536415..f77b8339a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -164,27 +164,21 @@ if (NOT CAPSTONE_X86_ONLY AND CAPSTONE_ARM64_SUPPORT) arch/AArch64/AArch64AddressingModes.h arch/AArch64/AArch64BaseInfo.h arch/AArch64/AArch64Disassembler.h + arch/AArch64/AArch64InstPrinter.h + arch/AArch64/AArch64Mapping.h arch/AArch64/AArch64GenAsmWriter.inc arch/AArch64/AArch64GenDisassemblerTables.inc arch/AArch64/AArch64GenInstrInfo.inc arch/AArch64/AArch64GenRegisterInfo.inc + arch/AArch64/AArch64GenRegisterName.inc + arch/AArch64/AArch64GenRegisterV.inc arch/AArch64/AArch64GenSubtargetInfo.inc - arch/AArch64/AArch64InstPrinter.h - arch/AArch64/AArch64Mapping.h + arch/AArch64/AArch64GenSystemOperands.inc + arch/AArch64/AArch64GenSystemOperands_enum.inc arch/AArch64/AArch64MappingInsn.inc - ) - set(HEADERS_ARM64 - arch/AArch64/AArch64AddressingModes.h - arch/AArch64/AArch64BaseInfo.h - arch/AArch64/AArch64Disassembler.h - arch/AArch64/AArch64GenAsmWriter.inc - arch/AArch64/AArch64GenDisassemblerTables.inc - arch/AArch64/AArch64GenInstrInfo.inc - arch/AArch64/AArch64GenRegisterInfo.inc - arch/AArch64/AArch64GenSubtargetInfo.inc - arch/AArch64/AArch64InstPrinter.h - arch/AArch64/AArch64Mapping.h - ) + arch/AArch64/AArch64MappingInsnName.inc + arch/AArch64/AArch64MappingInsnOp.inc + ) set(TEST_SOURCES ${TEST_SOURCES} test_arm64.c) endif () diff --git a/MCRegisterInfo.h b/MCRegisterInfo.h index bee66aeab..c7932fcbf 100644 --- a/MCRegisterInfo.h +++ b/MCRegisterInfo.h @@ -26,6 +26,13 @@ typedef uint16_t MCPhysReg; typedef const MCPhysReg* iterator; +typedef struct MCRegisterClass2 { + iterator RegsBegin; + const uint8_t *RegSet; + uint8_t RegsSize; + uint8_t RegSetSize; +} MCRegisterClass2; + typedef struct MCRegisterClass { iterator RegsBegin; const uint8_t *RegSet; diff --git a/SStream.c b/SStream.c index d8dd841c8..303760ca9 100644 --- a/SStream.c +++ b/SStream.c @@ -39,6 +39,15 @@ void SStream_concat0(SStream *ss, const char *s) #endif } +void SStream_concat1(SStream *ss, const char c) +{ +#ifndef CAPSTONE_DIET + ss->buffer[ss->index] = c; + ss->index++; + ss->buffer[ss->index] = '\0'; +#endif +} + void SStream_concat(SStream *ss, const char *fmt, ...) { #ifndef CAPSTONE_DIET diff --git a/SStream.h b/SStream.h index 4ebf1f0d9..3e061139e 100644 --- a/SStream.h +++ b/SStream.h @@ -17,6 +17,8 @@ void SStream_concat(SStream *ss, const char *fmt, ...); void SStream_concat0(SStream *ss, const char *s); +void SStream_concat1(SStream *ss, const char c); + void printInt64Bang(SStream *O, int64_t val); void printUInt64Bang(SStream *O, uint64_t val); diff --git a/arch/AArch64/AArch64AddressingModes.h b/arch/AArch64/AArch64AddressingModes.h index 75ecf0b48..aca1d2613 100644 --- a/arch/AArch64/AArch64AddressingModes.h +++ b/arch/AArch64/AArch64AddressingModes.h @@ -88,6 +88,7 @@ static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, u { // assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); unsigned STEnc = 0; + switch (ST) { default: // llvm_unreachable("Invalid shift requested"); case AArch64_AM_LSL: STEnc = 0; break; @@ -96,6 +97,7 @@ static inline unsigned AArch64_AM_getShifterImm(AArch64_AM_ShiftExtendType ST, u case AArch64_AM_ROR: STEnc = 3; break; case AArch64_AM_MSL: STEnc = 4; break; } + return (STEnc << 6) | (Imm & 0x3f); } @@ -163,7 +165,7 @@ inline unsigned AArch64_AM_getExtendEncoding(AArch64_AM_ShiftExtendType ET) static inline unsigned AArch64_AM_getArithExtendImm(AArch64_AM_ShiftExtendType ET, unsigned Imm) { // assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!"); - return (getExtendEncoding(ET) << 3) | (Imm & 0x7); + return (AArch64_AM_getExtendEncoding(ET) << 3) | (Imm & 0x7); } /// getMemDoShift - Extract the "do shift" flag value for load/store @@ -177,25 +179,15 @@ static inline bool AArch64_AM_getMemDoShift(unsigned Imm) /// loads/stores. static inline AArch64_AM_ShiftExtendType AArch64_AM_getMemExtendType(unsigned Imm) { - return AArch64_AM_getMemExtendType((Imm >> 1) & 0x7); + return AArch64_AM_getExtendType((Imm >> 1) & 0x7); } -/// getExtendImm - Encode the extend type and amount for a load/store inst: -/// doshift: should the offset be scaled by the access size -/// shifter: 000 ==> uxtb -/// 001 ==> uxth -/// 010 ==> uxtw -/// 011 ==> uxtx -/// 100 ==> sxtb -/// 101 ==> sxth -/// 110 ==> sxtw -/// 111 ==> sxtx -/// {3-1} = shifter -/// {0} = doshift +#if 0 static inline unsigned AArch64_AM_getMemExtendImm(AArch64_AM_ShiftExtendType ET, bool DoShift) { - return (getExtendEncoding(ET) << 1) | unsigned(DoShift); + return (AArch64_AM_getExtendEncoding(ET) << 1) | unsigned(DoShift); } +#endif static inline uint64_t ror(uint64_t elt, unsigned size) { @@ -206,61 +198,78 @@ static inline uint64_t ror(uint64_t elt, unsigned size) /// as the immediate operand of a logical instruction for the given register /// size. If so, return true with "encoding" set to the encoded value in /// the form N:immr:imms. -static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding) +static inline bool AArch64_AM_processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t *Encoding) { + unsigned Size, Immr, N; + uint32_t CTO, I; + uint64_t Mask, NImms; + if (Imm == 0ULL || Imm == ~0ULL || (RegSize != 64 && (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize))))) { return false; } + // First, determine the element size. - unsigned Size = RegSize; + Size = RegSize; do { + uint64_t Mask; + Size /= 2; - uint64_t Mask = (1ULL << Size) - 1; + Mask = (1ULL << Size) - 1; if ((Imm & Mask) != ((Imm >> Size) & Mask)) { Size *= 2; break; } } while (Size > 2); + // Second, determine the rotation to make the element be: 0^m 1^n. - uint32_t CTO, I; - uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size); + Mask = ((uint64_t)-1LL) >> (64 - Size); Imm &= Mask; + if (isShiftedMask_64(Imm)) { - I = countTrailingZeros(Imm); + I = CountTrailingZeros_32(Imm); // assert(I < 64 && "undefined behavior"); - CTO = countTrailingOnes(Imm >> I); + CTO = CountTrailingOnes_32(Imm >> I); } else { + unsigned CLO; + Imm |= ~Mask; if (!isShiftedMask_64(~Imm)) return false; - unsigned CLO = countLeadingOnes(Imm); + + CLO = CountLeadingOnes_32(Imm); I = 64 - CLO; - CTO = CLO + countTrailingOnes(Imm) - (64 - Size); + CTO = CLO + CountTrailingOnes_32(Imm) - (64 - Size); } + // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n // to our target value, where I is the number of RORs to go the opposite // direction. // assert(Size > I && "I should be smaller than element size"); - unsigned Immr = (Size - I) & (Size - 1); + Immr = (Size - I) & (Size - 1); + // If size has a 1 in the n'th bit, create a value that has zeroes in // bits [0, n] and ones above that. - uint64_t NImms = ~(Size-1) << 1; + NImms = ~(Size-1) << 1; + // Or the CTO value into the low bits, which must be below the Nth bit // bit mentioned above. NImms |= (CTO-1); + // Extract the seventh bit and toggle it to create the N field. - unsigned N = ((NImms >> 6) & 1) ^ 1; - Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); + N = ((NImms >> 6) & 1) ^ 1; + + *Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f); + return true; } /// isLogicalImmediate - Return true if the immediate is valid for a logical /// immediate instruction of the given register size. Return false otherwise. -static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize) +static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) { uint64_t encoding; - return AArch64_AM_processLogicalImmediate(imm, regSize, encoding); + return AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); } /// encodeLogicalImmediate - Return the encoded immediate value for a logical @@ -268,9 +277,11 @@ static inline bool AArch64_AM_isLogicalImmediate(uint64_t imm, unsigned regSize) static inline uint64_t AArch64_AM_encodeLogicalImmediate(uint64_t imm, unsigned regSize) { uint64_t encoding = 0; - bool res = AArch64_AM_processLogicalImmediate(imm, regSize, encoding); + + bool res = AArch64_AM_processLogicalImmediate(imm, regSize, &encoding); // assert(res && "invalid logical immediate"); (void)res; + return encoding; } @@ -283,16 +294,20 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned unsigned N = (val >> 12) & 1; unsigned immr = (val >> 6) & 0x3f; unsigned imms = val & 0x3f; - unsigned i; + unsigned i, size, R, S; + uint64_t pattern; // assert((regSize == 64 || N == 0) && "undefined logical immediate encoding"); - int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); + int len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); + // assert(len >= 0 && "undefined logical immediate encoding"); - unsigned size = (1 << len); - unsigned R = immr & (size - 1); - unsigned S = imms & (size - 1); + size = (1 << len); + R = immr & (size - 1); + S = imms & (size - 1); + // assert(S != size - 1 && "undefined logical immediate encoding"); - uint64_t pattern = (1ULL << (S + 1)) - 1; + pattern = (1ULL << (S + 1)) - 1; + for (i = 0; i < R; ++i) pattern = ror(pattern, size); @@ -310,8 +325,7 @@ static inline uint64_t AArch64_AM_decodeLogicalImmediate(uint64_t val, unsigned /// is a valid encoding for an integer value with regSize bits. static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize) { - unsigned size; - unsigned S; + unsigned size, S; int len; // Extract the N and imms fields needed for checking. unsigned N = (val >> 12) & 1; @@ -319,7 +333,7 @@ static inline bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsign if (regSize == 32 && N != 0) // undefined logical immediate encoding return false; - len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); + len = 31 - CountLeadingZeros_32((N << 6) | (~imms & 0x3f)); if (len < 0) // undefined logical immediate encoding return false; size = (1 << len); @@ -360,6 +374,7 @@ static inline float AArch64_AM_getFPImmFloat(unsigned Imm) return FPUnion.F; } +#if 0 /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit /// floating-point value. If the value cannot be represented as an 8-bit /// floating-point value, then return -1. @@ -378,6 +393,7 @@ static inline int AArch64_AM_getFP16Imm(const APInt &Imm) // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 if (Exp < -3 || Exp > 4) return -1; + Exp = ((Exp + 3) & 0x7) ^ 4; return ((int)Sign << 7) | (Exp << 4) | Mantissa; @@ -408,6 +424,7 @@ static inline int AArch64_AM_getFP32Imm(const APInt &Imm) // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 if (Exp < -3 || Exp > 4) return -1; + Exp = ((Exp + 3) & 0x7) ^ 4; return ((int)Sign << 7) | (Exp << 4) | Mantissa; @@ -438,6 +455,7 @@ static inline int AArch64_AM_getFP64Imm(const APInt &Imm) // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3 if (Exp < -3 || Exp > 4) return -1; + Exp = ((Exp + 3) & 0x7) ^ 4; return ((int)Sign << 7) | (Exp << 4) | Mantissa; @@ -447,6 +465,7 @@ static inline int AArch64_AM_getFP64Imm(const APFloat &FPImm) { return getFP64Imm(FPImm.bitcastToAPInt()); } +#endif //===--------------------------------------------------------------------===// // AdvSIMD Modified Immediates @@ -456,7 +475,7 @@ static inline int AArch64_AM_getFP64Imm(const APFloat &FPImm) static inline bool AArch64_AM_isAdvSIMDModImmType1(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xffffff00ffffff00ULL) == 0); + ((Imm & 0xffffff00ffffff00ULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm) @@ -467,6 +486,7 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType1(uint64_t Imm) static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm) { uint64_t EncVal = Imm; + return (EncVal << 32) | EncVal; } @@ -474,7 +494,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType1(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType2(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xffff00ffffff00ffULL) == 0); + ((Imm & 0xffff00ffffff00ffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType2(uint64_t Imm) @@ -492,7 +512,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType2(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType3(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xff00ffffff00ffffULL) == 0); + ((Imm & 0xff00ffffff00ffffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType3(uint64_t Imm) @@ -510,7 +530,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType3(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType4(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0x00ffffff00ffffffULL) == 0); + ((Imm & 0x00ffffff00ffffffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType4(uint64_t Imm) @@ -528,8 +548,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType4(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType5(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) && - ((Imm & 0xff00ff00ff00ff00ULL) == 0); + (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) && + ((Imm & 0xff00ff00ff00ff00ULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType5(uint64_t Imm) @@ -547,8 +567,8 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType5(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType6(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) && - ((Imm & 0x00ff00ff00ff00ffULL) == 0); + (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) && + ((Imm & 0x00ff00ff00ff00ffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType6(uint64_t Imm) @@ -566,7 +586,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType6(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType7(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL); + ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType7(uint64_t Imm) @@ -584,7 +604,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType7(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType8(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL); + ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL); } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType8(uint8_t Imm) @@ -602,8 +622,8 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType8(uint64_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType9(uint64_t Imm) { return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - ((Imm >> 48) == (Imm & 0x0000ffffULL)) && - ((Imm >> 56) == (Imm & 0x000000ffULL)); + ((Imm >> 48) == (Imm & 0x0000ffffULL)) && + ((Imm >> 56) == (Imm & 0x000000ffULL)); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType9(uint64_t Imm) @@ -617,6 +637,7 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType9(uint8_t Imm) EncVal |= (EncVal << 8); EncVal |= (EncVal << 16); EncVal |= (EncVal << 32); + return EncVal; } @@ -634,13 +655,13 @@ static inline bool AArch64_AM_isAdvSIMDModImmType10(uint64_t Imm) uint64_t ByteH = Imm & 0x00000000000000ffULL; return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) && - (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) && - (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) && - (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) && - (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) && - (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) && - (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) && - (ByteH == 0ULL || ByteH == 0x00000000000000ffULL); + (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) && + (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) && + (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) && + (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) && + (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) && + (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) && + (ByteH == 0ULL || ByteH == 0x00000000000000ffULL); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) @@ -655,6 +676,7 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0; uint8_t EncVal = BitA; + EncVal <<= 1; EncVal |= BitB; EncVal <<= 1; @@ -669,28 +691,38 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType10(uint64_t Imm) EncVal |= BitG; EncVal <<= 1; EncVal |= BitH; + return EncVal; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) { uint64_t EncVal = 0; + if (Imm & 0x80) EncVal |= 0xff00000000000000ULL; + if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL; + if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL; + if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL; + if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL; + if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL; + if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL; + if (Imm & 0x01) EncVal |= 0x00000000000000ffULL; + return EncVal; } @@ -698,9 +730,10 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType10(uint8_t Imm) static inline bool AArch64_AM_isAdvSIMDModImmType11(uint64_t Imm) { uint64_t BString = (Imm & 0x7E000000ULL) >> 25; + return ((Imm >> 32) == (Imm & 0xffffffffULL)) && - (BString == 0x1f || BString == 0x20) && - ((Imm & 0x0007ffff0007ffffULL) == 0); + (BString == 0x1f || BString == 0x20) && + ((Imm & 0x0007ffff0007ffffULL) == 0); } static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm) @@ -729,30 +762,40 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType11(uint64_t Imm) EncVal |= BitG; EncVal <<= 1; EncVal |= BitH; + return EncVal; } static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType11(uint8_t Imm) { uint64_t EncVal = 0; + if (Imm & 0x80) EncVal |= 0x80000000ULL; + if (Imm & 0x40) EncVal |= 0x3e000000ULL; else EncVal |= 0x40000000ULL; + if (Imm & 0x20) EncVal |= 0x01000000ULL; + if (Imm & 0x10) EncVal |= 0x00800000ULL; + if (Imm & 0x08) EncVal |= 0x00400000ULL; + if (Imm & 0x04) EncVal |= 0x00200000ULL; + if (Imm & 0x02) EncVal |= 0x00100000ULL; + if (Imm & 0x01) EncVal |= 0x00080000ULL; + return (EncVal << 32) | EncVal; } @@ -790,6 +833,7 @@ static inline uint8_t AArch64_AM_encodeAdvSIMDModImmType12(uint64_t Imm) EncVal |= BitG; EncVal <<= 1; EncVal |= BitH; + return EncVal; } @@ -798,58 +842,129 @@ static inline uint64_t AArch64_AM_decodeAdvSIMDModImmType12(uint8_t Imm) uint64_t EncVal = 0; if (Imm & 0x80) EncVal |= 0x8000000000000000ULL; + if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL; else EncVal |= 0x4000000000000000ULL; + if (Imm & 0x20) EncVal |= 0x0020000000000000ULL; + if (Imm & 0x10) EncVal |= 0x0010000000000000ULL; + if (Imm & 0x08) EncVal |= 0x0008000000000000ULL; + if (Imm & 0x04) EncVal |= 0x0004000000000000ULL; + if (Imm & 0x02) EncVal |= 0x0002000000000000ULL; + if (Imm & 0x01) EncVal |= 0x0001000000000000ULL; + return (EncVal << 32) | EncVal; } /// Returns true if Imm is the concatenation of a repeating pattern of type T. -// static inline bool AArch64_AM_isSVEMaskOfIdenticalElements(int64_t Imm) -// { -// union { -// int64_t Whole; -// T Parts[sizeof(int64_t) / sizeof(T)]; -// } Vec{Imm}; +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements8(int64_t Imm) +{ +#define _VECSIZE (sizeof(int64_t)/sizeof(int8_t)) + unsigned int i; + union { + int64_t Whole; + int8_t Parts[_VECSIZE]; + } Vec; + + Vec.Whole = Imm; -// return all_of(Vec.Parts, [Vec](T Elem) { return Elem == Vec.Parts[0]; }); -// } + for(i = 1; i < _VECSIZE; i++) { + if (Vec.Parts[i] != Vec.Parts[0]) + return false; + } +#undef _VECSIZE -// /// Returns true if Imm is valid for CPY/DUP. -// static inline bool AArch64_AM_isSVECpyImm(int64_t Imm) -// { -// bool IsImm8 = int8_t(Imm) == Imm; -// bool IsImm16 = int16_t(Imm & ~0xff) == Imm; + return true; +} -// if (std::is_same::type>::value) -// return IsImm8 || uint8_t(Imm) == Imm; +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements16(int64_t Imm) +{ +#define _VECSIZE (sizeof(int64_t)/sizeof(int16_t)) + unsigned int i; + union { + int64_t Whole; + int16_t Parts[_VECSIZE]; + } Vec; -// if (std::is_same::type>::value) -// return IsImm8 || IsImm16 || uint16_t(Imm & ~0xff) == Imm; + Vec.Whole = Imm; -// return IsImm8 || IsImm16; -// } + for(i = 1; i < _VECSIZE; i++) { + if (Vec.Parts[i] != Vec.Parts[0]) + return false; + } +#undef _VECSIZE -// /// Returns true if Imm is valid for ADD/SUB. -// static inline bool AArch64_AM_isSVEAddSubImm(int64_t Imm) -// { -// bool IsInt8t = -// std::is_same::type>::value; -// return uint8_t(Imm) == Imm || (!IsInt8t && uint16_t(Imm & ~0xff) == Imm); -// } + return true; +} + +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements32(int64_t Imm) +{ +#define _VECSIZE (sizeof(int64_t)/sizeof(int32_t)) + unsigned int i; + union { + int64_t Whole; + int32_t Parts[_VECSIZE]; + } Vec; + + Vec.Whole = Imm; + + for(i = 1; i < _VECSIZE; i++) { + if (Vec.Parts[i] != Vec.Parts[0]) + return false; + } +#undef _VECSIZE + + return true; +} + +static inline bool AArch64_AM_isSVEMaskOfIdenticalElements64(int64_t Imm) +{ + return true; +} + +static inline bool isSVECpyImm8(int64_t Imm) +{ + bool IsImm8 = (int8_t)Imm == Imm; + + return IsImm8 || (uint8_t)Imm == Imm; +} + +static inline bool isSVECpyImm16(int64_t Imm) +{ + bool IsImm8 = (int8_t)Imm == Imm; + bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; + + return IsImm8 || IsImm16 || (uint16_t)(Imm & ~0xff) == Imm; +} + +static inline bool isSVECpyImm32(int64_t Imm) +{ + bool IsImm8 = (int8_t)Imm == Imm; + bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; + + return IsImm8 || IsImm16; +} + +static inline bool isSVECpyImm64(int64_t Imm) +{ + bool IsImm8 = (int8_t)Imm == Imm; + bool IsImm16 = (int16_t)(Imm & ~0xff) == Imm; + + return IsImm8 || IsImm16; +} /// Return true if Imm is valid for DUPM and has no single CPY/DUP equivalent. static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm) @@ -861,25 +976,25 @@ static inline bool AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(int64_t Imm int8_t B[8]; } Vec = {Imm}; - if (isSVECpyImm(Vec.D)) + if (isSVECpyImm64(Vec.D)) return false; - if (isSVEMaskOfIdenticalElements(Imm) && - isSVECpyImm(Vec.S[0])) + if (AArch64_AM_isSVEMaskOfIdenticalElements32(Imm) && + isSVECpyImm32(Vec.S[0])) return false; - if (isSVEMaskOfIdenticalElements(Imm) && - isSVECpyImm(Vec.H[0])) + if (AArch64_AM_isSVEMaskOfIdenticalElements16(Imm) && + isSVECpyImm16(Vec.H[0])) return false; - if (isSVEMaskOfIdenticalElements(Imm) && - isSVECpyImm(Vec.B[0])) + if (AArch64_AM_isSVEMaskOfIdenticalElements8(Imm) && + isSVECpyImm8(Vec.B[0])) return false; return isLogicalImmediate(Vec.D, 64); } -inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth) +inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) if ((Value & ~(0xffffULL << Shift)) == 0) @@ -888,7 +1003,7 @@ inline static bool AArch64_AM_isAnyMOVZMovAlias(uint64_t Value, int RegWidth) return false; } -inline static bool AArch64_AM_isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) +inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { if (RegWidth == 32) Value &= 0xffffffffULL; diff --git a/arch/AArch64/AArch64BaseInfo.c b/arch/AArch64/AArch64BaseInfo.c index bb2d642c1..6aaef6432 100644 --- a/arch/AArch64/AArch64BaseInfo.c +++ b/arch/AArch64/AArch64BaseInfo.c @@ -27,63 +27,15 @@ #include #include "AArch64BaseInfo.h" + #include "AArch64GenSystemOperands.inc" -const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid) -{ - unsigned i; - for (i = 0; i < N->NumPairs; ++i) { - if (N->Pairs[i].Value == Value) { - *Valid = true; - return N->Pairs[i].Name; - } - } - - *Valid = false; - return 0; -} - -// compare s1 with lower(s2) -// return true if s1 == lower(f2), and false otherwise -static bool compare_lower_str(const char *s1, const char *s2) -{ - bool res; - char *lower = cs_strdup(s2), *c; - for (c = lower; *c; c++) - *c = (char)tolower((int) *c); - - res = (strcmp(s1, lower) == 0); - cs_mem_free(lower); - - return res; -} - -uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid) -{ - unsigned i; - for (i = 0; i < N->NumPairs; ++i) { - if (compare_lower_str(N->Pairs[i].Name, Name)) { - *Valid = true; - return N->Pairs[i].Value; - } - } - - *Valid = false; - return (uint32_t)-1; -} - -bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value) -{ - return Value < N->TooBigImm; -} - // return a string representing the number X -// NOTE: caller must free() the result itself to avoid memory leak -static char *utostr(uint64_t X, bool isNeg) +// NOTE: result must be big enough to contain the data +static void utostr(uint64_t X, bool isNeg, char *result) { char Buffer[22]; - char *BufPtr = Buffer+21; - char *result; + char *BufPtr = Buffer + 21; Buffer[21] = '\0'; if (X == 0) *--BufPtr = '0'; // Handle special case... @@ -95,127 +47,31 @@ static char *utostr(uint64_t X, bool isNeg) if (isNeg) *--BufPtr = '-'; // Add negative sign... - result = cs_strdup(BufPtr); - return result; + // suppose that result is big enough + strncpy(result, BufPtr, sizeof(Buffer)); } -// result must be a big enough buffer: 128 bytes is more than enough -void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result) +// NOTE: result must be big enough to contain the result +void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result) { + // assert(Bits < 0x10000); + char Op0Str[32], Op1Str[32], CRnStr[32], CRmStr[32], Op2Str[32]; int dummy; - uint32_t Op0, Op1, CRn, CRm, Op2; - char *Op0S, *Op1S, *CRnS, *CRmS, *Op2S; - unsigned i; + uint32_t Op0 = (Bits >> 14) & 0x3; + uint32_t Op1 = (Bits >> 11) & 0x7; + uint32_t CRn = (Bits >> 7) & 0xf; + uint32_t CRm = (Bits >> 3) & 0xf; + uint32_t Op2 = Bits & 0x7; - // First search the registers shared by all - for (i = 0; i < ARR_SIZE(SysRegPairs); ++i) { - if (SysRegPairs[i].Value == Bits) { - strcpy(result, SysRegPairs[i].Name); - return; - } - } + utostr(Op0, false, Op0Str); + utostr(Op1, false, Op1Str); + utostr(Op2, false, Op2Str); + utostr(CRn, false, CRnStr); + utostr(CRm, false, CRmStr); - // Next search for target specific registers - // if (FeatureBits & AArch64_ProcCyclone) { - if (true) { - for (i = 0; i < ARR_SIZE(CycloneSysRegPairs); ++i) { - if (CycloneSysRegPairs[i].Value == Bits) { - strcpy(result, CycloneSysRegPairs[i].Name); - return; - } - } - } - - // Now try the instruction-specific registers (either read-only or - // write-only). - for (i = 0; i < S->NumInstPairs; ++i) { - if (S->InstPairs[i].Value == Bits) { - strcpy(result, S->InstPairs[i].Name); - return; - } - } - - Op0 = (Bits >> 14) & 0x3; - Op1 = (Bits >> 11) & 0x7; - CRn = (Bits >> 7) & 0xf; - CRm = (Bits >> 3) & 0xf; - Op2 = Bits & 0x7; - - Op0S = utostr(Op0, false); - Op1S = utostr(Op1, false); - CRnS = utostr(CRn, false); - CRmS = utostr(CRm, false); - Op2S = utostr(Op2, false); - - //printf("Op1S: %s, CRnS: %s, CRmS: %s, Op2S: %s\n", Op1S, CRnS, CRmS, Op2S); - dummy = cs_snprintf(result, 128, "s3_%s_c%s_c%s_%s", Op1S, CRnS, CRmS, Op2S); + dummy = cs_snprintf(result, 128, "s%s_%s_c%s_c%s_%s", + Op0Str, Op1Str, CRnStr, CRmStr, Op2Str); (void)dummy; - - cs_mem_free(Op0S); - cs_mem_free(Op1S); - cs_mem_free(CRnS); - cs_mem_free(CRmS); - cs_mem_free(Op2S); } -const A64NamedImmMapper A64TLBI_TLBIMapper = { - TLBIPairs, - ARR_SIZE(TLBIPairs), - 0, -}; - -const A64NamedImmMapper A64AT_ATMapper = { - ATPairs, - ARR_SIZE(ATPairs), - 0, -}; - -const A64NamedImmMapper A64DB_DBarrierMapper = { - DBarrierPairs, - ARR_SIZE(DBarrierPairs), - 16, -}; - -const A64NamedImmMapper A64DC_DCMapper = { - DCPairs, - ARR_SIZE(DCPairs), - 0, -}; - -const A64NamedImmMapper A64IC_ICMapper = { - ICPairs, - ARR_SIZE(ICPairs), - 0, -}; - -const A64NamedImmMapper A64ISB_ISBMapper = { - ISBPairs, - ARR_SIZE(ISBPairs), - 16, -}; - -const A64NamedImmMapper A64PRFM_PRFMMapper = { - PRFMPairs, - ARR_SIZE(PRFMPairs), - 32, -}; - -const A64NamedImmMapper A64PState_PStateMapper = { - PStatePairs, - ARR_SIZE(PStatePairs), - 0, -}; - -const A64SysRegMapper AArch64_MRSMapper = { - NULL, - MRSPairs, - ARR_SIZE(MRSPairs), -}; - -const A64SysRegMapper AArch64_MSRMapper = { - NULL, - MSRPairs, - ARR_SIZE(MSRPairs), -}; - #endif diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h index 54e15201a..eeb7301d8 100644 --- a/arch/AArch64/AArch64BaseInfo.h +++ b/arch/AArch64/AArch64BaseInfo.h @@ -22,6 +22,7 @@ #include #include +#include "AArch64Mapping.h" #ifndef __cplusplus #if defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64) @@ -32,6 +33,7 @@ inline static unsigned getWRegFromXReg(unsigned Reg) { switch (Reg) { + default: break; case ARM64_REG_X0: return ARM64_REG_W0; case ARM64_REG_X1: return ARM64_REG_W1; case ARM64_REG_X2: return ARM64_REG_W2; @@ -107,6 +109,7 @@ inline static unsigned getXRegFromWReg(unsigned Reg) case ARM64_REG_W30: return ARM64_REG_LR; case ARM64_REG_WSP: return ARM64_REG_SP; case ARM64_REG_WZR: return ARM64_REG_XZR; + } // For anything else, return it unchanged. return Reg; @@ -193,83 +196,84 @@ inline static unsigned getDRegFromBReg(unsigned Reg) // For anything else, return it unchanged. return Reg; } + // // Enums corresponding to AArch64 condition codes // The CondCodes constants map directly to the 4-bit encoding of the // condition field for predicated instructions. -typedef enum A64CC_CondCode { // Meaning (integer) Meaning (floating-point) - A64CC_EQ = 0, // Equal Equal - A64CC_NE, // Not equal Not equal, or unordered - A64CC_HS, // Unsigned higher or same >, ==, or unordered - A64CC_LO, // Unsigned lower or same Less than - A64CC_MI, // Minus, negative Less than - A64CC_PL, // Plus, positive or zero >, ==, or unordered - A64CC_VS, // Overflow Unordered - A64CC_VC, // No overflow Ordered - A64CC_HI, // Unsigned higher Greater than, or unordered - A64CC_LS, // Unsigned lower or same Less than or equal - A64CC_GE, // Greater than or equal Greater than or equal - A64CC_LT, // Less than Less than, or unordered - A64CC_GT, // Signed greater than Greater than - A64CC_LE, // Signed less than or equal <, ==, or unordered - A64CC_AL, // Always (unconditional) Always (unconditional) - A64CC_NV, // Always (unconditional) Always (unconditional) +typedef enum AArch64CC_CondCode { // Meaning (integer) Meaning (floating-point) + AArch64CC_EQ = 0x0, // Equal Equal + AArch64CC_NE = 0x1, // Not equal Not equal, or unordered + AArch64CC_HS = 0x2, // Unsigned higher or same >, ==, or unordered + AArch64CC_LO = 0x3, // Unsigned lower Less than + AArch64CC_MI = 0x4, // Minus, negative Less than + AArch64CC_PL = 0x5, // Plus, positive or zero >, ==, or unordered + AArch64CC_VS = 0x6, // Overflow Unordered + AArch64CC_VC = 0x7, // No overflow Not unordered + AArch64CC_HI = 0x8, // Unsigned higher Greater than, or unordered + AArch64CC_LS = 0x9, // Unsigned lower or same Less than or equal + AArch64CC_GE = 0xa, // Greater than or equal Greater than or equal + AArch64CC_LT = 0xb, // Less than Less than, or unordered + AArch64CC_GT = 0xc, // Greater than Greater than + AArch64CC_LE = 0xd, // Less than or equal <, ==, or unordered + AArch64CC_AL = 0xe, // Always (unconditional) Always (unconditional) + AArch64CC_NV = 0xf, // Always (unconditional) Always (unconditional) // Note the NV exists purely to disassemble 0b1111. Execution is "always". - A64CC_Invalid -} A64CC_CondCode; + AArch64CC_Invalid +} AArch64CC_CondCode; -inline static const char *getCondCodeName(A64CC_CondCode CC) +inline static AArch64CC_CondCode getInvertedCondCode(AArch64CC_CondCode Code) +{ + // To reverse a condition it's necessary to only invert the low bit: + return (AArch64CC_CondCode)((unsigned)Code ^ 0x1); +} + +inline static const char *getCondCodeName(AArch64CC_CondCode CC) { switch (CC) { default: return NULL; // never reach - case A64CC_EQ: return "eq"; - case A64CC_NE: return "ne"; - case A64CC_HS: return "hs"; - case A64CC_LO: return "lo"; - case A64CC_MI: return "mi"; - case A64CC_PL: return "pl"; - case A64CC_VS: return "vs"; - case A64CC_VC: return "vc"; - case A64CC_HI: return "hi"; - case A64CC_LS: return "ls"; - case A64CC_GE: return "ge"; - case A64CC_LT: return "lt"; - case A64CC_GT: return "gt"; - case A64CC_LE: return "le"; - case A64CC_AL: return "al"; - case A64CC_NV: return "nv"; + case AArch64CC_EQ: return "eq"; + case AArch64CC_NE: return "ne"; + case AArch64CC_HS: return "hs"; + case AArch64CC_LO: return "lo"; + case AArch64CC_MI: return "mi"; + case AArch64CC_PL: return "pl"; + case AArch64CC_VS: return "vs"; + case AArch64CC_VC: return "vc"; + case AArch64CC_HI: return "hi"; + case AArch64CC_LS: return "ls"; + case AArch64CC_GE: return "ge"; + case AArch64CC_LT: return "lt"; + case AArch64CC_GT: return "gt"; + case AArch64CC_LE: return "le"; + case AArch64CC_AL: return "al"; + case AArch64CC_NV: return "nv"; } } -inline static A64CC_CondCode getInvertedCondCode(A64CC_CondCode Code) -{ - // To reverse a condition it's necessary to only invert the low bit: - return (A64CC_CondCode)((unsigned)Code ^ 0x1); -} - /// Given a condition code, return NZCV flags that would satisfy that condition. /// The flag bits are in the format expected by the ccmp instructions. /// Note that many different flag settings can satisfy a given condition code, /// this function just returns one of them. -inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) +inline static unsigned getNZCVToSatisfyCondCode(AArch64CC_CondCode Code) { // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. enum { N = 8, Z = 4, C = 2, V = 1 }; switch (Code) { default: // llvm_unreachable("Unknown condition code"); - case EQ: return Z; // Z == 1 - case NE: return 0; // Z == 0 - case HS: return C; // C == 1 - case LO: return 0; // C == 0 - case MI: return N; // N == 1 - case PL: return 0; // N == 0 - case VS: return V; // V == 1 - case VC: return 0; // V == 0 - case HI: return C; // C == 1 && Z == 0 - case LS: return 0; // C == 0 || Z == 1 - case GE: return 0; // N == V - case LT: return N; // N != V - case GT: return 0; // Z == 0 && N == V - case LE: return Z; // Z == 1 || N != V + case AArch64CC_EQ: return Z; // Z == 1 + case AArch64CC_NE: return 0; // Z == 0 + case AArch64CC_HS: return C; // C == 1 + case AArch64CC_LO: return 0; // C == 0 + case AArch64CC_MI: return N; // N == 1 + case AArch64CC_PL: return 0; // N == 0 + case AArch64CC_VS: return V; // V == 1 + case AArch64CC_VC: return 0; // V == 0 + case AArch64CC_HI: return C; // C == 1 && Z == 0 + case AArch64CC_LS: return 0; // C == 0 || Z == 1 + case AArch64CC_GE: return 0; // N == V + case AArch64CC_LT: return N; // N != V + case AArch64CC_GT: return 0; // Z == 0 && N == V + case AArch64CC_LE: return Z; // Z == 1 || N != V } } @@ -301,20 +305,6 @@ typedef struct A64SysRegMapper { size_t NumInstPairs; } A64SysRegMapper; -extern const A64SysRegMapper AArch64_MSRMapper; -extern const A64SysRegMapper AArch64_MRSMapper; - -extern const A64NamedImmMapper A64DB_DBarrierMapper; -extern const A64NamedImmMapper A64AT_ATMapper; -extern const A64NamedImmMapper A64DC_DCMapper; -extern const A64NamedImmMapper A64IC_ICMapper; -extern const A64NamedImmMapper A64ISB_ISBMapper; -extern const A64NamedImmMapper A64PRFM_PRFMMapper; -extern const A64NamedImmMapper A64PState_PStateMapper; -extern const A64NamedImmMapper A64TLBI_TLBIMapper; - -#include "AArch64GenSystemOperands.inc" - typedef enum A64SE_ShiftExtSpecifiers { A64SE_Invalid = -1, A64SE_LSL, @@ -354,9 +344,10 @@ typedef enum A64Layout_VectorLayout { A64Layout_VL_D } A64Layout_VectorLayout; -inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout) +inline static const char *AArch64VectorLayoutToString(A64Layout_VectorLayout Layout) { switch (Layout) { + default: return NULL; // never reach case A64Layout_VL_8B: return ".8b"; case A64Layout_VL_4H: return ".4h"; case A64Layout_VL_2S: return ".2s"; @@ -369,67 +360,167 @@ inline static const char *A64VectorLayoutToString(A64Layout_VectorLayout Layout) case A64Layout_VL_H: return ".h"; case A64Layout_VL_S: return ".s"; case A64Layout_VL_D: return ".d"; - default: return NULL; // never reach } } -bool A64Imms_isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t *Imm); +inline static A64Layout_VectorLayout AArch64StringToVectorLayout(char *LayoutStr) +{ + if (!strcmp(LayoutStr, ".8b")) + return A64Layout_VL_8B; -const char *A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid); + if (!strcmp(LayoutStr, ".4h")) + return A64Layout_VL_4H; -uint32_t A64NamedImmMapper_fromString(const A64NamedImmMapper *N, char *Name, bool *Valid); + if (!strcmp(LayoutStr, ".2s")) + return A64Layout_VL_2S; -bool A64NamedImmMapper_validImm(const A64NamedImmMapper *N, uint32_t Value); + if (!strcmp(LayoutStr, ".1d")) + return A64Layout_VL_1D; -void A64SysRegMapper_toString(const A64SysRegMapper *S, uint32_t Bits, char *result); + if (!strcmp(LayoutStr, ".16b")) + return A64Layout_VL_16B; + + if (!strcmp(LayoutStr, ".8h")) + return A64Layout_VL_8H; + + if (!strcmp(LayoutStr, ".4s")) + return A64Layout_VL_4S; + + if (!strcmp(LayoutStr, ".2d")) + return A64Layout_VL_2D; + + if (!strcmp(LayoutStr, ".b")) + return A64Layout_VL_B; + + if (!strcmp(LayoutStr, ".s")) + return A64Layout_VL_S; + + if (!strcmp(LayoutStr, ".d")) + return A64Layout_VL_D; + + return A64Layout_Invalid; +} /// Target Operand Flag enum. enum TOF { //===------------------------------------------------------------------===// // AArch64 Specific MachineOperand flags. + MO_NO_FLAG, + MO_FRAGMENT = 0xf, + /// MO_PAGE - A symbol operand with this flag represents the pc-relative /// offset of the 4K page containing the symbol. This is used with the /// ADRP instruction. MO_PAGE = 1, + /// MO_PAGEOFF - A symbol operand with this flag represents the offset of /// that symbol within a 4K page. This offset is added to the page address /// to produce the complete address. MO_PAGEOFF = 2, + /// MO_G3 - A symbol operand with this flag (granule 3) represents the high /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction MO_G3 = 3, + /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction MO_G2 = 4, + /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction MO_G1 = 5, + /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction MO_G0 = 6, + /// MO_HI12 - This flag indicates that a symbol operand represents the bits /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left- /// by-12-bits instruction. MO_HI12 = 7, + /// MO_GOT - This flag indicates that a symbol operand represents the /// address of the GOT entry for the symbol, rather than the address of /// the symbol itself. MO_GOT = 0x10, + /// MO_NC - Indicates whether the linker is expected to check the symbol /// reference for overflow. For example in an ADRP/ADD pair of relocations /// the ADRP usually does check, but not the ADD. MO_NC = 0x20, + /// MO_TLS - Indicates that the operand being accessed is some kind of /// thread-local symbol. On Darwin, only one type of thread-local access /// exists (pre linker-relaxation), but on ELF the TLSModel used for the /// referee will affect interpretation. MO_TLS = 0x40, + /// MO_DLLIMPORT - On a symbol operand, this represents that the reference /// to the symbol is for an import stub. This is used for DLL import /// storage class indication on Windows. MO_DLLIMPORT = 0x80, }; +typedef struct SysAlias { + const char *Name; + uint16_t Encoding; +} SysAlias; + +#define AT SysAlias +#define DB SysAlias +#define DC SysAlias +#define SVEPRFM SysAlias +#define PRFM SysAlias +#define PSB SysAlias +#define ISB SysAlias +#define TSB SysAlias +#define PState SysAlias +#define SVEPREDPAT SysAlias + +typedef struct SysAliasReg { + const char *Name; + uint16_t Encoding; + bool NeedsReg; +} SysAliasReg; + +#define IC SysAliasReg +#define TLBI SysAliasReg + +typedef struct SysAliasSysReg { + const char *Name; + uint16_t Encoding; + bool Readable; + bool Writeable; +} SysAliasSysReg; + +#define SysReg SysAliasSysReg + +typedef struct ExactFPImm { + const char *Name; + int Enum; + const char *Repr; +} ExactFPImm; + +const AT *lookupATByEncoding(uint16_t Encoding); +const DB *lookupDBByEncoding(uint16_t Encoding); +const DC *lookupDCByEncoding(uint16_t Encoding); +const IC *lookupICByEncoding(uint16_t Encoding); +const TLBI *lookupTLBIByEncoding(uint16_t Encoding); +const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding); +const PRFM *lookupPRFMByEncoding(uint16_t Encoding); +const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding); +const ISB *lookupISBByEncoding(uint16_t Encoding); +const TSB *lookupTSBByEncoding(uint16_t Encoding); +const SysReg *lookupSysRegByEncoding(uint16_t Encoding); +const PState *lookupPStateByEncoding(uint16_t Encoding); +const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding); +const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding); + +// NOTE: result must be 128 bytes to contain the result +void AArch64SysReg_genericRegisterString(uint32_t Bits, char *result); + +#include "AArch64GenSystemOperands_enum.inc" + #endif diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c index daadac69b..be8009840 100644 --- a/arch/AArch64/AArch64Disassembler.c +++ b/arch/AArch64/AArch64Disassembler.c @@ -38,81 +38,55 @@ // Forward declare these because the autogenerated code will reference them. // Definitions are further down. static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); + unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); + unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, - unsigned RegNo, uint64_t Address, - const void *Decoder); + unsigned RegNo, uint64_t Address, const void *Decoder); static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); - + uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, @@ -120,69 +94,49 @@ static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, uint64_t Address, const void *Decoder); static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, - uint32_t insn, - uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, - uint32_t insn, - uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, - uint32_t insn, uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, - uint32_t insn, - uint64_t Address, - const void *Decoder); + uint32_t insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, uint64_t Address, const void *Decoder); - static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder); + uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder); + uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder); + uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm, @@ -194,34 +148,39 @@ static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm, static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder); + unsigned RegNo, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder); + unsigned RegNo, uint64_t Addr, const void *Decoder); static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Address, - const void *Decoder); + uint64_t Address, const void *Decoder); static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, - const void *Decoder); + const void *Decoder, int Bits); static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, - const void *Decoder); + const void *Decoder, int ElementWidth); static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder); + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, + uint32_t insn, uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Addr, const void *Decoder); + static bool Check(DecodeStatus *Out, DecodeStatus In) { switch (In) { default: // never reach return true; + case MCDisassembler_Success: // Out stays the same. return true; + case MCDisassembler_SoftFail: *Out = In; return true; + case MCDisassembler_Fail: *Out = In; return false; @@ -230,7 +189,7 @@ static bool Check(DecodeStatus *Out, DecodeStatus In) } // Hacky: enable all features for disassembler -static uint64_t getFeatureBits(int feature) +uint64_t AArch64_getFeatureBits(int feature) { // enable all features return (uint64_t)-1; @@ -281,14 +240,17 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI, (code[1] << 8) | (code[0] << 0); // Calling the auto-generated decoder function. - result = decodeInstruction(DecoderTable32, MI, insn, Address, MRI, 0); + result = decodeInstruction_4(DecoderTable32, MI, insn, Address); if (result != MCDisassembler_Fail) { *Size = 4; + return result; } + // invalid code MCInst_clear(MI); *Size = 0; + return MCDisassembler_Fail; } @@ -314,21 +276,21 @@ static const unsigned FPR128DecoderTable[] = { }; static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; + if (RegNo > 31) return Fail; Register = FPR128DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { if (RegNo > 15) return Fail; @@ -347,8 +309,7 @@ static const unsigned FPR64DecoderTable[] = { }; static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -357,6 +318,7 @@ static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo, Register = FPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -371,8 +333,7 @@ static const unsigned FPR32DecoderTable[] = { }; static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -381,6 +342,7 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo, Register = FPR32DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -395,8 +357,7 @@ static const unsigned FPR16DecoderTable[] = { }; static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -405,6 +366,7 @@ static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo, Register = FPR16DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -419,8 +381,7 @@ static const unsigned FPR8DecoderTable[] = { }; static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -429,6 +390,7 @@ static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo, Register = FPR8DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -443,20 +405,21 @@ static const unsigned GPR64DecoderTable[] = { }; static DecodeStatus DecodeGPR64commonRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { + unsigned Register; + if (RegNo > 30) return Fail; - unsigned Register = GPR64DecoderTable[RegNo]; + Register = GPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -465,19 +428,24 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, Register = GPR64DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = GPR64DecoderTable[RegNo]; + + Register = GPR64DecoderTable[RegNo]; if (Register == AArch64_XZR) Register = AArch64_SP; + MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -492,67 +460,76 @@ static const unsigned GPR32DecoderTable[] = { }; static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) + uint64_t Addr, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = GPR32DecoderTable[RegNo]; + Register = GPR32DecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = GPR32DecoderTable[RegNo]; + Register = GPR32DecoderTable[RegNo]; if (Register == AArch64_WZR) Register = AArch64_WSP; + MCOperand_CreateReg0(Inst, Register); + return Success; } static const unsigned ZPRDecoderTable[] = { - AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, - AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, - AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, - AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, - AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, - AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, - AArch64_Z30, AArch64_Z31 + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, + AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, + AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, + AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, + AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, + AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, + AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27, + AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31 }; static DecodeStatus DecodeZPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = ZPRDecoderTable[RegNo]; + Register = ZPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } -static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) +static DecodeStatus DecodeZPR_4bRegisterClass(MCInst *Inst, unsigned RegNo, + uint64_t Address, const void *Decoder) { if (RegNo > 15) return Fail; + return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); } static DecodeStatus DecodeZPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { if (RegNo > 7) return Fail; + return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder); } @@ -568,13 +545,16 @@ static const unsigned ZZDecoderTable[] = { }; static DecodeStatus DecodeZPR2RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = ZZDecoderTable[RegNo]; + + Register = ZZDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -593,13 +573,16 @@ static const unsigned ZZZDecoderTable[] = { }; static DecodeStatus DecodeZPR3RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = ZZZDecoderTable[RegNo]; + + Register = ZZZDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -618,36 +601,42 @@ static const unsigned ZZZZDecoderTable[] = { }; static DecodeStatus DecodeZPR4RegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { + unsigned Register; + if (RegNo > 31) return Fail; - unsigned Register = ZZZZDecoderTable[RegNo]; + + Register = ZZZZDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static const unsigned PPRDecoderTable[] = { - AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, - AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, + AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, + AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, + AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15 }; static DecodeStatus DecodePPRRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, const void *Decoder) + uint64_t Addr, const void *Decoder) { + unsigned Register; + if (RegNo > 15) return Fail; - unsigned Register = PPRDecoderTable[RegNo]; + Register = PPRDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodePPR_3bRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { if (RegNo > 7) return Fail; @@ -667,8 +656,7 @@ static const unsigned VectorDecoderTable[] = { }; static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -677,6 +665,7 @@ static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo, Register = VectorDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -701,6 +690,7 @@ static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo, Register = QQDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -728,6 +718,7 @@ static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo, Register = QQQDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -746,15 +737,16 @@ static const unsigned QQQQDecoderTable[] = { }; static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; + if (RegNo > 31) return Fail; Register = QQQQDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -779,6 +771,7 @@ static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo, Register = DDDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -806,6 +799,7 @@ static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo, Register = DDDDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } @@ -824,8 +818,7 @@ static const unsigned DDDDDecoderTable[] = { }; static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { unsigned Register; @@ -834,24 +827,25 @@ static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo, Register = DDDDDecoderTable[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { // scale{5} is asserted as 1 in tblgen. Imm |= 0x20; MCOperand_CreateImm0(Inst, 64 - Imm); + return Success; } static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { MCOperand_CreateImm0(Inst, 64 - Imm); + return Success; } @@ -865,6 +859,7 @@ static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm, ImmVal |= ~((1LL << 19) - 1); MCOperand_CreateImm0(Inst, ImmVal); + return Success; } @@ -873,6 +868,7 @@ static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm, { MCOperand_CreateImm0(Inst, (Imm >> 1) & 1); MCOperand_CreateImm0(Inst, Imm & 1); + return Success; } @@ -887,8 +883,7 @@ static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm, } static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { MCOperand_CreateImm0(Inst, Imm); @@ -896,14 +891,13 @@ static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm, } static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, - const void *Decoder) + uint64_t Address, const void *Decoder) { // This decoder exists to add the dummy Lane operand to the MCInst, which must // be 1 in assembly but has no other real manifestation. - unsigned Rd = fieldFromInstruction(Insn, 0, 5); - unsigned Rn = fieldFromInstruction(Insn, 5, 5); - unsigned IsToVec = fieldFromInstruction(Insn, 16, 1); + unsigned Rd = fieldFromInstruction_4(Insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(Insn, 5, 5); + unsigned IsToVec = fieldFromInstruction_4(Insn, 16, 1); if (IsToVec) { DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); @@ -923,6 +917,7 @@ static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm, unsigned Add) { MCOperand_CreateImm0(Inst, Add - Imm); + return Success; } @@ -930,6 +925,7 @@ static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm, unsigned Add) { MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1)); + return Success; } @@ -940,8 +936,7 @@ static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm, } static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x20, 64); } @@ -953,8 +948,7 @@ static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm, } static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x10, 32); } @@ -966,8 +960,7 @@ static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm, } static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { return DecodeVecShiftRImm(Inst, Imm | 0x8, 16); } @@ -1003,19 +996,19 @@ static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm, } static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned Rm = fieldFromInstruction(insn, 16, 5); - unsigned shiftHi = fieldFromInstruction(insn, 22, 2); - unsigned shiftLo = fieldFromInstruction(insn, 10, 6); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rm = fieldFromInstruction_4(insn, 16, 5); + unsigned shiftHi = fieldFromInstruction_4(insn, 22, 2); + unsigned shiftLo = fieldFromInstruction_4(insn, 10, 6); unsigned shift = (shiftHi << 6) | shiftLo; switch (MCInst_getOpcode(Inst)) { default: return Fail; + case AArch64_ADDWrs: case AArch64_ADDSWrs: case AArch64_SUBWrs: @@ -1024,6 +1017,7 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, if (shiftHi == 0x3) return Fail; // Deliberate fallthrough + case AArch64_ANDWrs: case AArch64_ANDSWrs: case AArch64_BICWrs: @@ -1032,22 +1026,25 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, case AArch64_ORNWrs: case AArch64_EORWrs: case AArch64_EONWrs: { - // if sf == '0' and imm6<5> == '1' then ReservedValue() - if (shiftLo >> 5 == 1) - return Fail; - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - } + // if sf == '0' and imm6<5> == '1' then ReservedValue() + if (shiftLo >> 5 == 1) + return Fail; + + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + } + case AArch64_ADDXrs: case AArch64_ADDSXrs: case AArch64_SUBXrs: case AArch64_SUBSXrs: - // if shift == '11' then ReservedValue() - if (shiftHi == 0x3) - return Fail; - // Deliberate fallthrough + // if shift == '11' then ReservedValue() + if (shiftHi == 0x3) + return Fail; + // Deliberate fallthrough + case AArch64_ANDXrs: case AArch64_ANDSXrs: case AArch64_BICXrs: @@ -1056,29 +1053,30 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst, case AArch64_ORNXrs: case AArch64_EORXrs: case AArch64_EONXrs: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - break; + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; } MCOperand_CreateImm0(Inst, shift); + return Success; } static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - unsigned imm = fieldFromInstruction(insn, 5, 16); - unsigned shift = fieldFromInstruction(insn, 21, 2); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned imm = fieldFromInstruction_4(insn, 5, 16); + unsigned shift = fieldFromInstruction_4(insn, 21, 2); shift <<= 4; switch (MCInst_getOpcode(Inst)) { default: return Fail; + case AArch64_MOVZWi: case AArch64_MOVNWi: case AArch64_MOVKWi: @@ -1086,6 +1084,7 @@ static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, return Fail; DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); break; + case AArch64_MOVZXi: case AArch64_MOVNXi: case AArch64_MOVKXi: @@ -1099,24 +1098,26 @@ static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn, MCOperand_CreateImm0(Inst, imm); MCOperand_CreateImm0(Inst, shift); + return Success; } static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rt = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned offset = fieldFromInstruction(insn, 10, 12); + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned offset = fieldFromInstruction_4(insn, 10, 12); switch (MCInst_getOpcode(Inst)) { default: return Fail; + case AArch64_PRFMui: // Rt is an immediate in prefetch. MCOperand_CreateImm0(Inst, Rt); break; + case AArch64_STRBBui: case AArch64_LDRBBui: case AArch64_LDRSBWui: @@ -1127,6 +1128,7 @@ static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, case AArch64_LDRWui: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDRSBXui: case AArch64_LDRSHXui: case AArch64_LDRSWui: @@ -1134,22 +1136,27 @@ static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, case AArch64_LDRXui: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDRQui: case AArch64_STRQui: DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDRDui: case AArch64_STRDui: DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDRSui: case AArch64_STRSui: DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDRHui: case AArch64_STRHui: DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDRBui: case AArch64_STRBui: DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); @@ -1157,6 +1164,7 @@ static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, } DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4)) MCOperand_CreateImm0(Inst, offset); @@ -1164,15 +1172,12 @@ static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst, } static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - bool IsLoad; - bool IsIndexed; - bool IsFP; - unsigned Rt = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - int64_t offset = fieldFromInstruction(insn, 12, 9); + bool IsLoad, IsIndexed, IsFP; + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + int64_t offset = fieldFromInstruction_4(insn, 12, 9); // offset is a 9-bit signed immediate, so sign extend it to // fill the unsigned. @@ -1183,6 +1188,7 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, switch (MCInst_getOpcode(Inst)) { default: break; + case AArch64_LDRSBWpre: case AArch64_LDRSHWpre: case AArch64_STRBBpre: @@ -1236,10 +1242,12 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, switch (MCInst_getOpcode(Inst)) { default: return Fail; + case AArch64_PRFUMi: // Rt is an immediate in prefetch. MCOperand_CreateImm0(Inst, Rt); break; + case AArch64_STURBBi: case AArch64_LDURBBi: case AArch64_LDURSBWi: @@ -1272,8 +1280,17 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, case AArch64_LDRHHpost: case AArch64_STRWpost: case AArch64_LDRWpost: + case AArch64_STLURBi: + case AArch64_STLURHi: + case AArch64_STLURWi: + case AArch64_LDAPURBi: + case AArch64_LDAPURSBWi: + case AArch64_LDAPURHi: + case AArch64_LDAPURSHWi: + case AArch64_LDAPURi: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDURSBXi: case AArch64_LDURSHXi: case AArch64_LDURSWi: @@ -1294,8 +1311,14 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, case AArch64_STRXpost: case AArch64_LDRSWpost: case AArch64_LDRXpost: + case AArch64_LDAPURSWi: + case AArch64_LDAPURSHXi: + case AArch64_LDAPURSBXi: + case AArch64_STLURXi: + case AArch64_LDAPURXi: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDURQi: case AArch64_STURQi: case AArch64_LDRQpre: @@ -1304,6 +1327,7 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, case AArch64_STRQpost: DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDURDi: case AArch64_STURDi: case AArch64_LDRDpre: @@ -1312,6 +1336,7 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, case AArch64_STRDpost: DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDURSi: case AArch64_STURSi: case AArch64_LDRSpre: @@ -1320,6 +1345,7 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, case AArch64_STRSpost: DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDURHi: case AArch64_STURHi: case AArch64_LDRHpre: @@ -1328,6 +1354,7 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, case AArch64_STRHpost: DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_LDURBi: case AArch64_STURBi: case AArch64_LDRBpre: @@ -1341,9 +1368,9 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); MCOperand_CreateImm0(Inst, offset); - IsLoad = fieldFromInstruction(insn, 22, 1) != 0; - IsIndexed = fieldFromInstruction(insn, 10, 2) != 0; - IsFP = fieldFromInstruction(insn, 26, 1) != 0; + IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0; + IsIndexed = fieldFromInstruction_4(insn, 10, 2) != 0; + IsFP = fieldFromInstruction_4(insn, 26, 1) != 0; // Cannot write back to a transfer register (but xzr != sp). if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) @@ -1353,18 +1380,18 @@ static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst, } static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rt = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned Rt2 = fieldFromInstruction(insn, 10, 5); - unsigned Rs = fieldFromInstruction(insn, 16, 5); + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); + unsigned Rs = fieldFromInstruction_4(insn, 16, 5); unsigned Opcode = MCInst_getOpcode(Inst); switch (Opcode) { default: return Fail; + case AArch64_STLXRW: case AArch64_STLXRB: case AArch64_STLXRH: @@ -1385,8 +1412,15 @@ static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, case AArch64_STLRW: case AArch64_STLRB: case AArch64_STLRH: + case AArch64_STLLRW: + case AArch64_STLLRB: + case AArch64_STLLRH: + case AArch64_LDLARW: + case AArch64_LDLARB: + case AArch64_LDLARH: DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_STLXRX: case AArch64_STXRX: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); @@ -1395,8 +1429,11 @@ static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, case AArch64_LDAXRX: case AArch64_LDXRX: case AArch64_STLRX: + case AArch64_LDLARX: + case AArch64_STLLRX: DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); break; + case AArch64_STLXPW: case AArch64_STXPW: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); @@ -1406,6 +1443,7 @@ static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; + case AArch64_STLXPX: case AArch64_STXPX: DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder); @@ -1421,22 +1459,21 @@ static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst, // You shouldn't load to the same register twice in an instruction... if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW || - Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && - Rt == Rt2) + Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) && + Rt == Rt2) return SoftFail; return Success; } static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { - unsigned Rt = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned Rt2 = fieldFromInstruction(insn, 10, 5); - int32_t offset = fieldFromInstruction(insn, 15, 7); - bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0; + unsigned Rt = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Rt2 = fieldFromInstruction_4(insn, 10, 5); + int32_t offset = fieldFromInstruction_4(insn, 15, 7); + bool IsLoad = fieldFromInstruction_4(insn, 22, 1) != 0; unsigned Opcode = MCInst_getOpcode(Inst); bool NeedsDisjointWritebackTransfer = false; @@ -1449,6 +1486,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, switch (Opcode) { default: break; + case AArch64_LDPXpost: case AArch64_STPXpost: case AArch64_LDPSWpost: @@ -1478,6 +1516,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, switch (Opcode) { default: return Fail; + case AArch64_LDPXpost: case AArch64_STPXpost: case AArch64_LDPSWpost: @@ -1494,6 +1533,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; + case AArch64_LDPWpost: case AArch64_STPWpost: case AArch64_LDPWpre: @@ -1507,6 +1547,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); break; + case AArch64_LDNPQi: case AArch64_STNPQi: case AArch64_LDPQpost: @@ -1518,6 +1559,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); break; + case AArch64_LDNPDi: case AArch64_STNPDi: case AArch64_LDPDpost: @@ -1529,6 +1571,7 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); break; + case AArch64_LDNPSi: case AArch64_STNPSi: case AArch64_LDPSpost: @@ -1558,72 +1601,77 @@ static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn, } static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { unsigned Rd, Rn, Rm; - unsigned extend = fieldFromInstruction(insn, 10, 6); + unsigned extend = fieldFromInstruction_4(insn, 10, 6); unsigned shift = extend & 0x7; if (shift > 4) return Fail; - Rd = fieldFromInstruction(insn, 0, 5); - Rn = fieldFromInstruction(insn, 5, 5); - Rm = fieldFromInstruction(insn, 16, 5); + Rd = fieldFromInstruction_4(insn, 0, 5); + Rn = fieldFromInstruction_4(insn, 5, 5); + Rm = fieldFromInstruction_4(insn, 16, 5); switch (MCInst_getOpcode(Inst)) { - default: - return Fail; - case AArch64_ADDWrx: - case AArch64_SUBWrx: - DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - case AArch64_ADDSWrx: - case AArch64_SUBSWrx: - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - case AArch64_ADDXrx: - case AArch64_SUBXrx: - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - case AArch64_ADDSXrx: - case AArch64_SUBSXrx: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); - break; - case AArch64_ADDXrx64: - case AArch64_SUBXrx64: - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - break; - case AArch64_SUBSXrx64: - case AArch64_ADDSXrx64: - DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); - DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); - DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); - break; + default: + return Fail; + + case AArch64_ADDWrx: + case AArch64_SUBWrx: + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + + case AArch64_ADDSWrx: + case AArch64_SUBSWrx: + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + + case AArch64_ADDXrx: + case AArch64_SUBXrx: + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + + case AArch64_ADDSXrx: + case AArch64_SUBSXrx: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); + break; + + case AArch64_ADDXrx64: + case AArch64_SUBXrx64: + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; + + case AArch64_SUBSXrx64: + case AArch64_ADDSXrx64: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; } MCOperand_CreateImm0(Inst, extend); + return Success; } static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned Datasize = fieldFromInstruction(insn, 31, 1); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); unsigned imm; if (Datasize) { @@ -1631,8 +1679,10 @@ static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); - imm = fieldFromInstruction(insn, 10, 13); + + imm = fieldFromInstruction_4(insn, 10, 13); if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) return Fail; } else { @@ -1640,24 +1690,26 @@ static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst, DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); - imm = fieldFromInstruction(insn, 10, 12); + + imm = fieldFromInstruction_4(insn, 10, 12); if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32)) return Fail; } MCOperand_CreateImm0(Inst, imm); + return Success; } static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - unsigned cmode = fieldFromInstruction(insn, 12, 4); - unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; - imm |= fieldFromInstruction(insn, 5, 5); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned cmode = fieldFromInstruction_4(insn, 12, 4); + unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; + imm |= fieldFromInstruction_4(insn, 5, 5); if (MCInst_getOpcode(Inst) == AArch64_MOVID) DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder); @@ -1669,6 +1721,7 @@ static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, switch (MCInst_getOpcode(Inst)) { default: break; + case AArch64_MOVIv4i16: case AArch64_MOVIv8i16: case AArch64_MVNIv4i16: @@ -1679,6 +1732,7 @@ static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, case AArch64_MVNIv4i32: MCOperand_CreateImm0(Inst, (cmode & 6) << 2); break; + case AArch64_MOVIv2s_msl: case AArch64_MOVIv4s_msl: case AArch64_MVNIv2s_msl: @@ -1691,13 +1745,12 @@ static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn, } static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - unsigned cmode = fieldFromInstruction(insn, 12, 4); - unsigned imm = fieldFromInstruction(insn, 16, 3) << 5; - imm |= fieldFromInstruction(insn, 5, 5); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned cmode = fieldFromInstruction_4(insn, 12, 4); + unsigned imm = fieldFromInstruction_4(insn, 16, 3) << 5; + imm |= fieldFromInstruction_4(insn, 5, 5); // Tied operands added twice. DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder); @@ -1712,9 +1765,9 @@ static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst, static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - int64_t imm = fieldFromInstruction(insn, 5, 19) << 2; - imm |= fieldFromInstruction(insn, 29, 2); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + int64_t imm = fieldFromInstruction_4(insn, 5, 19) << 2; + imm |= fieldFromInstruction_4(insn, 29, 2); // Sign-extend the 21-bit immediate. if (imm & (1 << (21 - 1))) @@ -1730,11 +1783,11 @@ static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn, static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { - unsigned Rd = fieldFromInstruction(insn, 0, 5); - unsigned Rn = fieldFromInstruction(insn, 5, 5); - unsigned Imm = fieldFromInstruction(insn, 10, 14); - unsigned S = fieldFromInstruction(insn, 29, 1); - unsigned Datasize = fieldFromInstruction(insn, 31, 1); + unsigned Rd = fieldFromInstruction_4(insn, 0, 5); + unsigned Rn = fieldFromInstruction_4(insn, 5, 5); + unsigned Imm = fieldFromInstruction_4(insn, 10, 14); + unsigned S = fieldFromInstruction_4(insn, 29, 1); + unsigned Datasize = fieldFromInstruction_4(insn, 31, 1); unsigned ShifterVal = (Imm >> 12) & 3; unsigned ImmVal = Imm & 0xFFF; @@ -1747,26 +1800,28 @@ static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn, DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); } else { if (Rd == 31 && !S) DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); else DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder); } //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4)) MCOperand_CreateImm0(Inst, ImmVal); MCOperand_CreateImm0(Inst, 12 * ShifterVal); + return Success; } static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { - int64_t imm = fieldFromInstruction(insn, 0, 26); + int64_t imm = fieldFromInstruction_4(insn, 0, 26); // Sign-extend the 26-bit immediate. if (imm & (1 << (26 - 1))) @@ -1779,86 +1834,87 @@ static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, } static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst, - uint32_t insn, uint64_t Addr, - const void *Decoder) + uint32_t insn, uint64_t Addr, const void *Decoder) { - uint32_t op1 = fieldFromInstruction(insn, 16, 3); - uint32_t op2 = fieldFromInstruction(insn, 5, 3); - uint32_t crm = fieldFromInstruction(insn, 8, 4); - bool ValidNamed; + uint32_t op1 = fieldFromInstruction_4(insn, 16, 3); + uint32_t op2 = fieldFromInstruction_4(insn, 5, 3); + uint32_t crm = fieldFromInstruction_4(insn, 8, 4); uint32_t pstate_field = (op1 << 3) | op2; + if ((pstate_field == AArch64PState_PAN || + pstate_field == AArch64PState_UAO) && crm > 1) + return Fail; + MCOperand_CreateImm0(Inst, pstate_field); MCOperand_CreateImm0(Inst, crm); - A64NamedImmMapper_toString(&A64PState_PStateMapper, pstate_field, &ValidNamed); + if (lookupPStateByEncoding(pstate_field)) + return Success; - return ValidNamed ? Success : Fail; + return Fail; } static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn, uint64_t Addr, const void *Decoder) { - uint32_t Rt = fieldFromInstruction(insn, 0, 5); - uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5; - uint64_t dst = fieldFromInstruction(insn, 5, 14); + uint32_t Rt = fieldFromInstruction_4(insn, 0, 5); + uint32_t bit = fieldFromInstruction_4(insn, 31, 1) << 5; + uint64_t dst = fieldFromInstruction_4(insn, 5, 14); - bit |= fieldFromInstruction(insn, 19, 5); + bit |= fieldFromInstruction_4(insn, 19, 5); // Sign-extend 14-bit immediate. if (dst & (1 << (14 - 1))) dst |= ~((1LL << 14) - 1); - if (fieldFromInstruction(insn, 31, 1) == 0) + if (fieldFromInstruction_4(insn, 31, 1) == 0) DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); else DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); MCOperand_CreateImm0(Inst, bit); + //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4)) MCOperand_CreateImm0(Inst, dst); return Success; +} static DecodeStatus DecodeGPRSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegClassID, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) + unsigned RegClassID, unsigned RegNo, uint64_t Addr, const void *Decoder) { + unsigned Register; + // Register number must be even (see CASP instruction) if (RegNo & 0x1) return Fail; - unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); + Register = AArch64MCRegisterClasses[RegClassID].RegsBegin[RegNo]; MCOperand_CreateReg0(Inst, Register); + return Success; } static DecodeStatus DecodeWSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) + unsigned RegNo, uint64_t Addr, const void *Decoder) { - return DecodeGPRSeqPairsClassRegisterClass( - Inst, AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder); + return DecodeGPRSeqPairsClassRegisterClass(Inst, + AArch64_WSeqPairsClassRegClassID, RegNo, Addr, Decoder); } static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst *Inst, - unsigned RegNo, - uint64_t Addr, - const void *Decoder) + unsigned RegNo, uint64_t Addr, const void *Decoder) { - return DecodeGPRSeqPairsClassRegisterClass( - Inst, AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder); + return DecodeGPRSeqPairsClassRegisterClass(Inst, + AArch64_XSeqPairsClassRegClassID, RegNo, Addr, Decoder); } static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, - uint64_t Addr, - const void *Decoder) + uint64_t Addr, const void *Decoder) { - unsigned Zdn = fieldFromInstruction(insn, 0, 5); - unsigned imm = fieldFromInstruction(insn, 5, 13); + unsigned Zdn = fieldFromInstruction_4(insn, 0, 5); + unsigned imm = fieldFromInstruction_4(insn, 5, 13); + if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64)) return Fail; @@ -1866,12 +1922,14 @@ static DecodeStatus DecodeSVELogicalImmInstruction(MCInst *Inst, uint32_t insn, DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); if (MCInst_getOpcode(Inst) != AArch64_DUPM_ZI) DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + MCOperand_CreateImm0(Inst, imm); + return Success; } static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, - const void *Decoder) + const void *Decoder, int Bits) { if (Imm & ~((1LL << Bits) - 1)) return Fail; @@ -1881,49 +1939,53 @@ static DecodeStatus DecodeSImm(MCInst *Inst, uint64_t Imm, uint64_t Address, Imm |= ~((1LL << Bits) - 1); MCOperand_CreateImm0(Inst, Imm); + return Success; } // Decode 8-bit signed/unsigned immediate for a given element width. static DecodeStatus DecodeImm8OptLsl(MCInst *Inst, unsigned Imm, uint64_t Addr, - const void *Decoder) + const void *Decoder, int ElementWidth) { unsigned Val = (uint8_t)Imm; unsigned Shift = (Imm & 0x100) ? 8 : 0; + if (ElementWidth == 8 && Shift) return Fail; - MCInst_addOperand2(MCOperand_CreateImm0(Val)); - MCInst_addOperand2(MCOperand_CreateImm0(Shift)); + + MCOperand_CreateImm0(Inst, Val); + MCOperand_CreateImm0(Inst, Shift); + return Success; } // Decode uimm4 ranged from 1-16. static DecodeStatus DecodeSVEIncDecImm(MCInst *Inst, unsigned Imm, - uint64_t Addr, const void *Decoder) + uint64_t Addr, const void *Decoder) { - MCInst_addOperand2(MCOperand_CreateImm0(Imm + 1)); + MCOperand_CreateImm0(Inst, Imm + 1); + return Success; } void AArch64_init(MCRegisterInfo *MRI) { /* - InitMCRegisterInfo(AArch64RegDesc, 420, - RA, PC, - AArch64MCRegisterClasses, 43, - AArch64RegUnitRoots, 66, AArch64RegDiffLists, - AArch64RegStrings, - AArch64SubRegIdxLists, 53, - AArch64SubRegIdxRanges, - AArch64RegEncodingTable); + InitMCRegisterInfo(AArch64RegDesc, 661, + RA, PC, + AArch64MCRegisterClasses, 100, + AArch64RegUnitRoots, 115, AArch64RegDiffLists, + AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, + AArch64SubRegIdxLists, 100, + AArch64SubRegIdxRanges, AArch64RegEncodingTable); */ - MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420, + MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 661, 0, 0, - AArch64MCRegisterClasses, 43, + AArch64MCRegisterClasses, 100, 0, 0, AArch64RegDiffLists, 0, - AArch64SubRegIdxLists, 53, + AArch64SubRegIdxLists, 100, 0); } diff --git a/arch/AArch64/AArch64Disassembler.h b/arch/AArch64/AArch64Disassembler.h index 0eb55d62d..2816cbbc5 100644 --- a/arch/AArch64/AArch64Disassembler.h +++ b/arch/AArch64/AArch64Disassembler.h @@ -13,4 +13,6 @@ void AArch64_init(MCRegisterInfo *MRI); bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info); +uint64_t AArch64_getFeatureBits(int feature); + #endif diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc index 69dea4338..f6c96685a 100644 --- a/arch/AArch64/AArch64GenAsmWriter.inc +++ b/arch/AArch64/AArch64GenAsmWriter.inc @@ -1,2418 +1,5345 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| -|*Assembly Writer Source Fragment *| +|* Assembly Writer Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) +static void printInstruction(MCInst *MI, SStream *O) { - static const uint32_t OpInfo[] = { +#ifndef CAPSTONE_DIET + static const char AsmStrs[] = { + /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, + /* 9 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '0', 9, 0, + /* 20 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, + /* 31 */ 'l', 'd', '1', 9, 0, + /* 36 */ 't', 'r', 'n', '1', 9, 0, + /* 42 */ 'z', 'i', 'p', '1', 9, 0, + /* 48 */ 'u', 'z', 'p', '1', 9, 0, + /* 54 */ 'd', 'c', 'p', 's', '1', 9, 0, + /* 61 */ 's', 'm', '3', 's', 's', '1', 9, 0, + /* 69 */ 's', 't', '1', 9, 0, + /* 74 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, + /* 83 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '1', 9, 0, + /* 94 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, + /* 105 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '1', 9, 0, + /* 116 */ 'r', 'a', 'x', '1', 9, 0, + /* 122 */ 'r', 'e', 'v', '3', '2', 9, 0, + /* 129 */ 'l', 'd', '2', 9, 0, + /* 134 */ 's', 'h', 'a', '5', '1', '2', 'h', '2', 9, 0, + /* 144 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, + /* 154 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, + /* 162 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, + /* 170 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, + /* 180 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, + /* 188 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, + /* 196 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, + /* 204 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, + /* 212 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, + /* 220 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, + /* 228 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, + /* 236 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, + /* 244 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, + /* 252 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, + /* 260 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 270 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 278 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 286 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, + /* 294 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, + /* 304 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, + /* 312 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, + /* 320 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, + /* 328 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, + /* 337 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, + /* 346 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, + /* 355 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, + /* 364 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, + /* 374 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, + /* 384 */ 't', 'r', 'n', '2', 9, 0, + /* 390 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, + /* 398 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, + /* 406 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, + /* 414 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, + /* 424 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, + /* 435 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, + /* 444 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, + /* 453 */ 'z', 'i', 'p', '2', 9, 0, + /* 459 */ 'u', 'z', 'p', '2', 9, 0, + /* 465 */ 'd', 'c', 'p', 's', '2', 9, 0, + /* 472 */ 's', 't', '2', 9, 0, + /* 477 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, + /* 485 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, + /* 493 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, + /* 501 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, + /* 509 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '2', 9, 0, + /* 520 */ 'l', 'd', '3', 9, 0, + /* 525 */ 'e', 'o', 'r', '3', 9, 0, + /* 531 */ 'd', 'c', 'p', 's', '3', 9, 0, + /* 538 */ 's', 't', '3', 9, 0, + /* 543 */ 'r', 'e', 'v', '6', '4', 9, 0, + /* 550 */ 'l', 'd', '4', 9, 0, + /* 555 */ 's', 't', '4', 9, 0, + /* 560 */ 's', 'e', 't', 'f', '1', '6', 9, 0, + /* 568 */ 'r', 'e', 'v', '1', '6', 9, 0, + /* 575 */ 's', 'e', 't', 'f', '8', 9, 0, + /* 582 */ 's', 'm', '3', 't', 't', '1', 'a', 9, 0, + /* 591 */ 's', 'm', '3', 't', 't', '2', 'a', 9, 0, + /* 600 */ 'b', 'r', 'a', 'a', 9, 0, + /* 606 */ 'l', 'd', 'r', 'a', 'a', 9, 0, + /* 613 */ 'b', 'l', 'r', 'a', 'a', 9, 0, + /* 620 */ 's', 'a', 'b', 'a', 9, 0, + /* 626 */ 'u', 'a', 'b', 'a', 9, 0, + /* 632 */ 'p', 'a', 'c', 'd', 'a', 9, 0, + /* 639 */ 'l', 'd', 'a', 'd', 'd', 'a', 9, 0, + /* 647 */ 'f', 'a', 'd', 'd', 'a', 9, 0, + /* 654 */ 'a', 'u', 't', 'd', 'a', 9, 0, + /* 661 */ 'p', 'a', 'c', 'g', 'a', 9, 0, + /* 668 */ 'p', 'a', 'c', 'i', 'a', 9, 0, + /* 675 */ 'a', 'u', 't', 'i', 'a', 9, 0, + /* 682 */ 'b', 'r', 'k', 'a', 9, 0, + /* 688 */ 'f', 'c', 'm', 'l', 'a', 9, 0, + /* 695 */ 'f', 'm', 'l', 'a', 9, 0, + /* 701 */ 'f', 'n', 'm', 'l', 'a', 9, 0, + /* 708 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 9, 0, + /* 717 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 9, 0, + /* 726 */ 'b', 'r', 'k', 'p', 'a', 9, 0, + /* 733 */ 'c', 'a', 's', 'p', 'a', 9, 0, + /* 740 */ 's', 'w', 'p', 'a', 9, 0, + /* 746 */ 'f', 'e', 'x', 'p', 'a', 9, 0, + /* 753 */ 'l', 'd', 'c', 'l', 'r', 'a', 9, 0, + /* 761 */ 'l', 'd', 'e', 'o', 'r', 'a', 9, 0, + /* 769 */ 's', 'r', 's', 'r', 'a', 9, 0, + /* 776 */ 'u', 'r', 's', 'r', 'a', 9, 0, + /* 783 */ 's', 's', 'r', 'a', 9, 0, + /* 789 */ 'u', 's', 'r', 'a', 9, 0, + /* 795 */ 'c', 'a', 's', 'a', 9, 0, + /* 801 */ 'l', 'd', 's', 'e', 't', 'a', 9, 0, + /* 809 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, + /* 817 */ 'c', 'l', 'a', 's', 't', 'a', 9, 0, + /* 825 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 9, 0, + /* 834 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 9, 0, + /* 843 */ 'p', 'a', 'c', 'd', 'z', 'a', 9, 0, + /* 851 */ 'a', 'u', 't', 'd', 'z', 'a', 9, 0, + /* 859 */ 'p', 'a', 'c', 'i', 'z', 'a', 9, 0, + /* 867 */ 'a', 'u', 't', 'i', 'z', 'a', 9, 0, + /* 875 */ 'l', 'd', '1', 'b', 9, 0, + /* 881 */ 'l', 'd', 'f', 'f', '1', 'b', 9, 0, + /* 889 */ 'l', 'd', 'n', 'f', '1', 'b', 9, 0, + /* 897 */ 'l', 'd', 'n', 't', '1', 'b', 9, 0, + /* 905 */ 's', 't', 'n', 't', '1', 'b', 9, 0, + /* 913 */ 's', 't', '1', 'b', 9, 0, + /* 919 */ 's', 'm', '3', 't', 't', '1', 'b', 9, 0, + /* 928 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, + /* 936 */ 'l', 'd', '2', 'b', 9, 0, + /* 942 */ 's', 't', '2', 'b', 9, 0, + /* 948 */ 's', 'm', '3', 't', 't', '2', 'b', 9, 0, + /* 957 */ 'l', 'd', '3', 'b', 9, 0, + /* 963 */ 's', 't', '3', 'b', 9, 0, + /* 969 */ 'l', 'd', '4', 'b', 9, 0, + /* 975 */ 's', 't', '4', 'b', 9, 0, + /* 981 */ 'l', 'd', 'a', 'd', 'd', 'a', 'b', 9, 0, + /* 990 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'b', 9, 0, + /* 1000 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'b', 9, 0, + /* 1010 */ 's', 'w', 'p', 'a', 'b', 9, 0, + /* 1017 */ 'b', 'r', 'a', 'b', 9, 0, + /* 1023 */ 'l', 'd', 'r', 'a', 'b', 9, 0, + /* 1030 */ 'b', 'l', 'r', 'a', 'b', 9, 0, + /* 1037 */ 'l', 'd', 'c', 'l', 'r', 'a', 'b', 9, 0, + /* 1046 */ 'l', 'd', 'e', 'o', 'r', 'a', 'b', 9, 0, + /* 1055 */ 'c', 'a', 's', 'a', 'b', 9, 0, + /* 1062 */ 'l', 'd', 's', 'e', 't', 'a', 'b', 9, 0, + /* 1071 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'b', 9, 0, + /* 1081 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'b', 9, 0, + /* 1091 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, + /* 1100 */ 's', 'q', 'd', 'e', 'c', 'b', 9, 0, + /* 1108 */ 'u', 'q', 'd', 'e', 'c', 'b', 9, 0, + /* 1116 */ 's', 'q', 'i', 'n', 'c', 'b', 9, 0, + /* 1124 */ 'u', 'q', 'i', 'n', 'c', 'b', 9, 0, + /* 1132 */ 'p', 'a', 'c', 'd', 'b', 9, 0, + /* 1139 */ 'l', 'd', 'a', 'd', 'd', 'b', 9, 0, + /* 1147 */ 'a', 'u', 't', 'd', 'b', 9, 0, + /* 1154 */ 'p', 'r', 'f', 'b', 9, 0, + /* 1160 */ 'p', 'a', 'c', 'i', 'b', 9, 0, + /* 1167 */ 'a', 'u', 't', 'i', 'b', 9, 0, + /* 1174 */ 'b', 'r', 'k', 'b', 9, 0, + /* 1180 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'b', 9, 0, + /* 1190 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, + /* 1201 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, + /* 1212 */ 's', 'w', 'p', 'a', 'l', 'b', 9, 0, + /* 1220 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'b', 9, 0, + /* 1230 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'b', 9, 0, + /* 1240 */ 'c', 'a', 's', 'a', 'l', 'b', 9, 0, + /* 1248 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'b', 9, 0, + /* 1258 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, + /* 1269 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, + /* 1280 */ 'l', 'd', 'a', 'd', 'd', 'l', 'b', 9, 0, + /* 1289 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'b', 9, 0, + /* 1299 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'b', 9, 0, + /* 1309 */ 's', 'w', 'p', 'l', 'b', 9, 0, + /* 1316 */ 'l', 'd', 'c', 'l', 'r', 'l', 'b', 9, 0, + /* 1325 */ 'l', 'd', 'e', 'o', 'r', 'l', 'b', 9, 0, + /* 1334 */ 'c', 'a', 's', 'l', 'b', 9, 0, + /* 1341 */ 'l', 'd', 's', 'e', 't', 'l', 'b', 9, 0, + /* 1350 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'b', 9, 0, + /* 1360 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'b', 9, 0, + /* 1370 */ 'd', 'm', 'b', 9, 0, + /* 1375 */ 'l', 'd', 's', 'm', 'i', 'n', 'b', 9, 0, + /* 1384 */ 'l', 'd', 'u', 'm', 'i', 'n', 'b', 9, 0, + /* 1393 */ 'b', 'r', 'k', 'p', 'b', 9, 0, + /* 1400 */ 's', 'w', 'p', 'b', 9, 0, + /* 1406 */ 'l', 'd', '1', 'r', 'q', 'b', 9, 0, + /* 1414 */ 'l', 'd', '1', 'r', 'b', 9, 0, + /* 1421 */ 'l', 'd', 'a', 'r', 'b', 9, 0, + /* 1428 */ 'l', 'd', 'l', 'a', 'r', 'b', 9, 0, + /* 1436 */ 'l', 'd', 'r', 'b', 9, 0, + /* 1442 */ 'l', 'd', 'c', 'l', 'r', 'b', 9, 0, + /* 1450 */ 's', 't', 'l', 'l', 'r', 'b', 9, 0, + /* 1458 */ 's', 't', 'l', 'r', 'b', 9, 0, + /* 1465 */ 'l', 'd', 'e', 'o', 'r', 'b', 9, 0, + /* 1473 */ 'l', 'd', 'a', 'p', 'r', 'b', 9, 0, + /* 1481 */ 'l', 'd', 't', 'r', 'b', 9, 0, + /* 1488 */ 's', 't', 'r', 'b', 9, 0, + /* 1494 */ 's', 't', 't', 'r', 'b', 9, 0, + /* 1501 */ 'l', 'd', 'u', 'r', 'b', 9, 0, + /* 1508 */ 's', 't', 'l', 'u', 'r', 'b', 9, 0, + /* 1516 */ 'l', 'd', 'a', 'p', 'u', 'r', 'b', 9, 0, + /* 1525 */ 's', 't', 'u', 'r', 'b', 9, 0, + /* 1532 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, + /* 1540 */ 'l', 'd', 'x', 'r', 'b', 9, 0, + /* 1547 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, + /* 1555 */ 's', 't', 'x', 'r', 'b', 9, 0, + /* 1562 */ 'l', 'd', '1', 's', 'b', 9, 0, + /* 1569 */ 'l', 'd', 'f', 'f', '1', 's', 'b', 9, 0, + /* 1578 */ 'l', 'd', 'n', 'f', '1', 's', 'b', 9, 0, + /* 1587 */ 'c', 'a', 's', 'b', 9, 0, + /* 1593 */ 'd', 's', 'b', 9, 0, + /* 1598 */ 'i', 's', 'b', 9, 0, + /* 1603 */ 'f', 'm', 's', 'b', 9, 0, + /* 1609 */ 'f', 'n', 'm', 's', 'b', 9, 0, + /* 1616 */ 'l', 'd', '1', 'r', 's', 'b', 9, 0, + /* 1624 */ 'l', 'd', 'r', 's', 'b', 9, 0, + /* 1631 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, + /* 1639 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, + /* 1647 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'b', 9, 0, + /* 1657 */ 't', 's', 'b', 9, 0, + /* 1662 */ 'l', 'd', 's', 'e', 't', 'b', 9, 0, + /* 1670 */ 'c', 'n', 't', 'b', 9, 0, + /* 1676 */ 'c', 'l', 'a', 's', 't', 'b', 9, 0, + /* 1684 */ 's', 'x', 't', 'b', 9, 0, + /* 1690 */ 'u', 'x', 't', 'b', 9, 0, + /* 1696 */ 'f', 's', 'u', 'b', 9, 0, + /* 1702 */ 's', 'h', 's', 'u', 'b', 9, 0, + /* 1709 */ 'u', 'h', 's', 'u', 'b', 9, 0, + /* 1716 */ 'f', 'm', 's', 'u', 'b', 9, 0, + /* 1723 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, + /* 1731 */ 's', 'q', 's', 'u', 'b', 9, 0, + /* 1738 */ 'u', 'q', 's', 'u', 'b', 9, 0, + /* 1745 */ 'r', 'e', 'v', 'b', 9, 0, + /* 1751 */ 'l', 'd', 's', 'm', 'a', 'x', 'b', 9, 0, + /* 1760 */ 'l', 'd', 'u', 'm', 'a', 'x', 'b', 9, 0, + /* 1769 */ 'p', 'a', 'c', 'd', 'z', 'b', 9, 0, + /* 1777 */ 'a', 'u', 't', 'd', 'z', 'b', 9, 0, + /* 1785 */ 'p', 'a', 'c', 'i', 'z', 'b', 9, 0, + /* 1793 */ 'a', 'u', 't', 'i', 'z', 'b', 9, 0, + /* 1801 */ 's', 'h', 'a', '1', 'c', 9, 0, + /* 1808 */ 's', 'b', 'c', 9, 0, + /* 1813 */ 'a', 'd', 'c', 9, 0, + /* 1818 */ 'b', 'i', 'c', 9, 0, + /* 1823 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, + /* 1831 */ 'a', 'e', 's', 'm', 'c', 9, 0, + /* 1838 */ 'c', 's', 'i', 'n', 'c', 9, 0, + /* 1845 */ 'h', 'v', 'c', 9, 0, + /* 1850 */ 's', 'v', 'c', 9, 0, + /* 1855 */ 'l', 'd', '1', 'd', 9, 0, + /* 1861 */ 'l', 'd', 'f', 'f', '1', 'd', 9, 0, + /* 1869 */ 'l', 'd', 'n', 'f', '1', 'd', 9, 0, + /* 1877 */ 'l', 'd', 'n', 't', '1', 'd', 9, 0, + /* 1885 */ 's', 't', 'n', 't', '1', 'd', 9, 0, + /* 1893 */ 's', 't', '1', 'd', 9, 0, + /* 1899 */ 'l', 'd', '2', 'd', 9, 0, + /* 1905 */ 's', 't', '2', 'd', 9, 0, + /* 1911 */ 'l', 'd', '3', 'd', 9, 0, + /* 1917 */ 's', 't', '3', 'd', 9, 0, + /* 1923 */ 'l', 'd', '4', 'd', 9, 0, + /* 1929 */ 's', 't', '4', 'd', 9, 0, + /* 1935 */ 'f', 'm', 'a', 'd', 9, 0, + /* 1941 */ 'f', 'n', 'm', 'a', 'd', 9, 0, + /* 1948 */ 'f', 't', 'm', 'a', 'd', 9, 0, + /* 1955 */ 'f', 'a', 'b', 'd', 9, 0, + /* 1961 */ 's', 'a', 'b', 'd', 9, 0, + /* 1967 */ 'u', 'a', 'b', 'd', 9, 0, + /* 1973 */ 'x', 'p', 'a', 'c', 'd', 9, 0, + /* 1980 */ 's', 'q', 'd', 'e', 'c', 'd', 9, 0, + /* 1988 */ 'u', 'q', 'd', 'e', 'c', 'd', 9, 0, + /* 1996 */ 's', 'q', 'i', 'n', 'c', 'd', 9, 0, + /* 2004 */ 'u', 'q', 'i', 'n', 'c', 'd', 9, 0, + /* 2012 */ 'f', 'c', 'a', 'd', 'd', 9, 0, + /* 2019 */ 'l', 'd', 'a', 'd', 'd', 9, 0, + /* 2026 */ 'f', 'a', 'd', 'd', 9, 0, + /* 2032 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, + /* 2040 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, + /* 2048 */ 's', 'h', 'a', 'd', 'd', 9, 0, + /* 2055 */ 'u', 'h', 'a', 'd', 'd', 9, 0, + /* 2062 */ 'f', 'm', 'a', 'd', 'd', 9, 0, + /* 2069 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, + /* 2077 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, + /* 2085 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, + /* 2093 */ 'p', 'r', 'f', 'd', 9, 0, + /* 2099 */ 'n', 'a', 'n', 'd', 9, 0, + /* 2105 */ 'l', 'd', '1', 'r', 'q', 'd', 9, 0, + /* 2113 */ 'l', 'd', '1', 'r', 'd', 9, 0, + /* 2120 */ 'a', 's', 'r', 'd', 9, 0, + /* 2126 */ 'a', 'e', 's', 'd', 9, 0, + /* 2132 */ 'c', 'n', 't', 'd', 9, 0, + /* 2138 */ 's', 'm', '4', 'e', 9, 0, + /* 2144 */ 's', 'p', 'l', 'i', 'c', 'e', 9, 0, + /* 2152 */ 'f', 'a', 'c', 'g', 'e', 9, 0, + /* 2159 */ 'f', 'c', 'm', 'g', 'e', 9, 0, + /* 2166 */ 'c', 'm', 'p', 'g', 'e', 9, 0, + /* 2173 */ 'f', 's', 'c', 'a', 'l', 'e', 9, 0, + /* 2181 */ 'w', 'h', 'i', 'l', 'e', 'l', 'e', 9, 0, + /* 2190 */ 'f', 'c', 'm', 'l', 'e', 9, 0, + /* 2197 */ 'c', 'm', 'p', 'l', 'e', 9, 0, + /* 2204 */ 'f', 'c', 'm', 'n', 'e', 9, 0, + /* 2211 */ 'c', 't', 'e', 'r', 'm', 'n', 'e', 9, 0, + /* 2220 */ 'c', 'm', 'p', 'n', 'e', 9, 0, + /* 2227 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, + /* 2235 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, + /* 2243 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, + /* 2251 */ 'f', 'c', 'm', 'p', 'e', 9, 0, + /* 2258 */ 'a', 'e', 's', 'e', 9, 0, + /* 2264 */ 'p', 'f', 'a', 'l', 's', 'e', 9, 0, + /* 2272 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, + /* 2281 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, + /* 2290 */ 'p', 't', 'r', 'u', 'e', 9, 0, + /* 2297 */ 'b', 'i', 'f', 9, 0, + /* 2302 */ 'r', 'm', 'i', 'f', 9, 0, + /* 2308 */ 's', 'c', 'v', 't', 'f', 9, 0, + /* 2315 */ 'u', 'c', 'v', 't', 'f', 9, 0, + /* 2322 */ 'f', 'n', 'e', 'g', 9, 0, + /* 2328 */ 's', 'q', 'n', 'e', 'g', 9, 0, + /* 2335 */ 'c', 's', 'n', 'e', 'g', 9, 0, + /* 2342 */ 's', 'h', 'a', '1', 'h', 9, 0, + /* 2349 */ 'l', 'd', '1', 'h', 9, 0, + /* 2355 */ 'l', 'd', 'f', 'f', '1', 'h', 9, 0, + /* 2363 */ 'l', 'd', 'n', 'f', '1', 'h', 9, 0, + /* 2371 */ 'l', 'd', 'n', 't', '1', 'h', 9, 0, + /* 2379 */ 's', 't', 'n', 't', '1', 'h', 9, 0, + /* 2387 */ 's', 't', '1', 'h', 9, 0, + /* 2393 */ 's', 'h', 'a', '5', '1', '2', 'h', 9, 0, + /* 2402 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, + /* 2410 */ 'l', 'd', '2', 'h', 9, 0, + /* 2416 */ 's', 't', '2', 'h', 9, 0, + /* 2422 */ 'l', 'd', '3', 'h', 9, 0, + /* 2428 */ 's', 't', '3', 'h', 9, 0, + /* 2434 */ 'l', 'd', '4', 'h', 9, 0, + /* 2440 */ 's', 't', '4', 'h', 9, 0, + /* 2446 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, + /* 2455 */ 'l', 'd', 'a', 'd', 'd', 'a', 'h', 9, 0, + /* 2464 */ 's', 'q', 'r', 'd', 'm', 'l', 'a', 'h', 9, 0, + /* 2474 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'h', 9, 0, + /* 2484 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'h', 9, 0, + /* 2494 */ 's', 'w', 'p', 'a', 'h', 9, 0, + /* 2501 */ 'l', 'd', 'c', 'l', 'r', 'a', 'h', 9, 0, + /* 2510 */ 'l', 'd', 'e', 'o', 'r', 'a', 'h', 9, 0, + /* 2519 */ 'c', 'a', 's', 'a', 'h', 9, 0, + /* 2526 */ 'l', 'd', 's', 'e', 't', 'a', 'h', 9, 0, + /* 2535 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'h', 9, 0, + /* 2545 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'h', 9, 0, + /* 2555 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, + /* 2564 */ 's', 'q', 'd', 'e', 'c', 'h', 9, 0, + /* 2572 */ 'u', 'q', 'd', 'e', 'c', 'h', 9, 0, + /* 2580 */ 's', 'q', 'i', 'n', 'c', 'h', 9, 0, + /* 2588 */ 'u', 'q', 'i', 'n', 'c', 'h', 9, 0, + /* 2596 */ 'l', 'd', 'a', 'd', 'd', 'h', 9, 0, + /* 2604 */ 'p', 'r', 'f', 'h', 9, 0, + /* 2610 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'h', 9, 0, + /* 2620 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, + /* 2631 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, + /* 2642 */ 's', 'w', 'p', 'a', 'l', 'h', 9, 0, + /* 2650 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'h', 9, 0, + /* 2660 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'h', 9, 0, + /* 2670 */ 'c', 'a', 's', 'a', 'l', 'h', 9, 0, + /* 2678 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'h', 9, 0, + /* 2688 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, + /* 2699 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, + /* 2710 */ 'l', 'd', 'a', 'd', 'd', 'l', 'h', 9, 0, + /* 2719 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'h', 9, 0, + /* 2729 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'h', 9, 0, + /* 2739 */ 's', 'w', 'p', 'l', 'h', 9, 0, + /* 2746 */ 'l', 'd', 'c', 'l', 'r', 'l', 'h', 9, 0, + /* 2755 */ 'l', 'd', 'e', 'o', 'r', 'l', 'h', 9, 0, + /* 2764 */ 'c', 'a', 's', 'l', 'h', 9, 0, + /* 2771 */ 'l', 'd', 's', 'e', 't', 'l', 'h', 9, 0, + /* 2780 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, + /* 2789 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, + /* 2799 */ 's', 'm', 'u', 'l', 'h', 9, 0, + /* 2806 */ 'u', 'm', 'u', 'l', 'h', 9, 0, + /* 2813 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'h', 9, 0, + /* 2823 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'h', 9, 0, + /* 2833 */ 'l', 'd', 's', 'm', 'i', 'n', 'h', 9, 0, + /* 2842 */ 'l', 'd', 'u', 'm', 'i', 'n', 'h', 9, 0, + /* 2851 */ 's', 'w', 'p', 'h', 9, 0, + /* 2857 */ 'l', 'd', '1', 'r', 'q', 'h', 9, 0, + /* 2865 */ 'l', 'd', '1', 'r', 'h', 9, 0, + /* 2872 */ 'l', 'd', 'a', 'r', 'h', 9, 0, + /* 2879 */ 'l', 'd', 'l', 'a', 'r', 'h', 9, 0, + /* 2887 */ 'l', 'd', 'r', 'h', 9, 0, + /* 2893 */ 'l', 'd', 'c', 'l', 'r', 'h', 9, 0, + /* 2901 */ 's', 't', 'l', 'l', 'r', 'h', 9, 0, + /* 2909 */ 's', 't', 'l', 'r', 'h', 9, 0, + /* 2916 */ 'l', 'd', 'e', 'o', 'r', 'h', 9, 0, + /* 2924 */ 'l', 'd', 'a', 'p', 'r', 'h', 9, 0, + /* 2932 */ 'l', 'd', 't', 'r', 'h', 9, 0, + /* 2939 */ 's', 't', 'r', 'h', 9, 0, + /* 2945 */ 's', 't', 't', 'r', 'h', 9, 0, + /* 2952 */ 'l', 'd', 'u', 'r', 'h', 9, 0, + /* 2959 */ 's', 't', 'l', 'u', 'r', 'h', 9, 0, + /* 2967 */ 'l', 'd', 'a', 'p', 'u', 'r', 'h', 9, 0, + /* 2976 */ 's', 't', 'u', 'r', 'h', 9, 0, + /* 2983 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, + /* 2991 */ 'l', 'd', 'x', 'r', 'h', 9, 0, + /* 2998 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, + /* 3006 */ 's', 't', 'x', 'r', 'h', 9, 0, + /* 3013 */ 'l', 'd', '1', 's', 'h', 9, 0, + /* 3020 */ 'l', 'd', 'f', 'f', '1', 's', 'h', 9, 0, + /* 3029 */ 'l', 'd', 'n', 'f', '1', 's', 'h', 9, 0, + /* 3038 */ 'c', 'a', 's', 'h', 9, 0, + /* 3044 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', 9, 0, + /* 3054 */ 'l', 'd', '1', 'r', 's', 'h', 9, 0, + /* 3062 */ 'l', 'd', 'r', 's', 'h', 9, 0, + /* 3069 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, + /* 3077 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, + /* 3085 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'h', 9, 0, + /* 3095 */ 'l', 'd', 's', 'e', 't', 'h', 9, 0, + /* 3103 */ 'c', 'n', 't', 'h', 9, 0, + /* 3109 */ 's', 'x', 't', 'h', 9, 0, + /* 3115 */ 'u', 'x', 't', 'h', 9, 0, + /* 3121 */ 'r', 'e', 'v', 'h', 9, 0, + /* 3127 */ 'l', 'd', 's', 'm', 'a', 'x', 'h', 9, 0, + /* 3136 */ 'l', 'd', 'u', 'm', 'a', 'x', 'h', 9, 0, + /* 3145 */ 'x', 'p', 'a', 'c', 'i', 9, 0, + /* 3152 */ 'p', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, + /* 3161 */ 's', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, + /* 3170 */ 'u', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, + /* 3179 */ 'c', 'm', 'h', 'i', 9, 0, + /* 3185 */ 'c', 'm', 'p', 'h', 'i', 9, 0, + /* 3192 */ 's', 'l', 'i', 9, 0, + /* 3197 */ 'm', 'v', 'n', 'i', 9, 0, + /* 3203 */ 's', 'r', 'i', 9, 0, + /* 3208 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, + /* 3216 */ 'm', 'o', 'v', 'i', 9, 0, + /* 3222 */ 'b', 'r', 'k', 9, 0, + /* 3227 */ 'm', 'o', 'v', 'k', 9, 0, + /* 3233 */ 's', 'a', 'b', 'a', 'l', 9, 0, + /* 3240 */ 'u', 'a', 'b', 'a', 'l', 9, 0, + /* 3247 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 9, 0, + /* 3256 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, + /* 3265 */ 's', 'm', 'l', 'a', 'l', 9, 0, + /* 3272 */ 'u', 'm', 'l', 'a', 'l', 9, 0, + /* 3279 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 9, 0, + /* 3289 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 9, 0, + /* 3299 */ 'c', 'a', 's', 'p', 'a', 'l', 9, 0, + /* 3307 */ 's', 'w', 'p', 'a', 'l', 9, 0, + /* 3314 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 9, 0, + /* 3323 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 9, 0, + /* 3332 */ 'c', 'a', 's', 'a', 'l', 9, 0, + /* 3339 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 9, 0, + /* 3348 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 9, 0, + /* 3358 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 9, 0, + /* 3368 */ 't', 'b', 'l', 9, 0, + /* 3373 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, + /* 3381 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, + /* 3389 */ 's', 's', 'u', 'b', 'l', 9, 0, + /* 3396 */ 'u', 's', 'u', 'b', 'l', 9, 0, + /* 3403 */ 's', 'a', 'b', 'd', 'l', 9, 0, + /* 3410 */ 'u', 'a', 'b', 'd', 'l', 9, 0, + /* 3417 */ 'l', 'd', 'a', 'd', 'd', 'l', 9, 0, + /* 3425 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, + /* 3433 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, + /* 3441 */ 's', 'a', 'd', 'd', 'l', 9, 0, + /* 3448 */ 'u', 'a', 'd', 'd', 'l', 9, 0, + /* 3455 */ 'f', 'c', 's', 'e', 'l', 9, 0, + /* 3462 */ 'f', 't', 's', 's', 'e', 'l', 9, 0, + /* 3470 */ 's', 'q', 's', 'h', 'l', 9, 0, + /* 3477 */ 'u', 'q', 's', 'h', 'l', 9, 0, + /* 3484 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, + /* 3492 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, + /* 3500 */ 's', 'r', 's', 'h', 'l', 9, 0, + /* 3507 */ 'u', 'r', 's', 'h', 'l', 9, 0, + /* 3514 */ 's', 's', 'h', 'l', 9, 0, + /* 3520 */ 'u', 's', 'h', 'l', 9, 0, + /* 3526 */ 's', 's', 'h', 'l', 'l', 9, 0, + /* 3533 */ 'u', 's', 'h', 'l', 'l', 9, 0, + /* 3540 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, + /* 3549 */ 'p', 'm', 'u', 'l', 'l', 9, 0, + /* 3556 */ 's', 'm', 'u', 'l', 'l', 9, 0, + /* 3563 */ 'u', 'm', 'u', 'l', 'l', 9, 0, + /* 3570 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 9, 0, + /* 3579 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 9, 0, + /* 3588 */ 'a', 'd', 'd', 'p', 'l', 9, 0, + /* 3595 */ 'c', 'a', 's', 'p', 'l', 9, 0, + /* 3602 */ 's', 'w', 'p', 'l', 9, 0, + /* 3608 */ 'l', 'd', 'c', 'l', 'r', 'l', 9, 0, + /* 3616 */ 'l', 'd', 'e', 'o', 'r', 'l', 9, 0, + /* 3624 */ 'c', 'a', 's', 'l', 9, 0, + /* 3630 */ 'b', 's', 'l', 9, 0, + /* 3635 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, + /* 3644 */ 's', 'm', 'l', 's', 'l', 9, 0, + /* 3651 */ 'u', 'm', 'l', 's', 'l', 9, 0, + /* 3658 */ 's', 'y', 's', 'l', 9, 0, + /* 3664 */ 'l', 'd', 's', 'e', 't', 'l', 9, 0, + /* 3672 */ 'f', 'c', 'v', 't', 'l', 9, 0, + /* 3679 */ 'f', 'm', 'u', 'l', 9, 0, + /* 3685 */ 'f', 'n', 'm', 'u', 'l', 9, 0, + /* 3692 */ 'p', 'm', 'u', 'l', 9, 0, + /* 3698 */ 'f', 't', 's', 'm', 'u', 'l', 9, 0, + /* 3706 */ 'a', 'd', 'd', 'v', 'l', 9, 0, + /* 3713 */ 'r', 'd', 'v', 'l', 9, 0, + /* 3719 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 9, 0, + /* 3728 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 9, 0, + /* 3737 */ 's', 'h', 'a', '1', 'm', 9, 0, + /* 3744 */ 's', 'b', 'f', 'm', 9, 0, + /* 3750 */ 'u', 'b', 'f', 'm', 9, 0, + /* 3756 */ 'p', 'r', 'f', 'm', 9, 0, + /* 3762 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, + /* 3770 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, + /* 3778 */ 'd', 'u', 'p', 'm', 9, 0, + /* 3784 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, + /* 3792 */ 'p', 'r', 'f', 'u', 'm', 9, 0, + /* 3799 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, + /* 3807 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, + /* 3815 */ 'f', 'm', 'i', 'n', 9, 0, + /* 3821 */ 'l', 'd', 's', 'm', 'i', 'n', 9, 0, + /* 3829 */ 'l', 'd', 'u', 'm', 'i', 'n', 9, 0, + /* 3837 */ 'b', 'r', 'k', 'n', 9, 0, + /* 3843 */ 'c', 'c', 'm', 'n', 9, 0, + /* 3849 */ 'e', 'o', 'n', 9, 0, + /* 3854 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, + /* 3862 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, + /* 3870 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, + /* 3879 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, + /* 3888 */ 'o', 'r', 'n', 9, 0, + /* 3893 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, + /* 3901 */ 'f', 'c', 'v', 't', 'n', 9, 0, + /* 3908 */ 's', 'q', 'x', 't', 'n', 9, 0, + /* 3915 */ 'u', 'q', 'x', 't', 'n', 9, 0, + /* 3922 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, + /* 3931 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, + /* 3941 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, + /* 3949 */ 'm', 'o', 'v', 'n', 9, 0, + /* 3955 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, + /* 3963 */ 'w', 'h', 'i', 'l', 'e', 'l', 'o', 9, 0, + /* 3972 */ 'p', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, + /* 3981 */ 's', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, + /* 3990 */ 'u', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, + /* 3999 */ 'c', 'm', 'p', 'l', 'o', 9, 0, + /* 4006 */ 'f', 'c', 'm', 'u', 'o', 9, 0, + /* 4013 */ 's', 'h', 'a', '1', 'p', 9, 0, + /* 4020 */ 's', 'q', 'd', 'e', 'c', 'p', 9, 0, + /* 4028 */ 'u', 'q', 'd', 'e', 'c', 'p', 9, 0, + /* 4036 */ 's', 'q', 'i', 'n', 'c', 'p', 9, 0, + /* 4044 */ 'u', 'q', 'i', 'n', 'c', 'p', 9, 0, + /* 4052 */ 'f', 'a', 'd', 'd', 'p', 9, 0, + /* 4059 */ 'l', 'd', 'p', 9, 0, + /* 4064 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, + /* 4072 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, + /* 4080 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, + /* 4088 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, + /* 4096 */ 'f', 'c', 'c', 'm', 'p', 9, 0, + /* 4103 */ 'f', 'c', 'm', 'p', 9, 0, + /* 4109 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, + /* 4118 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, + /* 4127 */ 'l', 'd', 'n', 'p', 9, 0, + /* 4133 */ 'f', 'm', 'i', 'n', 'p', 9, 0, + /* 4140 */ 's', 'm', 'i', 'n', 'p', 9, 0, + /* 4147 */ 'u', 'm', 'i', 'n', 'p', 9, 0, + /* 4154 */ 's', 't', 'n', 'p', 9, 0, + /* 4160 */ 'a', 'd', 'r', 'p', 9, 0, + /* 4166 */ 'c', 'a', 's', 'p', 9, 0, + /* 4172 */ 'c', 'n', 't', 'p', 9, 0, + /* 4178 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, + /* 4186 */ 's', 't', 'p', 9, 0, + /* 4191 */ 'f', 'd', 'u', 'p', 9, 0, + /* 4197 */ 's', 'w', 'p', 9, 0, + /* 4202 */ 'l', 'd', 'a', 'x', 'p', 9, 0, + /* 4209 */ 'f', 'm', 'a', 'x', 'p', 9, 0, + /* 4216 */ 's', 'm', 'a', 'x', 'p', 9, 0, + /* 4223 */ 'u', 'm', 'a', 'x', 'p', 9, 0, + /* 4230 */ 'l', 'd', 'x', 'p', 9, 0, + /* 4236 */ 's', 't', 'l', 'x', 'p', 9, 0, + /* 4243 */ 's', 't', 'x', 'p', 9, 0, + /* 4249 */ 'f', 'c', 'm', 'e', 'q', 9, 0, + /* 4256 */ 'c', 't', 'e', 'r', 'm', 'e', 'q', 9, 0, + /* 4265 */ 'c', 'm', 'p', 'e', 'q', 9, 0, + /* 4272 */ 'l', 'd', '1', 'r', 9, 0, + /* 4278 */ 'l', 'd', '2', 'r', 9, 0, + /* 4284 */ 'l', 'd', '3', 'r', 9, 0, + /* 4290 */ 'l', 'd', '4', 'r', 9, 0, + /* 4296 */ 'l', 'd', 'a', 'r', 9, 0, + /* 4302 */ 'l', 'd', 'l', 'a', 'r', 9, 0, + /* 4309 */ 'x', 'a', 'r', 9, 0, + /* 4314 */ 'f', 's', 'u', 'b', 'r', 9, 0, + /* 4321 */ 'a', 'd', 'r', 9, 0, + /* 4326 */ 'l', 'd', 'r', 9, 0, + /* 4331 */ 'r', 'd', 'f', 'f', 'r', 9, 0, + /* 4338 */ 'w', 'r', 'f', 'f', 'r', 9, 0, + /* 4345 */ 's', 'r', 's', 'h', 'r', 9, 0, + /* 4352 */ 'u', 'r', 's', 'h', 'r', 9, 0, + /* 4359 */ 's', 's', 'h', 'r', 9, 0, + /* 4365 */ 'u', 's', 'h', 'r', 9, 0, + /* 4371 */ 'b', 'l', 'r', 9, 0, + /* 4376 */ 'l', 'd', 'c', 'l', 'r', 9, 0, + /* 4383 */ 's', 't', 'l', 'l', 'r', 9, 0, + /* 4390 */ 'l', 's', 'l', 'r', 9, 0, + /* 4396 */ 's', 't', 'l', 'r', 9, 0, + /* 4402 */ 'l', 'd', 'e', 'o', 'r', 9, 0, + /* 4409 */ 'n', 'o', 'r', 9, 0, + /* 4414 */ 'r', 'o', 'r', 9, 0, + /* 4419 */ 'l', 'd', 'a', 'p', 'r', 9, 0, + /* 4426 */ 'o', 'r', 'r', 9, 0, + /* 4431 */ 'a', 's', 'r', 'r', 9, 0, + /* 4437 */ 'l', 's', 'r', 'r', 9, 0, + /* 4443 */ 'a', 's', 'r', 9, 0, + /* 4448 */ 'l', 's', 'r', 9, 0, + /* 4453 */ 'm', 's', 'r', 9, 0, + /* 4458 */ 'i', 'n', 's', 'r', 9, 0, + /* 4464 */ 'l', 'd', 't', 'r', 9, 0, + /* 4470 */ 's', 't', 'r', 9, 0, + /* 4475 */ 's', 't', 't', 'r', 9, 0, + /* 4481 */ 'e', 'x', 't', 'r', 9, 0, + /* 4487 */ 'l', 'd', 'u', 'r', 9, 0, + /* 4493 */ 's', 't', 'l', 'u', 'r', 9, 0, + /* 4500 */ 'l', 'd', 'a', 'p', 'u', 'r', 9, 0, + /* 4508 */ 's', 't', 'u', 'r', 9, 0, + /* 4514 */ 'f', 'd', 'i', 'v', 'r', 9, 0, + /* 4521 */ 's', 'd', 'i', 'v', 'r', 9, 0, + /* 4528 */ 'u', 'd', 'i', 'v', 'r', 9, 0, + /* 4535 */ 'l', 'd', 'a', 'x', 'r', 9, 0, + /* 4542 */ 'l', 'd', 'x', 'r', 9, 0, + /* 4548 */ 's', 't', 'l', 'x', 'r', 9, 0, + /* 4555 */ 's', 't', 'x', 'r', 9, 0, + /* 4561 */ 'c', 'a', 's', 9, 0, + /* 4566 */ 'b', 'r', 'k', 'a', 's', 9, 0, + /* 4573 */ 'b', 'r', 'k', 'p', 'a', 's', 9, 0, + /* 4581 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, + /* 4589 */ 'f', 'a', 'b', 's', 9, 0, + /* 4595 */ 's', 'q', 'a', 'b', 's', 9, 0, + /* 4602 */ 'b', 'r', 'k', 'b', 's', 9, 0, + /* 4609 */ 'b', 'r', 'k', 'p', 'b', 's', 9, 0, + /* 4617 */ 's', 'u', 'b', 's', 9, 0, + /* 4623 */ 's', 'b', 'c', 's', 9, 0, + /* 4629 */ 'a', 'd', 'c', 's', 9, 0, + /* 4635 */ 'b', 'i', 'c', 's', 9, 0, + /* 4641 */ 'a', 'd', 'd', 's', 9, 0, + /* 4647 */ 'n', 'a', 'n', 'd', 's', 9, 0, + /* 4654 */ 'p', 't', 'r', 'u', 'e', 's', 9, 0, + /* 4662 */ 'c', 'm', 'h', 's', 9, 0, + /* 4668 */ 'c', 'm', 'p', 'h', 's', 9, 0, + /* 4675 */ 'c', 'l', 's', 9, 0, + /* 4680 */ 'w', 'h', 'i', 'l', 'e', 'l', 's', 9, 0, + /* 4689 */ 'f', 'm', 'l', 's', 9, 0, + /* 4695 */ 'f', 'n', 'm', 'l', 's', 9, 0, + /* 4702 */ 'c', 'm', 'p', 'l', 's', 9, 0, + /* 4709 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, + /* 4717 */ 'i', 'n', 's', 9, 0, + /* 4722 */ 'b', 'r', 'k', 'n', 's', 9, 0, + /* 4729 */ 'o', 'r', 'n', 's', 9, 0, + /* 4735 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, + /* 4743 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, + /* 4751 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, + /* 4759 */ 'r', 'd', 'f', 'f', 'r', 's', 9, 0, + /* 4767 */ 'm', 'r', 's', 9, 0, + /* 4772 */ 'e', 'o', 'r', 's', 9, 0, + /* 4778 */ 'n', 'o', 'r', 's', 9, 0, + /* 4784 */ 'o', 'r', 'r', 's', 9, 0, + /* 4790 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, + /* 4799 */ 's', 'y', 's', 9, 0, + /* 4804 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, + /* 4812 */ 'f', 'j', 'c', 'v', 't', 'z', 's', 9, 0, + /* 4821 */ 'c', 'o', 'm', 'p', 'a', 'c', 't', 9, 0, + /* 4830 */ 'r', 'e', 't', 9, 0, + /* 4835 */ 'l', 'd', 's', 'e', 't', 9, 0, + /* 4842 */ 'f', 'a', 'c', 'g', 't', 9, 0, + /* 4849 */ 'f', 'c', 'm', 'g', 't', 9, 0, + /* 4856 */ 'c', 'm', 'p', 'g', 't', 9, 0, + /* 4863 */ 'r', 'b', 'i', 't', 9, 0, + /* 4869 */ 'w', 'h', 'i', 'l', 'e', 'l', 't', 9, 0, + /* 4878 */ 'h', 'l', 't', 9, 0, + /* 4883 */ 'f', 'c', 'm', 'l', 't', 9, 0, + /* 4890 */ 'c', 'm', 'p', 'l', 't', 9, 0, + /* 4897 */ 'c', 'n', 't', 9, 0, + /* 4902 */ 'h', 'i', 'n', 't', 9, 0, + /* 4908 */ 's', 'd', 'o', 't', 9, 0, + /* 4914 */ 'u', 'd', 'o', 't', 9, 0, + /* 4920 */ 'c', 'n', 'o', 't', 9, 0, + /* 4926 */ 'f', 's', 'q', 'r', 't', 9, 0, + /* 4933 */ 'p', 't', 'e', 's', 't', 9, 0, + /* 4940 */ 'p', 'f', 'i', 'r', 's', 't', 9, 0, + /* 4948 */ 'c', 'm', 't', 's', 't', 9, 0, + /* 4955 */ 'f', 'c', 'v', 't', 9, 0, + /* 4961 */ 'p', 'n', 'e', 'x', 't', 9, 0, + /* 4968 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, + /* 4976 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, + /* 4984 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, + /* 4992 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, + /* 5000 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, + /* 5008 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, + /* 5016 */ 'f', 'a', 'd', 'd', 'v', 9, 0, + /* 5023 */ 's', 'a', 'd', 'd', 'v', 9, 0, + /* 5030 */ 'u', 'a', 'd', 'd', 'v', 9, 0, + /* 5037 */ 'a', 'n', 'd', 'v', 9, 0, + /* 5043 */ 'r', 'e', 'v', 9, 0, + /* 5048 */ 'f', 'd', 'i', 'v', 9, 0, + /* 5054 */ 's', 'd', 'i', 'v', 9, 0, + /* 5060 */ 'u', 'd', 'i', 'v', 9, 0, + /* 5066 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, + /* 5074 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, + /* 5082 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, + /* 5091 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, + /* 5100 */ 'f', 'm', 'i', 'n', 'v', 9, 0, + /* 5107 */ 's', 'm', 'i', 'n', 'v', 9, 0, + /* 5114 */ 'u', 'm', 'i', 'n', 'v', 9, 0, + /* 5121 */ 'c', 's', 'i', 'n', 'v', 9, 0, + /* 5128 */ 'f', 'm', 'o', 'v', 9, 0, + /* 5134 */ 's', 'm', 'o', 'v', 9, 0, + /* 5140 */ 'u', 'm', 'o', 'v', 9, 0, + /* 5146 */ 'e', 'o', 'r', 'v', 9, 0, + /* 5152 */ 'f', 'm', 'a', 'x', 'v', 9, 0, + /* 5159 */ 's', 'm', 'a', 'x', 'v', 9, 0, + /* 5166 */ 'u', 'm', 'a', 'x', 'v', 9, 0, + /* 5173 */ 'l', 'd', '1', 'w', 9, 0, + /* 5179 */ 'l', 'd', 'f', 'f', '1', 'w', 9, 0, + /* 5187 */ 'l', 'd', 'n', 'f', '1', 'w', 9, 0, + /* 5195 */ 'l', 'd', 'n', 't', '1', 'w', 9, 0, + /* 5203 */ 's', 't', 'n', 't', '1', 'w', 9, 0, + /* 5211 */ 's', 't', '1', 'w', 9, 0, + /* 5217 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, + /* 5225 */ 'l', 'd', '2', 'w', 9, 0, + /* 5231 */ 's', 't', '2', 'w', 9, 0, + /* 5237 */ 'l', 'd', '3', 'w', 9, 0, + /* 5243 */ 's', 't', '3', 'w', 9, 0, + /* 5249 */ 'l', 'd', '4', 'w', 9, 0, + /* 5255 */ 's', 't', '4', 'w', 9, 0, + /* 5261 */ 's', 's', 'u', 'b', 'w', 9, 0, + /* 5268 */ 'u', 's', 'u', 'b', 'w', 9, 0, + /* 5275 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, + /* 5284 */ 's', 'q', 'd', 'e', 'c', 'w', 9, 0, + /* 5292 */ 'u', 'q', 'd', 'e', 'c', 'w', 9, 0, + /* 5300 */ 's', 'q', 'i', 'n', 'c', 'w', 9, 0, + /* 5308 */ 'u', 'q', 'i', 'n', 'c', 'w', 9, 0, + /* 5316 */ 's', 'a', 'd', 'd', 'w', 9, 0, + /* 5323 */ 'u', 'a', 'd', 'd', 'w', 9, 0, + /* 5330 */ 'p', 'r', 'f', 'w', 9, 0, + /* 5336 */ 'l', 'd', '1', 'r', 'q', 'w', 9, 0, + /* 5344 */ 'l', 'd', '1', 'r', 'w', 9, 0, + /* 5351 */ 'l', 'd', '1', 's', 'w', 9, 0, + /* 5358 */ 'l', 'd', 'f', 'f', '1', 's', 'w', 9, 0, + /* 5367 */ 'l', 'd', 'n', 'f', '1', 's', 'w', 9, 0, + /* 5376 */ 'l', 'd', 'p', 's', 'w', 9, 0, + /* 5383 */ 'l', 'd', '1', 'r', 's', 'w', 9, 0, + /* 5391 */ 'l', 'd', 'r', 's', 'w', 9, 0, + /* 5398 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, + /* 5406 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, + /* 5414 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'w', 9, 0, + /* 5424 */ 'c', 'n', 't', 'w', 9, 0, + /* 5430 */ 's', 'x', 't', 'w', 9, 0, + /* 5436 */ 'u', 'x', 't', 'w', 9, 0, + /* 5442 */ 'r', 'e', 'v', 'w', 9, 0, + /* 5448 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, + /* 5456 */ 'b', 'c', 'a', 'x', 9, 0, + /* 5462 */ 'f', 'm', 'a', 'x', 9, 0, + /* 5468 */ 'l', 'd', 's', 'm', 'a', 'x', 9, 0, + /* 5476 */ 'l', 'd', 'u', 'm', 'a', 'x', 9, 0, + /* 5484 */ 't', 'b', 'x', 9, 0, + /* 5489 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, + /* 5498 */ 'i', 'n', 'd', 'e', 'x', 9, 0, + /* 5505 */ 'c', 'l', 'r', 'e', 'x', 9, 0, + /* 5512 */ 'm', 'o', 'v', 'p', 'r', 'f', 'x', 9, 0, + /* 5521 */ 'f', 'm', 'u', 'l', 'x', 9, 0, + /* 5528 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, + /* 5536 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, + /* 5544 */ 's', 'm', '4', 'e', 'k', 'e', 'y', 9, 0, + /* 5553 */ 'f', 'c', 'p', 'y', 9, 0, + /* 5559 */ 'b', 'r', 'a', 'a', 'z', 9, 0, + /* 5566 */ 'b', 'l', 'r', 'a', 'a', 'z', 9, 0, + /* 5574 */ 'b', 'r', 'a', 'b', 'z', 9, 0, + /* 5581 */ 'b', 'l', 'r', 'a', 'b', 'z', 9, 0, + /* 5589 */ 'c', 'b', 'z', 9, 0, + /* 5594 */ 't', 'b', 'z', 9, 0, + /* 5599 */ 'c', 'l', 'z', 9, 0, + /* 5604 */ 'c', 'b', 'n', 'z', 9, 0, + /* 5610 */ 't', 'b', 'n', 'z', 9, 0, + /* 5616 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, + /* 5624 */ 'm', 'o', 'v', 'z', 9, 0, + /* 5630 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, + /* 5644 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, + /* 5675 */ 'b', '.', 0, + /* 5678 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 5702 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, + /* 5727 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, + /* 5750 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, + /* 5773 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, + /* 5795 */ 'p', 'a', 'c', 'i', 'a', '1', '7', '1', '6', 0, + /* 5805 */ 'a', 'u', 't', 'i', 'a', '1', '7', '1', '6', 0, + /* 5815 */ 'p', 'a', 'c', 'i', 'b', '1', '7', '1', '6', 0, + /* 5825 */ 'a', 'u', 't', 'i', 'b', '1', '7', '1', '6', 0, + /* 5835 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, + /* 5848 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, + /* 5855 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, + /* 5865 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, + /* 5875 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 5890 */ 'e', 'r', 'e', 't', 'a', 'a', 0, + /* 5897 */ 'e', 'r', 'e', 't', 'a', 'b', 0, + /* 5904 */ 'x', 'p', 'a', 'c', 'l', 'r', 'i', 0, + /* 5912 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, + /* 5926 */ 'p', 'a', 'c', 'i', 'a', 's', 'p', 0, + /* 5934 */ 'a', 'u', 't', 'i', 'a', 's', 'p', 0, + /* 5942 */ 'p', 'a', 'c', 'i', 'b', 's', 'p', 0, + /* 5950 */ 'a', 'u', 't', 'i', 'b', 's', 'p', 0, + /* 5958 */ 's', 'e', 't', 'f', 'f', 'r', 0, + /* 5965 */ 'd', 'r', 'p', 's', 0, + /* 5970 */ 'e', 'r', 'e', 't', 0, + /* 5975 */ 'c', 'f', 'i', 'n', 'v', 0, + /* 5981 */ 'p', 'a', 'c', 'i', 'a', 'z', 0, + /* 5988 */ 'a', 'u', 't', 'i', 'a', 'z', 0, + /* 5995 */ 'p', 'a', 'c', 'i', 'b', 'z', 0, + /* 6002 */ 'a', 'u', 't', 'i', 'b', 'z', 0, + }; +#endif + + static const uint32_t OpInfo0[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG 0U, // IMPLICIT_DEF 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS - 2694U, // DBG_VALUE + 5856U, // DBG_VALUE + 5866U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY - 2687U, // BUNDLE - 2704U, // LIFETIME_START - 2674U, // LIFETIME_END + 5849U, // BUNDLE + 5876U, // LIFETIME_START + 5836U, // LIFETIME_END 0U, // STACKMAP + 5913U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 6182U, // ABSv16i8 - 553920550U, // ABSv1i64 - 1074272294U, // ABSv2i32 - 1611405350U, // ABSv2i64 - 2148538406U, // ABSv4i16 - 2685671462U, // ABSv4i32 - 3222804518U, // ABSv8i16 - 3759937574U, // ABSv8i8 - 17049662U, // ADCSWr - 17049662U, // ADCSXr - 17048298U, // ADCWr - 17048298U, // ADCXr - 537400863U, // ADDHNv2i64_v2i32 - 571748634U, // ADDHNv2i64_v4i32 - 1074796063U, // ADDHNv4i32_v4i16 - 1108881690U, // ADDHNv4i32_v8i16 - 1644179738U, // ADDHNv8i16_v16i8 - 1612453407U, // ADDHNv8i16_v8i8 - 2147489464U, // ADDPv16i8 - 2684884664U, // ADDPv2i32 - 537663160U, // ADDPv2i64 - 1610884792U, // ADDPv2i64p - 3222279864U, // ADDPv4i16 - 1075058360U, // ADDPv4i32 - 1612191416U, // ADDPv8i16 - 3759937208U, // ADDPv8i8 - 17049674U, // ADDSWri + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 5728U, // PATCHABLE_FUNCTION_ENTER + 5645U, // PATCHABLE_RET + 5774U, // PATCHABLE_FUNCTION_EXIT + 5751U, // PATCHABLE_TAIL_CALL + 5703U, // PATCHABLE_EVENT_CALL + 5679U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 12783U, // ABS_ZPmZ_B + 20975U, // ABS_ZPmZ_D + 2181591535U, // ABS_ZPmZ_H + 37359U, // ABS_ZPmZ_S + 68202991U, // ABSv16i8 + 2248200687U, // ABSv1i64 + 68727279U, // ABSv2i32 + 2216735215U, // ABSv2i64 + 69775855U, // ABSv4i16 + 2217783791U, // ABSv4i32 + 70824431U, // ABSv8i16 + 2218832367U, // ABSv8i8 + 100717078U, // ADCSWr + 100717078U, // ADCSXr + 100714262U, // ADCWr + 100714262U, // ADCXr + 2216210145U, // ADDHNv2i64_v2i32 + 2284904787U, // ADDHNv2i64_v4i32 + 69775073U, // ADDHNv4i32_v4i16 + 137945427U, // ADDHNv4i32_v8i16 + 2282807635U, // ADDHNv8i16_v16i8 + 2218831585U, // ADDHNv8i16_v8i8 + 100716037U, // ADDPL_XXI + 68202454U, // ADDPv16i8 + 2216210390U, // ADDPv2i32 + 2216734678U, // ADDPv2i64 + 2214645718U, // ADDPv2i64p + 69775318U, // ADDPv4i16 + 70299606U, // ADDPv4i32 + 2218307542U, // ADDPv8i16 + 2218831830U, // ADDPv8i8 + 100717090U, // ADDSWri 0U, // ADDSWrr - 17049674U, // ADDSWrs - 17049674U, // ADDSWrx - 17049674U, // ADDSXri + 100717090U, // ADDSWrs + 100717090U, // ADDSWrx + 100717090U, // ADDSXri 0U, // ADDSXrr - 17049674U, // ADDSXrs - 17049674U, // ADDSXrx - 17049674U, // ADDSXrx64 - 272671U, // ADDVv16i8v - 2147756319U, // ADDVv4i16v - 2684627231U, // ADDVv4i32v - 3221498143U, // ADDVv8i16v - 3758369055U, // ADDVv8i8v - 17048359U, // ADDWri + 100717090U, // ADDSXrs + 100717090U, // ADDSXrx + 100717090U, // ADDSXrx64 + 100716155U, // ADDVL_XXI + 67163034U, // ADDVv16i8v + 67163034U, // ADDVv4i16v + 2214646682U, // ADDVv4i32v + 67163034U, // ADDVv8i16v + 2214646682U, // ADDVv8i8v + 100714463U, // ADDWri 0U, // ADDWrr - 17048359U, // ADDWrs - 17048359U, // ADDWrx - 17048359U, // ADDXri + 100714463U, // ADDWrs + 100714463U, // ADDWrx + 100714463U, // ADDXri 0U, // ADDXrr - 17048359U, // ADDXrs - 17048359U, // ADDXrx - 17048359U, // ADDXrx64 - 2147488551U, // ADDv16i8 - 17048359U, // ADDv1i64 - 2684883751U, // ADDv2i32 - 537662247U, // ADDv2i64 - 3222278951U, // ADDv4i16 - 1075057447U, // ADDv4i32 - 1612190503U, // ADDv8i16 - 3759936295U, // ADDv8i8 + 100714463U, // ADDXrs + 100714463U, // ADDXrx + 100714463U, // ADDXrx64 + 167782367U, // ADD_ZI_B + 201344991U, // ADD_ZI_D + 239626207U, // ADD_ZI_H + 268470239U, // ADD_ZI_S + 302000095U, // ADD_ZPmZ_B + 302008287U, // ADD_ZPmZ_D + 2186307551U, // ADD_ZPmZ_H + 302024671U, // ADD_ZPmZ_S + 167782367U, // ADD_ZZZ_B + 201344991U, // ADD_ZZZ_D + 2387109855U, // ADD_ZZZ_H + 268470239U, // ADD_ZZZ_S + 0U, // ADDlowTLS + 68200415U, // ADDv16i8 + 100714463U, // ADDv1i64 + 2216208351U, // ADDv2i32 + 2216732639U, // ADDv2i64 + 69773279U, // ADDv4i16 + 70297567U, // ADDv4i32 + 2218305503U, // ADDv8i16 + 2218829791U, // ADDv8i8 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP - 553920403U, // ADR - 50603811U, // ADRP - 33567598U, // AESDrr - 33567656U, // AESErr - 4852U, // AESIMCrr - 4860U, // AESMCrr - 17049680U, // ANDSWri + 2248200418U, // ADR + 335597633U, // ADRP + 207114466U, // ADR_LSL_ZZZ_D_0 + 207114466U, // ADR_LSL_ZZZ_D_1 + 207114466U, // ADR_LSL_ZZZ_D_2 + 207114466U, // ADR_LSL_ZZZ_D_3 + 274239714U, // ADR_LSL_ZZZ_S_0 + 274239714U, // ADR_LSL_ZZZ_S_1 + 274239714U, // ADR_LSL_ZZZ_S_2 + 274239714U, // ADR_LSL_ZZZ_S_3 + 207114466U, // ADR_SXTW_ZZZ_D_0 + 207114466U, // ADR_SXTW_ZZZ_D_1 + 207114466U, // ADR_SXTW_ZZZ_D_2 + 207114466U, // ADR_SXTW_ZZZ_D_3 + 207114466U, // ADR_UXTW_ZZZ_D_0 + 207114466U, // ADR_UXTW_ZZZ_D_1 + 207114466U, // ADR_UXTW_ZZZ_D_2 + 207114466U, // ADR_UXTW_ZZZ_D_3 + 135325775U, // AESDrr + 135325907U, // AESErr + 68200224U, // AESIMCrr + 0U, // AESIMCrrTied + 68200232U, // AESMCrr + 0U, // AESMCrrTied + 100717097U, // ANDSWri 0U, // ANDSWrr - 17049680U, // ANDSWrs - 17049680U, // ANDSXri + 100717097U, // ANDSWrs + 100717097U, // ANDSXri 0U, // ANDSXrr - 17049680U, // ANDSXrs - 17048425U, // ANDWri + 100717097U, // ANDSXrs + 302002729U, // ANDS_PPzPP + 302044078U, // ANDV_VPZ_B + 302044078U, // ANDV_VPZ_D + 302044078U, // ANDV_VPZ_H + 302044078U, // ANDV_VPZ_S + 100714549U, // ANDWri 0U, // ANDWrr - 17048425U, // ANDWrs - 17048425U, // ANDXri + 100714549U, // ANDWrs + 100714549U, // ANDXri 0U, // ANDXrr - 17048425U, // ANDXrs - 2147488617U, // ANDv16i8 - 3759936361U, // ANDv8i8 - 17049553U, // ASRVWr - 17049553U, // ASRVXr - 16935U, // B - 67380710U, // BFMWri - 67380710U, // BFMXri + 100714549U, // ANDXrs + 302000181U, // AND_PPzPP + 201345077U, // AND_ZI + 302000181U, // AND_ZPmZ_B + 302008373U, // AND_ZPmZ_D + 2186307637U, // AND_ZPmZ_H + 302024757U, // AND_ZPmZ_S + 201345077U, // AND_ZZZ + 68200501U, // ANDv16i8 + 2218829877U, // ANDv8i8 + 302000201U, // ASRD_ZPmI_B + 302008393U, // ASRD_ZPmI_D + 2186307657U, // ASRD_ZPmI_H + 302024777U, // ASRD_ZPmI_S + 302002512U, // ASRR_ZPmZ_B + 302010704U, // ASRR_ZPmZ_D + 2186309968U, // ASRR_ZPmZ_H + 302027088U, // ASRR_ZPmZ_S + 100716892U, // ASRVWr + 100716892U, // ASRVXr + 302002524U, // ASR_WIDE_ZPmZ_B + 2186309980U, // ASR_WIDE_ZPmZ_H + 302027100U, // ASR_WIDE_ZPmZ_S + 167784796U, // ASR_WIDE_ZZZ_B + 2387112284U, // ASR_WIDE_ZZZ_H + 268472668U, // ASR_WIDE_ZZZ_S + 302002524U, // ASR_ZPmI_B + 302010716U, // ASR_ZPmI_D + 2186309980U, // ASR_ZPmI_H + 302027100U, // ASR_ZPmI_S + 302002524U, // ASR_ZPmZ_B + 302010716U, // ASR_ZPmZ_D + 2186309980U, // ASR_ZPmZ_H + 302027100U, // ASR_ZPmZ_S + 167784796U, // ASR_ZZI_B + 201347420U, // ASR_ZZI_D + 239628636U, // ASR_ZZI_H + 268472668U, // ASR_ZZI_S + 2248196751U, // AUTDA + 2248197244U, // AUTDB + 6341460U, // AUTDZA + 6342386U, // AUTDZB + 2248196772U, // AUTIA + 5806U, // AUTIA1716 + 5935U, // AUTIASP + 5989U, // AUTIAZ + 2248197264U, // AUTIB + 5826U, // AUTIB1716 + 5951U, // AUTIBSP + 6003U, // AUTIBZ + 6341476U, // AUTIZA + 6342402U, // AUTIZB + 66415U, // B + 68203857U, // BCAX + 369151650U, // BFMWri + 369151650U, // BFMXri 0U, // BICSWrr - 17049668U, // BICSWrs + 100717084U, // BICSWrs 0U, // BICSXrr - 17049668U, // BICSXrs + 100717084U, // BICSXrs + 302002716U, // BICS_PPzPP 0U, // BICWrr - 17048303U, // BICWrs + 100714267U, // BICWrs 0U, // BICXrr - 17048303U, // BICXrs - 2147488495U, // BICv16i8 - 84423407U, // BICv2i32 - 84947695U, // BICv4i16 - 85209839U, // BICv4i32 - 85471983U, // BICv8i16 - 3759936239U, // BICv8i8 - 2147488704U, // BIFv16i8 - 3759936448U, // BIFv8i8 - 2181052603U, // BITv16i8 - 3793500347U, // BITv8i8 - 17641U, // BL - 2107319U, // BLR - 2107279U, // BR - 21688U, // BRK - 2181051810U, // BSLv16i8 - 3793499554U, // BSLv8i8 - 27247U, // Bcc - 100936257U, // CBNZW - 100936257U, // CBNZX - 100936242U, // CBZW - 100936242U, // CBZX - 17049144U, // CCMNWi - 17049144U, // CCMNWr - 17049144U, // CCMNXi - 17049144U, // CCMNXr - 17049316U, // CCMPWi - 17049316U, // CCMPWr - 17049316U, // CCMPXi - 17049316U, // CCMPXr - 2107924U, // CLREX - 553920604U, // CLSWr - 553920604U, // CLSXr - 6236U, // CLSv16i8 - 1074272348U, // CLSv2i32 - 2148538460U, // CLSv4i16 - 2685671516U, // CLSv4i32 - 3222804572U, // CLSv8i16 - 3759937628U, // CLSv8i8 - 553921084U, // CLZWr - 553921084U, // CLZXr - 6716U, // CLZv16i8 - 1074272828U, // CLZv2i32 - 2148538940U, // CLZv4i16 - 2685671996U, // CLZv4i32 - 3222805052U, // CLZv8i16 - 3759938108U, // CLZv8i8 - 2147489643U, // CMEQv16i8 - 5995U, // CMEQv16i8rz - 17049451U, // CMEQv1i64 - 553920363U, // CMEQv1i64rz - 2684884843U, // CMEQv2i32 - 1074272107U, // CMEQv2i32rz - 537663339U, // CMEQv2i64 - 1611405163U, // CMEQv2i64rz - 3222280043U, // CMEQv4i16 - 2148538219U, // CMEQv4i16rz - 1075058539U, // CMEQv4i32 - 2685671275U, // CMEQv4i32rz - 1612191595U, // CMEQv8i16 - 3222804331U, // CMEQv8i16rz - 3759937387U, // CMEQv8i8 - 3759937387U, // CMEQv8i8rz - 2147488636U, // CMGEv16i8 - 4988U, // CMGEv16i8rz - 17048444U, // CMGEv1i64 - 553919356U, // CMGEv1i64rz - 2684883836U, // CMGEv2i32 - 1074271100U, // CMGEv2i32rz - 537662332U, // CMGEv2i64 - 1611404156U, // CMGEv2i64rz - 3222279036U, // CMGEv4i16 - 2148537212U, // CMGEv4i16rz - 1075057532U, // CMGEv4i32 - 2685670268U, // CMGEv4i32rz - 1612190588U, // CMGEv8i16 - 3222803324U, // CMGEv8i16rz - 3759936380U, // CMGEv8i8 - 3759936380U, // CMGEv8i8rz - 2147489972U, // CMGTv16i8 - 6324U, // CMGTv16i8rz - 17049780U, // CMGTv1i64 - 553920692U, // CMGTv1i64rz - 2684885172U, // CMGTv2i32 - 1074272436U, // CMGTv2i32rz - 537663668U, // CMGTv2i64 - 1611405492U, // CMGTv2i64rz - 3222280372U, // CMGTv4i16 - 2148538548U, // CMGTv4i16rz - 1075058868U, // CMGTv4i32 - 2685671604U, // CMGTv4i32rz - 1612191924U, // CMGTv8i16 - 3222804660U, // CMGTv8i16rz - 3759937716U, // CMGTv8i8 - 3759937716U, // CMGTv8i8rz - 2147488916U, // CMHIv16i8 - 17048724U, // CMHIv1i64 - 2684884116U, // CMHIv2i32 - 537662612U, // CMHIv2i64 - 3222279316U, // CMHIv4i16 - 1075057812U, // CMHIv4i32 - 1612190868U, // CMHIv8i16 - 3759936660U, // CMHIv8i8 - 2147489878U, // CMHSv16i8 - 17049686U, // CMHSv1i64 - 2684885078U, // CMHSv2i32 - 537663574U, // CMHSv2i64 - 3222280278U, // CMHSv4i16 - 1075058774U, // CMHSv4i32 - 1612191830U, // CMHSv8i16 - 3759937622U, // CMHSv8i8 - 4995U, // CMLEv16i8rz - 553919363U, // CMLEv1i64rz - 1074271107U, // CMLEv2i32rz - 1611404163U, // CMLEv2i64rz - 2148537219U, // CMLEv4i16rz - 2685670275U, // CMLEv4i32rz - 3222803331U, // CMLEv8i16rz - 3759936387U, // CMLEv8i8rz - 6342U, // CMLTv16i8rz - 553920710U, // CMLTv1i64rz - 1074272454U, // CMLTv2i32rz - 1611405510U, // CMLTv2i64rz - 2148538566U, // CMLTv4i16rz - 2685671622U, // CMLTv4i32rz - 3222804678U, // CMLTv8i16rz - 3759937734U, // CMLTv8i8rz - 2147490013U, // CMTSTv16i8 - 17049821U, // CMTSTv1i64 - 2684885213U, // CMTSTv2i32 - 537663709U, // CMTSTv2i64 - 3222280413U, // CMTSTv4i16 - 1075058909U, // CMTSTv4i32 - 1612191965U, // CMTSTv8i16 - 3759937757U, // CMTSTv8i8 - 6348U, // CNTv16i8 - 3759937740U, // CNTv8i8 - 272763U, // CPYi16 - 537143675U, // CPYi32 - 1074014587U, // CPYi64 - 1610885499U, // CPYi8 - 17048098U, // CRC32Brr - 17048106U, // CRC32CBrr - 17048575U, // CRC32CHrr - 17050039U, // CRC32CWrr - 17050123U, // CRC32CXrr - 17048558U, // CRC32Hrr - 17050017U, // CRC32Wrr - 17050092U, // CRC32Xrr - 17048888U, // CSELWr - 17048888U, // CSELXr - 17048323U, // CSINCWr - 17048323U, // CSINCXr - 17049971U, // CSINVWr - 17049971U, // CSINVXr - 17048544U, // CSNEGWr - 17048544U, // CSNEGXr - 20524U, // DCPS1 - 20889U, // DCPS2 - 20938U, // DCPS3 - 29235U, // DMB - 2719U, // DRPS - 29324U, // DSB - 553654070U, // DUPv16i8gpr - 1610618678U, // DUPv16i8lane - 554178358U, // DUPv2i32gpr - 537401142U, // DUPv2i32lane - 554440502U, // DUPv2i64gpr - 1074534198U, // DUPv2i64lane - 554702646U, // DUPv4i16gpr - 1054518U, // DUPv4i16lane - 554964790U, // DUPv4i32gpr - 538187574U, // DUPv4i32lane - 555226934U, // DUPv8i16gpr - 1578806U, // DUPv8i16lane - 555489078U, // DUPv8i8gpr - 1612453686U, // DUPv8i8lane + 100714267U, // BICXrs + 301999899U, // BIC_PPzPP + 301999899U, // BIC_ZPmZ_B + 302008091U, // BIC_ZPmZ_D + 2186307355U, // BIC_ZPmZ_H + 302024475U, // BIC_ZPmZ_S + 201344795U, // BIC_ZZZ + 68200219U, // BICv16i8 + 404285211U, // BICv2i32 + 405333787U, // BICv4i16 + 405858075U, // BICv4i32 + 406382363U, // BICv8i16 + 2218829595U, // BICv8i8 + 68200698U, // BIFv16i8 + 2218830074U, // BIFv8i8 + 135328513U, // BITv16i8 + 2285957889U, // BITv8i8 + 68906U, // BL + 6344980U, // BLR + 2248196710U, // BLRAA + 6346175U, // BLRAAZ + 2248197127U, // BLRAB + 6346190U, // BLRABZ + 6344926U, // BR + 2248196697U, // BRAA + 6346168U, // BRAAZ + 2248197114U, // BRAB + 6346183U, // BRABZ + 76951U, // BRK + 302002647U, // BRKAS_PPzP + 8875U, // BRKA_PPmP + 301998763U, // BRKA_PPzP + 302002683U, // BRKBS_PPzP + 9367U, // BRKB_PPmP + 301999255U, // BRKB_PPzP + 302002803U, // BRKNS_PPzP + 302001918U, // BRKN_PPzP + 302002654U, // BRKPAS_PPzPP + 301998807U, // BRKPA_PPzPP + 302002690U, // BRKPBS_PPzPP + 301999474U, // BRKPB_PPzPP + 135327279U, // BSLv16i8 + 2285956655U, // BSLv8i8 + 87596U, // Bcc + 2516673568U, // CASAB + 2516675032U, // CASAH + 2516673753U, // CASALB + 2516675183U, // CASALH + 2516675845U, // CASALW + 2516675845U, // CASALX + 2516673308U, // CASAW + 2516673308U, // CASAX + 2516674100U, // CASB + 2516675551U, // CASH + 2516673847U, // CASLB + 2516675277U, // CASLH + 2516676137U, // CASLW + 2516676137U, // CASLX + 101604U, // CASPALW + 109796U, // CASPALX + 99038U, // CASPAW + 107230U, // CASPAX + 101900U, // CASPLW + 110092U, // CASPLX + 102471U, // CASPW + 110663U, // CASPX + 2516677074U, // CASW + 2516677074U, // CASX + 436262373U, // CBNZW + 436262373U, // CBNZX + 436262358U, // CBZW + 436262358U, // CBZX + 100716292U, // CCMNWi + 100716292U, // CCMNWr + 100716292U, // CCMNXi + 100716292U, // CCMNXr + 100716546U, // CCMPWi + 100716546U, // CCMPWr + 100716546U, // CCMPXi + 100716546U, // CCMPXr + 5976U, // CFINV + 302039858U, // CLASTA_RPZ_B + 302039858U, // CLASTA_RPZ_D + 302039858U, // CLASTA_RPZ_H + 302039858U, // CLASTA_RPZ_S + 302039858U, // CLASTA_VPZ_B + 302039858U, // CLASTA_VPZ_D + 302039858U, // CLASTA_VPZ_H + 302039858U, // CLASTA_VPZ_S + 301998898U, // CLASTA_ZPZ_B + 302007090U, // CLASTA_ZPZ_D + 2387632946U, // CLASTA_ZPZ_H + 302023474U, // CLASTA_ZPZ_S + 302040717U, // CLASTB_RPZ_B + 302040717U, // CLASTB_RPZ_D + 302040717U, // CLASTB_RPZ_H + 302040717U, // CLASTB_RPZ_S + 302040717U, // CLASTB_VPZ_B + 302040717U, // CLASTB_VPZ_D + 302040717U, // CLASTB_VPZ_H + 302040717U, // CLASTB_VPZ_S + 301999757U, // CLASTB_ZPZ_B + 302007949U, // CLASTB_ZPZ_D + 2387633805U, // CLASTB_ZPZ_H + 302024333U, // CLASTB_ZPZ_S + 6346114U, // CLREX + 2248200772U, // CLSWr + 2248200772U, // CLSXr + 12868U, // CLS_ZPmZ_B + 21060U, // CLS_ZPmZ_D + 2181591620U, // CLS_ZPmZ_H + 37444U, // CLS_ZPmZ_S + 68203076U, // CLSv16i8 + 68727364U, // CLSv2i32 + 69775940U, // CLSv4i16 + 2217783876U, // CLSv4i32 + 70824516U, // CLSv8i16 + 2218832452U, // CLSv8i8 + 2248201696U, // CLZWr + 2248201696U, // CLZXr + 13792U, // CLZ_ZPmZ_B + 21984U, // CLZ_ZPmZ_D + 2181592544U, // CLZ_ZPmZ_H + 38368U, // CLZ_ZPmZ_S + 68204000U, // CLZv16i8 + 68728288U, // CLZv2i32 + 69776864U, // CLZv4i16 + 2217784800U, // CLZv4i32 + 70825440U, // CLZv8i16 + 2218833376U, // CLZv8i8 + 68202651U, // CMEQv16i8 + 68202651U, // CMEQv16i8rz + 100716699U, // CMEQv1i64 + 2248200347U, // CMEQv1i64rz + 2216210587U, // CMEQv2i32 + 68726939U, // CMEQv2i32rz + 2216734875U, // CMEQv2i64 + 2216734875U, // CMEQv2i64rz + 69775515U, // CMEQv4i16 + 69775515U, // CMEQv4i16rz + 70299803U, // CMEQv4i32 + 2217783451U, // CMEQv4i32rz + 2218307739U, // CMEQv8i16 + 70824091U, // CMEQv8i16rz + 2218832027U, // CMEQv8i8 + 2218832027U, // CMEQv8i8rz + 68200561U, // CMGEv16i8 + 68200561U, // CMGEv16i8rz + 100714609U, // CMGEv1i64 + 2248198257U, // CMGEv1i64rz + 2216208497U, // CMGEv2i32 + 68724849U, // CMGEv2i32rz + 2216732785U, // CMGEv2i64 + 2216732785U, // CMGEv2i64rz + 69773425U, // CMGEv4i16 + 69773425U, // CMGEv4i16rz + 70297713U, // CMGEv4i32 + 2217781361U, // CMGEv4i32rz + 2218305649U, // CMGEv8i16 + 70822001U, // CMGEv8i16rz + 2218829937U, // CMGEv8i8 + 2218829937U, // CMGEv8i8rz + 68203251U, // CMGTv16i8 + 68203251U, // CMGTv16i8rz + 100717299U, // CMGTv1i64 + 2248200947U, // CMGTv1i64rz + 2216211187U, // CMGTv2i32 + 68727539U, // CMGTv2i32rz + 2216735475U, // CMGTv2i64 + 2216735475U, // CMGTv2i64rz + 69776115U, // CMGTv4i16 + 69776115U, // CMGTv4i16rz + 70300403U, // CMGTv4i32 + 2217784051U, // CMGTv4i32rz + 2218308339U, // CMGTv8i16 + 70824691U, // CMGTv8i16rz + 2218832627U, // CMGTv8i8 + 2218832627U, // CMGTv8i8rz + 68201580U, // CMHIv16i8 + 100715628U, // CMHIv1i64 + 2216209516U, // CMHIv2i32 + 2216733804U, // CMHIv2i64 + 69774444U, // CMHIv4i16 + 70298732U, // CMHIv4i32 + 2218306668U, // CMHIv8i16 + 2218830956U, // CMHIv8i8 + 68203063U, // CMHSv16i8 + 100717111U, // CMHSv1i64 + 2216210999U, // CMHSv2i32 + 2216735287U, // CMHSv2i64 + 69775927U, // CMHSv4i16 + 70300215U, // CMHSv4i32 + 2218308151U, // CMHSv8i16 + 2218832439U, // CMHSv8i8 + 68200592U, // CMLEv16i8rz + 2248198288U, // CMLEv1i64rz + 68724880U, // CMLEv2i32rz + 2216732816U, // CMLEv2i64rz + 69773456U, // CMLEv4i16rz + 2217781392U, // CMLEv4i32rz + 70822032U, // CMLEv8i16rz + 2218829968U, // CMLEv8i8rz + 68203285U, // CMLTv16i8rz + 2248200981U, // CMLTv1i64rz + 68727573U, // CMLTv2i32rz + 2216735509U, // CMLTv2i64rz + 69776149U, // CMLTv4i16rz + 2217784085U, // CMLTv4i32rz + 70824725U, // CMLTv8i16rz + 2218832661U, // CMLTv8i8rz + 302002346U, // CMPEQ_PPzZI_B + 302010538U, // CMPEQ_PPzZI_D + 2622517418U, // CMPEQ_PPzZI_H + 302026922U, // CMPEQ_PPzZI_S + 302002346U, // CMPEQ_PPzZZ_B + 302010538U, // CMPEQ_PPzZZ_D + 2622517418U, // CMPEQ_PPzZZ_H + 302026922U, // CMPEQ_PPzZZ_S + 302002346U, // CMPEQ_WIDE_PPzZZ_B + 2622517418U, // CMPEQ_WIDE_PPzZZ_H + 302026922U, // CMPEQ_WIDE_PPzZZ_S + 302000247U, // CMPGE_PPzZI_B + 302008439U, // CMPGE_PPzZI_D + 2622515319U, // CMPGE_PPzZI_H + 302024823U, // CMPGE_PPzZI_S + 302000247U, // CMPGE_PPzZZ_B + 302008439U, // CMPGE_PPzZZ_D + 2622515319U, // CMPGE_PPzZZ_H + 302024823U, // CMPGE_PPzZZ_S + 302000247U, // CMPGE_WIDE_PPzZZ_B + 2622515319U, // CMPGE_WIDE_PPzZZ_H + 302024823U, // CMPGE_WIDE_PPzZZ_S + 302002937U, // CMPGT_PPzZI_B + 302011129U, // CMPGT_PPzZI_D + 2622518009U, // CMPGT_PPzZI_H + 302027513U, // CMPGT_PPzZI_S + 302002937U, // CMPGT_PPzZZ_B + 302011129U, // CMPGT_PPzZZ_D + 2622518009U, // CMPGT_PPzZZ_H + 302027513U, // CMPGT_PPzZZ_S + 302002937U, // CMPGT_WIDE_PPzZZ_B + 2622518009U, // CMPGT_WIDE_PPzZZ_H + 302027513U, // CMPGT_WIDE_PPzZZ_S + 302001266U, // CMPHI_PPzZI_B + 302009458U, // CMPHI_PPzZI_D + 2622516338U, // CMPHI_PPzZI_H + 302025842U, // CMPHI_PPzZI_S + 302001266U, // CMPHI_PPzZZ_B + 302009458U, // CMPHI_PPzZZ_D + 2622516338U, // CMPHI_PPzZZ_H + 302025842U, // CMPHI_PPzZZ_S + 302001266U, // CMPHI_WIDE_PPzZZ_B + 2622516338U, // CMPHI_WIDE_PPzZZ_H + 302025842U, // CMPHI_WIDE_PPzZZ_S + 302002749U, // CMPHS_PPzZI_B + 302010941U, // CMPHS_PPzZI_D + 2622517821U, // CMPHS_PPzZI_H + 302027325U, // CMPHS_PPzZI_S + 302002749U, // CMPHS_PPzZZ_B + 302010941U, // CMPHS_PPzZZ_D + 2622517821U, // CMPHS_PPzZZ_H + 302027325U, // CMPHS_PPzZZ_S + 302002749U, // CMPHS_WIDE_PPzZZ_B + 2622517821U, // CMPHS_WIDE_PPzZZ_H + 302027325U, // CMPHS_WIDE_PPzZZ_S + 302000278U, // CMPLE_PPzZI_B + 302008470U, // CMPLE_PPzZI_D + 2622515350U, // CMPLE_PPzZI_H + 302024854U, // CMPLE_PPzZI_S + 302000278U, // CMPLE_WIDE_PPzZZ_B + 2622515350U, // CMPLE_WIDE_PPzZZ_H + 302024854U, // CMPLE_WIDE_PPzZZ_S + 302002080U, // CMPLO_PPzZI_B + 302010272U, // CMPLO_PPzZI_D + 2622517152U, // CMPLO_PPzZI_H + 302026656U, // CMPLO_PPzZI_S + 302002080U, // CMPLO_WIDE_PPzZZ_B + 2622517152U, // CMPLO_WIDE_PPzZZ_H + 302026656U, // CMPLO_WIDE_PPzZZ_S + 302002783U, // CMPLS_PPzZI_B + 302010975U, // CMPLS_PPzZI_D + 2622517855U, // CMPLS_PPzZI_H + 302027359U, // CMPLS_PPzZI_S + 302002783U, // CMPLS_WIDE_PPzZZ_B + 2622517855U, // CMPLS_WIDE_PPzZZ_H + 302027359U, // CMPLS_WIDE_PPzZZ_S + 302002971U, // CMPLT_PPzZI_B + 302011163U, // CMPLT_PPzZI_D + 2622518043U, // CMPLT_PPzZI_H + 302027547U, // CMPLT_PPzZI_S + 302002971U, // CMPLT_WIDE_PPzZZ_B + 2622518043U, // CMPLT_WIDE_PPzZZ_H + 302027547U, // CMPLT_WIDE_PPzZZ_S + 302000301U, // CMPNE_PPzZI_B + 302008493U, // CMPNE_PPzZI_D + 2622515373U, // CMPNE_PPzZI_H + 302024877U, // CMPNE_PPzZI_S + 302000301U, // CMPNE_PPzZZ_B + 302008493U, // CMPNE_PPzZZ_D + 2622515373U, // CMPNE_PPzZZ_H + 302024877U, // CMPNE_PPzZZ_S + 302000301U, // CMPNE_WIDE_PPzZZ_B + 2622515373U, // CMPNE_WIDE_PPzZZ_H + 302024877U, // CMPNE_WIDE_PPzZZ_S + 0U, // CMP_SWAP_128 + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 68203349U, // CMTSTv16i8 + 100717397U, // CMTSTv1i64 + 2216211285U, // CMTSTv2i32 + 2216735573U, // CMTSTv2i64 + 69776213U, // CMTSTv4i16 + 70300501U, // CMTSTv4i32 + 2218308437U, // CMTSTv8i16 + 2218832725U, // CMTSTv8i8 + 13113U, // CNOT_ZPmZ_B + 21305U, // CNOT_ZPmZ_D + 2181591865U, // CNOT_ZPmZ_H + 37689U, // CNOT_ZPmZ_S + 503367303U, // CNTB_XPiI + 503367765U, // CNTD_XPiI + 503368736U, // CNTH_XPiI + 302043213U, // CNTP_XPP_B + 302043213U, // CNTP_XPP_D + 302043213U, // CNTP_XPP_H + 302043213U, // CNTP_XPP_S + 503371057U, // CNTW_XPiI + 13090U, // CNT_ZPmZ_B + 21282U, // CNT_ZPmZ_D + 2181591842U, // CNT_ZPmZ_H + 37666U, // CNT_ZPmZ_S + 68203298U, // CNTv16i8 + 2218832674U, // CNTv8i8 + 302011094U, // COMPACT_ZPZ_D + 302027478U, // COMPACT_ZPZ_S + 13747U, // CPY_ZPmI_B + 21939U, // CPY_ZPmI_D + 2181592499U, // CPY_ZPmI_H + 38323U, // CPY_ZPmI_S + 13747U, // CPY_ZPmR_B + 21939U, // CPY_ZPmR_D + 34108851U, // CPY_ZPmR_H + 38323U, // CPY_ZPmR_S + 13747U, // CPY_ZPmV_B + 21939U, // CPY_ZPmV_D + 34108851U, // CPY_ZPmV_H + 38323U, // CPY_ZPmV_S + 302003635U, // CPY_ZPzI_B + 302011827U, // CPY_ZPzI_D + 2622518707U, // CPY_ZPzI_H + 302028211U, // CPY_ZPzI_S + 67163146U, // CPYi16 + 2214646794U, // CPYi32 + 67163146U, // CPYi64 + 2214646794U, // CPYi8 + 100713377U, // CRC32Brr + 100713540U, // CRC32CBrr + 100715004U, // CRC32CHrr + 100717724U, // CRC32CWrr + 100717938U, // CRC32CXrr + 100714851U, // CRC32Hrr + 100717666U, // CRC32Wrr + 100717897U, // CRC32Xrr + 100715905U, // CSELWr + 100715905U, // CSELXr + 100714287U, // CSINCWr + 100714287U, // CSINCXr + 100717570U, // CSINVWr + 100717570U, // CSINVXr + 100714784U, // CSNEGWr + 100714784U, // CSNEGXr + 2248200353U, // CTERMEQ_WW + 2248200353U, // CTERMEQ_XX + 2248198308U, // CTERMNE_WW + 2248198308U, // CTERMNE_XX + 0U, // CompilerBarrier + 73783U, // DCPS1 + 74194U, // DCPS2 + 74260U, // DCPS3 + 536921167U, // DECB_XPiI + 536922047U, // DECD_XPiI + 536889279U, // DECD_ZPiI + 536922631U, // DECH_XPiI + 6842887U, // DECH_ZPiI + 2315308983U, // DECP_XP_B + 2348863415U, // DECP_XP_D + 2717962167U, // DECP_XP_H + 2415972279U, // DECP_XP_S + 2147504055U, // DECP_ZP_D + 604532663U, // DECP_ZP_H + 2147520439U, // DECP_ZP_S + 536925351U, // DECW_XPiI + 536908967U, // DECW_ZPiI + 116059U, // DMB + 5966U, // DRPS + 116282U, // DSB + 637554371U, // DUPM_ZI + 671101025U, // DUP_ZI_B + 704663649U, // DUP_ZI_D + 7368801U, // DUP_ZI_H + 738234465U, // DUP_ZI_S + 2248159329U, // DUP_ZR_B + 2248167521U, // DUP_ZR_D + 611872865U, // DUP_ZR_H + 2248183905U, // DUP_ZR_S + 167784545U, // DUP_ZZI_B + 201347169U, // DUP_ZZI_D + 776499297U, // DUP_ZZI_H + 127073U, // DUP_ZZI_Q + 268472417U, // DUP_ZZI_S + 2249240673U, // DUPv16i8gpr + 2215686241U, // DUPv16i8lane + 2249764961U, // DUPv2i32gpr + 2216210529U, // DUPv2i32lane + 2250289249U, // DUPv2i64gpr + 69251169U, // DUPv2i64lane + 2250813537U, // DUPv4i16gpr + 69775457U, // DUPv4i16lane + 2251337825U, // DUPv4i32gpr + 2217783393U, // DUPv4i32lane + 2251862113U, // DUPv8i16gpr + 70824033U, // DUPv8i16lane + 2252386401U, // DUPv8i8gpr + 2218831969U, // DUPv8i8lane 0U, // EONWrr - 17049150U, // EONWrs + 100716298U, // EONWrs 0U, // EONXrr - 17049150U, // EONXrs - 17049538U, // EORWri + 100716298U, // EONXrs + 68198926U, // EOR3 + 302002853U, // EORS_PPzPP + 302044187U, // EORV_VPZ_B + 302044187U, // EORV_VPZ_D + 302044187U, // EORV_VPZ_H + 302044187U, // EORV_VPZ_S + 100716853U, // EORWri 0U, // EORWrr - 17049538U, // EORWrs - 17049538U, // EORXri + 100716853U, // EORWrs + 100716853U, // EORXri 0U, // EORXrr - 17049538U, // EORXrs - 2147489730U, // EORv16i8 - 3759937474U, // EORv8i8 - 2724U, // ERET - 17049585U, // EXTRWrri - 17049585U, // EXTRXrri - 2147490026U, // EXTv16i8 - 3759937770U, // EXTv8i8 + 100716853U, // EORXrs + 302002485U, // EOR_PPzPP + 201347381U, // EOR_ZI + 302002485U, // EOR_ZPmZ_B + 302010677U, // EOR_ZPmZ_D + 2186309941U, // EOR_ZPmZ_H + 302027061U, // EOR_ZPmZ_S + 201347381U, // EOR_ZZZ + 68202805U, // EORv16i8 + 2218832181U, // EORv8i8 + 5971U, // ERET + 5891U, // ERETAA + 5898U, // ERETAB + 100716930U, // EXTRWrri + 100716930U, // EXTRXrri + 167785316U, // EXT_ZZI + 68203364U, // EXTv16i8 + 2218832740U, // EXTv8i8 0U, // F128CSEL - 17048340U, // FABD32 - 17048340U, // FABD64 - 2684883732U, // FABDv2f32 - 537662228U, // FABDv2f64 - 1075057428U, // FABDv4f32 - 553920549U, // FABSDr - 553920549U, // FABSSr - 1074272293U, // FABSv2f32 - 1611405349U, // FABSv2f64 - 2685671461U, // FABSv4f32 - 17048436U, // FACGE32 - 17048436U, // FACGE64 - 2684883828U, // FACGEv2f32 - 537662324U, // FACGEv2f64 - 1075057524U, // FACGEv4f32 - 17049772U, // FACGT32 - 17049772U, // FACGT64 - 2684885164U, // FACGTv2f32 - 537663660U, // FACGTv2f64 - 1075058860U, // FACGTv4f32 - 17048358U, // FADDDrr - 2684884663U, // FADDPv2f32 - 537663159U, // FADDPv2f64 - 1074013879U, // FADDPv2i32p - 1610884791U, // FADDPv2i64p - 1075058359U, // FADDPv4f32 - 17048358U, // FADDSrr - 2684883750U, // FADDv2f32 - 537662246U, // FADDv2f64 - 1075057446U, // FADDv4f32 - 17049315U, // FCCMPDrr - 17048473U, // FCCMPEDrr - 17048473U, // FCCMPESrr - 17049315U, // FCCMPSrr - 17049450U, // FCMEQ32 - 17049450U, // FCMEQ64 - 2164533098U, // FCMEQv1i32rz - 2164533098U, // FCMEQv1i64rz - 2684884842U, // FCMEQv2f32 - 537663338U, // FCMEQv2f64 - 2684884842U, // FCMEQv2i32rz - 3222017898U, // FCMEQv2i64rz - 1075058538U, // FCMEQv4f32 - 3759413098U, // FCMEQv4i32rz - 17048443U, // FCMGE32 - 17048443U, // FCMGE64 - 2164532091U, // FCMGEv1i32rz - 2164532091U, // FCMGEv1i64rz - 2684883835U, // FCMGEv2f32 - 537662331U, // FCMGEv2f64 - 2684883835U, // FCMGEv2i32rz - 3222016891U, // FCMGEv2i64rz - 1075057531U, // FCMGEv4f32 - 3759412091U, // FCMGEv4i32rz - 17049779U, // FCMGT32 - 17049779U, // FCMGT64 - 2164533427U, // FCMGTv1i32rz - 2164533427U, // FCMGTv1i64rz - 2684885171U, // FCMGTv2f32 - 537663667U, // FCMGTv2f64 - 2684885171U, // FCMGTv2i32rz - 3222018227U, // FCMGTv2i64rz - 1075058867U, // FCMGTv4f32 - 3759413427U, // FCMGTv4i32rz - 2164532098U, // FCMLEv1i32rz - 2164532098U, // FCMLEv1i64rz - 2684883842U, // FCMLEv2i32rz - 3222016898U, // FCMLEv2i64rz - 3759412098U, // FCMLEv4i32rz - 2164533445U, // FCMLTv1i32rz - 2164533445U, // FCMLTv1i64rz - 2684885189U, // FCMLTv2i32rz - 3222018245U, // FCMLTv2i64rz - 3759413445U, // FCMLTv4i32rz - 2369258U, // FCMPDri - 553920234U, // FCMPDrr - 2368417U, // FCMPEDri - 553919393U, // FCMPEDrr - 2368417U, // FCMPESri - 553919393U, // FCMPESrr - 2369258U, // FCMPSri - 553920234U, // FCMPSrr - 17048887U, // FCSELDrrr - 17048887U, // FCSELSrrr - 553920541U, // FCVTASUWDr - 553920541U, // FCVTASUWSr - 553920541U, // FCVTASUXDr - 553920541U, // FCVTASUXSr - 553920541U, // FCVTASv1i32 - 553920541U, // FCVTASv1i64 - 1074272285U, // FCVTASv2f32 - 1611405341U, // FCVTASv2f64 - 2685671453U, // FCVTASv4f32 - 553920751U, // FCVTAUUWDr - 553920751U, // FCVTAUUWSr - 553920751U, // FCVTAUUXDr - 553920751U, // FCVTAUUXSr - 553920751U, // FCVTAUv1i32 - 553920751U, // FCVTAUv1i64 - 1074272495U, // FCVTAUv2f32 - 1611405551U, // FCVTAUv2f64 - 2685671663U, // FCVTAUv4f32 - 553920740U, // FCVTDHr - 553920740U, // FCVTDSr - 553920740U, // FCVTHDr - 553920740U, // FCVTHSr - 1074533828U, // FCVTLv2i32 - 2148799940U, // FCVTLv4i16 - 2685145352U, // FCVTLv4i32 - 3222540552U, // FCVTLv8i16 - 553920615U, // FCVTMSUWDr - 553920615U, // FCVTMSUWSr - 553920615U, // FCVTMSUXDr - 553920615U, // FCVTMSUXSr - 553920615U, // FCVTMSv1i32 - 553920615U, // FCVTMSv1i64 - 1074272359U, // FCVTMSv2f32 - 1611405415U, // FCVTMSv2f64 - 2685671527U, // FCVTMSv4f32 - 553920767U, // FCVTMUUWDr - 553920767U, // FCVTMUUWSr - 553920767U, // FCVTMUUXDr - 553920767U, // FCVTMUUXSr - 553920767U, // FCVTMUv1i32 - 553920767U, // FCVTMUv1i64 - 1074272511U, // FCVTMUv2f32 - 1611405567U, // FCVTMUv2f64 - 2685671679U, // FCVTMUv4f32 - 553920628U, // FCVTNSUWDr - 553920628U, // FCVTNSUWSr - 553920628U, // FCVTNSUXDr - 553920628U, // FCVTNSUXSr - 553920628U, // FCVTNSv1i32 - 553920628U, // FCVTNSv1i64 - 1074272372U, // FCVTNSv2f32 - 1611405428U, // FCVTNSv2f64 - 2685671540U, // FCVTNSv4f32 - 553920775U, // FCVTNUUWDr - 553920775U, // FCVTNUUWSr - 553920775U, // FCVTNUUXDr - 553920775U, // FCVTNUUXSr - 553920775U, // FCVTNUv1i32 - 553920775U, // FCVTNUv1i64 - 1074272519U, // FCVTNUv2f32 - 1611405575U, // FCVTNUv2f64 - 2685671687U, // FCVTNUv4f32 - 1611142770U, // FCVTNv2i32 - 2685408882U, // FCVTNv4i16 - 1645490510U, // FCVTNv4i32 - 2719494478U, // FCVTNv8i16 - 553920644U, // FCVTPSUWDr - 553920644U, // FCVTPSUWSr - 553920644U, // FCVTPSUXDr - 553920644U, // FCVTPSUXSr - 553920644U, // FCVTPSv1i32 - 553920644U, // FCVTPSv1i64 - 1074272388U, // FCVTPSv2f32 - 1611405444U, // FCVTPSv2f64 - 2685671556U, // FCVTPSv4f32 - 553920783U, // FCVTPUUWDr - 553920783U, // FCVTPUUWSr - 553920783U, // FCVTPUUXDr - 553920783U, // FCVTPUUXSr - 553920783U, // FCVTPUv1i32 - 553920783U, // FCVTPUv1i64 - 1074272527U, // FCVTPUv2f32 - 1611405583U, // FCVTPUv2f64 - 2685671695U, // FCVTPUv4f32 - 553920740U, // FCVTSDr - 553920740U, // FCVTSHr - 553920168U, // FCVTXNv1i64 - 1611142824U, // FCVTXNv2f32 - 1645490564U, // FCVTXNv4f32 - 17049759U, // FCVTZSSWDri - 17049759U, // FCVTZSSWSri - 17049759U, // FCVTZSSXDri - 17049759U, // FCVTZSSXSri - 553920671U, // FCVTZSUWDr - 553920671U, // FCVTZSUWSr - 553920671U, // FCVTZSUXDr - 553920671U, // FCVTZSUXSr - 17049759U, // FCVTZS_IntSWDri - 17049759U, // FCVTZS_IntSWSri - 17049759U, // FCVTZS_IntSXDri - 17049759U, // FCVTZS_IntSXSri - 553920671U, // FCVTZS_IntUWDr - 553920671U, // FCVTZS_IntUWSr - 553920671U, // FCVTZS_IntUXDr - 553920671U, // FCVTZS_IntUXSr - 1074272415U, // FCVTZS_Intv2f32 - 1611405471U, // FCVTZS_Intv2f64 - 2685671583U, // FCVTZS_Intv4f32 - 17049759U, // FCVTZSd - 17049759U, // FCVTZSs - 553920671U, // FCVTZSv1i32 - 553920671U, // FCVTZSv1i64 - 1074272415U, // FCVTZSv2f32 - 1611405471U, // FCVTZSv2f64 - 2684885151U, // FCVTZSv2i32_shift - 537663647U, // FCVTZSv2i64_shift - 2685671583U, // FCVTZSv4f32 - 1075058847U, // FCVTZSv4i32_shift - 17049879U, // FCVTZUSWDri - 17049879U, // FCVTZUSWSri - 17049879U, // FCVTZUSXDri - 17049879U, // FCVTZUSXSri - 553920791U, // FCVTZUUWDr - 553920791U, // FCVTZUUWSr - 553920791U, // FCVTZUUXDr - 553920791U, // FCVTZUUXSr - 17049879U, // FCVTZU_IntSWDri - 17049879U, // FCVTZU_IntSWSri - 17049879U, // FCVTZU_IntSXDri - 17049879U, // FCVTZU_IntSXSri - 553920791U, // FCVTZU_IntUWDr - 553920791U, // FCVTZU_IntUWSr - 553920791U, // FCVTZU_IntUXDr - 553920791U, // FCVTZU_IntUXSr - 1074272535U, // FCVTZU_Intv2f32 - 1611405591U, // FCVTZU_Intv2f64 - 2685671703U, // FCVTZU_Intv4f32 - 17049879U, // FCVTZUd - 17049879U, // FCVTZUs - 553920791U, // FCVTZUv1i32 - 553920791U, // FCVTZUv1i64 - 1074272535U, // FCVTZUv2f32 - 1611405591U, // FCVTZUv2f64 - 2684885271U, // FCVTZUv2i32_shift - 537663767U, // FCVTZUv2i64_shift - 2685671703U, // FCVTZUv4f32 - 1075058967U, // FCVTZUv4i32_shift - 17049898U, // FDIVDrr - 17049898U, // FDIVSrr - 2684885290U, // FDIVv2f32 - 537663786U, // FDIVv2f64 - 1075058986U, // FDIVv4f32 - 17048394U, // FMADDDrrr - 17048394U, // FMADDSrrr - 17050100U, // FMAXDrr - 17049087U, // FMAXNMDrr - 2684884729U, // FMAXNMPv2f32 - 537663225U, // FMAXNMPv2f64 - 1074013945U, // FMAXNMPv2i32p - 1610884857U, // FMAXNMPv2i64p - 1075058425U, // FMAXNMPv4f32 - 17049087U, // FMAXNMSrr - 2684627285U, // FMAXNMVv4i32v - 2684884479U, // FMAXNMv2f32 - 537662975U, // FMAXNMv2f64 - 1075058175U, // FMAXNMv4f32 - 2684884802U, // FMAXPv2f32 - 537663298U, // FMAXPv2f64 - 1074014018U, // FMAXPv2i32p - 1610884930U, // FMAXPv2i64p - 1075058498U, // FMAXPv4f32 - 17050100U, // FMAXSrr - 2684627340U, // FMAXVv4i32v - 2684885492U, // FMAXv2f32 - 537663988U, // FMAXv2f64 - 1075059188U, // FMAXv4f32 - 17049126U, // FMINDrr - 17049079U, // FMINNMDrr - 2684884720U, // FMINNMPv2f32 - 537663216U, // FMINNMPv2f64 - 1074013936U, // FMINNMPv2i32p - 1610884848U, // FMINNMPv2i64p - 1075058416U, // FMINNMPv4f32 - 17049079U, // FMINNMSrr - 2684627276U, // FMINNMVv4i32v - 2684884471U, // FMINNMv2f32 - 537662967U, // FMINNMv2f64 - 1075058167U, // FMINNMv4f32 - 2684884744U, // FMINPv2f32 - 537663240U, // FMINPv2f64 - 1074013960U, // FMINPv2i32p - 1610884872U, // FMINPv2i64p - 1075058440U, // FMINPv4f32 - 17049126U, // FMINSrr - 2684627294U, // FMINVv4i32v - 2684884518U, // FMINv2f32 - 537663014U, // FMINv2f64 - 1075058214U, // FMINv4f32 - 67404282U, // FMLAv1i32_indexed - 67404282U, // FMLAv1i64_indexed - 2718446074U, // FMLAv2f32 - 571224570U, // FMLAv2f64 - 2718446074U, // FMLAv2i32_indexed - 571224570U, // FMLAv2i64_indexed - 1108619770U, // FMLAv4f32 - 1108619770U, // FMLAv4i32_indexed - 67405921U, // FMLSv1i32_indexed - 67405921U, // FMLSv1i64_indexed - 2718447713U, // FMLSv2f32 - 571226209U, // FMLSv2f64 - 2718447713U, // FMLSv2i32_indexed - 571226209U, // FMLSv2i64_indexed - 1108621409U, // FMLSv4f32 - 1108621409U, // FMLSv4i32_indexed - 1074014586U, // FMOVDXHighr - 553920890U, // FMOVDXr - 117713274U, // FMOVDi - 553920890U, // FMOVDr - 553920890U, // FMOVSWr - 117713274U, // FMOVSi - 553920890U, // FMOVSr - 553920890U, // FMOVWSr - 556276090U, // FMOVXDHighr - 553920890U, // FMOVXDr - 117971322U, // FMOVv2f32_ns - 118233466U, // FMOVv2f64_ns - 118757754U, // FMOVv4f32_ns - 17048257U, // FMSUBDrrr - 17048257U, // FMSUBSrrr - 17049035U, // FMULDrr - 17049035U, // FMULSrr - 17050139U, // FMULX32 - 17050139U, // FMULX64 - 17050139U, // FMULXv1i32_indexed - 17050139U, // FMULXv1i64_indexed - 2684885531U, // FMULXv2f32 - 537664027U, // FMULXv2f64 - 2684885531U, // FMULXv2i32_indexed - 537664027U, // FMULXv2i64_indexed - 1075059227U, // FMULXv4f32 - 1075059227U, // FMULXv4i32_indexed - 17049035U, // FMULv1i32_indexed - 17049035U, // FMULv1i64_indexed - 2684884427U, // FMULv2f32 - 537662923U, // FMULv2f64 - 2684884427U, // FMULv2i32_indexed - 537662923U, // FMULv2i64_indexed - 1075058123U, // FMULv4f32 - 1075058123U, // FMULv4i32_indexed - 553919443U, // FNEGDr - 553919443U, // FNEGSr - 1074271187U, // FNEGv2f32 - 1611404243U, // FNEGv2f64 - 2685670355U, // FNEGv4f32 - 17048401U, // FNMADDDrrr - 17048401U, // FNMADDSrrr - 17048264U, // FNMSUBDrrr - 17048264U, // FNMSUBSrrr - 17049041U, // FNMULDrr - 17049041U, // FNMULSrr - 553919369U, // FRECPEv1i32 - 553919369U, // FRECPEv1i64 - 1074271113U, // FRECPEv2f32 - 1611404169U, // FRECPEv2f64 - 2685670281U, // FRECPEv4f32 - 17049724U, // FRECPS32 - 17049724U, // FRECPS64 - 2684885116U, // FRECPSv2f32 - 537663612U, // FRECPSv2f64 - 1075058812U, // FRECPSv4f32 - 553921058U, // FRECPXv1i32 - 553921058U, // FRECPXv1i64 - 553919002U, // FRINTADr - 553919002U, // FRINTASr - 1074270746U, // FRINTAv2f32 - 1611403802U, // FRINTAv2f64 - 2685669914U, // FRINTAv4f32 - 553919658U, // FRINTIDr - 553919658U, // FRINTISr - 1074271402U, // FRINTIv2f32 - 1611404458U, // FRINTIv2f64 - 2685670570U, // FRINTIv4f32 - 553920007U, // FRINTMDr - 553920007U, // FRINTMSr - 1074271751U, // FRINTMv2f32 - 1611404807U, // FRINTMv2f64 - 2685670919U, // FRINTMv4f32 - 553920106U, // FRINTNDr - 553920106U, // FRINTNSr - 1074271850U, // FRINTNv2f32 - 1611404906U, // FRINTNv2f64 - 2685671018U, // FRINTNv4f32 - 553920297U, // FRINTPDr - 553920297U, // FRINTPSr - 1074272041U, // FRINTPv2f32 - 1611405097U, // FRINTPv2f64 - 2685671209U, // FRINTPv4f32 - 553921066U, // FRINTXDr - 553921066U, // FRINTXSr - 1074272810U, // FRINTXv2f32 - 1611405866U, // FRINTXv2f64 - 2685671978U, // FRINTXv4f32 - 553921101U, // FRINTZDr - 553921101U, // FRINTZSr - 1074272845U, // FRINTZv2f32 - 1611405901U, // FRINTZv2f64 - 2685672013U, // FRINTZv4f32 - 553919406U, // FRSQRTEv1i32 - 553919406U, // FRSQRTEv1i64 - 1074271150U, // FRSQRTEv2f32 - 1611404206U, // FRSQRTEv2f64 - 2685670318U, // FRSQRTEv4f32 - 17049745U, // FRSQRTS32 - 17049745U, // FRSQRTS64 - 2684885137U, // FRSQRTSv2f32 - 537663633U, // FRSQRTSv2f64 - 1075058833U, // FRSQRTSv4f32 - 553920726U, // FSQRTDr - 553920726U, // FSQRTSr - 1074272470U, // FSQRTv2f32 - 1611405526U, // FSQRTv2f64 - 2685671638U, // FSQRTv4f32 - 17048237U, // FSUBDrr - 17048237U, // FSUBSrr - 2684883629U, // FSUBv2f32 - 537662125U, // FSUBv2f64 - 1075057325U, // FSUBv4f32 - 23145U, // HINT - 22720U, // HLT - 21258U, // HVC - 137115759U, // INSvi16gpr - 153892975U, // INSvi16lane - 137377903U, // INSvi32gpr - 691026031U, // INSvi32lane - 136853615U, // INSvi64gpr - 1227372655U, // INSvi64lane - 137640047U, // INSvi8gpr - 1765029999U, // INSvi8lane - 29329U, // ISB - 36885U, // LD1Fourv16b - 3710997U, // LD1Fourv16b_POST - 45077U, // LD1Fourv1d - 3981333U, // LD1Fourv1d_POST - 53269U, // LD1Fourv2d - 3727381U, // LD1Fourv2d_POST - 61461U, // LD1Fourv2s - 3997717U, // LD1Fourv2s_POST - 69653U, // LD1Fourv4h - 4005909U, // LD1Fourv4h_POST - 77845U, // LD1Fourv4s - 3751957U, // LD1Fourv4s_POST - 86037U, // LD1Fourv8b - 4022293U, // LD1Fourv8b_POST - 94229U, // LD1Fourv8h - 3768341U, // LD1Fourv8h_POST - 36885U, // LD1Onev16b - 4235285U, // LD1Onev16b_POST - 45077U, // LD1Onev1d - 4505621U, // LD1Onev1d_POST - 53269U, // LD1Onev2d - 4251669U, // LD1Onev2d_POST - 61461U, // LD1Onev2s - 4522005U, // LD1Onev2s_POST - 69653U, // LD1Onev4h - 4530197U, // LD1Onev4h_POST - 77845U, // LD1Onev4s - 4276245U, // LD1Onev4s_POST - 86037U, // LD1Onev8b - 4546581U, // LD1Onev8b_POST - 94229U, // LD1Onev8h - 4292629U, // LD1Onev8h_POST - 38769U, // LD1Rv16b - 4761457U, // LD1Rv16b_POST - 46961U, // LD1Rv1d - 4507505U, // LD1Rv1d_POST - 55153U, // LD1Rv2d - 4515697U, // LD1Rv2d_POST - 63345U, // LD1Rv2s - 5048177U, // LD1Rv2s_POST - 71537U, // LD1Rv4h - 5318513U, // LD1Rv4h_POST - 79729U, // LD1Rv4s - 5064561U, // LD1Rv4s_POST - 87921U, // LD1Rv8b - 4810609U, // LD1Rv8b_POST - 96113U, // LD1Rv8h - 5343089U, // LD1Rv8h_POST - 36885U, // LD1Threev16b - 5546005U, // LD1Threev16b_POST - 45077U, // LD1Threev1d - 5816341U, // LD1Threev1d_POST - 53269U, // LD1Threev2d - 5562389U, // LD1Threev2d_POST - 61461U, // LD1Threev2s - 5832725U, // LD1Threev2s_POST - 69653U, // LD1Threev4h - 5840917U, // LD1Threev4h_POST - 77845U, // LD1Threev4s - 5586965U, // LD1Threev4s_POST - 86037U, // LD1Threev8b - 5857301U, // LD1Threev8b_POST - 94229U, // LD1Threev8h - 5603349U, // LD1Threev8h_POST - 36885U, // LD1Twov16b - 3973141U, // LD1Twov16b_POST - 45077U, // LD1Twov1d - 4243477U, // LD1Twov1d_POST - 53269U, // LD1Twov2d - 3989525U, // LD1Twov2d_POST - 61461U, // LD1Twov2s - 4259861U, // LD1Twov2s_POST - 69653U, // LD1Twov4h - 4268053U, // LD1Twov4h_POST - 77845U, // LD1Twov4s - 4014101U, // LD1Twov4s_POST - 86037U, // LD1Twov8b - 4284437U, // LD1Twov8b_POST - 94229U, // LD1Twov8h - 4030485U, // LD1Twov8h_POST - 6131733U, // LD1i16 - 6397973U, // LD1i16_POST - 6139925U, // LD1i32 - 6668309U, // LD1i32_POST - 6148117U, // LD1i64 - 6938645U, // LD1i64_POST - 6156309U, // LD1i8 - 7208981U, // LD1i8_POST - 38775U, // LD2Rv16b - 5285751U, // LD2Rv16b_POST - 46967U, // LD2Rv1d - 4245367U, // LD2Rv1d_POST - 55159U, // LD2Rv2d - 4253559U, // LD2Rv2d_POST - 63351U, // LD2Rv2s - 4523895U, // LD2Rv2s_POST - 71543U, // LD2Rv4h - 5056375U, // LD2Rv4h_POST - 79735U, // LD2Rv4s - 4540279U, // LD2Rv4s_POST - 87927U, // LD2Rv8b - 5334903U, // LD2Rv8b_POST - 96119U, // LD2Rv8h - 5080951U, // LD2Rv8h_POST - 36947U, // LD2Twov16b - 3973203U, // LD2Twov16b_POST - 53331U, // LD2Twov2d - 3989587U, // LD2Twov2d_POST - 61523U, // LD2Twov2s - 4259923U, // LD2Twov2s_POST - 69715U, // LD2Twov4h - 4268115U, // LD2Twov4h_POST - 77907U, // LD2Twov4s - 4014163U, // LD2Twov4s_POST - 86099U, // LD2Twov8b - 4284499U, // LD2Twov8b_POST - 94291U, // LD2Twov8h - 4030547U, // LD2Twov8h_POST - 6131795U, // LD2i16 - 6660179U, // LD2i16_POST - 6139987U, // LD2i32 - 6930515U, // LD2i32_POST - 6148179U, // LD2i64 - 7462995U, // LD2i64_POST - 6156371U, // LD2i8 - 6422611U, // LD2i8_POST - 38781U, // LD3Rv16b - 7645053U, // LD3Rv16b_POST - 46973U, // LD3Rv1d - 5818237U, // LD3Rv1d_POST - 55165U, // LD3Rv2d - 5826429U, // LD3Rv2d_POST - 63357U, // LD3Rv2s - 7931773U, // LD3Rv2s_POST - 71549U, // LD3Rv4h - 8202109U, // LD3Rv4h_POST - 79741U, // LD3Rv4s - 7948157U, // LD3Rv4s_POST - 87933U, // LD3Rv8b - 7694205U, // LD3Rv8b_POST - 96125U, // LD3Rv8h - 8226685U, // LD3Rv8h_POST - 37317U, // LD3Threev16b - 5546437U, // LD3Threev16b_POST - 53701U, // LD3Threev2d - 5562821U, // LD3Threev2d_POST - 61893U, // LD3Threev2s - 5833157U, // LD3Threev2s_POST - 70085U, // LD3Threev4h - 5841349U, // LD3Threev4h_POST - 78277U, // LD3Threev4s - 5587397U, // LD3Threev4s_POST - 86469U, // LD3Threev8b - 5857733U, // LD3Threev8b_POST - 94661U, // LD3Threev8h - 5603781U, // LD3Threev8h_POST - 6132165U, // LD3i16 - 8495557U, // LD3i16_POST - 6140357U, // LD3i32 - 8765893U, // LD3i32_POST - 6148549U, // LD3i64 - 9036229U, // LD3i64_POST - 6156741U, // LD3i8 - 9306565U, // LD3i8_POST - 37341U, // LD4Fourv16b - 3711453U, // LD4Fourv16b_POST - 53725U, // LD4Fourv2d - 3727837U, // LD4Fourv2d_POST - 61917U, // LD4Fourv2s - 3998173U, // LD4Fourv2s_POST - 70109U, // LD4Fourv4h - 4006365U, // LD4Fourv4h_POST - 78301U, // LD4Fourv4s - 3752413U, // LD4Fourv4s_POST - 86493U, // LD4Fourv8b - 4022749U, // LD4Fourv8b_POST - 94685U, // LD4Fourv8h - 3768797U, // LD4Fourv8h_POST - 38787U, // LD4Rv16b - 5023619U, // LD4Rv16b_POST - 46979U, // LD4Rv1d - 3983235U, // LD4Rv1d_POST - 55171U, // LD4Rv2d - 3991427U, // LD4Rv2d_POST - 63363U, // LD4Rv2s - 4261763U, // LD4Rv2s_POST - 71555U, // LD4Rv4h - 4532099U, // LD4Rv4h_POST - 79747U, // LD4Rv4s - 4278147U, // LD4Rv4s_POST - 87939U, // LD4Rv8b - 5072771U, // LD4Rv8b_POST - 96131U, // LD4Rv8h - 4556675U, // LD4Rv8h_POST - 6132189U, // LD4i16 - 6922717U, // LD4i16_POST - 6140381U, // LD4i32 - 7455197U, // LD4i32_POST - 6148573U, // LD4i64 - 9560541U, // LD4i64_POST - 6156765U, // LD4i8 - 6685149U, // LD4i8_POST - 26485304U, // LDARB - 26485801U, // LDARH - 26486665U, // LDARW - 26486665U, // LDARX - 553920315U, // LDAXPW - 553920315U, // LDAXPX - 26485358U, // LDAXRB - 26485855U, // LDAXRH - 26486787U, // LDAXRW - 26486787U, // LDAXRX - 553920258U, // LDNPDi - 553920258U, // LDNPQi - 553920258U, // LDNPSi - 553920258U, // LDNPWi - 553920258U, // LDNPXi - 553920190U, // LDPDi - 604276414U, // LDPDpost - 604276414U, // LDPDpre - 553920190U, // LDPQi - 604276414U, // LDPQpost - 604276414U, // LDPQpre - 553920974U, // LDPSWi - 604277198U, // LDPSWpost - 604277198U, // LDPSWpre - 553920190U, // LDPSi - 604276414U, // LDPSpost - 604276414U, // LDPSpre - 553920190U, // LDPWi - 604276414U, // LDPWpost - 604276414U, // LDPWpre - 553920190U, // LDPXi - 604276414U, // LDPXpost - 604276414U, // LDPXpre - 1150583359U, // LDRBBpost - 76841535U, // LDRBBpre - 26485311U, // LDRBBroW - 26485311U, // LDRBBroX - 26485311U, // LDRBBui - 1150584728U, // LDRBpost - 76842904U, // LDRBpre - 26486680U, // LDRBroW - 26486680U, // LDRBroX - 26486680U, // LDRBui - 100935576U, // LDRDl - 1150584728U, // LDRDpost - 76842904U, // LDRDpre - 26486680U, // LDRDroW - 26486680U, // LDRDroX - 26486680U, // LDRDui - 1150583856U, // LDRHHpost - 76842032U, // LDRHHpre - 26485808U, // LDRHHroW - 26485808U, // LDRHHroX - 26485808U, // LDRHHui - 1150584728U, // LDRHpost - 76842904U, // LDRHpre - 26486680U, // LDRHroW - 26486680U, // LDRHroX - 26486680U, // LDRHui - 100935576U, // LDRQl - 1150584728U, // LDRQpost - 76842904U, // LDRQpre - 26486680U, // LDRQroW - 26486680U, // LDRQroX - 26486680U, // LDRQui - 1150583446U, // LDRSBWpost - 76841622U, // LDRSBWpre - 26485398U, // LDRSBWroW - 26485398U, // LDRSBWroX - 26485398U, // LDRSBWui - 1150583446U, // LDRSBXpost - 76841622U, // LDRSBXpre - 26485398U, // LDRSBXroW - 26485398U, // LDRSBXroX - 26485398U, // LDRSBXui - 1150583933U, // LDRSHWpost - 76842109U, // LDRSHWpre - 26485885U, // LDRSHWroW - 26485885U, // LDRSHWroX - 26485885U, // LDRSHWui - 1150583933U, // LDRSHXpost - 76842109U, // LDRSHXpre - 26485885U, // LDRSHXroW - 26485885U, // LDRSHXroX - 26485885U, // LDRSHXui - 100936149U, // LDRSWl - 1150585301U, // LDRSWpost - 76843477U, // LDRSWpre - 26487253U, // LDRSWroW - 26487253U, // LDRSWroX - 26487253U, // LDRSWui - 100935576U, // LDRSl - 1150584728U, // LDRSpost - 76842904U, // LDRSpre - 26486680U, // LDRSroW - 26486680U, // LDRSroX - 26486680U, // LDRSui - 100935576U, // LDRWl - 1150584728U, // LDRWpost - 76842904U, // LDRWpre - 26486680U, // LDRWroW - 26486680U, // LDRWroX - 26486680U, // LDRWui - 100935576U, // LDRXl - 1150584728U, // LDRXpost - 76842904U, // LDRXpre - 26486680U, // LDRXroW - 26486680U, // LDRXroX - 26486680U, // LDRXui - 26485324U, // LDTRBi - 26485821U, // LDTRHi - 26485405U, // LDTRSBWi - 26485405U, // LDTRSBXi - 26485892U, // LDTRSHWi - 26485892U, // LDTRSHXi - 26487260U, // LDTRSWi - 26486752U, // LDTRWi - 26486752U, // LDTRXi - 26485344U, // LDURBBi - 26486775U, // LDURBi - 26486775U, // LDURDi - 26485841U, // LDURHHi - 26486775U, // LDURHi - 26486775U, // LDURQi - 26485413U, // LDURSBWi - 26485413U, // LDURSBXi - 26485900U, // LDURSHWi - 26485900U, // LDURSHXi - 26487268U, // LDURSWi - 26486775U, // LDURSi - 26486775U, // LDURWi - 26486775U, // LDURXi - 553920343U, // LDXPW - 553920343U, // LDXPX - 26485366U, // LDXRB - 26485863U, // LDXRH - 26486794U, // LDXRW - 26486794U, // LDXRX + 100714404U, // FABD16 + 100714404U, // FABD32 + 100714404U, // FABD64 + 302008228U, // FABD_ZPmZ_D + 2186307492U, // FABD_ZPmZ_H + 302024612U, // FABD_ZPmZ_S + 2216208292U, // FABDv2f32 + 2216732580U, // FABDv2f64 + 69773220U, // FABDv4f16 + 70297508U, // FABDv4f32 + 2218305444U, // FABDv8f16 + 2248200686U, // FABSDr + 2248200686U, // FABSHr + 2248200686U, // FABSSr + 20974U, // FABS_ZPmZ_D + 2181591534U, // FABS_ZPmZ_H + 37358U, // FABS_ZPmZ_S + 68727278U, // FABSv2f32 + 2216735214U, // FABSv2f64 + 69775854U, // FABSv4f16 + 2217783790U, // FABSv4f32 + 70824430U, // FABSv8f16 + 100714601U, // FACGE16 + 100714601U, // FACGE32 + 100714601U, // FACGE64 + 302008425U, // FACGE_PPzZZ_D + 2622515305U, // FACGE_PPzZZ_H + 302024809U, // FACGE_PPzZZ_S + 2216208489U, // FACGEv2f32 + 2216732777U, // FACGEv2f64 + 69773417U, // FACGEv4f16 + 70297705U, // FACGEv4f32 + 2218305641U, // FACGEv8f16 + 100717291U, // FACGT16 + 100717291U, // FACGT32 + 100717291U, // FACGT64 + 302011115U, // FACGT_PPzZZ_D + 2622517995U, // FACGT_PPzZZ_H + 302027499U, // FACGT_PPzZZ_S + 2216211179U, // FACGTv2f32 + 2216735467U, // FACGTv2f64 + 69776107U, // FACGTv4f16 + 70300395U, // FACGTv4f32 + 2218308331U, // FACGTv8f16 + 302039688U, // FADDA_VPZ_D + 302039688U, // FADDA_VPZ_H + 302039688U, // FADDA_VPZ_S + 100714475U, // FADDDrr + 100714475U, // FADDHrr + 2216210389U, // FADDPv2f32 + 2216734677U, // FADDPv2f64 + 2214645717U, // FADDPv2i16p + 67162069U, // FADDPv2i32p + 2214645717U, // FADDPv2i64p + 69775317U, // FADDPv4f16 + 70299605U, // FADDPv4f32 + 2218307541U, // FADDPv8f16 + 100714475U, // FADDSrr + 302044057U, // FADDV_VPZ_D + 302044057U, // FADDV_VPZ_H + 302044057U, // FADDV_VPZ_S + 302008299U, // FADD_ZPmI_D + 2186307563U, // FADD_ZPmI_H + 302024683U, // FADD_ZPmI_S + 302008299U, // FADD_ZPmZ_D + 2186307563U, // FADD_ZPmZ_H + 302024683U, // FADD_ZPmZ_S + 201345003U, // FADD_ZZZ_D + 2387109867U, // FADD_ZZZ_H + 268470251U, // FADD_ZZZ_S + 2216208363U, // FADDv2f32 + 2216732651U, // FADDv2f64 + 69773291U, // FADDv4f16 + 70297579U, // FADDv4f32 + 2218305515U, // FADDv8f16 + 302008285U, // FCADD_ZPmZ_D + 2186307549U, // FCADD_ZPmZ_H + 302024669U, // FCADD_ZPmZ_S + 2216208349U, // FCADDv2f32 + 2216732637U, // FCADDv2f64 + 69773277U, // FCADDv4f16 + 70297565U, // FCADDv4f32 + 2218305501U, // FCADDv8f16 + 100716545U, // FCCMPDrr + 100714692U, // FCCMPEDrr + 100714692U, // FCCMPEHrr + 100714692U, // FCCMPESrr + 100716545U, // FCCMPHrr + 100716545U, // FCCMPSrr + 100716698U, // FCMEQ16 + 100716698U, // FCMEQ32 + 100716698U, // FCMEQ64 + 302010522U, // FCMEQ_PPzZ0_D + 2622517402U, // FCMEQ_PPzZ0_H + 302026906U, // FCMEQ_PPzZ0_S + 302010522U, // FCMEQ_PPzZZ_D + 2622517402U, // FCMEQ_PPzZZ_H + 302026906U, // FCMEQ_PPzZZ_S + 100716698U, // FCMEQv1i16rz + 100716698U, // FCMEQv1i32rz + 100716698U, // FCMEQv1i64rz + 2216210586U, // FCMEQv2f32 + 2216734874U, // FCMEQv2f64 + 2216210586U, // FCMEQv2i32rz + 69251226U, // FCMEQv2i64rz + 69775514U, // FCMEQv4f16 + 70299802U, // FCMEQv4f32 + 2217259162U, // FCMEQv4i16rz + 70299802U, // FCMEQv4i32rz + 2218307738U, // FCMEQv8f16 + 2218307738U, // FCMEQv8i16rz + 100714608U, // FCMGE16 + 100714608U, // FCMGE32 + 100714608U, // FCMGE64 + 302008432U, // FCMGE_PPzZ0_D + 2622515312U, // FCMGE_PPzZ0_H + 302024816U, // FCMGE_PPzZ0_S + 302008432U, // FCMGE_PPzZZ_D + 2622515312U, // FCMGE_PPzZZ_H + 302024816U, // FCMGE_PPzZZ_S + 100714608U, // FCMGEv1i16rz + 100714608U, // FCMGEv1i32rz + 100714608U, // FCMGEv1i64rz + 2216208496U, // FCMGEv2f32 + 2216732784U, // FCMGEv2f64 + 2216208496U, // FCMGEv2i32rz + 69249136U, // FCMGEv2i64rz + 69773424U, // FCMGEv4f16 + 70297712U, // FCMGEv4f32 + 2217257072U, // FCMGEv4i16rz + 70297712U, // FCMGEv4i32rz + 2218305648U, // FCMGEv8f16 + 2218305648U, // FCMGEv8i16rz + 100717298U, // FCMGT16 + 100717298U, // FCMGT32 + 100717298U, // FCMGT64 + 302011122U, // FCMGT_PPzZ0_D + 2622518002U, // FCMGT_PPzZ0_H + 302027506U, // FCMGT_PPzZ0_S + 302011122U, // FCMGT_PPzZZ_D + 2622518002U, // FCMGT_PPzZZ_H + 302027506U, // FCMGT_PPzZZ_S + 100717298U, // FCMGTv1i16rz + 100717298U, // FCMGTv1i32rz + 100717298U, // FCMGTv1i64rz + 2216211186U, // FCMGTv2f32 + 2216735474U, // FCMGTv2f64 + 2216211186U, // FCMGTv2i32rz + 69251826U, // FCMGTv2i64rz + 69776114U, // FCMGTv4f16 + 70300402U, // FCMGTv4f32 + 2217259762U, // FCMGTv4i16rz + 70300402U, // FCMGTv4i32rz + 2218308338U, // FCMGTv8f16 + 2218308338U, // FCMGTv8i16rz + 302006961U, // FCMLA_ZPmZZ_D + 2186306225U, // FCMLA_ZPmZZ_H + 302023345U, // FCMLA_ZPmZZ_S + 243294897U, // FCMLA_ZZZI_H + 2952823473U, // FCMLA_ZZZI_S + 2283332273U, // FCMLAv2f32 + 2283856561U, // FCMLAv2f64 + 136897201U, // FCMLAv4f16 + 136897201U, // FCMLAv4f16_indexed + 137421489U, // FCMLAv4f32 + 137421489U, // FCMLAv4f32_indexed + 2285429425U, // FCMLAv8f16 + 2285429425U, // FCMLAv8f16_indexed + 302008463U, // FCMLE_PPzZ0_D + 2622515343U, // FCMLE_PPzZ0_H + 302024847U, // FCMLE_PPzZ0_S + 100714639U, // FCMLEv1i16rz + 100714639U, // FCMLEv1i32rz + 100714639U, // FCMLEv1i64rz + 2216208527U, // FCMLEv2i32rz + 69249167U, // FCMLEv2i64rz + 2217257103U, // FCMLEv4i16rz + 70297743U, // FCMLEv4i32rz + 2218305679U, // FCMLEv8i16rz + 302011156U, // FCMLT_PPzZ0_D + 2622518036U, // FCMLT_PPzZ0_H + 302027540U, // FCMLT_PPzZ0_S + 100717332U, // FCMLTv1i16rz + 100717332U, // FCMLTv1i32rz + 100717332U, // FCMLTv1i64rz + 2216211220U, // FCMLTv2i32rz + 69251860U, // FCMLTv2i64rz + 2217259796U, // FCMLTv4i16rz + 70300436U, // FCMLTv4i32rz + 2218308372U, // FCMLTv8i16rz + 302008477U, // FCMNE_PPzZ0_D + 2622515357U, // FCMNE_PPzZ0_H + 302024861U, // FCMNE_PPzZ0_S + 302008477U, // FCMNE_PPzZZ_D + 2622515357U, // FCMNE_PPzZZ_H + 302024861U, // FCMNE_PPzZZ_S + 8966152U, // FCMPDri + 2248200200U, // FCMPDrr + 8964300U, // FCMPEDri + 2248198348U, // FCMPEDrr + 8964300U, // FCMPEHri + 2248198348U, // FCMPEHrr + 8964300U, // FCMPESri + 2248198348U, // FCMPESrr + 8966152U, // FCMPHri + 2248200200U, // FCMPHrr + 8966152U, // FCMPSri + 2248200200U, // FCMPSrr + 302010279U, // FCMUO_PPzZZ_D + 2622517159U, // FCMUO_PPzZZ_H + 302026663U, // FCMUO_PPzZZ_S + 21938U, // FCPY_ZPmI_D + 34108850U, // FCPY_ZPmI_H + 38322U, // FCPY_ZPmI_S + 100715904U, // FCSELDrrr + 100715904U, // FCSELHrrr + 100715904U, // FCSELSrrr + 2248200678U, // FCVTASUWDr + 2248200678U, // FCVTASUWHr + 2248200678U, // FCVTASUWSr + 2248200678U, // FCVTASUXDr + 2248200678U, // FCVTASUXHr + 2248200678U, // FCVTASUXSr + 2248200678U, // FCVTASv1f16 + 2248200678U, // FCVTASv1i32 + 2248200678U, // FCVTASv1i64 + 68727270U, // FCVTASv2f32 + 2216735206U, // FCVTASv2f64 + 69775846U, // FCVTASv4f16 + 2217783782U, // FCVTASv4f32 + 70824422U, // FCVTASv8f16 + 2248201065U, // FCVTAUUWDr + 2248201065U, // FCVTAUUWHr + 2248201065U, // FCVTAUUWSr + 2248201065U, // FCVTAUUXDr + 2248201065U, // FCVTAUUXHr + 2248201065U, // FCVTAUUXSr + 2248201065U, // FCVTAUv1f16 + 2248201065U, // FCVTAUv1i32 + 2248201065U, // FCVTAUv1i64 + 68727657U, // FCVTAUv2f32 + 2216735593U, // FCVTAUv2f64 + 69776233U, // FCVTAUv4f16 + 2217784169U, // FCVTAUv4f32 + 70824809U, // FCVTAUv8f16 + 2248201052U, // FCVTDHr + 2248201052U, // FCVTDSr + 2248201052U, // FCVTHDr + 2248201052U, // FCVTHSr + 69250649U, // FCVTLv2i32 + 70299225U, // FCVTLv4i16 + 2216730945U, // FCVTLv4i32 + 70295873U, // FCVTLv8i16 + 2248200806U, // FCVTMSUWDr + 2248200806U, // FCVTMSUWHr + 2248200806U, // FCVTMSUWSr + 2248200806U, // FCVTMSUXDr + 2248200806U, // FCVTMSUXHr + 2248200806U, // FCVTMSUXSr + 2248200806U, // FCVTMSv1f16 + 2248200806U, // FCVTMSv1i32 + 2248200806U, // FCVTMSv1i64 + 68727398U, // FCVTMSv2f32 + 2216735334U, // FCVTMSv2f64 + 69775974U, // FCVTMSv4f16 + 2217783910U, // FCVTMSv4f32 + 70824550U, // FCVTMSv8f16 + 2248201081U, // FCVTMUUWDr + 2248201081U, // FCVTMUUWHr + 2248201081U, // FCVTMUUWSr + 2248201081U, // FCVTMUUXDr + 2248201081U, // FCVTMUUXHr + 2248201081U, // FCVTMUUXSr + 2248201081U, // FCVTMUv1f16 + 2248201081U, // FCVTMUv1i32 + 2248201081U, // FCVTMUv1i64 + 68727673U, // FCVTMUv2f32 + 2216735609U, // FCVTMUv2f64 + 69776249U, // FCVTMUv4f16 + 2217784185U, // FCVTMUv4f32 + 70824825U, // FCVTMUv8f16 + 2248200832U, // FCVTNSUWDr + 2248200832U, // FCVTNSUWHr + 2248200832U, // FCVTNSUWSr + 2248200832U, // FCVTNSUXDr + 2248200832U, // FCVTNSUXHr + 2248200832U, // FCVTNSUXSr + 2248200832U, // FCVTNSv1f16 + 2248200832U, // FCVTNSv1i32 + 2248200832U, // FCVTNSv1i64 + 68727424U, // FCVTNSv2f32 + 2216735360U, // FCVTNSv2f64 + 69776000U, // FCVTNSv4f16 + 2217783936U, // FCVTNSv4f32 + 70824576U, // FCVTNSv8f16 + 2248201089U, // FCVTNUUWDr + 2248201089U, // FCVTNUUWHr + 2248201089U, // FCVTNUUWSr + 2248201089U, // FCVTNUUXDr + 2248201089U, // FCVTNUUXHr + 2248201089U, // FCVTNUUXSr + 2248201089U, // FCVTNUv1f16 + 2248201089U, // FCVTNUv1i32 + 2248201089U, // FCVTNUv1i64 + 68727681U, // FCVTNUv2f32 + 2216735617U, // FCVTNUv2f64 + 69776257U, // FCVTNUv4f16 + 2217784193U, // FCVTNUv4f32 + 70824833U, // FCVTNUv8f16 + 2216210238U, // FCVTNv2i32 + 2217258814U, // FCVTNv4i16 + 2284904839U, // FCVTNv4i32 + 2285429127U, // FCVTNv8i16 + 2248200848U, // FCVTPSUWDr + 2248200848U, // FCVTPSUWHr + 2248200848U, // FCVTPSUWSr + 2248200848U, // FCVTPSUXDr + 2248200848U, // FCVTPSUXHr + 2248200848U, // FCVTPSUXSr + 2248200848U, // FCVTPSv1f16 + 2248200848U, // FCVTPSv1i32 + 2248200848U, // FCVTPSv1i64 + 68727440U, // FCVTPSv2f32 + 2216735376U, // FCVTPSv2f64 + 69776016U, // FCVTPSv4f16 + 2217783952U, // FCVTPSv4f32 + 70824592U, // FCVTPSv8f16 + 2248201097U, // FCVTPUUWDr + 2248201097U, // FCVTPUUWHr + 2248201097U, // FCVTPUUWSr + 2248201097U, // FCVTPUUXDr + 2248201097U, // FCVTPUUXHr + 2248201097U, // FCVTPUUXSr + 2248201097U, // FCVTPUv1f16 + 2248201097U, // FCVTPUv1i32 + 2248201097U, // FCVTPUv1i64 + 68727689U, // FCVTPUv2f32 + 2216735625U, // FCVTPUv2f64 + 69776265U, // FCVTPUv4f16 + 2217784201U, // FCVTPUv4f32 + 70824841U, // FCVTPUv8f16 + 2248201052U, // FCVTSDr + 2248201052U, // FCVTSHr + 2248200052U, // FCVTXNv1i64 + 2216210292U, // FCVTXNv2f32 + 2284904893U, // FCVTXNv4f32 + 100717253U, // FCVTZSSWDri + 100717253U, // FCVTZSSWHri + 100717253U, // FCVTZSSWSri + 100717253U, // FCVTZSSXDri + 100717253U, // FCVTZSSXHri + 100717253U, // FCVTZSSXSri + 2248200901U, // FCVTZSUWDr + 2248200901U, // FCVTZSUWHr + 2248200901U, // FCVTZSUWSr + 2248200901U, // FCVTZSUXDr + 2248200901U, // FCVTZSUXHr + 2248200901U, // FCVTZSUXSr + 21189U, // FCVTZS_ZPmZ_DtoD + 37573U, // FCVTZS_ZPmZ_DtoS + 21189U, // FCVTZS_ZPmZ_HtoD + 2181591749U, // FCVTZS_ZPmZ_HtoH + 37573U, // FCVTZS_ZPmZ_HtoS + 21189U, // FCVTZS_ZPmZ_StoD + 37573U, // FCVTZS_ZPmZ_StoS + 100717253U, // FCVTZSd + 100717253U, // FCVTZSh + 100717253U, // FCVTZSs + 2248200901U, // FCVTZSv1f16 + 2248200901U, // FCVTZSv1i32 + 2248200901U, // FCVTZSv1i64 + 68727493U, // FCVTZSv2f32 + 2216735429U, // FCVTZSv2f64 + 2216211141U, // FCVTZSv2i32_shift + 2216735429U, // FCVTZSv2i64_shift + 69776069U, // FCVTZSv4f16 + 2217784005U, // FCVTZSv4f32 + 69776069U, // FCVTZSv4i16_shift + 70300357U, // FCVTZSv4i32_shift + 70824645U, // FCVTZSv8f16 + 2218308293U, // FCVTZSv8i16_shift + 100717457U, // FCVTZUSWDri + 100717457U, // FCVTZUSWHri + 100717457U, // FCVTZUSWSri + 100717457U, // FCVTZUSXDri + 100717457U, // FCVTZUSXHri + 100717457U, // FCVTZUSXSri + 2248201105U, // FCVTZUUWDr + 2248201105U, // FCVTZUUWHr + 2248201105U, // FCVTZUUWSr + 2248201105U, // FCVTZUUXDr + 2248201105U, // FCVTZUUXHr + 2248201105U, // FCVTZUUXSr + 21393U, // FCVTZU_ZPmZ_DtoD + 37777U, // FCVTZU_ZPmZ_DtoS + 21393U, // FCVTZU_ZPmZ_HtoD + 2181591953U, // FCVTZU_ZPmZ_HtoH + 37777U, // FCVTZU_ZPmZ_HtoS + 21393U, // FCVTZU_ZPmZ_StoD + 37777U, // FCVTZU_ZPmZ_StoS + 100717457U, // FCVTZUd + 100717457U, // FCVTZUh + 100717457U, // FCVTZUs + 2248201105U, // FCVTZUv1f16 + 2248201105U, // FCVTZUv1i32 + 2248201105U, // FCVTZUv1i64 + 68727697U, // FCVTZUv2f32 + 2216735633U, // FCVTZUv2f64 + 2216211345U, // FCVTZUv2i32_shift + 2216735633U, // FCVTZUv2i64_shift + 69776273U, // FCVTZUv4f16 + 2217784209U, // FCVTZUv4f32 + 69776273U, // FCVTZUv4i16_shift + 70300561U, // FCVTZUv4i32_shift + 70824849U, // FCVTZUv8f16 + 2218308497U, // FCVTZUv8i16_shift + 2181591900U, // FCVT_ZPmZ_DtoH + 37724U, // FCVT_ZPmZ_DtoS + 21340U, // FCVT_ZPmZ_HtoD + 37724U, // FCVT_ZPmZ_HtoS + 21340U, // FCVT_ZPmZ_StoD + 2181591900U, // FCVT_ZPmZ_StoH + 100717497U, // FDIVDrr + 100717497U, // FDIVHrr + 302010787U, // FDIVR_ZPmZ_D + 2186310051U, // FDIVR_ZPmZ_H + 302027171U, // FDIVR_ZPmZ_S + 100717497U, // FDIVSrr + 302011321U, // FDIV_ZPmZ_D + 2186310585U, // FDIV_ZPmZ_H + 302027705U, // FDIV_ZPmZ_S + 2216211385U, // FDIVv2f32 + 2216735673U, // FDIVv2f64 + 69776313U, // FDIVv4f16 + 70300601U, // FDIVv4f32 + 2218308537U, // FDIVv8f16 + 838881376U, // FDUP_ZI_D + 9465952U, // FDUP_ZI_H + 838897760U, // FDUP_ZI_S + 2348827371U, // FEXPA_ZZ_D + 608723691U, // FEXPA_ZZ_H + 2415952619U, // FEXPA_ZZ_S + 2248200909U, // FJCVTZS + 100714511U, // FMADDDrrr + 100714511U, // FMADDHrrr + 100714511U, // FMADDSrrr + 302008208U, // FMAD_ZPmZZ_D + 2186307472U, // FMAD_ZPmZZ_H + 302024592U, // FMAD_ZPmZZ_S + 100717911U, // FMAXDrr + 100717911U, // FMAXHrr + 100716219U, // FMAXNMDrr + 100716219U, // FMAXNMHrr + 2216210455U, // FMAXNMPv2f32 + 2216734743U, // FMAXNMPv2f64 + 2214645783U, // FMAXNMPv2i16p + 67162135U, // FMAXNMPv2i32p + 2214645783U, // FMAXNMPv2i64p + 69775383U, // FMAXNMPv4f16 + 70299671U, // FMAXNMPv4f32 + 2218307607U, // FMAXNMPv8f16 + 100716219U, // FMAXNMSrr + 302044132U, // FMAXNMV_VPZ_D + 302044132U, // FMAXNMV_VPZ_H + 302044132U, // FMAXNMV_VPZ_S + 67163108U, // FMAXNMVv4i16v + 2214646756U, // FMAXNMVv4i32v + 67163108U, // FMAXNMVv8i16v + 302010043U, // FMAXNM_ZPmI_D + 2186309307U, // FMAXNM_ZPmI_H + 302026427U, // FMAXNM_ZPmI_S + 302010043U, // FMAXNM_ZPmZ_D + 2186309307U, // FMAXNM_ZPmZ_H + 302026427U, // FMAXNM_ZPmZ_S + 2216210107U, // FMAXNMv2f32 + 2216734395U, // FMAXNMv2f64 + 69775035U, // FMAXNMv4f16 + 70299323U, // FMAXNMv4f32 + 2218307259U, // FMAXNMv8f16 + 2216210546U, // FMAXPv2f32 + 2216734834U, // FMAXPv2f64 + 2214645874U, // FMAXPv2i16p + 67162226U, // FMAXPv2i32p + 2214645874U, // FMAXPv2i64p + 69775474U, // FMAXPv4f16 + 70299762U, // FMAXPv4f32 + 2218307698U, // FMAXPv8f16 + 100717911U, // FMAXSrr + 302044193U, // FMAXV_VPZ_D + 302044193U, // FMAXV_VPZ_H + 302044193U, // FMAXV_VPZ_S + 67163169U, // FMAXVv4i16v + 2214646817U, // FMAXVv4i32v + 67163169U, // FMAXVv8i16v + 302011735U, // FMAX_ZPmI_D + 2186310999U, // FMAX_ZPmI_H + 302028119U, // FMAX_ZPmI_S + 302011735U, // FMAX_ZPmZ_D + 2186310999U, // FMAX_ZPmZ_H + 302028119U, // FMAX_ZPmZ_S + 2216211799U, // FMAXv2f32 + 2216736087U, // FMAXv2f64 + 69776727U, // FMAXv4f16 + 70301015U, // FMAXv4f32 + 2218308951U, // FMAXv8f16 + 100716264U, // FMINDrr + 100716264U, // FMINHrr + 100716211U, // FMINNMDrr + 100716211U, // FMINNMHrr + 2216210446U, // FMINNMPv2f32 + 2216734734U, // FMINNMPv2f64 + 2214645774U, // FMINNMPv2i16p + 67162126U, // FMINNMPv2i32p + 2214645774U, // FMINNMPv2i64p + 69775374U, // FMINNMPv4f16 + 70299662U, // FMINNMPv4f32 + 2218307598U, // FMINNMPv8f16 + 100716211U, // FMINNMSrr + 302044123U, // FMINNMV_VPZ_D + 302044123U, // FMINNMV_VPZ_H + 302044123U, // FMINNMV_VPZ_S + 67163099U, // FMINNMVv4i16v + 2214646747U, // FMINNMVv4i32v + 67163099U, // FMINNMVv8i16v + 302010035U, // FMINNM_ZPmI_D + 2186309299U, // FMINNM_ZPmI_H + 302026419U, // FMINNM_ZPmI_S + 302010035U, // FMINNM_ZPmZ_D + 2186309299U, // FMINNM_ZPmZ_H + 302026419U, // FMINNM_ZPmZ_S + 2216210099U, // FMINNMv2f32 + 2216734387U, // FMINNMv2f64 + 69775027U, // FMINNMv4f16 + 70299315U, // FMINNMv4f32 + 2218307251U, // FMINNMv8f16 + 2216210470U, // FMINPv2f32 + 2216734758U, // FMINPv2f64 + 2214645798U, // FMINPv2i16p + 67162150U, // FMINPv2i32p + 2214645798U, // FMINPv2i64p + 69775398U, // FMINPv4f16 + 70299686U, // FMINPv4f32 + 2218307622U, // FMINPv8f16 + 100716264U, // FMINSrr + 302044141U, // FMINV_VPZ_D + 302044141U, // FMINV_VPZ_H + 302044141U, // FMINV_VPZ_S + 67163117U, // FMINVv4i16v + 2214646765U, // FMINVv4i32v + 67163117U, // FMINVv8i16v + 302010088U, // FMIN_ZPmI_D + 2186309352U, // FMIN_ZPmI_H + 302026472U, // FMIN_ZPmI_S + 302010088U, // FMIN_ZPmZ_D + 2186309352U, // FMIN_ZPmZ_H + 302026472U, // FMIN_ZPmZ_S + 2216210152U, // FMINv2f32 + 2216734440U, // FMINv2f64 + 69775080U, // FMINv4f16 + 70299368U, // FMINv4f32 + 2218307304U, // FMINv8f16 + 302006968U, // FMLA_ZPmZZ_D + 2186306232U, // FMLA_ZPmZZ_H + 302023352U, // FMLA_ZPmZZ_S + 3019915960U, // FMLA_ZZZI_D + 612393656U, // FMLA_ZZZI_H + 2952823480U, // FMLA_ZZZI_S + 369189560U, // FMLAv1i16_indexed + 369189560U, // FMLAv1i32_indexed + 369189560U, // FMLAv1i64_indexed + 2283332280U, // FMLAv2f32 + 2283856568U, // FMLAv2f64 + 2283332280U, // FMLAv2i32_indexed + 2283856568U, // FMLAv2i64_indexed + 136897208U, // FMLAv4f16 + 137421496U, // FMLAv4f32 + 136897208U, // FMLAv4i16_indexed + 137421496U, // FMLAv4i32_indexed + 2285429432U, // FMLAv8f16 + 2285429432U, // FMLAv8i16_indexed + 302010962U, // FMLS_ZPmZZ_D + 2186310226U, // FMLS_ZPmZZ_H + 302027346U, // FMLS_ZPmZZ_S + 3019919954U, // FMLS_ZZZI_D + 612397650U, // FMLS_ZZZI_H + 2952827474U, // FMLS_ZZZI_S + 369193554U, // FMLSv1i16_indexed + 369193554U, // FMLSv1i32_indexed + 369193554U, // FMLSv1i64_indexed + 2283336274U, // FMLSv2f32 + 2283860562U, // FMLSv2f64 + 2283336274U, // FMLSv2i32_indexed + 2283860562U, // FMLSv2i64_indexed + 136901202U, // FMLSv4f16 + 137425490U, // FMLSv4f32 + 136901202U, // FMLSv4i16_indexed + 137425490U, // FMLSv4i32_indexed + 2285433426U, // FMLSv8f16 + 2285433426U, // FMLSv8i16_indexed + 0U, // FMOVD0 + 67163145U, // FMOVDXHighr + 2248201225U, // FMOVDXr + 838915081U, // FMOVDi + 2248201225U, // FMOVDr + 0U, // FMOVH0 + 2248201225U, // FMOVHWr + 2248201225U, // FMOVHXr + 838915081U, // FMOVHi + 2248201225U, // FMOVHr + 0U, // FMOVS0 + 2248201225U, // FMOVSWr + 838915081U, // FMOVSi + 2248201225U, // FMOVSr + 2248201225U, // FMOVWHr + 2248201225U, // FMOVWSr + 2258154505U, // FMOVXDHighr + 2248201225U, // FMOVXDr + 2248201225U, // FMOVXHr + 840479753U, // FMOVv2f32_ns + 841004041U, // FMOVv2f64_ns + 841528329U, // FMOVv4f16_ns + 842052617U, // FMOVv4f32_ns + 842576905U, // FMOVv8f16_ns + 302007876U, // FMSB_ZPmZZ_D + 2186307140U, // FMSB_ZPmZZ_H + 302024260U, // FMSB_ZPmZZ_S + 100714165U, // FMSUBDrrr + 100714165U, // FMSUBHrrr + 100714165U, // FMSUBSrrr + 100716128U, // FMULDrr + 100716128U, // FMULHrr + 100716128U, // FMULSrr + 100717970U, // FMULX16 + 100717970U, // FMULX32 + 100717970U, // FMULX64 + 302011794U, // FMULX_ZPmZ_D + 2186311058U, // FMULX_ZPmZ_H + 302028178U, // FMULX_ZPmZ_S + 100717970U, // FMULXv1i16_indexed + 100717970U, // FMULXv1i32_indexed + 100717970U, // FMULXv1i64_indexed + 2216211858U, // FMULXv2f32 + 2216736146U, // FMULXv2f64 + 2216211858U, // FMULXv2i32_indexed + 2216736146U, // FMULXv2i64_indexed + 69776786U, // FMULXv4f16 + 70301074U, // FMULXv4f32 + 69776786U, // FMULXv4i16_indexed + 70301074U, // FMULXv4i32_indexed + 2218309010U, // FMULXv8f16 + 2218309010U, // FMULXv8i16_indexed + 302009952U, // FMUL_ZPmI_D + 2186309216U, // FMUL_ZPmI_H + 302026336U, // FMUL_ZPmI_S + 302009952U, // FMUL_ZPmZ_D + 2186309216U, // FMUL_ZPmZ_H + 302026336U, // FMUL_ZPmZ_S + 201346656U, // FMUL_ZZZI_D + 2387111520U, // FMUL_ZZZI_H + 268471904U, // FMUL_ZZZI_S + 201346656U, // FMUL_ZZZ_D + 2387111520U, // FMUL_ZZZ_H + 268471904U, // FMUL_ZZZ_S + 100716128U, // FMULv1i16_indexed + 100716128U, // FMULv1i32_indexed + 100716128U, // FMULv1i64_indexed + 2216210016U, // FMULv2f32 + 2216734304U, // FMULv2f64 + 2216210016U, // FMULv2i32_indexed + 2216734304U, // FMULv2i64_indexed + 69774944U, // FMULv4f16 + 70299232U, // FMULv4f32 + 69774944U, // FMULv4i16_indexed + 70299232U, // FMULv4i32_indexed + 2218307168U, // FMULv8f16 + 2218307168U, // FMULv8i16_indexed + 2248198419U, // FNEGDr + 2248198419U, // FNEGHr + 2248198419U, // FNEGSr + 18707U, // FNEG_ZPmZ_D + 2181589267U, // FNEG_ZPmZ_H + 35091U, // FNEG_ZPmZ_S + 68725011U, // FNEGv2f32 + 2216732947U, // FNEGv2f64 + 69773587U, // FNEGv4f16 + 2217781523U, // FNEGv4f32 + 70822163U, // FNEGv8f16 + 100714518U, // FNMADDDrrr + 100714518U, // FNMADDHrrr + 100714518U, // FNMADDSrrr + 302008214U, // FNMAD_ZPmZZ_D + 2186307478U, // FNMAD_ZPmZZ_H + 302024598U, // FNMAD_ZPmZZ_S + 302006974U, // FNMLA_ZPmZZ_D + 2186306238U, // FNMLA_ZPmZZ_H + 302023358U, // FNMLA_ZPmZZ_S + 302010968U, // FNMLS_ZPmZZ_D + 2186310232U, // FNMLS_ZPmZZ_H + 302027352U, // FNMLS_ZPmZZ_S + 302007882U, // FNMSB_ZPmZZ_D + 2186307146U, // FNMSB_ZPmZZ_H + 302024266U, // FNMSB_ZPmZZ_S + 100714172U, // FNMSUBDrrr + 100714172U, // FNMSUBHrrr + 100714172U, // FNMSUBSrrr + 100716134U, // FNMULDrr + 100716134U, // FNMULHrr + 100716134U, // FNMULSrr + 2348828852U, // FRECPE_ZZ_D + 608725172U, // FRECPE_ZZ_H + 2415954100U, // FRECPE_ZZ_S + 2248198324U, // FRECPEv1f16 + 2248198324U, // FRECPEv1i32 + 2248198324U, // FRECPEv1i64 + 68724916U, // FRECPEv2f32 + 2216732852U, // FRECPEv2f64 + 69773492U, // FRECPEv4f16 + 2217781428U, // FRECPEv4f32 + 70822068U, // FRECPEv8f16 + 100717192U, // FRECPS16 + 100717192U, // FRECPS32 + 100717192U, // FRECPS64 + 201347720U, // FRECPS_ZZZ_D + 2387112584U, // FRECPS_ZZZ_H + 268472968U, // FRECPS_ZZZ_S + 2216211080U, // FRECPSv2f32 + 2216735368U, // FRECPSv2f64 + 69776008U, // FRECPSv4f16 + 70300296U, // FRECPSv4f32 + 2218308232U, // FRECPSv8f16 + 21913U, // FRECPX_ZPmZ_D + 2181592473U, // FRECPX_ZPmZ_H + 38297U, // FRECPX_ZPmZ_S + 2248201625U, // FRECPXv1f16 + 2248201625U, // FRECPXv1i32 + 2248201625U, // FRECPXv1i64 + 2248196906U, // FRINTADr + 2248196906U, // FRINTAHr + 2248196906U, // FRINTASr + 17194U, // FRINTA_ZPmZ_D + 2181587754U, // FRINTA_ZPmZ_H + 33578U, // FRINTA_ZPmZ_S + 68723498U, // FRINTAv2f32 + 2216731434U, // FRINTAv2f64 + 69772074U, // FRINTAv4f16 + 2217780010U, // FRINTAv4f32 + 70820650U, // FRINTAv8f16 + 2248199305U, // FRINTIDr + 2248199305U, // FRINTIHr + 2248199305U, // FRINTISr + 19593U, // FRINTI_ZPmZ_D + 2181590153U, // FRINTI_ZPmZ_H + 35977U, // FRINTI_ZPmZ_S + 68725897U, // FRINTIv2f32 + 2216733833U, // FRINTIv2f64 + 69774473U, // FRINTIv4f16 + 2217782409U, // FRINTIv4f32 + 70823049U, // FRINTIv8f16 + 2248199881U, // FRINTMDr + 2248199881U, // FRINTMHr + 2248199881U, // FRINTMSr + 20169U, // FRINTM_ZPmZ_D + 2181590729U, // FRINTM_ZPmZ_H + 36553U, // FRINTM_ZPmZ_S + 68726473U, // FRINTMv2f32 + 2216734409U, // FRINTMv2f64 + 69775049U, // FRINTMv4f16 + 2217782985U, // FRINTMv4f32 + 70823625U, // FRINTMv8f16 + 2248199990U, // FRINTNDr + 2248199990U, // FRINTNHr + 2248199990U, // FRINTNSr + 20278U, // FRINTN_ZPmZ_D + 2181590838U, // FRINTN_ZPmZ_H + 36662U, // FRINTN_ZPmZ_S + 68726582U, // FRINTNv2f32 + 2216734518U, // FRINTNv2f64 + 69775158U, // FRINTNv4f16 + 2217783094U, // FRINTNv4f32 + 70823734U, // FRINTNv8f16 + 2248200275U, // FRINTPDr + 2248200275U, // FRINTPHr + 2248200275U, // FRINTPSr + 20563U, // FRINTP_ZPmZ_D + 2181591123U, // FRINTP_ZPmZ_H + 36947U, // FRINTP_ZPmZ_S + 68726867U, // FRINTPv2f32 + 2216734803U, // FRINTPv2f64 + 69775443U, // FRINTPv4f16 + 2217783379U, // FRINTPv4f32 + 70824019U, // FRINTPv8f16 + 2248201633U, // FRINTXDr + 2248201633U, // FRINTXHr + 2248201633U, // FRINTXSr + 21921U, // FRINTX_ZPmZ_D + 2181592481U, // FRINTX_ZPmZ_H + 38305U, // FRINTX_ZPmZ_S + 68728225U, // FRINTXv2f32 + 2216736161U, // FRINTXv2f64 + 69776801U, // FRINTXv4f16 + 2217784737U, // FRINTXv4f32 + 70825377U, // FRINTXv8f16 + 2248201713U, // FRINTZDr + 2248201713U, // FRINTZHr + 2248201713U, // FRINTZSr + 22001U, // FRINTZ_ZPmZ_D + 2181592561U, // FRINTZ_ZPmZ_H + 38385U, // FRINTZ_ZPmZ_S + 68728305U, // FRINTZv2f32 + 2216736241U, // FRINTZv2f64 + 69776881U, // FRINTZv4f16 + 2217784817U, // FRINTZv4f32 + 70825457U, // FRINTZv8f16 + 2348828897U, // FRSQRTE_ZZ_D + 608725217U, // FRSQRTE_ZZ_H + 2415954145U, // FRSQRTE_ZZ_S + 2248198369U, // FRSQRTEv1f16 + 2248198369U, // FRSQRTEv1i32 + 2248198369U, // FRSQRTEv1i64 + 68724961U, // FRSQRTEv2f32 + 2216732897U, // FRSQRTEv2f64 + 69773537U, // FRSQRTEv4f16 + 2217781473U, // FRSQRTEv4f32 + 70822113U, // FRSQRTEv8f16 + 100717239U, // FRSQRTS16 + 100717239U, // FRSQRTS32 + 100717239U, // FRSQRTS64 + 201347767U, // FRSQRTS_ZZZ_D + 2387112631U, // FRSQRTS_ZZZ_H + 268473015U, // FRSQRTS_ZZZ_S + 2216211127U, // FRSQRTSv2f32 + 2216735415U, // FRSQRTSv2f64 + 69776055U, // FRSQRTSv4f16 + 70300343U, // FRSQRTSv4f32 + 2218308279U, // FRSQRTSv8f16 + 302008446U, // FSCALE_ZPmZ_D + 2186307710U, // FSCALE_ZPmZ_H + 302024830U, // FSCALE_ZPmZ_S + 2248201023U, // FSQRTDr + 2248201023U, // FSQRTHr + 2248201023U, // FSQRTSr + 21311U, // FSQRT_ZPmZ_D + 2181591871U, // FSQRT_ZPmZ_H + 37695U, // FSQRT_ZPmZ_S + 68727615U, // FSQRTv2f32 + 2216735551U, // FSQRTv2f64 + 69776191U, // FSQRTv4f16 + 2217784127U, // FSQRTv4f32 + 70824767U, // FSQRTv8f16 + 100714145U, // FSUBDrr + 100714145U, // FSUBHrr + 302010587U, // FSUBR_ZPmI_D + 2186309851U, // FSUBR_ZPmI_H + 302026971U, // FSUBR_ZPmI_S + 302010587U, // FSUBR_ZPmZ_D + 2186309851U, // FSUBR_ZPmZ_H + 302026971U, // FSUBR_ZPmZ_S + 100714145U, // FSUBSrr + 302007969U, // FSUB_ZPmI_D + 2186307233U, // FSUB_ZPmI_H + 302024353U, // FSUB_ZPmI_S + 302007969U, // FSUB_ZPmZ_D + 2186307233U, // FSUB_ZPmZ_H + 302024353U, // FSUB_ZPmZ_S + 201344673U, // FSUB_ZZZ_D + 2387109537U, // FSUB_ZZZ_H + 268469921U, // FSUB_ZZZ_S + 2216208033U, // FSUBv2f32 + 2216732321U, // FSUBv2f64 + 69772961U, // FSUBv4f16 + 70297249U, // FSUBv4f32 + 2218305185U, // FSUBv8f16 + 201344925U, // FTMAD_ZZI_D + 2387109789U, // FTMAD_ZZI_H + 268470173U, // FTMAD_ZZI_S + 201346675U, // FTSMUL_ZZZ_D + 2387111539U, // FTSMUL_ZZZ_H + 268471923U, // FTSMUL_ZZZ_S + 201346439U, // FTSSEL_ZZZ_D + 2387111303U, // FTSSEL_ZZZ_H + 268471687U, // FTSSEL_ZZZ_S + 883032940U, // GLD1B_D_IMM_REAL + 379716460U, // GLD1B_D_REAL + 379716460U, // GLD1B_D_SXTW_REAL + 379716460U, // GLD1B_D_UXTW_REAL + 815932268U, // GLD1B_S_IMM_REAL + 379724652U, // GLD1B_S_SXTW_REAL + 379724652U, // GLD1B_S_UXTW_REAL + 883033920U, // GLD1D_IMM_REAL + 379717440U, // GLD1D_REAL + 379717440U, // GLD1D_SCALED_REAL + 379717440U, // GLD1D_SXTW_REAL + 379717440U, // GLD1D_SXTW_SCALED_REAL + 379717440U, // GLD1D_UXTW_REAL + 379717440U, // GLD1D_UXTW_SCALED_REAL + 3030518062U, // GLD1H_D_IMM_REAL + 379717934U, // GLD1H_D_REAL + 379717934U, // GLD1H_D_SCALED_REAL + 379717934U, // GLD1H_D_SXTW_REAL + 379717934U, // GLD1H_D_SXTW_SCALED_REAL + 379717934U, // GLD1H_D_UXTW_REAL + 379717934U, // GLD1H_D_UXTW_SCALED_REAL + 2963417390U, // GLD1H_S_IMM_REAL + 379726126U, // GLD1H_S_SXTW_REAL + 379726126U, // GLD1H_S_SXTW_SCALED_REAL + 379726126U, // GLD1H_S_UXTW_REAL + 379726126U, // GLD1H_S_UXTW_SCALED_REAL + 883033627U, // GLD1SB_D_IMM_REAL + 379717147U, // GLD1SB_D_REAL + 379717147U, // GLD1SB_D_SXTW_REAL + 379717147U, // GLD1SB_D_UXTW_REAL + 815932955U, // GLD1SB_S_IMM_REAL + 379725339U, // GLD1SB_S_SXTW_REAL + 379725339U, // GLD1SB_S_UXTW_REAL + 3030518726U, // GLD1SH_D_IMM_REAL + 379718598U, // GLD1SH_D_REAL + 379718598U, // GLD1SH_D_SCALED_REAL + 379718598U, // GLD1SH_D_SXTW_REAL + 379718598U, // GLD1SH_D_SXTW_SCALED_REAL + 379718598U, // GLD1SH_D_UXTW_REAL + 379718598U, // GLD1SH_D_UXTW_SCALED_REAL + 2963418054U, // GLD1SH_S_IMM_REAL + 379726790U, // GLD1SH_S_SXTW_REAL + 379726790U, // GLD1SH_S_SXTW_SCALED_REAL + 379726790U, // GLD1SH_S_UXTW_REAL + 379726790U, // GLD1SH_S_UXTW_SCALED_REAL + 883037416U, // GLD1SW_D_IMM_REAL + 379720936U, // GLD1SW_D_REAL + 379720936U, // GLD1SW_D_SCALED_REAL + 379720936U, // GLD1SW_D_SXTW_REAL + 379720936U, // GLD1SW_D_SXTW_SCALED_REAL + 379720936U, // GLD1SW_D_UXTW_REAL + 379720936U, // GLD1SW_D_UXTW_SCALED_REAL + 883037238U, // GLD1W_D_IMM_REAL + 379720758U, // GLD1W_D_REAL + 379720758U, // GLD1W_D_SCALED_REAL + 379720758U, // GLD1W_D_SXTW_REAL + 379720758U, // GLD1W_D_SXTW_SCALED_REAL + 379720758U, // GLD1W_D_UXTW_REAL + 379720758U, // GLD1W_D_UXTW_SCALED_REAL + 815936566U, // GLD1W_IMM_REAL + 379728950U, // GLD1W_SXTW_REAL + 379728950U, // GLD1W_SXTW_SCALED_REAL + 379728950U, // GLD1W_UXTW_REAL + 379728950U, // GLD1W_UXTW_SCALED_REAL + 883032946U, // GLDFF1B_D_IMM_REAL + 379716466U, // GLDFF1B_D_REAL + 379716466U, // GLDFF1B_D_SXTW_REAL + 379716466U, // GLDFF1B_D_UXTW_REAL + 815932274U, // GLDFF1B_S_IMM_REAL + 379724658U, // GLDFF1B_S_SXTW_REAL + 379724658U, // GLDFF1B_S_UXTW_REAL + 883033926U, // GLDFF1D_IMM_REAL + 379717446U, // GLDFF1D_REAL + 379717446U, // GLDFF1D_SCALED_REAL + 379717446U, // GLDFF1D_SXTW_REAL + 379717446U, // GLDFF1D_SXTW_SCALED_REAL + 379717446U, // GLDFF1D_UXTW_REAL + 379717446U, // GLDFF1D_UXTW_SCALED_REAL + 3030518068U, // GLDFF1H_D_IMM_REAL + 379717940U, // GLDFF1H_D_REAL + 379717940U, // GLDFF1H_D_SCALED_REAL + 379717940U, // GLDFF1H_D_SXTW_REAL + 379717940U, // GLDFF1H_D_SXTW_SCALED_REAL + 379717940U, // GLDFF1H_D_UXTW_REAL + 379717940U, // GLDFF1H_D_UXTW_SCALED_REAL + 2963417396U, // GLDFF1H_S_IMM_REAL + 379726132U, // GLDFF1H_S_SXTW_REAL + 379726132U, // GLDFF1H_S_SXTW_SCALED_REAL + 379726132U, // GLDFF1H_S_UXTW_REAL + 379726132U, // GLDFF1H_S_UXTW_SCALED_REAL + 883033634U, // GLDFF1SB_D_IMM_REAL + 379717154U, // GLDFF1SB_D_REAL + 379717154U, // GLDFF1SB_D_SXTW_REAL + 379717154U, // GLDFF1SB_D_UXTW_REAL + 815932962U, // GLDFF1SB_S_IMM_REAL + 379725346U, // GLDFF1SB_S_SXTW_REAL + 379725346U, // GLDFF1SB_S_UXTW_REAL + 3030518733U, // GLDFF1SH_D_IMM_REAL + 379718605U, // GLDFF1SH_D_REAL + 379718605U, // GLDFF1SH_D_SCALED_REAL + 379718605U, // GLDFF1SH_D_SXTW_REAL + 379718605U, // GLDFF1SH_D_SXTW_SCALED_REAL + 379718605U, // GLDFF1SH_D_UXTW_REAL + 379718605U, // GLDFF1SH_D_UXTW_SCALED_REAL + 2963418061U, // GLDFF1SH_S_IMM_REAL + 379726797U, // GLDFF1SH_S_SXTW_REAL + 379726797U, // GLDFF1SH_S_SXTW_SCALED_REAL + 379726797U, // GLDFF1SH_S_UXTW_REAL + 379726797U, // GLDFF1SH_S_UXTW_SCALED_REAL + 883037423U, // GLDFF1SW_D_IMM_REAL + 379720943U, // GLDFF1SW_D_REAL + 379720943U, // GLDFF1SW_D_SCALED_REAL + 379720943U, // GLDFF1SW_D_SXTW_REAL + 379720943U, // GLDFF1SW_D_SXTW_SCALED_REAL + 379720943U, // GLDFF1SW_D_UXTW_REAL + 379720943U, // GLDFF1SW_D_UXTW_SCALED_REAL + 883037244U, // GLDFF1W_D_IMM_REAL + 379720764U, // GLDFF1W_D_REAL + 379720764U, // GLDFF1W_D_SCALED_REAL + 379720764U, // GLDFF1W_D_SXTW_REAL + 379720764U, // GLDFF1W_D_SXTW_SCALED_REAL + 379720764U, // GLDFF1W_D_UXTW_REAL + 379720764U, // GLDFF1W_D_UXTW_SCALED_REAL + 815936572U, // GLDFF1W_IMM_REAL + 379728956U, // GLDFF1W_SXTW_REAL + 379728956U, // GLDFF1W_SXTW_SCALED_REAL + 379728956U, // GLDFF1W_UXTW_REAL + 379728956U, // GLDFF1W_UXTW_SCALED_REAL + 152359U, // HINT + 78607U, // HLT + 75574U, // HVC + 536921183U, // INCB_XPiI + 536922063U, // INCD_XPiI + 536889295U, // INCD_ZPiI + 536922647U, // INCH_XPiI + 6842903U, // INCH_ZPiI + 2315308999U, // INCP_XP_B + 2348863431U, // INCP_XP_D + 2717962183U, // INCP_XP_H + 2415972295U, // INCP_XP_S + 2147504071U, // INCP_ZP_D + 604532679U, // INCP_ZP_H + 2147520455U, // INCP_ZP_S + 536925367U, // INCW_XPiI + 536908983U, // INCW_ZPiI + 100676987U, // INDEX_II_B + 100685179U, // INDEX_II_D + 242775419U, // INDEX_II_H + 100701563U, // INDEX_II_S + 100676987U, // INDEX_IR_B + 100685179U, // INDEX_IR_D + 242775419U, // INDEX_IR_H + 100701563U, // INDEX_IR_S + 100676987U, // INDEX_RI_B + 100685179U, // INDEX_RI_D + 242775419U, // INDEX_RI_H + 100701563U, // INDEX_RI_S + 100676987U, // INDEX_RR_B + 100685179U, // INDEX_RR_D + 242775419U, // INDEX_RR_H + 100701563U, // INDEX_RR_S + 2516595051U, // INSR_ZR_B + 2516603243U, // INSR_ZR_D + 615018859U, // INSR_ZR_H + 2516619627U, // INSR_ZR_S + 2516595051U, // INSR_ZV_B + 2516603243U, // INSR_ZV_D + 615018859U, // INSR_ZV_H + 2516619627U, // INSR_ZV_S + 3065049710U, // INSvi16gpr + 951120494U, // INSvi16lane + 3065573998U, // INSvi32gpr + 3099128430U, // INSvi32lane + 3063476846U, // INSvi64gpr + 949547630U, // INSvi64lane + 3066098286U, // INSvi8gpr + 3099652718U, // INSvi8lane + 116287U, // ISB + 302039859U, // LASTA_RPZ_B + 302039859U, // LASTA_RPZ_D + 302039859U, // LASTA_RPZ_H + 302039859U, // LASTA_RPZ_S + 302039859U, // LASTA_VPZ_B + 302039859U, // LASTA_VPZ_D + 302039859U, // LASTA_VPZ_H + 302039859U, // LASTA_VPZ_S + 302040718U, // LASTB_RPZ_B + 302040718U, // LASTB_RPZ_D + 302040718U, // LASTB_RPZ_H + 302040718U, // LASTB_RPZ_S + 302040718U, // LASTB_VPZ_B + 302040718U, // LASTB_VPZ_D + 302040718U, // LASTB_VPZ_H + 302040718U, // LASTB_VPZ_S + 379741036U, // LD1B + 379716460U, // LD1B_D + 379716460U, // LD1B_D_IMM_REAL + 379749228U, // LD1B_H + 379749228U, // LD1B_H_IMM_REAL + 379741036U, // LD1B_IMM_REAL + 379724652U, // LD1B_S + 379724652U, // LD1B_S_IMM_REAL + 379717440U, // LD1D + 379717440U, // LD1D_IMM_REAL + 172064U, // LD1Fourv16b + 13287456U, // LD1Fourv16b_POST + 188448U, // LD1Fourv1d + 13828128U, // LD1Fourv1d_POST + 204832U, // LD1Fourv2d + 13320224U, // LD1Fourv2d_POST + 221216U, // LD1Fourv2s + 13860896U, // LD1Fourv2s_POST + 237600U, // LD1Fourv4h + 13877280U, // LD1Fourv4h_POST + 253984U, // LD1Fourv4s + 13369376U, // LD1Fourv4s_POST + 270368U, // LD1Fourv8b + 13910048U, // LD1Fourv8b_POST + 286752U, // LD1Fourv8h + 13402144U, // LD1Fourv8h_POST + 379750702U, // LD1H + 379717934U, // LD1H_D + 379717934U, // LD1H_D_IMM_REAL + 379750702U, // LD1H_IMM_REAL + 379726126U, // LD1H_S + 379726126U, // LD1H_S_IMM_REAL + 172064U, // LD1Onev16b + 14336032U, // LD1Onev16b_POST + 188448U, // LD1Onev1d + 14876704U, // LD1Onev1d_POST + 204832U, // LD1Onev2d + 14368800U, // LD1Onev2d_POST + 221216U, // LD1Onev2s + 14909472U, // LD1Onev2s_POST + 237600U, // LD1Onev4h + 14925856U, // LD1Onev4h_POST + 253984U, // LD1Onev4s + 14417952U, // LD1Onev4s_POST + 270368U, // LD1Onev8b + 14958624U, // LD1Onev8b_POST + 286752U, // LD1Onev8h + 14450720U, // LD1Onev8h_POST + 379716999U, // LD1RB_D_IMM + 379749767U, // LD1RB_H_IMM + 379741575U, // LD1RB_IMM + 379725191U, // LD1RB_S_IMM + 379717698U, // LD1RD_IMM + 379718450U, // LD1RH_D_IMM + 379751218U, // LD1RH_IMM + 379726642U, // LD1RH_S_IMM + 379741567U, // LD1RQ_B + 379741567U, // LD1RQ_B_IMM + 379717690U, // LD1RQ_D + 379717690U, // LD1RQ_D_IMM + 379751210U, // LD1RQ_H + 379751210U, // LD1RQ_H_IMM + 379729113U, // LD1RQ_W + 379729113U, // LD1RQ_W_IMM + 379717201U, // LD1RSB_D_IMM + 379749969U, // LD1RSB_H_IMM + 379725393U, // LD1RSB_S_IMM + 379718639U, // LD1RSH_D_IMM + 379726831U, // LD1RSH_S_IMM + 379720968U, // LD1RSW_IMM + 379720929U, // LD1RW_D_IMM + 379729121U, // LD1RW_IMM + 176305U, // LD1Rv16b + 15388849U, // LD1Rv16b_POST + 192689U, // LD1Rv1d + 14880945U, // LD1Rv1d_POST + 209073U, // LD1Rv2d + 14897329U, // LD1Rv2d_POST + 225457U, // LD1Rv2s + 15962289U, // LD1Rv2s_POST + 241841U, // LD1Rv4h + 16502961U, // LD1Rv4h_POST + 258225U, // LD1Rv4s + 15995057U, // LD1Rv4s_POST + 274609U, // LD1Rv8b + 15487153U, // LD1Rv8b_POST + 290993U, // LD1Rv8h + 16552113U, // LD1Rv8h_POST + 379717147U, // LD1SB_D + 379717147U, // LD1SB_D_IMM_REAL + 379749915U, // LD1SB_H + 379749915U, // LD1SB_H_IMM_REAL + 379725339U, // LD1SB_S + 379725339U, // LD1SB_S_IMM_REAL + 379718598U, // LD1SH_D + 379718598U, // LD1SH_D_IMM_REAL + 379726790U, // LD1SH_S + 379726790U, // LD1SH_S_IMM_REAL + 379720936U, // LD1SW_D + 379720936U, // LD1SW_D_IMM_REAL + 172064U, // LD1Threev16b + 16957472U, // LD1Threev16b_POST + 188448U, // LD1Threev1d + 17498144U, // LD1Threev1d_POST + 204832U, // LD1Threev2d + 16990240U, // LD1Threev2d_POST + 221216U, // LD1Threev2s + 17530912U, // LD1Threev2s_POST + 237600U, // LD1Threev4h + 17547296U, // LD1Threev4h_POST + 253984U, // LD1Threev4s + 17039392U, // LD1Threev4s_POST + 270368U, // LD1Threev8b + 17580064U, // LD1Threev8b_POST + 286752U, // LD1Threev8h + 17072160U, // LD1Threev8h_POST + 172064U, // LD1Twov16b + 13811744U, // LD1Twov16b_POST + 188448U, // LD1Twov1d + 14352416U, // LD1Twov1d_POST + 204832U, // LD1Twov2d + 13844512U, // LD1Twov2d_POST + 221216U, // LD1Twov2s + 14385184U, // LD1Twov2s_POST + 237600U, // LD1Twov4h + 14401568U, // LD1Twov4h_POST + 253984U, // LD1Twov4s + 13893664U, // LD1Twov4s_POST + 270368U, // LD1Twov8b + 14434336U, // LD1Twov8b_POST + 286752U, // LD1Twov8h + 13926432U, // LD1Twov8h_POST + 379728950U, // LD1W + 379720758U, // LD1W_D + 379720758U, // LD1W_D_IMM_REAL + 379728950U, // LD1W_IMM_REAL + 18128928U, // LD1i16 + 18661408U, // LD1i16_POST + 18145312U, // LD1i32 + 19202080U, // LD1i32_POST + 18161696U, // LD1i64 + 19742752U, // LD1i64_POST + 18178080U, // LD1i8 + 20283424U, // LD1i8_POST + 379741097U, // LD2B + 379741097U, // LD2B_IMM + 379717484U, // LD2D + 379717484U, // LD2D_IMM + 379750763U, // LD2H + 379750763U, // LD2H_IMM + 176311U, // LD2Rv16b + 16437431U, // LD2Rv16b_POST + 192695U, // LD2Rv1d + 14356663U, // LD2Rv1d_POST + 209079U, // LD2Rv2d + 14373047U, // LD2Rv2d_POST + 225463U, // LD2Rv2s + 14913719U, // LD2Rv2s_POST + 241847U, // LD2Rv4h + 15978679U, // LD2Rv4h_POST + 258231U, // LD2Rv4s + 14946487U, // LD2Rv4s_POST + 274615U, // LD2Rv8b + 16535735U, // LD2Rv8b_POST + 290999U, // LD2Rv8h + 16027831U, // LD2Rv8h_POST + 172162U, // LD2Twov16b + 13811842U, // LD2Twov16b_POST + 204930U, // LD2Twov2d + 13844610U, // LD2Twov2d_POST + 221314U, // LD2Twov2s + 14385282U, // LD2Twov2s_POST + 237698U, // LD2Twov4h + 14401666U, // LD2Twov4h_POST + 254082U, // LD2Twov4s + 13893762U, // LD2Twov4s_POST + 270466U, // LD2Twov8b + 14434434U, // LD2Twov8b_POST + 286850U, // LD2Twov8h + 13926530U, // LD2Twov8h_POST + 379729002U, // LD2W + 379729002U, // LD2W_IMM + 18129026U, // LD2i16 + 19185794U, // LD2i16_POST + 18145410U, // LD2i32 + 19726466U, // LD2i32_POST + 18161794U, // LD2i64 + 20791426U, // LD2i64_POST + 18178178U, // LD2i8 + 18710658U, // LD2i8_POST + 379741118U, // LD3B + 379741118U, // LD3B_IMM + 379717496U, // LD3D + 379717496U, // LD3D_IMM + 379750775U, // LD3H + 379750775U, // LD3H_IMM + 176317U, // LD3Rv16b + 21156029U, // LD3Rv16b_POST + 192701U, // LD3Rv1d + 17502397U, // LD3Rv1d_POST + 209085U, // LD3Rv2d + 17518781U, // LD3Rv2d_POST + 225469U, // LD3Rv2s + 21729469U, // LD3Rv2s_POST + 241853U, // LD3Rv4h + 22270141U, // LD3Rv4h_POST + 258237U, // LD3Rv4s + 21762237U, // LD3Rv4s_POST + 274621U, // LD3Rv8b + 21254333U, // LD3Rv8b_POST + 291005U, // LD3Rv8h + 22319293U, // LD3Rv8h_POST + 172553U, // LD3Threev16b + 16957961U, // LD3Threev16b_POST + 205321U, // LD3Threev2d + 16990729U, // LD3Threev2d_POST + 221705U, // LD3Threev2s + 17531401U, // LD3Threev2s_POST + 238089U, // LD3Threev4h + 17547785U, // LD3Threev4h_POST + 254473U, // LD3Threev4s + 17039881U, // LD3Threev4s_POST + 270857U, // LD3Threev8b + 17580553U, // LD3Threev8b_POST + 287241U, // LD3Threev8h + 17072649U, // LD3Threev8h_POST + 379729014U, // LD3W + 379729014U, // LD3W_IMM + 18129417U, // LD3i16 + 22856201U, // LD3i16_POST + 18145801U, // LD3i32 + 23396873U, // LD3i32_POST + 18162185U, // LD3i64 + 23937545U, // LD3i64_POST + 18178569U, // LD3i8 + 24478217U, // LD3i8_POST + 379741130U, // LD4B + 379741130U, // LD4B_IMM + 379717508U, // LD4D + 379717508U, // LD4D_IMM + 172583U, // LD4Fourv16b + 13287975U, // LD4Fourv16b_POST + 205351U, // LD4Fourv2d + 13320743U, // LD4Fourv2d_POST + 221735U, // LD4Fourv2s + 13861415U, // LD4Fourv2s_POST + 238119U, // LD4Fourv4h + 13877799U, // LD4Fourv4h_POST + 254503U, // LD4Fourv4s + 13369895U, // LD4Fourv4s_POST + 270887U, // LD4Fourv8b + 13910567U, // LD4Fourv8b_POST + 287271U, // LD4Fourv8h + 13402663U, // LD4Fourv8h_POST + 379750787U, // LD4H + 379750787U, // LD4H_IMM + 176323U, // LD4Rv16b + 15913155U, // LD4Rv16b_POST + 192707U, // LD4Rv1d + 13832387U, // LD4Rv1d_POST + 209091U, // LD4Rv2d + 13848771U, // LD4Rv2d_POST + 225475U, // LD4Rv2s + 14389443U, // LD4Rv2s_POST + 241859U, // LD4Rv4h + 14930115U, // LD4Rv4h_POST + 258243U, // LD4Rv4s + 14422211U, // LD4Rv4s_POST + 274627U, // LD4Rv8b + 16011459U, // LD4Rv8b_POST + 291011U, // LD4Rv8h + 14979267U, // LD4Rv8h_POST + 379729026U, // LD4W + 379729026U, // LD4W_IMM + 18129447U, // LD4i16 + 19710503U, // LD4i16_POST + 18145831U, // LD4i32 + 20775463U, // LD4i32_POST + 18162215U, // LD4i64 + 24986151U, // LD4i64_POST + 18178599U, // LD4i8 + 19235367U, // LD4i8_POST + 973169622U, // LDADDAB + 973171096U, // LDADDAH + 973169821U, // LDADDALB + 973171251U, // LDADDALH + 973171888U, // LDADDALW + 973171888U, // LDADDALX + 973169280U, // LDADDAW + 973169280U, // LDADDAX + 973169780U, // LDADDB + 973171237U, // LDADDH + 973169921U, // LDADDLB + 973171351U, // LDADDLH + 973172058U, // LDADDLW + 973172058U, // LDADDLX + 973170660U, // LDADDW + 973170660U, // LDADDX + 2253964738U, // LDAPRB + 2253966189U, // LDAPRH + 2253967684U, // LDAPRW + 2253967684U, // LDAPRX + 106481133U, // LDAPURBi + 106482584U, // LDAPURHi + 106481264U, // LDAPURSBWi + 106481264U, // LDAPURSBXi + 106482702U, // LDAPURSHWi + 106482702U, // LDAPURSHXi + 106485031U, // LDAPURSWi + 106484117U, // LDAPURXi + 106484117U, // LDAPURi + 2253964686U, // LDARB + 2253966137U, // LDARH + 2253967561U, // LDARW + 2253967561U, // LDARX + 2248200299U, // LDAXPW + 2248200299U, // LDAXPX + 2253964797U, // LDAXRB + 2253966248U, // LDAXRH + 2253967800U, // LDAXRW + 2253967800U, // LDAXRX + 973169678U, // LDCLRAB + 973171142U, // LDCLRAH + 973169861U, // LDCLRALB + 973171291U, // LDCLRALH + 973171955U, // LDCLRALW + 973171955U, // LDCLRALX + 973169394U, // LDCLRAW + 973169394U, // LDCLRAX + 973170083U, // LDCLRB + 973171534U, // LDCLRH + 973169957U, // LDCLRLB + 973171387U, // LDCLRLH + 973172249U, // LDCLRLW + 973172249U, // LDCLRLX + 973173017U, // LDCLRW + 973173017U, // LDCLRX + 973169687U, // LDEORAB + 973171151U, // LDEORAH + 973169871U, // LDEORALB + 973171301U, // LDEORALH + 973171964U, // LDEORALW + 973171964U, // LDEORALX + 973169402U, // LDEORAW + 973169402U, // LDEORAX + 973170106U, // LDEORB + 973171557U, // LDEORH + 973169966U, // LDEORLB + 973171396U, // LDEORLH + 973172257U, // LDEORLW + 973172257U, // LDEORLX + 973173043U, // LDEORW + 973173043U, // LDEORX + 379716466U, // LDFF1B_D_REAL + 379749234U, // LDFF1B_H_REAL + 379741042U, // LDFF1B_REAL + 379724658U, // LDFF1B_S_REAL + 379717446U, // LDFF1D_REAL + 379717940U, // LDFF1H_D_REAL + 379750708U, // LDFF1H_REAL + 379726132U, // LDFF1H_S_REAL + 379717154U, // LDFF1SB_D_REAL + 379749922U, // LDFF1SB_H_REAL + 379725346U, // LDFF1SB_S_REAL + 379718605U, // LDFF1SH_D_REAL + 379726797U, // LDFF1SH_S_REAL + 379720943U, // LDFF1SW_D_REAL + 379720764U, // LDFF1W_D_REAL + 379728956U, // LDFF1W_REAL + 2253964693U, // LDLARB + 2253966144U, // LDLARH + 2253967567U, // LDLARW + 2253967567U, // LDLARX + 379716474U, // LDNF1B_D_IMM_REAL + 379749242U, // LDNF1B_H_IMM_REAL + 379741050U, // LDNF1B_IMM_REAL + 379724666U, // LDNF1B_S_IMM_REAL + 379717454U, // LDNF1D_IMM_REAL + 379717948U, // LDNF1H_D_IMM_REAL + 379750716U, // LDNF1H_IMM_REAL + 379726140U, // LDNF1H_S_IMM_REAL + 379717163U, // LDNF1SB_D_IMM_REAL + 379749931U, // LDNF1SB_H_IMM_REAL + 379725355U, // LDNF1SB_S_IMM_REAL + 379718614U, // LDNF1SH_D_IMM_REAL + 379726806U, // LDNF1SH_S_IMM_REAL + 379720952U, // LDNF1SW_D_IMM_REAL + 379720772U, // LDNF1W_D_IMM_REAL + 379728964U, // LDNF1W_IMM_REAL + 2248200224U, // LDNPDi + 2248200224U, // LDNPQi + 2248200224U, // LDNPSi + 2248200224U, // LDNPWi + 2248200224U, // LDNPXi + 379741058U, // LDNT1B_ZRI + 379741058U, // LDNT1B_ZRR + 379717462U, // LDNT1D_ZRI + 379717462U, // LDNT1D_ZRR + 379750724U, // LDNT1H_ZRI + 379750724U, // LDNT1H_ZRR + 379728972U, // LDNT1W_ZRI + 379728972U, // LDNT1W_ZRR + 2248200156U, // LDPDi + 2516676572U, // LDPDpost + 2516676572U, // LDPDpre + 2248200156U, // LDPQi + 2516676572U, // LDPQpost + 2516676572U, // LDPQpre + 2248201473U, // LDPSWi + 2516677889U, // LDPSWpost + 2516677889U, // LDPSWpre + 2248200156U, // LDPSi + 2516676572U, // LDPSpost + 2516676572U, // LDPSpre + 2248200156U, // LDPWi + 2516676572U, // LDPWpost + 2516676572U, // LDPWpre + 2248200156U, // LDPXi + 2516676572U, // LDPXpost + 2516676572U, // LDPXpre + 106480223U, // LDRAAindexed + 374956639U, // LDRAAwriteback + 106480640U, // LDRABindexed + 374957056U, // LDRABwriteback + 374957469U, // LDRBBpost + 374957469U, // LDRBBpre + 106481053U, // LDRBBroW + 106481053U, // LDRBBroX + 106481053U, // LDRBBui + 374960359U, // LDRBpost + 374960359U, // LDRBpre + 106483943U, // LDRBroW + 106483943U, // LDRBroX + 106483943U, // LDRBui + 436261095U, // LDRDl + 374960359U, // LDRDpost + 374960359U, // LDRDpre + 106483943U, // LDRDroW + 106483943U, // LDRDroX + 106483943U, // LDRDui + 374958920U, // LDRHHpost + 374958920U, // LDRHHpre + 106482504U, // LDRHHroW + 106482504U, // LDRHHroX + 106482504U, // LDRHHui + 374960359U, // LDRHpost + 374960359U, // LDRHpre + 106483943U, // LDRHroW + 106483943U, // LDRHroX + 106483943U, // LDRHui + 436261095U, // LDRQl + 374960359U, // LDRQpost + 374960359U, // LDRQpre + 106483943U, // LDRQroW + 106483943U, // LDRQroX + 106483943U, // LDRQui + 374957657U, // LDRSBWpost + 374957657U, // LDRSBWpre + 106481241U, // LDRSBWroW + 106481241U, // LDRSBWroX + 106481241U, // LDRSBWui + 374957657U, // LDRSBXpost + 374957657U, // LDRSBXpre + 106481241U, // LDRSBXroW + 106481241U, // LDRSBXroX + 106481241U, // LDRSBXui + 374959095U, // LDRSHWpost + 374959095U, // LDRSHWpre + 106482679U, // LDRSHWroW + 106482679U, // LDRSHWroX + 106482679U, // LDRSHWui + 374959095U, // LDRSHXpost + 374959095U, // LDRSHXpre + 106482679U, // LDRSHXroW + 106482679U, // LDRSHXroX + 106482679U, // LDRSHXui + 436262160U, // LDRSWl + 374961424U, // LDRSWpost + 374961424U, // LDRSWpre + 106485008U, // LDRSWroW + 106485008U, // LDRSWroX + 106485008U, // LDRSWui + 436261095U, // LDRSl + 374960359U, // LDRSpost + 374960359U, // LDRSpre + 106483943U, // LDRSroW + 106483943U, // LDRSroX + 106483943U, // LDRSui + 436261095U, // LDRWl + 374960359U, // LDRWpost + 374960359U, // LDRWpre + 106483943U, // LDRWroW + 106483943U, // LDRWroX + 106483943U, // LDRWui + 436261095U, // LDRXl + 374960359U, // LDRXpost + 374960359U, // LDRXpre + 106483943U, // LDRXroW + 106483943U, // LDRXroX + 106483943U, // LDRXui + 106803431U, // LDR_PXI + 106803431U, // LDR_ZXI + 973169703U, // LDSETAB + 973171167U, // LDSETAH + 973169889U, // LDSETALB + 973171319U, // LDSETALH + 973171980U, // LDSETALW + 973171980U, // LDSETALX + 973169442U, // LDSETAW + 973169442U, // LDSETAX + 973170303U, // LDSETB + 973171736U, // LDSETH + 973169982U, // LDSETLB + 973171412U, // LDSETLH + 973172305U, // LDSETLW + 973172305U, // LDSETLX + 973173476U, // LDSETW + 973173476U, // LDSETX + 973169712U, // LDSMAXAB + 973171176U, // LDSMAXAH + 973169899U, // LDSMAXALB + 973171329U, // LDSMAXALH + 973171989U, // LDSMAXALW + 973171989U, // LDSMAXALX + 973169466U, // LDSMAXAW + 973169466U, // LDSMAXAX + 973170392U, // LDSMAXB + 973171768U, // LDSMAXH + 973169991U, // LDSMAXLB + 973171454U, // LDSMAXLH + 973172360U, // LDSMAXLW + 973172360U, // LDSMAXLX + 973174109U, // LDSMAXW + 973174109U, // LDSMAXX + 973169631U, // LDSMINAB + 973171115U, // LDSMINAH + 973169831U, // LDSMINALB + 973171261U, // LDSMINALH + 973171920U, // LDSMINALW + 973171920U, // LDSMINALX + 973169349U, // LDSMINAW + 973169349U, // LDSMINAX + 973170016U, // LDSMINB + 973171474U, // LDSMINH + 973169930U, // LDSMINLB + 973171360U, // LDSMINLH + 973172211U, // LDSMINLW + 973172211U, // LDSMINLX + 973172462U, // LDSMINW + 973172462U, // LDSMINX + 106481098U, // LDTRBi + 106482549U, // LDTRHi + 106481248U, // LDTRSBWi + 106481248U, // LDTRSBXi + 106482686U, // LDTRSHWi + 106482686U, // LDTRSHXi + 106485015U, // LDTRSWi + 106484081U, // LDTRWi + 106484081U, // LDTRXi + 973169722U, // LDUMAXAB + 973171186U, // LDUMAXAH + 973169910U, // LDUMAXALB + 973171340U, // LDUMAXALH + 973171999U, // LDUMAXALW + 973171999U, // LDUMAXALX + 973169475U, // LDUMAXAW + 973169475U, // LDUMAXAX + 973170401U, // LDUMAXB + 973171777U, // LDUMAXH + 973170001U, // LDUMAXLB + 973171464U, // LDUMAXLH + 973172369U, // LDUMAXLW + 973172369U, // LDUMAXLX + 973174117U, // LDUMAXW + 973174117U, // LDUMAXX + 973169641U, // LDUMINAB + 973171125U, // LDUMINAH + 973169842U, // LDUMINALB + 973171272U, // LDUMINALH + 973171930U, // LDUMINALW + 973171930U, // LDUMINALX + 973169358U, // LDUMINAW + 973169358U, // LDUMINAX + 973170025U, // LDUMINB + 973171483U, // LDUMINH + 973169940U, // LDUMINLB + 973171370U, // LDUMINLH + 973172220U, // LDUMINLW + 973172220U, // LDUMINLX + 973172470U, // LDUMINW + 973172470U, // LDUMINX + 106481118U, // LDURBBi + 106484104U, // LDURBi + 106484104U, // LDURDi + 106482569U, // LDURHHi + 106484104U, // LDURHi + 106484104U, // LDURQi + 106481256U, // LDURSBWi + 106481256U, // LDURSBXi + 106482694U, // LDURSHWi + 106482694U, // LDURSHXi + 106485023U, // LDURSWi + 106484104U, // LDURSi + 106484104U, // LDURWi + 106484104U, // LDURXi + 2248200327U, // LDXPW + 2248200327U, // LDXPX + 2253964805U, // LDXRB + 2253966256U, // LDXRH + 2253967807U, // LDXRW + 2253967807U, // LDXRX 0U, // LOADgot - 17049003U, // LSLVWr - 17049003U, // LSLVXr - 17049558U, // LSRVWr - 17049558U, // LSRVXr - 17048395U, // MADDWrrr - 17048395U, // MADDXrrr - 2181050875U, // MLAv16i8 - 2718446075U, // MLAv2i32 - 2718446075U, // MLAv2i32_indexed - 3255841275U, // MLAv4i16 - 3255841275U, // MLAv4i16_indexed - 1108619771U, // MLAv4i32 - 1108619771U, // MLAv4i32_indexed - 1645752827U, // MLAv8i16 - 1645752827U, // MLAv8i16_indexed - 3793498619U, // MLAv8i8 - 2181052514U, // MLSv16i8 - 2718447714U, // MLSv2i32 - 2718447714U, // MLSv2i32_indexed - 3255842914U, // MLSv4i16 - 3255842914U, // MLSv4i16_indexed - 1108621410U, // MLSv4i32 - 1108621410U, // MLSv4i32_indexed - 1645754466U, // MLSv8i16 - 1645754466U, // MLSv8i16_indexed - 3793500258U, // MLSv8i8 - 168043698U, // MOVID - 721425586U, // MOVIv16b_ns - 168563890U, // MOVIv2d_ns - 1795691698U, // MOVIv2i32 - 1795691698U, // MOVIv2s_msl - 1796215986U, // MOVIv4i16 - 1796478130U, // MOVIv4i32 - 1796478130U, // MOVIv4s_msl - 723260594U, // MOVIv8b_ns - 1796740274U, // MOVIv8i16 - 84157629U, // MOVKWi - 84157629U, // MOVKXi - 1795434146U, // MOVNWi - 1795434146U, // MOVNXi - 1795435093U, // MOVZWi - 1795435093U, // MOVZXi + 302002471U, // LSLR_ZPmZ_B + 302010663U, // LSLR_ZPmZ_D + 2186309927U, // LSLR_ZPmZ_H + 302027047U, // LSLR_ZPmZ_S + 100716088U, // LSLVWr + 100716088U, // LSLVXr + 302001720U, // LSL_WIDE_ZPmZ_B + 2186309176U, // LSL_WIDE_ZPmZ_H + 302026296U, // LSL_WIDE_ZPmZ_S + 167783992U, // LSL_WIDE_ZZZ_B + 2387111480U, // LSL_WIDE_ZZZ_H + 268471864U, // LSL_WIDE_ZZZ_S + 302001720U, // LSL_ZPmI_B + 302009912U, // LSL_ZPmI_D + 2186309176U, // LSL_ZPmI_H + 302026296U, // LSL_ZPmI_S + 302001720U, // LSL_ZPmZ_B + 302009912U, // LSL_ZPmZ_D + 2186309176U, // LSL_ZPmZ_H + 302026296U, // LSL_ZPmZ_S + 167783992U, // LSL_ZZI_B + 201346616U, // LSL_ZZI_D + 239627832U, // LSL_ZZI_H + 268471864U, // LSL_ZZI_S + 302002518U, // LSRR_ZPmZ_B + 302010710U, // LSRR_ZPmZ_D + 2186309974U, // LSRR_ZPmZ_H + 302027094U, // LSRR_ZPmZ_S + 100716897U, // LSRVWr + 100716897U, // LSRVXr + 302002529U, // LSR_WIDE_ZPmZ_B + 2186309985U, // LSR_WIDE_ZPmZ_H + 302027105U, // LSR_WIDE_ZPmZ_S + 167784801U, // LSR_WIDE_ZZZ_B + 2387112289U, // LSR_WIDE_ZZZ_H + 268472673U, // LSR_WIDE_ZZZ_S + 302002529U, // LSR_ZPmI_B + 302010721U, // LSR_ZPmI_D + 2186309985U, // LSR_ZPmI_H + 302027105U, // LSR_ZPmI_S + 302002529U, // LSR_ZPmZ_B + 302010721U, // LSR_ZPmZ_D + 2186309985U, // LSR_ZPmZ_H + 302027105U, // LSR_ZPmZ_S + 167784801U, // LSR_ZZI_B + 201347425U, // LSR_ZZI_D + 239628641U, // LSR_ZZI_H + 268472673U, // LSR_ZZI_S + 100714512U, // MADDWrrr + 100714512U, // MADDXrrr + 302000017U, // MAD_ZPmZZ_B + 302008209U, // MAD_ZPmZZ_D + 2186307473U, // MAD_ZPmZZ_H + 302024593U, // MAD_ZPmZZ_S + 301998771U, // MLA_ZPmZZ_B + 302006963U, // MLA_ZPmZZ_D + 2186306227U, // MLA_ZPmZZ_H + 302023347U, // MLA_ZPmZZ_S + 135324339U, // MLAv16i8 + 2283332275U, // MLAv2i32 + 2283332275U, // MLAv2i32_indexed + 136897203U, // MLAv4i16 + 136897203U, // MLAv4i16_indexed + 137421491U, // MLAv4i32 + 137421491U, // MLAv4i32_indexed + 2285429427U, // MLAv8i16 + 2285429427U, // MLAv8i16_indexed + 2285953715U, // MLAv8i8 + 302002771U, // MLS_ZPmZZ_B + 302010963U, // MLS_ZPmZZ_D + 2186310227U, // MLS_ZPmZZ_H + 302027347U, // MLS_ZPmZZ_S + 135328339U, // MLSv16i8 + 2283336275U, // MLSv2i32 + 2283336275U, // MLSv2i32_indexed + 136901203U, // MLSv4i16 + 136901203U, // MLSv4i16_indexed + 137425491U, // MLSv4i32 + 137425491U, // MLSv4i32_indexed + 2285433427U, // MLSv8i16 + 2285433427U, // MLSv8i16_indexed + 2285957715U, // MLSv8i8 + 1006685329U, // MOVID + 3188763793U, // MOVIv16b_ns + 1008774289U, // MOVIv2d_ns + 3189288081U, // MOVIv2i32 + 3189288081U, // MOVIv2s_msl + 3190336657U, // MOVIv4i16 + 3190860945U, // MOVIv4i32 + 3190860945U, // MOVIv4s_msl + 3191909521U, // MOVIv8b_ns + 3191385233U, // MOVIv8i16 + 402705564U, // MOVKWi + 402705564U, // MOVKXi + 3187724142U, // MOVNWi + 3187724142U, // MOVNXi + 13705U, // MOVPRFX_ZPmZ_B + 21897U, // MOVPRFX_ZPmZ_D + 2181592457U, // MOVPRFX_ZPmZ_H + 38281U, // MOVPRFX_ZPmZ_S + 302003593U, // MOVPRFX_ZPzZ_B + 302011785U, // MOVPRFX_ZPzZ_D + 2622518665U, // MOVPRFX_ZPzZ_H + 302028169U, // MOVPRFX_ZPzZ_S + 2449847689U, // MOVPRFX_ZZ + 3187725817U, // MOVZWi + 3187725817U, // MOVZXi 0U, // MOVaddr 0U, // MOVaddrBA 0U, // MOVaddrCP 0U, // MOVaddrEXT 0U, // MOVaddrJT 0U, // MOVaddrTLS + 0U, // MOVbaseTLS 0U, // MOVi32imm 0U, // MOVi64imm - 201599116U, // MRS - 137179U, // MSR - 141275U, // MSRpstate - 17048258U, // MSUBWrrr - 17048258U, // MSUBXrrr - 2147489228U, // MULv16i8 - 2684884428U, // MULv2i32 - 2684884428U, // MULv2i32_indexed - 3222279628U, // MULv4i16 - 3222279628U, // MULv4i16_indexed - 1075058124U, // MULv4i32 - 1075058124U, // MULv4i32_indexed - 1612191180U, // MULv8i16 - 1612191180U, // MULv8i16_indexed - 3759936972U, // MULv8i8 - 1795691679U, // MVNIv2i32 - 1795691679U, // MVNIv2s_msl - 1796215967U, // MVNIv4i16 - 1796478111U, // MVNIv4i32 - 1796478111U, // MVNIv4s_msl - 1796740255U, // MVNIv8i16 - 5076U, // NEGv16i8 - 553919444U, // NEGv1i64 - 1074271188U, // NEGv2i32 - 1611404244U, // NEGv2i64 - 2148537300U, // NEGv4i16 - 2685670356U, // NEGv4i32 - 3222803412U, // NEGv8i16 - 3759936468U, // NEGv8i8 - 6353U, // NOTv16i8 - 3759937745U, // NOTv8i8 + 1073795744U, // MRS + 301999685U, // MSB_ZPmZZ_B + 302007877U, // MSB_ZPmZZ_D + 2186307141U, // MSB_ZPmZZ_H + 302024261U, // MSB_ZPmZZ_S + 381286U, // MSR + 389478U, // MSRpstateImm1 + 389478U, // MSRpstateImm4 + 100714166U, // MSUBWrrr + 100714166U, // MSUBXrrr + 167784033U, // MUL_ZI_B + 201346657U, // MUL_ZI_D + 239627873U, // MUL_ZI_H + 268471905U, // MUL_ZI_S + 302001761U, // MUL_ZPmZ_B + 302009953U, // MUL_ZPmZ_D + 2186309217U, // MUL_ZPmZ_H + 302026337U, // MUL_ZPmZ_S + 68202081U, // MULv16i8 + 2216210017U, // MULv2i32 + 2216210017U, // MULv2i32_indexed + 69774945U, // MULv4i16 + 69774945U, // MULv4i16_indexed + 70299233U, // MULv4i32 + 70299233U, // MULv4i32_indexed + 2218307169U, // MULv8i16 + 2218307169U, // MULv8i16_indexed + 2218831457U, // MULv8i8 + 3189288062U, // MVNIv2i32 + 3189288062U, // MVNIv2s_msl + 3190336638U, // MVNIv4i16 + 3190860926U, // MVNIv4i32 + 3190860926U, // MVNIv4s_msl + 3191385214U, // MVNIv8i16 + 302002728U, // NANDS_PPzPP + 302000180U, // NAND_PPzPP + 10516U, // NEG_ZPmZ_B + 18708U, // NEG_ZPmZ_D + 2181589268U, // NEG_ZPmZ_H + 35092U, // NEG_ZPmZ_S + 68200724U, // NEGv16i8 + 2248198420U, // NEGv1i64 + 68725012U, // NEGv2i32 + 2216732948U, // NEGv2i64 + 69773588U, // NEGv4i16 + 2217781524U, // NEGv4i32 + 70822164U, // NEGv8i16 + 2218830100U, // NEGv8i8 + 302002859U, // NORS_PPzPP + 302002490U, // NOR_PPzPP + 13114U, // NOT_ZPmZ_B + 21306U, // NOT_ZPmZ_D + 2181591866U, // NOT_ZPmZ_H + 37690U, // NOT_ZPmZ_S + 68203322U, // NOTv16i8 + 2218832698U, // NOTv8i8 + 302002810U, // ORNS_PPzPP 0U, // ORNWrr - 17049189U, // ORNWrs + 100716337U, // ORNWrs 0U, // ORNXrr - 17049189U, // ORNXrs - 2147489381U, // ORNv16i8 - 3759937125U, // ORNv8i8 - 17049548U, // ORRWri + 100716337U, // ORNXrs + 302001969U, // ORN_PPzPP + 68202289U, // ORNv16i8 + 2218831665U, // ORNv8i8 + 302002865U, // ORRS_PPzPP + 100716875U, // ORRWri 0U, // ORRWrr - 17049548U, // ORRWrs - 17049548U, // ORRXri + 100716875U, // ORRWrs + 100716875U, // ORRXri 0U, // ORRXrr - 17049548U, // ORRXrs - 2147489740U, // ORRv16i8 - 84424652U, // ORRv2i32 - 84948940U, // ORRv4i16 - 85211084U, // ORRv4i32 - 85473228U, // ORRv8i16 - 3759937484U, // ORRv8i8 - 2149060822U, // PMULLv16i8 - 228070797U, // PMULLv1i64 - 244846806U, // PMULLv2i64 - 3759674765U, // PMULLv8i8 - 2147489240U, // PMULv16i8 - 3759936984U, // PMULv8i8 - 101070321U, // PRFMl - 26621425U, // PRFMroW - 26621425U, // PRFMroX - 26621425U, // PRFMui - 26621455U, // PRFUMi - 537400862U, // RADDHNv2i64_v2i32 - 571748633U, // RADDHNv2i64_v4i32 - 1074796062U, // RADDHNv4i32_v4i16 - 1108881689U, // RADDHNv4i32_v8i16 - 1644179737U, // RADDHNv8i16_v16i8 - 1612453406U, // RADDHNv8i16_v8i8 - 553920698U, // RBITWr - 553920698U, // RBITXr - 6330U, // RBITv16i8 - 3759937722U, // RBITv8i8 - 2107559U, // RET + 100716875U, // ORRXrs + 302002507U, // ORR_PPzPP + 201347403U, // ORR_ZI + 302002507U, // ORR_ZPmZ_B + 302010699U, // ORR_ZPmZ_D + 2186309963U, // ORR_ZPmZ_H + 302027083U, // ORR_ZPmZ_S + 201347403U, // ORR_ZZZ + 68202827U, // ORRv16i8 + 404287819U, // ORRv2i32 + 405336395U, // ORRv4i16 + 405860683U, // ORRv4i32 + 406384971U, // ORRv8i16 + 2218832203U, // ORRv8i8 + 302044188U, // ORV_VPZ_B + 302044188U, // ORV_VPZ_D + 302044188U, // ORV_VPZ_H + 302044188U, // ORV_VPZ_S + 2248196729U, // PACDA + 2248197229U, // PACDB + 6341452U, // PACDZA + 6342378U, // PACDZB + 100713110U, // PACGA + 2248196765U, // PACIA + 5796U, // PACIA1716 + 5927U, // PACIASP + 5982U, // PACIAZ + 2248197257U, // PACIB + 5816U, // PACIB1716 + 5943U, // PACIBSP + 5996U, // PACIBZ + 6341468U, // PACIZA + 6342394U, // PACIZB + 6301913U, // PFALSE + 70820111U, // PMULLv16i8 + 1132506590U, // PMULLv1i64 + 1166057743U, // PMULLv2i64 + 2218307038U, // PMULLv8i8 + 68202093U, // PMULv16i8 + 2218831469U, // PMULv8i8 + 302003042U, // PNEXT_B + 302011234U, // PNEXT_D + 2387637090U, // PNEXT_H + 302027618U, // PNEXT_S + 3079537795U, // PRFB_D_PZI + 246285443U, // PRFB_D_SCALED + 2393769091U, // PRFB_D_SXTW_SCALED + 246285443U, // PRFB_D_UXTW_SCALED + 246285443U, // PRFB_PRI + 2393769091U, // PRFB_PRR + 3080062083U, // PRFB_S_PZI + 246285443U, // PRFB_S_SXTW_SCALED + 2393769091U, // PRFB_S_UXTW_SCALED + 1200490542U, // PRFD_D_PZI + 246286382U, // PRFD_D_SCALED + 2393770030U, // PRFD_D_SXTW_SCALED + 246286382U, // PRFD_D_UXTW_SCALED + 246286382U, // PRFD_PRI + 2393770030U, // PRFD_PRR + 1201014830U, // PRFD_S_PZI + 246286382U, // PRFD_S_SXTW_SCALED + 2393770030U, // PRFD_S_UXTW_SCALED + 1234045485U, // PRFH_D_PZI + 246286893U, // PRFH_D_SCALED + 2393770541U, // PRFH_D_SXTW_SCALED + 246286893U, // PRFH_D_UXTW_SCALED + 246286893U, // PRFH_PRI + 2393770541U, // PRFH_PRR + 1234569773U, // PRFH_S_PZI + 246286893U, // PRFH_S_SXTW_SCALED + 2393770541U, // PRFH_S_UXTW_SCALED + 436612781U, // PRFMl + 106835629U, // PRFMroW + 106835629U, // PRFMroX + 106835629U, // PRFMui + 246289619U, // PRFS_PRR + 106835665U, // PRFUMi + 1267602643U, // PRFW_D_PZI + 2393773267U, // PRFW_D_SCALED + 246289619U, // PRFW_D_SXTW_SCALED + 2393773267U, // PRFW_D_UXTW_SCALED + 246289619U, // PRFW_PRI + 1268126931U, // PRFW_S_PZI + 246289619U, // PRFW_S_SXTW_SCALED + 2393773267U, // PRFW_S_UXTW_SCALED + 2315629382U, // PTEST_PP + 2650812975U, // PTRUES_B + 2650821167U, // PTRUES_D + 26767919U, // PTRUES_H + 2650837551U, // PTRUES_S + 2650810611U, // PTRUE_B + 2650818803U, // PTRUE_D + 26765555U, // PTRUE_H + 2650835187U, // PTRUE_S + 27290705U, // PUNPKHI_PP + 27291525U, // PUNPKLO_PP + 2216210144U, // RADDHNv2i64_v2i32 + 2284904786U, // RADDHNv2i64_v4i32 + 69775072U, // RADDHNv4i32_v4i16 + 137945426U, // RADDHNv4i32_v8i16 + 2282807634U, // RADDHNv8i16_v16i8 + 2218831584U, // RADDHNv8i16_v8i8 + 2216730741U, // RAX1 + 2248200960U, // RBITWr + 2248200960U, // RBITXr + 13056U, // RBIT_ZPmZ_B + 21248U, // RBIT_ZPmZ_D + 2181591808U, // RBIT_ZPmZ_H + 37632U, // RBIT_ZPmZ_S + 68203264U, // RBITv16i8 + 2218832640U, // RBITv8i8 + 302002840U, // RDFFRS_PPz + 6303980U, // RDFFR_P + 302002412U, // RDFFR_PPz + 2248199810U, // RDVLI_XI + 6345439U, // RET + 5892U, // RETAA + 5899U, // RETAB 0U, // RET_ReallyLR - 553918951U, // REV16Wr - 553918951U, // REV16Xr - 4583U, // REV16v16i8 - 3759935975U, // REV16v8i8 - 553918540U, // REV32Xr - 4172U, // REV32v16i8 - 2148536396U, // REV32v4i16 - 3222802508U, // REV32v8i16 - 3759935564U, // REV32v8i8 - 4566U, // REV64v16i8 - 1074270678U, // REV64v2i32 - 2148536790U, // REV64v4i16 - 2685669846U, // REV64v4i32 - 3222802902U, // REV64v8i16 - 3759935958U, // REV64v8i8 - 553920805U, // REVWr - 553920805U, // REVXr - 17049543U, // RORVWr - 17049543U, // RORVXr - 1644179766U, // RSHRNv16i8_shift - 537400917U, // RSHRNv2i32_shift - 1074796117U, // RSHRNv4i16_shift - 571748662U, // RSHRNv4i32_shift - 1108881718U, // RSHRNv8i16_shift - 1612453461U, // RSHRNv8i8_shift - 537400854U, // RSUBHNv2i64_v2i32 - 571748624U, // RSUBHNv2i64_v4i32 - 1074796054U, // RSUBHNv4i32_v4i16 - 1108881680U, // RSUBHNv4i32_v8i16 - 1644179728U, // RSUBHNv8i16_v16i8 - 1612453398U, // RSUBHNv8i16_v8i8 - 2182623330U, // SABALv16i8_v8i16 - 2718708931U, // SABALv2i32_v2i64 - 3256104131U, // SABALv4i16_v4i32 - 1108095074U, // SABALv4i32_v2i64 - 1645490274U, // SABALv8i16_v4i32 - 3793237187U, // SABALv8i8_v8i16 - 2181050862U, // SABAv16i8 - 2718446062U, // SABAv2i32 - 3255841262U, // SABAv4i16 - 1108619758U, // SABAv4i32 - 1645752814U, // SABAv8i16 - 3793498606U, // SABAv8i8 - 2149060764U, // SABDLv16i8_v8i16 - 2685146379U, // SABDLv2i32_v2i64 - 3222541579U, // SABDLv4i16_v4i32 - 1074532508U, // SABDLv4i32_v2i64 - 1611927708U, // SABDLv8i16_v4i32 - 3759674635U, // SABDLv8i8_v8i16 - 2147488538U, // SABDv16i8 - 2684883738U, // SABDv2i32 - 3222278938U, // SABDv4i16 - 1075057434U, // SABDv4i32 - 1612190490U, // SABDv8i16 - 3759936282U, // SABDv8i8 - 35141315U, // SADALPv16i8_v8i16 - 1117533891U, // SADALPv2i32_v1i64 - 2181576387U, // SADALPv4i16_v2i32 - 2718709443U, // SADALPv4i32_v2i64 - 3256104643U, // SADALPv8i16_v4i32 - 3792713411U, // SADALPv8i8_v4i16 - 1578707U, // SADDLPv16i8_v8i16 - 1083971283U, // SADDLPv2i32_v1i64 - 2148013779U, // SADDLPv4i16_v2i32 - 2685146835U, // SADDLPv4i32_v2i64 - 3222542035U, // SADDLPv8i16_v4i32 - 3759150803U, // SADDLPv8i8_v4i16 - 272700U, // SADDLVv16i8v - 2147756348U, // SADDLVv4i16v - 2684627260U, // SADDLVv4i32v - 3221498172U, // SADDLVv8i16v - 3758369084U, // SADDLVv8i8v - 2149060780U, // SADDLv16i8_v8i16 - 2685146409U, // SADDLv2i32_v2i64 - 3222541609U, // SADDLv4i16_v4i32 - 1074532524U, // SADDLv4i32_v2i64 - 1611927724U, // SADDLv8i16_v4i32 - 3759674665U, // SADDLv8i8_v8i16 - 1612190133U, // SADDWv16i8_v8i16 - 537663936U, // SADDWv2i32_v2i64 - 1075059136U, // SADDWv4i16_v4i32 - 537661877U, // SADDWv4i32_v2i64 - 1075057077U, // SADDWv8i16_v4i32 - 1612192192U, // SADDWv8i8_v8i16 - 17049656U, // SBCSWr - 17049656U, // SBCSXr - 17048293U, // SBCWr - 17048293U, // SBCXr - 17049061U, // SBFMWri - 17049061U, // SBFMXri - 17048517U, // SCVTFSWDri - 17048517U, // SCVTFSWSri - 17048517U, // SCVTFSXDri - 17048517U, // SCVTFSXSri - 553919429U, // SCVTFUWDri - 553919429U, // SCVTFUWSri - 553919429U, // SCVTFUXDri - 553919429U, // SCVTFUXSri - 17048517U, // SCVTFd - 17048517U, // SCVTFs - 553919429U, // SCVTFv1i32 - 553919429U, // SCVTFv1i64 - 1074271173U, // SCVTFv2f32 - 1611404229U, // SCVTFv2f64 - 2684883909U, // SCVTFv2i32_shift - 537662405U, // SCVTFv2i64_shift - 2685670341U, // SCVTFv4f32 - 1075057605U, // SCVTFv4i32_shift - 17049904U, // SDIVWr - 17049904U, // SDIVXr - 17049904U, // SDIV_IntWr - 17049904U, // SDIV_IntXr - 67404510U, // SHA1Crrr - 553919463U, // SHA1Hrr - 67405278U, // SHA1Mrrr - 67405488U, // SHA1Prrr - 1108619265U, // SHA1SU0rrr - 2719232056U, // SHA1SU1rr - 67403864U, // SHA256H2rrr - 67404790U, // SHA256Hrrr - 2719232010U, // SHA256SU0rr - 1108619329U, // SHA256SU1rrr - 2147488572U, // SHADDv16i8 - 2684883772U, // SHADDv2i32 - 3222278972U, // SHADDv4i16 - 1075057468U, // SHADDv4i32 - 1612190524U, // SHADDv8i16 - 3759936316U, // SHADDv8i8 - 2149060797U, // SHLLv16i8 - 2685146487U, // SHLLv2i32 - 3222541687U, // SHLLv4i16 - 3758887101U, // SHLLv4i32 - 1315005U, // SHLLv8i16 - 538449271U, // SHLLv8i8 - 17048896U, // SHLd - 2147489088U, // SHLv16i8_shift - 2684884288U, // SHLv2i32_shift - 537662784U, // SHLv2i64_shift - 3222279488U, // SHLv4i16_shift - 1075057984U, // SHLv4i32_shift - 1612191040U, // SHLv8i16_shift - 3759936832U, // SHLv8i8_shift - 1644179748U, // SHRNv16i8_shift - 537400901U, // SHRNv2i32_shift - 1074796101U, // SHRNv4i16_shift - 571748644U, // SHRNv4i32_shift - 1108881700U, // SHRNv8i16_shift - 1612453445U, // SHRNv8i8_shift - 2147488435U, // SHSUBv16i8 - 2684883635U, // SHSUBv2i32 - 3222278835U, // SHSUBv4i16 - 1075057331U, // SHSUBv4i32 - 1612190387U, // SHSUBv8i16 - 3759936179U, // SHSUBv8i8 - 67404954U, // SLId - 2181051546U, // SLIv16i8_shift - 2718446746U, // SLIv2i32_shift - 571225242U, // SLIv2i64_shift - 3255841946U, // SLIv4i16_shift - 1108620442U, // SLIv4i32_shift - 1645753498U, // SLIv8i16_shift - 3793499290U, // SLIv8i8_shift - 17048857U, // SMADDLrrr - 2147489609U, // SMAXPv16i8 - 2684884809U, // SMAXPv2i32 - 3222280009U, // SMAXPv4i16 - 1075058505U, // SMAXPv4i32 - 1612191561U, // SMAXPv8i16 - 3759937353U, // SMAXPv8i8 - 272787U, // SMAXVv16i8v - 2147756435U, // SMAXVv4i16v - 2684627347U, // SMAXVv4i32v - 3221498259U, // SMAXVv8i16v - 3758369171U, // SMAXVv8i8v - 2147490298U, // SMAXv16i8 - 2684885498U, // SMAXv2i32 - 3222280698U, // SMAXv4i16 - 1075059194U, // SMAXv4i32 - 1612192250U, // SMAXv8i16 - 3759938042U, // SMAXv8i8 - 21246U, // SMC - 2147489551U, // SMINPv16i8 - 2684884751U, // SMINPv2i32 - 3222279951U, // SMINPv4i16 - 1075058447U, // SMINPv4i32 - 1612191503U, // SMINPv8i16 - 3759937295U, // SMINPv8i8 - 272741U, // SMINVv16i8v - 2147756389U, // SMINVv4i16v - 2684627301U, // SMINVv4i32v - 3221498213U, // SMINVv8i16v - 3758369125U, // SMINVv8i8v - 2147489324U, // SMINv16i8 - 2684884524U, // SMINv2i32 - 3222279724U, // SMINv4i16 - 1075058220U, // SMINv4i32 - 1612191276U, // SMINv8i16 - 3759937068U, // SMINv8i8 - 2182623356U, // SMLALv16i8_v8i16 - 2718708954U, // SMLALv2i32_indexed - 2718708954U, // SMLALv2i32_v2i64 - 3256104154U, // SMLALv4i16_indexed - 3256104154U, // SMLALv4i16_v4i32 - 1108095100U, // SMLALv4i32_indexed - 1108095100U, // SMLALv4i32_v2i64 - 1645490300U, // SMLALv8i16_indexed - 1645490300U, // SMLALv8i16_v4i32 - 3793237210U, // SMLALv8i8_v8i16 - 2182623480U, // SMLSLv16i8_v8i16 - 2718709168U, // SMLSLv2i32_indexed - 2718709168U, // SMLSLv2i32_v2i64 - 3256104368U, // SMLSLv4i16_indexed - 3256104368U, // SMLSLv4i16_v4i32 - 1108095224U, // SMLSLv4i32_indexed - 1108095224U, // SMLSLv4i32_v2i64 - 1645490424U, // SMLSLv8i16_indexed - 1645490424U, // SMLSLv8i16_v4i32 - 3793237424U, // SMLSLv8i8_v8i16 - 272768U, // SMOVvi16to32 - 272768U, // SMOVvi16to64 - 537143680U, // SMOVvi32to64 - 1610885504U, // SMOVvi8to32 - 1610885504U, // SMOVvi8to64 - 17048813U, // SMSUBLrrr - 17048603U, // SMULHrr - 2149060830U, // SMULLv16i8_v8i16 - 2685146516U, // SMULLv2i32_indexed - 2685146516U, // SMULLv2i32_v2i64 - 3222541716U, // SMULLv4i16_indexed - 3222541716U, // SMULLv4i16_v4i32 - 1074532574U, // SMULLv4i32_indexed - 1074532574U, // SMULLv4i32_v2i64 - 1611927774U, // SMULLv8i16_indexed - 1611927774U, // SMULLv8i16_v4i32 - 3759674772U, // SMULLv8i8_v8i16 - 6187U, // SQABSv16i8 - 553920555U, // SQABSv1i16 - 553920555U, // SQABSv1i32 - 553920555U, // SQABSv1i64 - 553920555U, // SQABSv1i8 - 1074272299U, // SQABSv2i32 - 1611405355U, // SQABSv2i64 - 2148538411U, // SQABSv4i16 - 2685671467U, // SQABSv4i32 - 3222804523U, // SQABSv8i16 - 3759937579U, // SQABSv8i8 - 2147488602U, // SQADDv16i8 - 17048410U, // SQADDv1i16 - 17048410U, // SQADDv1i32 - 17048410U, // SQADDv1i64 - 17048410U, // SQADDv1i8 - 2684883802U, // SQADDv2i32 - 537662298U, // SQADDv2i64 - 3222279002U, // SQADDv4i16 - 1075057498U, // SQADDv4i32 - 1612190554U, // SQADDv8i16 - 3759936346U, // SQADDv8i8 - 67405009U, // SQDMLALi16 - 67405009U, // SQDMLALi32 - 67405009U, // SQDMLALv1i32_indexed - 67405009U, // SQDMLALv1i64_indexed - 2718708945U, // SQDMLALv2i32_indexed - 2718708945U, // SQDMLALv2i32_v2i64 - 3256104145U, // SQDMLALv4i16_indexed - 3256104145U, // SQDMLALv4i16_v4i32 - 1108095090U, // SQDMLALv4i32_indexed - 1108095090U, // SQDMLALv4i32_v2i64 - 1645490290U, // SQDMLALv8i16_indexed - 1645490290U, // SQDMLALv8i16_v4i32 - 67405223U, // SQDMLSLi16 - 67405223U, // SQDMLSLi32 - 67405223U, // SQDMLSLv1i32_indexed - 67405223U, // SQDMLSLv1i64_indexed - 2718709159U, // SQDMLSLv2i32_indexed - 2718709159U, // SQDMLSLv2i32_v2i64 - 3256104359U, // SQDMLSLv4i16_indexed - 3256104359U, // SQDMLSLv4i16_v4i32 - 1108095214U, // SQDMLSLv4i32_indexed - 1108095214U, // SQDMLSLv4i32_v2i64 - 1645490414U, // SQDMLSLv8i16_indexed - 1645490414U, // SQDMLSLv8i16_v4i32 - 17048584U, // SQDMULHv1i16 - 17048584U, // SQDMULHv1i16_indexed - 17048584U, // SQDMULHv1i32 - 17048584U, // SQDMULHv1i32_indexed - 2684883976U, // SQDMULHv2i32 - 2684883976U, // SQDMULHv2i32_indexed - 3222279176U, // SQDMULHv4i16 - 3222279176U, // SQDMULHv4i16_indexed - 1075057672U, // SQDMULHv4i32 - 1075057672U, // SQDMULHv4i32_indexed - 1612190728U, // SQDMULHv8i16 - 1612190728U, // SQDMULHv8i16_indexed - 17048964U, // SQDMULLi16 - 17048964U, // SQDMULLi32 - 17048964U, // SQDMULLv1i32_indexed - 17048964U, // SQDMULLv1i64_indexed - 2685146500U, // SQDMULLv2i32_indexed - 2685146500U, // SQDMULLv2i32_v2i64 - 3222541700U, // SQDMULLv4i16_indexed - 3222541700U, // SQDMULLv4i16_v4i32 - 1074532556U, // SQDMULLv4i32_indexed - 1074532556U, // SQDMULLv4i32_v2i64 - 1611927756U, // SQDMULLv8i16_indexed - 1611927756U, // SQDMULLv8i16_v4i32 - 5081U, // SQNEGv16i8 - 553919449U, // SQNEGv1i16 - 553919449U, // SQNEGv1i32 - 553919449U, // SQNEGv1i64 - 553919449U, // SQNEGv1i8 - 1074271193U, // SQNEGv2i32 - 1611404249U, // SQNEGv2i64 - 2148537305U, // SQNEGv4i16 - 2685670361U, // SQNEGv4i32 - 3222803417U, // SQNEGv8i16 - 3759936473U, // SQNEGv8i8 - 17048593U, // SQRDMULHv1i16 - 17048593U, // SQRDMULHv1i16_indexed - 17048593U, // SQRDMULHv1i32 - 17048593U, // SQRDMULHv1i32_indexed - 2684883985U, // SQRDMULHv2i32 - 2684883985U, // SQRDMULHv2i32_indexed - 3222279185U, // SQRDMULHv4i16 - 3222279185U, // SQRDMULHv4i16_indexed - 1075057681U, // SQRDMULHv4i32 - 1075057681U, // SQRDMULHv4i32_indexed - 1612190737U, // SQRDMULHv8i16 - 1612190737U, // SQRDMULHv8i16_indexed - 2147489100U, // SQRSHLv16i8 - 17048908U, // SQRSHLv1i16 - 17048908U, // SQRSHLv1i32 - 17048908U, // SQRSHLv1i64 - 17048908U, // SQRSHLv1i8 - 2684884300U, // SQRSHLv2i32 - 537662796U, // SQRSHLv2i64 - 3222279500U, // SQRSHLv4i16 - 1075057996U, // SQRSHLv4i32 - 1612191052U, // SQRSHLv8i16 - 3759936844U, // SQRSHLv8i8 - 17049171U, // SQRSHRNb - 17049171U, // SQRSHRNh - 17049171U, // SQRSHRNs - 1644179764U, // SQRSHRNv16i8_shift - 537400915U, // SQRSHRNv2i32_shift - 1074796115U, // SQRSHRNv4i16_shift - 571748660U, // SQRSHRNv4i32_shift - 1108881716U, // SQRSHRNv8i16_shift - 1612453459U, // SQRSHRNv8i8_shift - 17049232U, // SQRSHRUNb - 17049232U, // SQRSHRUNh - 17049232U, // SQRSHRUNs - 1644179824U, // SQRSHRUNv16i8_shift - 537400976U, // SQRSHRUNv2i32_shift - 1074796176U, // SQRSHRUNv4i16_shift - 571748720U, // SQRSHRUNv4i32_shift - 1108881776U, // SQRSHRUNv8i16_shift - 1612453520U, // SQRSHRUNv8i8_shift - 17049847U, // SQSHLUb - 17049847U, // SQSHLUd - 17049847U, // SQSHLUh - 17049847U, // SQSHLUs - 2147490039U, // SQSHLUv16i8_shift - 2684885239U, // SQSHLUv2i32_shift - 537663735U, // SQSHLUv2i64_shift - 3222280439U, // SQSHLUv4i16_shift - 1075058935U, // SQSHLUv4i32_shift - 1612191991U, // SQSHLUv8i16_shift - 3759937783U, // SQSHLUv8i8_shift - 17048894U, // SQSHLb - 17048894U, // SQSHLd - 17048894U, // SQSHLh - 17048894U, // SQSHLs - 2147489086U, // SQSHLv16i8 - 2147489086U, // SQSHLv16i8_shift - 17048894U, // SQSHLv1i16 - 17048894U, // SQSHLv1i32 - 17048894U, // SQSHLv1i64 - 17048894U, // SQSHLv1i8 - 2684884286U, // SQSHLv2i32 - 2684884286U, // SQSHLv2i32_shift - 537662782U, // SQSHLv2i64 - 537662782U, // SQSHLv2i64_shift - 3222279486U, // SQSHLv4i16 - 3222279486U, // SQSHLv4i16_shift - 1075057982U, // SQSHLv4i32 - 1075057982U, // SQSHLv4i32_shift - 1612191038U, // SQSHLv8i16 - 1612191038U, // SQSHLv8i16_shift - 3759936830U, // SQSHLv8i8 - 3759936830U, // SQSHLv8i8_shift - 17049155U, // SQSHRNb - 17049155U, // SQSHRNh - 17049155U, // SQSHRNs - 1644179746U, // SQSHRNv16i8_shift - 537400899U, // SQSHRNv2i32_shift - 1074796099U, // SQSHRNv4i16_shift - 571748642U, // SQSHRNv4i32_shift - 1108881698U, // SQSHRNv8i16_shift - 1612453443U, // SQSHRNv8i8_shift - 17049223U, // SQSHRUNb - 17049223U, // SQSHRUNh - 17049223U, // SQSHRUNs - 1644179814U, // SQSHRUNv16i8_shift - 537400967U, // SQSHRUNv2i32_shift - 1074796167U, // SQSHRUNv4i16_shift - 571748710U, // SQSHRUNv4i32_shift - 1108881766U, // SQSHRUNv8i16_shift - 1612453511U, // SQSHRUNv8i8_shift - 2147488464U, // SQSUBv16i8 - 17048272U, // SQSUBv1i16 - 17048272U, // SQSUBv1i32 - 17048272U, // SQSUBv1i64 - 17048272U, // SQSUBv1i8 - 2684883664U, // SQSUBv2i32 - 537662160U, // SQSUBv2i64 - 3222278864U, // SQSUBv4i16 - 1075057360U, // SQSUBv4i32 - 1612190416U, // SQSUBv8i16 - 3759936208U, // SQSUBv8i8 - 3254792534U, // SQXTNv16i8 - 553920121U, // SQXTNv1i16 - 553920121U, // SQXTNv1i32 - 553920121U, // SQXTNv1i8 - 1611142777U, // SQXTNv2i32 - 2685408889U, // SQXTNv4i16 - 1645490518U, // SQXTNv4i32 - 2719494486U, // SQXTNv8i16 - 3223066233U, // SQXTNv8i8 - 3254792571U, // SQXTUNv16i8 - 553920154U, // SQXTUNv1i16 - 553920154U, // SQXTUNv1i32 - 553920154U, // SQXTUNv1i8 - 1611142810U, // SQXTUNv2i32 - 2685408922U, // SQXTUNv4i16 - 1645490555U, // SQXTUNv4i32 - 2719494523U, // SQXTUNv8i16 - 3223066266U, // SQXTUNv8i8 - 2147488556U, // SRHADDv16i8 - 2684883756U, // SRHADDv2i32 - 3222278956U, // SRHADDv4i16 - 1075057452U, // SRHADDv4i32 - 1612190508U, // SRHADDv8i16 - 3759936300U, // SRHADDv8i8 - 67404965U, // SRId - 2181051557U, // SRIv16i8_shift - 2718446757U, // SRIv2i32_shift - 571225253U, // SRIv2i64_shift - 3255841957U, // SRIv4i16_shift - 1108620453U, // SRIv4i32_shift - 1645753509U, // SRIv8i16_shift - 3793499301U, // SRIv8i8_shift - 2147489116U, // SRSHLv16i8 - 17048924U, // SRSHLv1i64 - 2684884316U, // SRSHLv2i32 - 537662812U, // SRSHLv2i64 - 3222279516U, // SRSHLv4i16 - 1075058012U, // SRSHLv4i32 - 1612191068U, // SRSHLv8i16 - 3759936860U, // SRSHLv8i8 - 17049501U, // SRSHRd - 2147489693U, // SRSHRv16i8_shift - 2684884893U, // SRSHRv2i32_shift - 537663389U, // SRSHRv2i64_shift - 3222280093U, // SRSHRv4i16_shift - 1075058589U, // SRSHRv4i32_shift - 1612191645U, // SRSHRv8i16_shift - 3759937437U, // SRSHRv8i8_shift - 67404288U, // SRSRAd - 2181050880U, // SRSRAv16i8_shift - 2718446080U, // SRSRAv2i32_shift - 571224576U, // SRSRAv2i64_shift - 3255841280U, // SRSRAv4i16_shift - 1108619776U, // SRSRAv4i32_shift - 1645752832U, // SRSRAv8i16_shift - 3793498624U, // SRSRAv8i8_shift - 2149060796U, // SSHLLv16i8_shift - 2685146486U, // SSHLLv2i32_shift - 3222541686U, // SSHLLv4i16_shift - 1074532540U, // SSHLLv4i32_shift - 1611927740U, // SSHLLv8i16_shift - 3759674742U, // SSHLLv8i8_shift - 2147489130U, // SSHLv16i8 - 17048938U, // SSHLv1i64 - 2684884330U, // SSHLv2i32 - 537662826U, // SSHLv2i64 - 3222279530U, // SSHLv4i16 - 1075058026U, // SSHLv4i32 - 1612191082U, // SSHLv8i16 - 3759936874U, // SSHLv8i8 - 17049515U, // SSHRd - 2147489707U, // SSHRv16i8_shift - 2684884907U, // SSHRv2i32_shift - 537663403U, // SSHRv2i64_shift - 3222280107U, // SSHRv4i16_shift - 1075058603U, // SSHRv4i32_shift - 1612191659U, // SSHRv8i16_shift - 3759937451U, // SSHRv8i8_shift - 67404302U, // SSRAd - 2181050894U, // SSRAv16i8_shift - 2718446094U, // SSRAv2i32_shift - 571224590U, // SSRAv2i64_shift - 3255841294U, // SSRAv4i16_shift - 1108619790U, // SSRAv4i32_shift - 1645752846U, // SSRAv8i16_shift - 3793498638U, // SSRAv8i8_shift - 2149060748U, // SSUBLv16i8_v8i16 - 2685146365U, // SSUBLv2i32_v2i64 - 3222541565U, // SSUBLv4i16_v4i32 - 1074532492U, // SSUBLv4i32_v2i64 - 1611927692U, // SSUBLv8i16_v4i32 - 3759674621U, // SSUBLv8i8_v8i16 - 1612190117U, // SSUBWv16i8_v8i16 - 537663913U, // SSUBWv2i32_v2i64 - 1075059113U, // SSUBWv4i16_v4i32 - 537661861U, // SSUBWv4i32_v2i64 - 1075057061U, // SSUBWv8i16_v4i32 - 1612192169U, // SSUBWv8i8_v8i16 - 36915U, // ST1Fourv16b - 3711027U, // ST1Fourv16b_POST - 45107U, // ST1Fourv1d - 3981363U, // ST1Fourv1d_POST - 53299U, // ST1Fourv2d - 3727411U, // ST1Fourv2d_POST - 61491U, // ST1Fourv2s - 3997747U, // ST1Fourv2s_POST - 69683U, // ST1Fourv4h - 4005939U, // ST1Fourv4h_POST - 77875U, // ST1Fourv4s - 3751987U, // ST1Fourv4s_POST - 86067U, // ST1Fourv8b - 4022323U, // ST1Fourv8b_POST - 94259U, // ST1Fourv8h - 3768371U, // ST1Fourv8h_POST - 36915U, // ST1Onev16b - 4235315U, // ST1Onev16b_POST - 45107U, // ST1Onev1d - 4505651U, // ST1Onev1d_POST - 53299U, // ST1Onev2d - 4251699U, // ST1Onev2d_POST - 61491U, // ST1Onev2s - 4522035U, // ST1Onev2s_POST - 69683U, // ST1Onev4h - 4530227U, // ST1Onev4h_POST - 77875U, // ST1Onev4s - 4276275U, // ST1Onev4s_POST - 86067U, // ST1Onev8b - 4546611U, // ST1Onev8b_POST - 94259U, // ST1Onev8h - 4292659U, // ST1Onev8h_POST - 36915U, // ST1Threev16b - 5546035U, // ST1Threev16b_POST - 45107U, // ST1Threev1d - 5816371U, // ST1Threev1d_POST - 53299U, // ST1Threev2d - 5562419U, // ST1Threev2d_POST - 61491U, // ST1Threev2s - 5832755U, // ST1Threev2s_POST - 69683U, // ST1Threev4h - 5840947U, // ST1Threev4h_POST - 77875U, // ST1Threev4s - 5586995U, // ST1Threev4s_POST - 86067U, // ST1Threev8b - 5857331U, // ST1Threev8b_POST - 94259U, // ST1Threev8h - 5603379U, // ST1Threev8h_POST - 36915U, // ST1Twov16b - 3973171U, // ST1Twov16b_POST - 45107U, // ST1Twov1d - 4243507U, // ST1Twov1d_POST - 53299U, // ST1Twov2d - 3989555U, // ST1Twov2d_POST - 61491U, // ST1Twov2s - 4259891U, // ST1Twov2s_POST - 69683U, // ST1Twov4h - 4268083U, // ST1Twov4h_POST - 77875U, // ST1Twov4s - 4014131U, // ST1Twov4s_POST - 86067U, // ST1Twov8b - 4284467U, // ST1Twov8b_POST - 94259U, // ST1Twov8h - 4030515U, // ST1Twov8h_POST - 147507U, // ST1i16 - 262246451U, // ST1i16_POST - 151603U, // ST1i32 - 279031859U, // ST1i32_POST - 155699U, // ST1i64 - 295817267U, // ST1i64_POST - 159795U, // ST1i8 - 312602675U, // ST1i8_POST - 37280U, // ST2Twov16b - 3973536U, // ST2Twov16b_POST - 53664U, // ST2Twov2d - 3989920U, // ST2Twov2d_POST - 61856U, // ST2Twov2s - 4260256U, // ST2Twov2s_POST - 70048U, // ST2Twov4h - 4268448U, // ST2Twov4h_POST - 78240U, // ST2Twov4s - 4014496U, // ST2Twov4s_POST - 86432U, // ST2Twov8b - 4284832U, // ST2Twov8b_POST - 94624U, // ST2Twov8h - 4030880U, // ST2Twov8h_POST - 147872U, // ST2i16 - 279024032U, // ST2i16_POST - 151968U, // ST2i32 - 295809440U, // ST2i32_POST - 156064U, // ST2i64 - 329372064U, // ST2i64_POST - 160160U, // ST2i8 - 262271392U, // ST2i8_POST - 37329U, // ST3Threev16b - 5546449U, // ST3Threev16b_POST - 53713U, // ST3Threev2d - 5562833U, // ST3Threev2d_POST - 61905U, // ST3Threev2s - 5833169U, // ST3Threev2s_POST - 70097U, // ST3Threev4h - 5841361U, // ST3Threev4h_POST - 78289U, // ST3Threev4s - 5587409U, // ST3Threev4s_POST - 86481U, // ST3Threev8b - 5857745U, // ST3Threev8b_POST - 94673U, // ST3Threev8h - 5603793U, // ST3Threev8h_POST - 147921U, // ST3i16 - 346132945U, // ST3i16_POST - 152017U, // ST3i32 - 362918353U, // ST3i32_POST - 156113U, // ST3i64 - 379703761U, // ST3i64_POST - 160209U, // ST3i8 - 396489169U, // ST3i8_POST - 37346U, // ST4Fourv16b - 3711458U, // ST4Fourv16b_POST - 53730U, // ST4Fourv2d - 3727842U, // ST4Fourv2d_POST - 61922U, // ST4Fourv2s - 3998178U, // ST4Fourv2s_POST - 70114U, // ST4Fourv4h - 4006370U, // ST4Fourv4h_POST - 78306U, // ST4Fourv4s - 3752418U, // ST4Fourv4s_POST - 86498U, // ST4Fourv8b - 4022754U, // ST4Fourv8b_POST - 94690U, // ST4Fourv8h - 3768802U, // ST4Fourv8h_POST - 147938U, // ST4i16 - 295801314U, // ST4i16_POST - 152034U, // ST4i32 - 329363938U, // ST4i32_POST - 156130U, // ST4i64 - 413258210U, // ST4i64_POST - 160226U, // ST4i8 - 279048674U, // ST4i8_POST - 26485317U, // STLRB - 26485814U, // STLRH - 26486716U, // STLRW - 26486716U, // STLRX - 17049437U, // STLXPW - 17049437U, // STLXPX - 553919101U, // STLXRB - 553919598U, // STLXRH - 553920528U, // STLXRW - 553920528U, // STLXRX - 553920285U, // STNPDi - 553920285U, // STNPQi - 553920285U, // STNPSi - 553920285U, // STNPWi - 553920285U, // STNPXi - 553920305U, // STPDi - 604276529U, // STPDpost - 604276529U, // STPDpre - 553920305U, // STPQi - 604276529U, // STPQpost - 604276529U, // STPQpre - 553920305U, // STPSi - 604276529U, // STPSpost - 604276529U, // STPSpre - 553920305U, // STPWi - 604276529U, // STPWpost - 604276529U, // STPWpre - 553920305U, // STPXi - 604276529U, // STPXpost - 604276529U, // STPXpre - 1150583379U, // STRBBpost - 76841555U, // STRBBpre - 26485331U, // STRBBroW - 26485331U, // STRBBroX - 26485331U, // STRBBui - 1150584806U, // STRBpost - 76842982U, // STRBpre - 26486758U, // STRBroW - 26486758U, // STRBroX - 26486758U, // STRBui - 1150584806U, // STRDpost - 76842982U, // STRDpre - 26486758U, // STRDroW - 26486758U, // STRDroX - 26486758U, // STRDui - 1150583876U, // STRHHpost - 76842052U, // STRHHpre - 26485828U, // STRHHroW - 26485828U, // STRHHroX - 26485828U, // STRHHui - 1150584806U, // STRHpost - 76842982U, // STRHpre - 26486758U, // STRHroW - 26486758U, // STRHroX - 26486758U, // STRHui - 1150584806U, // STRQpost - 76842982U, // STRQpre - 26486758U, // STRQroW - 26486758U, // STRQroX - 26486758U, // STRQui - 1150584806U, // STRSpost - 76842982U, // STRSpre - 26486758U, // STRSroW - 26486758U, // STRSroX - 26486758U, // STRSui - 1150584806U, // STRWpost - 76842982U, // STRWpre - 26486758U, // STRWroW - 26486758U, // STRWroX - 26486758U, // STRWui - 1150584806U, // STRXpost - 76842982U, // STRXpre - 26486758U, // STRXroW - 26486758U, // STRXroX - 26486758U, // STRXui - 26485337U, // STTRBi - 26485834U, // STTRHi - 26486763U, // STTRWi - 26486763U, // STTRXi - 26485351U, // STURBBi - 26486781U, // STURBi - 26486781U, // STURDi - 26485848U, // STURHHi - 26486781U, // STURHi - 26486781U, // STURQi - 26486781U, // STURSi - 26486781U, // STURWi - 26486781U, // STURXi - 17049444U, // STXPW - 17049444U, // STXPX - 553919109U, // STXRB - 553919606U, // STXRH - 553920535U, // STXRW - 553920535U, // STXRX - 537400855U, // SUBHNv2i64_v2i32 - 571748625U, // SUBHNv2i64_v4i32 - 1074796055U, // SUBHNv4i32_v4i16 - 1108881681U, // SUBHNv4i32_v8i16 - 1644179729U, // SUBHNv8i16_v16i8 - 1612453399U, // SUBHNv8i16_v8i8 - 17049650U, // SUBSWri + 2248196665U, // REV16Wr + 2248196665U, // REV16Xr + 68198969U, // REV16v16i8 + 2218828345U, // REV16v8i8 + 2248196219U, // REV32Xr + 68198523U, // REV32v16i8 + 69771387U, // REV32v4i16 + 70819963U, // REV32v8i16 + 2218827899U, // REV32v8i8 + 68198944U, // REV64v16i8 + 68723232U, // REV64v2i32 + 69771808U, // REV64v4i16 + 2217779744U, // REV64v4i32 + 70820384U, // REV64v8i16 + 2218828320U, // REV64v8i8 + 18130U, // REVB_ZPmZ_D + 2181588690U, // REVB_ZPmZ_H + 34514U, // REVB_ZPmZ_S + 19506U, // REVH_ZPmZ_D + 35890U, // REVH_ZPmZ_S + 21827U, // REVW_ZPmZ_D + 2248201140U, // REVWr + 2248201140U, // REVXr + 2315269044U, // REV_PP_B + 2348831668U, // REV_PP_D + 608727988U, // REV_PP_H + 2415956916U, // REV_PP_S + 2315269044U, // REV_ZZ_B + 2348831668U, // REV_ZZ_D + 608727988U, // REV_ZZ_H + 2415956916U, // REV_ZZ_S + 100714751U, // RMIF + 100716863U, // RORVWr + 100716863U, // RORVXr + 2282807663U, // RSHRNv16i8_shift + 2216210209U, // RSHRNv2i32_shift + 69775137U, // RSHRNv4i16_shift + 2284904815U, // RSHRNv4i32_shift + 137945455U, // RSHRNv8i16_shift + 2218831649U, // RSHRNv8i8_shift + 2216210136U, // RSUBHNv2i64_v2i32 + 2284904777U, // RSUBHNv2i64_v4i32 + 69775064U, // RSUBHNv4i32_v4i16 + 137945417U, // RSUBHNv4i32_v8i16 + 2282807625U, // RSUBHNv8i16_v16i8 + 2218831576U, // RSUBHNv8i16_v8i8 + 137945243U, // SABALv16i8_v8i16 + 2283859106U, // SABALv2i32_v2i64 + 137424034U, // SABALv4i16_v4i32 + 136372379U, // SABALv4i32_v2i64 + 2284904603U, // SABALv8i16_v4i32 + 2285431970U, // SABALv8i8_v8i16 + 135324269U, // SABAv16i8 + 2283332205U, // SABAv2i32 + 136897133U, // SABAv4i16 + 137421421U, // SABAv4i32 + 2285429357U, // SABAv8i16 + 2285953645U, // SABAv8i8 + 70820053U, // SABDLv16i8_v8i16 + 2216734028U, // SABDLv2i32_v2i64 + 70298956U, // SABDLv4i16_v4i32 + 69247189U, // SABDLv4i32_v2i64 + 2217779413U, // SABDLv8i16_v4i32 + 2218306892U, // SABDLv8i8_v8i16 + 302000042U, // SABD_ZPmZ_B + 302008234U, // SABD_ZPmZ_D + 2186307498U, // SABD_ZPmZ_H + 302024618U, // SABD_ZPmZ_S + 68200362U, // SABDv16i8 + 2216208298U, // SABDv2i32 + 69773226U, // SABDv4i16 + 70297514U, // SABDv4i32 + 2218305450U, // SABDv8i16 + 2218829738U, // SABDv8i8 + 137949153U, // SADALPv16i8_v8i16 + 162066401U, // SADALPv2i32_v1i64 + 135852001U, // SADALPv4i16_v2i32 + 2283859937U, // SADALPv4i32_v2i64 + 137424865U, // SADALPv8i16_v4i32 + 2284384225U, // SADALPv8i8_v4i16 + 70823921U, // SADDLPv16i8_v8i16 + 94941169U, // SADDLPv2i32_v1i64 + 68726769U, // SADDLPv4i16_v2i32 + 2216734705U, // SADDLPv4i32_v2i64 + 70299633U, // SADDLPv8i16_v4i32 + 2217258993U, // SADDLPv8i8_v4i16 + 67163083U, // SADDLVv16i8v + 67163083U, // SADDLVv4i16v + 2214646731U, // SADDLVv4i32v + 67163083U, // SADDLVv8i16v + 2214646731U, // SADDLVv8i8v + 70820069U, // SADDLv16i8_v8i16 + 2216734066U, // SADDLv2i32_v2i64 + 70298994U, // SADDLv4i16_v4i32 + 69247205U, // SADDLv4i32_v2i64 + 2217779429U, // SADDLv8i16_v4i32 + 2218306930U, // SADDLv8i8_v8i16 + 302044064U, // SADDV_VPZ_B + 302044064U, // SADDV_VPZ_H + 302044064U, // SADDV_VPZ_S + 2218303982U, // SADDWv16i8_v8i16 + 2216735941U, // SADDWv2i32_v2i64 + 70300869U, // SADDWv4i16_v4i32 + 2216731118U, // SADDWv4i32_v2i64 + 70296046U, // SADDWv8i16_v4i32 + 2218308805U, // SADDWv8i8_v8i16 + 100717072U, // SBCSWr + 100717072U, // SBCSXr + 100714257U, // SBCWr + 100714257U, // SBCXr + 100716193U, // SBFMWri + 100716193U, // SBFMXri + 100714757U, // SCVTFSWDri + 100714757U, // SCVTFSWHri + 100714757U, // SCVTFSWSri + 100714757U, // SCVTFSXDri + 100714757U, // SCVTFSXHri + 100714757U, // SCVTFSXSri + 2248198405U, // SCVTFUWDri + 2248198405U, // SCVTFUWHri + 2248198405U, // SCVTFUWSri + 2248198405U, // SCVTFUXDri + 2248198405U, // SCVTFUXHri + 2248198405U, // SCVTFUXSri + 18693U, // SCVTF_ZPmZ_DtoD + 2181589253U, // SCVTF_ZPmZ_DtoH + 35077U, // SCVTF_ZPmZ_DtoS + 2181589253U, // SCVTF_ZPmZ_HtoH + 18693U, // SCVTF_ZPmZ_StoD + 2181589253U, // SCVTF_ZPmZ_StoH + 35077U, // SCVTF_ZPmZ_StoS + 100714757U, // SCVTFd + 100714757U, // SCVTFh + 100714757U, // SCVTFs + 2248198405U, // SCVTFv1i16 + 2248198405U, // SCVTFv1i32 + 2248198405U, // SCVTFv1i64 + 68724997U, // SCVTFv2f32 + 2216732933U, // SCVTFv2f64 + 2216208645U, // SCVTFv2i32_shift + 2216732933U, // SCVTFv2i64_shift + 69773573U, // SCVTFv4f16 + 2217781509U, // SCVTFv4f32 + 69773573U, // SCVTFv4i16_shift + 70297861U, // SCVTFv4i32_shift + 70822149U, // SCVTFv8f16 + 2218305797U, // SCVTFv8i16_shift + 302010794U, // SDIVR_ZPmZ_D + 302027178U, // SDIVR_ZPmZ_S + 100717503U, // SDIVWr + 100717503U, // SDIVXr + 302011327U, // SDIV_ZPmZ_D + 302027711U, // SDIV_ZPmZ_S + 3422573357U, // SDOT_ZZZI_D + 3456144173U, // SDOT_ZZZI_S + 3422573357U, // SDOT_ZZZ_D + 3456144173U, // SDOT_ZZZ_S + 137425709U, // SDOTlanev16i8 + 2283336493U, // SDOTlanev8i8 + 137425709U, // SDOTv16i8 + 2283336493U, // SDOTv8i8 + 302001538U, // SEL_PPPP + 302001538U, // SEL_ZPZZ_B + 302009730U, // SEL_ZPZZ_D + 2387635586U, // SEL_ZPZZ_H + 302026114U, // SEL_ZPZZ_S + 6341169U, // SETF16 + 6341184U, // SETF8 + 5959U, // SETFFR + 369190666U, // SHA1Crrr + 2248198439U, // SHA1Hrr + 369192602U, // SHA1Mrrr + 369192878U, // SHA1Prrr + 137420801U, // SHA1SU0rrr + 2284904523U, // SHA1SU1rr + 369189009U, // SHA256H2rrr + 369191311U, // SHA256Hrrr + 2284904469U, // SHA256SU0rr + 137420895U, // SHA256SU1rrr + 369191258U, // SHA512H + 369188999U, // SHA512H2 + 2216730634U, // SHA512SU0 + 2283855956U, // SHA512SU1 + 68200449U, // SHADDv16i8 + 2216208385U, // SHADDv2i32 + 69773313U, // SHADDv4i16 + 70297601U, // SHADDv4i32 + 2218305537U, // SHADDv8i16 + 2218829825U, // SHADDv8i8 + 70820086U, // SHLLv16i8 + 2216734152U, // SHLLv2i32 + 70299080U, // SHLLv4i16 + 2216730870U, // SHLLv4i32 + 70295798U, // SHLLv8i16 + 2218307016U, // SHLLv8i8 + 100715921U, // SHLd + 68201873U, // SHLv16i8_shift + 2216209809U, // SHLv2i32_shift + 2216734097U, // SHLv2i64_shift + 69774737U, // SHLv4i16_shift + 70299025U, // SHLv4i32_shift + 2218306961U, // SHLv8i16_shift + 2218831249U, // SHLv8i8_shift + 2282807645U, // SHRNv16i8_shift + 2216210193U, // SHRNv2i32_shift + 69775121U, // SHRNv4i16_shift + 2284904797U, // SHRNv4i32_shift + 137945437U, // SHRNv8i16_shift + 2218831633U, // SHRNv8i8_shift + 68200103U, // SHSUBv16i8 + 2216208039U, // SHSUBv2i32 + 69772967U, // SHSUBv4i16 + 70297255U, // SHSUBv4i32 + 2218305191U, // SHSUBv8i16 + 2218829479U, // SHSUBv8i8 + 369192057U, // SLId + 135326841U, // SLIv16i8_shift + 2283334777U, // SLIv2i32_shift + 2283859065U, // SLIv2i64_shift + 136899705U, // SLIv4i16_shift + 137423993U, // SLIv4i32_shift + 2285431929U, // SLIv8i16_shift + 2285956217U, // SLIv8i8_shift + 137420906U, // SM3PARTW1 + 137421310U, // SM3PARTW2 + 70295614U, // SM3SS1 + 137421383U, // SM3TT1A + 137421720U, // SM3TT1B + 137421392U, // SM3TT2A + 137421749U, // SM3TT2B + 2217781339U, // SM4E + 70301097U, // SM4ENCKEY + 100715874U, // SMADDLrrr + 68202617U, // SMAXPv16i8 + 2216210553U, // SMAXPv2i32 + 69775481U, // SMAXPv4i16 + 70299769U, // SMAXPv4i32 + 2218307705U, // SMAXPv8i16 + 2218831993U, // SMAXPv8i8 + 302044200U, // SMAXV_VPZ_B + 302044200U, // SMAXV_VPZ_D + 302044200U, // SMAXV_VPZ_H + 302044200U, // SMAXV_VPZ_S + 67163176U, // SMAXVv16i8v + 67163176U, // SMAXVv4i16v + 2214646824U, // SMAXVv4i32v + 67163176U, // SMAXVv8i16v + 2214646824U, // SMAXVv8i8v + 167785823U, // SMAX_ZI_B + 201348447U, // SMAX_ZI_D + 239629663U, // SMAX_ZI_H + 268473695U, // SMAX_ZI_S + 302003551U, // SMAX_ZPmZ_B + 302011743U, // SMAX_ZPmZ_D + 2186311007U, // SMAX_ZPmZ_H + 302028127U, // SMAX_ZPmZ_S + 68203871U, // SMAXv16i8 + 2216211807U, // SMAXv2i32 + 69776735U, // SMAXv4i16 + 70301023U, // SMAXv4i32 + 2218308959U, // SMAXv8i16 + 2218833247U, // SMAXv8i8 + 75562U, // SMC + 68202541U, // SMINPv16i8 + 2216210477U, // SMINPv2i32 + 69775405U, // SMINPv4i16 + 70299693U, // SMINPv4i32 + 2218307629U, // SMINPv8i16 + 2218831917U, // SMINPv8i8 + 302044148U, // SMINV_VPZ_B + 302044148U, // SMINV_VPZ_D + 302044148U, // SMINV_VPZ_H + 302044148U, // SMINV_VPZ_S + 67163124U, // SMINVv16i8v + 67163124U, // SMINVv4i16v + 2214646772U, // SMINVv4i32v + 67163124U, // SMINVv8i16v + 2214646772U, // SMINVv8i8v + 167784176U, // SMIN_ZI_B + 201346800U, // SMIN_ZI_D + 239628016U, // SMIN_ZI_H + 268472048U, // SMIN_ZI_S + 302001904U, // SMIN_ZPmZ_B + 302010096U, // SMIN_ZPmZ_D + 2186309360U, // SMIN_ZPmZ_H + 302026480U, // SMIN_ZPmZ_S + 68202224U, // SMINv16i8 + 2216210160U, // SMINv2i32 + 69775088U, // SMINv4i16 + 70299376U, // SMINv4i32 + 2218307312U, // SMINv8i16 + 2218831600U, // SMINv8i8 + 137945269U, // SMLALv16i8_v8i16 + 2283859138U, // SMLALv2i32_indexed + 2283859138U, // SMLALv2i32_v2i64 + 137424066U, // SMLALv4i16_indexed + 137424066U, // SMLALv4i16_v4i32 + 136372405U, // SMLALv4i32_indexed + 136372405U, // SMLALv4i32_v2i64 + 2284904629U, // SMLALv8i16_indexed + 2284904629U, // SMLALv8i16_v4i32 + 2285432002U, // SMLALv8i8_v8i16 + 137945393U, // SMLSLv16i8_v8i16 + 2283859517U, // SMLSLv2i32_indexed + 2283859517U, // SMLSLv2i32_v2i64 + 137424445U, // SMLSLv4i16_indexed + 137424445U, // SMLSLv4i16_v4i32 + 136372529U, // SMLSLv4i32_indexed + 136372529U, // SMLSLv4i32_v2i64 + 2284904753U, // SMLSLv8i16_indexed + 2284904753U, // SMLSLv8i16_v4i32 + 2285432381U, // SMLSLv8i8_v8i16 + 67163151U, // SMOVvi16to32 + 67163151U, // SMOVvi16to64 + 2214646799U, // SMOVvi32to64 + 2214646799U, // SMOVvi8to32 + 2214646799U, // SMOVvi8to64 + 100715822U, // SMSUBLrrr + 302000880U, // SMULH_ZPmZ_B + 302009072U, // SMULH_ZPmZ_D + 2186308336U, // SMULH_ZPmZ_H + 302025456U, // SMULH_ZPmZ_S + 100715248U, // SMULHrr + 70820119U, // SMULLv16i8_v8i16 + 2216734181U, // SMULLv2i32_indexed + 2216734181U, // SMULLv2i32_v2i64 + 70299109U, // SMULLv4i16_indexed + 70299109U, // SMULLv4i16_v4i32 + 69247255U, // SMULLv4i32_indexed + 69247255U, // SMULLv4i32_v2i64 + 2217779479U, // SMULLv8i16_indexed + 2217779479U, // SMULLv8i16_v4i32 + 2218307045U, // SMULLv8i8_v8i16 + 302000225U, // SPLICE_ZPZ_B + 302008417U, // SPLICE_ZPZ_D + 2387634273U, // SPLICE_ZPZ_H + 302024801U, // SPLICE_ZPZ_S + 68202996U, // SQABSv16i8 + 2248200692U, // SQABSv1i16 + 2248200692U, // SQABSv1i32 + 2248200692U, // SQABSv1i64 + 2248200692U, // SQABSv1i8 + 68727284U, // SQABSv2i32 + 2216735220U, // SQABSv2i64 + 69775860U, // SQABSv4i16 + 2217783796U, // SQABSv4i32 + 70824436U, // SQABSv8i16 + 2218832372U, // SQABSv8i8 + 167782431U, // SQADD_ZI_B + 201345055U, // SQADD_ZI_D + 239626271U, // SQADD_ZI_H + 268470303U, // SQADD_ZI_S + 167782431U, // SQADD_ZZZ_B + 201345055U, // SQADD_ZZZ_D + 2387109919U, // SQADD_ZZZ_H + 268470303U, // SQADD_ZZZ_S + 68200479U, // SQADDv16i8 + 100714527U, // SQADDv1i16 + 100714527U, // SQADDv1i32 + 100714527U, // SQADDv1i64 + 100714527U, // SQADDv1i8 + 2216208415U, // SQADDv2i32 + 2216732703U, // SQADDv2i64 + 69773343U, // SQADDv4i16 + 70297631U, // SQADDv4i32 + 2218305567U, // SQADDv8i16 + 2218829855U, // SQADDv8i8 + 536921165U, // SQDECB_XPiI + 1342227533U, // SQDECB_XPiWdI + 536922045U, // SQDECD_XPiI + 1342228413U, // SQDECD_XPiWdI + 536889277U, // SQDECD_ZPiI + 536922629U, // SQDECH_XPiI + 1342228997U, // SQDECH_XPiWdI + 6842885U, // SQDECH_ZPiI + 167825333U, // SQDECP_XPWd_B + 201379765U, // SQDECP_XPWd_D + 570478517U, // SQDECP_XPWd_H + 268488629U, // SQDECP_XPWd_S + 2315308981U, // SQDECP_XP_B + 2348863413U, // SQDECP_XP_D + 2717962165U, // SQDECP_XP_H + 2415972277U, // SQDECP_XP_S + 2147504053U, // SQDECP_ZP_D + 604532661U, // SQDECP_ZP_H + 2147520437U, // SQDECP_ZP_S + 536925349U, // SQDECW_XPiI + 1342231717U, // SQDECW_XPiWdI + 536908965U, // SQDECW_ZPiI + 369192121U, // SQDMLALi16 + 369192121U, // SQDMLALi32 + 369192121U, // SQDMLALv1i32_indexed + 369192121U, // SQDMLALv1i64_indexed + 2283859129U, // SQDMLALv2i32_indexed + 2283859129U, // SQDMLALv2i32_v2i64 + 137424057U, // SQDMLALv4i16_indexed + 137424057U, // SQDMLALv4i16_v4i32 + 136372395U, // SQDMLALv4i32_indexed + 136372395U, // SQDMLALv4i32_v2i64 + 2284904619U, // SQDMLALv8i16_indexed + 2284904619U, // SQDMLALv8i16_v4i32 + 369192500U, // SQDMLSLi16 + 369192500U, // SQDMLSLi32 + 369192500U, // SQDMLSLv1i32_indexed + 369192500U, // SQDMLSLv1i64_indexed + 2283859508U, // SQDMLSLv2i32_indexed + 2283859508U, // SQDMLSLv2i32_v2i64 + 137424436U, // SQDMLSLv4i16_indexed + 137424436U, // SQDMLSLv4i16_v4i32 + 136372519U, // SQDMLSLv4i32_indexed + 136372519U, // SQDMLSLv4i32_v2i64 + 2284904743U, // SQDMLSLv8i16_indexed + 2284904743U, // SQDMLSLv8i16_v4i32 + 100715229U, // SQDMULHv1i16 + 100715229U, // SQDMULHv1i16_indexed + 100715229U, // SQDMULHv1i32 + 100715229U, // SQDMULHv1i32_indexed + 2216209117U, // SQDMULHv2i32 + 2216209117U, // SQDMULHv2i32_indexed + 69774045U, // SQDMULHv4i16 + 69774045U, // SQDMULHv4i16_indexed + 70298333U, // SQDMULHv4i32 + 70298333U, // SQDMULHv4i32_indexed + 2218306269U, // SQDMULHv8i16 + 2218306269U, // SQDMULHv8i16_indexed + 100715989U, // SQDMULLi16 + 100715989U, // SQDMULLi32 + 100715989U, // SQDMULLv1i32_indexed + 100715989U, // SQDMULLv1i64_indexed + 2216734165U, // SQDMULLv2i32_indexed + 2216734165U, // SQDMULLv2i32_v2i64 + 70299093U, // SQDMULLv4i16_indexed + 70299093U, // SQDMULLv4i16_v4i32 + 69247237U, // SQDMULLv4i32_indexed + 69247237U, // SQDMULLv4i32_v2i64 + 2217779461U, // SQDMULLv8i16_indexed + 2217779461U, // SQDMULLv8i16_v4i32 + 536921181U, // SQINCB_XPiI + 1342227549U, // SQINCB_XPiWdI + 536922061U, // SQINCD_XPiI + 1342228429U, // SQINCD_XPiWdI + 536889293U, // SQINCD_ZPiI + 536922645U, // SQINCH_XPiI + 1342229013U, // SQINCH_XPiWdI + 6842901U, // SQINCH_ZPiI + 167825349U, // SQINCP_XPWd_B + 201379781U, // SQINCP_XPWd_D + 570478533U, // SQINCP_XPWd_H + 268488645U, // SQINCP_XPWd_S + 2315308997U, // SQINCP_XP_B + 2348863429U, // SQINCP_XP_D + 2717962181U, // SQINCP_XP_H + 2415972293U, // SQINCP_XP_S + 2147504069U, // SQINCP_ZP_D + 604532677U, // SQINCP_ZP_H + 2147520453U, // SQINCP_ZP_S + 536925365U, // SQINCW_XPiI + 1342231733U, // SQINCW_XPiWdI + 536908981U, // SQINCW_ZPiI + 68200729U, // SQNEGv16i8 + 2248198425U, // SQNEGv1i16 + 2248198425U, // SQNEGv1i32 + 2248198425U, // SQNEGv1i64 + 2248198425U, // SQNEGv1i8 + 68725017U, // SQNEGv2i32 + 2216732953U, // SQNEGv2i64 + 69773593U, // SQNEGv4i16 + 2217781529U, // SQNEGv4i32 + 70822169U, // SQNEGv8i16 + 2218830105U, // SQNEGv8i8 + 369191329U, // SQRDMLAHi16_indexed + 369191329U, // SQRDMLAHi32_indexed + 369191329U, // SQRDMLAHv1i16 + 369191329U, // SQRDMLAHv1i32 + 2283334049U, // SQRDMLAHv2i32 + 2283334049U, // SQRDMLAHv2i32_indexed + 136898977U, // SQRDMLAHv4i16 + 136898977U, // SQRDMLAHv4i16_indexed + 137423265U, // SQRDMLAHv4i32 + 137423265U, // SQRDMLAHv4i32_indexed + 2285431201U, // SQRDMLAHv8i16 + 2285431201U, // SQRDMLAHv8i16_indexed + 369191909U, // SQRDMLSHi16_indexed + 369191909U, // SQRDMLSHi32_indexed + 369191909U, // SQRDMLSHv1i16 + 369191909U, // SQRDMLSHv1i32 + 2283334629U, // SQRDMLSHv2i32 + 2283334629U, // SQRDMLSHv2i32_indexed + 136899557U, // SQRDMLSHv4i16 + 136899557U, // SQRDMLSHv4i16_indexed + 137423845U, // SQRDMLSHv4i32 + 137423845U, // SQRDMLSHv4i32_indexed + 2285431781U, // SQRDMLSHv8i16 + 2285431781U, // SQRDMLSHv8i16_indexed + 100715238U, // SQRDMULHv1i16 + 100715238U, // SQRDMULHv1i16_indexed + 100715238U, // SQRDMULHv1i32 + 100715238U, // SQRDMULHv1i32_indexed + 2216209126U, // SQRDMULHv2i32 + 2216209126U, // SQRDMULHv2i32_indexed + 69774054U, // SQRDMULHv4i16 + 69774054U, // SQRDMULHv4i16_indexed + 70298342U, // SQRDMULHv4i32 + 70298342U, // SQRDMULHv4i32_indexed + 2218306278U, // SQRDMULHv8i16 + 2218306278U, // SQRDMULHv8i16_indexed + 68201885U, // SQRSHLv16i8 + 100715933U, // SQRSHLv1i16 + 100715933U, // SQRSHLv1i32 + 100715933U, // SQRSHLv1i64 + 100715933U, // SQRSHLv1i8 + 2216209821U, // SQRSHLv2i32 + 2216734109U, // SQRSHLv2i64 + 69774749U, // SQRSHLv4i16 + 70299037U, // SQRSHLv4i32 + 2218306973U, // SQRSHLv8i16 + 2218831261U, // SQRSHLv8i8 + 100716319U, // SQRSHRNb + 100716319U, // SQRSHRNh + 100716319U, // SQRSHRNs + 2282807661U, // SQRSHRNv16i8_shift + 2216210207U, // SQRSHRNv2i32_shift + 69775135U, // SQRSHRNv4i16_shift + 2284904813U, // SQRSHRNv4i32_shift + 137945453U, // SQRSHRNv8i16_shift + 2218831647U, // SQRSHRNv8i8_shift + 100716380U, // SQRSHRUNb + 100716380U, // SQRSHRUNh + 100716380U, // SQRSHRUNs + 2282807721U, // SQRSHRUNv16i8_shift + 2216210268U, // SQRSHRUNv2i32_shift + 69775196U, // SQRSHRUNv4i16_shift + 2284904873U, // SQRSHRUNv4i32_shift + 137945513U, // SQRSHRUNv8i16_shift + 2218831708U, // SQRSHRUNv8i8_shift + 100717425U, // SQSHLUb + 100717425U, // SQSHLUd + 100717425U, // SQSHLUh + 100717425U, // SQSHLUs + 68203377U, // SQSHLUv16i8_shift + 2216211313U, // SQSHLUv2i32_shift + 2216735601U, // SQSHLUv2i64_shift + 69776241U, // SQSHLUv4i16_shift + 70300529U, // SQSHLUv4i32_shift + 2218308465U, // SQSHLUv8i16_shift + 2218832753U, // SQSHLUv8i8_shift + 100715919U, // SQSHLb + 100715919U, // SQSHLd + 100715919U, // SQSHLh + 100715919U, // SQSHLs + 68201871U, // SQSHLv16i8 + 68201871U, // SQSHLv16i8_shift + 100715919U, // SQSHLv1i16 + 100715919U, // SQSHLv1i32 + 100715919U, // SQSHLv1i64 + 100715919U, // SQSHLv1i8 + 2216209807U, // SQSHLv2i32 + 2216209807U, // SQSHLv2i32_shift + 2216734095U, // SQSHLv2i64 + 2216734095U, // SQSHLv2i64_shift + 69774735U, // SQSHLv4i16 + 69774735U, // SQSHLv4i16_shift + 70299023U, // SQSHLv4i32 + 70299023U, // SQSHLv4i32_shift + 2218306959U, // SQSHLv8i16 + 2218306959U, // SQSHLv8i16_shift + 2218831247U, // SQSHLv8i8 + 2218831247U, // SQSHLv8i8_shift + 100716303U, // SQSHRNb + 100716303U, // SQSHRNh + 100716303U, // SQSHRNs + 2282807643U, // SQSHRNv16i8_shift + 2216210191U, // SQSHRNv2i32_shift + 69775119U, // SQSHRNv4i16_shift + 2284904795U, // SQSHRNv4i32_shift + 137945435U, // SQSHRNv8i16_shift + 2218831631U, // SQSHRNv8i8_shift + 100716371U, // SQSHRUNb + 100716371U, // SQSHRUNh + 100716371U, // SQSHRUNs + 2282807711U, // SQSHRUNv16i8_shift + 2216210259U, // SQSHRUNv2i32_shift + 69775187U, // SQSHRUNv4i16_shift + 2284904863U, // SQSHRUNv4i32_shift + 137945503U, // SQSHRUNv8i16_shift + 2218831699U, // SQSHRUNv8i8_shift + 167782084U, // SQSUB_ZI_B + 201344708U, // SQSUB_ZI_D + 239625924U, // SQSUB_ZI_H + 268469956U, // SQSUB_ZI_S + 167782084U, // SQSUB_ZZZ_B + 201344708U, // SQSUB_ZZZ_D + 2387109572U, // SQSUB_ZZZ_H + 268469956U, // SQSUB_ZZZ_S + 68200132U, // SQSUBv16i8 + 100714180U, // SQSUBv1i16 + 100714180U, // SQSUBv1i32 + 100714180U, // SQSUBv1i64 + 100714180U, // SQSUBv1i8 + 2216208068U, // SQSUBv2i32 + 2216732356U, // SQSUBv2i64 + 69772996U, // SQSUBv4i16 + 70297284U, // SQSUBv4i32 + 2218305220U, // SQSUBv8i16 + 2218829508U, // SQSUBv8i8 + 135324047U, // SQXTNv16i8 + 2248200005U, // SQXTNv1i16 + 2248200005U, // SQXTNv1i32 + 2248200005U, // SQXTNv1i8 + 2216210245U, // SQXTNv2i32 + 2217258821U, // SQXTNv4i16 + 2284904847U, // SQXTNv4i32 + 2285429135U, // SQXTNv8i16 + 71348037U, // SQXTNv8i8 + 135324084U, // SQXTUNv16i8 + 2248200038U, // SQXTUNv1i16 + 2248200038U, // SQXTUNv1i32 + 2248200038U, // SQXTUNv1i8 + 2216210278U, // SQXTUNv2i32 + 2217258854U, // SQXTUNv4i16 + 2284904884U, // SQXTUNv4i32 + 2285429172U, // SQXTUNv8i16 + 71348070U, // SQXTUNv8i8 + 68200433U, // SRHADDv16i8 + 2216208369U, // SRHADDv2i32 + 69773297U, // SRHADDv4i16 + 70297585U, // SRHADDv4i32 + 2218305521U, // SRHADDv8i16 + 2218829809U, // SRHADDv8i8 + 369192068U, // SRId + 135326852U, // SRIv16i8_shift + 2283334788U, // SRIv2i32_shift + 2283859076U, // SRIv2i64_shift + 136899716U, // SRIv4i16_shift + 137424004U, // SRIv4i32_shift + 2285431940U, // SRIv8i16_shift + 2285956228U, // SRIv8i8_shift + 68201901U, // SRSHLv16i8 + 100715949U, // SRSHLv1i64 + 2216209837U, // SRSHLv2i32 + 2216734125U, // SRSHLv2i64 + 69774765U, // SRSHLv4i16 + 70299053U, // SRSHLv4i32 + 2218306989U, // SRSHLv8i16 + 2218831277U, // SRSHLv8i8 + 100716794U, // SRSHRd + 68202746U, // SRSHRv16i8_shift + 2216210682U, // SRSHRv2i32_shift + 2216734970U, // SRSHRv2i64_shift + 69775610U, // SRSHRv4i16_shift + 70299898U, // SRSHRv4i32_shift + 2218307834U, // SRSHRv8i16_shift + 2218832122U, // SRSHRv8i8_shift + 369189634U, // SRSRAd + 135324418U, // SRSRAv16i8_shift + 2283332354U, // SRSRAv2i32_shift + 2283856642U, // SRSRAv2i64_shift + 136897282U, // SRSRAv4i16_shift + 137421570U, // SRSRAv4i32_shift + 2285429506U, // SRSRAv8i16_shift + 2285953794U, // SRSRAv8i8_shift + 70820085U, // SSHLLv16i8_shift + 2216734151U, // SSHLLv2i32_shift + 70299079U, // SSHLLv4i16_shift + 69247221U, // SSHLLv4i32_shift + 2217779445U, // SSHLLv8i16_shift + 2218307015U, // SSHLLv8i8_shift + 68201915U, // SSHLv16i8 + 100715963U, // SSHLv1i64 + 2216209851U, // SSHLv2i32 + 2216734139U, // SSHLv2i64 + 69774779U, // SSHLv4i16 + 70299067U, // SSHLv4i32 + 2218307003U, // SSHLv8i16 + 2218831291U, // SSHLv8i8 + 100716808U, // SSHRd + 68202760U, // SSHRv16i8_shift + 2216210696U, // SSHRv2i32_shift + 2216734984U, // SSHRv2i64_shift + 69775624U, // SSHRv4i16_shift + 70299912U, // SSHRv4i32_shift + 2218307848U, // SSHRv8i16_shift + 2218832136U, // SSHRv8i8_shift + 369189648U, // SSRAd + 135324432U, // SSRAv16i8_shift + 2283332368U, // SSRAv2i32_shift + 2283856656U, // SSRAv2i64_shift + 136897296U, // SSRAv4i16_shift + 137421584U, // SSRAv4i32_shift + 2285429520U, // SSRAv8i16_shift + 2285953808U, // SSRAv8i8_shift + 374997906U, // SST1B_D + 878314386U, // SST1B_D_IMM + 374997906U, // SST1B_D_SXTW + 374997906U, // SST1B_D_UXTW + 811213714U, // SST1B_S_IMM + 375006098U, // SST1B_S_SXTW + 375006098U, // SST1B_S_UXTW + 374998886U, // SST1D + 878315366U, // SST1D_IMM + 374998886U, // SST1D_SCALED + 374998886U, // SST1D_SXTW + 374998886U, // SST1D_SXTW_SCALED + 374998886U, // SST1D_UXTW + 374998886U, // SST1D_UXTW_SCALED + 374999380U, // SST1H_D + 3025799508U, // SST1H_D_IMM + 374999380U, // SST1H_D_SCALED + 374999380U, // SST1H_D_SXTW + 374999380U, // SST1H_D_SXTW_SCALED + 374999380U, // SST1H_D_UXTW + 374999380U, // SST1H_D_UXTW_SCALED + 2958698836U, // SST1H_S_IMM + 375007572U, // SST1H_S_SXTW + 375007572U, // SST1H_S_SXTW_SCALED + 375007572U, // SST1H_S_UXTW + 375007572U, // SST1H_S_UXTW_SCALED + 375002204U, // SST1W_D + 878318684U, // SST1W_D_IMM + 375002204U, // SST1W_D_SCALED + 375002204U, // SST1W_D_SXTW + 375002204U, // SST1W_D_SXTW_SCALED + 375002204U, // SST1W_D_UXTW + 375002204U, // SST1W_D_UXTW_SCALED + 811218012U, // SST1W_IMM + 375010396U, // SST1W_SXTW + 375010396U, // SST1W_SXTW_SCALED + 375010396U, // SST1W_UXTW + 375010396U, // SST1W_UXTW_SCALED + 70820037U, // SSUBLv16i8_v8i16 + 2216734014U, // SSUBLv2i32_v2i64 + 70298942U, // SSUBLv4i16_v4i32 + 69247173U, // SSUBLv4i32_v2i64 + 2217779397U, // SSUBLv8i16_v4i32 + 2218306878U, // SSUBLv8i8_v8i16 + 2218303966U, // SSUBWv16i8_v8i16 + 2216735886U, // SSUBWv2i32_v2i64 + 70300814U, // SSUBWv4i16_v4i32 + 2216731102U, // SSUBWv4i32_v2i64 + 70296030U, // SSUBWv8i16_v4i32 + 2218308750U, // SSUBWv8i8_v8i16 + 375022482U, // ST1B + 374997906U, // ST1B_D + 374997906U, // ST1B_D_IMM + 375030674U, // ST1B_H + 375030674U, // ST1B_H_IMM + 375022482U, // ST1B_IMM + 375006098U, // ST1B_S + 375006098U, // ST1B_S_IMM + 374998886U, // ST1D + 374998886U, // ST1D_IMM + 172102U, // ST1Fourv16b + 13287494U, // ST1Fourv16b_POST + 188486U, // ST1Fourv1d + 13828166U, // ST1Fourv1d_POST + 204870U, // ST1Fourv2d + 13320262U, // ST1Fourv2d_POST + 221254U, // ST1Fourv2s + 13860934U, // ST1Fourv2s_POST + 237638U, // ST1Fourv4h + 13877318U, // ST1Fourv4h_POST + 254022U, // ST1Fourv4s + 13369414U, // ST1Fourv4s_POST + 270406U, // ST1Fourv8b + 13910086U, // ST1Fourv8b_POST + 286790U, // ST1Fourv8h + 13402182U, // ST1Fourv8h_POST + 375032148U, // ST1H + 374999380U, // ST1H_D + 374999380U, // ST1H_D_IMM + 375032148U, // ST1H_IMM + 375007572U, // ST1H_S + 375007572U, // ST1H_S_IMM + 172102U, // ST1Onev16b + 14336070U, // ST1Onev16b_POST + 188486U, // ST1Onev1d + 14876742U, // ST1Onev1d_POST + 204870U, // ST1Onev2d + 14368838U, // ST1Onev2d_POST + 221254U, // ST1Onev2s + 14909510U, // ST1Onev2s_POST + 237638U, // ST1Onev4h + 14925894U, // ST1Onev4h_POST + 254022U, // ST1Onev4s + 14417990U, // ST1Onev4s_POST + 270406U, // ST1Onev8b + 14958662U, // ST1Onev8b_POST + 286790U, // ST1Onev8h + 14450758U, // ST1Onev8h_POST + 172102U, // ST1Threev16b + 16957510U, // ST1Threev16b_POST + 188486U, // ST1Threev1d + 17498182U, // ST1Threev1d_POST + 204870U, // ST1Threev2d + 16990278U, // ST1Threev2d_POST + 221254U, // ST1Threev2s + 17530950U, // ST1Threev2s_POST + 237638U, // ST1Threev4h + 17547334U, // ST1Threev4h_POST + 254022U, // ST1Threev4s + 17039430U, // ST1Threev4s_POST + 270406U, // ST1Threev8b + 17580102U, // ST1Threev8b_POST + 286790U, // ST1Threev8h + 17072198U, // ST1Threev8h_POST + 172102U, // ST1Twov16b + 13811782U, // ST1Twov16b_POST + 188486U, // ST1Twov1d + 14352454U, // ST1Twov1d_POST + 204870U, // ST1Twov2d + 13844550U, // ST1Twov2d_POST + 221254U, // ST1Twov2s + 14385222U, // ST1Twov2s_POST + 237638U, // ST1Twov4h + 14401606U, // ST1Twov4h_POST + 254022U, // ST1Twov4s + 13893702U, // ST1Twov4s_POST + 270406U, // ST1Twov8b + 14434374U, // ST1Twov8b_POST + 286790U, // ST1Twov8h + 13926470U, // ST1Twov8h_POST + 375010396U, // ST1W + 375002204U, // ST1W_D + 375002204U, // ST1W_D_IMM + 375010396U, // ST1W_IMM + 409670U, // ST1i16 + 1404346438U, // ST1i16_POST + 417862U, // ST1i32 + 1437917254U, // ST1i32_POST + 426054U, // ST1i64 + 1471488070U, // ST1i64_POST + 434246U, // ST1i8 + 1505058886U, // ST1i8_POST + 375022511U, // ST2B + 375022511U, // ST2B_IMM + 374998898U, // ST2D + 374998898U, // ST2D_IMM + 375032177U, // ST2H + 375032177U, // ST2H_IMM + 172505U, // ST2Twov16b + 13812185U, // ST2Twov16b_POST + 205273U, // ST2Twov2d + 13844953U, // ST2Twov2d_POST + 221657U, // ST2Twov2s + 14385625U, // ST2Twov2s_POST + 238041U, // ST2Twov4h + 14402009U, // ST2Twov4h_POST + 254425U, // ST2Twov4s + 13894105U, // ST2Twov4s_POST + 270809U, // ST2Twov8b + 14434777U, // ST2Twov8b_POST + 287193U, // ST2Twov8h + 13926873U, // ST2Twov8h_POST + 375010416U, // ST2W + 375010416U, // ST2W_IMM + 410073U, // ST2i16 + 1437901273U, // ST2i16_POST + 418265U, // ST2i32 + 1471472089U, // ST2i32_POST + 426457U, // ST2i64 + 1538597337U, // ST2i64_POST + 434649U, // ST2i8 + 1404395993U, // ST2i8_POST + 375022532U, // ST3B + 375022532U, // ST3B_IMM + 374998910U, // ST3D + 374998910U, // ST3D_IMM + 375032189U, // ST3H + 375032189U, // ST3H_IMM + 172571U, // ST3Threev16b + 16957979U, // ST3Threev16b_POST + 205339U, // ST3Threev2d + 16990747U, // ST3Threev2d_POST + 221723U, // ST3Threev2s + 17531419U, // ST3Threev2s_POST + 238107U, // ST3Threev4h + 17547803U, // ST3Threev4h_POST + 254491U, // ST3Threev4s + 17039899U, // ST3Threev4s_POST + 270875U, // ST3Threev8b + 17580571U, // ST3Threev8b_POST + 287259U, // ST3Threev8h + 17072667U, // ST3Threev8h_POST + 375010428U, // ST3W + 375010428U, // ST3W_IMM + 410139U, // ST3i16 + 1572119067U, // ST3i16_POST + 418331U, // ST3i32 + 1605689883U, // ST3i32_POST + 426523U, // ST3i64 + 1639260699U, // ST3i64_POST + 434715U, // ST3i8 + 1672831515U, // ST3i8_POST + 375022544U, // ST4B + 375022544U, // ST4B_IMM + 374998922U, // ST4D + 374998922U, // ST4D_IMM + 172588U, // ST4Fourv16b + 13287980U, // ST4Fourv16b_POST + 205356U, // ST4Fourv2d + 13320748U, // ST4Fourv2d_POST + 221740U, // ST4Fourv2s + 13861420U, // ST4Fourv2s_POST + 238124U, // ST4Fourv4h + 13877804U, // ST4Fourv4h_POST + 254508U, // ST4Fourv4s + 13369900U, // ST4Fourv4s_POST + 270892U, // ST4Fourv8b + 13910572U, // ST4Fourv8b_POST + 287276U, // ST4Fourv8h + 13402668U, // ST4Fourv8h_POST + 375032201U, // ST4H + 375032201U, // ST4H_IMM + 375010440U, // ST4W + 375010440U, // ST4W_IMM + 410156U, // ST4i16 + 1471455788U, // ST4i16_POST + 418348U, // ST4i32 + 1538581036U, // ST4i32_POST + 426540U, // ST4i64 + 1706369580U, // ST4i64_POST + 434732U, // ST4i8 + 1437950508U, // ST4i8_POST + 2253964715U, // STLLRB + 2253966166U, // STLLRH + 2253967648U, // STLLRW + 2253967648U, // STLLRX + 2253964723U, // STLRB + 2253966174U, // STLRH + 2253967661U, // STLRW + 2253967661U, // STLRX + 106481125U, // STLURBi + 106482576U, // STLURHi + 106484110U, // STLURWi + 106484110U, // STLURXi + 100716685U, // STLXPW + 100716685U, // STLXPX + 2248197644U, // STLXRB + 2248199095U, // STLXRH + 2248200645U, // STLXRW + 2248200645U, // STLXRX + 2248200251U, // STNPDi + 2248200251U, // STNPQi + 2248200251U, // STNPSi + 2248200251U, // STNPWi + 2248200251U, // STNPXi + 375022474U, // STNT1B_ZRI + 375022474U, // STNT1B_ZRR + 374998878U, // STNT1D_ZRI + 374998878U, // STNT1D_ZRR + 375032140U, // STNT1H_ZRI + 375032140U, // STNT1H_ZRR + 375010388U, // STNT1W_ZRI + 375010388U, // STNT1W_ZRR + 2248200283U, // STPDi + 2516676699U, // STPDpost + 2516676699U, // STPDpre + 2248200283U, // STPQi + 2516676699U, // STPQpost + 2516676699U, // STPQpre + 2248200283U, // STPSi + 2516676699U, // STPSpost + 2516676699U, // STPSpre + 2248200283U, // STPWi + 2516676699U, // STPWpost + 2516676699U, // STPWpre + 2248200283U, // STPXi + 2516676699U, // STPXpost + 2516676699U, // STPXpre + 374957521U, // STRBBpost + 374957521U, // STRBBpre + 106481105U, // STRBBroW + 106481105U, // STRBBroX + 106481105U, // STRBBui + 374960503U, // STRBpost + 374960503U, // STRBpre + 106484087U, // STRBroW + 106484087U, // STRBroX + 106484087U, // STRBui + 374960503U, // STRDpost + 374960503U, // STRDpre + 106484087U, // STRDroW + 106484087U, // STRDroX + 106484087U, // STRDui + 374958972U, // STRHHpost + 374958972U, // STRHHpre + 106482556U, // STRHHroW + 106482556U, // STRHHroX + 106482556U, // STRHHui + 374960503U, // STRHpost + 374960503U, // STRHpre + 106484087U, // STRHroW + 106484087U, // STRHroX + 106484087U, // STRHui + 374960503U, // STRQpost + 374960503U, // STRQpre + 106484087U, // STRQroW + 106484087U, // STRQroX + 106484087U, // STRQui + 374960503U, // STRSpost + 374960503U, // STRSpre + 106484087U, // STRSroW + 106484087U, // STRSroX + 106484087U, // STRSui + 374960503U, // STRWpost + 374960503U, // STRWpre + 106484087U, // STRWroW + 106484087U, // STRWroX + 106484087U, // STRWui + 374960503U, // STRXpost + 374960503U, // STRXpre + 106484087U, // STRXroW + 106484087U, // STRXroX + 106484087U, // STRXui + 106803575U, // STR_PXI + 106803575U, // STR_ZXI + 106481111U, // STTRBi + 106482562U, // STTRHi + 106484092U, // STTRWi + 106484092U, // STTRXi + 106481142U, // STURBBi + 106484125U, // STURBi + 106484125U, // STURDi + 106482593U, // STURHHi + 106484125U, // STURHi + 106484125U, // STURQi + 106484125U, // STURSi + 106484125U, // STURWi + 106484125U, // STURXi + 100716692U, // STXPW + 100716692U, // STXPX + 2248197652U, // STXRB + 2248199103U, // STXRH + 2248200652U, // STXRW + 2248200652U, // STXRX + 2216210137U, // SUBHNv2i64_v2i32 + 2284904778U, // SUBHNv2i64_v4i32 + 69775065U, // SUBHNv4i32_v4i16 + 137945418U, // SUBHNv4i32_v8i16 + 2282807626U, // SUBHNv8i16_v16i8 + 2218831577U, // SUBHNv8i16_v8i8 + 167784668U, // SUBR_ZI_B + 201347292U, // SUBR_ZI_D + 239628508U, // SUBR_ZI_H + 268472540U, // SUBR_ZI_S + 302002396U, // SUBR_ZPmZ_B + 302010588U, // SUBR_ZPmZ_D + 2186309852U, // SUBR_ZPmZ_H + 302026972U, // SUBR_ZPmZ_S + 100717066U, // SUBSWri 0U, // SUBSWrr - 17049650U, // SUBSWrs - 17049650U, // SUBSWrx - 17049650U, // SUBSXri + 100717066U, // SUBSWrs + 100717066U, // SUBSWrx + 100717066U, // SUBSXri 0U, // SUBSXrr - 17049650U, // SUBSXrs - 17049650U, // SUBSXrx - 17049650U, // SUBSXrx64 - 17048238U, // SUBWri + 100717066U, // SUBSXrs + 100717066U, // SUBSXrx + 100717066U, // SUBSXrx64 + 100714146U, // SUBWri 0U, // SUBWrr - 17048238U, // SUBWrs - 17048238U, // SUBWrx - 17048238U, // SUBXri + 100714146U, // SUBWrs + 100714146U, // SUBWrx + 100714146U, // SUBXri 0U, // SUBXrr - 17048238U, // SUBXrs - 17048238U, // SUBXrx - 17048238U, // SUBXrx64 - 2147488430U, // SUBv16i8 - 17048238U, // SUBv1i64 - 2684883630U, // SUBv2i32 - 537662126U, // SUBv2i64 - 3222278830U, // SUBv4i16 - 1075057326U, // SUBv4i32 - 1612190382U, // SUBv8i16 - 3759936174U, // SUBv8i8 - 33567585U, // SUQADDv16i8 - 604275553U, // SUQADDv1i16 - 604275553U, // SUQADDv1i32 - 604275553U, // SUQADDv1i64 - 604275553U, // SUQADDv1i8 - 1107833697U, // SUQADDv2i32 - 1644966753U, // SUQADDv2i64 - 2182099809U, // SUQADDv4i16 - 2719232865U, // SUQADDv4i32 - 3256365921U, // SUQADDv8i16 - 3793498977U, // SUQADDv8i8 - 21263U, // SVC - 17049022U, // SYSLxt - 419702938U, // SYSxt - 436212968U, // TBLv16i8Four - 436212968U, // TBLv16i8One - 436212968U, // TBLv16i8Three - 436212968U, // TBLv16i8Two - 4196144360U, // TBLv8i8Four - 4196144360U, // TBLv8i8One - 4196144360U, // TBLv8i8Three - 4196144360U, // TBLv8i8Two - 17050183U, // TBNZW - 17050183U, // TBNZX - 452999686U, // TBXv16i8Four - 452999686U, // TBXv16i8One - 452999686U, // TBXv16i8Three - 452999686U, // TBXv16i8Two - 4212931078U, // TBXv8i8Four - 4212931078U, // TBXv8i8One - 4212931078U, // TBXv8i8Three - 4212931078U, // TBXv8i8Two - 17050167U, // TBZW - 17050167U, // TBZX + 100714146U, // SUBXrs + 100714146U, // SUBXrx + 100714146U, // SUBXrx64 + 167782050U, // SUB_ZI_B + 201344674U, // SUB_ZI_D + 239625890U, // SUB_ZI_H + 268469922U, // SUB_ZI_S + 301999778U, // SUB_ZPmZ_B + 302007970U, // SUB_ZPmZ_D + 2186307234U, // SUB_ZPmZ_H + 302024354U, // SUB_ZPmZ_S + 167782050U, // SUB_ZZZ_B + 201344674U, // SUB_ZZZ_D + 2387109538U, // SUB_ZZZ_H + 268469922U, // SUB_ZZZ_S + 68200098U, // SUBv16i8 + 100714146U, // SUBv1i64 + 2216208034U, // SUBv2i32 + 2216732322U, // SUBv2i64 + 69772962U, // SUBv4i16 + 70297250U, // SUBv4i32 + 2218305186U, // SUBv8i16 + 2218829474U, // SUBv8i8 + 2415938650U, // SUNPKHI_ZZ_D + 27290714U, // SUNPKHI_ZZ_H + 2717944922U, // SUNPKHI_ZZ_S + 2415939470U, // SUNPKLO_ZZ_D + 27291534U, // SUNPKLO_ZZ_H + 2717945742U, // SUNPKLO_ZZ_S + 135325734U, // SUQADDv16i8 + 2516674598U, // SUQADDv1i16 + 2516674598U, // SUQADDv1i32 + 2516674598U, // SUQADDv1i64 + 2516674598U, // SUQADDv1i8 + 135850022U, // SUQADDv2i32 + 2283857958U, // SUQADDv2i64 + 136898598U, // SUQADDv4i16 + 2284906534U, // SUQADDv4i32 + 137947174U, // SUQADDv8i16 + 2285955110U, // SUQADDv8i8 + 75579U, // SVC + 973169651U, // SWPAB + 973171135U, // SWPAH + 973169853U, // SWPALB + 973171283U, // SWPALH + 973171948U, // SWPALW + 973171948U, // SWPALX + 973169381U, // SWPAW + 973169381U, // SWPAX + 973170041U, // SWPB + 973171492U, // SWPH + 973169950U, // SWPLB + 973171380U, // SWPLH + 973172243U, // SWPLW + 973172243U, // SWPLX + 973172838U, // SWPW + 973172838U, // SWPX + 18069U, // SXTB_ZPmZ_D + 2181588629U, // SXTB_ZPmZ_H + 34453U, // SXTB_ZPmZ_S + 19494U, // SXTH_ZPmZ_D + 35878U, // SXTH_ZPmZ_S + 21815U, // SXTW_ZPmZ_D + 100716107U, // SYSLxt + 1711329984U, // SYSxt + 1744842025U, // TBL_ZZZ_B + 1778404649U, // TBL_ZZZ_D + 28863785U, // TBL_ZZZ_H + 1811975465U, // TBL_ZZZ_S + 1846586665U, // TBLv16i8Four + 1846586665U, // TBLv16i8One + 1846586665U, // TBLv16i8Three + 1846586665U, // TBLv16i8Two + 3997216041U, // TBLv8i8Four + 3997216041U, // TBLv8i8One + 3997216041U, // TBLv8i8Three + 3997216041U, // TBLv8i8Two + 100718059U, // TBNZW + 100718059U, // TBNZX + 1880159597U, // TBXv16i8Four + 1880159597U, // TBXv16i8One + 1880159597U, // TBXv16i8Three + 1880159597U, // TBXv16i8Two + 4030788973U, // TBXv8i8Four + 4030788973U, // TBXv8i8One + 4030788973U, // TBXv8i8Three + 4030788973U, // TBXv8i8Two + 100718043U, // TBZW + 100718043U, // TBZX 0U, // TCRETURNdi 0U, // TCRETURNri - 2107995U, // TLSDESCCALL - 0U, // TLSDESC_BLR - 2147487770U, // TRN1v16i8 - 2684882970U, // TRN1v2i32 - 537661466U, // TRN1v2i64 - 3222278170U, // TRN1v4i16 - 1075056666U, // TRN1v4i32 - 1612189722U, // TRN1v8i16 - 3759935514U, // TRN1v8i8 - 2147488072U, // TRN2v16i8 - 2684883272U, // TRN2v2i32 - 537661768U, // TRN2v2i64 - 3222278472U, // TRN2v4i16 - 1075056968U, // TRN2v4i32 - 1612190024U, // TRN2v8i16 - 3759935816U, // TRN2v8i8 - 2182623338U, // UABALv16i8_v8i16 - 2718708938U, // UABALv2i32_v2i64 - 3256104138U, // UABALv4i16_v4i32 - 1108095082U, // UABALv4i32_v2i64 - 1645490282U, // UABALv8i16_v4i32 - 3793237194U, // UABALv8i8_v8i16 - 2181050868U, // UABAv16i8 - 2718446068U, // UABAv2i32 - 3255841268U, // UABAv4i16 - 1108619764U, // UABAv4i32 - 1645752820U, // UABAv8i16 - 3793498612U, // UABAv8i8 - 2149060772U, // UABDLv16i8_v8i16 - 2685146386U, // UABDLv2i32_v2i64 - 3222541586U, // UABDLv4i16_v4i32 - 1074532516U, // UABDLv4i32_v2i64 - 1611927716U, // UABDLv8i16_v4i32 - 3759674642U, // UABDLv8i8_v8i16 - 2147488544U, // UABDv16i8 - 2684883744U, // UABDv2i32 - 3222278944U, // UABDv4i16 - 1075057440U, // UABDv4i32 - 1612190496U, // UABDv8i16 - 3759936288U, // UABDv8i8 - 35141323U, // UADALPv16i8_v8i16 - 1117533899U, // UADALPv2i32_v1i64 - 2181576395U, // UADALPv4i16_v2i32 - 2718709451U, // UADALPv4i32_v2i64 - 3256104651U, // UADALPv8i16_v4i32 - 3792713419U, // UADALPv8i8_v4i16 - 1578715U, // UADDLPv16i8_v8i16 - 1083971291U, // UADDLPv2i32_v1i64 - 2148013787U, // UADDLPv4i16_v2i32 - 2685146843U, // UADDLPv4i32_v2i64 - 3222542043U, // UADDLPv8i16_v4i32 - 3759150811U, // UADDLPv8i8_v4i16 - 272708U, // UADDLVv16i8v - 2147756356U, // UADDLVv4i16v - 2684627268U, // UADDLVv4i32v - 3221498180U, // UADDLVv8i16v - 3758369092U, // UADDLVv8i8v - 2149060788U, // UADDLv16i8_v8i16 - 2685146416U, // UADDLv2i32_v2i64 - 3222541616U, // UADDLv4i16_v4i32 - 1074532532U, // UADDLv4i32_v2i64 - 1611927732U, // UADDLv8i16_v4i32 - 3759674672U, // UADDLv8i8_v8i16 - 1612190141U, // UADDWv16i8_v8i16 - 537663943U, // UADDWv2i32_v2i64 - 1075059143U, // UADDWv4i16_v4i32 - 537661885U, // UADDWv4i32_v2i64 - 1075057085U, // UADDWv8i16_v4i32 - 1612192199U, // UADDWv8i8_v8i16 - 17049067U, // UBFMWri - 17049067U, // UBFMXri - 17048524U, // UCVTFSWDri - 17048524U, // UCVTFSWSri - 17048524U, // UCVTFSXDri - 17048524U, // UCVTFSXSri - 553919436U, // UCVTFUWDri - 553919436U, // UCVTFUWSri - 553919436U, // UCVTFUXDri - 553919436U, // UCVTFUXSri - 17048524U, // UCVTFd - 17048524U, // UCVTFs - 553919436U, // UCVTFv1i32 - 553919436U, // UCVTFv1i64 - 1074271180U, // UCVTFv2f32 - 1611404236U, // UCVTFv2f64 - 2684883916U, // UCVTFv2i32_shift - 537662412U, // UCVTFv2i64_shift - 2685670348U, // UCVTFv4f32 - 1075057612U, // UCVTFv4i32_shift - 17049910U, // UDIVWr - 17049910U, // UDIVXr - 17049910U, // UDIV_IntWr - 17049910U, // UDIV_IntXr - 2147488579U, // UHADDv16i8 - 2684883779U, // UHADDv2i32 - 3222278979U, // UHADDv4i16 - 1075057475U, // UHADDv4i32 - 1612190531U, // UHADDv8i16 - 3759936323U, // UHADDv8i8 - 2147488442U, // UHSUBv16i8 - 2684883642U, // UHSUBv2i32 - 3222278842U, // UHSUBv4i16 - 1075057338U, // UHSUBv4i32 - 1612190394U, // UHSUBv8i16 - 3759936186U, // UHSUBv8i8 - 17048865U, // UMADDLrrr - 2147489616U, // UMAXPv16i8 - 2684884816U, // UMAXPv2i32 - 3222280016U, // UMAXPv4i16 - 1075058512U, // UMAXPv4i32 - 1612191568U, // UMAXPv8i16 - 3759937360U, // UMAXPv8i8 - 272794U, // UMAXVv16i8v - 2147756442U, // UMAXVv4i16v - 2684627354U, // UMAXVv4i32v - 3221498266U, // UMAXVv8i16v - 3758369178U, // UMAXVv8i8v - 2147490304U, // UMAXv16i8 - 2684885504U, // UMAXv2i32 - 3222280704U, // UMAXv4i16 - 1075059200U, // UMAXv4i32 - 1612192256U, // UMAXv8i16 - 3759938048U, // UMAXv8i8 - 2147489558U, // UMINPv16i8 - 2684884758U, // UMINPv2i32 - 3222279958U, // UMINPv4i16 - 1075058454U, // UMINPv4i32 - 1612191510U, // UMINPv8i16 - 3759937302U, // UMINPv8i8 - 272748U, // UMINVv16i8v - 2147756396U, // UMINVv4i16v - 2684627308U, // UMINVv4i32v - 3221498220U, // UMINVv8i16v - 3758369132U, // UMINVv8i8v - 2147489330U, // UMINv16i8 - 2684884530U, // UMINv2i32 - 3222279730U, // UMINv4i16 - 1075058226U, // UMINv4i32 - 1612191282U, // UMINv8i16 - 3759937074U, // UMINv8i8 - 2182623364U, // UMLALv16i8_v8i16 - 2718708961U, // UMLALv2i32_indexed - 2718708961U, // UMLALv2i32_v2i64 - 3256104161U, // UMLALv4i16_indexed - 3256104161U, // UMLALv4i16_v4i32 - 1108095108U, // UMLALv4i32_indexed - 1108095108U, // UMLALv4i32_v2i64 - 1645490308U, // UMLALv8i16_indexed - 1645490308U, // UMLALv8i16_v4i32 - 3793237217U, // UMLALv8i8_v8i16 - 2182623488U, // UMLSLv16i8_v8i16 - 2718709175U, // UMLSLv2i32_indexed - 2718709175U, // UMLSLv2i32_v2i64 - 3256104375U, // UMLSLv4i16_indexed - 3256104375U, // UMLSLv4i16_v4i32 - 1108095232U, // UMLSLv4i32_indexed - 1108095232U, // UMLSLv4i32_v2i64 - 1645490432U, // UMLSLv8i16_indexed - 1645490432U, // UMLSLv8i16_v4i32 - 3793237431U, // UMLSLv8i8_v8i16 - 272774U, // UMOVvi16 - 537143686U, // UMOVvi32 - 1074014598U, // UMOVvi64 - 1610885510U, // UMOVvi8 - 17048821U, // UMSUBLrrr - 17048610U, // UMULHrr - 2149060838U, // UMULLv16i8_v8i16 - 2685146523U, // UMULLv2i32_indexed - 2685146523U, // UMULLv2i32_v2i64 - 3222541723U, // UMULLv4i16_indexed - 3222541723U, // UMULLv4i16_v4i32 - 1074532582U, // UMULLv4i32_indexed - 1074532582U, // UMULLv4i32_v2i64 - 1611927782U, // UMULLv8i16_indexed - 1611927782U, // UMULLv8i16_v4i32 - 3759674779U, // UMULLv8i8_v8i16 - 2147488610U, // UQADDv16i8 - 17048418U, // UQADDv1i16 - 17048418U, // UQADDv1i32 - 17048418U, // UQADDv1i64 - 17048418U, // UQADDv1i8 - 2684883810U, // UQADDv2i32 - 537662306U, // UQADDv2i64 - 3222279010U, // UQADDv4i16 - 1075057506U, // UQADDv4i32 - 1612190562U, // UQADDv8i16 - 3759936354U, // UQADDv8i8 - 2147489108U, // UQRSHLv16i8 - 17048916U, // UQRSHLv1i16 - 17048916U, // UQRSHLv1i32 - 17048916U, // UQRSHLv1i64 - 17048916U, // UQRSHLv1i8 - 2684884308U, // UQRSHLv2i32 - 537662804U, // UQRSHLv2i64 - 3222279508U, // UQRSHLv4i16 - 1075058004U, // UQRSHLv4i32 - 1612191060U, // UQRSHLv8i16 - 3759936852U, // UQRSHLv8i8 - 17049180U, // UQRSHRNb - 17049180U, // UQRSHRNh - 17049180U, // UQRSHRNs - 1644179774U, // UQRSHRNv16i8_shift - 537400924U, // UQRSHRNv2i32_shift - 1074796124U, // UQRSHRNv4i16_shift - 571748670U, // UQRSHRNv4i32_shift - 1108881726U, // UQRSHRNv8i16_shift - 1612453468U, // UQRSHRNv8i8_shift - 17048901U, // UQSHLb - 17048901U, // UQSHLd - 17048901U, // UQSHLh - 17048901U, // UQSHLs - 2147489093U, // UQSHLv16i8 - 2147489093U, // UQSHLv16i8_shift - 17048901U, // UQSHLv1i16 - 17048901U, // UQSHLv1i32 - 17048901U, // UQSHLv1i64 - 17048901U, // UQSHLv1i8 - 2684884293U, // UQSHLv2i32 - 2684884293U, // UQSHLv2i32_shift - 537662789U, // UQSHLv2i64 - 537662789U, // UQSHLv2i64_shift - 3222279493U, // UQSHLv4i16 - 3222279493U, // UQSHLv4i16_shift - 1075057989U, // UQSHLv4i32 - 1075057989U, // UQSHLv4i32_shift - 1612191045U, // UQSHLv8i16 - 1612191045U, // UQSHLv8i16_shift - 3759936837U, // UQSHLv8i8 - 3759936837U, // UQSHLv8i8_shift - 17049163U, // UQSHRNb - 17049163U, // UQSHRNh - 17049163U, // UQSHRNs - 1644179755U, // UQSHRNv16i8_shift - 537400907U, // UQSHRNv2i32_shift - 1074796107U, // UQSHRNv4i16_shift - 571748651U, // UQSHRNv4i32_shift - 1108881707U, // UQSHRNv8i16_shift - 1612453451U, // UQSHRNv8i8_shift - 2147488471U, // UQSUBv16i8 - 17048279U, // UQSUBv1i16 - 17048279U, // UQSUBv1i32 - 17048279U, // UQSUBv1i64 - 17048279U, // UQSUBv1i8 - 2684883671U, // UQSUBv2i32 - 537662167U, // UQSUBv2i64 - 3222278871U, // UQSUBv4i16 - 1075057367U, // UQSUBv4i32 - 1612190423U, // UQSUBv8i16 - 3759936215U, // UQSUBv8i8 - 3254792542U, // UQXTNv16i8 - 553920128U, // UQXTNv1i16 - 553920128U, // UQXTNv1i32 - 553920128U, // UQXTNv1i8 - 1611142784U, // UQXTNv2i32 - 2685408896U, // UQXTNv4i16 - 1645490526U, // UQXTNv4i32 - 2719494494U, // UQXTNv8i16 - 3223066240U, // UQXTNv8i8 - 1074271121U, // URECPEv2i32 - 2685670289U, // URECPEv4i32 - 2147488564U, // URHADDv16i8 - 2684883764U, // URHADDv2i32 - 3222278964U, // URHADDv4i16 - 1075057460U, // URHADDv4i32 - 1612190516U, // URHADDv8i16 - 3759936308U, // URHADDv8i8 - 2147489123U, // URSHLv16i8 - 17048931U, // URSHLv1i64 - 2684884323U, // URSHLv2i32 - 537662819U, // URSHLv2i64 - 3222279523U, // URSHLv4i16 - 1075058019U, // URSHLv4i32 - 1612191075U, // URSHLv8i16 - 3759936867U, // URSHLv8i8 - 17049508U, // URSHRd - 2147489700U, // URSHRv16i8_shift - 2684884900U, // URSHRv2i32_shift - 537663396U, // URSHRv2i64_shift - 3222280100U, // URSHRv4i16_shift - 1075058596U, // URSHRv4i32_shift - 1612191652U, // URSHRv8i16_shift - 3759937444U, // URSHRv8i8_shift - 1074271159U, // URSQRTEv2i32 - 2685670327U, // URSQRTEv4i32 - 67404295U, // URSRAd - 2181050887U, // URSRAv16i8_shift - 2718446087U, // URSRAv2i32_shift - 571224583U, // URSRAv2i64_shift - 3255841287U, // URSRAv4i16_shift - 1108619783U, // URSRAv4i32_shift - 1645752839U, // URSRAv8i16_shift - 3793498631U, // URSRAv8i8_shift - 2149060804U, // USHLLv16i8_shift - 2685146493U, // USHLLv2i32_shift - 3222541693U, // USHLLv4i16_shift - 1074532548U, // USHLLv4i32_shift - 1611927748U, // USHLLv8i16_shift - 3759674749U, // USHLLv8i8_shift - 2147489136U, // USHLv16i8 - 17048944U, // USHLv1i64 - 2684884336U, // USHLv2i32 - 537662832U, // USHLv2i64 - 3222279536U, // USHLv4i16 - 1075058032U, // USHLv4i32 - 1612191088U, // USHLv8i16 - 3759936880U, // USHLv8i8 - 17049521U, // USHRd - 2147489713U, // USHRv16i8_shift - 2684884913U, // USHRv2i32_shift - 537663409U, // USHRv2i64_shift - 3222280113U, // USHRv4i16_shift - 1075058609U, // USHRv4i32_shift - 1612191665U, // USHRv8i16_shift - 3759937457U, // USHRv8i8_shift - 33567577U, // USQADDv16i8 - 604275545U, // USQADDv1i16 - 604275545U, // USQADDv1i32 - 604275545U, // USQADDv1i64 - 604275545U, // USQADDv1i8 - 1107833689U, // USQADDv2i32 - 1644966745U, // USQADDv2i64 - 2182099801U, // USQADDv4i16 - 2719232857U, // USQADDv4i32 - 3256365913U, // USQADDv8i16 - 3793498969U, // USQADDv8i8 - 67404308U, // USRAd - 2181050900U, // USRAv16i8_shift - 2718446100U, // USRAv2i32_shift - 571224596U, // USRAv2i64_shift - 3255841300U, // USRAv4i16_shift - 1108619796U, // USRAv4i32_shift - 1645752852U, // USRAv8i16_shift - 3793498644U, // USRAv8i8_shift - 2149060756U, // USUBLv16i8_v8i16 - 2685146372U, // USUBLv2i32_v2i64 - 3222541572U, // USUBLv4i16_v4i32 - 1074532500U, // USUBLv4i32_v2i64 - 1611927700U, // USUBLv8i16_v4i32 - 3759674628U, // USUBLv8i8_v8i16 - 1612190125U, // USUBWv16i8_v8i16 - 537663920U, // USUBWv2i32_v2i64 - 1075059120U, // USUBWv4i16_v4i32 - 537661869U, // USUBWv4i32_v2i64 - 1075057069U, // USUBWv8i16_v4i32 - 1612192176U, // USUBWv8i8_v8i16 - 2147487782U, // UZP1v16i8 - 2684882982U, // UZP1v2i32 - 537661478U, // UZP1v2i64 - 3222278182U, // UZP1v4i16 - 1075056678U, // UZP1v4i32 - 1612189734U, // UZP1v8i16 - 3759935526U, // UZP1v8i8 - 2147488147U, // UZP2v16i8 - 2684883347U, // UZP2v2i32 - 537661843U, // UZP2v2i64 - 3222278547U, // UZP2v4i16 - 1075057043U, // UZP2v4i32 - 1612190099U, // UZP2v8i16 - 3759935891U, // UZP2v8i8 - 3254792536U, // XTNv16i8 - 1611142779U, // XTNv2i32 - 2685408891U, // XTNv4i16 - 1645490520U, // XTNv4i32 - 2719494488U, // XTNv8i16 - 3223066235U, // XTNv8i8 - 2147487776U, // ZIP1v16i8 - 2684882976U, // ZIP1v2i32 - 537661472U, // ZIP1v2i64 - 3222278176U, // ZIP1v4i16 - 1075056672U, // ZIP1v4i32 - 1612189728U, // ZIP1v8i16 - 3759935520U, // ZIP1v8i8 - 2147488141U, // ZIP2v16i8 - 2684883341U, // ZIP2v2i32 - 537661837U, // ZIP2v2i64 - 3222278541U, // ZIP2v4i16 - 1075057037U, // ZIP2v4i32 - 1612190093U, // ZIP2v8i16 - 3759935885U, // ZIP2v8i8 - 0U + 6346239U, // TLSDESCCALL + 0U, // TLSDESC_CALLSEQ + 167780389U, // TRN1_PPP_B + 201343013U, // TRN1_PPP_D + 2387107877U, // TRN1_PPP_H + 268468261U, // TRN1_PPP_S + 167780389U, // TRN1_ZZZ_B + 201343013U, // TRN1_ZZZ_D + 2387107877U, // TRN1_ZZZ_H + 268468261U, // TRN1_ZZZ_S + 68198437U, // TRN1v16i8 + 2216206373U, // TRN1v2i32 + 2216730661U, // TRN1v2i64 + 69771301U, // TRN1v4i16 + 70295589U, // TRN1v4i32 + 2218303525U, // TRN1v8i16 + 2218827813U, // TRN1v8i8 + 167780737U, // TRN2_PPP_B + 201343361U, // TRN2_PPP_D + 2387108225U, // TRN2_PPP_H + 268468609U, // TRN2_PPP_S + 167780737U, // TRN2_ZZZ_B + 201343361U, // TRN2_ZZZ_D + 2387108225U, // TRN2_ZZZ_H + 268468609U, // TRN2_ZZZ_S + 68198785U, // TRN2v16i8 + 2216206721U, // TRN2v2i32 + 2216731009U, // TRN2v2i64 + 69771649U, // TRN2v4i16 + 70295937U, // TRN2v4i32 + 2218303873U, // TRN2v8i16 + 2218828161U, // TRN2v8i8 + 116346U, // TSB + 137945251U, // UABALv16i8_v8i16 + 2283859113U, // UABALv2i32_v2i64 + 137424041U, // UABALv4i16_v4i32 + 136372387U, // UABALv4i32_v2i64 + 2284904611U, // UABALv8i16_v4i32 + 2285431977U, // UABALv8i8_v8i16 + 135324275U, // UABAv16i8 + 2283332211U, // UABAv2i32 + 136897139U, // UABAv4i16 + 137421427U, // UABAv4i32 + 2285429363U, // UABAv8i16 + 2285953651U, // UABAv8i8 + 70820061U, // UABDLv16i8_v8i16 + 2216734035U, // UABDLv2i32_v2i64 + 70298963U, // UABDLv4i16_v4i32 + 69247197U, // UABDLv4i32_v2i64 + 2217779421U, // UABDLv8i16_v4i32 + 2218306899U, // UABDLv8i8_v8i16 + 302000048U, // UABD_ZPmZ_B + 302008240U, // UABD_ZPmZ_D + 2186307504U, // UABD_ZPmZ_H + 302024624U, // UABD_ZPmZ_S + 68200368U, // UABDv16i8 + 2216208304U, // UABDv2i32 + 69773232U, // UABDv4i16 + 70297520U, // UABDv4i32 + 2218305456U, // UABDv8i16 + 2218829744U, // UABDv8i8 + 137949161U, // UADALPv16i8_v8i16 + 162066409U, // UADALPv2i32_v1i64 + 135852009U, // UADALPv4i16_v2i32 + 2283859945U, // UADALPv4i32_v2i64 + 137424873U, // UADALPv8i16_v4i32 + 2284384233U, // UADALPv8i8_v4i16 + 70823929U, // UADDLPv16i8_v8i16 + 94941177U, // UADDLPv2i32_v1i64 + 68726777U, // UADDLPv4i16_v2i32 + 2216734713U, // UADDLPv4i32_v2i64 + 70299641U, // UADDLPv8i16_v4i32 + 2217259001U, // UADDLPv8i8_v4i16 + 67163091U, // UADDLVv16i8v + 67163091U, // UADDLVv4i16v + 2214646739U, // UADDLVv4i32v + 67163091U, // UADDLVv8i16v + 2214646739U, // UADDLVv8i8v + 70820077U, // UADDLv16i8_v8i16 + 2216734073U, // UADDLv2i32_v2i64 + 70299001U, // UADDLv4i16_v4i32 + 69247213U, // UADDLv4i32_v2i64 + 2217779437U, // UADDLv8i16_v4i32 + 2218306937U, // UADDLv8i8_v8i16 + 302044071U, // UADDV_VPZ_B + 302044071U, // UADDV_VPZ_D + 302044071U, // UADDV_VPZ_H + 302044071U, // UADDV_VPZ_S + 2218303990U, // UADDWv16i8_v8i16 + 2216735948U, // UADDWv2i32_v2i64 + 70300876U, // UADDWv4i16_v4i32 + 2216731126U, // UADDWv4i32_v2i64 + 70296054U, // UADDWv8i16_v4i32 + 2218308812U, // UADDWv8i8_v8i16 + 100716199U, // UBFMWri + 100716199U, // UBFMXri + 100714764U, // UCVTFSWDri + 100714764U, // UCVTFSWHri + 100714764U, // UCVTFSWSri + 100714764U, // UCVTFSXDri + 100714764U, // UCVTFSXHri + 100714764U, // UCVTFSXSri + 2248198412U, // UCVTFUWDri + 2248198412U, // UCVTFUWHri + 2248198412U, // UCVTFUWSri + 2248198412U, // UCVTFUXDri + 2248198412U, // UCVTFUXHri + 2248198412U, // UCVTFUXSri + 18700U, // UCVTF_ZPmZ_DtoD + 2181589260U, // UCVTF_ZPmZ_DtoH + 35084U, // UCVTF_ZPmZ_DtoS + 2181589260U, // UCVTF_ZPmZ_HtoH + 18700U, // UCVTF_ZPmZ_StoD + 2181589260U, // UCVTF_ZPmZ_StoH + 35084U, // UCVTF_ZPmZ_StoS + 100714764U, // UCVTFd + 100714764U, // UCVTFh + 100714764U, // UCVTFs + 2248198412U, // UCVTFv1i16 + 2248198412U, // UCVTFv1i32 + 2248198412U, // UCVTFv1i64 + 68725004U, // UCVTFv2f32 + 2216732940U, // UCVTFv2f64 + 2216208652U, // UCVTFv2i32_shift + 2216732940U, // UCVTFv2i64_shift + 69773580U, // UCVTFv4f16 + 2217781516U, // UCVTFv4f32 + 69773580U, // UCVTFv4i16_shift + 70297868U, // UCVTFv4i32_shift + 70822156U, // UCVTFv8f16 + 2218305804U, // UCVTFv8i16_shift + 302010801U, // UDIVR_ZPmZ_D + 302027185U, // UDIVR_ZPmZ_S + 100717509U, // UDIVWr + 100717509U, // UDIVXr + 302011333U, // UDIV_ZPmZ_D + 302027717U, // UDIV_ZPmZ_S + 3422573363U, // UDOT_ZZZI_D + 3456144179U, // UDOT_ZZZI_S + 3422573363U, // UDOT_ZZZ_D + 3456144179U, // UDOT_ZZZ_S + 137425715U, // UDOTlanev16i8 + 2283336499U, // UDOTlanev8i8 + 137425715U, // UDOTv16i8 + 2283336499U, // UDOTv8i8 + 68200456U, // UHADDv16i8 + 2216208392U, // UHADDv2i32 + 69773320U, // UHADDv4i16 + 70297608U, // UHADDv4i32 + 2218305544U, // UHADDv8i16 + 2218829832U, // UHADDv8i8 + 68200110U, // UHSUBv16i8 + 2216208046U, // UHSUBv2i32 + 69772974U, // UHSUBv4i16 + 70297262U, // UHSUBv4i32 + 2218305198U, // UHSUBv8i16 + 2218829486U, // UHSUBv8i8 + 100715882U, // UMADDLrrr + 68202624U, // UMAXPv16i8 + 2216210560U, // UMAXPv2i32 + 69775488U, // UMAXPv4i16 + 70299776U, // UMAXPv4i32 + 2218307712U, // UMAXPv8i16 + 2218832000U, // UMAXPv8i8 + 302044207U, // UMAXV_VPZ_B + 302044207U, // UMAXV_VPZ_D + 302044207U, // UMAXV_VPZ_H + 302044207U, // UMAXV_VPZ_S + 67163183U, // UMAXVv16i8v + 67163183U, // UMAXVv4i16v + 2214646831U, // UMAXVv4i32v + 67163183U, // UMAXVv8i16v + 2214646831U, // UMAXVv8i8v + 167785831U, // UMAX_ZI_B + 201348455U, // UMAX_ZI_D + 239629671U, // UMAX_ZI_H + 268473703U, // UMAX_ZI_S + 302003559U, // UMAX_ZPmZ_B + 302011751U, // UMAX_ZPmZ_D + 2186311015U, // UMAX_ZPmZ_H + 302028135U, // UMAX_ZPmZ_S + 68203879U, // UMAXv16i8 + 2216211815U, // UMAXv2i32 + 69776743U, // UMAXv4i16 + 70301031U, // UMAXv4i32 + 2218308967U, // UMAXv8i16 + 2218833255U, // UMAXv8i8 + 68202548U, // UMINPv16i8 + 2216210484U, // UMINPv2i32 + 69775412U, // UMINPv4i16 + 70299700U, // UMINPv4i32 + 2218307636U, // UMINPv8i16 + 2218831924U, // UMINPv8i8 + 302044155U, // UMINV_VPZ_B + 302044155U, // UMINV_VPZ_D + 302044155U, // UMINV_VPZ_H + 302044155U, // UMINV_VPZ_S + 67163131U, // UMINVv16i8v + 67163131U, // UMINVv4i16v + 2214646779U, // UMINVv4i32v + 67163131U, // UMINVv8i16v + 2214646779U, // UMINVv8i8v + 167784184U, // UMIN_ZI_B + 201346808U, // UMIN_ZI_D + 239628024U, // UMIN_ZI_H + 268472056U, // UMIN_ZI_S + 302001912U, // UMIN_ZPmZ_B + 302010104U, // UMIN_ZPmZ_D + 2186309368U, // UMIN_ZPmZ_H + 302026488U, // UMIN_ZPmZ_S + 68202232U, // UMINv16i8 + 2216210168U, // UMINv2i32 + 69775096U, // UMINv4i16 + 70299384U, // UMINv4i32 + 2218307320U, // UMINv8i16 + 2218831608U, // UMINv8i8 + 137945277U, // UMLALv16i8_v8i16 + 2283859145U, // UMLALv2i32_indexed + 2283859145U, // UMLALv2i32_v2i64 + 137424073U, // UMLALv4i16_indexed + 137424073U, // UMLALv4i16_v4i32 + 136372413U, // UMLALv4i32_indexed + 136372413U, // UMLALv4i32_v2i64 + 2284904637U, // UMLALv8i16_indexed + 2284904637U, // UMLALv8i16_v4i32 + 2285432009U, // UMLALv8i8_v8i16 + 137945401U, // UMLSLv16i8_v8i16 + 2283859524U, // UMLSLv2i32_indexed + 2283859524U, // UMLSLv2i32_v2i64 + 137424452U, // UMLSLv4i16_indexed + 137424452U, // UMLSLv4i16_v4i32 + 136372537U, // UMLSLv4i32_indexed + 136372537U, // UMLSLv4i32_v2i64 + 2284904761U, // UMLSLv8i16_indexed + 2284904761U, // UMLSLv8i16_v4i32 + 2285432388U, // UMLSLv8i8_v8i16 + 67163157U, // UMOVvi16 + 2214646805U, // UMOVvi32 + 67163157U, // UMOVvi64 + 2214646805U, // UMOVvi8 + 100715830U, // UMSUBLrrr + 302000887U, // UMULH_ZPmZ_B + 302009079U, // UMULH_ZPmZ_D + 2186308343U, // UMULH_ZPmZ_H + 302025463U, // UMULH_ZPmZ_S + 100715255U, // UMULHrr + 70820127U, // UMULLv16i8_v8i16 + 2216734188U, // UMULLv2i32_indexed + 2216734188U, // UMULLv2i32_v2i64 + 70299116U, // UMULLv4i16_indexed + 70299116U, // UMULLv4i16_v4i32 + 69247263U, // UMULLv4i32_indexed + 69247263U, // UMULLv4i32_v2i64 + 2217779487U, // UMULLv8i16_indexed + 2217779487U, // UMULLv8i16_v4i32 + 2218307052U, // UMULLv8i8_v8i16 + 167782439U, // UQADD_ZI_B + 201345063U, // UQADD_ZI_D + 239626279U, // UQADD_ZI_H + 268470311U, // UQADD_ZI_S + 167782439U, // UQADD_ZZZ_B + 201345063U, // UQADD_ZZZ_D + 2387109927U, // UQADD_ZZZ_H + 268470311U, // UQADD_ZZZ_S + 68200487U, // UQADDv16i8 + 100714535U, // UQADDv1i16 + 100714535U, // UQADDv1i32 + 100714535U, // UQADDv1i64 + 100714535U, // UQADDv1i8 + 2216208423U, // UQADDv2i32 + 2216732711U, // UQADDv2i64 + 69773351U, // UQADDv4i16 + 70297639U, // UQADDv4i32 + 2218305575U, // UQADDv8i16 + 2218829863U, // UQADDv8i8 + 536921173U, // UQDECB_WPiI + 536921173U, // UQDECB_XPiI + 536922053U, // UQDECD_WPiI + 536922053U, // UQDECD_XPiI + 536889285U, // UQDECD_ZPiI + 536922637U, // UQDECH_WPiI + 536922637U, // UQDECH_XPiI + 6842893U, // UQDECH_ZPiI + 2315308989U, // UQDECP_WP_B + 2348863421U, // UQDECP_WP_D + 2717962173U, // UQDECP_WP_H + 2415972285U, // UQDECP_WP_S + 2315308989U, // UQDECP_XP_B + 2348863421U, // UQDECP_XP_D + 2717962173U, // UQDECP_XP_H + 2415972285U, // UQDECP_XP_S + 2147504061U, // UQDECP_ZP_D + 604532669U, // UQDECP_ZP_H + 2147520445U, // UQDECP_ZP_S + 536925357U, // UQDECW_WPiI + 536925357U, // UQDECW_XPiI + 536908973U, // UQDECW_ZPiI + 536921189U, // UQINCB_WPiI + 536921189U, // UQINCB_XPiI + 536922069U, // UQINCD_WPiI + 536922069U, // UQINCD_XPiI + 536889301U, // UQINCD_ZPiI + 536922653U, // UQINCH_WPiI + 536922653U, // UQINCH_XPiI + 6842909U, // UQINCH_ZPiI + 2315309005U, // UQINCP_WP_B + 2348863437U, // UQINCP_WP_D + 2717962189U, // UQINCP_WP_H + 2415972301U, // UQINCP_WP_S + 2315309005U, // UQINCP_XP_B + 2348863437U, // UQINCP_XP_D + 2717962189U, // UQINCP_XP_H + 2415972301U, // UQINCP_XP_S + 2147504077U, // UQINCP_ZP_D + 604532685U, // UQINCP_ZP_H + 2147520461U, // UQINCP_ZP_S + 536925373U, // UQINCW_WPiI + 536925373U, // UQINCW_XPiI + 536908989U, // UQINCW_ZPiI + 68201893U, // UQRSHLv16i8 + 100715941U, // UQRSHLv1i16 + 100715941U, // UQRSHLv1i32 + 100715941U, // UQRSHLv1i64 + 100715941U, // UQRSHLv1i8 + 2216209829U, // UQRSHLv2i32 + 2216734117U, // UQRSHLv2i64 + 69774757U, // UQRSHLv4i16 + 70299045U, // UQRSHLv4i32 + 2218306981U, // UQRSHLv8i16 + 2218831269U, // UQRSHLv8i8 + 100716328U, // UQRSHRNb + 100716328U, // UQRSHRNh + 100716328U, // UQRSHRNs + 2282807671U, // UQRSHRNv16i8_shift + 2216210216U, // UQRSHRNv2i32_shift + 69775144U, // UQRSHRNv4i16_shift + 2284904823U, // UQRSHRNv4i32_shift + 137945463U, // UQRSHRNv8i16_shift + 2218831656U, // UQRSHRNv8i8_shift + 100715926U, // UQSHLb + 100715926U, // UQSHLd + 100715926U, // UQSHLh + 100715926U, // UQSHLs + 68201878U, // UQSHLv16i8 + 68201878U, // UQSHLv16i8_shift + 100715926U, // UQSHLv1i16 + 100715926U, // UQSHLv1i32 + 100715926U, // UQSHLv1i64 + 100715926U, // UQSHLv1i8 + 2216209814U, // UQSHLv2i32 + 2216209814U, // UQSHLv2i32_shift + 2216734102U, // UQSHLv2i64 + 2216734102U, // UQSHLv2i64_shift + 69774742U, // UQSHLv4i16 + 69774742U, // UQSHLv4i16_shift + 70299030U, // UQSHLv4i32 + 70299030U, // UQSHLv4i32_shift + 2218306966U, // UQSHLv8i16 + 2218306966U, // UQSHLv8i16_shift + 2218831254U, // UQSHLv8i8 + 2218831254U, // UQSHLv8i8_shift + 100716311U, // UQSHRNb + 100716311U, // UQSHRNh + 100716311U, // UQSHRNs + 2282807652U, // UQSHRNv16i8_shift + 2216210199U, // UQSHRNv2i32_shift + 69775127U, // UQSHRNv4i16_shift + 2284904804U, // UQSHRNv4i32_shift + 137945444U, // UQSHRNv8i16_shift + 2218831639U, // UQSHRNv8i8_shift + 167782091U, // UQSUB_ZI_B + 201344715U, // UQSUB_ZI_D + 239625931U, // UQSUB_ZI_H + 268469963U, // UQSUB_ZI_S + 167782091U, // UQSUB_ZZZ_B + 201344715U, // UQSUB_ZZZ_D + 2387109579U, // UQSUB_ZZZ_H + 268469963U, // UQSUB_ZZZ_S + 68200139U, // UQSUBv16i8 + 100714187U, // UQSUBv1i16 + 100714187U, // UQSUBv1i32 + 100714187U, // UQSUBv1i64 + 100714187U, // UQSUBv1i8 + 2216208075U, // UQSUBv2i32 + 2216732363U, // UQSUBv2i64 + 69773003U, // UQSUBv4i16 + 70297291U, // UQSUBv4i32 + 2218305227U, // UQSUBv8i16 + 2218829515U, // UQSUBv8i8 + 135324055U, // UQXTNv16i8 + 2248200012U, // UQXTNv1i16 + 2248200012U, // UQXTNv1i32 + 2248200012U, // UQXTNv1i8 + 2216210252U, // UQXTNv2i32 + 2217258828U, // UQXTNv4i16 + 2284904855U, // UQXTNv4i32 + 2285429143U, // UQXTNv8i16 + 71348044U, // UQXTNv8i8 + 68724924U, // URECPEv2i32 + 2217781436U, // URECPEv4i32 + 68200441U, // URHADDv16i8 + 2216208377U, // URHADDv2i32 + 69773305U, // URHADDv4i16 + 70297593U, // URHADDv4i32 + 2218305529U, // URHADDv8i16 + 2218829817U, // URHADDv8i8 + 68201908U, // URSHLv16i8 + 100715956U, // URSHLv1i64 + 2216209844U, // URSHLv2i32 + 2216734132U, // URSHLv2i64 + 69774772U, // URSHLv4i16 + 70299060U, // URSHLv4i32 + 2218306996U, // URSHLv8i16 + 2218831284U, // URSHLv8i8 + 100716801U, // URSHRd + 68202753U, // URSHRv16i8_shift + 2216210689U, // URSHRv2i32_shift + 2216734977U, // URSHRv2i64_shift + 69775617U, // URSHRv4i16_shift + 70299905U, // URSHRv4i32_shift + 2218307841U, // URSHRv8i16_shift + 2218832129U, // URSHRv8i8_shift + 68724970U, // URSQRTEv2i32 + 2217781482U, // URSQRTEv4i32 + 369189641U, // URSRAd + 135324425U, // URSRAv16i8_shift + 2283332361U, // URSRAv2i32_shift + 2283856649U, // URSRAv2i64_shift + 136897289U, // URSRAv4i16_shift + 137421577U, // URSRAv4i32_shift + 2285429513U, // URSRAv8i16_shift + 2285953801U, // URSRAv8i8_shift + 70820093U, // USHLLv16i8_shift + 2216734158U, // USHLLv2i32_shift + 70299086U, // USHLLv4i16_shift + 69247229U, // USHLLv4i32_shift + 2217779453U, // USHLLv8i16_shift + 2218307022U, // USHLLv8i8_shift + 68201921U, // USHLv16i8 + 100715969U, // USHLv1i64 + 2216209857U, // USHLv2i32 + 2216734145U, // USHLv2i64 + 69774785U, // USHLv4i16 + 70299073U, // USHLv4i32 + 2218307009U, // USHLv8i16 + 2218831297U, // USHLv8i8 + 100716814U, // USHRd + 68202766U, // USHRv16i8_shift + 2216210702U, // USHRv2i32_shift + 2216734990U, // USHRv2i64_shift + 69775630U, // USHRv4i16_shift + 70299918U, // USHRv4i32_shift + 2218307854U, // USHRv8i16_shift + 2218832142U, // USHRv8i8_shift + 135325726U, // USQADDv16i8 + 2516674590U, // USQADDv1i16 + 2516674590U, // USQADDv1i32 + 2516674590U, // USQADDv1i64 + 2516674590U, // USQADDv1i8 + 135850014U, // USQADDv2i32 + 2283857950U, // USQADDv2i64 + 136898590U, // USQADDv4i16 + 2284906526U, // USQADDv4i32 + 137947166U, // USQADDv8i16 + 2285955102U, // USQADDv8i8 + 369189654U, // USRAd + 135324438U, // USRAv16i8_shift + 2283332374U, // USRAv2i32_shift + 2283856662U, // USRAv2i64_shift + 136897302U, // USRAv4i16_shift + 137421590U, // USRAv4i32_shift + 2285429526U, // USRAv8i16_shift + 2285953814U, // USRAv8i8_shift + 70820045U, // USUBLv16i8_v8i16 + 2216734021U, // USUBLv2i32_v2i64 + 70298949U, // USUBLv4i16_v4i32 + 69247181U, // USUBLv4i32_v2i64 + 2217779405U, // USUBLv8i16_v4i32 + 2218306885U, // USUBLv8i8_v8i16 + 2218303974U, // USUBWv16i8_v8i16 + 2216735893U, // USUBWv2i32_v2i64 + 70300821U, // USUBWv4i16_v4i32 + 2216731110U, // USUBWv4i32_v2i64 + 70296038U, // USUBWv8i16_v4i32 + 2218308757U, // USUBWv8i8_v8i16 + 2415938659U, // UUNPKHI_ZZ_D + 27290723U, // UUNPKHI_ZZ_H + 2717944931U, // UUNPKHI_ZZ_S + 2415939479U, // UUNPKLO_ZZ_D + 27291543U, // UUNPKLO_ZZ_H + 2717945751U, // UUNPKLO_ZZ_S + 18075U, // UXTB_ZPmZ_D + 2181588635U, // UXTB_ZPmZ_H + 34459U, // UXTB_ZPmZ_S + 19500U, // UXTH_ZPmZ_D + 35884U, // UXTH_ZPmZ_S + 21821U, // UXTW_ZPmZ_D + 167780401U, // UZP1_PPP_B + 201343025U, // UZP1_PPP_D + 2387107889U, // UZP1_PPP_H + 268468273U, // UZP1_PPP_S + 167780401U, // UZP1_ZZZ_B + 201343025U, // UZP1_ZZZ_D + 2387107889U, // UZP1_ZZZ_H + 268468273U, // UZP1_ZZZ_S + 68198449U, // UZP1v16i8 + 2216206385U, // UZP1v2i32 + 2216730673U, // UZP1v2i64 + 69771313U, // UZP1v4i16 + 70295601U, // UZP1v4i32 + 2218303537U, // UZP1v8i16 + 2218827825U, // UZP1v8i8 + 167780812U, // UZP2_PPP_B + 201343436U, // UZP2_PPP_D + 2387108300U, // UZP2_PPP_H + 268468684U, // UZP2_PPP_S + 167780812U, // UZP2_ZZZ_B + 201343436U, // UZP2_ZZZ_D + 2387108300U, // UZP2_ZZZ_H + 268468684U, // UZP2_ZZZ_S + 68198860U, // UZP2v16i8 + 2216206796U, // UZP2v2i32 + 2216731084U, // UZP2v2i64 + 69771724U, // UZP2v4i16 + 70296012U, // UZP2v4i32 + 2218303948U, // UZP2v8i16 + 2218828236U, // UZP2v8i8 + 100673670U, // WHILELE_PWW_B + 100681862U, // WHILELE_PWW_D + 242772102U, // WHILELE_PWW_H + 100698246U, // WHILELE_PWW_S + 100673670U, // WHILELE_PXX_B + 100681862U, // WHILELE_PXX_D + 242772102U, // WHILELE_PXX_H + 100698246U, // WHILELE_PXX_S + 100675452U, // WHILELO_PWW_B + 100683644U, // WHILELO_PWW_D + 242773884U, // WHILELO_PWW_H + 100700028U, // WHILELO_PWW_S + 100675452U, // WHILELO_PXX_B + 100683644U, // WHILELO_PXX_D + 242773884U, // WHILELO_PXX_H + 100700028U, // WHILELO_PXX_S + 100676169U, // WHILELS_PWW_B + 100684361U, // WHILELS_PWW_D + 242774601U, // WHILELS_PWW_H + 100700745U, // WHILELS_PWW_S + 100676169U, // WHILELS_PXX_B + 100684361U, // WHILELS_PXX_D + 242774601U, // WHILELS_PXX_H + 100700745U, // WHILELS_PXX_S + 100676358U, // WHILELT_PWW_B + 100684550U, // WHILELT_PWW_D + 242774790U, // WHILELT_PWW_H + 100700934U, // WHILELT_PWW_S + 100676358U, // WHILELT_PXX_B + 100684550U, // WHILELT_PXX_D + 242774790U, // WHILELT_PXX_H + 100700934U, // WHILELT_PXX_S + 6303987U, // WRFFR + 2216734934U, // XAR + 6342582U, // XPACD + 6343754U, // XPACI + 5905U, // XPACLRI + 135324049U, // XTNv16i8 + 2216210247U, // XTNv2i32 + 2217258823U, // XTNv4i16 + 2284904849U, // XTNv4i32 + 2285429137U, // XTNv8i16 + 71348039U, // XTNv8i8 + 167780395U, // ZIP1_PPP_B + 201343019U, // ZIP1_PPP_D + 2387107883U, // ZIP1_PPP_H + 268468267U, // ZIP1_PPP_S + 167780395U, // ZIP1_ZZZ_B + 201343019U, // ZIP1_ZZZ_D + 2387107883U, // ZIP1_ZZZ_H + 268468267U, // ZIP1_ZZZ_S + 68198443U, // ZIP1v16i8 + 2216206379U, // ZIP1v2i32 + 2216730667U, // ZIP1v2i64 + 69771307U, // ZIP1v4i16 + 70295595U, // ZIP1v4i32 + 2218303531U, // ZIP1v8i16 + 2218827819U, // ZIP1v8i8 + 167780806U, // ZIP2_PPP_B + 201343430U, // ZIP2_PPP_D + 2387108294U, // ZIP2_PPP_H + 268468678U, // ZIP2_PPP_S + 167780806U, // ZIP2_ZZZ_B + 201343430U, // ZIP2_ZZZ_D + 2387108294U, // ZIP2_ZZZ_H + 268468678U, // ZIP2_ZZZ_S + 68198854U, // ZIP2v16i8 + 2216206790U, // ZIP2v2i32 + 2216731078U, // ZIP2v2i64 + 69771718U, // ZIP2v4i16 + 70296006U, // ZIP2v4i32 + 2218303942U, // ZIP2v8i16 + 2218828230U, // ZIP2v8i8 + 302003021U, // anonymous_1349 }; - static const uint32_t OpInfo2[] = { + static const uint32_t OpInfo1[] = { 0U, // PHI 0U, // INLINEASM 0U, // CFI_INSTRUCTION 0U, // EH_LABEL 0U, // GC_LABEL + 0U, // ANNOTATION_LABEL 0U, // KILL 0U, // EXTRACT_SUBREG 0U, // INSERT_SUBREG @@ -2420,725 +5347,1846 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // SUBREG_TO_REG 0U, // COPY_TO_REGCLASS 0U, // DBG_VALUE + 0U, // DBG_LABEL 0U, // REG_SEQUENCE 0U, // COPY 0U, // BUNDLE 0U, // LIFETIME_START 0U, // LIFETIME_END 0U, // STACKMAP + 0U, // FENTRY_CALL 0U, // PATCHPOINT 0U, // LOAD_STACK_GUARD 0U, // STATEPOINT - 0U, // FRAME_ALLOC - 0U, // ABSv16i8 - 0U, // ABSv1i64 - 0U, // ABSv2i32 - 0U, // ABSv2i64 - 0U, // ABSv4i16 - 0U, // ABSv4i32 - 0U, // ABSv8i16 - 0U, // ABSv8i8 - 1U, // ADCSWr - 1U, // ADCSXr - 1U, // ADCWr - 1U, // ADCXr - 265U, // ADDHNv2i64_v2i32 - 273U, // ADDHNv2i64_v4i32 - 521U, // ADDHNv4i32_v4i16 - 529U, // ADDHNv4i32_v8i16 - 785U, // ADDHNv8i16_v16i8 - 777U, // ADDHNv8i16_v8i8 - 1033U, // ADDPv16i8 - 1289U, // ADDPv2i32 - 265U, // ADDPv2i64 - 0U, // ADDPv2i64p - 1545U, // ADDPv4i16 - 521U, // ADDPv4i32 - 777U, // ADDPv8i16 - 1801U, // ADDPv8i8 - 25U, // ADDSWri + 0U, // LOCAL_ESCAPE + 0U, // FAULTING_OP + 0U, // PATCHABLE_OP + 0U, // PATCHABLE_FUNCTION_ENTER + 0U, // PATCHABLE_RET + 0U, // PATCHABLE_FUNCTION_EXIT + 0U, // PATCHABLE_TAIL_CALL + 0U, // PATCHABLE_EVENT_CALL + 0U, // PATCHABLE_TYPED_EVENT_CALL + 0U, // ICALL_BRANCH_FUNNEL + 0U, // G_ADD + 0U, // G_SUB + 0U, // G_MUL + 0U, // G_SDIV + 0U, // G_UDIV + 0U, // G_SREM + 0U, // G_UREM + 0U, // G_AND + 0U, // G_OR + 0U, // G_XOR + 0U, // G_IMPLICIT_DEF + 0U, // G_PHI + 0U, // G_FRAME_INDEX + 0U, // G_GLOBAL_VALUE + 0U, // G_EXTRACT + 0U, // G_UNMERGE_VALUES + 0U, // G_INSERT + 0U, // G_MERGE_VALUES + 0U, // G_PTRTOINT + 0U, // G_INTTOPTR + 0U, // G_BITCAST + 0U, // G_LOAD + 0U, // G_SEXTLOAD + 0U, // G_ZEXTLOAD + 0U, // G_STORE + 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS + 0U, // G_ATOMIC_CMPXCHG + 0U, // G_ATOMICRMW_XCHG + 0U, // G_ATOMICRMW_ADD + 0U, // G_ATOMICRMW_SUB + 0U, // G_ATOMICRMW_AND + 0U, // G_ATOMICRMW_NAND + 0U, // G_ATOMICRMW_OR + 0U, // G_ATOMICRMW_XOR + 0U, // G_ATOMICRMW_MAX + 0U, // G_ATOMICRMW_MIN + 0U, // G_ATOMICRMW_UMAX + 0U, // G_ATOMICRMW_UMIN + 0U, // G_BRCOND + 0U, // G_BRINDIRECT + 0U, // G_INTRINSIC + 0U, // G_INTRINSIC_W_SIDE_EFFECTS + 0U, // G_ANYEXT + 0U, // G_TRUNC + 0U, // G_CONSTANT + 0U, // G_FCONSTANT + 0U, // G_VASTART + 0U, // G_VAARG + 0U, // G_SEXT + 0U, // G_ZEXT + 0U, // G_SHL + 0U, // G_LSHR + 0U, // G_ASHR + 0U, // G_ICMP + 0U, // G_FCMP + 0U, // G_SELECT + 0U, // G_UADDE + 0U, // G_USUBE + 0U, // G_SADDO + 0U, // G_SSUBO + 0U, // G_UMULO + 0U, // G_SMULO + 0U, // G_UMULH + 0U, // G_SMULH + 0U, // G_FADD + 0U, // G_FSUB + 0U, // G_FMUL + 0U, // G_FMA + 0U, // G_FDIV + 0U, // G_FREM + 0U, // G_FPOW + 0U, // G_FEXP + 0U, // G_FEXP2 + 0U, // G_FLOG + 0U, // G_FLOG2 + 0U, // G_FNEG + 0U, // G_FPEXT + 0U, // G_FPTRUNC + 0U, // G_FPTOSI + 0U, // G_FPTOUI + 0U, // G_SITOFP + 0U, // G_UITOFP + 0U, // G_FABS + 0U, // G_GEP + 0U, // G_PTR_MASK + 0U, // G_BR + 0U, // G_INSERT_VECTOR_ELT + 0U, // G_EXTRACT_VECTOR_ELT + 0U, // G_SHUFFLE_VECTOR + 0U, // G_BSWAP + 0U, // G_ADDRSPACE_CAST + 0U, // G_BLOCK_ADDR + 0U, // ABS_ZPmZ_B + 64U, // ABS_ZPmZ_D + 128U, // ABS_ZPmZ_H + 192U, // ABS_ZPmZ_S + 1U, // ABSv16i8 + 1U, // ABSv1i64 + 2U, // ABSv2i32 + 2U, // ABSv2i64 + 3U, // ABSv4i16 + 3U, // ABSv4i32 + 4U, // ABSv8i16 + 4U, // ABSv8i8 + 261U, // ADCSWr + 261U, // ADCSXr + 261U, // ADCWr + 261U, // ADCXr + 8517U, // ADDHNv2i64_v2i32 + 8581U, // ADDHNv2i64_v4i32 + 16710U, // ADDHNv4i32_v4i16 + 16774U, // ADDHNv4i32_v8i16 + 24966U, // ADDHNv8i16_v16i8 + 24902U, // ADDHNv8i16_v8i8 + 261U, // ADDPL_XXI + 33095U, // ADDPv16i8 + 41287U, // ADDPv2i32 + 8517U, // ADDPv2i64 + 2U, // ADDPv2i64p + 49480U, // ADDPv4i16 + 16710U, // ADDPv4i32 + 24902U, // ADDPv8i16 + 57672U, // ADDPv8i8 + 453U, // ADDSWri 0U, // ADDSWrr - 33U, // ADDSWrs - 41U, // ADDSWrx - 25U, // ADDSXri + 517U, // ADDSWrs + 581U, // ADDSWrx + 453U, // ADDSXri 0U, // ADDSXrr - 33U, // ADDSXrs - 41U, // ADDSXrx - 2049U, // ADDSXrx64 - 0U, // ADDVv16i8v - 0U, // ADDVv4i16v - 0U, // ADDVv4i32v - 0U, // ADDVv8i16v - 0U, // ADDVv8i8v - 25U, // ADDWri + 517U, // ADDSXrs + 581U, // ADDSXrx + 65797U, // ADDSXrx64 + 261U, // ADDVL_XXI + 1U, // ADDVv16i8v + 3U, // ADDVv4i16v + 3U, // ADDVv4i32v + 4U, // ADDVv8i16v + 4U, // ADDVv8i8v + 453U, // ADDWri 0U, // ADDWrr - 33U, // ADDWrs - 41U, // ADDWrx - 25U, // ADDXri + 517U, // ADDWrs + 581U, // ADDWrx + 453U, // ADDXri 0U, // ADDXrr - 33U, // ADDXrs - 41U, // ADDXrx - 2049U, // ADDXrx64 - 1033U, // ADDv16i8 - 1U, // ADDv1i64 - 1289U, // ADDv2i32 - 265U, // ADDv2i64 - 1545U, // ADDv4i16 - 521U, // ADDv4i32 - 777U, // ADDv8i16 - 1801U, // ADDv8i8 + 517U, // ADDXrs + 581U, // ADDXrx + 65797U, // ADDXrx64 + 645U, // ADD_ZI_B + 709U, // ADD_ZI_D + 9U, // ADD_ZI_H + 773U, // ADD_ZI_S + 74560U, // ADD_ZPmZ_B + 598912U, // ADD_ZPmZ_D + 1131465U, // ADD_ZPmZ_H + 1647616U, // ADD_ZPmZ_S + 837U, // ADD_ZZZ_B + 901U, // ADD_ZZZ_D + 137U, // ADD_ZZZ_H + 1029U, // ADD_ZZZ_S + 0U, // ADDlowTLS + 33095U, // ADDv16i8 + 261U, // ADDv1i64 + 41287U, // ADDv2i32 + 8517U, // ADDv2i64 + 49480U, // ADDv4i16 + 16710U, // ADDv4i32 + 24902U, // ADDv8i16 + 57672U, // ADDv8i8 0U, // ADJCALLSTACKDOWN 0U, // ADJCALLSTACKUP - 0U, // ADR + 1U, // ADR 0U, // ADRP - 0U, // AESDrr - 0U, // AESErr - 0U, // AESIMCrr - 0U, // AESMCrr - 49U, // ANDSWri + 1093U, // ADR_LSL_ZZZ_D_0 + 1157U, // ADR_LSL_ZZZ_D_1 + 1221U, // ADR_LSL_ZZZ_D_2 + 1285U, // ADR_LSL_ZZZ_D_3 + 1349U, // ADR_LSL_ZZZ_S_0 + 1413U, // ADR_LSL_ZZZ_S_1 + 1477U, // ADR_LSL_ZZZ_S_2 + 1541U, // ADR_LSL_ZZZ_S_3 + 1605U, // ADR_SXTW_ZZZ_D_0 + 1669U, // ADR_SXTW_ZZZ_D_1 + 1733U, // ADR_SXTW_ZZZ_D_2 + 1797U, // ADR_SXTW_ZZZ_D_3 + 1861U, // ADR_UXTW_ZZZ_D_0 + 1925U, // ADR_UXTW_ZZZ_D_1 + 1989U, // ADR_UXTW_ZZZ_D_2 + 2053U, // ADR_UXTW_ZZZ_D_3 + 1U, // AESDrr + 1U, // AESErr + 1U, // AESIMCrr + 0U, // AESIMCrrTied + 1U, // AESMCrr + 0U, // AESMCrrTied + 2117U, // ANDSWri 0U, // ANDSWrr - 33U, // ANDSWrs - 57U, // ANDSXri + 517U, // ANDSWrs + 2181U, // ANDSXri 0U, // ANDSXrr - 33U, // ANDSXrs - 49U, // ANDWri + 517U, // ANDSXrs + 74570U, // ANDS_PPzPP + 837U, // ANDV_VPZ_B + 901U, // ANDV_VPZ_D + 2245U, // ANDV_VPZ_H + 1029U, // ANDV_VPZ_S + 2117U, // ANDWri 0U, // ANDWrr - 33U, // ANDWrs - 57U, // ANDXri + 517U, // ANDWrs + 2181U, // ANDXri 0U, // ANDXrr - 33U, // ANDXrs - 1033U, // ANDv16i8 - 1801U, // ANDv8i8 - 1U, // ASRVWr - 1U, // ASRVXr + 517U, // ANDXrs + 74570U, // AND_PPzPP + 2181U, // AND_ZI + 74560U, // AND_ZPmZ_B + 598912U, // AND_ZPmZ_D + 1131465U, // AND_ZPmZ_H + 1647616U, // AND_ZPmZ_S + 901U, // AND_ZZZ + 33095U, // ANDv16i8 + 57672U, // ANDv8i8 + 2171712U, // ASRD_ZPmI_B + 2171776U, // ASRD_ZPmI_D + 91081U, // ASRD_ZPmI_H + 2171904U, // ASRD_ZPmI_S + 74560U, // ASRR_ZPmZ_B + 598912U, // ASRR_ZPmZ_D + 1131465U, // ASRR_ZPmZ_H + 1647616U, // ASRR_ZPmZ_S + 261U, // ASRVWr + 261U, // ASRVXr + 598848U, // ASR_WIDE_ZPmZ_B + 99273U, // ASR_WIDE_ZPmZ_H + 599040U, // ASR_WIDE_ZPmZ_S + 901U, // ASR_WIDE_ZZZ_B + 10U, // ASR_WIDE_ZZZ_H + 901U, // ASR_WIDE_ZZZ_S + 2171712U, // ASR_ZPmI_B + 2171776U, // ASR_ZPmI_D + 91081U, // ASR_ZPmI_H + 2171904U, // ASR_ZPmI_S + 74560U, // ASR_ZPmZ_B + 598912U, // ASR_ZPmZ_D + 1131465U, // ASR_ZPmZ_H + 1647616U, // ASR_ZPmZ_S + 261U, // ASR_ZZI_B + 261U, // ASR_ZZI_D + 11U, // ASR_ZZI_H + 261U, // ASR_ZZI_S + 1U, // AUTDA + 1U, // AUTDB + 0U, // AUTDZA + 0U, // AUTDZB + 1U, // AUTIA + 0U, // AUTIA1716 + 0U, // AUTIASP + 0U, // AUTIAZ + 1U, // AUTIB + 0U, // AUTIB1716 + 0U, // AUTIBSP + 0U, // AUTIBZ + 0U, // AUTIZA + 0U, // AUTIZB 0U, // B - 2369U, // BFMWri - 2369U, // BFMXri + 36282695U, // BCAX + 3221765U, // BFMWri + 3221765U, // BFMXri 0U, // BICSWrr - 33U, // BICSWrs + 517U, // BICSWrs 0U, // BICSXrr - 33U, // BICSXrs + 517U, // BICSXrs + 74570U, // BICS_PPzPP 0U, // BICWrr - 33U, // BICWrs + 517U, // BICWrs 0U, // BICXrr - 33U, // BICXrs - 1033U, // BICv16i8 + 517U, // BICXrs + 74570U, // BIC_PPzPP + 74560U, // BIC_ZPmZ_B + 598912U, // BIC_ZPmZ_D + 1131465U, // BIC_ZPmZ_H + 1647616U, // BIC_ZPmZ_S + 901U, // BIC_ZZZ + 33095U, // BICv16i8 0U, // BICv2i32 0U, // BICv4i16 0U, // BICv4i32 0U, // BICv8i16 - 1801U, // BICv8i8 - 1033U, // BIFv16i8 - 1801U, // BIFv8i8 - 1041U, // BITv16i8 - 1809U, // BITv8i8 + 57672U, // BICv8i8 + 33095U, // BIFv16i8 + 57672U, // BIFv8i8 + 33159U, // BITv16i8 + 57736U, // BITv8i8 0U, // BL 0U, // BLR + 1U, // BLRAA + 0U, // BLRAAZ + 1U, // BLRAB + 0U, // BLRABZ 0U, // BR + 1U, // BRAA + 0U, // BRAAZ + 1U, // BRAB + 0U, // BRABZ 0U, // BRK - 1041U, // BSLv16i8 - 1809U, // BSLv8i8 + 842U, // BRKAS_PPzP + 0U, // BRKA_PPmP + 842U, // BRKA_PPzP + 842U, // BRKBS_PPzP + 0U, // BRKB_PPmP + 842U, // BRKB_PPzP + 74570U, // BRKNS_PPzP + 74570U, // BRKN_PPzP + 74570U, // BRKPAS_PPzPP + 74570U, // BRKPA_PPzPP + 74570U, // BRKPBS_PPzPP + 74570U, // BRKPB_PPzPP + 33159U, // BSLv16i8 + 57736U, // BSLv8i8 0U, // Bcc + 117003U, // CASAB + 117003U, // CASAH + 117003U, // CASALB + 117003U, // CASALH + 117003U, // CASALW + 117003U, // CASALX + 117003U, // CASAW + 117003U, // CASAX + 117003U, // CASB + 117003U, // CASH + 117003U, // CASLB + 117003U, // CASLH + 117003U, // CASLW + 117003U, // CASLX + 0U, // CASPALW + 0U, // CASPALX + 0U, // CASPAW + 0U, // CASPAX + 0U, // CASPLW + 0U, // CASPLX + 0U, // CASPW + 0U, // CASPX + 117003U, // CASW + 117003U, // CASX 0U, // CBNZW 0U, // CBNZX 0U, // CBZW 0U, // CBZX - 10497U, // CCMNWi - 10497U, // CCMNWr - 10497U, // CCMNXi - 10497U, // CCMNXr - 10497U, // CCMPWi - 10497U, // CCMPWr - 10497U, // CCMPXi - 10497U, // CCMPXr + 3744005U, // CCMNWi + 3744005U, // CCMNWr + 3744005U, // CCMNXi + 3744005U, // CCMNXr + 3744005U, // CCMPWi + 3744005U, // CCMPWr + 3744005U, // CCMPXi + 3744005U, // CCMPXr + 0U, // CFINV + 73989U, // CLASTA_RPZ_B + 598277U, // CLASTA_RPZ_D + 4268293U, // CLASTA_RPZ_H + 1646853U, // CLASTA_RPZ_S + 73989U, // CLASTA_VPZ_B + 598277U, // CLASTA_VPZ_D + 4268293U, // CLASTA_VPZ_H + 1646853U, // CLASTA_VPZ_S + 74565U, // CLASTA_ZPZ_B + 598917U, // CLASTA_ZPZ_D + 1131465U, // CLASTA_ZPZ_H + 1647621U, // CLASTA_ZPZ_S + 73989U, // CLASTB_RPZ_B + 598277U, // CLASTB_RPZ_D + 4268293U, // CLASTB_RPZ_H + 1646853U, // CLASTB_RPZ_S + 73989U, // CLASTB_VPZ_B + 598277U, // CLASTB_VPZ_D + 4268293U, // CLASTB_VPZ_H + 1646853U, // CLASTB_VPZ_S + 74565U, // CLASTB_ZPZ_B + 598917U, // CLASTB_ZPZ_D + 1131465U, // CLASTB_ZPZ_H + 1647621U, // CLASTB_ZPZ_S 0U, // CLREX - 0U, // CLSWr - 0U, // CLSXr - 0U, // CLSv16i8 - 0U, // CLSv2i32 - 0U, // CLSv4i16 - 0U, // CLSv4i32 - 0U, // CLSv8i16 - 0U, // CLSv8i8 - 0U, // CLZWr - 0U, // CLZXr - 0U, // CLZv16i8 - 0U, // CLZv2i32 - 0U, // CLZv4i16 - 0U, // CLZv4i32 - 0U, // CLZv8i16 - 0U, // CLZv8i8 - 1033U, // CMEQv16i8 - 2U, // CMEQv16i8rz - 1U, // CMEQv1i64 - 2U, // CMEQv1i64rz - 1289U, // CMEQv2i32 - 2U, // CMEQv2i32rz - 265U, // CMEQv2i64 - 2U, // CMEQv2i64rz - 1545U, // CMEQv4i16 - 2U, // CMEQv4i16rz - 521U, // CMEQv4i32 - 2U, // CMEQv4i32rz - 777U, // CMEQv8i16 - 2U, // CMEQv8i16rz - 1801U, // CMEQv8i8 - 2U, // CMEQv8i8rz - 1033U, // CMGEv16i8 - 2U, // CMGEv16i8rz - 1U, // CMGEv1i64 - 2U, // CMGEv1i64rz - 1289U, // CMGEv2i32 - 2U, // CMGEv2i32rz - 265U, // CMGEv2i64 - 2U, // CMGEv2i64rz - 1545U, // CMGEv4i16 - 2U, // CMGEv4i16rz - 521U, // CMGEv4i32 - 2U, // CMGEv4i32rz - 777U, // CMGEv8i16 - 2U, // CMGEv8i16rz - 1801U, // CMGEv8i8 - 2U, // CMGEv8i8rz - 1033U, // CMGTv16i8 - 2U, // CMGTv16i8rz - 1U, // CMGTv1i64 - 2U, // CMGTv1i64rz - 1289U, // CMGTv2i32 - 2U, // CMGTv2i32rz - 265U, // CMGTv2i64 - 2U, // CMGTv2i64rz - 1545U, // CMGTv4i16 - 2U, // CMGTv4i16rz - 521U, // CMGTv4i32 - 2U, // CMGTv4i32rz - 777U, // CMGTv8i16 - 2U, // CMGTv8i16rz - 1801U, // CMGTv8i8 - 2U, // CMGTv8i8rz - 1033U, // CMHIv16i8 - 1U, // CMHIv1i64 - 1289U, // CMHIv2i32 - 265U, // CMHIv2i64 - 1545U, // CMHIv4i16 - 521U, // CMHIv4i32 - 777U, // CMHIv8i16 - 1801U, // CMHIv8i8 - 1033U, // CMHSv16i8 - 1U, // CMHSv1i64 - 1289U, // CMHSv2i32 - 265U, // CMHSv2i64 - 1545U, // CMHSv4i16 - 521U, // CMHSv4i32 - 777U, // CMHSv8i16 - 1801U, // CMHSv8i8 - 2U, // CMLEv16i8rz - 2U, // CMLEv1i64rz - 2U, // CMLEv2i32rz - 2U, // CMLEv2i64rz - 2U, // CMLEv4i16rz - 2U, // CMLEv4i32rz - 2U, // CMLEv8i16rz - 2U, // CMLEv8i8rz - 2U, // CMLTv16i8rz - 2U, // CMLTv1i64rz - 2U, // CMLTv2i32rz - 2U, // CMLTv2i64rz - 2U, // CMLTv4i16rz - 2U, // CMLTv4i32rz - 2U, // CMLTv8i16rz - 2U, // CMLTv8i8rz - 1033U, // CMTSTv16i8 - 1U, // CMTSTv1i64 - 1289U, // CMTSTv2i32 - 265U, // CMTSTv2i64 - 1545U, // CMTSTv4i16 - 521U, // CMTSTv4i32 - 777U, // CMTSTv8i16 - 1801U, // CMTSTv8i8 - 0U, // CNTv16i8 - 0U, // CNTv8i8 - 75U, // CPYi16 - 75U, // CPYi32 - 75U, // CPYi64 - 75U, // CPYi8 - 1U, // CRC32Brr - 1U, // CRC32CBrr - 1U, // CRC32CHrr - 1U, // CRC32CWrr - 1U, // CRC32CXrr - 1U, // CRC32Hrr - 1U, // CRC32Wrr - 1U, // CRC32Xrr - 10497U, // CSELWr - 10497U, // CSELXr - 10497U, // CSINCWr - 10497U, // CSINCXr - 10497U, // CSINVWr - 10497U, // CSINVXr - 10497U, // CSNEGWr - 10497U, // CSNEGXr + 1U, // CLSWr + 1U, // CLSXr + 0U, // CLS_ZPmZ_B + 64U, // CLS_ZPmZ_D + 128U, // CLS_ZPmZ_H + 192U, // CLS_ZPmZ_S + 1U, // CLSv16i8 + 2U, // CLSv2i32 + 3U, // CLSv4i16 + 3U, // CLSv4i32 + 4U, // CLSv8i16 + 4U, // CLSv8i8 + 1U, // CLZWr + 1U, // CLZXr + 0U, // CLZ_ZPmZ_B + 64U, // CLZ_ZPmZ_D + 128U, // CLZ_ZPmZ_H + 192U, // CLZ_ZPmZ_S + 1U, // CLZv16i8 + 2U, // CLZv2i32 + 3U, // CLZv4i16 + 3U, // CLZv4i32 + 4U, // CLZv8i16 + 4U, // CLZv8i8 + 33095U, // CMEQv16i8 + 12U, // CMEQv16i8rz + 261U, // CMEQv1i64 + 12U, // CMEQv1i64rz + 41287U, // CMEQv2i32 + 13U, // CMEQv2i32rz + 8517U, // CMEQv2i64 + 13U, // CMEQv2i64rz + 49480U, // CMEQv4i16 + 14U, // CMEQv4i16rz + 16710U, // CMEQv4i32 + 14U, // CMEQv4i32rz + 24902U, // CMEQv8i16 + 15U, // CMEQv8i16rz + 57672U, // CMEQv8i8 + 15U, // CMEQv8i8rz + 33095U, // CMGEv16i8 + 12U, // CMGEv16i8rz + 261U, // CMGEv1i64 + 12U, // CMGEv1i64rz + 41287U, // CMGEv2i32 + 13U, // CMGEv2i32rz + 8517U, // CMGEv2i64 + 13U, // CMGEv2i64rz + 49480U, // CMGEv4i16 + 14U, // CMGEv4i16rz + 16710U, // CMGEv4i32 + 14U, // CMGEv4i32rz + 24902U, // CMGEv8i16 + 15U, // CMGEv8i16rz + 57672U, // CMGEv8i8 + 15U, // CMGEv8i8rz + 33095U, // CMGTv16i8 + 12U, // CMGTv16i8rz + 261U, // CMGTv1i64 + 12U, // CMGTv1i64rz + 41287U, // CMGTv2i32 + 13U, // CMGTv2i32rz + 8517U, // CMGTv2i64 + 13U, // CMGTv2i64rz + 49480U, // CMGTv4i16 + 14U, // CMGTv4i16rz + 16710U, // CMGTv4i32 + 14U, // CMGTv4i32rz + 24902U, // CMGTv8i16 + 15U, // CMGTv8i16rz + 57672U, // CMGTv8i8 + 15U, // CMGTv8i8rz + 33095U, // CMHIv16i8 + 261U, // CMHIv1i64 + 41287U, // CMHIv2i32 + 8517U, // CMHIv2i64 + 49480U, // CMHIv4i16 + 16710U, // CMHIv4i32 + 24902U, // CMHIv8i16 + 57672U, // CMHIv8i8 + 33095U, // CMHSv16i8 + 261U, // CMHSv1i64 + 41287U, // CMHSv2i32 + 8517U, // CMHSv2i64 + 49480U, // CMHSv4i16 + 16710U, // CMHSv4i32 + 24902U, // CMHSv8i16 + 57672U, // CMHSv8i8 + 12U, // CMLEv16i8rz + 12U, // CMLEv1i64rz + 13U, // CMLEv2i32rz + 13U, // CMLEv2i64rz + 14U, // CMLEv4i16rz + 14U, // CMLEv4i32rz + 15U, // CMLEv8i16rz + 15U, // CMLEv8i8rz + 12U, // CMLTv16i8rz + 12U, // CMLTv1i64rz + 13U, // CMLTv2i32rz + 13U, // CMLTv2i64rz + 14U, // CMLTv4i16rz + 14U, // CMLTv4i32rz + 15U, // CMLTv8i16rz + 15U, // CMLTv8i8rz + 2171722U, // CMPEQ_PPzZI_B + 2171786U, // CMPEQ_PPzZI_D + 91081U, // CMPEQ_PPzZI_H + 2171914U, // CMPEQ_PPzZI_S + 74570U, // CMPEQ_PPzZZ_B + 598922U, // CMPEQ_PPzZZ_D + 1131465U, // CMPEQ_PPzZZ_H + 1647626U, // CMPEQ_PPzZZ_S + 598858U, // CMPEQ_WIDE_PPzZZ_B + 99273U, // CMPEQ_WIDE_PPzZZ_H + 599050U, // CMPEQ_WIDE_PPzZZ_S + 2171722U, // CMPGE_PPzZI_B + 2171786U, // CMPGE_PPzZI_D + 91081U, // CMPGE_PPzZI_H + 2171914U, // CMPGE_PPzZI_S + 74570U, // CMPGE_PPzZZ_B + 598922U, // CMPGE_PPzZZ_D + 1131465U, // CMPGE_PPzZZ_H + 1647626U, // CMPGE_PPzZZ_S + 598858U, // CMPGE_WIDE_PPzZZ_B + 99273U, // CMPGE_WIDE_PPzZZ_H + 599050U, // CMPGE_WIDE_PPzZZ_S + 2171722U, // CMPGT_PPzZI_B + 2171786U, // CMPGT_PPzZI_D + 91081U, // CMPGT_PPzZI_H + 2171914U, // CMPGT_PPzZI_S + 74570U, // CMPGT_PPzZZ_B + 598922U, // CMPGT_PPzZZ_D + 1131465U, // CMPGT_PPzZZ_H + 1647626U, // CMPGT_PPzZZ_S + 598858U, // CMPGT_WIDE_PPzZZ_B + 99273U, // CMPGT_WIDE_PPzZZ_H + 599050U, // CMPGT_WIDE_PPzZZ_S + 4793162U, // CMPHI_PPzZI_B + 4793226U, // CMPHI_PPzZI_D + 123849U, // CMPHI_PPzZI_H + 4793354U, // CMPHI_PPzZI_S + 74570U, // CMPHI_PPzZZ_B + 598922U, // CMPHI_PPzZZ_D + 1131465U, // CMPHI_PPzZZ_H + 1647626U, // CMPHI_PPzZZ_S + 598858U, // CMPHI_WIDE_PPzZZ_B + 99273U, // CMPHI_WIDE_PPzZZ_H + 599050U, // CMPHI_WIDE_PPzZZ_S + 4793162U, // CMPHS_PPzZI_B + 4793226U, // CMPHS_PPzZI_D + 123849U, // CMPHS_PPzZI_H + 4793354U, // CMPHS_PPzZI_S + 74570U, // CMPHS_PPzZZ_B + 598922U, // CMPHS_PPzZZ_D + 1131465U, // CMPHS_PPzZZ_H + 1647626U, // CMPHS_PPzZZ_S + 598858U, // CMPHS_WIDE_PPzZZ_B + 99273U, // CMPHS_WIDE_PPzZZ_H + 599050U, // CMPHS_WIDE_PPzZZ_S + 2171722U, // CMPLE_PPzZI_B + 2171786U, // CMPLE_PPzZI_D + 91081U, // CMPLE_PPzZI_H + 2171914U, // CMPLE_PPzZI_S + 598858U, // CMPLE_WIDE_PPzZZ_B + 99273U, // CMPLE_WIDE_PPzZZ_H + 599050U, // CMPLE_WIDE_PPzZZ_S + 4793162U, // CMPLO_PPzZI_B + 4793226U, // CMPLO_PPzZI_D + 123849U, // CMPLO_PPzZI_H + 4793354U, // CMPLO_PPzZI_S + 598858U, // CMPLO_WIDE_PPzZZ_B + 99273U, // CMPLO_WIDE_PPzZZ_H + 599050U, // CMPLO_WIDE_PPzZZ_S + 4793162U, // CMPLS_PPzZI_B + 4793226U, // CMPLS_PPzZI_D + 123849U, // CMPLS_PPzZI_H + 4793354U, // CMPLS_PPzZI_S + 598858U, // CMPLS_WIDE_PPzZZ_B + 99273U, // CMPLS_WIDE_PPzZZ_H + 599050U, // CMPLS_WIDE_PPzZZ_S + 2171722U, // CMPLT_PPzZI_B + 2171786U, // CMPLT_PPzZI_D + 91081U, // CMPLT_PPzZI_H + 2171914U, // CMPLT_PPzZI_S + 598858U, // CMPLT_WIDE_PPzZZ_B + 99273U, // CMPLT_WIDE_PPzZZ_H + 599050U, // CMPLT_WIDE_PPzZZ_S + 2171722U, // CMPNE_PPzZI_B + 2171786U, // CMPNE_PPzZI_D + 91081U, // CMPNE_PPzZI_H + 2171914U, // CMPNE_PPzZI_S + 74570U, // CMPNE_PPzZZ_B + 598922U, // CMPNE_PPzZZ_D + 1131465U, // CMPNE_PPzZZ_H + 1647626U, // CMPNE_PPzZZ_S + 598858U, // CMPNE_WIDE_PPzZZ_B + 99273U, // CMPNE_WIDE_PPzZZ_H + 599050U, // CMPNE_WIDE_PPzZZ_S + 0U, // CMP_SWAP_128 + 0U, // CMP_SWAP_16 + 0U, // CMP_SWAP_32 + 0U, // CMP_SWAP_64 + 0U, // CMP_SWAP_8 + 33095U, // CMTSTv16i8 + 261U, // CMTSTv1i64 + 41287U, // CMTSTv2i32 + 8517U, // CMTSTv2i64 + 49480U, // CMTSTv4i16 + 16710U, // CMTSTv4i32 + 24902U, // CMTSTv8i16 + 57672U, // CMTSTv8i8 + 0U, // CNOT_ZPmZ_B + 64U, // CNOT_ZPmZ_D + 128U, // CNOT_ZPmZ_H + 192U, // CNOT_ZPmZ_S + 16U, // CNTB_XPiI + 16U, // CNTD_XPiI + 16U, // CNTH_XPiI + 837U, // CNTP_XPP_B + 901U, // CNTP_XPP_D + 2245U, // CNTP_XPP_H + 1029U, // CNTP_XPP_S + 16U, // CNTW_XPiI + 0U, // CNT_ZPmZ_B + 64U, // CNT_ZPmZ_D + 128U, // CNT_ZPmZ_H + 192U, // CNT_ZPmZ_S + 1U, // CNTv16i8 + 4U, // CNTv8i8 + 901U, // COMPACT_ZPZ_D + 1029U, // COMPACT_ZPZ_S + 2368U, // CPY_ZPmI_B + 2432U, // CPY_ZPmI_D + 16U, // CPY_ZPmI_H + 2496U, // CPY_ZPmI_S + 2304U, // CPY_ZPmR_B + 2304U, // CPY_ZPmR_D + 145U, // CPY_ZPmR_H + 2304U, // CPY_ZPmR_S + 2304U, // CPY_ZPmV_B + 2304U, // CPY_ZPmV_D + 145U, // CPY_ZPmV_H + 2304U, // CPY_ZPmV_S + 2570U, // CPY_ZPzI_B + 2634U, // CPY_ZPzI_D + 17U, // CPY_ZPzI_H + 2698U, // CPY_ZPzI_S + 2770U, // CPYi16 + 2770U, // CPYi32 + 2771U, // CPYi64 + 2771U, // CPYi8 + 261U, // CRC32Brr + 261U, // CRC32CBrr + 261U, // CRC32CHrr + 261U, // CRC32CWrr + 261U, // CRC32CXrr + 261U, // CRC32Hrr + 261U, // CRC32Wrr + 261U, // CRC32Xrr + 3744005U, // CSELWr + 3744005U, // CSELXr + 3744005U, // CSINCWr + 3744005U, // CSINCXr + 3744005U, // CSINVWr + 3744005U, // CSINVXr + 3744005U, // CSNEGWr + 3744005U, // CSNEGXr + 1U, // CTERMEQ_WW + 1U, // CTERMEQ_XX + 1U, // CTERMNE_WW + 1U, // CTERMNE_XX + 0U, // CompilerBarrier 0U, // DCPS1 0U, // DCPS2 0U, // DCPS3 + 0U, // DECB_XPiI + 0U, // DECD_XPiI + 0U, // DECD_ZPiI + 0U, // DECH_XPiI + 0U, // DECH_ZPiI + 1U, // DECP_XP_B + 1U, // DECP_XP_D + 1U, // DECP_XP_H + 1U, // DECP_XP_S + 1U, // DECP_ZP_D + 0U, // DECP_ZP_H + 1U, // DECP_ZP_S + 0U, // DECW_XPiI + 0U, // DECW_ZPiI 0U, // DMB 0U, // DRPS 0U, // DSB - 0U, // DUPv16i8gpr - 75U, // DUPv16i8lane - 0U, // DUPv2i32gpr - 75U, // DUPv2i32lane - 0U, // DUPv2i64gpr - 75U, // DUPv2i64lane - 0U, // DUPv4i16gpr - 75U, // DUPv4i16lane - 0U, // DUPv4i32gpr - 75U, // DUPv4i32lane - 0U, // DUPv8i16gpr - 75U, // DUPv8i16lane - 0U, // DUPv8i8gpr - 75U, // DUPv8i8lane + 0U, // DUPM_ZI + 0U, // DUP_ZI_B + 0U, // DUP_ZI_D + 0U, // DUP_ZI_H + 0U, // DUP_ZI_S + 1U, // DUP_ZR_B + 1U, // DUP_ZR_D + 0U, // DUP_ZR_H + 1U, // DUP_ZR_S + 20U, // DUP_ZZI_B + 20U, // DUP_ZZI_D + 0U, // DUP_ZZI_H + 0U, // DUP_ZZI_Q + 20U, // DUP_ZZI_S + 1U, // DUPv16i8gpr + 2771U, // DUPv16i8lane + 1U, // DUPv2i32gpr + 2770U, // DUPv2i32lane + 1U, // DUPv2i64gpr + 2771U, // DUPv2i64lane + 1U, // DUPv4i16gpr + 2770U, // DUPv4i16lane + 1U, // DUPv4i32gpr + 2770U, // DUPv4i32lane + 1U, // DUPv8i16gpr + 2770U, // DUPv8i16lane + 1U, // DUPv8i8gpr + 2771U, // DUPv8i8lane 0U, // EONWrr - 33U, // EONWrs + 517U, // EONWrs 0U, // EONXrr - 33U, // EONXrs - 49U, // EORWri + 517U, // EONXrs + 36282695U, // EOR3 + 74570U, // EORS_PPzPP + 837U, // EORV_VPZ_B + 901U, // EORV_VPZ_D + 2245U, // EORV_VPZ_H + 1029U, // EORV_VPZ_S + 2117U, // EORWri 0U, // EORWrr - 33U, // EORWrs - 57U, // EORXri + 517U, // EORWrs + 2181U, // EORXri 0U, // EORXrr - 33U, // EORXrs - 1033U, // EORv16i8 - 1801U, // EORv8i8 + 517U, // EORXrs + 74570U, // EOR_PPzPP + 2181U, // EOR_ZI + 74560U, // EOR_ZPmZ_B + 598912U, // EOR_ZPmZ_D + 1131465U, // EOR_ZPmZ_H + 1647616U, // EOR_ZPmZ_S + 901U, // EOR_ZZZ + 33095U, // EORv16i8 + 57672U, // EORv8i8 0U, // ERET - 18689U, // EXTRWrri - 18689U, // EXTRXrri - 2569U, // EXTv16i8 - 2825U, // EXTv8i8 + 0U, // ERETAA + 0U, // ERETAB + 2171141U, // EXTRWrri + 2171141U, // EXTRXrri + 4793157U, // EXT_ZZI + 2203975U, // EXTv16i8 + 131400U, // EXTv8i8 0U, // F128CSEL - 1U, // FABD32 - 1U, // FABD64 - 1289U, // FABDv2f32 - 265U, // FABDv2f64 - 521U, // FABDv4f32 - 0U, // FABSDr - 0U, // FABSSr - 0U, // FABSv2f32 - 0U, // FABSv2f64 - 0U, // FABSv4f32 - 1U, // FACGE32 - 1U, // FACGE64 - 1289U, // FACGEv2f32 - 265U, // FACGEv2f64 - 521U, // FACGEv4f32 - 1U, // FACGT32 - 1U, // FACGT64 - 1289U, // FACGTv2f32 - 265U, // FACGTv2f64 - 521U, // FACGTv4f32 - 1U, // FADDDrr - 1289U, // FADDPv2f32 - 265U, // FADDPv2f64 - 0U, // FADDPv2i32p - 0U, // FADDPv2i64p - 521U, // FADDPv4f32 - 1U, // FADDSrr - 1289U, // FADDv2f32 - 265U, // FADDv2f64 - 521U, // FADDv4f32 - 10497U, // FCCMPDrr - 10497U, // FCCMPEDrr - 10497U, // FCCMPESrr - 10497U, // FCCMPSrr - 1U, // FCMEQ32 - 1U, // FCMEQ64 - 3U, // FCMEQv1i32rz - 3U, // FCMEQv1i64rz - 1289U, // FCMEQv2f32 - 265U, // FCMEQv2f64 - 3U, // FCMEQv2i32rz - 3U, // FCMEQv2i64rz - 521U, // FCMEQv4f32 - 3U, // FCMEQv4i32rz - 1U, // FCMGE32 - 1U, // FCMGE64 - 3U, // FCMGEv1i32rz - 3U, // FCMGEv1i64rz - 1289U, // FCMGEv2f32 - 265U, // FCMGEv2f64 - 3U, // FCMGEv2i32rz - 3U, // FCMGEv2i64rz - 521U, // FCMGEv4f32 - 3U, // FCMGEv4i32rz - 1U, // FCMGT32 - 1U, // FCMGT64 - 3U, // FCMGTv1i32rz - 3U, // FCMGTv1i64rz - 1289U, // FCMGTv2f32 - 265U, // FCMGTv2f64 - 3U, // FCMGTv2i32rz - 3U, // FCMGTv2i64rz - 521U, // FCMGTv4f32 - 3U, // FCMGTv4i32rz - 3U, // FCMLEv1i32rz - 3U, // FCMLEv1i64rz - 3U, // FCMLEv2i32rz - 3U, // FCMLEv2i64rz - 3U, // FCMLEv4i32rz - 3U, // FCMLTv1i32rz - 3U, // FCMLTv1i64rz - 3U, // FCMLTv2i32rz - 3U, // FCMLTv2i64rz - 3U, // FCMLTv4i32rz + 261U, // FABD16 + 261U, // FABD32 + 261U, // FABD64 + 598912U, // FABD_ZPmZ_D + 1131465U, // FABD_ZPmZ_H + 1647616U, // FABD_ZPmZ_S + 41287U, // FABDv2f32 + 8517U, // FABDv2f64 + 49480U, // FABDv4f16 + 16710U, // FABDv4f32 + 24902U, // FABDv8f16 + 1U, // FABSDr + 1U, // FABSHr + 1U, // FABSSr + 64U, // FABS_ZPmZ_D + 128U, // FABS_ZPmZ_H + 192U, // FABS_ZPmZ_S + 2U, // FABSv2f32 + 2U, // FABSv2f64 + 3U, // FABSv4f16 + 3U, // FABSv4f32 + 4U, // FABSv8f16 + 261U, // FACGE16 + 261U, // FACGE32 + 261U, // FACGE64 + 598922U, // FACGE_PPzZZ_D + 1131465U, // FACGE_PPzZZ_H + 1647626U, // FACGE_PPzZZ_S + 41287U, // FACGEv2f32 + 8517U, // FACGEv2f64 + 49480U, // FACGEv4f16 + 16710U, // FACGEv4f32 + 24902U, // FACGEv8f16 + 261U, // FACGT16 + 261U, // FACGT32 + 261U, // FACGT64 + 598922U, // FACGT_PPzZZ_D + 1131465U, // FACGT_PPzZZ_H + 1647626U, // FACGT_PPzZZ_S + 41287U, // FACGTv2f32 + 8517U, // FACGTv2f64 + 49480U, // FACGTv4f16 + 16710U, // FACGTv4f32 + 24902U, // FACGTv8f16 + 598277U, // FADDA_VPZ_D + 4268293U, // FADDA_VPZ_H + 1646853U, // FADDA_VPZ_S + 261U, // FADDDrr + 261U, // FADDHrr + 41287U, // FADDPv2f32 + 8517U, // FADDPv2f64 + 20U, // FADDPv2i16p + 2U, // FADDPv2i32p + 2U, // FADDPv2i64p + 49480U, // FADDPv4f16 + 16710U, // FADDPv4f32 + 24902U, // FADDPv8f16 + 261U, // FADDSrr + 901U, // FADDV_VPZ_D + 2245U, // FADDV_VPZ_H + 1029U, // FADDV_VPZ_S + 5317504U, // FADD_ZPmI_D + 140233U, // FADD_ZPmI_H + 5317632U, // FADD_ZPmI_S + 598912U, // FADD_ZPmZ_D + 1131465U, // FADD_ZPmZ_H + 1647616U, // FADD_ZPmZ_S + 901U, // FADD_ZZZ_D + 137U, // FADD_ZZZ_H + 1029U, // FADD_ZZZ_S + 41287U, // FADDv2f32 + 8517U, // FADDv2f64 + 49480U, // FADDv4f16 + 16710U, // FADDv4f32 + 24902U, // FADDv8f16 + 67707776U, // FCADD_ZPmZ_D + 106513353U, // FCADD_ZPmZ_H + 68756480U, // FCADD_ZPmZ_S + 6439239U, // FCADDv2f32 + 6447429U, // FCADDv2f64 + 6455624U, // FCADDv4f16 + 6463814U, // FCADDv4f32 + 6472006U, // FCADDv8f16 + 3744005U, // FCCMPDrr + 3744005U, // FCCMPEDrr + 3744005U, // FCCMPEHrr + 3744005U, // FCCMPESrr + 3744005U, // FCCMPHrr + 3744005U, // FCCMPSrr + 261U, // FCMEQ16 + 261U, // FCMEQ32 + 261U, // FCMEQ64 + 189322U, // FCMEQ_PPzZ0_D + 2825U, // FCMEQ_PPzZ0_H + 189450U, // FCMEQ_PPzZ0_S + 598922U, // FCMEQ_PPzZZ_D + 1131465U, // FCMEQ_PPzZZ_H + 1647626U, // FCMEQ_PPzZZ_S + 21U, // FCMEQv1i16rz + 21U, // FCMEQv1i32rz + 21U, // FCMEQv1i64rz + 41287U, // FCMEQv2f32 + 8517U, // FCMEQv2f64 + 21U, // FCMEQv2i32rz + 22U, // FCMEQv2i64rz + 49480U, // FCMEQv4f16 + 16710U, // FCMEQv4f32 + 22U, // FCMEQv4i16rz + 23U, // FCMEQv4i32rz + 24902U, // FCMEQv8f16 + 23U, // FCMEQv8i16rz + 261U, // FCMGE16 + 261U, // FCMGE32 + 261U, // FCMGE64 + 189322U, // FCMGE_PPzZ0_D + 2825U, // FCMGE_PPzZ0_H + 189450U, // FCMGE_PPzZ0_S + 598922U, // FCMGE_PPzZZ_D + 1131465U, // FCMGE_PPzZZ_H + 1647626U, // FCMGE_PPzZZ_S + 21U, // FCMGEv1i16rz + 21U, // FCMGEv1i32rz + 21U, // FCMGEv1i64rz + 41287U, // FCMGEv2f32 + 8517U, // FCMGEv2f64 + 21U, // FCMGEv2i32rz + 22U, // FCMGEv2i64rz + 49480U, // FCMGEv4f16 + 16710U, // FCMGEv4f32 + 22U, // FCMGEv4i16rz + 23U, // FCMGEv4i32rz + 24902U, // FCMGEv8f16 + 23U, // FCMGEv8i16rz + 261U, // FCMGT16 + 261U, // FCMGT32 + 261U, // FCMGT64 + 189322U, // FCMGT_PPzZ0_D + 2825U, // FCMGT_PPzZ0_H + 189450U, // FCMGT_PPzZ0_S + 598922U, // FCMGT_PPzZZ_D + 1131465U, // FCMGT_PPzZZ_H + 1647626U, // FCMGT_PPzZZ_S + 21U, // FCMGTv1i16rz + 21U, // FCMGTv1i32rz + 21U, // FCMGTv1i64rz + 41287U, // FCMGTv2f32 + 8517U, // FCMGTv2f64 + 21U, // FCMGTv2i32rz + 22U, // FCMGTv2i64rz + 49480U, // FCMGTv4f16 + 16710U, // FCMGTv4f32 + 22U, // FCMGTv4i16rz + 23U, // FCMGTv4i32rz + 24902U, // FCMGTv8f16 + 23U, // FCMGTv8i16rz + 342433856U, // FCMLA_ZPmZZ_D + 140182464U, // FCMLA_ZPmZZ_H + 342958272U, // FCMLA_ZPmZZ_S + 24U, // FCMLA_ZZZI_H + 7940952U, // FCMLA_ZZZI_S + 8536455U, // FCMLAv2f32 + 8544645U, // FCMLAv2f64 + 8552840U, // FCMLAv4f16 + 344662408U, // FCMLAv4f16_indexed + 8561030U, // FCMLAv4f32 + 344670598U, // FCMLAv4f32_indexed + 8569222U, // FCMLAv8f16 + 344662406U, // FCMLAv8f16_indexed + 189322U, // FCMLE_PPzZ0_D + 2825U, // FCMLE_PPzZ0_H + 189450U, // FCMLE_PPzZ0_S + 21U, // FCMLEv1i16rz + 21U, // FCMLEv1i32rz + 21U, // FCMLEv1i64rz + 21U, // FCMLEv2i32rz + 22U, // FCMLEv2i64rz + 22U, // FCMLEv4i16rz + 23U, // FCMLEv4i32rz + 23U, // FCMLEv8i16rz + 189322U, // FCMLT_PPzZ0_D + 2825U, // FCMLT_PPzZ0_H + 189450U, // FCMLT_PPzZ0_S + 21U, // FCMLTv1i16rz + 21U, // FCMLTv1i32rz + 21U, // FCMLTv1i64rz + 21U, // FCMLTv2i32rz + 22U, // FCMLTv2i64rz + 22U, // FCMLTv4i16rz + 23U, // FCMLTv4i32rz + 23U, // FCMLTv8i16rz + 189322U, // FCMNE_PPzZ0_D + 2825U, // FCMNE_PPzZ0_H + 189450U, // FCMNE_PPzZ0_S + 598922U, // FCMNE_PPzZZ_D + 1131465U, // FCMNE_PPzZZ_H + 1647626U, // FCMNE_PPzZZ_S 0U, // FCMPDri - 0U, // FCMPDrr + 1U, // FCMPDrr 0U, // FCMPEDri - 0U, // FCMPEDrr + 1U, // FCMPEDrr + 0U, // FCMPEHri + 1U, // FCMPEHrr 0U, // FCMPESri - 0U, // FCMPESrr + 1U, // FCMPESrr + 0U, // FCMPHri + 1U, // FCMPHrr 0U, // FCMPSri - 0U, // FCMPSrr - 10497U, // FCSELDrrr - 10497U, // FCSELSrrr - 0U, // FCVTASUWDr - 0U, // FCVTASUWSr - 0U, // FCVTASUXDr - 0U, // FCVTASUXSr - 0U, // FCVTASv1i32 - 0U, // FCVTASv1i64 - 0U, // FCVTASv2f32 - 0U, // FCVTASv2f64 - 0U, // FCVTASv4f32 - 0U, // FCVTAUUWDr - 0U, // FCVTAUUWSr - 0U, // FCVTAUUXDr - 0U, // FCVTAUUXSr - 0U, // FCVTAUv1i32 - 0U, // FCVTAUv1i64 - 0U, // FCVTAUv2f32 - 0U, // FCVTAUv2f64 - 0U, // FCVTAUv4f32 - 0U, // FCVTDHr - 0U, // FCVTDSr - 0U, // FCVTHDr - 0U, // FCVTHSr - 0U, // FCVTLv2i32 - 0U, // FCVTLv4i16 - 0U, // FCVTLv4i32 - 0U, // FCVTLv8i16 - 0U, // FCVTMSUWDr - 0U, // FCVTMSUWSr - 0U, // FCVTMSUXDr - 0U, // FCVTMSUXSr - 0U, // FCVTMSv1i32 - 0U, // FCVTMSv1i64 - 0U, // FCVTMSv2f32 - 0U, // FCVTMSv2f64 - 0U, // FCVTMSv4f32 - 0U, // FCVTMUUWDr - 0U, // FCVTMUUWSr - 0U, // FCVTMUUXDr - 0U, // FCVTMUUXSr - 0U, // FCVTMUv1i32 - 0U, // FCVTMUv1i64 - 0U, // FCVTMUv2f32 - 0U, // FCVTMUv2f64 - 0U, // FCVTMUv4f32 - 0U, // FCVTNSUWDr - 0U, // FCVTNSUWSr - 0U, // FCVTNSUXDr - 0U, // FCVTNSUXSr - 0U, // FCVTNSv1i32 - 0U, // FCVTNSv1i64 - 0U, // FCVTNSv2f32 - 0U, // FCVTNSv2f64 - 0U, // FCVTNSv4f32 - 0U, // FCVTNUUWDr - 0U, // FCVTNUUWSr - 0U, // FCVTNUUXDr - 0U, // FCVTNUUXSr - 0U, // FCVTNUv1i32 - 0U, // FCVTNUv1i64 - 0U, // FCVTNUv2f32 - 0U, // FCVTNUv2f64 - 0U, // FCVTNUv4f32 - 0U, // FCVTNv2i32 - 0U, // FCVTNv4i16 - 0U, // FCVTNv4i32 - 0U, // FCVTNv8i16 - 0U, // FCVTPSUWDr - 0U, // FCVTPSUWSr - 0U, // FCVTPSUXDr - 0U, // FCVTPSUXSr - 0U, // FCVTPSv1i32 - 0U, // FCVTPSv1i64 - 0U, // FCVTPSv2f32 - 0U, // FCVTPSv2f64 - 0U, // FCVTPSv4f32 - 0U, // FCVTPUUWDr - 0U, // FCVTPUUWSr - 0U, // FCVTPUUXDr - 0U, // FCVTPUUXSr - 0U, // FCVTPUv1i32 - 0U, // FCVTPUv1i64 - 0U, // FCVTPUv2f32 - 0U, // FCVTPUv2f64 - 0U, // FCVTPUv4f32 - 0U, // FCVTSDr - 0U, // FCVTSHr - 0U, // FCVTXNv1i64 - 0U, // FCVTXNv2f32 - 0U, // FCVTXNv4f32 - 1U, // FCVTZSSWDri - 1U, // FCVTZSSWSri - 1U, // FCVTZSSXDri - 1U, // FCVTZSSXSri - 0U, // FCVTZSUWDr - 0U, // FCVTZSUWSr - 0U, // FCVTZSUXDr - 0U, // FCVTZSUXSr - 1U, // FCVTZS_IntSWDri - 1U, // FCVTZS_IntSWSri - 1U, // FCVTZS_IntSXDri - 1U, // FCVTZS_IntSXSri - 0U, // FCVTZS_IntUWDr - 0U, // FCVTZS_IntUWSr - 0U, // FCVTZS_IntUXDr - 0U, // FCVTZS_IntUXSr - 0U, // FCVTZS_Intv2f32 - 0U, // FCVTZS_Intv2f64 - 0U, // FCVTZS_Intv4f32 - 1U, // FCVTZSd - 1U, // FCVTZSs - 0U, // FCVTZSv1i32 - 0U, // FCVTZSv1i64 - 0U, // FCVTZSv2f32 - 0U, // FCVTZSv2f64 - 1U, // FCVTZSv2i32_shift - 1U, // FCVTZSv2i64_shift - 0U, // FCVTZSv4f32 - 1U, // FCVTZSv4i32_shift - 1U, // FCVTZUSWDri - 1U, // FCVTZUSWSri - 1U, // FCVTZUSXDri - 1U, // FCVTZUSXSri - 0U, // FCVTZUUWDr - 0U, // FCVTZUUWSr - 0U, // FCVTZUUXDr - 0U, // FCVTZUUXSr - 1U, // FCVTZU_IntSWDri - 1U, // FCVTZU_IntSWSri - 1U, // FCVTZU_IntSXDri - 1U, // FCVTZU_IntSXSri - 0U, // FCVTZU_IntUWDr - 0U, // FCVTZU_IntUWSr - 0U, // FCVTZU_IntUXDr - 0U, // FCVTZU_IntUXSr - 0U, // FCVTZU_Intv2f32 - 0U, // FCVTZU_Intv2f64 - 0U, // FCVTZU_Intv4f32 - 1U, // FCVTZUd - 1U, // FCVTZUs - 0U, // FCVTZUv1i32 - 0U, // FCVTZUv1i64 - 0U, // FCVTZUv2f32 - 0U, // FCVTZUv2f64 - 1U, // FCVTZUv2i32_shift - 1U, // FCVTZUv2i64_shift - 0U, // FCVTZUv4f32 - 1U, // FCVTZUv4i32_shift - 1U, // FDIVDrr - 1U, // FDIVSrr - 1289U, // FDIVv2f32 - 265U, // FDIVv2f64 - 521U, // FDIVv4f32 - 18689U, // FMADDDrrr - 18689U, // FMADDSrrr - 1U, // FMAXDrr - 1U, // FMAXNMDrr - 1289U, // FMAXNMPv2f32 - 265U, // FMAXNMPv2f64 - 0U, // FMAXNMPv2i32p - 0U, // FMAXNMPv2i64p - 521U, // FMAXNMPv4f32 - 1U, // FMAXNMSrr - 0U, // FMAXNMVv4i32v - 1289U, // FMAXNMv2f32 - 265U, // FMAXNMv2f64 - 521U, // FMAXNMv4f32 - 1289U, // FMAXPv2f32 - 265U, // FMAXPv2f64 - 0U, // FMAXPv2i32p - 0U, // FMAXPv2i64p - 521U, // FMAXPv4f32 - 1U, // FMAXSrr - 0U, // FMAXVv4i32v - 1289U, // FMAXv2f32 - 265U, // FMAXv2f64 - 521U, // FMAXv4f32 - 1U, // FMINDrr - 1U, // FMINNMDrr - 1289U, // FMINNMPv2f32 - 265U, // FMINNMPv2f64 - 0U, // FMINNMPv2i32p - 0U, // FMINNMPv2i64p - 521U, // FMINNMPv4f32 - 1U, // FMINNMSrr - 0U, // FMINNMVv4i32v - 1289U, // FMINNMv2f32 - 265U, // FMINNMv2f64 - 521U, // FMINNMv4f32 - 1289U, // FMINPv2f32 - 265U, // FMINPv2f64 - 0U, // FMINPv2i32p - 0U, // FMINPv2i64p - 521U, // FMINPv4f32 - 1U, // FMINSrr - 0U, // FMINVv4i32v - 1289U, // FMINv2f32 - 265U, // FMINv2f64 - 521U, // FMINv4f32 - 27665U, // FMLAv1i32_indexed - 27921U, // FMLAv1i64_indexed - 1297U, // FMLAv2f32 - 273U, // FMLAv2f64 - 27665U, // FMLAv2i32_indexed - 27921U, // FMLAv2i64_indexed - 529U, // FMLAv4f32 - 27665U, // FMLAv4i32_indexed - 27665U, // FMLSv1i32_indexed - 27921U, // FMLSv1i64_indexed - 1297U, // FMLSv2f32 - 273U, // FMLSv2f64 - 27665U, // FMLSv2i32_indexed - 27921U, // FMLSv2i64_indexed - 529U, // FMLSv4f32 - 27665U, // FMLSv4i32_indexed - 75U, // FMOVDXHighr - 0U, // FMOVDXr + 1U, // FCMPSrr + 598922U, // FCMUO_PPzZZ_D + 1131465U, // FCMUO_PPzZZ_H + 1647626U, // FCMUO_PPzZZ_S + 2944U, // FCPY_ZPmI_D + 25U, // FCPY_ZPmI_H + 2944U, // FCPY_ZPmI_S + 3744005U, // FCSELDrrr + 3744005U, // FCSELHrrr + 3744005U, // FCSELSrrr + 1U, // FCVTASUWDr + 1U, // FCVTASUWHr + 1U, // FCVTASUWSr + 1U, // FCVTASUXDr + 1U, // FCVTASUXHr + 1U, // FCVTASUXSr + 1U, // FCVTASv1f16 + 1U, // FCVTASv1i32 + 1U, // FCVTASv1i64 + 2U, // FCVTASv2f32 + 2U, // FCVTASv2f64 + 3U, // FCVTASv4f16 + 3U, // FCVTASv4f32 + 4U, // FCVTASv8f16 + 1U, // FCVTAUUWDr + 1U, // FCVTAUUWHr + 1U, // FCVTAUUWSr + 1U, // FCVTAUUXDr + 1U, // FCVTAUUXHr + 1U, // FCVTAUUXSr + 1U, // FCVTAUv1f16 + 1U, // FCVTAUv1i32 + 1U, // FCVTAUv1i64 + 2U, // FCVTAUv2f32 + 2U, // FCVTAUv2f64 + 3U, // FCVTAUv4f16 + 3U, // FCVTAUv4f32 + 4U, // FCVTAUv8f16 + 1U, // FCVTDHr + 1U, // FCVTDSr + 1U, // FCVTHDr + 1U, // FCVTHSr + 2U, // FCVTLv2i32 + 3U, // FCVTLv4i16 + 3U, // FCVTLv4i32 + 4U, // FCVTLv8i16 + 1U, // FCVTMSUWDr + 1U, // FCVTMSUWHr + 1U, // FCVTMSUWSr + 1U, // FCVTMSUXDr + 1U, // FCVTMSUXHr + 1U, // FCVTMSUXSr + 1U, // FCVTMSv1f16 + 1U, // FCVTMSv1i32 + 1U, // FCVTMSv1i64 + 2U, // FCVTMSv2f32 + 2U, // FCVTMSv2f64 + 3U, // FCVTMSv4f16 + 3U, // FCVTMSv4f32 + 4U, // FCVTMSv8f16 + 1U, // FCVTMUUWDr + 1U, // FCVTMUUWHr + 1U, // FCVTMUUWSr + 1U, // FCVTMUUXDr + 1U, // FCVTMUUXHr + 1U, // FCVTMUUXSr + 1U, // FCVTMUv1f16 + 1U, // FCVTMUv1i32 + 1U, // FCVTMUv1i64 + 2U, // FCVTMUv2f32 + 2U, // FCVTMUv2f64 + 3U, // FCVTMUv4f16 + 3U, // FCVTMUv4f32 + 4U, // FCVTMUv8f16 + 1U, // FCVTNSUWDr + 1U, // FCVTNSUWHr + 1U, // FCVTNSUWSr + 1U, // FCVTNSUXDr + 1U, // FCVTNSUXHr + 1U, // FCVTNSUXSr + 1U, // FCVTNSv1f16 + 1U, // FCVTNSv1i32 + 1U, // FCVTNSv1i64 + 2U, // FCVTNSv2f32 + 2U, // FCVTNSv2f64 + 3U, // FCVTNSv4f16 + 3U, // FCVTNSv4f32 + 4U, // FCVTNSv8f16 + 1U, // FCVTNUUWDr + 1U, // FCVTNUUWHr + 1U, // FCVTNUUWSr + 1U, // FCVTNUUXDr + 1U, // FCVTNUUXHr + 1U, // FCVTNUUXSr + 1U, // FCVTNUv1f16 + 1U, // FCVTNUv1i32 + 1U, // FCVTNUv1i64 + 2U, // FCVTNUv2f32 + 2U, // FCVTNUv2f64 + 3U, // FCVTNUv4f16 + 3U, // FCVTNUv4f32 + 4U, // FCVTNUv8f16 + 2U, // FCVTNv2i32 + 3U, // FCVTNv4i16 + 2U, // FCVTNv4i32 + 3U, // FCVTNv8i16 + 1U, // FCVTPSUWDr + 1U, // FCVTPSUWHr + 1U, // FCVTPSUWSr + 1U, // FCVTPSUXDr + 1U, // FCVTPSUXHr + 1U, // FCVTPSUXSr + 1U, // FCVTPSv1f16 + 1U, // FCVTPSv1i32 + 1U, // FCVTPSv1i64 + 2U, // FCVTPSv2f32 + 2U, // FCVTPSv2f64 + 3U, // FCVTPSv4f16 + 3U, // FCVTPSv4f32 + 4U, // FCVTPSv8f16 + 1U, // FCVTPUUWDr + 1U, // FCVTPUUWHr + 1U, // FCVTPUUWSr + 1U, // FCVTPUUXDr + 1U, // FCVTPUUXHr + 1U, // FCVTPUUXSr + 1U, // FCVTPUv1f16 + 1U, // FCVTPUv1i32 + 1U, // FCVTPUv1i64 + 2U, // FCVTPUv2f32 + 2U, // FCVTPUv2f64 + 3U, // FCVTPUv4f16 + 3U, // FCVTPUv4f32 + 4U, // FCVTPUv8f16 + 1U, // FCVTSDr + 1U, // FCVTSHr + 1U, // FCVTXNv1i64 + 2U, // FCVTXNv2f32 + 2U, // FCVTXNv4f32 + 261U, // FCVTZSSWDri + 261U, // FCVTZSSWHri + 261U, // FCVTZSSWSri + 261U, // FCVTZSSXDri + 261U, // FCVTZSSXHri + 261U, // FCVTZSSXSri + 1U, // FCVTZSUWDr + 1U, // FCVTZSUWHr + 1U, // FCVTZSUWSr + 1U, // FCVTZSUXDr + 1U, // FCVTZSUXHr + 1U, // FCVTZSUXSr + 64U, // FCVTZS_ZPmZ_DtoD + 64U, // FCVTZS_ZPmZ_DtoS + 3008U, // FCVTZS_ZPmZ_HtoD + 128U, // FCVTZS_ZPmZ_HtoH + 3008U, // FCVTZS_ZPmZ_HtoS + 192U, // FCVTZS_ZPmZ_StoD + 192U, // FCVTZS_ZPmZ_StoS + 261U, // FCVTZSd + 261U, // FCVTZSh + 261U, // FCVTZSs + 1U, // FCVTZSv1f16 + 1U, // FCVTZSv1i32 + 1U, // FCVTZSv1i64 + 2U, // FCVTZSv2f32 + 2U, // FCVTZSv2f64 + 263U, // FCVTZSv2i32_shift + 261U, // FCVTZSv2i64_shift + 3U, // FCVTZSv4f16 + 3U, // FCVTZSv4f32 + 264U, // FCVTZSv4i16_shift + 262U, // FCVTZSv4i32_shift + 4U, // FCVTZSv8f16 + 262U, // FCVTZSv8i16_shift + 261U, // FCVTZUSWDri + 261U, // FCVTZUSWHri + 261U, // FCVTZUSWSri + 261U, // FCVTZUSXDri + 261U, // FCVTZUSXHri + 261U, // FCVTZUSXSri + 1U, // FCVTZUUWDr + 1U, // FCVTZUUWHr + 1U, // FCVTZUUWSr + 1U, // FCVTZUUXDr + 1U, // FCVTZUUXHr + 1U, // FCVTZUUXSr + 64U, // FCVTZU_ZPmZ_DtoD + 64U, // FCVTZU_ZPmZ_DtoS + 3008U, // FCVTZU_ZPmZ_HtoD + 128U, // FCVTZU_ZPmZ_HtoH + 3008U, // FCVTZU_ZPmZ_HtoS + 192U, // FCVTZU_ZPmZ_StoD + 192U, // FCVTZU_ZPmZ_StoS + 261U, // FCVTZUd + 261U, // FCVTZUh + 261U, // FCVTZUs + 1U, // FCVTZUv1f16 + 1U, // FCVTZUv1i32 + 1U, // FCVTZUv1i64 + 2U, // FCVTZUv2f32 + 2U, // FCVTZUv2f64 + 263U, // FCVTZUv2i32_shift + 261U, // FCVTZUv2i64_shift + 3U, // FCVTZUv4f16 + 3U, // FCVTZUv4f32 + 264U, // FCVTZUv4i16_shift + 262U, // FCVTZUv4i32_shift + 4U, // FCVTZUv8f16 + 262U, // FCVTZUv8i16_shift + 153U, // FCVT_ZPmZ_DtoH + 64U, // FCVT_ZPmZ_DtoS + 3008U, // FCVT_ZPmZ_HtoD + 3008U, // FCVT_ZPmZ_HtoS + 192U, // FCVT_ZPmZ_StoD + 152U, // FCVT_ZPmZ_StoH + 261U, // FDIVDrr + 261U, // FDIVHrr + 598912U, // FDIVR_ZPmZ_D + 1131465U, // FDIVR_ZPmZ_H + 1647616U, // FDIVR_ZPmZ_S + 261U, // FDIVSrr + 598912U, // FDIV_ZPmZ_D + 1131465U, // FDIV_ZPmZ_H + 1647616U, // FDIV_ZPmZ_S + 41287U, // FDIVv2f32 + 8517U, // FDIVv2f64 + 49480U, // FDIVv4f16 + 16710U, // FDIVv4f32 + 24902U, // FDIVv8f16 + 0U, // FDUP_ZI_D + 0U, // FDUP_ZI_H + 0U, // FDUP_ZI_S + 1U, // FEXPA_ZZ_D + 0U, // FEXPA_ZZ_H + 1U, // FEXPA_ZZ_S + 1U, // FJCVTZS + 2171141U, // FMADDDrrr + 2171141U, // FMADDHrrr + 2171141U, // FMADDSrrr + 6889536U, // FMAD_ZPmZZ_D + 1246144U, // FMAD_ZPmZZ_H + 7413952U, // FMAD_ZPmZZ_S + 261U, // FMAXDrr + 261U, // FMAXHrr + 261U, // FMAXNMDrr + 261U, // FMAXNMHrr + 41287U, // FMAXNMPv2f32 + 8517U, // FMAXNMPv2f64 + 20U, // FMAXNMPv2i16p + 2U, // FMAXNMPv2i32p + 2U, // FMAXNMPv2i64p + 49480U, // FMAXNMPv4f16 + 16710U, // FMAXNMPv4f32 + 24902U, // FMAXNMPv8f16 + 261U, // FMAXNMSrr + 901U, // FMAXNMV_VPZ_D + 2245U, // FMAXNMV_VPZ_H + 1029U, // FMAXNMV_VPZ_S + 3U, // FMAXNMVv4i16v + 3U, // FMAXNMVv4i32v + 4U, // FMAXNMVv8i16v + 9511808U, // FMAXNM_ZPmI_D + 222153U, // FMAXNM_ZPmI_H + 9511936U, // FMAXNM_ZPmI_S + 598912U, // FMAXNM_ZPmZ_D + 1131465U, // FMAXNM_ZPmZ_H + 1647616U, // FMAXNM_ZPmZ_S + 41287U, // FMAXNMv2f32 + 8517U, // FMAXNMv2f64 + 49480U, // FMAXNMv4f16 + 16710U, // FMAXNMv4f32 + 24902U, // FMAXNMv8f16 + 41287U, // FMAXPv2f32 + 8517U, // FMAXPv2f64 + 20U, // FMAXPv2i16p + 2U, // FMAXPv2i32p + 2U, // FMAXPv2i64p + 49480U, // FMAXPv4f16 + 16710U, // FMAXPv4f32 + 24902U, // FMAXPv8f16 + 261U, // FMAXSrr + 901U, // FMAXV_VPZ_D + 2245U, // FMAXV_VPZ_H + 1029U, // FMAXV_VPZ_S + 3U, // FMAXVv4i16v + 3U, // FMAXVv4i32v + 4U, // FMAXVv8i16v + 9511808U, // FMAX_ZPmI_D + 222153U, // FMAX_ZPmI_H + 9511936U, // FMAX_ZPmI_S + 598912U, // FMAX_ZPmZ_D + 1131465U, // FMAX_ZPmZ_H + 1647616U, // FMAX_ZPmZ_S + 41287U, // FMAXv2f32 + 8517U, // FMAXv2f64 + 49480U, // FMAXv4f16 + 16710U, // FMAXv4f32 + 24902U, // FMAXv8f16 + 261U, // FMINDrr + 261U, // FMINHrr + 261U, // FMINNMDrr + 261U, // FMINNMHrr + 41287U, // FMINNMPv2f32 + 8517U, // FMINNMPv2f64 + 20U, // FMINNMPv2i16p + 2U, // FMINNMPv2i32p + 2U, // FMINNMPv2i64p + 49480U, // FMINNMPv4f16 + 16710U, // FMINNMPv4f32 + 24902U, // FMINNMPv8f16 + 261U, // FMINNMSrr + 901U, // FMINNMV_VPZ_D + 2245U, // FMINNMV_VPZ_H + 1029U, // FMINNMV_VPZ_S + 3U, // FMINNMVv4i16v + 3U, // FMINNMVv4i32v + 4U, // FMINNMVv8i16v + 9511808U, // FMINNM_ZPmI_D + 222153U, // FMINNM_ZPmI_H + 9511936U, // FMINNM_ZPmI_S + 598912U, // FMINNM_ZPmZ_D + 1131465U, // FMINNM_ZPmZ_H + 1647616U, // FMINNM_ZPmZ_S + 41287U, // FMINNMv2f32 + 8517U, // FMINNMv2f64 + 49480U, // FMINNMv4f16 + 16710U, // FMINNMv4f32 + 24902U, // FMINNMv8f16 + 41287U, // FMINPv2f32 + 8517U, // FMINPv2f64 + 20U, // FMINPv2i16p + 2U, // FMINPv2i32p + 2U, // FMINPv2i64p + 49480U, // FMINPv4f16 + 16710U, // FMINPv4f32 + 24902U, // FMINPv8f16 + 261U, // FMINSrr + 901U, // FMINV_VPZ_D + 2245U, // FMINV_VPZ_H + 1029U, // FMINV_VPZ_S + 3U, // FMINVv4i16v + 3U, // FMINVv4i32v + 4U, // FMINVv8i16v + 9511808U, // FMIN_ZPmI_D + 222153U, // FMIN_ZPmI_H + 9511936U, // FMIN_ZPmI_S + 598912U, // FMIN_ZPmZ_D + 1131465U, // FMIN_ZPmZ_H + 1647616U, // FMIN_ZPmZ_S + 41287U, // FMINv2f32 + 8517U, // FMINv2f64 + 49480U, // FMINv4f16 + 16710U, // FMINv4f32 + 24902U, // FMINv8f16 + 6889536U, // FMLA_ZPmZZ_D + 1246144U, // FMLA_ZPmZZ_H + 7413952U, // FMLA_ZPmZZ_S + 2905U, // FMLA_ZZZI_D + 0U, // FMLA_ZZZI_H + 2904U, // FMLA_ZZZI_S + 9118085U, // FMLAv1i16_indexed + 9126277U, // FMLAv1i32_indexed + 9142661U, // FMLAv1i64_indexed + 41351U, // FMLAv2f32 + 8581U, // FMLAv2f64 + 9126279U, // FMLAv2i32_indexed + 9142661U, // FMLAv2i64_indexed + 49544U, // FMLAv4f16 + 16774U, // FMLAv4f32 + 9118088U, // FMLAv4i16_indexed + 9126278U, // FMLAv4i32_indexed + 24966U, // FMLAv8f16 + 9118086U, // FMLAv8i16_indexed + 6889536U, // FMLS_ZPmZZ_D + 1246144U, // FMLS_ZPmZZ_H + 7413952U, // FMLS_ZPmZZ_S + 2905U, // FMLS_ZZZI_D + 0U, // FMLS_ZZZI_H + 2904U, // FMLS_ZZZI_S + 9118085U, // FMLSv1i16_indexed + 9126277U, // FMLSv1i32_indexed + 9142661U, // FMLSv1i64_indexed + 41351U, // FMLSv2f32 + 8581U, // FMLSv2f64 + 9126279U, // FMLSv2i32_indexed + 9142661U, // FMLSv2i64_indexed + 49544U, // FMLSv4f16 + 16774U, // FMLSv4f32 + 9118088U, // FMLSv4i16_indexed + 9126278U, // FMLSv4i32_indexed + 24966U, // FMLSv8f16 + 9118086U, // FMLSv8i16_indexed + 0U, // FMOVD0 + 2771U, // FMOVDXHighr + 1U, // FMOVDXr 0U, // FMOVDi - 0U, // FMOVDr - 0U, // FMOVSWr + 1U, // FMOVDr + 0U, // FMOVH0 + 1U, // FMOVHWr + 1U, // FMOVHXr + 0U, // FMOVHi + 1U, // FMOVHr + 0U, // FMOVS0 + 1U, // FMOVSWr 0U, // FMOVSi - 0U, // FMOVSr - 0U, // FMOVWSr - 0U, // FMOVXDHighr - 0U, // FMOVXDr + 1U, // FMOVSr + 1U, // FMOVWHr + 1U, // FMOVWSr + 1U, // FMOVXDHighr + 1U, // FMOVXDr + 1U, // FMOVXHr 0U, // FMOVv2f32_ns 0U, // FMOVv2f64_ns + 0U, // FMOVv4f16_ns 0U, // FMOVv4f32_ns - 18689U, // FMSUBDrrr - 18689U, // FMSUBSrrr - 1U, // FMULDrr - 1U, // FMULSrr - 1U, // FMULX32 - 1U, // FMULX64 - 35849U, // FMULXv1i32_indexed - 36105U, // FMULXv1i64_indexed - 1289U, // FMULXv2f32 - 265U, // FMULXv2f64 - 35849U, // FMULXv2i32_indexed - 36105U, // FMULXv2i64_indexed - 521U, // FMULXv4f32 - 35849U, // FMULXv4i32_indexed - 35849U, // FMULv1i32_indexed - 36105U, // FMULv1i64_indexed - 1289U, // FMULv2f32 - 265U, // FMULv2f64 - 35849U, // FMULv2i32_indexed - 36105U, // FMULv2i64_indexed - 521U, // FMULv4f32 - 35849U, // FMULv4i32_indexed - 0U, // FNEGDr - 0U, // FNEGSr - 0U, // FNEGv2f32 - 0U, // FNEGv2f64 - 0U, // FNEGv4f32 - 18689U, // FNMADDDrrr - 18689U, // FNMADDSrrr - 18689U, // FNMSUBDrrr - 18689U, // FNMSUBSrrr - 1U, // FNMULDrr - 1U, // FNMULSrr - 0U, // FRECPEv1i32 - 0U, // FRECPEv1i64 - 0U, // FRECPEv2f32 - 0U, // FRECPEv2f64 - 0U, // FRECPEv4f32 - 1U, // FRECPS32 - 1U, // FRECPS64 - 1289U, // FRECPSv2f32 - 265U, // FRECPSv2f64 - 521U, // FRECPSv4f32 - 0U, // FRECPXv1i32 - 0U, // FRECPXv1i64 - 0U, // FRINTADr - 0U, // FRINTASr - 0U, // FRINTAv2f32 - 0U, // FRINTAv2f64 - 0U, // FRINTAv4f32 - 0U, // FRINTIDr - 0U, // FRINTISr - 0U, // FRINTIv2f32 - 0U, // FRINTIv2f64 - 0U, // FRINTIv4f32 - 0U, // FRINTMDr - 0U, // FRINTMSr - 0U, // FRINTMv2f32 - 0U, // FRINTMv2f64 - 0U, // FRINTMv4f32 - 0U, // FRINTNDr - 0U, // FRINTNSr - 0U, // FRINTNv2f32 - 0U, // FRINTNv2f64 - 0U, // FRINTNv4f32 - 0U, // FRINTPDr - 0U, // FRINTPSr - 0U, // FRINTPv2f32 - 0U, // FRINTPv2f64 - 0U, // FRINTPv4f32 - 0U, // FRINTXDr - 0U, // FRINTXSr - 0U, // FRINTXv2f32 - 0U, // FRINTXv2f64 - 0U, // FRINTXv4f32 - 0U, // FRINTZDr - 0U, // FRINTZSr - 0U, // FRINTZv2f32 - 0U, // FRINTZv2f64 - 0U, // FRINTZv4f32 - 0U, // FRSQRTEv1i32 - 0U, // FRSQRTEv1i64 - 0U, // FRSQRTEv2f32 - 0U, // FRSQRTEv2f64 - 0U, // FRSQRTEv4f32 - 1U, // FRSQRTS32 - 1U, // FRSQRTS64 - 1289U, // FRSQRTSv2f32 - 265U, // FRSQRTSv2f64 - 521U, // FRSQRTSv4f32 - 0U, // FSQRTDr - 0U, // FSQRTSr - 0U, // FSQRTv2f32 - 0U, // FSQRTv2f64 - 0U, // FSQRTv4f32 - 1U, // FSUBDrr - 1U, // FSUBSrr - 1289U, // FSUBv2f32 - 265U, // FSUBv2f64 - 521U, // FSUBv4f32 + 0U, // FMOVv8f16_ns + 6889536U, // FMSB_ZPmZZ_D + 1246144U, // FMSB_ZPmZZ_H + 7413952U, // FMSB_ZPmZZ_S + 2171141U, // FMSUBDrrr + 2171141U, // FMSUBHrrr + 2171141U, // FMSUBSrrr + 261U, // FMULDrr + 261U, // FMULHrr + 261U, // FMULSrr + 261U, // FMULX16 + 261U, // FMULX32 + 261U, // FMULX64 + 598912U, // FMULX_ZPmZ_D + 1131465U, // FMULX_ZPmZ_H + 1647616U, // FMULX_ZPmZ_S + 10166597U, // FMULXv1i16_indexed + 10174789U, // FMULXv1i32_indexed + 10191173U, // FMULXv1i64_indexed + 41287U, // FMULXv2f32 + 8517U, // FMULXv2f64 + 10174791U, // FMULXv2i32_indexed + 10191173U, // FMULXv2i64_indexed + 49480U, // FMULXv4f16 + 16710U, // FMULXv4f32 + 10166600U, // FMULXv4i16_indexed + 10174790U, // FMULXv4i32_indexed + 24902U, // FMULXv8f16 + 10166598U, // FMULXv8i16_indexed + 10560384U, // FMUL_ZPmI_D + 238537U, // FMUL_ZPmI_H + 10560512U, // FMUL_ZPmI_S + 598912U, // FMUL_ZPmZ_D + 1131465U, // FMUL_ZPmZ_H + 1647616U, // FMUL_ZPmZ_S + 246661U, // FMUL_ZZZI_D + 3081U, // FMUL_ZZZI_H + 246789U, // FMUL_ZZZI_S + 901U, // FMUL_ZZZ_D + 137U, // FMUL_ZZZ_H + 1029U, // FMUL_ZZZ_S + 10166597U, // FMULv1i16_indexed + 10174789U, // FMULv1i32_indexed + 10191173U, // FMULv1i64_indexed + 41287U, // FMULv2f32 + 8517U, // FMULv2f64 + 10174791U, // FMULv2i32_indexed + 10191173U, // FMULv2i64_indexed + 49480U, // FMULv4f16 + 16710U, // FMULv4f32 + 10166600U, // FMULv4i16_indexed + 10174790U, // FMULv4i32_indexed + 24902U, // FMULv8f16 + 10166598U, // FMULv8i16_indexed + 1U, // FNEGDr + 1U, // FNEGHr + 1U, // FNEGSr + 64U, // FNEG_ZPmZ_D + 128U, // FNEG_ZPmZ_H + 192U, // FNEG_ZPmZ_S + 2U, // FNEGv2f32 + 2U, // FNEGv2f64 + 3U, // FNEGv4f16 + 3U, // FNEGv4f32 + 4U, // FNEGv8f16 + 2171141U, // FNMADDDrrr + 2171141U, // FNMADDHrrr + 2171141U, // FNMADDSrrr + 6889536U, // FNMAD_ZPmZZ_D + 1246144U, // FNMAD_ZPmZZ_H + 7413952U, // FNMAD_ZPmZZ_S + 6889536U, // FNMLA_ZPmZZ_D + 1246144U, // FNMLA_ZPmZZ_H + 7413952U, // FNMLA_ZPmZZ_S + 6889536U, // FNMLS_ZPmZZ_D + 1246144U, // FNMLS_ZPmZZ_H + 7413952U, // FNMLS_ZPmZZ_S + 6889536U, // FNMSB_ZPmZZ_D + 1246144U, // FNMSB_ZPmZZ_H + 7413952U, // FNMSB_ZPmZZ_S + 2171141U, // FNMSUBDrrr + 2171141U, // FNMSUBHrrr + 2171141U, // FNMSUBSrrr + 261U, // FNMULDrr + 261U, // FNMULHrr + 261U, // FNMULSrr + 1U, // FRECPE_ZZ_D + 0U, // FRECPE_ZZ_H + 1U, // FRECPE_ZZ_S + 1U, // FRECPEv1f16 + 1U, // FRECPEv1i32 + 1U, // FRECPEv1i64 + 2U, // FRECPEv2f32 + 2U, // FRECPEv2f64 + 3U, // FRECPEv4f16 + 3U, // FRECPEv4f32 + 4U, // FRECPEv8f16 + 261U, // FRECPS16 + 261U, // FRECPS32 + 261U, // FRECPS64 + 901U, // FRECPS_ZZZ_D + 137U, // FRECPS_ZZZ_H + 1029U, // FRECPS_ZZZ_S + 41287U, // FRECPSv2f32 + 8517U, // FRECPSv2f64 + 49480U, // FRECPSv4f16 + 16710U, // FRECPSv4f32 + 24902U, // FRECPSv8f16 + 64U, // FRECPX_ZPmZ_D + 128U, // FRECPX_ZPmZ_H + 192U, // FRECPX_ZPmZ_S + 1U, // FRECPXv1f16 + 1U, // FRECPXv1i32 + 1U, // FRECPXv1i64 + 1U, // FRINTADr + 1U, // FRINTAHr + 1U, // FRINTASr + 64U, // FRINTA_ZPmZ_D + 128U, // FRINTA_ZPmZ_H + 192U, // FRINTA_ZPmZ_S + 2U, // FRINTAv2f32 + 2U, // FRINTAv2f64 + 3U, // FRINTAv4f16 + 3U, // FRINTAv4f32 + 4U, // FRINTAv8f16 + 1U, // FRINTIDr + 1U, // FRINTIHr + 1U, // FRINTISr + 64U, // FRINTI_ZPmZ_D + 128U, // FRINTI_ZPmZ_H + 192U, // FRINTI_ZPmZ_S + 2U, // FRINTIv2f32 + 2U, // FRINTIv2f64 + 3U, // FRINTIv4f16 + 3U, // FRINTIv4f32 + 4U, // FRINTIv8f16 + 1U, // FRINTMDr + 1U, // FRINTMHr + 1U, // FRINTMSr + 64U, // FRINTM_ZPmZ_D + 128U, // FRINTM_ZPmZ_H + 192U, // FRINTM_ZPmZ_S + 2U, // FRINTMv2f32 + 2U, // FRINTMv2f64 + 3U, // FRINTMv4f16 + 3U, // FRINTMv4f32 + 4U, // FRINTMv8f16 + 1U, // FRINTNDr + 1U, // FRINTNHr + 1U, // FRINTNSr + 64U, // FRINTN_ZPmZ_D + 128U, // FRINTN_ZPmZ_H + 192U, // FRINTN_ZPmZ_S + 2U, // FRINTNv2f32 + 2U, // FRINTNv2f64 + 3U, // FRINTNv4f16 + 3U, // FRINTNv4f32 + 4U, // FRINTNv8f16 + 1U, // FRINTPDr + 1U, // FRINTPHr + 1U, // FRINTPSr + 64U, // FRINTP_ZPmZ_D + 128U, // FRINTP_ZPmZ_H + 192U, // FRINTP_ZPmZ_S + 2U, // FRINTPv2f32 + 2U, // FRINTPv2f64 + 3U, // FRINTPv4f16 + 3U, // FRINTPv4f32 + 4U, // FRINTPv8f16 + 1U, // FRINTXDr + 1U, // FRINTXHr + 1U, // FRINTXSr + 64U, // FRINTX_ZPmZ_D + 128U, // FRINTX_ZPmZ_H + 192U, // FRINTX_ZPmZ_S + 2U, // FRINTXv2f32 + 2U, // FRINTXv2f64 + 3U, // FRINTXv4f16 + 3U, // FRINTXv4f32 + 4U, // FRINTXv8f16 + 1U, // FRINTZDr + 1U, // FRINTZHr + 1U, // FRINTZSr + 64U, // FRINTZ_ZPmZ_D + 128U, // FRINTZ_ZPmZ_H + 192U, // FRINTZ_ZPmZ_S + 2U, // FRINTZv2f32 + 2U, // FRINTZv2f64 + 3U, // FRINTZv4f16 + 3U, // FRINTZv4f32 + 4U, // FRINTZv8f16 + 1U, // FRSQRTE_ZZ_D + 0U, // FRSQRTE_ZZ_H + 1U, // FRSQRTE_ZZ_S + 1U, // FRSQRTEv1f16 + 1U, // FRSQRTEv1i32 + 1U, // FRSQRTEv1i64 + 2U, // FRSQRTEv2f32 + 2U, // FRSQRTEv2f64 + 3U, // FRSQRTEv4f16 + 3U, // FRSQRTEv4f32 + 4U, // FRSQRTEv8f16 + 261U, // FRSQRTS16 + 261U, // FRSQRTS32 + 261U, // FRSQRTS64 + 901U, // FRSQRTS_ZZZ_D + 137U, // FRSQRTS_ZZZ_H + 1029U, // FRSQRTS_ZZZ_S + 41287U, // FRSQRTSv2f32 + 8517U, // FRSQRTSv2f64 + 49480U, // FRSQRTSv4f16 + 16710U, // FRSQRTSv4f32 + 24902U, // FRSQRTSv8f16 + 598912U, // FSCALE_ZPmZ_D + 1131465U, // FSCALE_ZPmZ_H + 1647616U, // FSCALE_ZPmZ_S + 1U, // FSQRTDr + 1U, // FSQRTHr + 1U, // FSQRTSr + 64U, // FSQRT_ZPmZ_D + 128U, // FSQRT_ZPmZ_H + 192U, // FSQRT_ZPmZ_S + 2U, // FSQRTv2f32 + 2U, // FSQRTv2f64 + 3U, // FSQRTv4f16 + 3U, // FSQRTv4f32 + 4U, // FSQRTv8f16 + 261U, // FSUBDrr + 261U, // FSUBHrr + 5317504U, // FSUBR_ZPmI_D + 140233U, // FSUBR_ZPmI_H + 5317632U, // FSUBR_ZPmI_S + 598912U, // FSUBR_ZPmZ_D + 1131465U, // FSUBR_ZPmZ_H + 1647616U, // FSUBR_ZPmZ_S + 261U, // FSUBSrr + 5317504U, // FSUB_ZPmI_D + 140233U, // FSUB_ZPmI_H + 5317632U, // FSUB_ZPmI_S + 598912U, // FSUB_ZPmZ_D + 1131465U, // FSUB_ZPmZ_H + 1647616U, // FSUB_ZPmZ_S + 901U, // FSUB_ZZZ_D + 137U, // FSUB_ZZZ_H + 1029U, // FSUB_ZZZ_S + 41287U, // FSUBv2f32 + 8517U, // FSUBv2f64 + 49480U, // FSUBv4f16 + 16710U, // FSUBv4f32 + 24902U, // FSUBv8f16 + 2171781U, // FTMAD_ZZI_D + 91081U, // FTMAD_ZZI_H + 2171909U, // FTMAD_ZZI_S + 901U, // FTSMUL_ZZZ_D + 137U, // FTSMUL_ZZZ_H + 1029U, // FTSMUL_ZZZ_S + 901U, // FTSSEL_ZZZ_D + 137U, // FTSSEL_ZZZ_H + 1029U, // FTSSEL_ZZZ_S + 3153U, // GLD1B_D_IMM_REAL + 3205U, // GLD1B_D_REAL + 3269U, // GLD1B_D_SXTW_REAL + 3333U, // GLD1B_D_UXTW_REAL + 3153U, // GLD1B_S_IMM_REAL + 3397U, // GLD1B_S_SXTW_REAL + 3461U, // GLD1B_S_UXTW_REAL + 26U, // GLD1D_IMM_REAL + 3205U, // GLD1D_REAL + 3525U, // GLD1D_SCALED_REAL + 3269U, // GLD1D_SXTW_REAL + 3589U, // GLD1D_SXTW_SCALED_REAL + 3333U, // GLD1D_UXTW_REAL + 3653U, // GLD1D_UXTW_SCALED_REAL + 26U, // GLD1H_D_IMM_REAL + 3205U, // GLD1H_D_REAL + 3717U, // GLD1H_D_SCALED_REAL + 3269U, // GLD1H_D_SXTW_REAL + 3781U, // GLD1H_D_SXTW_SCALED_REAL + 3333U, // GLD1H_D_UXTW_REAL + 3845U, // GLD1H_D_UXTW_SCALED_REAL + 26U, // GLD1H_S_IMM_REAL + 3397U, // GLD1H_S_SXTW_REAL + 3909U, // GLD1H_S_SXTW_SCALED_REAL + 3461U, // GLD1H_S_UXTW_REAL + 3973U, // GLD1H_S_UXTW_SCALED_REAL + 3153U, // GLD1SB_D_IMM_REAL + 3205U, // GLD1SB_D_REAL + 3269U, // GLD1SB_D_SXTW_REAL + 3333U, // GLD1SB_D_UXTW_REAL + 3153U, // GLD1SB_S_IMM_REAL + 3397U, // GLD1SB_S_SXTW_REAL + 3461U, // GLD1SB_S_UXTW_REAL + 26U, // GLD1SH_D_IMM_REAL + 3205U, // GLD1SH_D_REAL + 3717U, // GLD1SH_D_SCALED_REAL + 3269U, // GLD1SH_D_SXTW_REAL + 3781U, // GLD1SH_D_SXTW_SCALED_REAL + 3333U, // GLD1SH_D_UXTW_REAL + 3845U, // GLD1SH_D_UXTW_SCALED_REAL + 26U, // GLD1SH_S_IMM_REAL + 3397U, // GLD1SH_S_SXTW_REAL + 3909U, // GLD1SH_S_SXTW_SCALED_REAL + 3461U, // GLD1SH_S_UXTW_REAL + 3973U, // GLD1SH_S_UXTW_SCALED_REAL + 27U, // GLD1SW_D_IMM_REAL + 3205U, // GLD1SW_D_REAL + 4037U, // GLD1SW_D_SCALED_REAL + 3269U, // GLD1SW_D_SXTW_REAL + 4101U, // GLD1SW_D_SXTW_SCALED_REAL + 3333U, // GLD1SW_D_UXTW_REAL + 4165U, // GLD1SW_D_UXTW_SCALED_REAL + 27U, // GLD1W_D_IMM_REAL + 3205U, // GLD1W_D_REAL + 4037U, // GLD1W_D_SCALED_REAL + 3269U, // GLD1W_D_SXTW_REAL + 4101U, // GLD1W_D_SXTW_SCALED_REAL + 3333U, // GLD1W_D_UXTW_REAL + 4165U, // GLD1W_D_UXTW_SCALED_REAL + 27U, // GLD1W_IMM_REAL + 3397U, // GLD1W_SXTW_REAL + 4229U, // GLD1W_SXTW_SCALED_REAL + 3461U, // GLD1W_UXTW_REAL + 4293U, // GLD1W_UXTW_SCALED_REAL + 3153U, // GLDFF1B_D_IMM_REAL + 3205U, // GLDFF1B_D_REAL + 3269U, // GLDFF1B_D_SXTW_REAL + 3333U, // GLDFF1B_D_UXTW_REAL + 3153U, // GLDFF1B_S_IMM_REAL + 3397U, // GLDFF1B_S_SXTW_REAL + 3461U, // GLDFF1B_S_UXTW_REAL + 26U, // GLDFF1D_IMM_REAL + 3205U, // GLDFF1D_REAL + 3525U, // GLDFF1D_SCALED_REAL + 3269U, // GLDFF1D_SXTW_REAL + 3589U, // GLDFF1D_SXTW_SCALED_REAL + 3333U, // GLDFF1D_UXTW_REAL + 3653U, // GLDFF1D_UXTW_SCALED_REAL + 26U, // GLDFF1H_D_IMM_REAL + 3205U, // GLDFF1H_D_REAL + 3717U, // GLDFF1H_D_SCALED_REAL + 3269U, // GLDFF1H_D_SXTW_REAL + 3781U, // GLDFF1H_D_SXTW_SCALED_REAL + 3333U, // GLDFF1H_D_UXTW_REAL + 3845U, // GLDFF1H_D_UXTW_SCALED_REAL + 26U, // GLDFF1H_S_IMM_REAL + 3397U, // GLDFF1H_S_SXTW_REAL + 3909U, // GLDFF1H_S_SXTW_SCALED_REAL + 3461U, // GLDFF1H_S_UXTW_REAL + 3973U, // GLDFF1H_S_UXTW_SCALED_REAL + 3153U, // GLDFF1SB_D_IMM_REAL + 3205U, // GLDFF1SB_D_REAL + 3269U, // GLDFF1SB_D_SXTW_REAL + 3333U, // GLDFF1SB_D_UXTW_REAL + 3153U, // GLDFF1SB_S_IMM_REAL + 3397U, // GLDFF1SB_S_SXTW_REAL + 3461U, // GLDFF1SB_S_UXTW_REAL + 26U, // GLDFF1SH_D_IMM_REAL + 3205U, // GLDFF1SH_D_REAL + 3717U, // GLDFF1SH_D_SCALED_REAL + 3269U, // GLDFF1SH_D_SXTW_REAL + 3781U, // GLDFF1SH_D_SXTW_SCALED_REAL + 3333U, // GLDFF1SH_D_UXTW_REAL + 3845U, // GLDFF1SH_D_UXTW_SCALED_REAL + 26U, // GLDFF1SH_S_IMM_REAL + 3397U, // GLDFF1SH_S_SXTW_REAL + 3909U, // GLDFF1SH_S_SXTW_SCALED_REAL + 3461U, // GLDFF1SH_S_UXTW_REAL + 3973U, // GLDFF1SH_S_UXTW_SCALED_REAL + 27U, // GLDFF1SW_D_IMM_REAL + 3205U, // GLDFF1SW_D_REAL + 4037U, // GLDFF1SW_D_SCALED_REAL + 3269U, // GLDFF1SW_D_SXTW_REAL + 4101U, // GLDFF1SW_D_SXTW_SCALED_REAL + 3333U, // GLDFF1SW_D_UXTW_REAL + 4165U, // GLDFF1SW_D_UXTW_SCALED_REAL + 27U, // GLDFF1W_D_IMM_REAL + 3205U, // GLDFF1W_D_REAL + 4037U, // GLDFF1W_D_SCALED_REAL + 3269U, // GLDFF1W_D_SXTW_REAL + 4101U, // GLDFF1W_D_SXTW_SCALED_REAL + 3333U, // GLDFF1W_D_UXTW_REAL + 4165U, // GLDFF1W_D_UXTW_SCALED_REAL + 27U, // GLDFF1W_IMM_REAL + 3397U, // GLDFF1W_SXTW_REAL + 4229U, // GLDFF1W_SXTW_SCALED_REAL + 3461U, // GLDFF1W_UXTW_REAL + 4293U, // GLDFF1W_UXTW_SCALED_REAL 0U, // HINT 0U, // HLT 0U, // HVC - 0U, // INSvi16gpr - 83U, // INSvi16lane - 0U, // INSvi32gpr - 83U, // INSvi32lane - 0U, // INSvi64gpr - 83U, // INSvi64lane - 0U, // INSvi8gpr - 83U, // INSvi8lane + 0U, // INCB_XPiI + 0U, // INCD_XPiI + 0U, // INCD_ZPiI + 0U, // INCH_XPiI + 0U, // INCH_ZPiI + 1U, // INCP_XP_B + 1U, // INCP_XP_D + 1U, // INCP_XP_H + 1U, // INCP_XP_S + 1U, // INCP_ZP_D + 0U, // INCP_ZP_H + 1U, // INCP_ZP_S + 0U, // INCW_XPiI + 0U, // INCW_ZPiI + 261U, // INDEX_II_B + 261U, // INDEX_II_D + 11U, // INDEX_II_H + 261U, // INDEX_II_S + 261U, // INDEX_IR_B + 261U, // INDEX_IR_D + 11U, // INDEX_IR_H + 261U, // INDEX_IR_S + 261U, // INDEX_RI_B + 261U, // INDEX_RI_D + 11U, // INDEX_RI_H + 261U, // INDEX_RI_S + 261U, // INDEX_RR_B + 261U, // INDEX_RR_D + 11U, // INDEX_RR_H + 261U, // INDEX_RR_S + 1U, // INSR_ZR_B + 1U, // INSR_ZR_D + 0U, // INSR_ZR_H + 1U, // INSR_ZR_S + 1U, // INSR_ZV_B + 1U, // INSR_ZV_D + 0U, // INSR_ZV_H + 1U, // INSR_ZV_S + 1U, // INSvi16gpr + 2898U, // INSvi16lane + 1U, // INSvi32gpr + 2898U, // INSvi32lane + 1U, // INSvi64gpr + 2899U, // INSvi64lane + 1U, // INSvi8gpr + 2899U, // INSvi8lane 0U, // ISB + 837U, // LASTA_RPZ_B + 901U, // LASTA_RPZ_D + 2245U, // LASTA_RPZ_H + 1029U, // LASTA_RPZ_S + 837U, // LASTA_VPZ_B + 901U, // LASTA_VPZ_D + 2245U, // LASTA_VPZ_H + 1029U, // LASTA_VPZ_S + 837U, // LASTB_RPZ_B + 901U, // LASTB_RPZ_D + 2245U, // LASTB_RPZ_H + 1029U, // LASTB_RPZ_S + 837U, // LASTB_VPZ_B + 901U, // LASTB_VPZ_D + 2245U, // LASTB_VPZ_H + 1029U, // LASTB_VPZ_S + 4357U, // LD1B + 4357U, // LD1B_D + 256261U, // LD1B_D_IMM_REAL + 4357U, // LD1B_H + 256261U, // LD1B_H_IMM_REAL + 256261U, // LD1B_IMM_REAL + 4357U, // LD1B_S + 256261U, // LD1B_S_IMM_REAL + 4421U, // LD1D + 256261U, // LD1D_IMM_REAL 0U, // LD1Fourv16b 0U, // LD1Fourv16b_POST 0U, // LD1Fourv1d @@ -3155,6 +7203,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD1Fourv8b_POST 0U, // LD1Fourv8h 0U, // LD1Fourv8h_POST + 4485U, // LD1H + 4485U, // LD1H_D + 256261U, // LD1H_D_IMM_REAL + 256261U, // LD1H_IMM_REAL + 4485U, // LD1H_S + 256261U, // LD1H_S_IMM_REAL 0U, // LD1Onev16b 0U, // LD1Onev16b_POST 0U, // LD1Onev1d @@ -3171,6 +7225,30 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD1Onev8b_POST 0U, // LD1Onev8h 0U, // LD1Onev8h_POST + 116997U, // LD1RB_D_IMM + 116997U, // LD1RB_H_IMM + 116997U, // LD1RB_IMM + 116997U, // LD1RB_S_IMM + 119237U, // LD1RD_IMM + 119301U, // LD1RH_D_IMM + 119301U, // LD1RH_IMM + 119301U, // LD1RH_S_IMM + 4357U, // LD1RQ_B + 4677U, // LD1RQ_B_IMM + 4421U, // LD1RQ_D + 4677U, // LD1RQ_D_IMM + 4485U, // LD1RQ_H + 4677U, // LD1RQ_H_IMM + 4741U, // LD1RQ_W + 4677U, // LD1RQ_W_IMM + 116997U, // LD1RSB_D_IMM + 116997U, // LD1RSB_H_IMM + 116997U, // LD1RSB_S_IMM + 119301U, // LD1RSH_D_IMM + 119301U, // LD1RSH_S_IMM + 119493U, // LD1RSW_IMM + 119493U, // LD1RW_D_IMM + 119493U, // LD1RW_IMM 0U, // LD1Rv16b 0U, // LD1Rv16b_POST 0U, // LD1Rv1d @@ -3187,6 +7265,18 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD1Rv8b_POST 0U, // LD1Rv8h 0U, // LD1Rv8h_POST + 4357U, // LD1SB_D + 256261U, // LD1SB_D_IMM_REAL + 4357U, // LD1SB_H + 256261U, // LD1SB_H_IMM_REAL + 4357U, // LD1SB_S + 256261U, // LD1SB_S_IMM_REAL + 4485U, // LD1SH_D + 256261U, // LD1SH_D_IMM_REAL + 4485U, // LD1SH_S + 256261U, // LD1SH_S_IMM_REAL + 4741U, // LD1SW_D + 256261U, // LD1SW_D_IMM_REAL 0U, // LD1Threev16b 0U, // LD1Threev16b_POST 0U, // LD1Threev1d @@ -3219,6 +7309,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD1Twov8b_POST 0U, // LD1Twov8h 0U, // LD1Twov8h_POST + 4741U, // LD1W + 4741U, // LD1W_D + 256261U, // LD1W_D_IMM_REAL + 256261U, // LD1W_IMM_REAL 0U, // LD1i16 0U, // LD1i16_POST 0U, // LD1i32 @@ -3227,6 +7321,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD1i64_POST 0U, // LD1i8 0U, // LD1i8_POST + 4357U, // LD2B + 258565U, // LD2B_IMM + 4421U, // LD2D + 258565U, // LD2D_IMM + 4485U, // LD2H + 258565U, // LD2H_IMM 0U, // LD2Rv16b 0U, // LD2Rv16b_POST 0U, // LD2Rv1d @@ -3257,6 +7357,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD2Twov8b_POST 0U, // LD2Twov8h 0U, // LD2Twov8h_POST + 4741U, // LD2W + 258565U, // LD2W_IMM 0U, // LD2i16 0U, // LD2i16_POST 0U, // LD2i32 @@ -3265,6 +7367,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD2i64_POST 0U, // LD2i8 0U, // LD2i8_POST + 4357U, // LD3B + 4869U, // LD3B_IMM + 4421U, // LD3D + 4869U, // LD3D_IMM + 4485U, // LD3H + 4869U, // LD3H_IMM 0U, // LD3Rv16b 0U, // LD3Rv16b_POST 0U, // LD3Rv1d @@ -3295,6 +7403,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD3Threev8b_POST 0U, // LD3Threev8h 0U, // LD3Threev8h_POST + 4741U, // LD3W + 4869U, // LD3W_IMM 0U, // LD3i16 0U, // LD3i16_POST 0U, // LD3i32 @@ -3303,6 +7413,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD3i64_POST 0U, // LD3i8 0U, // LD3i8_POST + 4357U, // LD4B + 258757U, // LD4B_IMM + 4421U, // LD4D + 258757U, // LD4D_IMM 0U, // LD4Fourv16b 0U, // LD4Fourv16b_POST 0U, // LD4Fourv2d @@ -3317,6 +7431,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD4Fourv8b_POST 0U, // LD4Fourv8h 0U, // LD4Fourv8h_POST + 4485U, // LD4H + 258757U, // LD4H_IMM 0U, // LD4Rv16b 0U, // LD4Rv16b_POST 0U, // LD4Rv1d @@ -3333,6 +7449,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD4Rv8b_POST 0U, // LD4Rv8h 0U, // LD4Rv8h_POST + 4741U, // LD4W + 258757U, // LD4W_IMM 0U, // LD4i16 0U, // LD4i16_POST 0U, // LD4i32 @@ -3341,784 +7459,1392 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // LD4i64_POST 0U, // LD4i8 0U, // LD4i8_POST - 4U, // LDARB - 4U, // LDARH - 4U, // LDARW - 4U, // LDARX - 3588U, // LDAXPW - 3588U, // LDAXPX - 4U, // LDAXRB - 4U, // LDAXRH - 4U, // LDAXRW - 4U, // LDAXRX - 43268U, // LDNPDi - 51460U, // LDNPQi - 59652U, // LDNPSi - 59652U, // LDNPWi - 43268U, // LDNPXi - 43268U, // LDPDi - 69444U, // LDPDpost - 330052U, // LDPDpre - 51460U, // LDPQi - 77636U, // LDPQpost - 338244U, // LDPQpre - 59652U, // LDPSWi - 85828U, // LDPSWpost - 346436U, // LDPSWpre - 59652U, // LDPSi - 85828U, // LDPSpost - 346436U, // LDPSpre - 59652U, // LDPWi - 85828U, // LDPWpost - 346436U, // LDPWpre - 43268U, // LDPXi - 69444U, // LDPXpost - 330052U, // LDPXpre - 4U, // LDRBBpost - 4161U, // LDRBBpre - 92417U, // LDRBBroW - 100609U, // LDRBBroX - 89U, // LDRBBui - 4U, // LDRBpost - 4161U, // LDRBpre - 92417U, // LDRBroW - 100609U, // LDRBroX - 89U, // LDRBui + 0U, // LDADDAB + 0U, // LDADDAH + 0U, // LDADDALB + 0U, // LDADDALH + 0U, // LDADDALW + 0U, // LDADDALX + 0U, // LDADDAW + 0U, // LDADDAX + 0U, // LDADDB + 0U, // LDADDH + 0U, // LDADDLB + 0U, // LDADDLH + 0U, // LDADDLW + 0U, // LDADDLX + 0U, // LDADDW + 0U, // LDADDX + 27U, // LDAPRB + 27U, // LDAPRH + 27U, // LDAPRW + 27U, // LDAPRX + 114949U, // LDAPURBi + 114949U, // LDAPURHi + 114949U, // LDAPURSBWi + 114949U, // LDAPURSBXi + 114949U, // LDAPURSHWi + 114949U, // LDAPURSHXi + 114949U, // LDAPURSWi + 114949U, // LDAPURXi + 114949U, // LDAPURi + 27U, // LDARB + 27U, // LDARH + 27U, // LDARW + 27U, // LDARX + 114955U, // LDAXPW + 114955U, // LDAXPX + 27U, // LDAXRB + 27U, // LDAXRH + 27U, // LDAXRW + 27U, // LDAXRX + 0U, // LDCLRAB + 0U, // LDCLRAH + 0U, // LDCLRALB + 0U, // LDCLRALH + 0U, // LDCLRALW + 0U, // LDCLRALX + 0U, // LDCLRAW + 0U, // LDCLRAX + 0U, // LDCLRB + 0U, // LDCLRH + 0U, // LDCLRLB + 0U, // LDCLRLH + 0U, // LDCLRLW + 0U, // LDCLRLX + 0U, // LDCLRW + 0U, // LDCLRX + 0U, // LDEORAB + 0U, // LDEORAH + 0U, // LDEORALB + 0U, // LDEORALH + 0U, // LDEORALW + 0U, // LDEORALX + 0U, // LDEORAW + 0U, // LDEORAX + 0U, // LDEORB + 0U, // LDEORH + 0U, // LDEORLB + 0U, // LDEORLH + 0U, // LDEORLW + 0U, // LDEORLX + 0U, // LDEORW + 0U, // LDEORX + 4357U, // LDFF1B_D_REAL + 4357U, // LDFF1B_H_REAL + 4357U, // LDFF1B_REAL + 4357U, // LDFF1B_S_REAL + 4421U, // LDFF1D_REAL + 4485U, // LDFF1H_D_REAL + 4485U, // LDFF1H_REAL + 4485U, // LDFF1H_S_REAL + 4357U, // LDFF1SB_D_REAL + 4357U, // LDFF1SB_H_REAL + 4357U, // LDFF1SB_S_REAL + 4485U, // LDFF1SH_D_REAL + 4485U, // LDFF1SH_S_REAL + 4741U, // LDFF1SW_D_REAL + 4741U, // LDFF1W_D_REAL + 4741U, // LDFF1W_REAL + 27U, // LDLARB + 27U, // LDLARH + 27U, // LDLARW + 27U, // LDLARX + 256261U, // LDNF1B_D_IMM_REAL + 256261U, // LDNF1B_H_IMM_REAL + 256261U, // LDNF1B_IMM_REAL + 256261U, // LDNF1B_S_IMM_REAL + 256261U, // LDNF1D_IMM_REAL + 256261U, // LDNF1H_D_IMM_REAL + 256261U, // LDNF1H_IMM_REAL + 256261U, // LDNF1H_S_IMM_REAL + 256261U, // LDNF1SB_D_IMM_REAL + 256261U, // LDNF1SB_H_IMM_REAL + 256261U, // LDNF1SB_S_IMM_REAL + 256261U, // LDNF1SH_D_IMM_REAL + 256261U, // LDNF1SH_S_IMM_REAL + 256261U, // LDNF1SW_D_IMM_REAL + 256261U, // LDNF1W_D_IMM_REAL + 256261U, // LDNF1W_IMM_REAL + 11084043U, // LDNPDi + 11608331U, // LDNPQi + 12132619U, // LDNPSi + 12132619U, // LDNPWi + 11084043U, // LDNPXi + 256261U, // LDNT1B_ZRI + 4357U, // LDNT1B_ZRR + 256261U, // LDNT1D_ZRI + 4421U, // LDNT1D_ZRR + 256261U, // LDNT1H_ZRI + 4485U, // LDNT1H_ZRR + 256261U, // LDNT1W_ZRI + 4741U, // LDNT1W_ZRR + 11084043U, // LDPDi + 12847371U, // LDPDpost + 180431115U, // LDPDpre + 11608331U, // LDPQi + 13371659U, // LDPQpost + 180955403U, // LDPQpre + 12132619U, // LDPSWi + 13895947U, // LDPSWpost + 181479691U, // LDPSWpre + 12132619U, // LDPSi + 13895947U, // LDPSpost + 181479691U, // LDPSpre + 12132619U, // LDPWi + 13895947U, // LDPWpost + 181479691U, // LDPWpre + 11084043U, // LDPXi + 12847371U, // LDPXpost + 180431115U, // LDPXpre + 4933U, // LDRAAindexed + 274885U, // LDRAAwriteback + 4933U, // LDRABindexed + 274885U, // LDRABwriteback + 28U, // LDRBBpost + 272645U, // LDRBBpre + 14229765U, // LDRBBroW + 14754053U, // LDRBBroX + 4997U, // LDRBBui + 28U, // LDRBpost + 272645U, // LDRBpre + 14229765U, // LDRBroW + 14754053U, // LDRBroX + 4997U, // LDRBui 0U, // LDRDl - 4U, // LDRDpost - 4161U, // LDRDpre - 108801U, // LDRDroW - 116993U, // LDRDroX - 97U, // LDRDui - 4U, // LDRHHpost - 4161U, // LDRHHpre - 125185U, // LDRHHroW - 133377U, // LDRHHroX - 105U, // LDRHHui - 4U, // LDRHpost - 4161U, // LDRHpre - 125185U, // LDRHroW - 133377U, // LDRHroX - 105U, // LDRHui + 28U, // LDRDpost + 272645U, // LDRDpre + 15278341U, // LDRDroW + 15802629U, // LDRDroX + 5061U, // LDRDui + 28U, // LDRHHpost + 272645U, // LDRHHpre + 16326917U, // LDRHHroW + 16851205U, // LDRHHroX + 5125U, // LDRHHui + 28U, // LDRHpost + 272645U, // LDRHpre + 16326917U, // LDRHroW + 16851205U, // LDRHroX + 5125U, // LDRHui 0U, // LDRQl - 4U, // LDRQpost - 4161U, // LDRQpre - 141569U, // LDRQroW - 149761U, // LDRQroX - 113U, // LDRQui - 4U, // LDRSBWpost - 4161U, // LDRSBWpre - 92417U, // LDRSBWroW - 100609U, // LDRSBWroX - 89U, // LDRSBWui - 4U, // LDRSBXpost - 4161U, // LDRSBXpre - 92417U, // LDRSBXroW - 100609U, // LDRSBXroX - 89U, // LDRSBXui - 4U, // LDRSHWpost - 4161U, // LDRSHWpre - 125185U, // LDRSHWroW - 133377U, // LDRSHWroX - 105U, // LDRSHWui - 4U, // LDRSHXpost - 4161U, // LDRSHXpre - 125185U, // LDRSHXroW - 133377U, // LDRSHXroX - 105U, // LDRSHXui + 28U, // LDRQpost + 272645U, // LDRQpre + 17375493U, // LDRQroW + 17899781U, // LDRQroX + 5189U, // LDRQui + 28U, // LDRSBWpost + 272645U, // LDRSBWpre + 14229765U, // LDRSBWroW + 14754053U, // LDRSBWroX + 4997U, // LDRSBWui + 28U, // LDRSBXpost + 272645U, // LDRSBXpre + 14229765U, // LDRSBXroW + 14754053U, // LDRSBXroX + 4997U, // LDRSBXui + 28U, // LDRSHWpost + 272645U, // LDRSHWpre + 16326917U, // LDRSHWroW + 16851205U, // LDRSHWroX + 5125U, // LDRSHWui + 28U, // LDRSHXpost + 272645U, // LDRSHXpre + 16326917U, // LDRSHXroW + 16851205U, // LDRSHXroX + 5125U, // LDRSHXui 0U, // LDRSWl - 4U, // LDRSWpost - 4161U, // LDRSWpre - 157953U, // LDRSWroW - 166145U, // LDRSWroX - 121U, // LDRSWui + 28U, // LDRSWpost + 272645U, // LDRSWpre + 18424069U, // LDRSWroW + 18948357U, // LDRSWroX + 5253U, // LDRSWui 0U, // LDRSl - 4U, // LDRSpost - 4161U, // LDRSpre - 157953U, // LDRSroW - 166145U, // LDRSroX - 121U, // LDRSui + 28U, // LDRSpost + 272645U, // LDRSpre + 18424069U, // LDRSroW + 18948357U, // LDRSroX + 5253U, // LDRSui 0U, // LDRWl - 4U, // LDRWpost - 4161U, // LDRWpre - 157953U, // LDRWroW - 166145U, // LDRWroX - 121U, // LDRWui + 28U, // LDRWpost + 272645U, // LDRWpre + 18424069U, // LDRWroW + 18948357U, // LDRWroX + 5253U, // LDRWui 0U, // LDRXl - 4U, // LDRXpost - 4161U, // LDRXpre - 108801U, // LDRXroW - 116993U, // LDRXroX - 97U, // LDRXui - 3585U, // LDTRBi - 3585U, // LDTRHi - 3585U, // LDTRSBWi - 3585U, // LDTRSBXi - 3585U, // LDTRSHWi - 3585U, // LDTRSHXi - 3585U, // LDTRSWi - 3585U, // LDTRWi - 3585U, // LDTRXi - 3585U, // LDURBBi - 3585U, // LDURBi - 3585U, // LDURDi - 3585U, // LDURHHi - 3585U, // LDURHi - 3585U, // LDURQi - 3585U, // LDURSBWi - 3585U, // LDURSBXi - 3585U, // LDURSHWi - 3585U, // LDURSHXi - 3585U, // LDURSWi - 3585U, // LDURSi - 3585U, // LDURWi - 3585U, // LDURXi - 3588U, // LDXPW - 3588U, // LDXPX - 4U, // LDXRB - 4U, // LDXRH - 4U, // LDXRW - 4U, // LDXRX + 28U, // LDRXpost + 272645U, // LDRXpre + 15278341U, // LDRXroW + 15802629U, // LDRXroX + 5061U, // LDRXui + 254213U, // LDR_PXI + 254213U, // LDR_ZXI + 0U, // LDSETAB + 0U, // LDSETAH + 0U, // LDSETALB + 0U, // LDSETALH + 0U, // LDSETALW + 0U, // LDSETALX + 0U, // LDSETAW + 0U, // LDSETAX + 0U, // LDSETB + 0U, // LDSETH + 0U, // LDSETLB + 0U, // LDSETLH + 0U, // LDSETLW + 0U, // LDSETLX + 0U, // LDSETW + 0U, // LDSETX + 0U, // LDSMAXAB + 0U, // LDSMAXAH + 0U, // LDSMAXALB + 0U, // LDSMAXALH + 0U, // LDSMAXALW + 0U, // LDSMAXALX + 0U, // LDSMAXAW + 0U, // LDSMAXAX + 0U, // LDSMAXB + 0U, // LDSMAXH + 0U, // LDSMAXLB + 0U, // LDSMAXLH + 0U, // LDSMAXLW + 0U, // LDSMAXLX + 0U, // LDSMAXW + 0U, // LDSMAXX + 0U, // LDSMINAB + 0U, // LDSMINAH + 0U, // LDSMINALB + 0U, // LDSMINALH + 0U, // LDSMINALW + 0U, // LDSMINALX + 0U, // LDSMINAW + 0U, // LDSMINAX + 0U, // LDSMINB + 0U, // LDSMINH + 0U, // LDSMINLB + 0U, // LDSMINLH + 0U, // LDSMINLW + 0U, // LDSMINLX + 0U, // LDSMINW + 0U, // LDSMINX + 114949U, // LDTRBi + 114949U, // LDTRHi + 114949U, // LDTRSBWi + 114949U, // LDTRSBXi + 114949U, // LDTRSHWi + 114949U, // LDTRSHXi + 114949U, // LDTRSWi + 114949U, // LDTRWi + 114949U, // LDTRXi + 0U, // LDUMAXAB + 0U, // LDUMAXAH + 0U, // LDUMAXALB + 0U, // LDUMAXALH + 0U, // LDUMAXALW + 0U, // LDUMAXALX + 0U, // LDUMAXAW + 0U, // LDUMAXAX + 0U, // LDUMAXB + 0U, // LDUMAXH + 0U, // LDUMAXLB + 0U, // LDUMAXLH + 0U, // LDUMAXLW + 0U, // LDUMAXLX + 0U, // LDUMAXW + 0U, // LDUMAXX + 0U, // LDUMINAB + 0U, // LDUMINAH + 0U, // LDUMINALB + 0U, // LDUMINALH + 0U, // LDUMINALW + 0U, // LDUMINALX + 0U, // LDUMINAW + 0U, // LDUMINAX + 0U, // LDUMINB + 0U, // LDUMINH + 0U, // LDUMINLB + 0U, // LDUMINLH + 0U, // LDUMINLW + 0U, // LDUMINLX + 0U, // LDUMINW + 0U, // LDUMINX + 114949U, // LDURBBi + 114949U, // LDURBi + 114949U, // LDURDi + 114949U, // LDURHHi + 114949U, // LDURHi + 114949U, // LDURQi + 114949U, // LDURSBWi + 114949U, // LDURSBXi + 114949U, // LDURSHWi + 114949U, // LDURSHXi + 114949U, // LDURSWi + 114949U, // LDURSi + 114949U, // LDURWi + 114949U, // LDURXi + 114955U, // LDXPW + 114955U, // LDXPX + 27U, // LDXRB + 27U, // LDXRH + 27U, // LDXRW + 27U, // LDXRX 0U, // LOADgot - 1U, // LSLVWr - 1U, // LSLVXr - 1U, // LSRVWr - 1U, // LSRVXr - 18689U, // MADDWrrr - 18689U, // MADDXrrr - 1041U, // MLAv16i8 - 1297U, // MLAv2i32 - 27665U, // MLAv2i32_indexed - 1553U, // MLAv4i16 - 28945U, // MLAv4i16_indexed - 529U, // MLAv4i32 - 27665U, // MLAv4i32_indexed - 785U, // MLAv8i16 - 28945U, // MLAv8i16_indexed - 1809U, // MLAv8i8 - 1041U, // MLSv16i8 - 1297U, // MLSv2i32 - 27665U, // MLSv2i32_indexed - 1553U, // MLSv4i16 - 28945U, // MLSv4i16_indexed - 529U, // MLSv4i32 - 27665U, // MLSv4i32_indexed - 785U, // MLSv8i16 - 28945U, // MLSv8i16_indexed - 1809U, // MLSv8i8 + 74560U, // LSLR_ZPmZ_B + 598912U, // LSLR_ZPmZ_D + 1131465U, // LSLR_ZPmZ_H + 1647616U, // LSLR_ZPmZ_S + 261U, // LSLVWr + 261U, // LSLVXr + 598848U, // LSL_WIDE_ZPmZ_B + 99273U, // LSL_WIDE_ZPmZ_H + 599040U, // LSL_WIDE_ZPmZ_S + 901U, // LSL_WIDE_ZZZ_B + 10U, // LSL_WIDE_ZZZ_H + 901U, // LSL_WIDE_ZZZ_S + 2171712U, // LSL_ZPmI_B + 2171776U, // LSL_ZPmI_D + 91081U, // LSL_ZPmI_H + 2171904U, // LSL_ZPmI_S + 74560U, // LSL_ZPmZ_B + 598912U, // LSL_ZPmZ_D + 1131465U, // LSL_ZPmZ_H + 1647616U, // LSL_ZPmZ_S + 261U, // LSL_ZZI_B + 261U, // LSL_ZZI_D + 11U, // LSL_ZZI_H + 261U, // LSL_ZZI_S + 74560U, // LSRR_ZPmZ_B + 598912U, // LSRR_ZPmZ_D + 1131465U, // LSRR_ZPmZ_H + 1647616U, // LSRR_ZPmZ_S + 261U, // LSRVWr + 261U, // LSRVXr + 598848U, // LSR_WIDE_ZPmZ_B + 99273U, // LSR_WIDE_ZPmZ_H + 599040U, // LSR_WIDE_ZPmZ_S + 901U, // LSR_WIDE_ZZZ_B + 10U, // LSR_WIDE_ZZZ_H + 901U, // LSR_WIDE_ZZZ_S + 2171712U, // LSR_ZPmI_B + 2171776U, // LSR_ZPmI_D + 91081U, // LSR_ZPmI_H + 2171904U, // LSR_ZPmI_S + 74560U, // LSR_ZPmZ_B + 598912U, // LSR_ZPmZ_D + 1131465U, // LSR_ZPmZ_H + 1647616U, // LSR_ZPmZ_S + 261U, // LSR_ZZI_B + 261U, // LSR_ZZI_D + 11U, // LSR_ZZI_H + 261U, // LSR_ZZI_S + 2171141U, // MADDWrrr + 2171141U, // MADDXrrr + 19472384U, // MAD_ZPmZZ_B + 6889536U, // MAD_ZPmZZ_D + 1246144U, // MAD_ZPmZZ_H + 7413952U, // MAD_ZPmZZ_S + 19472384U, // MLA_ZPmZZ_B + 6889536U, // MLA_ZPmZZ_D + 1246144U, // MLA_ZPmZZ_H + 7413952U, // MLA_ZPmZZ_S + 33159U, // MLAv16i8 + 41351U, // MLAv2i32 + 9126279U, // MLAv2i32_indexed + 49544U, // MLAv4i16 + 9118088U, // MLAv4i16_indexed + 16774U, // MLAv4i32 + 9126278U, // MLAv4i32_indexed + 24966U, // MLAv8i16 + 9118086U, // MLAv8i16_indexed + 57736U, // MLAv8i8 + 19472384U, // MLS_ZPmZZ_B + 6889536U, // MLS_ZPmZZ_D + 1246144U, // MLS_ZPmZZ_H + 7413952U, // MLS_ZPmZZ_S + 33159U, // MLSv16i8 + 41351U, // MLSv2i32 + 9126279U, // MLSv2i32_indexed + 49544U, // MLSv4i16 + 9118088U, // MLSv4i16_indexed + 16774U, // MLSv4i32 + 9126278U, // MLSv4i32_indexed + 24966U, // MLSv8i16 + 9118086U, // MLSv8i16_indexed + 57736U, // MLSv8i8 0U, // MOVID - 0U, // MOVIv16b_ns + 1U, // MOVIv16b_ns 0U, // MOVIv2d_ns - 4U, // MOVIv2i32 - 4U, // MOVIv2s_msl - 4U, // MOVIv4i16 - 4U, // MOVIv4i32 - 4U, // MOVIv4s_msl - 0U, // MOVIv8b_ns - 4U, // MOVIv8i16 + 28U, // MOVIv2i32 + 28U, // MOVIv2s_msl + 28U, // MOVIv4i16 + 28U, // MOVIv4i32 + 28U, // MOVIv4s_msl + 1U, // MOVIv8b_ns + 28U, // MOVIv8i16 0U, // MOVKWi 0U, // MOVKXi - 4U, // MOVNWi - 4U, // MOVNXi - 4U, // MOVZWi - 4U, // MOVZXi + 28U, // MOVNWi + 28U, // MOVNXi + 0U, // MOVPRFX_ZPmZ_B + 64U, // MOVPRFX_ZPmZ_D + 128U, // MOVPRFX_ZPmZ_H + 192U, // MOVPRFX_ZPmZ_S + 842U, // MOVPRFX_ZPzZ_B + 906U, // MOVPRFX_ZPzZ_D + 137U, // MOVPRFX_ZPzZ_H + 1034U, // MOVPRFX_ZPzZ_S + 1U, // MOVPRFX_ZZ + 28U, // MOVZWi + 28U, // MOVZXi 0U, // MOVaddr 0U, // MOVaddrBA 0U, // MOVaddrCP 0U, // MOVaddrEXT 0U, // MOVaddrJT 0U, // MOVaddrTLS + 0U, // MOVbaseTLS 0U, // MOVi32imm 0U, // MOVi64imm 0U, // MRS + 19472384U, // MSB_ZPmZZ_B + 6889536U, // MSB_ZPmZZ_D + 1246144U, // MSB_ZPmZZ_H + 7413952U, // MSB_ZPmZZ_S 0U, // MSR - 0U, // MSRpstate - 18689U, // MSUBWrrr - 18689U, // MSUBXrrr - 1033U, // MULv16i8 - 1289U, // MULv2i32 - 35849U, // MULv2i32_indexed - 1545U, // MULv4i16 - 37129U, // MULv4i16_indexed - 521U, // MULv4i32 - 35849U, // MULv4i32_indexed - 777U, // MULv8i16 - 37129U, // MULv8i16_indexed - 1801U, // MULv8i8 - 4U, // MVNIv2i32 - 4U, // MVNIv2s_msl - 4U, // MVNIv4i16 - 4U, // MVNIv4i32 - 4U, // MVNIv4s_msl - 4U, // MVNIv8i16 - 0U, // NEGv16i8 - 0U, // NEGv1i64 - 0U, // NEGv2i32 - 0U, // NEGv2i64 - 0U, // NEGv4i16 - 0U, // NEGv4i32 - 0U, // NEGv8i16 - 0U, // NEGv8i8 - 0U, // NOTv16i8 - 0U, // NOTv8i8 + 0U, // MSRpstateImm1 + 0U, // MSRpstateImm4 + 2171141U, // MSUBWrrr + 2171141U, // MSUBXrrr + 261U, // MUL_ZI_B + 261U, // MUL_ZI_D + 11U, // MUL_ZI_H + 261U, // MUL_ZI_S + 74560U, // MUL_ZPmZ_B + 598912U, // MUL_ZPmZ_D + 1131465U, // MUL_ZPmZ_H + 1647616U, // MUL_ZPmZ_S + 33095U, // MULv16i8 + 41287U, // MULv2i32 + 10174791U, // MULv2i32_indexed + 49480U, // MULv4i16 + 10166600U, // MULv4i16_indexed + 16710U, // MULv4i32 + 10174790U, // MULv4i32_indexed + 24902U, // MULv8i16 + 10166598U, // MULv8i16_indexed + 57672U, // MULv8i8 + 28U, // MVNIv2i32 + 28U, // MVNIv2s_msl + 28U, // MVNIv4i16 + 28U, // MVNIv4i32 + 28U, // MVNIv4s_msl + 28U, // MVNIv8i16 + 74570U, // NANDS_PPzPP + 74570U, // NAND_PPzPP + 0U, // NEG_ZPmZ_B + 64U, // NEG_ZPmZ_D + 128U, // NEG_ZPmZ_H + 192U, // NEG_ZPmZ_S + 1U, // NEGv16i8 + 1U, // NEGv1i64 + 2U, // NEGv2i32 + 2U, // NEGv2i64 + 3U, // NEGv4i16 + 3U, // NEGv4i32 + 4U, // NEGv8i16 + 4U, // NEGv8i8 + 74570U, // NORS_PPzPP + 74570U, // NOR_PPzPP + 0U, // NOT_ZPmZ_B + 64U, // NOT_ZPmZ_D + 128U, // NOT_ZPmZ_H + 192U, // NOT_ZPmZ_S + 1U, // NOTv16i8 + 4U, // NOTv8i8 + 74570U, // ORNS_PPzPP 0U, // ORNWrr - 33U, // ORNWrs + 517U, // ORNWrs 0U, // ORNXrr - 33U, // ORNXrs - 1033U, // ORNv16i8 - 1801U, // ORNv8i8 - 49U, // ORRWri + 517U, // ORNXrs + 74570U, // ORN_PPzPP + 33095U, // ORNv16i8 + 57672U, // ORNv8i8 + 74570U, // ORRS_PPzPP + 2117U, // ORRWri 0U, // ORRWrr - 33U, // ORRWrs - 57U, // ORRXri + 517U, // ORRWrs + 2181U, // ORRXri 0U, // ORRXrr - 33U, // ORRXrs - 1033U, // ORRv16i8 + 517U, // ORRXrs + 74570U, // ORR_PPzPP + 2181U, // ORR_ZI + 74560U, // ORR_ZPmZ_B + 598912U, // ORR_ZPmZ_D + 1131465U, // ORR_ZPmZ_H + 1647616U, // ORR_ZPmZ_S + 901U, // ORR_ZZZ + 33095U, // ORRv16i8 0U, // ORRv2i32 0U, // ORRv4i16 0U, // ORRv4i32 0U, // ORRv8i16 - 1801U, // ORRv8i8 - 1033U, // PMULLv16i8 + 57672U, // ORRv8i8 + 837U, // ORV_VPZ_B + 901U, // ORV_VPZ_D + 2245U, // ORV_VPZ_H + 1029U, // ORV_VPZ_S + 1U, // PACDA + 1U, // PACDB + 0U, // PACDZA + 0U, // PACDZB + 261U, // PACGA + 1U, // PACIA + 0U, // PACIA1716 + 0U, // PACIASP + 0U, // PACIAZ + 1U, // PACIB + 0U, // PACIB1716 + 0U, // PACIBSP + 0U, // PACIBZ + 0U, // PACIZA + 0U, // PACIZB + 0U, // PFALSE + 33095U, // PMULLv16i8 0U, // PMULLv1i64 0U, // PMULLv2i64 - 1801U, // PMULLv8i8 - 1033U, // PMULv16i8 - 1801U, // PMULv8i8 + 57672U, // PMULLv8i8 + 33095U, // PMULv16i8 + 57672U, // PMULv8i8 + 837U, // PNEXT_B + 901U, // PNEXT_D + 137U, // PNEXT_H + 1029U, // PNEXT_S + 27U, // PRFB_D_PZI + 29U, // PRFB_D_SCALED + 29U, // PRFB_D_SXTW_SCALED + 30U, // PRFB_D_UXTW_SCALED + 5329U, // PRFB_PRI + 30U, // PRFB_PRR + 27U, // PRFB_S_PZI + 31U, // PRFB_S_SXTW_SCALED + 31U, // PRFB_S_UXTW_SCALED + 0U, // PRFD_D_PZI + 32U, // PRFD_D_SCALED + 32U, // PRFD_D_SXTW_SCALED + 33U, // PRFD_D_UXTW_SCALED + 5329U, // PRFD_PRI + 33U, // PRFD_PRR + 0U, // PRFD_S_PZI + 34U, // PRFD_S_SXTW_SCALED + 34U, // PRFD_S_UXTW_SCALED + 0U, // PRFH_D_PZI + 35U, // PRFH_D_SCALED + 35U, // PRFH_D_SXTW_SCALED + 36U, // PRFH_D_UXTW_SCALED + 5329U, // PRFH_PRI + 36U, // PRFH_PRR + 0U, // PRFH_S_PZI + 37U, // PRFH_S_SXTW_SCALED + 37U, // PRFH_S_UXTW_SCALED 0U, // PRFMl - 108801U, // PRFMroW - 116993U, // PRFMroX - 97U, // PRFMui - 3585U, // PRFUMi - 265U, // RADDHNv2i64_v2i32 - 273U, // RADDHNv2i64_v4i32 - 521U, // RADDHNv4i32_v4i16 - 529U, // RADDHNv4i32_v8i16 - 785U, // RADDHNv8i16_v16i8 - 777U, // RADDHNv8i16_v8i8 - 0U, // RBITWr - 0U, // RBITXr - 0U, // RBITv16i8 - 0U, // RBITv8i8 + 15278341U, // PRFMroW + 15802629U, // PRFMroX + 5061U, // PRFMui + 38U, // PRFS_PRR + 114949U, // PRFUMi + 0U, // PRFW_D_PZI + 38U, // PRFW_D_SCALED + 39U, // PRFW_D_SXTW_SCALED + 39U, // PRFW_D_UXTW_SCALED + 5329U, // PRFW_PRI + 0U, // PRFW_S_PZI + 40U, // PRFW_S_SXTW_SCALED + 40U, // PRFW_S_UXTW_SCALED + 1U, // PTEST_PP + 1U, // PTRUES_B + 1U, // PTRUES_D + 0U, // PTRUES_H + 1U, // PTRUES_S + 1U, // PTRUE_B + 1U, // PTRUE_D + 0U, // PTRUE_H + 1U, // PTRUE_S + 0U, // PUNPKHI_PP + 0U, // PUNPKLO_PP + 8517U, // RADDHNv2i64_v2i32 + 8581U, // RADDHNv2i64_v4i32 + 16710U, // RADDHNv4i32_v4i16 + 16774U, // RADDHNv4i32_v8i16 + 24966U, // RADDHNv8i16_v16i8 + 24902U, // RADDHNv8i16_v8i8 + 8517U, // RAX1 + 1U, // RBITWr + 1U, // RBITXr + 0U, // RBIT_ZPmZ_B + 64U, // RBIT_ZPmZ_D + 128U, // RBIT_ZPmZ_H + 192U, // RBIT_ZPmZ_S + 1U, // RBITv16i8 + 4U, // RBITv8i8 + 41U, // RDFFRS_PPz + 0U, // RDFFR_P + 41U, // RDFFR_PPz + 1U, // RDVLI_XI 0U, // RET + 0U, // RETAA + 0U, // RETAB 0U, // RET_ReallyLR - 0U, // REV16Wr - 0U, // REV16Xr - 0U, // REV16v16i8 - 0U, // REV16v8i8 - 0U, // REV32Xr - 0U, // REV32v16i8 - 0U, // REV32v4i16 - 0U, // REV32v8i16 - 0U, // REV32v8i8 - 0U, // REV64v16i8 - 0U, // REV64v2i32 - 0U, // REV64v4i16 - 0U, // REV64v4i32 - 0U, // REV64v8i16 - 0U, // REV64v8i8 - 0U, // REVWr - 0U, // REVXr - 1U, // RORVWr - 1U, // RORVXr - 65U, // RSHRNv16i8_shift - 1U, // RSHRNv2i32_shift - 1U, // RSHRNv4i16_shift - 65U, // RSHRNv4i32_shift - 65U, // RSHRNv8i16_shift - 1U, // RSHRNv8i8_shift - 265U, // RSUBHNv2i64_v2i32 - 273U, // RSUBHNv2i64_v4i32 - 521U, // RSUBHNv4i32_v4i16 - 529U, // RSUBHNv4i32_v8i16 - 785U, // RSUBHNv8i16_v16i8 - 777U, // RSUBHNv8i16_v8i8 - 1041U, // SABALv16i8_v8i16 - 1297U, // SABALv2i32_v2i64 - 1553U, // SABALv4i16_v4i32 - 529U, // SABALv4i32_v2i64 - 785U, // SABALv8i16_v4i32 - 1809U, // SABALv8i8_v8i16 - 1041U, // SABAv16i8 - 1297U, // SABAv2i32 - 1553U, // SABAv4i16 - 529U, // SABAv4i32 - 785U, // SABAv8i16 - 1809U, // SABAv8i8 - 1033U, // SABDLv16i8_v8i16 - 1289U, // SABDLv2i32_v2i64 - 1545U, // SABDLv4i16_v4i32 - 521U, // SABDLv4i32_v2i64 - 777U, // SABDLv8i16_v4i32 - 1801U, // SABDLv8i8_v8i16 - 1033U, // SABDv16i8 - 1289U, // SABDv2i32 - 1545U, // SABDv4i16 - 521U, // SABDv4i32 - 777U, // SABDv8i16 - 1801U, // SABDv8i8 - 0U, // SADALPv16i8_v8i16 - 0U, // SADALPv2i32_v1i64 - 0U, // SADALPv4i16_v2i32 - 0U, // SADALPv4i32_v2i64 - 0U, // SADALPv8i16_v4i32 - 0U, // SADALPv8i8_v4i16 - 0U, // SADDLPv16i8_v8i16 - 0U, // SADDLPv2i32_v1i64 - 0U, // SADDLPv4i16_v2i32 - 0U, // SADDLPv4i32_v2i64 - 0U, // SADDLPv8i16_v4i32 - 0U, // SADDLPv8i8_v4i16 - 0U, // SADDLVv16i8v - 0U, // SADDLVv4i16v - 0U, // SADDLVv4i32v - 0U, // SADDLVv8i16v - 0U, // SADDLVv8i8v - 1033U, // SADDLv16i8_v8i16 - 1289U, // SADDLv2i32_v2i64 - 1545U, // SADDLv4i16_v4i32 - 521U, // SADDLv4i32_v2i64 - 777U, // SADDLv8i16_v4i32 - 1801U, // SADDLv8i8_v8i16 - 1033U, // SADDWv16i8_v8i16 - 1289U, // SADDWv2i32_v2i64 - 1545U, // SADDWv4i16_v4i32 - 521U, // SADDWv4i32_v2i64 - 777U, // SADDWv8i16_v4i32 - 1801U, // SADDWv8i8_v8i16 - 1U, // SBCSWr - 1U, // SBCSXr - 1U, // SBCWr - 1U, // SBCXr - 18689U, // SBFMWri - 18689U, // SBFMXri - 1U, // SCVTFSWDri - 1U, // SCVTFSWSri - 1U, // SCVTFSXDri - 1U, // SCVTFSXSri - 0U, // SCVTFUWDri - 0U, // SCVTFUWSri - 0U, // SCVTFUXDri - 0U, // SCVTFUXSri - 1U, // SCVTFd - 1U, // SCVTFs - 0U, // SCVTFv1i32 - 0U, // SCVTFv1i64 - 0U, // SCVTFv2f32 - 0U, // SCVTFv2f64 - 1U, // SCVTFv2i32_shift - 1U, // SCVTFv2i64_shift - 0U, // SCVTFv4f32 - 1U, // SCVTFv4i32_shift - 1U, // SDIVWr - 1U, // SDIVXr - 1U, // SDIV_IntWr - 1U, // SDIV_IntXr - 529U, // SHA1Crrr - 0U, // SHA1Hrr - 529U, // SHA1Mrrr - 529U, // SHA1Prrr - 529U, // SHA1SU0rrr - 0U, // SHA1SU1rr - 529U, // SHA256H2rrr - 529U, // SHA256Hrrr - 0U, // SHA256SU0rr - 529U, // SHA256SU1rrr - 1033U, // SHADDv16i8 - 1289U, // SHADDv2i32 - 1545U, // SHADDv4i16 - 521U, // SHADDv4i32 - 777U, // SHADDv8i16 - 1801U, // SHADDv8i8 - 4U, // SHLLv16i8 - 4U, // SHLLv2i32 - 4U, // SHLLv4i16 - 4U, // SHLLv4i32 - 5U, // SHLLv8i16 - 5U, // SHLLv8i8 - 1U, // SHLd - 1U, // SHLv16i8_shift - 1U, // SHLv2i32_shift - 1U, // SHLv2i64_shift - 1U, // SHLv4i16_shift - 1U, // SHLv4i32_shift - 1U, // SHLv8i16_shift - 1U, // SHLv8i8_shift - 65U, // SHRNv16i8_shift - 1U, // SHRNv2i32_shift - 1U, // SHRNv4i16_shift - 65U, // SHRNv4i32_shift - 65U, // SHRNv8i16_shift - 1U, // SHRNv8i8_shift - 1033U, // SHSUBv16i8 - 1289U, // SHSUBv2i32 - 1545U, // SHSUBv4i16 - 521U, // SHSUBv4i32 - 777U, // SHSUBv8i16 - 1801U, // SHSUBv8i8 - 65U, // SLId - 65U, // SLIv16i8_shift - 65U, // SLIv2i32_shift - 65U, // SLIv2i64_shift - 65U, // SLIv4i16_shift - 65U, // SLIv4i32_shift - 65U, // SLIv8i16_shift - 65U, // SLIv8i8_shift - 18689U, // SMADDLrrr - 1033U, // SMAXPv16i8 - 1289U, // SMAXPv2i32 - 1545U, // SMAXPv4i16 - 521U, // SMAXPv4i32 - 777U, // SMAXPv8i16 - 1801U, // SMAXPv8i8 - 0U, // SMAXVv16i8v - 0U, // SMAXVv4i16v - 0U, // SMAXVv4i32v - 0U, // SMAXVv8i16v - 0U, // SMAXVv8i8v - 1033U, // SMAXv16i8 - 1289U, // SMAXv2i32 - 1545U, // SMAXv4i16 - 521U, // SMAXv4i32 - 777U, // SMAXv8i16 - 1801U, // SMAXv8i8 + 1U, // REV16Wr + 1U, // REV16Xr + 1U, // REV16v16i8 + 4U, // REV16v8i8 + 1U, // REV32Xr + 1U, // REV32v16i8 + 3U, // REV32v4i16 + 4U, // REV32v8i16 + 4U, // REV32v8i8 + 1U, // REV64v16i8 + 2U, // REV64v2i32 + 3U, // REV64v4i16 + 3U, // REV64v4i32 + 4U, // REV64v8i16 + 4U, // REV64v8i8 + 64U, // REVB_ZPmZ_D + 128U, // REVB_ZPmZ_H + 192U, // REVB_ZPmZ_S + 64U, // REVH_ZPmZ_D + 192U, // REVH_ZPmZ_S + 64U, // REVW_ZPmZ_D + 1U, // REVWr + 1U, // REVXr + 1U, // REV_PP_B + 1U, // REV_PP_D + 0U, // REV_PP_H + 1U, // REV_PP_S + 1U, // REV_ZZ_B + 1U, // REV_ZZ_D + 0U, // REV_ZZ_H + 1U, // REV_ZZ_S + 261U, // RMIF + 261U, // RORVWr + 261U, // RORVXr + 2310U, // RSHRNv16i8_shift + 261U, // RSHRNv2i32_shift + 262U, // RSHRNv4i16_shift + 2309U, // RSHRNv4i32_shift + 2310U, // RSHRNv8i16_shift + 262U, // RSHRNv8i8_shift + 8517U, // RSUBHNv2i64_v2i32 + 8581U, // RSUBHNv2i64_v4i32 + 16710U, // RSUBHNv4i32_v4i16 + 16774U, // RSUBHNv4i32_v8i16 + 24966U, // RSUBHNv8i16_v16i8 + 24902U, // RSUBHNv8i16_v8i8 + 33159U, // SABALv16i8_v8i16 + 41351U, // SABALv2i32_v2i64 + 49544U, // SABALv4i16_v4i32 + 16774U, // SABALv4i32_v2i64 + 24966U, // SABALv8i16_v4i32 + 57736U, // SABALv8i8_v8i16 + 33159U, // SABAv16i8 + 41351U, // SABAv2i32 + 49544U, // SABAv4i16 + 16774U, // SABAv4i32 + 24966U, // SABAv8i16 + 57736U, // SABAv8i8 + 33095U, // SABDLv16i8_v8i16 + 41287U, // SABDLv2i32_v2i64 + 49480U, // SABDLv4i16_v4i32 + 16710U, // SABDLv4i32_v2i64 + 24902U, // SABDLv8i16_v4i32 + 57672U, // SABDLv8i8_v8i16 + 74560U, // SABD_ZPmZ_B + 598912U, // SABD_ZPmZ_D + 1131465U, // SABD_ZPmZ_H + 1647616U, // SABD_ZPmZ_S + 33095U, // SABDv16i8 + 41287U, // SABDv2i32 + 49480U, // SABDv4i16 + 16710U, // SABDv4i32 + 24902U, // SABDv8i16 + 57672U, // SABDv8i8 + 1U, // SADALPv16i8_v8i16 + 2U, // SADALPv2i32_v1i64 + 3U, // SADALPv4i16_v2i32 + 3U, // SADALPv4i32_v2i64 + 4U, // SADALPv8i16_v4i32 + 4U, // SADALPv8i8_v4i16 + 1U, // SADDLPv16i8_v8i16 + 2U, // SADDLPv2i32_v1i64 + 3U, // SADDLPv4i16_v2i32 + 3U, // SADDLPv4i32_v2i64 + 4U, // SADDLPv8i16_v4i32 + 4U, // SADDLPv8i8_v4i16 + 1U, // SADDLVv16i8v + 3U, // SADDLVv4i16v + 3U, // SADDLVv4i32v + 4U, // SADDLVv8i16v + 4U, // SADDLVv8i8v + 33095U, // SADDLv16i8_v8i16 + 41287U, // SADDLv2i32_v2i64 + 49480U, // SADDLv4i16_v4i32 + 16710U, // SADDLv4i32_v2i64 + 24902U, // SADDLv8i16_v4i32 + 57672U, // SADDLv8i8_v8i16 + 837U, // SADDV_VPZ_B + 2245U, // SADDV_VPZ_H + 1029U, // SADDV_VPZ_S + 33094U, // SADDWv16i8_v8i16 + 41285U, // SADDWv2i32_v2i64 + 49478U, // SADDWv4i16_v4i32 + 16709U, // SADDWv4i32_v2i64 + 24902U, // SADDWv8i16_v4i32 + 57670U, // SADDWv8i8_v8i16 + 261U, // SBCSWr + 261U, // SBCSXr + 261U, // SBCWr + 261U, // SBCXr + 2171141U, // SBFMWri + 2171141U, // SBFMXri + 261U, // SCVTFSWDri + 261U, // SCVTFSWHri + 261U, // SCVTFSWSri + 261U, // SCVTFSXDri + 261U, // SCVTFSXHri + 261U, // SCVTFSXSri + 1U, // SCVTFUWDri + 1U, // SCVTFUWHri + 1U, // SCVTFUWSri + 1U, // SCVTFUXDri + 1U, // SCVTFUXHri + 1U, // SCVTFUXSri + 64U, // SCVTF_ZPmZ_DtoD + 153U, // SCVTF_ZPmZ_DtoH + 64U, // SCVTF_ZPmZ_DtoS + 128U, // SCVTF_ZPmZ_HtoH + 192U, // SCVTF_ZPmZ_StoD + 152U, // SCVTF_ZPmZ_StoH + 192U, // SCVTF_ZPmZ_StoS + 261U, // SCVTFd + 261U, // SCVTFh + 261U, // SCVTFs + 1U, // SCVTFv1i16 + 1U, // SCVTFv1i32 + 1U, // SCVTFv1i64 + 2U, // SCVTFv2f32 + 2U, // SCVTFv2f64 + 263U, // SCVTFv2i32_shift + 261U, // SCVTFv2i64_shift + 3U, // SCVTFv4f16 + 3U, // SCVTFv4f32 + 264U, // SCVTFv4i16_shift + 262U, // SCVTFv4i32_shift + 4U, // SCVTFv8f16 + 262U, // SCVTFv8i16_shift + 598912U, // SDIVR_ZPmZ_D + 1647616U, // SDIVR_ZPmZ_S + 261U, // SDIVWr + 261U, // SDIVXr + 598912U, // SDIV_ZPmZ_D + 1647616U, // SDIV_ZPmZ_S + 41U, // SDOT_ZZZI_D + 41U, // SDOT_ZZZI_S + 1U, // SDOT_ZZZ_D + 1U, // SDOT_ZZZ_S + 278919U, // SDOTlanev16i8 + 278920U, // SDOTlanev8i8 + 33159U, // SDOTv16i8 + 57736U, // SDOTv8i8 + 74565U, // SEL_PPPP + 74565U, // SEL_ZPZZ_B + 598917U, // SEL_ZPZZ_D + 1131465U, // SEL_ZPZZ_H + 1647621U, // SEL_ZPZZ_S + 0U, // SETF16 + 0U, // SETF8 + 0U, // SETFFR + 16773U, // SHA1Crrr + 1U, // SHA1Hrr + 16773U, // SHA1Mrrr + 16773U, // SHA1Prrr + 16774U, // SHA1SU0rrr + 3U, // SHA1SU1rr + 16773U, // SHA256H2rrr + 16773U, // SHA256Hrrr + 3U, // SHA256SU0rr + 16774U, // SHA256SU1rrr + 8581U, // SHA512H + 8581U, // SHA512H2 + 2U, // SHA512SU0 + 8581U, // SHA512SU1 + 33095U, // SHADDv16i8 + 41287U, // SHADDv2i32 + 49480U, // SHADDv4i16 + 16710U, // SHADDv4i32 + 24902U, // SHADDv8i16 + 57672U, // SHADDv8i8 + 42U, // SHLLv16i8 + 42U, // SHLLv2i32 + 43U, // SHLLv4i16 + 43U, // SHLLv4i32 + 44U, // SHLLv8i16 + 44U, // SHLLv8i8 + 261U, // SHLd + 263U, // SHLv16i8_shift + 263U, // SHLv2i32_shift + 261U, // SHLv2i64_shift + 264U, // SHLv4i16_shift + 262U, // SHLv4i32_shift + 262U, // SHLv8i16_shift + 264U, // SHLv8i8_shift + 2310U, // SHRNv16i8_shift + 261U, // SHRNv2i32_shift + 262U, // SHRNv4i16_shift + 2309U, // SHRNv4i32_shift + 2310U, // SHRNv8i16_shift + 262U, // SHRNv8i8_shift + 33095U, // SHSUBv16i8 + 41287U, // SHSUBv2i32 + 49480U, // SHSUBv4i16 + 16710U, // SHSUBv4i32 + 24902U, // SHSUBv8i16 + 57672U, // SHSUBv8i8 + 2309U, // SLId + 2311U, // SLIv16i8_shift + 2311U, // SLIv2i32_shift + 2309U, // SLIv2i64_shift + 2312U, // SLIv4i16_shift + 2310U, // SLIv4i32_shift + 2310U, // SLIv8i16_shift + 2312U, // SLIv8i8_shift + 16774U, // SM3PARTW1 + 16774U, // SM3PARTW2 + 204120390U, // SM3SS1 + 9126278U, // SM3TT1A + 9126278U, // SM3TT1B + 9126278U, // SM3TT2A + 9126278U, // SM3TT2B + 3U, // SM4E + 16710U, // SM4ENCKEY + 2171141U, // SMADDLrrr + 33095U, // SMAXPv16i8 + 41287U, // SMAXPv2i32 + 49480U, // SMAXPv4i16 + 16710U, // SMAXPv4i32 + 24902U, // SMAXPv8i16 + 57672U, // SMAXPv8i8 + 837U, // SMAXV_VPZ_B + 901U, // SMAXV_VPZ_D + 2245U, // SMAXV_VPZ_H + 1029U, // SMAXV_VPZ_S + 1U, // SMAXVv16i8v + 3U, // SMAXVv4i16v + 3U, // SMAXVv4i32v + 4U, // SMAXVv8i16v + 4U, // SMAXVv8i8v + 261U, // SMAX_ZI_B + 261U, // SMAX_ZI_D + 11U, // SMAX_ZI_H + 261U, // SMAX_ZI_S + 74560U, // SMAX_ZPmZ_B + 598912U, // SMAX_ZPmZ_D + 1131465U, // SMAX_ZPmZ_H + 1647616U, // SMAX_ZPmZ_S + 33095U, // SMAXv16i8 + 41287U, // SMAXv2i32 + 49480U, // SMAXv4i16 + 16710U, // SMAXv4i32 + 24902U, // SMAXv8i16 + 57672U, // SMAXv8i8 0U, // SMC - 1033U, // SMINPv16i8 - 1289U, // SMINPv2i32 - 1545U, // SMINPv4i16 - 521U, // SMINPv4i32 - 777U, // SMINPv8i16 - 1801U, // SMINPv8i8 - 0U, // SMINVv16i8v - 0U, // SMINVv4i16v - 0U, // SMINVv4i32v - 0U, // SMINVv8i16v - 0U, // SMINVv8i8v - 1033U, // SMINv16i8 - 1289U, // SMINv2i32 - 1545U, // SMINv4i16 - 521U, // SMINv4i32 - 777U, // SMINv8i16 - 1801U, // SMINv8i8 - 1041U, // SMLALv16i8_v8i16 - 27665U, // SMLALv2i32_indexed - 1297U, // SMLALv2i32_v2i64 - 28945U, // SMLALv4i16_indexed - 1553U, // SMLALv4i16_v4i32 - 27665U, // SMLALv4i32_indexed - 529U, // SMLALv4i32_v2i64 - 28945U, // SMLALv8i16_indexed - 785U, // SMLALv8i16_v4i32 - 1809U, // SMLALv8i8_v8i16 - 1041U, // SMLSLv16i8_v8i16 - 27665U, // SMLSLv2i32_indexed - 1297U, // SMLSLv2i32_v2i64 - 28945U, // SMLSLv4i16_indexed - 1553U, // SMLSLv4i16_v4i32 - 27665U, // SMLSLv4i32_indexed - 529U, // SMLSLv4i32_v2i64 - 28945U, // SMLSLv8i16_indexed - 785U, // SMLSLv8i16_v4i32 - 1809U, // SMLSLv8i8_v8i16 - 75U, // SMOVvi16to32 - 75U, // SMOVvi16to64 - 75U, // SMOVvi32to64 - 75U, // SMOVvi8to32 - 75U, // SMOVvi8to64 - 18689U, // SMSUBLrrr - 1U, // SMULHrr - 1033U, // SMULLv16i8_v8i16 - 35849U, // SMULLv2i32_indexed - 1289U, // SMULLv2i32_v2i64 - 37129U, // SMULLv4i16_indexed - 1545U, // SMULLv4i16_v4i32 - 35849U, // SMULLv4i32_indexed - 521U, // SMULLv4i32_v2i64 - 37129U, // SMULLv8i16_indexed - 777U, // SMULLv8i16_v4i32 - 1801U, // SMULLv8i8_v8i16 - 0U, // SQABSv16i8 - 0U, // SQABSv1i16 - 0U, // SQABSv1i32 - 0U, // SQABSv1i64 - 0U, // SQABSv1i8 - 0U, // SQABSv2i32 - 0U, // SQABSv2i64 - 0U, // SQABSv4i16 - 0U, // SQABSv4i32 - 0U, // SQABSv8i16 - 0U, // SQABSv8i8 - 1033U, // SQADDv16i8 - 1U, // SQADDv1i16 - 1U, // SQADDv1i32 - 1U, // SQADDv1i64 - 1U, // SQADDv1i8 - 1289U, // SQADDv2i32 - 265U, // SQADDv2i64 - 1545U, // SQADDv4i16 - 521U, // SQADDv4i32 - 777U, // SQADDv8i16 - 1801U, // SQADDv8i8 - 65U, // SQDMLALi16 - 65U, // SQDMLALi32 - 28945U, // SQDMLALv1i32_indexed - 27665U, // SQDMLALv1i64_indexed - 27665U, // SQDMLALv2i32_indexed - 1297U, // SQDMLALv2i32_v2i64 - 28945U, // SQDMLALv4i16_indexed - 1553U, // SQDMLALv4i16_v4i32 - 27665U, // SQDMLALv4i32_indexed - 529U, // SQDMLALv4i32_v2i64 - 28945U, // SQDMLALv8i16_indexed - 785U, // SQDMLALv8i16_v4i32 - 65U, // SQDMLSLi16 - 65U, // SQDMLSLi32 - 28945U, // SQDMLSLv1i32_indexed - 27665U, // SQDMLSLv1i64_indexed - 27665U, // SQDMLSLv2i32_indexed - 1297U, // SQDMLSLv2i32_v2i64 - 28945U, // SQDMLSLv4i16_indexed - 1553U, // SQDMLSLv4i16_v4i32 - 27665U, // SQDMLSLv4i32_indexed - 529U, // SQDMLSLv4i32_v2i64 - 28945U, // SQDMLSLv8i16_indexed - 785U, // SQDMLSLv8i16_v4i32 - 1U, // SQDMULHv1i16 - 37129U, // SQDMULHv1i16_indexed - 1U, // SQDMULHv1i32 - 35849U, // SQDMULHv1i32_indexed - 1289U, // SQDMULHv2i32 - 35849U, // SQDMULHv2i32_indexed - 1545U, // SQDMULHv4i16 - 37129U, // SQDMULHv4i16_indexed - 521U, // SQDMULHv4i32 - 35849U, // SQDMULHv4i32_indexed - 777U, // SQDMULHv8i16 - 37129U, // SQDMULHv8i16_indexed - 1U, // SQDMULLi16 - 1U, // SQDMULLi32 - 37129U, // SQDMULLv1i32_indexed - 35849U, // SQDMULLv1i64_indexed - 35849U, // SQDMULLv2i32_indexed - 1289U, // SQDMULLv2i32_v2i64 - 37129U, // SQDMULLv4i16_indexed - 1545U, // SQDMULLv4i16_v4i32 - 35849U, // SQDMULLv4i32_indexed - 521U, // SQDMULLv4i32_v2i64 - 37129U, // SQDMULLv8i16_indexed - 777U, // SQDMULLv8i16_v4i32 - 0U, // SQNEGv16i8 - 0U, // SQNEGv1i16 - 0U, // SQNEGv1i32 - 0U, // SQNEGv1i64 - 0U, // SQNEGv1i8 - 0U, // SQNEGv2i32 - 0U, // SQNEGv2i64 - 0U, // SQNEGv4i16 - 0U, // SQNEGv4i32 - 0U, // SQNEGv8i16 - 0U, // SQNEGv8i8 - 1U, // SQRDMULHv1i16 - 37129U, // SQRDMULHv1i16_indexed - 1U, // SQRDMULHv1i32 - 35849U, // SQRDMULHv1i32_indexed - 1289U, // SQRDMULHv2i32 - 35849U, // SQRDMULHv2i32_indexed - 1545U, // SQRDMULHv4i16 - 37129U, // SQRDMULHv4i16_indexed - 521U, // SQRDMULHv4i32 - 35849U, // SQRDMULHv4i32_indexed - 777U, // SQRDMULHv8i16 - 37129U, // SQRDMULHv8i16_indexed - 1033U, // SQRSHLv16i8 - 1U, // SQRSHLv1i16 - 1U, // SQRSHLv1i32 - 1U, // SQRSHLv1i64 - 1U, // SQRSHLv1i8 - 1289U, // SQRSHLv2i32 - 265U, // SQRSHLv2i64 - 1545U, // SQRSHLv4i16 - 521U, // SQRSHLv4i32 - 777U, // SQRSHLv8i16 - 1801U, // SQRSHLv8i8 - 1U, // SQRSHRNb - 1U, // SQRSHRNh - 1U, // SQRSHRNs - 65U, // SQRSHRNv16i8_shift - 1U, // SQRSHRNv2i32_shift - 1U, // SQRSHRNv4i16_shift - 65U, // SQRSHRNv4i32_shift - 65U, // SQRSHRNv8i16_shift - 1U, // SQRSHRNv8i8_shift - 1U, // SQRSHRUNb - 1U, // SQRSHRUNh - 1U, // SQRSHRUNs - 65U, // SQRSHRUNv16i8_shift - 1U, // SQRSHRUNv2i32_shift - 1U, // SQRSHRUNv4i16_shift - 65U, // SQRSHRUNv4i32_shift - 65U, // SQRSHRUNv8i16_shift - 1U, // SQRSHRUNv8i8_shift - 1U, // SQSHLUb - 1U, // SQSHLUd - 1U, // SQSHLUh - 1U, // SQSHLUs - 1U, // SQSHLUv16i8_shift - 1U, // SQSHLUv2i32_shift - 1U, // SQSHLUv2i64_shift - 1U, // SQSHLUv4i16_shift - 1U, // SQSHLUv4i32_shift - 1U, // SQSHLUv8i16_shift - 1U, // SQSHLUv8i8_shift - 1U, // SQSHLb - 1U, // SQSHLd - 1U, // SQSHLh - 1U, // SQSHLs - 1033U, // SQSHLv16i8 - 1U, // SQSHLv16i8_shift - 1U, // SQSHLv1i16 - 1U, // SQSHLv1i32 - 1U, // SQSHLv1i64 - 1U, // SQSHLv1i8 - 1289U, // SQSHLv2i32 - 1U, // SQSHLv2i32_shift - 265U, // SQSHLv2i64 - 1U, // SQSHLv2i64_shift - 1545U, // SQSHLv4i16 - 1U, // SQSHLv4i16_shift - 521U, // SQSHLv4i32 - 1U, // SQSHLv4i32_shift - 777U, // SQSHLv8i16 - 1U, // SQSHLv8i16_shift - 1801U, // SQSHLv8i8 - 1U, // SQSHLv8i8_shift - 1U, // SQSHRNb - 1U, // SQSHRNh - 1U, // SQSHRNs - 65U, // SQSHRNv16i8_shift - 1U, // SQSHRNv2i32_shift - 1U, // SQSHRNv4i16_shift - 65U, // SQSHRNv4i32_shift - 65U, // SQSHRNv8i16_shift - 1U, // SQSHRNv8i8_shift - 1U, // SQSHRUNb - 1U, // SQSHRUNh - 1U, // SQSHRUNs - 65U, // SQSHRUNv16i8_shift - 1U, // SQSHRUNv2i32_shift - 1U, // SQSHRUNv4i16_shift - 65U, // SQSHRUNv4i32_shift - 65U, // SQSHRUNv8i16_shift - 1U, // SQSHRUNv8i8_shift - 1033U, // SQSUBv16i8 - 1U, // SQSUBv1i16 - 1U, // SQSUBv1i32 - 1U, // SQSUBv1i64 - 1U, // SQSUBv1i8 - 1289U, // SQSUBv2i32 - 265U, // SQSUBv2i64 - 1545U, // SQSUBv4i16 - 521U, // SQSUBv4i32 - 777U, // SQSUBv8i16 - 1801U, // SQSUBv8i8 - 0U, // SQXTNv16i8 - 0U, // SQXTNv1i16 - 0U, // SQXTNv1i32 - 0U, // SQXTNv1i8 - 0U, // SQXTNv2i32 - 0U, // SQXTNv4i16 - 0U, // SQXTNv4i32 - 0U, // SQXTNv8i16 - 0U, // SQXTNv8i8 - 0U, // SQXTUNv16i8 - 0U, // SQXTUNv1i16 - 0U, // SQXTUNv1i32 - 0U, // SQXTUNv1i8 - 0U, // SQXTUNv2i32 - 0U, // SQXTUNv4i16 - 0U, // SQXTUNv4i32 - 0U, // SQXTUNv8i16 - 0U, // SQXTUNv8i8 - 1033U, // SRHADDv16i8 - 1289U, // SRHADDv2i32 - 1545U, // SRHADDv4i16 - 521U, // SRHADDv4i32 - 777U, // SRHADDv8i16 - 1801U, // SRHADDv8i8 - 65U, // SRId - 65U, // SRIv16i8_shift - 65U, // SRIv2i32_shift - 65U, // SRIv2i64_shift - 65U, // SRIv4i16_shift - 65U, // SRIv4i32_shift - 65U, // SRIv8i16_shift - 65U, // SRIv8i8_shift - 1033U, // SRSHLv16i8 - 1U, // SRSHLv1i64 - 1289U, // SRSHLv2i32 - 265U, // SRSHLv2i64 - 1545U, // SRSHLv4i16 - 521U, // SRSHLv4i32 - 777U, // SRSHLv8i16 - 1801U, // SRSHLv8i8 - 1U, // SRSHRd - 1U, // SRSHRv16i8_shift - 1U, // SRSHRv2i32_shift - 1U, // SRSHRv2i64_shift - 1U, // SRSHRv4i16_shift - 1U, // SRSHRv4i32_shift - 1U, // SRSHRv8i16_shift - 1U, // SRSHRv8i8_shift - 65U, // SRSRAd - 65U, // SRSRAv16i8_shift - 65U, // SRSRAv2i32_shift - 65U, // SRSRAv2i64_shift - 65U, // SRSRAv4i16_shift - 65U, // SRSRAv4i32_shift - 65U, // SRSRAv8i16_shift - 65U, // SRSRAv8i8_shift - 1U, // SSHLLv16i8_shift - 1U, // SSHLLv2i32_shift - 1U, // SSHLLv4i16_shift - 1U, // SSHLLv4i32_shift - 1U, // SSHLLv8i16_shift - 1U, // SSHLLv8i8_shift - 1033U, // SSHLv16i8 - 1U, // SSHLv1i64 - 1289U, // SSHLv2i32 - 265U, // SSHLv2i64 - 1545U, // SSHLv4i16 - 521U, // SSHLv4i32 - 777U, // SSHLv8i16 - 1801U, // SSHLv8i8 - 1U, // SSHRd - 1U, // SSHRv16i8_shift - 1U, // SSHRv2i32_shift - 1U, // SSHRv2i64_shift - 1U, // SSHRv4i16_shift - 1U, // SSHRv4i32_shift - 1U, // SSHRv8i16_shift - 1U, // SSHRv8i8_shift - 65U, // SSRAd - 65U, // SSRAv16i8_shift - 65U, // SSRAv2i32_shift - 65U, // SSRAv2i64_shift - 65U, // SSRAv4i16_shift - 65U, // SSRAv4i32_shift - 65U, // SSRAv8i16_shift - 65U, // SSRAv8i8_shift - 1033U, // SSUBLv16i8_v8i16 - 1289U, // SSUBLv2i32_v2i64 - 1545U, // SSUBLv4i16_v4i32 - 521U, // SSUBLv4i32_v2i64 - 777U, // SSUBLv8i16_v4i32 - 1801U, // SSUBLv8i8_v8i16 - 1033U, // SSUBWv16i8_v8i16 - 1289U, // SSUBWv2i32_v2i64 - 1545U, // SSUBWv4i16_v4i32 - 521U, // SSUBWv4i32_v2i64 - 777U, // SSUBWv8i16_v4i32 - 1801U, // SSUBWv8i8_v8i16 + 33095U, // SMINPv16i8 + 41287U, // SMINPv2i32 + 49480U, // SMINPv4i16 + 16710U, // SMINPv4i32 + 24902U, // SMINPv8i16 + 57672U, // SMINPv8i8 + 837U, // SMINV_VPZ_B + 901U, // SMINV_VPZ_D + 2245U, // SMINV_VPZ_H + 1029U, // SMINV_VPZ_S + 1U, // SMINVv16i8v + 3U, // SMINVv4i16v + 3U, // SMINVv4i32v + 4U, // SMINVv8i16v + 4U, // SMINVv8i8v + 261U, // SMIN_ZI_B + 261U, // SMIN_ZI_D + 11U, // SMIN_ZI_H + 261U, // SMIN_ZI_S + 74560U, // SMIN_ZPmZ_B + 598912U, // SMIN_ZPmZ_D + 1131465U, // SMIN_ZPmZ_H + 1647616U, // SMIN_ZPmZ_S + 33095U, // SMINv16i8 + 41287U, // SMINv2i32 + 49480U, // SMINv4i16 + 16710U, // SMINv4i32 + 24902U, // SMINv8i16 + 57672U, // SMINv8i8 + 33159U, // SMLALv16i8_v8i16 + 9126279U, // SMLALv2i32_indexed + 41351U, // SMLALv2i32_v2i64 + 9118088U, // SMLALv4i16_indexed + 49544U, // SMLALv4i16_v4i32 + 9126278U, // SMLALv4i32_indexed + 16774U, // SMLALv4i32_v2i64 + 9118086U, // SMLALv8i16_indexed + 24966U, // SMLALv8i16_v4i32 + 57736U, // SMLALv8i8_v8i16 + 33159U, // SMLSLv16i8_v8i16 + 9126279U, // SMLSLv2i32_indexed + 41351U, // SMLSLv2i32_v2i64 + 9118088U, // SMLSLv4i16_indexed + 49544U, // SMLSLv4i16_v4i32 + 9126278U, // SMLSLv4i32_indexed + 16774U, // SMLSLv4i32_v2i64 + 9118086U, // SMLSLv8i16_indexed + 24966U, // SMLSLv8i16_v4i32 + 57736U, // SMLSLv8i8_v8i16 + 2770U, // SMOVvi16to32 + 2770U, // SMOVvi16to64 + 2770U, // SMOVvi32to64 + 2771U, // SMOVvi8to32 + 2771U, // SMOVvi8to64 + 2171141U, // SMSUBLrrr + 74560U, // SMULH_ZPmZ_B + 598912U, // SMULH_ZPmZ_D + 1131465U, // SMULH_ZPmZ_H + 1647616U, // SMULH_ZPmZ_S + 261U, // SMULHrr + 33095U, // SMULLv16i8_v8i16 + 10174791U, // SMULLv2i32_indexed + 41287U, // SMULLv2i32_v2i64 + 10166600U, // SMULLv4i16_indexed + 49480U, // SMULLv4i16_v4i32 + 10174790U, // SMULLv4i32_indexed + 16710U, // SMULLv4i32_v2i64 + 10166598U, // SMULLv8i16_indexed + 24902U, // SMULLv8i16_v4i32 + 57672U, // SMULLv8i8_v8i16 + 74565U, // SPLICE_ZPZ_B + 598917U, // SPLICE_ZPZ_D + 1131465U, // SPLICE_ZPZ_H + 1647621U, // SPLICE_ZPZ_S + 1U, // SQABSv16i8 + 1U, // SQABSv1i16 + 1U, // SQABSv1i32 + 1U, // SQABSv1i64 + 1U, // SQABSv1i8 + 2U, // SQABSv2i32 + 2U, // SQABSv2i64 + 3U, // SQABSv4i16 + 3U, // SQABSv4i32 + 4U, // SQABSv8i16 + 4U, // SQABSv8i8 + 645U, // SQADD_ZI_B + 709U, // SQADD_ZI_D + 9U, // SQADD_ZI_H + 773U, // SQADD_ZI_S + 837U, // SQADD_ZZZ_B + 901U, // SQADD_ZZZ_D + 137U, // SQADD_ZZZ_H + 1029U, // SQADD_ZZZ_S + 33095U, // SQADDv16i8 + 261U, // SQADDv1i16 + 261U, // SQADDv1i32 + 261U, // SQADDv1i64 + 261U, // SQADDv1i8 + 41287U, // SQADDv2i32 + 8517U, // SQADDv2i64 + 49480U, // SQADDv4i16 + 16710U, // SQADDv4i32 + 24902U, // SQADDv8i16 + 57672U, // SQADDv8i8 + 0U, // SQDECB_XPiI + 0U, // SQDECB_XPiWdI + 0U, // SQDECD_XPiI + 0U, // SQDECD_XPiWdI + 0U, // SQDECD_ZPiI + 0U, // SQDECH_XPiI + 0U, // SQDECH_XPiWdI + 0U, // SQDECH_ZPiI + 5381U, // SQDECP_XPWd_B + 5381U, // SQDECP_XPWd_D + 5381U, // SQDECP_XPWd_H + 5381U, // SQDECP_XPWd_S + 1U, // SQDECP_XP_B + 1U, // SQDECP_XP_D + 1U, // SQDECP_XP_H + 1U, // SQDECP_XP_S + 1U, // SQDECP_ZP_D + 0U, // SQDECP_ZP_H + 1U, // SQDECP_ZP_S + 0U, // SQDECW_XPiI + 0U, // SQDECW_XPiWdI + 0U, // SQDECW_ZPiI + 2309U, // SQDMLALi16 + 2309U, // SQDMLALi32 + 9118085U, // SQDMLALv1i32_indexed + 9126277U, // SQDMLALv1i64_indexed + 9126279U, // SQDMLALv2i32_indexed + 41351U, // SQDMLALv2i32_v2i64 + 9118088U, // SQDMLALv4i16_indexed + 49544U, // SQDMLALv4i16_v4i32 + 9126278U, // SQDMLALv4i32_indexed + 16774U, // SQDMLALv4i32_v2i64 + 9118086U, // SQDMLALv8i16_indexed + 24966U, // SQDMLALv8i16_v4i32 + 2309U, // SQDMLSLi16 + 2309U, // SQDMLSLi32 + 9118085U, // SQDMLSLv1i32_indexed + 9126277U, // SQDMLSLv1i64_indexed + 9126279U, // SQDMLSLv2i32_indexed + 41351U, // SQDMLSLv2i32_v2i64 + 9118088U, // SQDMLSLv4i16_indexed + 49544U, // SQDMLSLv4i16_v4i32 + 9126278U, // SQDMLSLv4i32_indexed + 16774U, // SQDMLSLv4i32_v2i64 + 9118086U, // SQDMLSLv8i16_indexed + 24966U, // SQDMLSLv8i16_v4i32 + 261U, // SQDMULHv1i16 + 10166597U, // SQDMULHv1i16_indexed + 261U, // SQDMULHv1i32 + 10174789U, // SQDMULHv1i32_indexed + 41287U, // SQDMULHv2i32 + 10174791U, // SQDMULHv2i32_indexed + 49480U, // SQDMULHv4i16 + 10166600U, // SQDMULHv4i16_indexed + 16710U, // SQDMULHv4i32 + 10174790U, // SQDMULHv4i32_indexed + 24902U, // SQDMULHv8i16 + 10166598U, // SQDMULHv8i16_indexed + 261U, // SQDMULLi16 + 261U, // SQDMULLi32 + 10166597U, // SQDMULLv1i32_indexed + 10174789U, // SQDMULLv1i64_indexed + 10174791U, // SQDMULLv2i32_indexed + 41287U, // SQDMULLv2i32_v2i64 + 10166600U, // SQDMULLv4i16_indexed + 49480U, // SQDMULLv4i16_v4i32 + 10174790U, // SQDMULLv4i32_indexed + 16710U, // SQDMULLv4i32_v2i64 + 10166598U, // SQDMULLv8i16_indexed + 24902U, // SQDMULLv8i16_v4i32 + 0U, // SQINCB_XPiI + 0U, // SQINCB_XPiWdI + 0U, // SQINCD_XPiI + 0U, // SQINCD_XPiWdI + 0U, // SQINCD_ZPiI + 0U, // SQINCH_XPiI + 0U, // SQINCH_XPiWdI + 0U, // SQINCH_ZPiI + 5381U, // SQINCP_XPWd_B + 5381U, // SQINCP_XPWd_D + 5381U, // SQINCP_XPWd_H + 5381U, // SQINCP_XPWd_S + 1U, // SQINCP_XP_B + 1U, // SQINCP_XP_D + 1U, // SQINCP_XP_H + 1U, // SQINCP_XP_S + 1U, // SQINCP_ZP_D + 0U, // SQINCP_ZP_H + 1U, // SQINCP_ZP_S + 0U, // SQINCW_XPiI + 0U, // SQINCW_XPiWdI + 0U, // SQINCW_ZPiI + 1U, // SQNEGv16i8 + 1U, // SQNEGv1i16 + 1U, // SQNEGv1i32 + 1U, // SQNEGv1i64 + 1U, // SQNEGv1i8 + 2U, // SQNEGv2i32 + 2U, // SQNEGv2i64 + 3U, // SQNEGv4i16 + 3U, // SQNEGv4i32 + 4U, // SQNEGv8i16 + 4U, // SQNEGv8i8 + 9118085U, // SQRDMLAHi16_indexed + 9126277U, // SQRDMLAHi32_indexed + 2309U, // SQRDMLAHv1i16 + 2309U, // SQRDMLAHv1i32 + 41351U, // SQRDMLAHv2i32 + 9126279U, // SQRDMLAHv2i32_indexed + 49544U, // SQRDMLAHv4i16 + 9118088U, // SQRDMLAHv4i16_indexed + 16774U, // SQRDMLAHv4i32 + 9126278U, // SQRDMLAHv4i32_indexed + 24966U, // SQRDMLAHv8i16 + 9118086U, // SQRDMLAHv8i16_indexed + 9118085U, // SQRDMLSHi16_indexed + 9126277U, // SQRDMLSHi32_indexed + 2309U, // SQRDMLSHv1i16 + 2309U, // SQRDMLSHv1i32 + 41351U, // SQRDMLSHv2i32 + 9126279U, // SQRDMLSHv2i32_indexed + 49544U, // SQRDMLSHv4i16 + 9118088U, // SQRDMLSHv4i16_indexed + 16774U, // SQRDMLSHv4i32 + 9126278U, // SQRDMLSHv4i32_indexed + 24966U, // SQRDMLSHv8i16 + 9118086U, // SQRDMLSHv8i16_indexed + 261U, // SQRDMULHv1i16 + 10166597U, // SQRDMULHv1i16_indexed + 261U, // SQRDMULHv1i32 + 10174789U, // SQRDMULHv1i32_indexed + 41287U, // SQRDMULHv2i32 + 10174791U, // SQRDMULHv2i32_indexed + 49480U, // SQRDMULHv4i16 + 10166600U, // SQRDMULHv4i16_indexed + 16710U, // SQRDMULHv4i32 + 10174790U, // SQRDMULHv4i32_indexed + 24902U, // SQRDMULHv8i16 + 10166598U, // SQRDMULHv8i16_indexed + 33095U, // SQRSHLv16i8 + 261U, // SQRSHLv1i16 + 261U, // SQRSHLv1i32 + 261U, // SQRSHLv1i64 + 261U, // SQRSHLv1i8 + 41287U, // SQRSHLv2i32 + 8517U, // SQRSHLv2i64 + 49480U, // SQRSHLv4i16 + 16710U, // SQRSHLv4i32 + 24902U, // SQRSHLv8i16 + 57672U, // SQRSHLv8i8 + 261U, // SQRSHRNb + 261U, // SQRSHRNh + 261U, // SQRSHRNs + 2310U, // SQRSHRNv16i8_shift + 261U, // SQRSHRNv2i32_shift + 262U, // SQRSHRNv4i16_shift + 2309U, // SQRSHRNv4i32_shift + 2310U, // SQRSHRNv8i16_shift + 262U, // SQRSHRNv8i8_shift + 261U, // SQRSHRUNb + 261U, // SQRSHRUNh + 261U, // SQRSHRUNs + 2310U, // SQRSHRUNv16i8_shift + 261U, // SQRSHRUNv2i32_shift + 262U, // SQRSHRUNv4i16_shift + 2309U, // SQRSHRUNv4i32_shift + 2310U, // SQRSHRUNv8i16_shift + 262U, // SQRSHRUNv8i8_shift + 261U, // SQSHLUb + 261U, // SQSHLUd + 261U, // SQSHLUh + 261U, // SQSHLUs + 263U, // SQSHLUv16i8_shift + 263U, // SQSHLUv2i32_shift + 261U, // SQSHLUv2i64_shift + 264U, // SQSHLUv4i16_shift + 262U, // SQSHLUv4i32_shift + 262U, // SQSHLUv8i16_shift + 264U, // SQSHLUv8i8_shift + 261U, // SQSHLb + 261U, // SQSHLd + 261U, // SQSHLh + 261U, // SQSHLs + 33095U, // SQSHLv16i8 + 263U, // SQSHLv16i8_shift + 261U, // SQSHLv1i16 + 261U, // SQSHLv1i32 + 261U, // SQSHLv1i64 + 261U, // SQSHLv1i8 + 41287U, // SQSHLv2i32 + 263U, // SQSHLv2i32_shift + 8517U, // SQSHLv2i64 + 261U, // SQSHLv2i64_shift + 49480U, // SQSHLv4i16 + 264U, // SQSHLv4i16_shift + 16710U, // SQSHLv4i32 + 262U, // SQSHLv4i32_shift + 24902U, // SQSHLv8i16 + 262U, // SQSHLv8i16_shift + 57672U, // SQSHLv8i8 + 264U, // SQSHLv8i8_shift + 261U, // SQSHRNb + 261U, // SQSHRNh + 261U, // SQSHRNs + 2310U, // SQSHRNv16i8_shift + 261U, // SQSHRNv2i32_shift + 262U, // SQSHRNv4i16_shift + 2309U, // SQSHRNv4i32_shift + 2310U, // SQSHRNv8i16_shift + 262U, // SQSHRNv8i8_shift + 261U, // SQSHRUNb + 261U, // SQSHRUNh + 261U, // SQSHRUNs + 2310U, // SQSHRUNv16i8_shift + 261U, // SQSHRUNv2i32_shift + 262U, // SQSHRUNv4i16_shift + 2309U, // SQSHRUNv4i32_shift + 2310U, // SQSHRUNv8i16_shift + 262U, // SQSHRUNv8i8_shift + 645U, // SQSUB_ZI_B + 709U, // SQSUB_ZI_D + 9U, // SQSUB_ZI_H + 773U, // SQSUB_ZI_S + 837U, // SQSUB_ZZZ_B + 901U, // SQSUB_ZZZ_D + 137U, // SQSUB_ZZZ_H + 1029U, // SQSUB_ZZZ_S + 33095U, // SQSUBv16i8 + 261U, // SQSUBv1i16 + 261U, // SQSUBv1i32 + 261U, // SQSUBv1i64 + 261U, // SQSUBv1i8 + 41287U, // SQSUBv2i32 + 8517U, // SQSUBv2i64 + 49480U, // SQSUBv4i16 + 16710U, // SQSUBv4i32 + 24902U, // SQSUBv8i16 + 57672U, // SQSUBv8i8 + 4U, // SQXTNv16i8 + 1U, // SQXTNv1i16 + 1U, // SQXTNv1i32 + 1U, // SQXTNv1i8 + 2U, // SQXTNv2i32 + 3U, // SQXTNv4i16 + 2U, // SQXTNv4i32 + 3U, // SQXTNv8i16 + 4U, // SQXTNv8i8 + 4U, // SQXTUNv16i8 + 1U, // SQXTUNv1i16 + 1U, // SQXTUNv1i32 + 1U, // SQXTUNv1i8 + 2U, // SQXTUNv2i32 + 3U, // SQXTUNv4i16 + 2U, // SQXTUNv4i32 + 3U, // SQXTUNv8i16 + 4U, // SQXTUNv8i8 + 33095U, // SRHADDv16i8 + 41287U, // SRHADDv2i32 + 49480U, // SRHADDv4i16 + 16710U, // SRHADDv4i32 + 24902U, // SRHADDv8i16 + 57672U, // SRHADDv8i8 + 2309U, // SRId + 2311U, // SRIv16i8_shift + 2311U, // SRIv2i32_shift + 2309U, // SRIv2i64_shift + 2312U, // SRIv4i16_shift + 2310U, // SRIv4i32_shift + 2310U, // SRIv8i16_shift + 2312U, // SRIv8i8_shift + 33095U, // SRSHLv16i8 + 261U, // SRSHLv1i64 + 41287U, // SRSHLv2i32 + 8517U, // SRSHLv2i64 + 49480U, // SRSHLv4i16 + 16710U, // SRSHLv4i32 + 24902U, // SRSHLv8i16 + 57672U, // SRSHLv8i8 + 261U, // SRSHRd + 263U, // SRSHRv16i8_shift + 263U, // SRSHRv2i32_shift + 261U, // SRSHRv2i64_shift + 264U, // SRSHRv4i16_shift + 262U, // SRSHRv4i32_shift + 262U, // SRSHRv8i16_shift + 264U, // SRSHRv8i8_shift + 2309U, // SRSRAd + 2311U, // SRSRAv16i8_shift + 2311U, // SRSRAv2i32_shift + 2309U, // SRSRAv2i64_shift + 2312U, // SRSRAv4i16_shift + 2310U, // SRSRAv4i32_shift + 2310U, // SRSRAv8i16_shift + 2312U, // SRSRAv8i8_shift + 263U, // SSHLLv16i8_shift + 263U, // SSHLLv2i32_shift + 264U, // SSHLLv4i16_shift + 262U, // SSHLLv4i32_shift + 262U, // SSHLLv8i16_shift + 264U, // SSHLLv8i8_shift + 33095U, // SSHLv16i8 + 261U, // SSHLv1i64 + 41287U, // SSHLv2i32 + 8517U, // SSHLv2i64 + 49480U, // SSHLv4i16 + 16710U, // SSHLv4i32 + 24902U, // SSHLv8i16 + 57672U, // SSHLv8i8 + 261U, // SSHRd + 263U, // SSHRv16i8_shift + 263U, // SSHRv2i32_shift + 261U, // SSHRv2i64_shift + 264U, // SSHRv4i16_shift + 262U, // SSHRv4i32_shift + 262U, // SSHRv8i16_shift + 264U, // SSHRv8i8_shift + 2309U, // SSRAd + 2311U, // SSRAv16i8_shift + 2311U, // SSRAv2i32_shift + 2309U, // SSRAv2i64_shift + 2312U, // SSRAv4i16_shift + 2310U, // SSRAv4i32_shift + 2310U, // SSRAv8i16_shift + 2312U, // SSRAv8i8_shift + 3205U, // SST1B_D + 3153U, // SST1B_D_IMM + 3269U, // SST1B_D_SXTW + 3333U, // SST1B_D_UXTW + 3153U, // SST1B_S_IMM + 3397U, // SST1B_S_SXTW + 3461U, // SST1B_S_UXTW + 3205U, // SST1D + 26U, // SST1D_IMM + 3525U, // SST1D_SCALED + 3269U, // SST1D_SXTW + 3589U, // SST1D_SXTW_SCALED + 3333U, // SST1D_UXTW + 3653U, // SST1D_UXTW_SCALED + 3205U, // SST1H_D + 26U, // SST1H_D_IMM + 3717U, // SST1H_D_SCALED + 3269U, // SST1H_D_SXTW + 3781U, // SST1H_D_SXTW_SCALED + 3333U, // SST1H_D_UXTW + 3845U, // SST1H_D_UXTW_SCALED + 26U, // SST1H_S_IMM + 3397U, // SST1H_S_SXTW + 3909U, // SST1H_S_SXTW_SCALED + 3461U, // SST1H_S_UXTW + 3973U, // SST1H_S_UXTW_SCALED + 3205U, // SST1W_D + 27U, // SST1W_D_IMM + 4037U, // SST1W_D_SCALED + 3269U, // SST1W_D_SXTW + 4101U, // SST1W_D_SXTW_SCALED + 3333U, // SST1W_D_UXTW + 4165U, // SST1W_D_UXTW_SCALED + 27U, // SST1W_IMM + 3397U, // SST1W_SXTW + 4229U, // SST1W_SXTW_SCALED + 3461U, // SST1W_UXTW + 4293U, // SST1W_UXTW_SCALED + 33095U, // SSUBLv16i8_v8i16 + 41287U, // SSUBLv2i32_v2i64 + 49480U, // SSUBLv4i16_v4i32 + 16710U, // SSUBLv4i32_v2i64 + 24902U, // SSUBLv8i16_v4i32 + 57672U, // SSUBLv8i8_v8i16 + 33094U, // SSUBWv16i8_v8i16 + 41285U, // SSUBWv2i32_v2i64 + 49478U, // SSUBWv4i16_v4i32 + 16709U, // SSUBWv4i32_v2i64 + 24902U, // SSUBWv8i16_v4i32 + 57670U, // SSUBWv8i8_v8i16 + 4357U, // ST1B + 4357U, // ST1B_D + 256261U, // ST1B_D_IMM + 4357U, // ST1B_H + 256261U, // ST1B_H_IMM + 256261U, // ST1B_IMM + 4357U, // ST1B_S + 256261U, // ST1B_S_IMM + 4421U, // ST1D + 256261U, // ST1D_IMM 0U, // ST1Fourv16b 0U, // ST1Fourv16b_POST 0U, // ST1Fourv1d @@ -4135,6 +8861,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST1Fourv8b_POST 0U, // ST1Fourv8h 0U, // ST1Fourv8h_POST + 4485U, // ST1H + 4485U, // ST1H_D + 256261U, // ST1H_D_IMM + 256261U, // ST1H_IMM + 4485U, // ST1H_S + 256261U, // ST1H_S_IMM 0U, // ST1Onev16b 0U, // ST1Onev16b_POST 0U, // ST1Onev1d @@ -4183,6 +8915,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST1Twov8b_POST 0U, // ST1Twov8h 0U, // ST1Twov8h_POST + 4741U, // ST1W + 4741U, // ST1W_D + 256261U, // ST1W_D_IMM + 256261U, // ST1W_IMM 0U, // ST1i16 0U, // ST1i16_POST 0U, // ST1i32 @@ -4191,6 +8927,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST1i64_POST 0U, // ST1i8 0U, // ST1i8_POST + 4357U, // ST2B + 258565U, // ST2B_IMM + 4421U, // ST2D + 258565U, // ST2D_IMM + 4485U, // ST2H + 258565U, // ST2H_IMM 0U, // ST2Twov16b 0U, // ST2Twov16b_POST 0U, // ST2Twov2d @@ -4205,6 +8947,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST2Twov8b_POST 0U, // ST2Twov8h 0U, // ST2Twov8h_POST + 4741U, // ST2W + 258565U, // ST2W_IMM 0U, // ST2i16 0U, // ST2i16_POST 0U, // ST2i32 @@ -4213,6 +8957,12 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST2i64_POST 0U, // ST2i8 0U, // ST2i8_POST + 4357U, // ST3B + 4869U, // ST3B_IMM + 4421U, // ST3D + 4869U, // ST3D_IMM + 4485U, // ST3H + 4869U, // ST3H_IMM 0U, // ST3Threev16b 0U, // ST3Threev16b_POST 0U, // ST3Threev2d @@ -4227,6 +8977,8 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST3Threev8b_POST 0U, // ST3Threev8h 0U, // ST3Threev8h_POST + 4741U, // ST3W + 4869U, // ST3W_IMM 0U, // ST3i16 0U, // ST3i16_POST 0U, // ST3i32 @@ -4235,6 +8987,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST3i64_POST 0U, // ST3i8 0U, // ST3i8_POST + 4357U, // ST4B + 258757U, // ST4B_IMM + 4421U, // ST4D + 258757U, // ST4D_IMM 0U, // ST4Fourv16b 0U, // ST4Fourv16b_POST 0U, // ST4Fourv2d @@ -4249,6 +9005,10 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST4Fourv8b_POST 0U, // ST4Fourv8h 0U, // ST4Fourv8h_POST + 4485U, // ST4H + 258757U, // ST4H_IMM + 4741U, // ST4W + 258757U, // ST4W_IMM 0U, // ST4i16 0U, // ST4i16_POST 0U, // ST4i32 @@ -4257,2842 +9017,3466 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) 0U, // ST4i64_POST 0U, // ST4i8 0U, // ST4i8_POST - 4U, // STLRB - 4U, // STLRH - 4U, // STLRW - 4U, // STLRX - 4609U, // STLXPW - 4609U, // STLXPX - 3588U, // STLXRB - 3588U, // STLXRH - 3588U, // STLXRW - 3588U, // STLXRX - 43268U, // STNPDi - 51460U, // STNPQi - 59652U, // STNPSi - 59652U, // STNPWi - 43268U, // STNPXi - 43268U, // STPDi - 69444U, // STPDpost - 330052U, // STPDpre - 51460U, // STPQi - 77636U, // STPQpost - 338244U, // STPQpre - 59652U, // STPSi - 85828U, // STPSpost - 346436U, // STPSpre - 59652U, // STPWi - 85828U, // STPWpost - 346436U, // STPWpre - 43268U, // STPXi - 69444U, // STPXpost - 330052U, // STPXpre - 4U, // STRBBpost - 4161U, // STRBBpre - 92417U, // STRBBroW - 100609U, // STRBBroX - 89U, // STRBBui - 4U, // STRBpost - 4161U, // STRBpre - 92417U, // STRBroW - 100609U, // STRBroX - 89U, // STRBui - 4U, // STRDpost - 4161U, // STRDpre - 108801U, // STRDroW - 116993U, // STRDroX - 97U, // STRDui - 4U, // STRHHpost - 4161U, // STRHHpre - 125185U, // STRHHroW - 133377U, // STRHHroX - 105U, // STRHHui - 4U, // STRHpost - 4161U, // STRHpre - 125185U, // STRHroW - 133377U, // STRHroX - 105U, // STRHui - 4U, // STRQpost - 4161U, // STRQpre - 141569U, // STRQroW - 149761U, // STRQroX - 113U, // STRQui - 4U, // STRSpost - 4161U, // STRSpre - 157953U, // STRSroW - 166145U, // STRSroX - 121U, // STRSui - 4U, // STRWpost - 4161U, // STRWpre - 157953U, // STRWroW - 166145U, // STRWroX - 121U, // STRWui - 4U, // STRXpost - 4161U, // STRXpre - 108801U, // STRXroW - 116993U, // STRXroX - 97U, // STRXui - 3585U, // STTRBi - 3585U, // STTRHi - 3585U, // STTRWi - 3585U, // STTRXi - 3585U, // STURBBi - 3585U, // STURBi - 3585U, // STURDi - 3585U, // STURHHi - 3585U, // STURHi - 3585U, // STURQi - 3585U, // STURSi - 3585U, // STURWi - 3585U, // STURXi - 4609U, // STXPW - 4609U, // STXPX - 3588U, // STXRB - 3588U, // STXRH - 3588U, // STXRW - 3588U, // STXRX - 265U, // SUBHNv2i64_v2i32 - 273U, // SUBHNv2i64_v4i32 - 521U, // SUBHNv4i32_v4i16 - 529U, // SUBHNv4i32_v8i16 - 785U, // SUBHNv8i16_v16i8 - 777U, // SUBHNv8i16_v8i8 - 25U, // SUBSWri + 27U, // STLLRB + 27U, // STLLRH + 27U, // STLLRW + 27U, // STLLRX + 27U, // STLRB + 27U, // STLRH + 27U, // STLRW + 27U, // STLRX + 114949U, // STLURBi + 114949U, // STLURHi + 114949U, // STLURWi + 114949U, // STLURXi + 286981U, // STLXPW + 286981U, // STLXPX + 114955U, // STLXRB + 114955U, // STLXRH + 114955U, // STLXRW + 114955U, // STLXRX + 11084043U, // STNPDi + 11608331U, // STNPQi + 12132619U, // STNPSi + 12132619U, // STNPWi + 11084043U, // STNPXi + 256261U, // STNT1B_ZRI + 4357U, // STNT1B_ZRR + 256261U, // STNT1D_ZRI + 4421U, // STNT1D_ZRR + 256261U, // STNT1H_ZRI + 4485U, // STNT1H_ZRR + 256261U, // STNT1W_ZRI + 4741U, // STNT1W_ZRR + 11084043U, // STPDi + 12847371U, // STPDpost + 180431115U, // STPDpre + 11608331U, // STPQi + 13371659U, // STPQpost + 180955403U, // STPQpre + 12132619U, // STPSi + 13895947U, // STPSpost + 181479691U, // STPSpre + 12132619U, // STPWi + 13895947U, // STPWpost + 181479691U, // STPWpre + 11084043U, // STPXi + 12847371U, // STPXpost + 180431115U, // STPXpre + 28U, // STRBBpost + 272645U, // STRBBpre + 14229765U, // STRBBroW + 14754053U, // STRBBroX + 4997U, // STRBBui + 28U, // STRBpost + 272645U, // STRBpre + 14229765U, // STRBroW + 14754053U, // STRBroX + 4997U, // STRBui + 28U, // STRDpost + 272645U, // STRDpre + 15278341U, // STRDroW + 15802629U, // STRDroX + 5061U, // STRDui + 28U, // STRHHpost + 272645U, // STRHHpre + 16326917U, // STRHHroW + 16851205U, // STRHHroX + 5125U, // STRHHui + 28U, // STRHpost + 272645U, // STRHpre + 16326917U, // STRHroW + 16851205U, // STRHroX + 5125U, // STRHui + 28U, // STRQpost + 272645U, // STRQpre + 17375493U, // STRQroW + 17899781U, // STRQroX + 5189U, // STRQui + 28U, // STRSpost + 272645U, // STRSpre + 18424069U, // STRSroW + 18948357U, // STRSroX + 5253U, // STRSui + 28U, // STRWpost + 272645U, // STRWpre + 18424069U, // STRWroW + 18948357U, // STRWroX + 5253U, // STRWui + 28U, // STRXpost + 272645U, // STRXpre + 15278341U, // STRXroW + 15802629U, // STRXroX + 5061U, // STRXui + 254213U, // STR_PXI + 254213U, // STR_ZXI + 114949U, // STTRBi + 114949U, // STTRHi + 114949U, // STTRWi + 114949U, // STTRXi + 114949U, // STURBBi + 114949U, // STURBi + 114949U, // STURDi + 114949U, // STURHHi + 114949U, // STURHi + 114949U, // STURQi + 114949U, // STURSi + 114949U, // STURWi + 114949U, // STURXi + 286981U, // STXPW + 286981U, // STXPX + 114955U, // STXRB + 114955U, // STXRH + 114955U, // STXRW + 114955U, // STXRX + 8517U, // SUBHNv2i64_v2i32 + 8581U, // SUBHNv2i64_v4i32 + 16710U, // SUBHNv4i32_v4i16 + 16774U, // SUBHNv4i32_v8i16 + 24966U, // SUBHNv8i16_v16i8 + 24902U, // SUBHNv8i16_v8i8 + 645U, // SUBR_ZI_B + 709U, // SUBR_ZI_D + 9U, // SUBR_ZI_H + 773U, // SUBR_ZI_S + 74560U, // SUBR_ZPmZ_B + 598912U, // SUBR_ZPmZ_D + 1131465U, // SUBR_ZPmZ_H + 1647616U, // SUBR_ZPmZ_S + 453U, // SUBSWri 0U, // SUBSWrr - 33U, // SUBSWrs - 41U, // SUBSWrx - 25U, // SUBSXri + 517U, // SUBSWrs + 581U, // SUBSWrx + 453U, // SUBSXri 0U, // SUBSXrr - 33U, // SUBSXrs - 41U, // SUBSXrx - 2049U, // SUBSXrx64 - 25U, // SUBWri + 517U, // SUBSXrs + 581U, // SUBSXrx + 65797U, // SUBSXrx64 + 453U, // SUBWri 0U, // SUBWrr - 33U, // SUBWrs - 41U, // SUBWrx - 25U, // SUBXri + 517U, // SUBWrs + 581U, // SUBWrx + 453U, // SUBXri 0U, // SUBXrr - 33U, // SUBXrs - 41U, // SUBXrx - 2049U, // SUBXrx64 - 1033U, // SUBv16i8 - 1U, // SUBv1i64 - 1289U, // SUBv2i32 - 265U, // SUBv2i64 - 1545U, // SUBv4i16 - 521U, // SUBv4i32 - 777U, // SUBv8i16 - 1801U, // SUBv8i8 - 0U, // SUQADDv16i8 - 0U, // SUQADDv1i16 - 0U, // SUQADDv1i32 - 0U, // SUQADDv1i64 - 0U, // SUQADDv1i8 - 0U, // SUQADDv2i32 - 0U, // SUQADDv2i64 - 0U, // SUQADDv4i16 - 0U, // SUQADDv4i32 - 0U, // SUQADDv8i16 - 0U, // SUQADDv8i8 + 517U, // SUBXrs + 581U, // SUBXrx + 65797U, // SUBXrx64 + 645U, // SUB_ZI_B + 709U, // SUB_ZI_D + 9U, // SUB_ZI_H + 773U, // SUB_ZI_S + 74560U, // SUB_ZPmZ_B + 598912U, // SUB_ZPmZ_D + 1131465U, // SUB_ZPmZ_H + 1647616U, // SUB_ZPmZ_S + 837U, // SUB_ZZZ_B + 901U, // SUB_ZZZ_D + 137U, // SUB_ZZZ_H + 1029U, // SUB_ZZZ_S + 33095U, // SUBv16i8 + 261U, // SUBv1i64 + 41287U, // SUBv2i32 + 8517U, // SUBv2i64 + 49480U, // SUBv4i16 + 16710U, // SUBv4i32 + 24902U, // SUBv8i16 + 57672U, // SUBv8i8 + 1U, // SUNPKHI_ZZ_D + 0U, // SUNPKHI_ZZ_H + 1U, // SUNPKHI_ZZ_S + 1U, // SUNPKLO_ZZ_D + 0U, // SUNPKLO_ZZ_H + 1U, // SUNPKLO_ZZ_S + 1U, // SUQADDv16i8 + 1U, // SUQADDv1i16 + 1U, // SUQADDv1i32 + 1U, // SUQADDv1i64 + 1U, // SUQADDv1i8 + 2U, // SUQADDv2i32 + 2U, // SUQADDv2i64 + 3U, // SUQADDv4i16 + 3U, // SUQADDv4i32 + 4U, // SUQADDv8i16 + 4U, // SUQADDv8i8 0U, // SVC - 129U, // SYSLxt + 0U, // SWPAB + 0U, // SWPAH + 0U, // SWPALB + 0U, // SWPALH + 0U, // SWPALW + 0U, // SWPALX + 0U, // SWPAW + 0U, // SWPAX + 0U, // SWPB + 0U, // SWPH + 0U, // SWPLB + 0U, // SWPLH + 0U, // SWPLW + 0U, // SWPLX + 0U, // SWPW + 0U, // SWPX + 64U, // SXTB_ZPmZ_D + 128U, // SXTB_ZPmZ_H + 192U, // SXTB_ZPmZ_S + 64U, // SXTH_ZPmZ_D + 192U, // SXTH_ZPmZ_S + 64U, // SXTW_ZPmZ_D + 5445U, // SYSLxt 0U, // SYSxt - 0U, // TBLv16i8Four - 0U, // TBLv16i8One - 0U, // TBLv16i8Three - 0U, // TBLv16i8Two - 0U, // TBLv8i8Four - 0U, // TBLv8i8One - 0U, // TBLv8i8Three - 0U, // TBLv8i8Two - 137U, // TBNZW - 137U, // TBNZX - 0U, // TBXv16i8Four - 0U, // TBXv16i8One - 0U, // TBXv16i8Three - 0U, // TBXv16i8Two - 0U, // TBXv8i8Four - 0U, // TBXv8i8One - 0U, // TBXv8i8Three - 0U, // TBXv8i8Two - 137U, // TBZW - 137U, // TBZX + 0U, // TBL_ZZZ_B + 0U, // TBL_ZZZ_D + 0U, // TBL_ZZZ_H + 0U, // TBL_ZZZ_S + 1U, // TBLv16i8Four + 1U, // TBLv16i8One + 1U, // TBLv16i8Three + 1U, // TBLv16i8Two + 4U, // TBLv8i8Four + 4U, // TBLv8i8One + 4U, // TBLv8i8Three + 4U, // TBLv8i8Two + 5509U, // TBNZW + 5509U, // TBNZX + 1U, // TBXv16i8Four + 1U, // TBXv16i8One + 1U, // TBXv16i8Three + 1U, // TBXv16i8Two + 4U, // TBXv8i8Four + 4U, // TBXv8i8One + 4U, // TBXv8i8Three + 4U, // TBXv8i8Two + 5509U, // TBZW + 5509U, // TBZX 0U, // TCRETURNdi 0U, // TCRETURNri 0U, // TLSDESCCALL - 0U, // TLSDESC_BLR - 1033U, // TRN1v16i8 - 1289U, // TRN1v2i32 - 265U, // TRN1v2i64 - 1545U, // TRN1v4i16 - 521U, // TRN1v4i32 - 777U, // TRN1v8i16 - 1801U, // TRN1v8i8 - 1033U, // TRN2v16i8 - 1289U, // TRN2v2i32 - 265U, // TRN2v2i64 - 1545U, // TRN2v4i16 - 521U, // TRN2v4i32 - 777U, // TRN2v8i16 - 1801U, // TRN2v8i8 - 1041U, // UABALv16i8_v8i16 - 1297U, // UABALv2i32_v2i64 - 1553U, // UABALv4i16_v4i32 - 529U, // UABALv4i32_v2i64 - 785U, // UABALv8i16_v4i32 - 1809U, // UABALv8i8_v8i16 - 1041U, // UABAv16i8 - 1297U, // UABAv2i32 - 1553U, // UABAv4i16 - 529U, // UABAv4i32 - 785U, // UABAv8i16 - 1809U, // UABAv8i8 - 1033U, // UABDLv16i8_v8i16 - 1289U, // UABDLv2i32_v2i64 - 1545U, // UABDLv4i16_v4i32 - 521U, // UABDLv4i32_v2i64 - 777U, // UABDLv8i16_v4i32 - 1801U, // UABDLv8i8_v8i16 - 1033U, // UABDv16i8 - 1289U, // UABDv2i32 - 1545U, // UABDv4i16 - 521U, // UABDv4i32 - 777U, // UABDv8i16 - 1801U, // UABDv8i8 - 0U, // UADALPv16i8_v8i16 - 0U, // UADALPv2i32_v1i64 - 0U, // UADALPv4i16_v2i32 - 0U, // UADALPv4i32_v2i64 - 0U, // UADALPv8i16_v4i32 - 0U, // UADALPv8i8_v4i16 - 0U, // UADDLPv16i8_v8i16 - 0U, // UADDLPv2i32_v1i64 - 0U, // UADDLPv4i16_v2i32 - 0U, // UADDLPv4i32_v2i64 - 0U, // UADDLPv8i16_v4i32 - 0U, // UADDLPv8i8_v4i16 - 0U, // UADDLVv16i8v - 0U, // UADDLVv4i16v - 0U, // UADDLVv4i32v - 0U, // UADDLVv8i16v - 0U, // UADDLVv8i8v - 1033U, // UADDLv16i8_v8i16 - 1289U, // UADDLv2i32_v2i64 - 1545U, // UADDLv4i16_v4i32 - 521U, // UADDLv4i32_v2i64 - 777U, // UADDLv8i16_v4i32 - 1801U, // UADDLv8i8_v8i16 - 1033U, // UADDWv16i8_v8i16 - 1289U, // UADDWv2i32_v2i64 - 1545U, // UADDWv4i16_v4i32 - 521U, // UADDWv4i32_v2i64 - 777U, // UADDWv8i16_v4i32 - 1801U, // UADDWv8i8_v8i16 - 18689U, // UBFMWri - 18689U, // UBFMXri - 1U, // UCVTFSWDri - 1U, // UCVTFSWSri - 1U, // UCVTFSXDri - 1U, // UCVTFSXSri - 0U, // UCVTFUWDri - 0U, // UCVTFUWSri - 0U, // UCVTFUXDri - 0U, // UCVTFUXSri - 1U, // UCVTFd - 1U, // UCVTFs - 0U, // UCVTFv1i32 - 0U, // UCVTFv1i64 - 0U, // UCVTFv2f32 - 0U, // UCVTFv2f64 - 1U, // UCVTFv2i32_shift - 1U, // UCVTFv2i64_shift - 0U, // UCVTFv4f32 - 1U, // UCVTFv4i32_shift - 1U, // UDIVWr - 1U, // UDIVXr - 1U, // UDIV_IntWr - 1U, // UDIV_IntXr - 1033U, // UHADDv16i8 - 1289U, // UHADDv2i32 - 1545U, // UHADDv4i16 - 521U, // UHADDv4i32 - 777U, // UHADDv8i16 - 1801U, // UHADDv8i8 - 1033U, // UHSUBv16i8 - 1289U, // UHSUBv2i32 - 1545U, // UHSUBv4i16 - 521U, // UHSUBv4i32 - 777U, // UHSUBv8i16 - 1801U, // UHSUBv8i8 - 18689U, // UMADDLrrr - 1033U, // UMAXPv16i8 - 1289U, // UMAXPv2i32 - 1545U, // UMAXPv4i16 - 521U, // UMAXPv4i32 - 777U, // UMAXPv8i16 - 1801U, // UMAXPv8i8 - 0U, // UMAXVv16i8v - 0U, // UMAXVv4i16v - 0U, // UMAXVv4i32v - 0U, // UMAXVv8i16v - 0U, // UMAXVv8i8v - 1033U, // UMAXv16i8 - 1289U, // UMAXv2i32 - 1545U, // UMAXv4i16 - 521U, // UMAXv4i32 - 777U, // UMAXv8i16 - 1801U, // UMAXv8i8 - 1033U, // UMINPv16i8 - 1289U, // UMINPv2i32 - 1545U, // UMINPv4i16 - 521U, // UMINPv4i32 - 777U, // UMINPv8i16 - 1801U, // UMINPv8i8 - 0U, // UMINVv16i8v - 0U, // UMINVv4i16v - 0U, // UMINVv4i32v - 0U, // UMINVv8i16v - 0U, // UMINVv8i8v - 1033U, // UMINv16i8 - 1289U, // UMINv2i32 - 1545U, // UMINv4i16 - 521U, // UMINv4i32 - 777U, // UMINv8i16 - 1801U, // UMINv8i8 - 1041U, // UMLALv16i8_v8i16 - 27665U, // UMLALv2i32_indexed - 1297U, // UMLALv2i32_v2i64 - 28945U, // UMLALv4i16_indexed - 1553U, // UMLALv4i16_v4i32 - 27665U, // UMLALv4i32_indexed - 529U, // UMLALv4i32_v2i64 - 28945U, // UMLALv8i16_indexed - 785U, // UMLALv8i16_v4i32 - 1809U, // UMLALv8i8_v8i16 - 1041U, // UMLSLv16i8_v8i16 - 27665U, // UMLSLv2i32_indexed - 1297U, // UMLSLv2i32_v2i64 - 28945U, // UMLSLv4i16_indexed - 1553U, // UMLSLv4i16_v4i32 - 27665U, // UMLSLv4i32_indexed - 529U, // UMLSLv4i32_v2i64 - 28945U, // UMLSLv8i16_indexed - 785U, // UMLSLv8i16_v4i32 - 1809U, // UMLSLv8i8_v8i16 - 75U, // UMOVvi16 - 75U, // UMOVvi32 - 75U, // UMOVvi64 - 75U, // UMOVvi8 - 18689U, // UMSUBLrrr - 1U, // UMULHrr - 1033U, // UMULLv16i8_v8i16 - 35849U, // UMULLv2i32_indexed - 1289U, // UMULLv2i32_v2i64 - 37129U, // UMULLv4i16_indexed - 1545U, // UMULLv4i16_v4i32 - 35849U, // UMULLv4i32_indexed - 521U, // UMULLv4i32_v2i64 - 37129U, // UMULLv8i16_indexed - 777U, // UMULLv8i16_v4i32 - 1801U, // UMULLv8i8_v8i16 - 1033U, // UQADDv16i8 - 1U, // UQADDv1i16 - 1U, // UQADDv1i32 - 1U, // UQADDv1i64 - 1U, // UQADDv1i8 - 1289U, // UQADDv2i32 - 265U, // UQADDv2i64 - 1545U, // UQADDv4i16 - 521U, // UQADDv4i32 - 777U, // UQADDv8i16 - 1801U, // UQADDv8i8 - 1033U, // UQRSHLv16i8 - 1U, // UQRSHLv1i16 - 1U, // UQRSHLv1i32 - 1U, // UQRSHLv1i64 - 1U, // UQRSHLv1i8 - 1289U, // UQRSHLv2i32 - 265U, // UQRSHLv2i64 - 1545U, // UQRSHLv4i16 - 521U, // UQRSHLv4i32 - 777U, // UQRSHLv8i16 - 1801U, // UQRSHLv8i8 - 1U, // UQRSHRNb - 1U, // UQRSHRNh - 1U, // UQRSHRNs - 65U, // UQRSHRNv16i8_shift - 1U, // UQRSHRNv2i32_shift - 1U, // UQRSHRNv4i16_shift - 65U, // UQRSHRNv4i32_shift - 65U, // UQRSHRNv8i16_shift - 1U, // UQRSHRNv8i8_shift - 1U, // UQSHLb - 1U, // UQSHLd - 1U, // UQSHLh - 1U, // UQSHLs - 1033U, // UQSHLv16i8 - 1U, // UQSHLv16i8_shift - 1U, // UQSHLv1i16 - 1U, // UQSHLv1i32 - 1U, // UQSHLv1i64 - 1U, // UQSHLv1i8 - 1289U, // UQSHLv2i32 - 1U, // UQSHLv2i32_shift - 265U, // UQSHLv2i64 - 1U, // UQSHLv2i64_shift - 1545U, // UQSHLv4i16 - 1U, // UQSHLv4i16_shift - 521U, // UQSHLv4i32 - 1U, // UQSHLv4i32_shift - 777U, // UQSHLv8i16 - 1U, // UQSHLv8i16_shift - 1801U, // UQSHLv8i8 - 1U, // UQSHLv8i8_shift - 1U, // UQSHRNb - 1U, // UQSHRNh - 1U, // UQSHRNs - 65U, // UQSHRNv16i8_shift - 1U, // UQSHRNv2i32_shift - 1U, // UQSHRNv4i16_shift - 65U, // UQSHRNv4i32_shift - 65U, // UQSHRNv8i16_shift - 1U, // UQSHRNv8i8_shift - 1033U, // UQSUBv16i8 - 1U, // UQSUBv1i16 - 1U, // UQSUBv1i32 - 1U, // UQSUBv1i64 - 1U, // UQSUBv1i8 - 1289U, // UQSUBv2i32 - 265U, // UQSUBv2i64 - 1545U, // UQSUBv4i16 - 521U, // UQSUBv4i32 - 777U, // UQSUBv8i16 - 1801U, // UQSUBv8i8 - 0U, // UQXTNv16i8 - 0U, // UQXTNv1i16 - 0U, // UQXTNv1i32 - 0U, // UQXTNv1i8 - 0U, // UQXTNv2i32 - 0U, // UQXTNv4i16 - 0U, // UQXTNv4i32 - 0U, // UQXTNv8i16 - 0U, // UQXTNv8i8 - 0U, // URECPEv2i32 - 0U, // URECPEv4i32 - 1033U, // URHADDv16i8 - 1289U, // URHADDv2i32 - 1545U, // URHADDv4i16 - 521U, // URHADDv4i32 - 777U, // URHADDv8i16 - 1801U, // URHADDv8i8 - 1033U, // URSHLv16i8 - 1U, // URSHLv1i64 - 1289U, // URSHLv2i32 - 265U, // URSHLv2i64 - 1545U, // URSHLv4i16 - 521U, // URSHLv4i32 - 777U, // URSHLv8i16 - 1801U, // URSHLv8i8 - 1U, // URSHRd - 1U, // URSHRv16i8_shift - 1U, // URSHRv2i32_shift - 1U, // URSHRv2i64_shift - 1U, // URSHRv4i16_shift - 1U, // URSHRv4i32_shift - 1U, // URSHRv8i16_shift - 1U, // URSHRv8i8_shift - 0U, // URSQRTEv2i32 - 0U, // URSQRTEv4i32 - 65U, // URSRAd - 65U, // URSRAv16i8_shift - 65U, // URSRAv2i32_shift - 65U, // URSRAv2i64_shift - 65U, // URSRAv4i16_shift - 65U, // URSRAv4i32_shift - 65U, // URSRAv8i16_shift - 65U, // URSRAv8i8_shift - 1U, // USHLLv16i8_shift - 1U, // USHLLv2i32_shift - 1U, // USHLLv4i16_shift - 1U, // USHLLv4i32_shift - 1U, // USHLLv8i16_shift - 1U, // USHLLv8i8_shift - 1033U, // USHLv16i8 - 1U, // USHLv1i64 - 1289U, // USHLv2i32 - 265U, // USHLv2i64 - 1545U, // USHLv4i16 - 521U, // USHLv4i32 - 777U, // USHLv8i16 - 1801U, // USHLv8i8 - 1U, // USHRd - 1U, // USHRv16i8_shift - 1U, // USHRv2i32_shift - 1U, // USHRv2i64_shift - 1U, // USHRv4i16_shift - 1U, // USHRv4i32_shift - 1U, // USHRv8i16_shift - 1U, // USHRv8i8_shift - 0U, // USQADDv16i8 - 0U, // USQADDv1i16 - 0U, // USQADDv1i32 - 0U, // USQADDv1i64 - 0U, // USQADDv1i8 - 0U, // USQADDv2i32 - 0U, // USQADDv2i64 - 0U, // USQADDv4i16 - 0U, // USQADDv4i32 - 0U, // USQADDv8i16 - 0U, // USQADDv8i8 - 65U, // USRAd - 65U, // USRAv16i8_shift - 65U, // USRAv2i32_shift - 65U, // USRAv2i64_shift - 65U, // USRAv4i16_shift - 65U, // USRAv4i32_shift - 65U, // USRAv8i16_shift - 65U, // USRAv8i8_shift - 1033U, // USUBLv16i8_v8i16 - 1289U, // USUBLv2i32_v2i64 - 1545U, // USUBLv4i16_v4i32 - 521U, // USUBLv4i32_v2i64 - 777U, // USUBLv8i16_v4i32 - 1801U, // USUBLv8i8_v8i16 - 1033U, // USUBWv16i8_v8i16 - 1289U, // USUBWv2i32_v2i64 - 1545U, // USUBWv4i16_v4i32 - 521U, // USUBWv4i32_v2i64 - 777U, // USUBWv8i16_v4i32 - 1801U, // USUBWv8i8_v8i16 - 1033U, // UZP1v16i8 - 1289U, // UZP1v2i32 - 265U, // UZP1v2i64 - 1545U, // UZP1v4i16 - 521U, // UZP1v4i32 - 777U, // UZP1v8i16 - 1801U, // UZP1v8i8 - 1033U, // UZP2v16i8 - 1289U, // UZP2v2i32 - 265U, // UZP2v2i64 - 1545U, // UZP2v4i16 - 521U, // UZP2v4i32 - 777U, // UZP2v8i16 - 1801U, // UZP2v8i8 - 0U, // XTNv16i8 - 0U, // XTNv2i32 - 0U, // XTNv4i16 - 0U, // XTNv4i32 - 0U, // XTNv8i16 - 0U, // XTNv8i8 - 1033U, // ZIP1v16i8 - 1289U, // ZIP1v2i32 - 265U, // ZIP1v2i64 - 1545U, // ZIP1v4i16 - 521U, // ZIP1v4i32 - 777U, // ZIP1v8i16 - 1801U, // ZIP1v8i8 - 1033U, // ZIP2v16i8 - 1289U, // ZIP2v2i32 - 265U, // ZIP2v2i64 - 1545U, // ZIP2v4i16 - 521U, // ZIP2v4i32 - 777U, // ZIP2v8i16 - 1801U, // ZIP2v8i8 - 0U + 0U, // TLSDESC_CALLSEQ + 837U, // TRN1_PPP_B + 901U, // TRN1_PPP_D + 137U, // TRN1_PPP_H + 1029U, // TRN1_PPP_S + 837U, // TRN1_ZZZ_B + 901U, // TRN1_ZZZ_D + 137U, // TRN1_ZZZ_H + 1029U, // TRN1_ZZZ_S + 33095U, // TRN1v16i8 + 41287U, // TRN1v2i32 + 8517U, // TRN1v2i64 + 49480U, // TRN1v4i16 + 16710U, // TRN1v4i32 + 24902U, // TRN1v8i16 + 57672U, // TRN1v8i8 + 837U, // TRN2_PPP_B + 901U, // TRN2_PPP_D + 137U, // TRN2_PPP_H + 1029U, // TRN2_PPP_S + 837U, // TRN2_ZZZ_B + 901U, // TRN2_ZZZ_D + 137U, // TRN2_ZZZ_H + 1029U, // TRN2_ZZZ_S + 33095U, // TRN2v16i8 + 41287U, // TRN2v2i32 + 8517U, // TRN2v2i64 + 49480U, // TRN2v4i16 + 16710U, // TRN2v4i32 + 24902U, // TRN2v8i16 + 57672U, // TRN2v8i8 + 0U, // TSB + 33159U, // UABALv16i8_v8i16 + 41351U, // UABALv2i32_v2i64 + 49544U, // UABALv4i16_v4i32 + 16774U, // UABALv4i32_v2i64 + 24966U, // UABALv8i16_v4i32 + 57736U, // UABALv8i8_v8i16 + 33159U, // UABAv16i8 + 41351U, // UABAv2i32 + 49544U, // UABAv4i16 + 16774U, // UABAv4i32 + 24966U, // UABAv8i16 + 57736U, // UABAv8i8 + 33095U, // UABDLv16i8_v8i16 + 41287U, // UABDLv2i32_v2i64 + 49480U, // UABDLv4i16_v4i32 + 16710U, // UABDLv4i32_v2i64 + 24902U, // UABDLv8i16_v4i32 + 57672U, // UABDLv8i8_v8i16 + 74560U, // UABD_ZPmZ_B + 598912U, // UABD_ZPmZ_D + 1131465U, // UABD_ZPmZ_H + 1647616U, // UABD_ZPmZ_S + 33095U, // UABDv16i8 + 41287U, // UABDv2i32 + 49480U, // UABDv4i16 + 16710U, // UABDv4i32 + 24902U, // UABDv8i16 + 57672U, // UABDv8i8 + 1U, // UADALPv16i8_v8i16 + 2U, // UADALPv2i32_v1i64 + 3U, // UADALPv4i16_v2i32 + 3U, // UADALPv4i32_v2i64 + 4U, // UADALPv8i16_v4i32 + 4U, // UADALPv8i8_v4i16 + 1U, // UADDLPv16i8_v8i16 + 2U, // UADDLPv2i32_v1i64 + 3U, // UADDLPv4i16_v2i32 + 3U, // UADDLPv4i32_v2i64 + 4U, // UADDLPv8i16_v4i32 + 4U, // UADDLPv8i8_v4i16 + 1U, // UADDLVv16i8v + 3U, // UADDLVv4i16v + 3U, // UADDLVv4i32v + 4U, // UADDLVv8i16v + 4U, // UADDLVv8i8v + 33095U, // UADDLv16i8_v8i16 + 41287U, // UADDLv2i32_v2i64 + 49480U, // UADDLv4i16_v4i32 + 16710U, // UADDLv4i32_v2i64 + 24902U, // UADDLv8i16_v4i32 + 57672U, // UADDLv8i8_v8i16 + 837U, // UADDV_VPZ_B + 901U, // UADDV_VPZ_D + 2245U, // UADDV_VPZ_H + 1029U, // UADDV_VPZ_S + 33094U, // UADDWv16i8_v8i16 + 41285U, // UADDWv2i32_v2i64 + 49478U, // UADDWv4i16_v4i32 + 16709U, // UADDWv4i32_v2i64 + 24902U, // UADDWv8i16_v4i32 + 57670U, // UADDWv8i8_v8i16 + 2171141U, // UBFMWri + 2171141U, // UBFMXri + 261U, // UCVTFSWDri + 261U, // UCVTFSWHri + 261U, // UCVTFSWSri + 261U, // UCVTFSXDri + 261U, // UCVTFSXHri + 261U, // UCVTFSXSri + 1U, // UCVTFUWDri + 1U, // UCVTFUWHri + 1U, // UCVTFUWSri + 1U, // UCVTFUXDri + 1U, // UCVTFUXHri + 1U, // UCVTFUXSri + 64U, // UCVTF_ZPmZ_DtoD + 153U, // UCVTF_ZPmZ_DtoH + 64U, // UCVTF_ZPmZ_DtoS + 128U, // UCVTF_ZPmZ_HtoH + 192U, // UCVTF_ZPmZ_StoD + 152U, // UCVTF_ZPmZ_StoH + 192U, // UCVTF_ZPmZ_StoS + 261U, // UCVTFd + 261U, // UCVTFh + 261U, // UCVTFs + 1U, // UCVTFv1i16 + 1U, // UCVTFv1i32 + 1U, // UCVTFv1i64 + 2U, // UCVTFv2f32 + 2U, // UCVTFv2f64 + 263U, // UCVTFv2i32_shift + 261U, // UCVTFv2i64_shift + 3U, // UCVTFv4f16 + 3U, // UCVTFv4f32 + 264U, // UCVTFv4i16_shift + 262U, // UCVTFv4i32_shift + 4U, // UCVTFv8f16 + 262U, // UCVTFv8i16_shift + 598912U, // UDIVR_ZPmZ_D + 1647616U, // UDIVR_ZPmZ_S + 261U, // UDIVWr + 261U, // UDIVXr + 598912U, // UDIV_ZPmZ_D + 1647616U, // UDIV_ZPmZ_S + 41U, // UDOT_ZZZI_D + 41U, // UDOT_ZZZI_S + 1U, // UDOT_ZZZ_D + 1U, // UDOT_ZZZ_S + 278919U, // UDOTlanev16i8 + 278920U, // UDOTlanev8i8 + 33159U, // UDOTv16i8 + 57736U, // UDOTv8i8 + 33095U, // UHADDv16i8 + 41287U, // UHADDv2i32 + 49480U, // UHADDv4i16 + 16710U, // UHADDv4i32 + 24902U, // UHADDv8i16 + 57672U, // UHADDv8i8 + 33095U, // UHSUBv16i8 + 41287U, // UHSUBv2i32 + 49480U, // UHSUBv4i16 + 16710U, // UHSUBv4i32 + 24902U, // UHSUBv8i16 + 57672U, // UHSUBv8i8 + 2171141U, // UMADDLrrr + 33095U, // UMAXPv16i8 + 41287U, // UMAXPv2i32 + 49480U, // UMAXPv4i16 + 16710U, // UMAXPv4i32 + 24902U, // UMAXPv8i16 + 57672U, // UMAXPv8i8 + 837U, // UMAXV_VPZ_B + 901U, // UMAXV_VPZ_D + 2245U, // UMAXV_VPZ_H + 1029U, // UMAXV_VPZ_S + 1U, // UMAXVv16i8v + 3U, // UMAXVv4i16v + 3U, // UMAXVv4i32v + 4U, // UMAXVv8i16v + 4U, // UMAXVv8i8v + 5573U, // UMAX_ZI_B + 5573U, // UMAX_ZI_D + 45U, // UMAX_ZI_H + 5573U, // UMAX_ZI_S + 74560U, // UMAX_ZPmZ_B + 598912U, // UMAX_ZPmZ_D + 1131465U, // UMAX_ZPmZ_H + 1647616U, // UMAX_ZPmZ_S + 33095U, // UMAXv16i8 + 41287U, // UMAXv2i32 + 49480U, // UMAXv4i16 + 16710U, // UMAXv4i32 + 24902U, // UMAXv8i16 + 57672U, // UMAXv8i8 + 33095U, // UMINPv16i8 + 41287U, // UMINPv2i32 + 49480U, // UMINPv4i16 + 16710U, // UMINPv4i32 + 24902U, // UMINPv8i16 + 57672U, // UMINPv8i8 + 837U, // UMINV_VPZ_B + 901U, // UMINV_VPZ_D + 2245U, // UMINV_VPZ_H + 1029U, // UMINV_VPZ_S + 1U, // UMINVv16i8v + 3U, // UMINVv4i16v + 3U, // UMINVv4i32v + 4U, // UMINVv8i16v + 4U, // UMINVv8i8v + 5573U, // UMIN_ZI_B + 5573U, // UMIN_ZI_D + 45U, // UMIN_ZI_H + 5573U, // UMIN_ZI_S + 74560U, // UMIN_ZPmZ_B + 598912U, // UMIN_ZPmZ_D + 1131465U, // UMIN_ZPmZ_H + 1647616U, // UMIN_ZPmZ_S + 33095U, // UMINv16i8 + 41287U, // UMINv2i32 + 49480U, // UMINv4i16 + 16710U, // UMINv4i32 + 24902U, // UMINv8i16 + 57672U, // UMINv8i8 + 33159U, // UMLALv16i8_v8i16 + 9126279U, // UMLALv2i32_indexed + 41351U, // UMLALv2i32_v2i64 + 9118088U, // UMLALv4i16_indexed + 49544U, // UMLALv4i16_v4i32 + 9126278U, // UMLALv4i32_indexed + 16774U, // UMLALv4i32_v2i64 + 9118086U, // UMLALv8i16_indexed + 24966U, // UMLALv8i16_v4i32 + 57736U, // UMLALv8i8_v8i16 + 33159U, // UMLSLv16i8_v8i16 + 9126279U, // UMLSLv2i32_indexed + 41351U, // UMLSLv2i32_v2i64 + 9118088U, // UMLSLv4i16_indexed + 49544U, // UMLSLv4i16_v4i32 + 9126278U, // UMLSLv4i32_indexed + 16774U, // UMLSLv4i32_v2i64 + 9118086U, // UMLSLv8i16_indexed + 24966U, // UMLSLv8i16_v4i32 + 57736U, // UMLSLv8i8_v8i16 + 2770U, // UMOVvi16 + 2770U, // UMOVvi32 + 2771U, // UMOVvi64 + 2771U, // UMOVvi8 + 2171141U, // UMSUBLrrr + 74560U, // UMULH_ZPmZ_B + 598912U, // UMULH_ZPmZ_D + 1131465U, // UMULH_ZPmZ_H + 1647616U, // UMULH_ZPmZ_S + 261U, // UMULHrr + 33095U, // UMULLv16i8_v8i16 + 10174791U, // UMULLv2i32_indexed + 41287U, // UMULLv2i32_v2i64 + 10166600U, // UMULLv4i16_indexed + 49480U, // UMULLv4i16_v4i32 + 10174790U, // UMULLv4i32_indexed + 16710U, // UMULLv4i32_v2i64 + 10166598U, // UMULLv8i16_indexed + 24902U, // UMULLv8i16_v4i32 + 57672U, // UMULLv8i8_v8i16 + 645U, // UQADD_ZI_B + 709U, // UQADD_ZI_D + 9U, // UQADD_ZI_H + 773U, // UQADD_ZI_S + 837U, // UQADD_ZZZ_B + 901U, // UQADD_ZZZ_D + 137U, // UQADD_ZZZ_H + 1029U, // UQADD_ZZZ_S + 33095U, // UQADDv16i8 + 261U, // UQADDv1i16 + 261U, // UQADDv1i32 + 261U, // UQADDv1i64 + 261U, // UQADDv1i8 + 41287U, // UQADDv2i32 + 8517U, // UQADDv2i64 + 49480U, // UQADDv4i16 + 16710U, // UQADDv4i32 + 24902U, // UQADDv8i16 + 57672U, // UQADDv8i8 + 0U, // UQDECB_WPiI + 0U, // UQDECB_XPiI + 0U, // UQDECD_WPiI + 0U, // UQDECD_XPiI + 0U, // UQDECD_ZPiI + 0U, // UQDECH_WPiI + 0U, // UQDECH_XPiI + 0U, // UQDECH_ZPiI + 1U, // UQDECP_WP_B + 1U, // UQDECP_WP_D + 1U, // UQDECP_WP_H + 1U, // UQDECP_WP_S + 1U, // UQDECP_XP_B + 1U, // UQDECP_XP_D + 1U, // UQDECP_XP_H + 1U, // UQDECP_XP_S + 1U, // UQDECP_ZP_D + 0U, // UQDECP_ZP_H + 1U, // UQDECP_ZP_S + 0U, // UQDECW_WPiI + 0U, // UQDECW_XPiI + 0U, // UQDECW_ZPiI + 0U, // UQINCB_WPiI + 0U, // UQINCB_XPiI + 0U, // UQINCD_WPiI + 0U, // UQINCD_XPiI + 0U, // UQINCD_ZPiI + 0U, // UQINCH_WPiI + 0U, // UQINCH_XPiI + 0U, // UQINCH_ZPiI + 1U, // UQINCP_WP_B + 1U, // UQINCP_WP_D + 1U, // UQINCP_WP_H + 1U, // UQINCP_WP_S + 1U, // UQINCP_XP_B + 1U, // UQINCP_XP_D + 1U, // UQINCP_XP_H + 1U, // UQINCP_XP_S + 1U, // UQINCP_ZP_D + 0U, // UQINCP_ZP_H + 1U, // UQINCP_ZP_S + 0U, // UQINCW_WPiI + 0U, // UQINCW_XPiI + 0U, // UQINCW_ZPiI + 33095U, // UQRSHLv16i8 + 261U, // UQRSHLv1i16 + 261U, // UQRSHLv1i32 + 261U, // UQRSHLv1i64 + 261U, // UQRSHLv1i8 + 41287U, // UQRSHLv2i32 + 8517U, // UQRSHLv2i64 + 49480U, // UQRSHLv4i16 + 16710U, // UQRSHLv4i32 + 24902U, // UQRSHLv8i16 + 57672U, // UQRSHLv8i8 + 261U, // UQRSHRNb + 261U, // UQRSHRNh + 261U, // UQRSHRNs + 2310U, // UQRSHRNv16i8_shift + 261U, // UQRSHRNv2i32_shift + 262U, // UQRSHRNv4i16_shift + 2309U, // UQRSHRNv4i32_shift + 2310U, // UQRSHRNv8i16_shift + 262U, // UQRSHRNv8i8_shift + 261U, // UQSHLb + 261U, // UQSHLd + 261U, // UQSHLh + 261U, // UQSHLs + 33095U, // UQSHLv16i8 + 263U, // UQSHLv16i8_shift + 261U, // UQSHLv1i16 + 261U, // UQSHLv1i32 + 261U, // UQSHLv1i64 + 261U, // UQSHLv1i8 + 41287U, // UQSHLv2i32 + 263U, // UQSHLv2i32_shift + 8517U, // UQSHLv2i64 + 261U, // UQSHLv2i64_shift + 49480U, // UQSHLv4i16 + 264U, // UQSHLv4i16_shift + 16710U, // UQSHLv4i32 + 262U, // UQSHLv4i32_shift + 24902U, // UQSHLv8i16 + 262U, // UQSHLv8i16_shift + 57672U, // UQSHLv8i8 + 264U, // UQSHLv8i8_shift + 261U, // UQSHRNb + 261U, // UQSHRNh + 261U, // UQSHRNs + 2310U, // UQSHRNv16i8_shift + 261U, // UQSHRNv2i32_shift + 262U, // UQSHRNv4i16_shift + 2309U, // UQSHRNv4i32_shift + 2310U, // UQSHRNv8i16_shift + 262U, // UQSHRNv8i8_shift + 645U, // UQSUB_ZI_B + 709U, // UQSUB_ZI_D + 9U, // UQSUB_ZI_H + 773U, // UQSUB_ZI_S + 837U, // UQSUB_ZZZ_B + 901U, // UQSUB_ZZZ_D + 137U, // UQSUB_ZZZ_H + 1029U, // UQSUB_ZZZ_S + 33095U, // UQSUBv16i8 + 261U, // UQSUBv1i16 + 261U, // UQSUBv1i32 + 261U, // UQSUBv1i64 + 261U, // UQSUBv1i8 + 41287U, // UQSUBv2i32 + 8517U, // UQSUBv2i64 + 49480U, // UQSUBv4i16 + 16710U, // UQSUBv4i32 + 24902U, // UQSUBv8i16 + 57672U, // UQSUBv8i8 + 4U, // UQXTNv16i8 + 1U, // UQXTNv1i16 + 1U, // UQXTNv1i32 + 1U, // UQXTNv1i8 + 2U, // UQXTNv2i32 + 3U, // UQXTNv4i16 + 2U, // UQXTNv4i32 + 3U, // UQXTNv8i16 + 4U, // UQXTNv8i8 + 2U, // URECPEv2i32 + 3U, // URECPEv4i32 + 33095U, // URHADDv16i8 + 41287U, // URHADDv2i32 + 49480U, // URHADDv4i16 + 16710U, // URHADDv4i32 + 24902U, // URHADDv8i16 + 57672U, // URHADDv8i8 + 33095U, // URSHLv16i8 + 261U, // URSHLv1i64 + 41287U, // URSHLv2i32 + 8517U, // URSHLv2i64 + 49480U, // URSHLv4i16 + 16710U, // URSHLv4i32 + 24902U, // URSHLv8i16 + 57672U, // URSHLv8i8 + 261U, // URSHRd + 263U, // URSHRv16i8_shift + 263U, // URSHRv2i32_shift + 261U, // URSHRv2i64_shift + 264U, // URSHRv4i16_shift + 262U, // URSHRv4i32_shift + 262U, // URSHRv8i16_shift + 264U, // URSHRv8i8_shift + 2U, // URSQRTEv2i32 + 3U, // URSQRTEv4i32 + 2309U, // URSRAd + 2311U, // URSRAv16i8_shift + 2311U, // URSRAv2i32_shift + 2309U, // URSRAv2i64_shift + 2312U, // URSRAv4i16_shift + 2310U, // URSRAv4i32_shift + 2310U, // URSRAv8i16_shift + 2312U, // URSRAv8i8_shift + 263U, // USHLLv16i8_shift + 263U, // USHLLv2i32_shift + 264U, // USHLLv4i16_shift + 262U, // USHLLv4i32_shift + 262U, // USHLLv8i16_shift + 264U, // USHLLv8i8_shift + 33095U, // USHLv16i8 + 261U, // USHLv1i64 + 41287U, // USHLv2i32 + 8517U, // USHLv2i64 + 49480U, // USHLv4i16 + 16710U, // USHLv4i32 + 24902U, // USHLv8i16 + 57672U, // USHLv8i8 + 261U, // USHRd + 263U, // USHRv16i8_shift + 263U, // USHRv2i32_shift + 261U, // USHRv2i64_shift + 264U, // USHRv4i16_shift + 262U, // USHRv4i32_shift + 262U, // USHRv8i16_shift + 264U, // USHRv8i8_shift + 1U, // USQADDv16i8 + 1U, // USQADDv1i16 + 1U, // USQADDv1i32 + 1U, // USQADDv1i64 + 1U, // USQADDv1i8 + 2U, // USQADDv2i32 + 2U, // USQADDv2i64 + 3U, // USQADDv4i16 + 3U, // USQADDv4i32 + 4U, // USQADDv8i16 + 4U, // USQADDv8i8 + 2309U, // USRAd + 2311U, // USRAv16i8_shift + 2311U, // USRAv2i32_shift + 2309U, // USRAv2i64_shift + 2312U, // USRAv4i16_shift + 2310U, // USRAv4i32_shift + 2310U, // USRAv8i16_shift + 2312U, // USRAv8i8_shift + 33095U, // USUBLv16i8_v8i16 + 41287U, // USUBLv2i32_v2i64 + 49480U, // USUBLv4i16_v4i32 + 16710U, // USUBLv4i32_v2i64 + 24902U, // USUBLv8i16_v4i32 + 57672U, // USUBLv8i8_v8i16 + 33094U, // USUBWv16i8_v8i16 + 41285U, // USUBWv2i32_v2i64 + 49478U, // USUBWv4i16_v4i32 + 16709U, // USUBWv4i32_v2i64 + 24902U, // USUBWv8i16_v4i32 + 57670U, // USUBWv8i8_v8i16 + 1U, // UUNPKHI_ZZ_D + 0U, // UUNPKHI_ZZ_H + 1U, // UUNPKHI_ZZ_S + 1U, // UUNPKLO_ZZ_D + 0U, // UUNPKLO_ZZ_H + 1U, // UUNPKLO_ZZ_S + 64U, // UXTB_ZPmZ_D + 128U, // UXTB_ZPmZ_H + 192U, // UXTB_ZPmZ_S + 64U, // UXTH_ZPmZ_D + 192U, // UXTH_ZPmZ_S + 64U, // UXTW_ZPmZ_D + 837U, // UZP1_PPP_B + 901U, // UZP1_PPP_D + 137U, // UZP1_PPP_H + 1029U, // UZP1_PPP_S + 837U, // UZP1_ZZZ_B + 901U, // UZP1_ZZZ_D + 137U, // UZP1_ZZZ_H + 1029U, // UZP1_ZZZ_S + 33095U, // UZP1v16i8 + 41287U, // UZP1v2i32 + 8517U, // UZP1v2i64 + 49480U, // UZP1v4i16 + 16710U, // UZP1v4i32 + 24902U, // UZP1v8i16 + 57672U, // UZP1v8i8 + 837U, // UZP2_PPP_B + 901U, // UZP2_PPP_D + 137U, // UZP2_PPP_H + 1029U, // UZP2_PPP_S + 837U, // UZP2_ZZZ_B + 901U, // UZP2_ZZZ_D + 137U, // UZP2_ZZZ_H + 1029U, // UZP2_ZZZ_S + 33095U, // UZP2v16i8 + 41287U, // UZP2v2i32 + 8517U, // UZP2v2i64 + 49480U, // UZP2v4i16 + 16710U, // UZP2v4i32 + 24902U, // UZP2v8i16 + 57672U, // UZP2v8i8 + 261U, // WHILELE_PWW_B + 261U, // WHILELE_PWW_D + 11U, // WHILELE_PWW_H + 261U, // WHILELE_PWW_S + 261U, // WHILELE_PXX_B + 261U, // WHILELE_PXX_D + 11U, // WHILELE_PXX_H + 261U, // WHILELE_PXX_S + 261U, // WHILELO_PWW_B + 261U, // WHILELO_PWW_D + 11U, // WHILELO_PWW_H + 261U, // WHILELO_PWW_S + 261U, // WHILELO_PXX_B + 261U, // WHILELO_PXX_D + 11U, // WHILELO_PXX_H + 261U, // WHILELO_PXX_S + 261U, // WHILELS_PWW_B + 261U, // WHILELS_PWW_D + 11U, // WHILELS_PWW_H + 261U, // WHILELS_PWW_S + 261U, // WHILELS_PXX_B + 261U, // WHILELS_PXX_D + 11U, // WHILELS_PXX_H + 261U, // WHILELS_PXX_S + 261U, // WHILELT_PWW_B + 261U, // WHILELT_PWW_D + 11U, // WHILELT_PWW_H + 261U, // WHILELT_PWW_S + 261U, // WHILELT_PXX_B + 261U, // WHILELT_PXX_D + 11U, // WHILELT_PXX_H + 261U, // WHILELT_PXX_S + 0U, // WRFFR + 2253125U, // XAR + 0U, // XPACD + 0U, // XPACI + 0U, // XPACLRI + 4U, // XTNv16i8 + 2U, // XTNv2i32 + 3U, // XTNv4i16 + 2U, // XTNv4i32 + 3U, // XTNv8i16 + 4U, // XTNv8i8 + 837U, // ZIP1_PPP_B + 901U, // ZIP1_PPP_D + 137U, // ZIP1_PPP_H + 1029U, // ZIP1_PPP_S + 837U, // ZIP1_ZZZ_B + 901U, // ZIP1_ZZZ_D + 137U, // ZIP1_ZZZ_H + 1029U, // ZIP1_ZZZ_S + 33095U, // ZIP1v16i8 + 41287U, // ZIP1v2i32 + 8517U, // ZIP1v2i64 + 49480U, // ZIP1v4i16 + 16710U, // ZIP1v4i32 + 24902U, // ZIP1v8i16 + 57672U, // ZIP1v8i8 + 837U, // ZIP2_PPP_B + 901U, // ZIP2_PPP_D + 137U, // ZIP2_PPP_H + 1029U, // ZIP2_PPP_S + 837U, // ZIP2_ZZZ_B + 901U, // ZIP2_ZZZ_D + 137U, // ZIP2_ZZZ_H + 1029U, // ZIP2_ZZZ_S + 33095U, // ZIP2v16i8 + 41287U, // ZIP2v2i32 + 8517U, // ZIP2v2i64 + 49480U, // ZIP2v4i16 + 16710U, // ZIP2v4i32 + 24902U, // ZIP2v8i16 + 57672U, // ZIP2v8i8 + 837U, // anonymous_1349 }; -#ifndef CAPSTONE_DIET - static const char AsmStrs[] = { - /* 0 */ 's', 'h', 'a', '1', 's', 'u', '0', 9, 0, - /* 9 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '0', 9, 0, - /* 20 */ 'l', 'd', '1', 9, 0, - /* 25 */ 't', 'r', 'n', '1', 9, 0, - /* 31 */ 'z', 'i', 'p', '1', 9, 0, - /* 37 */ 'u', 'z', 'p', '1', 9, 0, - /* 43 */ 'd', 'c', 'p', 's', '1', 9, 0, - /* 50 */ 's', 't', '1', 9, 0, - /* 55 */ 's', 'h', 'a', '1', 's', 'u', '1', 9, 0, - /* 64 */ 's', 'h', 'a', '2', '5', '6', 's', 'u', '1', 9, 0, - /* 75 */ 'r', 'e', 'v', '3', '2', 9, 0, - /* 82 */ 'l', 'd', '2', 9, 0, - /* 87 */ 's', 'h', 'a', '2', '5', '6', 'h', '2', 9, 0, - /* 97 */ 's', 'a', 'b', 'a', 'l', '2', 9, 0, - /* 105 */ 'u', 'a', 'b', 'a', 'l', '2', 9, 0, - /* 113 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', 9, 0, - /* 123 */ 's', 'm', 'l', 'a', 'l', '2', 9, 0, - /* 131 */ 'u', 'm', 'l', 'a', 'l', '2', 9, 0, - /* 139 */ 's', 's', 'u', 'b', 'l', '2', 9, 0, - /* 147 */ 'u', 's', 'u', 'b', 'l', '2', 9, 0, - /* 155 */ 's', 'a', 'b', 'd', 'l', '2', 9, 0, - /* 163 */ 'u', 'a', 'b', 'd', 'l', '2', 9, 0, - /* 171 */ 's', 'a', 'd', 'd', 'l', '2', 9, 0, - /* 179 */ 'u', 'a', 'd', 'd', 'l', '2', 9, 0, - /* 187 */ 's', 's', 'h', 'l', 'l', '2', 9, 0, - /* 195 */ 'u', 's', 'h', 'l', 'l', '2', 9, 0, - /* 203 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 213 */ 'p', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 221 */ 's', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 229 */ 'u', 'm', 'u', 'l', 'l', '2', 9, 0, - /* 237 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', 9, 0, - /* 247 */ 's', 'm', 'l', 's', 'l', '2', 9, 0, - /* 255 */ 'u', 'm', 'l', 's', 'l', '2', 9, 0, - /* 263 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, - /* 271 */ 'r', 's', 'u', 'b', 'h', 'n', '2', 9, 0, - /* 280 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', 9, 0, - /* 289 */ 's', 'q', 's', 'h', 'r', 'n', '2', 9, 0, - /* 298 */ 'u', 'q', 's', 'h', 'r', 'n', '2', 9, 0, - /* 307 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, - /* 317 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', 9, 0, - /* 327 */ 't', 'r', 'n', '2', 9, 0, - /* 333 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, - /* 341 */ 's', 'q', 'x', 't', 'n', '2', 9, 0, - /* 349 */ 'u', 'q', 'x', 't', 'n', '2', 9, 0, - /* 357 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', 9, 0, - /* 367 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', 9, 0, - /* 378 */ 's', 'q', 'x', 't', 'u', 'n', '2', 9, 0, - /* 387 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, - /* 396 */ 'z', 'i', 'p', '2', 9, 0, - /* 402 */ 'u', 'z', 'p', '2', 9, 0, - /* 408 */ 'd', 'c', 'p', 's', '2', 9, 0, - /* 415 */ 's', 't', '2', 9, 0, - /* 420 */ 's', 's', 'u', 'b', 'w', '2', 9, 0, - /* 428 */ 'u', 's', 'u', 'b', 'w', '2', 9, 0, - /* 436 */ 's', 'a', 'd', 'd', 'w', '2', 9, 0, - /* 444 */ 'u', 'a', 'd', 'd', 'w', '2', 9, 0, - /* 452 */ 'l', 'd', '3', 9, 0, - /* 457 */ 'd', 'c', 'p', 's', '3', 9, 0, - /* 464 */ 's', 't', '3', 9, 0, - /* 469 */ 'r', 'e', 'v', '6', '4', 9, 0, - /* 476 */ 'l', 'd', '4', 9, 0, - /* 481 */ 's', 't', '4', 9, 0, - /* 486 */ 'r', 'e', 'v', '1', '6', 9, 0, - /* 493 */ 's', 'a', 'b', 'a', 9, 0, - /* 499 */ 'u', 'a', 'b', 'a', 9, 0, - /* 505 */ 'f', 'm', 'l', 'a', 9, 0, - /* 511 */ 's', 'r', 's', 'r', 'a', 9, 0, - /* 518 */ 'u', 'r', 's', 'r', 'a', 9, 0, - /* 525 */ 's', 's', 'r', 'a', 9, 0, - /* 531 */ 'u', 's', 'r', 'a', 9, 0, - /* 537 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, - /* 545 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, - /* 553 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, - /* 562 */ 'd', 'm', 'b', 9, 0, - /* 567 */ 'l', 'd', 'a', 'r', 'b', 9, 0, - /* 574 */ 'l', 'd', 'r', 'b', 9, 0, - /* 580 */ 's', 't', 'l', 'r', 'b', 9, 0, - /* 587 */ 'l', 'd', 't', 'r', 'b', 9, 0, - /* 594 */ 's', 't', 'r', 'b', 9, 0, - /* 600 */ 's', 't', 't', 'r', 'b', 9, 0, - /* 607 */ 'l', 'd', 'u', 'r', 'b', 9, 0, - /* 614 */ 's', 't', 'u', 'r', 'b', 9, 0, - /* 621 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, - /* 629 */ 'l', 'd', 'x', 'r', 'b', 9, 0, - /* 636 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, - /* 644 */ 's', 't', 'x', 'r', 'b', 9, 0, - /* 651 */ 'd', 's', 'b', 9, 0, - /* 656 */ 'i', 's', 'b', 9, 0, - /* 661 */ 'l', 'd', 'r', 's', 'b', 9, 0, - /* 668 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, - /* 676 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, - /* 684 */ 'f', 's', 'u', 'b', 9, 0, - /* 690 */ 's', 'h', 's', 'u', 'b', 9, 0, - /* 697 */ 'u', 'h', 's', 'u', 'b', 9, 0, - /* 704 */ 'f', 'm', 's', 'u', 'b', 9, 0, - /* 711 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, - /* 719 */ 's', 'q', 's', 'u', 'b', 9, 0, - /* 726 */ 'u', 'q', 's', 'u', 'b', 9, 0, - /* 733 */ 's', 'h', 'a', '1', 'c', 9, 0, - /* 740 */ 's', 'b', 'c', 9, 0, - /* 745 */ 'a', 'd', 'c', 9, 0, - /* 750 */ 'b', 'i', 'c', 9, 0, - /* 755 */ 'a', 'e', 's', 'i', 'm', 'c', 9, 0, - /* 763 */ 'a', 'e', 's', 'm', 'c', 9, 0, - /* 770 */ 'c', 's', 'i', 'n', 'c', 9, 0, - /* 777 */ 'h', 'v', 'c', 9, 0, - /* 782 */ 's', 'v', 'c', 9, 0, - /* 787 */ 'f', 'a', 'b', 'd', 9, 0, - /* 793 */ 's', 'a', 'b', 'd', 9, 0, - /* 799 */ 'u', 'a', 'b', 'd', 9, 0, - /* 805 */ 'f', 'a', 'd', 'd', 9, 0, - /* 811 */ 's', 'r', 'h', 'a', 'd', 'd', 9, 0, - /* 819 */ 'u', 'r', 'h', 'a', 'd', 'd', 9, 0, - /* 827 */ 's', 'h', 'a', 'd', 'd', 9, 0, - /* 834 */ 'u', 'h', 'a', 'd', 'd', 9, 0, - /* 841 */ 'f', 'm', 'a', 'd', 'd', 9, 0, - /* 848 */ 'f', 'n', 'm', 'a', 'd', 'd', 9, 0, - /* 856 */ 'u', 's', 'q', 'a', 'd', 'd', 9, 0, - /* 864 */ 's', 'u', 'q', 'a', 'd', 'd', 9, 0, - /* 872 */ 'a', 'n', 'd', 9, 0, - /* 877 */ 'a', 'e', 's', 'd', 9, 0, - /* 883 */ 'f', 'a', 'c', 'g', 'e', 9, 0, - /* 890 */ 'f', 'c', 'm', 'g', 'e', 9, 0, - /* 897 */ 'f', 'c', 'm', 'l', 'e', 9, 0, - /* 904 */ 'f', 'r', 'e', 'c', 'p', 'e', 9, 0, - /* 912 */ 'u', 'r', 'e', 'c', 'p', 'e', 9, 0, - /* 920 */ 'f', 'c', 'c', 'm', 'p', 'e', 9, 0, - /* 928 */ 'f', 'c', 'm', 'p', 'e', 9, 0, - /* 935 */ 'a', 'e', 's', 'e', 9, 0, - /* 941 */ 'f', 'r', 's', 'q', 'r', 't', 'e', 9, 0, - /* 950 */ 'u', 'r', 's', 'q', 'r', 't', 'e', 9, 0, - /* 959 */ 'b', 'i', 'f', 9, 0, - /* 964 */ 's', 'c', 'v', 't', 'f', 9, 0, - /* 971 */ 'u', 'c', 'v', 't', 'f', 9, 0, - /* 978 */ 'f', 'n', 'e', 'g', 9, 0, - /* 984 */ 's', 'q', 'n', 'e', 'g', 9, 0, - /* 991 */ 'c', 's', 'n', 'e', 'g', 9, 0, - /* 998 */ 's', 'h', 'a', '1', 'h', 9, 0, - /* 1005 */ 'c', 'r', 'c', '3', '2', 'h', 9, 0, - /* 1013 */ 's', 'h', 'a', '2', '5', '6', 'h', 9, 0, - /* 1022 */ 'c', 'r', 'c', '3', '2', 'c', 'h', 9, 0, - /* 1031 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, - /* 1040 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, - /* 1050 */ 's', 'm', 'u', 'l', 'h', 9, 0, - /* 1057 */ 'u', 'm', 'u', 'l', 'h', 9, 0, - /* 1064 */ 'l', 'd', 'a', 'r', 'h', 9, 0, - /* 1071 */ 'l', 'd', 'r', 'h', 9, 0, - /* 1077 */ 's', 't', 'l', 'r', 'h', 9, 0, - /* 1084 */ 'l', 'd', 't', 'r', 'h', 9, 0, - /* 1091 */ 's', 't', 'r', 'h', 9, 0, - /* 1097 */ 's', 't', 't', 'r', 'h', 9, 0, - /* 1104 */ 'l', 'd', 'u', 'r', 'h', 9, 0, - /* 1111 */ 's', 't', 'u', 'r', 'h', 9, 0, - /* 1118 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, - /* 1126 */ 'l', 'd', 'x', 'r', 'h', 9, 0, - /* 1133 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, - /* 1141 */ 's', 't', 'x', 'r', 'h', 9, 0, - /* 1148 */ 'l', 'd', 'r', 's', 'h', 9, 0, - /* 1155 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, - /* 1163 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, - /* 1171 */ 'c', 'm', 'h', 'i', 9, 0, - /* 1177 */ 's', 'l', 'i', 9, 0, - /* 1182 */ 'm', 'v', 'n', 'i', 9, 0, - /* 1188 */ 's', 'r', 'i', 9, 0, - /* 1193 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, - /* 1201 */ 'm', 'o', 'v', 'i', 9, 0, - /* 1207 */ 'b', 'r', 'k', 9, 0, - /* 1212 */ 'm', 'o', 'v', 'k', 9, 0, - /* 1218 */ 's', 'a', 'b', 'a', 'l', 9, 0, - /* 1225 */ 'u', 'a', 'b', 'a', 'l', 9, 0, - /* 1232 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, - /* 1241 */ 's', 'm', 'l', 'a', 'l', 9, 0, - /* 1248 */ 'u', 'm', 'l', 'a', 'l', 9, 0, - /* 1255 */ 't', 'b', 'l', 9, 0, - /* 1260 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, - /* 1268 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, - /* 1276 */ 's', 's', 'u', 'b', 'l', 9, 0, - /* 1283 */ 'u', 's', 'u', 'b', 'l', 9, 0, - /* 1290 */ 's', 'a', 'b', 'd', 'l', 9, 0, - /* 1297 */ 'u', 'a', 'b', 'd', 'l', 9, 0, - /* 1304 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, - /* 1312 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, - /* 1320 */ 's', 'a', 'd', 'd', 'l', 9, 0, - /* 1327 */ 'u', 'a', 'd', 'd', 'l', 9, 0, - /* 1334 */ 'f', 'c', 's', 'e', 'l', 9, 0, - /* 1341 */ 's', 'q', 's', 'h', 'l', 9, 0, - /* 1348 */ 'u', 'q', 's', 'h', 'l', 9, 0, - /* 1355 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, - /* 1363 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, - /* 1371 */ 's', 'r', 's', 'h', 'l', 9, 0, - /* 1378 */ 'u', 'r', 's', 'h', 'l', 9, 0, - /* 1385 */ 's', 's', 'h', 'l', 9, 0, - /* 1391 */ 'u', 's', 'h', 'l', 9, 0, - /* 1397 */ 's', 's', 'h', 'l', 'l', 9, 0, - /* 1404 */ 'u', 's', 'h', 'l', 'l', 9, 0, - /* 1411 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, - /* 1420 */ 'p', 'm', 'u', 'l', 'l', 9, 0, - /* 1427 */ 's', 'm', 'u', 'l', 'l', 9, 0, - /* 1434 */ 'u', 'm', 'u', 'l', 'l', 9, 0, - /* 1441 */ 'b', 's', 'l', 9, 0, - /* 1446 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, - /* 1455 */ 's', 'm', 'l', 's', 'l', 9, 0, - /* 1462 */ 'u', 'm', 'l', 's', 'l', 9, 0, - /* 1469 */ 's', 'y', 's', 'l', 9, 0, - /* 1475 */ 'f', 'c', 'v', 't', 'l', 9, 0, - /* 1482 */ 'f', 'm', 'u', 'l', 9, 0, - /* 1488 */ 'f', 'n', 'm', 'u', 'l', 9, 0, - /* 1495 */ 'p', 'm', 'u', 'l', 9, 0, - /* 1501 */ 's', 'h', 'a', '1', 'm', 9, 0, - /* 1508 */ 's', 'b', 'f', 'm', 9, 0, - /* 1514 */ 'u', 'b', 'f', 'm', 9, 0, - /* 1520 */ 'p', 'r', 'f', 'm', 9, 0, - /* 1526 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, - /* 1534 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, - /* 1542 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, - /* 1550 */ 'p', 'r', 'f', 'u', 'm', 9, 0, - /* 1557 */ 'r', 's', 'u', 'b', 'h', 'n', 9, 0, - /* 1565 */ 'r', 'a', 'd', 'd', 'h', 'n', 9, 0, - /* 1573 */ 'f', 'm', 'i', 'n', 9, 0, - /* 1579 */ 's', 'm', 'i', 'n', 9, 0, - /* 1585 */ 'u', 'm', 'i', 'n', 9, 0, - /* 1591 */ 'c', 'c', 'm', 'n', 9, 0, - /* 1597 */ 'e', 'o', 'n', 9, 0, - /* 1602 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, - /* 1610 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, - /* 1618 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, - /* 1627 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, - /* 1636 */ 'o', 'r', 'n', 9, 0, - /* 1641 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, - /* 1649 */ 'f', 'c', 'v', 't', 'n', 9, 0, - /* 1656 */ 's', 'q', 'x', 't', 'n', 9, 0, - /* 1663 */ 'u', 'q', 'x', 't', 'n', 9, 0, - /* 1670 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, - /* 1679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, - /* 1689 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, - /* 1697 */ 'm', 'o', 'v', 'n', 9, 0, - /* 1703 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, - /* 1711 */ 's', 'h', 'a', '1', 'p', 9, 0, - /* 1718 */ 'f', 'a', 'd', 'd', 'p', 9, 0, - /* 1725 */ 'l', 'd', 'p', 9, 0, - /* 1730 */ 's', 'a', 'd', 'a', 'l', 'p', 9, 0, - /* 1738 */ 'u', 'a', 'd', 'a', 'l', 'p', 9, 0, - /* 1746 */ 's', 'a', 'd', 'd', 'l', 'p', 9, 0, - /* 1754 */ 'u', 'a', 'd', 'd', 'l', 'p', 9, 0, - /* 1762 */ 'f', 'c', 'c', 'm', 'p', 9, 0, - /* 1769 */ 'f', 'c', 'm', 'p', 9, 0, - /* 1775 */ 'f', 'm', 'i', 'n', 'n', 'm', 'p', 9, 0, - /* 1784 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', 9, 0, - /* 1793 */ 'l', 'd', 'n', 'p', 9, 0, - /* 1799 */ 'f', 'm', 'i', 'n', 'p', 9, 0, - /* 1806 */ 's', 'm', 'i', 'n', 'p', 9, 0, - /* 1813 */ 'u', 'm', 'i', 'n', 'p', 9, 0, - /* 1820 */ 's', 't', 'n', 'p', 9, 0, - /* 1826 */ 'a', 'd', 'r', 'p', 9, 0, - /* 1832 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, - /* 1840 */ 's', 't', 'p', 9, 0, - /* 1845 */ 'd', 'u', 'p', 9, 0, - /* 1850 */ 'l', 'd', 'a', 'x', 'p', 9, 0, - /* 1857 */ 'f', 'm', 'a', 'x', 'p', 9, 0, - /* 1864 */ 's', 'm', 'a', 'x', 'p', 9, 0, - /* 1871 */ 'u', 'm', 'a', 'x', 'p', 9, 0, - /* 1878 */ 'l', 'd', 'x', 'p', 9, 0, - /* 1884 */ 's', 't', 'l', 'x', 'p', 9, 0, - /* 1891 */ 's', 't', 'x', 'p', 9, 0, - /* 1897 */ 'f', 'c', 'm', 'e', 'q', 9, 0, - /* 1904 */ 'l', 'd', '1', 'r', 9, 0, - /* 1910 */ 'l', 'd', '2', 'r', 9, 0, - /* 1916 */ 'l', 'd', '3', 'r', 9, 0, - /* 1922 */ 'l', 'd', '4', 'r', 9, 0, - /* 1928 */ 'l', 'd', 'a', 'r', 9, 0, - /* 1934 */ 'b', 'r', 9, 0, - /* 1938 */ 'a', 'd', 'r', 9, 0, - /* 1943 */ 'l', 'd', 'r', 9, 0, - /* 1948 */ 's', 'r', 's', 'h', 'r', 9, 0, - /* 1955 */ 'u', 'r', 's', 'h', 'r', 9, 0, - /* 1962 */ 's', 's', 'h', 'r', 9, 0, - /* 1968 */ 'u', 's', 'h', 'r', 9, 0, - /* 1974 */ 'b', 'l', 'r', 9, 0, - /* 1979 */ 's', 't', 'l', 'r', 9, 0, - /* 1985 */ 'e', 'o', 'r', 9, 0, - /* 1990 */ 'r', 'o', 'r', 9, 0, - /* 1995 */ 'o', 'r', 'r', 9, 0, - /* 2000 */ 'a', 's', 'r', 9, 0, - /* 2005 */ 'l', 's', 'r', 9, 0, - /* 2010 */ 'm', 's', 'r', 9, 0, - /* 2015 */ 'l', 'd', 't', 'r', 9, 0, - /* 2021 */ 's', 't', 'r', 9, 0, - /* 2026 */ 's', 't', 't', 'r', 9, 0, - /* 2032 */ 'e', 'x', 't', 'r', 9, 0, - /* 2038 */ 'l', 'd', 'u', 'r', 9, 0, - /* 2044 */ 's', 't', 'u', 'r', 9, 0, - /* 2050 */ 'l', 'd', 'a', 'x', 'r', 9, 0, - /* 2057 */ 'l', 'd', 'x', 'r', 9, 0, - /* 2063 */ 's', 't', 'l', 'x', 'r', 9, 0, - /* 2070 */ 's', 't', 'x', 'r', 9, 0, - /* 2076 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, - /* 2084 */ 'f', 'a', 'b', 's', 9, 0, - /* 2090 */ 's', 'q', 'a', 'b', 's', 9, 0, - /* 2097 */ 's', 'u', 'b', 's', 9, 0, - /* 2103 */ 's', 'b', 'c', 's', 9, 0, - /* 2109 */ 'a', 'd', 'c', 's', 9, 0, - /* 2115 */ 'b', 'i', 'c', 's', 9, 0, - /* 2121 */ 'a', 'd', 'd', 's', 9, 0, - /* 2127 */ 'a', 'n', 'd', 's', 9, 0, - /* 2133 */ 'c', 'm', 'h', 's', 9, 0, - /* 2139 */ 'c', 'l', 's', 9, 0, - /* 2144 */ 'f', 'm', 'l', 's', 9, 0, - /* 2150 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, - /* 2158 */ 'i', 'n', 's', 9, 0, - /* 2163 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, - /* 2171 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, - /* 2179 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, - /* 2187 */ 'm', 'r', 's', 9, 0, - /* 2192 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, - /* 2201 */ 's', 'y', 's', 9, 0, - /* 2206 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, - /* 2214 */ 'r', 'e', 't', 9, 0, - /* 2219 */ 'f', 'a', 'c', 'g', 't', 9, 0, - /* 2226 */ 'f', 'c', 'm', 'g', 't', 9, 0, - /* 2233 */ 'r', 'b', 'i', 't', 9, 0, - /* 2239 */ 'h', 'l', 't', 9, 0, - /* 2244 */ 'f', 'c', 'm', 'l', 't', 9, 0, - /* 2251 */ 'c', 'n', 't', 9, 0, - /* 2256 */ 'n', 'o', 't', 9, 0, - /* 2261 */ 'f', 's', 'q', 'r', 't', 9, 0, - /* 2268 */ 'c', 'm', 't', 's', 't', 9, 0, - /* 2275 */ 'f', 'c', 'v', 't', 9, 0, - /* 2281 */ 'e', 'x', 't', 9, 0, - /* 2286 */ 'f', 'c', 'v', 't', 'a', 'u', 9, 0, - /* 2294 */ 's', 'q', 's', 'h', 'l', 'u', 9, 0, - /* 2302 */ 'f', 'c', 'v', 't', 'm', 'u', 9, 0, - /* 2310 */ 'f', 'c', 'v', 't', 'n', 'u', 9, 0, - /* 2318 */ 'f', 'c', 'v', 't', 'p', 'u', 9, 0, - /* 2326 */ 'f', 'c', 'v', 't', 'z', 'u', 9, 0, - /* 2334 */ 'a', 'd', 'd', 'v', 9, 0, - /* 2340 */ 'r', 'e', 'v', 9, 0, - /* 2345 */ 'f', 'd', 'i', 'v', 9, 0, - /* 2351 */ 's', 'd', 'i', 'v', 9, 0, - /* 2357 */ 'u', 'd', 'i', 'v', 9, 0, - /* 2363 */ 's', 'a', 'd', 'd', 'l', 'v', 9, 0, - /* 2371 */ 'u', 'a', 'd', 'd', 'l', 'v', 9, 0, - /* 2379 */ 'f', 'm', 'i', 'n', 'n', 'm', 'v', 9, 0, - /* 2388 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, - /* 2397 */ 'f', 'm', 'i', 'n', 'v', 9, 0, - /* 2404 */ 's', 'm', 'i', 'n', 'v', 9, 0, - /* 2411 */ 'u', 'm', 'i', 'n', 'v', 9, 0, - /* 2418 */ 'c', 's', 'i', 'n', 'v', 9, 0, - /* 2425 */ 'f', 'm', 'o', 'v', 9, 0, - /* 2431 */ 's', 'm', 'o', 'v', 9, 0, - /* 2437 */ 'u', 'm', 'o', 'v', 9, 0, - /* 2443 */ 'f', 'm', 'a', 'x', 'v', 9, 0, - /* 2450 */ 's', 'm', 'a', 'x', 'v', 9, 0, - /* 2457 */ 'u', 'm', 'a', 'x', 'v', 9, 0, - /* 2464 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, - /* 2472 */ 's', 's', 'u', 'b', 'w', 9, 0, - /* 2479 */ 'u', 's', 'u', 'b', 'w', 9, 0, - /* 2486 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, - /* 2495 */ 's', 'a', 'd', 'd', 'w', 9, 0, - /* 2502 */ 'u', 'a', 'd', 'd', 'w', 9, 0, - /* 2509 */ 'l', 'd', 'p', 's', 'w', 9, 0, - /* 2516 */ 'l', 'd', 'r', 's', 'w', 9, 0, - /* 2523 */ 'l', 'd', 't', 'r', 's', 'w', 9, 0, - /* 2531 */ 'l', 'd', 'u', 'r', 's', 'w', 9, 0, - /* 2539 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, - /* 2547 */ 'f', 'm', 'a', 'x', 9, 0, - /* 2553 */ 's', 'm', 'a', 'x', 9, 0, - /* 2559 */ 'u', 'm', 'a', 'x', 9, 0, - /* 2565 */ 't', 'b', 'x', 9, 0, - /* 2570 */ 'c', 'r', 'c', '3', '2', 'c', 'x', 9, 0, - /* 2579 */ 'c', 'l', 'r', 'e', 'x', 9, 0, - /* 2586 */ 'f', 'm', 'u', 'l', 'x', 9, 0, - /* 2593 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, - /* 2601 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, - /* 2609 */ 'c', 'b', 'z', 9, 0, - /* 2614 */ 't', 'b', 'z', 9, 0, - /* 2619 */ 'c', 'l', 'z', 9, 0, - /* 2624 */ 'c', 'b', 'n', 'z', 9, 0, - /* 2630 */ 't', 'b', 'n', 'z', 9, 0, - /* 2636 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, - /* 2644 */ 'm', 'o', 'v', 'z', 9, 0, - /* 2650 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, - /* 2664 */ 'h', 'i', 'n', 't', 32, 0, - /* 2670 */ 'b', '.', 0, - /* 2673 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 2686 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 2693 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 2703 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, - /* 2718 */ 'd', 'r', 'p', 's', 0, - /* 2723 */ 'e', 'r', 'e', 't', 0, - }; -#endif + unsigned int opcode = MCInst_getOpcode(MI); + // printf("opcode = %u\n", opcode); // Emit the opcode for the instruction. - uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; - uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; - uint64_t Bits = (Bits2 << 32) | Bits1; - // assert(Bits != 0 && "Cannot print this instruction."); -#ifndef CAPSTONE_DIET - SStream_concat0(O, AsmStrs+(Bits & 4095)-1); -#endif + uint64_t Bits = 0; + Bits |= (uint64_t)OpInfo0[opcode] << 0; + Bits |= (uint64_t)OpInfo1[opcode] << 32; + SStream_concat0(O, AsmStrs+(Bits & 8191)-1); - - // Fragment 0 encoded into 6 bits for 40 unique commands. - //printf("Frag-0: %"PRIu64"\n", (Bits >> 12) & 63); - switch ((Bits >> 12) & 63) { - default: // unreachable. + // Fragment 0 encoded into 6 bits for 54 unique commands. + // printf("Fragment 0: %"PRIu64"\n", ((Bits >> 13) & 63)); + switch ((Bits >> 13) & 63) { + default: // unreachable case 0: - // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, DRPS, ERET + // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; break; case 1: - // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... - printVRegOperand(MI, 0, O); + // ABS_ZPmZ_B, ADD_ZI_B, ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, AND_PPzPP, AN... + printSVERegOp(MI, 0, O, 'b'); break; case 2: - // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... - printOperand(MI, 0, O); + // ABS_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_... + printSVERegOp(MI, 0, O, 'd'); break; case 3: - // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... - printVRegOperand(MI, 1, O); + // ABS_ZPmZ_H, ADD_ZI_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ... + printSVERegOp(MI, 0, O, 'h'); + SStream_concat0(O, ", "); break; case 4: - // B, BL - printAlignedLabel(MI, 0, O); - return; + // ABS_ZPmZ_S, ADD_ZI_S, ADD_ZPmZ_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_... + printSVERegOp(MI, 0, O, 's'); break; case 5: - // BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, SMC, SVC - printHexImm(MI, 0, O); - return; + // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... + printVRegOperand(MI, 0, O); break; case 6: - // Bcc - printCondCode(MI, 0, O); - SStream_concat0(O, "\t"); - printAlignedLabel(MI, 1, O); - return; + // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPv2i64p, ADDSWri... + printOperand(MI, 0, O); break; case 7: - // DMB, DSB, ISB - printBarrierOption(MI, 0, O); - return; + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... + printVRegOperand(MI, 1, O); break; case 8: - // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexed, FMLSv1i64_ind... - printOperand(MI, 1, O); + // B, BL + printAlignedLabel(MI, 0, O); + return; break; case 9: - // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... - printTypedVectorList(MI, 0, O, 16, 'b', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC + printImmHex(MI, 0, O); return; break; case 10: - // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... - printTypedVectorList(MI, 1, O, 16, 'b', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); - set_mem_access(MI, false); + // Bcc + printCondCode(MI, 0, O); + SStream_concat0(O, "\t"); + printAlignedLabel(MI, 1, O); + return; break; case 11: - // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... - printTypedVectorList(MI, 0, O, 1, 'd', MRI); - SStream_concat0(O, ", ["); + // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... + printOperand(MI, 1, O); + break; + case 12: + // CASPALW, CASPAW, CASPLW, CASPW + printGPRSeqPairsClassOperand(MI, 1, O, 32); + SStream_concat0(O, ", "); + printGPRSeqPairsClassOperand(MI, 2, O, 32); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 3, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; - case 12: - // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 1, 'd', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); - set_mem_access(MI, false); - break; case 13: - // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... - printTypedVectorList(MI, 0, O, 2, 'd', MRI); - SStream_concat0(O, ", ["); + // CASPALX, CASPAX, CASPLX, CASPX + printGPRSeqPairsClassOperand(MI, 1, O, 64); + SStream_concat0(O, ", "); + printGPRSeqPairsClassOperand(MI, 2, O, 64); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 3, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 14: - // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 2, 'd', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); - set_mem_access(MI, false); + // DMB, DSB, ISB, TSB + printBarrierOption(MI, 0, O); + return; break; case 15: - // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... - printTypedVectorList(MI, 0, O, 2, 's', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + // DUP_ZZI_Q + printSVERegOp(MI, 0, O, 'q'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 1, O, 'q'); + printVectorIndex(MI, 2, O); return; break; case 16: - // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 2, 's', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); - set_mem_access(MI, false); + // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... + printTypedVectorList(MI, 0, O, 0,'d'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 1, O, 0); break; case 17: - // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... - printTypedVectorList(MI, 0, O, 4, 'h', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; + // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... + printTypedVectorList(MI, 0, O, 0,'s'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 1, O, 0); break; case 18: - // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 4, 'h', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); - set_mem_access(MI, false); - break; - case 19: - // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... - printTypedVectorList(MI, 0, O, 4, 's', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + // HINT + printImm(MI, 0, O); return; break; + case 19: + // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RQ_B, LD1RQ_B_IMM, LD2B, LD2B_IMM, ... + printTypedVectorList(MI, 0, O, 0,'b'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 1, O, 0); + break; case 20: - // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 4, 's', MRI); - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); - set_mem_access(MI, false); + // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ... + printTypedVectorList(MI, 0, O, 0,'h'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 1, O, 0); break; case 21: - // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... - printTypedVectorList(MI, 0, O, 8, 'b', MRI); - SStream_concat0(O, ", ["); + // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... + printTypedVectorList(MI, 0, O, 16, 'b'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 22: - // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 8, 'b', MRI); - SStream_concat0(O, ", ["); + // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... + printTypedVectorList(MI, 1, O, 16, 'b'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 23: - // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... - printTypedVectorList(MI, 0, O, 8, 'h', MRI); - SStream_concat0(O, ", ["); + // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... + printTypedVectorList(MI, 0, O, 1, 'd'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 1, O); - SStream_concat0(O, "]"); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 24: - // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... - printTypedVectorList(MI, 1, O, 8, 'h', MRI); - SStream_concat0(O, ", ["); + // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 1, 'd'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 25: - // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... - printTypedVectorList(MI, 1, O, 0, 'h', MRI); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", ["); + // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... + printTypedVectorList(MI, 0, O, 2, 'd'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 3, O); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; break; case 26: - // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST - printTypedVectorList(MI, 2, O, 0, 'h', MRI); - printVectorIndex(MI, 3, O); - SStream_concat0(O, ", ["); + // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 2, 'd'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 4, O); - SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 27: - // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... - printTypedVectorList(MI, 1, O, 0, 's', MRI); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", ["); + // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... + printTypedVectorList(MI, 0, O, 2, 's'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 3, O); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; break; case 28: - // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST - printTypedVectorList(MI, 2, O, 0, 's', MRI); - printVectorIndex(MI, 3, O); - SStream_concat0(O, ", ["); + // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 2, 's'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 4, O); - SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 29: - // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... - printTypedVectorList(MI, 1, O, 0, 'd', MRI); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", ["); + // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... + printTypedVectorList(MI, 0, O, 4, 'h'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 3, O); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; break; case 30: - // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST - printTypedVectorList(MI, 2, O, 0, 'd', MRI); - printVectorIndex(MI, 3, O); - SStream_concat0(O, ", ["); + // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 4, 'h'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 4, O); - SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 31: - // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... - printTypedVectorList(MI, 1, O, 0, 'b', MRI); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", ["); + // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... + printTypedVectorList(MI, 0, O, 4, 's'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 3, O); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; break; case 32: - // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST - printTypedVectorList(MI, 2, O, 0, 'b', MRI); - printVectorIndex(MI, 3, O); - SStream_concat0(O, ", ["); + // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 4, 's'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 4, O); - SStream_concat0(O, "], "); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); break; case 33: - // MSR - printMSRSystemRegister(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); + // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... + printTypedVectorList(MI, 0, O, 8, 'b'); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); return; break; case 34: - // MSRpstate - printSystemPStateField(MI, 0, O); - SStream_concat0(O, ", "); - printOperand(MI, 1, O); - return; + // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 8, 'b'); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); break; case 35: - // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi - printPrefetchOp(MI, 0, O); + // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... + printTypedVectorList(MI, 0, O, 8, 'h'); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 1, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; break; case 36: - // ST1i16, ST2i16, ST3i16, ST4i16 - printTypedVectorList(MI, 0, O, 0, 'h', MRI); - printVectorIndex(MI, 1, O); - SStream_concat0(O, ", ["); + // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... + printTypedVectorList(MI, 1, O, 8, 'h'); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "]"); + printOperand(MI, 2, O); + SStream_concat0(O, "], "); set_mem_access(MI, false); - return; break; case 37: - // ST1i32, ST2i32, ST3i32, ST4i32 - printTypedVectorList(MI, 0, O, 0, 's', MRI); - printVectorIndex(MI, 1, O); - SStream_concat0(O, ", ["); + // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... + printTypedVectorList(MI, 1, O, 0, 'h'); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; + printOperand(MI, 3, O); break; case 38: - // ST1i64, ST2i64, ST3i64, ST4i64 - printTypedVectorList(MI, 0, O, 0, 'd', MRI); - printVectorIndex(MI, 1, O); - SStream_concat0(O, ", ["); + // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST + printTypedVectorList(MI, 2, O, 0, 'h'); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "]"); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 39: + // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... + printTypedVectorList(MI, 1, O, 0, 's'); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 40: + // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST + printTypedVectorList(MI, 2, O, 0, 's'); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 41: + // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... + printTypedVectorList(MI, 1, O, 0, 'd'); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 42: + // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST + printTypedVectorList(MI, 2, O, 0, 'd'); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 43: + // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... + printTypedVectorList(MI, 1, O, 0, 'b'); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 3, O); + break; + case 44: + // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST + printTypedVectorList(MI, 2, O, 0, 'b'); + printVectorIndex(MI, 3, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 4, O); + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 45: + // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI + printSVERegOp(MI, 0, O, 0); + break; + case 46: + // MSR + printMSRSystemRegister(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 47: + // MSRpstateImm1, MSRpstateImm4 + printSystemPStateField(MI, 0, O); + SStream_concat0(O, ", "); + printOperand(MI, 1, O); + return; + break; + case 48: + // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... + printPrefetchOp(MI, 0, O, true); + SStream_concat0(O, ", "); + printSVERegOp(MI, 1, O, 0); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + break; + case 49: + // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi + printPrefetchOp(MI, 0, O, false); + break; + case 50: + // ST1i16, ST2i16, ST3i16, ST4i16 + printTypedVectorList(MI, 0, O, 0, 'h'); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; - case 39: - // ST1i8, ST2i8, ST3i8, ST4i8 - printTypedVectorList(MI, 0, O, 0, 'b', MRI); - printVectorIndex(MI, 1, O); - SStream_concat0(O, ", ["); + case 51: + // ST1i32, ST2i32, ST3i32, ST4i32 + printTypedVectorList(MI, 0, O, 0, 's'); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 2, O); - SStream_concat0(O, "]"); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 52: + // ST1i64, ST2i64, ST3i64, ST4i64 + printTypedVectorList(MI, 0, O, 0, 'd'); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 53: + // ST1i8, ST2i8, ST3i8, ST4i8 + printTypedVectorList(MI, 0, O, 0, 'b'); + printVectorIndex(MI, 1, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; } - // Fragment 1 encoded into 6 bits for 41 unique commands. - //printf("Frag-1: %"PRIu64"\n", (Bits >> 18) & 63); - switch ((Bits >> 18) & 63) { - default: // unreachable. + // Fragment 1 encoded into 6 bits for 56 unique commands. + // printf("Fragment 1: %"PRIu64"\n", ((Bits >> 19) & 63)); + switch ((Bits >> 19) & 63) { + default: // unreachable case 0: - // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... - SStream_concat0(O, ".16b, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv1i64, ADCSWr, ADCSXr, ADCWr, A... + SStream_concat0(O, ", "); break; case 1: - // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPv2i64p, ADDSWri, ADDSWrs, ... - SStream_concat0(O, ", "); + // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, CPY_ZPmI_... + printSVERegOp(MI, 2, O, 0); break; case 2: - // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... - SStream_concat0(O, ".2s, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + // ABSv16i8, ADDHNv8i16_v16i8, ADDPv16i8, ADDv16i8, AESDrr, AESErr, AESIM... + SStream_concat0(O, ".16b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); break; case 3: - // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... - SStream_concat0(O, ".2d, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + // ABSv2i32, ADDHNv2i64_v2i32, ADDPv2i32, ADDv2i32, BICv2i32, CLSv2i32, C... + SStream_concat0(O, ".2s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); break; case 4: - // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... - SStream_concat0(O, ".4h, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + // ABSv2i64, ADDPv2i64, ADDv2i64, CMEQv2i64, CMEQv2i64rz, CMGEv2i64, CMGE... + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); break; case 5: - // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... - SStream_concat0(O, ".4s, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + // ABSv4i16, ADDHNv4i32_v4i16, ADDPv4i16, ADDv4i16, BICv4i16, CLSv4i16, C... + SStream_concat0(O, ".4h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); break; case 6: - // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... - SStream_concat0(O, ".8h, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + // ABSv4i32, ADDHNv2i64_v4i32, ADDPv4i32, ADDv4i32, BICv4i32, CLSv4i32, C... + SStream_concat0(O, ".4s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); break; case 7: - // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... - SStream_concat0(O, ".8b, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + // ABSv8i16, ADDHNv4i32_v8i16, ADDPv8i16, ADDv8i16, BICv8i16, CLSv8i16, C... + SStream_concat0(O, ".8h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); break; case 8: - // BLR, BR, CLREX, RET, TLSDESCCALL - return; + // ABSv8i8, ADDHNv8i16_v8i8, ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8... + SStream_concat0(O, ".8b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); break; case 9: - // FCMPDri, FCMPEDri, FCMPESri, FCMPSri - SStream_concat0(O, ", #0.0"); - arm64_op_addFP(MI, 0.0); - return; + // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, DUP_ZZI_H, FADD_ZZZ_H,... + printSVERegOp(MI, 1, O, 'h'); break; case 10: + // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... + printSVERegOp(MI, 1, O, 0); + break; + case 11: + // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + break; + case 12: + // AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, BRAAZ, BRABZ,... + return; + break; + case 13: + // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... + printSVEPattern(MI, 2, O); + SStream_concat0(O, ", mul "); + printOperand(MI, 3, O); + return; + break; + case 14: + // DUP_ZI_H + printImm8OptLsl32(MI, 1, O); + return; + break; + case 15: + // DUP_ZR_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, WHILELE_PWW_... + printOperand(MI, 1, O); + break; + case 16: + // FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H + printSVERegOp(MI, 2, O, 'h'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 3, O, 'h'); + printVectorIndex(MI, 4, O); + break; + case 17: + // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri + SStream_concat0(O, ", #0.0"); + arm64_op_addFP(MI, 0); + return; + break; + case 18: + // FDUP_ZI_H + printFPImmOperand(MI, 1, O); + return; + break; + case 19: // FMOVXDHighr, INSvi64gpr, INSvi64lane SStream_concat0(O, ".d"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", "); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); break; - case 11: + case 20: + // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... + SStream_concat0(O, "/z, ["); + set_mem_access(MI, true); + break; + case 21: + // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S... + printOperand(MI, 2, O); + break; + case 22: // INSvi16gpr, INSvi16lane SStream_concat0(O, ".h"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); break; - case 12: + case 23: // INSvi32gpr, INSvi32lane SStream_concat0(O, ".s"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); break; - case 13: + case 24: // INSvi8gpr, INSvi8lane SStream_concat0(O, ".b"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); - printVectorIndex(MI, 2, O); - SStream_concat0(O, ", "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B); + printVectorIndex(MI, 2, O); + SStream_concat0(O, ", "); break; - case 14: + case 25: // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... - printPostIncOperand2(MI, 3, O, 64); + printPostIncOperand(MI, 3, O, 64); return; break; - case 15: + case 26: // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... - printPostIncOperand2(MI, 3, O, 32); + printPostIncOperand(MI, 3, O, 32); return; break; - case 16: + case 27: // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... - printPostIncOperand2(MI, 3, O, 16); + printPostIncOperand(MI, 3, O, 16); return; break; - case 17: + case 28: // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... - printPostIncOperand2(MI, 3, O, 8); + printPostIncOperand(MI, 3, O, 8); return; break; - case 18: + case 29: // LD1Rv16b_POST, LD1Rv8b_POST - printPostIncOperand2(MI, 3, O, 1); + printPostIncOperand(MI, 3, O, 1); return; break; - case 19: + case 30: // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... - printPostIncOperand2(MI, 3, O, 4); + printPostIncOperand(MI, 3, O, 4); return; break; - case 20: + case 31: // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST - printPostIncOperand2(MI, 3, O, 2); + printPostIncOperand(MI, 3, O, 2); return; break; - case 21: + case 32: // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... - printPostIncOperand2(MI, 3, O, 48); + printPostIncOperand(MI, 3, O, 48); return; break; - case 22: + case 33: // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... - printPostIncOperand2(MI, 3, O, 24); + printPostIncOperand(MI, 3, O, 24); return; break; - case 23: + case 34: // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... - SStream_concat0(O, "]"); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; - case 24: + case 35: // LD1i16_POST, LD2i8_POST - printPostIncOperand2(MI, 5, O, 2); + printPostIncOperand(MI, 5, O, 2); return; break; - case 25: + case 36: // LD1i32_POST, LD2i16_POST, LD4i8_POST - printPostIncOperand2(MI, 5, O, 4); + printPostIncOperand(MI, 5, O, 4); return; break; - case 26: + case 37: // LD1i64_POST, LD2i32_POST, LD4i16_POST - printPostIncOperand2(MI, 5, O, 8); + printPostIncOperand(MI, 5, O, 8); return; break; - case 27: + case 38: // LD1i8_POST - printPostIncOperand2(MI, 5, O, 1); + printPostIncOperand(MI, 5, O, 1); return; break; - case 28: + case 39: // LD2i64_POST, LD4i32_POST - printPostIncOperand2(MI, 5, O, 16); + printPostIncOperand(MI, 5, O, 16); return; break; - case 29: + case 40: // LD3Rv16b_POST, LD3Rv8b_POST - printPostIncOperand2(MI, 3, O, 3); - return; - break; - case 30: - // LD3Rv2s_POST, LD3Rv4s_POST - printPostIncOperand2(MI, 3, O, 12); - return; - break; - case 31: - // LD3Rv4h_POST, LD3Rv8h_POST - printPostIncOperand2(MI, 3, O, 6); - return; - break; - case 32: - // LD3i16_POST - printPostIncOperand2(MI, 5, O, 6); - return; - break; - case 33: - // LD3i32_POST - printPostIncOperand2(MI, 5, O, 12); - return; - break; - case 34: - // LD3i64_POST - printPostIncOperand2(MI, 5, O, 24); - return; - break; - case 35: - // LD3i8_POST - printPostIncOperand2(MI, 5, O, 3); - return; - break; - case 36: - // LD4i64_POST - printPostIncOperand2(MI, 5, O, 32); - return; - break; - case 37: - // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDRBBpost,... - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - break; - case 38: - // PMULLv1i64, PMULLv2i64 - SStream_concat0(O, ".1q, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); - printVRegOperand(MI, 1, O); - break; - case 39: - // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... - SStream_concat0(O, ".1d, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); - break; - case 40: - // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... - SStream_concat0(O, "], "); - set_mem_access(MI, false); - break; - } - - - // Fragment 2 encoded into 5 bits for 28 unique commands. - //printf("Frag-2: %"PRIu64"\n", (Bits >> 24) & 31); - switch ((Bits >> 24) & 31) { - default: // unreachable. - case 0: - // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... - printVRegOperand(MI, 1, O); - break; - case 1: - // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADD... - printOperand(MI, 1, O); - break; - case 2: - // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... - printVRegOperand(MI, 2, O); - break; - case 3: - // ADRP - printAdrpLabel(MI, 1, O); - return; - break; - case 4: - // BFMWri, BFMXri, FMLAv1i32_indexed, FMLAv1i64_indexed, FMLSv1i32_indexe... - printOperand(MI, 2, O); - break; - case 5: - // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... - printHexImm(MI, 2, O); - printShifter(MI, 3, O); - return; - break; - case 6: - // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... - printAlignedLabel(MI, 1, O); - return; - break; - case 7: - // FMOVDi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_ns, FMOVv4f32_ns - printFPImmOperand(MI, 1, O); - return; - break; - case 8: - // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr - printOperand(MI, 3, O); - return; - break; - case 9: - // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane - printVRegOperand(MI, 3, O); - break; - case 10: - // MOVID, MOVIv2d_ns - printSIMDType10Operand(MI, 1, O); - return; - break; - case 11: - // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... - printHexImm(MI, 1, O); - break; - case 12: - // MRS - printMRSSystemRegister(MI, 1, O); - return; - break; - case 13: - // PMULLv1i64 - SStream_concat0(O, ".1d, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); - printVRegOperand(MI, 2, O); - SStream_concat0(O, ".1d"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); - return; - break; - case 14: - // PMULLv2i64 - SStream_concat0(O, ".2d, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); - printVRegOperand(MI, 2, O); - SStream_concat0(O, ".2d"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); - return; - break; - case 15: - // ST1i16_POST, ST2i8_POST - printPostIncOperand2(MI, 4, O, 2); - return; - break; - case 16: - // ST1i32_POST, ST2i16_POST, ST4i8_POST - printPostIncOperand2(MI, 4, O, 4); - return; - break; - case 17: - // ST1i64_POST, ST2i32_POST, ST4i16_POST - printPostIncOperand2(MI, 4, O, 8); - return; - break; - case 18: - // ST1i8_POST - printPostIncOperand2(MI, 4, O, 1); - return; - break; - case 19: - // ST2i64_POST, ST4i32_POST - printPostIncOperand2(MI, 4, O, 16); - return; - break; - case 20: - // ST3i16_POST - printPostIncOperand2(MI, 4, O, 6); - return; - break; - case 21: - // ST3i32_POST - printPostIncOperand2(MI, 4, O, 12); - return; - break; - case 22: - // ST3i64_POST - printPostIncOperand2(MI, 4, O, 24); - return; - break; - case 23: - // ST3i8_POST - printPostIncOperand2(MI, 4, O, 3); - return; - break; - case 24: - // ST4i64_POST - printPostIncOperand2(MI, 4, O, 32); - return; - break; - case 25: - // SYSxt - printSysCROperand(MI, 1, O); - SStream_concat0(O, ", "); - printSysCROperand(MI, 2, O); - SStream_concat0(O, ", "); - printOperand(MI, 3, O); - SStream_concat0(O, ", "); - printOperand(MI, 4, O); - return; - break; - case 26: - // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... - printTypedVectorList(MI, 1, O, 16, 'b', MRI); - SStream_concat0(O, ", "); - printVRegOperand(MI, 2, O); - break; - case 27: - // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... - printTypedVectorList(MI, 2, O, 16, 'b', MRI); - SStream_concat0(O, ", "); - printVRegOperand(MI, 3, O); - break; - } - - - // Fragment 3 encoded into 6 bits for 42 unique commands. - //printf("Frag-3: %"PRIu64"\n", (Bits >> 29) & 63); - switch ((Bits >> 29) & 63) { - default: // unreachable. - case 0: - // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... - SStream_concat0(O, ".16b"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); - return; - break; - case 1: - // ABSv1i64, ADR, CLSWr, CLSXr, CLZWr, CLZXr, DUPv16i8gpr, DUPv2i32gpr, D... - return; - break; - case 2: - // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... - SStream_concat0(O, ".2s"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); - return; - break; - case 3: - // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... - SStream_concat0(O, ".2d"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); - return; - break; - case 4: - // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FCVTLv4i16, NEGv4i16, REV32v... - SStream_concat0(O, ".4h"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); - return; - break; - case 5: - // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... - SStream_concat0(O, ".4s"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); - return; - break; - case 6: - // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FCVTLv8i16, NEGv8i16, REV32v... - SStream_concat0(O, ".8h"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); - return; - break; - case 7: - // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... - SStream_concat0(O, ".8b"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); - return; - break; - case 8: - // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSWri, ADDSWrs, ADDSWrx, ADDSXri, ADDS... - SStream_concat0(O, ", "); - break; - case 9: - // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... - SStream_concat0(O, ".2d, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); - break; - case 10: - // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... - SStream_concat0(O, ".4s, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); - break; - case 11: - // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... - SStream_concat0(O, ".8h, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); - break; - case 12: - // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... - SStream_concat0(O, ".16b, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); - break; - case 13: - // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... - SStream_concat0(O, ".2s, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); - break; - case 14: - // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... - SStream_concat0(O, ".4h, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); - break; - case 15: - // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... - SStream_concat0(O, ".8b, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); - break; - case 16: - // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz - SStream_concat0(O, ".16b, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); - arm64_op_addFP(MI, 0.0); - return; - break; - case 17: - // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz - SStream_concat0(O, ", #0"); - arm64_op_addImm(MI, 0); - return; - break; - case 18: - // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz - SStream_concat0(O, ".2s, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); - arm64_op_addImm(MI, 0); - return; - break; - case 19: - // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz - SStream_concat0(O, ".2d, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); - arm64_op_addImm(MI, 0); - return; - break; - case 20: - // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz - SStream_concat0(O, ".4h, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); - arm64_op_addImm(MI, 0); - return; - break; - case 21: - // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz - SStream_concat0(O, ".4s, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); - arm64_op_addImm(MI, 0); - return; - break; - case 22: - // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz - SStream_concat0(O, ".8h, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); - arm64_op_addImm(MI, 0); - return; - break; - case 23: - // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz - SStream_concat0(O, ".8b, #0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); - arm64_op_addImm(MI, 0); - return; - break; - case 24: - // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... - SStream_concat0(O, ".h"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); - break; - case 25: - // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... - SStream_concat0(O, ".s"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); - break; - case 26: - // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 - SStream_concat0(O, ".d"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); - break; - case 27: - // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... - SStream_concat0(O, ".b"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_B); - break; - case 28: - // FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i32rz, FCMGEv1i64rz, FCMGTv1i32rz, ... - SStream_concat0(O, ", #0.0"); - arm64_op_addFP(MI, 0.0); - return; - break; - case 29: - // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz - SStream_concat0(O, ".2s, #0.0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); - arm64_op_addFP(MI, 0.0); - return; - break; - case 30: - // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz - SStream_concat0(O, ".2d, #0.0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); - arm64_op_addFP(MI, 0.0); - return; - break; - case 31: - // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz - SStream_concat0(O, ".4s, #0.0"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); - arm64_op_addFP(MI, 0.0); - return; - break; - case 32: - // LDARB, LDARH, LDARW, LDARX, LDAXRB, LDAXRH, LDAXRW, LDAXRX, LDXRB, LDX... - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 33: - // LDAXPW, LDAXPX, LDNPDi, LDNPQi, LDNPSi, LDNPWi, LDNPXi, LDPDi, LDPDpos... - SStream_concat0(O, ", ["); - set_mem_access(MI, true); - break; - case 34: - // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... - SStream_concat0(O, "], "); - set_mem_access(MI, false); - printOperand(MI, 3, O); - return; - break; - case 35: - // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... - printShifter(MI, 2, O); - return; - break; - case 36: - // SHLLv16i8 - SStream_concat0(O, ".16b, #8"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); - arm64_op_addImm(MI, 8); - return; - break; - case 37: - // SHLLv2i32 - SStream_concat0(O, ".2s, #32"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); - arm64_op_addImm(MI, 32); - return; - break; - case 38: - // SHLLv4i16 - SStream_concat0(O, ".4h, #16"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); - arm64_op_addImm(MI, 16); - return; - break; - case 39: - // SHLLv4i32 - SStream_concat0(O, ".4s, #32"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); - arm64_op_addImm(MI, 32); - return; - break; - case 40: - // SHLLv8i16 - SStream_concat0(O, ".8h, #16"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); - arm64_op_addImm(MI, 16); + printPostIncOperand(MI, 3, O, 3); return; break; case 41: - // SHLLv8i8 - SStream_concat0(O, ".8b, #8"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); - arm64_op_addImm(MI, 8); + // LD3Rv2s_POST, LD3Rv4s_POST + printPostIncOperand(MI, 3, O, 12); + return; + break; + case 42: + // LD3Rv4h_POST, LD3Rv8h_POST + printPostIncOperand(MI, 3, O, 6); + return; + break; + case 43: + // LD3i16_POST + printPostIncOperand(MI, 5, O, 6); + return; + break; + case 44: + // LD3i32_POST + printPostIncOperand(MI, 5, O, 12); + return; + break; + case 45: + // LD3i64_POST + printPostIncOperand(MI, 5, O, 24); + return; + break; + case 46: + // LD3i8_POST + printPostIncOperand(MI, 5, O, 3); + return; + break; + case 47: + // LD4i64_POST + printPostIncOperand(MI, 5, O, 32); + return; + break; + case 48: + // PMULLv1i64, PMULLv2i64 + SStream_concat0(O, ".1q, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1Q); + printVRegOperand(MI, 1, O); + break; + case 49: + // PRFB_D_PZI, PRFD_D_PZI, PRFH_D_PZI, PRFW_D_PZI + printSVERegOp(MI, 2, O, 'd'); + SStream_concat0(O, ", "); + break; + case 50: + // PRFB_S_PZI, PRFD_S_PZI, PRFH_S_PZI, PRFW_S_PZI + printSVERegOp(MI, 2, O, 's'); + SStream_concat0(O, ", "); + break; + case 51: + // PTRUES_H, PTRUE_H + printSVEPattern(MI, 1, O); + return; + break; + case 52: + // PUNPKHI_PP, PUNPKLO_PP, SUNPKHI_ZZ_H, SUNPKLO_ZZ_H, UUNPKHI_ZZ_H, UUNP... + printSVERegOp(MI, 1, O, 'b'); + return; + break; + case 53: + // SADALPv2i32_v1i64, SADDLPv2i32_v1i64, UADALPv2i32_v1i64, UADDLPv2i32_v... + SStream_concat0(O, ".1d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + break; + case 54: + // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 55: + // TBL_ZZZ_H + printTypedVectorList(MI, 1, O, 0,'h'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 2, O, 'h'); return; break; } - // Fragment 4 encoded into 5 bits for 18 unique commands. - //printf("Frag-4: %"PRIu64"\n", (Bits >> 35) & 31); - switch ((Bits >> 35) & 31) { - default: // unreachable. + // Fragment 2 encoded into 6 bits for 57 unique commands. + // printf("Fragment 2: %"PRIu64"\n", ((Bits >> 25) & 63)); + switch ((Bits >> 25) & 63) { + default: // unreachable case 0: - // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDSXrx64, ADDXrx64, ADDv1i64, ASRVWr, A... - printOperand(MI, 2, O); + // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... + printSVERegOp(MI, 2, O, 0); break; case 1: - // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... - printVRegOperand(MI, 2, O); + // ABS_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE... + SStream_concat0(O, "/m, "); break; case 2: - // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... - printVRegOperand(MI, 3, O); + // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... + printVRegOperand(MI, 1, O); break; case 3: - // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri - printAddSubImm(MI, 2, O); - return; + // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, A... + printOperand(MI, 1, O); break; case 4: - // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... - printShiftedRegister(MI, 2, O); - return; + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... + printVRegOperand(MI, 2, O); break; case 5: - // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx - printExtendedRegister(MI, 2, O); - return; + // ADD_ZI_B, ADD_ZZZ_B, ASR_WIDE_ZZZ_B, ASR_ZZI_B, DECP_XP_B, DUP_ZZI_B, ... + printSVERegOp(MI, 1, O, 'b'); break; case 6: - // ANDSWri, ANDWri, EORWri, ORRWri - printLogicalImm32(MI, 2, O); - return; + // ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2... + printSVERegOp(MI, 1, O, 'd'); break; case 7: - // ANDSXri, ANDXri, EORXri, ORRXri - printLogicalImm64(MI, 2, O); - return; + // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, CLASTA_ZPZ_H, CLASTB_Z... + SStream_concat0(O, ", "); break; case 8: - // BFMWri, BFMXri, LDPDpost, LDPDpre, LDPQpost, LDPQpre, LDPSWpost, LDPSW... - printOperand(MI, 3, O); + // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... + printSVERegOp(MI, 1, O, 's'); break; case 9: - // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... - printVectorIndex(MI, 2, O); - return; + // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, ANDV_VPZ_B, ANDV_VPZ_D... + printSVERegOp(MI, 1, O, 0); break; case 10: - // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane - printVectorIndex(MI, 4, O); + // ADRP + printAdrpLabel(MI, 1, O); return; break; case 11: - // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui - printUImm12Offset2(MI, 2, O, 1); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; + // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... + printOperand(MI, 2, O); break; case 12: - // LDRDui, LDRXui, PRFMui, STRDui, STRXui - printUImm12Offset2(MI, 2, O, 8); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... + printImm(MI, 2, O); + printShifter(MI, 3, O); return; break; case 13: - // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui - printUImm12Offset2(MI, 2, O, 2); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... + printAlignedLabel(MI, 1, O); return; break; case 14: - // LDRQui, STRQui - printUImm12Offset2(MI, 2, O, 16); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; + // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... + SStream_concat0(O, "/z, "); break; case 15: - // LDRSWui, LDRSui, LDRWui, STRSui, STRWui - printUImm12Offset2(MI, 2, O, 4); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; + // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... + printSVEPattern(MI, 1, O); break; case 16: - // SYSLxt - printSysCROperand(MI, 2, O); - SStream_concat0(O, ", "); - printSysCROperand(MI, 3, O); - SStream_concat0(O, ", "); - printOperand(MI, 4, O); + // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... + printSVEPattern(MI, 2, O); + SStream_concat0(O, ", mul "); + printOperand(MI, 3, O); return; break; case 17: - // TBNZW, TBNZX, TBZW, TBZX - printAlignedLabel(MI, 2, O); + // DECP_XP_H, INCP_XP_H, SQDECP_XPWd_H, SQDECP_XP_H, SQINCP_XPWd_H, SQINC... + printSVERegOp(MI, 1, O, 'h'); + break; + case 18: + // DECP_ZP_H, DUP_ZR_H, FEXPA_ZZ_H, FMLA_ZZZI_H, FMLS_ZZZI_H, FRECPE_ZZ_H... + return; + break; + case 19: + // DUPM_ZI + printLogicalImm64(MI, 1, O); + return; + break; + case 20: + // DUP_ZI_B + printImm8OptLsl32(MI, 1, O); + return; + break; + case 21: + // DUP_ZI_D + printImm8OptLsl64(MI, 1, O); + return; + break; + case 22: + // DUP_ZI_S + printImm8OptLsl32(MI, 1, O); + return; + break; + case 23: + // DUP_ZZI_H + printVectorIndex(MI, 2, O); + return; + break; + case 24: + // FCMLA_ZZZI_S, FMLA_ZZZI_S, FMLS_ZZZI_S, GLD1B_S_IMM_REAL, GLD1H_S_IMM_... + printSVERegOp(MI, 2, O, 's'); + SStream_concat0(O, ", "); + break; + case 25: + // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... + printFPImmOperand(MI, 1, O); + return; + break; + case 26: + // FMLA_ZZZI_D, FMLS_ZZZI_D, GLD1B_D_IMM_REAL, GLD1D_IMM_REAL, GLD1H_D_IM... + printSVERegOp(MI, 2, O, 'd'); + SStream_concat0(O, ", "); + break; + case 27: + // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr, PRFB_D_PZI, PRFB_S_PZI + printOperand(MI, 3, O); + break; + case 28: + // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane + printVRegOperand(MI, 3, O); + break; + case 29: + // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... + printOperand(MI, 0, O); + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + printOperand(MI, 2, O); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 30: + // MOVID, MOVIv2d_ns + printSIMDType10Operand(MI, 1, O); + return; + break; + case 31: + // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... + printImm(MI, 1, O); + break; + case 32: + // MRS + printMRSSystemRegister(MI, 1, O); + return; + break; + case 33: + // PMULLv1i64 + SStream_concat0(O, ".1d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + printVRegOperand(MI, 2, O); + SStream_concat0(O, ".1d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + return; + break; + case 34: + // PMULLv2i64 + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + printVRegOperand(MI, 2, O); + SStream_concat0(O, ".2d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + return; + break; + case 35: + // PRFD_D_PZI, PRFD_S_PZI + printImmScale(MI, 3, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 36: + // PRFH_D_PZI, PRFH_S_PZI + printImmScale(MI, 3, O, 2); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 37: + // PRFW_D_PZI, PRFW_S_PZI + printImmScale(MI, 3, O, 4); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 38: + // SDOT_ZZZI_D, SDOT_ZZZ_D, UDOT_ZZZI_D, UDOT_ZZZ_D + printSVERegOp(MI, 2, O, 'h'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 3, O, 'h'); + break; + case 39: + // SDOT_ZZZI_S, SDOT_ZZZ_S, UDOT_ZZZI_S, UDOT_ZZZ_S + printSVERegOp(MI, 2, O, 'b'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 3, O, 'b'); + break; + case 40: + // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... + printGPR64as32(MI, 1, O); + SStream_concat0(O, ", "); + printSVEPattern(MI, 2, O); + SStream_concat0(O, ", mul "); + printOperand(MI, 3, O); + return; + break; + case 41: + // ST1i16_POST, ST2i8_POST + printPostIncOperand(MI, 4, O, 2); + return; + break; + case 42: + // ST1i32_POST, ST2i16_POST, ST4i8_POST + printPostIncOperand(MI, 4, O, 4); + return; + break; + case 43: + // ST1i64_POST, ST2i32_POST, ST4i16_POST + printPostIncOperand(MI, 4, O, 8); + return; + break; + case 44: + // ST1i8_POST + printPostIncOperand(MI, 4, O, 1); + return; + break; + case 45: + // ST2i64_POST, ST4i32_POST + printPostIncOperand(MI, 4, O, 16); + return; + break; + case 46: + // ST3i16_POST + printPostIncOperand(MI, 4, O, 6); + return; + break; + case 47: + // ST3i32_POST + printPostIncOperand(MI, 4, O, 12); + return; + break; + case 48: + // ST3i64_POST + printPostIncOperand(MI, 4, O, 24); + return; + break; + case 49: + // ST3i8_POST + printPostIncOperand(MI, 4, O, 3); + return; + break; + case 50: + // ST4i64_POST + printPostIncOperand(MI, 4, O, 32); + return; + break; + case 51: + // SYSxt + printSysCROperand(MI, 1, O); + SStream_concat0(O, ", "); + printSysCROperand(MI, 2, O); + SStream_concat0(O, ", "); + printOperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 52: + // TBL_ZZZ_B + printTypedVectorList(MI, 1, O, 0,'b'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 2, O, 'b'); + return; + break; + case 53: + // TBL_ZZZ_D + printTypedVectorList(MI, 1, O, 0,'d'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 2, O, 'd'); + return; + break; + case 54: + // TBL_ZZZ_S + printTypedVectorList(MI, 1, O, 0,'s'); + SStream_concat0(O, ", "); + printSVERegOp(MI, 2, O, 's'); + return; + break; + case 55: + // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... + printTypedVectorList(MI, 1, O, 16, 'b'); + SStream_concat0(O, ", "); + printVRegOperand(MI, 2, O); + break; + case 56: + // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... + printTypedVectorList(MI, 2, O, 16, 'b'); + SStream_concat0(O, ", "); + printVRegOperand(MI, 3, O); + break; + } + + + // Fragment 3 encoded into 7 bits for 91 unique commands. + // printf("Fragment 3: %"PRIu64"\n", ((Bits >> 31) & 127)); + switch ((Bits >> 31) & 127) { + default: // unreachable + case 0: + // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S... + SStream_concat0(O, "/m, "); + break; + case 1: + // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... + printSVERegOp(MI, 3, O, 'h'); + break; + case 2: + // ABSv16i8, ADDVv16i8v, AESDrr, AESErr, AESIMCrr, AESMCrr, CLSv16i8, CLZ... + SStream_concat0(O, ".16b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + return; + break; + case 3: + // ABSv1i64, ADR, AUTDA, AUTDB, AUTIA, AUTIB, BLRAA, BLRAB, BRAA, BRAB, C... + return; + break; + case 4: + // ABSv2i32, CLSv2i32, CLZv2i32, FABSv2f32, FADDPv2i32p, FCVTASv2f32, FCV... + SStream_concat0(O, ".2s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + return; + break; + case 5: + // ABSv2i64, ADDPv2i64p, FABSv2f64, FADDPv2i64p, FCVTASv2f64, FCVTAUv2f64... + SStream_concat0(O, ".2d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + return; + break; + case 6: + // ABSv4i16, ADDVv4i16v, CLSv4i16, CLZv4i16, FABSv4f16, FCVTASv4f16, FCVT... + SStream_concat0(O, ".4h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + return; + break; + case 7: + // ABSv4i32, ADDVv4i32v, CLSv4i32, CLZv4i32, FABSv4f32, FCVTASv4f32, FCVT... + SStream_concat0(O, ".4s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + return; + break; + case 8: + // ABSv8i16, ADDVv8i16v, CLSv8i16, CLZv8i16, FABSv8f16, FCVTASv8f16, FCVT... + SStream_concat0(O, ".8h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + return; + break; + case 9: + // ABSv8i8, ADDVv8i8v, CLSv8i8, CLZv8i8, CNTv8i8, NEGv8i8, NOTv8i8, RBITv... + SStream_concat0(O, ".8b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + return; + break; + case 10: + // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, ADDSWrx, AD... + SStream_concat0(O, ", "); + break; + case 11: + // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + break; + case 12: + // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... + SStream_concat0(O, ".4s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + break; + case 13: + // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... + SStream_concat0(O, ".8h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + break; + case 14: + // ADDPv16i8, ADDv16i8, ANDv16i8, BCAX, BICv16i8, BIFv16i8, BITv16i8, BSL... + SStream_concat0(O, ".16b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + break; + case 15: + // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... + SStream_concat0(O, ".2s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + break; + case 16: + // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... + SStream_concat0(O, ".4h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + break; + case 17: + // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... + SStream_concat0(O, ".8b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + break; + case 18: + // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... + printImm8OptLsl32(MI, 2, O); + return; + break; + case 19: + // ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_... + printSVERegOp(MI, 2, O, 'h'); + break; + case 20: + // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... + SStream_concat0(O, "/z, "); + break; + case 21: + // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H + printSVERegOp(MI, 2, O, 'd'); + return; + break; + case 22: + // ASR_ZZI_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, LSL_ZZI_H, ... + printOperand(MI, 2, O); + return; + break; + case 23: + // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... + SStream_concat0(O, ", ["); + set_mem_access(MI, true); + break; + case 24: + // CMEQv16i8rz, CMGEv16i8rz, CMGTv16i8rz, CMLEv16i8rz, CMLTv16i8rz + SStream_concat0(O, ".16b, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + arm64_op_addImm(MI, 0); + return; + break; + case 25: + // CMEQv1i64rz, CMGEv1i64rz, CMGTv1i64rz, CMLEv1i64rz, CMLTv1i64rz + SStream_concat0(O, ", #0"); + op_addImm(MI, 0); + arm64_op_addImm(MI, 0); + return; + break; + case 26: + // CMEQv2i32rz, CMGEv2i32rz, CMGTv2i32rz, CMLEv2i32rz, CMLTv2i32rz + SStream_concat0(O, ".2s, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + arm64_op_addImm(MI, 0); + return; + break; + case 27: + // CMEQv2i64rz, CMGEv2i64rz, CMGTv2i64rz, CMLEv2i64rz, CMLTv2i64rz + SStream_concat0(O, ".2d, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + arm64_op_addImm(MI, 0); + return; + break; + case 28: + // CMEQv4i16rz, CMGEv4i16rz, CMGTv4i16rz, CMLEv4i16rz, CMLTv4i16rz + SStream_concat0(O, ".4h, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + arm64_op_addImm(MI, 0); + return; + break; + case 29: + // CMEQv4i32rz, CMGEv4i32rz, CMGTv4i32rz, CMLEv4i32rz, CMLTv4i32rz + SStream_concat0(O, ".4s, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + arm64_op_addImm(MI, 0); + return; + break; + case 30: + // CMEQv8i16rz, CMGEv8i16rz, CMGTv8i16rz, CMLEv8i16rz, CMLTv8i16rz + SStream_concat0(O, ".8h, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + arm64_op_addImm(MI, 0); + return; + break; + case 31: + // CMEQv8i8rz, CMGEv8i8rz, CMGTv8i8rz, CMLEv8i8rz, CMLTv8i8rz + SStream_concat0(O, ".8b, #0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + arm64_op_addImm(MI, 0); + return; + break; + case 32: + // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI + SStream_concat0(O, ", mul "); + printOperand(MI, 2, O); + return; + break; + case 33: + // CPY_ZPmI_H + printImm8OptLsl32(MI, 3, O); + return; + break; + case 34: + // CPY_ZPmR_H, CPY_ZPmV_H, GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_I... + printOperand(MI, 3, O); + break; + case 35: + // CPY_ZPzI_H + printImm8OptLsl32(MI, 2, O); + return; + break; + case 36: + // CPYi16, DUPv4i16lane, DUPv8i16lane, INSvi16lane, SMOVvi16to32, SMOVvi1... + SStream_concat0(O, ".h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H); + break; + case 37: + // CPYi32, DUPv2i32lane, DUPv4i32lane, INSvi32lane, SMOVvi32to64, UMOVvi3... + SStream_concat0(O, ".s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); + break; + case 38: + // CPYi64, DUPv2i64lane, FMOVDXHighr, INSvi64lane, UMOVvi64 + SStream_concat0(O, ".d"); + break; + case 39: + // CPYi8, DUPv16i8lane, DUPv8i8lane, INSvi8lane, SMOVvi8to32, SMOVvi8to64... + SStream_concat0(O, ".b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1B); + break; + case 40: + // DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S + printVectorIndex(MI, 2, O); + return; + break; + case 41: + // FADDPv2i16p, FMAXNMPv2i16p, FMAXPv2i16p, FMINNMPv2i16p, FMINPv2i16p + SStream_concat0(O, ".2h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2H); + return; + break; + case 42: + // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMGEv1i16rz, FCMGEv1i32rz, ... + SStream_concat0(O, ", #0.0"); + arm64_op_addFP(MI, 0); + return; + break; + case 43: + // FCMEQv2i32rz, FCMGEv2i32rz, FCMGTv2i32rz, FCMLEv2i32rz, FCMLTv2i32rz + SStream_concat0(O, ".2s, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + arm64_op_addFP(MI, 0); + return; + break; + case 44: + // FCMEQv2i64rz, FCMGEv2i64rz, FCMGTv2i64rz, FCMLEv2i64rz, FCMLTv2i64rz + SStream_concat0(O, ".2d, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + arm64_op_addFP(MI, 0); + return; + break; + case 45: + // FCMEQv4i16rz, FCMGEv4i16rz, FCMGTv4i16rz, FCMLEv4i16rz, FCMLTv4i16rz + SStream_concat0(O, ".4h, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + arm64_op_addFP(MI, 0); + return; + break; + case 46: + // FCMEQv4i32rz, FCMGEv4i32rz, FCMGTv4i32rz, FCMLEv4i32rz, FCMLTv4i32rz + SStream_concat0(O, ".4s, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + arm64_op_addFP(MI, 0); + return; + break; + case 47: + // FCMEQv8i16rz, FCMGEv8i16rz, FCMGTv8i16rz, FCMLEv8i16rz, FCMLTv8i16rz + SStream_concat0(O, ".8h, #0.0"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + arm64_op_addFP(MI, 0); + return; + break; + case 48: + // FCMLA_ZZZI_H + printComplexRotationOp(MI, 5, O, 90, 0); + return; + break; + case 49: + // FCMLA_ZZZI_S, FCVT_ZPmZ_StoH, FMLA_ZZZI_S, FMLS_ZZZI_S, SCVTF_ZPmZ_Sto... + printSVERegOp(MI, 3, O, 's'); + break; + case 50: + // FCPY_ZPmI_H + printFPImmOperand(MI, 3, O); + return; + break; + case 51: + // FCVT_ZPmZ_DtoH, FMLA_ZZZI_D, FMLS_ZZZI_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_... + printSVERegOp(MI, 3, O, 'd'); + break; + case 52: + // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, SST1D_IMM + printImmScale(MI, 3, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 53: + // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... + printImmScale(MI, 3, O, 2); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 54: + // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... + printImmScale(MI, 3, O, 4); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 55: + // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD... + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 56: + // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + printOperand(MI, 3, O); + return; + break; + case 57: + // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... + printShifter(MI, 2, O); + return; + break; + case 58: + // PRFB_D_SCALED + printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 59: + // PRFB_D_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 60: + // PRFB_D_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 61: + // PRFB_PRR + printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 62: + // PRFB_S_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 63: + // PRFB_S_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 64: + // PRFD_D_SCALED + printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 65: + // PRFD_D_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 66: + // PRFD_D_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 67: + // PRFD_PRR + printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 68: + // PRFD_S_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 69: + // PRFD_S_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 70: + // PRFH_D_SCALED + printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 71: + // PRFH_D_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 72: + // PRFH_D_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 73: + // PRFH_PRR + printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 74: + // PRFH_S_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 75: + // PRFH_S_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 76: + // PRFS_PRR + printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 77: + // PRFW_D_SCALED + printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 78: + // PRFW_D_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 79: + // PRFW_D_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 80: + // PRFW_S_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 81: + // PRFW_S_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 82: + // RDFFRS_PPz, RDFFR_PPz + SStream_concat0(O, "/z"); + return; + break; + case 83: + // SDOT_ZZZI_D, SDOT_ZZZI_S, UDOT_ZZZI_D, UDOT_ZZZI_S + printVectorIndex(MI, 4, O); + return; + break; + case 84: + // SHLLv16i8 + SStream_concat0(O, ".16b, #8"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + arm64_op_addImm(MI, 8); + return; + break; + case 85: + // SHLLv2i32 + SStream_concat0(O, ".2s, #32"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + arm64_op_addImm(MI, 32); + return; + break; + case 86: + // SHLLv4i16 + SStream_concat0(O, ".4h, #16"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + arm64_op_addImm(MI, 16); + return; + break; + case 87: + // SHLLv4i32 + SStream_concat0(O, ".4s, #32"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + arm64_op_addImm(MI, 32); + return; + break; + case 88: + // SHLLv8i16 + SStream_concat0(O, ".8h, #16"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + arm64_op_addImm(MI, 16); + return; + break; + case 89: + // SHLLv8i8 + SStream_concat0(O, ".8b, #8"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + arm64_op_addImm(MI, 8); + return; + break; + case 90: + // UMAX_ZI_H, UMIN_ZI_H + printImm(MI, 2, O); return; break; } - // Fragment 5 encoded into 5 bits for 19 unique commands. - //printf("Frag-5: %"PRIu64"\n", (Bits >> 40) & 31); - switch ((Bits >> 40) & 31) { - default: // unreachable. + // Fragment 4 encoded into 7 bits for 88 unique commands. + // printf("Fragment 4: %"PRIu64"\n", ((Bits >> 38) & 127)); + switch ((Bits >> 38) & 127) { + default: // unreachable case 0: - // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDv1i64, ASRVWr, ASRVXr, CMEQv1i64, CMG... + // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, CLZ_ZPmZ_B, CNOT_ZPmZ_B,... + printSVERegOp(MI, 3, O, 'b'); + break; + case 1: + // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... + printSVERegOp(MI, 3, O, 'd'); + break; + case 2: + // ABS_ZPmZ_H, ADD_ZZZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H... + return; + break; + case 3: + // ABS_ZPmZ_S, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPmZ_S, FABS_ZPmZ... + printSVERegOp(MI, 3, O, 's'); + break; + case 4: + // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6... + printOperand(MI, 2, O); + break; + case 5: + // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... + printVRegOperand(MI, 2, O); + break; + case 6: + // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... + printVRegOperand(MI, 3, O); + break; + case 7: + // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri + printAddSubImm(MI, 2, O); + return; + break; + case 8: + // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... + printShiftedRegister(MI, 2, O); + return; + break; + case 9: + // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx + printExtendedRegister(MI, 2, O); + return; + break; + case 10: + // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... + printImm8OptLsl32(MI, 2, O); + return; + break; + case 11: + // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... + printImm8OptLsl64(MI, 2, O); + return; + break; + case 12: + // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... + printImm8OptLsl32(MI, 2, O); + return; + break; + case 13: + // ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, ANDV_VPZ_B, AND_PPzPP, AND_ZPmZ_B, ... + printSVERegOp(MI, 2, O, 'b'); + break; + case 14: + // ADD_ZPmZ_D, ADD_ZZZ_D, ANDV_VPZ_D, AND_ZPmZ_D, AND_ZZZ, ASRD_ZPmI_D, A... + printSVERegOp(MI, 2, O, 'd'); + break; + case 15: + // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... + SStream_concat0(O, ", "); + break; + case 16: + // ADD_ZPmZ_S, ADD_ZZZ_S, ANDV_VPZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ_... + printSVERegOp(MI, 2, O, 's'); + break; + case 17: + // ADR_LSL_ZZZ_D_0 + printRegWithShiftExtend(MI, 2, O, false, 8, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 18: + // ADR_LSL_ZZZ_D_1 + printRegWithShiftExtend(MI, 2, O, false, 16, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 19: + // ADR_LSL_ZZZ_D_2 + printRegWithShiftExtend(MI, 2, O, false, 32, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 20: + // ADR_LSL_ZZZ_D_3 + printRegWithShiftExtend(MI, 2, O, false, 64, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 21: + // ADR_LSL_ZZZ_S_0 + printRegWithShiftExtend(MI, 2, O, false, 8, 'x', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 22: + // ADR_LSL_ZZZ_S_1 + printRegWithShiftExtend(MI, 2, O, false, 16, 'x', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 23: + // ADR_LSL_ZZZ_S_2 + printRegWithShiftExtend(MI, 2, O, false, 32, 'x', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 24: + // ADR_LSL_ZZZ_S_3 + printRegWithShiftExtend(MI, 2, O, false, 64, 'x', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 25: + // ADR_SXTW_ZZZ_D_0 + printRegWithShiftExtend(MI, 2, O, true, 8, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 26: + // ADR_SXTW_ZZZ_D_1 + printRegWithShiftExtend(MI, 2, O, true, 16, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 27: + // ADR_SXTW_ZZZ_D_2 + printRegWithShiftExtend(MI, 2, O, true, 32, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 28: + // ADR_SXTW_ZZZ_D_3 + printRegWithShiftExtend(MI, 2, O, true, 64, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 29: + // ADR_UXTW_ZZZ_D_0 + printRegWithShiftExtend(MI, 2, O, false, 8, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 30: + // ADR_UXTW_ZZZ_D_1 + printRegWithShiftExtend(MI, 2, O, false, 16, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 31: + // ADR_UXTW_ZZZ_D_2 + printRegWithShiftExtend(MI, 2, O, false, 32, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 32: + // ADR_UXTW_ZZZ_D_3 + printRegWithShiftExtend(MI, 2, O, false, 64, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 33: + // ANDSWri, ANDWri, EORWri, ORRWri + printLogicalImm32(MI, 2, O); + return; + break; + case 34: + // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI + printLogicalImm64(MI, 2, O); + return; + break; + case 35: + // ANDV_VPZ_H, CNTP_XPP_H, EORV_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV_... + printSVERegOp(MI, 2, O, 'h'); + return; + break; + case 36: + // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... + printOperand(MI, 3, O); + break; + case 37: + // CPY_ZPmI_B + printImm8OptLsl32(MI, 3, O); + return; + break; + case 38: + // CPY_ZPmI_D + printImm8OptLsl64(MI, 3, O); + return; + break; + case 39: + // CPY_ZPmI_S + printImm8OptLsl32(MI, 3, O); + return; + break; + case 40: + // CPY_ZPzI_B + printImm8OptLsl32(MI, 2, O); + return; + break; + case 41: + // CPY_ZPzI_D + printImm8OptLsl64(MI, 2, O); + return; + break; + case 42: + // CPY_ZPzI_S + printImm8OptLsl32(MI, 2, O); + return; + break; + case 43: + // CPYi16, CPYi32, CPYi64, CPYi8, DUPv16i8lane, DUPv2i32lane, DUPv2i64lan... + printVectorIndex(MI, 2, O); + return; + break; + case 44: + // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... + SStream_concat0(O, ", #0.0"); + arm64_op_addFP(MI, 0); + return; + break; + case 45: + // FCMLA_ZZZI_S, FMLA_ZZZI_D, FMLA_ZZZI_S, FMLS_ZZZI_D, FMLS_ZZZI_S, INSv... + printVectorIndex(MI, 4, O); + break; + case 46: + // FCPY_ZPmI_D, FCPY_ZPmI_S + printFPImmOperand(MI, 3, O); + return; + break; + case 47: + // FCVTZS_ZPmZ_HtoD, FCVTZS_ZPmZ_HtoS, FCVTZU_ZPmZ_HtoD, FCVTZU_ZPmZ_HtoS... + printSVERegOp(MI, 3, O, 'h'); + return; + break; + case 48: + // FMUL_ZZZI_H + printVectorIndex(MI, 3, O); + return; + break; + case 49: + // GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_IMM_REAL, GLD1SB_S_IMM_RE... + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 50: + // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... + printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 51: + // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... + printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 52: + // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... + printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 53: + // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... + printRegWithShiftExtend(MI, 3, O, true, 8, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 54: + // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... + printRegWithShiftExtend(MI, 3, O, false, 8, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 55: + // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED + printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 56: + // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 64, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 57: + // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 64, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 58: + // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... + printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 59: + // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... + printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 60: + // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... + printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 61: + // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... + printRegWithShiftExtend(MI, 3, O, true, 16, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 62: + // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... + printRegWithShiftExtend(MI, 3, O, false, 16, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 63: + // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... + printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 64: + // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... + printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 65: + // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... + printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 'd'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 66: + // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED + printRegWithShiftExtend(MI, 3, O, true, 32, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 67: + // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED + printRegWithShiftExtend(MI, 3, O, false, 32, 'w', 's'); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 68: + // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RQ_B, LD1SB_D, LD1SB_H, LD1SB_S, LD2B... + printRegWithShiftExtend(MI, 3, O, false, 8, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 69: + // LD1D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1D, ST2D, ... + printRegWithShiftExtend(MI, 3, O, false, 64, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 70: + // LD1H, LD1H_D, LD1H_S, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, LD4H, LDF... + printRegWithShiftExtend(MI, 3, O, false, 16, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 71: + // LD1RD_IMM, LDRAAwriteback, LDRABwriteback + printImmScale(MI, 3, O, 8); + break; + case 72: + // LD1RH_D_IMM, LD1RH_IMM, LD1RH_S_IMM, LD1RSH_D_IMM, LD1RSH_S_IMM, LD2B_... + printImmScale(MI, 3, O, 2); + break; + case 73: + // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM + printImmScale(MI, 3, O, 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 74: + // LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_REAL, LDFF... + printRegWithShiftExtend(MI, 3, O, false, 32, 'x', 0); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 75: + // LD1RSW_IMM, LD1RW_D_IMM, LD1RW_IMM, LD4B_IMM, LD4D_IMM, LD4H_IMM, LD4W... + printImmScale(MI, 3, O, 4); + break; + case 76: + // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ... + printImmScale(MI, 3, O, 3); + SStream_concat0(O, ", mul vl]"); + set_mem_access(MI, false); + return; + break; + case 77: + // LDRAAindexed, LDRABindexed + printImmScale(MI, 2, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 78: + // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui + printUImm12Offset(MI, 2, O, 1); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 79: + // LDRDui, LDRXui, PRFMui, STRDui, STRXui + printUImm12Offset(MI, 2, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 80: + // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui + printUImm12Offset(MI, 2, O, 2); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 81: + // LDRQui, STRQui + printUImm12Offset(MI, 2, O, 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 82: + // LDRSWui, LDRSui, LDRWui, STRSui, STRWui + printUImm12Offset(MI, 2, O, 4); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 83: + // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI + SStream_concat0(O, ", mul vl]"); + set_mem_access(MI, false); + return; + break; + case 84: + // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... + printGPR64as32(MI, 2, O); + return; + break; + case 85: + // SYSLxt + printSysCROperand(MI, 2, O); + SStream_concat0(O, ", "); + printSysCROperand(MI, 3, O); + SStream_concat0(O, ", "); + printOperand(MI, 4, O); + return; + break; + case 86: + // TBNZW, TBNZX, TBZW, TBZX + printAlignedLabel(MI, 2, O); + return; + break; + case 87: + // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S + printImm(MI, 2, O); + return; + break; + } + + + // Fragment 5 encoded into 6 bits for 36 unique commands. + // printf("Fragment 5: %"PRIu64"\n", ((Bits >> 45) & 63)); + switch ((Bits >> 45) & 63) { + default: // unreachable + case 0: + // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDP... return; break; case 1: // ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDPv2i64, ADDv2i64, CMEQv2i64, CM... - SStream_concat0(O, ".2d"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + SStream_concat0(O, ".2d"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); return; break; case 2: // ADDHNv4i32_v4i16, ADDHNv4i32_v8i16, ADDPv4i32, ADDv4i32, CMEQv4i32, CM... - SStream_concat0(O, ".4s"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + SStream_concat0(O, ".4s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); return; break; case 3: // ADDHNv8i16_v16i8, ADDHNv8i16_v8i8, ADDPv8i16, ADDv8i16, CMEQv8i16, CMG... - SStream_concat0(O, ".8h"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + SStream_concat0(O, ".8h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); return; break; case 4: // ADDPv16i8, ADDv16i8, ANDv16i8, BICv16i8, BIFv16i8, BITv16i8, BSLv16i8,... - SStream_concat0(O, ".16b"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + SStream_concat0(O, ".16b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); return; break; case 5: // ADDPv2i32, ADDv2i32, CMEQv2i32, CMGEv2i32, CMGTv2i32, CMHIv2i32, CMHSv... - SStream_concat0(O, ".2s"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + SStream_concat0(O, ".2s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); return; break; case 6: // ADDPv4i16, ADDv4i16, CMEQv4i16, CMGEv4i16, CMGTv4i16, CMHIv4i16, CMHSv... - SStream_concat0(O, ".4h"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + SStream_concat0(O, ".4h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); return; break; case 7: // ADDPv8i8, ADDv8i8, ANDv8i8, BICv8i8, BIFv8i8, BITv8i8, BSLv8i8, CMEQv8... - SStream_concat0(O, ".8b"); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + SStream_concat0(O, ".8b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); return; break; case 8: // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 - printArithExtend(MI, 3, O); + printArithExtend(MI, 3, O); return; break; case 9: - // BFMWri, BFMXri, CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi... - SStream_concat0(O, ", "); + // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B,... + SStream_concat0(O, ", "); break; case 10: - // EXTv16i8 - SStream_concat0(O, ".16b, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); - printOperand(MI, 3, O); - return; + // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... + printSVERegOp(MI, 3, O, 'h'); break; case 11: - // EXTv8i8 - SStream_concat0(O, ".8b, "); - arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); - printOperand(MI, 3, O); + // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... + printOperand(MI, 3, O); return; break; case 12: - // FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_indexed, FMLSv1i32_ind... - SStream_concat0(O, ".s"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_S); + // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... + printSVERegOp(MI, 3, O, 'd'); + return; break; case 13: - // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... - SStream_concat0(O, ".d"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_D); + // BCAX, EOR3, EXTv16i8 + SStream_concat0(O, ".16b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); break; case 14: - // LDAXPW, LDAXPX, LDTRBi, LDTRHi, LDTRSBWi, LDTRSBXi, LDTRSHWi, LDTRSHXi... - SStream_concat0(O, "]"); + // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; case 15: - // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... - SStream_concat0(O, "], "); - set_mem_access(MI, false); + // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H + printImm(MI, 3, O); + return; break; case 16: - // LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, LDRHpre, LDRQpre, LDRSBWpre, LDR... - SStream_concat0(O, "]!"); - set_mem_access(MI, false); + // EXTv8i8 + SStream_concat0(O, ".8b, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8B); + printOperand(MI, 3, O); return; break; case 17: - // MLAv4i16_indexed, MLAv8i16_indexed, MLSv4i16_indexed, MLSv8i16_indexed... - SStream_concat0(O, ".h"); - arm64_op_addVectorElementSizeSpecifier(MI, ARM64_VESS_H); + // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H + printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one); + return; break; case 18: + // FCADDv2f32, FCMLAv2f32 + SStream_concat0(O, ".2s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2S); + break; + case 19: + // FCADDv2f64, FCMLAv2f64, XAR + SStream_concat0(O, ".2d, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_2D); + break; + case 20: + // FCADDv4f16, FCMLAv4f16 + SStream_concat0(O, ".4h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4H); + break; + case 21: + // FCADDv4f32, FCMLAv4f32, SM3SS1 + SStream_concat0(O, ".4s, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); + break; + case 22: + // FCADDv8f16, FCMLAv8f16 + SStream_concat0(O, ".8h, "); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_8H); + break; + case 23: + // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... + SStream_concat0(O, ", #0.0"); + arm64_op_addFP(MI, 0); + return; + break; + case 24: + // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,... + printSVERegOp(MI, 4, O, 'h'); + break; + case 25: + // FCMLAv4f16_indexed, FCMLAv8f16_indexed, FMLAv1i16_indexed, FMLAv4i16_i... + SStream_concat0(O, ".h"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1H); + break; + case 26: + // FCMLAv4f32_indexed, FMLAv1i32_indexed, FMLAv2i32_indexed, FMLAv4i32_in... + SStream_concat0(O, ".s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); + break; + case 27: + // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H + printExactFPImm(MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one); + return; + break; + case 28: + // FMLAv1i64_indexed, FMLAv2i64_indexed, FMLSv1i64_indexed, FMLSv2i64_ind... + SStream_concat0(O, ".d"); + break; + case 29: + // FMUL_ZPmI_H + printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two); + return; + break; + case 30: + // FMUL_ZZZI_D, FMUL_ZZZI_S + printVectorIndex(MI, 3, O); + return; + break; + case 31: + // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D... + SStream_concat0(O, ", mul vl]"); + set_mem_access(MI, false); + return; + break; + case 32: + // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... + SStream_concat0(O, "], "); + set_mem_access(MI, false); + break; + case 33: + // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ... + SStream_concat0(O, "]!"); + set_mem_access(MI, false); + return; + break; + case 34: + // SDOTlanev16i8, SDOTlanev8i8, UDOTlanev16i8, UDOTlanev8i8 + SStream_concat0(O, ".4b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4B); + printVectorIndex(MI, 4, O); + return; + break; + case 35: // STLXPW, STLXPX, STXPW, STXPX - SStream_concat0(O, ", ["); + SStream_concat0(O, ", ["); set_mem_access(MI, true); - printOperand(MI, 3, O); - SStream_concat0(O, "]"); + printOperand(MI, 3, O); + SStream_concat0(O, "]"); set_mem_access(MI, false); return; break; } - // Fragment 6 encoded into 5 bits for 21 unique commands. - //printf("Frag-6: %"PRIu64"\n", (Bits >> 45) & 31); - switch ((Bits >> 45) & 31) { - default: // unreachable. + // Fragment 6 encoded into 6 bits for 38 unique commands. + // printf("Fragment 6: %"PRIu64"\n", ((Bits >> 51) & 63)); + switch ((Bits >> 51) & 63) { + default: // unreachable case 0: - // BFMWri, BFMXri - printOperand(MI, 4, O); + // ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_B, ASR_ZPmZ_B... + printSVERegOp(MI, 3, O, 'b'); return; break; case 1: - // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... - printCondCode(MI, 3, O); - return; + // ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR_WIDE_ZPmZ_S,... + printSVERegOp(MI, 3, O, 'd'); break; case 2: - // EXTRWrri, EXTRXrri, FMADDDrrr, FMADDSrrr, FMSUBDrrr, FMSUBSrrr, FNMADD... - printOperand(MI, 3, O); + // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... return; break; case 3: - // FMLAv1i32_indexed, FMLAv1i64_indexed, FMLAv2i32_indexed, FMLAv2i64_ind... - printVectorIndex(MI, 4, O); - return; + // ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ_S, CLASTA_RP... + printSVERegOp(MI, 3, O, 's'); break; case 4: - // FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32_indexed, FMULXv2i64... - printVectorIndex(MI, 3, O); + // ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, ASR_ZPm... + printOperand(MI, 3, O); return; break; case 5: + // BCAX, EOR3, SM3SS1 + printVRegOperand(MI, 3, O); + break; + case 6: + // BFMWri, BFMXri + printOperand(MI, 4, O); + return; + break; + case 7: + // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... + printCondCode(MI, 3, O); + return; + break; + case 8: + // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H, FADDA_VPZ_H + printSVERegOp(MI, 3, O, 'h'); + return; + break; + case 9: + // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... + printImm(MI, 3, O); + return; + break; + case 10: + // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... + printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_one); + return; + break; + case 11: + // FCADD_ZPmZ_H, FCMLA_ZPmZZ_H + SStream_concat0(O, ", "); + break; + case 12: + // FCADDv2f32, FCADDv2f64, FCADDv4f16, FCADDv4f32, FCADDv8f16 + printComplexRotationOp(MI, 3, O, 180, 90); + return; + break; + case 13: + // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... + printSVERegOp(MI, 4, O, 'd'); + break; + case 14: + // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... + printSVERegOp(MI, 4, O, 's'); + break; + case 15: + // FCMLA_ZZZI_S + printComplexRotationOp(MI, 5, O, 90, 0); + return; + break; + case 16: + // FCMLAv2f32, FCMLAv2f64, FCMLAv4f16, FCMLAv4f32, FCMLAv8f16 + printComplexRotationOp(MI, 4, O, 90, 0); + return; + break; + case 17: + // FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv8f16_indexed, FMLAv1i16_... + printVectorIndex(MI, 4, O); + break; + case 18: + // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... + printExactFPImm(MI, 3, O, AArch64ExactFPImm_zero, AArch64ExactFPImm_one); + return; + break; + case 19: + // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... + printVectorIndex(MI, 3, O); + return; + break; + case 20: + // FMUL_ZPmI_D, FMUL_ZPmI_S + printExactFPImm(MI, 3, O, AArch64ExactFPImm_half, AArch64ExactFPImm_two); + return; + break; + case 21: // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi - printImmScale(MI, 3, O, 8); - SStream_concat0(O, "]"); + printImmScale(MI, 3, O, 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 22: + // LDNPQi, LDPQi, STNPQi, STPQi + printImmScale(MI, 3, O, 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 23: + // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi + printImmScale(MI, 3, O, 4); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 24: + // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... + printImmScale(MI, 4, O, 8); + break; + case 25: + // LDPQpost, LDPQpre, STPQpost, STPQpre + printImmScale(MI, 4, O, 16); + break; + case 26: + // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... + printImmScale(MI, 4, O, 4); + break; + case 27: + // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW + printMemExtend(MI, 3, O, 'w', 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 28: + // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX + printMemExtend(MI, 3, O, 'x', 8); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 29: + // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW + printMemExtend(MI, 3, O, 'w', 64); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 30: + // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX + printMemExtend(MI, 3, O, 'x', 64); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 31: + // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW + printMemExtend(MI, 3, O, 'w', 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 32: + // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX + printMemExtend(MI, 3, O, 'x', 16); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 33: + // LDRQroW, STRQroW + printMemExtend(MI, 3, O, 'w', 128); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 34: + // LDRQroX, STRQroX + printMemExtend(MI, 3, O, 'x', 128); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 35: + // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW + printMemExtend(MI, 3, O, 'w', 32); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 36: + // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX + printMemExtend(MI, 3, O, 'x', 32); + SStream_concat0(O, "]"); + set_mem_access(MI, false); + return; + break; + case 37: + // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B + printSVERegOp(MI, 4, O, 'b'); + return; + break; + } + + + // Fragment 7 encoded into 3 bits for 7 unique commands. + // printf("Fragment 7: %"PRIu64"\n", ((Bits >> 57) & 7)); + switch ((Bits >> 57) & 7) { + default: // unreachable + case 0: + // ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ_S, ASRR_ZPmZ_D, ASRR_ZPmZ... + return; + break; + case 1: + // BCAX, EOR3 + SStream_concat0(O, ".16b"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_16B); + return; + break; + case 2: + // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_i... + SStream_concat0(O, ", "); + break; + case 3: + // FCADD_ZPmZ_H + printComplexRotationOp(MI, 4, O, 180, 90); + return; + break; + case 4: + // FCMLA_ZPmZZ_H + printComplexRotationOp(MI, 5, O, 90, 0); + return; + break; + case 5: + // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... + SStream_concat0(O, "]!"); set_mem_access(MI, false); return; break; case 6: - // LDNPQi, LDPQi, STNPQi, STPQi - printImmScale(MI, 3, O, 16); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 7: - // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi - printImmScale(MI, 3, O, 4); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 8: - // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... - printImmScale(MI, 4, O, 8); - break; - case 9: - // LDPQpost, LDPQpre, STPQpost, STPQpre - printImmScale(MI, 4, O, 16); - break; - case 10: - // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... - printImmScale(MI, 4, O, 4); - break; - case 11: - // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW - printMemExtend(MI, 3, O, 'w', 8); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 12: - // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX - printMemExtend(MI, 3, O, 'x', 8); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 13: - // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW - printMemExtend(MI, 3, O, 'w', 64); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 14: - // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX - printMemExtend(MI, 3, O, 'x', 64); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 15: - // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW - printMemExtend(MI, 3, O, 'w', 16); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 16: - // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX - printMemExtend(MI, 3, O, 'x', 16); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 17: - // LDRQroW, STRQroW - printMemExtend(MI, 3, O, 'w', 128); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 18: - // LDRQroX, STRQroX - printMemExtend(MI, 3, O, 'x', 128); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 19: - // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW - printMemExtend(MI, 3, O, 'w', 32); - SStream_concat0(O, "]"); - set_mem_access(MI, false); - return; - break; - case 20: - // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX - printMemExtend(MI, 3, O, 'x', 32); - SStream_concat0(O, "]"); - set_mem_access(MI, false); + // SM3SS1 + SStream_concat0(O, ".4s"); + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_4S); return; break; } - // Fragment 7 encoded into 1 bits for 2 unique commands. - //printf("Frag-7: %"PRIu64"\n", (Bits >> 50) & 1); - if ((Bits >> 50) & 1) { - // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... - SStream_concat0(O, "]!"); - set_mem_access(MI, false); + // Fragment 8 encoded into 1 bits for 2 unique commands. + // printf("Fragment 8: %"PRIu64"\n", ((Bits >> 60) & 1)); + if ((Bits >> 60) & 1) { + // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S, FCMLAv4f16_indexed, FCMLAv4f32_indexed, ... + printComplexRotationOp(MI, 5, O, 90, 0); return; } else { - // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... + // FCADD_ZPmZ_D, FCADD_ZPmZ_S + printComplexRotationOp(MI, 4, O, 180, 90); return; } + } -/// getRegisterName - This method is automatically generated by tblgen -/// from the register set description. This returns the assembler name -/// for the specified register. -static const char *getRegisterName(unsigned RegNo, int AltIdx) -{ - // assert(RegNo && RegNo < 420 && "Invalid register number!"); - -#ifndef CAPSTONE_DIET - static const char AsmStrsNoRegAltName[] = { - /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, - /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, - /* 26 */ 'b', '1', '0', 0, - /* 30 */ 'd', '1', '0', 0, - /* 34 */ 'h', '1', '0', 0, - /* 38 */ 'q', '1', '0', 0, - /* 42 */ 's', '1', '0', 0, - /* 46 */ 'w', '1', '0', 0, - /* 50 */ 'x', '1', '0', 0, - /* 54 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, - /* 70 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, - /* 86 */ 'b', '2', '0', 0, - /* 90 */ 'd', '2', '0', 0, - /* 94 */ 'h', '2', '0', 0, - /* 98 */ 'q', '2', '0', 0, - /* 102 */ 's', '2', '0', 0, - /* 106 */ 'w', '2', '0', 0, - /* 110 */ 'x', '2', '0', 0, - /* 114 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, - /* 130 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, - /* 146 */ 'b', '3', '0', 0, - /* 150 */ 'd', '3', '0', 0, - /* 154 */ 'h', '3', '0', 0, - /* 158 */ 'q', '3', '0', 0, - /* 162 */ 's', '3', '0', 0, - /* 166 */ 'w', '3', '0', 0, - /* 170 */ 'x', '3', '0', 0, - /* 174 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, - /* 189 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, - /* 204 */ 'b', '0', 0, - /* 207 */ 'd', '0', 0, - /* 210 */ 'h', '0', 0, - /* 213 */ 'q', '0', 0, - /* 216 */ 's', '0', 0, - /* 219 */ 'w', '0', 0, - /* 222 */ 'x', '0', 0, - /* 225 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, - /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, - /* 253 */ 'b', '1', '1', 0, - /* 257 */ 'd', '1', '1', 0, - /* 261 */ 'h', '1', '1', 0, - /* 265 */ 'q', '1', '1', 0, - /* 269 */ 's', '1', '1', 0, - /* 273 */ 'w', '1', '1', 0, - /* 277 */ 'x', '1', '1', 0, - /* 281 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, - /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, - /* 313 */ 'b', '2', '1', 0, - /* 317 */ 'd', '2', '1', 0, - /* 321 */ 'h', '2', '1', 0, - /* 325 */ 'q', '2', '1', 0, - /* 329 */ 's', '2', '1', 0, - /* 333 */ 'w', '2', '1', 0, - /* 337 */ 'x', '2', '1', 0, - /* 341 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, - /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, - /* 373 */ 'b', '3', '1', 0, - /* 377 */ 'd', '3', '1', 0, - /* 381 */ 'h', '3', '1', 0, - /* 385 */ 'q', '3', '1', 0, - /* 389 */ 's', '3', '1', 0, - /* 393 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, - /* 407 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, - /* 421 */ 'b', '1', 0, - /* 424 */ 'd', '1', 0, - /* 427 */ 'h', '1', 0, - /* 430 */ 'q', '1', 0, - /* 433 */ 's', '1', 0, - /* 436 */ 'w', '1', 0, - /* 439 */ 'x', '1', 0, - /* 442 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, - /* 457 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, - /* 472 */ 'b', '1', '2', 0, - /* 476 */ 'd', '1', '2', 0, - /* 480 */ 'h', '1', '2', 0, - /* 484 */ 'q', '1', '2', 0, - /* 488 */ 's', '1', '2', 0, - /* 492 */ 'w', '1', '2', 0, - /* 496 */ 'x', '1', '2', 0, - /* 500 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, - /* 516 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, - /* 532 */ 'b', '2', '2', 0, - /* 536 */ 'd', '2', '2', 0, - /* 540 */ 'h', '2', '2', 0, - /* 544 */ 'q', '2', '2', 0, - /* 548 */ 's', '2', '2', 0, - /* 552 */ 'w', '2', '2', 0, - /* 556 */ 'x', '2', '2', 0, - /* 560 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, - /* 573 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, - /* 586 */ 'b', '2', 0, - /* 589 */ 'd', '2', 0, - /* 592 */ 'h', '2', 0, - /* 595 */ 'q', '2', 0, - /* 598 */ 's', '2', 0, - /* 601 */ 'w', '2', 0, - /* 604 */ 'x', '2', 0, - /* 607 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, - /* 623 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, - /* 639 */ 'b', '1', '3', 0, - /* 643 */ 'd', '1', '3', 0, - /* 647 */ 'h', '1', '3', 0, - /* 651 */ 'q', '1', '3', 0, - /* 655 */ 's', '1', '3', 0, - /* 659 */ 'w', '1', '3', 0, - /* 663 */ 'x', '1', '3', 0, - /* 667 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, - /* 683 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, - /* 699 */ 'b', '2', '3', 0, - /* 703 */ 'd', '2', '3', 0, - /* 707 */ 'h', '2', '3', 0, - /* 711 */ 'q', '2', '3', 0, - /* 715 */ 's', '2', '3', 0, - /* 719 */ 'w', '2', '3', 0, - /* 723 */ 'x', '2', '3', 0, - /* 727 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, - /* 739 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, - /* 751 */ 'b', '3', 0, - /* 754 */ 'd', '3', 0, - /* 757 */ 'h', '3', 0, - /* 760 */ 'q', '3', 0, - /* 763 */ 's', '3', 0, - /* 766 */ 'w', '3', 0, - /* 769 */ 'x', '3', 0, - /* 772 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, - /* 788 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, - /* 804 */ 'b', '1', '4', 0, - /* 808 */ 'd', '1', '4', 0, - /* 812 */ 'h', '1', '4', 0, - /* 816 */ 'q', '1', '4', 0, - /* 820 */ 's', '1', '4', 0, - /* 824 */ 'w', '1', '4', 0, - /* 828 */ 'x', '1', '4', 0, - /* 832 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, - /* 848 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, - /* 864 */ 'b', '2', '4', 0, - /* 868 */ 'd', '2', '4', 0, - /* 872 */ 'h', '2', '4', 0, - /* 876 */ 'q', '2', '4', 0, - /* 880 */ 's', '2', '4', 0, - /* 884 */ 'w', '2', '4', 0, - /* 888 */ 'x', '2', '4', 0, - /* 892 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, - /* 904 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, - /* 916 */ 'b', '4', 0, - /* 919 */ 'd', '4', 0, - /* 922 */ 'h', '4', 0, - /* 925 */ 'q', '4', 0, - /* 928 */ 's', '4', 0, - /* 931 */ 'w', '4', 0, - /* 934 */ 'x', '4', 0, - /* 937 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, - /* 953 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, - /* 969 */ 'b', '1', '5', 0, - /* 973 */ 'd', '1', '5', 0, - /* 977 */ 'h', '1', '5', 0, - /* 981 */ 'q', '1', '5', 0, - /* 985 */ 's', '1', '5', 0, - /* 989 */ 'w', '1', '5', 0, - /* 993 */ 'x', '1', '5', 0, - /* 997 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, - /* 1013 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, - /* 1029 */ 'b', '2', '5', 0, - /* 1033 */ 'd', '2', '5', 0, - /* 1037 */ 'h', '2', '5', 0, - /* 1041 */ 'q', '2', '5', 0, - /* 1045 */ 's', '2', '5', 0, - /* 1049 */ 'w', '2', '5', 0, - /* 1053 */ 'x', '2', '5', 0, - /* 1057 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, - /* 1069 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, - /* 1081 */ 'b', '5', 0, - /* 1084 */ 'd', '5', 0, - /* 1087 */ 'h', '5', 0, - /* 1090 */ 'q', '5', 0, - /* 1093 */ 's', '5', 0, - /* 1096 */ 'w', '5', 0, - /* 1099 */ 'x', '5', 0, - /* 1102 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, - /* 1118 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, - /* 1134 */ 'b', '1', '6', 0, - /* 1138 */ 'd', '1', '6', 0, - /* 1142 */ 'h', '1', '6', 0, - /* 1146 */ 'q', '1', '6', 0, - /* 1150 */ 's', '1', '6', 0, - /* 1154 */ 'w', '1', '6', 0, - /* 1158 */ 'x', '1', '6', 0, - /* 1162 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, - /* 1178 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, - /* 1194 */ 'b', '2', '6', 0, - /* 1198 */ 'd', '2', '6', 0, - /* 1202 */ 'h', '2', '6', 0, - /* 1206 */ 'q', '2', '6', 0, - /* 1210 */ 's', '2', '6', 0, - /* 1214 */ 'w', '2', '6', 0, - /* 1218 */ 'x', '2', '6', 0, - /* 1222 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, - /* 1234 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, - /* 1246 */ 'b', '6', 0, - /* 1249 */ 'd', '6', 0, - /* 1252 */ 'h', '6', 0, - /* 1255 */ 'q', '6', 0, - /* 1258 */ 's', '6', 0, - /* 1261 */ 'w', '6', 0, - /* 1264 */ 'x', '6', 0, - /* 1267 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, - /* 1283 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, - /* 1299 */ 'b', '1', '7', 0, - /* 1303 */ 'd', '1', '7', 0, - /* 1307 */ 'h', '1', '7', 0, - /* 1311 */ 'q', '1', '7', 0, - /* 1315 */ 's', '1', '7', 0, - /* 1319 */ 'w', '1', '7', 0, - /* 1323 */ 'x', '1', '7', 0, - /* 1327 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, - /* 1343 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, - /* 1359 */ 'b', '2', '7', 0, - /* 1363 */ 'd', '2', '7', 0, - /* 1367 */ 'h', '2', '7', 0, - /* 1371 */ 'q', '2', '7', 0, - /* 1375 */ 's', '2', '7', 0, - /* 1379 */ 'w', '2', '7', 0, - /* 1383 */ 'x', '2', '7', 0, - /* 1387 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, - /* 1399 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, - /* 1411 */ 'b', '7', 0, - /* 1414 */ 'd', '7', 0, - /* 1417 */ 'h', '7', 0, - /* 1420 */ 'q', '7', 0, - /* 1423 */ 's', '7', 0, - /* 1426 */ 'w', '7', 0, - /* 1429 */ 'x', '7', 0, - /* 1432 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, - /* 1448 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, - /* 1464 */ 'b', '1', '8', 0, - /* 1468 */ 'd', '1', '8', 0, - /* 1472 */ 'h', '1', '8', 0, - /* 1476 */ 'q', '1', '8', 0, - /* 1480 */ 's', '1', '8', 0, - /* 1484 */ 'w', '1', '8', 0, - /* 1488 */ 'x', '1', '8', 0, - /* 1492 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, - /* 1508 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, - /* 1524 */ 'b', '2', '8', 0, - /* 1528 */ 'd', '2', '8', 0, - /* 1532 */ 'h', '2', '8', 0, - /* 1536 */ 'q', '2', '8', 0, - /* 1540 */ 's', '2', '8', 0, - /* 1544 */ 'w', '2', '8', 0, - /* 1548 */ 'x', '2', '8', 0, - /* 1552 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, - /* 1564 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, - /* 1576 */ 'b', '8', 0, - /* 1579 */ 'd', '8', 0, - /* 1582 */ 'h', '8', 0, - /* 1585 */ 'q', '8', 0, - /* 1588 */ 's', '8', 0, - /* 1591 */ 'w', '8', 0, - /* 1594 */ 'x', '8', 0, - /* 1597 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, - /* 1613 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, - /* 1629 */ 'b', '1', '9', 0, - /* 1633 */ 'd', '1', '9', 0, - /* 1637 */ 'h', '1', '9', 0, - /* 1641 */ 'q', '1', '9', 0, - /* 1645 */ 's', '1', '9', 0, - /* 1649 */ 'w', '1', '9', 0, - /* 1653 */ 'x', '1', '9', 0, - /* 1657 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, - /* 1673 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, - /* 1689 */ 'b', '2', '9', 0, - /* 1693 */ 'd', '2', '9', 0, - /* 1697 */ 'h', '2', '9', 0, - /* 1701 */ 'q', '2', '9', 0, - /* 1705 */ 's', '2', '9', 0, - /* 1709 */ 'w', '2', '9', 0, - /* 1713 */ 'x', '2', '9', 0, - /* 1717 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, - /* 1729 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, - /* 1741 */ 'b', '9', 0, - /* 1744 */ 'd', '9', 0, - /* 1747 */ 'h', '9', 0, - /* 1750 */ 'q', '9', 0, - /* 1753 */ 's', '9', 0, - /* 1756 */ 'w', '9', 0, - /* 1759 */ 'x', '9', 0, - /* 1762 */ 'w', 's', 'p', 0, - /* 1766 */ 'w', 'z', 'r', 0, - /* 1770 */ 'x', 'z', 'r', 0, - /* 1774 */ 'n', 'z', 'c', 'v', 0, - }; - - static const uint16_t RegAsmOffsetNoRegAltName[] = { - 1713, 170, 1774, 1763, 1762, 1766, 1770, 204, 421, 586, 751, 916, 1081, 1246, - 1411, 1576, 1741, 26, 253, 472, 639, 804, 969, 1134, 1299, 1464, 1629, 86, - 313, 532, 699, 864, 1029, 1194, 1359, 1524, 1689, 146, 373, 207, 424, 589, - 754, 919, 1084, 1249, 1414, 1579, 1744, 30, 257, 476, 643, 808, 973, 1138, - 1303, 1468, 1633, 90, 317, 536, 703, 868, 1033, 1198, 1363, 1528, 1693, 150, - 377, 210, 427, 592, 757, 922, 1087, 1252, 1417, 1582, 1747, 34, 261, 480, - 647, 812, 977, 1142, 1307, 1472, 1637, 94, 321, 540, 707, 872, 1037, 1202, - 1367, 1532, 1697, 154, 381, 213, 430, 595, 760, 925, 1090, 1255, 1420, 1585, - 1750, 38, 265, 484, 651, 816, 981, 1146, 1311, 1476, 1641, 98, 325, 544, - 711, 876, 1041, 1206, 1371, 1536, 1701, 158, 385, 216, 433, 598, 763, 928, - 1093, 1258, 1423, 1588, 1753, 42, 269, 488, 655, 820, 985, 1150, 1315, 1480, - 1645, 102, 329, 548, 715, 880, 1045, 1210, 1375, 1540, 1705, 162, 389, 219, - 436, 601, 766, 931, 1096, 1261, 1426, 1591, 1756, 46, 273, 492, 659, 824, - 989, 1154, 1319, 1484, 1649, 106, 333, 552, 719, 884, 1049, 1214, 1379, 1544, - 1709, 166, 222, 439, 604, 769, 934, 1099, 1264, 1429, 1594, 1759, 50, 277, - 496, 663, 828, 993, 1158, 1323, 1488, 1653, 110, 337, 556, 723, 888, 1053, - 1218, 1383, 1548, 401, 567, 733, 898, 1063, 1228, 1393, 1558, 1723, 6, 231, - 449, 615, 780, 945, 1110, 1275, 1440, 1605, 62, 289, 508, 675, 840, 1005, - 1170, 1335, 1500, 1665, 122, 349, 182, 727, 892, 1057, 1222, 1387, 1552, 1717, - 0, 225, 442, 607, 772, 937, 1102, 1267, 1432, 1597, 54, 281, 500, 667, - 832, 997, 1162, 1327, 1492, 1657, 114, 341, 174, 393, 560, 564, 730, 895, - 1060, 1225, 1390, 1555, 1720, 3, 228, 445, 611, 776, 941, 1106, 1271, 1436, - 1601, 58, 285, 504, 671, 836, 1001, 1166, 1331, 1496, 1661, 118, 345, 178, - 397, 415, 580, 745, 910, 1075, 1240, 1405, 1570, 1735, 19, 245, 464, 631, - 796, 961, 1126, 1291, 1456, 1621, 78, 305, 524, 691, 856, 1021, 1186, 1351, - 1516, 1681, 138, 365, 197, 739, 904, 1069, 1234, 1399, 1564, 1729, 13, 239, - 457, 623, 788, 953, 1118, 1283, 1448, 1613, 70, 297, 516, 683, 848, 1013, - 1178, 1343, 1508, 1673, 130, 357, 189, 407, 573, 577, 742, 907, 1072, 1237, - 1402, 1567, 1732, 16, 242, 460, 627, 792, 957, 1122, 1287, 1452, 1617, 74, - 301, 520, 687, 852, 1017, 1182, 1347, 1512, 1677, 134, 361, 193, 411, - }; - - static const char AsmStrsvreg[] = { - /* 0 */ 'v', '1', '0', 0, - /* 4 */ 'v', '2', '0', 0, - /* 8 */ 'v', '3', '0', 0, - /* 12 */ 'v', '0', 0, - /* 15 */ 'v', '1', '1', 0, - /* 19 */ 'v', '2', '1', 0, - /* 23 */ 'v', '3', '1', 0, - /* 27 */ 'v', '1', 0, - /* 30 */ 'v', '1', '2', 0, - /* 34 */ 'v', '2', '2', 0, - /* 38 */ 'v', '2', 0, - /* 41 */ 'v', '1', '3', 0, - /* 45 */ 'v', '2', '3', 0, - /* 49 */ 'v', '3', 0, - /* 52 */ 'v', '1', '4', 0, - /* 56 */ 'v', '2', '4', 0, - /* 60 */ 'v', '4', 0, - /* 63 */ 'v', '1', '5', 0, - /* 67 */ 'v', '2', '5', 0, - /* 71 */ 'v', '5', 0, - /* 74 */ 'v', '1', '6', 0, - /* 78 */ 'v', '2', '6', 0, - /* 82 */ 'v', '6', 0, - /* 85 */ 'v', '1', '7', 0, - /* 89 */ 'v', '2', '7', 0, - /* 93 */ 'v', '7', 0, - /* 96 */ 'v', '1', '8', 0, - /* 100 */ 'v', '2', '8', 0, - /* 104 */ 'v', '8', 0, - /* 107 */ 'v', '1', '9', 0, - /* 111 */ 'v', '2', '9', 0, - /* 115 */ 'v', '9', 0, - }; - - static const uint16_t RegAsmOffsetvreg[] = { - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, - 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, - 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, - 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, - 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, - 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, - 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, - 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, - 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, - 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, - 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, - 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, - 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, - 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, - 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, - 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, - 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, - 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, - 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, - }; - - const uint16_t *RegAsmOffset; - const char *AsmStrs; - - switch(AltIdx) { - default: // llvm_unreachable("Invalid register alt name index!"); - case AArch64_NoRegAltName: - AsmStrs = AsmStrsNoRegAltName; - RegAsmOffset = RegAsmOffsetNoRegAltName; - break; - case AArch64_vreg: - AsmStrs = AsmStrsvreg; - RegAsmOffset = RegAsmOffsetvreg; - break; - } - //int i; - //for (i = 0; i < sizeof(RegAsmOffsetNoRegAltName)/2; i++) - // printf("%s = %u\n", AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[i], i + 1); - //printf("*************************\n"); - //for (i = 0; i < sizeof(RegAsmOffsetvreg)/2; i++) - // printf("%s = %u\n", AsmStrsvreg+RegAsmOffsetvreg[i], i + 1); - //printf("-------------------------\n"); - return AsmStrs+RegAsmOffset[RegNo-1]; -#else - return NULL; -#endif -} #ifdef PRINT_ALIAS_INSTR #undef PRINT_ALIAS_INSTR -static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, SStream *OS, MCRegisterInfo *MRI) -{ - // printf(">>>> Method: %u, opIdx: %x\n", PrintMethodIdx, OpIdx); - switch (PrintMethodIdx) { - default: - // llvm_unreachable("Unknown PrintMethod kind"); - break; - case 0: - printAddSubImm(MI, OpIdx, OS); - break; - case 1: - printShifter(MI, OpIdx, OS); - break; - case 2: - printArithExtend(MI, OpIdx, OS); - break; - case 3: - printLogicalImm32(MI, OpIdx, OS); - break; - case 4: - printLogicalImm64(MI, OpIdx, OS); - break; - case 5: - printVRegOperand(MI, OpIdx, OS); - break; - case 6: - printHexImm(MI, OpIdx, OS); - break; - case 7: - printInverseCondCode(MI, OpIdx, OS); - break; - case 8: - printVectorIndex(MI, OpIdx, OS); - break; - case 9: - printTypedVectorList(MI, OpIdx, OS, 16, 'b', MRI); - break; - case 10: - printTypedVectorList(MI, OpIdx, OS, 1, 'd', MRI); - break; - case 11: - printTypedVectorList(MI, OpIdx, OS, 2, 'd', MRI); - break; - case 12: - printTypedVectorList(MI, OpIdx, OS, 2, 's', MRI); - break; - case 13: - printTypedVectorList(MI, OpIdx, OS, 4, 'h', MRI); - break; - case 14: - printTypedVectorList(MI, OpIdx, OS, 4, 's', MRI); - break; - case 15: - printTypedVectorList(MI, OpIdx, OS, 8, 'b', MRI); - break; - case 16: - printTypedVectorList(MI, OpIdx, OS, 8, 'h', MRI); - break; - case 17: - printTypedVectorList(MI, OpIdx, OS, 0, 'h', MRI); - break; - case 18: - printTypedVectorList(MI, OpIdx, OS, 0, 's', MRI); - break; - case 19: - printTypedVectorList(MI, OpIdx, OS, 0, 'd', MRI); - break; - case 20: - printTypedVectorList(MI, OpIdx, OS, 0, 'b', MRI); - break; - case 21: - printPrefetchOp(MI, OpIdx, OS); - break; - case 22: - printSysCROperand(MI, OpIdx, OS); - break; - } -} - -static bool AArch64InstPrinterValidateMCOperand( - MCOperand *MCOp, unsigned PredicateIndex) -{ - switch (PredicateIndex) { - default: - // llvm_unreachable("Unknown MCOperandPredicate kind"); - case 1: { - return (MCOperand_isImm(MCOp) && - MCOperand_getImm(MCOp) != ARM64_CC_AL && - MCOperand_getImm(MCOp) != ARM64_CC_NV); - } - } -} - -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) +static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, + unsigned PredicateIndex); +static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI) { #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg))) + unsigned int I = 0, OpIdx, PrintMethodIdx; + char *tmpString; const char *AsmString; - char *tmp, *AsmMnem, *AsmOps, *c; - int OpIdx, PrintMethodIdx; - MCRegisterInfo *MRI = (MCRegisterInfo *)info; switch (MCInst_getOpcode(MI)) { - default: return NULL; + default: return false; case AArch64_ADDSWri: if (MCInst_getNumOperands(MI) == 4 && MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - AsmString = "cmn $\x02, $\xFF\x03\x01"; + AsmString = "cmn $\x02, $\xFF\x03\x01"; break; } return NULL; @@ -7106,7 +12490,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - AsmString = "cmn $\x02, $\x03"; + AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7116,7 +12500,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; + AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7129,7 +12513,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "adds $\x01, $\x02, $\x03"; + AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; @@ -7143,7 +12527,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - AsmString = "cmn $\x02, $\x03"; + AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7153,7 +12537,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; + AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7166,7 +12550,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - AsmString = "adds $\x01, $\x02, $\x03"; + AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; @@ -7176,7 +12560,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - AsmString = "cmn $\x02, $\xFF\x03\x01"; + AsmString = "cmn $\x02, $\xFF\x03\x01"; break; } return NULL; @@ -7190,7 +12574,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - AsmString = "cmn $\x02, $\x03"; + AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7200,7 +12584,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; + AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7213,7 +12597,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "adds $\x01, $\x02, $\x03"; + AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; @@ -7225,7 +12609,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; + AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; break; } return NULL; @@ -7239,7 +12623,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - AsmString = "cmn $\x02, $\x03"; + AsmString = "cmn $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7249,7 +12633,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; + AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7262,7 +12646,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - AsmString = "adds $\x01, $\x02, $\x03"; + AsmString = "adds $\x01, $\x02, $\x03"; break; } return NULL; @@ -7305,7 +12689,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "add $\x01, $\x02, $\x03"; + AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; @@ -7320,7 +12704,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - AsmString = "add $\x01, $\x02, $\x03"; + AsmString = "add $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7333,7 +12717,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - AsmString = "add $\x01, $\x02, $\x03"; + AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; @@ -7376,7 +12760,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "add $\x01, $\x02, $\x03"; + AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; @@ -7391,7 +12775,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - AsmString = "add $\x01, $\x02, $\x03"; + AsmString = "add $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7404,7 +12788,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - AsmString = "add $\x01, $\x02, $\x03"; + AsmString = "add $\x01, $\x02, $\x03"; break; } return NULL; @@ -7451,7 +12835,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "ands $\x01, $\x02, $\x03"; + AsmString = "ands $\x01, $\x02, $\x03"; break; } return NULL; @@ -7498,7 +12882,23 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "ands $\x01, $\x02, $\x03"; + AsmString = "ands $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ANDS_PPzPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 2)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) + AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; break; } return NULL; @@ -7513,7 +12913,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "and $\x01, $\x02, $\x03"; + AsmString = "and $\x01, $\x02, $\x03"; break; } return NULL; @@ -7528,7 +12928,52 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "and $\x01, $\x02, $\x03"; + AsmString = "and $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_AND_PPzPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 2)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; + break; + } + return NULL; + case AArch64_AND_ZI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) + AsmString = "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) + AsmString = "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) + AsmString = "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; break; } return NULL; @@ -7543,7 +12988,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "bics $\x01, $\x02, $\x03"; + AsmString = "bics $\x01, $\x02, $\x03"; break; } return NULL; @@ -7558,7 +13003,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "bics $\x01, $\x02, $\x03"; + AsmString = "bics $\x01, $\x02, $\x03"; break; } return NULL; @@ -7573,7 +13018,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "bic $\x01, $\x02, $\x03"; + AsmString = "bic $\x01, $\x02, $\x03"; break; } return NULL; @@ -7588,51 +13033,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "bic $\x01, $\x02, $\x03"; - break; - } - return NULL; - case AArch64_BICv2i32: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (BICv2i32 V64:$Vd, imm0_255:$imm, 0) - AsmString = "bic $\xFF\x01\x06.2s, $\xFF\x02\x07"; - break; - } - return NULL; - case AArch64_BICv4i16: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (BICv4i16 V64:$Vd, imm0_255:$imm, 0) - AsmString = "bic $\xFF\x01\x06.4h, $\xFF\x02\x07"; - break; - } - return NULL; - case AArch64_BICv4i32: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (BICv4i32 V128:$Vd, imm0_255:$imm, 0) - AsmString = "bic $\xFF\x01\x06.4s, $\xFF\x02\x07"; - break; - } - return NULL; - case AArch64_BICv8i16: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (BICv8i16 V128:$Vd, imm0_255:$imm, 0) - AsmString = "bic $\xFF\x01\x06.8h, $\xFF\x02\x07"; + AsmString = "bic $\x01, $\x02, $\x03"; break; } return NULL; @@ -7645,15 +13046,319 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) break; } return NULL; + case AArch64_CNTB_XPiI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) + AsmString = "cntb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) + AsmString = "cntb $\x01, $\xFF\x02\x0E"; + break; + } + return NULL; + case AArch64_CNTD_XPiI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) + AsmString = "cntd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) + AsmString = "cntd $\x01, $\xFF\x02\x0E"; + break; + } + return NULL; + case AArch64_CNTH_XPiI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) + AsmString = "cnth $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) + AsmString = "cnth $\x01, $\xFF\x02\x0E"; + break; + } + return NULL; + case AArch64_CNTW_XPiI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) + AsmString = "cntw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) + AsmString = "cntw $\x01, $\xFF\x02\x0E"; + break; + } + return NULL; + case AArch64_CPY_ZPmI_B: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) + AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F"; + break; + } + return NULL; + case AArch64_CPY_ZPmI_D: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) + AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11"; + break; + } + return NULL; + case AArch64_CPY_ZPmI_H: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) + AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12"; + break; + } + return NULL; + case AArch64_CPY_ZPmI_S: + if (MCInst_getNumOperands(MI) == 5 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13"; + break; + } + return NULL; + case AArch64_CPY_ZPmR_B: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) + AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmR_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) + AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmR_H: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) + AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmR_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmV_B: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR8RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) + AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmV_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) + AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmV_H: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR16RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) + AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPmV_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR32RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; + break; + } + return NULL; + case AArch64_CPY_ZPzI_B: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F"; + break; + } + return NULL; + case AArch64_CPY_ZPzI_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11"; + break; + } + return NULL; + case AArch64_CPY_ZPzI_H: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) + AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12"; + break; + } + return NULL; + case AArch64_CPY_ZPzI_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13"; + break; + } + return NULL; case AArch64_CSINCWr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - AsmString = "cset $\x01, $\xFF\x04\x08"; + AsmString = "cset $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7663,9 +13368,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; + AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; @@ -7675,9 +13380,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - AsmString = "cset $\x01, $\xFF\x04\x08"; + AsmString = "cset $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7687,9 +13392,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - AsmString = "cinc $\x01, $\x02, $\xFF\x04\x08"; + AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; @@ -7699,9 +13404,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_WZR && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) - AsmString = "csetm $\x01, $\xFF\x04\x08"; + AsmString = "csetm $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7711,9 +13416,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; + AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; @@ -7723,9 +13428,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_XZR && MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) - AsmString = "csetm $\x01, $\xFF\x04\x08"; + AsmString = "csetm $\x01, $\xFF\x04\x14"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -7735,9 +13440,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - AsmString = "cinv $\x01, $\x02, $\xFF\x04\x08"; + AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; @@ -7749,9 +13454,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) - AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; + AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; @@ -7763,9 +13468,9 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && - AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 1)) { + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 3), 4)) { // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) - AsmString = "cneg $\x01, $\x02, $\xFF\x04\x08"; + AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; break; } return NULL; @@ -7796,6 +13501,474 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) break; } return NULL; + case AArch64_DECB_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "decb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "decb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DECD_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "decd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "decd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DECD_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "decd $\xFF\x01\x10"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "decd $\xFF\x01\x10, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DECH_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "dech $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "dech $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DECH_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "dech $\xFF\x01\x09"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "dech $\xFF\x01\x09, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DECW_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "decw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "decw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DECW_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "decw $\xFF\x01\x0B"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "decw $\xFF\x01\x0B, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_DUPM_ZI: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 5) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) + AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x15"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 6) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x16"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 7) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x17"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) + AsmString = "dupm $\xFF\x01\x06, $\xFF\x02\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) + AsmString = "dupm $\xFF\x01\x09, $\xFF\x02\x0A"; + break; + } + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 1), 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) + AsmString = "dupm $\xFF\x01\x0B, $\xFF\x02\x04"; + break; + } + return NULL; + case AArch64_DUP_ZI_B: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x0F"; + break; + } + return NULL; + case AArch64_DUP_ZI_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x11"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_D ZPR64:$Zd, 0, 0) + AsmString = "fmov $\xFF\x01\x10, #0.0"; + break; + } + return NULL; + case AArch64_DUP_ZI_H: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) + AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x12"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_H ZPR16:$Zd, 0, 0) + AsmString = "fmov $\xFF\x01\x09, #0.0"; + break; + } + return NULL; + case AArch64_DUP_ZI_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x13"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZI_S ZPR32:$Zd, 0, 0) + AsmString = "fmov $\xFF\x01\x0B, #0.0"; + break; + } + return NULL; + case AArch64_DUP_ZR_B: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) + AsmString = "mov $\xFF\x01\x06, $\x02"; + break; + } + return NULL; + case AArch64_DUP_ZR_D: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) + AsmString = "mov $\xFF\x01\x10, $\x02"; + break; + } + return NULL; + case AArch64_DUP_ZR_H: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) + AsmString = "mov $\xFF\x01\x09, $\x02"; + break; + } + return NULL; + case AArch64_DUP_ZR_S: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) + AsmString = "mov $\xFF\x01\x0B, $\x02"; + break; + } + return NULL; + case AArch64_DUP_ZZI_B: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x18"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19"; + break; + } + return NULL; + case AArch64_DUP_ZZI_D: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x1A"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19"; + break; + } + return NULL; + case AArch64_DUP_ZZI_H: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) + AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x1B"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) + AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19"; + break; + } + return NULL; + case AArch64_DUP_ZZI_Q: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) + AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1D"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) + AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19"; + break; + } + return NULL; + case AArch64_DUP_ZZI_S: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x1E"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19"; + break; + } + return NULL; case AArch64_EONWrs: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -7807,7 +13980,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "eon $\x01, $\x02, $\x03"; + AsmString = "eon $\x01, $\x02, $\x03"; break; } return NULL; @@ -7822,7 +13995,23 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "eon $\x01, $\x02, $\x03"; + AsmString = "eon $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_EORS_PPzPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) + AsmString = "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; break; } return NULL; @@ -7837,7 +14026,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "eor $\x01, $\x02, $\x03"; + AsmString = "eor $\x01, $\x02, $\x03"; break; } return NULL; @@ -7852,7 +14041,52 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "eor $\x01, $\x02, $\x03"; + AsmString = "eor $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_EOR_PPzPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) + AsmString = "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; + break; + } + return NULL; + case AArch64_EOR_ZI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) + AsmString = "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) + AsmString = "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) + AsmString = "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; break; } return NULL; @@ -7882,6 +14116,456 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) break; } return NULL; + case AArch64_FCPY_ZPmI_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) + AsmString = "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F"; + break; + } + return NULL; + case AArch64_FCPY_ZPmI_H: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) + AsmString = "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F"; + break; + } + return NULL; + case AArch64_FCPY_ZPmI_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) + AsmString = "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F"; + break; + } + return NULL; + case AArch64_FDUP_ZI_D: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) + AsmString = "fmov $\xFF\x01\x10, $\xFF\x02\x1F"; + break; + } + return NULL; + case AArch64_FDUP_ZI_H: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) + AsmString = "fmov $\xFF\x01\x09, $\xFF\x02\x1F"; + break; + } + return NULL; + case AArch64_FDUP_ZI_S: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) + AsmString = "fmov $\xFF\x01\x0B, $\xFF\x02\x1F"; + break; + } + return NULL; + case AArch64_GLD1B_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1B_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLD1D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1H_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1H_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLD1SB_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1SB_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLD1SH_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1SH_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLD1SW_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1W_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLD1W_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLDFF1B_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1B_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLDFF1D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1H_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1H_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLDFF1SB_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1SB_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLDFF1SH_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1SH_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_GLDFF1SW_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1W_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_GLDFF1W_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; + break; + } + return NULL; case AArch64_HINT: if (MCInst_getNumOperands(MI) == 1 && MCOperand_isImm(MCInst_getOperand(MI, 0)) && @@ -7925,92 +14609,290 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) AsmString = "sevl"; break; } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 16 && + AArch64_getFeatureBits(AArch64_FeatureRAS)) { + // (HINT { 1, 0, 0, 0, 0 }) + AsmString = "esb"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + MCOperand_isImm(MCInst_getOperand(MI, 0)) && + MCOperand_getImm(MCInst_getOperand(MI, 0)) == 20) { + // (HINT 20) + AsmString = "csdb"; + break; + } + if (MCInst_getNumOperands(MI) == 1 && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 0), 8) && + AArch64_getFeatureBits(AArch64_FeatureSPE)) { + // (HINT psbhint_op:$op) + AsmString = "psb $\xFF\x01\x22"; + break; + } + return NULL; + case AArch64_INCB_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "incb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "incb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_INCD_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "incd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "incd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_INCD_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "incd $\xFF\x01\x10"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "incd $\xFF\x01\x10, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_INCH_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "inch $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "inch $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_INCH_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "inch $\xFF\x01\x09"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "inch $\xFF\x01\x09, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_INCW_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "incw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "incw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_INCW_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "incw $\xFF\x01\x0B"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "incw $\xFF\x01\x0B, $\xFF\x03\x0E"; + break; + } return NULL; case AArch64_INSvi16gpr: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) - AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\x03"; + AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi16lane: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) - AsmString = "mov $\xFF\x01\x06.h$\xFF\x02\x09, $\xFF\x03\x06.h$\xFF\x04\x09"; + AsmString = "mov $\xFF\x01\x0C.h$\xFF\x03\x19, $\xFF\x04\x0C.h$\xFF\x05\x19"; break; } return NULL; case AArch64_INSvi32gpr: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) - AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\x03"; + AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi32lane: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) - AsmString = "mov $\xFF\x01\x06.s$\xFF\x02\x09, $\xFF\x03\x06.s$\xFF\x04\x09"; + AsmString = "mov $\xFF\x01\x0C.s$\xFF\x03\x19, $\xFF\x04\x0C.s$\xFF\x05\x19"; break; } return NULL; case AArch64_INSvi64gpr: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) - AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\x03"; + AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi64lane: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) - AsmString = "mov $\xFF\x01\x06.d$\xFF\x02\x09, $\xFF\x03\x06.d$\xFF\x04\x09"; + AsmString = "mov $\xFF\x01\x0C.d$\xFF\x03\x19, $\xFF\x04\x0C.d$\xFF\x05\x19"; break; } return NULL; case AArch64_INSvi8gpr: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) - AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\x03"; + AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\x04"; break; } return NULL; case AArch64_INSvi8lane: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isReg(MCInst_getOperand(MI, 2)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 2)) { + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 3) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) - AsmString = "mov $\xFF\x01\x06.b$\xFF\x02\x09, $\xFF\x03\x06.b$\xFF\x04\x09"; + AsmString = "mov $\xFF\x01\x0C.b$\xFF\x03\x19, $\xFF\x04\x0C.b$\xFF\x05\x19"; break; } return NULL; @@ -8023,1215 +14905,3018 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) break; } return NULL; + case AArch64_LD1B_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1B_H_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1B_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1B_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; case AArch64_LD1Fourv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #64"; + AsmString = "ld1 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_LD1Fourv1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x26, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #64"; + AsmString = "ld1 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_LD1Fourv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #64"; + AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_LD1Fourv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x10, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_LD1Fourv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x11, [$\x01], #64"; + AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD1H_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1H_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1H_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Onev16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x25, [$\x01], #16"; break; } return NULL; case AArch64_LD1Onev1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #8"; + AsmString = "ld1 $\xFF\x02\x26, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x27, [$\x01], #16"; break; } return NULL; case AArch64_LD1Onev2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #8"; + AsmString = "ld1 $\xFF\x02\x28, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #8"; + AsmString = "ld1 $\xFF\x02\x29, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #16"; break; } return NULL; case AArch64_LD1Onev8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x10, [$\x01], #8"; + AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #8"; break; } return NULL; case AArch64_LD1Onev8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x11, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #16"; + break; + } + return NULL; + case AArch64_LD1RB_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RB_H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RB_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RB_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RD_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RH_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RH_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RH_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RQ_B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rqb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RQ_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RQ_H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rqh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RQ_W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RSB_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RSB_H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RSB_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RSH_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RSH_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RSW_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RW_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1RW_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Rv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x0A, [$\x01], #1"; + AsmString = "ld1r $\xFF\x02\x25, [$\x01], #1"; break; } return NULL; case AArch64_LD1Rv1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x0B, [$\x01], #8"; + AsmString = "ld1r $\xFF\x02\x26, [$\x01], #8"; break; } return NULL; case AArch64_LD1Rv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x0C, [$\x01], #8"; + AsmString = "ld1r $\xFF\x02\x27, [$\x01], #8"; break; } return NULL; case AArch64_LD1Rv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x0D, [$\x01], #4"; + AsmString = "ld1r $\xFF\x02\x28, [$\x01], #4"; break; } return NULL; case AArch64_LD1Rv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x0E, [$\x01], #2"; + AsmString = "ld1r $\xFF\x02\x29, [$\x01], #2"; break; } return NULL; case AArch64_LD1Rv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x0F, [$\x01], #4"; + AsmString = "ld1r $\xFF\x02\x2A, [$\x01], #4"; break; } return NULL; case AArch64_LD1Rv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x10, [$\x01], #1"; + AsmString = "ld1r $\xFF\x02\x2B, [$\x01], #1"; break; } return NULL; case AArch64_LD1Rv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - AsmString = "ld1r $\xFF\x02\x11, [$\x01], #2"; + AsmString = "ld1r $\xFF\x02\x2C, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD1SB_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1SB_H_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1SB_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1SH_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1SH_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1SW_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1Threev16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #48"; + AsmString = "ld1 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_LD1Threev1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #24"; + AsmString = "ld1 $\xFF\x02\x26, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #48"; + AsmString = "ld1 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_LD1Threev2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #24"; + AsmString = "ld1 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #24"; + AsmString = "ld1 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #48"; + AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_LD1Threev8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x10, [$\x01], #24"; + AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_LD1Threev8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x11, [$\x01], #48"; + AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #48"; break; } return NULL; case AArch64_LD1Twov16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0A, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_LD1Twov1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0B, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x26, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0C, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_LD1Twov2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0D, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0E, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x0F, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_LD1Twov8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x10, [$\x01], #16"; + AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_LD1Twov8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - AsmString = "ld1 $\xFF\x02\x11, [$\x01], #32"; + AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD1W_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD1W_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD1i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "ld1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; + AsmString = "ld1 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #2"; break; } return NULL; case AArch64_LD1i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - AsmString = "ld1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; + AsmString = "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4"; break; } return NULL; case AArch64_LD1i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - AsmString = "ld1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; + AsmString = "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8"; break; } return NULL; case AArch64_LD1i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - AsmString = "ld1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; + AsmString = "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #1"; + break; + } + return NULL; + case AArch64_LD2B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld2b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD2D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD2H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld2h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD2Rv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x0A, [$\x01], #2"; + AsmString = "ld2r $\xFF\x02\x25, [$\x01], #2"; break; } return NULL; case AArch64_LD2Rv1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x0B, [$\x01], #16"; + AsmString = "ld2r $\xFF\x02\x26, [$\x01], #16"; break; } return NULL; case AArch64_LD2Rv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x0C, [$\x01], #16"; + AsmString = "ld2r $\xFF\x02\x27, [$\x01], #16"; break; } return NULL; case AArch64_LD2Rv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x0D, [$\x01], #8"; + AsmString = "ld2r $\xFF\x02\x28, [$\x01], #8"; break; } return NULL; case AArch64_LD2Rv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x0E, [$\x01], #4"; + AsmString = "ld2r $\xFF\x02\x29, [$\x01], #4"; break; } return NULL; case AArch64_LD2Rv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x0F, [$\x01], #8"; + AsmString = "ld2r $\xFF\x02\x2A, [$\x01], #8"; break; } return NULL; case AArch64_LD2Rv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x10, [$\x01], #2"; + AsmString = "ld2r $\xFF\x02\x2B, [$\x01], #2"; break; } return NULL; case AArch64_LD2Rv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - AsmString = "ld2r $\xFF\x02\x11, [$\x01], #4"; + AsmString = "ld2r $\xFF\x02\x2C, [$\x01], #4"; break; } return NULL; case AArch64_LD2Twov16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x0A, [$\x01], #32"; + AsmString = "ld2 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_LD2Twov2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x0C, [$\x01], #32"; + AsmString = "ld2 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_LD2Twov2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x0D, [$\x01], #16"; + AsmString = "ld2 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_LD2Twov4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x0E, [$\x01], #16"; + AsmString = "ld2 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_LD2Twov4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x0F, [$\x01], #32"; + AsmString = "ld2 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_LD2Twov8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x10, [$\x01], #16"; + AsmString = "ld2 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_LD2Twov8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - AsmString = "ld2 $\xFF\x02\x11, [$\x01], #32"; + AsmString = "ld2 $\xFF\x02\x2C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_LD2W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD2i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "ld2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; + AsmString = "ld2 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #4"; break; } return NULL; case AArch64_LD2i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - AsmString = "ld2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; + AsmString = "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8"; break; } return NULL; case AArch64_LD2i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - AsmString = "ld2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; + AsmString = "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16"; break; } return NULL; case AArch64_LD2i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - AsmString = "ld2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; + AsmString = "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #2"; + break; + } + return NULL; + case AArch64_LD3B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld3b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD3D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD3H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld3h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD3Rv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x0A, [$\x01], #3"; + AsmString = "ld3r $\xFF\x02\x25, [$\x01], #3"; break; } return NULL; case AArch64_LD3Rv1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x0B, [$\x01], #24"; + AsmString = "ld3r $\xFF\x02\x26, [$\x01], #24"; break; } return NULL; case AArch64_LD3Rv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x0C, [$\x01], #24"; + AsmString = "ld3r $\xFF\x02\x27, [$\x01], #24"; break; } return NULL; case AArch64_LD3Rv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x0D, [$\x01], #12"; + AsmString = "ld3r $\xFF\x02\x28, [$\x01], #12"; break; } return NULL; case AArch64_LD3Rv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x0E, [$\x01], #6"; + AsmString = "ld3r $\xFF\x02\x29, [$\x01], #6"; break; } return NULL; case AArch64_LD3Rv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x0F, [$\x01], #12"; + AsmString = "ld3r $\xFF\x02\x2A, [$\x01], #12"; break; } return NULL; case AArch64_LD3Rv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x10, [$\x01], #3"; + AsmString = "ld3r $\xFF\x02\x2B, [$\x01], #3"; break; } return NULL; case AArch64_LD3Rv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - AsmString = "ld3r $\xFF\x02\x11, [$\x01], #6"; + AsmString = "ld3r $\xFF\x02\x2C, [$\x01], #6"; break; } return NULL; case AArch64_LD3Threev16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x0A, [$\x01], #48"; + AsmString = "ld3 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_LD3Threev2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x0C, [$\x01], #48"; + AsmString = "ld3 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_LD3Threev2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x0D, [$\x01], #24"; + AsmString = "ld3 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_LD3Threev4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x0E, [$\x01], #24"; + AsmString = "ld3 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_LD3Threev4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x0F, [$\x01], #48"; + AsmString = "ld3 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_LD3Threev8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x10, [$\x01], #24"; + AsmString = "ld3 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_LD3Threev8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - AsmString = "ld3 $\xFF\x02\x11, [$\x01], #48"; + AsmString = "ld3 $\xFF\x02\x2C, [$\x01], #48"; + break; + } + return NULL; + case AArch64_LD3W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD3i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "ld3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; + AsmString = "ld3 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #6"; break; } return NULL; case AArch64_LD3i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - AsmString = "ld3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; + AsmString = "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #12"; break; } return NULL; case AArch64_LD3i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - AsmString = "ld3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; + AsmString = "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #24"; break; } return NULL; case AArch64_LD3i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - AsmString = "ld3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; + AsmString = "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #3"; + break; + } + return NULL; + case AArch64_LD4B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld4b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LD4D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4Fourv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x0A, [$\x01], #64"; + AsmString = "ld4 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_LD4Fourv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x0C, [$\x01], #64"; + AsmString = "ld4 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_LD4Fourv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x0D, [$\x01], #32"; + AsmString = "ld4 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_LD4Fourv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x0E, [$\x01], #32"; + AsmString = "ld4 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_LD4Fourv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x0F, [$\x01], #64"; + AsmString = "ld4 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_LD4Fourv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x10, [$\x01], #32"; + AsmString = "ld4 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_LD4Fourv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - AsmString = "ld4 $\xFF\x02\x11, [$\x01], #64"; + AsmString = "ld4 $\xFF\x02\x2C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_LD4H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld4h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4Rv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x0A, [$\x01], #4"; + AsmString = "ld4r $\xFF\x02\x25, [$\x01], #4"; break; } return NULL; case AArch64_LD4Rv1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x0B, [$\x01], #32"; + AsmString = "ld4r $\xFF\x02\x26, [$\x01], #32"; break; } return NULL; case AArch64_LD4Rv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x0C, [$\x01], #32"; + AsmString = "ld4r $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_LD4Rv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x0D, [$\x01], #16"; + AsmString = "ld4r $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_LD4Rv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x0E, [$\x01], #8"; + AsmString = "ld4r $\xFF\x02\x29, [$\x01], #8"; break; } return NULL; case AArch64_LD4Rv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x0F, [$\x01], #16"; + AsmString = "ld4r $\xFF\x02\x2A, [$\x01], #16"; break; } return NULL; case AArch64_LD4Rv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x10, [$\x01], #4"; + AsmString = "ld4r $\xFF\x02\x2B, [$\x01], #4"; break; } return NULL; case AArch64_LD4Rv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - AsmString = "ld4r $\xFF\x02\x11, [$\x01], #8"; + AsmString = "ld4r $\xFF\x02\x2C, [$\x01], #8"; + break; + } + return NULL; + case AArch64_LD4W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; case AArch64_LD4i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "ld4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; + AsmString = "ld4 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #8"; break; } return NULL; case AArch64_LD4i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - AsmString = "ld4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; + AsmString = "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #16"; break; } return NULL; case AArch64_LD4i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - AsmString = "ld4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; + AsmString = "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #32"; break; } return NULL; case AArch64_LD4i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 6 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 5)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - AsmString = "ld4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; + AsmString = "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #4"; + break; + } + return NULL; + case AArch64_LDADDB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "staddb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "staddh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "staddlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "staddlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "staddl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "staddl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stadd $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDADDX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stadd $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDAPURBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapurb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapurh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURSBWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapursb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURSBXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapursb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURSHWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapursh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURSHXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapursh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURSWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapursw $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDAPURi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldapur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDCLRB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stclrb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stclrh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stclrlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stclrlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stclrl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stclrl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stclr $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDCLRX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stclr $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "steorb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "steorh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "steorlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "steorlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "steorl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "steorl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "steor $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDEORX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "steor $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1B_D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1B_H_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1B_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1B_S_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1H_D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1H_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1H_S_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1SB_D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1SB_H_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1SB_S_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1SH_D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1SH_S_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1SW_D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1W_D_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDFF1W_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) + AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1B_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1B_H_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1B_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1B_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1H_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1H_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1H_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1SB_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1SB_H_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1SB_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1SH_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1SH_S_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1SW_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1W_D_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNF1W_IMM_REAL: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; break; } return NULL; @@ -9245,7 +17930,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) + // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } @@ -9260,7 +17945,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) + // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } @@ -9275,7 +17960,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) + // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } @@ -9290,7 +17975,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) + // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } @@ -9305,11 +17990,75 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "ldnp $\x01, $\x02, [$\x03]"; break; } return NULL; + case AArch64_LDNT1B_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNT1D_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNT1H_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; + case AArch64_LDNT1W_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; + break; + } + return NULL; case AArch64_LDPDi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -9320,8 +18069,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) - AsmString = "ldp $\x01, $\x02, [$\x03]"; + // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -9335,8 +18084,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) - AsmString = "ldp $\x01, $\x02, [$\x03]"; + // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -9350,8 +18099,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDPSWi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) - AsmString = "ldpsw $\x01, $\x02, [$\x03]"; + // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldpsw $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -9365,8 +18114,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) - AsmString = "ldp $\x01, $\x02, [$\x03]"; + // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -9380,8 +18129,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) - AsmString = "ldp $\x01, $\x02, [$\x03]"; + // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -9395,8 +18144,36 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (LDPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) - AsmString = "ldp $\x01, $\x02, [$\x03]"; + // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) + AsmString = "ldp $\x01, $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDRAAindexed: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_3aOps)) { + // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldraa $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDRABindexed: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_3aOps)) { + // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldrab $\x01, [$\x02]"; break; } return NULL; @@ -9413,7 +18190,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrb $\x01, [$\x02, $\x03]"; + AsmString = "ldrb $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9426,7 +18203,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrb $\x01, [$\x02]"; + AsmString = "ldrb $\x01, [$\x02]"; break; } return NULL; @@ -9442,8 +18219,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (LDRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9455,8 +18232,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRBui FPR8:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; @@ -9472,8 +18249,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (LDRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9485,8 +18262,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRDui FPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; @@ -9503,7 +18280,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrh $\x01, [$\x02, $\x03]"; + AsmString = "ldrh $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9516,7 +18293,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrh $\x01, [$\x02]"; + AsmString = "ldrh $\x01, [$\x02]"; break; } return NULL; @@ -9532,8 +18309,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (LDRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9545,8 +18322,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRHui FPR16:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; @@ -9562,8 +18339,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (LDRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9575,8 +18352,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRQui FPR128:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; @@ -9593,7 +18370,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrsb $\x01, [$\x02, $\x03]"; + AsmString = "ldrsb $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9606,7 +18383,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrsb $\x01, [$\x02]"; + AsmString = "ldrsb $\x01, [$\x02]"; break; } return NULL; @@ -9623,7 +18400,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrsb $\x01, [$\x02, $\x03]"; + AsmString = "ldrsb $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9636,7 +18413,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrsb $\x01, [$\x02]"; + AsmString = "ldrsb $\x01, [$\x02]"; break; } return NULL; @@ -9653,7 +18430,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrsh $\x01, [$\x02, $\x03]"; + AsmString = "ldrsh $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9666,7 +18443,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrsh $\x01, [$\x02]"; + AsmString = "ldrsh $\x01, [$\x02]"; break; } return NULL; @@ -9683,7 +18460,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrsh $\x01, [$\x02, $\x03]"; + AsmString = "ldrsh $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9696,7 +18473,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrsh $\x01, [$\x02]"; + AsmString = "ldrsh $\x01, [$\x02]"; break; } return NULL; @@ -9713,7 +18490,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldrsw $\x01, [$\x02, $\x03]"; + AsmString = "ldrsw $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9726,7 +18503,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldrsw $\x01, [$\x02]"; + AsmString = "ldrsw $\x01, [$\x02]"; break; } return NULL; @@ -9742,8 +18519,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (LDRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9755,8 +18532,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRSui FPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; @@ -9773,7 +18550,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9785,8 +18562,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRWui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; break; } return NULL; @@ -9803,7 +18580,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "ldr $\x01, [$\x02, $\x03]"; + AsmString = "ldr $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -9815,8 +18592,348 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDRXui GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldr $\x01, [$\x02]"; + // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDR_PXI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) + AsmString = "ldr $\xFF\x01\x07, [$\x02]"; + break; + } + return NULL; + case AArch64_LDR_ZXI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) + AsmString = "ldr $\xFF\x01\x07, [$\x02]"; + break; + } + return NULL; + case AArch64_LDSETB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsetb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stseth $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsetlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsetlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsetl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stsetl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stset $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSETX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stset $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmaxb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmaxh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmaxlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmaxlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmaxl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stsmaxl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmax $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMAXX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stsmax $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsminb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsminh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsminlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsminlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsminl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stsminl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stsmin $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDSMINX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stsmin $\x02, [$\x03]"; break; } return NULL; @@ -9829,7 +18946,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrb $\x01, [$\x02]"; + AsmString = "ldtrb $\x01, [$\x02]"; break; } return NULL; @@ -9842,7 +18959,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrh $\x01, [$\x02]"; + AsmString = "ldtrh $\x01, [$\x02]"; break; } return NULL; @@ -9855,7 +18972,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrsb $\x01, [$\x02]"; + AsmString = "ldtrsb $\x01, [$\x02]"; break; } return NULL; @@ -9868,7 +18985,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrsb $\x01, [$\x02]"; + AsmString = "ldtrsb $\x01, [$\x02]"; break; } return NULL; @@ -9881,7 +18998,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrsh $\x01, [$\x02]"; + AsmString = "ldtrsh $\x01, [$\x02]"; break; } return NULL; @@ -9894,7 +19011,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrsh $\x01, [$\x02]"; + AsmString = "ldtrsh $\x01, [$\x02]"; break; } return NULL; @@ -9907,7 +19024,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtrsw $\x01, [$\x02]"; + AsmString = "ldtrsw $\x01, [$\x02]"; break; } return NULL; @@ -9920,7 +19037,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtr $\x01, [$\x02]"; + AsmString = "ldtr $\x01, [$\x02]"; break; } return NULL; @@ -9933,7 +19050,215 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldtr $\x01, [$\x02]"; + AsmString = "ldtr $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_LDUMAXB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumaxb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumaxh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumaxlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumaxlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumaxl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stumaxl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumax $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMAXX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stumax $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stuminb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stuminh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINLB: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stuminlb $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINLH: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stuminlh $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINLW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stuminl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINLX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stuminl $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINW: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_WZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) + AsmString = "stumin $\x02, [$\x03]"; + break; + } + return NULL; + case AArch64_LDUMINX: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + AArch64_getFeatureBits(AArch64_FeatureLSE)) { + // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) + AsmString = "stumin $\x02, [$\x03]"; break; } return NULL; @@ -9946,7 +19271,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldurb $\x01, [$\x02]"; + AsmString = "ldurb $\x01, [$\x02]"; break; } return NULL; @@ -9958,8 +19283,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURBi FPR8:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -9971,8 +19296,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURDi FPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -9985,7 +19310,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldurh $\x01, [$\x02]"; + AsmString = "ldurh $\x01, [$\x02]"; break; } return NULL; @@ -9997,8 +19322,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURHi FPR16:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -10010,8 +19335,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURQi FPR128:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -10024,7 +19349,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldursb $\x01, [$\x02]"; + AsmString = "ldursb $\x01, [$\x02]"; break; } return NULL; @@ -10037,7 +19362,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldursb $\x01, [$\x02]"; + AsmString = "ldursb $\x01, [$\x02]"; break; } return NULL; @@ -10050,7 +19375,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldursh $\x01, [$\x02]"; + AsmString = "ldursh $\x01, [$\x02]"; break; } return NULL; @@ -10063,7 +19388,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldursh $\x01, [$\x02]"; + AsmString = "ldursh $\x01, [$\x02]"; break; } return NULL; @@ -10076,7 +19401,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldursw $\x01, [$\x02]"; + AsmString = "ldursw $\x01, [$\x02]"; break; } return NULL; @@ -10088,8 +19413,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURSi FPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -10101,8 +19426,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -10114,8 +19439,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (LDURXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "ldur $\x01, [$\x02]"; + // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) + AsmString = "ldur $\x01, [$\x02]"; break; } return NULL; @@ -10129,7 +19454,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - AsmString = "mul $\x01, $\x02, $\x03"; + AsmString = "mul $\x01, $\x02, $\x03"; break; } return NULL; @@ -10143,47 +19468,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - AsmString = "mul $\x01, $\x02, $\x03"; - break; - } - return NULL; - case AArch64_MOVKWi: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { - // (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16) - AsmString = "movk $\x01, $\x02"; - break; - } - return NULL; - case AArch64_MOVKXi: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 48) { - // (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48) - AsmString = "movk $\x01, $\x02"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 32) { - // (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32) - AsmString = "movk $\x01, $\x02"; - break; - } - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 16) { - // (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16) - AsmString = "movk $\x01, $\x02"; + AsmString = "mul $\x01, $\x02, $\x03"; break; } return NULL; @@ -10197,7 +19482,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_WZR) { // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) - AsmString = "mneg $\x01, $\x02, $\x03"; + AsmString = "mneg $\x01, $\x02, $\x03"; break; } return NULL; @@ -10211,7 +19496,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) - AsmString = "mneg $\x01, $\x02, $\x03"; + AsmString = "mneg $\x01, $\x02, $\x03"; break; } return NULL; @@ -10222,7 +19507,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { // (NOTv16i8 V128:$Vd, V128:$Vn) - AsmString = "mvn $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; + AsmString = "mvn $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; break; } return NULL; @@ -10233,7 +19518,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1)) { // (NOTv8i8 V64:$Vd, V64:$Vn) - AsmString = "mvn $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; + AsmString = "mvn $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; break; } return NULL; @@ -10270,7 +19555,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "orn $\x01, $\x02, $\x03"; + AsmString = "orn $\x01, $\x02, $\x03"; break; } return NULL; @@ -10307,7 +19592,23 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "orn $\x01, $\x02, $\x03"; + AsmString = "orn $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ORRS_PPzPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) + AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x06"; break; } return NULL; @@ -10334,7 +19635,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "orr $\x01, $\x02, $\x03"; + AsmString = "orr $\x01, $\x02, $\x03"; break; } return NULL; @@ -10361,7 +19662,66 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "orr $\x01, $\x02, $\x03"; + AsmString = "orr $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_ORR_PPzPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06"; + break; + } + return NULL; + case AArch64_ORR_ZI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 1) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) + AsmString = "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 2) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) + AsmString = "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; + break; + } + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + AArch64InstPrinterValidateMCOperand(MCInst_getOperand(MI, 2), 3) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) + AsmString = "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; + break; + } + return NULL; + case AArch64_ORR_ZZZ: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10"; break; } return NULL; @@ -10374,51 +19734,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (ORRv16i8 V128:$dst, V128:$src, V128:$src) - AsmString = "mov $\xFF\x01\x06.16b, $\xFF\x02\x06.16b"; - break; - } - return NULL; - case AArch64_ORRv2i32: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ORRv2i32 V64:$Vd, imm0_255:$imm, 0) - AsmString = "orr $\xFF\x01\x06.2s, $\xFF\x02\x07"; - break; - } - return NULL; - case AArch64_ORRv4i16: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ORRv4i16 V64:$Vd, imm0_255:$imm, 0) - AsmString = "orr $\xFF\x01\x06.4h, $\xFF\x02\x07"; - break; - } - return NULL; - case AArch64_ORRv4i32: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ORRv4i32 V128:$Vd, imm0_255:$imm, 0) - AsmString = "orr $\xFF\x01\x06.4s, $\xFF\x02\x07"; - break; - } - return NULL; - case AArch64_ORRv8i16: - if (MCInst_getNumOperands(MI) == 3 && - MCOperand_isReg(MCInst_getOperand(MI, 0)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 0) && - MCOperand_isImm(MCInst_getOperand(MI, 2)) && - MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (ORRv8i16 V128:$Vd, imm0_255:$imm, 0) - AsmString = "orr $\xFF\x01\x06.8h, $\xFF\x02\x07"; + AsmString = "mov $\xFF\x01\x0C.16b, $\xFF\x02\x0C.16b"; break; } return NULL; @@ -10431,7 +19747,133 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && MCOperand_getReg(MCInst_getOperand(MI, 2)) == MCOperand_getReg(MCInst_getOperand(MI, 1))) { // (ORRv8i8 V64:$dst, V64:$src, V64:$src) - AsmString = "mov $\xFF\x01\x06.8b, $\xFF\x02\x06.8b"; + AsmString = "mov $\xFF\x01\x0C.8b, $\xFF\x02\x0C.8b"; + break; + } + return NULL; + case AArch64_PRFB_D_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_PRFB_PRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_PRFB_S_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_PRFD_D_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_PRFD_PRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_PRFD_S_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_PRFH_D_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_PRFH_PRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_PRFH_S_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; break; } return NULL; @@ -10446,7 +19888,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "prfm $\xFF\x01\x16, [$\x02, $\x03]"; + AsmString = "prfm $\xFF\x01\x33, [$\x02, $\x03]"; break; } return NULL; @@ -10457,7 +19899,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) - AsmString = "prfm $\xFF\x01\x16, [$\x02]"; + AsmString = "prfm $\xFF\x01\x33, [$\x02]"; break; } return NULL; @@ -10468,7 +19910,145 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) - AsmString = "prfum $\xFF\x01\x16, [$\x02]"; + AsmString = "prfum $\xFF\x01\x33, [$\x02]"; + break; + } + return NULL; + case AArch64_PRFW_D_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_PRFW_PRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_PRFW_S_PZI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_PTRUES_B: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrues $\xFF\x01\x06"; + break; + } + return NULL; + case AArch64_PTRUES_D: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrues $\xFF\x01\x10"; + break; + } + return NULL; + case AArch64_PTRUES_H: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrues $\xFF\x01\x09"; + break; + } + return NULL; + case AArch64_PTRUES_S: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrues $\xFF\x01\x0B"; + break; + } + return NULL; + case AArch64_PTRUE_B: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrue $\xFF\x01\x06"; + break; + } + return NULL; + case AArch64_PTRUE_D: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrue $\xFF\x01\x10"; + break; + } + return NULL; + case AArch64_PTRUE_H: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrue $\xFF\x01\x09"; + break; + } + return NULL; + case AArch64_PTRUE_S: + if (MCInst_getNumOperands(MI) == 2 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && + MCOperand_getImm(MCInst_getOperand(MI, 1)) == 31 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) + AsmString = "ptrue $\xFF\x01\x0B"; break; } return NULL; @@ -10619,6 +20199,86 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) break; } return NULL; + case AArch64_SEL_PPPP: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; + break; + } + return NULL; + case AArch64_SEL_ZPZZ_B: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) + AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; + break; + } + return NULL; + case AArch64_SEL_ZPZZ_D: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) + AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10"; + break; + } + return NULL; + case AArch64_SEL_ZPZZ_H: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) + AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09"; + break; + } + return NULL; + case AArch64_SEL_ZPZZ_S: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isReg(MCInst_getOperand(MI, 3)) && + MCOperand_getReg(MCInst_getOperand(MI, 3)) == MCOperand_getReg(MCInst_getOperand(MI, 0)) && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) + AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B"; + break; + } + return NULL; case AArch64_SMADDLrrr: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -10629,7 +20289,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - AsmString = "smull $\x01, $\x02, $\x03"; + AsmString = "smull $\x01, $\x02, $\x03"; break; } return NULL; @@ -10643,835 +20303,1984 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - AsmString = "smnegl $\x01, $\x02, $\x03"; + AsmString = "smnegl $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_SQDECB_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECB_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecb $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECD_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECD_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecd $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECD_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecd $\xFF\x01\x10"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECH_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdech $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdech $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECH_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdech $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqdech $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECH_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdech $\xFF\x01\x09"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdech $\xFF\x01\x09, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECW_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECW_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecw $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQDECW_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqdecw $\xFF\x01\x0B"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCB_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqincb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCB_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincb $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqincb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCD_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqincd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCD_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincd $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqincd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCD_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincd $\xFF\x01\x10"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "sqincd $\xFF\x01\x10, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCH_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqinch $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqinch $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCH_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqinch $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqinch $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCH_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqinch $\xFF\x01\x09"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "sqinch $\xFF\x01\x09, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCW_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "sqincw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCW_XPiWdI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincw $\x01, $\xFF\x02\x34"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) + AsmString = "sqincw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SQINCW_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "sqincw $\xFF\x01\x0B"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_SST1B_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_SST1B_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_SST1D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_SST1H_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_SST1H_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_SST1W_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) + AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; + break; + } + return NULL; + case AArch64_SST1W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) + AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; + break; + } + return NULL; + case AArch64_ST1B_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1B_H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1B_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1Fourv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0A, [$\x01], #64"; + AsmString = "st1 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_ST1Fourv1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0B, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x26, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0C, [$\x01], #64"; + AsmString = "st1 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_ST1Fourv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0D, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0E, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0F, [$\x01], #64"; + AsmString = "st1 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_ST1Fourv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x10, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_ST1Fourv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x11, [$\x01], #64"; + AsmString = "st1 $\xFF\x02\x2C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST1H_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1H_S_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1Onev16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0A, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x25, [$\x01], #16"; break; } return NULL; case AArch64_ST1Onev1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0B, [$\x01], #8"; + AsmString = "st1 $\xFF\x02\x26, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0C, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x27, [$\x01], #16"; break; } return NULL; case AArch64_ST1Onev2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0D, [$\x01], #8"; + AsmString = "st1 $\xFF\x02\x28, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0E, [$\x01], #8"; + AsmString = "st1 $\xFF\x02\x29, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0F, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x2A, [$\x01], #16"; break; } return NULL; case AArch64_ST1Onev8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR64RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x10, [$\x01], #8"; + AsmString = "st1 $\xFF\x02\x2B, [$\x01], #8"; break; } return NULL; case AArch64_ST1Onev8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x11, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x2C, [$\x01], #16"; break; } return NULL; case AArch64_ST1Threev16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0A, [$\x01], #48"; + AsmString = "st1 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_ST1Threev1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0B, [$\x01], #24"; + AsmString = "st1 $\xFF\x02\x26, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0C, [$\x01], #48"; + AsmString = "st1 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_ST1Threev2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0D, [$\x01], #24"; + AsmString = "st1 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0E, [$\x01], #24"; + AsmString = "st1 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0F, [$\x01], #48"; + AsmString = "st1 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_ST1Threev8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x10, [$\x01], #24"; + AsmString = "st1 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_ST1Threev8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x11, [$\x01], #48"; + AsmString = "st1 $\xFF\x02\x2C, [$\x01], #48"; break; } return NULL; case AArch64_ST1Twov16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0A, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_ST1Twov1d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0B, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x26, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0C, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_ST1Twov2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0D, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0E, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x0F, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_ST1Twov8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x10, [$\x01], #16"; + AsmString = "st1 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_ST1Twov8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - AsmString = "st1 $\xFF\x02\x11, [$\x01], #32"; + AsmString = "st1 $\xFF\x02\x2C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST1W_D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST1W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST1i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "st1 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #2"; + AsmString = "st1 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #2"; break; } return NULL; case AArch64_ST1i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) - AsmString = "st1 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #4"; + AsmString = "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4"; break; } return NULL; case AArch64_ST1i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) - AsmString = "st1 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #8"; + AsmString = "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8"; break; } return NULL; case AArch64_ST1i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) - AsmString = "st1 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #1"; + AsmString = "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #1"; + break; + } + return NULL; + case AArch64_ST2B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st2b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST2D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST2H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st2h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST2Twov16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x0A, [$\x01], #32"; + AsmString = "st2 $\xFF\x02\x25, [$\x01], #32"; break; } return NULL; case AArch64_ST2Twov2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x0C, [$\x01], #32"; + AsmString = "st2 $\xFF\x02\x27, [$\x01], #32"; break; } return NULL; case AArch64_ST2Twov2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x0D, [$\x01], #16"; + AsmString = "st2 $\xFF\x02\x28, [$\x01], #16"; break; } return NULL; case AArch64_ST2Twov4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x0E, [$\x01], #16"; + AsmString = "st2 $\xFF\x02\x29, [$\x01], #16"; break; } return NULL; case AArch64_ST2Twov4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x0F, [$\x01], #32"; + AsmString = "st2 $\xFF\x02\x2A, [$\x01], #32"; break; } return NULL; case AArch64_ST2Twov8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x10, [$\x01], #16"; + AsmString = "st2 $\xFF\x02\x2B, [$\x01], #16"; break; } return NULL; case AArch64_ST2Twov8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) - AsmString = "st2 $\xFF\x02\x11, [$\x01], #32"; + AsmString = "st2 $\xFF\x02\x2C, [$\x01], #32"; + break; + } + return NULL; + case AArch64_ST2W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR2RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST2i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "st2 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #4"; + AsmString = "st2 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #4"; break; } return NULL; case AArch64_ST2i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) - AsmString = "st2 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #8"; + AsmString = "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8"; break; } return NULL; case AArch64_ST2i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) - AsmString = "st2 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #16"; + AsmString = "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16"; break; } return NULL; case AArch64_ST2i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) - AsmString = "st2 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #2"; + AsmString = "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #2"; + break; + } + return NULL; + case AArch64_ST3B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st3b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST3D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST3H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st3h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST3Threev16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x0A, [$\x01], #48"; + AsmString = "st3 $\xFF\x02\x25, [$\x01], #48"; break; } return NULL; case AArch64_ST3Threev2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x0C, [$\x01], #48"; + AsmString = "st3 $\xFF\x02\x27, [$\x01], #48"; break; } return NULL; case AArch64_ST3Threev2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x0D, [$\x01], #24"; + AsmString = "st3 $\xFF\x02\x28, [$\x01], #24"; break; } return NULL; case AArch64_ST3Threev4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x0E, [$\x01], #24"; + AsmString = "st3 $\xFF\x02\x29, [$\x01], #24"; break; } return NULL; case AArch64_ST3Threev4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x0F, [$\x01], #48"; + AsmString = "st3 $\xFF\x02\x2A, [$\x01], #48"; break; } return NULL; case AArch64_ST3Threev8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x10, [$\x01], #24"; + AsmString = "st3 $\xFF\x02\x2B, [$\x01], #24"; break; } return NULL; case AArch64_ST3Threev8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) - AsmString = "st3 $\xFF\x02\x11, [$\x01], #48"; + AsmString = "st3 $\xFF\x02\x2C, [$\x01], #48"; + break; + } + return NULL; + case AArch64_ST3W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR3RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST3i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "st3 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #6"; + AsmString = "st3 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #6"; break; } return NULL; case AArch64_ST3i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) - AsmString = "st3 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #12"; + AsmString = "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #12"; break; } return NULL; case AArch64_ST3i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) - AsmString = "st3 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #24"; + AsmString = "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #24"; break; } return NULL; case AArch64_ST3i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) - AsmString = "st3 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #3"; + AsmString = "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #3"; + break; + } + return NULL; + case AArch64_ST4B_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st4b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST4D_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST4Fourv16b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x0A, [$\x01], #64"; + AsmString = "st4 $\xFF\x02\x25, [$\x01], #64"; break; } return NULL; case AArch64_ST4Fourv2d_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x0C, [$\x01], #64"; + AsmString = "st4 $\xFF\x02\x27, [$\x01], #64"; break; } return NULL; case AArch64_ST4Fourv2s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x0D, [$\x01], #32"; + AsmString = "st4 $\xFF\x02\x28, [$\x01], #32"; break; } return NULL; case AArch64_ST4Fourv4h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x0E, [$\x01], #32"; + AsmString = "st4 $\xFF\x02\x29, [$\x01], #32"; break; } return NULL; case AArch64_ST4Fourv4s_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x0F, [$\x01], #64"; + AsmString = "st4 $\xFF\x02\x2A, [$\x01], #64"; break; } return NULL; case AArch64_ST4Fourv8b_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_DDDDRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x10, [$\x01], #32"; + AsmString = "st4 $\xFF\x02\x2B, [$\x01], #32"; break; } return NULL; case AArch64_ST4Fourv8h_POST: - if (MCInst_getNumOperands(MI) == 3 && + if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 2)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) - AsmString = "st4 $\xFF\x02\x11, [$\x01], #64"; + AsmString = "st4 $\xFF\x02\x2C, [$\x01], #64"; + break; + } + return NULL; + case AArch64_ST4H_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st4h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_ST4W_IMM: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPR4RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; break; } return NULL; case AArch64_ST4i16_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) - AsmString = "st4 $\xFF\x02\x12$\xFF\x03\x09, [$\x01], #8"; + AsmString = "st4 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #8"; break; } return NULL; case AArch64_ST4i32_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) - AsmString = "st4 $\xFF\x02\x13$\xFF\x03\x09, [$\x01], #16"; + AsmString = "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #16"; break; } return NULL; case AArch64_ST4i64_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) - AsmString = "st4 $\xFF\x02\x14$\xFF\x03\x09, [$\x01], #32"; + AsmString = "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #32"; break; } return NULL; case AArch64_ST4i8_POST: - if (MCInst_getNumOperands(MI) == 4 && + if (MCInst_getNumOperands(MI) == 5 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_QQQQRegClassID, 1) && - MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { + MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) - AsmString = "st4 $\xFF\x02\x15$\xFF\x03\x09, [$\x01], #4"; + AsmString = "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #4"; + break; + } + return NULL; + case AArch64_STLURBi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "stlurb $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STLURHi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "stlurh $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STLURWi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) + AsmString = "stlur $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STLURXi: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_HasV8_4aOps)) { + // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) + AsmString = "stlur $\x01, [$\x02]"; break; } return NULL; @@ -11485,7 +22294,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STNPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) + // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } @@ -11500,7 +22309,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) + // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } @@ -11515,7 +22324,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STNPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) + // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } @@ -11530,7 +22339,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STNPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) + // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } @@ -11545,11 +22354,75 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STNPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) + // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) AsmString = "stnp $\x01, $\x02, [$\x03]"; break; } return NULL; + case AArch64_STNT1B_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_STNT1D_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_STNT1H_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; + case AArch64_STNT1W_ZRI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_PPR_3bRegClassID, 1) && + MCOperand_isReg(MCInst_getOperand(MI, 2)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) + AsmString = "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; + break; + } + return NULL; case AArch64_STPDi: if (MCInst_getNumOperands(MI) == 4 && MCOperand_isReg(MCInst_getOperand(MI, 0)) && @@ -11560,8 +22433,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STPDi FPR64:$Rt, FPR64:$Rt2, GPR64sp:$Rn, 0) - AsmString = "stp $\x01, $\x02, [$\x03]"; + // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -11575,8 +22448,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, 0) - AsmString = "stp $\x01, $\x02, [$\x03]"; + // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -11590,8 +22463,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STPSi FPR32:$Rt, FPR32:$Rt2, GPR64sp:$Rn, 0) - AsmString = "stp $\x01, $\x02, [$\x03]"; + // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -11605,8 +22478,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STPWi GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn, 0) - AsmString = "stp $\x01, $\x02, [$\x03]"; + // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -11620,8 +22493,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 2) && MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { - // (STPXi GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn, 0) - AsmString = "stp $\x01, $\x02, [$\x03]"; + // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) + AsmString = "stp $\x01, $\x02, [$\x03]"; break; } return NULL; @@ -11638,7 +22511,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "strb $\x01, [$\x02, $\x03]"; + AsmString = "strb $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11650,8 +22523,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRBBui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "strb $\x01, [$\x02]"; + // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "strb $\x01, [$\x02]"; break; } return NULL; @@ -11667,8 +22540,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (STRBroX FPR8:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11680,8 +22553,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRBui FPR8:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; break; } return NULL; @@ -11697,8 +22570,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (STRDroX FPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11710,8 +22583,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRDui FPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; break; } return NULL; @@ -11728,7 +22601,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "strh $\x01, [$\x02, $\x03]"; + AsmString = "strh $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11740,8 +22613,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRHHui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "strh $\x01, [$\x02]"; + // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "strh $\x01, [$\x02]"; break; } return NULL; @@ -11757,8 +22630,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (STRHroX FPR16:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11770,8 +22643,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRHui FPR16:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; break; } return NULL; @@ -11787,8 +22660,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (STRQroX FPR128:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11800,8 +22673,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRQui FPR128:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; break; } return NULL; @@ -11817,8 +22690,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0 && MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { - // (STRSroX FPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11830,8 +22703,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRSui FPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; break; } return NULL; @@ -11848,7 +22721,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11860,8 +22733,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRWui GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; break; } return NULL; @@ -11878,7 +22751,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 4)) && MCOperand_getImm(MCInst_getOperand(MI, 4)) == 0) { // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) - AsmString = "str $\x01, [$\x02, $\x03]"; + AsmString = "str $\x01, [$\x02, $\x03]"; break; } return NULL; @@ -11890,8 +22763,36 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STRXui GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "str $\x01, [$\x02]"; + // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) + AsmString = "str $\x01, [$\x02]"; + break; + } + return NULL; + case AArch64_STR_PXI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_PPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) + AsmString = "str $\xFF\x01\x07, [$\x02]"; + break; + } + return NULL; + case AArch64_STR_ZXI: + if (MCInst_getNumOperands(MI) == 3 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isReg(MCInst_getOperand(MI, 1)) && + GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) + AsmString = "str $\xFF\x01\x07, [$\x02]"; break; } return NULL; @@ -11904,7 +22805,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "sttrb $\x01, [$\x02]"; + AsmString = "sttrb $\x01, [$\x02]"; break; } return NULL; @@ -11917,7 +22818,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "sttrh $\x01, [$\x02]"; + AsmString = "sttrh $\x01, [$\x02]"; break; } return NULL; @@ -11930,7 +22831,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "sttr $\x01, [$\x02]"; + AsmString = "sttr $\x01, [$\x02]"; break; } return NULL; @@ -11943,7 +22844,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "sttr $\x01, [$\x02]"; + AsmString = "sttr $\x01, [$\x02]"; break; } return NULL; @@ -11955,8 +22856,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURBBi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "sturb $\x01, [$\x02]"; + // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "sturb $\x01, [$\x02]"; break; } return NULL; @@ -11968,8 +22869,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURBi FPR8:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -11981,8 +22882,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURDi FPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -11994,8 +22895,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURHHi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "sturh $\x01, [$\x02]"; + // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "sturh $\x01, [$\x02]"; break; } return NULL; @@ -12007,8 +22908,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURHi FPR16:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -12020,8 +22921,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURQi FPR128:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -12033,8 +22934,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURSi FPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -12046,8 +22947,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURWi GPR32:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -12059,8 +22960,8 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1) && MCOperand_isImm(MCInst_getOperand(MI, 2)) && MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) { - // (STURXi GPR64:$Rt, GPR64sp:$Rn, 0) - AsmString = "stur $\x01, [$\x02]"; + // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) + AsmString = "stur $\x01, [$\x02]"; break; } return NULL; @@ -12070,7 +22971,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR32spRegClassID, 1)) { // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) - AsmString = "cmp $\x02, $\xFF\x03\x01"; + AsmString = "cmp $\x02, $\xFF\x03\x01"; break; } return NULL; @@ -12084,7 +22985,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) - AsmString = "cmp $\x02, $\x03"; + AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12094,7 +22995,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) - AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; + AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12129,7 +23030,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "subs $\x01, $\x02, $\x03"; + AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; @@ -12143,7 +23044,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) - AsmString = "cmp $\x02, $\x03"; + AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12153,7 +23054,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) - AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; + AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12166,7 +23067,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - AsmString = "subs $\x01, $\x02, $\x03"; + AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; @@ -12176,7 +23077,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 1)) && GETREGCLASS_CONTAIN(AArch64_GPR64spRegClassID, 1)) { // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) - AsmString = "cmp $\x02, $\xFF\x03\x01"; + AsmString = "cmp $\x02, $\xFF\x03\x01"; break; } return NULL; @@ -12190,7 +23091,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) - AsmString = "cmp $\x02, $\x03"; + AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12200,7 +23101,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) - AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; + AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12235,7 +23136,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "subs $\x01, $\x02, $\x03"; + AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; @@ -12247,7 +23148,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2)) { // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) - AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; + AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; break; } return NULL; @@ -12261,7 +23162,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) - AsmString = "cmp $\x02, $\x03"; + AsmString = "cmp $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12271,7 +23172,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 2)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 2)) { // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) - AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; + AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12284,7 +23185,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - AsmString = "subs $\x01, $\x02, $\x03"; + AsmString = "subs $\x01, $\x02, $\x03"; break; } return NULL; @@ -12321,7 +23222,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) - AsmString = "sub $\x01, $\x02, $\x03"; + AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; @@ -12336,7 +23237,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) - AsmString = "sub $\x01, $\x02, $\x03"; + AsmString = "sub $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12349,7 +23250,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 16) { // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) - AsmString = "sub $\x01, $\x02, $\x03"; + AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; @@ -12386,7 +23287,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) { // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) - AsmString = "sub $\x01, $\x02, $\x03"; + AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; @@ -12401,7 +23302,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) - AsmString = "sub $\x01, $\x02, $\x03"; + AsmString = "sub $\x01, $\x02, $\x03"; break; } if (MCInst_getNumOperands(MI) == 4 && @@ -12414,7 +23315,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isImm(MCInst_getOperand(MI, 3)) && MCOperand_getImm(MCInst_getOperand(MI, 3)) == 24) { // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) - AsmString = "sub $\x01, $\x02, $\x03"; + AsmString = "sub $\x01, $\x02, $\x03"; break; } return NULL; @@ -12422,7 +23323,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) if (MCInst_getNumOperands(MI) == 5 && MCOperand_getReg(MCInst_getOperand(MI, 4)) == AArch64_XZR) { // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) - AsmString = "sys $\x01, $\xFF\x02\x17, $\xFF\x03\x17, $\x04"; + AsmString = "sys $\x01, $\xFF\x02\x35, $\xFF\x03\x35, $\x04"; break; } return NULL; @@ -12527,7 +23428,7 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - AsmString = "umull $\x01, $\x02, $\x03"; + AsmString = "umull $\x01, $\x02, $\x03"; break; } return NULL; @@ -12536,9 +23437,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) - AsmString = "mov $\x01, $\xFF\x02\x06.s$\xFF\x03\x09"; + AsmString = "mov $\x01, $\xFF\x02\x0C.s$\xFF\x03\x19"; break; } return NULL; @@ -12547,9 +23449,10 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) MCOperand_isReg(MCInst_getOperand(MI, 0)) && GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && MCOperand_isReg(MCInst_getOperand(MI, 1)) && - GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1)) { + GETREGCLASS_CONTAIN(AArch64_FPR128RegClassID, 1) && + AArch64_getFeatureBits(AArch64_FeatureNEON)) { // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) - AsmString = "mov $\x01, $\xFF\x02\x06.d$\xFF\x03\x09"; + AsmString = "mov $\x01, $\xFF\x02\x0C.d$\xFF\x03\x19"; break; } return NULL; @@ -12563,49 +23466,821 @@ static char *printAliasInstr(MCInst *MI, SStream *OS, void *info) GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 2) && MCOperand_getReg(MCInst_getOperand(MI, 3)) == AArch64_XZR) { // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) - AsmString = "umnegl $\x01, $\x02, $\x03"; + AsmString = "umnegl $\x01, $\x02, $\x03"; + break; + } + return NULL; + case AArch64_UQDECB_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECB_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECD_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECD_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECD_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecd $\xFF\x01\x10"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECH_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdech $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdech $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECH_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdech $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdech $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECH_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdech $\xFF\x01\x09"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdech $\xFF\x01\x09, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECW_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECW_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQDECW_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqdecw $\xFF\x01\x0B"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCB_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCB_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincb $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincb $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCD_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCD_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincd $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincd $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCD_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincd $\xFF\x01\x10"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincd $\xFF\x01\x10, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCH_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqinch $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqinch $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCH_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqinch $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqinch $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCH_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqinch $\xFF\x01\x09"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "uqinch $\xFF\x01\x09, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCW_WPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR32RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCW_XPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincw $\x01"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_GPR64RegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincw $\x01, $\xFF\x03\x0E"; + break; + } + return NULL; + case AArch64_UQINCW_ZPiI: + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 2)) && + MCOperand_getImm(MCInst_getOperand(MI, 2)) == 31 && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) + AsmString = "uqincw $\xFF\x01\x0B"; + break; + } + if (MCInst_getNumOperands(MI) == 4 && + MCOperand_isReg(MCInst_getOperand(MI, 0)) && + GETREGCLASS_CONTAIN(AArch64_ZPRRegClassID, 0) && + MCOperand_isImm(MCInst_getOperand(MI, 3)) && + MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1 && + AArch64_getFeatureBits(AArch64_FeatureSVE)) { + // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) + AsmString = "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; break; } return NULL; } - tmp = cs_strdup(AsmString); - AsmMnem = tmp; - for(AsmOps = tmp; *AsmOps; AsmOps++) { - if (*AsmOps == ' ' || *AsmOps == '\t') { - *AsmOps = '\0'; - AsmOps++; - break; + + tmpString = cs_strdup(AsmString); + + while (AsmString[I] != ' ' && AsmString[I] != '\t' && + AsmString[I] != '$' && AsmString[I] != '\0') + ++I; + + tmpString[I] = 0; + SStream_concat0(OS, tmpString); + + if (AsmString[I] != '\0') { + if (AsmString[I] == ' ' || AsmString[I] == '\t') { + SStream_concat0(OS, " "); + ++I; } - } - SStream_concat0(OS, AsmMnem); - if (*AsmOps) { - SStream_concat0(OS, "\t"); - for (c = AsmOps; *c; c++) { - if (*c == '[') { - SStream_concat0(OS, "["); - set_mem_access(MI, true); - } - else if (*c == ']') { - SStream_concat0(OS, "]"); - set_mem_access(MI, false); - } - else if (*c == '$') { - c += 1; - if (*c == (char)0xff) { - c += 1; - OpIdx = *c - 1; - c += 1; - PrintMethodIdx = *c - 1; - printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS, MRI); - } else - printOperand(MI, *c - 1, OS); + + do { + if (AsmString[I] == '$') { + ++I; + if (AsmString[I] == (char)0xff) { + ++I; + OpIdx = AsmString[I++] - 1; + PrintMethodIdx = AsmString[I++] - 1; + printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS); + } else { + printOperand(MI, (unsigned)(AsmString[I++]) - 1, OS); + } } else { - SStream_concat(OS, "%c", *c); + SStream_concat1(OS, AsmString[I++]); } + } while (AsmString[I] != '\0'); + } + + return tmpString; +} + +static void printCustomAliasOperand( + MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, + SStream *OS) +{ + switch (PrintMethodIdx) { + default: + break; + case 0: + printAddSubImm(MI, OpIdx, OS); + break; + case 1: + printShifter(MI, OpIdx, OS); + break; + case 2: + printArithExtend(MI, OpIdx, OS); + break; + case 3: + printLogicalImm32(MI, OpIdx, OS); + break; + case 4: + printLogicalImm64(MI, OpIdx, OS); + break; + case 5: + printSVERegOp(MI, OpIdx, OS, 'b'); + break; + case 6: + printSVERegOp(MI, OpIdx, OS, 0); + break; + case 7: + printLogicalImm32(MI, OpIdx, OS); + break; + case 8: + printSVERegOp(MI, OpIdx, OS, 'h'); + break; + case 9: + printLogicalImm32(MI, OpIdx, OS); + break; + case 10: + printSVERegOp(MI, OpIdx, OS, 's'); + break; + case 11: + printVRegOperand(MI, OpIdx, OS); + break; + case 12: + printImm(MI, OpIdx, OS); + break; + case 13: + printSVEPattern(MI, OpIdx, OS); + break; + case 14: + printImm8OptLsl32(MI, OpIdx, OS); + break; + case 15: + printSVERegOp(MI, OpIdx, OS, 'd'); + break; + case 16: + printImm8OptLsl64(MI, OpIdx, OS); + break; + case 17: + printImm8OptLsl32(MI, OpIdx, OS); + break; + case 18: + printImm8OptLsl32(MI, OpIdx, OS); + break; + case 19: + printInverseCondCode(MI, OpIdx, OS); + break; + case 20: + printSVELogicalImm16(MI, OpIdx, OS); + break; + case 21: + printSVELogicalImm32(MI, OpIdx, OS); + break; + case 22: + printSVELogicalImm64(MI, OpIdx, OS); + break; + case 23: + printZPRasFPR(MI, OpIdx, OS, 8); + break; + case 24: + printVectorIndex(MI, OpIdx, OS); + break; + case 25: + printZPRasFPR(MI, OpIdx, OS, 64); + break; + case 26: + printZPRasFPR(MI, OpIdx, OS, 16); + break; + case 27: + printSVERegOp(MI, OpIdx, OS, 'q'); + break; + case 28: + printZPRasFPR(MI, OpIdx, OS, 128); + break; + case 29: + printZPRasFPR(MI, OpIdx, OS, 32); + break; + case 30: + printFPImmOperand(MI, OpIdx, OS); + break; + case 31: + printTypedVectorList(MI, OpIdx, OS, 0,'d'); + break; + case 32: + printTypedVectorList(MI, OpIdx, OS, 0,'s'); + break; + case 33: + printPSBHintOp(MI, OpIdx, OS); + break; + case 34: + printTypedVectorList(MI, OpIdx, OS, 0,'h'); + break; + case 35: + printTypedVectorList(MI, OpIdx, OS, 0,'b'); + break; + case 36: + printTypedVectorList(MI, OpIdx, OS, 16, 'b'); + break; + case 37: + printTypedVectorList(MI, OpIdx, OS, 1, 'd'); + break; + case 38: + printTypedVectorList(MI, OpIdx, OS, 2, 'd'); + break; + case 39: + printTypedVectorList(MI, OpIdx, OS, 2, 's'); + break; + case 40: + printTypedVectorList(MI, OpIdx, OS, 4, 'h'); + break; + case 41: + printTypedVectorList(MI, OpIdx, OS, 4, 's'); + break; + case 42: + printTypedVectorList(MI, OpIdx, OS, 8, 'b'); + break; + case 43: + printTypedVectorList(MI, OpIdx, OS, 8, 'h'); + break; + case 44: + printTypedVectorList(MI, OpIdx, OS, 0, 'h'); + break; + case 45: + printTypedVectorList(MI, OpIdx, OS, 0, 's'); + break; + case 46: + printTypedVectorList(MI, OpIdx, OS, 0, 'd'); + break; + case 47: + printTypedVectorList(MI, OpIdx, OS, 0, 'b'); + break; + case 48: + printImmHex(MI, OpIdx, OS); + break; + case 49: + printPrefetchOp(MI, OpIdx, OS, true); + break; + case 50: + printPrefetchOp(MI, OpIdx, OS, false); + break; + case 51: + printGPR64as32(MI, OpIdx, OS); + break; + case 52: + printSysCROperand(MI, OpIdx, OS); + break; + } +} + +static bool AArch64InstPrinterValidateMCOperand(MCOperand *MCOp, + unsigned PredicateIndex) { + int64_t Val; + switch (PredicateIndex) { + default: + return false; // never reach + break; + case 1: { + + if (!MCOperand_isImm(MCOp)) + return false; + Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); + return AArch64_AM_isSVEMaskOfIdenticalElements8(Val); + + } + case 2: { + + if (!MCOperand_isImm(MCOp)) + return false; + Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); + return AArch64_AM_isSVEMaskOfIdenticalElements16(Val); + + } + case 3: { + + if (!MCOperand_isImm(MCOp)) + return false; + Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); + return AArch64_AM_isSVEMaskOfIdenticalElements32(Val); + + } + case 4: { + + return MCOperand_isImm(MCOp) && + MCOperand_getImm(MCOp) != AArch64CC_AL && + MCOperand_getImm(MCOp) != AArch64CC_NV; + + } + case 5: { + + if (!MCOperand_isImm(MCOp)) + return false; + Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); + return AArch64_AM_isSVEMaskOfIdenticalElements16(Val) && + AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); + + } + case 6: { + + if (!MCOperand_isImm(MCOp)) + return false; + Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); + return AArch64_AM_isSVEMaskOfIdenticalElements32(Val) && + AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); + + } + case 7: { + + if (!MCOperand_isImm(MCOp)) + return false; + Val = AArch64_AM_decodeLogicalImmediate(MCOperand_getImm(MCOp), 64); + return AArch64_AM_isSVEMaskOfIdenticalElements64(Val) && + AArch64_AM_isSVEMoveMaskPreferredLogicalImmediate(Val); + + } + case 8: { + + // Check, if operand is valid, to fix exhaustive aliasing in disassembly. + // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. + if (!MCOperand_isImm(MCOp)) + return false; + return AArch64PSBHint_lookupPSBByEncoding(MCOperand_getImm(MCOp)) != NULL; + } } - return tmp; } #endif // PRINT_ALIAS_INSTR diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc index ac4ca8dcb..76323be71 100644 --- a/arch/AArch64/AArch64GenDisassemblerTables.inc +++ b/arch/AArch64/AArch64GenDisassemblerTables.inc @@ -1,23 +1,22 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|* * AArch64 Disassembler *| -|* *| -|* Automatically generated file, do not edit! *| -|* *| -\*===----------------------------------------------------------------------===*/ - /* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ +/* By Nguyen Anh Quynh , 2013-2019 */ +/* Automatically generated file, do not edit! */ #include "../../MCInst.h" #include "../../LEB128.h" + // Helper function for extracting fields from encoded instructions. + +//#if defined(_MSC_VER) && !defined(__clang__) +//__declspec(noinline) +//#endif + #define FieldFromInstruction(fname, InsnType) \ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ { \ InsnType fieldMask; \ - if (numBits == sizeof(InsnType)*8) \ + if (numBits == sizeof(InsnType) * 8) \ fieldMask = (InsnType)(-1LL); \ else \ fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \ @@ -26,12650 +25,22424 @@ static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \ static const uint8_t DecoderTable32[] = { /* 0 */ MCD_OPC_ExtractField, 26, 3, // Inst{28-26} ... -/* 3 */ MCD_OPC_FilterValue, 2, 86, 4, // Skip to: 1117 -/* 7 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 10 */ MCD_OPC_FilterValue, 0, 132, 0, // Skip to: 146 -/* 14 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 17 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 98 -/* 21 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 24 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 47 -/* 28 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 31 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 39 -/* 35 */ MCD_OPC_Decode, 147, 15, 0, // Opcode: STXRB -/* 39 */ MCD_OPC_FilterValue, 1, 150, 158, // Skip to: 40641 -/* 43 */ MCD_OPC_Decode, 191, 14, 0, // Opcode: STLXRB -/* 47 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 70 -/* 51 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 54 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 62 -/* 58 */ MCD_OPC_Decode, 171, 8, 0, // Opcode: LDXRB -/* 62 */ MCD_OPC_FilterValue, 1, 127, 158, // Skip to: 40641 -/* 66 */ MCD_OPC_Decode, 171, 7, 0, // Opcode: LDAXRB -/* 70 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 84 -/* 74 */ MCD_OPC_CheckField, 15, 1, 1, 113, 158, // Skip to: 40641 -/* 80 */ MCD_OPC_Decode, 185, 14, 0, // Opcode: STLRB -/* 84 */ MCD_OPC_FilterValue, 6, 105, 158, // Skip to: 40641 -/* 88 */ MCD_OPC_CheckField, 15, 1, 1, 99, 158, // Skip to: 40641 -/* 94 */ MCD_OPC_Decode, 165, 7, 0, // Opcode: LDARB -/* 98 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 119 -/* 102 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 105 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 112 -/* 109 */ MCD_OPC_Decode, 95, 1, // Opcode: ANDWrs -/* 112 */ MCD_OPC_FilterValue, 1, 77, 158, // Skip to: 40641 -/* 116 */ MCD_OPC_Decode, 111, 1, // Opcode: BICWrs -/* 119 */ MCD_OPC_FilterValue, 3, 70, 158, // Skip to: 40641 -/* 123 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 126 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 133 -/* 130 */ MCD_OPC_Decode, 64, 1, // Opcode: ADDWrs -/* 133 */ MCD_OPC_FilterValue, 1, 56, 158, // Skip to: 40641 -/* 137 */ MCD_OPC_CheckField, 22, 2, 0, 50, 158, // Skip to: 40641 -/* 143 */ MCD_OPC_Decode, 65, 2, // Opcode: ADDWrx -/* 146 */ MCD_OPC_FilterValue, 1, 131, 0, // Skip to: 281 -/* 150 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 153 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 192 -/* 157 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 160 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 168 -/* 164 */ MCD_OPC_Decode, 198, 14, 3, // Opcode: STNPWi -/* 168 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 176 -/* 172 */ MCD_OPC_Decode, 178, 7, 3, // Opcode: LDNPWi -/* 176 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 184 -/* 180 */ MCD_OPC_Decode, 210, 14, 3, // Opcode: STPWpost -/* 184 */ MCD_OPC_FilterValue, 3, 5, 158, // Skip to: 40641 -/* 188 */ MCD_OPC_Decode, 193, 7, 3, // Opcode: LDPWpost -/* 192 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 231 -/* 196 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 199 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 207 -/* 203 */ MCD_OPC_Decode, 209, 14, 3, // Opcode: STPWi -/* 207 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 215 -/* 211 */ MCD_OPC_Decode, 192, 7, 3, // Opcode: LDPWi -/* 215 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 223 -/* 219 */ MCD_OPC_Decode, 211, 14, 3, // Opcode: STPWpre -/* 223 */ MCD_OPC_FilterValue, 3, 222, 157, // Skip to: 40641 -/* 227 */ MCD_OPC_Decode, 194, 7, 3, // Opcode: LDPWpre -/* 231 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 254 -/* 235 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 238 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 246 -/* 242 */ MCD_OPC_Decode, 137, 9, 1, // Opcode: ORRWrs -/* 246 */ MCD_OPC_FilterValue, 1, 199, 157, // Skip to: 40641 -/* 250 */ MCD_OPC_Decode, 130, 9, 1, // Opcode: ORNWrs -/* 254 */ MCD_OPC_FilterValue, 3, 191, 157, // Skip to: 40641 -/* 258 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 261 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 268 -/* 265 */ MCD_OPC_Decode, 50, 1, // Opcode: ADDSWrs -/* 268 */ MCD_OPC_FilterValue, 1, 177, 157, // Skip to: 40641 -/* 272 */ MCD_OPC_CheckField, 22, 2, 0, 171, 157, // Skip to: 40641 -/* 278 */ MCD_OPC_Decode, 51, 2, // Opcode: ADDSWrx -/* 281 */ MCD_OPC_FilterValue, 2, 136, 0, // Skip to: 421 -/* 285 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 288 */ MCD_OPC_FilterValue, 0, 77, 0, // Skip to: 369 -/* 292 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 295 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 318 -/* 299 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 302 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 310 -/* 306 */ MCD_OPC_Decode, 148, 15, 0, // Opcode: STXRH -/* 310 */ MCD_OPC_FilterValue, 1, 135, 157, // Skip to: 40641 -/* 314 */ MCD_OPC_Decode, 192, 14, 0, // Opcode: STLXRH -/* 318 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 341 -/* 322 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 325 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 333 -/* 329 */ MCD_OPC_Decode, 172, 8, 0, // Opcode: LDXRH -/* 333 */ MCD_OPC_FilterValue, 1, 112, 157, // Skip to: 40641 -/* 337 */ MCD_OPC_Decode, 172, 7, 0, // Opcode: LDAXRH -/* 341 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 355 -/* 345 */ MCD_OPC_CheckField, 15, 1, 1, 98, 157, // Skip to: 40641 -/* 351 */ MCD_OPC_Decode, 186, 14, 0, // Opcode: STLRH -/* 355 */ MCD_OPC_FilterValue, 6, 90, 157, // Skip to: 40641 -/* 359 */ MCD_OPC_CheckField, 15, 1, 1, 84, 157, // Skip to: 40641 -/* 365 */ MCD_OPC_Decode, 166, 7, 0, // Opcode: LDARH -/* 369 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 392 -/* 373 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 376 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 384 -/* 380 */ MCD_OPC_Decode, 168, 2, 1, // Opcode: EORWrs -/* 384 */ MCD_OPC_FilterValue, 1, 61, 157, // Skip to: 40641 -/* 388 */ MCD_OPC_Decode, 163, 2, 1, // Opcode: EONWrs -/* 392 */ MCD_OPC_FilterValue, 3, 53, 157, // Skip to: 40641 -/* 396 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 399 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 407 -/* 403 */ MCD_OPC_Decode, 168, 15, 1, // Opcode: SUBWrs -/* 407 */ MCD_OPC_FilterValue, 1, 38, 157, // Skip to: 40641 -/* 411 */ MCD_OPC_CheckField, 22, 2, 0, 32, 157, // Skip to: 40641 -/* 417 */ MCD_OPC_Decode, 169, 15, 2, // Opcode: SUBWrx -/* 421 */ MCD_OPC_FilterValue, 3, 90, 0, // Skip to: 515 -/* 425 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 428 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 442 -/* 432 */ MCD_OPC_CheckField, 22, 2, 3, 11, 157, // Skip to: 40641 -/* 438 */ MCD_OPC_Decode, 187, 7, 3, // Opcode: LDPSWpost -/* 442 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 465 -/* 446 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 449 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 457 -/* 453 */ MCD_OPC_Decode, 186, 7, 3, // Opcode: LDPSWi -/* 457 */ MCD_OPC_FilterValue, 3, 244, 156, // Skip to: 40641 -/* 461 */ MCD_OPC_Decode, 188, 7, 3, // Opcode: LDPSWpre -/* 465 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 486 -/* 469 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 472 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 479 -/* 476 */ MCD_OPC_Decode, 89, 1, // Opcode: ANDSWrs -/* 479 */ MCD_OPC_FilterValue, 1, 222, 156, // Skip to: 40641 -/* 483 */ MCD_OPC_Decode, 107, 1, // Opcode: BICSWrs -/* 486 */ MCD_OPC_FilterValue, 3, 215, 156, // Skip to: 40641 -/* 490 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 493 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 501 -/* 497 */ MCD_OPC_Decode, 159, 15, 1, // Opcode: SUBSWrs -/* 501 */ MCD_OPC_FilterValue, 1, 200, 156, // Skip to: 40641 -/* 505 */ MCD_OPC_CheckField, 22, 2, 0, 194, 156, // Skip to: 40641 -/* 511 */ MCD_OPC_Decode, 160, 15, 2, // Opcode: SUBSWrx -/* 515 */ MCD_OPC_FilterValue, 4, 188, 0, // Skip to: 707 -/* 519 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 522 */ MCD_OPC_FilterValue, 0, 123, 0, // Skip to: 649 -/* 526 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 529 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 552 -/* 533 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 536 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 544 -/* 540 */ MCD_OPC_Decode, 149, 15, 0, // Opcode: STXRW -/* 544 */ MCD_OPC_FilterValue, 1, 157, 156, // Skip to: 40641 -/* 548 */ MCD_OPC_Decode, 193, 14, 0, // Opcode: STLXRW -/* 552 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 575 -/* 556 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 559 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 567 -/* 563 */ MCD_OPC_Decode, 145, 15, 0, // Opcode: STXPW -/* 567 */ MCD_OPC_FilterValue, 1, 134, 156, // Skip to: 40641 -/* 571 */ MCD_OPC_Decode, 189, 14, 0, // Opcode: STLXPW -/* 575 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 598 -/* 579 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 582 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 590 -/* 586 */ MCD_OPC_Decode, 173, 8, 0, // Opcode: LDXRW -/* 590 */ MCD_OPC_FilterValue, 1, 111, 156, // Skip to: 40641 -/* 594 */ MCD_OPC_Decode, 173, 7, 0, // Opcode: LDAXRW -/* 598 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 621 -/* 602 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 605 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 613 -/* 609 */ MCD_OPC_Decode, 169, 8, 0, // Opcode: LDXPW -/* 613 */ MCD_OPC_FilterValue, 1, 88, 156, // Skip to: 40641 -/* 617 */ MCD_OPC_Decode, 169, 7, 0, // Opcode: LDAXPW -/* 621 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 635 -/* 625 */ MCD_OPC_CheckField, 15, 1, 1, 74, 156, // Skip to: 40641 -/* 631 */ MCD_OPC_Decode, 187, 14, 0, // Opcode: STLRW -/* 635 */ MCD_OPC_FilterValue, 6, 66, 156, // Skip to: 40641 -/* 639 */ MCD_OPC_CheckField, 15, 1, 1, 60, 156, // Skip to: 40641 -/* 645 */ MCD_OPC_Decode, 167, 7, 0, // Opcode: LDARW -/* 649 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 670 -/* 653 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 656 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 663 -/* 660 */ MCD_OPC_Decode, 98, 1, // Opcode: ANDXrs -/* 663 */ MCD_OPC_FilterValue, 1, 38, 156, // Skip to: 40641 -/* 667 */ MCD_OPC_Decode, 113, 1, // Opcode: BICXrs -/* 670 */ MCD_OPC_FilterValue, 3, 31, 156, // Skip to: 40641 -/* 674 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 677 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 684 -/* 681 */ MCD_OPC_Decode, 68, 1, // Opcode: ADDXrs -/* 684 */ MCD_OPC_FilterValue, 1, 17, 156, // Skip to: 40641 -/* 688 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 691 */ MCD_OPC_FilterValue, 0, 10, 156, // Skip to: 40641 -/* 695 */ MCD_OPC_CheckField, 13, 2, 3, 3, 0, // Skip to: 704 -/* 701 */ MCD_OPC_Decode, 70, 2, // Opcode: ADDXrx64 -/* 704 */ MCD_OPC_Decode, 69, 2, // Opcode: ADDXrx -/* 707 */ MCD_OPC_FilterValue, 5, 141, 0, // Skip to: 852 -/* 711 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 714 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 753 -/* 718 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 721 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 729 -/* 725 */ MCD_OPC_Decode, 199, 14, 3, // Opcode: STNPXi -/* 729 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 737 -/* 733 */ MCD_OPC_Decode, 179, 7, 3, // Opcode: LDNPXi -/* 737 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 745 -/* 741 */ MCD_OPC_Decode, 213, 14, 3, // Opcode: STPXpost -/* 745 */ MCD_OPC_FilterValue, 3, 212, 155, // Skip to: 40641 -/* 749 */ MCD_OPC_Decode, 196, 7, 3, // Opcode: LDPXpost -/* 753 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 792 -/* 757 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 760 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 768 -/* 764 */ MCD_OPC_Decode, 212, 14, 3, // Opcode: STPXi -/* 768 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 776 -/* 772 */ MCD_OPC_Decode, 195, 7, 3, // Opcode: LDPXi -/* 776 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 784 -/* 780 */ MCD_OPC_Decode, 214, 14, 3, // Opcode: STPXpre -/* 784 */ MCD_OPC_FilterValue, 3, 173, 155, // Skip to: 40641 -/* 788 */ MCD_OPC_Decode, 197, 7, 3, // Opcode: LDPXpre -/* 792 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 815 -/* 796 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 799 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 807 -/* 803 */ MCD_OPC_Decode, 140, 9, 1, // Opcode: ORRXrs -/* 807 */ MCD_OPC_FilterValue, 1, 150, 155, // Skip to: 40641 -/* 811 */ MCD_OPC_Decode, 132, 9, 1, // Opcode: ORNXrs -/* 815 */ MCD_OPC_FilterValue, 3, 142, 155, // Skip to: 40641 -/* 819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 822 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 829 -/* 826 */ MCD_OPC_Decode, 54, 1, // Opcode: ADDSXrs -/* 829 */ MCD_OPC_FilterValue, 1, 128, 155, // Skip to: 40641 -/* 833 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 836 */ MCD_OPC_FilterValue, 0, 121, 155, // Skip to: 40641 -/* 840 */ MCD_OPC_CheckField, 13, 2, 3, 3, 0, // Skip to: 849 -/* 846 */ MCD_OPC_Decode, 56, 2, // Opcode: ADDSXrx64 -/* 849 */ MCD_OPC_Decode, 55, 2, // Opcode: ADDSXrx -/* 852 */ MCD_OPC_FilterValue, 6, 193, 0, // Skip to: 1049 -/* 856 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 859 */ MCD_OPC_FilterValue, 0, 123, 0, // Skip to: 986 -/* 863 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 866 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 889 -/* 870 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 873 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 881 -/* 877 */ MCD_OPC_Decode, 150, 15, 0, // Opcode: STXRX -/* 881 */ MCD_OPC_FilterValue, 1, 76, 155, // Skip to: 40641 -/* 885 */ MCD_OPC_Decode, 194, 14, 0, // Opcode: STLXRX -/* 889 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 912 -/* 893 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 896 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 904 -/* 900 */ MCD_OPC_Decode, 146, 15, 0, // Opcode: STXPX -/* 904 */ MCD_OPC_FilterValue, 1, 53, 155, // Skip to: 40641 -/* 908 */ MCD_OPC_Decode, 190, 14, 0, // Opcode: STLXPX -/* 912 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 935 -/* 916 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 919 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 927 -/* 923 */ MCD_OPC_Decode, 174, 8, 0, // Opcode: LDXRX -/* 927 */ MCD_OPC_FilterValue, 1, 30, 155, // Skip to: 40641 -/* 931 */ MCD_OPC_Decode, 174, 7, 0, // Opcode: LDAXRX -/* 935 */ MCD_OPC_FilterValue, 3, 19, 0, // Skip to: 958 -/* 939 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 942 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 950 -/* 946 */ MCD_OPC_Decode, 170, 8, 0, // Opcode: LDXPX -/* 950 */ MCD_OPC_FilterValue, 1, 7, 155, // Skip to: 40641 -/* 954 */ MCD_OPC_Decode, 170, 7, 0, // Opcode: LDAXPX -/* 958 */ MCD_OPC_FilterValue, 4, 10, 0, // Skip to: 972 -/* 962 */ MCD_OPC_CheckField, 15, 1, 1, 249, 154, // Skip to: 40641 -/* 968 */ MCD_OPC_Decode, 188, 14, 0, // Opcode: STLRX -/* 972 */ MCD_OPC_FilterValue, 6, 241, 154, // Skip to: 40641 -/* 976 */ MCD_OPC_CheckField, 15, 1, 1, 235, 154, // Skip to: 40641 -/* 982 */ MCD_OPC_Decode, 168, 7, 0, // Opcode: LDARX -/* 986 */ MCD_OPC_FilterValue, 2, 19, 0, // Skip to: 1009 -/* 990 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 993 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1001 -/* 997 */ MCD_OPC_Decode, 171, 2, 1, // Opcode: EORXrs -/* 1001 */ MCD_OPC_FilterValue, 1, 212, 154, // Skip to: 40641 -/* 1005 */ MCD_OPC_Decode, 165, 2, 1, // Opcode: EONXrs -/* 1009 */ MCD_OPC_FilterValue, 3, 204, 154, // Skip to: 40641 -/* 1013 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 1016 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1024 -/* 1020 */ MCD_OPC_Decode, 172, 15, 1, // Opcode: SUBXrs -/* 1024 */ MCD_OPC_FilterValue, 1, 189, 154, // Skip to: 40641 -/* 1028 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 1031 */ MCD_OPC_FilterValue, 0, 182, 154, // Skip to: 40641 -/* 1035 */ MCD_OPC_CheckField, 13, 2, 3, 4, 0, // Skip to: 1045 -/* 1041 */ MCD_OPC_Decode, 174, 15, 2, // Opcode: SUBXrx64 -/* 1045 */ MCD_OPC_Decode, 173, 15, 2, // Opcode: SUBXrx -/* 1049 */ MCD_OPC_FilterValue, 7, 164, 154, // Skip to: 40641 -/* 1053 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 1056 */ MCD_OPC_FilterValue, 0, 18, 0, // Skip to: 1078 -/* 1060 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 1063 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1070 -/* 1067 */ MCD_OPC_Decode, 92, 1, // Opcode: ANDSXrs -/* 1070 */ MCD_OPC_FilterValue, 3, 143, 154, // Skip to: 40641 -/* 1074 */ MCD_OPC_Decode, 163, 15, 1, // Opcode: SUBSXrs -/* 1078 */ MCD_OPC_FilterValue, 1, 135, 154, // Skip to: 40641 -/* 1082 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 1085 */ MCD_OPC_FilterValue, 2, 3, 0, // Skip to: 1092 -/* 1089 */ MCD_OPC_Decode, 109, 1, // Opcode: BICSXrs -/* 1092 */ MCD_OPC_FilterValue, 3, 121, 154, // Skip to: 40641 -/* 1096 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 1099 */ MCD_OPC_FilterValue, 0, 114, 154, // Skip to: 40641 -/* 1103 */ MCD_OPC_CheckField, 13, 2, 3, 4, 0, // Skip to: 1113 -/* 1109 */ MCD_OPC_Decode, 165, 15, 2, // Opcode: SUBSXrx64 -/* 1113 */ MCD_OPC_Decode, 164, 15, 2, // Opcode: SUBSXrx -/* 1117 */ MCD_OPC_FilterValue, 3, 236, 110, // Skip to: 29517 -/* 1121 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 1124 */ MCD_OPC_FilterValue, 0, 165, 2, // Skip to: 1805 -/* 1128 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 1131 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 1438 -/* 1135 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 1138 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1150 -/* 1142 */ MCD_OPC_CheckPredicate, 0, 71, 154, // Skip to: 40641 -/* 1146 */ MCD_OPC_Decode, 173, 14, 4, // Opcode: ST4Fourv8b -/* 1150 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1162 -/* 1154 */ MCD_OPC_CheckPredicate, 0, 59, 154, // Skip to: 40641 -/* 1158 */ MCD_OPC_Decode, 169, 14, 4, // Opcode: ST4Fourv4h -/* 1162 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1174 -/* 1166 */ MCD_OPC_CheckPredicate, 0, 47, 154, // Skip to: 40641 -/* 1170 */ MCD_OPC_Decode, 167, 14, 4, // Opcode: ST4Fourv2s -/* 1174 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1186 -/* 1178 */ MCD_OPC_CheckPredicate, 0, 35, 154, // Skip to: 40641 -/* 1182 */ MCD_OPC_Decode, 187, 13, 4, // Opcode: ST1Fourv8b -/* 1186 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1198 -/* 1190 */ MCD_OPC_CheckPredicate, 0, 23, 154, // Skip to: 40641 -/* 1194 */ MCD_OPC_Decode, 183, 13, 4, // Opcode: ST1Fourv4h -/* 1198 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1210 -/* 1202 */ MCD_OPC_CheckPredicate, 0, 11, 154, // Skip to: 40641 -/* 1206 */ MCD_OPC_Decode, 181, 13, 4, // Opcode: ST1Fourv2s -/* 1210 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1222 -/* 1214 */ MCD_OPC_CheckPredicate, 0, 255, 153, // Skip to: 40641 -/* 1218 */ MCD_OPC_Decode, 177, 13, 4, // Opcode: ST1Fourv1d -/* 1222 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1234 -/* 1226 */ MCD_OPC_CheckPredicate, 0, 243, 153, // Skip to: 40641 -/* 1230 */ MCD_OPC_Decode, 151, 14, 5, // Opcode: ST3Threev8b -/* 1234 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1246 -/* 1238 */ MCD_OPC_CheckPredicate, 0, 231, 153, // Skip to: 40641 -/* 1242 */ MCD_OPC_Decode, 147, 14, 5, // Opcode: ST3Threev4h -/* 1246 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1258 -/* 1250 */ MCD_OPC_CheckPredicate, 0, 219, 153, // Skip to: 40641 -/* 1254 */ MCD_OPC_Decode, 145, 14, 5, // Opcode: ST3Threev2s -/* 1258 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1270 -/* 1262 */ MCD_OPC_CheckPredicate, 0, 207, 153, // Skip to: 40641 -/* 1266 */ MCD_OPC_Decode, 219, 13, 5, // Opcode: ST1Threev8b -/* 1270 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1282 -/* 1274 */ MCD_OPC_CheckPredicate, 0, 195, 153, // Skip to: 40641 -/* 1278 */ MCD_OPC_Decode, 215, 13, 5, // Opcode: ST1Threev4h -/* 1282 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1294 -/* 1286 */ MCD_OPC_CheckPredicate, 0, 183, 153, // Skip to: 40641 -/* 1290 */ MCD_OPC_Decode, 213, 13, 5, // Opcode: ST1Threev2s -/* 1294 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1306 -/* 1298 */ MCD_OPC_CheckPredicate, 0, 171, 153, // Skip to: 40641 -/* 1302 */ MCD_OPC_Decode, 209, 13, 5, // Opcode: ST1Threev1d -/* 1306 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1318 -/* 1310 */ MCD_OPC_CheckPredicate, 0, 159, 153, // Skip to: 40641 -/* 1314 */ MCD_OPC_Decode, 203, 13, 6, // Opcode: ST1Onev8b -/* 1318 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1330 -/* 1322 */ MCD_OPC_CheckPredicate, 0, 147, 153, // Skip to: 40641 -/* 1326 */ MCD_OPC_Decode, 199, 13, 6, // Opcode: ST1Onev4h -/* 1330 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 1342 -/* 1334 */ MCD_OPC_CheckPredicate, 0, 135, 153, // Skip to: 40641 -/* 1338 */ MCD_OPC_Decode, 197, 13, 6, // Opcode: ST1Onev2s -/* 1342 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1354 -/* 1346 */ MCD_OPC_CheckPredicate, 0, 123, 153, // Skip to: 40641 -/* 1350 */ MCD_OPC_Decode, 193, 13, 6, // Opcode: ST1Onev1d -/* 1354 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 1366 -/* 1358 */ MCD_OPC_CheckPredicate, 0, 111, 153, // Skip to: 40641 -/* 1362 */ MCD_OPC_Decode, 129, 14, 7, // Opcode: ST2Twov8b -/* 1366 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 1378 -/* 1370 */ MCD_OPC_CheckPredicate, 0, 99, 153, // Skip to: 40641 -/* 1374 */ MCD_OPC_Decode, 253, 13, 7, // Opcode: ST2Twov4h -/* 1378 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 1390 -/* 1382 */ MCD_OPC_CheckPredicate, 0, 87, 153, // Skip to: 40641 -/* 1386 */ MCD_OPC_Decode, 251, 13, 7, // Opcode: ST2Twov2s -/* 1390 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 1402 -/* 1394 */ MCD_OPC_CheckPredicate, 0, 75, 153, // Skip to: 40641 -/* 1398 */ MCD_OPC_Decode, 235, 13, 7, // Opcode: ST1Twov8b -/* 1402 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 1414 -/* 1406 */ MCD_OPC_CheckPredicate, 0, 63, 153, // Skip to: 40641 -/* 1410 */ MCD_OPC_Decode, 231, 13, 7, // Opcode: ST1Twov4h -/* 1414 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 1426 -/* 1418 */ MCD_OPC_CheckPredicate, 0, 51, 153, // Skip to: 40641 -/* 1422 */ MCD_OPC_Decode, 229, 13, 7, // Opcode: ST1Twov2s -/* 1426 */ MCD_OPC_FilterValue, 43, 43, 153, // Skip to: 40641 -/* 1430 */ MCD_OPC_CheckPredicate, 0, 39, 153, // Skip to: 40641 -/* 1434 */ MCD_OPC_Decode, 225, 13, 7, // Opcode: ST1Twov1d -/* 1438 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1446 -/* 1442 */ MCD_OPC_Decode, 197, 14, 3, // Opcode: STNPSi -/* 1446 */ MCD_OPC_FilterValue, 2, 83, 1, // Skip to: 1789 -/* 1450 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 1453 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1465 -/* 1457 */ MCD_OPC_CheckPredicate, 0, 12, 153, // Skip to: 40641 -/* 1461 */ MCD_OPC_Decode, 163, 14, 8, // Opcode: ST4Fourv16b -/* 1465 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1477 -/* 1469 */ MCD_OPC_CheckPredicate, 0, 0, 153, // Skip to: 40641 -/* 1473 */ MCD_OPC_Decode, 175, 14, 8, // Opcode: ST4Fourv8h -/* 1477 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1489 -/* 1481 */ MCD_OPC_CheckPredicate, 0, 244, 152, // Skip to: 40641 -/* 1485 */ MCD_OPC_Decode, 171, 14, 8, // Opcode: ST4Fourv4s -/* 1489 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 1501 -/* 1493 */ MCD_OPC_CheckPredicate, 0, 232, 152, // Skip to: 40641 -/* 1497 */ MCD_OPC_Decode, 165, 14, 8, // Opcode: ST4Fourv2d -/* 1501 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1513 -/* 1505 */ MCD_OPC_CheckPredicate, 0, 220, 152, // Skip to: 40641 -/* 1509 */ MCD_OPC_Decode, 175, 13, 8, // Opcode: ST1Fourv16b -/* 1513 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1525 -/* 1517 */ MCD_OPC_CheckPredicate, 0, 208, 152, // Skip to: 40641 -/* 1521 */ MCD_OPC_Decode, 189, 13, 8, // Opcode: ST1Fourv8h -/* 1525 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1537 -/* 1529 */ MCD_OPC_CheckPredicate, 0, 196, 152, // Skip to: 40641 -/* 1533 */ MCD_OPC_Decode, 185, 13, 8, // Opcode: ST1Fourv4s -/* 1537 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1549 -/* 1541 */ MCD_OPC_CheckPredicate, 0, 184, 152, // Skip to: 40641 -/* 1545 */ MCD_OPC_Decode, 179, 13, 8, // Opcode: ST1Fourv2d -/* 1549 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1561 -/* 1553 */ MCD_OPC_CheckPredicate, 0, 172, 152, // Skip to: 40641 -/* 1557 */ MCD_OPC_Decode, 141, 14, 9, // Opcode: ST3Threev16b -/* 1561 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1573 -/* 1565 */ MCD_OPC_CheckPredicate, 0, 160, 152, // Skip to: 40641 -/* 1569 */ MCD_OPC_Decode, 153, 14, 9, // Opcode: ST3Threev8h -/* 1573 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1585 -/* 1577 */ MCD_OPC_CheckPredicate, 0, 148, 152, // Skip to: 40641 -/* 1581 */ MCD_OPC_Decode, 149, 14, 9, // Opcode: ST3Threev4s -/* 1585 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 1597 -/* 1589 */ MCD_OPC_CheckPredicate, 0, 136, 152, // Skip to: 40641 -/* 1593 */ MCD_OPC_Decode, 143, 14, 9, // Opcode: ST3Threev2d -/* 1597 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1609 -/* 1601 */ MCD_OPC_CheckPredicate, 0, 124, 152, // Skip to: 40641 -/* 1605 */ MCD_OPC_Decode, 207, 13, 9, // Opcode: ST1Threev16b -/* 1609 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1621 -/* 1613 */ MCD_OPC_CheckPredicate, 0, 112, 152, // Skip to: 40641 -/* 1617 */ MCD_OPC_Decode, 221, 13, 9, // Opcode: ST1Threev8h -/* 1621 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1633 -/* 1625 */ MCD_OPC_CheckPredicate, 0, 100, 152, // Skip to: 40641 -/* 1629 */ MCD_OPC_Decode, 217, 13, 9, // Opcode: ST1Threev4s -/* 1633 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1645 -/* 1637 */ MCD_OPC_CheckPredicate, 0, 88, 152, // Skip to: 40641 -/* 1641 */ MCD_OPC_Decode, 211, 13, 9, // Opcode: ST1Threev2d -/* 1645 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1657 -/* 1649 */ MCD_OPC_CheckPredicate, 0, 76, 152, // Skip to: 40641 -/* 1653 */ MCD_OPC_Decode, 191, 13, 10, // Opcode: ST1Onev16b -/* 1657 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 1669 -/* 1661 */ MCD_OPC_CheckPredicate, 0, 64, 152, // Skip to: 40641 -/* 1665 */ MCD_OPC_Decode, 205, 13, 10, // Opcode: ST1Onev8h -/* 1669 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 1681 -/* 1673 */ MCD_OPC_CheckPredicate, 0, 52, 152, // Skip to: 40641 -/* 1677 */ MCD_OPC_Decode, 201, 13, 10, // Opcode: ST1Onev4s -/* 1681 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 1693 -/* 1685 */ MCD_OPC_CheckPredicate, 0, 40, 152, // Skip to: 40641 -/* 1689 */ MCD_OPC_Decode, 195, 13, 10, // Opcode: ST1Onev2d -/* 1693 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 1705 -/* 1697 */ MCD_OPC_CheckPredicate, 0, 28, 152, // Skip to: 40641 -/* 1701 */ MCD_OPC_Decode, 247, 13, 11, // Opcode: ST2Twov16b -/* 1705 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 1717 -/* 1709 */ MCD_OPC_CheckPredicate, 0, 16, 152, // Skip to: 40641 -/* 1713 */ MCD_OPC_Decode, 131, 14, 11, // Opcode: ST2Twov8h -/* 1717 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 1729 -/* 1721 */ MCD_OPC_CheckPredicate, 0, 4, 152, // Skip to: 40641 -/* 1725 */ MCD_OPC_Decode, 255, 13, 11, // Opcode: ST2Twov4s -/* 1729 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 1741 -/* 1733 */ MCD_OPC_CheckPredicate, 0, 248, 151, // Skip to: 40641 -/* 1737 */ MCD_OPC_Decode, 249, 13, 11, // Opcode: ST2Twov2d -/* 1741 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 1753 -/* 1745 */ MCD_OPC_CheckPredicate, 0, 236, 151, // Skip to: 40641 -/* 1749 */ MCD_OPC_Decode, 223, 13, 11, // Opcode: ST1Twov16b -/* 1753 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 1765 -/* 1757 */ MCD_OPC_CheckPredicate, 0, 224, 151, // Skip to: 40641 -/* 1761 */ MCD_OPC_Decode, 237, 13, 11, // Opcode: ST1Twov8h -/* 1765 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 1777 -/* 1769 */ MCD_OPC_CheckPredicate, 0, 212, 151, // Skip to: 40641 -/* 1773 */ MCD_OPC_Decode, 233, 13, 11, // Opcode: ST1Twov4s -/* 1777 */ MCD_OPC_FilterValue, 43, 204, 151, // Skip to: 40641 -/* 1781 */ MCD_OPC_CheckPredicate, 0, 200, 151, // Skip to: 40641 -/* 1785 */ MCD_OPC_Decode, 227, 13, 11, // Opcode: ST1Twov2d -/* 1789 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1797 -/* 1793 */ MCD_OPC_Decode, 195, 14, 3, // Opcode: STNPDi -/* 1797 */ MCD_OPC_FilterValue, 5, 184, 151, // Skip to: 40641 -/* 1801 */ MCD_OPC_Decode, 196, 14, 3, // Opcode: STNPQi -/* 1805 */ MCD_OPC_FilterValue, 1, 165, 2, // Skip to: 2486 -/* 1809 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 1812 */ MCD_OPC_FilterValue, 0, 47, 1, // Skip to: 2119 -/* 1816 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 1819 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 1831 -/* 1823 */ MCD_OPC_CheckPredicate, 0, 158, 151, // Skip to: 40641 -/* 1827 */ MCD_OPC_Decode, 137, 7, 4, // Opcode: LD4Fourv8b -/* 1831 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 1843 -/* 1835 */ MCD_OPC_CheckPredicate, 0, 146, 151, // Skip to: 40641 -/* 1839 */ MCD_OPC_Decode, 133, 7, 4, // Opcode: LD4Fourv4h -/* 1843 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 1855 -/* 1847 */ MCD_OPC_CheckPredicate, 0, 134, 151, // Skip to: 40641 -/* 1851 */ MCD_OPC_Decode, 131, 7, 4, // Opcode: LD4Fourv2s -/* 1855 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 1867 -/* 1859 */ MCD_OPC_CheckPredicate, 0, 122, 151, // Skip to: 40641 -/* 1863 */ MCD_OPC_Decode, 231, 5, 4, // Opcode: LD1Fourv8b -/* 1867 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 1879 -/* 1871 */ MCD_OPC_CheckPredicate, 0, 110, 151, // Skip to: 40641 -/* 1875 */ MCD_OPC_Decode, 227, 5, 4, // Opcode: LD1Fourv4h -/* 1879 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 1891 -/* 1883 */ MCD_OPC_CheckPredicate, 0, 98, 151, // Skip to: 40641 -/* 1887 */ MCD_OPC_Decode, 225, 5, 4, // Opcode: LD1Fourv2s -/* 1891 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 1903 -/* 1895 */ MCD_OPC_CheckPredicate, 0, 86, 151, // Skip to: 40641 -/* 1899 */ MCD_OPC_Decode, 221, 5, 4, // Opcode: LD1Fourv1d -/* 1903 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 1915 -/* 1907 */ MCD_OPC_CheckPredicate, 0, 74, 151, // Skip to: 40641 -/* 1911 */ MCD_OPC_Decode, 243, 6, 5, // Opcode: LD3Threev8b -/* 1915 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 1927 -/* 1919 */ MCD_OPC_CheckPredicate, 0, 62, 151, // Skip to: 40641 -/* 1923 */ MCD_OPC_Decode, 239, 6, 5, // Opcode: LD3Threev4h -/* 1927 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 1939 -/* 1931 */ MCD_OPC_CheckPredicate, 0, 50, 151, // Skip to: 40641 -/* 1935 */ MCD_OPC_Decode, 237, 6, 5, // Opcode: LD3Threev2s -/* 1939 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 1951 -/* 1943 */ MCD_OPC_CheckPredicate, 0, 38, 151, // Skip to: 40641 -/* 1947 */ MCD_OPC_Decode, 151, 6, 5, // Opcode: LD1Threev8b -/* 1951 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 1963 -/* 1955 */ MCD_OPC_CheckPredicate, 0, 26, 151, // Skip to: 40641 -/* 1959 */ MCD_OPC_Decode, 147, 6, 5, // Opcode: LD1Threev4h -/* 1963 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 1975 -/* 1967 */ MCD_OPC_CheckPredicate, 0, 14, 151, // Skip to: 40641 -/* 1971 */ MCD_OPC_Decode, 145, 6, 5, // Opcode: LD1Threev2s -/* 1975 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 1987 -/* 1979 */ MCD_OPC_CheckPredicate, 0, 2, 151, // Skip to: 40641 -/* 1983 */ MCD_OPC_Decode, 141, 6, 5, // Opcode: LD1Threev1d -/* 1987 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 1999 -/* 1991 */ MCD_OPC_CheckPredicate, 0, 246, 150, // Skip to: 40641 -/* 1995 */ MCD_OPC_Decode, 247, 5, 6, // Opcode: LD1Onev8b -/* 1999 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 2011 -/* 2003 */ MCD_OPC_CheckPredicate, 0, 234, 150, // Skip to: 40641 -/* 2007 */ MCD_OPC_Decode, 243, 5, 6, // Opcode: LD1Onev4h -/* 2011 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 2023 -/* 2015 */ MCD_OPC_CheckPredicate, 0, 222, 150, // Skip to: 40641 -/* 2019 */ MCD_OPC_Decode, 241, 5, 6, // Opcode: LD1Onev2s -/* 2023 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 2035 -/* 2027 */ MCD_OPC_CheckPredicate, 0, 210, 150, // Skip to: 40641 -/* 2031 */ MCD_OPC_Decode, 237, 5, 6, // Opcode: LD1Onev1d -/* 2035 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 2047 -/* 2039 */ MCD_OPC_CheckPredicate, 0, 198, 150, // Skip to: 40641 -/* 2043 */ MCD_OPC_Decode, 205, 6, 7, // Opcode: LD2Twov8b -/* 2047 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 2059 -/* 2051 */ MCD_OPC_CheckPredicate, 0, 186, 150, // Skip to: 40641 -/* 2055 */ MCD_OPC_Decode, 201, 6, 7, // Opcode: LD2Twov4h -/* 2059 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 2071 -/* 2063 */ MCD_OPC_CheckPredicate, 0, 174, 150, // Skip to: 40641 -/* 2067 */ MCD_OPC_Decode, 199, 6, 7, // Opcode: LD2Twov2s -/* 2071 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 2083 -/* 2075 */ MCD_OPC_CheckPredicate, 0, 162, 150, // Skip to: 40641 -/* 2079 */ MCD_OPC_Decode, 167, 6, 7, // Opcode: LD1Twov8b -/* 2083 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 2095 -/* 2087 */ MCD_OPC_CheckPredicate, 0, 150, 150, // Skip to: 40641 -/* 2091 */ MCD_OPC_Decode, 163, 6, 7, // Opcode: LD1Twov4h -/* 2095 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 2107 -/* 2099 */ MCD_OPC_CheckPredicate, 0, 138, 150, // Skip to: 40641 -/* 2103 */ MCD_OPC_Decode, 161, 6, 7, // Opcode: LD1Twov2s -/* 2107 */ MCD_OPC_FilterValue, 43, 130, 150, // Skip to: 40641 -/* 2111 */ MCD_OPC_CheckPredicate, 0, 126, 150, // Skip to: 40641 -/* 2115 */ MCD_OPC_Decode, 157, 6, 7, // Opcode: LD1Twov1d -/* 2119 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2127 -/* 2123 */ MCD_OPC_Decode, 177, 7, 3, // Opcode: LDNPSi -/* 2127 */ MCD_OPC_FilterValue, 2, 83, 1, // Skip to: 2470 -/* 2131 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... -/* 2134 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 2146 -/* 2138 */ MCD_OPC_CheckPredicate, 0, 99, 150, // Skip to: 40641 -/* 2142 */ MCD_OPC_Decode, 255, 6, 8, // Opcode: LD4Fourv16b -/* 2146 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 2158 -/* 2150 */ MCD_OPC_CheckPredicate, 0, 87, 150, // Skip to: 40641 -/* 2154 */ MCD_OPC_Decode, 139, 7, 8, // Opcode: LD4Fourv8h -/* 2158 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 2170 -/* 2162 */ MCD_OPC_CheckPredicate, 0, 75, 150, // Skip to: 40641 -/* 2166 */ MCD_OPC_Decode, 135, 7, 8, // Opcode: LD4Fourv4s -/* 2170 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 2182 -/* 2174 */ MCD_OPC_CheckPredicate, 0, 63, 150, // Skip to: 40641 -/* 2178 */ MCD_OPC_Decode, 129, 7, 8, // Opcode: LD4Fourv2d -/* 2182 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 2194 -/* 2186 */ MCD_OPC_CheckPredicate, 0, 51, 150, // Skip to: 40641 -/* 2190 */ MCD_OPC_Decode, 219, 5, 8, // Opcode: LD1Fourv16b -/* 2194 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 2206 -/* 2198 */ MCD_OPC_CheckPredicate, 0, 39, 150, // Skip to: 40641 -/* 2202 */ MCD_OPC_Decode, 233, 5, 8, // Opcode: LD1Fourv8h -/* 2206 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 2218 -/* 2210 */ MCD_OPC_CheckPredicate, 0, 27, 150, // Skip to: 40641 -/* 2214 */ MCD_OPC_Decode, 229, 5, 8, // Opcode: LD1Fourv4s -/* 2218 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 2230 -/* 2222 */ MCD_OPC_CheckPredicate, 0, 15, 150, // Skip to: 40641 -/* 2226 */ MCD_OPC_Decode, 223, 5, 8, // Opcode: LD1Fourv2d -/* 2230 */ MCD_OPC_FilterValue, 16, 8, 0, // Skip to: 2242 -/* 2234 */ MCD_OPC_CheckPredicate, 0, 3, 150, // Skip to: 40641 -/* 2238 */ MCD_OPC_Decode, 233, 6, 9, // Opcode: LD3Threev16b -/* 2242 */ MCD_OPC_FilterValue, 17, 8, 0, // Skip to: 2254 -/* 2246 */ MCD_OPC_CheckPredicate, 0, 247, 149, // Skip to: 40641 -/* 2250 */ MCD_OPC_Decode, 245, 6, 9, // Opcode: LD3Threev8h -/* 2254 */ MCD_OPC_FilterValue, 18, 8, 0, // Skip to: 2266 -/* 2258 */ MCD_OPC_CheckPredicate, 0, 235, 149, // Skip to: 40641 -/* 2262 */ MCD_OPC_Decode, 241, 6, 9, // Opcode: LD3Threev4s -/* 2266 */ MCD_OPC_FilterValue, 19, 8, 0, // Skip to: 2278 -/* 2270 */ MCD_OPC_CheckPredicate, 0, 223, 149, // Skip to: 40641 -/* 2274 */ MCD_OPC_Decode, 235, 6, 9, // Opcode: LD3Threev2d -/* 2278 */ MCD_OPC_FilterValue, 24, 8, 0, // Skip to: 2290 -/* 2282 */ MCD_OPC_CheckPredicate, 0, 211, 149, // Skip to: 40641 -/* 2286 */ MCD_OPC_Decode, 139, 6, 9, // Opcode: LD1Threev16b -/* 2290 */ MCD_OPC_FilterValue, 25, 8, 0, // Skip to: 2302 -/* 2294 */ MCD_OPC_CheckPredicate, 0, 199, 149, // Skip to: 40641 -/* 2298 */ MCD_OPC_Decode, 153, 6, 9, // Opcode: LD1Threev8h -/* 2302 */ MCD_OPC_FilterValue, 26, 8, 0, // Skip to: 2314 -/* 2306 */ MCD_OPC_CheckPredicate, 0, 187, 149, // Skip to: 40641 -/* 2310 */ MCD_OPC_Decode, 149, 6, 9, // Opcode: LD1Threev4s -/* 2314 */ MCD_OPC_FilterValue, 27, 8, 0, // Skip to: 2326 -/* 2318 */ MCD_OPC_CheckPredicate, 0, 175, 149, // Skip to: 40641 -/* 2322 */ MCD_OPC_Decode, 143, 6, 9, // Opcode: LD1Threev2d -/* 2326 */ MCD_OPC_FilterValue, 28, 8, 0, // Skip to: 2338 -/* 2330 */ MCD_OPC_CheckPredicate, 0, 163, 149, // Skip to: 40641 -/* 2334 */ MCD_OPC_Decode, 235, 5, 10, // Opcode: LD1Onev16b -/* 2338 */ MCD_OPC_FilterValue, 29, 8, 0, // Skip to: 2350 -/* 2342 */ MCD_OPC_CheckPredicate, 0, 151, 149, // Skip to: 40641 -/* 2346 */ MCD_OPC_Decode, 249, 5, 10, // Opcode: LD1Onev8h -/* 2350 */ MCD_OPC_FilterValue, 30, 8, 0, // Skip to: 2362 -/* 2354 */ MCD_OPC_CheckPredicate, 0, 139, 149, // Skip to: 40641 -/* 2358 */ MCD_OPC_Decode, 245, 5, 10, // Opcode: LD1Onev4s -/* 2362 */ MCD_OPC_FilterValue, 31, 8, 0, // Skip to: 2374 -/* 2366 */ MCD_OPC_CheckPredicate, 0, 127, 149, // Skip to: 40641 -/* 2370 */ MCD_OPC_Decode, 239, 5, 10, // Opcode: LD1Onev2d -/* 2374 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 2386 -/* 2378 */ MCD_OPC_CheckPredicate, 0, 115, 149, // Skip to: 40641 -/* 2382 */ MCD_OPC_Decode, 195, 6, 11, // Opcode: LD2Twov16b -/* 2386 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 2398 -/* 2390 */ MCD_OPC_CheckPredicate, 0, 103, 149, // Skip to: 40641 -/* 2394 */ MCD_OPC_Decode, 207, 6, 11, // Opcode: LD2Twov8h -/* 2398 */ MCD_OPC_FilterValue, 34, 8, 0, // Skip to: 2410 -/* 2402 */ MCD_OPC_CheckPredicate, 0, 91, 149, // Skip to: 40641 -/* 2406 */ MCD_OPC_Decode, 203, 6, 11, // Opcode: LD2Twov4s -/* 2410 */ MCD_OPC_FilterValue, 35, 8, 0, // Skip to: 2422 -/* 2414 */ MCD_OPC_CheckPredicate, 0, 79, 149, // Skip to: 40641 -/* 2418 */ MCD_OPC_Decode, 197, 6, 11, // Opcode: LD2Twov2d -/* 2422 */ MCD_OPC_FilterValue, 40, 8, 0, // Skip to: 2434 -/* 2426 */ MCD_OPC_CheckPredicate, 0, 67, 149, // Skip to: 40641 -/* 2430 */ MCD_OPC_Decode, 155, 6, 11, // Opcode: LD1Twov16b -/* 2434 */ MCD_OPC_FilterValue, 41, 8, 0, // Skip to: 2446 -/* 2438 */ MCD_OPC_CheckPredicate, 0, 55, 149, // Skip to: 40641 -/* 2442 */ MCD_OPC_Decode, 169, 6, 11, // Opcode: LD1Twov8h -/* 2446 */ MCD_OPC_FilterValue, 42, 8, 0, // Skip to: 2458 -/* 2450 */ MCD_OPC_CheckPredicate, 0, 43, 149, // Skip to: 40641 -/* 2454 */ MCD_OPC_Decode, 165, 6, 11, // Opcode: LD1Twov4s -/* 2458 */ MCD_OPC_FilterValue, 43, 35, 149, // Skip to: 40641 -/* 2462 */ MCD_OPC_CheckPredicate, 0, 31, 149, // Skip to: 40641 -/* 2466 */ MCD_OPC_Decode, 159, 6, 11, // Opcode: LD1Twov2d -/* 2470 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2478 -/* 2474 */ MCD_OPC_Decode, 175, 7, 3, // Opcode: LDNPDi -/* 2478 */ MCD_OPC_FilterValue, 5, 15, 149, // Skip to: 40641 -/* 2482 */ MCD_OPC_Decode, 176, 7, 3, // Opcode: LDNPQi -/* 2486 */ MCD_OPC_FilterValue, 2, 227, 3, // Skip to: 3485 -/* 2490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 2493 */ MCD_OPC_FilterValue, 0, 197, 1, // Skip to: 2950 -/* 2497 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 2500 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2518 -/* 2504 */ MCD_OPC_CheckPredicate, 0, 245, 148, // Skip to: 40641 -/* 2508 */ MCD_OPC_CheckField, 21, 1, 0, 239, 148, // Skip to: 40641 -/* 2514 */ MCD_OPC_Decode, 174, 14, 12, // Opcode: ST4Fourv8b_POST -/* 2518 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 2536 -/* 2522 */ MCD_OPC_CheckPredicate, 0, 227, 148, // Skip to: 40641 -/* 2526 */ MCD_OPC_CheckField, 21, 1, 0, 221, 148, // Skip to: 40641 -/* 2532 */ MCD_OPC_Decode, 170, 14, 12, // Opcode: ST4Fourv4h_POST -/* 2536 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 2554 -/* 2540 */ MCD_OPC_CheckPredicate, 0, 209, 148, // Skip to: 40641 -/* 2544 */ MCD_OPC_CheckField, 21, 1, 0, 203, 148, // Skip to: 40641 -/* 2550 */ MCD_OPC_Decode, 168, 14, 12, // Opcode: ST4Fourv2s_POST -/* 2554 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 2572 -/* 2558 */ MCD_OPC_CheckPredicate, 0, 191, 148, // Skip to: 40641 -/* 2562 */ MCD_OPC_CheckField, 21, 1, 0, 185, 148, // Skip to: 40641 -/* 2568 */ MCD_OPC_Decode, 188, 13, 12, // Opcode: ST1Fourv8b_POST -/* 2572 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 2590 -/* 2576 */ MCD_OPC_CheckPredicate, 0, 173, 148, // Skip to: 40641 -/* 2580 */ MCD_OPC_CheckField, 21, 1, 0, 167, 148, // Skip to: 40641 -/* 2586 */ MCD_OPC_Decode, 184, 13, 12, // Opcode: ST1Fourv4h_POST -/* 2590 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 2608 -/* 2594 */ MCD_OPC_CheckPredicate, 0, 155, 148, // Skip to: 40641 -/* 2598 */ MCD_OPC_CheckField, 21, 1, 0, 149, 148, // Skip to: 40641 -/* 2604 */ MCD_OPC_Decode, 182, 13, 12, // Opcode: ST1Fourv2s_POST -/* 2608 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 2626 -/* 2612 */ MCD_OPC_CheckPredicate, 0, 137, 148, // Skip to: 40641 -/* 2616 */ MCD_OPC_CheckField, 21, 1, 0, 131, 148, // Skip to: 40641 -/* 2622 */ MCD_OPC_Decode, 178, 13, 12, // Opcode: ST1Fourv1d_POST -/* 2626 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 2644 -/* 2630 */ MCD_OPC_CheckPredicate, 0, 119, 148, // Skip to: 40641 -/* 2634 */ MCD_OPC_CheckField, 21, 1, 0, 113, 148, // Skip to: 40641 -/* 2640 */ MCD_OPC_Decode, 152, 14, 13, // Opcode: ST3Threev8b_POST -/* 2644 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 2662 -/* 2648 */ MCD_OPC_CheckPredicate, 0, 101, 148, // Skip to: 40641 -/* 2652 */ MCD_OPC_CheckField, 21, 1, 0, 95, 148, // Skip to: 40641 -/* 2658 */ MCD_OPC_Decode, 148, 14, 13, // Opcode: ST3Threev4h_POST -/* 2662 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 2680 -/* 2666 */ MCD_OPC_CheckPredicate, 0, 83, 148, // Skip to: 40641 -/* 2670 */ MCD_OPC_CheckField, 21, 1, 0, 77, 148, // Skip to: 40641 -/* 2676 */ MCD_OPC_Decode, 146, 14, 13, // Opcode: ST3Threev2s_POST -/* 2680 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 2698 -/* 2684 */ MCD_OPC_CheckPredicate, 0, 65, 148, // Skip to: 40641 -/* 2688 */ MCD_OPC_CheckField, 21, 1, 0, 59, 148, // Skip to: 40641 -/* 2694 */ MCD_OPC_Decode, 220, 13, 13, // Opcode: ST1Threev8b_POST -/* 2698 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 2716 -/* 2702 */ MCD_OPC_CheckPredicate, 0, 47, 148, // Skip to: 40641 -/* 2706 */ MCD_OPC_CheckField, 21, 1, 0, 41, 148, // Skip to: 40641 -/* 2712 */ MCD_OPC_Decode, 216, 13, 13, // Opcode: ST1Threev4h_POST -/* 2716 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 2734 -/* 2720 */ MCD_OPC_CheckPredicate, 0, 29, 148, // Skip to: 40641 -/* 2724 */ MCD_OPC_CheckField, 21, 1, 0, 23, 148, // Skip to: 40641 -/* 2730 */ MCD_OPC_Decode, 214, 13, 13, // Opcode: ST1Threev2s_POST -/* 2734 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 2752 -/* 2738 */ MCD_OPC_CheckPredicate, 0, 11, 148, // Skip to: 40641 -/* 2742 */ MCD_OPC_CheckField, 21, 1, 0, 5, 148, // Skip to: 40641 -/* 2748 */ MCD_OPC_Decode, 210, 13, 13, // Opcode: ST1Threev1d_POST -/* 2752 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 2770 -/* 2756 */ MCD_OPC_CheckPredicate, 0, 249, 147, // Skip to: 40641 -/* 2760 */ MCD_OPC_CheckField, 21, 1, 0, 243, 147, // Skip to: 40641 -/* 2766 */ MCD_OPC_Decode, 204, 13, 14, // Opcode: ST1Onev8b_POST -/* 2770 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 2788 -/* 2774 */ MCD_OPC_CheckPredicate, 0, 231, 147, // Skip to: 40641 -/* 2778 */ MCD_OPC_CheckField, 21, 1, 0, 225, 147, // Skip to: 40641 -/* 2784 */ MCD_OPC_Decode, 200, 13, 14, // Opcode: ST1Onev4h_POST -/* 2788 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 2806 -/* 2792 */ MCD_OPC_CheckPredicate, 0, 213, 147, // Skip to: 40641 -/* 2796 */ MCD_OPC_CheckField, 21, 1, 0, 207, 147, // Skip to: 40641 -/* 2802 */ MCD_OPC_Decode, 198, 13, 14, // Opcode: ST1Onev2s_POST -/* 2806 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 2824 -/* 2810 */ MCD_OPC_CheckPredicate, 0, 195, 147, // Skip to: 40641 -/* 2814 */ MCD_OPC_CheckField, 21, 1, 0, 189, 147, // Skip to: 40641 -/* 2820 */ MCD_OPC_Decode, 194, 13, 14, // Opcode: ST1Onev1d_POST -/* 2824 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 2842 -/* 2828 */ MCD_OPC_CheckPredicate, 0, 177, 147, // Skip to: 40641 -/* 2832 */ MCD_OPC_CheckField, 21, 1, 0, 171, 147, // Skip to: 40641 -/* 2838 */ MCD_OPC_Decode, 130, 14, 15, // Opcode: ST2Twov8b_POST -/* 2842 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 2860 -/* 2846 */ MCD_OPC_CheckPredicate, 0, 159, 147, // Skip to: 40641 -/* 2850 */ MCD_OPC_CheckField, 21, 1, 0, 153, 147, // Skip to: 40641 -/* 2856 */ MCD_OPC_Decode, 254, 13, 15, // Opcode: ST2Twov4h_POST -/* 2860 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 2878 -/* 2864 */ MCD_OPC_CheckPredicate, 0, 141, 147, // Skip to: 40641 -/* 2868 */ MCD_OPC_CheckField, 21, 1, 0, 135, 147, // Skip to: 40641 -/* 2874 */ MCD_OPC_Decode, 252, 13, 15, // Opcode: ST2Twov2s_POST -/* 2878 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 2896 -/* 2882 */ MCD_OPC_CheckPredicate, 0, 123, 147, // Skip to: 40641 -/* 2886 */ MCD_OPC_CheckField, 21, 1, 0, 117, 147, // Skip to: 40641 -/* 2892 */ MCD_OPC_Decode, 236, 13, 15, // Opcode: ST1Twov8b_POST -/* 2896 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 2914 -/* 2900 */ MCD_OPC_CheckPredicate, 0, 105, 147, // Skip to: 40641 -/* 2904 */ MCD_OPC_CheckField, 21, 1, 0, 99, 147, // Skip to: 40641 -/* 2910 */ MCD_OPC_Decode, 232, 13, 15, // Opcode: ST1Twov4h_POST -/* 2914 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 2932 -/* 2918 */ MCD_OPC_CheckPredicate, 0, 87, 147, // Skip to: 40641 -/* 2922 */ MCD_OPC_CheckField, 21, 1, 0, 81, 147, // Skip to: 40641 -/* 2928 */ MCD_OPC_Decode, 230, 13, 15, // Opcode: ST1Twov2s_POST -/* 2932 */ MCD_OPC_FilterValue, 43, 73, 147, // Skip to: 40641 -/* 2936 */ MCD_OPC_CheckPredicate, 0, 69, 147, // Skip to: 40641 -/* 2940 */ MCD_OPC_CheckField, 21, 1, 0, 63, 147, // Skip to: 40641 -/* 2946 */ MCD_OPC_Decode, 226, 13, 15, // Opcode: ST1Twov1d_POST -/* 2950 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2958 -/* 2954 */ MCD_OPC_Decode, 207, 14, 3, // Opcode: STPSpost -/* 2958 */ MCD_OPC_FilterValue, 2, 251, 1, // Skip to: 3469 -/* 2962 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 2965 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 2983 -/* 2969 */ MCD_OPC_CheckPredicate, 0, 36, 147, // Skip to: 40641 -/* 2973 */ MCD_OPC_CheckField, 21, 1, 0, 30, 147, // Skip to: 40641 -/* 2979 */ MCD_OPC_Decode, 164, 14, 16, // Opcode: ST4Fourv16b_POST -/* 2983 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3001 -/* 2987 */ MCD_OPC_CheckPredicate, 0, 18, 147, // Skip to: 40641 -/* 2991 */ MCD_OPC_CheckField, 21, 1, 0, 12, 147, // Skip to: 40641 -/* 2997 */ MCD_OPC_Decode, 176, 14, 16, // Opcode: ST4Fourv8h_POST -/* 3001 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3019 -/* 3005 */ MCD_OPC_CheckPredicate, 0, 0, 147, // Skip to: 40641 -/* 3009 */ MCD_OPC_CheckField, 21, 1, 0, 250, 146, // Skip to: 40641 -/* 3015 */ MCD_OPC_Decode, 172, 14, 16, // Opcode: ST4Fourv4s_POST -/* 3019 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 3037 -/* 3023 */ MCD_OPC_CheckPredicate, 0, 238, 146, // Skip to: 40641 -/* 3027 */ MCD_OPC_CheckField, 21, 1, 0, 232, 146, // Skip to: 40641 -/* 3033 */ MCD_OPC_Decode, 166, 14, 16, // Opcode: ST4Fourv2d_POST -/* 3037 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3055 -/* 3041 */ MCD_OPC_CheckPredicate, 0, 220, 146, // Skip to: 40641 -/* 3045 */ MCD_OPC_CheckField, 21, 1, 0, 214, 146, // Skip to: 40641 -/* 3051 */ MCD_OPC_Decode, 176, 13, 16, // Opcode: ST1Fourv16b_POST -/* 3055 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3073 -/* 3059 */ MCD_OPC_CheckPredicate, 0, 202, 146, // Skip to: 40641 -/* 3063 */ MCD_OPC_CheckField, 21, 1, 0, 196, 146, // Skip to: 40641 -/* 3069 */ MCD_OPC_Decode, 190, 13, 16, // Opcode: ST1Fourv8h_POST -/* 3073 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 3091 -/* 3077 */ MCD_OPC_CheckPredicate, 0, 184, 146, // Skip to: 40641 -/* 3081 */ MCD_OPC_CheckField, 21, 1, 0, 178, 146, // Skip to: 40641 -/* 3087 */ MCD_OPC_Decode, 186, 13, 16, // Opcode: ST1Fourv4s_POST -/* 3091 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 3109 -/* 3095 */ MCD_OPC_CheckPredicate, 0, 166, 146, // Skip to: 40641 -/* 3099 */ MCD_OPC_CheckField, 21, 1, 0, 160, 146, // Skip to: 40641 -/* 3105 */ MCD_OPC_Decode, 180, 13, 16, // Opcode: ST1Fourv2d_POST -/* 3109 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 3127 -/* 3113 */ MCD_OPC_CheckPredicate, 0, 148, 146, // Skip to: 40641 -/* 3117 */ MCD_OPC_CheckField, 21, 1, 0, 142, 146, // Skip to: 40641 -/* 3123 */ MCD_OPC_Decode, 142, 14, 17, // Opcode: ST3Threev16b_POST -/* 3127 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3145 -/* 3131 */ MCD_OPC_CheckPredicate, 0, 130, 146, // Skip to: 40641 -/* 3135 */ MCD_OPC_CheckField, 21, 1, 0, 124, 146, // Skip to: 40641 -/* 3141 */ MCD_OPC_Decode, 154, 14, 17, // Opcode: ST3Threev8h_POST -/* 3145 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 3163 -/* 3149 */ MCD_OPC_CheckPredicate, 0, 112, 146, // Skip to: 40641 -/* 3153 */ MCD_OPC_CheckField, 21, 1, 0, 106, 146, // Skip to: 40641 -/* 3159 */ MCD_OPC_Decode, 150, 14, 17, // Opcode: ST3Threev4s_POST -/* 3163 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 3181 -/* 3167 */ MCD_OPC_CheckPredicate, 0, 94, 146, // Skip to: 40641 -/* 3171 */ MCD_OPC_CheckField, 21, 1, 0, 88, 146, // Skip to: 40641 -/* 3177 */ MCD_OPC_Decode, 144, 14, 17, // Opcode: ST3Threev2d_POST -/* 3181 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3199 -/* 3185 */ MCD_OPC_CheckPredicate, 0, 76, 146, // Skip to: 40641 -/* 3189 */ MCD_OPC_CheckField, 21, 1, 0, 70, 146, // Skip to: 40641 -/* 3195 */ MCD_OPC_Decode, 208, 13, 17, // Opcode: ST1Threev16b_POST -/* 3199 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3217 -/* 3203 */ MCD_OPC_CheckPredicate, 0, 58, 146, // Skip to: 40641 -/* 3207 */ MCD_OPC_CheckField, 21, 1, 0, 52, 146, // Skip to: 40641 -/* 3213 */ MCD_OPC_Decode, 222, 13, 17, // Opcode: ST1Threev8h_POST -/* 3217 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 3235 -/* 3221 */ MCD_OPC_CheckPredicate, 0, 40, 146, // Skip to: 40641 -/* 3225 */ MCD_OPC_CheckField, 21, 1, 0, 34, 146, // Skip to: 40641 -/* 3231 */ MCD_OPC_Decode, 218, 13, 17, // Opcode: ST1Threev4s_POST -/* 3235 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3253 -/* 3239 */ MCD_OPC_CheckPredicate, 0, 22, 146, // Skip to: 40641 -/* 3243 */ MCD_OPC_CheckField, 21, 1, 0, 16, 146, // Skip to: 40641 -/* 3249 */ MCD_OPC_Decode, 212, 13, 17, // Opcode: ST1Threev2d_POST -/* 3253 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3271 -/* 3257 */ MCD_OPC_CheckPredicate, 0, 4, 146, // Skip to: 40641 -/* 3261 */ MCD_OPC_CheckField, 21, 1, 0, 254, 145, // Skip to: 40641 -/* 3267 */ MCD_OPC_Decode, 192, 13, 18, // Opcode: ST1Onev16b_POST -/* 3271 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3289 -/* 3275 */ MCD_OPC_CheckPredicate, 0, 242, 145, // Skip to: 40641 -/* 3279 */ MCD_OPC_CheckField, 21, 1, 0, 236, 145, // Skip to: 40641 -/* 3285 */ MCD_OPC_Decode, 206, 13, 18, // Opcode: ST1Onev8h_POST -/* 3289 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 3307 -/* 3293 */ MCD_OPC_CheckPredicate, 0, 224, 145, // Skip to: 40641 -/* 3297 */ MCD_OPC_CheckField, 21, 1, 0, 218, 145, // Skip to: 40641 -/* 3303 */ MCD_OPC_Decode, 202, 13, 18, // Opcode: ST1Onev4s_POST -/* 3307 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3325 -/* 3311 */ MCD_OPC_CheckPredicate, 0, 206, 145, // Skip to: 40641 -/* 3315 */ MCD_OPC_CheckField, 21, 1, 0, 200, 145, // Skip to: 40641 -/* 3321 */ MCD_OPC_Decode, 196, 13, 18, // Opcode: ST1Onev2d_POST -/* 3325 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3343 -/* 3329 */ MCD_OPC_CheckPredicate, 0, 188, 145, // Skip to: 40641 -/* 3333 */ MCD_OPC_CheckField, 21, 1, 0, 182, 145, // Skip to: 40641 -/* 3339 */ MCD_OPC_Decode, 248, 13, 19, // Opcode: ST2Twov16b_POST -/* 3343 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3361 -/* 3347 */ MCD_OPC_CheckPredicate, 0, 170, 145, // Skip to: 40641 -/* 3351 */ MCD_OPC_CheckField, 21, 1, 0, 164, 145, // Skip to: 40641 -/* 3357 */ MCD_OPC_Decode, 132, 14, 19, // Opcode: ST2Twov8h_POST -/* 3361 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3379 -/* 3365 */ MCD_OPC_CheckPredicate, 0, 152, 145, // Skip to: 40641 -/* 3369 */ MCD_OPC_CheckField, 21, 1, 0, 146, 145, // Skip to: 40641 -/* 3375 */ MCD_OPC_Decode, 128, 14, 19, // Opcode: ST2Twov4s_POST -/* 3379 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 3397 -/* 3383 */ MCD_OPC_CheckPredicate, 0, 134, 145, // Skip to: 40641 -/* 3387 */ MCD_OPC_CheckField, 21, 1, 0, 128, 145, // Skip to: 40641 -/* 3393 */ MCD_OPC_Decode, 250, 13, 19, // Opcode: ST2Twov2d_POST -/* 3397 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3415 -/* 3401 */ MCD_OPC_CheckPredicate, 0, 116, 145, // Skip to: 40641 -/* 3405 */ MCD_OPC_CheckField, 21, 1, 0, 110, 145, // Skip to: 40641 -/* 3411 */ MCD_OPC_Decode, 224, 13, 19, // Opcode: ST1Twov16b_POST -/* 3415 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3433 -/* 3419 */ MCD_OPC_CheckPredicate, 0, 98, 145, // Skip to: 40641 -/* 3423 */ MCD_OPC_CheckField, 21, 1, 0, 92, 145, // Skip to: 40641 -/* 3429 */ MCD_OPC_Decode, 238, 13, 19, // Opcode: ST1Twov8h_POST -/* 3433 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3451 -/* 3437 */ MCD_OPC_CheckPredicate, 0, 80, 145, // Skip to: 40641 -/* 3441 */ MCD_OPC_CheckField, 21, 1, 0, 74, 145, // Skip to: 40641 -/* 3447 */ MCD_OPC_Decode, 234, 13, 19, // Opcode: ST1Twov4s_POST -/* 3451 */ MCD_OPC_FilterValue, 43, 66, 145, // Skip to: 40641 -/* 3455 */ MCD_OPC_CheckPredicate, 0, 62, 145, // Skip to: 40641 -/* 3459 */ MCD_OPC_CheckField, 21, 1, 0, 56, 145, // Skip to: 40641 -/* 3465 */ MCD_OPC_Decode, 228, 13, 19, // Opcode: ST1Twov2d_POST -/* 3469 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 3477 -/* 3473 */ MCD_OPC_Decode, 201, 14, 3, // Opcode: STPDpost -/* 3477 */ MCD_OPC_FilterValue, 5, 40, 145, // Skip to: 40641 -/* 3481 */ MCD_OPC_Decode, 204, 14, 3, // Opcode: STPQpost -/* 3485 */ MCD_OPC_FilterValue, 3, 227, 3, // Skip to: 4484 -/* 3489 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 3492 */ MCD_OPC_FilterValue, 0, 197, 1, // Skip to: 3949 -/* 3496 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 3499 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3517 -/* 3503 */ MCD_OPC_CheckPredicate, 0, 14, 145, // Skip to: 40641 -/* 3507 */ MCD_OPC_CheckField, 21, 1, 0, 8, 145, // Skip to: 40641 -/* 3513 */ MCD_OPC_Decode, 138, 7, 12, // Opcode: LD4Fourv8b_POST -/* 3517 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 3535 -/* 3521 */ MCD_OPC_CheckPredicate, 0, 252, 144, // Skip to: 40641 -/* 3525 */ MCD_OPC_CheckField, 21, 1, 0, 246, 144, // Skip to: 40641 -/* 3531 */ MCD_OPC_Decode, 134, 7, 12, // Opcode: LD4Fourv4h_POST -/* 3535 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 3553 -/* 3539 */ MCD_OPC_CheckPredicate, 0, 234, 144, // Skip to: 40641 -/* 3543 */ MCD_OPC_CheckField, 21, 1, 0, 228, 144, // Skip to: 40641 -/* 3549 */ MCD_OPC_Decode, 132, 7, 12, // Opcode: LD4Fourv2s_POST -/* 3553 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 3571 -/* 3557 */ MCD_OPC_CheckPredicate, 0, 216, 144, // Skip to: 40641 -/* 3561 */ MCD_OPC_CheckField, 21, 1, 0, 210, 144, // Skip to: 40641 -/* 3567 */ MCD_OPC_Decode, 232, 5, 12, // Opcode: LD1Fourv8b_POST -/* 3571 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 3589 -/* 3575 */ MCD_OPC_CheckPredicate, 0, 198, 144, // Skip to: 40641 -/* 3579 */ MCD_OPC_CheckField, 21, 1, 0, 192, 144, // Skip to: 40641 -/* 3585 */ MCD_OPC_Decode, 228, 5, 12, // Opcode: LD1Fourv4h_POST -/* 3589 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 3607 -/* 3593 */ MCD_OPC_CheckPredicate, 0, 180, 144, // Skip to: 40641 -/* 3597 */ MCD_OPC_CheckField, 21, 1, 0, 174, 144, // Skip to: 40641 -/* 3603 */ MCD_OPC_Decode, 226, 5, 12, // Opcode: LD1Fourv2s_POST -/* 3607 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 3625 -/* 3611 */ MCD_OPC_CheckPredicate, 0, 162, 144, // Skip to: 40641 -/* 3615 */ MCD_OPC_CheckField, 21, 1, 0, 156, 144, // Skip to: 40641 -/* 3621 */ MCD_OPC_Decode, 222, 5, 12, // Opcode: LD1Fourv1d_POST -/* 3625 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 3643 -/* 3629 */ MCD_OPC_CheckPredicate, 0, 144, 144, // Skip to: 40641 -/* 3633 */ MCD_OPC_CheckField, 21, 1, 0, 138, 144, // Skip to: 40641 -/* 3639 */ MCD_OPC_Decode, 244, 6, 13, // Opcode: LD3Threev8b_POST -/* 3643 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 3661 -/* 3647 */ MCD_OPC_CheckPredicate, 0, 126, 144, // Skip to: 40641 -/* 3651 */ MCD_OPC_CheckField, 21, 1, 0, 120, 144, // Skip to: 40641 -/* 3657 */ MCD_OPC_Decode, 240, 6, 13, // Opcode: LD3Threev4h_POST -/* 3661 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 3679 -/* 3665 */ MCD_OPC_CheckPredicate, 0, 108, 144, // Skip to: 40641 -/* 3669 */ MCD_OPC_CheckField, 21, 1, 0, 102, 144, // Skip to: 40641 -/* 3675 */ MCD_OPC_Decode, 238, 6, 13, // Opcode: LD3Threev2s_POST -/* 3679 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 3697 -/* 3683 */ MCD_OPC_CheckPredicate, 0, 90, 144, // Skip to: 40641 -/* 3687 */ MCD_OPC_CheckField, 21, 1, 0, 84, 144, // Skip to: 40641 -/* 3693 */ MCD_OPC_Decode, 152, 6, 13, // Opcode: LD1Threev8b_POST -/* 3697 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 3715 -/* 3701 */ MCD_OPC_CheckPredicate, 0, 72, 144, // Skip to: 40641 -/* 3705 */ MCD_OPC_CheckField, 21, 1, 0, 66, 144, // Skip to: 40641 -/* 3711 */ MCD_OPC_Decode, 148, 6, 13, // Opcode: LD1Threev4h_POST -/* 3715 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 3733 -/* 3719 */ MCD_OPC_CheckPredicate, 0, 54, 144, // Skip to: 40641 -/* 3723 */ MCD_OPC_CheckField, 21, 1, 0, 48, 144, // Skip to: 40641 -/* 3729 */ MCD_OPC_Decode, 146, 6, 13, // Opcode: LD1Threev2s_POST -/* 3733 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 3751 -/* 3737 */ MCD_OPC_CheckPredicate, 0, 36, 144, // Skip to: 40641 -/* 3741 */ MCD_OPC_CheckField, 21, 1, 0, 30, 144, // Skip to: 40641 -/* 3747 */ MCD_OPC_Decode, 142, 6, 13, // Opcode: LD1Threev1d_POST -/* 3751 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 3769 -/* 3755 */ MCD_OPC_CheckPredicate, 0, 18, 144, // Skip to: 40641 -/* 3759 */ MCD_OPC_CheckField, 21, 1, 0, 12, 144, // Skip to: 40641 -/* 3765 */ MCD_OPC_Decode, 248, 5, 14, // Opcode: LD1Onev8b_POST -/* 3769 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 3787 -/* 3773 */ MCD_OPC_CheckPredicate, 0, 0, 144, // Skip to: 40641 -/* 3777 */ MCD_OPC_CheckField, 21, 1, 0, 250, 143, // Skip to: 40641 -/* 3783 */ MCD_OPC_Decode, 244, 5, 14, // Opcode: LD1Onev4h_POST -/* 3787 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 3805 -/* 3791 */ MCD_OPC_CheckPredicate, 0, 238, 143, // Skip to: 40641 -/* 3795 */ MCD_OPC_CheckField, 21, 1, 0, 232, 143, // Skip to: 40641 -/* 3801 */ MCD_OPC_Decode, 242, 5, 14, // Opcode: LD1Onev2s_POST -/* 3805 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 3823 -/* 3809 */ MCD_OPC_CheckPredicate, 0, 220, 143, // Skip to: 40641 -/* 3813 */ MCD_OPC_CheckField, 21, 1, 0, 214, 143, // Skip to: 40641 -/* 3819 */ MCD_OPC_Decode, 238, 5, 14, // Opcode: LD1Onev1d_POST -/* 3823 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 3841 -/* 3827 */ MCD_OPC_CheckPredicate, 0, 202, 143, // Skip to: 40641 -/* 3831 */ MCD_OPC_CheckField, 21, 1, 0, 196, 143, // Skip to: 40641 -/* 3837 */ MCD_OPC_Decode, 206, 6, 15, // Opcode: LD2Twov8b_POST -/* 3841 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 3859 -/* 3845 */ MCD_OPC_CheckPredicate, 0, 184, 143, // Skip to: 40641 -/* 3849 */ MCD_OPC_CheckField, 21, 1, 0, 178, 143, // Skip to: 40641 -/* 3855 */ MCD_OPC_Decode, 202, 6, 15, // Opcode: LD2Twov4h_POST -/* 3859 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 3877 -/* 3863 */ MCD_OPC_CheckPredicate, 0, 166, 143, // Skip to: 40641 -/* 3867 */ MCD_OPC_CheckField, 21, 1, 0, 160, 143, // Skip to: 40641 -/* 3873 */ MCD_OPC_Decode, 200, 6, 15, // Opcode: LD2Twov2s_POST -/* 3877 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 3895 -/* 3881 */ MCD_OPC_CheckPredicate, 0, 148, 143, // Skip to: 40641 -/* 3885 */ MCD_OPC_CheckField, 21, 1, 0, 142, 143, // Skip to: 40641 -/* 3891 */ MCD_OPC_Decode, 168, 6, 15, // Opcode: LD1Twov8b_POST -/* 3895 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 3913 -/* 3899 */ MCD_OPC_CheckPredicate, 0, 130, 143, // Skip to: 40641 -/* 3903 */ MCD_OPC_CheckField, 21, 1, 0, 124, 143, // Skip to: 40641 -/* 3909 */ MCD_OPC_Decode, 164, 6, 15, // Opcode: LD1Twov4h_POST -/* 3913 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 3931 -/* 3917 */ MCD_OPC_CheckPredicate, 0, 112, 143, // Skip to: 40641 -/* 3921 */ MCD_OPC_CheckField, 21, 1, 0, 106, 143, // Skip to: 40641 -/* 3927 */ MCD_OPC_Decode, 162, 6, 15, // Opcode: LD1Twov2s_POST -/* 3931 */ MCD_OPC_FilterValue, 43, 98, 143, // Skip to: 40641 -/* 3935 */ MCD_OPC_CheckPredicate, 0, 94, 143, // Skip to: 40641 -/* 3939 */ MCD_OPC_CheckField, 21, 1, 0, 88, 143, // Skip to: 40641 -/* 3945 */ MCD_OPC_Decode, 158, 6, 15, // Opcode: LD1Twov1d_POST -/* 3949 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 3957 -/* 3953 */ MCD_OPC_Decode, 190, 7, 3, // Opcode: LDPSpost -/* 3957 */ MCD_OPC_FilterValue, 2, 251, 1, // Skip to: 4468 -/* 3961 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 3964 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 3982 -/* 3968 */ MCD_OPC_CheckPredicate, 0, 61, 143, // Skip to: 40641 -/* 3972 */ MCD_OPC_CheckField, 21, 1, 0, 55, 143, // Skip to: 40641 -/* 3978 */ MCD_OPC_Decode, 128, 7, 16, // Opcode: LD4Fourv16b_POST -/* 3982 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4000 -/* 3986 */ MCD_OPC_CheckPredicate, 0, 43, 143, // Skip to: 40641 -/* 3990 */ MCD_OPC_CheckField, 21, 1, 0, 37, 143, // Skip to: 40641 -/* 3996 */ MCD_OPC_Decode, 140, 7, 16, // Opcode: LD4Fourv8h_POST -/* 4000 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 4018 -/* 4004 */ MCD_OPC_CheckPredicate, 0, 25, 143, // Skip to: 40641 -/* 4008 */ MCD_OPC_CheckField, 21, 1, 0, 19, 143, // Skip to: 40641 -/* 4014 */ MCD_OPC_Decode, 136, 7, 16, // Opcode: LD4Fourv4s_POST -/* 4018 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 4036 -/* 4022 */ MCD_OPC_CheckPredicate, 0, 7, 143, // Skip to: 40641 -/* 4026 */ MCD_OPC_CheckField, 21, 1, 0, 1, 143, // Skip to: 40641 -/* 4032 */ MCD_OPC_Decode, 130, 7, 16, // Opcode: LD4Fourv2d_POST -/* 4036 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 4054 -/* 4040 */ MCD_OPC_CheckPredicate, 0, 245, 142, // Skip to: 40641 -/* 4044 */ MCD_OPC_CheckField, 21, 1, 0, 239, 142, // Skip to: 40641 -/* 4050 */ MCD_OPC_Decode, 220, 5, 16, // Opcode: LD1Fourv16b_POST -/* 4054 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 4072 -/* 4058 */ MCD_OPC_CheckPredicate, 0, 227, 142, // Skip to: 40641 -/* 4062 */ MCD_OPC_CheckField, 21, 1, 0, 221, 142, // Skip to: 40641 -/* 4068 */ MCD_OPC_Decode, 234, 5, 16, // Opcode: LD1Fourv8h_POST -/* 4072 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 4090 -/* 4076 */ MCD_OPC_CheckPredicate, 0, 209, 142, // Skip to: 40641 -/* 4080 */ MCD_OPC_CheckField, 21, 1, 0, 203, 142, // Skip to: 40641 -/* 4086 */ MCD_OPC_Decode, 230, 5, 16, // Opcode: LD1Fourv4s_POST -/* 4090 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 4108 -/* 4094 */ MCD_OPC_CheckPredicate, 0, 191, 142, // Skip to: 40641 -/* 4098 */ MCD_OPC_CheckField, 21, 1, 0, 185, 142, // Skip to: 40641 -/* 4104 */ MCD_OPC_Decode, 224, 5, 16, // Opcode: LD1Fourv2d_POST -/* 4108 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 4126 -/* 4112 */ MCD_OPC_CheckPredicate, 0, 173, 142, // Skip to: 40641 -/* 4116 */ MCD_OPC_CheckField, 21, 1, 0, 167, 142, // Skip to: 40641 -/* 4122 */ MCD_OPC_Decode, 234, 6, 17, // Opcode: LD3Threev16b_POST -/* 4126 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 4144 -/* 4130 */ MCD_OPC_CheckPredicate, 0, 155, 142, // Skip to: 40641 -/* 4134 */ MCD_OPC_CheckField, 21, 1, 0, 149, 142, // Skip to: 40641 -/* 4140 */ MCD_OPC_Decode, 246, 6, 17, // Opcode: LD3Threev8h_POST -/* 4144 */ MCD_OPC_FilterValue, 18, 14, 0, // Skip to: 4162 -/* 4148 */ MCD_OPC_CheckPredicate, 0, 137, 142, // Skip to: 40641 -/* 4152 */ MCD_OPC_CheckField, 21, 1, 0, 131, 142, // Skip to: 40641 -/* 4158 */ MCD_OPC_Decode, 242, 6, 17, // Opcode: LD3Threev4s_POST -/* 4162 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 4180 -/* 4166 */ MCD_OPC_CheckPredicate, 0, 119, 142, // Skip to: 40641 -/* 4170 */ MCD_OPC_CheckField, 21, 1, 0, 113, 142, // Skip to: 40641 -/* 4176 */ MCD_OPC_Decode, 236, 6, 17, // Opcode: LD3Threev2d_POST -/* 4180 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 4198 -/* 4184 */ MCD_OPC_CheckPredicate, 0, 101, 142, // Skip to: 40641 -/* 4188 */ MCD_OPC_CheckField, 21, 1, 0, 95, 142, // Skip to: 40641 -/* 4194 */ MCD_OPC_Decode, 140, 6, 17, // Opcode: LD1Threev16b_POST -/* 4198 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 4216 -/* 4202 */ MCD_OPC_CheckPredicate, 0, 83, 142, // Skip to: 40641 -/* 4206 */ MCD_OPC_CheckField, 21, 1, 0, 77, 142, // Skip to: 40641 -/* 4212 */ MCD_OPC_Decode, 154, 6, 17, // Opcode: LD1Threev8h_POST -/* 4216 */ MCD_OPC_FilterValue, 26, 14, 0, // Skip to: 4234 -/* 4220 */ MCD_OPC_CheckPredicate, 0, 65, 142, // Skip to: 40641 -/* 4224 */ MCD_OPC_CheckField, 21, 1, 0, 59, 142, // Skip to: 40641 -/* 4230 */ MCD_OPC_Decode, 150, 6, 17, // Opcode: LD1Threev4s_POST -/* 4234 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 4252 -/* 4238 */ MCD_OPC_CheckPredicate, 0, 47, 142, // Skip to: 40641 -/* 4242 */ MCD_OPC_CheckField, 21, 1, 0, 41, 142, // Skip to: 40641 -/* 4248 */ MCD_OPC_Decode, 144, 6, 17, // Opcode: LD1Threev2d_POST -/* 4252 */ MCD_OPC_FilterValue, 28, 14, 0, // Skip to: 4270 -/* 4256 */ MCD_OPC_CheckPredicate, 0, 29, 142, // Skip to: 40641 -/* 4260 */ MCD_OPC_CheckField, 21, 1, 0, 23, 142, // Skip to: 40641 -/* 4266 */ MCD_OPC_Decode, 236, 5, 18, // Opcode: LD1Onev16b_POST -/* 4270 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 4288 -/* 4274 */ MCD_OPC_CheckPredicate, 0, 11, 142, // Skip to: 40641 -/* 4278 */ MCD_OPC_CheckField, 21, 1, 0, 5, 142, // Skip to: 40641 -/* 4284 */ MCD_OPC_Decode, 250, 5, 18, // Opcode: LD1Onev8h_POST -/* 4288 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 4306 -/* 4292 */ MCD_OPC_CheckPredicate, 0, 249, 141, // Skip to: 40641 -/* 4296 */ MCD_OPC_CheckField, 21, 1, 0, 243, 141, // Skip to: 40641 -/* 4302 */ MCD_OPC_Decode, 246, 5, 18, // Opcode: LD1Onev4s_POST -/* 4306 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 4324 -/* 4310 */ MCD_OPC_CheckPredicate, 0, 231, 141, // Skip to: 40641 -/* 4314 */ MCD_OPC_CheckField, 21, 1, 0, 225, 141, // Skip to: 40641 -/* 4320 */ MCD_OPC_Decode, 240, 5, 18, // Opcode: LD1Onev2d_POST -/* 4324 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 4342 -/* 4328 */ MCD_OPC_CheckPredicate, 0, 213, 141, // Skip to: 40641 -/* 4332 */ MCD_OPC_CheckField, 21, 1, 0, 207, 141, // Skip to: 40641 -/* 4338 */ MCD_OPC_Decode, 196, 6, 19, // Opcode: LD2Twov16b_POST -/* 4342 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 4360 -/* 4346 */ MCD_OPC_CheckPredicate, 0, 195, 141, // Skip to: 40641 -/* 4350 */ MCD_OPC_CheckField, 21, 1, 0, 189, 141, // Skip to: 40641 -/* 4356 */ MCD_OPC_Decode, 208, 6, 19, // Opcode: LD2Twov8h_POST -/* 4360 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 4378 -/* 4364 */ MCD_OPC_CheckPredicate, 0, 177, 141, // Skip to: 40641 -/* 4368 */ MCD_OPC_CheckField, 21, 1, 0, 171, 141, // Skip to: 40641 -/* 4374 */ MCD_OPC_Decode, 204, 6, 19, // Opcode: LD2Twov4s_POST -/* 4378 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 4396 -/* 4382 */ MCD_OPC_CheckPredicate, 0, 159, 141, // Skip to: 40641 -/* 4386 */ MCD_OPC_CheckField, 21, 1, 0, 153, 141, // Skip to: 40641 -/* 4392 */ MCD_OPC_Decode, 198, 6, 19, // Opcode: LD2Twov2d_POST -/* 4396 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 4414 -/* 4400 */ MCD_OPC_CheckPredicate, 0, 141, 141, // Skip to: 40641 -/* 4404 */ MCD_OPC_CheckField, 21, 1, 0, 135, 141, // Skip to: 40641 -/* 4410 */ MCD_OPC_Decode, 156, 6, 19, // Opcode: LD1Twov16b_POST -/* 4414 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 4432 -/* 4418 */ MCD_OPC_CheckPredicate, 0, 123, 141, // Skip to: 40641 -/* 4422 */ MCD_OPC_CheckField, 21, 1, 0, 117, 141, // Skip to: 40641 -/* 4428 */ MCD_OPC_Decode, 170, 6, 19, // Opcode: LD1Twov8h_POST -/* 4432 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 4450 -/* 4436 */ MCD_OPC_CheckPredicate, 0, 105, 141, // Skip to: 40641 -/* 4440 */ MCD_OPC_CheckField, 21, 1, 0, 99, 141, // Skip to: 40641 -/* 4446 */ MCD_OPC_Decode, 166, 6, 19, // Opcode: LD1Twov4s_POST -/* 4450 */ MCD_OPC_FilterValue, 43, 91, 141, // Skip to: 40641 -/* 4454 */ MCD_OPC_CheckPredicate, 0, 87, 141, // Skip to: 40641 -/* 4458 */ MCD_OPC_CheckField, 21, 1, 0, 81, 141, // Skip to: 40641 -/* 4464 */ MCD_OPC_Decode, 160, 6, 19, // Opcode: LD1Twov2d_POST -/* 4468 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 4476 -/* 4472 */ MCD_OPC_Decode, 181, 7, 3, // Opcode: LDPDpost -/* 4476 */ MCD_OPC_FilterValue, 5, 65, 141, // Skip to: 40641 -/* 4480 */ MCD_OPC_Decode, 184, 7, 3, // Opcode: LDPQpost -/* 4484 */ MCD_OPC_FilterValue, 4, 155, 1, // Skip to: 4899 -/* 4488 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 4491 */ MCD_OPC_FilterValue, 0, 117, 1, // Skip to: 4868 -/* 4495 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... -/* 4498 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4516 -/* 4502 */ MCD_OPC_CheckPredicate, 0, 39, 141, // Skip to: 40641 -/* 4506 */ MCD_OPC_CheckField, 31, 1, 0, 33, 141, // Skip to: 40641 -/* 4512 */ MCD_OPC_Decode, 245, 13, 20, // Opcode: ST1i8 -/* 4516 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4534 -/* 4520 */ MCD_OPC_CheckPredicate, 0, 21, 141, // Skip to: 40641 -/* 4524 */ MCD_OPC_CheckField, 31, 1, 0, 15, 141, // Skip to: 40641 -/* 4530 */ MCD_OPC_Decode, 161, 14, 21, // Opcode: ST3i8 -/* 4534 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 4558 -/* 4538 */ MCD_OPC_CheckPredicate, 0, 3, 141, // Skip to: 40641 -/* 4542 */ MCD_OPC_CheckField, 31, 1, 0, 253, 140, // Skip to: 40641 -/* 4548 */ MCD_OPC_CheckField, 10, 1, 0, 247, 140, // Skip to: 40641 -/* 4554 */ MCD_OPC_Decode, 239, 13, 22, // Opcode: ST1i16 -/* 4558 */ MCD_OPC_FilterValue, 3, 20, 0, // Skip to: 4582 -/* 4562 */ MCD_OPC_CheckPredicate, 0, 235, 140, // Skip to: 40641 -/* 4566 */ MCD_OPC_CheckField, 31, 1, 0, 229, 140, // Skip to: 40641 -/* 4572 */ MCD_OPC_CheckField, 10, 1, 0, 223, 140, // Skip to: 40641 -/* 4578 */ MCD_OPC_Decode, 155, 14, 23, // Opcode: ST3i16 -/* 4582 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 4631 -/* 4586 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 4589 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4607 -/* 4593 */ MCD_OPC_CheckPredicate, 0, 204, 140, // Skip to: 40641 -/* 4597 */ MCD_OPC_CheckField, 31, 1, 0, 198, 140, // Skip to: 40641 -/* 4603 */ MCD_OPC_Decode, 241, 13, 24, // Opcode: ST1i32 -/* 4607 */ MCD_OPC_FilterValue, 1, 190, 140, // Skip to: 40641 -/* 4611 */ MCD_OPC_CheckPredicate, 0, 186, 140, // Skip to: 40641 -/* 4615 */ MCD_OPC_CheckField, 31, 1, 0, 180, 140, // Skip to: 40641 -/* 4621 */ MCD_OPC_CheckField, 12, 1, 0, 174, 140, // Skip to: 40641 -/* 4627 */ MCD_OPC_Decode, 243, 13, 25, // Opcode: ST1i64 -/* 4631 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 4680 -/* 4635 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 4638 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4656 -/* 4642 */ MCD_OPC_CheckPredicate, 0, 155, 140, // Skip to: 40641 -/* 4646 */ MCD_OPC_CheckField, 31, 1, 0, 149, 140, // Skip to: 40641 -/* 4652 */ MCD_OPC_Decode, 157, 14, 26, // Opcode: ST3i32 -/* 4656 */ MCD_OPC_FilterValue, 1, 141, 140, // Skip to: 40641 -/* 4660 */ MCD_OPC_CheckPredicate, 0, 137, 140, // Skip to: 40641 -/* 4664 */ MCD_OPC_CheckField, 31, 1, 0, 131, 140, // Skip to: 40641 -/* 4670 */ MCD_OPC_CheckField, 12, 1, 0, 125, 140, // Skip to: 40641 -/* 4676 */ MCD_OPC_Decode, 159, 14, 27, // Opcode: ST3i64 -/* 4680 */ MCD_OPC_FilterValue, 128, 2, 14, 0, // Skip to: 4699 -/* 4685 */ MCD_OPC_CheckPredicate, 0, 112, 140, // Skip to: 40641 -/* 4689 */ MCD_OPC_CheckField, 31, 1, 0, 106, 140, // Skip to: 40641 -/* 4695 */ MCD_OPC_Decode, 139, 14, 28, // Opcode: ST2i8 -/* 4699 */ MCD_OPC_FilterValue, 129, 2, 14, 0, // Skip to: 4718 -/* 4704 */ MCD_OPC_CheckPredicate, 0, 93, 140, // Skip to: 40641 -/* 4708 */ MCD_OPC_CheckField, 31, 1, 0, 87, 140, // Skip to: 40641 -/* 4714 */ MCD_OPC_Decode, 183, 14, 29, // Opcode: ST4i8 -/* 4718 */ MCD_OPC_FilterValue, 130, 2, 20, 0, // Skip to: 4743 -/* 4723 */ MCD_OPC_CheckPredicate, 0, 74, 140, // Skip to: 40641 -/* 4727 */ MCD_OPC_CheckField, 31, 1, 0, 68, 140, // Skip to: 40641 -/* 4733 */ MCD_OPC_CheckField, 10, 1, 0, 62, 140, // Skip to: 40641 -/* 4739 */ MCD_OPC_Decode, 133, 14, 30, // Opcode: ST2i16 -/* 4743 */ MCD_OPC_FilterValue, 131, 2, 20, 0, // Skip to: 4768 -/* 4748 */ MCD_OPC_CheckPredicate, 0, 49, 140, // Skip to: 40641 -/* 4752 */ MCD_OPC_CheckField, 31, 1, 0, 43, 140, // Skip to: 40641 -/* 4758 */ MCD_OPC_CheckField, 10, 1, 0, 37, 140, // Skip to: 40641 -/* 4764 */ MCD_OPC_Decode, 177, 14, 31, // Opcode: ST4i16 -/* 4768 */ MCD_OPC_FilterValue, 132, 2, 45, 0, // Skip to: 4818 -/* 4773 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 4776 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4794 -/* 4780 */ MCD_OPC_CheckPredicate, 0, 17, 140, // Skip to: 40641 -/* 4784 */ MCD_OPC_CheckField, 31, 1, 0, 11, 140, // Skip to: 40641 -/* 4790 */ MCD_OPC_Decode, 135, 14, 32, // Opcode: ST2i32 -/* 4794 */ MCD_OPC_FilterValue, 1, 3, 140, // Skip to: 40641 -/* 4798 */ MCD_OPC_CheckPredicate, 0, 255, 139, // Skip to: 40641 -/* 4802 */ MCD_OPC_CheckField, 31, 1, 0, 249, 139, // Skip to: 40641 -/* 4808 */ MCD_OPC_CheckField, 12, 1, 0, 243, 139, // Skip to: 40641 -/* 4814 */ MCD_OPC_Decode, 137, 14, 33, // Opcode: ST2i64 -/* 4818 */ MCD_OPC_FilterValue, 133, 2, 234, 139, // Skip to: 40641 -/* 4823 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 4826 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4844 -/* 4830 */ MCD_OPC_CheckPredicate, 0, 223, 139, // Skip to: 40641 -/* 4834 */ MCD_OPC_CheckField, 31, 1, 0, 217, 139, // Skip to: 40641 -/* 4840 */ MCD_OPC_Decode, 179, 14, 34, // Opcode: ST4i32 -/* 4844 */ MCD_OPC_FilterValue, 1, 209, 139, // Skip to: 40641 -/* 4848 */ MCD_OPC_CheckPredicate, 0, 205, 139, // Skip to: 40641 -/* 4852 */ MCD_OPC_CheckField, 31, 1, 0, 199, 139, // Skip to: 40641 -/* 4858 */ MCD_OPC_CheckField, 12, 1, 0, 193, 139, // Skip to: 40641 -/* 4864 */ MCD_OPC_Decode, 181, 14, 35, // Opcode: ST4i64 -/* 4868 */ MCD_OPC_FilterValue, 1, 185, 139, // Skip to: 40641 -/* 4872 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 4875 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 4883 -/* 4879 */ MCD_OPC_Decode, 206, 14, 3, // Opcode: STPSi -/* 4883 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 4891 -/* 4887 */ MCD_OPC_Decode, 200, 14, 3, // Opcode: STPDi -/* 4891 */ MCD_OPC_FilterValue, 2, 162, 139, // Skip to: 40641 -/* 4895 */ MCD_OPC_Decode, 203, 14, 3, // Opcode: STPQi -/* 4899 */ MCD_OPC_FilterValue, 5, 169, 3, // Skip to: 5840 -/* 4903 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 4906 */ MCD_OPC_FilterValue, 0, 131, 3, // Skip to: 5809 -/* 4910 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... -/* 4913 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 4931 -/* 4917 */ MCD_OPC_CheckPredicate, 0, 136, 139, // Skip to: 40641 -/* 4921 */ MCD_OPC_CheckField, 31, 1, 0, 130, 139, // Skip to: 40641 -/* 4927 */ MCD_OPC_Decode, 177, 6, 36, // Opcode: LD1i8 -/* 4931 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 4949 -/* 4935 */ MCD_OPC_CheckPredicate, 0, 118, 139, // Skip to: 40641 -/* 4939 */ MCD_OPC_CheckField, 31, 1, 0, 112, 139, // Skip to: 40641 -/* 4945 */ MCD_OPC_Decode, 253, 6, 37, // Opcode: LD3i8 -/* 4949 */ MCD_OPC_FilterValue, 2, 20, 0, // Skip to: 4973 -/* 4953 */ MCD_OPC_CheckPredicate, 0, 100, 139, // Skip to: 40641 -/* 4957 */ MCD_OPC_CheckField, 31, 1, 0, 94, 139, // Skip to: 40641 -/* 4963 */ MCD_OPC_CheckField, 10, 1, 0, 88, 139, // Skip to: 40641 -/* 4969 */ MCD_OPC_Decode, 171, 6, 38, // Opcode: LD1i16 -/* 4973 */ MCD_OPC_FilterValue, 3, 20, 0, // Skip to: 4997 -/* 4977 */ MCD_OPC_CheckPredicate, 0, 76, 139, // Skip to: 40641 -/* 4981 */ MCD_OPC_CheckField, 31, 1, 0, 70, 139, // Skip to: 40641 -/* 4987 */ MCD_OPC_CheckField, 10, 1, 0, 64, 139, // Skip to: 40641 -/* 4993 */ MCD_OPC_Decode, 247, 6, 39, // Opcode: LD3i16 -/* 4997 */ MCD_OPC_FilterValue, 4, 45, 0, // Skip to: 5046 -/* 5001 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5004 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5022 -/* 5008 */ MCD_OPC_CheckPredicate, 0, 45, 139, // Skip to: 40641 -/* 5012 */ MCD_OPC_CheckField, 31, 1, 0, 39, 139, // Skip to: 40641 -/* 5018 */ MCD_OPC_Decode, 173, 6, 40, // Opcode: LD1i32 -/* 5022 */ MCD_OPC_FilterValue, 1, 31, 139, // Skip to: 40641 -/* 5026 */ MCD_OPC_CheckPredicate, 0, 27, 139, // Skip to: 40641 -/* 5030 */ MCD_OPC_CheckField, 31, 1, 0, 21, 139, // Skip to: 40641 -/* 5036 */ MCD_OPC_CheckField, 12, 1, 0, 15, 139, // Skip to: 40641 -/* 5042 */ MCD_OPC_Decode, 175, 6, 41, // Opcode: LD1i64 -/* 5046 */ MCD_OPC_FilterValue, 5, 45, 0, // Skip to: 5095 -/* 5050 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5053 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5071 -/* 5057 */ MCD_OPC_CheckPredicate, 0, 252, 138, // Skip to: 40641 -/* 5061 */ MCD_OPC_CheckField, 31, 1, 0, 246, 138, // Skip to: 40641 -/* 5067 */ MCD_OPC_Decode, 249, 6, 42, // Opcode: LD3i32 -/* 5071 */ MCD_OPC_FilterValue, 1, 238, 138, // Skip to: 40641 -/* 5075 */ MCD_OPC_CheckPredicate, 0, 234, 138, // Skip to: 40641 -/* 5079 */ MCD_OPC_CheckField, 31, 1, 0, 228, 138, // Skip to: 40641 -/* 5085 */ MCD_OPC_CheckField, 12, 1, 0, 222, 138, // Skip to: 40641 -/* 5091 */ MCD_OPC_Decode, 251, 6, 43, // Opcode: LD3i64 -/* 5095 */ MCD_OPC_FilterValue, 6, 127, 0, // Skip to: 5226 -/* 5099 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 5102 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5133 -/* 5106 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5109 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5121 -/* 5113 */ MCD_OPC_CheckPredicate, 0, 196, 138, // Skip to: 40641 -/* 5117 */ MCD_OPC_Decode, 135, 6, 6, // Opcode: LD1Rv8b -/* 5121 */ MCD_OPC_FilterValue, 1, 188, 138, // Skip to: 40641 -/* 5125 */ MCD_OPC_CheckPredicate, 0, 184, 138, // Skip to: 40641 -/* 5129 */ MCD_OPC_Decode, 251, 5, 10, // Opcode: LD1Rv16b -/* 5133 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5164 -/* 5137 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5140 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5152 -/* 5144 */ MCD_OPC_CheckPredicate, 0, 165, 138, // Skip to: 40641 -/* 5148 */ MCD_OPC_Decode, 131, 6, 6, // Opcode: LD1Rv4h -/* 5152 */ MCD_OPC_FilterValue, 1, 157, 138, // Skip to: 40641 -/* 5156 */ MCD_OPC_CheckPredicate, 0, 153, 138, // Skip to: 40641 -/* 5160 */ MCD_OPC_Decode, 137, 6, 10, // Opcode: LD1Rv8h -/* 5164 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5195 -/* 5168 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5183 -/* 5175 */ MCD_OPC_CheckPredicate, 0, 134, 138, // Skip to: 40641 -/* 5179 */ MCD_OPC_Decode, 129, 6, 6, // Opcode: LD1Rv2s -/* 5183 */ MCD_OPC_FilterValue, 1, 126, 138, // Skip to: 40641 -/* 5187 */ MCD_OPC_CheckPredicate, 0, 122, 138, // Skip to: 40641 -/* 5191 */ MCD_OPC_Decode, 133, 6, 10, // Opcode: LD1Rv4s -/* 5195 */ MCD_OPC_FilterValue, 3, 114, 138, // Skip to: 40641 -/* 5199 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5202 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5214 -/* 5206 */ MCD_OPC_CheckPredicate, 0, 103, 138, // Skip to: 40641 -/* 5210 */ MCD_OPC_Decode, 253, 5, 6, // Opcode: LD1Rv1d -/* 5214 */ MCD_OPC_FilterValue, 1, 95, 138, // Skip to: 40641 -/* 5218 */ MCD_OPC_CheckPredicate, 0, 91, 138, // Skip to: 40641 -/* 5222 */ MCD_OPC_Decode, 255, 5, 10, // Opcode: LD1Rv2d -/* 5226 */ MCD_OPC_FilterValue, 7, 127, 0, // Skip to: 5357 -/* 5230 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 5233 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5264 -/* 5237 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5240 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5252 -/* 5244 */ MCD_OPC_CheckPredicate, 0, 65, 138, // Skip to: 40641 -/* 5248 */ MCD_OPC_Decode, 229, 6, 5, // Opcode: LD3Rv8b -/* 5252 */ MCD_OPC_FilterValue, 1, 57, 138, // Skip to: 40641 -/* 5256 */ MCD_OPC_CheckPredicate, 0, 53, 138, // Skip to: 40641 -/* 5260 */ MCD_OPC_Decode, 217, 6, 9, // Opcode: LD3Rv16b -/* 5264 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5295 -/* 5268 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5271 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5283 -/* 5275 */ MCD_OPC_CheckPredicate, 0, 34, 138, // Skip to: 40641 -/* 5279 */ MCD_OPC_Decode, 225, 6, 5, // Opcode: LD3Rv4h -/* 5283 */ MCD_OPC_FilterValue, 1, 26, 138, // Skip to: 40641 -/* 5287 */ MCD_OPC_CheckPredicate, 0, 22, 138, // Skip to: 40641 -/* 5291 */ MCD_OPC_Decode, 231, 6, 9, // Opcode: LD3Rv8h -/* 5295 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5326 -/* 5299 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5302 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5314 -/* 5306 */ MCD_OPC_CheckPredicate, 0, 3, 138, // Skip to: 40641 -/* 5310 */ MCD_OPC_Decode, 223, 6, 5, // Opcode: LD3Rv2s -/* 5314 */ MCD_OPC_FilterValue, 1, 251, 137, // Skip to: 40641 -/* 5318 */ MCD_OPC_CheckPredicate, 0, 247, 137, // Skip to: 40641 -/* 5322 */ MCD_OPC_Decode, 227, 6, 9, // Opcode: LD3Rv4s -/* 5326 */ MCD_OPC_FilterValue, 3, 239, 137, // Skip to: 40641 -/* 5330 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5345 -/* 5337 */ MCD_OPC_CheckPredicate, 0, 228, 137, // Skip to: 40641 -/* 5341 */ MCD_OPC_Decode, 219, 6, 5, // Opcode: LD3Rv1d -/* 5345 */ MCD_OPC_FilterValue, 1, 220, 137, // Skip to: 40641 -/* 5349 */ MCD_OPC_CheckPredicate, 0, 216, 137, // Skip to: 40641 -/* 5353 */ MCD_OPC_Decode, 221, 6, 9, // Opcode: LD3Rv2d -/* 5357 */ MCD_OPC_FilterValue, 128, 2, 14, 0, // Skip to: 5376 -/* 5362 */ MCD_OPC_CheckPredicate, 0, 203, 137, // Skip to: 40641 -/* 5366 */ MCD_OPC_CheckField, 31, 1, 0, 197, 137, // Skip to: 40641 -/* 5372 */ MCD_OPC_Decode, 215, 6, 44, // Opcode: LD2i8 -/* 5376 */ MCD_OPC_FilterValue, 129, 2, 14, 0, // Skip to: 5395 -/* 5381 */ MCD_OPC_CheckPredicate, 0, 184, 137, // Skip to: 40641 -/* 5385 */ MCD_OPC_CheckField, 31, 1, 0, 178, 137, // Skip to: 40641 -/* 5391 */ MCD_OPC_Decode, 163, 7, 45, // Opcode: LD4i8 -/* 5395 */ MCD_OPC_FilterValue, 130, 2, 20, 0, // Skip to: 5420 -/* 5400 */ MCD_OPC_CheckPredicate, 0, 165, 137, // Skip to: 40641 -/* 5404 */ MCD_OPC_CheckField, 31, 1, 0, 159, 137, // Skip to: 40641 -/* 5410 */ MCD_OPC_CheckField, 10, 1, 0, 153, 137, // Skip to: 40641 -/* 5416 */ MCD_OPC_Decode, 209, 6, 46, // Opcode: LD2i16 -/* 5420 */ MCD_OPC_FilterValue, 131, 2, 20, 0, // Skip to: 5445 -/* 5425 */ MCD_OPC_CheckPredicate, 0, 140, 137, // Skip to: 40641 -/* 5429 */ MCD_OPC_CheckField, 31, 1, 0, 134, 137, // Skip to: 40641 -/* 5435 */ MCD_OPC_CheckField, 10, 1, 0, 128, 137, // Skip to: 40641 -/* 5441 */ MCD_OPC_Decode, 157, 7, 47, // Opcode: LD4i16 -/* 5445 */ MCD_OPC_FilterValue, 132, 2, 45, 0, // Skip to: 5495 -/* 5450 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5453 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5471 -/* 5457 */ MCD_OPC_CheckPredicate, 0, 108, 137, // Skip to: 40641 -/* 5461 */ MCD_OPC_CheckField, 31, 1, 0, 102, 137, // Skip to: 40641 -/* 5467 */ MCD_OPC_Decode, 211, 6, 48, // Opcode: LD2i32 -/* 5471 */ MCD_OPC_FilterValue, 1, 94, 137, // Skip to: 40641 -/* 5475 */ MCD_OPC_CheckPredicate, 0, 90, 137, // Skip to: 40641 -/* 5479 */ MCD_OPC_CheckField, 31, 1, 0, 84, 137, // Skip to: 40641 -/* 5485 */ MCD_OPC_CheckField, 12, 1, 0, 78, 137, // Skip to: 40641 -/* 5491 */ MCD_OPC_Decode, 213, 6, 49, // Opcode: LD2i64 -/* 5495 */ MCD_OPC_FilterValue, 133, 2, 45, 0, // Skip to: 5545 -/* 5500 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 5503 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5521 -/* 5507 */ MCD_OPC_CheckPredicate, 0, 58, 137, // Skip to: 40641 -/* 5511 */ MCD_OPC_CheckField, 31, 1, 0, 52, 137, // Skip to: 40641 -/* 5517 */ MCD_OPC_Decode, 159, 7, 50, // Opcode: LD4i32 -/* 5521 */ MCD_OPC_FilterValue, 1, 44, 137, // Skip to: 40641 -/* 5525 */ MCD_OPC_CheckPredicate, 0, 40, 137, // Skip to: 40641 -/* 5529 */ MCD_OPC_CheckField, 31, 1, 0, 34, 137, // Skip to: 40641 -/* 5535 */ MCD_OPC_CheckField, 12, 1, 0, 28, 137, // Skip to: 40641 -/* 5541 */ MCD_OPC_Decode, 161, 7, 51, // Opcode: LD4i64 -/* 5545 */ MCD_OPC_FilterValue, 134, 2, 127, 0, // Skip to: 5677 -/* 5550 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 5553 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5584 -/* 5557 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5560 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5572 -/* 5564 */ MCD_OPC_CheckPredicate, 0, 1, 137, // Skip to: 40641 -/* 5568 */ MCD_OPC_Decode, 191, 6, 7, // Opcode: LD2Rv8b -/* 5572 */ MCD_OPC_FilterValue, 1, 249, 136, // Skip to: 40641 -/* 5576 */ MCD_OPC_CheckPredicate, 0, 245, 136, // Skip to: 40641 -/* 5580 */ MCD_OPC_Decode, 179, 6, 11, // Opcode: LD2Rv16b -/* 5584 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5615 -/* 5588 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5591 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5603 -/* 5595 */ MCD_OPC_CheckPredicate, 0, 226, 136, // Skip to: 40641 -/* 5599 */ MCD_OPC_Decode, 187, 6, 7, // Opcode: LD2Rv4h -/* 5603 */ MCD_OPC_FilterValue, 1, 218, 136, // Skip to: 40641 -/* 5607 */ MCD_OPC_CheckPredicate, 0, 214, 136, // Skip to: 40641 -/* 5611 */ MCD_OPC_Decode, 193, 6, 11, // Opcode: LD2Rv8h -/* 5615 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5646 -/* 5619 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5622 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5634 -/* 5626 */ MCD_OPC_CheckPredicate, 0, 195, 136, // Skip to: 40641 -/* 5630 */ MCD_OPC_Decode, 185, 6, 7, // Opcode: LD2Rv2s -/* 5634 */ MCD_OPC_FilterValue, 1, 187, 136, // Skip to: 40641 -/* 5638 */ MCD_OPC_CheckPredicate, 0, 183, 136, // Skip to: 40641 -/* 5642 */ MCD_OPC_Decode, 189, 6, 11, // Opcode: LD2Rv4s -/* 5646 */ MCD_OPC_FilterValue, 3, 175, 136, // Skip to: 40641 -/* 5650 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5653 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5665 -/* 5657 */ MCD_OPC_CheckPredicate, 0, 164, 136, // Skip to: 40641 -/* 5661 */ MCD_OPC_Decode, 181, 6, 7, // Opcode: LD2Rv1d -/* 5665 */ MCD_OPC_FilterValue, 1, 156, 136, // Skip to: 40641 -/* 5669 */ MCD_OPC_CheckPredicate, 0, 152, 136, // Skip to: 40641 -/* 5673 */ MCD_OPC_Decode, 183, 6, 11, // Opcode: LD2Rv2d -/* 5677 */ MCD_OPC_FilterValue, 135, 2, 143, 136, // Skip to: 40641 -/* 5682 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 5685 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 5716 -/* 5689 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5692 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5704 -/* 5696 */ MCD_OPC_CheckPredicate, 0, 125, 136, // Skip to: 40641 -/* 5700 */ MCD_OPC_Decode, 153, 7, 4, // Opcode: LD4Rv8b -/* 5704 */ MCD_OPC_FilterValue, 1, 117, 136, // Skip to: 40641 -/* 5708 */ MCD_OPC_CheckPredicate, 0, 113, 136, // Skip to: 40641 -/* 5712 */ MCD_OPC_Decode, 141, 7, 8, // Opcode: LD4Rv16b -/* 5716 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 5747 -/* 5720 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5723 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5735 -/* 5727 */ MCD_OPC_CheckPredicate, 0, 94, 136, // Skip to: 40641 -/* 5731 */ MCD_OPC_Decode, 149, 7, 4, // Opcode: LD4Rv4h -/* 5735 */ MCD_OPC_FilterValue, 1, 86, 136, // Skip to: 40641 -/* 5739 */ MCD_OPC_CheckPredicate, 0, 82, 136, // Skip to: 40641 -/* 5743 */ MCD_OPC_Decode, 155, 7, 8, // Opcode: LD4Rv8h -/* 5747 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 5778 -/* 5751 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5754 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5766 -/* 5758 */ MCD_OPC_CheckPredicate, 0, 63, 136, // Skip to: 40641 -/* 5762 */ MCD_OPC_Decode, 147, 7, 4, // Opcode: LD4Rv2s -/* 5766 */ MCD_OPC_FilterValue, 1, 55, 136, // Skip to: 40641 -/* 5770 */ MCD_OPC_CheckPredicate, 0, 51, 136, // Skip to: 40641 -/* 5774 */ MCD_OPC_Decode, 151, 7, 8, // Opcode: LD4Rv4s -/* 5778 */ MCD_OPC_FilterValue, 3, 43, 136, // Skip to: 40641 -/* 5782 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5785 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 5797 -/* 5789 */ MCD_OPC_CheckPredicate, 0, 32, 136, // Skip to: 40641 -/* 5793 */ MCD_OPC_Decode, 143, 7, 4, // Opcode: LD4Rv1d -/* 5797 */ MCD_OPC_FilterValue, 1, 24, 136, // Skip to: 40641 -/* 5801 */ MCD_OPC_CheckPredicate, 0, 20, 136, // Skip to: 40641 -/* 5805 */ MCD_OPC_Decode, 145, 7, 8, // Opcode: LD4Rv2d -/* 5809 */ MCD_OPC_FilterValue, 1, 12, 136, // Skip to: 40641 -/* 5813 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 5816 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 5824 -/* 5820 */ MCD_OPC_Decode, 189, 7, 3, // Opcode: LDPSi -/* 5824 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 5832 -/* 5828 */ MCD_OPC_Decode, 180, 7, 3, // Opcode: LDPDi -/* 5832 */ MCD_OPC_FilterValue, 2, 245, 135, // Skip to: 40641 -/* 5836 */ MCD_OPC_Decode, 183, 7, 3, // Opcode: LDPQi -/* 5840 */ MCD_OPC_FilterValue, 6, 191, 1, // Skip to: 6291 -/* 5844 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 5847 */ MCD_OPC_FilterValue, 0, 153, 1, // Skip to: 6260 -/* 5851 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 5854 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 5897 -/* 5858 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5861 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5879 -/* 5865 */ MCD_OPC_CheckPredicate, 0, 212, 135, // Skip to: 40641 -/* 5869 */ MCD_OPC_CheckField, 31, 1, 0, 206, 135, // Skip to: 40641 -/* 5875 */ MCD_OPC_Decode, 246, 13, 52, // Opcode: ST1i8_POST -/* 5879 */ MCD_OPC_FilterValue, 1, 198, 135, // Skip to: 40641 -/* 5883 */ MCD_OPC_CheckPredicate, 0, 194, 135, // Skip to: 40641 -/* 5887 */ MCD_OPC_CheckField, 31, 1, 0, 188, 135, // Skip to: 40641 -/* 5893 */ MCD_OPC_Decode, 140, 14, 53, // Opcode: ST2i8_POST -/* 5897 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 5940 -/* 5901 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5904 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 5922 -/* 5908 */ MCD_OPC_CheckPredicate, 0, 169, 135, // Skip to: 40641 -/* 5912 */ MCD_OPC_CheckField, 31, 1, 0, 163, 135, // Skip to: 40641 -/* 5918 */ MCD_OPC_Decode, 162, 14, 54, // Opcode: ST3i8_POST -/* 5922 */ MCD_OPC_FilterValue, 1, 155, 135, // Skip to: 40641 -/* 5926 */ MCD_OPC_CheckPredicate, 0, 151, 135, // Skip to: 40641 -/* 5930 */ MCD_OPC_CheckField, 31, 1, 0, 145, 135, // Skip to: 40641 -/* 5936 */ MCD_OPC_Decode, 184, 14, 55, // Opcode: ST4i8_POST -/* 5940 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 5995 -/* 5944 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 5947 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 5971 -/* 5951 */ MCD_OPC_CheckPredicate, 0, 126, 135, // Skip to: 40641 -/* 5955 */ MCD_OPC_CheckField, 31, 1, 0, 120, 135, // Skip to: 40641 -/* 5961 */ MCD_OPC_CheckField, 10, 1, 0, 114, 135, // Skip to: 40641 -/* 5967 */ MCD_OPC_Decode, 240, 13, 56, // Opcode: ST1i16_POST -/* 5971 */ MCD_OPC_FilterValue, 1, 106, 135, // Skip to: 40641 -/* 5975 */ MCD_OPC_CheckPredicate, 0, 102, 135, // Skip to: 40641 -/* 5979 */ MCD_OPC_CheckField, 31, 1, 0, 96, 135, // Skip to: 40641 -/* 5985 */ MCD_OPC_CheckField, 10, 1, 0, 90, 135, // Skip to: 40641 -/* 5991 */ MCD_OPC_Decode, 134, 14, 57, // Opcode: ST2i16_POST -/* 5995 */ MCD_OPC_FilterValue, 3, 51, 0, // Skip to: 6050 -/* 5999 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6002 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6026 -/* 6006 */ MCD_OPC_CheckPredicate, 0, 71, 135, // Skip to: 40641 -/* 6010 */ MCD_OPC_CheckField, 31, 1, 0, 65, 135, // Skip to: 40641 -/* 6016 */ MCD_OPC_CheckField, 10, 1, 0, 59, 135, // Skip to: 40641 -/* 6022 */ MCD_OPC_Decode, 156, 14, 58, // Opcode: ST3i16_POST -/* 6026 */ MCD_OPC_FilterValue, 1, 51, 135, // Skip to: 40641 -/* 6030 */ MCD_OPC_CheckPredicate, 0, 47, 135, // Skip to: 40641 -/* 6034 */ MCD_OPC_CheckField, 31, 1, 0, 41, 135, // Skip to: 40641 -/* 6040 */ MCD_OPC_CheckField, 10, 1, 0, 35, 135, // Skip to: 40641 -/* 6046 */ MCD_OPC_Decode, 178, 14, 59, // Opcode: ST4i16_POST -/* 6050 */ MCD_OPC_FilterValue, 4, 101, 0, // Skip to: 6155 -/* 6054 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 6057 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6100 -/* 6061 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6064 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6082 -/* 6068 */ MCD_OPC_CheckPredicate, 0, 9, 135, // Skip to: 40641 -/* 6072 */ MCD_OPC_CheckField, 31, 1, 0, 3, 135, // Skip to: 40641 -/* 6078 */ MCD_OPC_Decode, 242, 13, 60, // Opcode: ST1i32_POST -/* 6082 */ MCD_OPC_FilterValue, 1, 251, 134, // Skip to: 40641 -/* 6086 */ MCD_OPC_CheckPredicate, 0, 247, 134, // Skip to: 40641 -/* 6090 */ MCD_OPC_CheckField, 31, 1, 0, 241, 134, // Skip to: 40641 -/* 6096 */ MCD_OPC_Decode, 136, 14, 61, // Opcode: ST2i32_POST -/* 6100 */ MCD_OPC_FilterValue, 1, 233, 134, // Skip to: 40641 -/* 6104 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6107 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6131 -/* 6111 */ MCD_OPC_CheckPredicate, 0, 222, 134, // Skip to: 40641 -/* 6115 */ MCD_OPC_CheckField, 31, 1, 0, 216, 134, // Skip to: 40641 -/* 6121 */ MCD_OPC_CheckField, 12, 1, 0, 210, 134, // Skip to: 40641 -/* 6127 */ MCD_OPC_Decode, 244, 13, 62, // Opcode: ST1i64_POST -/* 6131 */ MCD_OPC_FilterValue, 1, 202, 134, // Skip to: 40641 -/* 6135 */ MCD_OPC_CheckPredicate, 0, 198, 134, // Skip to: 40641 -/* 6139 */ MCD_OPC_CheckField, 31, 1, 0, 192, 134, // Skip to: 40641 -/* 6145 */ MCD_OPC_CheckField, 12, 1, 0, 186, 134, // Skip to: 40641 -/* 6151 */ MCD_OPC_Decode, 138, 14, 63, // Opcode: ST2i64_POST -/* 6155 */ MCD_OPC_FilterValue, 5, 178, 134, // Skip to: 40641 -/* 6159 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 6162 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6205 -/* 6166 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6169 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6187 -/* 6173 */ MCD_OPC_CheckPredicate, 0, 160, 134, // Skip to: 40641 -/* 6177 */ MCD_OPC_CheckField, 31, 1, 0, 154, 134, // Skip to: 40641 -/* 6183 */ MCD_OPC_Decode, 158, 14, 64, // Opcode: ST3i32_POST -/* 6187 */ MCD_OPC_FilterValue, 1, 146, 134, // Skip to: 40641 -/* 6191 */ MCD_OPC_CheckPredicate, 0, 142, 134, // Skip to: 40641 -/* 6195 */ MCD_OPC_CheckField, 31, 1, 0, 136, 134, // Skip to: 40641 -/* 6201 */ MCD_OPC_Decode, 180, 14, 65, // Opcode: ST4i32_POST -/* 6205 */ MCD_OPC_FilterValue, 1, 128, 134, // Skip to: 40641 -/* 6209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6212 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6236 -/* 6216 */ MCD_OPC_CheckPredicate, 0, 117, 134, // Skip to: 40641 -/* 6220 */ MCD_OPC_CheckField, 31, 1, 0, 111, 134, // Skip to: 40641 -/* 6226 */ MCD_OPC_CheckField, 12, 1, 0, 105, 134, // Skip to: 40641 -/* 6232 */ MCD_OPC_Decode, 160, 14, 66, // Opcode: ST3i64_POST -/* 6236 */ MCD_OPC_FilterValue, 1, 97, 134, // Skip to: 40641 -/* 6240 */ MCD_OPC_CheckPredicate, 0, 93, 134, // Skip to: 40641 -/* 6244 */ MCD_OPC_CheckField, 31, 1, 0, 87, 134, // Skip to: 40641 -/* 6250 */ MCD_OPC_CheckField, 12, 1, 0, 81, 134, // Skip to: 40641 -/* 6256 */ MCD_OPC_Decode, 182, 14, 67, // Opcode: ST4i64_POST -/* 6260 */ MCD_OPC_FilterValue, 1, 73, 134, // Skip to: 40641 -/* 6264 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6267 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 6275 -/* 6271 */ MCD_OPC_Decode, 208, 14, 3, // Opcode: STPSpre -/* 6275 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 6283 -/* 6279 */ MCD_OPC_Decode, 202, 14, 3, // Opcode: STPDpre -/* 6283 */ MCD_OPC_FilterValue, 2, 50, 134, // Skip to: 40641 -/* 6287 */ MCD_OPC_Decode, 205, 14, 3, // Opcode: STPQpre -/* 6291 */ MCD_OPC_FilterValue, 7, 245, 3, // Skip to: 7308 -/* 6295 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... -/* 6298 */ MCD_OPC_FilterValue, 0, 207, 3, // Skip to: 7277 -/* 6302 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 6305 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6348 -/* 6309 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6312 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6330 -/* 6316 */ MCD_OPC_CheckPredicate, 0, 17, 134, // Skip to: 40641 -/* 6320 */ MCD_OPC_CheckField, 31, 1, 0, 11, 134, // Skip to: 40641 -/* 6326 */ MCD_OPC_Decode, 178, 6, 68, // Opcode: LD1i8_POST -/* 6330 */ MCD_OPC_FilterValue, 1, 3, 134, // Skip to: 40641 -/* 6334 */ MCD_OPC_CheckPredicate, 0, 255, 133, // Skip to: 40641 -/* 6338 */ MCD_OPC_CheckField, 31, 1, 0, 249, 133, // Skip to: 40641 -/* 6344 */ MCD_OPC_Decode, 216, 6, 69, // Opcode: LD2i8_POST -/* 6348 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 6391 -/* 6352 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6355 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6373 -/* 6359 */ MCD_OPC_CheckPredicate, 0, 230, 133, // Skip to: 40641 -/* 6363 */ MCD_OPC_CheckField, 31, 1, 0, 224, 133, // Skip to: 40641 -/* 6369 */ MCD_OPC_Decode, 254, 6, 70, // Opcode: LD3i8_POST -/* 6373 */ MCD_OPC_FilterValue, 1, 216, 133, // Skip to: 40641 -/* 6377 */ MCD_OPC_CheckPredicate, 0, 212, 133, // Skip to: 40641 -/* 6381 */ MCD_OPC_CheckField, 31, 1, 0, 206, 133, // Skip to: 40641 -/* 6387 */ MCD_OPC_Decode, 164, 7, 71, // Opcode: LD4i8_POST -/* 6391 */ MCD_OPC_FilterValue, 2, 51, 0, // Skip to: 6446 -/* 6395 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6398 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6422 -/* 6402 */ MCD_OPC_CheckPredicate, 0, 187, 133, // Skip to: 40641 -/* 6406 */ MCD_OPC_CheckField, 31, 1, 0, 181, 133, // Skip to: 40641 -/* 6412 */ MCD_OPC_CheckField, 10, 1, 0, 175, 133, // Skip to: 40641 -/* 6418 */ MCD_OPC_Decode, 172, 6, 72, // Opcode: LD1i16_POST -/* 6422 */ MCD_OPC_FilterValue, 1, 167, 133, // Skip to: 40641 -/* 6426 */ MCD_OPC_CheckPredicate, 0, 163, 133, // Skip to: 40641 -/* 6430 */ MCD_OPC_CheckField, 31, 1, 0, 157, 133, // Skip to: 40641 -/* 6436 */ MCD_OPC_CheckField, 10, 1, 0, 151, 133, // Skip to: 40641 -/* 6442 */ MCD_OPC_Decode, 210, 6, 73, // Opcode: LD2i16_POST -/* 6446 */ MCD_OPC_FilterValue, 3, 51, 0, // Skip to: 6501 -/* 6450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6453 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6477 -/* 6457 */ MCD_OPC_CheckPredicate, 0, 132, 133, // Skip to: 40641 -/* 6461 */ MCD_OPC_CheckField, 31, 1, 0, 126, 133, // Skip to: 40641 -/* 6467 */ MCD_OPC_CheckField, 10, 1, 0, 120, 133, // Skip to: 40641 -/* 6473 */ MCD_OPC_Decode, 248, 6, 74, // Opcode: LD3i16_POST -/* 6477 */ MCD_OPC_FilterValue, 1, 112, 133, // Skip to: 40641 -/* 6481 */ MCD_OPC_CheckPredicate, 0, 108, 133, // Skip to: 40641 -/* 6485 */ MCD_OPC_CheckField, 31, 1, 0, 102, 133, // Skip to: 40641 -/* 6491 */ MCD_OPC_CheckField, 10, 1, 0, 96, 133, // Skip to: 40641 -/* 6497 */ MCD_OPC_Decode, 158, 7, 75, // Opcode: LD4i16_POST -/* 6501 */ MCD_OPC_FilterValue, 4, 101, 0, // Skip to: 6606 -/* 6505 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 6508 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6551 -/* 6512 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6515 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6533 -/* 6519 */ MCD_OPC_CheckPredicate, 0, 70, 133, // Skip to: 40641 -/* 6523 */ MCD_OPC_CheckField, 31, 1, 0, 64, 133, // Skip to: 40641 -/* 6529 */ MCD_OPC_Decode, 174, 6, 76, // Opcode: LD1i32_POST -/* 6533 */ MCD_OPC_FilterValue, 1, 56, 133, // Skip to: 40641 -/* 6537 */ MCD_OPC_CheckPredicate, 0, 52, 133, // Skip to: 40641 -/* 6541 */ MCD_OPC_CheckField, 31, 1, 0, 46, 133, // Skip to: 40641 -/* 6547 */ MCD_OPC_Decode, 212, 6, 77, // Opcode: LD2i32_POST -/* 6551 */ MCD_OPC_FilterValue, 1, 38, 133, // Skip to: 40641 -/* 6555 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6558 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6582 -/* 6562 */ MCD_OPC_CheckPredicate, 0, 27, 133, // Skip to: 40641 -/* 6566 */ MCD_OPC_CheckField, 31, 1, 0, 21, 133, // Skip to: 40641 -/* 6572 */ MCD_OPC_CheckField, 12, 1, 0, 15, 133, // Skip to: 40641 -/* 6578 */ MCD_OPC_Decode, 176, 6, 78, // Opcode: LD1i64_POST -/* 6582 */ MCD_OPC_FilterValue, 1, 7, 133, // Skip to: 40641 -/* 6586 */ MCD_OPC_CheckPredicate, 0, 3, 133, // Skip to: 40641 -/* 6590 */ MCD_OPC_CheckField, 31, 1, 0, 253, 132, // Skip to: 40641 -/* 6596 */ MCD_OPC_CheckField, 12, 1, 0, 247, 132, // Skip to: 40641 -/* 6602 */ MCD_OPC_Decode, 214, 6, 79, // Opcode: LD2i64_POST -/* 6606 */ MCD_OPC_FilterValue, 5, 101, 0, // Skip to: 6711 -/* 6610 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 6613 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 6656 -/* 6617 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6620 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 6638 -/* 6624 */ MCD_OPC_CheckPredicate, 0, 221, 132, // Skip to: 40641 -/* 6628 */ MCD_OPC_CheckField, 31, 1, 0, 215, 132, // Skip to: 40641 -/* 6634 */ MCD_OPC_Decode, 250, 6, 80, // Opcode: LD3i32_POST -/* 6638 */ MCD_OPC_FilterValue, 1, 207, 132, // Skip to: 40641 -/* 6642 */ MCD_OPC_CheckPredicate, 0, 203, 132, // Skip to: 40641 -/* 6646 */ MCD_OPC_CheckField, 31, 1, 0, 197, 132, // Skip to: 40641 -/* 6652 */ MCD_OPC_Decode, 160, 7, 81, // Opcode: LD4i32_POST -/* 6656 */ MCD_OPC_FilterValue, 1, 189, 132, // Skip to: 40641 -/* 6660 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6663 */ MCD_OPC_FilterValue, 0, 20, 0, // Skip to: 6687 -/* 6667 */ MCD_OPC_CheckPredicate, 0, 178, 132, // Skip to: 40641 -/* 6671 */ MCD_OPC_CheckField, 31, 1, 0, 172, 132, // Skip to: 40641 -/* 6677 */ MCD_OPC_CheckField, 12, 1, 0, 166, 132, // Skip to: 40641 -/* 6683 */ MCD_OPC_Decode, 252, 6, 82, // Opcode: LD3i64_POST -/* 6687 */ MCD_OPC_FilterValue, 1, 158, 132, // Skip to: 40641 -/* 6691 */ MCD_OPC_CheckPredicate, 0, 154, 132, // Skip to: 40641 -/* 6695 */ MCD_OPC_CheckField, 31, 1, 0, 148, 132, // Skip to: 40641 -/* 6701 */ MCD_OPC_CheckField, 12, 1, 0, 142, 132, // Skip to: 40641 -/* 6707 */ MCD_OPC_Decode, 162, 7, 83, // Opcode: LD4i64_POST -/* 6711 */ MCD_OPC_FilterValue, 6, 23, 1, // Skip to: 6994 -/* 6715 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 6718 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 6787 -/* 6722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6725 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6756 -/* 6729 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6732 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6744 -/* 6736 */ MCD_OPC_CheckPredicate, 0, 109, 132, // Skip to: 40641 -/* 6740 */ MCD_OPC_Decode, 136, 6, 14, // Opcode: LD1Rv8b_POST -/* 6744 */ MCD_OPC_FilterValue, 1, 101, 132, // Skip to: 40641 -/* 6748 */ MCD_OPC_CheckPredicate, 0, 97, 132, // Skip to: 40641 -/* 6752 */ MCD_OPC_Decode, 252, 5, 18, // Opcode: LD1Rv16b_POST -/* 6756 */ MCD_OPC_FilterValue, 1, 89, 132, // Skip to: 40641 -/* 6760 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6763 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6775 -/* 6767 */ MCD_OPC_CheckPredicate, 0, 78, 132, // Skip to: 40641 -/* 6771 */ MCD_OPC_Decode, 192, 6, 15, // Opcode: LD2Rv8b_POST -/* 6775 */ MCD_OPC_FilterValue, 1, 70, 132, // Skip to: 40641 -/* 6779 */ MCD_OPC_CheckPredicate, 0, 66, 132, // Skip to: 40641 -/* 6783 */ MCD_OPC_Decode, 180, 6, 19, // Opcode: LD2Rv16b_POST -/* 6787 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 6856 -/* 6791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6794 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6825 -/* 6798 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6801 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6813 -/* 6805 */ MCD_OPC_CheckPredicate, 0, 40, 132, // Skip to: 40641 -/* 6809 */ MCD_OPC_Decode, 132, 6, 14, // Opcode: LD1Rv4h_POST -/* 6813 */ MCD_OPC_FilterValue, 1, 32, 132, // Skip to: 40641 -/* 6817 */ MCD_OPC_CheckPredicate, 0, 28, 132, // Skip to: 40641 -/* 6821 */ MCD_OPC_Decode, 138, 6, 18, // Opcode: LD1Rv8h_POST -/* 6825 */ MCD_OPC_FilterValue, 1, 20, 132, // Skip to: 40641 -/* 6829 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6832 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6844 -/* 6836 */ MCD_OPC_CheckPredicate, 0, 9, 132, // Skip to: 40641 -/* 6840 */ MCD_OPC_Decode, 188, 6, 15, // Opcode: LD2Rv4h_POST -/* 6844 */ MCD_OPC_FilterValue, 1, 1, 132, // Skip to: 40641 -/* 6848 */ MCD_OPC_CheckPredicate, 0, 253, 131, // Skip to: 40641 -/* 6852 */ MCD_OPC_Decode, 194, 6, 19, // Opcode: LD2Rv8h_POST -/* 6856 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 6925 -/* 6860 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6863 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6894 -/* 6867 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6870 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6882 -/* 6874 */ MCD_OPC_CheckPredicate, 0, 227, 131, // Skip to: 40641 -/* 6878 */ MCD_OPC_Decode, 130, 6, 14, // Opcode: LD1Rv2s_POST -/* 6882 */ MCD_OPC_FilterValue, 1, 219, 131, // Skip to: 40641 -/* 6886 */ MCD_OPC_CheckPredicate, 0, 215, 131, // Skip to: 40641 -/* 6890 */ MCD_OPC_Decode, 134, 6, 18, // Opcode: LD1Rv4s_POST -/* 6894 */ MCD_OPC_FilterValue, 1, 207, 131, // Skip to: 40641 -/* 6898 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6901 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6913 -/* 6905 */ MCD_OPC_CheckPredicate, 0, 196, 131, // Skip to: 40641 -/* 6909 */ MCD_OPC_Decode, 186, 6, 15, // Opcode: LD2Rv2s_POST -/* 6913 */ MCD_OPC_FilterValue, 1, 188, 131, // Skip to: 40641 -/* 6917 */ MCD_OPC_CheckPredicate, 0, 184, 131, // Skip to: 40641 -/* 6921 */ MCD_OPC_Decode, 190, 6, 19, // Opcode: LD2Rv4s_POST -/* 6925 */ MCD_OPC_FilterValue, 3, 176, 131, // Skip to: 40641 -/* 6929 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 6932 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 6963 -/* 6936 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6939 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6951 -/* 6943 */ MCD_OPC_CheckPredicate, 0, 158, 131, // Skip to: 40641 -/* 6947 */ MCD_OPC_Decode, 254, 5, 14, // Opcode: LD1Rv1d_POST -/* 6951 */ MCD_OPC_FilterValue, 1, 150, 131, // Skip to: 40641 -/* 6955 */ MCD_OPC_CheckPredicate, 0, 146, 131, // Skip to: 40641 -/* 6959 */ MCD_OPC_Decode, 128, 6, 18, // Opcode: LD1Rv2d_POST -/* 6963 */ MCD_OPC_FilterValue, 1, 138, 131, // Skip to: 40641 -/* 6967 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 6970 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 6982 -/* 6974 */ MCD_OPC_CheckPredicate, 0, 127, 131, // Skip to: 40641 -/* 6978 */ MCD_OPC_Decode, 182, 6, 15, // Opcode: LD2Rv1d_POST -/* 6982 */ MCD_OPC_FilterValue, 1, 119, 131, // Skip to: 40641 -/* 6986 */ MCD_OPC_CheckPredicate, 0, 115, 131, // Skip to: 40641 -/* 6990 */ MCD_OPC_Decode, 184, 6, 19, // Opcode: LD2Rv2d_POST -/* 6994 */ MCD_OPC_FilterValue, 7, 107, 131, // Skip to: 40641 -/* 6998 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... -/* 7001 */ MCD_OPC_FilterValue, 0, 65, 0, // Skip to: 7070 -/* 7005 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7008 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7039 -/* 7012 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7015 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7027 -/* 7019 */ MCD_OPC_CheckPredicate, 0, 82, 131, // Skip to: 40641 -/* 7023 */ MCD_OPC_Decode, 230, 6, 13, // Opcode: LD3Rv8b_POST -/* 7027 */ MCD_OPC_FilterValue, 1, 74, 131, // Skip to: 40641 -/* 7031 */ MCD_OPC_CheckPredicate, 0, 70, 131, // Skip to: 40641 -/* 7035 */ MCD_OPC_Decode, 218, 6, 17, // Opcode: LD3Rv16b_POST -/* 7039 */ MCD_OPC_FilterValue, 1, 62, 131, // Skip to: 40641 -/* 7043 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7046 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7058 -/* 7050 */ MCD_OPC_CheckPredicate, 0, 51, 131, // Skip to: 40641 -/* 7054 */ MCD_OPC_Decode, 154, 7, 12, // Opcode: LD4Rv8b_POST -/* 7058 */ MCD_OPC_FilterValue, 1, 43, 131, // Skip to: 40641 -/* 7062 */ MCD_OPC_CheckPredicate, 0, 39, 131, // Skip to: 40641 -/* 7066 */ MCD_OPC_Decode, 142, 7, 16, // Opcode: LD4Rv16b_POST -/* 7070 */ MCD_OPC_FilterValue, 1, 65, 0, // Skip to: 7139 -/* 7074 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7077 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7108 -/* 7081 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7084 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7096 -/* 7088 */ MCD_OPC_CheckPredicate, 0, 13, 131, // Skip to: 40641 -/* 7092 */ MCD_OPC_Decode, 226, 6, 13, // Opcode: LD3Rv4h_POST -/* 7096 */ MCD_OPC_FilterValue, 1, 5, 131, // Skip to: 40641 -/* 7100 */ MCD_OPC_CheckPredicate, 0, 1, 131, // Skip to: 40641 -/* 7104 */ MCD_OPC_Decode, 232, 6, 17, // Opcode: LD3Rv8h_POST -/* 7108 */ MCD_OPC_FilterValue, 1, 249, 130, // Skip to: 40641 -/* 7112 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7115 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7127 -/* 7119 */ MCD_OPC_CheckPredicate, 0, 238, 130, // Skip to: 40641 -/* 7123 */ MCD_OPC_Decode, 150, 7, 12, // Opcode: LD4Rv4h_POST -/* 7127 */ MCD_OPC_FilterValue, 1, 230, 130, // Skip to: 40641 -/* 7131 */ MCD_OPC_CheckPredicate, 0, 226, 130, // Skip to: 40641 -/* 7135 */ MCD_OPC_Decode, 156, 7, 16, // Opcode: LD4Rv8h_POST -/* 7139 */ MCD_OPC_FilterValue, 2, 65, 0, // Skip to: 7208 -/* 7143 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7146 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7177 -/* 7150 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7153 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7165 -/* 7157 */ MCD_OPC_CheckPredicate, 0, 200, 130, // Skip to: 40641 -/* 7161 */ MCD_OPC_Decode, 224, 6, 13, // Opcode: LD3Rv2s_POST -/* 7165 */ MCD_OPC_FilterValue, 1, 192, 130, // Skip to: 40641 -/* 7169 */ MCD_OPC_CheckPredicate, 0, 188, 130, // Skip to: 40641 -/* 7173 */ MCD_OPC_Decode, 228, 6, 17, // Opcode: LD3Rv4s_POST -/* 7177 */ MCD_OPC_FilterValue, 1, 180, 130, // Skip to: 40641 -/* 7181 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7184 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7196 -/* 7188 */ MCD_OPC_CheckPredicate, 0, 169, 130, // Skip to: 40641 -/* 7192 */ MCD_OPC_Decode, 148, 7, 12, // Opcode: LD4Rv2s_POST -/* 7196 */ MCD_OPC_FilterValue, 1, 161, 130, // Skip to: 40641 -/* 7200 */ MCD_OPC_CheckPredicate, 0, 157, 130, // Skip to: 40641 -/* 7204 */ MCD_OPC_Decode, 152, 7, 16, // Opcode: LD4Rv4s_POST -/* 7208 */ MCD_OPC_FilterValue, 3, 149, 130, // Skip to: 40641 -/* 7212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7215 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7246 -/* 7219 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7222 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7234 -/* 7226 */ MCD_OPC_CheckPredicate, 0, 131, 130, // Skip to: 40641 -/* 7230 */ MCD_OPC_Decode, 220, 6, 13, // Opcode: LD3Rv1d_POST -/* 7234 */ MCD_OPC_FilterValue, 1, 123, 130, // Skip to: 40641 -/* 7238 */ MCD_OPC_CheckPredicate, 0, 119, 130, // Skip to: 40641 -/* 7242 */ MCD_OPC_Decode, 222, 6, 17, // Opcode: LD3Rv2d_POST -/* 7246 */ MCD_OPC_FilterValue, 1, 111, 130, // Skip to: 40641 -/* 7250 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7253 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7265 -/* 7257 */ MCD_OPC_CheckPredicate, 0, 100, 130, // Skip to: 40641 -/* 7261 */ MCD_OPC_Decode, 144, 7, 12, // Opcode: LD4Rv1d_POST -/* 7265 */ MCD_OPC_FilterValue, 1, 92, 130, // Skip to: 40641 -/* 7269 */ MCD_OPC_CheckPredicate, 0, 88, 130, // Skip to: 40641 -/* 7273 */ MCD_OPC_Decode, 146, 7, 16, // Opcode: LD4Rv2d_POST -/* 7277 */ MCD_OPC_FilterValue, 1, 80, 130, // Skip to: 40641 -/* 7281 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... -/* 7284 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 7292 -/* 7288 */ MCD_OPC_Decode, 191, 7, 3, // Opcode: LDPSpre -/* 7292 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 7300 -/* 7296 */ MCD_OPC_Decode, 182, 7, 3, // Opcode: LDPDpre -/* 7300 */ MCD_OPC_FilterValue, 2, 57, 130, // Skip to: 40641 -/* 7304 */ MCD_OPC_Decode, 185, 7, 3, // Opcode: LDPQpre -/* 7308 */ MCD_OPC_FilterValue, 8, 171, 21, // Skip to: 12859 -/* 7312 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 7315 */ MCD_OPC_FilterValue, 0, 36, 6, // Skip to: 8891 -/* 7319 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 7322 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 7353 -/* 7326 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7329 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7341 -/* 7333 */ MCD_OPC_CheckPredicate, 0, 24, 130, // Skip to: 40641 -/* 7337 */ MCD_OPC_Decode, 202, 15, 84, // Opcode: TBLv8i8One -/* 7341 */ MCD_OPC_FilterValue, 1, 16, 130, // Skip to: 40641 -/* 7345 */ MCD_OPC_CheckPredicate, 0, 12, 130, // Skip to: 40641 -/* 7349 */ MCD_OPC_Decode, 247, 9, 85, // Opcode: SADDLv8i8_v8i16 -/* 7353 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 7428 -/* 7357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7360 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 7416 -/* 7364 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 7367 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7404 -/* 7371 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 7374 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7392 -/* 7378 */ MCD_OPC_CheckPredicate, 0, 235, 129, // Skip to: 40641 -/* 7382 */ MCD_OPC_CheckField, 18, 1, 1, 229, 129, // Skip to: 40641 -/* 7388 */ MCD_OPC_Decode, 151, 2, 86, // Opcode: DUPv2i32lane -/* 7392 */ MCD_OPC_FilterValue, 1, 221, 129, // Skip to: 40641 -/* 7396 */ MCD_OPC_CheckPredicate, 0, 217, 129, // Skip to: 40641 -/* 7400 */ MCD_OPC_Decode, 155, 2, 87, // Opcode: DUPv4i16lane -/* 7404 */ MCD_OPC_FilterValue, 1, 209, 129, // Skip to: 40641 -/* 7408 */ MCD_OPC_CheckPredicate, 0, 205, 129, // Skip to: 40641 -/* 7412 */ MCD_OPC_Decode, 161, 2, 88, // Opcode: DUPv8i8lane -/* 7416 */ MCD_OPC_FilterValue, 1, 197, 129, // Skip to: 40641 -/* 7420 */ MCD_OPC_CheckPredicate, 0, 193, 129, // Skip to: 40641 -/* 7424 */ MCD_OPC_Decode, 169, 10, 89, // Opcode: SHADDv8i8 -/* 7428 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 7446 -/* 7432 */ MCD_OPC_CheckPredicate, 0, 181, 129, // Skip to: 40641 -/* 7436 */ MCD_OPC_CheckField, 16, 6, 32, 175, 129, // Skip to: 40641 -/* 7442 */ MCD_OPC_Decode, 184, 9, 90, // Opcode: REV64v8i8 -/* 7446 */ MCD_OPC_FilterValue, 3, 58, 0, // Skip to: 7508 -/* 7450 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7453 */ MCD_OPC_FilterValue, 0, 39, 0, // Skip to: 7496 -/* 7457 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 7460 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 7472 -/* 7464 */ MCD_OPC_CheckPredicate, 0, 149, 129, // Skip to: 40641 -/* 7468 */ MCD_OPC_Decode, 160, 2, 91, // Opcode: DUPv8i8gpr -/* 7472 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 7484 -/* 7476 */ MCD_OPC_CheckPredicate, 0, 137, 129, // Skip to: 40641 -/* 7480 */ MCD_OPC_Decode, 154, 2, 91, // Opcode: DUPv4i16gpr -/* 7484 */ MCD_OPC_FilterValue, 4, 129, 129, // Skip to: 40641 -/* 7488 */ MCD_OPC_CheckPredicate, 0, 125, 129, // Skip to: 40641 -/* 7492 */ MCD_OPC_Decode, 150, 2, 91, // Opcode: DUPv2i32gpr -/* 7496 */ MCD_OPC_FilterValue, 1, 117, 129, // Skip to: 40641 -/* 7500 */ MCD_OPC_CheckPredicate, 0, 113, 129, // Skip to: 40641 -/* 7504 */ MCD_OPC_Decode, 170, 11, 89, // Opcode: SQADDv8i8 -/* 7508 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 7539 -/* 7512 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7515 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7527 -/* 7519 */ MCD_OPC_CheckPredicate, 0, 94, 129, // Skip to: 40641 -/* 7523 */ MCD_OPC_Decode, 212, 15, 92, // Opcode: TBXv8i8One -/* 7527 */ MCD_OPC_FilterValue, 1, 86, 129, // Skip to: 40641 -/* 7531 */ MCD_OPC_CheckPredicate, 0, 82, 129, // Skip to: 40641 -/* 7535 */ MCD_OPC_Decode, 253, 9, 93, // Opcode: SADDWv8i8_v8i16 -/* 7539 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 7557 -/* 7543 */ MCD_OPC_CheckPredicate, 0, 70, 129, // Skip to: 40641 -/* 7547 */ MCD_OPC_CheckField, 21, 1, 1, 64, 129, // Skip to: 40641 -/* 7553 */ MCD_OPC_Decode, 228, 12, 89, // Opcode: SRHADDv8i8 -/* 7557 */ MCD_OPC_FilterValue, 6, 33, 0, // Skip to: 7594 -/* 7561 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7564 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7576 -/* 7568 */ MCD_OPC_CheckPredicate, 0, 45, 129, // Skip to: 40641 -/* 7572 */ MCD_OPC_Decode, 186, 18, 89, // Opcode: UZP1v8i8 -/* 7576 */ MCD_OPC_FilterValue, 1, 37, 129, // Skip to: 40641 -/* 7580 */ MCD_OPC_CheckPredicate, 0, 33, 129, // Skip to: 40641 -/* 7584 */ MCD_OPC_CheckField, 16, 5, 0, 27, 129, // Skip to: 40641 -/* 7590 */ MCD_OPC_Decode, 173, 9, 90, // Opcode: REV16v8i8 -/* 7594 */ MCD_OPC_FilterValue, 7, 13, 0, // Skip to: 7611 -/* 7598 */ MCD_OPC_CheckPredicate, 0, 15, 129, // Skip to: 40641 -/* 7602 */ MCD_OPC_CheckField, 21, 1, 1, 9, 129, // Skip to: 40641 -/* 7608 */ MCD_OPC_Decode, 100, 89, // Opcode: ANDv8i8 -/* 7611 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 7642 -/* 7615 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7618 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7630 -/* 7622 */ MCD_OPC_CheckPredicate, 0, 247, 128, // Skip to: 40641 -/* 7626 */ MCD_OPC_Decode, 204, 15, 94, // Opcode: TBLv8i8Two -/* 7630 */ MCD_OPC_FilterValue, 1, 239, 128, // Skip to: 40641 -/* 7634 */ MCD_OPC_CheckPredicate, 0, 235, 128, // Skip to: 40641 -/* 7638 */ MCD_OPC_Decode, 168, 13, 85, // Opcode: SSUBLv8i8_v8i16 -/* 7642 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 7660 -/* 7646 */ MCD_OPC_CheckPredicate, 0, 223, 128, // Skip to: 40641 -/* 7650 */ MCD_OPC_CheckField, 21, 1, 1, 217, 128, // Skip to: 40641 -/* 7656 */ MCD_OPC_Decode, 195, 10, 89, // Opcode: SHSUBv8i8 -/* 7660 */ MCD_OPC_FilterValue, 10, 46, 0, // Skip to: 7710 -/* 7664 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7667 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7679 -/* 7671 */ MCD_OPC_CheckPredicate, 0, 198, 128, // Skip to: 40641 -/* 7675 */ MCD_OPC_Decode, 227, 15, 89, // Opcode: TRN1v8i8 -/* 7679 */ MCD_OPC_FilterValue, 1, 190, 128, // Skip to: 40641 -/* 7683 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 7686 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7698 -/* 7690 */ MCD_OPC_CheckPredicate, 0, 179, 128, // Skip to: 40641 -/* 7694 */ MCD_OPC_Decode, 236, 9, 90, // Opcode: SADDLPv8i8_v4i16 -/* 7698 */ MCD_OPC_FilterValue, 1, 171, 128, // Skip to: 40641 -/* 7702 */ MCD_OPC_CheckPredicate, 0, 167, 128, // Skip to: 40641 -/* 7706 */ MCD_OPC_Decode, 199, 18, 95, // Opcode: XTNv8i8 -/* 7710 */ MCD_OPC_FilterValue, 11, 52, 0, // Skip to: 7766 -/* 7714 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7717 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7754 -/* 7721 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 7724 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7742 -/* 7728 */ MCD_OPC_CheckPredicate, 0, 141, 128, // Skip to: 40641 -/* 7732 */ MCD_OPC_CheckField, 17, 1, 1, 135, 128, // Skip to: 40641 -/* 7738 */ MCD_OPC_Decode, 132, 11, 96, // Opcode: SMOVvi16to32 -/* 7742 */ MCD_OPC_FilterValue, 1, 127, 128, // Skip to: 40641 -/* 7746 */ MCD_OPC_CheckPredicate, 0, 123, 128, // Skip to: 40641 -/* 7750 */ MCD_OPC_Decode, 135, 11, 97, // Opcode: SMOVvi8to32 -/* 7754 */ MCD_OPC_FilterValue, 1, 115, 128, // Skip to: 40641 -/* 7758 */ MCD_OPC_CheckPredicate, 0, 111, 128, // Skip to: 40641 -/* 7762 */ MCD_OPC_Decode, 204, 12, 89, // Opcode: SQSUBv8i8 -/* 7766 */ MCD_OPC_FilterValue, 12, 27, 0, // Skip to: 7797 -/* 7770 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7773 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7785 -/* 7777 */ MCD_OPC_CheckPredicate, 0, 92, 128, // Skip to: 40641 -/* 7781 */ MCD_OPC_Decode, 214, 15, 98, // Opcode: TBXv8i8Two -/* 7785 */ MCD_OPC_FilterValue, 1, 84, 128, // Skip to: 40641 -/* 7789 */ MCD_OPC_CheckPredicate, 0, 80, 128, // Skip to: 40641 -/* 7793 */ MCD_OPC_Decode, 174, 13, 93, // Opcode: SSUBWv8i8_v8i16 -/* 7797 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 7815 -/* 7801 */ MCD_OPC_CheckPredicate, 0, 68, 128, // Skip to: 40641 -/* 7805 */ MCD_OPC_CheckField, 21, 1, 1, 62, 128, // Skip to: 40641 -/* 7811 */ MCD_OPC_Decode, 206, 1, 89, // Opcode: CMGTv8i8 -/* 7815 */ MCD_OPC_FilterValue, 14, 46, 0, // Skip to: 7865 -/* 7819 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7822 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7834 -/* 7826 */ MCD_OPC_CheckPredicate, 0, 43, 128, // Skip to: 40641 -/* 7830 */ MCD_OPC_Decode, 206, 18, 89, // Opcode: ZIP1v8i8 -/* 7834 */ MCD_OPC_FilterValue, 1, 35, 128, // Skip to: 40641 -/* 7838 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 7841 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7853 -/* 7845 */ MCD_OPC_CheckPredicate, 0, 24, 128, // Skip to: 40641 -/* 7849 */ MCD_OPC_Decode, 193, 15, 99, // Opcode: SUQADDv8i8 -/* 7853 */ MCD_OPC_FilterValue, 16, 16, 128, // Skip to: 40641 -/* 7857 */ MCD_OPC_CheckPredicate, 0, 12, 128, // Skip to: 40641 -/* 7861 */ MCD_OPC_Decode, 241, 9, 100, // Opcode: SADDLVv8i8v -/* 7865 */ MCD_OPC_FilterValue, 15, 71, 0, // Skip to: 7940 -/* 7869 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7872 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 7928 -/* 7876 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 7879 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 7916 -/* 7883 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 7886 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 7904 -/* 7890 */ MCD_OPC_CheckPredicate, 0, 235, 127, // Skip to: 40641 -/* 7894 */ MCD_OPC_CheckField, 18, 1, 1, 229, 127, // Skip to: 40641 -/* 7900 */ MCD_OPC_Decode, 252, 16, 101, // Opcode: UMOVvi32 -/* 7904 */ MCD_OPC_FilterValue, 1, 221, 127, // Skip to: 40641 -/* 7908 */ MCD_OPC_CheckPredicate, 0, 217, 127, // Skip to: 40641 -/* 7912 */ MCD_OPC_Decode, 251, 16, 96, // Opcode: UMOVvi16 -/* 7916 */ MCD_OPC_FilterValue, 1, 209, 127, // Skip to: 40641 -/* 7920 */ MCD_OPC_CheckPredicate, 0, 205, 127, // Skip to: 40641 -/* 7924 */ MCD_OPC_Decode, 254, 16, 97, // Opcode: UMOVvi8 -/* 7928 */ MCD_OPC_FilterValue, 1, 197, 127, // Skip to: 40641 -/* 7932 */ MCD_OPC_CheckPredicate, 0, 193, 127, // Skip to: 40641 -/* 7936 */ MCD_OPC_Decode, 190, 1, 89, // Opcode: CMGEv8i8 -/* 7940 */ MCD_OPC_FilterValue, 16, 26, 0, // Skip to: 7970 -/* 7944 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 7947 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 7959 -/* 7951 */ MCD_OPC_CheckPredicate, 0, 174, 127, // Skip to: 40641 -/* 7955 */ MCD_OPC_Decode, 203, 15, 102, // Opcode: TBLv8i8Three -/* 7959 */ MCD_OPC_FilterValue, 1, 166, 127, // Skip to: 40641 -/* 7963 */ MCD_OPC_CheckPredicate, 0, 162, 127, // Skip to: 40641 -/* 7967 */ MCD_OPC_Decode, 39, 103, // Opcode: ADDHNv8i16_v8i8 -/* 7970 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 7988 -/* 7974 */ MCD_OPC_CheckPredicate, 0, 151, 127, // Skip to: 40641 -/* 7978 */ MCD_OPC_CheckField, 21, 1, 1, 145, 127, // Skip to: 40641 -/* 7984 */ MCD_OPC_Decode, 146, 13, 89, // Opcode: SSHLv8i8 -/* 7988 */ MCD_OPC_FilterValue, 18, 27, 0, // Skip to: 8019 -/* 7992 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 7995 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8007 -/* 7999 */ MCD_OPC_CheckPredicate, 0, 126, 127, // Skip to: 40641 -/* 8003 */ MCD_OPC_Decode, 151, 1, 90, // Opcode: CLSv8i8 -/* 8007 */ MCD_OPC_FilterValue, 33, 118, 127, // Skip to: 40641 -/* 8011 */ MCD_OPC_CheckPredicate, 0, 114, 127, // Skip to: 40641 -/* 8015 */ MCD_OPC_Decode, 213, 12, 95, // Opcode: SQXTNv8i8 -/* 8019 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 8037 -/* 8023 */ MCD_OPC_CheckPredicate, 0, 102, 127, // Skip to: 40641 -/* 8027 */ MCD_OPC_CheckField, 21, 1, 1, 96, 127, // Skip to: 40641 -/* 8033 */ MCD_OPC_Decode, 174, 12, 89, // Opcode: SQSHLv8i8 -/* 8037 */ MCD_OPC_FilterValue, 20, 27, 0, // Skip to: 8068 -/* 8041 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8044 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8056 -/* 8048 */ MCD_OPC_CheckPredicate, 0, 77, 127, // Skip to: 40641 -/* 8052 */ MCD_OPC_Decode, 213, 15, 104, // Opcode: TBXv8i8Three -/* 8056 */ MCD_OPC_FilterValue, 1, 69, 127, // Skip to: 40641 -/* 8060 */ MCD_OPC_CheckPredicate, 0, 65, 127, // Skip to: 40641 -/* 8064 */ MCD_OPC_Decode, 206, 9, 105, // Opcode: SABALv8i8_v8i16 -/* 8068 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 8086 -/* 8072 */ MCD_OPC_CheckPredicate, 0, 53, 127, // Skip to: 40641 -/* 8076 */ MCD_OPC_CheckField, 21, 1, 1, 47, 127, // Skip to: 40641 -/* 8082 */ MCD_OPC_Decode, 244, 12, 89, // Opcode: SRSHLv8i8 -/* 8086 */ MCD_OPC_FilterValue, 22, 33, 0, // Skip to: 8123 -/* 8090 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8093 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8105 -/* 8097 */ MCD_OPC_CheckPredicate, 0, 28, 127, // Skip to: 40641 -/* 8101 */ MCD_OPC_Decode, 193, 18, 89, // Opcode: UZP2v8i8 -/* 8105 */ MCD_OPC_FilterValue, 1, 20, 127, // Skip to: 40641 -/* 8109 */ MCD_OPC_CheckPredicate, 0, 16, 127, // Skip to: 40641 -/* 8113 */ MCD_OPC_CheckField, 16, 5, 0, 10, 127, // Skip to: 40641 -/* 8119 */ MCD_OPC_Decode, 249, 1, 90, // Opcode: CNTv8i8 -/* 8123 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 8141 -/* 8127 */ MCD_OPC_CheckPredicate, 0, 254, 126, // Skip to: 40641 -/* 8131 */ MCD_OPC_CheckField, 21, 1, 1, 248, 126, // Skip to: 40641 -/* 8137 */ MCD_OPC_Decode, 252, 11, 89, // Opcode: SQRSHLv8i8 -/* 8141 */ MCD_OPC_FilterValue, 24, 27, 0, // Skip to: 8172 -/* 8145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8148 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8160 -/* 8152 */ MCD_OPC_CheckPredicate, 0, 229, 126, // Skip to: 40641 -/* 8156 */ MCD_OPC_Decode, 201, 15, 106, // Opcode: TBLv8i8Four -/* 8160 */ MCD_OPC_FilterValue, 1, 221, 126, // Skip to: 40641 -/* 8164 */ MCD_OPC_CheckPredicate, 0, 217, 126, // Skip to: 40641 -/* 8168 */ MCD_OPC_Decode, 156, 15, 103, // Opcode: SUBHNv8i16_v8i8 -/* 8172 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 8190 -/* 8176 */ MCD_OPC_CheckPredicate, 0, 205, 126, // Skip to: 40641 -/* 8180 */ MCD_OPC_CheckField, 21, 1, 1, 199, 126, // Skip to: 40641 -/* 8186 */ MCD_OPC_Decode, 221, 10, 89, // Opcode: SMAXv8i8 -/* 8190 */ MCD_OPC_FilterValue, 26, 46, 0, // Skip to: 8240 -/* 8194 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8197 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8209 -/* 8201 */ MCD_OPC_CheckPredicate, 0, 180, 126, // Skip to: 40641 -/* 8205 */ MCD_OPC_Decode, 234, 15, 89, // Opcode: TRN2v8i8 -/* 8209 */ MCD_OPC_FilterValue, 1, 172, 126, // Skip to: 40641 -/* 8213 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 8216 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8228 -/* 8220 */ MCD_OPC_CheckPredicate, 0, 161, 126, // Skip to: 40641 -/* 8224 */ MCD_OPC_Decode, 230, 9, 99, // Opcode: SADALPv8i8_v4i16 -/* 8228 */ MCD_OPC_FilterValue, 1, 153, 126, // Skip to: 40641 -/* 8232 */ MCD_OPC_CheckPredicate, 0, 149, 126, // Skip to: 40641 -/* 8236 */ MCD_OPC_Decode, 199, 3, 95, // Opcode: FCVTNv4i16 -/* 8240 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 8258 -/* 8244 */ MCD_OPC_CheckPredicate, 0, 137, 126, // Skip to: 40641 -/* 8248 */ MCD_OPC_CheckField, 21, 1, 1, 131, 126, // Skip to: 40641 -/* 8254 */ MCD_OPC_Decode, 239, 10, 89, // Opcode: SMINv8i8 -/* 8258 */ MCD_OPC_FilterValue, 28, 27, 0, // Skip to: 8289 -/* 8262 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8265 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8277 -/* 8269 */ MCD_OPC_CheckPredicate, 0, 112, 126, // Skip to: 40641 -/* 8273 */ MCD_OPC_Decode, 211, 15, 107, // Opcode: TBXv8i8Four -/* 8277 */ MCD_OPC_FilterValue, 1, 104, 126, // Skip to: 40641 -/* 8281 */ MCD_OPC_CheckPredicate, 0, 100, 126, // Skip to: 40641 -/* 8285 */ MCD_OPC_Decode, 218, 9, 85, // Opcode: SABDLv8i8_v8i16 -/* 8289 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 8307 -/* 8293 */ MCD_OPC_CheckPredicate, 0, 88, 126, // Skip to: 40641 -/* 8297 */ MCD_OPC_CheckField, 21, 1, 1, 82, 126, // Skip to: 40641 -/* 8303 */ MCD_OPC_Decode, 224, 9, 89, // Opcode: SABDv8i8 -/* 8307 */ MCD_OPC_FilterValue, 30, 46, 0, // Skip to: 8357 -/* 8311 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8314 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8326 -/* 8318 */ MCD_OPC_CheckPredicate, 0, 63, 126, // Skip to: 40641 -/* 8322 */ MCD_OPC_Decode, 213, 18, 89, // Opcode: ZIP2v8i8 -/* 8326 */ MCD_OPC_FilterValue, 1, 55, 126, // Skip to: 40641 -/* 8330 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 8333 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8345 -/* 8337 */ MCD_OPC_CheckPredicate, 0, 44, 126, // Skip to: 40641 -/* 8341 */ MCD_OPC_Decode, 159, 11, 90, // Opcode: SQABSv8i8 -/* 8345 */ MCD_OPC_FilterValue, 1, 36, 126, // Skip to: 40641 -/* 8349 */ MCD_OPC_CheckPredicate, 0, 32, 126, // Skip to: 40641 -/* 8353 */ MCD_OPC_Decode, 159, 3, 108, // Opcode: FCVTLv4i16 -/* 8357 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 8375 -/* 8361 */ MCD_OPC_CheckPredicate, 0, 20, 126, // Skip to: 40641 -/* 8365 */ MCD_OPC_CheckField, 21, 1, 1, 14, 126, // Skip to: 40641 -/* 8371 */ MCD_OPC_Decode, 212, 9, 109, // Opcode: SABAv8i8 -/* 8375 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 8393 -/* 8379 */ MCD_OPC_CheckPredicate, 0, 2, 126, // Skip to: 40641 -/* 8383 */ MCD_OPC_CheckField, 21, 1, 1, 252, 125, // Skip to: 40641 -/* 8389 */ MCD_OPC_Decode, 249, 10, 105, // Opcode: SMLALv8i8_v8i16 -/* 8393 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 8410 -/* 8397 */ MCD_OPC_CheckPredicate, 0, 240, 125, // Skip to: 40641 -/* 8401 */ MCD_OPC_CheckField, 21, 1, 1, 234, 125, // Skip to: 40641 -/* 8407 */ MCD_OPC_Decode, 78, 89, // Opcode: ADDv8i8 -/* 8410 */ MCD_OPC_FilterValue, 34, 27, 0, // Skip to: 8441 -/* 8414 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 8417 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8429 -/* 8421 */ MCD_OPC_CheckPredicate, 0, 216, 125, // Skip to: 40641 -/* 8425 */ MCD_OPC_Decode, 207, 1, 90, // Opcode: CMGTv8i8rz -/* 8429 */ MCD_OPC_FilterValue, 33, 208, 125, // Skip to: 40641 -/* 8433 */ MCD_OPC_CheckPredicate, 0, 204, 125, // Skip to: 40641 -/* 8437 */ MCD_OPC_Decode, 169, 5, 90, // Opcode: FRINTNv2f32 -/* 8441 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 8459 -/* 8445 */ MCD_OPC_CheckPredicate, 0, 192, 125, // Skip to: 40641 -/* 8449 */ MCD_OPC_CheckField, 21, 1, 1, 186, 125, // Skip to: 40641 -/* 8455 */ MCD_OPC_Decode, 247, 1, 89, // Opcode: CMTSTv8i8 -/* 8459 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 8477 -/* 8463 */ MCD_OPC_CheckPredicate, 0, 174, 125, // Skip to: 40641 -/* 8467 */ MCD_OPC_CheckField, 21, 1, 1, 168, 125, // Skip to: 40641 -/* 8473 */ MCD_OPC_Decode, 191, 8, 109, // Opcode: MLAv8i8 -/* 8477 */ MCD_OPC_FilterValue, 38, 27, 0, // Skip to: 8508 -/* 8481 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 8484 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8496 -/* 8488 */ MCD_OPC_CheckPredicate, 0, 149, 125, // Skip to: 40641 -/* 8492 */ MCD_OPC_Decode, 175, 1, 90, // Opcode: CMEQv8i8rz -/* 8496 */ MCD_OPC_FilterValue, 33, 141, 125, // Skip to: 40641 -/* 8500 */ MCD_OPC_CheckPredicate, 0, 137, 125, // Skip to: 40641 -/* 8504 */ MCD_OPC_Decode, 164, 5, 90, // Opcode: FRINTMv2f32 -/* 8508 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 8526 -/* 8512 */ MCD_OPC_CheckPredicate, 0, 125, 125, // Skip to: 40641 -/* 8516 */ MCD_OPC_CheckField, 21, 1, 1, 119, 125, // Skip to: 40641 -/* 8522 */ MCD_OPC_Decode, 240, 8, 89, // Opcode: MULv8i8 -/* 8526 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 8544 -/* 8530 */ MCD_OPC_CheckPredicate, 0, 107, 125, // Skip to: 40641 -/* 8534 */ MCD_OPC_CheckField, 21, 1, 1, 101, 125, // Skip to: 40641 -/* 8540 */ MCD_OPC_Decode, 131, 11, 105, // Opcode: SMLSLv8i8_v8i16 -/* 8544 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 8562 -/* 8548 */ MCD_OPC_CheckPredicate, 0, 89, 125, // Skip to: 40641 -/* 8552 */ MCD_OPC_CheckField, 21, 1, 1, 83, 125, // Skip to: 40641 -/* 8558 */ MCD_OPC_Decode, 210, 10, 89, // Opcode: SMAXPv8i8 -/* 8562 */ MCD_OPC_FilterValue, 42, 51, 0, // Skip to: 8617 -/* 8566 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 8569 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 8581 -/* 8573 */ MCD_OPC_CheckPredicate, 0, 64, 125, // Skip to: 40641 -/* 8577 */ MCD_OPC_Decode, 239, 1, 90, // Opcode: CMLTv8i8rz -/* 8581 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 8593 -/* 8585 */ MCD_OPC_CheckPredicate, 0, 52, 125, // Skip to: 40641 -/* 8589 */ MCD_OPC_Decode, 186, 3, 90, // Opcode: FCVTNSv2f32 -/* 8593 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 8605 -/* 8597 */ MCD_OPC_CheckPredicate, 0, 40, 125, // Skip to: 40641 -/* 8601 */ MCD_OPC_Decode, 215, 10, 110, // Opcode: SMAXVv8i8v -/* 8605 */ MCD_OPC_FilterValue, 49, 32, 125, // Skip to: 40641 -/* 8609 */ MCD_OPC_CheckPredicate, 0, 28, 125, // Skip to: 40641 -/* 8613 */ MCD_OPC_Decode, 233, 10, 110, // Opcode: SMINVv8i8v -/* 8617 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 8635 -/* 8621 */ MCD_OPC_CheckPredicate, 0, 16, 125, // Skip to: 40641 -/* 8625 */ MCD_OPC_CheckField, 21, 1, 1, 10, 125, // Skip to: 40641 -/* 8631 */ MCD_OPC_Decode, 228, 10, 89, // Opcode: SMINPv8i8 -/* 8635 */ MCD_OPC_FilterValue, 46, 37, 0, // Skip to: 8676 -/* 8639 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 8642 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 8653 -/* 8646 */ MCD_OPC_CheckPredicate, 0, 247, 124, // Skip to: 40641 -/* 8650 */ MCD_OPC_Decode, 29, 90, // Opcode: ABSv8i8 -/* 8653 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 8665 -/* 8657 */ MCD_OPC_CheckPredicate, 0, 236, 124, // Skip to: 40641 -/* 8661 */ MCD_OPC_Decode, 168, 3, 90, // Opcode: FCVTMSv2f32 -/* 8665 */ MCD_OPC_FilterValue, 49, 228, 124, // Skip to: 40641 -/* 8669 */ MCD_OPC_CheckPredicate, 0, 224, 124, // Skip to: 40641 -/* 8673 */ MCD_OPC_Decode, 61, 110, // Opcode: ADDVv8i8v -/* 8676 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 8693 -/* 8680 */ MCD_OPC_CheckPredicate, 0, 213, 124, // Skip to: 40641 -/* 8684 */ MCD_OPC_CheckField, 21, 1, 1, 207, 124, // Skip to: 40641 -/* 8690 */ MCD_OPC_Decode, 47, 89, // Opcode: ADDPv8i8 -/* 8693 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 8711 -/* 8697 */ MCD_OPC_CheckPredicate, 0, 196, 124, // Skip to: 40641 -/* 8701 */ MCD_OPC_CheckField, 21, 1, 1, 190, 124, // Skip to: 40641 -/* 8707 */ MCD_OPC_Decode, 148, 11, 85, // Opcode: SMULLv8i8_v8i16 -/* 8711 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 8729 -/* 8715 */ MCD_OPC_CheckPredicate, 0, 178, 124, // Skip to: 40641 -/* 8719 */ MCD_OPC_CheckField, 21, 1, 1, 172, 124, // Skip to: 40641 -/* 8725 */ MCD_OPC_Decode, 171, 4, 89, // Opcode: FMAXNMv2f32 -/* 8729 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 8747 -/* 8733 */ MCD_OPC_CheckPredicate, 0, 160, 124, // Skip to: 40641 -/* 8737 */ MCD_OPC_CheckField, 16, 6, 33, 154, 124, // Skip to: 40641 -/* 8743 */ MCD_OPC_Decode, 142, 3, 90, // Opcode: FCVTASv2f32 -/* 8747 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 8765 -/* 8751 */ MCD_OPC_CheckPredicate, 0, 142, 124, // Skip to: 40641 -/* 8755 */ MCD_OPC_CheckField, 21, 1, 1, 136, 124, // Skip to: 40641 -/* 8761 */ MCD_OPC_Decode, 208, 4, 109, // Opcode: FMLAv2f32 -/* 8765 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 8783 -/* 8769 */ MCD_OPC_CheckPredicate, 0, 124, 124, // Skip to: 40641 -/* 8773 */ MCD_OPC_CheckField, 21, 1, 1, 118, 124, // Skip to: 40641 -/* 8779 */ MCD_OPC_Decode, 207, 2, 89, // Opcode: FADDv2f32 -/* 8783 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 8801 -/* 8787 */ MCD_OPC_CheckPredicate, 0, 106, 124, // Skip to: 40641 -/* 8791 */ MCD_OPC_CheckField, 16, 6, 33, 100, 124, // Skip to: 40641 -/* 8797 */ MCD_OPC_Decode, 144, 10, 90, // Opcode: SCVTFv2f32 -/* 8801 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 8819 -/* 8805 */ MCD_OPC_CheckPredicate, 0, 88, 124, // Skip to: 40641 -/* 8809 */ MCD_OPC_CheckField, 21, 1, 1, 82, 124, // Skip to: 40641 -/* 8815 */ MCD_OPC_Decode, 243, 4, 89, // Opcode: FMULXv2f32 -/* 8819 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 8837 -/* 8823 */ MCD_OPC_CheckPredicate, 0, 70, 124, // Skip to: 40641 -/* 8827 */ MCD_OPC_CheckField, 21, 1, 1, 64, 124, // Skip to: 40641 -/* 8833 */ MCD_OPC_Decode, 150, 9, 85, // Opcode: PMULLv8i8 -/* 8837 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 8855 -/* 8841 */ MCD_OPC_CheckPredicate, 0, 52, 124, // Skip to: 40641 -/* 8845 */ MCD_OPC_CheckField, 21, 1, 1, 46, 124, // Skip to: 40641 -/* 8851 */ MCD_OPC_Decode, 218, 2, 89, // Opcode: FCMEQv2f32 -/* 8855 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 8873 -/* 8859 */ MCD_OPC_CheckPredicate, 0, 34, 124, // Skip to: 40641 -/* 8863 */ MCD_OPC_CheckField, 21, 1, 1, 28, 124, // Skip to: 40641 -/* 8869 */ MCD_OPC_Decode, 181, 4, 89, // Opcode: FMAXv2f32 -/* 8873 */ MCD_OPC_FilterValue, 63, 20, 124, // Skip to: 40641 -/* 8877 */ MCD_OPC_CheckPredicate, 0, 16, 124, // Skip to: 40641 -/* 8881 */ MCD_OPC_CheckField, 21, 1, 1, 10, 124, // Skip to: 40641 -/* 8887 */ MCD_OPC_Decode, 147, 5, 89, // Opcode: FRECPSv2f32 -/* 8891 */ MCD_OPC_FilterValue, 1, 85, 4, // Skip to: 10004 -/* 8895 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... -/* 8898 */ MCD_OPC_FilterValue, 0, 64, 1, // Skip to: 9222 -/* 8902 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 8905 */ MCD_OPC_FilterValue, 0, 162, 0, // Skip to: 9071 -/* 8909 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 8912 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8924 -/* 8916 */ MCD_OPC_CheckPredicate, 0, 233, 123, // Skip to: 40641 -/* 8920 */ MCD_OPC_Decode, 178, 2, 111, // Opcode: EXTv8i8 -/* 8924 */ MCD_OPC_FilterValue, 1, 225, 123, // Skip to: 40641 -/* 8928 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 8931 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 8943 -/* 8935 */ MCD_OPC_CheckPredicate, 0, 214, 123, // Skip to: 40641 -/* 8939 */ MCD_OPC_Decode, 153, 16, 85, // Opcode: UADDLv8i8_v8i16 -/* 8943 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 8961 -/* 8947 */ MCD_OPC_CheckPredicate, 0, 202, 123, // Skip to: 40641 -/* 8951 */ MCD_OPC_CheckField, 16, 5, 0, 196, 123, // Skip to: 40641 -/* 8957 */ MCD_OPC_Decode, 178, 9, 90, // Opcode: REV32v8i8 -/* 8961 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 8973 -/* 8965 */ MCD_OPC_CheckPredicate, 0, 184, 123, // Skip to: 40641 -/* 8969 */ MCD_OPC_Decode, 159, 16, 93, // Opcode: UADDWv8i8_v8i16 -/* 8973 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 8985 -/* 8977 */ MCD_OPC_CheckPredicate, 0, 172, 123, // Skip to: 40641 -/* 8981 */ MCD_OPC_Decode, 173, 18, 85, // Opcode: USUBLv8i8_v8i16 -/* 8985 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 9016 -/* 8989 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 8992 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9004 -/* 8996 */ MCD_OPC_CheckPredicate, 0, 153, 123, // Skip to: 40641 -/* 9000 */ MCD_OPC_Decode, 142, 16, 90, // Opcode: UADDLPv8i8_v4i16 -/* 9004 */ MCD_OPC_FilterValue, 1, 145, 123, // Skip to: 40641 -/* 9008 */ MCD_OPC_CheckPredicate, 0, 141, 123, // Skip to: 40641 -/* 9012 */ MCD_OPC_Decode, 222, 12, 95, // Opcode: SQXTUNv8i8 -/* 9016 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 9028 -/* 9020 */ MCD_OPC_CheckPredicate, 0, 129, 123, // Skip to: 40641 -/* 9024 */ MCD_OPC_Decode, 179, 18, 93, // Opcode: USUBWv8i8_v8i16 -/* 9028 */ MCD_OPC_FilterValue, 7, 121, 123, // Skip to: 40641 -/* 9032 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 9035 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 9047 -/* 9039 */ MCD_OPC_CheckPredicate, 0, 110, 123, // Skip to: 40641 -/* 9043 */ MCD_OPC_Decode, 159, 18, 99, // Opcode: USQADDv8i8 -/* 9047 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 9059 -/* 9051 */ MCD_OPC_CheckPredicate, 0, 98, 123, // Skip to: 40641 -/* 9055 */ MCD_OPC_Decode, 175, 10, 108, // Opcode: SHLLv8i8 -/* 9059 */ MCD_OPC_FilterValue, 16, 90, 123, // Skip to: 40641 -/* 9063 */ MCD_OPC_CheckPredicate, 0, 86, 123, // Skip to: 40641 -/* 9067 */ MCD_OPC_Decode, 147, 16, 100, // Opcode: UADDLVv8i8v -/* 9071 */ MCD_OPC_FilterValue, 1, 78, 123, // Skip to: 40641 -/* 9075 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... -/* 9078 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9096 -/* 9082 */ MCD_OPC_CheckPredicate, 0, 67, 123, // Skip to: 40641 -/* 9086 */ MCD_OPC_CheckField, 21, 1, 1, 61, 123, // Skip to: 40641 -/* 9092 */ MCD_OPC_Decode, 189, 16, 89, // Opcode: UHADDv8i8 -/* 9096 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9114 -/* 9100 */ MCD_OPC_CheckPredicate, 0, 49, 123, // Skip to: 40641 -/* 9104 */ MCD_OPC_CheckField, 21, 1, 1, 43, 123, // Skip to: 40641 -/* 9110 */ MCD_OPC_Decode, 149, 17, 89, // Opcode: UQADDv8i8 -/* 9114 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9132 -/* 9118 */ MCD_OPC_CheckPredicate, 0, 31, 123, // Skip to: 40641 -/* 9122 */ MCD_OPC_CheckField, 21, 1, 1, 25, 123, // Skip to: 40641 -/* 9128 */ MCD_OPC_Decode, 228, 17, 89, // Opcode: URHADDv8i8 -/* 9132 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9150 -/* 9136 */ MCD_OPC_CheckPredicate, 0, 13, 123, // Skip to: 40641 -/* 9140 */ MCD_OPC_CheckField, 21, 1, 1, 7, 123, // Skip to: 40641 -/* 9146 */ MCD_OPC_Decode, 173, 2, 89, // Opcode: EORv8i8 -/* 9150 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 9168 -/* 9154 */ MCD_OPC_CheckPredicate, 0, 251, 122, // Skip to: 40641 -/* 9158 */ MCD_OPC_CheckField, 21, 1, 1, 245, 122, // Skip to: 40641 -/* 9164 */ MCD_OPC_Decode, 195, 16, 89, // Opcode: UHSUBv8i8 -/* 9168 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9186 -/* 9172 */ MCD_OPC_CheckPredicate, 0, 233, 122, // Skip to: 40641 -/* 9176 */ MCD_OPC_CheckField, 21, 1, 1, 227, 122, // Skip to: 40641 -/* 9182 */ MCD_OPC_Decode, 211, 17, 89, // Opcode: UQSUBv8i8 -/* 9186 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9204 -/* 9190 */ MCD_OPC_CheckPredicate, 0, 215, 122, // Skip to: 40641 -/* 9194 */ MCD_OPC_CheckField, 21, 1, 1, 209, 122, // Skip to: 40641 -/* 9200 */ MCD_OPC_Decode, 215, 1, 89, // Opcode: CMHIv8i8 -/* 9204 */ MCD_OPC_FilterValue, 7, 201, 122, // Skip to: 40641 -/* 9208 */ MCD_OPC_CheckPredicate, 0, 197, 122, // Skip to: 40641 -/* 9212 */ MCD_OPC_CheckField, 21, 1, 1, 191, 122, // Skip to: 40641 -/* 9218 */ MCD_OPC_Decode, 223, 1, 89, // Opcode: CMHSv8i8 -/* 9222 */ MCD_OPC_FilterValue, 1, 48, 1, // Skip to: 9530 -/* 9226 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 9229 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9247 -/* 9233 */ MCD_OPC_CheckPredicate, 0, 172, 122, // Skip to: 40641 -/* 9237 */ MCD_OPC_CheckField, 21, 1, 1, 166, 122, // Skip to: 40641 -/* 9243 */ MCD_OPC_Decode, 163, 9, 103, // Opcode: RADDHNv8i16_v8i8 -/* 9247 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9265 -/* 9251 */ MCD_OPC_CheckPredicate, 0, 154, 122, // Skip to: 40641 -/* 9255 */ MCD_OPC_CheckField, 21, 1, 1, 148, 122, // Skip to: 40641 -/* 9261 */ MCD_OPC_Decode, 140, 18, 89, // Opcode: USHLv8i8 -/* 9265 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 9296 -/* 9269 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 9272 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9284 -/* 9276 */ MCD_OPC_CheckPredicate, 0, 129, 122, // Skip to: 40641 -/* 9280 */ MCD_OPC_Decode, 159, 1, 90, // Opcode: CLZv8i8 -/* 9284 */ MCD_OPC_FilterValue, 33, 121, 122, // Skip to: 40641 -/* 9288 */ MCD_OPC_CheckPredicate, 0, 117, 122, // Skip to: 40641 -/* 9292 */ MCD_OPC_Decode, 220, 17, 95, // Opcode: UQXTNv8i8 -/* 9296 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9314 -/* 9300 */ MCD_OPC_CheckPredicate, 0, 105, 122, // Skip to: 40641 -/* 9304 */ MCD_OPC_CheckField, 21, 1, 1, 99, 122, // Skip to: 40641 -/* 9310 */ MCD_OPC_Decode, 190, 17, 89, // Opcode: UQSHLv8i8 -/* 9314 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 9332 -/* 9318 */ MCD_OPC_CheckPredicate, 0, 87, 122, // Skip to: 40641 -/* 9322 */ MCD_OPC_CheckField, 21, 1, 1, 81, 122, // Skip to: 40641 -/* 9328 */ MCD_OPC_Decode, 240, 15, 105, // Opcode: UABALv8i8_v8i16 -/* 9332 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9350 -/* 9336 */ MCD_OPC_CheckPredicate, 0, 69, 122, // Skip to: 40641 -/* 9340 */ MCD_OPC_CheckField, 21, 1, 1, 63, 122, // Skip to: 40641 -/* 9346 */ MCD_OPC_Decode, 236, 17, 89, // Opcode: URSHLv8i8 -/* 9350 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9368 -/* 9354 */ MCD_OPC_CheckPredicate, 0, 51, 122, // Skip to: 40641 -/* 9358 */ MCD_OPC_CheckField, 16, 6, 32, 45, 122, // Skip to: 40641 -/* 9364 */ MCD_OPC_Decode, 128, 9, 90, // Opcode: NOTv8i8 -/* 9368 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9386 -/* 9372 */ MCD_OPC_CheckPredicate, 0, 33, 122, // Skip to: 40641 -/* 9376 */ MCD_OPC_CheckField, 21, 1, 1, 27, 122, // Skip to: 40641 -/* 9382 */ MCD_OPC_Decode, 160, 17, 89, // Opcode: UQRSHLv8i8 -/* 9386 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 9404 -/* 9390 */ MCD_OPC_CheckPredicate, 0, 15, 122, // Skip to: 40641 -/* 9394 */ MCD_OPC_CheckField, 21, 1, 1, 9, 122, // Skip to: 40641 -/* 9400 */ MCD_OPC_Decode, 200, 9, 103, // Opcode: RSUBHNv8i16_v8i8 -/* 9404 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9422 -/* 9408 */ MCD_OPC_CheckPredicate, 0, 253, 121, // Skip to: 40641 -/* 9412 */ MCD_OPC_CheckField, 21, 1, 1, 247, 121, // Skip to: 40641 -/* 9418 */ MCD_OPC_Decode, 213, 16, 89, // Opcode: UMAXv8i8 -/* 9422 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 9440 -/* 9426 */ MCD_OPC_CheckPredicate, 0, 235, 121, // Skip to: 40641 -/* 9430 */ MCD_OPC_CheckField, 16, 6, 32, 229, 121, // Skip to: 40641 -/* 9436 */ MCD_OPC_Decode, 136, 16, 99, // Opcode: UADALPv8i8_v4i16 -/* 9440 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9458 -/* 9444 */ MCD_OPC_CheckPredicate, 0, 217, 121, // Skip to: 40641 -/* 9448 */ MCD_OPC_CheckField, 21, 1, 1, 211, 121, // Skip to: 40641 -/* 9454 */ MCD_OPC_Decode, 230, 16, 89, // Opcode: UMINv8i8 -/* 9458 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 9476 -/* 9462 */ MCD_OPC_CheckPredicate, 0, 199, 121, // Skip to: 40641 -/* 9466 */ MCD_OPC_CheckField, 21, 1, 1, 193, 121, // Skip to: 40641 -/* 9472 */ MCD_OPC_Decode, 252, 15, 85, // Opcode: UABDLv8i8_v8i16 -/* 9476 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 9494 -/* 9480 */ MCD_OPC_CheckPredicate, 0, 181, 121, // Skip to: 40641 -/* 9484 */ MCD_OPC_CheckField, 21, 1, 1, 175, 121, // Skip to: 40641 -/* 9490 */ MCD_OPC_Decode, 130, 16, 89, // Opcode: UABDv8i8 -/* 9494 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 9512 -/* 9498 */ MCD_OPC_CheckPredicate, 0, 163, 121, // Skip to: 40641 -/* 9502 */ MCD_OPC_CheckField, 16, 6, 32, 157, 121, // Skip to: 40641 -/* 9508 */ MCD_OPC_Decode, 229, 11, 90, // Opcode: SQNEGv8i8 -/* 9512 */ MCD_OPC_FilterValue, 15, 149, 121, // Skip to: 40641 -/* 9516 */ MCD_OPC_CheckPredicate, 0, 145, 121, // Skip to: 40641 -/* 9520 */ MCD_OPC_CheckField, 21, 1, 1, 139, 121, // Skip to: 40641 -/* 9526 */ MCD_OPC_Decode, 246, 15, 109, // Opcode: UABAv8i8 -/* 9530 */ MCD_OPC_FilterValue, 2, 27, 1, // Skip to: 9817 -/* 9534 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 9537 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9555 -/* 9541 */ MCD_OPC_CheckPredicate, 0, 120, 121, // Skip to: 40641 -/* 9545 */ MCD_OPC_CheckField, 21, 1, 1, 114, 121, // Skip to: 40641 -/* 9551 */ MCD_OPC_Decode, 240, 16, 105, // Opcode: UMLALv8i8_v8i16 -/* 9555 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9573 -/* 9559 */ MCD_OPC_CheckPredicate, 0, 102, 121, // Skip to: 40641 -/* 9563 */ MCD_OPC_CheckField, 21, 1, 1, 96, 121, // Skip to: 40641 -/* 9569 */ MCD_OPC_Decode, 182, 15, 89, // Opcode: SUBv8i8 -/* 9573 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 9604 -/* 9577 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 9580 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9592 -/* 9584 */ MCD_OPC_CheckPredicate, 0, 77, 121, // Skip to: 40641 -/* 9588 */ MCD_OPC_Decode, 191, 1, 90, // Opcode: CMGEv8i8rz -/* 9592 */ MCD_OPC_FilterValue, 33, 69, 121, // Skip to: 40641 -/* 9596 */ MCD_OPC_CheckPredicate, 0, 65, 121, // Skip to: 40641 -/* 9600 */ MCD_OPC_Decode, 154, 5, 90, // Opcode: FRINTAv2f32 -/* 9604 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 9622 -/* 9608 */ MCD_OPC_CheckPredicate, 0, 53, 121, // Skip to: 40641 -/* 9612 */ MCD_OPC_CheckField, 21, 1, 1, 47, 121, // Skip to: 40641 -/* 9618 */ MCD_OPC_Decode, 174, 1, 89, // Opcode: CMEQv8i8 -/* 9622 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9640 -/* 9626 */ MCD_OPC_CheckPredicate, 0, 35, 121, // Skip to: 40641 -/* 9630 */ MCD_OPC_CheckField, 21, 1, 1, 29, 121, // Skip to: 40641 -/* 9636 */ MCD_OPC_Decode, 201, 8, 109, // Opcode: MLSv8i8 -/* 9640 */ MCD_OPC_FilterValue, 6, 27, 0, // Skip to: 9671 -/* 9644 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 9647 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9659 -/* 9651 */ MCD_OPC_CheckPredicate, 0, 10, 121, // Skip to: 40641 -/* 9655 */ MCD_OPC_Decode, 231, 1, 90, // Opcode: CMLEv8i8rz -/* 9659 */ MCD_OPC_FilterValue, 33, 2, 121, // Skip to: 40641 -/* 9663 */ MCD_OPC_CheckPredicate, 0, 254, 120, // Skip to: 40641 -/* 9667 */ MCD_OPC_Decode, 179, 5, 90, // Opcode: FRINTXv2f32 -/* 9671 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9689 -/* 9675 */ MCD_OPC_CheckPredicate, 0, 242, 120, // Skip to: 40641 -/* 9679 */ MCD_OPC_CheckField, 21, 1, 1, 236, 120, // Skip to: 40641 -/* 9685 */ MCD_OPC_Decode, 152, 9, 89, // Opcode: PMULv8i8 -/* 9689 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 9707 -/* 9693 */ MCD_OPC_CheckPredicate, 0, 224, 120, // Skip to: 40641 -/* 9697 */ MCD_OPC_CheckField, 21, 1, 1, 218, 120, // Skip to: 40641 -/* 9703 */ MCD_OPC_Decode, 250, 16, 105, // Opcode: UMLSLv8i8_v8i16 -/* 9707 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9725 -/* 9711 */ MCD_OPC_CheckPredicate, 0, 206, 120, // Skip to: 40641 -/* 9715 */ MCD_OPC_CheckField, 21, 1, 1, 200, 120, // Skip to: 40641 -/* 9721 */ MCD_OPC_Decode, 202, 16, 89, // Opcode: UMAXPv8i8 -/* 9725 */ MCD_OPC_FilterValue, 10, 39, 0, // Skip to: 9768 -/* 9729 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 9732 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 9744 -/* 9736 */ MCD_OPC_CheckPredicate, 0, 181, 120, // Skip to: 40641 -/* 9740 */ MCD_OPC_Decode, 195, 3, 90, // Opcode: FCVTNUv2f32 -/* 9744 */ MCD_OPC_FilterValue, 48, 8, 0, // Skip to: 9756 -/* 9748 */ MCD_OPC_CheckPredicate, 0, 169, 120, // Skip to: 40641 -/* 9752 */ MCD_OPC_Decode, 207, 16, 110, // Opcode: UMAXVv8i8v -/* 9756 */ MCD_OPC_FilterValue, 49, 161, 120, // Skip to: 40641 -/* 9760 */ MCD_OPC_CheckPredicate, 0, 157, 120, // Skip to: 40641 -/* 9764 */ MCD_OPC_Decode, 224, 16, 110, // Opcode: UMINVv8i8v -/* 9768 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9786 -/* 9772 */ MCD_OPC_CheckPredicate, 0, 145, 120, // Skip to: 40641 -/* 9776 */ MCD_OPC_CheckField, 21, 1, 1, 139, 120, // Skip to: 40641 -/* 9782 */ MCD_OPC_Decode, 219, 16, 89, // Opcode: UMINPv8i8 -/* 9786 */ MCD_OPC_FilterValue, 14, 131, 120, // Skip to: 40641 -/* 9790 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 9793 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 9805 -/* 9797 */ MCD_OPC_CheckPredicate, 0, 120, 120, // Skip to: 40641 -/* 9801 */ MCD_OPC_Decode, 254, 8, 90, // Opcode: NEGv8i8 -/* 9805 */ MCD_OPC_FilterValue, 33, 112, 120, // Skip to: 40641 -/* 9809 */ MCD_OPC_CheckPredicate, 0, 108, 120, // Skip to: 40641 -/* 9813 */ MCD_OPC_Decode, 177, 3, 90, // Opcode: FCVTMUv2f32 -/* 9817 */ MCD_OPC_FilterValue, 3, 100, 120, // Skip to: 40641 -/* 9821 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... -/* 9824 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 9842 -/* 9828 */ MCD_OPC_CheckPredicate, 0, 89, 120, // Skip to: 40641 -/* 9832 */ MCD_OPC_CheckField, 21, 1, 1, 83, 120, // Skip to: 40641 -/* 9838 */ MCD_OPC_Decode, 138, 17, 85, // Opcode: UMULLv8i8_v8i16 -/* 9842 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 9860 -/* 9846 */ MCD_OPC_CheckPredicate, 0, 71, 120, // Skip to: 40641 -/* 9850 */ MCD_OPC_CheckField, 21, 1, 1, 65, 120, // Skip to: 40641 -/* 9856 */ MCD_OPC_Decode, 164, 4, 89, // Opcode: FMAXNMPv2f32 -/* 9860 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 9878 -/* 9864 */ MCD_OPC_CheckPredicate, 0, 53, 120, // Skip to: 40641 -/* 9868 */ MCD_OPC_CheckField, 16, 6, 33, 47, 120, // Skip to: 40641 -/* 9874 */ MCD_OPC_Decode, 151, 3, 90, // Opcode: FCVTAUv2f32 -/* 9878 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 9896 -/* 9882 */ MCD_OPC_CheckPredicate, 0, 35, 120, // Skip to: 40641 -/* 9886 */ MCD_OPC_CheckField, 21, 1, 1, 29, 120, // Skip to: 40641 -/* 9892 */ MCD_OPC_Decode, 201, 2, 89, // Opcode: FADDPv2f32 -/* 9896 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 9914 -/* 9900 */ MCD_OPC_CheckPredicate, 0, 17, 120, // Skip to: 40641 -/* 9904 */ MCD_OPC_CheckField, 16, 6, 33, 11, 120, // Skip to: 40641 -/* 9910 */ MCD_OPC_Decode, 174, 16, 90, // Opcode: UCVTFv2f32 -/* 9914 */ MCD_OPC_FilterValue, 7, 14, 0, // Skip to: 9932 -/* 9918 */ MCD_OPC_CheckPredicate, 0, 255, 119, // Skip to: 40641 -/* 9922 */ MCD_OPC_CheckField, 21, 1, 1, 249, 119, // Skip to: 40641 -/* 9928 */ MCD_OPC_Decode, 251, 4, 89, // Opcode: FMULv2f32 -/* 9932 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 9950 -/* 9936 */ MCD_OPC_CheckPredicate, 0, 237, 119, // Skip to: 40641 -/* 9940 */ MCD_OPC_CheckField, 21, 1, 1, 231, 119, // Skip to: 40641 -/* 9946 */ MCD_OPC_Decode, 228, 2, 89, // Opcode: FCMGEv2f32 -/* 9950 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 9968 -/* 9954 */ MCD_OPC_CheckPredicate, 0, 219, 119, // Skip to: 40641 -/* 9958 */ MCD_OPC_CheckField, 21, 1, 1, 213, 119, // Skip to: 40641 -/* 9964 */ MCD_OPC_Decode, 192, 2, 89, // Opcode: FACGEv2f32 -/* 9968 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 9986 -/* 9972 */ MCD_OPC_CheckPredicate, 0, 201, 119, // Skip to: 40641 -/* 9976 */ MCD_OPC_CheckField, 21, 1, 1, 195, 119, // Skip to: 40641 -/* 9982 */ MCD_OPC_Decode, 174, 4, 89, // Opcode: FMAXPv2f32 -/* 9986 */ MCD_OPC_FilterValue, 15, 187, 119, // Skip to: 40641 -/* 9990 */ MCD_OPC_CheckPredicate, 0, 183, 119, // Skip to: 40641 -/* 9994 */ MCD_OPC_CheckField, 21, 1, 1, 177, 119, // Skip to: 40641 -/* 10000 */ MCD_OPC_Decode, 157, 4, 89, // Opcode: FDIVv2f32 -/* 10004 */ MCD_OPC_FilterValue, 2, 181, 6, // Skip to: 11725 -/* 10008 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 10011 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 10042 -/* 10015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10018 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10030 -/* 10022 */ MCD_OPC_CheckPredicate, 0, 151, 119, // Skip to: 40641 -/* 10026 */ MCD_OPC_Decode, 198, 15, 112, // Opcode: TBLv16i8One -/* 10030 */ MCD_OPC_FilterValue, 1, 143, 119, // Skip to: 40641 -/* 10034 */ MCD_OPC_CheckPredicate, 0, 139, 119, // Skip to: 40641 -/* 10038 */ MCD_OPC_Decode, 242, 9, 112, // Opcode: SADDLv16i8_v8i16 -/* 10042 */ MCD_OPC_FilterValue, 1, 90, 0, // Skip to: 10136 -/* 10046 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10049 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 10124 -/* 10053 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 10056 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 10112 -/* 10060 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 10063 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 10100 -/* 10067 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 10070 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10088 -/* 10074 */ MCD_OPC_CheckPredicate, 0, 99, 119, // Skip to: 40641 -/* 10078 */ MCD_OPC_CheckField, 19, 1, 1, 93, 119, // Skip to: 40641 -/* 10084 */ MCD_OPC_Decode, 153, 2, 113, // Opcode: DUPv2i64lane -/* 10088 */ MCD_OPC_FilterValue, 1, 85, 119, // Skip to: 40641 -/* 10092 */ MCD_OPC_CheckPredicate, 0, 81, 119, // Skip to: 40641 -/* 10096 */ MCD_OPC_Decode, 157, 2, 114, // Opcode: DUPv4i32lane -/* 10100 */ MCD_OPC_FilterValue, 1, 73, 119, // Skip to: 40641 -/* 10104 */ MCD_OPC_CheckPredicate, 0, 69, 119, // Skip to: 40641 -/* 10108 */ MCD_OPC_Decode, 159, 2, 115, // Opcode: DUPv8i16lane -/* 10112 */ MCD_OPC_FilterValue, 1, 61, 119, // Skip to: 40641 -/* 10116 */ MCD_OPC_CheckPredicate, 0, 57, 119, // Skip to: 40641 -/* 10120 */ MCD_OPC_Decode, 149, 2, 116, // Opcode: DUPv16i8lane -/* 10124 */ MCD_OPC_FilterValue, 1, 49, 119, // Skip to: 40641 -/* 10128 */ MCD_OPC_CheckPredicate, 0, 45, 119, // Skip to: 40641 -/* 10132 */ MCD_OPC_Decode, 164, 10, 112, // Opcode: SHADDv16i8 -/* 10136 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 10154 -/* 10140 */ MCD_OPC_CheckPredicate, 0, 33, 119, // Skip to: 40641 -/* 10144 */ MCD_OPC_CheckField, 16, 6, 32, 27, 119, // Skip to: 40641 -/* 10150 */ MCD_OPC_Decode, 179, 9, 117, // Opcode: REV64v16i8 -/* 10154 */ MCD_OPC_FilterValue, 3, 70, 0, // Skip to: 10228 -/* 10158 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10161 */ MCD_OPC_FilterValue, 0, 51, 0, // Skip to: 10216 -/* 10165 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10168 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 10180 -/* 10172 */ MCD_OPC_CheckPredicate, 0, 1, 119, // Skip to: 40641 -/* 10176 */ MCD_OPC_Decode, 148, 2, 118, // Opcode: DUPv16i8gpr -/* 10180 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 10192 -/* 10184 */ MCD_OPC_CheckPredicate, 0, 245, 118, // Skip to: 40641 -/* 10188 */ MCD_OPC_Decode, 158, 2, 118, // Opcode: DUPv8i16gpr -/* 10192 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 10204 -/* 10196 */ MCD_OPC_CheckPredicate, 0, 233, 118, // Skip to: 40641 -/* 10200 */ MCD_OPC_Decode, 156, 2, 118, // Opcode: DUPv4i32gpr -/* 10204 */ MCD_OPC_FilterValue, 8, 225, 118, // Skip to: 40641 -/* 10208 */ MCD_OPC_CheckPredicate, 0, 221, 118, // Skip to: 40641 -/* 10212 */ MCD_OPC_Decode, 152, 2, 119, // Opcode: DUPv2i64gpr -/* 10216 */ MCD_OPC_FilterValue, 1, 213, 118, // Skip to: 40641 -/* 10220 */ MCD_OPC_CheckPredicate, 0, 209, 118, // Skip to: 40641 -/* 10224 */ MCD_OPC_Decode, 160, 11, 112, // Opcode: SQADDv16i8 -/* 10228 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 10259 -/* 10232 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10235 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10247 -/* 10239 */ MCD_OPC_CheckPredicate, 0, 190, 118, // Skip to: 40641 -/* 10243 */ MCD_OPC_Decode, 208, 15, 120, // Opcode: TBXv16i8One -/* 10247 */ MCD_OPC_FilterValue, 1, 182, 118, // Skip to: 40641 -/* 10251 */ MCD_OPC_CheckPredicate, 0, 178, 118, // Skip to: 40641 -/* 10255 */ MCD_OPC_Decode, 248, 9, 112, // Opcode: SADDWv16i8_v8i16 -/* 10259 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 10277 -/* 10263 */ MCD_OPC_CheckPredicate, 0, 166, 118, // Skip to: 40641 -/* 10267 */ MCD_OPC_CheckField, 21, 1, 1, 160, 118, // Skip to: 40641 -/* 10273 */ MCD_OPC_Decode, 223, 12, 112, // Opcode: SRHADDv16i8 -/* 10277 */ MCD_OPC_FilterValue, 6, 33, 0, // Skip to: 10314 -/* 10281 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10284 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10296 -/* 10288 */ MCD_OPC_CheckPredicate, 0, 141, 118, // Skip to: 40641 -/* 10292 */ MCD_OPC_Decode, 180, 18, 112, // Opcode: UZP1v16i8 -/* 10296 */ MCD_OPC_FilterValue, 1, 133, 118, // Skip to: 40641 -/* 10300 */ MCD_OPC_CheckPredicate, 0, 129, 118, // Skip to: 40641 -/* 10304 */ MCD_OPC_CheckField, 16, 5, 0, 123, 118, // Skip to: 40641 -/* 10310 */ MCD_OPC_Decode, 172, 9, 117, // Opcode: REV16v16i8 -/* 10314 */ MCD_OPC_FilterValue, 7, 89, 0, // Skip to: 10407 -/* 10318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10321 */ MCD_OPC_FilterValue, 0, 71, 0, // Skip to: 10396 -/* 10325 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 10328 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 10384 -/* 10332 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 10335 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 10372 -/* 10339 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 10342 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10360 -/* 10346 */ MCD_OPC_CheckPredicate, 0, 83, 118, // Skip to: 40641 -/* 10350 */ MCD_OPC_CheckField, 19, 1, 1, 77, 118, // Skip to: 40641 -/* 10356 */ MCD_OPC_Decode, 214, 5, 121, // Opcode: INSvi64gpr -/* 10360 */ MCD_OPC_FilterValue, 1, 69, 118, // Skip to: 40641 -/* 10364 */ MCD_OPC_CheckPredicate, 0, 65, 118, // Skip to: 40641 -/* 10368 */ MCD_OPC_Decode, 212, 5, 122, // Opcode: INSvi32gpr -/* 10372 */ MCD_OPC_FilterValue, 1, 57, 118, // Skip to: 40641 -/* 10376 */ MCD_OPC_CheckPredicate, 0, 53, 118, // Skip to: 40641 -/* 10380 */ MCD_OPC_Decode, 210, 5, 123, // Opcode: INSvi16gpr -/* 10384 */ MCD_OPC_FilterValue, 1, 45, 118, // Skip to: 40641 -/* 10388 */ MCD_OPC_CheckPredicate, 0, 41, 118, // Skip to: 40641 -/* 10392 */ MCD_OPC_Decode, 216, 5, 124, // Opcode: INSvi8gpr -/* 10396 */ MCD_OPC_FilterValue, 1, 33, 118, // Skip to: 40641 -/* 10400 */ MCD_OPC_CheckPredicate, 0, 29, 118, // Skip to: 40641 -/* 10404 */ MCD_OPC_Decode, 99, 112, // Opcode: ANDv16i8 -/* 10407 */ MCD_OPC_FilterValue, 8, 27, 0, // Skip to: 10438 -/* 10411 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10414 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10426 -/* 10418 */ MCD_OPC_CheckPredicate, 0, 11, 118, // Skip to: 40641 -/* 10422 */ MCD_OPC_Decode, 200, 15, 125, // Opcode: TBLv16i8Two -/* 10426 */ MCD_OPC_FilterValue, 1, 3, 118, // Skip to: 40641 -/* 10430 */ MCD_OPC_CheckPredicate, 0, 255, 117, // Skip to: 40641 -/* 10434 */ MCD_OPC_Decode, 163, 13, 112, // Opcode: SSUBLv16i8_v8i16 -/* 10438 */ MCD_OPC_FilterValue, 9, 14, 0, // Skip to: 10456 -/* 10442 */ MCD_OPC_CheckPredicate, 0, 243, 117, // Skip to: 40641 -/* 10446 */ MCD_OPC_CheckField, 21, 1, 1, 237, 117, // Skip to: 40641 -/* 10452 */ MCD_OPC_Decode, 190, 10, 112, // Opcode: SHSUBv16i8 -/* 10456 */ MCD_OPC_FilterValue, 10, 46, 0, // Skip to: 10506 -/* 10460 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10463 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10475 -/* 10467 */ MCD_OPC_CheckPredicate, 0, 218, 117, // Skip to: 40641 -/* 10471 */ MCD_OPC_Decode, 221, 15, 112, // Opcode: TRN1v16i8 -/* 10475 */ MCD_OPC_FilterValue, 1, 210, 117, // Skip to: 40641 -/* 10479 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10482 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10494 -/* 10486 */ MCD_OPC_CheckPredicate, 0, 199, 117, // Skip to: 40641 -/* 10490 */ MCD_OPC_Decode, 231, 9, 117, // Opcode: SADDLPv16i8_v8i16 -/* 10494 */ MCD_OPC_FilterValue, 1, 191, 117, // Skip to: 40641 -/* 10498 */ MCD_OPC_CheckPredicate, 0, 187, 117, // Skip to: 40641 -/* 10502 */ MCD_OPC_Decode, 194, 18, 126, // Opcode: XTNv16i8 -/* 10506 */ MCD_OPC_FilterValue, 11, 73, 0, // Skip to: 10583 -/* 10510 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10513 */ MCD_OPC_FilterValue, 0, 54, 0, // Skip to: 10571 -/* 10517 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 10520 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 10558 -/* 10524 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 10527 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 10545 -/* 10531 */ MCD_OPC_CheckPredicate, 0, 154, 117, // Skip to: 40641 -/* 10535 */ MCD_OPC_CheckField, 18, 1, 1, 148, 117, // Skip to: 40641 -/* 10541 */ MCD_OPC_Decode, 134, 11, 127, // Opcode: SMOVvi32to64 -/* 10545 */ MCD_OPC_FilterValue, 1, 140, 117, // Skip to: 40641 -/* 10549 */ MCD_OPC_CheckPredicate, 0, 136, 117, // Skip to: 40641 -/* 10553 */ MCD_OPC_Decode, 133, 11, 128, 1, // Opcode: SMOVvi16to64 -/* 10558 */ MCD_OPC_FilterValue, 1, 127, 117, // Skip to: 40641 -/* 10562 */ MCD_OPC_CheckPredicate, 0, 123, 117, // Skip to: 40641 -/* 10566 */ MCD_OPC_Decode, 136, 11, 129, 1, // Opcode: SMOVvi8to64 -/* 10571 */ MCD_OPC_FilterValue, 1, 114, 117, // Skip to: 40641 -/* 10575 */ MCD_OPC_CheckPredicate, 0, 110, 117, // Skip to: 40641 -/* 10579 */ MCD_OPC_Decode, 194, 12, 112, // Opcode: SQSUBv16i8 -/* 10583 */ MCD_OPC_FilterValue, 12, 28, 0, // Skip to: 10615 -/* 10587 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10590 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10603 -/* 10594 */ MCD_OPC_CheckPredicate, 0, 91, 117, // Skip to: 40641 -/* 10598 */ MCD_OPC_Decode, 210, 15, 130, 1, // Opcode: TBXv16i8Two -/* 10603 */ MCD_OPC_FilterValue, 1, 82, 117, // Skip to: 40641 -/* 10607 */ MCD_OPC_CheckPredicate, 0, 78, 117, // Skip to: 40641 -/* 10611 */ MCD_OPC_Decode, 169, 13, 112, // Opcode: SSUBWv16i8_v8i16 -/* 10615 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 10633 -/* 10619 */ MCD_OPC_CheckPredicate, 0, 66, 117, // Skip to: 40641 -/* 10623 */ MCD_OPC_CheckField, 21, 1, 1, 60, 117, // Skip to: 40641 -/* 10629 */ MCD_OPC_Decode, 192, 1, 112, // Opcode: CMGTv16i8 -/* 10633 */ MCD_OPC_FilterValue, 14, 47, 0, // Skip to: 10684 -/* 10637 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10640 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10652 -/* 10644 */ MCD_OPC_CheckPredicate, 0, 41, 117, // Skip to: 40641 -/* 10648 */ MCD_OPC_Decode, 200, 18, 112, // Opcode: ZIP1v16i8 -/* 10652 */ MCD_OPC_FilterValue, 1, 33, 117, // Skip to: 40641 -/* 10656 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10659 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10671 -/* 10663 */ MCD_OPC_CheckPredicate, 0, 22, 117, // Skip to: 40641 -/* 10667 */ MCD_OPC_Decode, 183, 15, 126, // Opcode: SUQADDv16i8 -/* 10671 */ MCD_OPC_FilterValue, 16, 14, 117, // Skip to: 40641 -/* 10675 */ MCD_OPC_CheckPredicate, 0, 10, 117, // Skip to: 40641 -/* 10679 */ MCD_OPC_Decode, 237, 9, 131, 1, // Opcode: SADDLVv16i8v -/* 10684 */ MCD_OPC_FilterValue, 15, 34, 0, // Skip to: 10722 -/* 10688 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10691 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 10710 -/* 10695 */ MCD_OPC_CheckPredicate, 0, 246, 116, // Skip to: 40641 -/* 10699 */ MCD_OPC_CheckField, 16, 4, 8, 240, 116, // Skip to: 40641 -/* 10705 */ MCD_OPC_Decode, 253, 16, 132, 1, // Opcode: UMOVvi64 -/* 10710 */ MCD_OPC_FilterValue, 1, 231, 116, // Skip to: 40641 -/* 10714 */ MCD_OPC_CheckPredicate, 0, 227, 116, // Skip to: 40641 -/* 10718 */ MCD_OPC_Decode, 176, 1, 112, // Opcode: CMGEv16i8 -/* 10722 */ MCD_OPC_FilterValue, 16, 27, 0, // Skip to: 10753 -/* 10726 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10729 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10742 -/* 10733 */ MCD_OPC_CheckPredicate, 0, 208, 116, // Skip to: 40641 -/* 10737 */ MCD_OPC_Decode, 199, 15, 133, 1, // Opcode: TBLv16i8Three -/* 10742 */ MCD_OPC_FilterValue, 1, 199, 116, // Skip to: 40641 -/* 10746 */ MCD_OPC_CheckPredicate, 0, 195, 116, // Skip to: 40641 -/* 10750 */ MCD_OPC_Decode, 38, 120, // Opcode: ADDHNv8i16_v16i8 -/* 10753 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 10771 -/* 10757 */ MCD_OPC_CheckPredicate, 0, 184, 116, // Skip to: 40641 -/* 10761 */ MCD_OPC_CheckField, 21, 1, 1, 178, 116, // Skip to: 40641 -/* 10767 */ MCD_OPC_Decode, 139, 13, 112, // Opcode: SSHLv16i8 -/* 10771 */ MCD_OPC_FilterValue, 18, 38, 0, // Skip to: 10813 -/* 10775 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 10778 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 10790 -/* 10782 */ MCD_OPC_CheckPredicate, 0, 159, 116, // Skip to: 40641 -/* 10786 */ MCD_OPC_Decode, 146, 1, 117, // Opcode: CLSv16i8 -/* 10790 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 10802 -/* 10794 */ MCD_OPC_CheckPredicate, 0, 147, 116, // Skip to: 40641 -/* 10798 */ MCD_OPC_Decode, 205, 12, 126, // Opcode: SQXTNv16i8 -/* 10802 */ MCD_OPC_FilterValue, 40, 139, 116, // Skip to: 40641 -/* 10806 */ MCD_OPC_CheckPredicate, 1, 135, 116, // Skip to: 40641 -/* 10810 */ MCD_OPC_Decode, 84, 126, // Opcode: AESErr -/* 10813 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 10831 -/* 10817 */ MCD_OPC_CheckPredicate, 0, 124, 116, // Skip to: 40641 -/* 10821 */ MCD_OPC_CheckField, 21, 1, 1, 118, 116, // Skip to: 40641 -/* 10827 */ MCD_OPC_Decode, 158, 12, 112, // Opcode: SQSHLv16i8 -/* 10831 */ MCD_OPC_FilterValue, 20, 28, 0, // Skip to: 10863 -/* 10835 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10838 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10851 -/* 10842 */ MCD_OPC_CheckPredicate, 0, 99, 116, // Skip to: 40641 -/* 10846 */ MCD_OPC_Decode, 209, 15, 134, 1, // Opcode: TBXv16i8Three -/* 10851 */ MCD_OPC_FilterValue, 1, 90, 116, // Skip to: 40641 -/* 10855 */ MCD_OPC_CheckPredicate, 0, 86, 116, // Skip to: 40641 -/* 10859 */ MCD_OPC_Decode, 201, 9, 120, // Opcode: SABALv16i8_v8i16 -/* 10863 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 10881 -/* 10867 */ MCD_OPC_CheckPredicate, 0, 74, 116, // Skip to: 40641 -/* 10871 */ MCD_OPC_CheckField, 21, 1, 1, 68, 116, // Skip to: 40641 -/* 10877 */ MCD_OPC_Decode, 237, 12, 112, // Opcode: SRSHLv16i8 -/* 10881 */ MCD_OPC_FilterValue, 22, 45, 0, // Skip to: 10930 -/* 10885 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10888 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10900 -/* 10892 */ MCD_OPC_CheckPredicate, 0, 49, 116, // Skip to: 40641 -/* 10896 */ MCD_OPC_Decode, 187, 18, 112, // Opcode: UZP2v16i8 -/* 10900 */ MCD_OPC_FilterValue, 1, 41, 116, // Skip to: 40641 -/* 10904 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 10907 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 10919 -/* 10911 */ MCD_OPC_CheckPredicate, 0, 30, 116, // Skip to: 40641 -/* 10915 */ MCD_OPC_Decode, 248, 1, 117, // Opcode: CNTv16i8 -/* 10919 */ MCD_OPC_FilterValue, 8, 22, 116, // Skip to: 40641 -/* 10923 */ MCD_OPC_CheckPredicate, 1, 18, 116, // Skip to: 40641 -/* 10927 */ MCD_OPC_Decode, 83, 126, // Opcode: AESDrr -/* 10930 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 10948 -/* 10934 */ MCD_OPC_CheckPredicate, 0, 7, 116, // Skip to: 40641 -/* 10938 */ MCD_OPC_CheckField, 21, 1, 1, 1, 116, // Skip to: 40641 -/* 10944 */ MCD_OPC_Decode, 242, 11, 112, // Opcode: SQRSHLv16i8 -/* 10948 */ MCD_OPC_FilterValue, 24, 28, 0, // Skip to: 10980 -/* 10952 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 10955 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 10968 -/* 10959 */ MCD_OPC_CheckPredicate, 0, 238, 115, // Skip to: 40641 -/* 10963 */ MCD_OPC_Decode, 197, 15, 135, 1, // Opcode: TBLv16i8Four -/* 10968 */ MCD_OPC_FilterValue, 1, 229, 115, // Skip to: 40641 -/* 10972 */ MCD_OPC_CheckPredicate, 0, 225, 115, // Skip to: 40641 -/* 10976 */ MCD_OPC_Decode, 155, 15, 120, // Opcode: SUBHNv8i16_v16i8 -/* 10980 */ MCD_OPC_FilterValue, 25, 14, 0, // Skip to: 10998 -/* 10984 */ MCD_OPC_CheckPredicate, 0, 213, 115, // Skip to: 40641 -/* 10988 */ MCD_OPC_CheckField, 21, 1, 1, 207, 115, // Skip to: 40641 -/* 10994 */ MCD_OPC_Decode, 216, 10, 112, // Opcode: SMAXv16i8 -/* 10998 */ MCD_OPC_FilterValue, 26, 57, 0, // Skip to: 11059 -/* 11002 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 11005 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11017 -/* 11009 */ MCD_OPC_CheckPredicate, 0, 188, 115, // Skip to: 40641 -/* 11013 */ MCD_OPC_Decode, 228, 15, 112, // Opcode: TRN2v16i8 -/* 11017 */ MCD_OPC_FilterValue, 1, 180, 115, // Skip to: 40641 -/* 11021 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 11024 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11036 -/* 11028 */ MCD_OPC_CheckPredicate, 0, 169, 115, // Skip to: 40641 -/* 11032 */ MCD_OPC_Decode, 225, 9, 126, // Opcode: SADALPv16i8_v8i16 -/* 11036 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11048 -/* 11040 */ MCD_OPC_CheckPredicate, 0, 157, 115, // Skip to: 40641 -/* 11044 */ MCD_OPC_Decode, 201, 3, 126, // Opcode: FCVTNv8i16 -/* 11048 */ MCD_OPC_FilterValue, 8, 149, 115, // Skip to: 40641 -/* 11052 */ MCD_OPC_CheckPredicate, 1, 145, 115, // Skip to: 40641 -/* 11056 */ MCD_OPC_Decode, 86, 117, // Opcode: AESMCrr -/* 11059 */ MCD_OPC_FilterValue, 27, 14, 0, // Skip to: 11077 -/* 11063 */ MCD_OPC_CheckPredicate, 0, 134, 115, // Skip to: 40641 -/* 11067 */ MCD_OPC_CheckField, 21, 1, 1, 128, 115, // Skip to: 40641 -/* 11073 */ MCD_OPC_Decode, 234, 10, 112, // Opcode: SMINv16i8 -/* 11077 */ MCD_OPC_FilterValue, 28, 28, 0, // Skip to: 11109 -/* 11081 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 11084 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11097 -/* 11088 */ MCD_OPC_CheckPredicate, 0, 109, 115, // Skip to: 40641 -/* 11092 */ MCD_OPC_Decode, 207, 15, 136, 1, // Opcode: TBXv16i8Four -/* 11097 */ MCD_OPC_FilterValue, 1, 100, 115, // Skip to: 40641 -/* 11101 */ MCD_OPC_CheckPredicate, 0, 96, 115, // Skip to: 40641 -/* 11105 */ MCD_OPC_Decode, 213, 9, 112, // Opcode: SABDLv16i8_v8i16 -/* 11109 */ MCD_OPC_FilterValue, 29, 14, 0, // Skip to: 11127 -/* 11113 */ MCD_OPC_CheckPredicate, 0, 84, 115, // Skip to: 40641 -/* 11117 */ MCD_OPC_CheckField, 21, 1, 1, 78, 115, // Skip to: 40641 -/* 11123 */ MCD_OPC_Decode, 219, 9, 112, // Opcode: SABDv16i8 -/* 11127 */ MCD_OPC_FilterValue, 30, 57, 0, // Skip to: 11188 -/* 11131 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 11134 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11146 -/* 11138 */ MCD_OPC_CheckPredicate, 0, 59, 115, // Skip to: 40641 -/* 11142 */ MCD_OPC_Decode, 207, 18, 112, // Opcode: ZIP2v16i8 -/* 11146 */ MCD_OPC_FilterValue, 1, 51, 115, // Skip to: 40641 -/* 11150 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 11153 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11165 -/* 11157 */ MCD_OPC_CheckPredicate, 0, 40, 115, // Skip to: 40641 -/* 11161 */ MCD_OPC_Decode, 149, 11, 117, // Opcode: SQABSv16i8 -/* 11165 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11177 -/* 11169 */ MCD_OPC_CheckPredicate, 0, 28, 115, // Skip to: 40641 -/* 11173 */ MCD_OPC_Decode, 161, 3, 117, // Opcode: FCVTLv8i16 -/* 11177 */ MCD_OPC_FilterValue, 8, 20, 115, // Skip to: 40641 -/* 11181 */ MCD_OPC_CheckPredicate, 1, 16, 115, // Skip to: 40641 -/* 11185 */ MCD_OPC_Decode, 85, 117, // Opcode: AESIMCrr -/* 11188 */ MCD_OPC_FilterValue, 31, 14, 0, // Skip to: 11206 -/* 11192 */ MCD_OPC_CheckPredicate, 0, 5, 115, // Skip to: 40641 -/* 11196 */ MCD_OPC_CheckField, 21, 1, 1, 255, 114, // Skip to: 40641 -/* 11202 */ MCD_OPC_Decode, 207, 9, 120, // Opcode: SABAv16i8 -/* 11206 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 11224 -/* 11210 */ MCD_OPC_CheckPredicate, 0, 243, 114, // Skip to: 40641 -/* 11214 */ MCD_OPC_CheckField, 21, 1, 1, 237, 114, // Skip to: 40641 -/* 11220 */ MCD_OPC_Decode, 240, 10, 120, // Opcode: SMLALv16i8_v8i16 -/* 11224 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 11241 -/* 11228 */ MCD_OPC_CheckPredicate, 0, 225, 114, // Skip to: 40641 -/* 11232 */ MCD_OPC_CheckField, 21, 1, 1, 219, 114, // Skip to: 40641 -/* 11238 */ MCD_OPC_Decode, 71, 112, // Opcode: ADDv16i8 -/* 11241 */ MCD_OPC_FilterValue, 34, 27, 0, // Skip to: 11272 -/* 11245 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 11248 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11260 -/* 11252 */ MCD_OPC_CheckPredicate, 0, 201, 114, // Skip to: 40641 -/* 11256 */ MCD_OPC_Decode, 193, 1, 117, // Opcode: CMGTv16i8rz -/* 11260 */ MCD_OPC_FilterValue, 33, 193, 114, // Skip to: 40641 -/* 11264 */ MCD_OPC_CheckPredicate, 0, 189, 114, // Skip to: 40641 -/* 11268 */ MCD_OPC_Decode, 171, 5, 117, // Opcode: FRINTNv4f32 -/* 11272 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 11290 -/* 11276 */ MCD_OPC_CheckPredicate, 0, 177, 114, // Skip to: 40641 -/* 11280 */ MCD_OPC_CheckField, 21, 1, 1, 171, 114, // Skip to: 40641 -/* 11286 */ MCD_OPC_Decode, 240, 1, 112, // Opcode: CMTSTv16i8 -/* 11290 */ MCD_OPC_FilterValue, 37, 14, 0, // Skip to: 11308 -/* 11294 */ MCD_OPC_CheckPredicate, 0, 159, 114, // Skip to: 40641 -/* 11298 */ MCD_OPC_CheckField, 21, 1, 1, 153, 114, // Skip to: 40641 -/* 11304 */ MCD_OPC_Decode, 182, 8, 120, // Opcode: MLAv16i8 -/* 11308 */ MCD_OPC_FilterValue, 38, 27, 0, // Skip to: 11339 -/* 11312 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 11315 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11327 -/* 11319 */ MCD_OPC_CheckPredicate, 0, 134, 114, // Skip to: 40641 -/* 11323 */ MCD_OPC_Decode, 161, 1, 117, // Opcode: CMEQv16i8rz -/* 11327 */ MCD_OPC_FilterValue, 33, 126, 114, // Skip to: 40641 -/* 11331 */ MCD_OPC_CheckPredicate, 0, 122, 114, // Skip to: 40641 -/* 11335 */ MCD_OPC_Decode, 166, 5, 117, // Opcode: FRINTMv4f32 -/* 11339 */ MCD_OPC_FilterValue, 39, 14, 0, // Skip to: 11357 -/* 11343 */ MCD_OPC_CheckPredicate, 0, 110, 114, // Skip to: 40641 -/* 11347 */ MCD_OPC_CheckField, 21, 1, 1, 104, 114, // Skip to: 40641 -/* 11353 */ MCD_OPC_Decode, 231, 8, 112, // Opcode: MULv16i8 -/* 11357 */ MCD_OPC_FilterValue, 40, 14, 0, // Skip to: 11375 -/* 11361 */ MCD_OPC_CheckPredicate, 0, 92, 114, // Skip to: 40641 -/* 11365 */ MCD_OPC_CheckField, 21, 1, 1, 86, 114, // Skip to: 40641 -/* 11371 */ MCD_OPC_Decode, 250, 10, 120, // Opcode: SMLSLv16i8_v8i16 -/* 11375 */ MCD_OPC_FilterValue, 41, 14, 0, // Skip to: 11393 -/* 11379 */ MCD_OPC_CheckPredicate, 0, 74, 114, // Skip to: 40641 -/* 11383 */ MCD_OPC_CheckField, 21, 1, 1, 68, 114, // Skip to: 40641 -/* 11389 */ MCD_OPC_Decode, 205, 10, 112, // Opcode: SMAXPv16i8 -/* 11393 */ MCD_OPC_FilterValue, 42, 53, 0, // Skip to: 11450 -/* 11397 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 11400 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 11412 -/* 11404 */ MCD_OPC_CheckPredicate, 0, 49, 114, // Skip to: 40641 -/* 11408 */ MCD_OPC_Decode, 232, 1, 117, // Opcode: CMLTv16i8rz -/* 11412 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 11424 -/* 11416 */ MCD_OPC_CheckPredicate, 0, 37, 114, // Skip to: 40641 -/* 11420 */ MCD_OPC_Decode, 188, 3, 117, // Opcode: FCVTNSv4f32 -/* 11424 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 11437 -/* 11428 */ MCD_OPC_CheckPredicate, 0, 25, 114, // Skip to: 40641 -/* 11432 */ MCD_OPC_Decode, 211, 10, 137, 1, // Opcode: SMAXVv16i8v -/* 11437 */ MCD_OPC_FilterValue, 49, 16, 114, // Skip to: 40641 -/* 11441 */ MCD_OPC_CheckPredicate, 0, 12, 114, // Skip to: 40641 -/* 11445 */ MCD_OPC_Decode, 229, 10, 137, 1, // Opcode: SMINVv16i8v -/* 11450 */ MCD_OPC_FilterValue, 43, 14, 0, // Skip to: 11468 -/* 11454 */ MCD_OPC_CheckPredicate, 0, 255, 113, // Skip to: 40641 -/* 11458 */ MCD_OPC_CheckField, 21, 1, 1, 249, 113, // Skip to: 40641 -/* 11464 */ MCD_OPC_Decode, 223, 10, 112, // Opcode: SMINPv16i8 -/* 11468 */ MCD_OPC_FilterValue, 46, 38, 0, // Skip to: 11510 -/* 11472 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 11475 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 11486 -/* 11479 */ MCD_OPC_CheckPredicate, 0, 230, 113, // Skip to: 40641 -/* 11483 */ MCD_OPC_Decode, 22, 117, // Opcode: ABSv16i8 -/* 11486 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 11498 -/* 11490 */ MCD_OPC_CheckPredicate, 0, 219, 113, // Skip to: 40641 -/* 11494 */ MCD_OPC_Decode, 170, 3, 117, // Opcode: FCVTMSv4f32 -/* 11498 */ MCD_OPC_FilterValue, 49, 211, 113, // Skip to: 40641 -/* 11502 */ MCD_OPC_CheckPredicate, 0, 207, 113, // Skip to: 40641 -/* 11506 */ MCD_OPC_Decode, 57, 137, 1, // Opcode: ADDVv16i8v -/* 11510 */ MCD_OPC_FilterValue, 47, 13, 0, // Skip to: 11527 -/* 11514 */ MCD_OPC_CheckPredicate, 0, 195, 113, // Skip to: 40641 -/* 11518 */ MCD_OPC_CheckField, 21, 1, 1, 189, 113, // Skip to: 40641 -/* 11524 */ MCD_OPC_Decode, 40, 112, // Opcode: ADDPv16i8 -/* 11527 */ MCD_OPC_FilterValue, 48, 14, 0, // Skip to: 11545 -/* 11531 */ MCD_OPC_CheckPredicate, 0, 178, 113, // Skip to: 40641 -/* 11535 */ MCD_OPC_CheckField, 21, 1, 1, 172, 113, // Skip to: 40641 -/* 11541 */ MCD_OPC_Decode, 139, 11, 112, // Opcode: SMULLv16i8_v8i16 -/* 11545 */ MCD_OPC_FilterValue, 49, 14, 0, // Skip to: 11563 -/* 11549 */ MCD_OPC_CheckPredicate, 0, 160, 113, // Skip to: 40641 -/* 11553 */ MCD_OPC_CheckField, 21, 1, 1, 154, 113, // Skip to: 40641 -/* 11559 */ MCD_OPC_Decode, 173, 4, 112, // Opcode: FMAXNMv4f32 -/* 11563 */ MCD_OPC_FilterValue, 50, 14, 0, // Skip to: 11581 -/* 11567 */ MCD_OPC_CheckPredicate, 0, 142, 113, // Skip to: 40641 -/* 11571 */ MCD_OPC_CheckField, 16, 6, 33, 136, 113, // Skip to: 40641 -/* 11577 */ MCD_OPC_Decode, 144, 3, 117, // Opcode: FCVTASv4f32 -/* 11581 */ MCD_OPC_FilterValue, 51, 14, 0, // Skip to: 11599 -/* 11585 */ MCD_OPC_CheckPredicate, 0, 124, 113, // Skip to: 40641 -/* 11589 */ MCD_OPC_CheckField, 21, 1, 1, 118, 113, // Skip to: 40641 -/* 11595 */ MCD_OPC_Decode, 212, 4, 120, // Opcode: FMLAv4f32 -/* 11599 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 11617 -/* 11603 */ MCD_OPC_CheckPredicate, 0, 106, 113, // Skip to: 40641 -/* 11607 */ MCD_OPC_CheckField, 21, 1, 1, 100, 113, // Skip to: 40641 -/* 11613 */ MCD_OPC_Decode, 209, 2, 112, // Opcode: FADDv4f32 -/* 11617 */ MCD_OPC_FilterValue, 54, 14, 0, // Skip to: 11635 -/* 11621 */ MCD_OPC_CheckPredicate, 0, 88, 113, // Skip to: 40641 -/* 11625 */ MCD_OPC_CheckField, 16, 6, 33, 82, 113, // Skip to: 40641 -/* 11631 */ MCD_OPC_Decode, 148, 10, 117, // Opcode: SCVTFv4f32 -/* 11635 */ MCD_OPC_FilterValue, 55, 14, 0, // Skip to: 11653 -/* 11639 */ MCD_OPC_CheckPredicate, 0, 70, 113, // Skip to: 40641 -/* 11643 */ MCD_OPC_CheckField, 21, 1, 1, 64, 113, // Skip to: 40641 -/* 11649 */ MCD_OPC_Decode, 247, 4, 112, // Opcode: FMULXv4f32 -/* 11653 */ MCD_OPC_FilterValue, 56, 14, 0, // Skip to: 11671 -/* 11657 */ MCD_OPC_CheckPredicate, 0, 52, 113, // Skip to: 40641 -/* 11661 */ MCD_OPC_CheckField, 21, 1, 1, 46, 113, // Skip to: 40641 -/* 11667 */ MCD_OPC_Decode, 147, 9, 112, // Opcode: PMULLv16i8 -/* 11671 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 11689 -/* 11675 */ MCD_OPC_CheckPredicate, 0, 34, 113, // Skip to: 40641 -/* 11679 */ MCD_OPC_CheckField, 21, 1, 1, 28, 113, // Skip to: 40641 -/* 11685 */ MCD_OPC_Decode, 222, 2, 112, // Opcode: FCMEQv4f32 -/* 11689 */ MCD_OPC_FilterValue, 61, 14, 0, // Skip to: 11707 -/* 11693 */ MCD_OPC_CheckPredicate, 0, 16, 113, // Skip to: 40641 -/* 11697 */ MCD_OPC_CheckField, 21, 1, 1, 10, 113, // Skip to: 40641 -/* 11703 */ MCD_OPC_Decode, 183, 4, 112, // Opcode: FMAXv4f32 -/* 11707 */ MCD_OPC_FilterValue, 63, 2, 113, // Skip to: 40641 -/* 11711 */ MCD_OPC_CheckPredicate, 0, 254, 112, // Skip to: 40641 -/* 11715 */ MCD_OPC_CheckField, 21, 1, 1, 248, 112, // Skip to: 40641 -/* 11721 */ MCD_OPC_Decode, 149, 5, 112, // Opcode: FRECPSv4f32 -/* 11725 */ MCD_OPC_FilterValue, 3, 240, 112, // Skip to: 40641 -/* 11729 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 11732 */ MCD_OPC_FilterValue, 0, 60, 2, // Skip to: 12308 -/* 11736 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 11739 */ MCD_OPC_FilterValue, 0, 41, 1, // Skip to: 12040 -/* 11743 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 11746 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 11759 -/* 11750 */ MCD_OPC_CheckPredicate, 0, 215, 112, // Skip to: 40641 -/* 11754 */ MCD_OPC_Decode, 177, 2, 138, 1, // Opcode: EXTv16i8 -/* 11759 */ MCD_OPC_FilterValue, 1, 206, 112, // Skip to: 40641 -/* 11763 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 11766 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11778 -/* 11770 */ MCD_OPC_CheckPredicate, 0, 195, 112, // Skip to: 40641 -/* 11774 */ MCD_OPC_Decode, 148, 16, 112, // Opcode: UADDLv16i8_v8i16 -/* 11778 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 11796 -/* 11782 */ MCD_OPC_CheckPredicate, 0, 183, 112, // Skip to: 40641 -/* 11786 */ MCD_OPC_CheckField, 16, 5, 0, 177, 112, // Skip to: 40641 -/* 11792 */ MCD_OPC_Decode, 175, 9, 117, // Opcode: REV32v16i8 -/* 11796 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 11808 -/* 11800 */ MCD_OPC_CheckPredicate, 0, 165, 112, // Skip to: 40641 -/* 11804 */ MCD_OPC_Decode, 154, 16, 112, // Opcode: UADDWv16i8_v8i16 -/* 11808 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 11820 -/* 11812 */ MCD_OPC_CheckPredicate, 0, 153, 112, // Skip to: 40641 -/* 11816 */ MCD_OPC_Decode, 168, 18, 112, // Opcode: USUBLv16i8_v8i16 -/* 11820 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 11851 -/* 11824 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 11827 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11839 -/* 11831 */ MCD_OPC_CheckPredicate, 0, 134, 112, // Skip to: 40641 -/* 11835 */ MCD_OPC_Decode, 137, 16, 117, // Opcode: UADDLPv16i8_v8i16 -/* 11839 */ MCD_OPC_FilterValue, 1, 126, 112, // Skip to: 40641 -/* 11843 */ MCD_OPC_CheckPredicate, 0, 122, 112, // Skip to: 40641 -/* 11847 */ MCD_OPC_Decode, 214, 12, 126, // Opcode: SQXTUNv16i8 -/* 11851 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 11863 -/* 11855 */ MCD_OPC_CheckPredicate, 0, 110, 112, // Skip to: 40641 -/* 11859 */ MCD_OPC_Decode, 174, 18, 112, // Opcode: USUBWv16i8_v8i16 -/* 11863 */ MCD_OPC_FilterValue, 7, 40, 0, // Skip to: 11907 -/* 11867 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 11870 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11882 -/* 11874 */ MCD_OPC_CheckPredicate, 0, 91, 112, // Skip to: 40641 -/* 11878 */ MCD_OPC_Decode, 149, 18, 126, // Opcode: USQADDv16i8 -/* 11882 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 11894 -/* 11886 */ MCD_OPC_CheckPredicate, 0, 79, 112, // Skip to: 40641 -/* 11890 */ MCD_OPC_Decode, 170, 10, 117, // Opcode: SHLLv16i8 -/* 11894 */ MCD_OPC_FilterValue, 16, 71, 112, // Skip to: 40641 -/* 11898 */ MCD_OPC_CheckPredicate, 0, 67, 112, // Skip to: 40641 -/* 11902 */ MCD_OPC_Decode, 143, 16, 131, 1, // Opcode: UADDLVv16i8v -/* 11907 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 11919 -/* 11911 */ MCD_OPC_CheckPredicate, 0, 54, 112, // Skip to: 40641 -/* 11915 */ MCD_OPC_Decode, 162, 9, 120, // Opcode: RADDHNv8i16_v16i8 -/* 11919 */ MCD_OPC_FilterValue, 9, 27, 0, // Skip to: 11950 -/* 11923 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 11926 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 11938 -/* 11930 */ MCD_OPC_CheckPredicate, 0, 35, 112, // Skip to: 40641 -/* 11934 */ MCD_OPC_Decode, 154, 1, 117, // Opcode: CLZv16i8 -/* 11938 */ MCD_OPC_FilterValue, 1, 27, 112, // Skip to: 40641 -/* 11942 */ MCD_OPC_CheckPredicate, 0, 23, 112, // Skip to: 40641 -/* 11946 */ MCD_OPC_Decode, 212, 17, 126, // Opcode: UQXTNv16i8 -/* 11950 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 11962 -/* 11954 */ MCD_OPC_CheckPredicate, 0, 11, 112, // Skip to: 40641 -/* 11958 */ MCD_OPC_Decode, 235, 15, 120, // Opcode: UABALv16i8_v8i16 -/* 11962 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 11980 -/* 11966 */ MCD_OPC_CheckPredicate, 0, 255, 111, // Skip to: 40641 -/* 11970 */ MCD_OPC_CheckField, 16, 5, 0, 249, 111, // Skip to: 40641 -/* 11976 */ MCD_OPC_Decode, 255, 8, 117, // Opcode: NOTv16i8 -/* 11980 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 11992 -/* 11984 */ MCD_OPC_CheckPredicate, 0, 237, 111, // Skip to: 40641 -/* 11988 */ MCD_OPC_Decode, 199, 9, 120, // Opcode: RSUBHNv8i16_v16i8 -/* 11992 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12010 -/* 11996 */ MCD_OPC_CheckPredicate, 0, 225, 111, // Skip to: 40641 -/* 12000 */ MCD_OPC_CheckField, 16, 5, 0, 219, 111, // Skip to: 40641 -/* 12006 */ MCD_OPC_Decode, 131, 16, 126, // Opcode: UADALPv16i8_v8i16 -/* 12010 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 12022 -/* 12014 */ MCD_OPC_CheckPredicate, 0, 207, 111, // Skip to: 40641 -/* 12018 */ MCD_OPC_Decode, 247, 15, 112, // Opcode: UABDLv16i8_v8i16 -/* 12022 */ MCD_OPC_FilterValue, 15, 199, 111, // Skip to: 40641 -/* 12026 */ MCD_OPC_CheckPredicate, 0, 195, 111, // Skip to: 40641 -/* 12030 */ MCD_OPC_CheckField, 16, 5, 0, 189, 111, // Skip to: 40641 -/* 12036 */ MCD_OPC_Decode, 219, 11, 117, // Opcode: SQNEGv16i8 -/* 12040 */ MCD_OPC_FilterValue, 1, 181, 111, // Skip to: 40641 -/* 12044 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 12047 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12065 -/* 12051 */ MCD_OPC_CheckPredicate, 0, 170, 111, // Skip to: 40641 -/* 12055 */ MCD_OPC_CheckField, 21, 1, 1, 164, 111, // Skip to: 40641 -/* 12061 */ MCD_OPC_Decode, 231, 16, 120, // Opcode: UMLALv16i8_v8i16 -/* 12065 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 12096 -/* 12069 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 12072 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12084 -/* 12076 */ MCD_OPC_CheckPredicate, 0, 145, 111, // Skip to: 40641 -/* 12080 */ MCD_OPC_Decode, 177, 1, 117, // Opcode: CMGEv16i8rz -/* 12084 */ MCD_OPC_FilterValue, 33, 137, 111, // Skip to: 40641 -/* 12088 */ MCD_OPC_CheckPredicate, 0, 133, 111, // Skip to: 40641 -/* 12092 */ MCD_OPC_Decode, 156, 5, 117, // Opcode: FRINTAv4f32 -/* 12096 */ MCD_OPC_FilterValue, 3, 27, 0, // Skip to: 12127 -/* 12100 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 12103 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12115 -/* 12107 */ MCD_OPC_CheckPredicate, 0, 114, 111, // Skip to: 40641 -/* 12111 */ MCD_OPC_Decode, 224, 1, 117, // Opcode: CMLEv16i8rz -/* 12115 */ MCD_OPC_FilterValue, 33, 106, 111, // Skip to: 40641 -/* 12119 */ MCD_OPC_CheckPredicate, 0, 102, 111, // Skip to: 40641 -/* 12123 */ MCD_OPC_Decode, 181, 5, 117, // Opcode: FRINTXv4f32 -/* 12127 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12145 -/* 12131 */ MCD_OPC_CheckPredicate, 0, 90, 111, // Skip to: 40641 -/* 12135 */ MCD_OPC_CheckField, 21, 1, 1, 84, 111, // Skip to: 40641 -/* 12141 */ MCD_OPC_Decode, 241, 16, 120, // Opcode: UMLSLv16i8_v8i16 -/* 12145 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 12190 -/* 12149 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 12152 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 12164 -/* 12156 */ MCD_OPC_CheckPredicate, 0, 65, 111, // Skip to: 40641 -/* 12160 */ MCD_OPC_Decode, 197, 3, 117, // Opcode: FCVTNUv4f32 -/* 12164 */ MCD_OPC_FilterValue, 48, 9, 0, // Skip to: 12177 -/* 12168 */ MCD_OPC_CheckPredicate, 0, 53, 111, // Skip to: 40641 -/* 12172 */ MCD_OPC_Decode, 203, 16, 137, 1, // Opcode: UMAXVv16i8v -/* 12177 */ MCD_OPC_FilterValue, 49, 44, 111, // Skip to: 40641 -/* 12181 */ MCD_OPC_CheckPredicate, 0, 40, 111, // Skip to: 40641 -/* 12185 */ MCD_OPC_Decode, 220, 16, 137, 1, // Opcode: UMINVv16i8v -/* 12190 */ MCD_OPC_FilterValue, 7, 27, 0, // Skip to: 12221 -/* 12194 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 12197 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 12209 -/* 12201 */ MCD_OPC_CheckPredicate, 0, 20, 111, // Skip to: 40641 -/* 12205 */ MCD_OPC_Decode, 247, 8, 117, // Opcode: NEGv16i8 -/* 12209 */ MCD_OPC_FilterValue, 33, 12, 111, // Skip to: 40641 -/* 12213 */ MCD_OPC_CheckPredicate, 0, 8, 111, // Skip to: 40641 -/* 12217 */ MCD_OPC_Decode, 179, 3, 117, // Opcode: FCVTMUv4f32 -/* 12221 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12239 -/* 12225 */ MCD_OPC_CheckPredicate, 0, 252, 110, // Skip to: 40641 -/* 12229 */ MCD_OPC_CheckField, 21, 1, 1, 246, 110, // Skip to: 40641 -/* 12235 */ MCD_OPC_Decode, 129, 17, 112, // Opcode: UMULLv16i8_v8i16 -/* 12239 */ MCD_OPC_FilterValue, 9, 28, 0, // Skip to: 12271 -/* 12243 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 12246 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 12258 -/* 12250 */ MCD_OPC_CheckPredicate, 0, 227, 110, // Skip to: 40641 -/* 12254 */ MCD_OPC_Decode, 153, 3, 117, // Opcode: FCVTAUv4f32 -/* 12258 */ MCD_OPC_FilterValue, 48, 219, 110, // Skip to: 40641 -/* 12262 */ MCD_OPC_CheckPredicate, 0, 215, 110, // Skip to: 40641 -/* 12266 */ MCD_OPC_Decode, 170, 4, 139, 1, // Opcode: FMAXNMVv4i32v -/* 12271 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12289 -/* 12275 */ MCD_OPC_CheckPredicate, 0, 202, 110, // Skip to: 40641 -/* 12279 */ MCD_OPC_CheckField, 16, 6, 33, 196, 110, // Skip to: 40641 -/* 12285 */ MCD_OPC_Decode, 178, 16, 117, // Opcode: UCVTFv4f32 -/* 12289 */ MCD_OPC_FilterValue, 15, 188, 110, // Skip to: 40641 -/* 12293 */ MCD_OPC_CheckPredicate, 0, 184, 110, // Skip to: 40641 -/* 12297 */ MCD_OPC_CheckField, 16, 6, 48, 178, 110, // Skip to: 40641 -/* 12303 */ MCD_OPC_Decode, 180, 4, 139, 1, // Opcode: FMAXVv4i32v -/* 12308 */ MCD_OPC_FilterValue, 1, 169, 110, // Skip to: 40641 -/* 12312 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 12315 */ MCD_OPC_FilterValue, 0, 43, 1, // Skip to: 12618 -/* 12319 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 12322 */ MCD_OPC_FilterValue, 0, 93, 0, // Skip to: 12419 -/* 12326 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 12329 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 12406 -/* 12333 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 12336 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 12387 -/* 12340 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 12343 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 12368 -/* 12347 */ MCD_OPC_CheckPredicate, 0, 130, 110, // Skip to: 40641 -/* 12351 */ MCD_OPC_CheckField, 19, 1, 1, 124, 110, // Skip to: 40641 -/* 12357 */ MCD_OPC_CheckField, 11, 3, 0, 118, 110, // Skip to: 40641 -/* 12363 */ MCD_OPC_Decode, 215, 5, 140, 1, // Opcode: INSvi64lane -/* 12368 */ MCD_OPC_FilterValue, 1, 109, 110, // Skip to: 40641 -/* 12372 */ MCD_OPC_CheckPredicate, 0, 105, 110, // Skip to: 40641 -/* 12376 */ MCD_OPC_CheckField, 11, 2, 0, 99, 110, // Skip to: 40641 -/* 12382 */ MCD_OPC_Decode, 213, 5, 141, 1, // Opcode: INSvi32lane -/* 12387 */ MCD_OPC_FilterValue, 1, 90, 110, // Skip to: 40641 -/* 12391 */ MCD_OPC_CheckPredicate, 0, 86, 110, // Skip to: 40641 -/* 12395 */ MCD_OPC_CheckField, 11, 1, 0, 80, 110, // Skip to: 40641 -/* 12401 */ MCD_OPC_Decode, 211, 5, 142, 1, // Opcode: INSvi16lane -/* 12406 */ MCD_OPC_FilterValue, 1, 71, 110, // Skip to: 40641 -/* 12410 */ MCD_OPC_CheckPredicate, 0, 67, 110, // Skip to: 40641 -/* 12414 */ MCD_OPC_Decode, 217, 5, 143, 1, // Opcode: INSvi8lane -/* 12419 */ MCD_OPC_FilterValue, 1, 58, 110, // Skip to: 40641 -/* 12423 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 12426 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 12438 -/* 12430 */ MCD_OPC_CheckPredicate, 0, 47, 110, // Skip to: 40641 -/* 12434 */ MCD_OPC_Decode, 184, 16, 112, // Opcode: UHADDv16i8 -/* 12438 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 12450 -/* 12442 */ MCD_OPC_CheckPredicate, 0, 35, 110, // Skip to: 40641 -/* 12446 */ MCD_OPC_Decode, 139, 17, 112, // Opcode: UQADDv16i8 -/* 12450 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 12462 -/* 12454 */ MCD_OPC_CheckPredicate, 0, 23, 110, // Skip to: 40641 -/* 12458 */ MCD_OPC_Decode, 223, 17, 112, // Opcode: URHADDv16i8 -/* 12462 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 12474 -/* 12466 */ MCD_OPC_CheckPredicate, 0, 11, 110, // Skip to: 40641 -/* 12470 */ MCD_OPC_Decode, 172, 2, 112, // Opcode: EORv16i8 -/* 12474 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 12486 -/* 12478 */ MCD_OPC_CheckPredicate, 0, 255, 109, // Skip to: 40641 -/* 12482 */ MCD_OPC_Decode, 190, 16, 112, // Opcode: UHSUBv16i8 -/* 12486 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 12498 -/* 12490 */ MCD_OPC_CheckPredicate, 0, 243, 109, // Skip to: 40641 -/* 12494 */ MCD_OPC_Decode, 201, 17, 112, // Opcode: UQSUBv16i8 -/* 12498 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 12510 -/* 12502 */ MCD_OPC_CheckPredicate, 0, 231, 109, // Skip to: 40641 -/* 12506 */ MCD_OPC_Decode, 208, 1, 112, // Opcode: CMHIv16i8 -/* 12510 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 12522 -/* 12514 */ MCD_OPC_CheckPredicate, 0, 219, 109, // Skip to: 40641 -/* 12518 */ MCD_OPC_Decode, 216, 1, 112, // Opcode: CMHSv16i8 -/* 12522 */ MCD_OPC_FilterValue, 8, 8, 0, // Skip to: 12534 -/* 12526 */ MCD_OPC_CheckPredicate, 0, 207, 109, // Skip to: 40641 -/* 12530 */ MCD_OPC_Decode, 133, 18, 112, // Opcode: USHLv16i8 -/* 12534 */ MCD_OPC_FilterValue, 9, 8, 0, // Skip to: 12546 -/* 12538 */ MCD_OPC_CheckPredicate, 0, 195, 109, // Skip to: 40641 -/* 12542 */ MCD_OPC_Decode, 174, 17, 112, // Opcode: UQSHLv16i8 -/* 12546 */ MCD_OPC_FilterValue, 10, 8, 0, // Skip to: 12558 -/* 12550 */ MCD_OPC_CheckPredicate, 0, 183, 109, // Skip to: 40641 -/* 12554 */ MCD_OPC_Decode, 229, 17, 112, // Opcode: URSHLv16i8 -/* 12558 */ MCD_OPC_FilterValue, 11, 8, 0, // Skip to: 12570 -/* 12562 */ MCD_OPC_CheckPredicate, 0, 171, 109, // Skip to: 40641 -/* 12566 */ MCD_OPC_Decode, 150, 17, 112, // Opcode: UQRSHLv16i8 -/* 12570 */ MCD_OPC_FilterValue, 12, 8, 0, // Skip to: 12582 -/* 12574 */ MCD_OPC_CheckPredicate, 0, 159, 109, // Skip to: 40641 -/* 12578 */ MCD_OPC_Decode, 208, 16, 112, // Opcode: UMAXv16i8 -/* 12582 */ MCD_OPC_FilterValue, 13, 8, 0, // Skip to: 12594 -/* 12586 */ MCD_OPC_CheckPredicate, 0, 147, 109, // Skip to: 40641 -/* 12590 */ MCD_OPC_Decode, 225, 16, 112, // Opcode: UMINv16i8 -/* 12594 */ MCD_OPC_FilterValue, 14, 8, 0, // Skip to: 12606 -/* 12598 */ MCD_OPC_CheckPredicate, 0, 135, 109, // Skip to: 40641 -/* 12602 */ MCD_OPC_Decode, 253, 15, 112, // Opcode: UABDv16i8 -/* 12606 */ MCD_OPC_FilterValue, 15, 127, 109, // Skip to: 40641 -/* 12610 */ MCD_OPC_CheckPredicate, 0, 123, 109, // Skip to: 40641 -/* 12614 */ MCD_OPC_Decode, 241, 15, 120, // Opcode: UABAv16i8 -/* 12618 */ MCD_OPC_FilterValue, 1, 115, 109, // Skip to: 40641 -/* 12622 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... -/* 12625 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12643 -/* 12629 */ MCD_OPC_CheckPredicate, 0, 104, 109, // Skip to: 40641 -/* 12633 */ MCD_OPC_CheckField, 21, 1, 1, 98, 109, // Skip to: 40641 -/* 12639 */ MCD_OPC_Decode, 175, 15, 112, // Opcode: SUBv16i8 -/* 12643 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12661 -/* 12647 */ MCD_OPC_CheckPredicate, 0, 86, 109, // Skip to: 40641 -/* 12651 */ MCD_OPC_CheckField, 21, 1, 1, 80, 109, // Skip to: 40641 -/* 12657 */ MCD_OPC_Decode, 160, 1, 112, // Opcode: CMEQv16i8 -/* 12661 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12679 -/* 12665 */ MCD_OPC_CheckPredicate, 0, 68, 109, // Skip to: 40641 -/* 12669 */ MCD_OPC_CheckField, 21, 1, 1, 62, 109, // Skip to: 40641 -/* 12675 */ MCD_OPC_Decode, 192, 8, 120, // Opcode: MLSv16i8 -/* 12679 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 12697 -/* 12683 */ MCD_OPC_CheckPredicate, 0, 50, 109, // Skip to: 40641 -/* 12687 */ MCD_OPC_CheckField, 21, 1, 1, 44, 109, // Skip to: 40641 -/* 12693 */ MCD_OPC_Decode, 151, 9, 112, // Opcode: PMULv16i8 -/* 12697 */ MCD_OPC_FilterValue, 4, 14, 0, // Skip to: 12715 -/* 12701 */ MCD_OPC_CheckPredicate, 0, 32, 109, // Skip to: 40641 -/* 12705 */ MCD_OPC_CheckField, 21, 1, 1, 26, 109, // Skip to: 40641 -/* 12711 */ MCD_OPC_Decode, 197, 16, 112, // Opcode: UMAXPv16i8 -/* 12715 */ MCD_OPC_FilterValue, 5, 14, 0, // Skip to: 12733 -/* 12719 */ MCD_OPC_CheckPredicate, 0, 14, 109, // Skip to: 40641 -/* 12723 */ MCD_OPC_CheckField, 21, 1, 1, 8, 109, // Skip to: 40641 -/* 12729 */ MCD_OPC_Decode, 214, 16, 112, // Opcode: UMINPv16i8 -/* 12733 */ MCD_OPC_FilterValue, 8, 14, 0, // Skip to: 12751 -/* 12737 */ MCD_OPC_CheckPredicate, 0, 252, 108, // Skip to: 40641 -/* 12741 */ MCD_OPC_CheckField, 21, 1, 1, 246, 108, // Skip to: 40641 -/* 12747 */ MCD_OPC_Decode, 168, 4, 112, // Opcode: FMAXNMPv4f32 -/* 12751 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 12769 -/* 12755 */ MCD_OPC_CheckPredicate, 0, 234, 108, // Skip to: 40641 -/* 12759 */ MCD_OPC_CheckField, 21, 1, 1, 228, 108, // Skip to: 40641 -/* 12765 */ MCD_OPC_Decode, 205, 2, 112, // Opcode: FADDPv4f32 -/* 12769 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 12787 -/* 12773 */ MCD_OPC_CheckPredicate, 0, 216, 108, // Skip to: 40641 -/* 12777 */ MCD_OPC_CheckField, 21, 1, 1, 210, 108, // Skip to: 40641 -/* 12783 */ MCD_OPC_Decode, 255, 4, 112, // Opcode: FMULv4f32 -/* 12787 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 12805 -/* 12791 */ MCD_OPC_CheckPredicate, 0, 198, 108, // Skip to: 40641 -/* 12795 */ MCD_OPC_CheckField, 21, 1, 1, 192, 108, // Skip to: 40641 -/* 12801 */ MCD_OPC_Decode, 232, 2, 112, // Opcode: FCMGEv4f32 -/* 12805 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 12823 -/* 12809 */ MCD_OPC_CheckPredicate, 0, 180, 108, // Skip to: 40641 -/* 12813 */ MCD_OPC_CheckField, 21, 1, 1, 174, 108, // Skip to: 40641 -/* 12819 */ MCD_OPC_Decode, 194, 2, 112, // Opcode: FACGEv4f32 -/* 12823 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 12841 -/* 12827 */ MCD_OPC_CheckPredicate, 0, 162, 108, // Skip to: 40641 -/* 12831 */ MCD_OPC_CheckField, 21, 1, 1, 156, 108, // Skip to: 40641 -/* 12837 */ MCD_OPC_Decode, 178, 4, 112, // Opcode: FMAXPv4f32 -/* 12841 */ MCD_OPC_FilterValue, 15, 148, 108, // Skip to: 40641 -/* 12845 */ MCD_OPC_CheckPredicate, 0, 144, 108, // Skip to: 40641 -/* 12849 */ MCD_OPC_CheckField, 21, 1, 1, 138, 108, // Skip to: 40641 -/* 12855 */ MCD_OPC_Decode, 159, 4, 112, // Opcode: FDIVv4f32 -/* 12859 */ MCD_OPC_FilterValue, 9, 131, 18, // Skip to: 17602 -/* 12863 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 12866 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 12945 -/* 12870 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 12873 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12891 -/* 12877 */ MCD_OPC_CheckPredicate, 0, 112, 108, // Skip to: 40641 -/* 12881 */ MCD_OPC_CheckField, 21, 1, 1, 106, 108, // Skip to: 40641 -/* 12887 */ MCD_OPC_Decode, 244, 9, 85, // Opcode: SADDLv4i16_v4i32 -/* 12891 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12909 -/* 12895 */ MCD_OPC_CheckPredicate, 0, 94, 108, // Skip to: 40641 -/* 12899 */ MCD_OPC_CheckField, 21, 1, 1, 88, 108, // Skip to: 40641 -/* 12905 */ MCD_OPC_Decode, 150, 16, 85, // Opcode: UADDLv4i16_v4i32 -/* 12909 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 12927 -/* 12913 */ MCD_OPC_CheckPredicate, 0, 76, 108, // Skip to: 40641 -/* 12917 */ MCD_OPC_CheckField, 21, 1, 1, 70, 108, // Skip to: 40641 -/* 12923 */ MCD_OPC_Decode, 246, 9, 112, // Opcode: SADDLv8i16_v4i32 -/* 12927 */ MCD_OPC_FilterValue, 3, 62, 108, // Skip to: 40641 -/* 12931 */ MCD_OPC_CheckPredicate, 0, 58, 108, // Skip to: 40641 -/* 12935 */ MCD_OPC_CheckField, 21, 1, 1, 52, 108, // Skip to: 40641 -/* 12941 */ MCD_OPC_Decode, 152, 16, 112, // Opcode: UADDLv8i16_v4i32 -/* 12945 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 13024 -/* 12949 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 12952 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 12970 -/* 12956 */ MCD_OPC_CheckPredicate, 0, 33, 108, // Skip to: 40641 -/* 12960 */ MCD_OPC_CheckField, 21, 1, 1, 27, 108, // Skip to: 40641 -/* 12966 */ MCD_OPC_Decode, 166, 10, 89, // Opcode: SHADDv4i16 -/* 12970 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 12988 -/* 12974 */ MCD_OPC_CheckPredicate, 0, 15, 108, // Skip to: 40641 -/* 12978 */ MCD_OPC_CheckField, 21, 1, 1, 9, 108, // Skip to: 40641 -/* 12984 */ MCD_OPC_Decode, 186, 16, 89, // Opcode: UHADDv4i16 -/* 12988 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13006 -/* 12992 */ MCD_OPC_CheckPredicate, 0, 253, 107, // Skip to: 40641 -/* 12996 */ MCD_OPC_CheckField, 21, 1, 1, 247, 107, // Skip to: 40641 -/* 13002 */ MCD_OPC_Decode, 168, 10, 112, // Opcode: SHADDv8i16 -/* 13006 */ MCD_OPC_FilterValue, 3, 239, 107, // Skip to: 40641 -/* 13010 */ MCD_OPC_CheckPredicate, 0, 235, 107, // Skip to: 40641 -/* 13014 */ MCD_OPC_CheckField, 21, 1, 1, 229, 107, // Skip to: 40641 -/* 13020 */ MCD_OPC_Decode, 188, 16, 112, // Opcode: UHADDv8i16 -/* 13024 */ MCD_OPC_FilterValue, 2, 75, 0, // Skip to: 13103 -/* 13028 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13031 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13049 -/* 13035 */ MCD_OPC_CheckPredicate, 0, 210, 107, // Skip to: 40641 -/* 13039 */ MCD_OPC_CheckField, 16, 6, 32, 204, 107, // Skip to: 40641 -/* 13045 */ MCD_OPC_Decode, 181, 9, 90, // Opcode: REV64v4i16 -/* 13049 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13067 -/* 13053 */ MCD_OPC_CheckPredicate, 0, 192, 107, // Skip to: 40641 -/* 13057 */ MCD_OPC_CheckField, 16, 6, 32, 186, 107, // Skip to: 40641 -/* 13063 */ MCD_OPC_Decode, 176, 9, 90, // Opcode: REV32v4i16 -/* 13067 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13085 -/* 13071 */ MCD_OPC_CheckPredicate, 0, 174, 107, // Skip to: 40641 -/* 13075 */ MCD_OPC_CheckField, 16, 6, 32, 168, 107, // Skip to: 40641 -/* 13081 */ MCD_OPC_Decode, 183, 9, 117, // Opcode: REV64v8i16 -/* 13085 */ MCD_OPC_FilterValue, 3, 160, 107, // Skip to: 40641 -/* 13089 */ MCD_OPC_CheckPredicate, 0, 156, 107, // Skip to: 40641 -/* 13093 */ MCD_OPC_CheckField, 16, 6, 32, 150, 107, // Skip to: 40641 -/* 13099 */ MCD_OPC_Decode, 177, 9, 117, // Opcode: REV32v8i16 -/* 13103 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 13182 -/* 13107 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13110 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13128 -/* 13114 */ MCD_OPC_CheckPredicate, 0, 131, 107, // Skip to: 40641 -/* 13118 */ MCD_OPC_CheckField, 21, 1, 1, 125, 107, // Skip to: 40641 -/* 13124 */ MCD_OPC_Decode, 167, 11, 89, // Opcode: SQADDv4i16 -/* 13128 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13146 -/* 13132 */ MCD_OPC_CheckPredicate, 0, 113, 107, // Skip to: 40641 -/* 13136 */ MCD_OPC_CheckField, 21, 1, 1, 107, 107, // Skip to: 40641 -/* 13142 */ MCD_OPC_Decode, 146, 17, 89, // Opcode: UQADDv4i16 -/* 13146 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13164 -/* 13150 */ MCD_OPC_CheckPredicate, 0, 95, 107, // Skip to: 40641 -/* 13154 */ MCD_OPC_CheckField, 21, 1, 1, 89, 107, // Skip to: 40641 -/* 13160 */ MCD_OPC_Decode, 169, 11, 112, // Opcode: SQADDv8i16 -/* 13164 */ MCD_OPC_FilterValue, 3, 81, 107, // Skip to: 40641 -/* 13168 */ MCD_OPC_CheckPredicate, 0, 77, 107, // Skip to: 40641 -/* 13172 */ MCD_OPC_CheckField, 21, 1, 1, 71, 107, // Skip to: 40641 -/* 13178 */ MCD_OPC_Decode, 148, 17, 112, // Opcode: UQADDv8i16 -/* 13182 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 13261 -/* 13186 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13189 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13207 -/* 13193 */ MCD_OPC_CheckPredicate, 0, 52, 107, // Skip to: 40641 -/* 13197 */ MCD_OPC_CheckField, 21, 1, 1, 46, 107, // Skip to: 40641 -/* 13203 */ MCD_OPC_Decode, 250, 9, 93, // Opcode: SADDWv4i16_v4i32 -/* 13207 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13225 -/* 13211 */ MCD_OPC_CheckPredicate, 0, 34, 107, // Skip to: 40641 -/* 13215 */ MCD_OPC_CheckField, 21, 1, 1, 28, 107, // Skip to: 40641 -/* 13221 */ MCD_OPC_Decode, 156, 16, 93, // Opcode: UADDWv4i16_v4i32 -/* 13225 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13243 -/* 13229 */ MCD_OPC_CheckPredicate, 0, 16, 107, // Skip to: 40641 -/* 13233 */ MCD_OPC_CheckField, 21, 1, 1, 10, 107, // Skip to: 40641 -/* 13239 */ MCD_OPC_Decode, 252, 9, 112, // Opcode: SADDWv8i16_v4i32 -/* 13243 */ MCD_OPC_FilterValue, 3, 2, 107, // Skip to: 40641 -/* 13247 */ MCD_OPC_CheckPredicate, 0, 254, 106, // Skip to: 40641 -/* 13251 */ MCD_OPC_CheckField, 21, 1, 1, 248, 106, // Skip to: 40641 -/* 13257 */ MCD_OPC_Decode, 158, 16, 112, // Opcode: UADDWv8i16_v4i32 -/* 13261 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 13340 -/* 13265 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13268 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13286 -/* 13272 */ MCD_OPC_CheckPredicate, 0, 229, 106, // Skip to: 40641 -/* 13276 */ MCD_OPC_CheckField, 21, 1, 1, 223, 106, // Skip to: 40641 -/* 13282 */ MCD_OPC_Decode, 225, 12, 89, // Opcode: SRHADDv4i16 -/* 13286 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13304 -/* 13290 */ MCD_OPC_CheckPredicate, 0, 211, 106, // Skip to: 40641 -/* 13294 */ MCD_OPC_CheckField, 21, 1, 1, 205, 106, // Skip to: 40641 -/* 13300 */ MCD_OPC_Decode, 225, 17, 89, // Opcode: URHADDv4i16 -/* 13304 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13322 -/* 13308 */ MCD_OPC_CheckPredicate, 0, 193, 106, // Skip to: 40641 -/* 13312 */ MCD_OPC_CheckField, 21, 1, 1, 187, 106, // Skip to: 40641 -/* 13318 */ MCD_OPC_Decode, 227, 12, 112, // Opcode: SRHADDv8i16 -/* 13322 */ MCD_OPC_FilterValue, 3, 179, 106, // Skip to: 40641 -/* 13326 */ MCD_OPC_CheckPredicate, 0, 175, 106, // Skip to: 40641 -/* 13330 */ MCD_OPC_CheckField, 21, 1, 1, 169, 106, // Skip to: 40641 -/* 13336 */ MCD_OPC_Decode, 227, 17, 112, // Opcode: URHADDv8i16 -/* 13340 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 13383 -/* 13344 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13347 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13365 -/* 13351 */ MCD_OPC_CheckPredicate, 0, 150, 106, // Skip to: 40641 -/* 13355 */ MCD_OPC_CheckField, 21, 1, 0, 144, 106, // Skip to: 40641 -/* 13361 */ MCD_OPC_Decode, 183, 18, 89, // Opcode: UZP1v4i16 -/* 13365 */ MCD_OPC_FilterValue, 2, 136, 106, // Skip to: 40641 -/* 13369 */ MCD_OPC_CheckPredicate, 0, 132, 106, // Skip to: 40641 -/* 13373 */ MCD_OPC_CheckField, 21, 1, 0, 126, 106, // Skip to: 40641 -/* 13379 */ MCD_OPC_Decode, 185, 18, 112, // Opcode: UZP1v8i16 -/* 13383 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 13460 -/* 13387 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13390 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 13407 -/* 13394 */ MCD_OPC_CheckPredicate, 0, 107, 106, // Skip to: 40641 -/* 13398 */ MCD_OPC_CheckField, 21, 1, 1, 101, 106, // Skip to: 40641 -/* 13404 */ MCD_OPC_Decode, 119, 89, // Opcode: BICv8i8 -/* 13407 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13425 -/* 13411 */ MCD_OPC_CheckPredicate, 0, 90, 106, // Skip to: 40641 -/* 13415 */ MCD_OPC_CheckField, 21, 1, 1, 84, 106, // Skip to: 40641 -/* 13421 */ MCD_OPC_Decode, 129, 1, 109, // Opcode: BSLv8i8 -/* 13425 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 13442 -/* 13429 */ MCD_OPC_CheckPredicate, 0, 72, 106, // Skip to: 40641 -/* 13433 */ MCD_OPC_CheckField, 21, 1, 1, 66, 106, // Skip to: 40641 -/* 13439 */ MCD_OPC_Decode, 114, 112, // Opcode: BICv16i8 -/* 13442 */ MCD_OPC_FilterValue, 3, 59, 106, // Skip to: 40641 -/* 13446 */ MCD_OPC_CheckPredicate, 0, 55, 106, // Skip to: 40641 -/* 13450 */ MCD_OPC_CheckField, 21, 1, 1, 49, 106, // Skip to: 40641 -/* 13456 */ MCD_OPC_Decode, 128, 1, 120, // Opcode: BSLv16i8 -/* 13460 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 13539 -/* 13464 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13467 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13485 -/* 13471 */ MCD_OPC_CheckPredicate, 0, 30, 106, // Skip to: 40641 -/* 13475 */ MCD_OPC_CheckField, 21, 1, 1, 24, 106, // Skip to: 40641 -/* 13481 */ MCD_OPC_Decode, 165, 13, 85, // Opcode: SSUBLv4i16_v4i32 -/* 13485 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13503 -/* 13489 */ MCD_OPC_CheckPredicate, 0, 12, 106, // Skip to: 40641 -/* 13493 */ MCD_OPC_CheckField, 21, 1, 1, 6, 106, // Skip to: 40641 -/* 13499 */ MCD_OPC_Decode, 170, 18, 85, // Opcode: USUBLv4i16_v4i32 -/* 13503 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13521 -/* 13507 */ MCD_OPC_CheckPredicate, 0, 250, 105, // Skip to: 40641 -/* 13511 */ MCD_OPC_CheckField, 21, 1, 1, 244, 105, // Skip to: 40641 -/* 13517 */ MCD_OPC_Decode, 167, 13, 112, // Opcode: SSUBLv8i16_v4i32 -/* 13521 */ MCD_OPC_FilterValue, 3, 236, 105, // Skip to: 40641 -/* 13525 */ MCD_OPC_CheckPredicate, 0, 232, 105, // Skip to: 40641 -/* 13529 */ MCD_OPC_CheckField, 21, 1, 1, 226, 105, // Skip to: 40641 -/* 13535 */ MCD_OPC_Decode, 172, 18, 112, // Opcode: USUBLv8i16_v4i32 -/* 13539 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 13618 -/* 13543 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13546 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13564 -/* 13550 */ MCD_OPC_CheckPredicate, 0, 207, 105, // Skip to: 40641 -/* 13554 */ MCD_OPC_CheckField, 21, 1, 1, 201, 105, // Skip to: 40641 -/* 13560 */ MCD_OPC_Decode, 192, 10, 89, // Opcode: SHSUBv4i16 -/* 13564 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13582 -/* 13568 */ MCD_OPC_CheckPredicate, 0, 189, 105, // Skip to: 40641 -/* 13572 */ MCD_OPC_CheckField, 21, 1, 1, 183, 105, // Skip to: 40641 -/* 13578 */ MCD_OPC_Decode, 192, 16, 89, // Opcode: UHSUBv4i16 -/* 13582 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13600 -/* 13586 */ MCD_OPC_CheckPredicate, 0, 171, 105, // Skip to: 40641 -/* 13590 */ MCD_OPC_CheckField, 21, 1, 1, 165, 105, // Skip to: 40641 -/* 13596 */ MCD_OPC_Decode, 194, 10, 112, // Opcode: SHSUBv8i16 -/* 13600 */ MCD_OPC_FilterValue, 3, 157, 105, // Skip to: 40641 -/* 13604 */ MCD_OPC_CheckPredicate, 0, 153, 105, // Skip to: 40641 -/* 13608 */ MCD_OPC_CheckField, 21, 1, 1, 147, 105, // Skip to: 40641 -/* 13614 */ MCD_OPC_Decode, 194, 16, 112, // Opcode: UHSUBv8i16 -/* 13618 */ MCD_OPC_FilterValue, 10, 165, 0, // Skip to: 13787 -/* 13622 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13625 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 13675 -/* 13629 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13632 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13644 -/* 13636 */ MCD_OPC_CheckPredicate, 0, 121, 105, // Skip to: 40641 -/* 13640 */ MCD_OPC_Decode, 224, 15, 89, // Opcode: TRN1v4i16 -/* 13644 */ MCD_OPC_FilterValue, 1, 113, 105, // Skip to: 40641 -/* 13648 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 13651 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13663 -/* 13655 */ MCD_OPC_CheckPredicate, 0, 102, 105, // Skip to: 40641 -/* 13659 */ MCD_OPC_Decode, 233, 9, 90, // Opcode: SADDLPv4i16_v2i32 -/* 13663 */ MCD_OPC_FilterValue, 1, 94, 105, // Skip to: 40641 -/* 13667 */ MCD_OPC_CheckPredicate, 0, 90, 105, // Skip to: 40641 -/* 13671 */ MCD_OPC_Decode, 196, 18, 95, // Opcode: XTNv4i16 -/* 13675 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 13706 -/* 13679 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 13682 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 13694 -/* 13686 */ MCD_OPC_CheckPredicate, 0, 71, 105, // Skip to: 40641 -/* 13690 */ MCD_OPC_Decode, 139, 16, 90, // Opcode: UADDLPv4i16_v2i32 -/* 13694 */ MCD_OPC_FilterValue, 33, 63, 105, // Skip to: 40641 -/* 13698 */ MCD_OPC_CheckPredicate, 0, 59, 105, // Skip to: 40641 -/* 13702 */ MCD_OPC_Decode, 219, 12, 95, // Opcode: SQXTUNv4i16 -/* 13706 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 13756 -/* 13710 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 13713 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13725 -/* 13717 */ MCD_OPC_CheckPredicate, 0, 40, 105, // Skip to: 40641 -/* 13721 */ MCD_OPC_Decode, 226, 15, 112, // Opcode: TRN1v8i16 -/* 13725 */ MCD_OPC_FilterValue, 1, 32, 105, // Skip to: 40641 -/* 13729 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 13732 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 13744 -/* 13736 */ MCD_OPC_CheckPredicate, 0, 21, 105, // Skip to: 40641 -/* 13740 */ MCD_OPC_Decode, 235, 9, 117, // Opcode: SADDLPv8i16_v4i32 -/* 13744 */ MCD_OPC_FilterValue, 1, 13, 105, // Skip to: 40641 -/* 13748 */ MCD_OPC_CheckPredicate, 0, 9, 105, // Skip to: 40641 -/* 13752 */ MCD_OPC_Decode, 198, 18, 126, // Opcode: XTNv8i16 -/* 13756 */ MCD_OPC_FilterValue, 3, 1, 105, // Skip to: 40641 -/* 13760 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 13763 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 13775 -/* 13767 */ MCD_OPC_CheckPredicate, 0, 246, 104, // Skip to: 40641 -/* 13771 */ MCD_OPC_Decode, 141, 16, 117, // Opcode: UADDLPv8i16_v4i32 -/* 13775 */ MCD_OPC_FilterValue, 33, 238, 104, // Skip to: 40641 -/* 13779 */ MCD_OPC_CheckPredicate, 0, 234, 104, // Skip to: 40641 -/* 13783 */ MCD_OPC_Decode, 221, 12, 126, // Opcode: SQXTUNv8i16 -/* 13787 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 13866 -/* 13791 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13794 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13812 -/* 13798 */ MCD_OPC_CheckPredicate, 0, 215, 104, // Skip to: 40641 -/* 13802 */ MCD_OPC_CheckField, 21, 1, 1, 209, 104, // Skip to: 40641 -/* 13808 */ MCD_OPC_Decode, 201, 12, 89, // Opcode: SQSUBv4i16 -/* 13812 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13830 -/* 13816 */ MCD_OPC_CheckPredicate, 0, 197, 104, // Skip to: 40641 -/* 13820 */ MCD_OPC_CheckField, 21, 1, 1, 191, 104, // Skip to: 40641 -/* 13826 */ MCD_OPC_Decode, 208, 17, 89, // Opcode: UQSUBv4i16 -/* 13830 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13848 -/* 13834 */ MCD_OPC_CheckPredicate, 0, 179, 104, // Skip to: 40641 -/* 13838 */ MCD_OPC_CheckField, 21, 1, 1, 173, 104, // Skip to: 40641 -/* 13844 */ MCD_OPC_Decode, 203, 12, 112, // Opcode: SQSUBv8i16 -/* 13848 */ MCD_OPC_FilterValue, 3, 165, 104, // Skip to: 40641 -/* 13852 */ MCD_OPC_CheckPredicate, 0, 161, 104, // Skip to: 40641 -/* 13856 */ MCD_OPC_CheckField, 21, 1, 1, 155, 104, // Skip to: 40641 -/* 13862 */ MCD_OPC_Decode, 210, 17, 112, // Opcode: UQSUBv8i16 -/* 13866 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 13945 -/* 13870 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13873 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13891 -/* 13877 */ MCD_OPC_CheckPredicate, 0, 136, 104, // Skip to: 40641 -/* 13881 */ MCD_OPC_CheckField, 21, 1, 1, 130, 104, // Skip to: 40641 -/* 13887 */ MCD_OPC_Decode, 171, 13, 93, // Opcode: SSUBWv4i16_v4i32 -/* 13891 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13909 -/* 13895 */ MCD_OPC_CheckPredicate, 0, 118, 104, // Skip to: 40641 -/* 13899 */ MCD_OPC_CheckField, 21, 1, 1, 112, 104, // Skip to: 40641 -/* 13905 */ MCD_OPC_Decode, 176, 18, 93, // Opcode: USUBWv4i16_v4i32 -/* 13909 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 13927 -/* 13913 */ MCD_OPC_CheckPredicate, 0, 100, 104, // Skip to: 40641 -/* 13917 */ MCD_OPC_CheckField, 21, 1, 1, 94, 104, // Skip to: 40641 -/* 13923 */ MCD_OPC_Decode, 173, 13, 112, // Opcode: SSUBWv8i16_v4i32 -/* 13927 */ MCD_OPC_FilterValue, 3, 86, 104, // Skip to: 40641 -/* 13931 */ MCD_OPC_CheckPredicate, 0, 82, 104, // Skip to: 40641 -/* 13935 */ MCD_OPC_CheckField, 21, 1, 1, 76, 104, // Skip to: 40641 -/* 13941 */ MCD_OPC_Decode, 178, 18, 112, // Opcode: USUBWv8i16_v4i32 -/* 13945 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 14024 -/* 13949 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 13952 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 13970 -/* 13956 */ MCD_OPC_CheckPredicate, 0, 57, 104, // Skip to: 40641 -/* 13960 */ MCD_OPC_CheckField, 21, 1, 1, 51, 104, // Skip to: 40641 -/* 13966 */ MCD_OPC_Decode, 200, 1, 89, // Opcode: CMGTv4i16 -/* 13970 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 13988 -/* 13974 */ MCD_OPC_CheckPredicate, 0, 39, 104, // Skip to: 40641 -/* 13978 */ MCD_OPC_CheckField, 21, 1, 1, 33, 104, // Skip to: 40641 -/* 13984 */ MCD_OPC_Decode, 212, 1, 89, // Opcode: CMHIv4i16 -/* 13988 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14006 -/* 13992 */ MCD_OPC_CheckPredicate, 0, 21, 104, // Skip to: 40641 -/* 13996 */ MCD_OPC_CheckField, 21, 1, 1, 15, 104, // Skip to: 40641 -/* 14002 */ MCD_OPC_Decode, 204, 1, 112, // Opcode: CMGTv8i16 -/* 14006 */ MCD_OPC_FilterValue, 3, 7, 104, // Skip to: 40641 -/* 14010 */ MCD_OPC_CheckPredicate, 0, 3, 104, // Skip to: 40641 -/* 14014 */ MCD_OPC_CheckField, 21, 1, 1, 253, 103, // Skip to: 40641 -/* 14020 */ MCD_OPC_Decode, 214, 1, 112, // Opcode: CMHIv8i16 -/* 14024 */ MCD_OPC_FilterValue, 14, 193, 0, // Skip to: 14221 -/* 14028 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14031 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 14082 -/* 14035 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 14038 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14050 -/* 14042 */ MCD_OPC_CheckPredicate, 0, 227, 103, // Skip to: 40641 -/* 14046 */ MCD_OPC_Decode, 203, 18, 89, // Opcode: ZIP1v4i16 -/* 14050 */ MCD_OPC_FilterValue, 1, 219, 103, // Skip to: 40641 -/* 14054 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14057 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14069 -/* 14061 */ MCD_OPC_CheckPredicate, 0, 208, 103, // Skip to: 40641 -/* 14065 */ MCD_OPC_Decode, 190, 15, 99, // Opcode: SUQADDv4i16 -/* 14069 */ MCD_OPC_FilterValue, 16, 200, 103, // Skip to: 40641 -/* 14073 */ MCD_OPC_CheckPredicate, 0, 196, 103, // Skip to: 40641 -/* 14077 */ MCD_OPC_Decode, 238, 9, 144, 1, // Opcode: SADDLVv4i16v -/* 14082 */ MCD_OPC_FilterValue, 1, 40, 0, // Skip to: 14126 -/* 14086 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 14089 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14101 -/* 14093 */ MCD_OPC_CheckPredicate, 0, 176, 103, // Skip to: 40641 -/* 14097 */ MCD_OPC_Decode, 156, 18, 99, // Opcode: USQADDv4i16 -/* 14101 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 14113 -/* 14105 */ MCD_OPC_CheckPredicate, 0, 164, 103, // Skip to: 40641 -/* 14109 */ MCD_OPC_Decode, 172, 10, 108, // Opcode: SHLLv4i16 -/* 14113 */ MCD_OPC_FilterValue, 48, 156, 103, // Skip to: 40641 -/* 14117 */ MCD_OPC_CheckPredicate, 0, 152, 103, // Skip to: 40641 -/* 14121 */ MCD_OPC_Decode, 144, 16, 144, 1, // Opcode: UADDLVv4i16v -/* 14126 */ MCD_OPC_FilterValue, 2, 47, 0, // Skip to: 14177 -/* 14130 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 14133 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14145 -/* 14137 */ MCD_OPC_CheckPredicate, 0, 132, 103, // Skip to: 40641 -/* 14141 */ MCD_OPC_Decode, 205, 18, 112, // Opcode: ZIP1v8i16 -/* 14145 */ MCD_OPC_FilterValue, 1, 124, 103, // Skip to: 40641 -/* 14149 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 14152 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 14164 -/* 14156 */ MCD_OPC_CheckPredicate, 0, 113, 103, // Skip to: 40641 -/* 14160 */ MCD_OPC_Decode, 192, 15, 126, // Opcode: SUQADDv8i16 -/* 14164 */ MCD_OPC_FilterValue, 16, 105, 103, // Skip to: 40641 -/* 14168 */ MCD_OPC_CheckPredicate, 0, 101, 103, // Skip to: 40641 -/* 14172 */ MCD_OPC_Decode, 240, 9, 139, 1, // Opcode: SADDLVv8i16v -/* 14177 */ MCD_OPC_FilterValue, 3, 92, 103, // Skip to: 40641 -/* 14181 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 14184 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14196 -/* 14188 */ MCD_OPC_CheckPredicate, 0, 81, 103, // Skip to: 40641 -/* 14192 */ MCD_OPC_Decode, 158, 18, 126, // Opcode: USQADDv8i16 -/* 14196 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 14208 -/* 14200 */ MCD_OPC_CheckPredicate, 0, 69, 103, // Skip to: 40641 -/* 14204 */ MCD_OPC_Decode, 174, 10, 117, // Opcode: SHLLv8i16 -/* 14208 */ MCD_OPC_FilterValue, 48, 61, 103, // Skip to: 40641 -/* 14212 */ MCD_OPC_CheckPredicate, 0, 57, 103, // Skip to: 40641 -/* 14216 */ MCD_OPC_Decode, 146, 16, 139, 1, // Opcode: UADDLVv8i16v -/* 14221 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 14300 -/* 14225 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14228 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14246 -/* 14232 */ MCD_OPC_CheckPredicate, 0, 37, 103, // Skip to: 40641 -/* 14236 */ MCD_OPC_CheckField, 21, 1, 1, 31, 103, // Skip to: 40641 -/* 14242 */ MCD_OPC_Decode, 184, 1, 89, // Opcode: CMGEv4i16 -/* 14246 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14264 -/* 14250 */ MCD_OPC_CheckPredicate, 0, 19, 103, // Skip to: 40641 -/* 14254 */ MCD_OPC_CheckField, 21, 1, 1, 13, 103, // Skip to: 40641 -/* 14260 */ MCD_OPC_Decode, 220, 1, 89, // Opcode: CMHSv4i16 -/* 14264 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14282 -/* 14268 */ MCD_OPC_CheckPredicate, 0, 1, 103, // Skip to: 40641 -/* 14272 */ MCD_OPC_CheckField, 21, 1, 1, 251, 102, // Skip to: 40641 -/* 14278 */ MCD_OPC_Decode, 188, 1, 112, // Opcode: CMGEv8i16 -/* 14282 */ MCD_OPC_FilterValue, 3, 243, 102, // Skip to: 40641 -/* 14286 */ MCD_OPC_CheckPredicate, 0, 239, 102, // Skip to: 40641 -/* 14290 */ MCD_OPC_CheckField, 21, 1, 1, 233, 102, // Skip to: 40641 -/* 14296 */ MCD_OPC_Decode, 222, 1, 112, // Opcode: CMHSv8i16 -/* 14300 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 14377 -/* 14304 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14307 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 14324 -/* 14311 */ MCD_OPC_CheckPredicate, 0, 214, 102, // Skip to: 40641 -/* 14315 */ MCD_OPC_CheckField, 21, 1, 1, 208, 102, // Skip to: 40641 -/* 14321 */ MCD_OPC_Decode, 36, 103, // Opcode: ADDHNv4i32_v4i16 -/* 14324 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14342 -/* 14328 */ MCD_OPC_CheckPredicate, 0, 197, 102, // Skip to: 40641 -/* 14332 */ MCD_OPC_CheckField, 21, 1, 1, 191, 102, // Skip to: 40641 -/* 14338 */ MCD_OPC_Decode, 160, 9, 103, // Opcode: RADDHNv4i32_v4i16 -/* 14342 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 14359 -/* 14346 */ MCD_OPC_CheckPredicate, 0, 179, 102, // Skip to: 40641 -/* 14350 */ MCD_OPC_CheckField, 21, 1, 1, 173, 102, // Skip to: 40641 -/* 14356 */ MCD_OPC_Decode, 37, 120, // Opcode: ADDHNv4i32_v8i16 -/* 14359 */ MCD_OPC_FilterValue, 3, 166, 102, // Skip to: 40641 -/* 14363 */ MCD_OPC_CheckPredicate, 0, 162, 102, // Skip to: 40641 -/* 14367 */ MCD_OPC_CheckField, 21, 1, 1, 156, 102, // Skip to: 40641 -/* 14373 */ MCD_OPC_Decode, 161, 9, 120, // Opcode: RADDHNv4i32_v8i16 -/* 14377 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 14456 -/* 14381 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14384 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14402 -/* 14388 */ MCD_OPC_CheckPredicate, 0, 137, 102, // Skip to: 40641 -/* 14392 */ MCD_OPC_CheckField, 21, 1, 1, 131, 102, // Skip to: 40641 -/* 14398 */ MCD_OPC_Decode, 143, 13, 89, // Opcode: SSHLv4i16 -/* 14402 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14420 -/* 14406 */ MCD_OPC_CheckPredicate, 0, 119, 102, // Skip to: 40641 -/* 14410 */ MCD_OPC_CheckField, 21, 1, 1, 113, 102, // Skip to: 40641 -/* 14416 */ MCD_OPC_Decode, 137, 18, 89, // Opcode: USHLv4i16 -/* 14420 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14438 -/* 14424 */ MCD_OPC_CheckPredicate, 0, 101, 102, // Skip to: 40641 -/* 14428 */ MCD_OPC_CheckField, 21, 1, 1, 95, 102, // Skip to: 40641 -/* 14434 */ MCD_OPC_Decode, 145, 13, 112, // Opcode: SSHLv8i16 -/* 14438 */ MCD_OPC_FilterValue, 3, 87, 102, // Skip to: 40641 -/* 14442 */ MCD_OPC_CheckPredicate, 0, 83, 102, // Skip to: 40641 -/* 14446 */ MCD_OPC_CheckField, 21, 1, 1, 77, 102, // Skip to: 40641 -/* 14452 */ MCD_OPC_Decode, 139, 18, 112, // Opcode: USHLv8i16 -/* 14456 */ MCD_OPC_FilterValue, 18, 127, 0, // Skip to: 14587 -/* 14460 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14463 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 14494 -/* 14467 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 14470 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14482 -/* 14474 */ MCD_OPC_CheckPredicate, 0, 51, 102, // Skip to: 40641 -/* 14478 */ MCD_OPC_Decode, 148, 1, 90, // Opcode: CLSv4i16 -/* 14482 */ MCD_OPC_FilterValue, 33, 43, 102, // Skip to: 40641 -/* 14486 */ MCD_OPC_CheckPredicate, 0, 39, 102, // Skip to: 40641 -/* 14490 */ MCD_OPC_Decode, 210, 12, 95, // Opcode: SQXTNv4i16 -/* 14494 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 14525 -/* 14498 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 14501 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14513 -/* 14505 */ MCD_OPC_CheckPredicate, 0, 20, 102, // Skip to: 40641 -/* 14509 */ MCD_OPC_Decode, 156, 1, 90, // Opcode: CLZv4i16 -/* 14513 */ MCD_OPC_FilterValue, 33, 12, 102, // Skip to: 40641 -/* 14517 */ MCD_OPC_CheckPredicate, 0, 8, 102, // Skip to: 40641 -/* 14521 */ MCD_OPC_Decode, 217, 17, 95, // Opcode: UQXTNv4i16 -/* 14525 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 14556 -/* 14529 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 14532 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14544 -/* 14536 */ MCD_OPC_CheckPredicate, 0, 245, 101, // Skip to: 40641 -/* 14540 */ MCD_OPC_Decode, 150, 1, 117, // Opcode: CLSv8i16 -/* 14544 */ MCD_OPC_FilterValue, 33, 237, 101, // Skip to: 40641 -/* 14548 */ MCD_OPC_CheckPredicate, 0, 233, 101, // Skip to: 40641 -/* 14552 */ MCD_OPC_Decode, 212, 12, 126, // Opcode: SQXTNv8i16 -/* 14556 */ MCD_OPC_FilterValue, 3, 225, 101, // Skip to: 40641 -/* 14560 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 14563 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 14575 -/* 14567 */ MCD_OPC_CheckPredicate, 0, 214, 101, // Skip to: 40641 -/* 14571 */ MCD_OPC_Decode, 158, 1, 117, // Opcode: CLZv8i16 -/* 14575 */ MCD_OPC_FilterValue, 33, 206, 101, // Skip to: 40641 -/* 14579 */ MCD_OPC_CheckPredicate, 0, 202, 101, // Skip to: 40641 -/* 14583 */ MCD_OPC_Decode, 219, 17, 126, // Opcode: UQXTNv8i16 -/* 14587 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 14666 -/* 14591 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14594 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14612 -/* 14598 */ MCD_OPC_CheckPredicate, 0, 183, 101, // Skip to: 40641 -/* 14602 */ MCD_OPC_CheckField, 21, 1, 1, 177, 101, // Skip to: 40641 -/* 14608 */ MCD_OPC_Decode, 168, 12, 89, // Opcode: SQSHLv4i16 -/* 14612 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14630 -/* 14616 */ MCD_OPC_CheckPredicate, 0, 165, 101, // Skip to: 40641 -/* 14620 */ MCD_OPC_CheckField, 21, 1, 1, 159, 101, // Skip to: 40641 -/* 14626 */ MCD_OPC_Decode, 184, 17, 89, // Opcode: UQSHLv4i16 -/* 14630 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14648 -/* 14634 */ MCD_OPC_CheckPredicate, 0, 147, 101, // Skip to: 40641 -/* 14638 */ MCD_OPC_CheckField, 21, 1, 1, 141, 101, // Skip to: 40641 -/* 14644 */ MCD_OPC_Decode, 172, 12, 112, // Opcode: SQSHLv8i16 -/* 14648 */ MCD_OPC_FilterValue, 3, 133, 101, // Skip to: 40641 -/* 14652 */ MCD_OPC_CheckPredicate, 0, 129, 101, // Skip to: 40641 -/* 14656 */ MCD_OPC_CheckField, 21, 1, 1, 123, 101, // Skip to: 40641 -/* 14662 */ MCD_OPC_Decode, 188, 17, 112, // Opcode: UQSHLv8i16 -/* 14666 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 14745 -/* 14670 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14673 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14691 -/* 14677 */ MCD_OPC_CheckPredicate, 0, 104, 101, // Skip to: 40641 -/* 14681 */ MCD_OPC_CheckField, 21, 1, 1, 98, 101, // Skip to: 40641 -/* 14687 */ MCD_OPC_Decode, 203, 9, 105, // Opcode: SABALv4i16_v4i32 -/* 14691 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14709 -/* 14695 */ MCD_OPC_CheckPredicate, 0, 86, 101, // Skip to: 40641 -/* 14699 */ MCD_OPC_CheckField, 21, 1, 1, 80, 101, // Skip to: 40641 -/* 14705 */ MCD_OPC_Decode, 237, 15, 105, // Opcode: UABALv4i16_v4i32 -/* 14709 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14727 -/* 14713 */ MCD_OPC_CheckPredicate, 0, 68, 101, // Skip to: 40641 -/* 14717 */ MCD_OPC_CheckField, 21, 1, 1, 62, 101, // Skip to: 40641 -/* 14723 */ MCD_OPC_Decode, 205, 9, 120, // Opcode: SABALv8i16_v4i32 -/* 14727 */ MCD_OPC_FilterValue, 3, 54, 101, // Skip to: 40641 -/* 14731 */ MCD_OPC_CheckPredicate, 0, 50, 101, // Skip to: 40641 -/* 14735 */ MCD_OPC_CheckField, 21, 1, 1, 44, 101, // Skip to: 40641 -/* 14741 */ MCD_OPC_Decode, 239, 15, 120, // Opcode: UABALv8i16_v4i32 -/* 14745 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 14824 -/* 14749 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14752 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14770 -/* 14756 */ MCD_OPC_CheckPredicate, 0, 25, 101, // Skip to: 40641 -/* 14760 */ MCD_OPC_CheckField, 21, 1, 1, 19, 101, // Skip to: 40641 -/* 14766 */ MCD_OPC_Decode, 241, 12, 89, // Opcode: SRSHLv4i16 -/* 14770 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14788 -/* 14774 */ MCD_OPC_CheckPredicate, 0, 7, 101, // Skip to: 40641 -/* 14778 */ MCD_OPC_CheckField, 21, 1, 1, 1, 101, // Skip to: 40641 -/* 14784 */ MCD_OPC_Decode, 233, 17, 89, // Opcode: URSHLv4i16 -/* 14788 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14806 -/* 14792 */ MCD_OPC_CheckPredicate, 0, 245, 100, // Skip to: 40641 -/* 14796 */ MCD_OPC_CheckField, 21, 1, 1, 239, 100, // Skip to: 40641 -/* 14802 */ MCD_OPC_Decode, 243, 12, 112, // Opcode: SRSHLv8i16 -/* 14806 */ MCD_OPC_FilterValue, 3, 231, 100, // Skip to: 40641 -/* 14810 */ MCD_OPC_CheckPredicate, 0, 227, 100, // Skip to: 40641 -/* 14814 */ MCD_OPC_CheckField, 21, 1, 1, 221, 100, // Skip to: 40641 -/* 14820 */ MCD_OPC_Decode, 235, 17, 112, // Opcode: URSHLv8i16 -/* 14824 */ MCD_OPC_FilterValue, 22, 75, 0, // Skip to: 14903 -/* 14828 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14831 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14849 -/* 14835 */ MCD_OPC_CheckPredicate, 0, 202, 100, // Skip to: 40641 -/* 14839 */ MCD_OPC_CheckField, 21, 1, 0, 196, 100, // Skip to: 40641 -/* 14845 */ MCD_OPC_Decode, 190, 18, 89, // Opcode: UZP2v4i16 -/* 14849 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14867 -/* 14853 */ MCD_OPC_CheckPredicate, 0, 184, 100, // Skip to: 40641 -/* 14857 */ MCD_OPC_CheckField, 16, 6, 32, 178, 100, // Skip to: 40641 -/* 14863 */ MCD_OPC_Decode, 167, 9, 90, // Opcode: RBITv8i8 -/* 14867 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14885 -/* 14871 */ MCD_OPC_CheckPredicate, 0, 166, 100, // Skip to: 40641 -/* 14875 */ MCD_OPC_CheckField, 21, 1, 0, 160, 100, // Skip to: 40641 -/* 14881 */ MCD_OPC_Decode, 192, 18, 112, // Opcode: UZP2v8i16 -/* 14885 */ MCD_OPC_FilterValue, 3, 152, 100, // Skip to: 40641 -/* 14889 */ MCD_OPC_CheckPredicate, 0, 148, 100, // Skip to: 40641 -/* 14893 */ MCD_OPC_CheckField, 16, 6, 32, 142, 100, // Skip to: 40641 -/* 14899 */ MCD_OPC_Decode, 166, 9, 117, // Opcode: RBITv16i8 -/* 14903 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 14982 -/* 14907 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14910 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 14928 -/* 14914 */ MCD_OPC_CheckPredicate, 0, 123, 100, // Skip to: 40641 -/* 14918 */ MCD_OPC_CheckField, 21, 1, 1, 117, 100, // Skip to: 40641 -/* 14924 */ MCD_OPC_Decode, 249, 11, 89, // Opcode: SQRSHLv4i16 -/* 14928 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 14946 -/* 14932 */ MCD_OPC_CheckPredicate, 0, 105, 100, // Skip to: 40641 -/* 14936 */ MCD_OPC_CheckField, 21, 1, 1, 99, 100, // Skip to: 40641 -/* 14942 */ MCD_OPC_Decode, 157, 17, 89, // Opcode: UQRSHLv4i16 -/* 14946 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 14964 -/* 14950 */ MCD_OPC_CheckPredicate, 0, 87, 100, // Skip to: 40641 -/* 14954 */ MCD_OPC_CheckField, 21, 1, 1, 81, 100, // Skip to: 40641 -/* 14960 */ MCD_OPC_Decode, 251, 11, 112, // Opcode: SQRSHLv8i16 -/* 14964 */ MCD_OPC_FilterValue, 3, 73, 100, // Skip to: 40641 -/* 14968 */ MCD_OPC_CheckPredicate, 0, 69, 100, // Skip to: 40641 -/* 14972 */ MCD_OPC_CheckField, 21, 1, 1, 63, 100, // Skip to: 40641 -/* 14978 */ MCD_OPC_Decode, 159, 17, 112, // Opcode: UQRSHLv8i16 -/* 14982 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 15061 -/* 14986 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 14989 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15007 -/* 14993 */ MCD_OPC_CheckPredicate, 0, 44, 100, // Skip to: 40641 -/* 14997 */ MCD_OPC_CheckField, 21, 1, 1, 38, 100, // Skip to: 40641 -/* 15003 */ MCD_OPC_Decode, 153, 15, 103, // Opcode: SUBHNv4i32_v4i16 -/* 15007 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15025 -/* 15011 */ MCD_OPC_CheckPredicate, 0, 26, 100, // Skip to: 40641 -/* 15015 */ MCD_OPC_CheckField, 21, 1, 1, 20, 100, // Skip to: 40641 -/* 15021 */ MCD_OPC_Decode, 197, 9, 103, // Opcode: RSUBHNv4i32_v4i16 -/* 15025 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15043 -/* 15029 */ MCD_OPC_CheckPredicate, 0, 8, 100, // Skip to: 40641 -/* 15033 */ MCD_OPC_CheckField, 21, 1, 1, 2, 100, // Skip to: 40641 -/* 15039 */ MCD_OPC_Decode, 154, 15, 120, // Opcode: SUBHNv4i32_v8i16 -/* 15043 */ MCD_OPC_FilterValue, 3, 250, 99, // Skip to: 40641 -/* 15047 */ MCD_OPC_CheckPredicate, 0, 246, 99, // Skip to: 40641 -/* 15051 */ MCD_OPC_CheckField, 21, 1, 1, 240, 99, // Skip to: 40641 -/* 15057 */ MCD_OPC_Decode, 198, 9, 120, // Opcode: RSUBHNv4i32_v8i16 -/* 15061 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 15140 -/* 15065 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15068 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15086 -/* 15072 */ MCD_OPC_CheckPredicate, 0, 221, 99, // Skip to: 40641 -/* 15076 */ MCD_OPC_CheckField, 21, 1, 1, 215, 99, // Skip to: 40641 -/* 15082 */ MCD_OPC_Decode, 218, 10, 89, // Opcode: SMAXv4i16 -/* 15086 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15104 -/* 15090 */ MCD_OPC_CheckPredicate, 0, 203, 99, // Skip to: 40641 -/* 15094 */ MCD_OPC_CheckField, 21, 1, 1, 197, 99, // Skip to: 40641 -/* 15100 */ MCD_OPC_Decode, 210, 16, 89, // Opcode: UMAXv4i16 -/* 15104 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15122 -/* 15108 */ MCD_OPC_CheckPredicate, 0, 185, 99, // Skip to: 40641 -/* 15112 */ MCD_OPC_CheckField, 21, 1, 1, 179, 99, // Skip to: 40641 -/* 15118 */ MCD_OPC_Decode, 220, 10, 112, // Opcode: SMAXv8i16 -/* 15122 */ MCD_OPC_FilterValue, 3, 171, 99, // Skip to: 40641 -/* 15126 */ MCD_OPC_CheckPredicate, 0, 167, 99, // Skip to: 40641 -/* 15130 */ MCD_OPC_CheckField, 21, 1, 1, 161, 99, // Skip to: 40641 -/* 15136 */ MCD_OPC_Decode, 212, 16, 112, // Opcode: UMAXv8i16 -/* 15140 */ MCD_OPC_FilterValue, 26, 165, 0, // Skip to: 15309 -/* 15144 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15147 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15197 -/* 15151 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 15154 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15166 -/* 15158 */ MCD_OPC_CheckPredicate, 0, 135, 99, // Skip to: 40641 -/* 15162 */ MCD_OPC_Decode, 231, 15, 89, // Opcode: TRN2v4i16 -/* 15166 */ MCD_OPC_FilterValue, 1, 127, 99, // Skip to: 40641 -/* 15170 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15173 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15185 -/* 15177 */ MCD_OPC_CheckPredicate, 0, 116, 99, // Skip to: 40641 -/* 15181 */ MCD_OPC_Decode, 227, 9, 99, // Opcode: SADALPv4i16_v2i32 -/* 15185 */ MCD_OPC_FilterValue, 1, 108, 99, // Skip to: 40641 -/* 15189 */ MCD_OPC_CheckPredicate, 0, 104, 99, // Skip to: 40641 -/* 15193 */ MCD_OPC_Decode, 198, 3, 95, // Opcode: FCVTNv2i32 -/* 15197 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 15228 -/* 15201 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 15204 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15216 -/* 15208 */ MCD_OPC_CheckPredicate, 0, 85, 99, // Skip to: 40641 -/* 15212 */ MCD_OPC_Decode, 133, 16, 99, // Opcode: UADALPv4i16_v2i32 -/* 15216 */ MCD_OPC_FilterValue, 33, 77, 99, // Skip to: 40641 -/* 15220 */ MCD_OPC_CheckPredicate, 0, 73, 99, // Skip to: 40641 -/* 15224 */ MCD_OPC_Decode, 223, 3, 95, // Opcode: FCVTXNv2f32 -/* 15228 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 15278 -/* 15232 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 15235 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15247 -/* 15239 */ MCD_OPC_CheckPredicate, 0, 54, 99, // Skip to: 40641 -/* 15243 */ MCD_OPC_Decode, 233, 15, 112, // Opcode: TRN2v8i16 -/* 15247 */ MCD_OPC_FilterValue, 1, 46, 99, // Skip to: 40641 -/* 15251 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15254 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15266 -/* 15258 */ MCD_OPC_CheckPredicate, 0, 35, 99, // Skip to: 40641 -/* 15262 */ MCD_OPC_Decode, 229, 9, 126, // Opcode: SADALPv8i16_v4i32 -/* 15266 */ MCD_OPC_FilterValue, 1, 27, 99, // Skip to: 40641 -/* 15270 */ MCD_OPC_CheckPredicate, 0, 23, 99, // Skip to: 40641 -/* 15274 */ MCD_OPC_Decode, 200, 3, 126, // Opcode: FCVTNv4i32 -/* 15278 */ MCD_OPC_FilterValue, 3, 15, 99, // Skip to: 40641 -/* 15282 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 15285 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15297 -/* 15289 */ MCD_OPC_CheckPredicate, 0, 4, 99, // Skip to: 40641 -/* 15293 */ MCD_OPC_Decode, 135, 16, 126, // Opcode: UADALPv8i16_v4i32 -/* 15297 */ MCD_OPC_FilterValue, 33, 252, 98, // Skip to: 40641 -/* 15301 */ MCD_OPC_CheckPredicate, 0, 248, 98, // Skip to: 40641 -/* 15305 */ MCD_OPC_Decode, 224, 3, 126, // Opcode: FCVTXNv4f32 -/* 15309 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 15388 -/* 15313 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15316 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15334 -/* 15320 */ MCD_OPC_CheckPredicate, 0, 229, 98, // Skip to: 40641 -/* 15324 */ MCD_OPC_CheckField, 21, 1, 1, 223, 98, // Skip to: 40641 -/* 15330 */ MCD_OPC_Decode, 236, 10, 89, // Opcode: SMINv4i16 -/* 15334 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15352 -/* 15338 */ MCD_OPC_CheckPredicate, 0, 211, 98, // Skip to: 40641 -/* 15342 */ MCD_OPC_CheckField, 21, 1, 1, 205, 98, // Skip to: 40641 -/* 15348 */ MCD_OPC_Decode, 227, 16, 89, // Opcode: UMINv4i16 -/* 15352 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15370 -/* 15356 */ MCD_OPC_CheckPredicate, 0, 193, 98, // Skip to: 40641 -/* 15360 */ MCD_OPC_CheckField, 21, 1, 1, 187, 98, // Skip to: 40641 -/* 15366 */ MCD_OPC_Decode, 238, 10, 112, // Opcode: SMINv8i16 -/* 15370 */ MCD_OPC_FilterValue, 3, 179, 98, // Skip to: 40641 -/* 15374 */ MCD_OPC_CheckPredicate, 0, 175, 98, // Skip to: 40641 -/* 15378 */ MCD_OPC_CheckField, 21, 1, 1, 169, 98, // Skip to: 40641 -/* 15384 */ MCD_OPC_Decode, 229, 16, 112, // Opcode: UMINv8i16 -/* 15388 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 15467 -/* 15392 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15395 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15413 -/* 15399 */ MCD_OPC_CheckPredicate, 0, 150, 98, // Skip to: 40641 -/* 15403 */ MCD_OPC_CheckField, 21, 1, 1, 144, 98, // Skip to: 40641 -/* 15409 */ MCD_OPC_Decode, 215, 9, 85, // Opcode: SABDLv4i16_v4i32 -/* 15413 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15431 -/* 15417 */ MCD_OPC_CheckPredicate, 0, 132, 98, // Skip to: 40641 -/* 15421 */ MCD_OPC_CheckField, 21, 1, 1, 126, 98, // Skip to: 40641 -/* 15427 */ MCD_OPC_Decode, 249, 15, 85, // Opcode: UABDLv4i16_v4i32 -/* 15431 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15449 -/* 15435 */ MCD_OPC_CheckPredicate, 0, 114, 98, // Skip to: 40641 -/* 15439 */ MCD_OPC_CheckField, 21, 1, 1, 108, 98, // Skip to: 40641 -/* 15445 */ MCD_OPC_Decode, 217, 9, 112, // Opcode: SABDLv8i16_v4i32 -/* 15449 */ MCD_OPC_FilterValue, 3, 100, 98, // Skip to: 40641 -/* 15453 */ MCD_OPC_CheckPredicate, 0, 96, 98, // Skip to: 40641 -/* 15457 */ MCD_OPC_CheckField, 21, 1, 1, 90, 98, // Skip to: 40641 -/* 15463 */ MCD_OPC_Decode, 251, 15, 112, // Opcode: UABDLv8i16_v4i32 -/* 15467 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 15546 -/* 15471 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15474 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15492 -/* 15478 */ MCD_OPC_CheckPredicate, 0, 71, 98, // Skip to: 40641 -/* 15482 */ MCD_OPC_CheckField, 21, 1, 1, 65, 98, // Skip to: 40641 -/* 15488 */ MCD_OPC_Decode, 221, 9, 89, // Opcode: SABDv4i16 -/* 15492 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15510 -/* 15496 */ MCD_OPC_CheckPredicate, 0, 53, 98, // Skip to: 40641 -/* 15500 */ MCD_OPC_CheckField, 21, 1, 1, 47, 98, // Skip to: 40641 -/* 15506 */ MCD_OPC_Decode, 255, 15, 89, // Opcode: UABDv4i16 -/* 15510 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15528 -/* 15514 */ MCD_OPC_CheckPredicate, 0, 35, 98, // Skip to: 40641 -/* 15518 */ MCD_OPC_CheckField, 21, 1, 1, 29, 98, // Skip to: 40641 -/* 15524 */ MCD_OPC_Decode, 223, 9, 112, // Opcode: SABDv8i16 -/* 15528 */ MCD_OPC_FilterValue, 3, 21, 98, // Skip to: 40641 -/* 15532 */ MCD_OPC_CheckPredicate, 0, 17, 98, // Skip to: 40641 -/* 15536 */ MCD_OPC_CheckField, 21, 1, 1, 11, 98, // Skip to: 40641 -/* 15542 */ MCD_OPC_Decode, 129, 16, 112, // Opcode: UABDv8i16 -/* 15546 */ MCD_OPC_FilterValue, 30, 139, 0, // Skip to: 15689 -/* 15550 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15553 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 15603 -/* 15557 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 15560 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15572 -/* 15564 */ MCD_OPC_CheckPredicate, 0, 241, 97, // Skip to: 40641 -/* 15568 */ MCD_OPC_Decode, 210, 18, 89, // Opcode: ZIP2v4i16 -/* 15572 */ MCD_OPC_FilterValue, 1, 233, 97, // Skip to: 40641 -/* 15576 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15579 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15591 -/* 15583 */ MCD_OPC_CheckPredicate, 0, 222, 97, // Skip to: 40641 -/* 15587 */ MCD_OPC_Decode, 156, 11, 90, // Opcode: SQABSv4i16 -/* 15591 */ MCD_OPC_FilterValue, 1, 214, 97, // Skip to: 40641 -/* 15595 */ MCD_OPC_CheckPredicate, 0, 210, 97, // Skip to: 40641 -/* 15599 */ MCD_OPC_Decode, 158, 3, 108, // Opcode: FCVTLv2i32 -/* 15603 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15621 -/* 15607 */ MCD_OPC_CheckPredicate, 0, 198, 97, // Skip to: 40641 -/* 15611 */ MCD_OPC_CheckField, 16, 6, 32, 192, 97, // Skip to: 40641 -/* 15617 */ MCD_OPC_Decode, 226, 11, 90, // Opcode: SQNEGv4i16 -/* 15621 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 15671 -/* 15625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 15628 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15640 -/* 15632 */ MCD_OPC_CheckPredicate, 0, 173, 97, // Skip to: 40641 -/* 15636 */ MCD_OPC_Decode, 212, 18, 112, // Opcode: ZIP2v8i16 -/* 15640 */ MCD_OPC_FilterValue, 1, 165, 97, // Skip to: 40641 -/* 15644 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 15647 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 15659 -/* 15651 */ MCD_OPC_CheckPredicate, 0, 154, 97, // Skip to: 40641 -/* 15655 */ MCD_OPC_Decode, 158, 11, 117, // Opcode: SQABSv8i16 -/* 15659 */ MCD_OPC_FilterValue, 1, 146, 97, // Skip to: 40641 -/* 15663 */ MCD_OPC_CheckPredicate, 0, 142, 97, // Skip to: 40641 -/* 15667 */ MCD_OPC_Decode, 160, 3, 117, // Opcode: FCVTLv4i32 -/* 15671 */ MCD_OPC_FilterValue, 3, 134, 97, // Skip to: 40641 -/* 15675 */ MCD_OPC_CheckPredicate, 0, 130, 97, // Skip to: 40641 -/* 15679 */ MCD_OPC_CheckField, 16, 6, 32, 124, 97, // Skip to: 40641 -/* 15685 */ MCD_OPC_Decode, 228, 11, 117, // Opcode: SQNEGv8i16 -/* 15689 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 15768 -/* 15693 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15696 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15714 -/* 15700 */ MCD_OPC_CheckPredicate, 0, 105, 97, // Skip to: 40641 -/* 15704 */ MCD_OPC_CheckField, 21, 1, 1, 99, 97, // Skip to: 40641 -/* 15710 */ MCD_OPC_Decode, 209, 9, 109, // Opcode: SABAv4i16 -/* 15714 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15732 -/* 15718 */ MCD_OPC_CheckPredicate, 0, 87, 97, // Skip to: 40641 -/* 15722 */ MCD_OPC_CheckField, 21, 1, 1, 81, 97, // Skip to: 40641 -/* 15728 */ MCD_OPC_Decode, 243, 15, 109, // Opcode: UABAv4i16 -/* 15732 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15750 -/* 15736 */ MCD_OPC_CheckPredicate, 0, 69, 97, // Skip to: 40641 -/* 15740 */ MCD_OPC_CheckField, 21, 1, 1, 63, 97, // Skip to: 40641 -/* 15746 */ MCD_OPC_Decode, 211, 9, 120, // Opcode: SABAv8i16 -/* 15750 */ MCD_OPC_FilterValue, 3, 55, 97, // Skip to: 40641 -/* 15754 */ MCD_OPC_CheckPredicate, 0, 51, 97, // Skip to: 40641 -/* 15758 */ MCD_OPC_CheckField, 21, 1, 1, 45, 97, // Skip to: 40641 -/* 15764 */ MCD_OPC_Decode, 245, 15, 120, // Opcode: UABAv8i16 -/* 15768 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 15847 -/* 15772 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15775 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15793 -/* 15779 */ MCD_OPC_CheckPredicate, 0, 26, 97, // Skip to: 40641 -/* 15783 */ MCD_OPC_CheckField, 21, 1, 1, 20, 97, // Skip to: 40641 -/* 15789 */ MCD_OPC_Decode, 244, 10, 105, // Opcode: SMLALv4i16_v4i32 -/* 15793 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15811 -/* 15797 */ MCD_OPC_CheckPredicate, 0, 8, 97, // Skip to: 40641 -/* 15801 */ MCD_OPC_CheckField, 21, 1, 1, 2, 97, // Skip to: 40641 -/* 15807 */ MCD_OPC_Decode, 235, 16, 105, // Opcode: UMLALv4i16_v4i32 -/* 15811 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 15829 -/* 15815 */ MCD_OPC_CheckPredicate, 0, 246, 96, // Skip to: 40641 -/* 15819 */ MCD_OPC_CheckField, 21, 1, 1, 240, 96, // Skip to: 40641 -/* 15825 */ MCD_OPC_Decode, 248, 10, 120, // Opcode: SMLALv8i16_v4i32 -/* 15829 */ MCD_OPC_FilterValue, 3, 232, 96, // Skip to: 40641 -/* 15833 */ MCD_OPC_CheckPredicate, 0, 228, 96, // Skip to: 40641 -/* 15837 */ MCD_OPC_CheckField, 21, 1, 1, 222, 96, // Skip to: 40641 -/* 15843 */ MCD_OPC_Decode, 239, 16, 120, // Opcode: UMLALv8i16_v4i32 -/* 15847 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 15924 -/* 15851 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15854 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 15871 -/* 15858 */ MCD_OPC_CheckPredicate, 0, 203, 96, // Skip to: 40641 -/* 15862 */ MCD_OPC_CheckField, 21, 1, 1, 197, 96, // Skip to: 40641 -/* 15868 */ MCD_OPC_Decode, 75, 89, // Opcode: ADDv4i16 -/* 15871 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15889 -/* 15875 */ MCD_OPC_CheckPredicate, 0, 186, 96, // Skip to: 40641 -/* 15879 */ MCD_OPC_CheckField, 21, 1, 1, 180, 96, // Skip to: 40641 -/* 15885 */ MCD_OPC_Decode, 179, 15, 89, // Opcode: SUBv4i16 -/* 15889 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 15906 -/* 15893 */ MCD_OPC_CheckPredicate, 0, 168, 96, // Skip to: 40641 -/* 15897 */ MCD_OPC_CheckField, 21, 1, 1, 162, 96, // Skip to: 40641 -/* 15903 */ MCD_OPC_Decode, 77, 112, // Opcode: ADDv8i16 -/* 15906 */ MCD_OPC_FilterValue, 3, 155, 96, // Skip to: 40641 -/* 15910 */ MCD_OPC_CheckPredicate, 0, 151, 96, // Skip to: 40641 -/* 15914 */ MCD_OPC_CheckField, 21, 1, 1, 145, 96, // Skip to: 40641 -/* 15920 */ MCD_OPC_Decode, 181, 15, 112, // Opcode: SUBv8i16 -/* 15924 */ MCD_OPC_FilterValue, 34, 101, 0, // Skip to: 16029 -/* 15928 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 15931 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 15949 -/* 15935 */ MCD_OPC_CheckPredicate, 0, 126, 96, // Skip to: 40641 -/* 15939 */ MCD_OPC_CheckField, 16, 6, 32, 120, 96, // Skip to: 40641 -/* 15945 */ MCD_OPC_Decode, 201, 1, 90, // Opcode: CMGTv4i16rz -/* 15949 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 15967 -/* 15953 */ MCD_OPC_CheckPredicate, 0, 108, 96, // Skip to: 40641 -/* 15957 */ MCD_OPC_CheckField, 16, 6, 32, 102, 96, // Skip to: 40641 -/* 15963 */ MCD_OPC_Decode, 185, 1, 90, // Opcode: CMGEv4i16rz -/* 15967 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 15998 -/* 15971 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 15974 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 15986 -/* 15978 */ MCD_OPC_CheckPredicate, 0, 83, 96, // Skip to: 40641 -/* 15982 */ MCD_OPC_Decode, 205, 1, 117, // Opcode: CMGTv8i16rz -/* 15986 */ MCD_OPC_FilterValue, 33, 75, 96, // Skip to: 40641 -/* 15990 */ MCD_OPC_CheckPredicate, 0, 71, 96, // Skip to: 40641 -/* 15994 */ MCD_OPC_Decode, 170, 5, 117, // Opcode: FRINTNv2f64 -/* 15998 */ MCD_OPC_FilterValue, 3, 63, 96, // Skip to: 40641 -/* 16002 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 16005 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16017 -/* 16009 */ MCD_OPC_CheckPredicate, 0, 52, 96, // Skip to: 40641 -/* 16013 */ MCD_OPC_Decode, 189, 1, 117, // Opcode: CMGEv8i16rz -/* 16017 */ MCD_OPC_FilterValue, 33, 44, 96, // Skip to: 40641 -/* 16021 */ MCD_OPC_CheckPredicate, 0, 40, 96, // Skip to: 40641 -/* 16025 */ MCD_OPC_Decode, 155, 5, 117, // Opcode: FRINTAv2f64 -/* 16029 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 16108 -/* 16033 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16036 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16054 -/* 16040 */ MCD_OPC_CheckPredicate, 0, 21, 96, // Skip to: 40641 -/* 16044 */ MCD_OPC_CheckField, 21, 1, 1, 15, 96, // Skip to: 40641 -/* 16050 */ MCD_OPC_Decode, 244, 1, 89, // Opcode: CMTSTv4i16 -/* 16054 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16072 -/* 16058 */ MCD_OPC_CheckPredicate, 0, 3, 96, // Skip to: 40641 -/* 16062 */ MCD_OPC_CheckField, 21, 1, 1, 253, 95, // Skip to: 40641 -/* 16068 */ MCD_OPC_Decode, 168, 1, 89, // Opcode: CMEQv4i16 -/* 16072 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16090 -/* 16076 */ MCD_OPC_CheckPredicate, 0, 241, 95, // Skip to: 40641 -/* 16080 */ MCD_OPC_CheckField, 21, 1, 1, 235, 95, // Skip to: 40641 -/* 16086 */ MCD_OPC_Decode, 246, 1, 112, // Opcode: CMTSTv8i16 -/* 16090 */ MCD_OPC_FilterValue, 3, 227, 95, // Skip to: 40641 -/* 16094 */ MCD_OPC_CheckPredicate, 0, 223, 95, // Skip to: 40641 -/* 16098 */ MCD_OPC_CheckField, 21, 1, 1, 217, 95, // Skip to: 40641 -/* 16104 */ MCD_OPC_Decode, 172, 1, 112, // Opcode: CMEQv8i16 -/* 16108 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 16151 -/* 16112 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16115 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16133 -/* 16119 */ MCD_OPC_CheckPredicate, 0, 198, 95, // Skip to: 40641 -/* 16123 */ MCD_OPC_CheckField, 21, 1, 1, 192, 95, // Skip to: 40641 -/* 16129 */ MCD_OPC_Decode, 178, 11, 105, // Opcode: SQDMLALv4i16_v4i32 -/* 16133 */ MCD_OPC_FilterValue, 2, 184, 95, // Skip to: 40641 -/* 16137 */ MCD_OPC_CheckPredicate, 0, 180, 95, // Skip to: 40641 -/* 16141 */ MCD_OPC_CheckField, 21, 1, 1, 174, 95, // Skip to: 40641 -/* 16147 */ MCD_OPC_Decode, 182, 11, 120, // Opcode: SQDMLALv8i16_v4i32 -/* 16151 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 16230 -/* 16155 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16158 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16176 -/* 16162 */ MCD_OPC_CheckPredicate, 0, 155, 95, // Skip to: 40641 -/* 16166 */ MCD_OPC_CheckField, 21, 1, 1, 149, 95, // Skip to: 40641 -/* 16172 */ MCD_OPC_Decode, 185, 8, 109, // Opcode: MLAv4i16 -/* 16176 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16194 -/* 16180 */ MCD_OPC_CheckPredicate, 0, 137, 95, // Skip to: 40641 -/* 16184 */ MCD_OPC_CheckField, 21, 1, 1, 131, 95, // Skip to: 40641 -/* 16190 */ MCD_OPC_Decode, 195, 8, 109, // Opcode: MLSv4i16 -/* 16194 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16212 -/* 16198 */ MCD_OPC_CheckPredicate, 0, 119, 95, // Skip to: 40641 -/* 16202 */ MCD_OPC_CheckField, 21, 1, 1, 113, 95, // Skip to: 40641 -/* 16208 */ MCD_OPC_Decode, 189, 8, 120, // Opcode: MLAv8i16 -/* 16212 */ MCD_OPC_FilterValue, 3, 105, 95, // Skip to: 40641 -/* 16216 */ MCD_OPC_CheckPredicate, 0, 101, 95, // Skip to: 40641 -/* 16220 */ MCD_OPC_CheckField, 21, 1, 1, 95, 95, // Skip to: 40641 -/* 16226 */ MCD_OPC_Decode, 199, 8, 120, // Opcode: MLSv8i16 -/* 16230 */ MCD_OPC_FilterValue, 38, 101, 0, // Skip to: 16335 -/* 16234 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16237 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16255 -/* 16241 */ MCD_OPC_CheckPredicate, 0, 76, 95, // Skip to: 40641 -/* 16245 */ MCD_OPC_CheckField, 16, 6, 32, 70, 95, // Skip to: 40641 -/* 16251 */ MCD_OPC_Decode, 169, 1, 90, // Opcode: CMEQv4i16rz -/* 16255 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16273 -/* 16259 */ MCD_OPC_CheckPredicate, 0, 58, 95, // Skip to: 40641 -/* 16263 */ MCD_OPC_CheckField, 16, 6, 32, 52, 95, // Skip to: 40641 -/* 16269 */ MCD_OPC_Decode, 228, 1, 90, // Opcode: CMLEv4i16rz -/* 16273 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 16304 -/* 16277 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 16280 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16292 -/* 16284 */ MCD_OPC_CheckPredicate, 0, 33, 95, // Skip to: 40641 -/* 16288 */ MCD_OPC_Decode, 173, 1, 117, // Opcode: CMEQv8i16rz -/* 16292 */ MCD_OPC_FilterValue, 33, 25, 95, // Skip to: 40641 -/* 16296 */ MCD_OPC_CheckPredicate, 0, 21, 95, // Skip to: 40641 -/* 16300 */ MCD_OPC_Decode, 165, 5, 117, // Opcode: FRINTMv2f64 -/* 16304 */ MCD_OPC_FilterValue, 3, 13, 95, // Skip to: 40641 -/* 16308 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 16311 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 16323 -/* 16315 */ MCD_OPC_CheckPredicate, 0, 2, 95, // Skip to: 40641 -/* 16319 */ MCD_OPC_Decode, 230, 1, 117, // Opcode: CMLEv8i16rz -/* 16323 */ MCD_OPC_FilterValue, 33, 250, 94, // Skip to: 40641 -/* 16327 */ MCD_OPC_CheckPredicate, 0, 246, 94, // Skip to: 40641 -/* 16331 */ MCD_OPC_Decode, 180, 5, 117, // Opcode: FRINTXv2f64 -/* 16335 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 16378 -/* 16339 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16342 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16360 -/* 16346 */ MCD_OPC_CheckPredicate, 0, 227, 94, // Skip to: 40641 -/* 16350 */ MCD_OPC_CheckField, 21, 1, 1, 221, 94, // Skip to: 40641 -/* 16356 */ MCD_OPC_Decode, 234, 8, 89, // Opcode: MULv4i16 -/* 16360 */ MCD_OPC_FilterValue, 2, 213, 94, // Skip to: 40641 -/* 16364 */ MCD_OPC_CheckPredicate, 0, 209, 94, // Skip to: 40641 -/* 16368 */ MCD_OPC_CheckField, 21, 1, 1, 203, 94, // Skip to: 40641 -/* 16374 */ MCD_OPC_Decode, 238, 8, 112, // Opcode: MULv8i16 -/* 16378 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 16457 -/* 16382 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16385 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16403 -/* 16389 */ MCD_OPC_CheckPredicate, 0, 184, 94, // Skip to: 40641 -/* 16393 */ MCD_OPC_CheckField, 21, 1, 1, 178, 94, // Skip to: 40641 -/* 16399 */ MCD_OPC_Decode, 254, 10, 105, // Opcode: SMLSLv4i16_v4i32 -/* 16403 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16421 -/* 16407 */ MCD_OPC_CheckPredicate, 0, 166, 94, // Skip to: 40641 -/* 16411 */ MCD_OPC_CheckField, 21, 1, 1, 160, 94, // Skip to: 40641 -/* 16417 */ MCD_OPC_Decode, 245, 16, 105, // Opcode: UMLSLv4i16_v4i32 -/* 16421 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16439 -/* 16425 */ MCD_OPC_CheckPredicate, 0, 148, 94, // Skip to: 40641 -/* 16429 */ MCD_OPC_CheckField, 21, 1, 1, 142, 94, // Skip to: 40641 -/* 16435 */ MCD_OPC_Decode, 130, 11, 120, // Opcode: SMLSLv8i16_v4i32 -/* 16439 */ MCD_OPC_FilterValue, 3, 134, 94, // Skip to: 40641 -/* 16443 */ MCD_OPC_CheckPredicate, 0, 130, 94, // Skip to: 40641 -/* 16447 */ MCD_OPC_CheckField, 21, 1, 1, 124, 94, // Skip to: 40641 -/* 16453 */ MCD_OPC_Decode, 249, 16, 120, // Opcode: UMLSLv8i16_v4i32 -/* 16457 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 16536 -/* 16461 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16464 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16482 -/* 16468 */ MCD_OPC_CheckPredicate, 0, 105, 94, // Skip to: 40641 -/* 16472 */ MCD_OPC_CheckField, 21, 1, 1, 99, 94, // Skip to: 40641 -/* 16478 */ MCD_OPC_Decode, 207, 10, 89, // Opcode: SMAXPv4i16 -/* 16482 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16500 -/* 16486 */ MCD_OPC_CheckPredicate, 0, 87, 94, // Skip to: 40641 -/* 16490 */ MCD_OPC_CheckField, 21, 1, 1, 81, 94, // Skip to: 40641 -/* 16496 */ MCD_OPC_Decode, 199, 16, 89, // Opcode: UMAXPv4i16 -/* 16500 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16518 -/* 16504 */ MCD_OPC_CheckPredicate, 0, 69, 94, // Skip to: 40641 -/* 16508 */ MCD_OPC_CheckField, 21, 1, 1, 63, 94, // Skip to: 40641 -/* 16514 */ MCD_OPC_Decode, 209, 10, 112, // Opcode: SMAXPv8i16 -/* 16518 */ MCD_OPC_FilterValue, 3, 55, 94, // Skip to: 40641 -/* 16522 */ MCD_OPC_CheckPredicate, 0, 51, 94, // Skip to: 40641 -/* 16526 */ MCD_OPC_CheckField, 21, 1, 1, 45, 94, // Skip to: 40641 -/* 16532 */ MCD_OPC_Decode, 201, 16, 112, // Opcode: UMAXPv8i16 -/* 16536 */ MCD_OPC_FilterValue, 42, 179, 0, // Skip to: 16719 -/* 16540 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 16543 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 16574 -/* 16547 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16550 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16562 -/* 16554 */ MCD_OPC_CheckPredicate, 0, 19, 94, // Skip to: 40641 -/* 16558 */ MCD_OPC_Decode, 236, 1, 90, // Opcode: CMLTv4i16rz -/* 16562 */ MCD_OPC_FilterValue, 2, 11, 94, // Skip to: 40641 -/* 16566 */ MCD_OPC_CheckPredicate, 0, 7, 94, // Skip to: 40641 -/* 16570 */ MCD_OPC_Decode, 238, 1, 117, // Opcode: CMLTv8i16rz -/* 16574 */ MCD_OPC_FilterValue, 33, 27, 0, // Skip to: 16605 -/* 16578 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16581 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 16593 -/* 16585 */ MCD_OPC_CheckPredicate, 0, 244, 93, // Skip to: 40641 -/* 16589 */ MCD_OPC_Decode, 187, 3, 117, // Opcode: FCVTNSv2f64 -/* 16593 */ MCD_OPC_FilterValue, 3, 236, 93, // Skip to: 40641 -/* 16597 */ MCD_OPC_CheckPredicate, 0, 232, 93, // Skip to: 40641 -/* 16601 */ MCD_OPC_Decode, 196, 3, 117, // Opcode: FCVTNUv2f64 -/* 16605 */ MCD_OPC_FilterValue, 48, 53, 0, // Skip to: 16662 -/* 16609 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16612 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16624 -/* 16616 */ MCD_OPC_CheckPredicate, 0, 213, 93, // Skip to: 40641 -/* 16620 */ MCD_OPC_Decode, 212, 10, 100, // Opcode: SMAXVv4i16v -/* 16624 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16636 -/* 16628 */ MCD_OPC_CheckPredicate, 0, 201, 93, // Skip to: 40641 -/* 16632 */ MCD_OPC_Decode, 204, 16, 100, // Opcode: UMAXVv4i16v -/* 16636 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16649 -/* 16640 */ MCD_OPC_CheckPredicate, 0, 189, 93, // Skip to: 40641 -/* 16644 */ MCD_OPC_Decode, 214, 10, 131, 1, // Opcode: SMAXVv8i16v -/* 16649 */ MCD_OPC_FilterValue, 3, 180, 93, // Skip to: 40641 -/* 16653 */ MCD_OPC_CheckPredicate, 0, 176, 93, // Skip to: 40641 -/* 16657 */ MCD_OPC_Decode, 206, 16, 131, 1, // Opcode: UMAXVv8i16v -/* 16662 */ MCD_OPC_FilterValue, 49, 167, 93, // Skip to: 40641 -/* 16666 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16669 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 16681 -/* 16673 */ MCD_OPC_CheckPredicate, 0, 156, 93, // Skip to: 40641 -/* 16677 */ MCD_OPC_Decode, 230, 10, 100, // Opcode: SMINVv4i16v -/* 16681 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 16693 -/* 16685 */ MCD_OPC_CheckPredicate, 0, 144, 93, // Skip to: 40641 -/* 16689 */ MCD_OPC_Decode, 221, 16, 100, // Opcode: UMINVv4i16v -/* 16693 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 16706 -/* 16697 */ MCD_OPC_CheckPredicate, 0, 132, 93, // Skip to: 40641 -/* 16701 */ MCD_OPC_Decode, 232, 10, 131, 1, // Opcode: SMINVv8i16v -/* 16706 */ MCD_OPC_FilterValue, 3, 123, 93, // Skip to: 40641 -/* 16710 */ MCD_OPC_CheckPredicate, 0, 119, 93, // Skip to: 40641 -/* 16714 */ MCD_OPC_Decode, 223, 16, 131, 1, // Opcode: UMINVv8i16v -/* 16719 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 16798 -/* 16723 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16726 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16744 -/* 16730 */ MCD_OPC_CheckPredicate, 0, 99, 93, // Skip to: 40641 -/* 16734 */ MCD_OPC_CheckField, 21, 1, 1, 93, 93, // Skip to: 40641 -/* 16740 */ MCD_OPC_Decode, 225, 10, 89, // Opcode: SMINPv4i16 -/* 16744 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16762 -/* 16748 */ MCD_OPC_CheckPredicate, 0, 81, 93, // Skip to: 40641 -/* 16752 */ MCD_OPC_CheckField, 21, 1, 1, 75, 93, // Skip to: 40641 -/* 16758 */ MCD_OPC_Decode, 216, 16, 89, // Opcode: UMINPv4i16 -/* 16762 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16780 -/* 16766 */ MCD_OPC_CheckPredicate, 0, 63, 93, // Skip to: 40641 -/* 16770 */ MCD_OPC_CheckField, 21, 1, 1, 57, 93, // Skip to: 40641 -/* 16776 */ MCD_OPC_Decode, 227, 10, 112, // Opcode: SMINPv8i16 -/* 16780 */ MCD_OPC_FilterValue, 3, 49, 93, // Skip to: 40641 -/* 16784 */ MCD_OPC_CheckPredicate, 0, 45, 93, // Skip to: 40641 -/* 16788 */ MCD_OPC_CheckField, 21, 1, 1, 39, 93, // Skip to: 40641 -/* 16794 */ MCD_OPC_Decode, 218, 16, 112, // Opcode: UMINPv8i16 -/* 16798 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 16841 -/* 16802 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16805 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16823 -/* 16809 */ MCD_OPC_CheckPredicate, 0, 20, 93, // Skip to: 40641 -/* 16813 */ MCD_OPC_CheckField, 21, 1, 1, 14, 93, // Skip to: 40641 -/* 16819 */ MCD_OPC_Decode, 190, 11, 105, // Opcode: SQDMLSLv4i16_v4i32 -/* 16823 */ MCD_OPC_FilterValue, 2, 6, 93, // Skip to: 40641 -/* 16827 */ MCD_OPC_CheckPredicate, 0, 2, 93, // Skip to: 40641 -/* 16831 */ MCD_OPC_CheckField, 21, 1, 1, 252, 92, // Skip to: 40641 -/* 16837 */ MCD_OPC_Decode, 194, 11, 120, // Opcode: SQDMLSLv8i16_v4i32 -/* 16841 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 16920 -/* 16845 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16848 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 16866 -/* 16852 */ MCD_OPC_CheckPredicate, 0, 233, 92, // Skip to: 40641 -/* 16856 */ MCD_OPC_CheckField, 21, 1, 1, 227, 92, // Skip to: 40641 -/* 16862 */ MCD_OPC_Decode, 201, 11, 89, // Opcode: SQDMULHv4i16 -/* 16866 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16884 -/* 16870 */ MCD_OPC_CheckPredicate, 0, 215, 92, // Skip to: 40641 -/* 16874 */ MCD_OPC_CheckField, 21, 1, 1, 209, 92, // Skip to: 40641 -/* 16880 */ MCD_OPC_Decode, 236, 11, 89, // Opcode: SQRDMULHv4i16 -/* 16884 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 16902 -/* 16888 */ MCD_OPC_CheckPredicate, 0, 197, 92, // Skip to: 40641 -/* 16892 */ MCD_OPC_CheckField, 21, 1, 1, 191, 92, // Skip to: 40641 -/* 16898 */ MCD_OPC_Decode, 205, 11, 112, // Opcode: SQDMULHv8i16 -/* 16902 */ MCD_OPC_FilterValue, 3, 183, 92, // Skip to: 40641 -/* 16906 */ MCD_OPC_CheckPredicate, 0, 179, 92, // Skip to: 40641 -/* 16910 */ MCD_OPC_CheckField, 21, 1, 1, 173, 92, // Skip to: 40641 -/* 16916 */ MCD_OPC_Decode, 240, 11, 112, // Opcode: SQRDMULHv8i16 -/* 16920 */ MCD_OPC_FilterValue, 46, 123, 0, // Skip to: 17047 -/* 16924 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 16927 */ MCD_OPC_FilterValue, 0, 25, 0, // Skip to: 16956 -/* 16931 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 16934 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 16945 -/* 16938 */ MCD_OPC_CheckPredicate, 0, 147, 92, // Skip to: 40641 -/* 16942 */ MCD_OPC_Decode, 26, 90, // Opcode: ABSv4i16 -/* 16945 */ MCD_OPC_FilterValue, 49, 140, 92, // Skip to: 40641 -/* 16949 */ MCD_OPC_CheckPredicate, 0, 136, 92, // Skip to: 40641 -/* 16953 */ MCD_OPC_Decode, 58, 100, // Opcode: ADDVv4i16v -/* 16956 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 16974 -/* 16960 */ MCD_OPC_CheckPredicate, 0, 125, 92, // Skip to: 40641 -/* 16964 */ MCD_OPC_CheckField, 16, 6, 32, 119, 92, // Skip to: 40641 -/* 16970 */ MCD_OPC_Decode, 251, 8, 90, // Opcode: NEGv4i16 -/* 16974 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 17016 -/* 16978 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 16981 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 16992 -/* 16985 */ MCD_OPC_CheckPredicate, 0, 100, 92, // Skip to: 40641 -/* 16989 */ MCD_OPC_Decode, 28, 117, // Opcode: ABSv8i16 -/* 16992 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 17004 -/* 16996 */ MCD_OPC_CheckPredicate, 0, 89, 92, // Skip to: 40641 -/* 17000 */ MCD_OPC_Decode, 169, 3, 117, // Opcode: FCVTMSv2f64 -/* 17004 */ MCD_OPC_FilterValue, 49, 81, 92, // Skip to: 40641 -/* 17008 */ MCD_OPC_CheckPredicate, 0, 77, 92, // Skip to: 40641 -/* 17012 */ MCD_OPC_Decode, 60, 131, 1, // Opcode: ADDVv8i16v -/* 17016 */ MCD_OPC_FilterValue, 3, 69, 92, // Skip to: 40641 -/* 17020 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 17023 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 17035 -/* 17027 */ MCD_OPC_CheckPredicate, 0, 58, 92, // Skip to: 40641 -/* 17031 */ MCD_OPC_Decode, 253, 8, 117, // Opcode: NEGv8i16 -/* 17035 */ MCD_OPC_FilterValue, 33, 50, 92, // Skip to: 40641 -/* 17039 */ MCD_OPC_CheckPredicate, 0, 46, 92, // Skip to: 40641 -/* 17043 */ MCD_OPC_Decode, 178, 3, 117, // Opcode: FCVTMUv2f64 -/* 17047 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 17088 -/* 17051 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17054 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 17071 -/* 17058 */ MCD_OPC_CheckPredicate, 0, 27, 92, // Skip to: 40641 -/* 17062 */ MCD_OPC_CheckField, 21, 1, 1, 21, 92, // Skip to: 40641 -/* 17068 */ MCD_OPC_Decode, 44, 89, // Opcode: ADDPv4i16 -/* 17071 */ MCD_OPC_FilterValue, 2, 14, 92, // Skip to: 40641 -/* 17075 */ MCD_OPC_CheckPredicate, 0, 10, 92, // Skip to: 40641 -/* 17079 */ MCD_OPC_CheckField, 21, 1, 1, 4, 92, // Skip to: 40641 -/* 17085 */ MCD_OPC_Decode, 46, 112, // Opcode: ADDPv8i16 -/* 17088 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 17167 -/* 17092 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17095 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17113 -/* 17099 */ MCD_OPC_CheckPredicate, 0, 242, 91, // Skip to: 40641 -/* 17103 */ MCD_OPC_CheckField, 21, 1, 1, 236, 91, // Skip to: 40641 -/* 17109 */ MCD_OPC_Decode, 143, 11, 85, // Opcode: SMULLv4i16_v4i32 -/* 17113 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17131 -/* 17117 */ MCD_OPC_CheckPredicate, 0, 224, 91, // Skip to: 40641 -/* 17121 */ MCD_OPC_CheckField, 21, 1, 1, 218, 91, // Skip to: 40641 -/* 17127 */ MCD_OPC_Decode, 133, 17, 85, // Opcode: UMULLv4i16_v4i32 -/* 17131 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17149 -/* 17135 */ MCD_OPC_CheckPredicate, 0, 206, 91, // Skip to: 40641 -/* 17139 */ MCD_OPC_CheckField, 21, 1, 1, 200, 91, // Skip to: 40641 -/* 17145 */ MCD_OPC_Decode, 147, 11, 112, // Opcode: SMULLv8i16_v4i32 -/* 17149 */ MCD_OPC_FilterValue, 3, 192, 91, // Skip to: 40641 -/* 17153 */ MCD_OPC_CheckPredicate, 0, 188, 91, // Skip to: 40641 -/* 17157 */ MCD_OPC_CheckField, 21, 1, 1, 182, 91, // Skip to: 40641 -/* 17163 */ MCD_OPC_Decode, 137, 17, 112, // Opcode: UMULLv8i16_v4i32 -/* 17167 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 17210 -/* 17171 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17174 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17192 -/* 17178 */ MCD_OPC_CheckPredicate, 0, 163, 91, // Skip to: 40641 -/* 17182 */ MCD_OPC_CheckField, 21, 1, 1, 157, 91, // Skip to: 40641 -/* 17188 */ MCD_OPC_Decode, 172, 4, 112, // Opcode: FMAXNMv2f64 -/* 17192 */ MCD_OPC_FilterValue, 3, 149, 91, // Skip to: 40641 -/* 17196 */ MCD_OPC_CheckPredicate, 0, 145, 91, // Skip to: 40641 -/* 17200 */ MCD_OPC_CheckField, 21, 1, 1, 139, 91, // Skip to: 40641 -/* 17206 */ MCD_OPC_Decode, 165, 4, 112, // Opcode: FMAXNMPv2f64 -/* 17210 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 17253 -/* 17214 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17217 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17235 -/* 17221 */ MCD_OPC_CheckPredicate, 0, 120, 91, // Skip to: 40641 -/* 17225 */ MCD_OPC_CheckField, 16, 6, 33, 114, 91, // Skip to: 40641 -/* 17231 */ MCD_OPC_Decode, 143, 3, 117, // Opcode: FCVTASv2f64 -/* 17235 */ MCD_OPC_FilterValue, 3, 106, 91, // Skip to: 40641 -/* 17239 */ MCD_OPC_CheckPredicate, 0, 102, 91, // Skip to: 40641 -/* 17243 */ MCD_OPC_CheckField, 16, 6, 33, 96, 91, // Skip to: 40641 -/* 17249 */ MCD_OPC_Decode, 152, 3, 117, // Opcode: FCVTAUv2f64 -/* 17253 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 17277 -/* 17257 */ MCD_OPC_CheckPredicate, 0, 84, 91, // Skip to: 40641 -/* 17261 */ MCD_OPC_CheckField, 29, 3, 2, 78, 91, // Skip to: 40641 -/* 17267 */ MCD_OPC_CheckField, 21, 1, 1, 72, 91, // Skip to: 40641 -/* 17273 */ MCD_OPC_Decode, 209, 4, 120, // Opcode: FMLAv2f64 -/* 17277 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 17320 -/* 17281 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17284 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17302 -/* 17288 */ MCD_OPC_CheckPredicate, 0, 53, 91, // Skip to: 40641 -/* 17292 */ MCD_OPC_CheckField, 21, 1, 1, 47, 91, // Skip to: 40641 -/* 17298 */ MCD_OPC_Decode, 214, 11, 85, // Opcode: SQDMULLv4i16_v4i32 -/* 17302 */ MCD_OPC_FilterValue, 2, 39, 91, // Skip to: 40641 -/* 17306 */ MCD_OPC_CheckPredicate, 0, 35, 91, // Skip to: 40641 -/* 17310 */ MCD_OPC_CheckField, 21, 1, 1, 29, 91, // Skip to: 40641 -/* 17316 */ MCD_OPC_Decode, 218, 11, 112, // Opcode: SQDMULLv8i16_v4i32 -/* 17320 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 17363 -/* 17324 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17327 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17345 -/* 17331 */ MCD_OPC_CheckPredicate, 0, 10, 91, // Skip to: 40641 -/* 17335 */ MCD_OPC_CheckField, 21, 1, 1, 4, 91, // Skip to: 40641 -/* 17341 */ MCD_OPC_Decode, 208, 2, 112, // Opcode: FADDv2f64 -/* 17345 */ MCD_OPC_FilterValue, 3, 252, 90, // Skip to: 40641 -/* 17349 */ MCD_OPC_CheckPredicate, 0, 248, 90, // Skip to: 40641 -/* 17353 */ MCD_OPC_CheckField, 21, 1, 1, 242, 90, // Skip to: 40641 -/* 17359 */ MCD_OPC_Decode, 202, 2, 112, // Opcode: FADDPv2f64 -/* 17363 */ MCD_OPC_FilterValue, 54, 39, 0, // Skip to: 17406 -/* 17367 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17370 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17388 -/* 17374 */ MCD_OPC_CheckPredicate, 0, 223, 90, // Skip to: 40641 -/* 17378 */ MCD_OPC_CheckField, 16, 6, 33, 217, 90, // Skip to: 40641 -/* 17384 */ MCD_OPC_Decode, 145, 10, 117, // Opcode: SCVTFv2f64 -/* 17388 */ MCD_OPC_FilterValue, 3, 209, 90, // Skip to: 40641 -/* 17392 */ MCD_OPC_CheckPredicate, 0, 205, 90, // Skip to: 40641 -/* 17396 */ MCD_OPC_CheckField, 16, 6, 33, 199, 90, // Skip to: 40641 -/* 17402 */ MCD_OPC_Decode, 175, 16, 117, // Opcode: UCVTFv2f64 -/* 17406 */ MCD_OPC_FilterValue, 55, 39, 0, // Skip to: 17449 -/* 17410 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17413 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17431 -/* 17417 */ MCD_OPC_CheckPredicate, 0, 180, 90, // Skip to: 40641 -/* 17421 */ MCD_OPC_CheckField, 21, 1, 1, 174, 90, // Skip to: 40641 -/* 17427 */ MCD_OPC_Decode, 244, 4, 112, // Opcode: FMULXv2f64 -/* 17431 */ MCD_OPC_FilterValue, 3, 166, 90, // Skip to: 40641 -/* 17435 */ MCD_OPC_CheckPredicate, 0, 162, 90, // Skip to: 40641 -/* 17439 */ MCD_OPC_CheckField, 21, 1, 1, 156, 90, // Skip to: 40641 -/* 17445 */ MCD_OPC_Decode, 252, 4, 112, // Opcode: FMULv2f64 -/* 17449 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 17492 -/* 17453 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17456 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17474 -/* 17460 */ MCD_OPC_CheckPredicate, 0, 137, 90, // Skip to: 40641 -/* 17464 */ MCD_OPC_CheckField, 21, 1, 1, 131, 90, // Skip to: 40641 -/* 17470 */ MCD_OPC_Decode, 219, 2, 112, // Opcode: FCMEQv2f64 -/* 17474 */ MCD_OPC_FilterValue, 3, 123, 90, // Skip to: 40641 -/* 17478 */ MCD_OPC_CheckPredicate, 0, 119, 90, // Skip to: 40641 -/* 17482 */ MCD_OPC_CheckField, 21, 1, 1, 113, 90, // Skip to: 40641 -/* 17488 */ MCD_OPC_Decode, 229, 2, 112, // Opcode: FCMGEv2f64 -/* 17492 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 17516 -/* 17496 */ MCD_OPC_CheckPredicate, 0, 101, 90, // Skip to: 40641 -/* 17500 */ MCD_OPC_CheckField, 29, 3, 3, 95, 90, // Skip to: 40641 -/* 17506 */ MCD_OPC_CheckField, 21, 1, 1, 89, 90, // Skip to: 40641 -/* 17512 */ MCD_OPC_Decode, 193, 2, 112, // Opcode: FACGEv2f64 -/* 17516 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 17559 -/* 17520 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17523 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17541 -/* 17527 */ MCD_OPC_CheckPredicate, 0, 70, 90, // Skip to: 40641 -/* 17531 */ MCD_OPC_CheckField, 21, 1, 1, 64, 90, // Skip to: 40641 -/* 17537 */ MCD_OPC_Decode, 182, 4, 112, // Opcode: FMAXv2f64 -/* 17541 */ MCD_OPC_FilterValue, 3, 56, 90, // Skip to: 40641 -/* 17545 */ MCD_OPC_CheckPredicate, 0, 52, 90, // Skip to: 40641 -/* 17549 */ MCD_OPC_CheckField, 21, 1, 1, 46, 90, // Skip to: 40641 -/* 17555 */ MCD_OPC_Decode, 175, 4, 112, // Opcode: FMAXPv2f64 -/* 17559 */ MCD_OPC_FilterValue, 63, 38, 90, // Skip to: 40641 -/* 17563 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17566 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17584 -/* 17570 */ MCD_OPC_CheckPredicate, 0, 27, 90, // Skip to: 40641 -/* 17574 */ MCD_OPC_CheckField, 21, 1, 1, 21, 90, // Skip to: 40641 -/* 17580 */ MCD_OPC_Decode, 148, 5, 112, // Opcode: FRECPSv2f64 -/* 17584 */ MCD_OPC_FilterValue, 3, 13, 90, // Skip to: 40641 -/* 17588 */ MCD_OPC_CheckPredicate, 0, 9, 90, // Skip to: 40641 -/* 17592 */ MCD_OPC_CheckField, 21, 1, 1, 3, 90, // Skip to: 40641 -/* 17598 */ MCD_OPC_Decode, 158, 4, 112, // Opcode: FDIVv2f64 -/* 17602 */ MCD_OPC_FilterValue, 10, 165, 19, // Skip to: 22635 -/* 17606 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 17609 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 17688 -/* 17613 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17616 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17634 -/* 17620 */ MCD_OPC_CheckPredicate, 0, 233, 89, // Skip to: 40641 -/* 17624 */ MCD_OPC_CheckField, 21, 1, 1, 227, 89, // Skip to: 40641 -/* 17630 */ MCD_OPC_Decode, 243, 9, 85, // Opcode: SADDLv2i32_v2i64 -/* 17634 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17652 -/* 17638 */ MCD_OPC_CheckPredicate, 0, 215, 89, // Skip to: 40641 -/* 17642 */ MCD_OPC_CheckField, 21, 1, 1, 209, 89, // Skip to: 40641 -/* 17648 */ MCD_OPC_Decode, 149, 16, 85, // Opcode: UADDLv2i32_v2i64 -/* 17652 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17670 -/* 17656 */ MCD_OPC_CheckPredicate, 0, 197, 89, // Skip to: 40641 -/* 17660 */ MCD_OPC_CheckField, 21, 1, 1, 191, 89, // Skip to: 40641 -/* 17666 */ MCD_OPC_Decode, 245, 9, 112, // Opcode: SADDLv4i32_v2i64 -/* 17670 */ MCD_OPC_FilterValue, 3, 183, 89, // Skip to: 40641 -/* 17674 */ MCD_OPC_CheckPredicate, 0, 179, 89, // Skip to: 40641 -/* 17678 */ MCD_OPC_CheckField, 21, 1, 1, 173, 89, // Skip to: 40641 -/* 17684 */ MCD_OPC_Decode, 151, 16, 112, // Opcode: UADDLv4i32_v2i64 -/* 17688 */ MCD_OPC_FilterValue, 1, 75, 0, // Skip to: 17767 -/* 17692 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17695 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17713 -/* 17699 */ MCD_OPC_CheckPredicate, 0, 154, 89, // Skip to: 40641 -/* 17703 */ MCD_OPC_CheckField, 21, 1, 1, 148, 89, // Skip to: 40641 -/* 17709 */ MCD_OPC_Decode, 165, 10, 89, // Opcode: SHADDv2i32 -/* 17713 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17731 -/* 17717 */ MCD_OPC_CheckPredicate, 0, 136, 89, // Skip to: 40641 -/* 17721 */ MCD_OPC_CheckField, 21, 1, 1, 130, 89, // Skip to: 40641 -/* 17727 */ MCD_OPC_Decode, 185, 16, 89, // Opcode: UHADDv2i32 -/* 17731 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17749 -/* 17735 */ MCD_OPC_CheckPredicate, 0, 118, 89, // Skip to: 40641 -/* 17739 */ MCD_OPC_CheckField, 21, 1, 1, 112, 89, // Skip to: 40641 -/* 17745 */ MCD_OPC_Decode, 167, 10, 112, // Opcode: SHADDv4i32 -/* 17749 */ MCD_OPC_FilterValue, 3, 104, 89, // Skip to: 40641 -/* 17753 */ MCD_OPC_CheckPredicate, 0, 100, 89, // Skip to: 40641 -/* 17757 */ MCD_OPC_CheckField, 21, 1, 1, 94, 89, // Skip to: 40641 -/* 17763 */ MCD_OPC_Decode, 187, 16, 112, // Opcode: UHADDv4i32 -/* 17767 */ MCD_OPC_FilterValue, 2, 39, 0, // Skip to: 17810 -/* 17771 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17774 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17792 -/* 17778 */ MCD_OPC_CheckPredicate, 0, 75, 89, // Skip to: 40641 -/* 17782 */ MCD_OPC_CheckField, 16, 6, 32, 69, 89, // Skip to: 40641 -/* 17788 */ MCD_OPC_Decode, 180, 9, 90, // Opcode: REV64v2i32 -/* 17792 */ MCD_OPC_FilterValue, 2, 61, 89, // Skip to: 40641 -/* 17796 */ MCD_OPC_CheckPredicate, 0, 57, 89, // Skip to: 40641 -/* 17800 */ MCD_OPC_CheckField, 16, 6, 32, 51, 89, // Skip to: 40641 -/* 17806 */ MCD_OPC_Decode, 182, 9, 117, // Opcode: REV64v4i32 -/* 17810 */ MCD_OPC_FilterValue, 3, 75, 0, // Skip to: 17889 -/* 17814 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17817 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17835 -/* 17821 */ MCD_OPC_CheckPredicate, 0, 32, 89, // Skip to: 40641 -/* 17825 */ MCD_OPC_CheckField, 21, 1, 1, 26, 89, // Skip to: 40641 -/* 17831 */ MCD_OPC_Decode, 165, 11, 89, // Opcode: SQADDv2i32 -/* 17835 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17853 -/* 17839 */ MCD_OPC_CheckPredicate, 0, 14, 89, // Skip to: 40641 -/* 17843 */ MCD_OPC_CheckField, 21, 1, 1, 8, 89, // Skip to: 40641 -/* 17849 */ MCD_OPC_Decode, 144, 17, 89, // Opcode: UQADDv2i32 -/* 17853 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17871 -/* 17857 */ MCD_OPC_CheckPredicate, 0, 252, 88, // Skip to: 40641 -/* 17861 */ MCD_OPC_CheckField, 21, 1, 1, 246, 88, // Skip to: 40641 -/* 17867 */ MCD_OPC_Decode, 168, 11, 112, // Opcode: SQADDv4i32 -/* 17871 */ MCD_OPC_FilterValue, 3, 238, 88, // Skip to: 40641 -/* 17875 */ MCD_OPC_CheckPredicate, 0, 234, 88, // Skip to: 40641 -/* 17879 */ MCD_OPC_CheckField, 21, 1, 1, 228, 88, // Skip to: 40641 -/* 17885 */ MCD_OPC_Decode, 147, 17, 112, // Opcode: UQADDv4i32 -/* 17889 */ MCD_OPC_FilterValue, 4, 75, 0, // Skip to: 17968 -/* 17893 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17896 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17914 -/* 17900 */ MCD_OPC_CheckPredicate, 0, 209, 88, // Skip to: 40641 -/* 17904 */ MCD_OPC_CheckField, 21, 1, 1, 203, 88, // Skip to: 40641 -/* 17910 */ MCD_OPC_Decode, 249, 9, 93, // Opcode: SADDWv2i32_v2i64 -/* 17914 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 17932 -/* 17918 */ MCD_OPC_CheckPredicate, 0, 191, 88, // Skip to: 40641 -/* 17922 */ MCD_OPC_CheckField, 21, 1, 1, 185, 88, // Skip to: 40641 -/* 17928 */ MCD_OPC_Decode, 155, 16, 93, // Opcode: UADDWv2i32_v2i64 -/* 17932 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 17950 -/* 17936 */ MCD_OPC_CheckPredicate, 0, 173, 88, // Skip to: 40641 -/* 17940 */ MCD_OPC_CheckField, 21, 1, 1, 167, 88, // Skip to: 40641 -/* 17946 */ MCD_OPC_Decode, 251, 9, 112, // Opcode: SADDWv4i32_v2i64 -/* 17950 */ MCD_OPC_FilterValue, 3, 159, 88, // Skip to: 40641 -/* 17954 */ MCD_OPC_CheckPredicate, 0, 155, 88, // Skip to: 40641 -/* 17958 */ MCD_OPC_CheckField, 21, 1, 1, 149, 88, // Skip to: 40641 -/* 17964 */ MCD_OPC_Decode, 157, 16, 112, // Opcode: UADDWv4i32_v2i64 -/* 17968 */ MCD_OPC_FilterValue, 5, 75, 0, // Skip to: 18047 -/* 17972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 17975 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 17993 -/* 17979 */ MCD_OPC_CheckPredicate, 0, 130, 88, // Skip to: 40641 -/* 17983 */ MCD_OPC_CheckField, 21, 1, 1, 124, 88, // Skip to: 40641 -/* 17989 */ MCD_OPC_Decode, 224, 12, 89, // Opcode: SRHADDv2i32 -/* 17993 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18011 -/* 17997 */ MCD_OPC_CheckPredicate, 0, 112, 88, // Skip to: 40641 -/* 18001 */ MCD_OPC_CheckField, 21, 1, 1, 106, 88, // Skip to: 40641 -/* 18007 */ MCD_OPC_Decode, 224, 17, 89, // Opcode: URHADDv2i32 -/* 18011 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18029 -/* 18015 */ MCD_OPC_CheckPredicate, 0, 94, 88, // Skip to: 40641 -/* 18019 */ MCD_OPC_CheckField, 21, 1, 1, 88, 88, // Skip to: 40641 -/* 18025 */ MCD_OPC_Decode, 226, 12, 112, // Opcode: SRHADDv4i32 -/* 18029 */ MCD_OPC_FilterValue, 3, 80, 88, // Skip to: 40641 -/* 18033 */ MCD_OPC_CheckPredicate, 0, 76, 88, // Skip to: 40641 -/* 18037 */ MCD_OPC_CheckField, 21, 1, 1, 70, 88, // Skip to: 40641 -/* 18043 */ MCD_OPC_Decode, 226, 17, 112, // Opcode: URHADDv4i32 -/* 18047 */ MCD_OPC_FilterValue, 6, 39, 0, // Skip to: 18090 -/* 18051 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18054 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18072 -/* 18058 */ MCD_OPC_CheckPredicate, 0, 51, 88, // Skip to: 40641 -/* 18062 */ MCD_OPC_CheckField, 21, 1, 0, 45, 88, // Skip to: 40641 -/* 18068 */ MCD_OPC_Decode, 181, 18, 89, // Opcode: UZP1v2i32 -/* 18072 */ MCD_OPC_FilterValue, 2, 37, 88, // Skip to: 40641 -/* 18076 */ MCD_OPC_CheckPredicate, 0, 33, 88, // Skip to: 40641 -/* 18080 */ MCD_OPC_CheckField, 21, 1, 0, 27, 88, // Skip to: 40641 -/* 18086 */ MCD_OPC_Decode, 184, 18, 112, // Opcode: UZP1v4i32 -/* 18090 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 18167 -/* 18094 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18097 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18115 -/* 18101 */ MCD_OPC_CheckPredicate, 0, 8, 88, // Skip to: 40641 -/* 18105 */ MCD_OPC_CheckField, 21, 1, 1, 2, 88, // Skip to: 40641 -/* 18111 */ MCD_OPC_Decode, 146, 9, 89, // Opcode: ORRv8i8 -/* 18115 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 18132 -/* 18119 */ MCD_OPC_CheckPredicate, 0, 246, 87, // Skip to: 40641 -/* 18123 */ MCD_OPC_CheckField, 21, 1, 1, 240, 87, // Skip to: 40641 -/* 18129 */ MCD_OPC_Decode, 123, 109, // Opcode: BITv8i8 -/* 18132 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18150 -/* 18136 */ MCD_OPC_CheckPredicate, 0, 229, 87, // Skip to: 40641 -/* 18140 */ MCD_OPC_CheckField, 21, 1, 1, 223, 87, // Skip to: 40641 -/* 18146 */ MCD_OPC_Decode, 141, 9, 112, // Opcode: ORRv16i8 -/* 18150 */ MCD_OPC_FilterValue, 3, 215, 87, // Skip to: 40641 -/* 18154 */ MCD_OPC_CheckPredicate, 0, 211, 87, // Skip to: 40641 -/* 18158 */ MCD_OPC_CheckField, 21, 1, 1, 205, 87, // Skip to: 40641 -/* 18164 */ MCD_OPC_Decode, 122, 120, // Opcode: BITv16i8 -/* 18167 */ MCD_OPC_FilterValue, 8, 75, 0, // Skip to: 18246 -/* 18171 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18174 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18192 -/* 18178 */ MCD_OPC_CheckPredicate, 0, 187, 87, // Skip to: 40641 -/* 18182 */ MCD_OPC_CheckField, 21, 1, 1, 181, 87, // Skip to: 40641 -/* 18188 */ MCD_OPC_Decode, 164, 13, 85, // Opcode: SSUBLv2i32_v2i64 -/* 18192 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18210 -/* 18196 */ MCD_OPC_CheckPredicate, 0, 169, 87, // Skip to: 40641 -/* 18200 */ MCD_OPC_CheckField, 21, 1, 1, 163, 87, // Skip to: 40641 -/* 18206 */ MCD_OPC_Decode, 169, 18, 85, // Opcode: USUBLv2i32_v2i64 -/* 18210 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18228 -/* 18214 */ MCD_OPC_CheckPredicate, 0, 151, 87, // Skip to: 40641 -/* 18218 */ MCD_OPC_CheckField, 21, 1, 1, 145, 87, // Skip to: 40641 -/* 18224 */ MCD_OPC_Decode, 166, 13, 112, // Opcode: SSUBLv4i32_v2i64 -/* 18228 */ MCD_OPC_FilterValue, 3, 137, 87, // Skip to: 40641 -/* 18232 */ MCD_OPC_CheckPredicate, 0, 133, 87, // Skip to: 40641 -/* 18236 */ MCD_OPC_CheckField, 21, 1, 1, 127, 87, // Skip to: 40641 -/* 18242 */ MCD_OPC_Decode, 171, 18, 112, // Opcode: USUBLv4i32_v2i64 -/* 18246 */ MCD_OPC_FilterValue, 9, 75, 0, // Skip to: 18325 -/* 18250 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18253 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18271 -/* 18257 */ MCD_OPC_CheckPredicate, 0, 108, 87, // Skip to: 40641 -/* 18261 */ MCD_OPC_CheckField, 21, 1, 1, 102, 87, // Skip to: 40641 -/* 18267 */ MCD_OPC_Decode, 191, 10, 89, // Opcode: SHSUBv2i32 -/* 18271 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18289 -/* 18275 */ MCD_OPC_CheckPredicate, 0, 90, 87, // Skip to: 40641 -/* 18279 */ MCD_OPC_CheckField, 21, 1, 1, 84, 87, // Skip to: 40641 -/* 18285 */ MCD_OPC_Decode, 191, 16, 89, // Opcode: UHSUBv2i32 -/* 18289 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18307 -/* 18293 */ MCD_OPC_CheckPredicate, 0, 72, 87, // Skip to: 40641 -/* 18297 */ MCD_OPC_CheckField, 21, 1, 1, 66, 87, // Skip to: 40641 -/* 18303 */ MCD_OPC_Decode, 193, 10, 112, // Opcode: SHSUBv4i32 -/* 18307 */ MCD_OPC_FilterValue, 3, 58, 87, // Skip to: 40641 -/* 18311 */ MCD_OPC_CheckPredicate, 0, 54, 87, // Skip to: 40641 -/* 18315 */ MCD_OPC_CheckField, 21, 1, 1, 48, 87, // Skip to: 40641 -/* 18321 */ MCD_OPC_Decode, 193, 16, 112, // Opcode: UHSUBv4i32 -/* 18325 */ MCD_OPC_FilterValue, 10, 165, 0, // Skip to: 18494 -/* 18329 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18332 */ MCD_OPC_FilterValue, 0, 46, 0, // Skip to: 18382 -/* 18336 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 18339 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18351 -/* 18343 */ MCD_OPC_CheckPredicate, 0, 22, 87, // Skip to: 40641 -/* 18347 */ MCD_OPC_Decode, 222, 15, 89, // Opcode: TRN1v2i32 -/* 18351 */ MCD_OPC_FilterValue, 1, 14, 87, // Skip to: 40641 -/* 18355 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 18358 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18370 -/* 18362 */ MCD_OPC_CheckPredicate, 0, 3, 87, // Skip to: 40641 -/* 18366 */ MCD_OPC_Decode, 232, 9, 90, // Opcode: SADDLPv2i32_v1i64 -/* 18370 */ MCD_OPC_FilterValue, 1, 251, 86, // Skip to: 40641 -/* 18374 */ MCD_OPC_CheckPredicate, 0, 247, 86, // Skip to: 40641 -/* 18378 */ MCD_OPC_Decode, 195, 18, 95, // Opcode: XTNv2i32 -/* 18382 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 18413 -/* 18386 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 18389 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18401 -/* 18393 */ MCD_OPC_CheckPredicate, 0, 228, 86, // Skip to: 40641 -/* 18397 */ MCD_OPC_Decode, 138, 16, 90, // Opcode: UADDLPv2i32_v1i64 -/* 18401 */ MCD_OPC_FilterValue, 33, 220, 86, // Skip to: 40641 -/* 18405 */ MCD_OPC_CheckPredicate, 0, 216, 86, // Skip to: 40641 -/* 18409 */ MCD_OPC_Decode, 218, 12, 95, // Opcode: SQXTUNv2i32 -/* 18413 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 18463 -/* 18417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 18420 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18432 -/* 18424 */ MCD_OPC_CheckPredicate, 0, 197, 86, // Skip to: 40641 -/* 18428 */ MCD_OPC_Decode, 225, 15, 112, // Opcode: TRN1v4i32 -/* 18432 */ MCD_OPC_FilterValue, 1, 189, 86, // Skip to: 40641 -/* 18436 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 18439 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18451 -/* 18443 */ MCD_OPC_CheckPredicate, 0, 178, 86, // Skip to: 40641 -/* 18447 */ MCD_OPC_Decode, 234, 9, 117, // Opcode: SADDLPv4i32_v2i64 -/* 18451 */ MCD_OPC_FilterValue, 1, 170, 86, // Skip to: 40641 -/* 18455 */ MCD_OPC_CheckPredicate, 0, 166, 86, // Skip to: 40641 -/* 18459 */ MCD_OPC_Decode, 197, 18, 126, // Opcode: XTNv4i32 -/* 18463 */ MCD_OPC_FilterValue, 3, 158, 86, // Skip to: 40641 -/* 18467 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 18470 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18482 -/* 18474 */ MCD_OPC_CheckPredicate, 0, 147, 86, // Skip to: 40641 -/* 18478 */ MCD_OPC_Decode, 140, 16, 117, // Opcode: UADDLPv4i32_v2i64 -/* 18482 */ MCD_OPC_FilterValue, 33, 139, 86, // Skip to: 40641 -/* 18486 */ MCD_OPC_CheckPredicate, 0, 135, 86, // Skip to: 40641 -/* 18490 */ MCD_OPC_Decode, 220, 12, 126, // Opcode: SQXTUNv4i32 -/* 18494 */ MCD_OPC_FilterValue, 11, 75, 0, // Skip to: 18573 -/* 18498 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18501 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18519 -/* 18505 */ MCD_OPC_CheckPredicate, 0, 116, 86, // Skip to: 40641 -/* 18509 */ MCD_OPC_CheckField, 21, 1, 1, 110, 86, // Skip to: 40641 -/* 18515 */ MCD_OPC_Decode, 199, 12, 89, // Opcode: SQSUBv2i32 -/* 18519 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18537 -/* 18523 */ MCD_OPC_CheckPredicate, 0, 98, 86, // Skip to: 40641 -/* 18527 */ MCD_OPC_CheckField, 21, 1, 1, 92, 86, // Skip to: 40641 -/* 18533 */ MCD_OPC_Decode, 206, 17, 89, // Opcode: UQSUBv2i32 -/* 18537 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18555 -/* 18541 */ MCD_OPC_CheckPredicate, 0, 80, 86, // Skip to: 40641 -/* 18545 */ MCD_OPC_CheckField, 21, 1, 1, 74, 86, // Skip to: 40641 -/* 18551 */ MCD_OPC_Decode, 202, 12, 112, // Opcode: SQSUBv4i32 -/* 18555 */ MCD_OPC_FilterValue, 3, 66, 86, // Skip to: 40641 -/* 18559 */ MCD_OPC_CheckPredicate, 0, 62, 86, // Skip to: 40641 -/* 18563 */ MCD_OPC_CheckField, 21, 1, 1, 56, 86, // Skip to: 40641 -/* 18569 */ MCD_OPC_Decode, 209, 17, 112, // Opcode: UQSUBv4i32 -/* 18573 */ MCD_OPC_FilterValue, 12, 75, 0, // Skip to: 18652 -/* 18577 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18580 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18598 -/* 18584 */ MCD_OPC_CheckPredicate, 0, 37, 86, // Skip to: 40641 -/* 18588 */ MCD_OPC_CheckField, 21, 1, 1, 31, 86, // Skip to: 40641 -/* 18594 */ MCD_OPC_Decode, 170, 13, 93, // Opcode: SSUBWv2i32_v2i64 -/* 18598 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18616 -/* 18602 */ MCD_OPC_CheckPredicate, 0, 19, 86, // Skip to: 40641 -/* 18606 */ MCD_OPC_CheckField, 21, 1, 1, 13, 86, // Skip to: 40641 -/* 18612 */ MCD_OPC_Decode, 175, 18, 93, // Opcode: USUBWv2i32_v2i64 -/* 18616 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18634 -/* 18620 */ MCD_OPC_CheckPredicate, 0, 1, 86, // Skip to: 40641 -/* 18624 */ MCD_OPC_CheckField, 21, 1, 1, 251, 85, // Skip to: 40641 -/* 18630 */ MCD_OPC_Decode, 172, 13, 112, // Opcode: SSUBWv4i32_v2i64 -/* 18634 */ MCD_OPC_FilterValue, 3, 243, 85, // Skip to: 40641 -/* 18638 */ MCD_OPC_CheckPredicate, 0, 239, 85, // Skip to: 40641 -/* 18642 */ MCD_OPC_CheckField, 21, 1, 1, 233, 85, // Skip to: 40641 -/* 18648 */ MCD_OPC_Decode, 177, 18, 112, // Opcode: USUBWv4i32_v2i64 -/* 18652 */ MCD_OPC_FilterValue, 13, 75, 0, // Skip to: 18731 -/* 18656 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18659 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18677 -/* 18663 */ MCD_OPC_CheckPredicate, 0, 214, 85, // Skip to: 40641 -/* 18667 */ MCD_OPC_CheckField, 21, 1, 1, 208, 85, // Skip to: 40641 -/* 18673 */ MCD_OPC_Decode, 196, 1, 89, // Opcode: CMGTv2i32 -/* 18677 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18695 -/* 18681 */ MCD_OPC_CheckPredicate, 0, 196, 85, // Skip to: 40641 -/* 18685 */ MCD_OPC_CheckField, 21, 1, 1, 190, 85, // Skip to: 40641 -/* 18691 */ MCD_OPC_Decode, 210, 1, 89, // Opcode: CMHIv2i32 -/* 18695 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18713 -/* 18699 */ MCD_OPC_CheckPredicate, 0, 178, 85, // Skip to: 40641 -/* 18703 */ MCD_OPC_CheckField, 21, 1, 1, 172, 85, // Skip to: 40641 -/* 18709 */ MCD_OPC_Decode, 202, 1, 112, // Opcode: CMGTv4i32 -/* 18713 */ MCD_OPC_FilterValue, 3, 164, 85, // Skip to: 40641 -/* 18717 */ MCD_OPC_CheckPredicate, 0, 160, 85, // Skip to: 40641 -/* 18721 */ MCD_OPC_CheckField, 21, 1, 1, 154, 85, // Skip to: 40641 -/* 18727 */ MCD_OPC_Decode, 213, 1, 112, // Opcode: CMHIv4i32 -/* 18731 */ MCD_OPC_FilterValue, 14, 164, 0, // Skip to: 18899 -/* 18735 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18738 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 18775 -/* 18742 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 18745 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18757 -/* 18749 */ MCD_OPC_CheckPredicate, 0, 128, 85, // Skip to: 40641 -/* 18753 */ MCD_OPC_Decode, 201, 18, 89, // Opcode: ZIP1v2i32 -/* 18757 */ MCD_OPC_FilterValue, 1, 120, 85, // Skip to: 40641 -/* 18761 */ MCD_OPC_CheckPredicate, 0, 116, 85, // Skip to: 40641 -/* 18765 */ MCD_OPC_CheckField, 16, 5, 0, 110, 85, // Skip to: 40641 -/* 18771 */ MCD_OPC_Decode, 188, 15, 99, // Opcode: SUQADDv2i32 -/* 18775 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 18806 -/* 18779 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 18782 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18794 -/* 18786 */ MCD_OPC_CheckPredicate, 0, 91, 85, // Skip to: 40641 -/* 18790 */ MCD_OPC_Decode, 154, 18, 99, // Opcode: USQADDv2i32 -/* 18794 */ MCD_OPC_FilterValue, 33, 83, 85, // Skip to: 40641 -/* 18798 */ MCD_OPC_CheckPredicate, 0, 79, 85, // Skip to: 40641 -/* 18802 */ MCD_OPC_Decode, 171, 10, 108, // Opcode: SHLLv2i32 -/* 18806 */ MCD_OPC_FilterValue, 2, 46, 0, // Skip to: 18856 -/* 18810 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 18813 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18825 -/* 18817 */ MCD_OPC_CheckPredicate, 0, 60, 85, // Skip to: 40641 -/* 18821 */ MCD_OPC_Decode, 204, 18, 112, // Opcode: ZIP1v4i32 -/* 18825 */ MCD_OPC_FilterValue, 1, 52, 85, // Skip to: 40641 -/* 18829 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 18832 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 18844 -/* 18836 */ MCD_OPC_CheckPredicate, 0, 41, 85, // Skip to: 40641 -/* 18840 */ MCD_OPC_Decode, 191, 15, 126, // Opcode: SUQADDv4i32 -/* 18844 */ MCD_OPC_FilterValue, 16, 33, 85, // Skip to: 40641 -/* 18848 */ MCD_OPC_CheckPredicate, 0, 29, 85, // Skip to: 40641 -/* 18852 */ MCD_OPC_Decode, 239, 9, 95, // Opcode: SADDLVv4i32v -/* 18856 */ MCD_OPC_FilterValue, 3, 21, 85, // Skip to: 40641 -/* 18860 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 18863 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 18875 -/* 18867 */ MCD_OPC_CheckPredicate, 0, 10, 85, // Skip to: 40641 -/* 18871 */ MCD_OPC_Decode, 157, 18, 126, // Opcode: USQADDv4i32 -/* 18875 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 18887 -/* 18879 */ MCD_OPC_CheckPredicate, 0, 254, 84, // Skip to: 40641 -/* 18883 */ MCD_OPC_Decode, 173, 10, 117, // Opcode: SHLLv4i32 -/* 18887 */ MCD_OPC_FilterValue, 48, 246, 84, // Skip to: 40641 -/* 18891 */ MCD_OPC_CheckPredicate, 0, 242, 84, // Skip to: 40641 -/* 18895 */ MCD_OPC_Decode, 145, 16, 95, // Opcode: UADDLVv4i32v -/* 18899 */ MCD_OPC_FilterValue, 15, 75, 0, // Skip to: 18978 -/* 18903 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18906 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 18924 -/* 18910 */ MCD_OPC_CheckPredicate, 0, 223, 84, // Skip to: 40641 -/* 18914 */ MCD_OPC_CheckField, 21, 1, 1, 217, 84, // Skip to: 40641 -/* 18920 */ MCD_OPC_Decode, 180, 1, 89, // Opcode: CMGEv2i32 -/* 18924 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 18942 -/* 18928 */ MCD_OPC_CheckPredicate, 0, 205, 84, // Skip to: 40641 -/* 18932 */ MCD_OPC_CheckField, 21, 1, 1, 199, 84, // Skip to: 40641 -/* 18938 */ MCD_OPC_Decode, 218, 1, 89, // Opcode: CMHSv2i32 -/* 18942 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 18960 -/* 18946 */ MCD_OPC_CheckPredicate, 0, 187, 84, // Skip to: 40641 -/* 18950 */ MCD_OPC_CheckField, 21, 1, 1, 181, 84, // Skip to: 40641 -/* 18956 */ MCD_OPC_Decode, 186, 1, 112, // Opcode: CMGEv4i32 -/* 18960 */ MCD_OPC_FilterValue, 3, 173, 84, // Skip to: 40641 -/* 18964 */ MCD_OPC_CheckPredicate, 0, 169, 84, // Skip to: 40641 -/* 18968 */ MCD_OPC_CheckField, 21, 1, 1, 163, 84, // Skip to: 40641 -/* 18974 */ MCD_OPC_Decode, 221, 1, 112, // Opcode: CMHSv4i32 -/* 18978 */ MCD_OPC_FilterValue, 16, 73, 0, // Skip to: 19055 -/* 18982 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 18985 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 19002 -/* 18989 */ MCD_OPC_CheckPredicate, 0, 144, 84, // Skip to: 40641 -/* 18993 */ MCD_OPC_CheckField, 21, 1, 1, 138, 84, // Skip to: 40641 -/* 18999 */ MCD_OPC_Decode, 34, 103, // Opcode: ADDHNv2i64_v2i32 -/* 19002 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19020 -/* 19006 */ MCD_OPC_CheckPredicate, 0, 127, 84, // Skip to: 40641 -/* 19010 */ MCD_OPC_CheckField, 21, 1, 1, 121, 84, // Skip to: 40641 -/* 19016 */ MCD_OPC_Decode, 158, 9, 103, // Opcode: RADDHNv2i64_v2i32 -/* 19020 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 19037 -/* 19024 */ MCD_OPC_CheckPredicate, 0, 109, 84, // Skip to: 40641 -/* 19028 */ MCD_OPC_CheckField, 21, 1, 1, 103, 84, // Skip to: 40641 -/* 19034 */ MCD_OPC_Decode, 35, 120, // Opcode: ADDHNv2i64_v4i32 -/* 19037 */ MCD_OPC_FilterValue, 3, 96, 84, // Skip to: 40641 -/* 19041 */ MCD_OPC_CheckPredicate, 0, 92, 84, // Skip to: 40641 -/* 19045 */ MCD_OPC_CheckField, 21, 1, 1, 86, 84, // Skip to: 40641 -/* 19051 */ MCD_OPC_Decode, 159, 9, 120, // Opcode: RADDHNv2i64_v4i32 -/* 19055 */ MCD_OPC_FilterValue, 17, 75, 0, // Skip to: 19134 -/* 19059 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19062 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19080 -/* 19066 */ MCD_OPC_CheckPredicate, 0, 67, 84, // Skip to: 40641 -/* 19070 */ MCD_OPC_CheckField, 21, 1, 1, 61, 84, // Skip to: 40641 -/* 19076 */ MCD_OPC_Decode, 141, 13, 89, // Opcode: SSHLv2i32 -/* 19080 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19098 -/* 19084 */ MCD_OPC_CheckPredicate, 0, 49, 84, // Skip to: 40641 -/* 19088 */ MCD_OPC_CheckField, 21, 1, 1, 43, 84, // Skip to: 40641 -/* 19094 */ MCD_OPC_Decode, 135, 18, 89, // Opcode: USHLv2i32 -/* 19098 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19116 -/* 19102 */ MCD_OPC_CheckPredicate, 0, 31, 84, // Skip to: 40641 -/* 19106 */ MCD_OPC_CheckField, 21, 1, 1, 25, 84, // Skip to: 40641 -/* 19112 */ MCD_OPC_Decode, 144, 13, 112, // Opcode: SSHLv4i32 -/* 19116 */ MCD_OPC_FilterValue, 3, 17, 84, // Skip to: 40641 -/* 19120 */ MCD_OPC_CheckPredicate, 0, 13, 84, // Skip to: 40641 -/* 19124 */ MCD_OPC_CheckField, 21, 1, 1, 7, 84, // Skip to: 40641 -/* 19130 */ MCD_OPC_Decode, 138, 18, 112, // Opcode: USHLv4i32 -/* 19134 */ MCD_OPC_FilterValue, 18, 127, 0, // Skip to: 19265 -/* 19138 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19141 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 19172 -/* 19145 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 19148 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19160 -/* 19152 */ MCD_OPC_CheckPredicate, 0, 237, 83, // Skip to: 40641 -/* 19156 */ MCD_OPC_Decode, 147, 1, 90, // Opcode: CLSv2i32 -/* 19160 */ MCD_OPC_FilterValue, 33, 229, 83, // Skip to: 40641 -/* 19164 */ MCD_OPC_CheckPredicate, 0, 225, 83, // Skip to: 40641 -/* 19168 */ MCD_OPC_Decode, 209, 12, 95, // Opcode: SQXTNv2i32 -/* 19172 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 19203 -/* 19176 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 19179 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19191 -/* 19183 */ MCD_OPC_CheckPredicate, 0, 206, 83, // Skip to: 40641 -/* 19187 */ MCD_OPC_Decode, 155, 1, 90, // Opcode: CLZv2i32 -/* 19191 */ MCD_OPC_FilterValue, 33, 198, 83, // Skip to: 40641 -/* 19195 */ MCD_OPC_CheckPredicate, 0, 194, 83, // Skip to: 40641 -/* 19199 */ MCD_OPC_Decode, 216, 17, 95, // Opcode: UQXTNv2i32 -/* 19203 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 19234 -/* 19207 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 19210 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19222 -/* 19214 */ MCD_OPC_CheckPredicate, 0, 175, 83, // Skip to: 40641 -/* 19218 */ MCD_OPC_Decode, 149, 1, 117, // Opcode: CLSv4i32 -/* 19222 */ MCD_OPC_FilterValue, 33, 167, 83, // Skip to: 40641 -/* 19226 */ MCD_OPC_CheckPredicate, 0, 163, 83, // Skip to: 40641 -/* 19230 */ MCD_OPC_Decode, 211, 12, 126, // Opcode: SQXTNv4i32 -/* 19234 */ MCD_OPC_FilterValue, 3, 155, 83, // Skip to: 40641 -/* 19238 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 19241 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 19253 -/* 19245 */ MCD_OPC_CheckPredicate, 0, 144, 83, // Skip to: 40641 -/* 19249 */ MCD_OPC_Decode, 157, 1, 117, // Opcode: CLZv4i32 -/* 19253 */ MCD_OPC_FilterValue, 33, 136, 83, // Skip to: 40641 -/* 19257 */ MCD_OPC_CheckPredicate, 0, 132, 83, // Skip to: 40641 -/* 19261 */ MCD_OPC_Decode, 218, 17, 126, // Opcode: UQXTNv4i32 -/* 19265 */ MCD_OPC_FilterValue, 19, 75, 0, // Skip to: 19344 -/* 19269 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19272 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19290 -/* 19276 */ MCD_OPC_CheckPredicate, 0, 113, 83, // Skip to: 40641 -/* 19280 */ MCD_OPC_CheckField, 21, 1, 1, 107, 83, // Skip to: 40641 -/* 19286 */ MCD_OPC_Decode, 164, 12, 89, // Opcode: SQSHLv2i32 -/* 19290 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19308 -/* 19294 */ MCD_OPC_CheckPredicate, 0, 95, 83, // Skip to: 40641 -/* 19298 */ MCD_OPC_CheckField, 21, 1, 1, 89, 83, // Skip to: 40641 -/* 19304 */ MCD_OPC_Decode, 180, 17, 89, // Opcode: UQSHLv2i32 -/* 19308 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19326 -/* 19312 */ MCD_OPC_CheckPredicate, 0, 77, 83, // Skip to: 40641 -/* 19316 */ MCD_OPC_CheckField, 21, 1, 1, 71, 83, // Skip to: 40641 -/* 19322 */ MCD_OPC_Decode, 170, 12, 112, // Opcode: SQSHLv4i32 -/* 19326 */ MCD_OPC_FilterValue, 3, 63, 83, // Skip to: 40641 -/* 19330 */ MCD_OPC_CheckPredicate, 0, 59, 83, // Skip to: 40641 -/* 19334 */ MCD_OPC_CheckField, 21, 1, 1, 53, 83, // Skip to: 40641 -/* 19340 */ MCD_OPC_Decode, 186, 17, 112, // Opcode: UQSHLv4i32 -/* 19344 */ MCD_OPC_FilterValue, 20, 75, 0, // Skip to: 19423 -/* 19348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19351 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19369 -/* 19355 */ MCD_OPC_CheckPredicate, 0, 34, 83, // Skip to: 40641 -/* 19359 */ MCD_OPC_CheckField, 21, 1, 1, 28, 83, // Skip to: 40641 -/* 19365 */ MCD_OPC_Decode, 202, 9, 105, // Opcode: SABALv2i32_v2i64 -/* 19369 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19387 -/* 19373 */ MCD_OPC_CheckPredicate, 0, 16, 83, // Skip to: 40641 -/* 19377 */ MCD_OPC_CheckField, 21, 1, 1, 10, 83, // Skip to: 40641 -/* 19383 */ MCD_OPC_Decode, 236, 15, 105, // Opcode: UABALv2i32_v2i64 -/* 19387 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19405 -/* 19391 */ MCD_OPC_CheckPredicate, 0, 254, 82, // Skip to: 40641 -/* 19395 */ MCD_OPC_CheckField, 21, 1, 1, 248, 82, // Skip to: 40641 -/* 19401 */ MCD_OPC_Decode, 204, 9, 120, // Opcode: SABALv4i32_v2i64 -/* 19405 */ MCD_OPC_FilterValue, 3, 240, 82, // Skip to: 40641 -/* 19409 */ MCD_OPC_CheckPredicate, 0, 236, 82, // Skip to: 40641 -/* 19413 */ MCD_OPC_CheckField, 21, 1, 1, 230, 82, // Skip to: 40641 -/* 19419 */ MCD_OPC_Decode, 238, 15, 120, // Opcode: UABALv4i32_v2i64 -/* 19423 */ MCD_OPC_FilterValue, 21, 75, 0, // Skip to: 19502 -/* 19427 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19430 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19448 -/* 19434 */ MCD_OPC_CheckPredicate, 0, 211, 82, // Skip to: 40641 -/* 19438 */ MCD_OPC_CheckField, 21, 1, 1, 205, 82, // Skip to: 40641 -/* 19444 */ MCD_OPC_Decode, 239, 12, 89, // Opcode: SRSHLv2i32 -/* 19448 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19466 -/* 19452 */ MCD_OPC_CheckPredicate, 0, 193, 82, // Skip to: 40641 -/* 19456 */ MCD_OPC_CheckField, 21, 1, 1, 187, 82, // Skip to: 40641 -/* 19462 */ MCD_OPC_Decode, 231, 17, 89, // Opcode: URSHLv2i32 -/* 19466 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19484 -/* 19470 */ MCD_OPC_CheckPredicate, 0, 175, 82, // Skip to: 40641 -/* 19474 */ MCD_OPC_CheckField, 21, 1, 1, 169, 82, // Skip to: 40641 -/* 19480 */ MCD_OPC_Decode, 242, 12, 112, // Opcode: SRSHLv4i32 -/* 19484 */ MCD_OPC_FilterValue, 3, 161, 82, // Skip to: 40641 -/* 19488 */ MCD_OPC_CheckPredicate, 0, 157, 82, // Skip to: 40641 -/* 19492 */ MCD_OPC_CheckField, 21, 1, 1, 151, 82, // Skip to: 40641 -/* 19498 */ MCD_OPC_Decode, 234, 17, 112, // Opcode: URSHLv4i32 -/* 19502 */ MCD_OPC_FilterValue, 22, 39, 0, // Skip to: 19545 -/* 19506 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19509 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19527 -/* 19513 */ MCD_OPC_CheckPredicate, 0, 132, 82, // Skip to: 40641 -/* 19517 */ MCD_OPC_CheckField, 21, 1, 0, 126, 82, // Skip to: 40641 -/* 19523 */ MCD_OPC_Decode, 188, 18, 89, // Opcode: UZP2v2i32 -/* 19527 */ MCD_OPC_FilterValue, 2, 118, 82, // Skip to: 40641 -/* 19531 */ MCD_OPC_CheckPredicate, 0, 114, 82, // Skip to: 40641 -/* 19535 */ MCD_OPC_CheckField, 21, 1, 0, 108, 82, // Skip to: 40641 -/* 19541 */ MCD_OPC_Decode, 191, 18, 112, // Opcode: UZP2v4i32 -/* 19545 */ MCD_OPC_FilterValue, 23, 75, 0, // Skip to: 19624 -/* 19549 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19552 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19570 -/* 19556 */ MCD_OPC_CheckPredicate, 0, 89, 82, // Skip to: 40641 -/* 19560 */ MCD_OPC_CheckField, 21, 1, 1, 83, 82, // Skip to: 40641 -/* 19566 */ MCD_OPC_Decode, 247, 11, 89, // Opcode: SQRSHLv2i32 -/* 19570 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19588 -/* 19574 */ MCD_OPC_CheckPredicate, 0, 71, 82, // Skip to: 40641 -/* 19578 */ MCD_OPC_CheckField, 21, 1, 1, 65, 82, // Skip to: 40641 -/* 19584 */ MCD_OPC_Decode, 155, 17, 89, // Opcode: UQRSHLv2i32 -/* 19588 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19606 -/* 19592 */ MCD_OPC_CheckPredicate, 0, 53, 82, // Skip to: 40641 -/* 19596 */ MCD_OPC_CheckField, 21, 1, 1, 47, 82, // Skip to: 40641 -/* 19602 */ MCD_OPC_Decode, 250, 11, 112, // Opcode: SQRSHLv4i32 -/* 19606 */ MCD_OPC_FilterValue, 3, 39, 82, // Skip to: 40641 -/* 19610 */ MCD_OPC_CheckPredicate, 0, 35, 82, // Skip to: 40641 -/* 19614 */ MCD_OPC_CheckField, 21, 1, 1, 29, 82, // Skip to: 40641 -/* 19620 */ MCD_OPC_Decode, 158, 17, 112, // Opcode: UQRSHLv4i32 -/* 19624 */ MCD_OPC_FilterValue, 24, 75, 0, // Skip to: 19703 -/* 19628 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19631 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19649 -/* 19635 */ MCD_OPC_CheckPredicate, 0, 10, 82, // Skip to: 40641 -/* 19639 */ MCD_OPC_CheckField, 21, 1, 1, 4, 82, // Skip to: 40641 -/* 19645 */ MCD_OPC_Decode, 151, 15, 103, // Opcode: SUBHNv2i64_v2i32 -/* 19649 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19667 -/* 19653 */ MCD_OPC_CheckPredicate, 0, 248, 81, // Skip to: 40641 -/* 19657 */ MCD_OPC_CheckField, 21, 1, 1, 242, 81, // Skip to: 40641 -/* 19663 */ MCD_OPC_Decode, 195, 9, 103, // Opcode: RSUBHNv2i64_v2i32 -/* 19667 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19685 -/* 19671 */ MCD_OPC_CheckPredicate, 0, 230, 81, // Skip to: 40641 -/* 19675 */ MCD_OPC_CheckField, 21, 1, 1, 224, 81, // Skip to: 40641 -/* 19681 */ MCD_OPC_Decode, 152, 15, 120, // Opcode: SUBHNv2i64_v4i32 -/* 19685 */ MCD_OPC_FilterValue, 3, 216, 81, // Skip to: 40641 -/* 19689 */ MCD_OPC_CheckPredicate, 0, 212, 81, // Skip to: 40641 -/* 19693 */ MCD_OPC_CheckField, 21, 1, 1, 206, 81, // Skip to: 40641 -/* 19699 */ MCD_OPC_Decode, 196, 9, 120, // Opcode: RSUBHNv2i64_v4i32 -/* 19703 */ MCD_OPC_FilterValue, 25, 75, 0, // Skip to: 19782 -/* 19707 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19710 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19728 -/* 19714 */ MCD_OPC_CheckPredicate, 0, 187, 81, // Skip to: 40641 -/* 19718 */ MCD_OPC_CheckField, 21, 1, 1, 181, 81, // Skip to: 40641 -/* 19724 */ MCD_OPC_Decode, 217, 10, 89, // Opcode: SMAXv2i32 -/* 19728 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19746 -/* 19732 */ MCD_OPC_CheckPredicate, 0, 169, 81, // Skip to: 40641 -/* 19736 */ MCD_OPC_CheckField, 21, 1, 1, 163, 81, // Skip to: 40641 -/* 19742 */ MCD_OPC_Decode, 209, 16, 89, // Opcode: UMAXv2i32 -/* 19746 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19764 -/* 19750 */ MCD_OPC_CheckPredicate, 0, 151, 81, // Skip to: 40641 -/* 19754 */ MCD_OPC_CheckField, 21, 1, 1, 145, 81, // Skip to: 40641 -/* 19760 */ MCD_OPC_Decode, 219, 10, 112, // Opcode: SMAXv4i32 -/* 19764 */ MCD_OPC_FilterValue, 3, 137, 81, // Skip to: 40641 -/* 19768 */ MCD_OPC_CheckPredicate, 0, 133, 81, // Skip to: 40641 -/* 19772 */ MCD_OPC_CheckField, 21, 1, 1, 127, 81, // Skip to: 40641 -/* 19778 */ MCD_OPC_Decode, 211, 16, 112, // Opcode: UMAXv4i32 -/* 19782 */ MCD_OPC_FilterValue, 26, 113, 0, // Skip to: 19899 -/* 19786 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19789 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 19826 -/* 19793 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 19796 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 19808 -/* 19800 */ MCD_OPC_CheckPredicate, 0, 101, 81, // Skip to: 40641 -/* 19804 */ MCD_OPC_Decode, 229, 15, 89, // Opcode: TRN2v2i32 -/* 19808 */ MCD_OPC_FilterValue, 1, 93, 81, // Skip to: 40641 -/* 19812 */ MCD_OPC_CheckPredicate, 0, 89, 81, // Skip to: 40641 -/* 19816 */ MCD_OPC_CheckField, 16, 5, 0, 83, 81, // Skip to: 40641 -/* 19822 */ MCD_OPC_Decode, 226, 9, 99, // Opcode: SADALPv2i32_v1i64 -/* 19826 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19844 -/* 19830 */ MCD_OPC_CheckPredicate, 0, 71, 81, // Skip to: 40641 -/* 19834 */ MCD_OPC_CheckField, 16, 6, 32, 65, 81, // Skip to: 40641 -/* 19840 */ MCD_OPC_Decode, 132, 16, 99, // Opcode: UADALPv2i32_v1i64 -/* 19844 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 19881 -/* 19848 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 19851 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 19863 -/* 19855 */ MCD_OPC_CheckPredicate, 0, 46, 81, // Skip to: 40641 -/* 19859 */ MCD_OPC_Decode, 232, 15, 112, // Opcode: TRN2v4i32 -/* 19863 */ MCD_OPC_FilterValue, 1, 38, 81, // Skip to: 40641 -/* 19867 */ MCD_OPC_CheckPredicate, 0, 34, 81, // Skip to: 40641 -/* 19871 */ MCD_OPC_CheckField, 16, 5, 0, 28, 81, // Skip to: 40641 -/* 19877 */ MCD_OPC_Decode, 228, 9, 126, // Opcode: SADALPv4i32_v2i64 -/* 19881 */ MCD_OPC_FilterValue, 3, 20, 81, // Skip to: 40641 -/* 19885 */ MCD_OPC_CheckPredicate, 0, 16, 81, // Skip to: 40641 -/* 19889 */ MCD_OPC_CheckField, 16, 6, 32, 10, 81, // Skip to: 40641 -/* 19895 */ MCD_OPC_Decode, 134, 16, 126, // Opcode: UADALPv4i32_v2i64 -/* 19899 */ MCD_OPC_FilterValue, 27, 75, 0, // Skip to: 19978 -/* 19903 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19906 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 19924 -/* 19910 */ MCD_OPC_CheckPredicate, 0, 247, 80, // Skip to: 40641 -/* 19914 */ MCD_OPC_CheckField, 21, 1, 1, 241, 80, // Skip to: 40641 -/* 19920 */ MCD_OPC_Decode, 235, 10, 89, // Opcode: SMINv2i32 -/* 19924 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 19942 -/* 19928 */ MCD_OPC_CheckPredicate, 0, 229, 80, // Skip to: 40641 -/* 19932 */ MCD_OPC_CheckField, 21, 1, 1, 223, 80, // Skip to: 40641 -/* 19938 */ MCD_OPC_Decode, 226, 16, 89, // Opcode: UMINv2i32 -/* 19942 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 19960 -/* 19946 */ MCD_OPC_CheckPredicate, 0, 211, 80, // Skip to: 40641 -/* 19950 */ MCD_OPC_CheckField, 21, 1, 1, 205, 80, // Skip to: 40641 -/* 19956 */ MCD_OPC_Decode, 237, 10, 112, // Opcode: SMINv4i32 -/* 19960 */ MCD_OPC_FilterValue, 3, 197, 80, // Skip to: 40641 -/* 19964 */ MCD_OPC_CheckPredicate, 0, 193, 80, // Skip to: 40641 -/* 19968 */ MCD_OPC_CheckField, 21, 1, 1, 187, 80, // Skip to: 40641 -/* 19974 */ MCD_OPC_Decode, 228, 16, 112, // Opcode: UMINv4i32 -/* 19978 */ MCD_OPC_FilterValue, 28, 75, 0, // Skip to: 20057 -/* 19982 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 19985 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20003 -/* 19989 */ MCD_OPC_CheckPredicate, 0, 168, 80, // Skip to: 40641 -/* 19993 */ MCD_OPC_CheckField, 21, 1, 1, 162, 80, // Skip to: 40641 -/* 19999 */ MCD_OPC_Decode, 214, 9, 85, // Opcode: SABDLv2i32_v2i64 -/* 20003 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20021 -/* 20007 */ MCD_OPC_CheckPredicate, 0, 150, 80, // Skip to: 40641 -/* 20011 */ MCD_OPC_CheckField, 21, 1, 1, 144, 80, // Skip to: 40641 -/* 20017 */ MCD_OPC_Decode, 248, 15, 85, // Opcode: UABDLv2i32_v2i64 -/* 20021 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20039 -/* 20025 */ MCD_OPC_CheckPredicate, 0, 132, 80, // Skip to: 40641 -/* 20029 */ MCD_OPC_CheckField, 21, 1, 1, 126, 80, // Skip to: 40641 -/* 20035 */ MCD_OPC_Decode, 216, 9, 112, // Opcode: SABDLv4i32_v2i64 -/* 20039 */ MCD_OPC_FilterValue, 3, 118, 80, // Skip to: 40641 -/* 20043 */ MCD_OPC_CheckPredicate, 0, 114, 80, // Skip to: 40641 -/* 20047 */ MCD_OPC_CheckField, 21, 1, 1, 108, 80, // Skip to: 40641 -/* 20053 */ MCD_OPC_Decode, 250, 15, 112, // Opcode: UABDLv4i32_v2i64 -/* 20057 */ MCD_OPC_FilterValue, 29, 75, 0, // Skip to: 20136 -/* 20061 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20064 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20082 -/* 20068 */ MCD_OPC_CheckPredicate, 0, 89, 80, // Skip to: 40641 -/* 20072 */ MCD_OPC_CheckField, 21, 1, 1, 83, 80, // Skip to: 40641 -/* 20078 */ MCD_OPC_Decode, 220, 9, 89, // Opcode: SABDv2i32 -/* 20082 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20100 -/* 20086 */ MCD_OPC_CheckPredicate, 0, 71, 80, // Skip to: 40641 -/* 20090 */ MCD_OPC_CheckField, 21, 1, 1, 65, 80, // Skip to: 40641 -/* 20096 */ MCD_OPC_Decode, 254, 15, 89, // Opcode: UABDv2i32 -/* 20100 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20118 -/* 20104 */ MCD_OPC_CheckPredicate, 0, 53, 80, // Skip to: 40641 -/* 20108 */ MCD_OPC_CheckField, 21, 1, 1, 47, 80, // Skip to: 40641 -/* 20114 */ MCD_OPC_Decode, 222, 9, 112, // Opcode: SABDv4i32 -/* 20118 */ MCD_OPC_FilterValue, 3, 39, 80, // Skip to: 40641 -/* 20122 */ MCD_OPC_CheckPredicate, 0, 35, 80, // Skip to: 40641 -/* 20126 */ MCD_OPC_CheckField, 21, 1, 1, 29, 80, // Skip to: 40641 -/* 20132 */ MCD_OPC_Decode, 128, 16, 112, // Opcode: UABDv4i32 -/* 20136 */ MCD_OPC_FilterValue, 30, 113, 0, // Skip to: 20253 -/* 20140 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20143 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 20180 -/* 20147 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 20150 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 20162 -/* 20154 */ MCD_OPC_CheckPredicate, 0, 3, 80, // Skip to: 40641 -/* 20158 */ MCD_OPC_Decode, 208, 18, 89, // Opcode: ZIP2v2i32 -/* 20162 */ MCD_OPC_FilterValue, 1, 251, 79, // Skip to: 40641 -/* 20166 */ MCD_OPC_CheckPredicate, 0, 247, 79, // Skip to: 40641 -/* 20170 */ MCD_OPC_CheckField, 16, 5, 0, 241, 79, // Skip to: 40641 -/* 20176 */ MCD_OPC_Decode, 154, 11, 90, // Opcode: SQABSv2i32 -/* 20180 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20198 -/* 20184 */ MCD_OPC_CheckPredicate, 0, 229, 79, // Skip to: 40641 -/* 20188 */ MCD_OPC_CheckField, 16, 6, 32, 223, 79, // Skip to: 40641 -/* 20194 */ MCD_OPC_Decode, 224, 11, 90, // Opcode: SQNEGv2i32 -/* 20198 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 20235 -/* 20202 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 20205 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 20217 -/* 20209 */ MCD_OPC_CheckPredicate, 0, 204, 79, // Skip to: 40641 -/* 20213 */ MCD_OPC_Decode, 211, 18, 112, // Opcode: ZIP2v4i32 -/* 20217 */ MCD_OPC_FilterValue, 1, 196, 79, // Skip to: 40641 -/* 20221 */ MCD_OPC_CheckPredicate, 0, 192, 79, // Skip to: 40641 -/* 20225 */ MCD_OPC_CheckField, 16, 5, 0, 186, 79, // Skip to: 40641 -/* 20231 */ MCD_OPC_Decode, 157, 11, 117, // Opcode: SQABSv4i32 -/* 20235 */ MCD_OPC_FilterValue, 3, 178, 79, // Skip to: 40641 -/* 20239 */ MCD_OPC_CheckPredicate, 0, 174, 79, // Skip to: 40641 -/* 20243 */ MCD_OPC_CheckField, 16, 6, 32, 168, 79, // Skip to: 40641 -/* 20249 */ MCD_OPC_Decode, 227, 11, 117, // Opcode: SQNEGv4i32 -/* 20253 */ MCD_OPC_FilterValue, 31, 75, 0, // Skip to: 20332 -/* 20257 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20260 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20278 -/* 20264 */ MCD_OPC_CheckPredicate, 0, 149, 79, // Skip to: 40641 -/* 20268 */ MCD_OPC_CheckField, 21, 1, 1, 143, 79, // Skip to: 40641 -/* 20274 */ MCD_OPC_Decode, 208, 9, 109, // Opcode: SABAv2i32 -/* 20278 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20296 -/* 20282 */ MCD_OPC_CheckPredicate, 0, 131, 79, // Skip to: 40641 -/* 20286 */ MCD_OPC_CheckField, 21, 1, 1, 125, 79, // Skip to: 40641 -/* 20292 */ MCD_OPC_Decode, 242, 15, 109, // Opcode: UABAv2i32 -/* 20296 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20314 -/* 20300 */ MCD_OPC_CheckPredicate, 0, 113, 79, // Skip to: 40641 -/* 20304 */ MCD_OPC_CheckField, 21, 1, 1, 107, 79, // Skip to: 40641 -/* 20310 */ MCD_OPC_Decode, 210, 9, 120, // Opcode: SABAv4i32 -/* 20314 */ MCD_OPC_FilterValue, 3, 99, 79, // Skip to: 40641 -/* 20318 */ MCD_OPC_CheckPredicate, 0, 95, 79, // Skip to: 40641 -/* 20322 */ MCD_OPC_CheckField, 21, 1, 1, 89, 79, // Skip to: 40641 -/* 20328 */ MCD_OPC_Decode, 244, 15, 120, // Opcode: UABAv4i32 -/* 20332 */ MCD_OPC_FilterValue, 32, 75, 0, // Skip to: 20411 -/* 20336 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20339 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20357 -/* 20343 */ MCD_OPC_CheckPredicate, 0, 70, 79, // Skip to: 40641 -/* 20347 */ MCD_OPC_CheckField, 21, 1, 1, 64, 79, // Skip to: 40641 -/* 20353 */ MCD_OPC_Decode, 242, 10, 105, // Opcode: SMLALv2i32_v2i64 -/* 20357 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20375 -/* 20361 */ MCD_OPC_CheckPredicate, 0, 52, 79, // Skip to: 40641 -/* 20365 */ MCD_OPC_CheckField, 21, 1, 1, 46, 79, // Skip to: 40641 -/* 20371 */ MCD_OPC_Decode, 233, 16, 105, // Opcode: UMLALv2i32_v2i64 -/* 20375 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20393 -/* 20379 */ MCD_OPC_CheckPredicate, 0, 34, 79, // Skip to: 40641 -/* 20383 */ MCD_OPC_CheckField, 21, 1, 1, 28, 79, // Skip to: 40641 -/* 20389 */ MCD_OPC_Decode, 246, 10, 120, // Opcode: SMLALv4i32_v2i64 -/* 20393 */ MCD_OPC_FilterValue, 3, 20, 79, // Skip to: 40641 -/* 20397 */ MCD_OPC_CheckPredicate, 0, 16, 79, // Skip to: 40641 -/* 20401 */ MCD_OPC_CheckField, 21, 1, 1, 10, 79, // Skip to: 40641 -/* 20407 */ MCD_OPC_Decode, 237, 16, 120, // Opcode: UMLALv4i32_v2i64 -/* 20411 */ MCD_OPC_FilterValue, 33, 73, 0, // Skip to: 20488 -/* 20415 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20418 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 20435 -/* 20422 */ MCD_OPC_CheckPredicate, 0, 247, 78, // Skip to: 40641 -/* 20426 */ MCD_OPC_CheckField, 21, 1, 1, 241, 78, // Skip to: 40641 -/* 20432 */ MCD_OPC_Decode, 73, 89, // Opcode: ADDv2i32 -/* 20435 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20453 -/* 20439 */ MCD_OPC_CheckPredicate, 0, 230, 78, // Skip to: 40641 -/* 20443 */ MCD_OPC_CheckField, 21, 1, 1, 224, 78, // Skip to: 40641 -/* 20449 */ MCD_OPC_Decode, 177, 15, 89, // Opcode: SUBv2i32 -/* 20453 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 20470 -/* 20457 */ MCD_OPC_CheckPredicate, 0, 212, 78, // Skip to: 40641 -/* 20461 */ MCD_OPC_CheckField, 21, 1, 1, 206, 78, // Skip to: 40641 -/* 20467 */ MCD_OPC_Decode, 76, 112, // Opcode: ADDv4i32 -/* 20470 */ MCD_OPC_FilterValue, 3, 199, 78, // Skip to: 40641 -/* 20474 */ MCD_OPC_CheckPredicate, 0, 195, 78, // Skip to: 40641 -/* 20478 */ MCD_OPC_CheckField, 21, 1, 1, 189, 78, // Skip to: 40641 -/* 20484 */ MCD_OPC_Decode, 180, 15, 112, // Opcode: SUBv4i32 -/* 20488 */ MCD_OPC_FilterValue, 34, 101, 0, // Skip to: 20593 -/* 20492 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20495 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 20526 -/* 20499 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 20502 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20514 -/* 20506 */ MCD_OPC_CheckPredicate, 0, 163, 78, // Skip to: 40641 -/* 20510 */ MCD_OPC_Decode, 197, 1, 90, // Opcode: CMGTv2i32rz -/* 20514 */ MCD_OPC_FilterValue, 33, 155, 78, // Skip to: 40641 -/* 20518 */ MCD_OPC_CheckPredicate, 0, 151, 78, // Skip to: 40641 -/* 20522 */ MCD_OPC_Decode, 174, 5, 90, // Opcode: FRINTPv2f32 -/* 20526 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20544 -/* 20530 */ MCD_OPC_CheckPredicate, 0, 139, 78, // Skip to: 40641 -/* 20534 */ MCD_OPC_CheckField, 16, 6, 32, 133, 78, // Skip to: 40641 -/* 20540 */ MCD_OPC_Decode, 181, 1, 90, // Opcode: CMGEv2i32rz -/* 20544 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 20575 -/* 20548 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 20551 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20563 -/* 20555 */ MCD_OPC_CheckPredicate, 0, 114, 78, // Skip to: 40641 -/* 20559 */ MCD_OPC_Decode, 203, 1, 117, // Opcode: CMGTv4i32rz -/* 20563 */ MCD_OPC_FilterValue, 33, 106, 78, // Skip to: 40641 -/* 20567 */ MCD_OPC_CheckPredicate, 0, 102, 78, // Skip to: 40641 -/* 20571 */ MCD_OPC_Decode, 176, 5, 117, // Opcode: FRINTPv4f32 -/* 20575 */ MCD_OPC_FilterValue, 3, 94, 78, // Skip to: 40641 -/* 20579 */ MCD_OPC_CheckPredicate, 0, 90, 78, // Skip to: 40641 -/* 20583 */ MCD_OPC_CheckField, 16, 6, 32, 84, 78, // Skip to: 40641 -/* 20589 */ MCD_OPC_Decode, 187, 1, 117, // Opcode: CMGEv4i32rz -/* 20593 */ MCD_OPC_FilterValue, 35, 75, 0, // Skip to: 20672 -/* 20597 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20600 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20618 -/* 20604 */ MCD_OPC_CheckPredicate, 0, 65, 78, // Skip to: 40641 -/* 20608 */ MCD_OPC_CheckField, 21, 1, 1, 59, 78, // Skip to: 40641 -/* 20614 */ MCD_OPC_Decode, 242, 1, 89, // Opcode: CMTSTv2i32 -/* 20618 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20636 -/* 20622 */ MCD_OPC_CheckPredicate, 0, 47, 78, // Skip to: 40641 -/* 20626 */ MCD_OPC_CheckField, 21, 1, 1, 41, 78, // Skip to: 40641 -/* 20632 */ MCD_OPC_Decode, 164, 1, 89, // Opcode: CMEQv2i32 -/* 20636 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20654 -/* 20640 */ MCD_OPC_CheckPredicate, 0, 29, 78, // Skip to: 40641 -/* 20644 */ MCD_OPC_CheckField, 21, 1, 1, 23, 78, // Skip to: 40641 -/* 20650 */ MCD_OPC_Decode, 245, 1, 112, // Opcode: CMTSTv4i32 -/* 20654 */ MCD_OPC_FilterValue, 3, 15, 78, // Skip to: 40641 -/* 20658 */ MCD_OPC_CheckPredicate, 0, 11, 78, // Skip to: 40641 -/* 20662 */ MCD_OPC_CheckField, 21, 1, 1, 5, 78, // Skip to: 40641 -/* 20668 */ MCD_OPC_Decode, 170, 1, 112, // Opcode: CMEQv4i32 -/* 20672 */ MCD_OPC_FilterValue, 36, 39, 0, // Skip to: 20715 -/* 20676 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20679 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20697 -/* 20683 */ MCD_OPC_CheckPredicate, 0, 242, 77, // Skip to: 40641 -/* 20687 */ MCD_OPC_CheckField, 21, 1, 1, 236, 77, // Skip to: 40641 -/* 20693 */ MCD_OPC_Decode, 176, 11, 105, // Opcode: SQDMLALv2i32_v2i64 -/* 20697 */ MCD_OPC_FilterValue, 2, 228, 77, // Skip to: 40641 -/* 20701 */ MCD_OPC_CheckPredicate, 0, 224, 77, // Skip to: 40641 -/* 20705 */ MCD_OPC_CheckField, 21, 1, 1, 218, 77, // Skip to: 40641 -/* 20711 */ MCD_OPC_Decode, 180, 11, 120, // Opcode: SQDMLALv4i32_v2i64 -/* 20715 */ MCD_OPC_FilterValue, 37, 75, 0, // Skip to: 20794 -/* 20719 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20722 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20740 -/* 20726 */ MCD_OPC_CheckPredicate, 0, 199, 77, // Skip to: 40641 -/* 20730 */ MCD_OPC_CheckField, 21, 1, 1, 193, 77, // Skip to: 40641 -/* 20736 */ MCD_OPC_Decode, 183, 8, 109, // Opcode: MLAv2i32 -/* 20740 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 20758 -/* 20744 */ MCD_OPC_CheckPredicate, 0, 181, 77, // Skip to: 40641 -/* 20748 */ MCD_OPC_CheckField, 21, 1, 1, 175, 77, // Skip to: 40641 -/* 20754 */ MCD_OPC_Decode, 193, 8, 109, // Opcode: MLSv2i32 -/* 20758 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 20776 -/* 20762 */ MCD_OPC_CheckPredicate, 0, 163, 77, // Skip to: 40641 -/* 20766 */ MCD_OPC_CheckField, 21, 1, 1, 157, 77, // Skip to: 40641 -/* 20772 */ MCD_OPC_Decode, 187, 8, 120, // Opcode: MLAv4i32 -/* 20776 */ MCD_OPC_FilterValue, 3, 149, 77, // Skip to: 40641 -/* 20780 */ MCD_OPC_CheckPredicate, 0, 145, 77, // Skip to: 40641 -/* 20784 */ MCD_OPC_CheckField, 21, 1, 1, 139, 77, // Skip to: 40641 -/* 20790 */ MCD_OPC_Decode, 197, 8, 120, // Opcode: MLSv4i32 -/* 20794 */ MCD_OPC_FilterValue, 38, 127, 0, // Skip to: 20925 -/* 20798 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20801 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 20832 -/* 20805 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 20808 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20820 -/* 20812 */ MCD_OPC_CheckPredicate, 0, 113, 77, // Skip to: 40641 -/* 20816 */ MCD_OPC_Decode, 165, 1, 90, // Opcode: CMEQv2i32rz -/* 20820 */ MCD_OPC_FilterValue, 33, 105, 77, // Skip to: 40641 -/* 20824 */ MCD_OPC_CheckPredicate, 0, 101, 77, // Skip to: 40641 -/* 20828 */ MCD_OPC_Decode, 184, 5, 90, // Opcode: FRINTZv2f32 -/* 20832 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 20863 -/* 20836 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 20839 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20851 -/* 20843 */ MCD_OPC_CheckPredicate, 0, 82, 77, // Skip to: 40641 -/* 20847 */ MCD_OPC_Decode, 226, 1, 90, // Opcode: CMLEv2i32rz -/* 20851 */ MCD_OPC_FilterValue, 33, 74, 77, // Skip to: 40641 -/* 20855 */ MCD_OPC_CheckPredicate, 0, 70, 77, // Skip to: 40641 -/* 20859 */ MCD_OPC_Decode, 159, 5, 90, // Opcode: FRINTIv2f32 -/* 20863 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 20894 -/* 20867 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 20870 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20882 -/* 20874 */ MCD_OPC_CheckPredicate, 0, 51, 77, // Skip to: 40641 -/* 20878 */ MCD_OPC_Decode, 171, 1, 117, // Opcode: CMEQv4i32rz -/* 20882 */ MCD_OPC_FilterValue, 33, 43, 77, // Skip to: 40641 -/* 20886 */ MCD_OPC_CheckPredicate, 0, 39, 77, // Skip to: 40641 -/* 20890 */ MCD_OPC_Decode, 186, 5, 117, // Opcode: FRINTZv4f32 -/* 20894 */ MCD_OPC_FilterValue, 3, 31, 77, // Skip to: 40641 -/* 20898 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 20901 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 20913 -/* 20905 */ MCD_OPC_CheckPredicate, 0, 20, 77, // Skip to: 40641 -/* 20909 */ MCD_OPC_Decode, 229, 1, 117, // Opcode: CMLEv4i32rz -/* 20913 */ MCD_OPC_FilterValue, 33, 12, 77, // Skip to: 40641 -/* 20917 */ MCD_OPC_CheckPredicate, 0, 8, 77, // Skip to: 40641 -/* 20921 */ MCD_OPC_Decode, 161, 5, 117, // Opcode: FRINTIv4f32 -/* 20925 */ MCD_OPC_FilterValue, 39, 39, 0, // Skip to: 20968 -/* 20929 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20932 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20950 -/* 20936 */ MCD_OPC_CheckPredicate, 0, 245, 76, // Skip to: 40641 -/* 20940 */ MCD_OPC_CheckField, 21, 1, 1, 239, 76, // Skip to: 40641 -/* 20946 */ MCD_OPC_Decode, 232, 8, 89, // Opcode: MULv2i32 -/* 20950 */ MCD_OPC_FilterValue, 2, 231, 76, // Skip to: 40641 -/* 20954 */ MCD_OPC_CheckPredicate, 0, 227, 76, // Skip to: 40641 -/* 20958 */ MCD_OPC_CheckField, 21, 1, 1, 221, 76, // Skip to: 40641 -/* 20964 */ MCD_OPC_Decode, 236, 8, 112, // Opcode: MULv4i32 -/* 20968 */ MCD_OPC_FilterValue, 40, 75, 0, // Skip to: 21047 -/* 20972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 20975 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 20993 -/* 20979 */ MCD_OPC_CheckPredicate, 0, 202, 76, // Skip to: 40641 -/* 20983 */ MCD_OPC_CheckField, 21, 1, 1, 196, 76, // Skip to: 40641 -/* 20989 */ MCD_OPC_Decode, 252, 10, 105, // Opcode: SMLSLv2i32_v2i64 -/* 20993 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21011 -/* 20997 */ MCD_OPC_CheckPredicate, 0, 184, 76, // Skip to: 40641 -/* 21001 */ MCD_OPC_CheckField, 21, 1, 1, 178, 76, // Skip to: 40641 -/* 21007 */ MCD_OPC_Decode, 243, 16, 105, // Opcode: UMLSLv2i32_v2i64 -/* 21011 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21029 -/* 21015 */ MCD_OPC_CheckPredicate, 0, 166, 76, // Skip to: 40641 -/* 21019 */ MCD_OPC_CheckField, 21, 1, 1, 160, 76, // Skip to: 40641 -/* 21025 */ MCD_OPC_Decode, 128, 11, 120, // Opcode: SMLSLv4i32_v2i64 -/* 21029 */ MCD_OPC_FilterValue, 3, 152, 76, // Skip to: 40641 -/* 21033 */ MCD_OPC_CheckPredicate, 0, 148, 76, // Skip to: 40641 -/* 21037 */ MCD_OPC_CheckField, 21, 1, 1, 142, 76, // Skip to: 40641 -/* 21043 */ MCD_OPC_Decode, 247, 16, 120, // Opcode: UMLSLv4i32_v2i64 -/* 21047 */ MCD_OPC_FilterValue, 41, 75, 0, // Skip to: 21126 -/* 21051 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21054 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21072 -/* 21058 */ MCD_OPC_CheckPredicate, 0, 123, 76, // Skip to: 40641 -/* 21062 */ MCD_OPC_CheckField, 21, 1, 1, 117, 76, // Skip to: 40641 -/* 21068 */ MCD_OPC_Decode, 206, 10, 89, // Opcode: SMAXPv2i32 -/* 21072 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21090 -/* 21076 */ MCD_OPC_CheckPredicate, 0, 105, 76, // Skip to: 40641 -/* 21080 */ MCD_OPC_CheckField, 21, 1, 1, 99, 76, // Skip to: 40641 -/* 21086 */ MCD_OPC_Decode, 198, 16, 89, // Opcode: UMAXPv2i32 -/* 21090 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21108 -/* 21094 */ MCD_OPC_CheckPredicate, 0, 87, 76, // Skip to: 40641 -/* 21098 */ MCD_OPC_CheckField, 21, 1, 1, 81, 76, // Skip to: 40641 -/* 21104 */ MCD_OPC_Decode, 208, 10, 112, // Opcode: SMAXPv4i32 -/* 21108 */ MCD_OPC_FilterValue, 3, 73, 76, // Skip to: 40641 -/* 21112 */ MCD_OPC_CheckPredicate, 0, 69, 76, // Skip to: 40641 -/* 21116 */ MCD_OPC_CheckField, 21, 1, 1, 63, 76, // Skip to: 40641 -/* 21122 */ MCD_OPC_Decode, 200, 16, 112, // Opcode: UMAXPv4i32 -/* 21126 */ MCD_OPC_FilterValue, 42, 155, 0, // Skip to: 21285 -/* 21130 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21133 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 21164 -/* 21137 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21140 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 21152 -/* 21144 */ MCD_OPC_CheckPredicate, 0, 37, 76, // Skip to: 40641 -/* 21148 */ MCD_OPC_Decode, 234, 1, 90, // Opcode: CMLTv2i32rz -/* 21152 */ MCD_OPC_FilterValue, 2, 29, 76, // Skip to: 40641 -/* 21156 */ MCD_OPC_CheckPredicate, 0, 25, 76, // Skip to: 40641 -/* 21160 */ MCD_OPC_Decode, 237, 1, 117, // Opcode: CMLTv4i32rz -/* 21164 */ MCD_OPC_FilterValue, 33, 51, 0, // Skip to: 21219 -/* 21168 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21171 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 21183 -/* 21175 */ MCD_OPC_CheckPredicate, 0, 6, 76, // Skip to: 40641 -/* 21179 */ MCD_OPC_Decode, 208, 3, 90, // Opcode: FCVTPSv2f32 -/* 21183 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 21195 -/* 21187 */ MCD_OPC_CheckPredicate, 0, 250, 75, // Skip to: 40641 -/* 21191 */ MCD_OPC_Decode, 217, 3, 90, // Opcode: FCVTPUv2f32 -/* 21195 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 21207 -/* 21199 */ MCD_OPC_CheckPredicate, 0, 238, 75, // Skip to: 40641 -/* 21203 */ MCD_OPC_Decode, 210, 3, 117, // Opcode: FCVTPSv4f32 -/* 21207 */ MCD_OPC_FilterValue, 3, 230, 75, // Skip to: 40641 -/* 21211 */ MCD_OPC_CheckPredicate, 0, 226, 75, // Skip to: 40641 -/* 21215 */ MCD_OPC_Decode, 219, 3, 117, // Opcode: FCVTPUv4f32 -/* 21219 */ MCD_OPC_FilterValue, 48, 29, 0, // Skip to: 21252 -/* 21223 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21226 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 21239 -/* 21230 */ MCD_OPC_CheckPredicate, 0, 207, 75, // Skip to: 40641 -/* 21234 */ MCD_OPC_Decode, 213, 10, 139, 1, // Opcode: SMAXVv4i32v -/* 21239 */ MCD_OPC_FilterValue, 3, 198, 75, // Skip to: 40641 -/* 21243 */ MCD_OPC_CheckPredicate, 0, 194, 75, // Skip to: 40641 -/* 21247 */ MCD_OPC_Decode, 205, 16, 139, 1, // Opcode: UMAXVv4i32v -/* 21252 */ MCD_OPC_FilterValue, 49, 185, 75, // Skip to: 40641 -/* 21256 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21259 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 21272 -/* 21263 */ MCD_OPC_CheckPredicate, 0, 174, 75, // Skip to: 40641 -/* 21267 */ MCD_OPC_Decode, 231, 10, 139, 1, // Opcode: SMINVv4i32v -/* 21272 */ MCD_OPC_FilterValue, 3, 165, 75, // Skip to: 40641 -/* 21276 */ MCD_OPC_CheckPredicate, 0, 161, 75, // Skip to: 40641 -/* 21280 */ MCD_OPC_Decode, 222, 16, 139, 1, // Opcode: UMINVv4i32v -/* 21285 */ MCD_OPC_FilterValue, 43, 75, 0, // Skip to: 21364 -/* 21289 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21292 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21310 -/* 21296 */ MCD_OPC_CheckPredicate, 0, 141, 75, // Skip to: 40641 -/* 21300 */ MCD_OPC_CheckField, 21, 1, 1, 135, 75, // Skip to: 40641 -/* 21306 */ MCD_OPC_Decode, 224, 10, 89, // Opcode: SMINPv2i32 -/* 21310 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21328 -/* 21314 */ MCD_OPC_CheckPredicate, 0, 123, 75, // Skip to: 40641 -/* 21318 */ MCD_OPC_CheckField, 21, 1, 1, 117, 75, // Skip to: 40641 -/* 21324 */ MCD_OPC_Decode, 215, 16, 89, // Opcode: UMINPv2i32 -/* 21328 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21346 -/* 21332 */ MCD_OPC_CheckPredicate, 0, 105, 75, // Skip to: 40641 -/* 21336 */ MCD_OPC_CheckField, 21, 1, 1, 99, 75, // Skip to: 40641 -/* 21342 */ MCD_OPC_Decode, 226, 10, 112, // Opcode: SMINPv4i32 -/* 21346 */ MCD_OPC_FilterValue, 3, 91, 75, // Skip to: 40641 -/* 21350 */ MCD_OPC_CheckPredicate, 0, 87, 75, // Skip to: 40641 -/* 21354 */ MCD_OPC_CheckField, 21, 1, 1, 81, 75, // Skip to: 40641 -/* 21360 */ MCD_OPC_Decode, 217, 16, 112, // Opcode: UMINPv4i32 -/* 21364 */ MCD_OPC_FilterValue, 44, 39, 0, // Skip to: 21407 -/* 21368 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21371 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21389 -/* 21375 */ MCD_OPC_CheckPredicate, 0, 62, 75, // Skip to: 40641 -/* 21379 */ MCD_OPC_CheckField, 21, 1, 1, 56, 75, // Skip to: 40641 -/* 21385 */ MCD_OPC_Decode, 188, 11, 105, // Opcode: SQDMLSLv2i32_v2i64 -/* 21389 */ MCD_OPC_FilterValue, 2, 48, 75, // Skip to: 40641 -/* 21393 */ MCD_OPC_CheckPredicate, 0, 44, 75, // Skip to: 40641 -/* 21397 */ MCD_OPC_CheckField, 21, 1, 1, 38, 75, // Skip to: 40641 -/* 21403 */ MCD_OPC_Decode, 192, 11, 120, // Opcode: SQDMLSLv4i32_v2i64 -/* 21407 */ MCD_OPC_FilterValue, 45, 75, 0, // Skip to: 21486 -/* 21411 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21414 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21432 -/* 21418 */ MCD_OPC_CheckPredicate, 0, 19, 75, // Skip to: 40641 -/* 21422 */ MCD_OPC_CheckField, 21, 1, 1, 13, 75, // Skip to: 40641 -/* 21428 */ MCD_OPC_Decode, 199, 11, 89, // Opcode: SQDMULHv2i32 -/* 21432 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21450 -/* 21436 */ MCD_OPC_CheckPredicate, 0, 1, 75, // Skip to: 40641 -/* 21440 */ MCD_OPC_CheckField, 21, 1, 1, 251, 74, // Skip to: 40641 -/* 21446 */ MCD_OPC_Decode, 234, 11, 89, // Opcode: SQRDMULHv2i32 -/* 21450 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21468 -/* 21454 */ MCD_OPC_CheckPredicate, 0, 239, 74, // Skip to: 40641 -/* 21458 */ MCD_OPC_CheckField, 21, 1, 1, 233, 74, // Skip to: 40641 -/* 21464 */ MCD_OPC_Decode, 203, 11, 112, // Opcode: SQDMULHv4i32 -/* 21468 */ MCD_OPC_FilterValue, 3, 225, 74, // Skip to: 40641 -/* 21472 */ MCD_OPC_CheckPredicate, 0, 221, 74, // Skip to: 40641 -/* 21476 */ MCD_OPC_CheckField, 21, 1, 1, 215, 74, // Skip to: 40641 -/* 21482 */ MCD_OPC_Decode, 238, 11, 112, // Opcode: SQRDMULHv4i32 -/* 21486 */ MCD_OPC_FilterValue, 46, 137, 0, // Skip to: 21627 -/* 21490 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21493 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 21523 -/* 21497 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21500 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 21511 -/* 21504 */ MCD_OPC_CheckPredicate, 0, 189, 74, // Skip to: 40641 -/* 21508 */ MCD_OPC_Decode, 24, 90, // Opcode: ABSv2i32 -/* 21511 */ MCD_OPC_FilterValue, 33, 182, 74, // Skip to: 40641 -/* 21515 */ MCD_OPC_CheckPredicate, 0, 178, 74, // Skip to: 40641 -/* 21519 */ MCD_OPC_Decode, 248, 3, 90, // Opcode: FCVTZSv2f32 -/* 21523 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 21554 -/* 21527 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21530 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21542 -/* 21534 */ MCD_OPC_CheckPredicate, 0, 159, 74, // Skip to: 40641 -/* 21538 */ MCD_OPC_Decode, 249, 8, 90, // Opcode: NEGv2i32 -/* 21542 */ MCD_OPC_FilterValue, 33, 151, 74, // Skip to: 40641 -/* 21546 */ MCD_OPC_CheckPredicate, 0, 147, 74, // Skip to: 40641 -/* 21550 */ MCD_OPC_Decode, 149, 4, 90, // Opcode: FCVTZUv2f32 -/* 21554 */ MCD_OPC_FilterValue, 2, 38, 0, // Skip to: 21596 -/* 21558 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21561 */ MCD_OPC_FilterValue, 32, 7, 0, // Skip to: 21572 -/* 21565 */ MCD_OPC_CheckPredicate, 0, 128, 74, // Skip to: 40641 -/* 21569 */ MCD_OPC_Decode, 27, 117, // Opcode: ABSv4i32 -/* 21572 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 21584 -/* 21576 */ MCD_OPC_CheckPredicate, 0, 117, 74, // Skip to: 40641 -/* 21580 */ MCD_OPC_Decode, 252, 3, 117, // Opcode: FCVTZSv4f32 -/* 21584 */ MCD_OPC_FilterValue, 49, 109, 74, // Skip to: 40641 -/* 21588 */ MCD_OPC_CheckPredicate, 0, 105, 74, // Skip to: 40641 -/* 21592 */ MCD_OPC_Decode, 59, 139, 1, // Opcode: ADDVv4i32v -/* 21596 */ MCD_OPC_FilterValue, 3, 97, 74, // Skip to: 40641 -/* 21600 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21603 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21615 -/* 21607 */ MCD_OPC_CheckPredicate, 0, 86, 74, // Skip to: 40641 -/* 21611 */ MCD_OPC_Decode, 252, 8, 117, // Opcode: NEGv4i32 -/* 21615 */ MCD_OPC_FilterValue, 33, 78, 74, // Skip to: 40641 -/* 21619 */ MCD_OPC_CheckPredicate, 0, 74, 74, // Skip to: 40641 -/* 21623 */ MCD_OPC_Decode, 153, 4, 117, // Opcode: FCVTZUv4f32 -/* 21627 */ MCD_OPC_FilterValue, 47, 37, 0, // Skip to: 21668 -/* 21631 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21634 */ MCD_OPC_FilterValue, 0, 13, 0, // Skip to: 21651 -/* 21638 */ MCD_OPC_CheckPredicate, 0, 55, 74, // Skip to: 40641 -/* 21642 */ MCD_OPC_CheckField, 21, 1, 1, 49, 74, // Skip to: 40641 -/* 21648 */ MCD_OPC_Decode, 41, 89, // Opcode: ADDPv2i32 -/* 21651 */ MCD_OPC_FilterValue, 2, 42, 74, // Skip to: 40641 -/* 21655 */ MCD_OPC_CheckPredicate, 0, 38, 74, // Skip to: 40641 -/* 21659 */ MCD_OPC_CheckField, 21, 1, 1, 32, 74, // Skip to: 40641 -/* 21665 */ MCD_OPC_Decode, 45, 112, // Opcode: ADDPv4i32 -/* 21668 */ MCD_OPC_FilterValue, 48, 75, 0, // Skip to: 21747 -/* 21672 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21675 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21693 -/* 21679 */ MCD_OPC_CheckPredicate, 0, 14, 74, // Skip to: 40641 -/* 21683 */ MCD_OPC_CheckField, 21, 1, 1, 8, 74, // Skip to: 40641 -/* 21689 */ MCD_OPC_Decode, 141, 11, 85, // Opcode: SMULLv2i32_v2i64 -/* 21693 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21711 -/* 21697 */ MCD_OPC_CheckPredicate, 0, 252, 73, // Skip to: 40641 -/* 21701 */ MCD_OPC_CheckField, 21, 1, 1, 246, 73, // Skip to: 40641 -/* 21707 */ MCD_OPC_Decode, 131, 17, 85, // Opcode: UMULLv2i32_v2i64 -/* 21711 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21729 -/* 21715 */ MCD_OPC_CheckPredicate, 0, 234, 73, // Skip to: 40641 -/* 21719 */ MCD_OPC_CheckField, 21, 1, 1, 228, 73, // Skip to: 40641 -/* 21725 */ MCD_OPC_Decode, 145, 11, 112, // Opcode: SMULLv4i32_v2i64 -/* 21729 */ MCD_OPC_FilterValue, 3, 220, 73, // Skip to: 40641 -/* 21733 */ MCD_OPC_CheckPredicate, 0, 216, 73, // Skip to: 40641 -/* 21737 */ MCD_OPC_CheckField, 21, 1, 1, 210, 73, // Skip to: 40641 -/* 21743 */ MCD_OPC_Decode, 135, 17, 112, // Opcode: UMULLv4i32_v2i64 -/* 21747 */ MCD_OPC_FilterValue, 49, 75, 0, // Skip to: 21826 -/* 21751 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21754 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21772 -/* 21758 */ MCD_OPC_CheckPredicate, 0, 191, 73, // Skip to: 40641 -/* 21762 */ MCD_OPC_CheckField, 21, 1, 1, 185, 73, // Skip to: 40641 -/* 21768 */ MCD_OPC_Decode, 193, 4, 89, // Opcode: FMINNMv2f32 -/* 21772 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 21790 -/* 21776 */ MCD_OPC_CheckPredicate, 0, 173, 73, // Skip to: 40641 -/* 21780 */ MCD_OPC_CheckField, 21, 1, 1, 167, 73, // Skip to: 40641 -/* 21786 */ MCD_OPC_Decode, 186, 4, 89, // Opcode: FMINNMPv2f32 -/* 21790 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 21808 -/* 21794 */ MCD_OPC_CheckPredicate, 0, 155, 73, // Skip to: 40641 -/* 21798 */ MCD_OPC_CheckField, 21, 1, 1, 149, 73, // Skip to: 40641 -/* 21804 */ MCD_OPC_Decode, 195, 4, 112, // Opcode: FMINNMv4f32 -/* 21808 */ MCD_OPC_FilterValue, 3, 141, 73, // Skip to: 40641 -/* 21812 */ MCD_OPC_CheckPredicate, 0, 137, 73, // Skip to: 40641 -/* 21816 */ MCD_OPC_CheckField, 21, 1, 1, 131, 73, // Skip to: 40641 -/* 21822 */ MCD_OPC_Decode, 190, 4, 112, // Opcode: FMINNMPv4f32 -/* 21826 */ MCD_OPC_FilterValue, 50, 140, 0, // Skip to: 21970 -/* 21830 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21833 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 21864 -/* 21837 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21840 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21852 -/* 21844 */ MCD_OPC_CheckPredicate, 0, 105, 73, // Skip to: 40641 -/* 21848 */ MCD_OPC_Decode, 240, 2, 90, // Opcode: FCMGTv2i32rz -/* 21852 */ MCD_OPC_FilterValue, 33, 97, 73, // Skip to: 40641 -/* 21856 */ MCD_OPC_CheckPredicate, 0, 93, 73, // Skip to: 40641 -/* 21860 */ MCD_OPC_Decode, 221, 17, 90, // Opcode: URECPEv2i32 -/* 21864 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 21895 -/* 21868 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21871 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21883 -/* 21875 */ MCD_OPC_CheckPredicate, 0, 74, 73, // Skip to: 40641 -/* 21879 */ MCD_OPC_Decode, 230, 2, 90, // Opcode: FCMGEv2i32rz -/* 21883 */ MCD_OPC_FilterValue, 33, 66, 73, // Skip to: 40641 -/* 21887 */ MCD_OPC_CheckPredicate, 0, 62, 73, // Skip to: 40641 -/* 21891 */ MCD_OPC_Decode, 245, 17, 90, // Opcode: URSQRTEv2i32 -/* 21895 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 21926 -/* 21899 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21902 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21914 -/* 21906 */ MCD_OPC_CheckPredicate, 0, 43, 73, // Skip to: 40641 -/* 21910 */ MCD_OPC_Decode, 243, 2, 117, // Opcode: FCMGTv4i32rz -/* 21914 */ MCD_OPC_FilterValue, 33, 35, 73, // Skip to: 40641 -/* 21918 */ MCD_OPC_CheckPredicate, 0, 31, 73, // Skip to: 40641 -/* 21922 */ MCD_OPC_Decode, 222, 17, 117, // Opcode: URECPEv4i32 -/* 21926 */ MCD_OPC_FilterValue, 3, 23, 73, // Skip to: 40641 -/* 21930 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 21933 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 21945 -/* 21937 */ MCD_OPC_CheckPredicate, 0, 12, 73, // Skip to: 40641 -/* 21941 */ MCD_OPC_Decode, 233, 2, 117, // Opcode: FCMGEv4i32rz -/* 21945 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 21957 -/* 21949 */ MCD_OPC_CheckPredicate, 0, 0, 73, // Skip to: 40641 -/* 21953 */ MCD_OPC_Decode, 246, 17, 117, // Opcode: URSQRTEv4i32 -/* 21957 */ MCD_OPC_FilterValue, 48, 248, 72, // Skip to: 40641 -/* 21961 */ MCD_OPC_CheckPredicate, 0, 244, 72, // Skip to: 40641 -/* 21965 */ MCD_OPC_Decode, 192, 4, 139, 1, // Opcode: FMINNMVv4i32v -/* 21970 */ MCD_OPC_FilterValue, 51, 39, 0, // Skip to: 22013 -/* 21974 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 21977 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 21995 -/* 21981 */ MCD_OPC_CheckPredicate, 0, 224, 72, // Skip to: 40641 -/* 21985 */ MCD_OPC_CheckField, 21, 1, 1, 218, 72, // Skip to: 40641 -/* 21991 */ MCD_OPC_Decode, 216, 4, 109, // Opcode: FMLSv2f32 -/* 21995 */ MCD_OPC_FilterValue, 2, 210, 72, // Skip to: 40641 -/* 21999 */ MCD_OPC_CheckPredicate, 0, 206, 72, // Skip to: 40641 -/* 22003 */ MCD_OPC_CheckField, 21, 1, 1, 200, 72, // Skip to: 40641 -/* 22009 */ MCD_OPC_Decode, 220, 4, 120, // Opcode: FMLSv4f32 -/* 22013 */ MCD_OPC_FilterValue, 52, 39, 0, // Skip to: 22056 -/* 22017 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22020 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22038 -/* 22024 */ MCD_OPC_CheckPredicate, 0, 181, 72, // Skip to: 40641 -/* 22028 */ MCD_OPC_CheckField, 21, 1, 1, 175, 72, // Skip to: 40641 -/* 22034 */ MCD_OPC_Decode, 212, 11, 85, // Opcode: SQDMULLv2i32_v2i64 -/* 22038 */ MCD_OPC_FilterValue, 2, 167, 72, // Skip to: 40641 -/* 22042 */ MCD_OPC_CheckPredicate, 0, 163, 72, // Skip to: 40641 -/* 22046 */ MCD_OPC_CheckField, 21, 1, 1, 157, 72, // Skip to: 40641 -/* 22052 */ MCD_OPC_Decode, 216, 11, 112, // Opcode: SQDMULLv4i32_v2i64 -/* 22056 */ MCD_OPC_FilterValue, 53, 75, 0, // Skip to: 22135 -/* 22060 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22063 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22081 -/* 22067 */ MCD_OPC_CheckPredicate, 0, 138, 72, // Skip to: 40641 -/* 22071 */ MCD_OPC_CheckField, 21, 1, 1, 132, 72, // Skip to: 40641 -/* 22077 */ MCD_OPC_Decode, 204, 5, 89, // Opcode: FSUBv2f32 -/* 22081 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22099 -/* 22085 */ MCD_OPC_CheckPredicate, 0, 120, 72, // Skip to: 40641 -/* 22089 */ MCD_OPC_CheckField, 21, 1, 1, 114, 72, // Skip to: 40641 -/* 22095 */ MCD_OPC_Decode, 182, 2, 89, // Opcode: FABDv2f32 -/* 22099 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22117 -/* 22103 */ MCD_OPC_CheckPredicate, 0, 102, 72, // Skip to: 40641 -/* 22107 */ MCD_OPC_CheckField, 21, 1, 1, 96, 72, // Skip to: 40641 -/* 22113 */ MCD_OPC_Decode, 206, 5, 112, // Opcode: FSUBv4f32 -/* 22117 */ MCD_OPC_FilterValue, 3, 88, 72, // Skip to: 40641 -/* 22121 */ MCD_OPC_CheckPredicate, 0, 84, 72, // Skip to: 40641 -/* 22125 */ MCD_OPC_CheckField, 21, 1, 1, 78, 72, // Skip to: 40641 -/* 22131 */ MCD_OPC_Decode, 184, 2, 112, // Opcode: FABDv4f32 -/* 22135 */ MCD_OPC_FilterValue, 54, 127, 0, // Skip to: 22266 -/* 22139 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22142 */ MCD_OPC_FilterValue, 0, 27, 0, // Skip to: 22173 -/* 22146 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 22149 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22161 -/* 22153 */ MCD_OPC_CheckPredicate, 0, 52, 72, // Skip to: 40641 -/* 22157 */ MCD_OPC_Decode, 220, 2, 90, // Opcode: FCMEQv2i32rz -/* 22161 */ MCD_OPC_FilterValue, 33, 44, 72, // Skip to: 40641 -/* 22165 */ MCD_OPC_CheckPredicate, 0, 40, 72, // Skip to: 40641 -/* 22169 */ MCD_OPC_Decode, 142, 5, 90, // Opcode: FRECPEv2f32 -/* 22173 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 22204 -/* 22177 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 22180 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22192 -/* 22184 */ MCD_OPC_CheckPredicate, 0, 21, 72, // Skip to: 40641 -/* 22188 */ MCD_OPC_Decode, 246, 2, 90, // Opcode: FCMLEv2i32rz -/* 22192 */ MCD_OPC_FilterValue, 33, 13, 72, // Skip to: 40641 -/* 22196 */ MCD_OPC_CheckPredicate, 0, 9, 72, // Skip to: 40641 -/* 22200 */ MCD_OPC_Decode, 189, 5, 90, // Opcode: FRSQRTEv2f32 -/* 22204 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 22235 -/* 22208 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 22211 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22223 -/* 22215 */ MCD_OPC_CheckPredicate, 0, 246, 71, // Skip to: 40641 -/* 22219 */ MCD_OPC_Decode, 223, 2, 117, // Opcode: FCMEQv4i32rz -/* 22223 */ MCD_OPC_FilterValue, 33, 238, 71, // Skip to: 40641 -/* 22227 */ MCD_OPC_CheckPredicate, 0, 234, 71, // Skip to: 40641 -/* 22231 */ MCD_OPC_Decode, 144, 5, 117, // Opcode: FRECPEv4f32 -/* 22235 */ MCD_OPC_FilterValue, 3, 226, 71, // Skip to: 40641 -/* 22239 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 22242 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22254 -/* 22246 */ MCD_OPC_CheckPredicate, 0, 215, 71, // Skip to: 40641 -/* 22250 */ MCD_OPC_Decode, 248, 2, 117, // Opcode: FCMLEv4i32rz -/* 22254 */ MCD_OPC_FilterValue, 33, 207, 71, // Skip to: 40641 -/* 22258 */ MCD_OPC_CheckPredicate, 0, 203, 71, // Skip to: 40641 -/* 22262 */ MCD_OPC_Decode, 191, 5, 117, // Opcode: FRSQRTEv4f32 -/* 22266 */ MCD_OPC_FilterValue, 57, 39, 0, // Skip to: 22309 -/* 22270 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22273 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22291 -/* 22277 */ MCD_OPC_CheckPredicate, 0, 184, 71, // Skip to: 40641 -/* 22281 */ MCD_OPC_CheckField, 21, 1, 1, 178, 71, // Skip to: 40641 -/* 22287 */ MCD_OPC_Decode, 238, 2, 89, // Opcode: FCMGTv2f32 -/* 22291 */ MCD_OPC_FilterValue, 3, 170, 71, // Skip to: 40641 -/* 22295 */ MCD_OPC_CheckPredicate, 0, 166, 71, // Skip to: 40641 -/* 22299 */ MCD_OPC_CheckField, 21, 1, 1, 160, 71, // Skip to: 40641 -/* 22305 */ MCD_OPC_Decode, 242, 2, 112, // Opcode: FCMGTv4f32 -/* 22309 */ MCD_OPC_FilterValue, 58, 39, 0, // Skip to: 22352 -/* 22313 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22316 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22334 -/* 22320 */ MCD_OPC_CheckPredicate, 0, 141, 71, // Skip to: 40641 -/* 22324 */ MCD_OPC_CheckField, 16, 6, 32, 135, 71, // Skip to: 40641 -/* 22330 */ MCD_OPC_Decode, 251, 2, 90, // Opcode: FCMLTv2i32rz -/* 22334 */ MCD_OPC_FilterValue, 2, 127, 71, // Skip to: 40641 -/* 22338 */ MCD_OPC_CheckPredicate, 0, 123, 71, // Skip to: 40641 -/* 22342 */ MCD_OPC_CheckField, 16, 6, 32, 117, 71, // Skip to: 40641 -/* 22348 */ MCD_OPC_Decode, 253, 2, 117, // Opcode: FCMLTv4i32rz -/* 22352 */ MCD_OPC_FilterValue, 59, 39, 0, // Skip to: 22395 -/* 22356 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22359 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22377 -/* 22363 */ MCD_OPC_CheckPredicate, 0, 98, 71, // Skip to: 40641 -/* 22367 */ MCD_OPC_CheckField, 21, 1, 1, 92, 71, // Skip to: 40641 -/* 22373 */ MCD_OPC_Decode, 197, 2, 89, // Opcode: FACGTv2f32 -/* 22377 */ MCD_OPC_FilterValue, 3, 84, 71, // Skip to: 40641 -/* 22381 */ MCD_OPC_CheckPredicate, 0, 80, 71, // Skip to: 40641 -/* 22385 */ MCD_OPC_CheckField, 21, 1, 1, 74, 71, // Skip to: 40641 -/* 22391 */ MCD_OPC_Decode, 199, 2, 112, // Opcode: FACGTv4f32 -/* 22395 */ MCD_OPC_FilterValue, 61, 75, 0, // Skip to: 22474 -/* 22399 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22402 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22420 -/* 22406 */ MCD_OPC_CheckPredicate, 0, 55, 71, // Skip to: 40641 -/* 22410 */ MCD_OPC_CheckField, 21, 1, 1, 49, 71, // Skip to: 40641 -/* 22416 */ MCD_OPC_Decode, 203, 4, 89, // Opcode: FMINv2f32 -/* 22420 */ MCD_OPC_FilterValue, 1, 14, 0, // Skip to: 22438 -/* 22424 */ MCD_OPC_CheckPredicate, 0, 37, 71, // Skip to: 40641 -/* 22428 */ MCD_OPC_CheckField, 21, 1, 1, 31, 71, // Skip to: 40641 -/* 22434 */ MCD_OPC_Decode, 196, 4, 89, // Opcode: FMINPv2f32 -/* 22438 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22456 -/* 22442 */ MCD_OPC_CheckPredicate, 0, 19, 71, // Skip to: 40641 -/* 22446 */ MCD_OPC_CheckField, 21, 1, 1, 13, 71, // Skip to: 40641 -/* 22452 */ MCD_OPC_Decode, 205, 4, 112, // Opcode: FMINv4f32 -/* 22456 */ MCD_OPC_FilterValue, 3, 5, 71, // Skip to: 40641 -/* 22460 */ MCD_OPC_CheckPredicate, 0, 1, 71, // Skip to: 40641 -/* 22464 */ MCD_OPC_CheckField, 21, 1, 1, 251, 70, // Skip to: 40641 -/* 22470 */ MCD_OPC_Decode, 200, 4, 112, // Opcode: FMINPv4f32 -/* 22474 */ MCD_OPC_FilterValue, 62, 114, 0, // Skip to: 22592 -/* 22478 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22481 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22499 -/* 22485 */ MCD_OPC_CheckPredicate, 0, 232, 70, // Skip to: 40641 -/* 22489 */ MCD_OPC_CheckField, 16, 6, 32, 226, 70, // Skip to: 40641 -/* 22495 */ MCD_OPC_Decode, 187, 2, 90, // Opcode: FABSv2f32 -/* 22499 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 22530 -/* 22503 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 22506 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22518 -/* 22510 */ MCD_OPC_CheckPredicate, 0, 207, 70, // Skip to: 40641 -/* 22514 */ MCD_OPC_Decode, 131, 5, 90, // Opcode: FNEGv2f32 -/* 22518 */ MCD_OPC_FilterValue, 33, 199, 70, // Skip to: 40641 -/* 22522 */ MCD_OPC_CheckPredicate, 0, 195, 70, // Skip to: 40641 -/* 22526 */ MCD_OPC_Decode, 199, 5, 90, // Opcode: FSQRTv2f32 -/* 22530 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22548 -/* 22534 */ MCD_OPC_CheckPredicate, 0, 183, 70, // Skip to: 40641 -/* 22538 */ MCD_OPC_CheckField, 16, 6, 32, 177, 70, // Skip to: 40641 -/* 22544 */ MCD_OPC_Decode, 189, 2, 117, // Opcode: FABSv4f32 -/* 22548 */ MCD_OPC_FilterValue, 3, 169, 70, // Skip to: 40641 -/* 22552 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 22555 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 22567 -/* 22559 */ MCD_OPC_CheckPredicate, 0, 158, 70, // Skip to: 40641 -/* 22563 */ MCD_OPC_Decode, 133, 5, 117, // Opcode: FNEGv4f32 -/* 22567 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 22579 -/* 22571 */ MCD_OPC_CheckPredicate, 0, 146, 70, // Skip to: 40641 -/* 22575 */ MCD_OPC_Decode, 201, 5, 117, // Opcode: FSQRTv4f32 -/* 22579 */ MCD_OPC_FilterValue, 48, 138, 70, // Skip to: 40641 -/* 22583 */ MCD_OPC_CheckPredicate, 0, 134, 70, // Skip to: 40641 -/* 22587 */ MCD_OPC_Decode, 202, 4, 139, 1, // Opcode: FMINVv4i32v -/* 22592 */ MCD_OPC_FilterValue, 63, 125, 70, // Skip to: 40641 -/* 22596 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22599 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22617 -/* 22603 */ MCD_OPC_CheckPredicate, 0, 114, 70, // Skip to: 40641 -/* 22607 */ MCD_OPC_CheckField, 21, 1, 1, 108, 70, // Skip to: 40641 -/* 22613 */ MCD_OPC_Decode, 194, 5, 89, // Opcode: FRSQRTSv2f32 -/* 22617 */ MCD_OPC_FilterValue, 2, 100, 70, // Skip to: 40641 -/* 22621 */ MCD_OPC_CheckPredicate, 0, 96, 70, // Skip to: 40641 -/* 22625 */ MCD_OPC_CheckField, 21, 1, 1, 90, 70, // Skip to: 40641 -/* 22631 */ MCD_OPC_Decode, 196, 5, 112, // Opcode: FRSQRTSv4f32 -/* 22635 */ MCD_OPC_FilterValue, 11, 193, 5, // Skip to: 24112 -/* 22639 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 22642 */ MCD_OPC_FilterValue, 3, 39, 0, // Skip to: 22685 -/* 22646 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22649 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22667 -/* 22653 */ MCD_OPC_CheckPredicate, 0, 64, 70, // Skip to: 40641 -/* 22657 */ MCD_OPC_CheckField, 21, 1, 1, 58, 70, // Skip to: 40641 -/* 22663 */ MCD_OPC_Decode, 166, 11, 112, // Opcode: SQADDv2i64 -/* 22667 */ MCD_OPC_FilterValue, 3, 50, 70, // Skip to: 40641 -/* 22671 */ MCD_OPC_CheckPredicate, 0, 46, 70, // Skip to: 40641 -/* 22675 */ MCD_OPC_CheckField, 21, 1, 1, 40, 70, // Skip to: 40641 -/* 22681 */ MCD_OPC_Decode, 145, 17, 112, // Opcode: UQADDv2i64 -/* 22685 */ MCD_OPC_FilterValue, 6, 20, 0, // Skip to: 22709 -/* 22689 */ MCD_OPC_CheckPredicate, 0, 28, 70, // Skip to: 40641 -/* 22693 */ MCD_OPC_CheckField, 29, 3, 2, 22, 70, // Skip to: 40641 -/* 22699 */ MCD_OPC_CheckField, 21, 1, 0, 16, 70, // Skip to: 40641 -/* 22705 */ MCD_OPC_Decode, 182, 18, 112, // Opcode: UZP1v2i64 -/* 22709 */ MCD_OPC_FilterValue, 7, 73, 0, // Skip to: 22786 -/* 22713 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22716 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22734 -/* 22720 */ MCD_OPC_CheckPredicate, 0, 253, 69, // Skip to: 40641 -/* 22724 */ MCD_OPC_CheckField, 21, 1, 1, 247, 69, // Skip to: 40641 -/* 22730 */ MCD_OPC_Decode, 134, 9, 89, // Opcode: ORNv8i8 -/* 22734 */ MCD_OPC_FilterValue, 1, 13, 0, // Skip to: 22751 -/* 22738 */ MCD_OPC_CheckPredicate, 0, 235, 69, // Skip to: 40641 -/* 22742 */ MCD_OPC_CheckField, 21, 1, 1, 229, 69, // Skip to: 40641 -/* 22748 */ MCD_OPC_Decode, 121, 89, // Opcode: BIFv8i8 -/* 22751 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22769 -/* 22755 */ MCD_OPC_CheckPredicate, 0, 218, 69, // Skip to: 40641 -/* 22759 */ MCD_OPC_CheckField, 21, 1, 1, 212, 69, // Skip to: 40641 -/* 22765 */ MCD_OPC_Decode, 133, 9, 112, // Opcode: ORNv16i8 -/* 22769 */ MCD_OPC_FilterValue, 3, 204, 69, // Skip to: 40641 -/* 22773 */ MCD_OPC_CheckPredicate, 0, 200, 69, // Skip to: 40641 -/* 22777 */ MCD_OPC_CheckField, 21, 1, 1, 194, 69, // Skip to: 40641 -/* 22783 */ MCD_OPC_Decode, 120, 112, // Opcode: BIFv16i8 -/* 22786 */ MCD_OPC_FilterValue, 10, 20, 0, // Skip to: 22810 -/* 22790 */ MCD_OPC_CheckPredicate, 0, 183, 69, // Skip to: 40641 -/* 22794 */ MCD_OPC_CheckField, 29, 3, 2, 177, 69, // Skip to: 40641 -/* 22800 */ MCD_OPC_CheckField, 21, 1, 0, 171, 69, // Skip to: 40641 -/* 22806 */ MCD_OPC_Decode, 223, 15, 112, // Opcode: TRN1v2i64 -/* 22810 */ MCD_OPC_FilterValue, 11, 39, 0, // Skip to: 22853 -/* 22814 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22817 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22835 -/* 22821 */ MCD_OPC_CheckPredicate, 0, 152, 69, // Skip to: 40641 -/* 22825 */ MCD_OPC_CheckField, 21, 1, 1, 146, 69, // Skip to: 40641 -/* 22831 */ MCD_OPC_Decode, 200, 12, 112, // Opcode: SQSUBv2i64 -/* 22835 */ MCD_OPC_FilterValue, 3, 138, 69, // Skip to: 40641 -/* 22839 */ MCD_OPC_CheckPredicate, 0, 134, 69, // Skip to: 40641 -/* 22843 */ MCD_OPC_CheckField, 21, 1, 1, 128, 69, // Skip to: 40641 -/* 22849 */ MCD_OPC_Decode, 207, 17, 112, // Opcode: UQSUBv2i64 -/* 22853 */ MCD_OPC_FilterValue, 13, 39, 0, // Skip to: 22896 -/* 22857 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22860 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22878 -/* 22864 */ MCD_OPC_CheckPredicate, 0, 109, 69, // Skip to: 40641 -/* 22868 */ MCD_OPC_CheckField, 21, 1, 1, 103, 69, // Skip to: 40641 -/* 22874 */ MCD_OPC_Decode, 198, 1, 112, // Opcode: CMGTv2i64 -/* 22878 */ MCD_OPC_FilterValue, 3, 95, 69, // Skip to: 40641 -/* 22882 */ MCD_OPC_CheckPredicate, 0, 91, 69, // Skip to: 40641 -/* 22886 */ MCD_OPC_CheckField, 21, 1, 1, 85, 69, // Skip to: 40641 -/* 22892 */ MCD_OPC_Decode, 211, 1, 112, // Opcode: CMHIv2i64 -/* 22896 */ MCD_OPC_FilterValue, 14, 64, 0, // Skip to: 22964 -/* 22900 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 22903 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 22921 -/* 22907 */ MCD_OPC_CheckPredicate, 0, 66, 69, // Skip to: 40641 -/* 22911 */ MCD_OPC_CheckField, 29, 3, 2, 60, 69, // Skip to: 40641 -/* 22917 */ MCD_OPC_Decode, 202, 18, 112, // Opcode: ZIP1v2i64 -/* 22921 */ MCD_OPC_FilterValue, 1, 52, 69, // Skip to: 40641 -/* 22925 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22928 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22946 -/* 22932 */ MCD_OPC_CheckPredicate, 0, 41, 69, // Skip to: 40641 -/* 22936 */ MCD_OPC_CheckField, 16, 5, 0, 35, 69, // Skip to: 40641 -/* 22942 */ MCD_OPC_Decode, 189, 15, 126, // Opcode: SUQADDv2i64 -/* 22946 */ MCD_OPC_FilterValue, 3, 27, 69, // Skip to: 40641 -/* 22950 */ MCD_OPC_CheckPredicate, 0, 23, 69, // Skip to: 40641 -/* 22954 */ MCD_OPC_CheckField, 16, 5, 0, 17, 69, // Skip to: 40641 -/* 22960 */ MCD_OPC_Decode, 155, 18, 126, // Opcode: USQADDv2i64 -/* 22964 */ MCD_OPC_FilterValue, 15, 39, 0, // Skip to: 23007 -/* 22968 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 22971 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 22989 -/* 22975 */ MCD_OPC_CheckPredicate, 0, 254, 68, // Skip to: 40641 -/* 22979 */ MCD_OPC_CheckField, 21, 1, 1, 248, 68, // Skip to: 40641 -/* 22985 */ MCD_OPC_Decode, 182, 1, 112, // Opcode: CMGEv2i64 -/* 22989 */ MCD_OPC_FilterValue, 3, 240, 68, // Skip to: 40641 -/* 22993 */ MCD_OPC_CheckPredicate, 0, 236, 68, // Skip to: 40641 -/* 22997 */ MCD_OPC_CheckField, 21, 1, 1, 230, 68, // Skip to: 40641 -/* 23003 */ MCD_OPC_Decode, 219, 1, 112, // Opcode: CMHSv2i64 -/* 23007 */ MCD_OPC_FilterValue, 17, 39, 0, // Skip to: 23050 -/* 23011 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23014 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23032 -/* 23018 */ MCD_OPC_CheckPredicate, 0, 211, 68, // Skip to: 40641 -/* 23022 */ MCD_OPC_CheckField, 21, 1, 1, 205, 68, // Skip to: 40641 -/* 23028 */ MCD_OPC_Decode, 142, 13, 112, // Opcode: SSHLv2i64 -/* 23032 */ MCD_OPC_FilterValue, 3, 197, 68, // Skip to: 40641 -/* 23036 */ MCD_OPC_CheckPredicate, 0, 193, 68, // Skip to: 40641 -/* 23040 */ MCD_OPC_CheckField, 21, 1, 1, 187, 68, // Skip to: 40641 -/* 23046 */ MCD_OPC_Decode, 136, 18, 112, // Opcode: USHLv2i64 -/* 23050 */ MCD_OPC_FilterValue, 19, 39, 0, // Skip to: 23093 -/* 23054 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23057 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23075 -/* 23061 */ MCD_OPC_CheckPredicate, 0, 168, 68, // Skip to: 40641 -/* 23065 */ MCD_OPC_CheckField, 21, 1, 1, 162, 68, // Skip to: 40641 -/* 23071 */ MCD_OPC_Decode, 166, 12, 112, // Opcode: SQSHLv2i64 -/* 23075 */ MCD_OPC_FilterValue, 3, 154, 68, // Skip to: 40641 -/* 23079 */ MCD_OPC_CheckPredicate, 0, 150, 68, // Skip to: 40641 -/* 23083 */ MCD_OPC_CheckField, 21, 1, 1, 144, 68, // Skip to: 40641 -/* 23089 */ MCD_OPC_Decode, 182, 17, 112, // Opcode: UQSHLv2i64 -/* 23093 */ MCD_OPC_FilterValue, 21, 39, 0, // Skip to: 23136 -/* 23097 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23100 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23118 -/* 23104 */ MCD_OPC_CheckPredicate, 0, 125, 68, // Skip to: 40641 -/* 23108 */ MCD_OPC_CheckField, 21, 1, 1, 119, 68, // Skip to: 40641 -/* 23114 */ MCD_OPC_Decode, 240, 12, 112, // Opcode: SRSHLv2i64 -/* 23118 */ MCD_OPC_FilterValue, 3, 111, 68, // Skip to: 40641 -/* 23122 */ MCD_OPC_CheckPredicate, 0, 107, 68, // Skip to: 40641 -/* 23126 */ MCD_OPC_CheckField, 21, 1, 1, 101, 68, // Skip to: 40641 -/* 23132 */ MCD_OPC_Decode, 232, 17, 112, // Opcode: URSHLv2i64 -/* 23136 */ MCD_OPC_FilterValue, 22, 20, 0, // Skip to: 23160 -/* 23140 */ MCD_OPC_CheckPredicate, 0, 89, 68, // Skip to: 40641 -/* 23144 */ MCD_OPC_CheckField, 29, 3, 2, 83, 68, // Skip to: 40641 -/* 23150 */ MCD_OPC_CheckField, 21, 1, 0, 77, 68, // Skip to: 40641 -/* 23156 */ MCD_OPC_Decode, 189, 18, 112, // Opcode: UZP2v2i64 -/* 23160 */ MCD_OPC_FilterValue, 23, 39, 0, // Skip to: 23203 -/* 23164 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23167 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23185 -/* 23171 */ MCD_OPC_CheckPredicate, 0, 58, 68, // Skip to: 40641 -/* 23175 */ MCD_OPC_CheckField, 21, 1, 1, 52, 68, // Skip to: 40641 -/* 23181 */ MCD_OPC_Decode, 248, 11, 112, // Opcode: SQRSHLv2i64 -/* 23185 */ MCD_OPC_FilterValue, 3, 44, 68, // Skip to: 40641 -/* 23189 */ MCD_OPC_CheckPredicate, 0, 40, 68, // Skip to: 40641 -/* 23193 */ MCD_OPC_CheckField, 21, 1, 1, 34, 68, // Skip to: 40641 -/* 23199 */ MCD_OPC_Decode, 156, 17, 112, // Opcode: UQRSHLv2i64 -/* 23203 */ MCD_OPC_FilterValue, 26, 20, 0, // Skip to: 23227 -/* 23207 */ MCD_OPC_CheckPredicate, 0, 22, 68, // Skip to: 40641 -/* 23211 */ MCD_OPC_CheckField, 29, 3, 2, 16, 68, // Skip to: 40641 -/* 23217 */ MCD_OPC_CheckField, 21, 1, 0, 10, 68, // Skip to: 40641 -/* 23223 */ MCD_OPC_Decode, 230, 15, 112, // Opcode: TRN2v2i64 -/* 23227 */ MCD_OPC_FilterValue, 30, 64, 0, // Skip to: 23295 -/* 23231 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 23234 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 23252 -/* 23238 */ MCD_OPC_CheckPredicate, 0, 247, 67, // Skip to: 40641 -/* 23242 */ MCD_OPC_CheckField, 29, 3, 2, 241, 67, // Skip to: 40641 -/* 23248 */ MCD_OPC_Decode, 209, 18, 112, // Opcode: ZIP2v2i64 -/* 23252 */ MCD_OPC_FilterValue, 1, 233, 67, // Skip to: 40641 -/* 23256 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23259 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23277 -/* 23263 */ MCD_OPC_CheckPredicate, 0, 222, 67, // Skip to: 40641 -/* 23267 */ MCD_OPC_CheckField, 16, 5, 0, 216, 67, // Skip to: 40641 -/* 23273 */ MCD_OPC_Decode, 155, 11, 117, // Opcode: SQABSv2i64 -/* 23277 */ MCD_OPC_FilterValue, 3, 208, 67, // Skip to: 40641 -/* 23281 */ MCD_OPC_CheckPredicate, 0, 204, 67, // Skip to: 40641 -/* 23285 */ MCD_OPC_CheckField, 16, 5, 0, 198, 67, // Skip to: 40641 -/* 23291 */ MCD_OPC_Decode, 225, 11, 117, // Opcode: SQNEGv2i64 -/* 23295 */ MCD_OPC_FilterValue, 33, 38, 0, // Skip to: 23337 -/* 23299 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23302 */ MCD_OPC_FilterValue, 2, 13, 0, // Skip to: 23319 -/* 23306 */ MCD_OPC_CheckPredicate, 0, 179, 67, // Skip to: 40641 -/* 23310 */ MCD_OPC_CheckField, 21, 1, 1, 173, 67, // Skip to: 40641 -/* 23316 */ MCD_OPC_Decode, 74, 112, // Opcode: ADDv2i64 -/* 23319 */ MCD_OPC_FilterValue, 3, 166, 67, // Skip to: 40641 -/* 23323 */ MCD_OPC_CheckPredicate, 0, 162, 67, // Skip to: 40641 -/* 23327 */ MCD_OPC_CheckField, 21, 1, 1, 156, 67, // Skip to: 40641 -/* 23333 */ MCD_OPC_Decode, 178, 15, 112, // Opcode: SUBv2i64 -/* 23337 */ MCD_OPC_FilterValue, 34, 52, 0, // Skip to: 23393 -/* 23341 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 23344 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23375 -/* 23348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23351 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23363 -/* 23355 */ MCD_OPC_CheckPredicate, 0, 130, 67, // Skip to: 40641 -/* 23359 */ MCD_OPC_Decode, 199, 1, 117, // Opcode: CMGTv2i64rz -/* 23363 */ MCD_OPC_FilterValue, 3, 122, 67, // Skip to: 40641 -/* 23367 */ MCD_OPC_CheckPredicate, 0, 118, 67, // Skip to: 40641 -/* 23371 */ MCD_OPC_Decode, 183, 1, 117, // Opcode: CMGEv2i64rz -/* 23375 */ MCD_OPC_FilterValue, 33, 110, 67, // Skip to: 40641 -/* 23379 */ MCD_OPC_CheckPredicate, 0, 106, 67, // Skip to: 40641 -/* 23383 */ MCD_OPC_CheckField, 29, 3, 2, 100, 67, // Skip to: 40641 -/* 23389 */ MCD_OPC_Decode, 175, 5, 117, // Opcode: FRINTPv2f64 -/* 23393 */ MCD_OPC_FilterValue, 35, 39, 0, // Skip to: 23436 -/* 23397 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23400 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23418 -/* 23404 */ MCD_OPC_CheckPredicate, 0, 81, 67, // Skip to: 40641 -/* 23408 */ MCD_OPC_CheckField, 21, 1, 1, 75, 67, // Skip to: 40641 -/* 23414 */ MCD_OPC_Decode, 243, 1, 112, // Opcode: CMTSTv2i64 -/* 23418 */ MCD_OPC_FilterValue, 3, 67, 67, // Skip to: 40641 -/* 23422 */ MCD_OPC_CheckPredicate, 0, 63, 67, // Skip to: 40641 -/* 23426 */ MCD_OPC_CheckField, 21, 1, 1, 57, 67, // Skip to: 40641 -/* 23432 */ MCD_OPC_Decode, 166, 1, 112, // Opcode: CMEQv2i64 -/* 23436 */ MCD_OPC_FilterValue, 38, 65, 0, // Skip to: 23505 -/* 23440 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 23443 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23474 -/* 23447 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23450 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23462 -/* 23454 */ MCD_OPC_CheckPredicate, 0, 31, 67, // Skip to: 40641 -/* 23458 */ MCD_OPC_Decode, 167, 1, 117, // Opcode: CMEQv2i64rz -/* 23462 */ MCD_OPC_FilterValue, 3, 23, 67, // Skip to: 40641 -/* 23466 */ MCD_OPC_CheckPredicate, 0, 19, 67, // Skip to: 40641 -/* 23470 */ MCD_OPC_Decode, 227, 1, 117, // Opcode: CMLEv2i64rz -/* 23474 */ MCD_OPC_FilterValue, 33, 11, 67, // Skip to: 40641 -/* 23478 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23481 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23493 -/* 23485 */ MCD_OPC_CheckPredicate, 0, 0, 67, // Skip to: 40641 -/* 23489 */ MCD_OPC_Decode, 185, 5, 117, // Opcode: FRINTZv2f64 -/* 23493 */ MCD_OPC_FilterValue, 3, 248, 66, // Skip to: 40641 -/* 23497 */ MCD_OPC_CheckPredicate, 0, 244, 66, // Skip to: 40641 -/* 23501 */ MCD_OPC_Decode, 160, 5, 117, // Opcode: FRINTIv2f64 -/* 23505 */ MCD_OPC_FilterValue, 42, 52, 0, // Skip to: 23561 -/* 23509 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 23512 */ MCD_OPC_FilterValue, 32, 14, 0, // Skip to: 23530 -/* 23516 */ MCD_OPC_CheckPredicate, 0, 225, 66, // Skip to: 40641 -/* 23520 */ MCD_OPC_CheckField, 29, 3, 2, 219, 66, // Skip to: 40641 -/* 23526 */ MCD_OPC_Decode, 235, 1, 117, // Opcode: CMLTv2i64rz -/* 23530 */ MCD_OPC_FilterValue, 33, 211, 66, // Skip to: 40641 -/* 23534 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23537 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23549 -/* 23541 */ MCD_OPC_CheckPredicate, 0, 200, 66, // Skip to: 40641 -/* 23545 */ MCD_OPC_Decode, 209, 3, 117, // Opcode: FCVTPSv2f64 -/* 23549 */ MCD_OPC_FilterValue, 3, 192, 66, // Skip to: 40641 -/* 23553 */ MCD_OPC_CheckPredicate, 0, 188, 66, // Skip to: 40641 -/* 23557 */ MCD_OPC_Decode, 218, 3, 117, // Opcode: FCVTPUv2f64 -/* 23561 */ MCD_OPC_FilterValue, 46, 64, 0, // Skip to: 23629 -/* 23565 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 23568 */ MCD_OPC_FilterValue, 32, 26, 0, // Skip to: 23598 -/* 23572 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23575 */ MCD_OPC_FilterValue, 2, 7, 0, // Skip to: 23586 -/* 23579 */ MCD_OPC_CheckPredicate, 0, 162, 66, // Skip to: 40641 -/* 23583 */ MCD_OPC_Decode, 25, 117, // Opcode: ABSv2i64 -/* 23586 */ MCD_OPC_FilterValue, 3, 155, 66, // Skip to: 40641 -/* 23590 */ MCD_OPC_CheckPredicate, 0, 151, 66, // Skip to: 40641 -/* 23594 */ MCD_OPC_Decode, 250, 8, 117, // Opcode: NEGv2i64 -/* 23598 */ MCD_OPC_FilterValue, 33, 143, 66, // Skip to: 40641 -/* 23602 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23605 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23617 -/* 23609 */ MCD_OPC_CheckPredicate, 0, 132, 66, // Skip to: 40641 -/* 23613 */ MCD_OPC_Decode, 249, 3, 117, // Opcode: FCVTZSv2f64 -/* 23617 */ MCD_OPC_FilterValue, 3, 124, 66, // Skip to: 40641 -/* 23621 */ MCD_OPC_CheckPredicate, 0, 120, 66, // Skip to: 40641 -/* 23625 */ MCD_OPC_Decode, 150, 4, 117, // Opcode: FCVTZUv2f64 -/* 23629 */ MCD_OPC_FilterValue, 47, 19, 0, // Skip to: 23652 -/* 23633 */ MCD_OPC_CheckPredicate, 0, 108, 66, // Skip to: 40641 -/* 23637 */ MCD_OPC_CheckField, 29, 3, 2, 102, 66, // Skip to: 40641 -/* 23643 */ MCD_OPC_CheckField, 21, 1, 1, 96, 66, // Skip to: 40641 -/* 23649 */ MCD_OPC_Decode, 42, 112, // Opcode: ADDPv2i64 -/* 23652 */ MCD_OPC_FilterValue, 49, 39, 0, // Skip to: 23695 -/* 23656 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23659 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23677 -/* 23663 */ MCD_OPC_CheckPredicate, 0, 78, 66, // Skip to: 40641 -/* 23667 */ MCD_OPC_CheckField, 21, 1, 1, 72, 66, // Skip to: 40641 -/* 23673 */ MCD_OPC_Decode, 194, 4, 112, // Opcode: FMINNMv2f64 -/* 23677 */ MCD_OPC_FilterValue, 3, 64, 66, // Skip to: 40641 -/* 23681 */ MCD_OPC_CheckPredicate, 0, 60, 66, // Skip to: 40641 -/* 23685 */ MCD_OPC_CheckField, 21, 1, 1, 54, 66, // Skip to: 40641 -/* 23691 */ MCD_OPC_Decode, 187, 4, 112, // Opcode: FMINNMPv2f64 -/* 23695 */ MCD_OPC_FilterValue, 50, 39, 0, // Skip to: 23738 -/* 23699 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23702 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23720 -/* 23706 */ MCD_OPC_CheckPredicate, 0, 35, 66, // Skip to: 40641 -/* 23710 */ MCD_OPC_CheckField, 16, 6, 32, 29, 66, // Skip to: 40641 -/* 23716 */ MCD_OPC_Decode, 241, 2, 117, // Opcode: FCMGTv2i64rz -/* 23720 */ MCD_OPC_FilterValue, 3, 21, 66, // Skip to: 40641 -/* 23724 */ MCD_OPC_CheckPredicate, 0, 17, 66, // Skip to: 40641 -/* 23728 */ MCD_OPC_CheckField, 16, 6, 32, 11, 66, // Skip to: 40641 -/* 23734 */ MCD_OPC_Decode, 231, 2, 117, // Opcode: FCMGEv2i64rz -/* 23738 */ MCD_OPC_FilterValue, 51, 20, 0, // Skip to: 23762 -/* 23742 */ MCD_OPC_CheckPredicate, 0, 255, 65, // Skip to: 40641 -/* 23746 */ MCD_OPC_CheckField, 29, 3, 2, 249, 65, // Skip to: 40641 -/* 23752 */ MCD_OPC_CheckField, 21, 1, 1, 243, 65, // Skip to: 40641 -/* 23758 */ MCD_OPC_Decode, 217, 4, 120, // Opcode: FMLSv2f64 -/* 23762 */ MCD_OPC_FilterValue, 53, 39, 0, // Skip to: 23805 -/* 23766 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23769 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 23787 -/* 23773 */ MCD_OPC_CheckPredicate, 0, 224, 65, // Skip to: 40641 -/* 23777 */ MCD_OPC_CheckField, 21, 1, 1, 218, 65, // Skip to: 40641 -/* 23783 */ MCD_OPC_Decode, 205, 5, 112, // Opcode: FSUBv2f64 -/* 23787 */ MCD_OPC_FilterValue, 3, 210, 65, // Skip to: 40641 -/* 23791 */ MCD_OPC_CheckPredicate, 0, 206, 65, // Skip to: 40641 -/* 23795 */ MCD_OPC_CheckField, 21, 1, 1, 200, 65, // Skip to: 40641 -/* 23801 */ MCD_OPC_Decode, 183, 2, 112, // Opcode: FABDv2f64 -/* 23805 */ MCD_OPC_FilterValue, 54, 65, 0, // Skip to: 23874 -/* 23809 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 23812 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 23843 -/* 23816 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23819 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23831 -/* 23823 */ MCD_OPC_CheckPredicate, 0, 174, 65, // Skip to: 40641 -/* 23827 */ MCD_OPC_Decode, 221, 2, 117, // Opcode: FCMEQv2i64rz -/* 23831 */ MCD_OPC_FilterValue, 3, 166, 65, // Skip to: 40641 -/* 23835 */ MCD_OPC_CheckPredicate, 0, 162, 65, // Skip to: 40641 -/* 23839 */ MCD_OPC_Decode, 247, 2, 117, // Opcode: FCMLEv2i64rz -/* 23843 */ MCD_OPC_FilterValue, 33, 154, 65, // Skip to: 40641 -/* 23847 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23850 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 23862 -/* 23854 */ MCD_OPC_CheckPredicate, 0, 143, 65, // Skip to: 40641 -/* 23858 */ MCD_OPC_Decode, 143, 5, 117, // Opcode: FRECPEv2f64 -/* 23862 */ MCD_OPC_FilterValue, 3, 135, 65, // Skip to: 40641 -/* 23866 */ MCD_OPC_CheckPredicate, 0, 131, 65, // Skip to: 40641 -/* 23870 */ MCD_OPC_Decode, 190, 5, 117, // Opcode: FRSQRTEv2f64 -/* 23874 */ MCD_OPC_FilterValue, 56, 39, 0, // Skip to: 23917 -/* 23878 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23881 */ MCD_OPC_FilterValue, 0, 14, 0, // Skip to: 23899 -/* 23885 */ MCD_OPC_CheckPredicate, 1, 112, 65, // Skip to: 40641 -/* 23889 */ MCD_OPC_CheckField, 21, 1, 1, 106, 65, // Skip to: 40641 -/* 23895 */ MCD_OPC_Decode, 148, 9, 85, // Opcode: PMULLv1i64 -/* 23899 */ MCD_OPC_FilterValue, 2, 98, 65, // Skip to: 40641 -/* 23903 */ MCD_OPC_CheckPredicate, 1, 94, 65, // Skip to: 40641 -/* 23907 */ MCD_OPC_CheckField, 21, 1, 1, 88, 65, // Skip to: 40641 -/* 23913 */ MCD_OPC_Decode, 149, 9, 112, // Opcode: PMULLv2i64 -/* 23917 */ MCD_OPC_FilterValue, 57, 20, 0, // Skip to: 23941 -/* 23921 */ MCD_OPC_CheckPredicate, 0, 76, 65, // Skip to: 40641 -/* 23925 */ MCD_OPC_CheckField, 29, 3, 3, 70, 65, // Skip to: 40641 -/* 23931 */ MCD_OPC_CheckField, 21, 1, 1, 64, 65, // Skip to: 40641 -/* 23937 */ MCD_OPC_Decode, 239, 2, 112, // Opcode: FCMGTv2f64 -/* 23941 */ MCD_OPC_FilterValue, 58, 20, 0, // Skip to: 23965 -/* 23945 */ MCD_OPC_CheckPredicate, 0, 52, 65, // Skip to: 40641 -/* 23949 */ MCD_OPC_CheckField, 29, 3, 2, 46, 65, // Skip to: 40641 -/* 23955 */ MCD_OPC_CheckField, 16, 6, 32, 40, 65, // Skip to: 40641 -/* 23961 */ MCD_OPC_Decode, 252, 2, 117, // Opcode: FCMLTv2i64rz -/* 23965 */ MCD_OPC_FilterValue, 59, 20, 0, // Skip to: 23989 -/* 23969 */ MCD_OPC_CheckPredicate, 0, 28, 65, // Skip to: 40641 -/* 23973 */ MCD_OPC_CheckField, 29, 3, 3, 22, 65, // Skip to: 40641 -/* 23979 */ MCD_OPC_CheckField, 21, 1, 1, 16, 65, // Skip to: 40641 -/* 23985 */ MCD_OPC_Decode, 198, 2, 112, // Opcode: FACGTv2f64 -/* 23989 */ MCD_OPC_FilterValue, 61, 39, 0, // Skip to: 24032 -/* 23993 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 23996 */ MCD_OPC_FilterValue, 2, 14, 0, // Skip to: 24014 -/* 24000 */ MCD_OPC_CheckPredicate, 0, 253, 64, // Skip to: 40641 -/* 24004 */ MCD_OPC_CheckField, 21, 1, 1, 247, 64, // Skip to: 40641 -/* 24010 */ MCD_OPC_Decode, 204, 4, 112, // Opcode: FMINv2f64 -/* 24014 */ MCD_OPC_FilterValue, 3, 239, 64, // Skip to: 40641 -/* 24018 */ MCD_OPC_CheckPredicate, 0, 235, 64, // Skip to: 40641 -/* 24022 */ MCD_OPC_CheckField, 21, 1, 1, 229, 64, // Skip to: 40641 -/* 24028 */ MCD_OPC_Decode, 197, 4, 112, // Opcode: FMINPv2f64 -/* 24032 */ MCD_OPC_FilterValue, 62, 52, 0, // Skip to: 24088 -/* 24036 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 24039 */ MCD_OPC_FilterValue, 32, 27, 0, // Skip to: 24070 -/* 24043 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 24046 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 24058 -/* 24050 */ MCD_OPC_CheckPredicate, 0, 203, 64, // Skip to: 40641 -/* 24054 */ MCD_OPC_Decode, 188, 2, 117, // Opcode: FABSv2f64 -/* 24058 */ MCD_OPC_FilterValue, 3, 195, 64, // Skip to: 40641 -/* 24062 */ MCD_OPC_CheckPredicate, 0, 191, 64, // Skip to: 40641 -/* 24066 */ MCD_OPC_Decode, 132, 5, 117, // Opcode: FNEGv2f64 -/* 24070 */ MCD_OPC_FilterValue, 33, 183, 64, // Skip to: 40641 -/* 24074 */ MCD_OPC_CheckPredicate, 0, 179, 64, // Skip to: 40641 -/* 24078 */ MCD_OPC_CheckField, 29, 3, 3, 173, 64, // Skip to: 40641 -/* 24084 */ MCD_OPC_Decode, 200, 5, 117, // Opcode: FSQRTv2f64 -/* 24088 */ MCD_OPC_FilterValue, 63, 165, 64, // Skip to: 40641 -/* 24092 */ MCD_OPC_CheckPredicate, 0, 161, 64, // Skip to: 40641 -/* 24096 */ MCD_OPC_CheckField, 29, 3, 2, 155, 64, // Skip to: 40641 -/* 24102 */ MCD_OPC_CheckField, 21, 1, 1, 149, 64, // Skip to: 40641 -/* 24108 */ MCD_OPC_Decode, 195, 5, 112, // Opcode: FRSQRTSv2f64 -/* 24112 */ MCD_OPC_FilterValue, 12, 165, 13, // Skip to: 27609 -/* 24116 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 24119 */ MCD_OPC_FilterValue, 0, 66, 3, // Skip to: 24957 -/* 24123 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 24126 */ MCD_OPC_FilterValue, 1, 171, 2, // Skip to: 24813 -/* 24130 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 24133 */ MCD_OPC_FilterValue, 0, 91, 1, // Skip to: 24484 -/* 24137 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 24140 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 24273 -/* 24144 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24147 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 24240 -/* 24151 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24154 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 24207 -/* 24158 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 24161 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24174 -/* 24165 */ MCD_OPC_CheckPredicate, 0, 88, 64, // Skip to: 40641 -/* 24169 */ MCD_OPC_Decode, 205, 8, 145, 1, // Opcode: MOVIv2i32 -/* 24174 */ MCD_OPC_FilterValue, 1, 79, 64, // Skip to: 40641 -/* 24178 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 24181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24194 -/* 24185 */ MCD_OPC_CheckPredicate, 0, 68, 64, // Skip to: 40641 -/* 24189 */ MCD_OPC_Decode, 154, 13, 146, 1, // Opcode: SSHRv8i8_shift -/* 24194 */ MCD_OPC_FilterValue, 1, 59, 64, // Skip to: 40641 -/* 24198 */ MCD_OPC_CheckPredicate, 0, 55, 64, // Skip to: 40641 -/* 24202 */ MCD_OPC_Decode, 252, 12, 146, 1, // Opcode: SRSHRv8i8_shift -/* 24207 */ MCD_OPC_FilterValue, 1, 46, 64, // Skip to: 40641 -/* 24211 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 24214 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24227 -/* 24218 */ MCD_OPC_CheckPredicate, 0, 35, 64, // Skip to: 40641 -/* 24222 */ MCD_OPC_Decode, 151, 13, 147, 1, // Opcode: SSHRv4i16_shift -/* 24227 */ MCD_OPC_FilterValue, 1, 26, 64, // Skip to: 40641 -/* 24231 */ MCD_OPC_CheckPredicate, 0, 22, 64, // Skip to: 40641 -/* 24235 */ MCD_OPC_Decode, 249, 12, 147, 1, // Opcode: SRSHRv4i16_shift -/* 24240 */ MCD_OPC_FilterValue, 1, 13, 64, // Skip to: 40641 -/* 24244 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 24247 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24260 -/* 24251 */ MCD_OPC_CheckPredicate, 0, 2, 64, // Skip to: 40641 -/* 24255 */ MCD_OPC_Decode, 149, 13, 148, 1, // Opcode: SSHRv2i32_shift -/* 24260 */ MCD_OPC_FilterValue, 1, 249, 63, // Skip to: 40641 -/* 24264 */ MCD_OPC_CheckPredicate, 0, 245, 63, // Skip to: 40641 -/* 24268 */ MCD_OPC_Decode, 247, 12, 148, 1, // Opcode: SRSHRv2i32_shift -/* 24273 */ MCD_OPC_FilterValue, 1, 236, 63, // Skip to: 40641 -/* 24277 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24280 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 24425 -/* 24284 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24287 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 24366 -/* 24291 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 24294 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24307 -/* 24298 */ MCD_OPC_CheckPredicate, 0, 211, 63, // Skip to: 40641 -/* 24302 */ MCD_OPC_Decode, 142, 9, 149, 1, // Opcode: ORRv2i32 -/* 24307 */ MCD_OPC_FilterValue, 1, 202, 63, // Skip to: 40641 -/* 24311 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 24314 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24327 -/* 24318 */ MCD_OPC_CheckPredicate, 0, 191, 63, // Skip to: 40641 -/* 24322 */ MCD_OPC_Decode, 162, 13, 150, 1, // Opcode: SSRAv8i8_shift -/* 24327 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24340 -/* 24331 */ MCD_OPC_CheckPredicate, 0, 178, 63, // Skip to: 40641 -/* 24335 */ MCD_OPC_Decode, 132, 13, 150, 1, // Opcode: SRSRAv8i8_shift -/* 24340 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24353 -/* 24344 */ MCD_OPC_CheckPredicate, 0, 165, 63, // Skip to: 40641 -/* 24348 */ MCD_OPC_Decode, 183, 10, 151, 1, // Opcode: SHLv8i8_shift -/* 24353 */ MCD_OPC_FilterValue, 3, 156, 63, // Skip to: 40641 -/* 24357 */ MCD_OPC_CheckPredicate, 0, 152, 63, // Skip to: 40641 -/* 24361 */ MCD_OPC_Decode, 175, 12, 151, 1, // Opcode: SQSHLv8i8_shift -/* 24366 */ MCD_OPC_FilterValue, 1, 143, 63, // Skip to: 40641 -/* 24370 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 24373 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24386 -/* 24377 */ MCD_OPC_CheckPredicate, 0, 132, 63, // Skip to: 40641 -/* 24381 */ MCD_OPC_Decode, 159, 13, 152, 1, // Opcode: SSRAv4i16_shift -/* 24386 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24399 -/* 24390 */ MCD_OPC_CheckPredicate, 0, 119, 63, // Skip to: 40641 -/* 24394 */ MCD_OPC_Decode, 129, 13, 152, 1, // Opcode: SRSRAv4i16_shift -/* 24399 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24412 -/* 24403 */ MCD_OPC_CheckPredicate, 0, 106, 63, // Skip to: 40641 -/* 24407 */ MCD_OPC_Decode, 180, 10, 153, 1, // Opcode: SHLv4i16_shift -/* 24412 */ MCD_OPC_FilterValue, 3, 97, 63, // Skip to: 40641 -/* 24416 */ MCD_OPC_CheckPredicate, 0, 93, 63, // Skip to: 40641 -/* 24420 */ MCD_OPC_Decode, 169, 12, 153, 1, // Opcode: SQSHLv4i16_shift -/* 24425 */ MCD_OPC_FilterValue, 1, 84, 63, // Skip to: 40641 -/* 24429 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 24432 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24445 -/* 24436 */ MCD_OPC_CheckPredicate, 0, 73, 63, // Skip to: 40641 -/* 24440 */ MCD_OPC_Decode, 157, 13, 154, 1, // Opcode: SSRAv2i32_shift -/* 24445 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 24458 -/* 24449 */ MCD_OPC_CheckPredicate, 0, 60, 63, // Skip to: 40641 -/* 24453 */ MCD_OPC_Decode, 255, 12, 154, 1, // Opcode: SRSRAv2i32_shift -/* 24458 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 24471 -/* 24462 */ MCD_OPC_CheckPredicate, 0, 47, 63, // Skip to: 40641 -/* 24466 */ MCD_OPC_Decode, 178, 10, 155, 1, // Opcode: SHLv2i32_shift -/* 24471 */ MCD_OPC_FilterValue, 3, 38, 63, // Skip to: 40641 -/* 24475 */ MCD_OPC_CheckPredicate, 0, 34, 63, // Skip to: 40641 -/* 24479 */ MCD_OPC_Decode, 165, 12, 155, 1, // Opcode: SQSHLv2i32_shift -/* 24484 */ MCD_OPC_FilterValue, 1, 25, 63, // Skip to: 40641 -/* 24488 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 24491 */ MCD_OPC_FilterValue, 0, 227, 0, // Skip to: 24722 -/* 24495 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 24498 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 24631 -/* 24502 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24505 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 24598 -/* 24509 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24512 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 24565 -/* 24516 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 24519 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24532 -/* 24523 */ MCD_OPC_CheckPredicate, 0, 242, 62, // Skip to: 40641 -/* 24527 */ MCD_OPC_Decode, 207, 8, 145, 1, // Opcode: MOVIv4i16 -/* 24532 */ MCD_OPC_FilterValue, 1, 233, 62, // Skip to: 40641 -/* 24536 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 24539 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24552 -/* 24543 */ MCD_OPC_CheckPredicate, 0, 222, 62, // Skip to: 40641 -/* 24547 */ MCD_OPC_Decode, 189, 10, 156, 1, // Opcode: SHRNv8i8_shift -/* 24552 */ MCD_OPC_FilterValue, 1, 213, 62, // Skip to: 40641 -/* 24556 */ MCD_OPC_CheckPredicate, 0, 209, 62, // Skip to: 40641 -/* 24560 */ MCD_OPC_Decode, 138, 13, 157, 1, // Opcode: SSHLLv8i8_shift -/* 24565 */ MCD_OPC_FilterValue, 1, 200, 62, // Skip to: 40641 -/* 24569 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 24572 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24585 -/* 24576 */ MCD_OPC_CheckPredicate, 0, 189, 62, // Skip to: 40641 -/* 24580 */ MCD_OPC_Decode, 186, 10, 158, 1, // Opcode: SHRNv4i16_shift -/* 24585 */ MCD_OPC_FilterValue, 1, 180, 62, // Skip to: 40641 -/* 24589 */ MCD_OPC_CheckPredicate, 0, 176, 62, // Skip to: 40641 -/* 24593 */ MCD_OPC_Decode, 135, 13, 159, 1, // Opcode: SSHLLv4i16_shift -/* 24598 */ MCD_OPC_FilterValue, 1, 167, 62, // Skip to: 40641 -/* 24602 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 24605 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24618 -/* 24609 */ MCD_OPC_CheckPredicate, 0, 156, 62, // Skip to: 40641 -/* 24613 */ MCD_OPC_Decode, 185, 10, 160, 1, // Opcode: SHRNv2i32_shift -/* 24618 */ MCD_OPC_FilterValue, 1, 147, 62, // Skip to: 40641 -/* 24622 */ MCD_OPC_CheckPredicate, 0, 143, 62, // Skip to: 40641 -/* 24626 */ MCD_OPC_Decode, 134, 13, 161, 1, // Opcode: SSHLLv2i32_shift -/* 24631 */ MCD_OPC_FilterValue, 1, 134, 62, // Skip to: 40641 -/* 24635 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24638 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 24703 -/* 24642 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24645 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24684 -/* 24649 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 24652 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 24665 -/* 24656 */ MCD_OPC_CheckPredicate, 0, 109, 62, // Skip to: 40641 -/* 24660 */ MCD_OPC_Decode, 143, 9, 149, 1, // Opcode: ORRv4i16 -/* 24665 */ MCD_OPC_FilterValue, 1, 100, 62, // Skip to: 40641 -/* 24669 */ MCD_OPC_CheckPredicate, 0, 96, 62, // Skip to: 40641 -/* 24673 */ MCD_OPC_CheckField, 13, 1, 0, 90, 62, // Skip to: 40641 -/* 24679 */ MCD_OPC_Decode, 184, 12, 156, 1, // Opcode: SQSHRNv8i8_shift -/* 24684 */ MCD_OPC_FilterValue, 1, 81, 62, // Skip to: 40641 -/* 24688 */ MCD_OPC_CheckPredicate, 0, 77, 62, // Skip to: 40641 -/* 24692 */ MCD_OPC_CheckField, 13, 1, 0, 71, 62, // Skip to: 40641 -/* 24698 */ MCD_OPC_Decode, 181, 12, 158, 1, // Opcode: SQSHRNv4i16_shift -/* 24703 */ MCD_OPC_FilterValue, 1, 62, 62, // Skip to: 40641 -/* 24707 */ MCD_OPC_CheckPredicate, 0, 58, 62, // Skip to: 40641 -/* 24711 */ MCD_OPC_CheckField, 13, 1, 0, 52, 62, // Skip to: 40641 -/* 24717 */ MCD_OPC_Decode, 180, 12, 160, 1, // Opcode: SQSHRNv2i32_shift -/* 24722 */ MCD_OPC_FilterValue, 1, 43, 62, // Skip to: 40641 -/* 24726 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 24729 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24748 -/* 24733 */ MCD_OPC_CheckPredicate, 0, 32, 62, // Skip to: 40641 -/* 24737 */ MCD_OPC_CheckField, 19, 3, 0, 26, 62, // Skip to: 40641 -/* 24743 */ MCD_OPC_Decode, 206, 8, 145, 1, // Opcode: MOVIv2s_msl -/* 24748 */ MCD_OPC_FilterValue, 1, 17, 62, // Skip to: 40641 -/* 24752 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 24755 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24794 -/* 24759 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24762 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24781 -/* 24766 */ MCD_OPC_CheckPredicate, 0, 255, 61, // Skip to: 40641 -/* 24770 */ MCD_OPC_CheckField, 19, 2, 0, 249, 61, // Skip to: 40641 -/* 24776 */ MCD_OPC_Decode, 210, 8, 145, 1, // Opcode: MOVIv8b_ns -/* 24781 */ MCD_OPC_FilterValue, 1, 240, 61, // Skip to: 40641 -/* 24785 */ MCD_OPC_CheckPredicate, 0, 236, 61, // Skip to: 40641 -/* 24789 */ MCD_OPC_Decode, 146, 10, 148, 1, // Opcode: SCVTFv2i32_shift -/* 24794 */ MCD_OPC_FilterValue, 1, 227, 61, // Skip to: 40641 -/* 24798 */ MCD_OPC_CheckPredicate, 0, 223, 61, // Skip to: 40641 -/* 24802 */ MCD_OPC_CheckField, 19, 3, 0, 217, 61, // Skip to: 40641 -/* 24808 */ MCD_OPC_Decode, 232, 4, 145, 1, // Opcode: FMOVv2f32_ns -/* 24813 */ MCD_OPC_FilterValue, 3, 208, 61, // Skip to: 40641 -/* 24817 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 24820 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 24879 -/* 24824 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24827 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24866 -/* 24831 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24834 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24853 -/* 24838 */ MCD_OPC_CheckPredicate, 0, 183, 61, // Skip to: 40641 -/* 24842 */ MCD_OPC_CheckField, 19, 1, 1, 177, 61, // Skip to: 40641 -/* 24848 */ MCD_OPC_Decode, 194, 9, 156, 1, // Opcode: RSHRNv8i8_shift -/* 24853 */ MCD_OPC_FilterValue, 1, 168, 61, // Skip to: 40641 -/* 24857 */ MCD_OPC_CheckPredicate, 0, 164, 61, // Skip to: 40641 -/* 24861 */ MCD_OPC_Decode, 191, 9, 158, 1, // Opcode: RSHRNv4i16_shift -/* 24866 */ MCD_OPC_FilterValue, 1, 155, 61, // Skip to: 40641 -/* 24870 */ MCD_OPC_CheckPredicate, 0, 151, 61, // Skip to: 40641 -/* 24874 */ MCD_OPC_Decode, 190, 9, 160, 1, // Opcode: RSHRNv2i32_shift -/* 24879 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 24938 -/* 24883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24886 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 24925 -/* 24890 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24893 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 24912 -/* 24897 */ MCD_OPC_CheckPredicate, 0, 124, 61, // Skip to: 40641 -/* 24901 */ MCD_OPC_CheckField, 19, 1, 1, 118, 61, // Skip to: 40641 -/* 24907 */ MCD_OPC_Decode, 133, 12, 156, 1, // Opcode: SQRSHRNv8i8_shift -/* 24912 */ MCD_OPC_FilterValue, 1, 109, 61, // Skip to: 40641 -/* 24916 */ MCD_OPC_CheckPredicate, 0, 105, 61, // Skip to: 40641 -/* 24920 */ MCD_OPC_Decode, 130, 12, 158, 1, // Opcode: SQRSHRNv4i16_shift -/* 24925 */ MCD_OPC_FilterValue, 1, 96, 61, // Skip to: 40641 -/* 24929 */ MCD_OPC_CheckPredicate, 0, 92, 61, // Skip to: 40641 -/* 24933 */ MCD_OPC_Decode, 129, 12, 160, 1, // Opcode: SQRSHRNv2i32_shift -/* 24938 */ MCD_OPC_FilterValue, 15, 83, 61, // Skip to: 40641 -/* 24942 */ MCD_OPC_CheckPredicate, 0, 79, 61, // Skip to: 40641 -/* 24946 */ MCD_OPC_CheckField, 21, 1, 1, 73, 61, // Skip to: 40641 -/* 24952 */ MCD_OPC_Decode, 250, 3, 148, 1, // Opcode: FCVTZSv2i32_shift -/* 24957 */ MCD_OPC_FilterValue, 1, 128, 3, // Skip to: 25857 -/* 24961 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 24964 */ MCD_OPC_FilterValue, 1, 233, 2, // Skip to: 25713 -/* 24968 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 24971 */ MCD_OPC_FilterValue, 0, 168, 1, // Skip to: 25399 -/* 24975 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 24978 */ MCD_OPC_FilterValue, 0, 207, 0, // Skip to: 25189 -/* 24982 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 24985 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 25130 -/* 24989 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 24992 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 25071 -/* 24996 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 24999 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25012 -/* 25003 */ MCD_OPC_CheckPredicate, 0, 18, 61, // Skip to: 40641 -/* 25007 */ MCD_OPC_Decode, 241, 8, 145, 1, // Opcode: MVNIv2i32 -/* 25012 */ MCD_OPC_FilterValue, 1, 9, 61, // Skip to: 40641 -/* 25016 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25019 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25032 -/* 25023 */ MCD_OPC_CheckPredicate, 0, 254, 60, // Skip to: 40641 -/* 25027 */ MCD_OPC_Decode, 148, 18, 146, 1, // Opcode: USHRv8i8_shift -/* 25032 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25045 -/* 25036 */ MCD_OPC_CheckPredicate, 0, 241, 60, // Skip to: 40641 -/* 25040 */ MCD_OPC_Decode, 244, 17, 146, 1, // Opcode: URSHRv8i8_shift -/* 25045 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25058 -/* 25049 */ MCD_OPC_CheckPredicate, 0, 228, 60, // Skip to: 40641 -/* 25053 */ MCD_OPC_Decode, 236, 12, 150, 1, // Opcode: SRIv8i8_shift -/* 25058 */ MCD_OPC_FilterValue, 3, 219, 60, // Skip to: 40641 -/* 25062 */ MCD_OPC_CheckPredicate, 0, 215, 60, // Skip to: 40641 -/* 25066 */ MCD_OPC_Decode, 153, 12, 151, 1, // Opcode: SQSHLUv8i8_shift -/* 25071 */ MCD_OPC_FilterValue, 1, 206, 60, // Skip to: 40641 -/* 25075 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25078 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25091 -/* 25082 */ MCD_OPC_CheckPredicate, 0, 195, 60, // Skip to: 40641 -/* 25086 */ MCD_OPC_Decode, 145, 18, 147, 1, // Opcode: USHRv4i16_shift -/* 25091 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25104 -/* 25095 */ MCD_OPC_CheckPredicate, 0, 182, 60, // Skip to: 40641 -/* 25099 */ MCD_OPC_Decode, 241, 17, 147, 1, // Opcode: URSHRv4i16_shift -/* 25104 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25117 -/* 25108 */ MCD_OPC_CheckPredicate, 0, 169, 60, // Skip to: 40641 -/* 25112 */ MCD_OPC_Decode, 233, 12, 152, 1, // Opcode: SRIv4i16_shift -/* 25117 */ MCD_OPC_FilterValue, 3, 160, 60, // Skip to: 40641 -/* 25121 */ MCD_OPC_CheckPredicate, 0, 156, 60, // Skip to: 40641 -/* 25125 */ MCD_OPC_Decode, 150, 12, 153, 1, // Opcode: SQSHLUv4i16_shift -/* 25130 */ MCD_OPC_FilterValue, 1, 147, 60, // Skip to: 40641 -/* 25134 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25137 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25150 -/* 25141 */ MCD_OPC_CheckPredicate, 0, 136, 60, // Skip to: 40641 -/* 25145 */ MCD_OPC_Decode, 143, 18, 148, 1, // Opcode: USHRv2i32_shift -/* 25150 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25163 -/* 25154 */ MCD_OPC_CheckPredicate, 0, 123, 60, // Skip to: 40641 -/* 25158 */ MCD_OPC_Decode, 239, 17, 148, 1, // Opcode: URSHRv2i32_shift -/* 25163 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25176 -/* 25167 */ MCD_OPC_CheckPredicate, 0, 110, 60, // Skip to: 40641 -/* 25171 */ MCD_OPC_Decode, 231, 12, 154, 1, // Opcode: SRIv2i32_shift -/* 25176 */ MCD_OPC_FilterValue, 3, 101, 60, // Skip to: 40641 -/* 25180 */ MCD_OPC_CheckPredicate, 0, 97, 60, // Skip to: 40641 -/* 25184 */ MCD_OPC_Decode, 148, 12, 155, 1, // Opcode: SQSHLUv2i32_shift -/* 25189 */ MCD_OPC_FilterValue, 1, 88, 60, // Skip to: 40641 -/* 25193 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25196 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 25340 -/* 25200 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25203 */ MCD_OPC_FilterValue, 0, 74, 0, // Skip to: 25281 -/* 25207 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 25210 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 25222 -/* 25214 */ MCD_OPC_CheckPredicate, 0, 63, 60, // Skip to: 40641 -/* 25218 */ MCD_OPC_Decode, 115, 149, 1, // Opcode: BICv2i32 -/* 25222 */ MCD_OPC_FilterValue, 1, 55, 60, // Skip to: 40641 -/* 25226 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25229 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25242 -/* 25233 */ MCD_OPC_CheckPredicate, 0, 44, 60, // Skip to: 40641 -/* 25237 */ MCD_OPC_Decode, 167, 18, 150, 1, // Opcode: USRAv8i8_shift -/* 25242 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25255 -/* 25246 */ MCD_OPC_CheckPredicate, 0, 31, 60, // Skip to: 40641 -/* 25250 */ MCD_OPC_Decode, 254, 17, 150, 1, // Opcode: URSRAv8i8_shift -/* 25255 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25268 -/* 25259 */ MCD_OPC_CheckPredicate, 0, 18, 60, // Skip to: 40641 -/* 25263 */ MCD_OPC_Decode, 203, 10, 162, 1, // Opcode: SLIv8i8_shift -/* 25268 */ MCD_OPC_FilterValue, 3, 9, 60, // Skip to: 40641 -/* 25272 */ MCD_OPC_CheckPredicate, 0, 5, 60, // Skip to: 40641 -/* 25276 */ MCD_OPC_Decode, 191, 17, 151, 1, // Opcode: UQSHLv8i8_shift -/* 25281 */ MCD_OPC_FilterValue, 1, 252, 59, // Skip to: 40641 -/* 25285 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25288 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25301 -/* 25292 */ MCD_OPC_CheckPredicate, 0, 241, 59, // Skip to: 40641 -/* 25296 */ MCD_OPC_Decode, 164, 18, 152, 1, // Opcode: USRAv4i16_shift -/* 25301 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25314 -/* 25305 */ MCD_OPC_CheckPredicate, 0, 228, 59, // Skip to: 40641 -/* 25309 */ MCD_OPC_Decode, 251, 17, 152, 1, // Opcode: URSRAv4i16_shift -/* 25314 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25327 -/* 25318 */ MCD_OPC_CheckPredicate, 0, 215, 59, // Skip to: 40641 -/* 25322 */ MCD_OPC_Decode, 200, 10, 163, 1, // Opcode: SLIv4i16_shift -/* 25327 */ MCD_OPC_FilterValue, 3, 206, 59, // Skip to: 40641 -/* 25331 */ MCD_OPC_CheckPredicate, 0, 202, 59, // Skip to: 40641 -/* 25335 */ MCD_OPC_Decode, 185, 17, 153, 1, // Opcode: UQSHLv4i16_shift -/* 25340 */ MCD_OPC_FilterValue, 1, 193, 59, // Skip to: 40641 -/* 25344 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25347 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25360 -/* 25351 */ MCD_OPC_CheckPredicate, 0, 182, 59, // Skip to: 40641 -/* 25355 */ MCD_OPC_Decode, 162, 18, 154, 1, // Opcode: USRAv2i32_shift -/* 25360 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 25373 -/* 25364 */ MCD_OPC_CheckPredicate, 0, 169, 59, // Skip to: 40641 -/* 25368 */ MCD_OPC_Decode, 249, 17, 154, 1, // Opcode: URSRAv2i32_shift -/* 25373 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 25386 -/* 25377 */ MCD_OPC_CheckPredicate, 0, 156, 59, // Skip to: 40641 -/* 25381 */ MCD_OPC_Decode, 198, 10, 164, 1, // Opcode: SLIv2i32_shift -/* 25386 */ MCD_OPC_FilterValue, 3, 147, 59, // Skip to: 40641 -/* 25390 */ MCD_OPC_CheckPredicate, 0, 143, 59, // Skip to: 40641 -/* 25394 */ MCD_OPC_Decode, 181, 17, 155, 1, // Opcode: UQSHLv2i32_shift -/* 25399 */ MCD_OPC_FilterValue, 1, 134, 59, // Skip to: 40641 -/* 25403 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 25406 */ MCD_OPC_FilterValue, 0, 226, 0, // Skip to: 25636 -/* 25410 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 25413 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 25546 -/* 25417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25420 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 25513 -/* 25424 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25427 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 25480 -/* 25431 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 25434 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25447 -/* 25438 */ MCD_OPC_CheckPredicate, 0, 95, 59, // Skip to: 40641 -/* 25442 */ MCD_OPC_Decode, 243, 8, 145, 1, // Opcode: MVNIv4i16 -/* 25447 */ MCD_OPC_FilterValue, 1, 86, 59, // Skip to: 40641 -/* 25451 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 25454 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25467 -/* 25458 */ MCD_OPC_CheckPredicate, 0, 75, 59, // Skip to: 40641 -/* 25462 */ MCD_OPC_Decode, 193, 12, 156, 1, // Opcode: SQSHRUNv8i8_shift -/* 25467 */ MCD_OPC_FilterValue, 1, 66, 59, // Skip to: 40641 -/* 25471 */ MCD_OPC_CheckPredicate, 0, 62, 59, // Skip to: 40641 -/* 25475 */ MCD_OPC_Decode, 132, 18, 157, 1, // Opcode: USHLLv8i8_shift -/* 25480 */ MCD_OPC_FilterValue, 1, 53, 59, // Skip to: 40641 -/* 25484 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 25487 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25500 -/* 25491 */ MCD_OPC_CheckPredicate, 0, 42, 59, // Skip to: 40641 -/* 25495 */ MCD_OPC_Decode, 190, 12, 158, 1, // Opcode: SQSHRUNv4i16_shift -/* 25500 */ MCD_OPC_FilterValue, 1, 33, 59, // Skip to: 40641 -/* 25504 */ MCD_OPC_CheckPredicate, 0, 29, 59, // Skip to: 40641 -/* 25508 */ MCD_OPC_Decode, 129, 18, 159, 1, // Opcode: USHLLv4i16_shift -/* 25513 */ MCD_OPC_FilterValue, 1, 20, 59, // Skip to: 40641 -/* 25517 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 25520 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25533 -/* 25524 */ MCD_OPC_CheckPredicate, 0, 9, 59, // Skip to: 40641 -/* 25528 */ MCD_OPC_Decode, 189, 12, 160, 1, // Opcode: SQSHRUNv2i32_shift -/* 25533 */ MCD_OPC_FilterValue, 1, 0, 59, // Skip to: 40641 -/* 25537 */ MCD_OPC_CheckPredicate, 0, 252, 58, // Skip to: 40641 -/* 25541 */ MCD_OPC_Decode, 128, 18, 161, 1, // Opcode: USHLLv2i32_shift -/* 25546 */ MCD_OPC_FilterValue, 1, 243, 58, // Skip to: 40641 -/* 25550 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25553 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 25617 -/* 25557 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25560 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 25598 -/* 25564 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 25567 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 25579 -/* 25571 */ MCD_OPC_CheckPredicate, 0, 218, 58, // Skip to: 40641 -/* 25575 */ MCD_OPC_Decode, 116, 149, 1, // Opcode: BICv4i16 -/* 25579 */ MCD_OPC_FilterValue, 1, 210, 58, // Skip to: 40641 -/* 25583 */ MCD_OPC_CheckPredicate, 0, 206, 58, // Skip to: 40641 -/* 25587 */ MCD_OPC_CheckField, 13, 1, 0, 200, 58, // Skip to: 40641 -/* 25593 */ MCD_OPC_Decode, 200, 17, 156, 1, // Opcode: UQSHRNv8i8_shift -/* 25598 */ MCD_OPC_FilterValue, 1, 191, 58, // Skip to: 40641 -/* 25602 */ MCD_OPC_CheckPredicate, 0, 187, 58, // Skip to: 40641 -/* 25606 */ MCD_OPC_CheckField, 13, 1, 0, 181, 58, // Skip to: 40641 -/* 25612 */ MCD_OPC_Decode, 197, 17, 158, 1, // Opcode: UQSHRNv4i16_shift -/* 25617 */ MCD_OPC_FilterValue, 1, 172, 58, // Skip to: 40641 -/* 25621 */ MCD_OPC_CheckPredicate, 0, 168, 58, // Skip to: 40641 -/* 25625 */ MCD_OPC_CheckField, 13, 1, 0, 162, 58, // Skip to: 40641 -/* 25631 */ MCD_OPC_Decode, 196, 17, 160, 1, // Opcode: UQSHRNv2i32_shift -/* 25636 */ MCD_OPC_FilterValue, 1, 153, 58, // Skip to: 40641 -/* 25640 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 25643 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25662 -/* 25647 */ MCD_OPC_CheckPredicate, 0, 142, 58, // Skip to: 40641 -/* 25651 */ MCD_OPC_CheckField, 19, 3, 0, 136, 58, // Skip to: 40641 -/* 25657 */ MCD_OPC_Decode, 242, 8, 145, 1, // Opcode: MVNIv2s_msl -/* 25662 */ MCD_OPC_FilterValue, 1, 127, 58, // Skip to: 40641 -/* 25666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25669 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 25694 -/* 25673 */ MCD_OPC_CheckPredicate, 0, 116, 58, // Skip to: 40641 -/* 25677 */ MCD_OPC_CheckField, 19, 2, 0, 110, 58, // Skip to: 40641 -/* 25683 */ MCD_OPC_CheckField, 12, 1, 0, 104, 58, // Skip to: 40641 -/* 25689 */ MCD_OPC_Decode, 202, 8, 145, 1, // Opcode: MOVID -/* 25694 */ MCD_OPC_FilterValue, 1, 95, 58, // Skip to: 40641 -/* 25698 */ MCD_OPC_CheckPredicate, 0, 91, 58, // Skip to: 40641 -/* 25702 */ MCD_OPC_CheckField, 12, 1, 0, 85, 58, // Skip to: 40641 -/* 25708 */ MCD_OPC_Decode, 176, 16, 148, 1, // Opcode: UCVTFv2i32_shift -/* 25713 */ MCD_OPC_FilterValue, 3, 76, 58, // Skip to: 40641 -/* 25717 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 25720 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 25779 -/* 25724 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25727 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 25766 -/* 25731 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25734 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25753 -/* 25738 */ MCD_OPC_CheckPredicate, 0, 51, 58, // Skip to: 40641 -/* 25742 */ MCD_OPC_CheckField, 19, 1, 1, 45, 58, // Skip to: 40641 -/* 25748 */ MCD_OPC_Decode, 142, 12, 156, 1, // Opcode: SQRSHRUNv8i8_shift -/* 25753 */ MCD_OPC_FilterValue, 1, 36, 58, // Skip to: 40641 -/* 25757 */ MCD_OPC_CheckPredicate, 0, 32, 58, // Skip to: 40641 -/* 25761 */ MCD_OPC_Decode, 139, 12, 158, 1, // Opcode: SQRSHRUNv4i16_shift -/* 25766 */ MCD_OPC_FilterValue, 1, 23, 58, // Skip to: 40641 -/* 25770 */ MCD_OPC_CheckPredicate, 0, 19, 58, // Skip to: 40641 -/* 25774 */ MCD_OPC_Decode, 138, 12, 160, 1, // Opcode: SQRSHRUNv2i32_shift -/* 25779 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 25838 -/* 25783 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25786 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 25825 -/* 25790 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25793 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 25812 -/* 25797 */ MCD_OPC_CheckPredicate, 0, 248, 57, // Skip to: 40641 -/* 25801 */ MCD_OPC_CheckField, 19, 1, 1, 242, 57, // Skip to: 40641 -/* 25807 */ MCD_OPC_Decode, 169, 17, 156, 1, // Opcode: UQRSHRNv8i8_shift -/* 25812 */ MCD_OPC_FilterValue, 1, 233, 57, // Skip to: 40641 -/* 25816 */ MCD_OPC_CheckPredicate, 0, 229, 57, // Skip to: 40641 -/* 25820 */ MCD_OPC_Decode, 166, 17, 158, 1, // Opcode: UQRSHRNv4i16_shift -/* 25825 */ MCD_OPC_FilterValue, 1, 220, 57, // Skip to: 40641 -/* 25829 */ MCD_OPC_CheckPredicate, 0, 216, 57, // Skip to: 40641 -/* 25833 */ MCD_OPC_Decode, 165, 17, 160, 1, // Opcode: UQRSHRNv2i32_shift -/* 25838 */ MCD_OPC_FilterValue, 15, 207, 57, // Skip to: 40641 -/* 25842 */ MCD_OPC_CheckPredicate, 0, 203, 57, // Skip to: 40641 -/* 25846 */ MCD_OPC_CheckField, 21, 1, 1, 197, 57, // Skip to: 40641 -/* 25852 */ MCD_OPC_Decode, 151, 4, 148, 1, // Opcode: FCVTZUv2i32_shift -/* 25857 */ MCD_OPC_FilterValue, 2, 66, 3, // Skip to: 26695 -/* 25861 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 25864 */ MCD_OPC_FilterValue, 1, 171, 2, // Skip to: 26551 -/* 25868 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 25871 */ MCD_OPC_FilterValue, 0, 91, 1, // Skip to: 26222 -/* 25875 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 25878 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 26011 -/* 25882 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 25885 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 25978 -/* 25889 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 25892 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 25945 -/* 25896 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 25899 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25912 -/* 25903 */ MCD_OPC_CheckPredicate, 0, 142, 57, // Skip to: 40641 -/* 25907 */ MCD_OPC_Decode, 208, 8, 145, 1, // Opcode: MOVIv4i32 -/* 25912 */ MCD_OPC_FilterValue, 1, 133, 57, // Skip to: 40641 -/* 25916 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25919 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25932 -/* 25923 */ MCD_OPC_CheckPredicate, 0, 122, 57, // Skip to: 40641 -/* 25927 */ MCD_OPC_Decode, 148, 13, 165, 1, // Opcode: SSHRv16i8_shift -/* 25932 */ MCD_OPC_FilterValue, 1, 113, 57, // Skip to: 40641 -/* 25936 */ MCD_OPC_CheckPredicate, 0, 109, 57, // Skip to: 40641 -/* 25940 */ MCD_OPC_Decode, 246, 12, 165, 1, // Opcode: SRSHRv16i8_shift -/* 25945 */ MCD_OPC_FilterValue, 1, 100, 57, // Skip to: 40641 -/* 25949 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25952 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25965 -/* 25956 */ MCD_OPC_CheckPredicate, 0, 89, 57, // Skip to: 40641 -/* 25960 */ MCD_OPC_Decode, 153, 13, 166, 1, // Opcode: SSHRv8i16_shift -/* 25965 */ MCD_OPC_FilterValue, 1, 80, 57, // Skip to: 40641 -/* 25969 */ MCD_OPC_CheckPredicate, 0, 76, 57, // Skip to: 40641 -/* 25973 */ MCD_OPC_Decode, 251, 12, 166, 1, // Opcode: SRSHRv8i16_shift -/* 25978 */ MCD_OPC_FilterValue, 1, 67, 57, // Skip to: 40641 -/* 25982 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 25985 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 25998 -/* 25989 */ MCD_OPC_CheckPredicate, 0, 56, 57, // Skip to: 40641 -/* 25993 */ MCD_OPC_Decode, 152, 13, 167, 1, // Opcode: SSHRv4i32_shift -/* 25998 */ MCD_OPC_FilterValue, 1, 47, 57, // Skip to: 40641 -/* 26002 */ MCD_OPC_CheckPredicate, 0, 43, 57, // Skip to: 40641 -/* 26006 */ MCD_OPC_Decode, 250, 12, 167, 1, // Opcode: SRSHRv4i32_shift -/* 26011 */ MCD_OPC_FilterValue, 1, 34, 57, // Skip to: 40641 -/* 26015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26018 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 26163 -/* 26022 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26025 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 26104 -/* 26029 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 26032 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26045 -/* 26036 */ MCD_OPC_CheckPredicate, 0, 9, 57, // Skip to: 40641 -/* 26040 */ MCD_OPC_Decode, 144, 9, 149, 1, // Opcode: ORRv4i32 -/* 26045 */ MCD_OPC_FilterValue, 1, 0, 57, // Skip to: 40641 -/* 26049 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26052 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26065 -/* 26056 */ MCD_OPC_CheckPredicate, 0, 245, 56, // Skip to: 40641 -/* 26060 */ MCD_OPC_Decode, 156, 13, 168, 1, // Opcode: SSRAv16i8_shift -/* 26065 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26078 -/* 26069 */ MCD_OPC_CheckPredicate, 0, 232, 56, // Skip to: 40641 -/* 26073 */ MCD_OPC_Decode, 254, 12, 168, 1, // Opcode: SRSRAv16i8_shift -/* 26078 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26091 -/* 26082 */ MCD_OPC_CheckPredicate, 0, 219, 56, // Skip to: 40641 -/* 26086 */ MCD_OPC_Decode, 177, 10, 169, 1, // Opcode: SHLv16i8_shift -/* 26091 */ MCD_OPC_FilterValue, 3, 210, 56, // Skip to: 40641 -/* 26095 */ MCD_OPC_CheckPredicate, 0, 206, 56, // Skip to: 40641 -/* 26099 */ MCD_OPC_Decode, 159, 12, 169, 1, // Opcode: SQSHLv16i8_shift -/* 26104 */ MCD_OPC_FilterValue, 1, 197, 56, // Skip to: 40641 -/* 26108 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26111 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26124 -/* 26115 */ MCD_OPC_CheckPredicate, 0, 186, 56, // Skip to: 40641 -/* 26119 */ MCD_OPC_Decode, 161, 13, 170, 1, // Opcode: SSRAv8i16_shift -/* 26124 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26137 -/* 26128 */ MCD_OPC_CheckPredicate, 0, 173, 56, // Skip to: 40641 -/* 26132 */ MCD_OPC_Decode, 131, 13, 170, 1, // Opcode: SRSRAv8i16_shift -/* 26137 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26150 -/* 26141 */ MCD_OPC_CheckPredicate, 0, 160, 56, // Skip to: 40641 -/* 26145 */ MCD_OPC_Decode, 182, 10, 171, 1, // Opcode: SHLv8i16_shift -/* 26150 */ MCD_OPC_FilterValue, 3, 151, 56, // Skip to: 40641 -/* 26154 */ MCD_OPC_CheckPredicate, 0, 147, 56, // Skip to: 40641 -/* 26158 */ MCD_OPC_Decode, 173, 12, 171, 1, // Opcode: SQSHLv8i16_shift -/* 26163 */ MCD_OPC_FilterValue, 1, 138, 56, // Skip to: 40641 -/* 26167 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26170 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26183 -/* 26174 */ MCD_OPC_CheckPredicate, 0, 127, 56, // Skip to: 40641 -/* 26178 */ MCD_OPC_Decode, 160, 13, 172, 1, // Opcode: SSRAv4i32_shift -/* 26183 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26196 -/* 26187 */ MCD_OPC_CheckPredicate, 0, 114, 56, // Skip to: 40641 -/* 26191 */ MCD_OPC_Decode, 130, 13, 172, 1, // Opcode: SRSRAv4i32_shift -/* 26196 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26209 -/* 26200 */ MCD_OPC_CheckPredicate, 0, 101, 56, // Skip to: 40641 -/* 26204 */ MCD_OPC_Decode, 181, 10, 173, 1, // Opcode: SHLv4i32_shift -/* 26209 */ MCD_OPC_FilterValue, 3, 92, 56, // Skip to: 40641 -/* 26213 */ MCD_OPC_CheckPredicate, 0, 88, 56, // Skip to: 40641 -/* 26217 */ MCD_OPC_Decode, 171, 12, 173, 1, // Opcode: SQSHLv4i32_shift -/* 26222 */ MCD_OPC_FilterValue, 1, 79, 56, // Skip to: 40641 -/* 26226 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 26229 */ MCD_OPC_FilterValue, 0, 227, 0, // Skip to: 26460 -/* 26233 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 26236 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 26369 -/* 26240 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26243 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 26336 -/* 26247 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26250 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 26303 -/* 26254 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 26257 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26270 -/* 26261 */ MCD_OPC_CheckPredicate, 0, 40, 56, // Skip to: 40641 -/* 26265 */ MCD_OPC_Decode, 211, 8, 145, 1, // Opcode: MOVIv8i16 -/* 26270 */ MCD_OPC_FilterValue, 1, 31, 56, // Skip to: 40641 -/* 26274 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 26277 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26290 -/* 26281 */ MCD_OPC_CheckPredicate, 0, 20, 56, // Skip to: 40641 -/* 26285 */ MCD_OPC_Decode, 184, 10, 174, 1, // Opcode: SHRNv16i8_shift -/* 26290 */ MCD_OPC_FilterValue, 1, 11, 56, // Skip to: 40641 -/* 26294 */ MCD_OPC_CheckPredicate, 0, 7, 56, // Skip to: 40641 -/* 26298 */ MCD_OPC_Decode, 133, 13, 169, 1, // Opcode: SSHLLv16i8_shift -/* 26303 */ MCD_OPC_FilterValue, 1, 254, 55, // Skip to: 40641 -/* 26307 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 26310 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26323 -/* 26314 */ MCD_OPC_CheckPredicate, 0, 243, 55, // Skip to: 40641 -/* 26318 */ MCD_OPC_Decode, 188, 10, 175, 1, // Opcode: SHRNv8i16_shift -/* 26323 */ MCD_OPC_FilterValue, 1, 234, 55, // Skip to: 40641 -/* 26327 */ MCD_OPC_CheckPredicate, 0, 230, 55, // Skip to: 40641 -/* 26331 */ MCD_OPC_Decode, 137, 13, 171, 1, // Opcode: SSHLLv8i16_shift -/* 26336 */ MCD_OPC_FilterValue, 1, 221, 55, // Skip to: 40641 -/* 26340 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 26343 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26356 -/* 26347 */ MCD_OPC_CheckPredicate, 0, 210, 55, // Skip to: 40641 -/* 26351 */ MCD_OPC_Decode, 187, 10, 176, 1, // Opcode: SHRNv4i32_shift -/* 26356 */ MCD_OPC_FilterValue, 1, 201, 55, // Skip to: 40641 -/* 26360 */ MCD_OPC_CheckPredicate, 0, 197, 55, // Skip to: 40641 -/* 26364 */ MCD_OPC_Decode, 136, 13, 173, 1, // Opcode: SSHLLv4i32_shift -/* 26369 */ MCD_OPC_FilterValue, 1, 188, 55, // Skip to: 40641 -/* 26373 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26376 */ MCD_OPC_FilterValue, 0, 61, 0, // Skip to: 26441 -/* 26380 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26383 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26422 -/* 26387 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 26390 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26403 -/* 26394 */ MCD_OPC_CheckPredicate, 0, 163, 55, // Skip to: 40641 -/* 26398 */ MCD_OPC_Decode, 145, 9, 149, 1, // Opcode: ORRv8i16 -/* 26403 */ MCD_OPC_FilterValue, 1, 154, 55, // Skip to: 40641 -/* 26407 */ MCD_OPC_CheckPredicate, 0, 150, 55, // Skip to: 40641 -/* 26411 */ MCD_OPC_CheckField, 13, 1, 0, 144, 55, // Skip to: 40641 -/* 26417 */ MCD_OPC_Decode, 179, 12, 174, 1, // Opcode: SQSHRNv16i8_shift -/* 26422 */ MCD_OPC_FilterValue, 1, 135, 55, // Skip to: 40641 -/* 26426 */ MCD_OPC_CheckPredicate, 0, 131, 55, // Skip to: 40641 -/* 26430 */ MCD_OPC_CheckField, 13, 1, 0, 125, 55, // Skip to: 40641 -/* 26436 */ MCD_OPC_Decode, 183, 12, 175, 1, // Opcode: SQSHRNv8i16_shift -/* 26441 */ MCD_OPC_FilterValue, 1, 116, 55, // Skip to: 40641 -/* 26445 */ MCD_OPC_CheckPredicate, 0, 112, 55, // Skip to: 40641 -/* 26449 */ MCD_OPC_CheckField, 13, 1, 0, 106, 55, // Skip to: 40641 -/* 26455 */ MCD_OPC_Decode, 182, 12, 176, 1, // Opcode: SQSHRNv4i32_shift -/* 26460 */ MCD_OPC_FilterValue, 1, 97, 55, // Skip to: 40641 -/* 26464 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 26467 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26486 -/* 26471 */ MCD_OPC_CheckPredicate, 0, 86, 55, // Skip to: 40641 -/* 26475 */ MCD_OPC_CheckField, 19, 3, 0, 80, 55, // Skip to: 40641 -/* 26481 */ MCD_OPC_Decode, 209, 8, 145, 1, // Opcode: MOVIv4s_msl -/* 26486 */ MCD_OPC_FilterValue, 1, 71, 55, // Skip to: 40641 -/* 26490 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 26493 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26532 -/* 26497 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26500 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26519 -/* 26504 */ MCD_OPC_CheckPredicate, 0, 53, 55, // Skip to: 40641 -/* 26508 */ MCD_OPC_CheckField, 19, 2, 0, 47, 55, // Skip to: 40641 -/* 26514 */ MCD_OPC_Decode, 203, 8, 145, 1, // Opcode: MOVIv16b_ns -/* 26519 */ MCD_OPC_FilterValue, 1, 38, 55, // Skip to: 40641 -/* 26523 */ MCD_OPC_CheckPredicate, 0, 34, 55, // Skip to: 40641 -/* 26527 */ MCD_OPC_Decode, 149, 10, 167, 1, // Opcode: SCVTFv4i32_shift -/* 26532 */ MCD_OPC_FilterValue, 1, 25, 55, // Skip to: 40641 -/* 26536 */ MCD_OPC_CheckPredicate, 0, 21, 55, // Skip to: 40641 -/* 26540 */ MCD_OPC_CheckField, 19, 3, 0, 15, 55, // Skip to: 40641 -/* 26546 */ MCD_OPC_Decode, 234, 4, 145, 1, // Opcode: FMOVv4f32_ns -/* 26551 */ MCD_OPC_FilterValue, 3, 6, 55, // Skip to: 40641 -/* 26555 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 26558 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 26617 -/* 26562 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26565 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26604 -/* 26569 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26572 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26591 -/* 26576 */ MCD_OPC_CheckPredicate, 0, 237, 54, // Skip to: 40641 -/* 26580 */ MCD_OPC_CheckField, 19, 1, 1, 231, 54, // Skip to: 40641 -/* 26586 */ MCD_OPC_Decode, 189, 9, 174, 1, // Opcode: RSHRNv16i8_shift -/* 26591 */ MCD_OPC_FilterValue, 1, 222, 54, // Skip to: 40641 -/* 26595 */ MCD_OPC_CheckPredicate, 0, 218, 54, // Skip to: 40641 -/* 26599 */ MCD_OPC_Decode, 193, 9, 175, 1, // Opcode: RSHRNv8i16_shift -/* 26604 */ MCD_OPC_FilterValue, 1, 209, 54, // Skip to: 40641 -/* 26608 */ MCD_OPC_CheckPredicate, 0, 205, 54, // Skip to: 40641 -/* 26612 */ MCD_OPC_Decode, 192, 9, 176, 1, // Opcode: RSHRNv4i32_shift -/* 26617 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 26676 -/* 26621 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26624 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 26663 -/* 26628 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26631 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 26650 -/* 26635 */ MCD_OPC_CheckPredicate, 0, 178, 54, // Skip to: 40641 -/* 26639 */ MCD_OPC_CheckField, 19, 1, 1, 172, 54, // Skip to: 40641 -/* 26645 */ MCD_OPC_Decode, 128, 12, 174, 1, // Opcode: SQRSHRNv16i8_shift -/* 26650 */ MCD_OPC_FilterValue, 1, 163, 54, // Skip to: 40641 -/* 26654 */ MCD_OPC_CheckPredicate, 0, 159, 54, // Skip to: 40641 -/* 26658 */ MCD_OPC_Decode, 132, 12, 175, 1, // Opcode: SQRSHRNv8i16_shift -/* 26663 */ MCD_OPC_FilterValue, 1, 150, 54, // Skip to: 40641 -/* 26667 */ MCD_OPC_CheckPredicate, 0, 146, 54, // Skip to: 40641 -/* 26671 */ MCD_OPC_Decode, 131, 12, 176, 1, // Opcode: SQRSHRNv4i32_shift -/* 26676 */ MCD_OPC_FilterValue, 15, 137, 54, // Skip to: 40641 -/* 26680 */ MCD_OPC_CheckPredicate, 0, 133, 54, // Skip to: 40641 -/* 26684 */ MCD_OPC_CheckField, 21, 1, 1, 127, 54, // Skip to: 40641 -/* 26690 */ MCD_OPC_Decode, 253, 3, 167, 1, // Opcode: FCVTZSv4i32_shift -/* 26695 */ MCD_OPC_FilterValue, 3, 118, 54, // Skip to: 40641 -/* 26699 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 26702 */ MCD_OPC_FilterValue, 1, 247, 2, // Skip to: 27465 -/* 26706 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 26709 */ MCD_OPC_FilterValue, 0, 168, 1, // Skip to: 27137 -/* 26713 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 26716 */ MCD_OPC_FilterValue, 0, 207, 0, // Skip to: 26927 -/* 26720 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26723 */ MCD_OPC_FilterValue, 0, 141, 0, // Skip to: 26868 -/* 26727 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26730 */ MCD_OPC_FilterValue, 0, 75, 0, // Skip to: 26809 -/* 26734 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 26737 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26750 -/* 26741 */ MCD_OPC_CheckPredicate, 0, 72, 54, // Skip to: 40641 -/* 26745 */ MCD_OPC_Decode, 244, 8, 145, 1, // Opcode: MVNIv4i32 -/* 26750 */ MCD_OPC_FilterValue, 1, 63, 54, // Skip to: 40641 -/* 26754 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26757 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26770 -/* 26761 */ MCD_OPC_CheckPredicate, 0, 52, 54, // Skip to: 40641 -/* 26765 */ MCD_OPC_Decode, 142, 18, 165, 1, // Opcode: USHRv16i8_shift -/* 26770 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26783 -/* 26774 */ MCD_OPC_CheckPredicate, 0, 39, 54, // Skip to: 40641 -/* 26778 */ MCD_OPC_Decode, 238, 17, 165, 1, // Opcode: URSHRv16i8_shift -/* 26783 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26796 -/* 26787 */ MCD_OPC_CheckPredicate, 0, 26, 54, // Skip to: 40641 -/* 26791 */ MCD_OPC_Decode, 230, 12, 168, 1, // Opcode: SRIv16i8_shift -/* 26796 */ MCD_OPC_FilterValue, 3, 17, 54, // Skip to: 40641 -/* 26800 */ MCD_OPC_CheckPredicate, 0, 13, 54, // Skip to: 40641 -/* 26804 */ MCD_OPC_Decode, 147, 12, 169, 1, // Opcode: SQSHLUv16i8_shift -/* 26809 */ MCD_OPC_FilterValue, 1, 4, 54, // Skip to: 40641 -/* 26813 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26816 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26829 -/* 26820 */ MCD_OPC_CheckPredicate, 0, 249, 53, // Skip to: 40641 -/* 26824 */ MCD_OPC_Decode, 147, 18, 166, 1, // Opcode: USHRv8i16_shift -/* 26829 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26842 -/* 26833 */ MCD_OPC_CheckPredicate, 0, 236, 53, // Skip to: 40641 -/* 26837 */ MCD_OPC_Decode, 243, 17, 166, 1, // Opcode: URSHRv8i16_shift -/* 26842 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26855 -/* 26846 */ MCD_OPC_CheckPredicate, 0, 223, 53, // Skip to: 40641 -/* 26850 */ MCD_OPC_Decode, 235, 12, 170, 1, // Opcode: SRIv8i16_shift -/* 26855 */ MCD_OPC_FilterValue, 3, 214, 53, // Skip to: 40641 -/* 26859 */ MCD_OPC_CheckPredicate, 0, 210, 53, // Skip to: 40641 -/* 26863 */ MCD_OPC_Decode, 152, 12, 171, 1, // Opcode: SQSHLUv8i16_shift -/* 26868 */ MCD_OPC_FilterValue, 1, 201, 53, // Skip to: 40641 -/* 26872 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26875 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26888 -/* 26879 */ MCD_OPC_CheckPredicate, 0, 190, 53, // Skip to: 40641 -/* 26883 */ MCD_OPC_Decode, 146, 18, 167, 1, // Opcode: USHRv4i32_shift -/* 26888 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26901 -/* 26892 */ MCD_OPC_CheckPredicate, 0, 177, 53, // Skip to: 40641 -/* 26896 */ MCD_OPC_Decode, 242, 17, 167, 1, // Opcode: URSHRv4i32_shift -/* 26901 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 26914 -/* 26905 */ MCD_OPC_CheckPredicate, 0, 164, 53, // Skip to: 40641 -/* 26909 */ MCD_OPC_Decode, 234, 12, 172, 1, // Opcode: SRIv4i32_shift -/* 26914 */ MCD_OPC_FilterValue, 3, 155, 53, // Skip to: 40641 -/* 26918 */ MCD_OPC_CheckPredicate, 0, 151, 53, // Skip to: 40641 -/* 26922 */ MCD_OPC_Decode, 151, 12, 173, 1, // Opcode: SQSHLUv4i32_shift -/* 26927 */ MCD_OPC_FilterValue, 1, 142, 53, // Skip to: 40641 -/* 26931 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 26934 */ MCD_OPC_FilterValue, 0, 140, 0, // Skip to: 27078 -/* 26938 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 26941 */ MCD_OPC_FilterValue, 0, 74, 0, // Skip to: 27019 -/* 26945 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 26948 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 26960 -/* 26952 */ MCD_OPC_CheckPredicate, 0, 117, 53, // Skip to: 40641 -/* 26956 */ MCD_OPC_Decode, 117, 149, 1, // Opcode: BICv4i32 -/* 26960 */ MCD_OPC_FilterValue, 1, 109, 53, // Skip to: 40641 -/* 26964 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 26967 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 26980 -/* 26971 */ MCD_OPC_CheckPredicate, 0, 98, 53, // Skip to: 40641 -/* 26975 */ MCD_OPC_Decode, 161, 18, 168, 1, // Opcode: USRAv16i8_shift -/* 26980 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 26993 -/* 26984 */ MCD_OPC_CheckPredicate, 0, 85, 53, // Skip to: 40641 -/* 26988 */ MCD_OPC_Decode, 248, 17, 168, 1, // Opcode: URSRAv16i8_shift -/* 26993 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27006 -/* 26997 */ MCD_OPC_CheckPredicate, 0, 72, 53, // Skip to: 40641 -/* 27001 */ MCD_OPC_Decode, 197, 10, 177, 1, // Opcode: SLIv16i8_shift -/* 27006 */ MCD_OPC_FilterValue, 3, 63, 53, // Skip to: 40641 -/* 27010 */ MCD_OPC_CheckPredicate, 0, 59, 53, // Skip to: 40641 -/* 27014 */ MCD_OPC_Decode, 175, 17, 169, 1, // Opcode: UQSHLv16i8_shift -/* 27019 */ MCD_OPC_FilterValue, 1, 50, 53, // Skip to: 40641 -/* 27023 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 27026 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27039 -/* 27030 */ MCD_OPC_CheckPredicate, 0, 39, 53, // Skip to: 40641 -/* 27034 */ MCD_OPC_Decode, 166, 18, 170, 1, // Opcode: USRAv8i16_shift -/* 27039 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27052 -/* 27043 */ MCD_OPC_CheckPredicate, 0, 26, 53, // Skip to: 40641 -/* 27047 */ MCD_OPC_Decode, 253, 17, 170, 1, // Opcode: URSRAv8i16_shift -/* 27052 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27065 -/* 27056 */ MCD_OPC_CheckPredicate, 0, 13, 53, // Skip to: 40641 -/* 27060 */ MCD_OPC_Decode, 202, 10, 178, 1, // Opcode: SLIv8i16_shift -/* 27065 */ MCD_OPC_FilterValue, 3, 4, 53, // Skip to: 40641 -/* 27069 */ MCD_OPC_CheckPredicate, 0, 0, 53, // Skip to: 40641 -/* 27073 */ MCD_OPC_Decode, 189, 17, 171, 1, // Opcode: UQSHLv8i16_shift -/* 27078 */ MCD_OPC_FilterValue, 1, 247, 52, // Skip to: 40641 -/* 27082 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 27085 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27098 -/* 27089 */ MCD_OPC_CheckPredicate, 0, 236, 52, // Skip to: 40641 -/* 27093 */ MCD_OPC_Decode, 165, 18, 172, 1, // Opcode: USRAv4i32_shift -/* 27098 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27111 -/* 27102 */ MCD_OPC_CheckPredicate, 0, 223, 52, // Skip to: 40641 -/* 27106 */ MCD_OPC_Decode, 252, 17, 172, 1, // Opcode: URSRAv4i32_shift -/* 27111 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 27124 -/* 27115 */ MCD_OPC_CheckPredicate, 0, 210, 52, // Skip to: 40641 -/* 27119 */ MCD_OPC_Decode, 201, 10, 179, 1, // Opcode: SLIv4i32_shift -/* 27124 */ MCD_OPC_FilterValue, 3, 201, 52, // Skip to: 40641 -/* 27128 */ MCD_OPC_CheckPredicate, 0, 197, 52, // Skip to: 40641 -/* 27132 */ MCD_OPC_Decode, 187, 17, 173, 1, // Opcode: UQSHLv4i32_shift -/* 27137 */ MCD_OPC_FilterValue, 1, 188, 52, // Skip to: 40641 -/* 27141 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... -/* 27144 */ MCD_OPC_FilterValue, 0, 226, 0, // Skip to: 27374 -/* 27148 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 27151 */ MCD_OPC_FilterValue, 0, 129, 0, // Skip to: 27284 -/* 27155 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27158 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 27251 -/* 27162 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 27165 */ MCD_OPC_FilterValue, 0, 49, 0, // Skip to: 27218 -/* 27169 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 27172 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27185 -/* 27176 */ MCD_OPC_CheckPredicate, 0, 149, 52, // Skip to: 40641 -/* 27180 */ MCD_OPC_Decode, 246, 8, 145, 1, // Opcode: MVNIv8i16 -/* 27185 */ MCD_OPC_FilterValue, 1, 140, 52, // Skip to: 40641 -/* 27189 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 27192 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27205 -/* 27196 */ MCD_OPC_CheckPredicate, 0, 129, 52, // Skip to: 40641 -/* 27200 */ MCD_OPC_Decode, 188, 12, 174, 1, // Opcode: SQSHRUNv16i8_shift -/* 27205 */ MCD_OPC_FilterValue, 1, 120, 52, // Skip to: 40641 -/* 27209 */ MCD_OPC_CheckPredicate, 0, 116, 52, // Skip to: 40641 -/* 27213 */ MCD_OPC_Decode, 255, 17, 169, 1, // Opcode: USHLLv16i8_shift -/* 27218 */ MCD_OPC_FilterValue, 1, 107, 52, // Skip to: 40641 -/* 27222 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 27225 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27238 -/* 27229 */ MCD_OPC_CheckPredicate, 0, 96, 52, // Skip to: 40641 -/* 27233 */ MCD_OPC_Decode, 192, 12, 175, 1, // Opcode: SQSHRUNv8i16_shift -/* 27238 */ MCD_OPC_FilterValue, 1, 87, 52, // Skip to: 40641 -/* 27242 */ MCD_OPC_CheckPredicate, 0, 83, 52, // Skip to: 40641 -/* 27246 */ MCD_OPC_Decode, 131, 18, 171, 1, // Opcode: USHLLv8i16_shift -/* 27251 */ MCD_OPC_FilterValue, 1, 74, 52, // Skip to: 40641 -/* 27255 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 27258 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27271 -/* 27262 */ MCD_OPC_CheckPredicate, 0, 63, 52, // Skip to: 40641 -/* 27266 */ MCD_OPC_Decode, 191, 12, 176, 1, // Opcode: SQSHRUNv4i32_shift -/* 27271 */ MCD_OPC_FilterValue, 1, 54, 52, // Skip to: 40641 -/* 27275 */ MCD_OPC_CheckPredicate, 0, 50, 52, // Skip to: 40641 -/* 27279 */ MCD_OPC_Decode, 130, 18, 173, 1, // Opcode: USHLLv4i32_shift -/* 27284 */ MCD_OPC_FilterValue, 1, 41, 52, // Skip to: 40641 -/* 27288 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27291 */ MCD_OPC_FilterValue, 0, 60, 0, // Skip to: 27355 -/* 27295 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 27298 */ MCD_OPC_FilterValue, 0, 34, 0, // Skip to: 27336 -/* 27302 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... -/* 27305 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 27317 -/* 27309 */ MCD_OPC_CheckPredicate, 0, 16, 52, // Skip to: 40641 -/* 27313 */ MCD_OPC_Decode, 118, 149, 1, // Opcode: BICv8i16 -/* 27317 */ MCD_OPC_FilterValue, 1, 8, 52, // Skip to: 40641 -/* 27321 */ MCD_OPC_CheckPredicate, 0, 4, 52, // Skip to: 40641 -/* 27325 */ MCD_OPC_CheckField, 13, 1, 0, 254, 51, // Skip to: 40641 -/* 27331 */ MCD_OPC_Decode, 195, 17, 174, 1, // Opcode: UQSHRNv16i8_shift -/* 27336 */ MCD_OPC_FilterValue, 1, 245, 51, // Skip to: 40641 -/* 27340 */ MCD_OPC_CheckPredicate, 0, 241, 51, // Skip to: 40641 -/* 27344 */ MCD_OPC_CheckField, 13, 1, 0, 235, 51, // Skip to: 40641 -/* 27350 */ MCD_OPC_Decode, 199, 17, 175, 1, // Opcode: UQSHRNv8i16_shift -/* 27355 */ MCD_OPC_FilterValue, 1, 226, 51, // Skip to: 40641 -/* 27359 */ MCD_OPC_CheckPredicate, 0, 222, 51, // Skip to: 40641 -/* 27363 */ MCD_OPC_CheckField, 13, 1, 0, 216, 51, // Skip to: 40641 -/* 27369 */ MCD_OPC_Decode, 198, 17, 176, 1, // Opcode: UQSHRNv4i32_shift -/* 27374 */ MCD_OPC_FilterValue, 1, 207, 51, // Skip to: 40641 -/* 27378 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... -/* 27381 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27400 -/* 27385 */ MCD_OPC_CheckPredicate, 0, 196, 51, // Skip to: 40641 -/* 27389 */ MCD_OPC_CheckField, 19, 3, 0, 190, 51, // Skip to: 40641 -/* 27395 */ MCD_OPC_Decode, 245, 8, 145, 1, // Opcode: MVNIv4s_msl -/* 27400 */ MCD_OPC_FilterValue, 1, 181, 51, // Skip to: 40641 -/* 27404 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 27407 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27446 -/* 27411 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27414 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27433 -/* 27418 */ MCD_OPC_CheckPredicate, 0, 163, 51, // Skip to: 40641 -/* 27422 */ MCD_OPC_CheckField, 19, 2, 0, 157, 51, // Skip to: 40641 -/* 27428 */ MCD_OPC_Decode, 204, 8, 145, 1, // Opcode: MOVIv2d_ns -/* 27433 */ MCD_OPC_FilterValue, 1, 148, 51, // Skip to: 40641 -/* 27437 */ MCD_OPC_CheckPredicate, 0, 144, 51, // Skip to: 40641 -/* 27441 */ MCD_OPC_Decode, 179, 16, 167, 1, // Opcode: UCVTFv4i32_shift -/* 27446 */ MCD_OPC_FilterValue, 1, 135, 51, // Skip to: 40641 -/* 27450 */ MCD_OPC_CheckPredicate, 0, 131, 51, // Skip to: 40641 -/* 27454 */ MCD_OPC_CheckField, 19, 3, 0, 125, 51, // Skip to: 40641 -/* 27460 */ MCD_OPC_Decode, 233, 4, 145, 1, // Opcode: FMOVv2f64_ns -/* 27465 */ MCD_OPC_FilterValue, 3, 116, 51, // Skip to: 40641 -/* 27469 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 27472 */ MCD_OPC_FilterValue, 8, 55, 0, // Skip to: 27531 -/* 27476 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27479 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27518 -/* 27483 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 27486 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27505 -/* 27490 */ MCD_OPC_CheckPredicate, 0, 91, 51, // Skip to: 40641 -/* 27494 */ MCD_OPC_CheckField, 19, 1, 1, 85, 51, // Skip to: 40641 -/* 27500 */ MCD_OPC_Decode, 137, 12, 174, 1, // Opcode: SQRSHRUNv16i8_shift -/* 27505 */ MCD_OPC_FilterValue, 1, 76, 51, // Skip to: 40641 -/* 27509 */ MCD_OPC_CheckPredicate, 0, 72, 51, // Skip to: 40641 -/* 27513 */ MCD_OPC_Decode, 141, 12, 175, 1, // Opcode: SQRSHRUNv8i16_shift -/* 27518 */ MCD_OPC_FilterValue, 1, 63, 51, // Skip to: 40641 -/* 27522 */ MCD_OPC_CheckPredicate, 0, 59, 51, // Skip to: 40641 -/* 27526 */ MCD_OPC_Decode, 140, 12, 176, 1, // Opcode: SQRSHRUNv4i32_shift -/* 27531 */ MCD_OPC_FilterValue, 9, 55, 0, // Skip to: 27590 -/* 27535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 27538 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 27577 -/* 27542 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 27545 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27564 -/* 27549 */ MCD_OPC_CheckPredicate, 0, 32, 51, // Skip to: 40641 -/* 27553 */ MCD_OPC_CheckField, 19, 1, 1, 26, 51, // Skip to: 40641 -/* 27559 */ MCD_OPC_Decode, 164, 17, 174, 1, // Opcode: UQRSHRNv16i8_shift -/* 27564 */ MCD_OPC_FilterValue, 1, 17, 51, // Skip to: 40641 -/* 27568 */ MCD_OPC_CheckPredicate, 0, 13, 51, // Skip to: 40641 -/* 27572 */ MCD_OPC_Decode, 168, 17, 175, 1, // Opcode: UQRSHRNv8i16_shift -/* 27577 */ MCD_OPC_FilterValue, 1, 4, 51, // Skip to: 40641 -/* 27581 */ MCD_OPC_CheckPredicate, 0, 0, 51, // Skip to: 40641 -/* 27585 */ MCD_OPC_Decode, 167, 17, 176, 1, // Opcode: UQRSHRNv4i32_shift -/* 27590 */ MCD_OPC_FilterValue, 15, 247, 50, // Skip to: 40641 -/* 27594 */ MCD_OPC_CheckPredicate, 0, 243, 50, // Skip to: 40641 -/* 27598 */ MCD_OPC_CheckField, 21, 1, 1, 237, 50, // Skip to: 40641 -/* 27604 */ MCD_OPC_Decode, 154, 4, 167, 1, // Opcode: FCVTZUv4i32_shift -/* 27609 */ MCD_OPC_FilterValue, 13, 221, 3, // Skip to: 28602 -/* 27613 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 27616 */ MCD_OPC_FilterValue, 0, 80, 0, // Skip to: 27700 -/* 27620 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 27623 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 27642 -/* 27627 */ MCD_OPC_CheckPredicate, 0, 210, 50, // Skip to: 40641 -/* 27631 */ MCD_OPC_CheckField, 10, 1, 0, 204, 50, // Skip to: 40641 -/* 27637 */ MCD_OPC_Decode, 186, 8, 180, 1, // Opcode: MLAv4i16_indexed -/* 27642 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 27661 -/* 27646 */ MCD_OPC_CheckPredicate, 0, 191, 50, // Skip to: 40641 -/* 27650 */ MCD_OPC_CheckField, 10, 2, 1, 185, 50, // Skip to: 40641 -/* 27656 */ MCD_OPC_Decode, 150, 13, 181, 1, // Opcode: SSHRv2i64_shift -/* 27661 */ MCD_OPC_FilterValue, 3, 176, 50, // Skip to: 40641 -/* 27665 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 27668 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27681 -/* 27672 */ MCD_OPC_CheckPredicate, 0, 165, 50, // Skip to: 40641 -/* 27676 */ MCD_OPC_Decode, 190, 8, 182, 1, // Opcode: MLAv8i16_indexed -/* 27681 */ MCD_OPC_FilterValue, 1, 156, 50, // Skip to: 40641 -/* 27685 */ MCD_OPC_CheckPredicate, 0, 152, 50, // Skip to: 40641 -/* 27689 */ MCD_OPC_CheckField, 11, 1, 0, 146, 50, // Skip to: 40641 -/* 27695 */ MCD_OPC_Decode, 144, 18, 181, 1, // Opcode: USHRv2i64_shift -/* 27700 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 27745 -/* 27704 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 27707 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 27726 -/* 27711 */ MCD_OPC_CheckPredicate, 0, 126, 50, // Skip to: 40641 -/* 27715 */ MCD_OPC_CheckField, 10, 2, 1, 120, 50, // Skip to: 40641 -/* 27721 */ MCD_OPC_Decode, 158, 13, 183, 1, // Opcode: SSRAv2i64_shift -/* 27726 */ MCD_OPC_FilterValue, 3, 111, 50, // Skip to: 40641 -/* 27730 */ MCD_OPC_CheckPredicate, 0, 107, 50, // Skip to: 40641 -/* 27734 */ MCD_OPC_CheckField, 10, 2, 1, 101, 50, // Skip to: 40641 -/* 27740 */ MCD_OPC_Decode, 163, 18, 183, 1, // Opcode: USRAv2i64_shift -/* 27745 */ MCD_OPC_FilterValue, 2, 119, 0, // Skip to: 27868 -/* 27749 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 27752 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27771 -/* 27756 */ MCD_OPC_CheckPredicate, 0, 81, 50, // Skip to: 40641 -/* 27760 */ MCD_OPC_CheckField, 10, 1, 0, 75, 50, // Skip to: 40641 -/* 27766 */ MCD_OPC_Decode, 243, 10, 184, 1, // Opcode: SMLALv4i16_indexed -/* 27771 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 27790 -/* 27775 */ MCD_OPC_CheckPredicate, 0, 62, 50, // Skip to: 40641 -/* 27779 */ MCD_OPC_CheckField, 10, 1, 0, 56, 50, // Skip to: 40641 -/* 27785 */ MCD_OPC_Decode, 234, 16, 184, 1, // Opcode: UMLALv4i16_indexed -/* 27790 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 27829 -/* 27794 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 27797 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27810 -/* 27801 */ MCD_OPC_CheckPredicate, 0, 36, 50, // Skip to: 40641 -/* 27805 */ MCD_OPC_Decode, 247, 10, 182, 1, // Opcode: SMLALv8i16_indexed -/* 27810 */ MCD_OPC_FilterValue, 1, 27, 50, // Skip to: 40641 -/* 27814 */ MCD_OPC_CheckPredicate, 0, 23, 50, // Skip to: 40641 -/* 27818 */ MCD_OPC_CheckField, 11, 1, 0, 17, 50, // Skip to: 40641 -/* 27824 */ MCD_OPC_Decode, 248, 12, 181, 1, // Opcode: SRSHRv2i64_shift -/* 27829 */ MCD_OPC_FilterValue, 3, 8, 50, // Skip to: 40641 -/* 27833 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 27836 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27849 -/* 27840 */ MCD_OPC_CheckPredicate, 0, 253, 49, // Skip to: 40641 -/* 27844 */ MCD_OPC_Decode, 238, 16, 182, 1, // Opcode: UMLALv8i16_indexed -/* 27849 */ MCD_OPC_FilterValue, 1, 244, 49, // Skip to: 40641 -/* 27853 */ MCD_OPC_CheckPredicate, 0, 240, 49, // Skip to: 40641 -/* 27857 */ MCD_OPC_CheckField, 11, 1, 0, 234, 49, // Skip to: 40641 -/* 27863 */ MCD_OPC_Decode, 240, 17, 181, 1, // Opcode: URSHRv2i64_shift -/* 27868 */ MCD_OPC_FilterValue, 3, 80, 0, // Skip to: 27952 -/* 27872 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 27875 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 27894 -/* 27879 */ MCD_OPC_CheckPredicate, 0, 214, 49, // Skip to: 40641 -/* 27883 */ MCD_OPC_CheckField, 10, 1, 0, 208, 49, // Skip to: 40641 -/* 27889 */ MCD_OPC_Decode, 177, 11, 184, 1, // Opcode: SQDMLALv4i16_indexed -/* 27894 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 27933 -/* 27898 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 27901 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 27914 -/* 27905 */ MCD_OPC_CheckPredicate, 0, 188, 49, // Skip to: 40641 -/* 27909 */ MCD_OPC_Decode, 181, 11, 182, 1, // Opcode: SQDMLALv8i16_indexed -/* 27914 */ MCD_OPC_FilterValue, 1, 179, 49, // Skip to: 40641 -/* 27918 */ MCD_OPC_CheckPredicate, 0, 175, 49, // Skip to: 40641 -/* 27922 */ MCD_OPC_CheckField, 11, 1, 0, 169, 49, // Skip to: 40641 -/* 27928 */ MCD_OPC_Decode, 128, 13, 183, 1, // Opcode: SRSRAv2i64_shift -/* 27933 */ MCD_OPC_FilterValue, 3, 160, 49, // Skip to: 40641 -/* 27937 */ MCD_OPC_CheckPredicate, 0, 156, 49, // Skip to: 40641 -/* 27941 */ MCD_OPC_CheckField, 10, 2, 1, 150, 49, // Skip to: 40641 -/* 27947 */ MCD_OPC_Decode, 250, 17, 183, 1, // Opcode: URSRAv2i64_shift -/* 27952 */ MCD_OPC_FilterValue, 4, 61, 0, // Skip to: 28017 -/* 27956 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 27959 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 27992 -/* 27963 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 27966 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 27979 -/* 27970 */ MCD_OPC_CheckPredicate, 0, 123, 49, // Skip to: 40641 -/* 27974 */ MCD_OPC_Decode, 196, 8, 180, 1, // Opcode: MLSv4i16_indexed -/* 27979 */ MCD_OPC_FilterValue, 3, 114, 49, // Skip to: 40641 -/* 27983 */ MCD_OPC_CheckPredicate, 0, 110, 49, // Skip to: 40641 -/* 27987 */ MCD_OPC_Decode, 200, 8, 182, 1, // Opcode: MLSv8i16_indexed -/* 27992 */ MCD_OPC_FilterValue, 1, 101, 49, // Skip to: 40641 -/* 27996 */ MCD_OPC_CheckPredicate, 0, 97, 49, // Skip to: 40641 -/* 28000 */ MCD_OPC_CheckField, 29, 3, 3, 91, 49, // Skip to: 40641 -/* 28006 */ MCD_OPC_CheckField, 11, 1, 0, 85, 49, // Skip to: 40641 -/* 28012 */ MCD_OPC_Decode, 232, 12, 183, 1, // Opcode: SRIv2i64_shift -/* 28017 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 28062 -/* 28021 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28024 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28043 -/* 28028 */ MCD_OPC_CheckPredicate, 0, 65, 49, // Skip to: 40641 -/* 28032 */ MCD_OPC_CheckField, 10, 2, 1, 59, 49, // Skip to: 40641 -/* 28038 */ MCD_OPC_Decode, 179, 10, 185, 1, // Opcode: SHLv2i64_shift -/* 28043 */ MCD_OPC_FilterValue, 3, 50, 49, // Skip to: 40641 -/* 28047 */ MCD_OPC_CheckPredicate, 0, 46, 49, // Skip to: 40641 -/* 28051 */ MCD_OPC_CheckField, 10, 2, 1, 40, 49, // Skip to: 40641 -/* 28057 */ MCD_OPC_Decode, 199, 10, 186, 1, // Opcode: SLIv2i64_shift -/* 28062 */ MCD_OPC_FilterValue, 6, 99, 0, // Skip to: 28165 -/* 28066 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28069 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28088 -/* 28073 */ MCD_OPC_CheckPredicate, 0, 20, 49, // Skip to: 40641 -/* 28077 */ MCD_OPC_CheckField, 10, 1, 0, 14, 49, // Skip to: 40641 -/* 28083 */ MCD_OPC_Decode, 253, 10, 184, 1, // Opcode: SMLSLv4i16_indexed -/* 28088 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28107 -/* 28092 */ MCD_OPC_CheckPredicate, 0, 1, 49, // Skip to: 40641 -/* 28096 */ MCD_OPC_CheckField, 10, 1, 0, 251, 48, // Skip to: 40641 -/* 28102 */ MCD_OPC_Decode, 244, 16, 184, 1, // Opcode: UMLSLv4i16_indexed -/* 28107 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28126 -/* 28111 */ MCD_OPC_CheckPredicate, 0, 238, 48, // Skip to: 40641 -/* 28115 */ MCD_OPC_CheckField, 10, 1, 0, 232, 48, // Skip to: 40641 -/* 28121 */ MCD_OPC_Decode, 129, 11, 182, 1, // Opcode: SMLSLv8i16_indexed -/* 28126 */ MCD_OPC_FilterValue, 3, 223, 48, // Skip to: 40641 -/* 28130 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 28133 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 28146 -/* 28137 */ MCD_OPC_CheckPredicate, 0, 212, 48, // Skip to: 40641 -/* 28141 */ MCD_OPC_Decode, 248, 16, 182, 1, // Opcode: UMLSLv8i16_indexed -/* 28146 */ MCD_OPC_FilterValue, 1, 203, 48, // Skip to: 40641 -/* 28150 */ MCD_OPC_CheckPredicate, 0, 199, 48, // Skip to: 40641 -/* 28154 */ MCD_OPC_CheckField, 11, 1, 0, 193, 48, // Skip to: 40641 -/* 28160 */ MCD_OPC_Decode, 149, 12, 185, 1, // Opcode: SQSHLUv2i64_shift -/* 28165 */ MCD_OPC_FilterValue, 7, 80, 0, // Skip to: 28249 -/* 28169 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28172 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28191 -/* 28176 */ MCD_OPC_CheckPredicate, 0, 173, 48, // Skip to: 40641 -/* 28180 */ MCD_OPC_CheckField, 10, 1, 0, 167, 48, // Skip to: 40641 -/* 28186 */ MCD_OPC_Decode, 189, 11, 184, 1, // Opcode: SQDMLSLv4i16_indexed -/* 28191 */ MCD_OPC_FilterValue, 2, 35, 0, // Skip to: 28230 -/* 28195 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 28198 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 28211 -/* 28202 */ MCD_OPC_CheckPredicate, 0, 147, 48, // Skip to: 40641 -/* 28206 */ MCD_OPC_Decode, 193, 11, 182, 1, // Opcode: SQDMLSLv8i16_indexed -/* 28211 */ MCD_OPC_FilterValue, 1, 138, 48, // Skip to: 40641 -/* 28215 */ MCD_OPC_CheckPredicate, 0, 134, 48, // Skip to: 40641 -/* 28219 */ MCD_OPC_CheckField, 11, 1, 0, 128, 48, // Skip to: 40641 -/* 28225 */ MCD_OPC_Decode, 167, 12, 185, 1, // Opcode: SQSHLv2i64_shift -/* 28230 */ MCD_OPC_FilterValue, 3, 119, 48, // Skip to: 40641 -/* 28234 */ MCD_OPC_CheckPredicate, 0, 115, 48, // Skip to: 40641 -/* 28238 */ MCD_OPC_CheckField, 10, 2, 1, 109, 48, // Skip to: 40641 -/* 28244 */ MCD_OPC_Decode, 183, 17, 185, 1, // Opcode: UQSHLv2i64_shift -/* 28249 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 28294 -/* 28253 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28256 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28275 -/* 28260 */ MCD_OPC_CheckPredicate, 0, 89, 48, // Skip to: 40641 -/* 28264 */ MCD_OPC_CheckField, 10, 1, 0, 83, 48, // Skip to: 40641 -/* 28270 */ MCD_OPC_Decode, 235, 8, 187, 1, // Opcode: MULv4i16_indexed -/* 28275 */ MCD_OPC_FilterValue, 2, 74, 48, // Skip to: 40641 -/* 28279 */ MCD_OPC_CheckPredicate, 0, 70, 48, // Skip to: 40641 -/* 28283 */ MCD_OPC_CheckField, 10, 1, 0, 64, 48, // Skip to: 40641 -/* 28289 */ MCD_OPC_Decode, 239, 8, 188, 1, // Opcode: MULv8i16_indexed -/* 28294 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 28377 -/* 28298 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28301 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28320 -/* 28305 */ MCD_OPC_CheckPredicate, 0, 44, 48, // Skip to: 40641 -/* 28309 */ MCD_OPC_CheckField, 10, 1, 0, 38, 48, // Skip to: 40641 -/* 28315 */ MCD_OPC_Decode, 142, 11, 189, 1, // Opcode: SMULLv4i16_indexed -/* 28320 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28339 -/* 28324 */ MCD_OPC_CheckPredicate, 0, 25, 48, // Skip to: 40641 -/* 28328 */ MCD_OPC_CheckField, 10, 1, 0, 19, 48, // Skip to: 40641 -/* 28334 */ MCD_OPC_Decode, 132, 17, 189, 1, // Opcode: UMULLv4i16_indexed -/* 28339 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28358 -/* 28343 */ MCD_OPC_CheckPredicate, 0, 6, 48, // Skip to: 40641 -/* 28347 */ MCD_OPC_CheckField, 10, 1, 0, 0, 48, // Skip to: 40641 -/* 28353 */ MCD_OPC_Decode, 146, 11, 188, 1, // Opcode: SMULLv8i16_indexed -/* 28358 */ MCD_OPC_FilterValue, 3, 247, 47, // Skip to: 40641 -/* 28362 */ MCD_OPC_CheckPredicate, 0, 243, 47, // Skip to: 40641 -/* 28366 */ MCD_OPC_CheckField, 10, 1, 0, 237, 47, // Skip to: 40641 -/* 28372 */ MCD_OPC_Decode, 136, 17, 188, 1, // Opcode: UMULLv8i16_indexed -/* 28377 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 28422 -/* 28381 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28384 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28403 -/* 28388 */ MCD_OPC_CheckPredicate, 0, 217, 47, // Skip to: 40641 -/* 28392 */ MCD_OPC_CheckField, 10, 1, 0, 211, 47, // Skip to: 40641 -/* 28398 */ MCD_OPC_Decode, 213, 11, 189, 1, // Opcode: SQDMULLv4i16_indexed -/* 28403 */ MCD_OPC_FilterValue, 2, 202, 47, // Skip to: 40641 -/* 28407 */ MCD_OPC_CheckPredicate, 0, 198, 47, // Skip to: 40641 -/* 28411 */ MCD_OPC_CheckField, 10, 1, 0, 192, 47, // Skip to: 40641 -/* 28417 */ MCD_OPC_Decode, 217, 11, 188, 1, // Opcode: SQDMULLv8i16_indexed -/* 28422 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 28467 -/* 28426 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28429 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28448 -/* 28433 */ MCD_OPC_CheckPredicate, 0, 172, 47, // Skip to: 40641 -/* 28437 */ MCD_OPC_CheckField, 10, 1, 0, 166, 47, // Skip to: 40641 -/* 28443 */ MCD_OPC_Decode, 202, 11, 187, 1, // Opcode: SQDMULHv4i16_indexed -/* 28448 */ MCD_OPC_FilterValue, 2, 157, 47, // Skip to: 40641 -/* 28452 */ MCD_OPC_CheckPredicate, 0, 153, 47, // Skip to: 40641 -/* 28456 */ MCD_OPC_CheckField, 10, 1, 0, 147, 47, // Skip to: 40641 -/* 28462 */ MCD_OPC_Decode, 206, 11, 188, 1, // Opcode: SQDMULHv8i16_indexed -/* 28467 */ MCD_OPC_FilterValue, 13, 41, 0, // Skip to: 28512 -/* 28471 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28474 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28493 -/* 28478 */ MCD_OPC_CheckPredicate, 0, 127, 47, // Skip to: 40641 -/* 28482 */ MCD_OPC_CheckField, 10, 1, 0, 121, 47, // Skip to: 40641 -/* 28488 */ MCD_OPC_Decode, 237, 11, 187, 1, // Opcode: SQRDMULHv4i16_indexed -/* 28493 */ MCD_OPC_FilterValue, 2, 112, 47, // Skip to: 40641 -/* 28497 */ MCD_OPC_CheckPredicate, 0, 108, 47, // Skip to: 40641 -/* 28501 */ MCD_OPC_CheckField, 10, 1, 0, 102, 47, // Skip to: 40641 -/* 28507 */ MCD_OPC_Decode, 241, 11, 188, 1, // Opcode: SQRDMULHv8i16_indexed -/* 28512 */ MCD_OPC_FilterValue, 14, 41, 0, // Skip to: 28557 -/* 28516 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28519 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28538 -/* 28523 */ MCD_OPC_CheckPredicate, 0, 82, 47, // Skip to: 40641 -/* 28527 */ MCD_OPC_CheckField, 10, 2, 1, 76, 47, // Skip to: 40641 -/* 28533 */ MCD_OPC_Decode, 147, 10, 181, 1, // Opcode: SCVTFv2i64_shift -/* 28538 */ MCD_OPC_FilterValue, 3, 67, 47, // Skip to: 40641 -/* 28542 */ MCD_OPC_CheckPredicate, 0, 63, 47, // Skip to: 40641 -/* 28546 */ MCD_OPC_CheckField, 10, 2, 1, 57, 47, // Skip to: 40641 -/* 28552 */ MCD_OPC_Decode, 177, 16, 181, 1, // Opcode: UCVTFv2i64_shift -/* 28557 */ MCD_OPC_FilterValue, 15, 48, 47, // Skip to: 40641 -/* 28561 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28564 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28583 -/* 28568 */ MCD_OPC_CheckPredicate, 0, 37, 47, // Skip to: 40641 -/* 28572 */ MCD_OPC_CheckField, 10, 2, 3, 31, 47, // Skip to: 40641 -/* 28578 */ MCD_OPC_Decode, 251, 3, 181, 1, // Opcode: FCVTZSv2i64_shift -/* 28583 */ MCD_OPC_FilterValue, 3, 22, 47, // Skip to: 40641 -/* 28587 */ MCD_OPC_CheckPredicate, 0, 18, 47, // Skip to: 40641 -/* 28591 */ MCD_OPC_CheckField, 10, 2, 3, 12, 47, // Skip to: 40641 -/* 28597 */ MCD_OPC_Decode, 152, 4, 181, 1, // Opcode: FCVTZUv2i64_shift -/* 28602 */ MCD_OPC_FilterValue, 14, 17, 3, // Skip to: 29391 -/* 28606 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 28609 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 28654 -/* 28613 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28616 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28635 -/* 28620 */ MCD_OPC_CheckPredicate, 0, 241, 46, // Skip to: 40641 -/* 28624 */ MCD_OPC_CheckField, 10, 1, 0, 235, 46, // Skip to: 40641 -/* 28630 */ MCD_OPC_Decode, 184, 8, 190, 1, // Opcode: MLAv2i32_indexed -/* 28635 */ MCD_OPC_FilterValue, 3, 226, 46, // Skip to: 40641 -/* 28639 */ MCD_OPC_CheckPredicate, 0, 222, 46, // Skip to: 40641 -/* 28643 */ MCD_OPC_CheckField, 10, 1, 0, 216, 46, // Skip to: 40641 -/* 28649 */ MCD_OPC_Decode, 188, 8, 191, 1, // Opcode: MLAv4i32_indexed -/* 28654 */ MCD_OPC_FilterValue, 1, 41, 0, // Skip to: 28699 -/* 28658 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28661 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28680 -/* 28665 */ MCD_OPC_CheckPredicate, 0, 196, 46, // Skip to: 40641 -/* 28669 */ MCD_OPC_CheckField, 10, 1, 0, 190, 46, // Skip to: 40641 -/* 28675 */ MCD_OPC_Decode, 210, 4, 190, 1, // Opcode: FMLAv2i32_indexed -/* 28680 */ MCD_OPC_FilterValue, 2, 181, 46, // Skip to: 40641 -/* 28684 */ MCD_OPC_CheckPredicate, 0, 177, 46, // Skip to: 40641 -/* 28688 */ MCD_OPC_CheckField, 10, 1, 0, 171, 46, // Skip to: 40641 -/* 28694 */ MCD_OPC_Decode, 213, 4, 191, 1, // Opcode: FMLAv4i32_indexed -/* 28699 */ MCD_OPC_FilterValue, 2, 79, 0, // Skip to: 28782 -/* 28703 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28706 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28725 -/* 28710 */ MCD_OPC_CheckPredicate, 0, 151, 46, // Skip to: 40641 -/* 28714 */ MCD_OPC_CheckField, 10, 1, 0, 145, 46, // Skip to: 40641 -/* 28720 */ MCD_OPC_Decode, 241, 10, 192, 1, // Opcode: SMLALv2i32_indexed -/* 28725 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28744 -/* 28729 */ MCD_OPC_CheckPredicate, 0, 132, 46, // Skip to: 40641 -/* 28733 */ MCD_OPC_CheckField, 10, 1, 0, 126, 46, // Skip to: 40641 -/* 28739 */ MCD_OPC_Decode, 232, 16, 192, 1, // Opcode: UMLALv2i32_indexed -/* 28744 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28763 -/* 28748 */ MCD_OPC_CheckPredicate, 0, 113, 46, // Skip to: 40641 -/* 28752 */ MCD_OPC_CheckField, 10, 1, 0, 107, 46, // Skip to: 40641 -/* 28758 */ MCD_OPC_Decode, 245, 10, 191, 1, // Opcode: SMLALv4i32_indexed -/* 28763 */ MCD_OPC_FilterValue, 3, 98, 46, // Skip to: 40641 -/* 28767 */ MCD_OPC_CheckPredicate, 0, 94, 46, // Skip to: 40641 -/* 28771 */ MCD_OPC_CheckField, 10, 1, 0, 88, 46, // Skip to: 40641 -/* 28777 */ MCD_OPC_Decode, 236, 16, 191, 1, // Opcode: UMLALv4i32_indexed -/* 28782 */ MCD_OPC_FilterValue, 3, 41, 0, // Skip to: 28827 -/* 28786 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28789 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28808 -/* 28793 */ MCD_OPC_CheckPredicate, 0, 68, 46, // Skip to: 40641 -/* 28797 */ MCD_OPC_CheckField, 10, 1, 0, 62, 46, // Skip to: 40641 -/* 28803 */ MCD_OPC_Decode, 175, 11, 192, 1, // Opcode: SQDMLALv2i32_indexed -/* 28808 */ MCD_OPC_FilterValue, 2, 53, 46, // Skip to: 40641 -/* 28812 */ MCD_OPC_CheckPredicate, 0, 49, 46, // Skip to: 40641 -/* 28816 */ MCD_OPC_CheckField, 10, 1, 0, 43, 46, // Skip to: 40641 -/* 28822 */ MCD_OPC_Decode, 179, 11, 191, 1, // Opcode: SQDMLALv4i32_indexed -/* 28827 */ MCD_OPC_FilterValue, 4, 41, 0, // Skip to: 28872 -/* 28831 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28834 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28853 -/* 28838 */ MCD_OPC_CheckPredicate, 0, 23, 46, // Skip to: 40641 -/* 28842 */ MCD_OPC_CheckField, 10, 1, 0, 17, 46, // Skip to: 40641 -/* 28848 */ MCD_OPC_Decode, 194, 8, 190, 1, // Opcode: MLSv2i32_indexed -/* 28853 */ MCD_OPC_FilterValue, 3, 8, 46, // Skip to: 40641 -/* 28857 */ MCD_OPC_CheckPredicate, 0, 4, 46, // Skip to: 40641 -/* 28861 */ MCD_OPC_CheckField, 10, 1, 0, 254, 45, // Skip to: 40641 -/* 28867 */ MCD_OPC_Decode, 198, 8, 191, 1, // Opcode: MLSv4i32_indexed -/* 28872 */ MCD_OPC_FilterValue, 5, 41, 0, // Skip to: 28917 -/* 28876 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28879 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28898 -/* 28883 */ MCD_OPC_CheckPredicate, 0, 234, 45, // Skip to: 40641 -/* 28887 */ MCD_OPC_CheckField, 10, 1, 0, 228, 45, // Skip to: 40641 -/* 28893 */ MCD_OPC_Decode, 218, 4, 190, 1, // Opcode: FMLSv2i32_indexed -/* 28898 */ MCD_OPC_FilterValue, 2, 219, 45, // Skip to: 40641 -/* 28902 */ MCD_OPC_CheckPredicate, 0, 215, 45, // Skip to: 40641 -/* 28906 */ MCD_OPC_CheckField, 10, 1, 0, 209, 45, // Skip to: 40641 -/* 28912 */ MCD_OPC_Decode, 221, 4, 191, 1, // Opcode: FMLSv4i32_indexed -/* 28917 */ MCD_OPC_FilterValue, 6, 79, 0, // Skip to: 29000 -/* 28921 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 28924 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 28943 -/* 28928 */ MCD_OPC_CheckPredicate, 0, 189, 45, // Skip to: 40641 -/* 28932 */ MCD_OPC_CheckField, 10, 1, 0, 183, 45, // Skip to: 40641 -/* 28938 */ MCD_OPC_Decode, 251, 10, 192, 1, // Opcode: SMLSLv2i32_indexed -/* 28943 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 28962 -/* 28947 */ MCD_OPC_CheckPredicate, 0, 170, 45, // Skip to: 40641 -/* 28951 */ MCD_OPC_CheckField, 10, 1, 0, 164, 45, // Skip to: 40641 -/* 28957 */ MCD_OPC_Decode, 242, 16, 192, 1, // Opcode: UMLSLv2i32_indexed -/* 28962 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 28981 -/* 28966 */ MCD_OPC_CheckPredicate, 0, 151, 45, // Skip to: 40641 -/* 28970 */ MCD_OPC_CheckField, 10, 1, 0, 145, 45, // Skip to: 40641 -/* 28976 */ MCD_OPC_Decode, 255, 10, 191, 1, // Opcode: SMLSLv4i32_indexed -/* 28981 */ MCD_OPC_FilterValue, 3, 136, 45, // Skip to: 40641 -/* 28985 */ MCD_OPC_CheckPredicate, 0, 132, 45, // Skip to: 40641 -/* 28989 */ MCD_OPC_CheckField, 10, 1, 0, 126, 45, // Skip to: 40641 -/* 28995 */ MCD_OPC_Decode, 246, 16, 191, 1, // Opcode: UMLSLv4i32_indexed -/* 29000 */ MCD_OPC_FilterValue, 7, 41, 0, // Skip to: 29045 -/* 29004 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29007 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29026 -/* 29011 */ MCD_OPC_CheckPredicate, 0, 106, 45, // Skip to: 40641 -/* 29015 */ MCD_OPC_CheckField, 10, 1, 0, 100, 45, // Skip to: 40641 -/* 29021 */ MCD_OPC_Decode, 187, 11, 192, 1, // Opcode: SQDMLSLv2i32_indexed -/* 29026 */ MCD_OPC_FilterValue, 2, 91, 45, // Skip to: 40641 -/* 29030 */ MCD_OPC_CheckPredicate, 0, 87, 45, // Skip to: 40641 -/* 29034 */ MCD_OPC_CheckField, 10, 1, 0, 81, 45, // Skip to: 40641 -/* 29040 */ MCD_OPC_Decode, 191, 11, 191, 1, // Opcode: SQDMLSLv4i32_indexed -/* 29045 */ MCD_OPC_FilterValue, 8, 41, 0, // Skip to: 29090 -/* 29049 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29052 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29071 -/* 29056 */ MCD_OPC_CheckPredicate, 0, 61, 45, // Skip to: 40641 -/* 29060 */ MCD_OPC_CheckField, 10, 1, 0, 55, 45, // Skip to: 40641 -/* 29066 */ MCD_OPC_Decode, 233, 8, 193, 1, // Opcode: MULv2i32_indexed -/* 29071 */ MCD_OPC_FilterValue, 2, 46, 45, // Skip to: 40641 -/* 29075 */ MCD_OPC_CheckPredicate, 0, 42, 45, // Skip to: 40641 -/* 29079 */ MCD_OPC_CheckField, 10, 1, 0, 36, 45, // Skip to: 40641 -/* 29085 */ MCD_OPC_Decode, 237, 8, 194, 1, // Opcode: MULv4i32_indexed -/* 29090 */ MCD_OPC_FilterValue, 9, 79, 0, // Skip to: 29173 -/* 29094 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29097 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29116 -/* 29101 */ MCD_OPC_CheckPredicate, 0, 16, 45, // Skip to: 40641 -/* 29105 */ MCD_OPC_CheckField, 10, 1, 0, 10, 45, // Skip to: 40641 -/* 29111 */ MCD_OPC_Decode, 253, 4, 193, 1, // Opcode: FMULv2i32_indexed -/* 29116 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 29135 -/* 29120 */ MCD_OPC_CheckPredicate, 0, 253, 44, // Skip to: 40641 -/* 29124 */ MCD_OPC_CheckField, 10, 1, 0, 247, 44, // Skip to: 40641 -/* 29130 */ MCD_OPC_Decode, 245, 4, 193, 1, // Opcode: FMULXv2i32_indexed -/* 29135 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 29154 -/* 29139 */ MCD_OPC_CheckPredicate, 0, 234, 44, // Skip to: 40641 -/* 29143 */ MCD_OPC_CheckField, 10, 1, 0, 228, 44, // Skip to: 40641 -/* 29149 */ MCD_OPC_Decode, 128, 5, 194, 1, // Opcode: FMULv4i32_indexed -/* 29154 */ MCD_OPC_FilterValue, 3, 219, 44, // Skip to: 40641 -/* 29158 */ MCD_OPC_CheckPredicate, 0, 215, 44, // Skip to: 40641 -/* 29162 */ MCD_OPC_CheckField, 10, 1, 0, 209, 44, // Skip to: 40641 -/* 29168 */ MCD_OPC_Decode, 248, 4, 194, 1, // Opcode: FMULXv4i32_indexed -/* 29173 */ MCD_OPC_FilterValue, 10, 79, 0, // Skip to: 29256 -/* 29177 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29180 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29199 -/* 29184 */ MCD_OPC_CheckPredicate, 0, 189, 44, // Skip to: 40641 -/* 29188 */ MCD_OPC_CheckField, 10, 1, 0, 183, 44, // Skip to: 40641 -/* 29194 */ MCD_OPC_Decode, 140, 11, 195, 1, // Opcode: SMULLv2i32_indexed -/* 29199 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 29218 -/* 29203 */ MCD_OPC_CheckPredicate, 0, 170, 44, // Skip to: 40641 -/* 29207 */ MCD_OPC_CheckField, 10, 1, 0, 164, 44, // Skip to: 40641 -/* 29213 */ MCD_OPC_Decode, 130, 17, 195, 1, // Opcode: UMULLv2i32_indexed -/* 29218 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 29237 -/* 29222 */ MCD_OPC_CheckPredicate, 0, 151, 44, // Skip to: 40641 -/* 29226 */ MCD_OPC_CheckField, 10, 1, 0, 145, 44, // Skip to: 40641 -/* 29232 */ MCD_OPC_Decode, 144, 11, 194, 1, // Opcode: SMULLv4i32_indexed -/* 29237 */ MCD_OPC_FilterValue, 3, 136, 44, // Skip to: 40641 -/* 29241 */ MCD_OPC_CheckPredicate, 0, 132, 44, // Skip to: 40641 -/* 29245 */ MCD_OPC_CheckField, 10, 1, 0, 126, 44, // Skip to: 40641 -/* 29251 */ MCD_OPC_Decode, 134, 17, 194, 1, // Opcode: UMULLv4i32_indexed -/* 29256 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 29301 -/* 29260 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29263 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29282 -/* 29267 */ MCD_OPC_CheckPredicate, 0, 106, 44, // Skip to: 40641 -/* 29271 */ MCD_OPC_CheckField, 10, 1, 0, 100, 44, // Skip to: 40641 -/* 29277 */ MCD_OPC_Decode, 211, 11, 195, 1, // Opcode: SQDMULLv2i32_indexed -/* 29282 */ MCD_OPC_FilterValue, 2, 91, 44, // Skip to: 40641 -/* 29286 */ MCD_OPC_CheckPredicate, 0, 87, 44, // Skip to: 40641 -/* 29290 */ MCD_OPC_CheckField, 10, 1, 0, 81, 44, // Skip to: 40641 -/* 29296 */ MCD_OPC_Decode, 215, 11, 194, 1, // Opcode: SQDMULLv4i32_indexed -/* 29301 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 29346 -/* 29305 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29308 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29327 -/* 29312 */ MCD_OPC_CheckPredicate, 0, 61, 44, // Skip to: 40641 -/* 29316 */ MCD_OPC_CheckField, 10, 1, 0, 55, 44, // Skip to: 40641 -/* 29322 */ MCD_OPC_Decode, 200, 11, 193, 1, // Opcode: SQDMULHv2i32_indexed -/* 29327 */ MCD_OPC_FilterValue, 2, 46, 44, // Skip to: 40641 -/* 29331 */ MCD_OPC_CheckPredicate, 0, 42, 44, // Skip to: 40641 -/* 29335 */ MCD_OPC_CheckField, 10, 1, 0, 36, 44, // Skip to: 40641 -/* 29341 */ MCD_OPC_Decode, 204, 11, 194, 1, // Opcode: SQDMULHv4i32_indexed -/* 29346 */ MCD_OPC_FilterValue, 13, 27, 44, // Skip to: 40641 -/* 29350 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29353 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 29372 -/* 29357 */ MCD_OPC_CheckPredicate, 0, 16, 44, // Skip to: 40641 -/* 29361 */ MCD_OPC_CheckField, 10, 1, 0, 10, 44, // Skip to: 40641 -/* 29367 */ MCD_OPC_Decode, 235, 11, 193, 1, // Opcode: SQRDMULHv2i32_indexed -/* 29372 */ MCD_OPC_FilterValue, 2, 1, 44, // Skip to: 40641 -/* 29376 */ MCD_OPC_CheckPredicate, 0, 253, 43, // Skip to: 40641 -/* 29380 */ MCD_OPC_CheckField, 10, 1, 0, 247, 43, // Skip to: 40641 -/* 29386 */ MCD_OPC_Decode, 239, 11, 194, 1, // Opcode: SQRDMULHv4i32_indexed -/* 29391 */ MCD_OPC_FilterValue, 15, 238, 43, // Skip to: 40641 -/* 29395 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 29398 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 29429 -/* 29402 */ MCD_OPC_CheckPredicate, 0, 227, 43, // Skip to: 40641 -/* 29406 */ MCD_OPC_CheckField, 29, 3, 2, 221, 43, // Skip to: 40641 -/* 29412 */ MCD_OPC_CheckField, 21, 1, 0, 215, 43, // Skip to: 40641 -/* 29418 */ MCD_OPC_CheckField, 10, 1, 0, 209, 43, // Skip to: 40641 -/* 29424 */ MCD_OPC_Decode, 211, 4, 196, 1, // Opcode: FMLAv2i64_indexed -/* 29429 */ MCD_OPC_FilterValue, 5, 27, 0, // Skip to: 29460 -/* 29433 */ MCD_OPC_CheckPredicate, 0, 196, 43, // Skip to: 40641 -/* 29437 */ MCD_OPC_CheckField, 29, 3, 2, 190, 43, // Skip to: 40641 -/* 29443 */ MCD_OPC_CheckField, 21, 1, 0, 184, 43, // Skip to: 40641 -/* 29449 */ MCD_OPC_CheckField, 10, 1, 0, 178, 43, // Skip to: 40641 -/* 29455 */ MCD_OPC_Decode, 219, 4, 196, 1, // Opcode: FMLSv2i64_indexed -/* 29460 */ MCD_OPC_FilterValue, 9, 169, 43, // Skip to: 40641 -/* 29464 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29467 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 29492 -/* 29471 */ MCD_OPC_CheckPredicate, 0, 158, 43, // Skip to: 40641 -/* 29475 */ MCD_OPC_CheckField, 21, 1, 0, 152, 43, // Skip to: 40641 -/* 29481 */ MCD_OPC_CheckField, 10, 1, 0, 146, 43, // Skip to: 40641 -/* 29487 */ MCD_OPC_Decode, 254, 4, 197, 1, // Opcode: FMULv2i64_indexed -/* 29492 */ MCD_OPC_FilterValue, 3, 137, 43, // Skip to: 40641 -/* 29496 */ MCD_OPC_CheckPredicate, 0, 133, 43, // Skip to: 40641 -/* 29500 */ MCD_OPC_CheckField, 21, 1, 0, 127, 43, // Skip to: 40641 -/* 29506 */ MCD_OPC_CheckField, 10, 1, 0, 121, 43, // Skip to: 40641 -/* 29512 */ MCD_OPC_Decode, 246, 4, 197, 1, // Opcode: FMULXv2i64_indexed -/* 29517 */ MCD_OPC_FilterValue, 4, 191, 1, // Skip to: 29968 -/* 29521 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 29524 */ MCD_OPC_FilterValue, 0, 19, 0, // Skip to: 29547 -/* 29528 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ... -/* 29531 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29539 -/* 29535 */ MCD_OPC_Decode, 81, 198, 1, // Opcode: ADR -/* 29539 */ MCD_OPC_FilterValue, 1, 90, 43, // Skip to: 40641 -/* 29543 */ MCD_OPC_Decode, 82, 198, 1, // Opcode: ADRP -/* 29547 */ MCD_OPC_FilterValue, 1, 71, 0, // Skip to: 29622 -/* 29551 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29554 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29562 -/* 29558 */ MCD_OPC_Decode, 62, 199, 1, // Opcode: ADDWri -/* 29562 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 29570 -/* 29566 */ MCD_OPC_Decode, 48, 199, 1, // Opcode: ADDSWri -/* 29570 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 29579 -/* 29574 */ MCD_OPC_Decode, 166, 15, 199, 1, // Opcode: SUBWri -/* 29579 */ MCD_OPC_FilterValue, 3, 5, 0, // Skip to: 29588 -/* 29583 */ MCD_OPC_Decode, 157, 15, 199, 1, // Opcode: SUBSWri -/* 29588 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 29596 -/* 29592 */ MCD_OPC_Decode, 66, 199, 1, // Opcode: ADDXri -/* 29596 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 29604 -/* 29600 */ MCD_OPC_Decode, 52, 199, 1, // Opcode: ADDSXri -/* 29604 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 29613 -/* 29608 */ MCD_OPC_Decode, 170, 15, 199, 1, // Opcode: SUBXri -/* 29613 */ MCD_OPC_FilterValue, 7, 16, 43, // Skip to: 40641 -/* 29617 */ MCD_OPC_Decode, 161, 15, 199, 1, // Opcode: SUBSXri -/* 29622 */ MCD_OPC_FilterValue, 2, 197, 0, // Skip to: 29823 -/* 29626 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29629 */ MCD_OPC_FilterValue, 0, 26, 0, // Skip to: 29659 -/* 29633 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 29636 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 29650 -/* 29640 */ MCD_OPC_CheckField, 22, 1, 0, 243, 42, // Skip to: 40641 -/* 29646 */ MCD_OPC_Decode, 93, 200, 1, // Opcode: ANDWri -/* 29650 */ MCD_OPC_FilterValue, 1, 235, 42, // Skip to: 40641 -/* 29654 */ MCD_OPC_Decode, 214, 8, 201, 1, // Opcode: MOVNWi -/* 29659 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 29674 -/* 29663 */ MCD_OPC_CheckField, 22, 2, 0, 220, 42, // Skip to: 40641 -/* 29669 */ MCD_OPC_Decode, 135, 9, 200, 1, // Opcode: ORRWri -/* 29674 */ MCD_OPC_FilterValue, 2, 27, 0, // Skip to: 29705 -/* 29678 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 29681 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 29696 -/* 29685 */ MCD_OPC_CheckField, 22, 1, 0, 198, 42, // Skip to: 40641 -/* 29691 */ MCD_OPC_Decode, 166, 2, 200, 1, // Opcode: EORWri -/* 29696 */ MCD_OPC_FilterValue, 1, 189, 42, // Skip to: 40641 -/* 29700 */ MCD_OPC_Decode, 216, 8, 201, 1, // Opcode: MOVZWi -/* 29705 */ MCD_OPC_FilterValue, 3, 26, 0, // Skip to: 29735 -/* 29709 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 29712 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 29726 -/* 29716 */ MCD_OPC_CheckField, 22, 1, 0, 167, 42, // Skip to: 40641 -/* 29722 */ MCD_OPC_Decode, 87, 200, 1, // Opcode: ANDSWri -/* 29726 */ MCD_OPC_FilterValue, 1, 159, 42, // Skip to: 40641 -/* 29730 */ MCD_OPC_Decode, 212, 8, 201, 1, // Opcode: MOVKWi -/* 29735 */ MCD_OPC_FilterValue, 4, 20, 0, // Skip to: 29759 -/* 29739 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 29742 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29750 -/* 29746 */ MCD_OPC_Decode, 96, 200, 1, // Opcode: ANDXri -/* 29750 */ MCD_OPC_FilterValue, 1, 135, 42, // Skip to: 40641 -/* 29754 */ MCD_OPC_Decode, 215, 8, 201, 1, // Opcode: MOVNXi -/* 29759 */ MCD_OPC_FilterValue, 5, 11, 0, // Skip to: 29774 -/* 29763 */ MCD_OPC_CheckField, 23, 1, 0, 120, 42, // Skip to: 40641 -/* 29769 */ MCD_OPC_Decode, 138, 9, 200, 1, // Opcode: ORRXri -/* 29774 */ MCD_OPC_FilterValue, 6, 21, 0, // Skip to: 29799 -/* 29778 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 29781 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 29790 -/* 29785 */ MCD_OPC_Decode, 169, 2, 200, 1, // Opcode: EORXri -/* 29790 */ MCD_OPC_FilterValue, 1, 95, 42, // Skip to: 40641 -/* 29794 */ MCD_OPC_Decode, 217, 8, 201, 1, // Opcode: MOVZXi -/* 29799 */ MCD_OPC_FilterValue, 7, 86, 42, // Skip to: 40641 -/* 29803 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... -/* 29806 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29814 -/* 29810 */ MCD_OPC_Decode, 90, 200, 1, // Opcode: ANDSXri -/* 29814 */ MCD_OPC_FilterValue, 1, 71, 42, // Skip to: 40641 -/* 29818 */ MCD_OPC_Decode, 213, 8, 201, 1, // Opcode: MOVKXi -/* 29823 */ MCD_OPC_FilterValue, 3, 62, 42, // Skip to: 40641 -/* 29827 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29830 */ MCD_OPC_FilterValue, 0, 33, 0, // Skip to: 29867 -/* 29834 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 29837 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 29852 -/* 29841 */ MCD_OPC_CheckField, 15, 1, 0, 42, 42, // Skip to: 40641 -/* 29847 */ MCD_OPC_Decode, 130, 10, 202, 1, // Opcode: SBFMWri -/* 29852 */ MCD_OPC_FilterValue, 4, 33, 42, // Skip to: 40641 -/* 29856 */ MCD_OPC_CheckField, 15, 1, 0, 27, 42, // Skip to: 40641 -/* 29862 */ MCD_OPC_Decode, 175, 2, 203, 1, // Opcode: EXTRWrri -/* 29867 */ MCD_OPC_FilterValue, 1, 16, 0, // Skip to: 29887 -/* 29871 */ MCD_OPC_CheckField, 21, 3, 0, 12, 42, // Skip to: 40641 -/* 29877 */ MCD_OPC_CheckField, 15, 1, 0, 6, 42, // Skip to: 40641 -/* 29883 */ MCD_OPC_Decode, 104, 204, 1, // Opcode: BFMWri -/* 29887 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 29908 -/* 29891 */ MCD_OPC_CheckField, 21, 3, 0, 248, 41, // Skip to: 40641 -/* 29897 */ MCD_OPC_CheckField, 15, 1, 0, 242, 41, // Skip to: 40641 -/* 29903 */ MCD_OPC_Decode, 160, 16, 202, 1, // Opcode: UBFMWri -/* 29908 */ MCD_OPC_FilterValue, 4, 27, 0, // Skip to: 29939 -/* 29912 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 29915 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 29924 -/* 29919 */ MCD_OPC_Decode, 131, 10, 205, 1, // Opcode: SBFMXri -/* 29924 */ MCD_OPC_FilterValue, 3, 217, 41, // Skip to: 40641 -/* 29928 */ MCD_OPC_CheckField, 21, 1, 0, 211, 41, // Skip to: 40641 -/* 29934 */ MCD_OPC_Decode, 176, 2, 206, 1, // Opcode: EXTRXrri -/* 29939 */ MCD_OPC_FilterValue, 5, 10, 0, // Skip to: 29953 -/* 29943 */ MCD_OPC_CheckField, 22, 2, 1, 196, 41, // Skip to: 40641 -/* 29949 */ MCD_OPC_Decode, 105, 207, 1, // Opcode: BFMXri -/* 29953 */ MCD_OPC_FilterValue, 6, 188, 41, // Skip to: 40641 -/* 29957 */ MCD_OPC_CheckField, 22, 2, 1, 182, 41, // Skip to: 40641 -/* 29963 */ MCD_OPC_Decode, 161, 16, 205, 1, // Opcode: UBFMXri -/* 29968 */ MCD_OPC_FilterValue, 5, 218, 1, // Skip to: 30446 -/* 29972 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 29975 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 29983 -/* 29979 */ MCD_OPC_Decode, 103, 208, 1, // Opcode: B -/* 29983 */ MCD_OPC_FilterValue, 1, 39, 0, // Skip to: 30026 -/* 29987 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 29990 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 29999 -/* 29994 */ MCD_OPC_Decode, 133, 1, 209, 1, // Opcode: CBZW -/* 29999 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30008 -/* 30003 */ MCD_OPC_Decode, 131, 1, 209, 1, // Opcode: CBNZW -/* 30008 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30017 -/* 30012 */ MCD_OPC_Decode, 215, 15, 210, 1, // Opcode: TBZW -/* 30017 */ MCD_OPC_FilterValue, 3, 124, 41, // Skip to: 40641 -/* 30021 */ MCD_OPC_Decode, 205, 15, 210, 1, // Opcode: TBNZW -/* 30026 */ MCD_OPC_FilterValue, 2, 17, 0, // Skip to: 30047 -/* 30030 */ MCD_OPC_CheckField, 24, 2, 0, 109, 41, // Skip to: 40641 -/* 30036 */ MCD_OPC_CheckField, 4, 1, 0, 103, 41, // Skip to: 40641 -/* 30042 */ MCD_OPC_Decode, 130, 1, 211, 1, // Opcode: Bcc -/* 30047 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 30055 -/* 30051 */ MCD_OPC_Decode, 124, 208, 1, // Opcode: BL -/* 30055 */ MCD_OPC_FilterValue, 5, 39, 0, // Skip to: 30098 -/* 30059 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 30062 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30071 -/* 30066 */ MCD_OPC_Decode, 134, 1, 212, 1, // Opcode: CBZX -/* 30071 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30080 -/* 30075 */ MCD_OPC_Decode, 132, 1, 212, 1, // Opcode: CBNZX -/* 30080 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30089 -/* 30084 */ MCD_OPC_Decode, 216, 15, 210, 1, // Opcode: TBZX -/* 30089 */ MCD_OPC_FilterValue, 3, 52, 41, // Skip to: 40641 -/* 30093 */ MCD_OPC_Decode, 206, 15, 210, 1, // Opcode: TBNZX -/* 30098 */ MCD_OPC_FilterValue, 6, 43, 41, // Skip to: 40641 -/* 30102 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... -/* 30105 */ MCD_OPC_FilterValue, 0, 30, 0, // Skip to: 30139 -/* 30109 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 30112 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30121 -/* 30116 */ MCD_OPC_Decode, 194, 15, 213, 1, // Opcode: SVC -/* 30121 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30130 -/* 30125 */ MCD_OPC_Decode, 209, 5, 213, 1, // Opcode: HVC -/* 30130 */ MCD_OPC_FilterValue, 3, 11, 41, // Skip to: 40641 -/* 30134 */ MCD_OPC_Decode, 222, 10, 213, 1, // Opcode: SMC -/* 30139 */ MCD_OPC_FilterValue, 1, 10, 0, // Skip to: 30153 -/* 30143 */ MCD_OPC_CheckField, 0, 5, 0, 252, 40, // Skip to: 40641 -/* 30149 */ MCD_OPC_Decode, 127, 213, 1, // Opcode: BRK -/* 30153 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 30168 -/* 30157 */ MCD_OPC_CheckField, 0, 5, 0, 238, 40, // Skip to: 40641 -/* 30163 */ MCD_OPC_Decode, 208, 5, 213, 1, // Opcode: HLT -/* 30168 */ MCD_OPC_FilterValue, 5, 30, 0, // Skip to: 30202 -/* 30172 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 30175 */ MCD_OPC_FilterValue, 1, 5, 0, // Skip to: 30184 -/* 30179 */ MCD_OPC_Decode, 142, 2, 213, 1, // Opcode: DCPS1 -/* 30184 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30193 -/* 30188 */ MCD_OPC_Decode, 143, 2, 213, 1, // Opcode: DCPS2 -/* 30193 */ MCD_OPC_FilterValue, 3, 204, 40, // Skip to: 40641 -/* 30197 */ MCD_OPC_Decode, 144, 2, 213, 1, // Opcode: DCPS3 -/* 30202 */ MCD_OPC_FilterValue, 8, 122, 0, // Skip to: 30328 -/* 30206 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... -/* 30209 */ MCD_OPC_FilterValue, 95, 11, 0, // Skip to: 30224 -/* 30213 */ MCD_OPC_CheckField, 12, 9, 51, 53, 0, // Skip to: 30272 -/* 30219 */ MCD_OPC_Decode, 143, 1, 214, 1, // Opcode: CLREX -/* 30224 */ MCD_OPC_FilterValue, 159, 1, 11, 0, // Skip to: 30240 -/* 30229 */ MCD_OPC_CheckField, 12, 9, 51, 37, 0, // Skip to: 30272 -/* 30235 */ MCD_OPC_Decode, 147, 2, 214, 1, // Opcode: DSB -/* 30240 */ MCD_OPC_FilterValue, 191, 1, 11, 0, // Skip to: 30256 -/* 30245 */ MCD_OPC_CheckField, 12, 9, 51, 21, 0, // Skip to: 30272 -/* 30251 */ MCD_OPC_Decode, 145, 2, 214, 1, // Opcode: DMB -/* 30256 */ MCD_OPC_FilterValue, 223, 1, 11, 0, // Skip to: 30272 -/* 30261 */ MCD_OPC_CheckField, 12, 9, 51, 5, 0, // Skip to: 30272 -/* 30267 */ MCD_OPC_Decode, 218, 5, 214, 1, // Opcode: ISB -/* 30272 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 30275 */ MCD_OPC_FilterValue, 31, 33, 0, // Skip to: 30312 -/* 30279 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 30282 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 30297 -/* 30286 */ MCD_OPC_CheckField, 16, 5, 3, 20, 0, // Skip to: 30312 -/* 30292 */ MCD_OPC_Decode, 207, 5, 215, 1, // Opcode: HINT -/* 30297 */ MCD_OPC_FilterValue, 4, 11, 0, // Skip to: 30312 -/* 30301 */ MCD_OPC_CheckField, 19, 2, 0, 5, 0, // Skip to: 30312 -/* 30307 */ MCD_OPC_Decode, 228, 8, 216, 1, // Opcode: MSRpstate -/* 30312 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, // Skip to: 30323 -/* 30318 */ MCD_OPC_Decode, 196, 15, 217, 1, // Opcode: SYSxt -/* 30323 */ MCD_OPC_Decode, 227, 8, 218, 1, // Opcode: MSR -/* 30328 */ MCD_OPC_FilterValue, 9, 16, 0, // Skip to: 30348 -/* 30332 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, // Skip to: 30343 -/* 30338 */ MCD_OPC_Decode, 195, 15, 219, 1, // Opcode: SYSLxt -/* 30343 */ MCD_OPC_Decode, 226, 8, 220, 1, // Opcode: MRS -/* 30348 */ MCD_OPC_FilterValue, 16, 17, 0, // Skip to: 30369 -/* 30352 */ MCD_OPC_CheckField, 10, 11, 192, 15, 42, 40, // Skip to: 40641 -/* 30359 */ MCD_OPC_CheckField, 0, 5, 0, 36, 40, // Skip to: 40641 -/* 30365 */ MCD_OPC_Decode, 126, 221, 1, // Opcode: BR -/* 30369 */ MCD_OPC_FilterValue, 17, 17, 0, // Skip to: 30390 -/* 30373 */ MCD_OPC_CheckField, 10, 11, 192, 15, 21, 40, // Skip to: 40641 -/* 30380 */ MCD_OPC_CheckField, 0, 5, 0, 15, 40, // Skip to: 40641 -/* 30386 */ MCD_OPC_Decode, 125, 221, 1, // Opcode: BLR -/* 30390 */ MCD_OPC_FilterValue, 18, 18, 0, // Skip to: 30412 -/* 30394 */ MCD_OPC_CheckField, 10, 11, 192, 15, 0, 40, // Skip to: 40641 -/* 30401 */ MCD_OPC_CheckField, 0, 5, 0, 250, 39, // Skip to: 40641 -/* 30407 */ MCD_OPC_Decode, 168, 9, 221, 1, // Opcode: RET -/* 30412 */ MCD_OPC_FilterValue, 20, 13, 0, // Skip to: 30429 -/* 30416 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 233, 39, // Skip to: 40641 -/* 30424 */ MCD_OPC_Decode, 174, 2, 222, 1, // Opcode: ERET -/* 30429 */ MCD_OPC_FilterValue, 21, 224, 39, // Skip to: 40641 -/* 30433 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 216, 39, // Skip to: 40641 -/* 30441 */ MCD_OPC_Decode, 146, 2, 222, 1, // Opcode: DRPS -/* 30446 */ MCD_OPC_FilterValue, 6, 54, 10, // Skip to: 33064 -/* 30450 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 30453 */ MCD_OPC_FilterValue, 0, 41, 1, // Skip to: 30754 -/* 30457 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 30460 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30469 -/* 30464 */ MCD_OPC_Decode, 134, 8, 209, 1, // Opcode: LDRWl -/* 30469 */ MCD_OPC_FilterValue, 2, 244, 0, // Skip to: 30717 -/* 30473 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 30476 */ MCD_OPC_FilterValue, 0, 68, 0, // Skip to: 30548 -/* 30480 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 30483 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 30497 -/* 30487 */ MCD_OPC_CheckField, 12, 4, 0, 164, 39, // Skip to: 40641 -/* 30493 */ MCD_OPC_Decode, 32, 223, 1, // Opcode: ADCWr -/* 30497 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 30506 -/* 30501 */ MCD_OPC_Decode, 134, 2, 224, 1, // Opcode: CSELWr -/* 30506 */ MCD_OPC_FilterValue, 6, 147, 39, // Skip to: 40641 -/* 30510 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 30513 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30522 -/* 30517 */ MCD_OPC_Decode, 176, 8, 223, 1, // Opcode: LSLVWr -/* 30522 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 30535 -/* 30526 */ MCD_OPC_CheckPredicate, 2, 127, 39, // Skip to: 40641 -/* 30530 */ MCD_OPC_Decode, 254, 1, 223, 1, // Opcode: CRC32Brr -/* 30535 */ MCD_OPC_FilterValue, 5, 118, 39, // Skip to: 40641 -/* 30539 */ MCD_OPC_CheckPredicate, 2, 114, 39, // Skip to: 40641 -/* 30543 */ MCD_OPC_Decode, 255, 1, 223, 1, // Opcode: CRC32CBrr -/* 30548 */ MCD_OPC_FilterValue, 1, 54, 0, // Skip to: 30606 -/* 30552 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 30555 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 30564 -/* 30559 */ MCD_OPC_Decode, 136, 2, 224, 1, // Opcode: CSINCWr -/* 30564 */ MCD_OPC_FilterValue, 6, 89, 39, // Skip to: 40641 -/* 30568 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 30571 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30580 -/* 30575 */ MCD_OPC_Decode, 178, 8, 223, 1, // Opcode: LSRVWr -/* 30580 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 30593 -/* 30584 */ MCD_OPC_CheckPredicate, 2, 69, 39, // Skip to: 40641 -/* 30588 */ MCD_OPC_Decode, 131, 2, 223, 1, // Opcode: CRC32Hrr -/* 30593 */ MCD_OPC_FilterValue, 5, 60, 39, // Skip to: 40641 -/* 30597 */ MCD_OPC_CheckPredicate, 2, 56, 39, // Skip to: 40641 -/* 30601 */ MCD_OPC_Decode, 128, 2, 223, 1, // Opcode: CRC32CHrr -/* 30606 */ MCD_OPC_FilterValue, 2, 70, 0, // Skip to: 30680 -/* 30610 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 30613 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30628 -/* 30617 */ MCD_OPC_CheckField, 21, 3, 6, 34, 39, // Skip to: 40641 -/* 30623 */ MCD_OPC_Decode, 180, 16, 223, 1, // Opcode: UDIVWr -/* 30628 */ MCD_OPC_FilterValue, 2, 10, 0, // Skip to: 30642 -/* 30632 */ MCD_OPC_CheckField, 21, 3, 6, 19, 39, // Skip to: 40641 -/* 30638 */ MCD_OPC_Decode, 101, 223, 1, // Opcode: ASRVWr -/* 30642 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 30661 -/* 30646 */ MCD_OPC_CheckPredicate, 2, 7, 39, // Skip to: 40641 -/* 30650 */ MCD_OPC_CheckField, 21, 3, 6, 1, 39, // Skip to: 40641 -/* 30656 */ MCD_OPC_Decode, 132, 2, 223, 1, // Opcode: CRC32Wrr -/* 30661 */ MCD_OPC_FilterValue, 5, 248, 38, // Skip to: 40641 -/* 30665 */ MCD_OPC_CheckPredicate, 2, 244, 38, // Skip to: 40641 -/* 30669 */ MCD_OPC_CheckField, 21, 3, 6, 238, 38, // Skip to: 40641 -/* 30675 */ MCD_OPC_Decode, 129, 2, 223, 1, // Opcode: CRC32CWrr -/* 30680 */ MCD_OPC_FilterValue, 3, 229, 38, // Skip to: 40641 -/* 30684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 30687 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30702 -/* 30691 */ MCD_OPC_CheckField, 21, 3, 6, 216, 38, // Skip to: 40641 -/* 30697 */ MCD_OPC_Decode, 150, 10, 223, 1, // Opcode: SDIVWr -/* 30702 */ MCD_OPC_FilterValue, 2, 207, 38, // Skip to: 40641 -/* 30706 */ MCD_OPC_CheckField, 21, 3, 6, 201, 38, // Skip to: 40641 -/* 30712 */ MCD_OPC_Decode, 187, 9, 223, 1, // Opcode: RORVWr -/* 30717 */ MCD_OPC_FilterValue, 3, 192, 38, // Skip to: 40641 -/* 30721 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 30724 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30739 -/* 30728 */ MCD_OPC_CheckField, 21, 3, 0, 179, 38, // Skip to: 40641 -/* 30734 */ MCD_OPC_Decode, 180, 8, 225, 1, // Opcode: MADDWrrr -/* 30739 */ MCD_OPC_FilterValue, 1, 170, 38, // Skip to: 40641 -/* 30743 */ MCD_OPC_CheckField, 21, 3, 0, 164, 38, // Skip to: 40641 -/* 30749 */ MCD_OPC_Decode, 229, 8, 225, 1, // Opcode: MSUBWrrr -/* 30754 */ MCD_OPC_FilterValue, 1, 224, 1, // Skip to: 31238 -/* 30758 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 30761 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 30854 -/* 30765 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 30768 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30783 -/* 30772 */ MCD_OPC_CheckField, 21, 1, 0, 135, 38, // Skip to: 40641 -/* 30778 */ MCD_OPC_Decode, 136, 15, 226, 1, // Opcode: STURBBi -/* 30783 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30798 -/* 30787 */ MCD_OPC_CheckField, 21, 1, 0, 120, 38, // Skip to: 40641 -/* 30793 */ MCD_OPC_Decode, 215, 14, 226, 1, // Opcode: STRBBpost -/* 30798 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 30839 -/* 30802 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30805 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30814 -/* 30809 */ MCD_OPC_Decode, 132, 15, 226, 1, // Opcode: STTRBi -/* 30814 */ MCD_OPC_FilterValue, 1, 95, 38, // Skip to: 40641 -/* 30818 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 30821 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30830 -/* 30825 */ MCD_OPC_Decode, 217, 14, 227, 1, // Opcode: STRBBroW -/* 30830 */ MCD_OPC_FilterValue, 3, 79, 38, // Skip to: 40641 -/* 30834 */ MCD_OPC_Decode, 218, 14, 228, 1, // Opcode: STRBBroX -/* 30839 */ MCD_OPC_FilterValue, 3, 70, 38, // Skip to: 40641 -/* 30843 */ MCD_OPC_CheckField, 21, 1, 0, 64, 38, // Skip to: 40641 -/* 30849 */ MCD_OPC_Decode, 216, 14, 226, 1, // Opcode: STRBBpre -/* 30854 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 30947 -/* 30858 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 30861 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30876 -/* 30865 */ MCD_OPC_CheckField, 21, 1, 0, 42, 38, // Skip to: 40641 -/* 30871 */ MCD_OPC_Decode, 155, 8, 226, 1, // Opcode: LDURBBi -/* 30876 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30891 -/* 30880 */ MCD_OPC_CheckField, 21, 1, 0, 27, 38, // Skip to: 40641 -/* 30886 */ MCD_OPC_Decode, 198, 7, 226, 1, // Opcode: LDRBBpost -/* 30891 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 30932 -/* 30895 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30898 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 30907 -/* 30902 */ MCD_OPC_Decode, 146, 8, 226, 1, // Opcode: LDTRBi -/* 30907 */ MCD_OPC_FilterValue, 1, 2, 38, // Skip to: 40641 -/* 30911 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 30914 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 30923 -/* 30918 */ MCD_OPC_Decode, 200, 7, 227, 1, // Opcode: LDRBBroW -/* 30923 */ MCD_OPC_FilterValue, 3, 242, 37, // Skip to: 40641 -/* 30927 */ MCD_OPC_Decode, 201, 7, 228, 1, // Opcode: LDRBBroX -/* 30932 */ MCD_OPC_FilterValue, 3, 233, 37, // Skip to: 40641 -/* 30936 */ MCD_OPC_CheckField, 21, 1, 0, 227, 37, // Skip to: 40641 -/* 30942 */ MCD_OPC_Decode, 199, 7, 226, 1, // Opcode: LDRBBpre -/* 30947 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 31040 -/* 30951 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 30954 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 30969 -/* 30958 */ MCD_OPC_CheckField, 21, 1, 0, 205, 37, // Skip to: 40641 -/* 30964 */ MCD_OPC_Decode, 162, 8, 226, 1, // Opcode: LDURSBXi -/* 30969 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 30984 -/* 30973 */ MCD_OPC_CheckField, 21, 1, 0, 190, 37, // Skip to: 40641 -/* 30979 */ MCD_OPC_Decode, 235, 7, 226, 1, // Opcode: LDRSBXpost -/* 30984 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31025 -/* 30988 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 30991 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31000 -/* 30995 */ MCD_OPC_Decode, 149, 8, 226, 1, // Opcode: LDTRSBXi -/* 31000 */ MCD_OPC_FilterValue, 1, 165, 37, // Skip to: 40641 -/* 31004 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 31007 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31016 -/* 31011 */ MCD_OPC_Decode, 237, 7, 229, 1, // Opcode: LDRSBXroW -/* 31016 */ MCD_OPC_FilterValue, 3, 149, 37, // Skip to: 40641 -/* 31020 */ MCD_OPC_Decode, 238, 7, 230, 1, // Opcode: LDRSBXroX -/* 31025 */ MCD_OPC_FilterValue, 3, 140, 37, // Skip to: 40641 -/* 31029 */ MCD_OPC_CheckField, 21, 1, 0, 134, 37, // Skip to: 40641 -/* 31035 */ MCD_OPC_Decode, 236, 7, 226, 1, // Opcode: LDRSBXpre -/* 31040 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 31133 -/* 31044 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31047 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31062 -/* 31051 */ MCD_OPC_CheckField, 21, 1, 0, 112, 37, // Skip to: 40641 -/* 31057 */ MCD_OPC_Decode, 161, 8, 226, 1, // Opcode: LDURSBWi -/* 31062 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31077 -/* 31066 */ MCD_OPC_CheckField, 21, 1, 0, 97, 37, // Skip to: 40641 -/* 31072 */ MCD_OPC_Decode, 230, 7, 226, 1, // Opcode: LDRSBWpost -/* 31077 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31118 -/* 31081 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 31084 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31093 -/* 31088 */ MCD_OPC_Decode, 148, 8, 226, 1, // Opcode: LDTRSBWi -/* 31093 */ MCD_OPC_FilterValue, 1, 72, 37, // Skip to: 40641 -/* 31097 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 31100 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31109 -/* 31104 */ MCD_OPC_Decode, 232, 7, 227, 1, // Opcode: LDRSBWroW -/* 31109 */ MCD_OPC_FilterValue, 3, 56, 37, // Skip to: 40641 -/* 31113 */ MCD_OPC_Decode, 233, 7, 228, 1, // Opcode: LDRSBWroX -/* 31118 */ MCD_OPC_FilterValue, 3, 47, 37, // Skip to: 40641 -/* 31122 */ MCD_OPC_CheckField, 21, 1, 0, 41, 37, // Skip to: 40641 -/* 31128 */ MCD_OPC_Decode, 231, 7, 226, 1, // Opcode: LDRSBWpre -/* 31133 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31142 -/* 31137 */ MCD_OPC_Decode, 219, 14, 231, 1, // Opcode: STRBBui -/* 31142 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 31151 -/* 31146 */ MCD_OPC_Decode, 202, 7, 231, 1, // Opcode: LDRBBui -/* 31151 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 31160 -/* 31155 */ MCD_OPC_Decode, 239, 7, 231, 1, // Opcode: LDRSBXui -/* 31160 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 31169 -/* 31164 */ MCD_OPC_Decode, 234, 7, 231, 1, // Opcode: LDRSBWui -/* 31169 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 31189 -/* 31173 */ MCD_OPC_CheckField, 21, 1, 0, 246, 36, // Skip to: 40641 -/* 31179 */ MCD_OPC_CheckField, 10, 6, 0, 240, 36, // Skip to: 40641 -/* 31185 */ MCD_OPC_Decode, 30, 223, 1, // Opcode: ADCSWr -/* 31189 */ MCD_OPC_FilterValue, 9, 232, 36, // Skip to: 40641 -/* 31193 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31196 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 31217 -/* 31200 */ MCD_OPC_CheckField, 21, 1, 0, 219, 36, // Skip to: 40641 -/* 31206 */ MCD_OPC_CheckField, 4, 1, 0, 213, 36, // Skip to: 40641 -/* 31212 */ MCD_OPC_Decode, 136, 1, 232, 1, // Opcode: CCMNWr -/* 31217 */ MCD_OPC_FilterValue, 2, 204, 36, // Skip to: 40641 -/* 31221 */ MCD_OPC_CheckField, 21, 1, 0, 198, 36, // Skip to: 40641 -/* 31227 */ MCD_OPC_CheckField, 4, 1, 0, 192, 36, // Skip to: 40641 -/* 31233 */ MCD_OPC_Decode, 135, 1, 233, 1, // Opcode: CCMNWi -/* 31238 */ MCD_OPC_FilterValue, 2, 132, 0, // Skip to: 31374 -/* 31242 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 31245 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31254 -/* 31249 */ MCD_OPC_Decode, 140, 8, 212, 1, // Opcode: LDRXl -/* 31254 */ MCD_OPC_FilterValue, 2, 167, 36, // Skip to: 40641 -/* 31258 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31261 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 31317 -/* 31265 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 31268 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31283 -/* 31272 */ MCD_OPC_CheckField, 12, 4, 0, 147, 36, // Skip to: 40641 -/* 31278 */ MCD_OPC_Decode, 128, 10, 223, 1, // Opcode: SBCWr -/* 31283 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31292 -/* 31287 */ MCD_OPC_Decode, 138, 2, 224, 1, // Opcode: CSINVWr -/* 31292 */ MCD_OPC_FilterValue, 6, 129, 36, // Skip to: 40641 -/* 31296 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 31299 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31308 -/* 31303 */ MCD_OPC_Decode, 164, 9, 234, 1, // Opcode: RBITWr -/* 31308 */ MCD_OPC_FilterValue, 1, 113, 36, // Skip to: 40641 -/* 31312 */ MCD_OPC_Decode, 152, 1, 234, 1, // Opcode: CLZWr -/* 31317 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 31358 -/* 31321 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 31324 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31333 -/* 31328 */ MCD_OPC_Decode, 140, 2, 224, 1, // Opcode: CSNEGWr -/* 31333 */ MCD_OPC_FilterValue, 6, 88, 36, // Skip to: 40641 -/* 31337 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 31340 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31349 -/* 31344 */ MCD_OPC_Decode, 170, 9, 234, 1, // Opcode: REV16Wr -/* 31349 */ MCD_OPC_FilterValue, 1, 72, 36, // Skip to: 40641 -/* 31353 */ MCD_OPC_Decode, 144, 1, 234, 1, // Opcode: CLSWr -/* 31358 */ MCD_OPC_FilterValue, 2, 63, 36, // Skip to: 40641 -/* 31362 */ MCD_OPC_CheckField, 12, 12, 128, 24, 56, 36, // Skip to: 40641 -/* 31369 */ MCD_OPC_Decode, 185, 9, 234, 1, // Opcode: REVWr -/* 31374 */ MCD_OPC_FilterValue, 3, 225, 1, // Skip to: 31859 -/* 31378 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 31381 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 31474 -/* 31385 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31388 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31403 -/* 31392 */ MCD_OPC_CheckField, 21, 1, 0, 27, 36, // Skip to: 40641 -/* 31398 */ MCD_OPC_Decode, 139, 15, 226, 1, // Opcode: STURHHi -/* 31403 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31418 -/* 31407 */ MCD_OPC_CheckField, 21, 1, 0, 12, 36, // Skip to: 40641 -/* 31413 */ MCD_OPC_Decode, 230, 14, 226, 1, // Opcode: STRHHpost -/* 31418 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31459 -/* 31422 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 31425 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31434 -/* 31429 */ MCD_OPC_Decode, 133, 15, 226, 1, // Opcode: STTRHi -/* 31434 */ MCD_OPC_FilterValue, 1, 243, 35, // Skip to: 40641 -/* 31438 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 31441 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31450 -/* 31445 */ MCD_OPC_Decode, 232, 14, 227, 1, // Opcode: STRHHroW -/* 31450 */ MCD_OPC_FilterValue, 3, 227, 35, // Skip to: 40641 -/* 31454 */ MCD_OPC_Decode, 233, 14, 228, 1, // Opcode: STRHHroX -/* 31459 */ MCD_OPC_FilterValue, 3, 218, 35, // Skip to: 40641 -/* 31463 */ MCD_OPC_CheckField, 21, 1, 0, 212, 35, // Skip to: 40641 -/* 31469 */ MCD_OPC_Decode, 231, 14, 226, 1, // Opcode: STRHHpre -/* 31474 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 31567 -/* 31478 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31481 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31496 -/* 31485 */ MCD_OPC_CheckField, 21, 1, 0, 190, 35, // Skip to: 40641 -/* 31491 */ MCD_OPC_Decode, 158, 8, 226, 1, // Opcode: LDURHHi -/* 31496 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31511 -/* 31500 */ MCD_OPC_CheckField, 21, 1, 0, 175, 35, // Skip to: 40641 -/* 31506 */ MCD_OPC_Decode, 214, 7, 226, 1, // Opcode: LDRHHpost -/* 31511 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31552 -/* 31515 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 31518 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31527 -/* 31522 */ MCD_OPC_Decode, 147, 8, 226, 1, // Opcode: LDTRHi -/* 31527 */ MCD_OPC_FilterValue, 1, 150, 35, // Skip to: 40641 -/* 31531 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 31534 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31543 -/* 31538 */ MCD_OPC_Decode, 216, 7, 227, 1, // Opcode: LDRHHroW -/* 31543 */ MCD_OPC_FilterValue, 3, 134, 35, // Skip to: 40641 -/* 31547 */ MCD_OPC_Decode, 217, 7, 228, 1, // Opcode: LDRHHroX -/* 31552 */ MCD_OPC_FilterValue, 3, 125, 35, // Skip to: 40641 -/* 31556 */ MCD_OPC_CheckField, 21, 1, 0, 119, 35, // Skip to: 40641 -/* 31562 */ MCD_OPC_Decode, 215, 7, 226, 1, // Opcode: LDRHHpre -/* 31567 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 31660 -/* 31571 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31574 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31589 -/* 31578 */ MCD_OPC_CheckField, 21, 1, 0, 97, 35, // Skip to: 40641 -/* 31584 */ MCD_OPC_Decode, 164, 8, 226, 1, // Opcode: LDURSHXi -/* 31589 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31604 -/* 31593 */ MCD_OPC_CheckField, 21, 1, 0, 82, 35, // Skip to: 40641 -/* 31599 */ MCD_OPC_Decode, 245, 7, 226, 1, // Opcode: LDRSHXpost -/* 31604 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31645 -/* 31608 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 31611 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31620 -/* 31615 */ MCD_OPC_Decode, 151, 8, 226, 1, // Opcode: LDTRSHXi -/* 31620 */ MCD_OPC_FilterValue, 1, 57, 35, // Skip to: 40641 -/* 31624 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 31627 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31636 -/* 31631 */ MCD_OPC_Decode, 247, 7, 229, 1, // Opcode: LDRSHXroW -/* 31636 */ MCD_OPC_FilterValue, 3, 41, 35, // Skip to: 40641 -/* 31640 */ MCD_OPC_Decode, 248, 7, 230, 1, // Opcode: LDRSHXroX -/* 31645 */ MCD_OPC_FilterValue, 3, 32, 35, // Skip to: 40641 -/* 31649 */ MCD_OPC_CheckField, 21, 1, 0, 26, 35, // Skip to: 40641 -/* 31655 */ MCD_OPC_Decode, 246, 7, 226, 1, // Opcode: LDRSHXpre -/* 31660 */ MCD_OPC_FilterValue, 3, 89, 0, // Skip to: 31753 -/* 31664 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31667 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31682 -/* 31671 */ MCD_OPC_CheckField, 21, 1, 0, 4, 35, // Skip to: 40641 -/* 31677 */ MCD_OPC_Decode, 163, 8, 226, 1, // Opcode: LDURSHWi -/* 31682 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 31697 -/* 31686 */ MCD_OPC_CheckField, 21, 1, 0, 245, 34, // Skip to: 40641 -/* 31692 */ MCD_OPC_Decode, 240, 7, 226, 1, // Opcode: LDRSHWpost -/* 31697 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 31738 -/* 31701 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 31704 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31713 -/* 31708 */ MCD_OPC_Decode, 150, 8, 226, 1, // Opcode: LDTRSHWi -/* 31713 */ MCD_OPC_FilterValue, 1, 220, 34, // Skip to: 40641 -/* 31717 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 31720 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 31729 -/* 31724 */ MCD_OPC_Decode, 242, 7, 227, 1, // Opcode: LDRSHWroW -/* 31729 */ MCD_OPC_FilterValue, 3, 204, 34, // Skip to: 40641 -/* 31733 */ MCD_OPC_Decode, 243, 7, 228, 1, // Opcode: LDRSHWroX -/* 31738 */ MCD_OPC_FilterValue, 3, 195, 34, // Skip to: 40641 -/* 31742 */ MCD_OPC_CheckField, 21, 1, 0, 189, 34, // Skip to: 40641 -/* 31748 */ MCD_OPC_Decode, 241, 7, 226, 1, // Opcode: LDRSHWpre -/* 31753 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31762 -/* 31757 */ MCD_OPC_Decode, 234, 14, 231, 1, // Opcode: STRHHui -/* 31762 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 31771 -/* 31766 */ MCD_OPC_Decode, 218, 7, 231, 1, // Opcode: LDRHHui -/* 31771 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 31780 -/* 31775 */ MCD_OPC_Decode, 249, 7, 231, 1, // Opcode: LDRSHXui -/* 31780 */ MCD_OPC_FilterValue, 7, 5, 0, // Skip to: 31789 -/* 31784 */ MCD_OPC_Decode, 244, 7, 231, 1, // Opcode: LDRSHWui -/* 31789 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 31810 -/* 31793 */ MCD_OPC_CheckField, 21, 1, 0, 138, 34, // Skip to: 40641 -/* 31799 */ MCD_OPC_CheckField, 10, 6, 0, 132, 34, // Skip to: 40641 -/* 31805 */ MCD_OPC_Decode, 254, 9, 223, 1, // Opcode: SBCSWr -/* 31810 */ MCD_OPC_FilterValue, 9, 123, 34, // Skip to: 40641 -/* 31814 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31817 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 31838 -/* 31821 */ MCD_OPC_CheckField, 21, 1, 0, 110, 34, // Skip to: 40641 -/* 31827 */ MCD_OPC_CheckField, 4, 1, 0, 104, 34, // Skip to: 40641 -/* 31833 */ MCD_OPC_Decode, 140, 1, 232, 1, // Opcode: CCMPWr -/* 31838 */ MCD_OPC_FilterValue, 2, 95, 34, // Skip to: 40641 -/* 31842 */ MCD_OPC_CheckField, 21, 1, 0, 89, 34, // Skip to: 40641 -/* 31848 */ MCD_OPC_CheckField, 4, 1, 0, 83, 34, // Skip to: 40641 -/* 31854 */ MCD_OPC_Decode, 139, 1, 233, 1, // Opcode: CCMPWi -/* 31859 */ MCD_OPC_FilterValue, 4, 62, 1, // Skip to: 32181 -/* 31863 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 31866 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 31875 -/* 31870 */ MCD_OPC_Decode, 250, 7, 212, 1, // Opcode: LDRSWl -/* 31875 */ MCD_OPC_FilterValue, 2, 190, 0, // Skip to: 32069 -/* 31879 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 31882 */ MCD_OPC_FilterValue, 0, 41, 0, // Skip to: 31927 -/* 31886 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 31889 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 31903 -/* 31893 */ MCD_OPC_CheckField, 12, 4, 0, 38, 34, // Skip to: 40641 -/* 31899 */ MCD_OPC_Decode, 33, 235, 1, // Opcode: ADCXr -/* 31903 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31912 -/* 31907 */ MCD_OPC_Decode, 135, 2, 236, 1, // Opcode: CSELXr -/* 31912 */ MCD_OPC_FilterValue, 6, 21, 34, // Skip to: 40641 -/* 31916 */ MCD_OPC_CheckField, 12, 4, 2, 15, 34, // Skip to: 40641 -/* 31922 */ MCD_OPC_Decode, 177, 8, 235, 1, // Opcode: LSLVXr -/* 31927 */ MCD_OPC_FilterValue, 1, 27, 0, // Skip to: 31958 -/* 31931 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 31934 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 31943 -/* 31938 */ MCD_OPC_Decode, 137, 2, 236, 1, // Opcode: CSINCXr -/* 31943 */ MCD_OPC_FilterValue, 6, 246, 33, // Skip to: 40641 -/* 31947 */ MCD_OPC_CheckField, 12, 4, 2, 240, 33, // Skip to: 40641 -/* 31953 */ MCD_OPC_Decode, 179, 8, 235, 1, // Opcode: LSRVXr -/* 31958 */ MCD_OPC_FilterValue, 2, 32, 0, // Skip to: 31994 -/* 31962 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 31965 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 31980 -/* 31969 */ MCD_OPC_CheckField, 21, 3, 6, 218, 33, // Skip to: 40641 -/* 31975 */ MCD_OPC_Decode, 181, 16, 235, 1, // Opcode: UDIVXr -/* 31980 */ MCD_OPC_FilterValue, 2, 209, 33, // Skip to: 40641 -/* 31984 */ MCD_OPC_CheckField, 21, 3, 6, 203, 33, // Skip to: 40641 -/* 31990 */ MCD_OPC_Decode, 102, 235, 1, // Opcode: ASRVXr -/* 31994 */ MCD_OPC_FilterValue, 3, 195, 33, // Skip to: 40641 -/* 31998 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 32001 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32016 -/* 32005 */ MCD_OPC_CheckField, 21, 3, 6, 182, 33, // Skip to: 40641 -/* 32011 */ MCD_OPC_Decode, 151, 10, 235, 1, // Opcode: SDIVXr -/* 32016 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32031 -/* 32020 */ MCD_OPC_CheckField, 21, 3, 6, 167, 33, // Skip to: 40641 -/* 32026 */ MCD_OPC_Decode, 188, 9, 235, 1, // Opcode: RORVXr -/* 32031 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 32050 -/* 32035 */ MCD_OPC_CheckPredicate, 2, 154, 33, // Skip to: 40641 -/* 32039 */ MCD_OPC_CheckField, 21, 3, 6, 148, 33, // Skip to: 40641 -/* 32045 */ MCD_OPC_Decode, 133, 2, 237, 1, // Opcode: CRC32Xrr -/* 32050 */ MCD_OPC_FilterValue, 5, 139, 33, // Skip to: 40641 -/* 32054 */ MCD_OPC_CheckPredicate, 2, 135, 33, // Skip to: 40641 -/* 32058 */ MCD_OPC_CheckField, 21, 3, 6, 129, 33, // Skip to: 40641 -/* 32064 */ MCD_OPC_Decode, 130, 2, 237, 1, // Opcode: CRC32CXrr -/* 32069 */ MCD_OPC_FilterValue, 3, 120, 33, // Skip to: 40641 -/* 32073 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 32076 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 32101 -/* 32080 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 32083 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32092 -/* 32087 */ MCD_OPC_Decode, 181, 8, 238, 1, // Opcode: MADDXrrr -/* 32092 */ MCD_OPC_FilterValue, 1, 97, 33, // Skip to: 40641 -/* 32096 */ MCD_OPC_Decode, 230, 8, 238, 1, // Opcode: MSUBXrrr -/* 32101 */ MCD_OPC_FilterValue, 1, 21, 0, // Skip to: 32126 -/* 32105 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 32108 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32117 -/* 32112 */ MCD_OPC_Decode, 204, 10, 239, 1, // Opcode: SMADDLrrr -/* 32117 */ MCD_OPC_FilterValue, 1, 72, 33, // Skip to: 40641 -/* 32121 */ MCD_OPC_Decode, 137, 11, 239, 1, // Opcode: SMSUBLrrr -/* 32126 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32141 -/* 32130 */ MCD_OPC_CheckField, 15, 1, 0, 57, 33, // Skip to: 40641 -/* 32136 */ MCD_OPC_Decode, 138, 11, 235, 1, // Opcode: SMULHrr -/* 32141 */ MCD_OPC_FilterValue, 5, 21, 0, // Skip to: 32166 -/* 32145 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 32148 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32157 -/* 32152 */ MCD_OPC_Decode, 196, 16, 239, 1, // Opcode: UMADDLrrr -/* 32157 */ MCD_OPC_FilterValue, 1, 32, 33, // Skip to: 40641 -/* 32161 */ MCD_OPC_Decode, 255, 16, 239, 1, // Opcode: UMSUBLrrr -/* 32166 */ MCD_OPC_FilterValue, 6, 23, 33, // Skip to: 40641 -/* 32170 */ MCD_OPC_CheckField, 15, 1, 0, 17, 33, // Skip to: 40641 -/* 32176 */ MCD_OPC_Decode, 128, 17, 235, 1, // Opcode: UMULHrr -/* 32181 */ MCD_OPC_FilterValue, 5, 122, 1, // Skip to: 32563 -/* 32185 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 32188 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 32281 -/* 32192 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32195 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32210 -/* 32199 */ MCD_OPC_CheckField, 21, 1, 0, 244, 32, // Skip to: 40641 -/* 32205 */ MCD_OPC_Decode, 143, 15, 226, 1, // Opcode: STURWi -/* 32210 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32225 -/* 32214 */ MCD_OPC_CheckField, 21, 1, 0, 229, 32, // Skip to: 40641 -/* 32220 */ MCD_OPC_Decode, 250, 14, 226, 1, // Opcode: STRWpost -/* 32225 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32266 -/* 32229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 32232 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32241 -/* 32236 */ MCD_OPC_Decode, 134, 15, 226, 1, // Opcode: STTRWi -/* 32241 */ MCD_OPC_FilterValue, 1, 204, 32, // Skip to: 40641 -/* 32245 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 32248 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32257 -/* 32252 */ MCD_OPC_Decode, 252, 14, 227, 1, // Opcode: STRWroW -/* 32257 */ MCD_OPC_FilterValue, 3, 188, 32, // Skip to: 40641 -/* 32261 */ MCD_OPC_Decode, 253, 14, 228, 1, // Opcode: STRWroX -/* 32266 */ MCD_OPC_FilterValue, 3, 179, 32, // Skip to: 40641 -/* 32270 */ MCD_OPC_CheckField, 21, 1, 0, 173, 32, // Skip to: 40641 -/* 32276 */ MCD_OPC_Decode, 251, 14, 226, 1, // Opcode: STRWpre -/* 32281 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 32374 -/* 32285 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32288 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32303 -/* 32292 */ MCD_OPC_CheckField, 21, 1, 0, 151, 32, // Skip to: 40641 -/* 32298 */ MCD_OPC_Decode, 167, 8, 226, 1, // Opcode: LDURWi -/* 32303 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32318 -/* 32307 */ MCD_OPC_CheckField, 21, 1, 0, 136, 32, // Skip to: 40641 -/* 32313 */ MCD_OPC_Decode, 135, 8, 226, 1, // Opcode: LDRWpost -/* 32318 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32359 -/* 32322 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 32325 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32334 -/* 32329 */ MCD_OPC_Decode, 153, 8, 226, 1, // Opcode: LDTRWi -/* 32334 */ MCD_OPC_FilterValue, 1, 111, 32, // Skip to: 40641 -/* 32338 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 32341 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32350 -/* 32345 */ MCD_OPC_Decode, 137, 8, 227, 1, // Opcode: LDRWroW -/* 32350 */ MCD_OPC_FilterValue, 3, 95, 32, // Skip to: 40641 -/* 32354 */ MCD_OPC_Decode, 138, 8, 228, 1, // Opcode: LDRWroX -/* 32359 */ MCD_OPC_FilterValue, 3, 86, 32, // Skip to: 40641 -/* 32363 */ MCD_OPC_CheckField, 21, 1, 0, 80, 32, // Skip to: 40641 -/* 32369 */ MCD_OPC_Decode, 136, 8, 226, 1, // Opcode: LDRWpre -/* 32374 */ MCD_OPC_FilterValue, 2, 89, 0, // Skip to: 32467 -/* 32378 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32381 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32396 -/* 32385 */ MCD_OPC_CheckField, 21, 1, 0, 58, 32, // Skip to: 40641 -/* 32391 */ MCD_OPC_Decode, 165, 8, 226, 1, // Opcode: LDURSWi -/* 32396 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32411 -/* 32400 */ MCD_OPC_CheckField, 21, 1, 0, 43, 32, // Skip to: 40641 -/* 32406 */ MCD_OPC_Decode, 251, 7, 226, 1, // Opcode: LDRSWpost -/* 32411 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32452 -/* 32415 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 32418 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32427 -/* 32422 */ MCD_OPC_Decode, 152, 8, 226, 1, // Opcode: LDTRSWi -/* 32427 */ MCD_OPC_FilterValue, 1, 18, 32, // Skip to: 40641 -/* 32431 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 32434 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32443 -/* 32438 */ MCD_OPC_Decode, 253, 7, 229, 1, // Opcode: LDRSWroW -/* 32443 */ MCD_OPC_FilterValue, 3, 2, 32, // Skip to: 40641 -/* 32447 */ MCD_OPC_Decode, 254, 7, 230, 1, // Opcode: LDRSWroX -/* 32452 */ MCD_OPC_FilterValue, 3, 249, 31, // Skip to: 40641 -/* 32456 */ MCD_OPC_CheckField, 21, 1, 0, 243, 31, // Skip to: 40641 -/* 32462 */ MCD_OPC_Decode, 252, 7, 226, 1, // Opcode: LDRSWpre -/* 32467 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32476 -/* 32471 */ MCD_OPC_Decode, 254, 14, 231, 1, // Opcode: STRWui -/* 32476 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 32485 -/* 32480 */ MCD_OPC_Decode, 139, 8, 231, 1, // Opcode: LDRWui -/* 32485 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 32494 -/* 32489 */ MCD_OPC_Decode, 255, 7, 231, 1, // Opcode: LDRSWui -/* 32494 */ MCD_OPC_FilterValue, 8, 16, 0, // Skip to: 32514 -/* 32498 */ MCD_OPC_CheckField, 21, 1, 0, 201, 31, // Skip to: 40641 -/* 32504 */ MCD_OPC_CheckField, 10, 6, 0, 195, 31, // Skip to: 40641 -/* 32510 */ MCD_OPC_Decode, 31, 235, 1, // Opcode: ADCSXr -/* 32514 */ MCD_OPC_FilterValue, 9, 187, 31, // Skip to: 40641 -/* 32518 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32521 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 32542 -/* 32525 */ MCD_OPC_CheckField, 21, 1, 0, 174, 31, // Skip to: 40641 -/* 32531 */ MCD_OPC_CheckField, 4, 1, 0, 168, 31, // Skip to: 40641 -/* 32537 */ MCD_OPC_Decode, 138, 1, 240, 1, // Opcode: CCMNXr -/* 32542 */ MCD_OPC_FilterValue, 2, 159, 31, // Skip to: 40641 -/* 32546 */ MCD_OPC_CheckField, 21, 1, 0, 153, 31, // Skip to: 40641 -/* 32552 */ MCD_OPC_CheckField, 4, 1, 0, 147, 31, // Skip to: 40641 -/* 32558 */ MCD_OPC_Decode, 137, 1, 241, 1, // Opcode: CCMNXi -/* 32563 */ MCD_OPC_FilterValue, 6, 148, 0, // Skip to: 32715 -/* 32567 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 32570 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32579 -/* 32574 */ MCD_OPC_Decode, 153, 9, 242, 1, // Opcode: PRFMl -/* 32579 */ MCD_OPC_FilterValue, 2, 122, 31, // Skip to: 40641 -/* 32583 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32586 */ MCD_OPC_FilterValue, 0, 52, 0, // Skip to: 32642 -/* 32590 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 32593 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32608 -/* 32597 */ MCD_OPC_CheckField, 12, 4, 0, 102, 31, // Skip to: 40641 -/* 32603 */ MCD_OPC_Decode, 129, 10, 235, 1, // Opcode: SBCXr -/* 32608 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32617 -/* 32612 */ MCD_OPC_Decode, 139, 2, 236, 1, // Opcode: CSINVXr -/* 32617 */ MCD_OPC_FilterValue, 6, 84, 31, // Skip to: 40641 -/* 32621 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 32624 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32633 -/* 32628 */ MCD_OPC_Decode, 165, 9, 243, 1, // Opcode: RBITXr -/* 32633 */ MCD_OPC_FilterValue, 1, 68, 31, // Skip to: 40641 -/* 32637 */ MCD_OPC_Decode, 153, 1, 243, 1, // Opcode: CLZXr -/* 32642 */ MCD_OPC_FilterValue, 1, 37, 0, // Skip to: 32683 -/* 32646 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 32649 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32658 -/* 32653 */ MCD_OPC_Decode, 141, 2, 236, 1, // Opcode: CSNEGXr -/* 32658 */ MCD_OPC_FilterValue, 6, 43, 31, // Skip to: 40641 -/* 32662 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... -/* 32665 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32674 -/* 32669 */ MCD_OPC_Decode, 171, 9, 243, 1, // Opcode: REV16Xr -/* 32674 */ MCD_OPC_FilterValue, 1, 27, 31, // Skip to: 40641 -/* 32678 */ MCD_OPC_Decode, 145, 1, 243, 1, // Opcode: CLSXr -/* 32683 */ MCD_OPC_FilterValue, 2, 12, 0, // Skip to: 32699 -/* 32687 */ MCD_OPC_CheckField, 12, 12, 128, 24, 11, 31, // Skip to: 40641 -/* 32694 */ MCD_OPC_Decode, 174, 9, 243, 1, // Opcode: REV32Xr -/* 32699 */ MCD_OPC_FilterValue, 3, 2, 31, // Skip to: 40641 -/* 32703 */ MCD_OPC_CheckField, 12, 12, 128, 24, 251, 30, // Skip to: 40641 -/* 32710 */ MCD_OPC_Decode, 186, 9, 243, 1, // Opcode: REVXr -/* 32715 */ MCD_OPC_FilterValue, 7, 242, 30, // Skip to: 40641 -/* 32719 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 32722 */ MCD_OPC_FilterValue, 0, 89, 0, // Skip to: 32815 -/* 32726 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32729 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32744 -/* 32733 */ MCD_OPC_CheckField, 21, 1, 0, 222, 30, // Skip to: 40641 -/* 32739 */ MCD_OPC_Decode, 144, 15, 226, 1, // Opcode: STURXi -/* 32744 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32759 -/* 32748 */ MCD_OPC_CheckField, 21, 1, 0, 207, 30, // Skip to: 40641 -/* 32754 */ MCD_OPC_Decode, 255, 14, 226, 1, // Opcode: STRXpost -/* 32759 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32800 -/* 32763 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 32766 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32775 -/* 32770 */ MCD_OPC_Decode, 135, 15, 226, 1, // Opcode: STTRXi -/* 32775 */ MCD_OPC_FilterValue, 1, 182, 30, // Skip to: 40641 -/* 32779 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 32782 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32791 -/* 32786 */ MCD_OPC_Decode, 129, 15, 229, 1, // Opcode: STRXroW -/* 32791 */ MCD_OPC_FilterValue, 3, 166, 30, // Skip to: 40641 -/* 32795 */ MCD_OPC_Decode, 130, 15, 230, 1, // Opcode: STRXroX -/* 32800 */ MCD_OPC_FilterValue, 3, 157, 30, // Skip to: 40641 -/* 32804 */ MCD_OPC_CheckField, 21, 1, 0, 151, 30, // Skip to: 40641 -/* 32810 */ MCD_OPC_Decode, 128, 15, 226, 1, // Opcode: STRXpre -/* 32815 */ MCD_OPC_FilterValue, 1, 89, 0, // Skip to: 32908 -/* 32819 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32822 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32837 -/* 32826 */ MCD_OPC_CheckField, 21, 1, 0, 129, 30, // Skip to: 40641 -/* 32832 */ MCD_OPC_Decode, 168, 8, 226, 1, // Opcode: LDURXi -/* 32837 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 32852 -/* 32841 */ MCD_OPC_CheckField, 21, 1, 0, 114, 30, // Skip to: 40641 -/* 32847 */ MCD_OPC_Decode, 141, 8, 226, 1, // Opcode: LDRXpost -/* 32852 */ MCD_OPC_FilterValue, 2, 37, 0, // Skip to: 32893 -/* 32856 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 32859 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 32868 -/* 32863 */ MCD_OPC_Decode, 154, 8, 226, 1, // Opcode: LDTRXi -/* 32868 */ MCD_OPC_FilterValue, 1, 89, 30, // Skip to: 40641 -/* 32872 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 32875 */ MCD_OPC_FilterValue, 2, 5, 0, // Skip to: 32884 -/* 32879 */ MCD_OPC_Decode, 143, 8, 229, 1, // Opcode: LDRXroW -/* 32884 */ MCD_OPC_FilterValue, 3, 73, 30, // Skip to: 40641 -/* 32888 */ MCD_OPC_Decode, 144, 8, 230, 1, // Opcode: LDRXroX -/* 32893 */ MCD_OPC_FilterValue, 3, 64, 30, // Skip to: 40641 -/* 32897 */ MCD_OPC_CheckField, 21, 1, 0, 58, 30, // Skip to: 40641 -/* 32903 */ MCD_OPC_Decode, 142, 8, 226, 1, // Opcode: LDRXpre -/* 32908 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 32967 -/* 32912 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 32915 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 32930 -/* 32919 */ MCD_OPC_CheckField, 21, 1, 0, 36, 30, // Skip to: 40641 -/* 32925 */ MCD_OPC_Decode, 157, 9, 226, 1, // Opcode: PRFUMi -/* 32930 */ MCD_OPC_FilterValue, 2, 27, 30, // Skip to: 40641 -/* 32934 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 32937 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 32952 -/* 32941 */ MCD_OPC_CheckField, 21, 1, 1, 14, 30, // Skip to: 40641 -/* 32947 */ MCD_OPC_Decode, 154, 9, 244, 1, // Opcode: PRFMroW -/* 32952 */ MCD_OPC_FilterValue, 3, 5, 30, // Skip to: 40641 -/* 32956 */ MCD_OPC_CheckField, 21, 1, 1, 255, 29, // Skip to: 40641 -/* 32962 */ MCD_OPC_Decode, 155, 9, 245, 1, // Opcode: PRFMroX -/* 32967 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 32976 -/* 32971 */ MCD_OPC_Decode, 131, 15, 231, 1, // Opcode: STRXui -/* 32976 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 32985 -/* 32980 */ MCD_OPC_Decode, 145, 8, 231, 1, // Opcode: LDRXui -/* 32985 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 32994 -/* 32989 */ MCD_OPC_Decode, 156, 9, 231, 1, // Opcode: PRFMui -/* 32994 */ MCD_OPC_FilterValue, 8, 17, 0, // Skip to: 33015 -/* 32998 */ MCD_OPC_CheckField, 21, 1, 0, 213, 29, // Skip to: 40641 -/* 33004 */ MCD_OPC_CheckField, 10, 6, 0, 207, 29, // Skip to: 40641 -/* 33010 */ MCD_OPC_Decode, 255, 9, 235, 1, // Opcode: SBCSXr -/* 33015 */ MCD_OPC_FilterValue, 9, 198, 29, // Skip to: 40641 -/* 33019 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 33022 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 33043 -/* 33026 */ MCD_OPC_CheckField, 21, 1, 0, 185, 29, // Skip to: 40641 -/* 33032 */ MCD_OPC_CheckField, 4, 1, 0, 179, 29, // Skip to: 40641 -/* 33038 */ MCD_OPC_Decode, 142, 1, 240, 1, // Opcode: CCMPXr -/* 33043 */ MCD_OPC_FilterValue, 2, 170, 29, // Skip to: 40641 -/* 33047 */ MCD_OPC_CheckField, 21, 1, 0, 164, 29, // Skip to: 40641 -/* 33053 */ MCD_OPC_CheckField, 4, 1, 0, 158, 29, // Skip to: 40641 -/* 33059 */ MCD_OPC_Decode, 141, 1, 241, 1, // Opcode: CCMPXi -/* 33064 */ MCD_OPC_FilterValue, 7, 149, 29, // Skip to: 40641 -/* 33068 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... -/* 33071 */ MCD_OPC_FilterValue, 0, 8, 6, // Skip to: 34619 -/* 33075 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 33078 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 33087 -/* 33082 */ MCD_OPC_Decode, 128, 8, 246, 1, // Opcode: LDRSl -/* 33087 */ MCD_OPC_FilterValue, 2, 109, 5, // Skip to: 34480 -/* 33091 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 33094 */ MCD_OPC_FilterValue, 0, 55, 0, // Skip to: 33153 -/* 33098 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... -/* 33101 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33114 -/* 33105 */ MCD_OPC_CheckPredicate, 3, 108, 29, // Skip to: 40641 -/* 33109 */ MCD_OPC_Decode, 133, 10, 247, 1, // Opcode: SCVTFSWSri -/* 33114 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33127 -/* 33118 */ MCD_OPC_CheckPredicate, 3, 95, 29, // Skip to: 40641 -/* 33122 */ MCD_OPC_Decode, 163, 16, 247, 1, // Opcode: UCVTFSWSri -/* 33127 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 33140 -/* 33131 */ MCD_OPC_CheckPredicate, 3, 82, 29, // Skip to: 40641 -/* 33135 */ MCD_OPC_Decode, 226, 3, 248, 1, // Opcode: FCVTZSSWSri -/* 33140 */ MCD_OPC_FilterValue, 51, 73, 29, // Skip to: 40641 -/* 33144 */ MCD_OPC_CheckPredicate, 3, 69, 29, // Skip to: 40641 -/* 33148 */ MCD_OPC_Decode, 255, 3, 248, 1, // Opcode: FCVTZUSWSri -/* 33153 */ MCD_OPC_FilterValue, 1, 125, 2, // Skip to: 33794 -/* 33157 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 33160 */ MCD_OPC_FilterValue, 0, 204, 1, // Skip to: 33624 -/* 33164 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 33167 */ MCD_OPC_FilterValue, 0, 178, 1, // Skip to: 33605 -/* 33171 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 33174 */ MCD_OPC_FilterValue, 0, 185, 0, // Skip to: 33363 -/* 33178 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 33181 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33194 -/* 33185 */ MCD_OPC_CheckPredicate, 3, 28, 29, // Skip to: 40641 -/* 33189 */ MCD_OPC_Decode, 181, 3, 249, 1, // Opcode: FCVTNSUWSr -/* 33194 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33207 -/* 33198 */ MCD_OPC_CheckPredicate, 3, 15, 29, // Skip to: 40641 -/* 33202 */ MCD_OPC_Decode, 190, 3, 249, 1, // Opcode: FCVTNUUWSr -/* 33207 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33220 -/* 33211 */ MCD_OPC_CheckPredicate, 3, 2, 29, // Skip to: 40641 -/* 33215 */ MCD_OPC_Decode, 137, 10, 250, 1, // Opcode: SCVTFUWSri -/* 33220 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33233 -/* 33224 */ MCD_OPC_CheckPredicate, 3, 245, 28, // Skip to: 40641 -/* 33228 */ MCD_OPC_Decode, 167, 16, 250, 1, // Opcode: UCVTFUWSri -/* 33233 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33246 -/* 33237 */ MCD_OPC_CheckPredicate, 3, 232, 28, // Skip to: 40641 -/* 33241 */ MCD_OPC_Decode, 137, 3, 249, 1, // Opcode: FCVTASUWSr -/* 33246 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33259 -/* 33250 */ MCD_OPC_CheckPredicate, 3, 219, 28, // Skip to: 40641 -/* 33254 */ MCD_OPC_Decode, 146, 3, 249, 1, // Opcode: FCVTAUUWSr -/* 33259 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33272 -/* 33263 */ MCD_OPC_CheckPredicate, 3, 206, 28, // Skip to: 40641 -/* 33267 */ MCD_OPC_Decode, 226, 4, 249, 1, // Opcode: FMOVSWr -/* 33272 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33285 -/* 33276 */ MCD_OPC_CheckPredicate, 3, 193, 28, // Skip to: 40641 -/* 33280 */ MCD_OPC_Decode, 229, 4, 250, 1, // Opcode: FMOVWSr -/* 33285 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33298 -/* 33289 */ MCD_OPC_CheckPredicate, 3, 180, 28, // Skip to: 40641 -/* 33293 */ MCD_OPC_Decode, 203, 3, 249, 1, // Opcode: FCVTPSUWSr -/* 33298 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 33311 -/* 33302 */ MCD_OPC_CheckPredicate, 3, 167, 28, // Skip to: 40641 -/* 33306 */ MCD_OPC_Decode, 212, 3, 249, 1, // Opcode: FCVTPUUWSr -/* 33311 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33324 -/* 33315 */ MCD_OPC_CheckPredicate, 3, 154, 28, // Skip to: 40641 -/* 33319 */ MCD_OPC_Decode, 163, 3, 249, 1, // Opcode: FCVTMSUWSr -/* 33324 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 33337 -/* 33328 */ MCD_OPC_CheckPredicate, 3, 141, 28, // Skip to: 40641 -/* 33332 */ MCD_OPC_Decode, 172, 3, 249, 1, // Opcode: FCVTMUUWSr -/* 33337 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 33350 -/* 33341 */ MCD_OPC_CheckPredicate, 3, 128, 28, // Skip to: 40641 -/* 33345 */ MCD_OPC_Decode, 230, 3, 249, 1, // Opcode: FCVTZSUWSr -/* 33350 */ MCD_OPC_FilterValue, 25, 119, 28, // Skip to: 40641 -/* 33354 */ MCD_OPC_CheckPredicate, 3, 115, 28, // Skip to: 40641 -/* 33358 */ MCD_OPC_Decode, 131, 4, 249, 1, // Opcode: FCVTZUUWSr -/* 33363 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 33422 -/* 33367 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 33370 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33383 -/* 33374 */ MCD_OPC_CheckPredicate, 3, 95, 28, // Skip to: 40641 -/* 33378 */ MCD_OPC_Decode, 133, 3, 251, 1, // Opcode: FCMPSrr -/* 33383 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33396 -/* 33387 */ MCD_OPC_CheckPredicate, 3, 82, 28, // Skip to: 40641 -/* 33391 */ MCD_OPC_Decode, 132, 3, 252, 1, // Opcode: FCMPSri -/* 33396 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33409 -/* 33400 */ MCD_OPC_CheckPredicate, 3, 69, 28, // Skip to: 40641 -/* 33404 */ MCD_OPC_Decode, 131, 3, 251, 1, // Opcode: FCMPESrr -/* 33409 */ MCD_OPC_FilterValue, 24, 60, 28, // Skip to: 40641 -/* 33413 */ MCD_OPC_CheckPredicate, 3, 56, 28, // Skip to: 40641 -/* 33417 */ MCD_OPC_Decode, 130, 3, 252, 1, // Opcode: FCMPESri -/* 33422 */ MCD_OPC_FilterValue, 2, 81, 0, // Skip to: 33507 -/* 33426 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 33429 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33442 -/* 33433 */ MCD_OPC_CheckPredicate, 3, 36, 28, // Skip to: 40641 -/* 33437 */ MCD_OPC_Decode, 228, 4, 253, 1, // Opcode: FMOVSr -/* 33442 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33455 -/* 33446 */ MCD_OPC_CheckPredicate, 3, 23, 28, // Skip to: 40641 -/* 33450 */ MCD_OPC_Decode, 130, 5, 253, 1, // Opcode: FNEGSr -/* 33455 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33468 -/* 33459 */ MCD_OPC_CheckPredicate, 3, 10, 28, // Skip to: 40641 -/* 33463 */ MCD_OPC_Decode, 168, 5, 253, 1, // Opcode: FRINTNSr -/* 33468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33481 -/* 33472 */ MCD_OPC_CheckPredicate, 3, 253, 27, // Skip to: 40641 -/* 33476 */ MCD_OPC_Decode, 163, 5, 253, 1, // Opcode: FRINTMSr -/* 33481 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33494 -/* 33485 */ MCD_OPC_CheckPredicate, 3, 240, 27, // Skip to: 40641 -/* 33489 */ MCD_OPC_Decode, 153, 5, 253, 1, // Opcode: FRINTASr -/* 33494 */ MCD_OPC_FilterValue, 7, 231, 27, // Skip to: 40641 -/* 33498 */ MCD_OPC_CheckPredicate, 3, 227, 27, // Skip to: 40641 -/* 33502 */ MCD_OPC_Decode, 178, 5, 253, 1, // Opcode: FRINTXSr -/* 33507 */ MCD_OPC_FilterValue, 6, 218, 27, // Skip to: 40641 -/* 33511 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 33514 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33527 -/* 33518 */ MCD_OPC_CheckPredicate, 3, 207, 27, // Skip to: 40641 -/* 33522 */ MCD_OPC_Decode, 186, 2, 253, 1, // Opcode: FABSSr -/* 33527 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33540 -/* 33531 */ MCD_OPC_CheckPredicate, 3, 194, 27, // Skip to: 40641 -/* 33535 */ MCD_OPC_Decode, 198, 5, 253, 1, // Opcode: FSQRTSr -/* 33540 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33553 -/* 33544 */ MCD_OPC_CheckPredicate, 3, 181, 27, // Skip to: 40641 -/* 33548 */ MCD_OPC_Decode, 155, 3, 254, 1, // Opcode: FCVTDSr -/* 33553 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33566 -/* 33557 */ MCD_OPC_CheckPredicate, 3, 168, 27, // Skip to: 40641 -/* 33561 */ MCD_OPC_Decode, 157, 3, 255, 1, // Opcode: FCVTHSr -/* 33566 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33579 -/* 33570 */ MCD_OPC_CheckPredicate, 3, 155, 27, // Skip to: 40641 -/* 33574 */ MCD_OPC_Decode, 173, 5, 253, 1, // Opcode: FRINTPSr -/* 33579 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33592 -/* 33583 */ MCD_OPC_CheckPredicate, 3, 142, 27, // Skip to: 40641 -/* 33587 */ MCD_OPC_Decode, 183, 5, 253, 1, // Opcode: FRINTZSr -/* 33592 */ MCD_OPC_FilterValue, 7, 133, 27, // Skip to: 40641 -/* 33596 */ MCD_OPC_CheckPredicate, 3, 129, 27, // Skip to: 40641 -/* 33600 */ MCD_OPC_Decode, 158, 5, 253, 1, // Opcode: FRINTISr -/* 33605 */ MCD_OPC_FilterValue, 1, 120, 27, // Skip to: 40641 -/* 33609 */ MCD_OPC_CheckPredicate, 3, 116, 27, // Skip to: 40641 -/* 33613 */ MCD_OPC_CheckField, 5, 5, 0, 110, 27, // Skip to: 40641 -/* 33619 */ MCD_OPC_Decode, 227, 4, 128, 2, // Opcode: FMOVSi -/* 33624 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 33657 -/* 33628 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 33631 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33644 -/* 33635 */ MCD_OPC_CheckPredicate, 3, 90, 27, // Skip to: 40641 -/* 33639 */ MCD_OPC_Decode, 213, 2, 129, 2, // Opcode: FCCMPSrr -/* 33644 */ MCD_OPC_FilterValue, 1, 81, 27, // Skip to: 40641 -/* 33648 */ MCD_OPC_CheckPredicate, 3, 77, 27, // Skip to: 40641 -/* 33652 */ MCD_OPC_Decode, 212, 2, 129, 2, // Opcode: FCCMPESrr -/* 33657 */ MCD_OPC_FilterValue, 2, 120, 0, // Skip to: 33781 -/* 33661 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 33664 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33677 -/* 33668 */ MCD_OPC_CheckPredicate, 3, 57, 27, // Skip to: 40641 -/* 33672 */ MCD_OPC_Decode, 238, 4, 130, 2, // Opcode: FMULSrr -/* 33677 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33690 -/* 33681 */ MCD_OPC_CheckPredicate, 3, 44, 27, // Skip to: 40641 -/* 33685 */ MCD_OPC_Decode, 156, 4, 130, 2, // Opcode: FDIVSrr -/* 33690 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 33703 -/* 33694 */ MCD_OPC_CheckPredicate, 3, 31, 27, // Skip to: 40641 -/* 33698 */ MCD_OPC_Decode, 206, 2, 130, 2, // Opcode: FADDSrr -/* 33703 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 33716 -/* 33707 */ MCD_OPC_CheckPredicate, 3, 18, 27, // Skip to: 40641 -/* 33711 */ MCD_OPC_Decode, 203, 5, 130, 2, // Opcode: FSUBSrr -/* 33716 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33729 -/* 33720 */ MCD_OPC_CheckPredicate, 3, 5, 27, // Skip to: 40641 -/* 33724 */ MCD_OPC_Decode, 179, 4, 130, 2, // Opcode: FMAXSrr -/* 33729 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33742 -/* 33733 */ MCD_OPC_CheckPredicate, 3, 248, 26, // Skip to: 40641 -/* 33737 */ MCD_OPC_Decode, 201, 4, 130, 2, // Opcode: FMINSrr -/* 33742 */ MCD_OPC_FilterValue, 6, 9, 0, // Skip to: 33755 -/* 33746 */ MCD_OPC_CheckPredicate, 3, 235, 26, // Skip to: 40641 -/* 33750 */ MCD_OPC_Decode, 169, 4, 130, 2, // Opcode: FMAXNMSrr -/* 33755 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33768 -/* 33759 */ MCD_OPC_CheckPredicate, 3, 222, 26, // Skip to: 40641 -/* 33763 */ MCD_OPC_Decode, 191, 4, 130, 2, // Opcode: FMINNMSrr -/* 33768 */ MCD_OPC_FilterValue, 8, 213, 26, // Skip to: 40641 -/* 33772 */ MCD_OPC_CheckPredicate, 3, 209, 26, // Skip to: 40641 -/* 33776 */ MCD_OPC_Decode, 139, 5, 130, 2, // Opcode: FNMULSrr -/* 33781 */ MCD_OPC_FilterValue, 3, 200, 26, // Skip to: 40641 -/* 33785 */ MCD_OPC_CheckPredicate, 3, 196, 26, // Skip to: 40641 -/* 33789 */ MCD_OPC_Decode, 135, 3, 131, 2, // Opcode: FCSELSrrr -/* 33794 */ MCD_OPC_FilterValue, 2, 55, 0, // Skip to: 33853 -/* 33798 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... -/* 33801 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33814 -/* 33805 */ MCD_OPC_CheckPredicate, 3, 176, 26, // Skip to: 40641 -/* 33809 */ MCD_OPC_Decode, 132, 10, 132, 2, // Opcode: SCVTFSWDri -/* 33814 */ MCD_OPC_FilterValue, 7, 9, 0, // Skip to: 33827 -/* 33818 */ MCD_OPC_CheckPredicate, 3, 163, 26, // Skip to: 40641 -/* 33822 */ MCD_OPC_Decode, 162, 16, 132, 2, // Opcode: UCVTFSWDri -/* 33827 */ MCD_OPC_FilterValue, 49, 9, 0, // Skip to: 33840 -/* 33831 */ MCD_OPC_CheckPredicate, 3, 150, 26, // Skip to: 40641 -/* 33835 */ MCD_OPC_Decode, 225, 3, 133, 2, // Opcode: FCVTZSSWDri -/* 33840 */ MCD_OPC_FilterValue, 51, 141, 26, // Skip to: 40641 -/* 33844 */ MCD_OPC_CheckPredicate, 3, 137, 26, // Skip to: 40641 -/* 33848 */ MCD_OPC_Decode, 254, 3, 133, 2, // Opcode: FCVTZUSWDri -/* 33853 */ MCD_OPC_FilterValue, 3, 76, 2, // Skip to: 34445 -/* 33857 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 33860 */ MCD_OPC_FilterValue, 0, 164, 1, // Skip to: 34284 -/* 33864 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... -/* 33867 */ MCD_OPC_FilterValue, 0, 138, 1, // Skip to: 34265 -/* 33871 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... -/* 33874 */ MCD_OPC_FilterValue, 0, 157, 0, // Skip to: 34035 -/* 33878 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 33881 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 33894 -/* 33885 */ MCD_OPC_CheckPredicate, 3, 96, 26, // Skip to: 40641 -/* 33889 */ MCD_OPC_Decode, 180, 3, 134, 2, // Opcode: FCVTNSUWDr -/* 33894 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 33907 -/* 33898 */ MCD_OPC_CheckPredicate, 3, 83, 26, // Skip to: 40641 -/* 33902 */ MCD_OPC_Decode, 189, 3, 134, 2, // Opcode: FCVTNUUWDr -/* 33907 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 33919 -/* 33911 */ MCD_OPC_CheckPredicate, 3, 70, 26, // Skip to: 40641 -/* 33915 */ MCD_OPC_Decode, 136, 10, 91, // Opcode: SCVTFUWDri -/* 33919 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 33931 -/* 33923 */ MCD_OPC_CheckPredicate, 3, 58, 26, // Skip to: 40641 -/* 33927 */ MCD_OPC_Decode, 166, 16, 91, // Opcode: UCVTFUWDri -/* 33931 */ MCD_OPC_FilterValue, 4, 9, 0, // Skip to: 33944 -/* 33935 */ MCD_OPC_CheckPredicate, 3, 46, 26, // Skip to: 40641 -/* 33939 */ MCD_OPC_Decode, 136, 3, 134, 2, // Opcode: FCVTASUWDr -/* 33944 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 33957 -/* 33948 */ MCD_OPC_CheckPredicate, 3, 33, 26, // Skip to: 40641 -/* 33952 */ MCD_OPC_Decode, 145, 3, 134, 2, // Opcode: FCVTAUUWDr -/* 33957 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 33970 -/* 33961 */ MCD_OPC_CheckPredicate, 3, 20, 26, // Skip to: 40641 -/* 33965 */ MCD_OPC_Decode, 202, 3, 134, 2, // Opcode: FCVTPSUWDr -/* 33970 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 33983 -/* 33974 */ MCD_OPC_CheckPredicate, 3, 7, 26, // Skip to: 40641 -/* 33978 */ MCD_OPC_Decode, 211, 3, 134, 2, // Opcode: FCVTPUUWDr -/* 33983 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 33996 -/* 33987 */ MCD_OPC_CheckPredicate, 3, 250, 25, // Skip to: 40641 -/* 33991 */ MCD_OPC_Decode, 162, 3, 134, 2, // Opcode: FCVTMSUWDr -/* 33996 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 34009 -/* 34000 */ MCD_OPC_CheckPredicate, 3, 237, 25, // Skip to: 40641 -/* 34004 */ MCD_OPC_Decode, 171, 3, 134, 2, // Opcode: FCVTMUUWDr -/* 34009 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 34022 -/* 34013 */ MCD_OPC_CheckPredicate, 3, 224, 25, // Skip to: 40641 -/* 34017 */ MCD_OPC_Decode, 229, 3, 134, 2, // Opcode: FCVTZSUWDr -/* 34022 */ MCD_OPC_FilterValue, 25, 215, 25, // Skip to: 40641 -/* 34026 */ MCD_OPC_CheckPredicate, 3, 211, 25, // Skip to: 40641 -/* 34030 */ MCD_OPC_Decode, 130, 4, 134, 2, // Opcode: FCVTZUUWDr -/* 34035 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 34094 -/* 34039 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... -/* 34042 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34055 -/* 34046 */ MCD_OPC_CheckPredicate, 3, 191, 25, // Skip to: 40641 -/* 34050 */ MCD_OPC_Decode, 255, 2, 135, 2, // Opcode: FCMPDrr -/* 34055 */ MCD_OPC_FilterValue, 8, 9, 0, // Skip to: 34068 -/* 34059 */ MCD_OPC_CheckPredicate, 3, 178, 25, // Skip to: 40641 -/* 34063 */ MCD_OPC_Decode, 254, 2, 136, 2, // Opcode: FCMPDri -/* 34068 */ MCD_OPC_FilterValue, 16, 9, 0, // Skip to: 34081 -/* 34072 */ MCD_OPC_CheckPredicate, 3, 165, 25, // Skip to: 40641 -/* 34076 */ MCD_OPC_Decode, 129, 3, 135, 2, // Opcode: FCMPEDrr -/* 34081 */ MCD_OPC_FilterValue, 24, 156, 25, // Skip to: 40641 -/* 34085 */ MCD_OPC_CheckPredicate, 3, 152, 25, // Skip to: 40641 -/* 34089 */ MCD_OPC_Decode, 128, 3, 136, 2, // Opcode: FCMPEDri -/* 34094 */ MCD_OPC_FilterValue, 2, 88, 0, // Skip to: 34186 -/* 34098 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 34101 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34113 -/* 34105 */ MCD_OPC_CheckPredicate, 3, 132, 25, // Skip to: 40641 -/* 34109 */ MCD_OPC_Decode, 225, 4, 90, // Opcode: FMOVDr -/* 34113 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34125 -/* 34117 */ MCD_OPC_CheckPredicate, 3, 120, 25, // Skip to: 40641 -/* 34121 */ MCD_OPC_Decode, 129, 5, 90, // Opcode: FNEGDr -/* 34125 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 34138 -/* 34129 */ MCD_OPC_CheckPredicate, 3, 108, 25, // Skip to: 40641 -/* 34133 */ MCD_OPC_Decode, 220, 3, 144, 1, // Opcode: FCVTSDr -/* 34138 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34150 -/* 34142 */ MCD_OPC_CheckPredicate, 3, 95, 25, // Skip to: 40641 -/* 34146 */ MCD_OPC_Decode, 167, 5, 90, // Opcode: FRINTNDr -/* 34150 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34162 -/* 34154 */ MCD_OPC_CheckPredicate, 3, 83, 25, // Skip to: 40641 -/* 34158 */ MCD_OPC_Decode, 162, 5, 90, // Opcode: FRINTMDr -/* 34162 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 34174 -/* 34166 */ MCD_OPC_CheckPredicate, 3, 71, 25, // Skip to: 40641 -/* 34170 */ MCD_OPC_Decode, 152, 5, 90, // Opcode: FRINTADr -/* 34174 */ MCD_OPC_FilterValue, 7, 63, 25, // Skip to: 40641 -/* 34178 */ MCD_OPC_CheckPredicate, 3, 59, 25, // Skip to: 40641 -/* 34182 */ MCD_OPC_Decode, 177, 5, 90, // Opcode: FRINTXDr -/* 34186 */ MCD_OPC_FilterValue, 6, 51, 25, // Skip to: 40641 -/* 34190 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... -/* 34193 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34205 -/* 34197 */ MCD_OPC_CheckPredicate, 3, 40, 25, // Skip to: 40641 -/* 34201 */ MCD_OPC_Decode, 185, 2, 90, // Opcode: FABSDr -/* 34205 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34217 -/* 34209 */ MCD_OPC_CheckPredicate, 3, 28, 25, // Skip to: 40641 -/* 34213 */ MCD_OPC_Decode, 197, 5, 90, // Opcode: FSQRTDr -/* 34217 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 34229 -/* 34221 */ MCD_OPC_CheckPredicate, 3, 16, 25, // Skip to: 40641 -/* 34225 */ MCD_OPC_Decode, 156, 3, 100, // Opcode: FCVTHDr -/* 34229 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34241 -/* 34233 */ MCD_OPC_CheckPredicate, 3, 4, 25, // Skip to: 40641 -/* 34237 */ MCD_OPC_Decode, 172, 5, 90, // Opcode: FRINTPDr -/* 34241 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34253 -/* 34245 */ MCD_OPC_CheckPredicate, 3, 248, 24, // Skip to: 40641 -/* 34249 */ MCD_OPC_Decode, 182, 5, 90, // Opcode: FRINTZDr -/* 34253 */ MCD_OPC_FilterValue, 7, 240, 24, // Skip to: 40641 -/* 34257 */ MCD_OPC_CheckPredicate, 3, 236, 24, // Skip to: 40641 -/* 34261 */ MCD_OPC_Decode, 157, 5, 90, // Opcode: FRINTIDr -/* 34265 */ MCD_OPC_FilterValue, 1, 228, 24, // Skip to: 40641 -/* 34269 */ MCD_OPC_CheckPredicate, 3, 224, 24, // Skip to: 40641 -/* 34273 */ MCD_OPC_CheckField, 5, 5, 0, 218, 24, // Skip to: 40641 -/* 34279 */ MCD_OPC_Decode, 224, 4, 137, 2, // Opcode: FMOVDi -/* 34284 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 34317 -/* 34288 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... -/* 34291 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34304 -/* 34295 */ MCD_OPC_CheckPredicate, 3, 198, 24, // Skip to: 40641 -/* 34299 */ MCD_OPC_Decode, 210, 2, 138, 2, // Opcode: FCCMPDrr -/* 34304 */ MCD_OPC_FilterValue, 1, 189, 24, // Skip to: 40641 -/* 34308 */ MCD_OPC_CheckPredicate, 3, 185, 24, // Skip to: 40641 -/* 34312 */ MCD_OPC_Decode, 211, 2, 138, 2, // Opcode: FCCMPEDrr -/* 34317 */ MCD_OPC_FilterValue, 2, 111, 0, // Skip to: 34432 -/* 34321 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 34324 */ MCD_OPC_FilterValue, 0, 8, 0, // Skip to: 34336 -/* 34328 */ MCD_OPC_CheckPredicate, 3, 165, 24, // Skip to: 40641 -/* 34332 */ MCD_OPC_Decode, 237, 4, 89, // Opcode: FMULDrr -/* 34336 */ MCD_OPC_FilterValue, 1, 8, 0, // Skip to: 34348 -/* 34340 */ MCD_OPC_CheckPredicate, 3, 153, 24, // Skip to: 40641 -/* 34344 */ MCD_OPC_Decode, 155, 4, 89, // Opcode: FDIVDrr -/* 34348 */ MCD_OPC_FilterValue, 2, 8, 0, // Skip to: 34360 -/* 34352 */ MCD_OPC_CheckPredicate, 3, 141, 24, // Skip to: 40641 -/* 34356 */ MCD_OPC_Decode, 200, 2, 89, // Opcode: FADDDrr -/* 34360 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 34372 -/* 34364 */ MCD_OPC_CheckPredicate, 3, 129, 24, // Skip to: 40641 -/* 34368 */ MCD_OPC_Decode, 202, 5, 89, // Opcode: FSUBDrr -/* 34372 */ MCD_OPC_FilterValue, 4, 8, 0, // Skip to: 34384 -/* 34376 */ MCD_OPC_CheckPredicate, 3, 117, 24, // Skip to: 40641 -/* 34380 */ MCD_OPC_Decode, 162, 4, 89, // Opcode: FMAXDrr -/* 34384 */ MCD_OPC_FilterValue, 5, 8, 0, // Skip to: 34396 -/* 34388 */ MCD_OPC_CheckPredicate, 3, 105, 24, // Skip to: 40641 -/* 34392 */ MCD_OPC_Decode, 184, 4, 89, // Opcode: FMINDrr -/* 34396 */ MCD_OPC_FilterValue, 6, 8, 0, // Skip to: 34408 -/* 34400 */ MCD_OPC_CheckPredicate, 3, 93, 24, // Skip to: 40641 -/* 34404 */ MCD_OPC_Decode, 163, 4, 89, // Opcode: FMAXNMDrr -/* 34408 */ MCD_OPC_FilterValue, 7, 8, 0, // Skip to: 34420 -/* 34412 */ MCD_OPC_CheckPredicate, 3, 81, 24, // Skip to: 40641 -/* 34416 */ MCD_OPC_Decode, 185, 4, 89, // Opcode: FMINNMDrr -/* 34420 */ MCD_OPC_FilterValue, 8, 73, 24, // Skip to: 40641 -/* 34424 */ MCD_OPC_CheckPredicate, 3, 69, 24, // Skip to: 40641 -/* 34428 */ MCD_OPC_Decode, 138, 5, 89, // Opcode: FNMULDrr -/* 34432 */ MCD_OPC_FilterValue, 3, 61, 24, // Skip to: 40641 -/* 34436 */ MCD_OPC_CheckPredicate, 3, 57, 24, // Skip to: 40641 -/* 34440 */ MCD_OPC_Decode, 134, 3, 139, 2, // Opcode: FCSELDrrr -/* 34445 */ MCD_OPC_FilterValue, 7, 48, 24, // Skip to: 40641 -/* 34449 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... -/* 34452 */ MCD_OPC_FilterValue, 144, 1, 9, 0, // Skip to: 34466 -/* 34457 */ MCD_OPC_CheckPredicate, 3, 36, 24, // Skip to: 40641 -/* 34461 */ MCD_OPC_Decode, 221, 3, 140, 2, // Opcode: FCVTSHr -/* 34466 */ MCD_OPC_FilterValue, 176, 1, 26, 24, // Skip to: 40641 -/* 34471 */ MCD_OPC_CheckPredicate, 3, 22, 24, // Skip to: 40641 -/* 34475 */ MCD_OPC_Decode, 154, 3, 141, 2, // Opcode: FCVTDHr -/* 34480 */ MCD_OPC_FilterValue, 3, 13, 24, // Skip to: 40641 -/* 34484 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 34487 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 34520 -/* 34491 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 34494 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34507 -/* 34498 */ MCD_OPC_CheckPredicate, 3, 251, 23, // Skip to: 40641 -/* 34502 */ MCD_OPC_Decode, 161, 4, 142, 2, // Opcode: FMADDSrrr -/* 34507 */ MCD_OPC_FilterValue, 1, 242, 23, // Skip to: 40641 -/* 34511 */ MCD_OPC_CheckPredicate, 3, 238, 23, // Skip to: 40641 -/* 34515 */ MCD_OPC_Decode, 236, 4, 142, 2, // Opcode: FMSUBSrrr -/* 34520 */ MCD_OPC_FilterValue, 1, 29, 0, // Skip to: 34553 -/* 34524 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 34527 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34540 -/* 34531 */ MCD_OPC_CheckPredicate, 3, 218, 23, // Skip to: 40641 -/* 34535 */ MCD_OPC_Decode, 135, 5, 142, 2, // Opcode: FNMADDSrrr -/* 34540 */ MCD_OPC_FilterValue, 1, 209, 23, // Skip to: 40641 -/* 34544 */ MCD_OPC_CheckPredicate, 3, 205, 23, // Skip to: 40641 -/* 34548 */ MCD_OPC_Decode, 137, 5, 142, 2, // Opcode: FNMSUBSrrr -/* 34553 */ MCD_OPC_FilterValue, 2, 29, 0, // Skip to: 34586 -/* 34557 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 34560 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34573 -/* 34564 */ MCD_OPC_CheckPredicate, 3, 185, 23, // Skip to: 40641 -/* 34568 */ MCD_OPC_Decode, 160, 4, 143, 2, // Opcode: FMADDDrrr -/* 34573 */ MCD_OPC_FilterValue, 1, 176, 23, // Skip to: 40641 -/* 34577 */ MCD_OPC_CheckPredicate, 3, 172, 23, // Skip to: 40641 -/* 34581 */ MCD_OPC_Decode, 235, 4, 143, 2, // Opcode: FMSUBDrrr -/* 34586 */ MCD_OPC_FilterValue, 3, 163, 23, // Skip to: 40641 -/* 34590 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... -/* 34593 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 34606 -/* 34597 */ MCD_OPC_CheckPredicate, 3, 152, 23, // Skip to: 40641 -/* 34601 */ MCD_OPC_Decode, 134, 5, 143, 2, // Opcode: FNMADDDrrr -/* 34606 */ MCD_OPC_FilterValue, 1, 143, 23, // Skip to: 40641 -/* 34610 */ MCD_OPC_CheckPredicate, 3, 139, 23, // Skip to: 40641 -/* 34614 */ MCD_OPC_Decode, 136, 5, 143, 2, // Opcode: FNMSUBDrrr -/* 34619 */ MCD_OPC_FilterValue, 1, 139, 1, // Skip to: 35018 -/* 34623 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 34626 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 34715 -/* 34630 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 34633 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34648 -/* 34637 */ MCD_OPC_CheckField, 21, 1, 0, 110, 23, // Skip to: 40641 -/* 34643 */ MCD_OPC_Decode, 137, 15, 226, 1, // Opcode: STURBi -/* 34648 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34663 -/* 34652 */ MCD_OPC_CheckField, 21, 1, 0, 95, 23, // Skip to: 40641 -/* 34658 */ MCD_OPC_Decode, 220, 14, 226, 1, // Opcode: STRBpost -/* 34663 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34700 -/* 34667 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 34670 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34685 -/* 34674 */ MCD_OPC_CheckField, 21, 1, 1, 73, 23, // Skip to: 40641 -/* 34680 */ MCD_OPC_Decode, 222, 14, 144, 2, // Opcode: STRBroW -/* 34685 */ MCD_OPC_FilterValue, 3, 64, 23, // Skip to: 40641 -/* 34689 */ MCD_OPC_CheckField, 21, 1, 1, 58, 23, // Skip to: 40641 -/* 34695 */ MCD_OPC_Decode, 223, 14, 145, 2, // Opcode: STRBroX -/* 34700 */ MCD_OPC_FilterValue, 3, 49, 23, // Skip to: 40641 -/* 34704 */ MCD_OPC_CheckField, 21, 1, 0, 43, 23, // Skip to: 40641 -/* 34710 */ MCD_OPC_Decode, 221, 14, 226, 1, // Opcode: STRBpre -/* 34715 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 34804 -/* 34719 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 34722 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34737 -/* 34726 */ MCD_OPC_CheckField, 21, 1, 0, 21, 23, // Skip to: 40641 -/* 34732 */ MCD_OPC_Decode, 156, 8, 226, 1, // Opcode: LDURBi -/* 34737 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34752 -/* 34741 */ MCD_OPC_CheckField, 21, 1, 0, 6, 23, // Skip to: 40641 -/* 34747 */ MCD_OPC_Decode, 203, 7, 226, 1, // Opcode: LDRBpost -/* 34752 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34789 -/* 34756 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 34759 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34774 -/* 34763 */ MCD_OPC_CheckField, 21, 1, 1, 240, 22, // Skip to: 40641 -/* 34769 */ MCD_OPC_Decode, 205, 7, 144, 2, // Opcode: LDRBroW -/* 34774 */ MCD_OPC_FilterValue, 3, 231, 22, // Skip to: 40641 -/* 34778 */ MCD_OPC_CheckField, 21, 1, 1, 225, 22, // Skip to: 40641 -/* 34784 */ MCD_OPC_Decode, 206, 7, 145, 2, // Opcode: LDRBroX -/* 34789 */ MCD_OPC_FilterValue, 3, 216, 22, // Skip to: 40641 -/* 34793 */ MCD_OPC_CheckField, 21, 1, 0, 210, 22, // Skip to: 40641 -/* 34799 */ MCD_OPC_Decode, 204, 7, 226, 1, // Opcode: LDRBpre -/* 34804 */ MCD_OPC_FilterValue, 2, 85, 0, // Skip to: 34893 -/* 34808 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 34811 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34826 -/* 34815 */ MCD_OPC_CheckField, 21, 1, 0, 188, 22, // Skip to: 40641 -/* 34821 */ MCD_OPC_Decode, 141, 15, 226, 1, // Opcode: STURQi -/* 34826 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34841 -/* 34830 */ MCD_OPC_CheckField, 21, 1, 0, 173, 22, // Skip to: 40641 -/* 34836 */ MCD_OPC_Decode, 240, 14, 226, 1, // Opcode: STRQpost -/* 34841 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34878 -/* 34845 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 34848 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34863 -/* 34852 */ MCD_OPC_CheckField, 21, 1, 1, 151, 22, // Skip to: 40641 -/* 34858 */ MCD_OPC_Decode, 242, 14, 146, 2, // Opcode: STRQroW -/* 34863 */ MCD_OPC_FilterValue, 3, 142, 22, // Skip to: 40641 -/* 34867 */ MCD_OPC_CheckField, 21, 1, 1, 136, 22, // Skip to: 40641 -/* 34873 */ MCD_OPC_Decode, 243, 14, 147, 2, // Opcode: STRQroX -/* 34878 */ MCD_OPC_FilterValue, 3, 127, 22, // Skip to: 40641 -/* 34882 */ MCD_OPC_CheckField, 21, 1, 0, 121, 22, // Skip to: 40641 -/* 34888 */ MCD_OPC_Decode, 241, 14, 226, 1, // Opcode: STRQpre -/* 34893 */ MCD_OPC_FilterValue, 3, 85, 0, // Skip to: 34982 -/* 34897 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 34900 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 34915 -/* 34904 */ MCD_OPC_CheckField, 21, 1, 0, 99, 22, // Skip to: 40641 -/* 34910 */ MCD_OPC_Decode, 160, 8, 226, 1, // Opcode: LDURQi -/* 34915 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 34930 -/* 34919 */ MCD_OPC_CheckField, 21, 1, 0, 84, 22, // Skip to: 40641 -/* 34925 */ MCD_OPC_Decode, 225, 7, 226, 1, // Opcode: LDRQpost -/* 34930 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 34967 -/* 34934 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 34937 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 34952 -/* 34941 */ MCD_OPC_CheckField, 21, 1, 1, 62, 22, // Skip to: 40641 -/* 34947 */ MCD_OPC_Decode, 227, 7, 146, 2, // Opcode: LDRQroW -/* 34952 */ MCD_OPC_FilterValue, 3, 53, 22, // Skip to: 40641 -/* 34956 */ MCD_OPC_CheckField, 21, 1, 1, 47, 22, // Skip to: 40641 -/* 34962 */ MCD_OPC_Decode, 228, 7, 147, 2, // Opcode: LDRQroX -/* 34967 */ MCD_OPC_FilterValue, 3, 38, 22, // Skip to: 40641 -/* 34971 */ MCD_OPC_CheckField, 21, 1, 0, 32, 22, // Skip to: 40641 -/* 34977 */ MCD_OPC_Decode, 226, 7, 226, 1, // Opcode: LDRQpre -/* 34982 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 34991 -/* 34986 */ MCD_OPC_Decode, 224, 14, 231, 1, // Opcode: STRBui -/* 34991 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 35000 -/* 34995 */ MCD_OPC_Decode, 207, 7, 231, 1, // Opcode: LDRBui -/* 35000 */ MCD_OPC_FilterValue, 6, 5, 0, // Skip to: 35009 -/* 35004 */ MCD_OPC_Decode, 244, 14, 231, 1, // Opcode: STRQui -/* 35009 */ MCD_OPC_FilterValue, 7, 252, 21, // Skip to: 40641 -/* 35013 */ MCD_OPC_Decode, 229, 7, 231, 1, // Opcode: LDRQui -/* 35018 */ MCD_OPC_FilterValue, 2, 240, 8, // Skip to: 37310 -/* 35022 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 35025 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 35034 -/* 35029 */ MCD_OPC_Decode, 208, 7, 148, 2, // Opcode: LDRDl -/* 35034 */ MCD_OPC_FilterValue, 2, 175, 5, // Skip to: 36493 -/* 35038 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 35041 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 35060 -/* 35045 */ MCD_OPC_CheckPredicate, 1, 216, 21, // Skip to: 40641 -/* 35049 */ MCD_OPC_CheckField, 21, 3, 0, 210, 21, // Skip to: 40641 -/* 35055 */ MCD_OPC_Decode, 154, 10, 149, 2, // Opcode: SHA1Crrr -/* 35060 */ MCD_OPC_FilterValue, 1, 99, 0, // Skip to: 35163 -/* 35064 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... -/* 35067 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 35144 -/* 35071 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... -/* 35074 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 35125 -/* 35078 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... -/* 35081 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 35106 -/* 35085 */ MCD_OPC_CheckPredicate, 0, 176, 21, // Skip to: 40641 -/* 35089 */ MCD_OPC_CheckField, 21, 3, 0, 170, 21, // Skip to: 40641 -/* 35095 */ MCD_OPC_CheckField, 19, 1, 1, 164, 21, // Skip to: 40641 -/* 35101 */ MCD_OPC_Decode, 252, 1, 150, 2, // Opcode: CPYi64 -/* 35106 */ MCD_OPC_FilterValue, 1, 155, 21, // Skip to: 40641 -/* 35110 */ MCD_OPC_CheckPredicate, 0, 151, 21, // Skip to: 40641 -/* 35114 */ MCD_OPC_CheckField, 21, 3, 0, 145, 21, // Skip to: 40641 -/* 35120 */ MCD_OPC_Decode, 251, 1, 151, 2, // Opcode: CPYi32 -/* 35125 */ MCD_OPC_FilterValue, 1, 136, 21, // Skip to: 40641 -/* 35129 */ MCD_OPC_CheckPredicate, 0, 132, 21, // Skip to: 40641 -/* 35133 */ MCD_OPC_CheckField, 21, 3, 0, 126, 21, // Skip to: 40641 -/* 35139 */ MCD_OPC_Decode, 250, 1, 152, 2, // Opcode: CPYi16 -/* 35144 */ MCD_OPC_FilterValue, 1, 117, 21, // Skip to: 40641 -/* 35148 */ MCD_OPC_CheckPredicate, 0, 113, 21, // Skip to: 40641 -/* 35152 */ MCD_OPC_CheckField, 21, 3, 0, 107, 21, // Skip to: 40641 -/* 35158 */ MCD_OPC_Decode, 253, 1, 153, 2, // Opcode: CPYi8 -/* 35163 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 35182 -/* 35167 */ MCD_OPC_CheckPredicate, 1, 94, 21, // Skip to: 40641 -/* 35171 */ MCD_OPC_CheckField, 16, 8, 40, 88, 21, // Skip to: 40641 -/* 35177 */ MCD_OPC_Decode, 155, 10, 253, 1, // Opcode: SHA1Hrr -/* 35182 */ MCD_OPC_FilterValue, 3, 54, 0, // Skip to: 35240 -/* 35186 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 35189 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35202 -/* 35193 */ MCD_OPC_CheckPredicate, 0, 68, 21, // Skip to: 40641 -/* 35197 */ MCD_OPC_Decode, 164, 11, 154, 2, // Opcode: SQADDv1i8 -/* 35202 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35215 -/* 35206 */ MCD_OPC_CheckPredicate, 0, 55, 21, // Skip to: 40641 -/* 35210 */ MCD_OPC_Decode, 161, 11, 155, 2, // Opcode: SQADDv1i16 -/* 35215 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35228 -/* 35219 */ MCD_OPC_CheckPredicate, 0, 42, 21, // Skip to: 40641 -/* 35223 */ MCD_OPC_Decode, 162, 11, 130, 2, // Opcode: SQADDv1i32 -/* 35228 */ MCD_OPC_FilterValue, 7, 33, 21, // Skip to: 40641 -/* 35232 */ MCD_OPC_CheckPredicate, 0, 29, 21, // Skip to: 40641 -/* 35236 */ MCD_OPC_Decode, 163, 11, 89, // Opcode: SQADDv1i64 -/* 35240 */ MCD_OPC_FilterValue, 4, 15, 0, // Skip to: 35259 -/* 35244 */ MCD_OPC_CheckPredicate, 1, 17, 21, // Skip to: 40641 -/* 35248 */ MCD_OPC_CheckField, 21, 3, 0, 11, 21, // Skip to: 40641 -/* 35254 */ MCD_OPC_Decode, 157, 10, 149, 2, // Opcode: SHA1Prrr -/* 35259 */ MCD_OPC_FilterValue, 6, 14, 0, // Skip to: 35277 -/* 35263 */ MCD_OPC_CheckPredicate, 1, 254, 20, // Skip to: 40641 -/* 35267 */ MCD_OPC_CheckField, 16, 8, 40, 248, 20, // Skip to: 40641 -/* 35273 */ MCD_OPC_Decode, 159, 10, 126, // Opcode: SHA1SU1rr -/* 35277 */ MCD_OPC_FilterValue, 8, 15, 0, // Skip to: 35296 -/* 35281 */ MCD_OPC_CheckPredicate, 1, 236, 20, // Skip to: 40641 -/* 35285 */ MCD_OPC_CheckField, 21, 3, 0, 230, 20, // Skip to: 40641 -/* 35291 */ MCD_OPC_Decode, 156, 10, 149, 2, // Opcode: SHA1Mrrr -/* 35296 */ MCD_OPC_FilterValue, 10, 14, 0, // Skip to: 35314 -/* 35300 */ MCD_OPC_CheckPredicate, 1, 217, 20, // Skip to: 40641 -/* 35304 */ MCD_OPC_CheckField, 16, 8, 40, 211, 20, // Skip to: 40641 -/* 35310 */ MCD_OPC_Decode, 162, 10, 126, // Opcode: SHA256SU0rr -/* 35314 */ MCD_OPC_FilterValue, 11, 54, 0, // Skip to: 35372 -/* 35318 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 35321 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35334 -/* 35325 */ MCD_OPC_CheckPredicate, 0, 192, 20, // Skip to: 40641 -/* 35329 */ MCD_OPC_Decode, 198, 12, 154, 2, // Opcode: SQSUBv1i8 -/* 35334 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35347 -/* 35338 */ MCD_OPC_CheckPredicate, 0, 179, 20, // Skip to: 40641 -/* 35342 */ MCD_OPC_Decode, 195, 12, 155, 2, // Opcode: SQSUBv1i16 -/* 35347 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35360 -/* 35351 */ MCD_OPC_CheckPredicate, 0, 166, 20, // Skip to: 40641 -/* 35355 */ MCD_OPC_Decode, 196, 12, 130, 2, // Opcode: SQSUBv1i32 -/* 35360 */ MCD_OPC_FilterValue, 7, 157, 20, // Skip to: 40641 -/* 35364 */ MCD_OPC_CheckPredicate, 0, 153, 20, // Skip to: 40641 -/* 35368 */ MCD_OPC_Decode, 197, 12, 89, // Opcode: SQSUBv1i64 -/* 35372 */ MCD_OPC_FilterValue, 12, 14, 0, // Skip to: 35390 -/* 35376 */ MCD_OPC_CheckPredicate, 1, 141, 20, // Skip to: 40641 -/* 35380 */ MCD_OPC_CheckField, 21, 3, 0, 135, 20, // Skip to: 40641 -/* 35386 */ MCD_OPC_Decode, 158, 10, 120, // Opcode: SHA1SU0rrr -/* 35390 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 35408 -/* 35394 */ MCD_OPC_CheckPredicate, 0, 123, 20, // Skip to: 40641 -/* 35398 */ MCD_OPC_CheckField, 21, 3, 7, 117, 20, // Skip to: 40641 -/* 35404 */ MCD_OPC_Decode, 194, 1, 89, // Opcode: CMGTv1i64 -/* 35408 */ MCD_OPC_FilterValue, 14, 56, 0, // Skip to: 35468 -/* 35412 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 35415 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 35428 -/* 35419 */ MCD_OPC_CheckPredicate, 0, 98, 20, // Skip to: 40641 -/* 35423 */ MCD_OPC_Decode, 187, 15, 156, 2, // Opcode: SUQADDv1i8 -/* 35428 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 35441 -/* 35432 */ MCD_OPC_CheckPredicate, 0, 85, 20, // Skip to: 40641 -/* 35436 */ MCD_OPC_Decode, 184, 15, 157, 2, // Opcode: SUQADDv1i16 -/* 35441 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 35455 -/* 35446 */ MCD_OPC_CheckPredicate, 0, 71, 20, // Skip to: 40641 -/* 35450 */ MCD_OPC_Decode, 185, 15, 158, 2, // Opcode: SUQADDv1i32 -/* 35455 */ MCD_OPC_FilterValue, 224, 1, 61, 20, // Skip to: 40641 -/* 35460 */ MCD_OPC_CheckPredicate, 0, 57, 20, // Skip to: 40641 -/* 35464 */ MCD_OPC_Decode, 186, 15, 99, // Opcode: SUQADDv1i64 -/* 35468 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 35486 -/* 35472 */ MCD_OPC_CheckPredicate, 0, 45, 20, // Skip to: 40641 -/* 35476 */ MCD_OPC_CheckField, 21, 3, 7, 39, 20, // Skip to: 40641 -/* 35482 */ MCD_OPC_Decode, 178, 1, 89, // Opcode: CMGEv1i64 -/* 35486 */ MCD_OPC_FilterValue, 16, 14, 0, // Skip to: 35504 -/* 35490 */ MCD_OPC_CheckPredicate, 1, 27, 20, // Skip to: 40641 -/* 35494 */ MCD_OPC_CheckField, 21, 3, 0, 21, 20, // Skip to: 40641 -/* 35500 */ MCD_OPC_Decode, 161, 10, 120, // Opcode: SHA256Hrrr -/* 35504 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 35522 -/* 35508 */ MCD_OPC_CheckPredicate, 0, 9, 20, // Skip to: 40641 -/* 35512 */ MCD_OPC_CheckField, 21, 3, 7, 3, 20, // Skip to: 40641 -/* 35518 */ MCD_OPC_Decode, 140, 13, 89, // Opcode: SSHLv1i64 -/* 35522 */ MCD_OPC_FilterValue, 18, 43, 0, // Skip to: 35569 -/* 35526 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 35529 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 35542 -/* 35533 */ MCD_OPC_CheckPredicate, 0, 240, 19, // Skip to: 40641 -/* 35537 */ MCD_OPC_Decode, 208, 12, 159, 2, // Opcode: SQXTNv1i8 -/* 35542 */ MCD_OPC_FilterValue, 97, 9, 0, // Skip to: 35555 -/* 35546 */ MCD_OPC_CheckPredicate, 0, 227, 19, // Skip to: 40641 -/* 35550 */ MCD_OPC_Decode, 206, 12, 255, 1, // Opcode: SQXTNv1i16 -/* 35555 */ MCD_OPC_FilterValue, 161, 1, 217, 19, // Skip to: 40641 -/* 35560 */ MCD_OPC_CheckPredicate, 0, 213, 19, // Skip to: 40641 -/* 35564 */ MCD_OPC_Decode, 207, 12, 144, 1, // Opcode: SQXTNv1i32 -/* 35569 */ MCD_OPC_FilterValue, 19, 54, 0, // Skip to: 35627 -/* 35573 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 35576 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35589 -/* 35580 */ MCD_OPC_CheckPredicate, 0, 193, 19, // Skip to: 40641 -/* 35584 */ MCD_OPC_Decode, 163, 12, 154, 2, // Opcode: SQSHLv1i8 -/* 35589 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35602 -/* 35593 */ MCD_OPC_CheckPredicate, 0, 180, 19, // Skip to: 40641 -/* 35597 */ MCD_OPC_Decode, 160, 12, 155, 2, // Opcode: SQSHLv1i16 -/* 35602 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35615 -/* 35606 */ MCD_OPC_CheckPredicate, 0, 167, 19, // Skip to: 40641 -/* 35610 */ MCD_OPC_Decode, 161, 12, 130, 2, // Opcode: SQSHLv1i32 -/* 35615 */ MCD_OPC_FilterValue, 7, 158, 19, // Skip to: 40641 -/* 35619 */ MCD_OPC_CheckPredicate, 0, 154, 19, // Skip to: 40641 -/* 35623 */ MCD_OPC_Decode, 162, 12, 89, // Opcode: SQSHLv1i64 -/* 35627 */ MCD_OPC_FilterValue, 20, 14, 0, // Skip to: 35645 -/* 35631 */ MCD_OPC_CheckPredicate, 1, 142, 19, // Skip to: 40641 -/* 35635 */ MCD_OPC_CheckField, 21, 3, 0, 136, 19, // Skip to: 40641 -/* 35641 */ MCD_OPC_Decode, 160, 10, 120, // Opcode: SHA256H2rrr -/* 35645 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 35663 -/* 35649 */ MCD_OPC_CheckPredicate, 0, 124, 19, // Skip to: 40641 -/* 35653 */ MCD_OPC_CheckField, 21, 3, 7, 118, 19, // Skip to: 40641 -/* 35659 */ MCD_OPC_Decode, 238, 12, 89, // Opcode: SRSHLv1i64 -/* 35663 */ MCD_OPC_FilterValue, 23, 54, 0, // Skip to: 35721 -/* 35667 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 35670 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 35683 -/* 35674 */ MCD_OPC_CheckPredicate, 0, 99, 19, // Skip to: 40641 -/* 35678 */ MCD_OPC_Decode, 246, 11, 154, 2, // Opcode: SQRSHLv1i8 -/* 35683 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35696 -/* 35687 */ MCD_OPC_CheckPredicate, 0, 86, 19, // Skip to: 40641 -/* 35691 */ MCD_OPC_Decode, 243, 11, 155, 2, // Opcode: SQRSHLv1i16 -/* 35696 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 35709 -/* 35700 */ MCD_OPC_CheckPredicate, 0, 73, 19, // Skip to: 40641 -/* 35704 */ MCD_OPC_Decode, 244, 11, 130, 2, // Opcode: SQRSHLv1i32 -/* 35709 */ MCD_OPC_FilterValue, 7, 64, 19, // Skip to: 40641 -/* 35713 */ MCD_OPC_CheckPredicate, 0, 60, 19, // Skip to: 40641 -/* 35717 */ MCD_OPC_Decode, 245, 11, 89, // Opcode: SQRSHLv1i64 -/* 35721 */ MCD_OPC_FilterValue, 24, 14, 0, // Skip to: 35739 -/* 35725 */ MCD_OPC_CheckPredicate, 1, 48, 19, // Skip to: 40641 -/* 35729 */ MCD_OPC_CheckField, 21, 3, 0, 42, 19, // Skip to: 40641 -/* 35735 */ MCD_OPC_Decode, 163, 10, 120, // Opcode: SHA256SU1rrr -/* 35739 */ MCD_OPC_FilterValue, 30, 56, 0, // Skip to: 35799 -/* 35743 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 35746 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 35759 -/* 35750 */ MCD_OPC_CheckPredicate, 0, 23, 19, // Skip to: 40641 -/* 35754 */ MCD_OPC_Decode, 153, 11, 160, 2, // Opcode: SQABSv1i8 -/* 35759 */ MCD_OPC_FilterValue, 96, 9, 0, // Skip to: 35772 -/* 35763 */ MCD_OPC_CheckPredicate, 0, 10, 19, // Skip to: 40641 -/* 35767 */ MCD_OPC_Decode, 150, 11, 161, 2, // Opcode: SQABSv1i16 -/* 35772 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 35786 -/* 35777 */ MCD_OPC_CheckPredicate, 0, 252, 18, // Skip to: 40641 -/* 35781 */ MCD_OPC_Decode, 151, 11, 253, 1, // Opcode: SQABSv1i32 -/* 35786 */ MCD_OPC_FilterValue, 224, 1, 242, 18, // Skip to: 40641 -/* 35791 */ MCD_OPC_CheckPredicate, 0, 238, 18, // Skip to: 40641 -/* 35795 */ MCD_OPC_Decode, 152, 11, 90, // Opcode: SQABSv1i64 -/* 35799 */ MCD_OPC_FilterValue, 33, 13, 0, // Skip to: 35816 -/* 35803 */ MCD_OPC_CheckPredicate, 0, 226, 18, // Skip to: 40641 -/* 35807 */ MCD_OPC_CheckField, 21, 3, 7, 220, 18, // Skip to: 40641 -/* 35813 */ MCD_OPC_Decode, 72, 89, // Opcode: ADDv1i64 -/* 35816 */ MCD_OPC_FilterValue, 34, 15, 0, // Skip to: 35835 -/* 35820 */ MCD_OPC_CheckPredicate, 0, 209, 18, // Skip to: 40641 -/* 35824 */ MCD_OPC_CheckField, 16, 8, 224, 1, 202, 18, // Skip to: 40641 -/* 35831 */ MCD_OPC_Decode, 195, 1, 90, // Opcode: CMGTv1i64rz -/* 35835 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 35853 -/* 35839 */ MCD_OPC_CheckPredicate, 0, 190, 18, // Skip to: 40641 -/* 35843 */ MCD_OPC_CheckField, 21, 3, 7, 184, 18, // Skip to: 40641 -/* 35849 */ MCD_OPC_Decode, 241, 1, 89, // Opcode: CMTSTv1i64 -/* 35853 */ MCD_OPC_FilterValue, 36, 29, 0, // Skip to: 35886 -/* 35857 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 35860 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35873 -/* 35864 */ MCD_OPC_CheckPredicate, 0, 165, 18, // Skip to: 40641 -/* 35868 */ MCD_OPC_Decode, 171, 11, 162, 2, // Opcode: SQDMLALi16 -/* 35873 */ MCD_OPC_FilterValue, 5, 156, 18, // Skip to: 40641 -/* 35877 */ MCD_OPC_CheckPredicate, 0, 152, 18, // Skip to: 40641 -/* 35881 */ MCD_OPC_Decode, 172, 11, 163, 2, // Opcode: SQDMLALi32 -/* 35886 */ MCD_OPC_FilterValue, 38, 15, 0, // Skip to: 35905 -/* 35890 */ MCD_OPC_CheckPredicate, 0, 139, 18, // Skip to: 40641 -/* 35894 */ MCD_OPC_CheckField, 16, 8, 224, 1, 132, 18, // Skip to: 40641 -/* 35901 */ MCD_OPC_Decode, 163, 1, 90, // Opcode: CMEQv1i64rz -/* 35905 */ MCD_OPC_FilterValue, 42, 68, 0, // Skip to: 35977 -/* 35909 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 35912 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 35925 -/* 35916 */ MCD_OPC_CheckPredicate, 0, 113, 18, // Skip to: 40641 -/* 35920 */ MCD_OPC_Decode, 184, 3, 253, 1, // Opcode: FCVTNSv1i32 -/* 35925 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 35937 -/* 35929 */ MCD_OPC_CheckPredicate, 0, 100, 18, // Skip to: 40641 -/* 35933 */ MCD_OPC_Decode, 185, 3, 90, // Opcode: FCVTNSv1i64 -/* 35937 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 35951 -/* 35942 */ MCD_OPC_CheckPredicate, 0, 87, 18, // Skip to: 40641 -/* 35946 */ MCD_OPC_Decode, 206, 3, 253, 1, // Opcode: FCVTPSv1i32 -/* 35951 */ MCD_OPC_FilterValue, 224, 1, 8, 0, // Skip to: 35964 -/* 35956 */ MCD_OPC_CheckPredicate, 0, 73, 18, // Skip to: 40641 -/* 35960 */ MCD_OPC_Decode, 233, 1, 90, // Opcode: CMLTv1i64rz -/* 35964 */ MCD_OPC_FilterValue, 225, 1, 64, 18, // Skip to: 40641 -/* 35969 */ MCD_OPC_CheckPredicate, 0, 60, 18, // Skip to: 40641 -/* 35973 */ MCD_OPC_Decode, 207, 3, 90, // Opcode: FCVTPSv1i64 -/* 35977 */ MCD_OPC_FilterValue, 44, 29, 0, // Skip to: 36010 -/* 35981 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 35984 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 35997 -/* 35988 */ MCD_OPC_CheckPredicate, 0, 41, 18, // Skip to: 40641 -/* 35992 */ MCD_OPC_Decode, 183, 11, 162, 2, // Opcode: SQDMLSLi16 -/* 35997 */ MCD_OPC_FilterValue, 5, 32, 18, // Skip to: 40641 -/* 36001 */ MCD_OPC_CheckPredicate, 0, 28, 18, // Skip to: 40641 -/* 36005 */ MCD_OPC_Decode, 184, 11, 163, 2, // Opcode: SQDMLSLi32 -/* 36010 */ MCD_OPC_FilterValue, 45, 29, 0, // Skip to: 36043 -/* 36014 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 36017 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36030 -/* 36021 */ MCD_OPC_CheckPredicate, 0, 8, 18, // Skip to: 40641 -/* 36025 */ MCD_OPC_Decode, 195, 11, 155, 2, // Opcode: SQDMULHv1i16 -/* 36030 */ MCD_OPC_FilterValue, 5, 255, 17, // Skip to: 40641 -/* 36034 */ MCD_OPC_CheckPredicate, 0, 251, 17, // Skip to: 40641 -/* 36038 */ MCD_OPC_Decode, 197, 11, 130, 2, // Opcode: SQDMULHv1i32 -/* 36043 */ MCD_OPC_FilterValue, 46, 79, 0, // Skip to: 36126 -/* 36047 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 36050 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36063 -/* 36054 */ MCD_OPC_CheckPredicate, 0, 231, 17, // Skip to: 40641 -/* 36058 */ MCD_OPC_Decode, 166, 3, 253, 1, // Opcode: FCVTMSv1i32 -/* 36063 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36075 -/* 36067 */ MCD_OPC_CheckPredicate, 0, 218, 17, // Skip to: 40641 -/* 36071 */ MCD_OPC_Decode, 167, 3, 90, // Opcode: FCVTMSv1i64 -/* 36075 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36089 -/* 36080 */ MCD_OPC_CheckPredicate, 0, 205, 17, // Skip to: 40641 -/* 36084 */ MCD_OPC_Decode, 246, 3, 253, 1, // Opcode: FCVTZSv1i32 -/* 36089 */ MCD_OPC_FilterValue, 224, 1, 7, 0, // Skip to: 36101 -/* 36094 */ MCD_OPC_CheckPredicate, 0, 191, 17, // Skip to: 40641 -/* 36098 */ MCD_OPC_Decode, 23, 90, // Opcode: ABSv1i64 -/* 36101 */ MCD_OPC_FilterValue, 225, 1, 8, 0, // Skip to: 36114 -/* 36106 */ MCD_OPC_CheckPredicate, 0, 179, 17, // Skip to: 40641 -/* 36110 */ MCD_OPC_Decode, 247, 3, 90, // Opcode: FCVTZSv1i64 -/* 36114 */ MCD_OPC_FilterValue, 241, 1, 170, 17, // Skip to: 40641 -/* 36119 */ MCD_OPC_CheckPredicate, 0, 166, 17, // Skip to: 40641 -/* 36123 */ MCD_OPC_Decode, 43, 95, // Opcode: ADDPv2i64p -/* 36126 */ MCD_OPC_FilterValue, 50, 55, 0, // Skip to: 36185 -/* 36130 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 36133 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36146 -/* 36137 */ MCD_OPC_CheckPredicate, 0, 148, 17, // Skip to: 40641 -/* 36141 */ MCD_OPC_Decode, 140, 3, 253, 1, // Opcode: FCVTASv1i32 -/* 36146 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36158 -/* 36150 */ MCD_OPC_CheckPredicate, 0, 135, 17, // Skip to: 40641 -/* 36154 */ MCD_OPC_Decode, 141, 3, 90, // Opcode: FCVTASv1i64 -/* 36158 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36172 -/* 36163 */ MCD_OPC_CheckPredicate, 0, 122, 17, // Skip to: 40641 -/* 36167 */ MCD_OPC_Decode, 236, 2, 253, 1, // Opcode: FCMGTv1i32rz -/* 36172 */ MCD_OPC_FilterValue, 224, 1, 112, 17, // Skip to: 40641 -/* 36177 */ MCD_OPC_CheckPredicate, 0, 108, 17, // Skip to: 40641 -/* 36181 */ MCD_OPC_Decode, 237, 2, 90, // Opcode: FCMGTv1i64rz -/* 36185 */ MCD_OPC_FilterValue, 52, 29, 0, // Skip to: 36218 -/* 36189 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 36192 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 36205 -/* 36196 */ MCD_OPC_CheckPredicate, 0, 89, 17, // Skip to: 40641 -/* 36200 */ MCD_OPC_Decode, 207, 11, 164, 2, // Opcode: SQDMULLi16 -/* 36205 */ MCD_OPC_FilterValue, 5, 80, 17, // Skip to: 40641 -/* 36209 */ MCD_OPC_CheckPredicate, 0, 76, 17, // Skip to: 40641 -/* 36213 */ MCD_OPC_Decode, 208, 11, 165, 2, // Opcode: SQDMULLi32 -/* 36218 */ MCD_OPC_FilterValue, 54, 82, 0, // Skip to: 36304 -/* 36222 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 36225 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 36238 -/* 36229 */ MCD_OPC_CheckPredicate, 0, 56, 17, // Skip to: 40641 -/* 36233 */ MCD_OPC_Decode, 142, 10, 253, 1, // Opcode: SCVTFv1i32 -/* 36238 */ MCD_OPC_FilterValue, 97, 8, 0, // Skip to: 36250 -/* 36242 */ MCD_OPC_CheckPredicate, 0, 43, 17, // Skip to: 40641 -/* 36246 */ MCD_OPC_Decode, 143, 10, 90, // Opcode: SCVTFv1i64 -/* 36250 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36264 -/* 36255 */ MCD_OPC_CheckPredicate, 0, 30, 17, // Skip to: 40641 -/* 36259 */ MCD_OPC_Decode, 216, 2, 253, 1, // Opcode: FCMEQv1i32rz -/* 36264 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36278 -/* 36269 */ MCD_OPC_CheckPredicate, 0, 16, 17, // Skip to: 40641 -/* 36273 */ MCD_OPC_Decode, 140, 5, 253, 1, // Opcode: FRECPEv1i32 -/* 36278 */ MCD_OPC_FilterValue, 224, 1, 8, 0, // Skip to: 36291 -/* 36283 */ MCD_OPC_CheckPredicate, 0, 2, 17, // Skip to: 40641 -/* 36287 */ MCD_OPC_Decode, 217, 2, 90, // Opcode: FCMEQv1i64rz -/* 36291 */ MCD_OPC_FilterValue, 225, 1, 249, 16, // Skip to: 40641 -/* 36296 */ MCD_OPC_CheckPredicate, 0, 245, 16, // Skip to: 40641 -/* 36300 */ MCD_OPC_Decode, 141, 5, 90, // Opcode: FRECPEv1i64 -/* 36304 */ MCD_OPC_FilterValue, 55, 28, 0, // Skip to: 36336 -/* 36308 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 36311 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36324 -/* 36315 */ MCD_OPC_CheckPredicate, 0, 226, 16, // Skip to: 40641 -/* 36319 */ MCD_OPC_Decode, 239, 4, 130, 2, // Opcode: FMULX32 -/* 36324 */ MCD_OPC_FilterValue, 3, 217, 16, // Skip to: 40641 -/* 36328 */ MCD_OPC_CheckPredicate, 0, 213, 16, // Skip to: 40641 -/* 36332 */ MCD_OPC_Decode, 240, 4, 89, // Opcode: FMULX64 -/* 36336 */ MCD_OPC_FilterValue, 57, 28, 0, // Skip to: 36368 -/* 36340 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 36343 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36356 -/* 36347 */ MCD_OPC_CheckPredicate, 0, 194, 16, // Skip to: 40641 -/* 36351 */ MCD_OPC_Decode, 214, 2, 130, 2, // Opcode: FCMEQ32 -/* 36356 */ MCD_OPC_FilterValue, 3, 185, 16, // Skip to: 40641 -/* 36360 */ MCD_OPC_CheckPredicate, 0, 181, 16, // Skip to: 40641 -/* 36364 */ MCD_OPC_Decode, 215, 2, 89, // Opcode: FCMEQ64 -/* 36368 */ MCD_OPC_FilterValue, 58, 30, 0, // Skip to: 36402 -/* 36372 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 36375 */ MCD_OPC_FilterValue, 160, 1, 9, 0, // Skip to: 36389 -/* 36380 */ MCD_OPC_CheckPredicate, 0, 161, 16, // Skip to: 40641 -/* 36384 */ MCD_OPC_Decode, 249, 2, 253, 1, // Opcode: FCMLTv1i32rz -/* 36389 */ MCD_OPC_FilterValue, 224, 1, 151, 16, // Skip to: 40641 -/* 36394 */ MCD_OPC_CheckPredicate, 0, 147, 16, // Skip to: 40641 -/* 36398 */ MCD_OPC_Decode, 250, 2, 90, // Opcode: FCMLTv1i64rz -/* 36402 */ MCD_OPC_FilterValue, 62, 30, 0, // Skip to: 36436 -/* 36406 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 36409 */ MCD_OPC_FilterValue, 161, 1, 9, 0, // Skip to: 36423 -/* 36414 */ MCD_OPC_CheckPredicate, 0, 127, 16, // Skip to: 40641 -/* 36418 */ MCD_OPC_Decode, 150, 5, 253, 1, // Opcode: FRECPXv1i32 -/* 36423 */ MCD_OPC_FilterValue, 225, 1, 117, 16, // Skip to: 40641 -/* 36428 */ MCD_OPC_CheckPredicate, 0, 113, 16, // Skip to: 40641 -/* 36432 */ MCD_OPC_Decode, 151, 5, 90, // Opcode: FRECPXv1i64 -/* 36436 */ MCD_OPC_FilterValue, 63, 105, 16, // Skip to: 40641 -/* 36440 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... -/* 36443 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36456 -/* 36447 */ MCD_OPC_CheckPredicate, 0, 94, 16, // Skip to: 40641 -/* 36451 */ MCD_OPC_Decode, 145, 5, 130, 2, // Opcode: FRECPS32 -/* 36456 */ MCD_OPC_FilterValue, 3, 8, 0, // Skip to: 36468 -/* 36460 */ MCD_OPC_CheckPredicate, 0, 81, 16, // Skip to: 40641 -/* 36464 */ MCD_OPC_Decode, 146, 5, 89, // Opcode: FRECPS64 -/* 36468 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 36481 -/* 36472 */ MCD_OPC_CheckPredicate, 0, 69, 16, // Skip to: 40641 -/* 36476 */ MCD_OPC_Decode, 192, 5, 130, 2, // Opcode: FRSQRTS32 -/* 36481 */ MCD_OPC_FilterValue, 7, 60, 16, // Skip to: 40641 -/* 36485 */ MCD_OPC_CheckPredicate, 0, 56, 16, // Skip to: 40641 -/* 36489 */ MCD_OPC_Decode, 193, 5, 89, // Opcode: FRSQRTS64 -/* 36493 */ MCD_OPC_FilterValue, 3, 48, 16, // Skip to: 40641 -/* 36497 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... -/* 36500 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 36525 -/* 36504 */ MCD_OPC_CheckPredicate, 0, 37, 16, // Skip to: 40641 -/* 36508 */ MCD_OPC_CheckField, 22, 2, 1, 31, 16, // Skip to: 40641 -/* 36514 */ MCD_OPC_CheckField, 10, 2, 1, 25, 16, // Skip to: 40641 -/* 36520 */ MCD_OPC_Decode, 147, 13, 166, 2, // Opcode: SSHRd -/* 36525 */ MCD_OPC_FilterValue, 1, 66, 0, // Skip to: 36595 -/* 36529 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 36532 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 36551 -/* 36536 */ MCD_OPC_CheckPredicate, 0, 5, 16, // Skip to: 40641 -/* 36540 */ MCD_OPC_CheckField, 10, 2, 1, 255, 15, // Skip to: 40641 -/* 36546 */ MCD_OPC_Decode, 155, 13, 167, 2, // Opcode: SSRAd -/* 36551 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 36570 -/* 36555 */ MCD_OPC_CheckPredicate, 0, 242, 15, // Skip to: 40641 -/* 36559 */ MCD_OPC_CheckField, 10, 1, 0, 236, 15, // Skip to: 40641 -/* 36565 */ MCD_OPC_Decode, 206, 4, 168, 2, // Opcode: FMLAv1i32_indexed -/* 36570 */ MCD_OPC_FilterValue, 3, 227, 15, // Skip to: 40641 -/* 36574 */ MCD_OPC_CheckPredicate, 0, 223, 15, // Skip to: 40641 -/* 36578 */ MCD_OPC_CheckField, 21, 1, 0, 217, 15, // Skip to: 40641 -/* 36584 */ MCD_OPC_CheckField, 10, 1, 0, 211, 15, // Skip to: 40641 -/* 36590 */ MCD_OPC_Decode, 207, 4, 169, 2, // Opcode: FMLAv1i64_indexed -/* 36595 */ MCD_OPC_FilterValue, 2, 21, 0, // Skip to: 36620 -/* 36599 */ MCD_OPC_CheckPredicate, 0, 198, 15, // Skip to: 40641 -/* 36603 */ MCD_OPC_CheckField, 22, 2, 1, 192, 15, // Skip to: 40641 -/* 36609 */ MCD_OPC_CheckField, 10, 2, 1, 186, 15, // Skip to: 40641 -/* 36615 */ MCD_OPC_Decode, 245, 12, 166, 2, // Opcode: SRSHRd -/* 36620 */ MCD_OPC_FilterValue, 3, 61, 0, // Skip to: 36685 -/* 36624 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 36627 */ MCD_OPC_FilterValue, 0, 29, 0, // Skip to: 36660 -/* 36631 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 36634 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 36647 -/* 36638 */ MCD_OPC_CheckPredicate, 0, 159, 15, // Skip to: 40641 -/* 36642 */ MCD_OPC_Decode, 173, 11, 170, 2, // Opcode: SQDMLALv1i32_indexed -/* 36647 */ MCD_OPC_FilterValue, 2, 150, 15, // Skip to: 40641 -/* 36651 */ MCD_OPC_CheckPredicate, 0, 146, 15, // Skip to: 40641 -/* 36655 */ MCD_OPC_Decode, 174, 11, 171, 2, // Opcode: SQDMLALv1i64_indexed -/* 36660 */ MCD_OPC_FilterValue, 1, 137, 15, // Skip to: 40641 -/* 36664 */ MCD_OPC_CheckPredicate, 0, 133, 15, // Skip to: 40641 -/* 36668 */ MCD_OPC_CheckField, 22, 2, 1, 127, 15, // Skip to: 40641 -/* 36674 */ MCD_OPC_CheckField, 11, 1, 0, 121, 15, // Skip to: 40641 -/* 36680 */ MCD_OPC_Decode, 253, 12, 167, 2, // Opcode: SRSRAd -/* 36685 */ MCD_OPC_FilterValue, 5, 66, 0, // Skip to: 36755 -/* 36689 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 36692 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 36711 -/* 36696 */ MCD_OPC_CheckPredicate, 0, 101, 15, // Skip to: 40641 -/* 36700 */ MCD_OPC_CheckField, 10, 2, 1, 95, 15, // Skip to: 40641 -/* 36706 */ MCD_OPC_Decode, 176, 10, 172, 2, // Opcode: SHLd -/* 36711 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 36730 -/* 36715 */ MCD_OPC_CheckPredicate, 0, 82, 15, // Skip to: 40641 -/* 36719 */ MCD_OPC_CheckField, 10, 1, 0, 76, 15, // Skip to: 40641 -/* 36725 */ MCD_OPC_Decode, 214, 4, 168, 2, // Opcode: FMLSv1i32_indexed -/* 36730 */ MCD_OPC_FilterValue, 3, 67, 15, // Skip to: 40641 -/* 36734 */ MCD_OPC_CheckPredicate, 0, 63, 15, // Skip to: 40641 -/* 36738 */ MCD_OPC_CheckField, 21, 1, 0, 57, 15, // Skip to: 40641 -/* 36744 */ MCD_OPC_CheckField, 10, 1, 0, 51, 15, // Skip to: 40641 -/* 36750 */ MCD_OPC_Decode, 215, 4, 169, 2, // Opcode: FMLSv1i64_indexed -/* 36755 */ MCD_OPC_FilterValue, 7, 138, 0, // Skip to: 36897 -/* 36759 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 36762 */ MCD_OPC_FilterValue, 0, 73, 0, // Skip to: 36839 -/* 36766 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36769 */ MCD_OPC_FilterValue, 0, 47, 0, // Skip to: 36820 -/* 36773 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 36776 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 36801 -/* 36780 */ MCD_OPC_CheckPredicate, 0, 17, 15, // Skip to: 40641 -/* 36784 */ MCD_OPC_CheckField, 19, 1, 1, 11, 15, // Skip to: 40641 -/* 36790 */ MCD_OPC_CheckField, 10, 2, 1, 5, 15, // Skip to: 40641 -/* 36796 */ MCD_OPC_Decode, 154, 12, 173, 2, // Opcode: SQSHLb -/* 36801 */ MCD_OPC_FilterValue, 1, 252, 14, // Skip to: 40641 -/* 36805 */ MCD_OPC_CheckPredicate, 0, 248, 14, // Skip to: 40641 -/* 36809 */ MCD_OPC_CheckField, 10, 2, 1, 242, 14, // Skip to: 40641 -/* 36815 */ MCD_OPC_Decode, 156, 12, 174, 2, // Opcode: SQSHLh -/* 36820 */ MCD_OPC_FilterValue, 1, 233, 14, // Skip to: 40641 -/* 36824 */ MCD_OPC_CheckPredicate, 0, 229, 14, // Skip to: 40641 -/* 36828 */ MCD_OPC_CheckField, 10, 2, 1, 223, 14, // Skip to: 40641 -/* 36834 */ MCD_OPC_Decode, 157, 12, 175, 2, // Opcode: SQSHLs -/* 36839 */ MCD_OPC_FilterValue, 1, 35, 0, // Skip to: 36878 -/* 36843 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... -/* 36846 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 36859 -/* 36850 */ MCD_OPC_CheckPredicate, 0, 203, 14, // Skip to: 40641 -/* 36854 */ MCD_OPC_Decode, 185, 11, 170, 2, // Opcode: SQDMLSLv1i32_indexed -/* 36859 */ MCD_OPC_FilterValue, 1, 194, 14, // Skip to: 40641 -/* 36863 */ MCD_OPC_CheckPredicate, 0, 190, 14, // Skip to: 40641 -/* 36867 */ MCD_OPC_CheckField, 11, 1, 0, 184, 14, // Skip to: 40641 -/* 36873 */ MCD_OPC_Decode, 155, 12, 172, 2, // Opcode: SQSHLd -/* 36878 */ MCD_OPC_FilterValue, 2, 175, 14, // Skip to: 40641 -/* 36882 */ MCD_OPC_CheckPredicate, 0, 171, 14, // Skip to: 40641 -/* 36886 */ MCD_OPC_CheckField, 10, 1, 0, 165, 14, // Skip to: 40641 -/* 36892 */ MCD_OPC_Decode, 186, 11, 171, 2, // Opcode: SQDMLSLv1i64_indexed -/* 36897 */ MCD_OPC_FilterValue, 9, 172, 0, // Skip to: 37073 -/* 36901 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 36904 */ MCD_OPC_FilterValue, 0, 121, 0, // Skip to: 37029 -/* 36908 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 36911 */ MCD_OPC_FilterValue, 1, 55, 0, // Skip to: 36970 -/* 36915 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36918 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 36957 -/* 36922 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 36925 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 36944 -/* 36929 */ MCD_OPC_CheckPredicate, 0, 124, 14, // Skip to: 40641 -/* 36933 */ MCD_OPC_CheckField, 19, 1, 1, 118, 14, // Skip to: 40641 -/* 36939 */ MCD_OPC_Decode, 176, 12, 176, 2, // Opcode: SQSHRNb -/* 36944 */ MCD_OPC_FilterValue, 1, 109, 14, // Skip to: 40641 -/* 36948 */ MCD_OPC_CheckPredicate, 0, 105, 14, // Skip to: 40641 -/* 36952 */ MCD_OPC_Decode, 177, 12, 177, 2, // Opcode: SQSHRNh -/* 36957 */ MCD_OPC_FilterValue, 1, 96, 14, // Skip to: 40641 -/* 36961 */ MCD_OPC_CheckPredicate, 0, 92, 14, // Skip to: 40641 -/* 36965 */ MCD_OPC_Decode, 178, 12, 178, 2, // Opcode: SQSHRNs -/* 36970 */ MCD_OPC_FilterValue, 3, 83, 14, // Skip to: 40641 -/* 36974 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 36977 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 37016 -/* 36981 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 36984 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 37003 -/* 36988 */ MCD_OPC_CheckPredicate, 0, 65, 14, // Skip to: 40641 -/* 36992 */ MCD_OPC_CheckField, 19, 1, 1, 59, 14, // Skip to: 40641 -/* 36998 */ MCD_OPC_Decode, 253, 11, 176, 2, // Opcode: SQRSHRNb -/* 37003 */ MCD_OPC_FilterValue, 1, 50, 14, // Skip to: 40641 -/* 37007 */ MCD_OPC_CheckPredicate, 0, 46, 14, // Skip to: 40641 -/* 37011 */ MCD_OPC_Decode, 254, 11, 177, 2, // Opcode: SQRSHRNh -/* 37016 */ MCD_OPC_FilterValue, 1, 37, 14, // Skip to: 40641 -/* 37020 */ MCD_OPC_CheckPredicate, 0, 33, 14, // Skip to: 40641 -/* 37024 */ MCD_OPC_Decode, 255, 11, 178, 2, // Opcode: SQRSHRNs -/* 37029 */ MCD_OPC_FilterValue, 2, 15, 0, // Skip to: 37048 -/* 37033 */ MCD_OPC_CheckPredicate, 0, 20, 14, // Skip to: 40641 -/* 37037 */ MCD_OPC_CheckField, 10, 1, 0, 14, 14, // Skip to: 40641 -/* 37043 */ MCD_OPC_Decode, 249, 4, 179, 2, // Opcode: FMULv1i32_indexed -/* 37048 */ MCD_OPC_FilterValue, 3, 5, 14, // Skip to: 40641 -/* 37052 */ MCD_OPC_CheckPredicate, 0, 1, 14, // Skip to: 40641 -/* 37056 */ MCD_OPC_CheckField, 21, 1, 0, 251, 13, // Skip to: 40641 -/* 37062 */ MCD_OPC_CheckField, 10, 1, 0, 245, 13, // Skip to: 40641 -/* 37068 */ MCD_OPC_Decode, 250, 4, 180, 2, // Opcode: FMULv1i64_indexed -/* 37073 */ MCD_OPC_FilterValue, 11, 41, 0, // Skip to: 37118 -/* 37077 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 37080 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37099 -/* 37084 */ MCD_OPC_CheckPredicate, 0, 225, 13, // Skip to: 40641 -/* 37088 */ MCD_OPC_CheckField, 10, 1, 0, 219, 13, // Skip to: 40641 -/* 37094 */ MCD_OPC_Decode, 209, 11, 181, 2, // Opcode: SQDMULLv1i32_indexed -/* 37099 */ MCD_OPC_FilterValue, 2, 210, 13, // Skip to: 40641 -/* 37103 */ MCD_OPC_CheckPredicate, 0, 206, 13, // Skip to: 40641 -/* 37107 */ MCD_OPC_CheckField, 10, 1, 0, 200, 13, // Skip to: 40641 -/* 37113 */ MCD_OPC_Decode, 210, 11, 182, 2, // Opcode: SQDMULLv1i64_indexed -/* 37118 */ MCD_OPC_FilterValue, 12, 41, 0, // Skip to: 37163 -/* 37122 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 37125 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37144 -/* 37129 */ MCD_OPC_CheckPredicate, 0, 180, 13, // Skip to: 40641 -/* 37133 */ MCD_OPC_CheckField, 10, 1, 0, 174, 13, // Skip to: 40641 -/* 37139 */ MCD_OPC_Decode, 196, 11, 183, 2, // Opcode: SQDMULHv1i16_indexed -/* 37144 */ MCD_OPC_FilterValue, 2, 165, 13, // Skip to: 40641 -/* 37148 */ MCD_OPC_CheckPredicate, 0, 161, 13, // Skip to: 40641 -/* 37152 */ MCD_OPC_CheckField, 10, 1, 0, 155, 13, // Skip to: 40641 -/* 37158 */ MCD_OPC_Decode, 198, 11, 179, 2, // Opcode: SQDMULHv1i32_indexed -/* 37163 */ MCD_OPC_FilterValue, 13, 41, 0, // Skip to: 37208 -/* 37167 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 37170 */ MCD_OPC_FilterValue, 1, 15, 0, // Skip to: 37189 -/* 37174 */ MCD_OPC_CheckPredicate, 0, 135, 13, // Skip to: 40641 -/* 37178 */ MCD_OPC_CheckField, 10, 1, 0, 129, 13, // Skip to: 40641 -/* 37184 */ MCD_OPC_Decode, 231, 11, 183, 2, // Opcode: SQRDMULHv1i16_indexed -/* 37189 */ MCD_OPC_FilterValue, 2, 120, 13, // Skip to: 40641 -/* 37193 */ MCD_OPC_CheckPredicate, 0, 116, 13, // Skip to: 40641 -/* 37197 */ MCD_OPC_CheckField, 10, 1, 0, 110, 13, // Skip to: 40641 -/* 37203 */ MCD_OPC_Decode, 233, 11, 179, 2, // Opcode: SQRDMULHv1i32_indexed -/* 37208 */ MCD_OPC_FilterValue, 14, 47, 0, // Skip to: 37259 -/* 37212 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 37215 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 37240 -/* 37219 */ MCD_OPC_CheckPredicate, 0, 90, 13, // Skip to: 40641 -/* 37223 */ MCD_OPC_CheckField, 21, 1, 1, 84, 13, // Skip to: 40641 -/* 37229 */ MCD_OPC_CheckField, 10, 2, 1, 78, 13, // Skip to: 40641 -/* 37235 */ MCD_OPC_Decode, 141, 10, 184, 2, // Opcode: SCVTFs -/* 37240 */ MCD_OPC_FilterValue, 1, 69, 13, // Skip to: 40641 -/* 37244 */ MCD_OPC_CheckPredicate, 0, 65, 13, // Skip to: 40641 -/* 37248 */ MCD_OPC_CheckField, 10, 2, 1, 59, 13, // Skip to: 40641 -/* 37254 */ MCD_OPC_Decode, 140, 10, 166, 2, // Opcode: SCVTFd -/* 37259 */ MCD_OPC_FilterValue, 15, 50, 13, // Skip to: 40641 -/* 37263 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... -/* 37266 */ MCD_OPC_FilterValue, 0, 21, 0, // Skip to: 37291 -/* 37270 */ MCD_OPC_CheckPredicate, 0, 39, 13, // Skip to: 40641 -/* 37274 */ MCD_OPC_CheckField, 21, 1, 1, 33, 13, // Skip to: 40641 -/* 37280 */ MCD_OPC_CheckField, 10, 2, 3, 27, 13, // Skip to: 40641 -/* 37286 */ MCD_OPC_Decode, 245, 3, 184, 2, // Opcode: FCVTZSs -/* 37291 */ MCD_OPC_FilterValue, 1, 18, 13, // Skip to: 40641 -/* 37295 */ MCD_OPC_CheckPredicate, 0, 14, 13, // Skip to: 40641 -/* 37299 */ MCD_OPC_CheckField, 10, 2, 3, 8, 13, // Skip to: 40641 -/* 37305 */ MCD_OPC_Decode, 244, 3, 166, 2, // Opcode: FCVTZSd -/* 37310 */ MCD_OPC_FilterValue, 3, 212, 8, // Skip to: 39574 -/* 37314 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 37317 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 37406 -/* 37321 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 37324 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 37339 -/* 37328 */ MCD_OPC_CheckField, 21, 1, 0, 235, 12, // Skip to: 40641 -/* 37334 */ MCD_OPC_Decode, 140, 15, 226, 1, // Opcode: STURHi -/* 37339 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 37354 -/* 37343 */ MCD_OPC_CheckField, 21, 1, 0, 220, 12, // Skip to: 40641 -/* 37349 */ MCD_OPC_Decode, 235, 14, 226, 1, // Opcode: STRHpost -/* 37354 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 37391 -/* 37358 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 37361 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 37376 -/* 37365 */ MCD_OPC_CheckField, 21, 1, 1, 198, 12, // Skip to: 40641 -/* 37371 */ MCD_OPC_Decode, 237, 14, 185, 2, // Opcode: STRHroW -/* 37376 */ MCD_OPC_FilterValue, 3, 189, 12, // Skip to: 40641 -/* 37380 */ MCD_OPC_CheckField, 21, 1, 1, 183, 12, // Skip to: 40641 -/* 37386 */ MCD_OPC_Decode, 238, 14, 186, 2, // Opcode: STRHroX -/* 37391 */ MCD_OPC_FilterValue, 3, 174, 12, // Skip to: 40641 -/* 37395 */ MCD_OPC_CheckField, 21, 1, 0, 168, 12, // Skip to: 40641 -/* 37401 */ MCD_OPC_Decode, 236, 14, 226, 1, // Opcode: STRHpre -/* 37406 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 37495 -/* 37410 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 37413 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 37428 -/* 37417 */ MCD_OPC_CheckField, 21, 1, 0, 146, 12, // Skip to: 40641 -/* 37423 */ MCD_OPC_Decode, 159, 8, 226, 1, // Opcode: LDURHi -/* 37428 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 37443 -/* 37432 */ MCD_OPC_CheckField, 21, 1, 0, 131, 12, // Skip to: 40641 -/* 37438 */ MCD_OPC_Decode, 219, 7, 226, 1, // Opcode: LDRHpost -/* 37443 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 37480 -/* 37447 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 37450 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 37465 -/* 37454 */ MCD_OPC_CheckField, 21, 1, 1, 109, 12, // Skip to: 40641 -/* 37460 */ MCD_OPC_Decode, 221, 7, 185, 2, // Opcode: LDRHroW -/* 37465 */ MCD_OPC_FilterValue, 3, 100, 12, // Skip to: 40641 -/* 37469 */ MCD_OPC_CheckField, 21, 1, 1, 94, 12, // Skip to: 40641 -/* 37475 */ MCD_OPC_Decode, 222, 7, 186, 2, // Opcode: LDRHroX -/* 37480 */ MCD_OPC_FilterValue, 3, 85, 12, // Skip to: 40641 -/* 37484 */ MCD_OPC_CheckField, 21, 1, 0, 79, 12, // Skip to: 40641 -/* 37490 */ MCD_OPC_Decode, 220, 7, 226, 1, // Opcode: LDRHpre -/* 37495 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 37504 -/* 37499 */ MCD_OPC_Decode, 239, 14, 231, 1, // Opcode: STRHui -/* 37504 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 37513 -/* 37508 */ MCD_OPC_Decode, 223, 7, 231, 1, // Opcode: LDRHui -/* 37513 */ MCD_OPC_FilterValue, 8, 60, 1, // Skip to: 37833 -/* 37517 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 37520 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 37539 -/* 37524 */ MCD_OPC_CheckPredicate, 0, 41, 12, // Skip to: 40641 -/* 37528 */ MCD_OPC_CheckField, 21, 1, 1, 35, 12, // Skip to: 40641 -/* 37534 */ MCD_OPC_Decode, 143, 17, 154, 2, // Opcode: UQADDv1i8 -/* 37539 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 37558 -/* 37543 */ MCD_OPC_CheckPredicate, 0, 22, 12, // Skip to: 40641 -/* 37547 */ MCD_OPC_CheckField, 16, 6, 33, 16, 12, // Skip to: 40641 -/* 37553 */ MCD_OPC_Decode, 217, 12, 159, 2, // Opcode: SQXTUNv1i8 -/* 37558 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 37577 -/* 37562 */ MCD_OPC_CheckPredicate, 0, 3, 12, // Skip to: 40641 -/* 37566 */ MCD_OPC_CheckField, 21, 1, 1, 253, 11, // Skip to: 40641 -/* 37572 */ MCD_OPC_Decode, 205, 17, 154, 2, // Opcode: UQSUBv1i8 -/* 37577 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 37596 -/* 37581 */ MCD_OPC_CheckPredicate, 0, 240, 11, // Skip to: 40641 -/* 37585 */ MCD_OPC_CheckField, 16, 6, 32, 234, 11, // Skip to: 40641 -/* 37591 */ MCD_OPC_Decode, 153, 18, 156, 2, // Opcode: USQADDv1i8 -/* 37596 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 37615 -/* 37600 */ MCD_OPC_CheckPredicate, 0, 221, 11, // Skip to: 40641 -/* 37604 */ MCD_OPC_CheckField, 16, 6, 33, 215, 11, // Skip to: 40641 -/* 37610 */ MCD_OPC_Decode, 215, 17, 159, 2, // Opcode: UQXTNv1i8 -/* 37615 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 37634 -/* 37619 */ MCD_OPC_CheckPredicate, 0, 202, 11, // Skip to: 40641 -/* 37623 */ MCD_OPC_CheckField, 21, 1, 1, 196, 11, // Skip to: 40641 -/* 37629 */ MCD_OPC_Decode, 179, 17, 154, 2, // Opcode: UQSHLv1i8 -/* 37634 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 37653 -/* 37638 */ MCD_OPC_CheckPredicate, 0, 183, 11, // Skip to: 40641 -/* 37642 */ MCD_OPC_CheckField, 21, 1, 1, 177, 11, // Skip to: 40641 -/* 37648 */ MCD_OPC_Decode, 154, 17, 154, 2, // Opcode: UQRSHLv1i8 -/* 37653 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 37672 -/* 37657 */ MCD_OPC_CheckPredicate, 0, 164, 11, // Skip to: 40641 -/* 37661 */ MCD_OPC_CheckField, 16, 6, 32, 158, 11, // Skip to: 40641 -/* 37667 */ MCD_OPC_Decode, 223, 11, 160, 2, // Opcode: SQNEGv1i8 -/* 37672 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 37691 -/* 37676 */ MCD_OPC_CheckPredicate, 0, 145, 11, // Skip to: 40641 -/* 37680 */ MCD_OPC_CheckField, 16, 6, 33, 139, 11, // Skip to: 40641 -/* 37686 */ MCD_OPC_Decode, 193, 3, 253, 1, // Opcode: FCVTNUv1i32 -/* 37691 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 37710 -/* 37695 */ MCD_OPC_CheckPredicate, 0, 126, 11, // Skip to: 40641 -/* 37699 */ MCD_OPC_CheckField, 16, 6, 33, 120, 11, // Skip to: 40641 -/* 37705 */ MCD_OPC_Decode, 175, 3, 253, 1, // Opcode: FCVTMUv1i32 -/* 37710 */ MCD_OPC_FilterValue, 50, 29, 0, // Skip to: 37743 -/* 37714 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 37717 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 37730 -/* 37721 */ MCD_OPC_CheckPredicate, 0, 100, 11, // Skip to: 40641 -/* 37725 */ MCD_OPC_Decode, 149, 3, 253, 1, // Opcode: FCVTAUv1i32 -/* 37730 */ MCD_OPC_FilterValue, 48, 91, 11, // Skip to: 40641 -/* 37734 */ MCD_OPC_CheckPredicate, 0, 87, 11, // Skip to: 40641 -/* 37738 */ MCD_OPC_Decode, 166, 4, 144, 1, // Opcode: FMAXNMPv2i32p -/* 37743 */ MCD_OPC_FilterValue, 54, 29, 0, // Skip to: 37776 -/* 37747 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 37750 */ MCD_OPC_FilterValue, 33, 9, 0, // Skip to: 37763 -/* 37754 */ MCD_OPC_CheckPredicate, 0, 67, 11, // Skip to: 40641 -/* 37758 */ MCD_OPC_Decode, 172, 16, 253, 1, // Opcode: UCVTFv1i32 -/* 37763 */ MCD_OPC_FilterValue, 48, 58, 11, // Skip to: 40641 -/* 37767 */ MCD_OPC_CheckPredicate, 0, 54, 11, // Skip to: 40641 -/* 37771 */ MCD_OPC_Decode, 203, 2, 144, 1, // Opcode: FADDPv2i32p -/* 37776 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 37795 -/* 37780 */ MCD_OPC_CheckPredicate, 0, 41, 11, // Skip to: 40641 -/* 37784 */ MCD_OPC_CheckField, 21, 1, 1, 35, 11, // Skip to: 40641 -/* 37790 */ MCD_OPC_Decode, 224, 2, 130, 2, // Opcode: FCMGE32 -/* 37795 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 37814 -/* 37799 */ MCD_OPC_CheckPredicate, 0, 22, 11, // Skip to: 40641 -/* 37803 */ MCD_OPC_CheckField, 21, 1, 1, 16, 11, // Skip to: 40641 -/* 37809 */ MCD_OPC_Decode, 190, 2, 130, 2, // Opcode: FACGE32 -/* 37814 */ MCD_OPC_FilterValue, 62, 7, 11, // Skip to: 40641 -/* 37818 */ MCD_OPC_CheckPredicate, 0, 3, 11, // Skip to: 40641 -/* 37822 */ MCD_OPC_CheckField, 16, 6, 48, 253, 10, // Skip to: 40641 -/* 37828 */ MCD_OPC_Decode, 176, 4, 144, 1, // Opcode: FMAXPv2i32p -/* 37833 */ MCD_OPC_FilterValue, 9, 89, 1, // Skip to: 38182 -/* 37837 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 37840 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 37859 -/* 37844 */ MCD_OPC_CheckPredicate, 0, 233, 10, // Skip to: 40641 -/* 37848 */ MCD_OPC_CheckField, 21, 1, 1, 227, 10, // Skip to: 40641 -/* 37854 */ MCD_OPC_Decode, 140, 17, 155, 2, // Opcode: UQADDv1i16 -/* 37859 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 37878 -/* 37863 */ MCD_OPC_CheckPredicate, 0, 214, 10, // Skip to: 40641 -/* 37867 */ MCD_OPC_CheckField, 16, 6, 33, 208, 10, // Skip to: 40641 -/* 37873 */ MCD_OPC_Decode, 215, 12, 255, 1, // Opcode: SQXTUNv1i16 -/* 37878 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 37897 -/* 37882 */ MCD_OPC_CheckPredicate, 0, 195, 10, // Skip to: 40641 -/* 37886 */ MCD_OPC_CheckField, 21, 1, 1, 189, 10, // Skip to: 40641 -/* 37892 */ MCD_OPC_Decode, 202, 17, 155, 2, // Opcode: UQSUBv1i16 -/* 37897 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 37916 -/* 37901 */ MCD_OPC_CheckPredicate, 0, 176, 10, // Skip to: 40641 -/* 37905 */ MCD_OPC_CheckField, 16, 6, 32, 170, 10, // Skip to: 40641 -/* 37911 */ MCD_OPC_Decode, 150, 18, 157, 2, // Opcode: USQADDv1i16 -/* 37916 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 37935 -/* 37920 */ MCD_OPC_CheckPredicate, 0, 157, 10, // Skip to: 40641 -/* 37924 */ MCD_OPC_CheckField, 16, 6, 33, 151, 10, // Skip to: 40641 -/* 37930 */ MCD_OPC_Decode, 213, 17, 255, 1, // Opcode: UQXTNv1i16 -/* 37935 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 37954 -/* 37939 */ MCD_OPC_CheckPredicate, 0, 138, 10, // Skip to: 40641 -/* 37943 */ MCD_OPC_CheckField, 21, 1, 1, 132, 10, // Skip to: 40641 -/* 37949 */ MCD_OPC_Decode, 176, 17, 155, 2, // Opcode: UQSHLv1i16 -/* 37954 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 37973 -/* 37958 */ MCD_OPC_CheckPredicate, 0, 119, 10, // Skip to: 40641 -/* 37962 */ MCD_OPC_CheckField, 21, 1, 1, 113, 10, // Skip to: 40641 -/* 37968 */ MCD_OPC_Decode, 151, 17, 155, 2, // Opcode: UQRSHLv1i16 -/* 37973 */ MCD_OPC_FilterValue, 26, 15, 0, // Skip to: 37992 -/* 37977 */ MCD_OPC_CheckPredicate, 0, 100, 10, // Skip to: 40641 -/* 37981 */ MCD_OPC_CheckField, 16, 6, 33, 94, 10, // Skip to: 40641 -/* 37987 */ MCD_OPC_Decode, 222, 3, 144, 1, // Opcode: FCVTXNv1i64 -/* 37992 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 38011 -/* 37996 */ MCD_OPC_CheckPredicate, 0, 81, 10, // Skip to: 40641 -/* 38000 */ MCD_OPC_CheckField, 16, 6, 32, 75, 10, // Skip to: 40641 -/* 38006 */ MCD_OPC_Decode, 220, 11, 161, 2, // Opcode: SQNEGv1i16 -/* 38011 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 38029 -/* 38015 */ MCD_OPC_CheckPredicate, 0, 62, 10, // Skip to: 40641 -/* 38019 */ MCD_OPC_CheckField, 16, 6, 33, 56, 10, // Skip to: 40641 -/* 38025 */ MCD_OPC_Decode, 194, 3, 90, // Opcode: FCVTNUv1i64 -/* 38029 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 38048 -/* 38033 */ MCD_OPC_CheckPredicate, 0, 44, 10, // Skip to: 40641 -/* 38037 */ MCD_OPC_CheckField, 21, 1, 1, 38, 10, // Skip to: 40641 -/* 38043 */ MCD_OPC_Decode, 230, 11, 155, 2, // Opcode: SQRDMULHv1i16 -/* 38048 */ MCD_OPC_FilterValue, 46, 14, 0, // Skip to: 38066 -/* 38052 */ MCD_OPC_CheckPredicate, 0, 25, 10, // Skip to: 40641 -/* 38056 */ MCD_OPC_CheckField, 16, 6, 33, 19, 10, // Skip to: 40641 -/* 38062 */ MCD_OPC_Decode, 176, 3, 90, // Opcode: FCVTMUv1i64 -/* 38066 */ MCD_OPC_FilterValue, 50, 27, 0, // Skip to: 38097 -/* 38070 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38073 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 38085 -/* 38077 */ MCD_OPC_CheckPredicate, 0, 0, 10, // Skip to: 40641 -/* 38081 */ MCD_OPC_Decode, 150, 3, 90, // Opcode: FCVTAUv1i64 -/* 38085 */ MCD_OPC_FilterValue, 48, 248, 9, // Skip to: 40641 -/* 38089 */ MCD_OPC_CheckPredicate, 0, 244, 9, // Skip to: 40641 -/* 38093 */ MCD_OPC_Decode, 167, 4, 95, // Opcode: FMAXNMPv2i64p -/* 38097 */ MCD_OPC_FilterValue, 54, 27, 0, // Skip to: 38128 -/* 38101 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38104 */ MCD_OPC_FilterValue, 33, 8, 0, // Skip to: 38116 -/* 38108 */ MCD_OPC_CheckPredicate, 0, 225, 9, // Skip to: 40641 -/* 38112 */ MCD_OPC_Decode, 173, 16, 90, // Opcode: UCVTFv1i64 -/* 38116 */ MCD_OPC_FilterValue, 48, 217, 9, // Skip to: 40641 -/* 38120 */ MCD_OPC_CheckPredicate, 0, 213, 9, // Skip to: 40641 -/* 38124 */ MCD_OPC_Decode, 204, 2, 95, // Opcode: FADDPv2i64p -/* 38128 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 38146 -/* 38132 */ MCD_OPC_CheckPredicate, 0, 201, 9, // Skip to: 40641 -/* 38136 */ MCD_OPC_CheckField, 21, 1, 1, 195, 9, // Skip to: 40641 -/* 38142 */ MCD_OPC_Decode, 225, 2, 89, // Opcode: FCMGE64 -/* 38146 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 38164 -/* 38150 */ MCD_OPC_CheckPredicate, 0, 183, 9, // Skip to: 40641 -/* 38154 */ MCD_OPC_CheckField, 21, 1, 1, 177, 9, // Skip to: 40641 -/* 38160 */ MCD_OPC_Decode, 191, 2, 89, // Opcode: FACGE64 -/* 38164 */ MCD_OPC_FilterValue, 62, 169, 9, // Skip to: 40641 -/* 38168 */ MCD_OPC_CheckPredicate, 0, 165, 9, // Skip to: 40641 -/* 38172 */ MCD_OPC_CheckField, 16, 6, 48, 159, 9, // Skip to: 40641 -/* 38178 */ MCD_OPC_Decode, 177, 4, 95, // Opcode: FMAXPv2i64p -/* 38182 */ MCD_OPC_FilterValue, 10, 98, 1, // Skip to: 38540 -/* 38186 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 38189 */ MCD_OPC_FilterValue, 3, 15, 0, // Skip to: 38208 -/* 38193 */ MCD_OPC_CheckPredicate, 0, 140, 9, // Skip to: 40641 -/* 38197 */ MCD_OPC_CheckField, 21, 1, 1, 134, 9, // Skip to: 40641 -/* 38203 */ MCD_OPC_Decode, 141, 17, 130, 2, // Opcode: UQADDv1i32 -/* 38208 */ MCD_OPC_FilterValue, 10, 15, 0, // Skip to: 38227 -/* 38212 */ MCD_OPC_CheckPredicate, 0, 121, 9, // Skip to: 40641 -/* 38216 */ MCD_OPC_CheckField, 16, 6, 33, 115, 9, // Skip to: 40641 -/* 38222 */ MCD_OPC_Decode, 216, 12, 144, 1, // Opcode: SQXTUNv1i32 -/* 38227 */ MCD_OPC_FilterValue, 11, 15, 0, // Skip to: 38246 -/* 38231 */ MCD_OPC_CheckPredicate, 0, 102, 9, // Skip to: 40641 -/* 38235 */ MCD_OPC_CheckField, 21, 1, 1, 96, 9, // Skip to: 40641 -/* 38241 */ MCD_OPC_Decode, 203, 17, 130, 2, // Opcode: UQSUBv1i32 -/* 38246 */ MCD_OPC_FilterValue, 14, 15, 0, // Skip to: 38265 -/* 38250 */ MCD_OPC_CheckPredicate, 0, 83, 9, // Skip to: 40641 -/* 38254 */ MCD_OPC_CheckField, 16, 6, 32, 77, 9, // Skip to: 40641 -/* 38260 */ MCD_OPC_Decode, 151, 18, 158, 2, // Opcode: USQADDv1i32 -/* 38265 */ MCD_OPC_FilterValue, 18, 15, 0, // Skip to: 38284 -/* 38269 */ MCD_OPC_CheckPredicate, 0, 64, 9, // Skip to: 40641 -/* 38273 */ MCD_OPC_CheckField, 16, 6, 33, 58, 9, // Skip to: 40641 -/* 38279 */ MCD_OPC_Decode, 214, 17, 144, 1, // Opcode: UQXTNv1i32 -/* 38284 */ MCD_OPC_FilterValue, 19, 15, 0, // Skip to: 38303 -/* 38288 */ MCD_OPC_CheckPredicate, 0, 45, 9, // Skip to: 40641 -/* 38292 */ MCD_OPC_CheckField, 21, 1, 1, 39, 9, // Skip to: 40641 -/* 38298 */ MCD_OPC_Decode, 177, 17, 130, 2, // Opcode: UQSHLv1i32 -/* 38303 */ MCD_OPC_FilterValue, 23, 15, 0, // Skip to: 38322 -/* 38307 */ MCD_OPC_CheckPredicate, 0, 26, 9, // Skip to: 40641 -/* 38311 */ MCD_OPC_CheckField, 21, 1, 1, 20, 9, // Skip to: 40641 -/* 38317 */ MCD_OPC_Decode, 152, 17, 130, 2, // Opcode: UQRSHLv1i32 -/* 38322 */ MCD_OPC_FilterValue, 30, 15, 0, // Skip to: 38341 -/* 38326 */ MCD_OPC_CheckPredicate, 0, 7, 9, // Skip to: 40641 -/* 38330 */ MCD_OPC_CheckField, 16, 6, 32, 1, 9, // Skip to: 40641 -/* 38336 */ MCD_OPC_Decode, 221, 11, 253, 1, // Opcode: SQNEGv1i32 -/* 38341 */ MCD_OPC_FilterValue, 42, 15, 0, // Skip to: 38360 -/* 38345 */ MCD_OPC_CheckPredicate, 0, 244, 8, // Skip to: 40641 -/* 38349 */ MCD_OPC_CheckField, 16, 6, 33, 238, 8, // Skip to: 40641 -/* 38355 */ MCD_OPC_Decode, 215, 3, 253, 1, // Opcode: FCVTPUv1i32 -/* 38360 */ MCD_OPC_FilterValue, 45, 15, 0, // Skip to: 38379 -/* 38364 */ MCD_OPC_CheckPredicate, 0, 225, 8, // Skip to: 40641 -/* 38368 */ MCD_OPC_CheckField, 21, 1, 1, 219, 8, // Skip to: 40641 -/* 38374 */ MCD_OPC_Decode, 232, 11, 130, 2, // Opcode: SQRDMULHv1i32 -/* 38379 */ MCD_OPC_FilterValue, 46, 15, 0, // Skip to: 38398 -/* 38383 */ MCD_OPC_CheckPredicate, 0, 206, 8, // Skip to: 40641 -/* 38387 */ MCD_OPC_CheckField, 16, 6, 33, 200, 8, // Skip to: 40641 -/* 38393 */ MCD_OPC_Decode, 147, 4, 253, 1, // Opcode: FCVTZUv1i32 -/* 38398 */ MCD_OPC_FilterValue, 50, 29, 0, // Skip to: 38431 -/* 38402 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38405 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 38418 -/* 38409 */ MCD_OPC_CheckPredicate, 0, 180, 8, // Skip to: 40641 -/* 38413 */ MCD_OPC_Decode, 226, 2, 253, 1, // Opcode: FCMGEv1i32rz -/* 38418 */ MCD_OPC_FilterValue, 48, 171, 8, // Skip to: 40641 -/* 38422 */ MCD_OPC_CheckPredicate, 0, 167, 8, // Skip to: 40641 -/* 38426 */ MCD_OPC_Decode, 188, 4, 144, 1, // Opcode: FMINNMPv2i32p -/* 38431 */ MCD_OPC_FilterValue, 53, 15, 0, // Skip to: 38450 -/* 38435 */ MCD_OPC_CheckPredicate, 0, 154, 8, // Skip to: 40641 -/* 38439 */ MCD_OPC_CheckField, 21, 1, 1, 148, 8, // Skip to: 40641 -/* 38445 */ MCD_OPC_Decode, 180, 2, 130, 2, // Opcode: FABD32 -/* 38450 */ MCD_OPC_FilterValue, 54, 29, 0, // Skip to: 38483 -/* 38454 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38457 */ MCD_OPC_FilterValue, 32, 9, 0, // Skip to: 38470 -/* 38461 */ MCD_OPC_CheckPredicate, 0, 128, 8, // Skip to: 40641 -/* 38465 */ MCD_OPC_Decode, 244, 2, 253, 1, // Opcode: FCMLEv1i32rz -/* 38470 */ MCD_OPC_FilterValue, 33, 119, 8, // Skip to: 40641 -/* 38474 */ MCD_OPC_CheckPredicate, 0, 115, 8, // Skip to: 40641 -/* 38478 */ MCD_OPC_Decode, 187, 5, 253, 1, // Opcode: FRSQRTEv1i32 -/* 38483 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 38502 -/* 38487 */ MCD_OPC_CheckPredicate, 0, 102, 8, // Skip to: 40641 -/* 38491 */ MCD_OPC_CheckField, 21, 1, 1, 96, 8, // Skip to: 40641 -/* 38497 */ MCD_OPC_Decode, 234, 2, 130, 2, // Opcode: FCMGT32 -/* 38502 */ MCD_OPC_FilterValue, 59, 15, 0, // Skip to: 38521 -/* 38506 */ MCD_OPC_CheckPredicate, 0, 83, 8, // Skip to: 40641 -/* 38510 */ MCD_OPC_CheckField, 21, 1, 1, 77, 8, // Skip to: 40641 -/* 38516 */ MCD_OPC_Decode, 195, 2, 130, 2, // Opcode: FACGT32 -/* 38521 */ MCD_OPC_FilterValue, 62, 68, 8, // Skip to: 40641 -/* 38525 */ MCD_OPC_CheckPredicate, 0, 64, 8, // Skip to: 40641 -/* 38529 */ MCD_OPC_CheckField, 16, 6, 48, 58, 8, // Skip to: 40641 -/* 38535 */ MCD_OPC_Decode, 198, 4, 144, 1, // Opcode: FMINPv2i32p -/* 38540 */ MCD_OPC_FilterValue, 11, 182, 1, // Skip to: 38982 -/* 38544 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 38547 */ MCD_OPC_FilterValue, 3, 14, 0, // Skip to: 38565 -/* 38551 */ MCD_OPC_CheckPredicate, 0, 38, 8, // Skip to: 40641 -/* 38555 */ MCD_OPC_CheckField, 21, 1, 1, 32, 8, // Skip to: 40641 -/* 38561 */ MCD_OPC_Decode, 142, 17, 89, // Opcode: UQADDv1i64 -/* 38565 */ MCD_OPC_FilterValue, 11, 14, 0, // Skip to: 38583 -/* 38569 */ MCD_OPC_CheckPredicate, 0, 20, 8, // Skip to: 40641 -/* 38573 */ MCD_OPC_CheckField, 21, 1, 1, 14, 8, // Skip to: 40641 -/* 38579 */ MCD_OPC_Decode, 204, 17, 89, // Opcode: UQSUBv1i64 -/* 38583 */ MCD_OPC_FilterValue, 13, 14, 0, // Skip to: 38601 -/* 38587 */ MCD_OPC_CheckPredicate, 0, 2, 8, // Skip to: 40641 -/* 38591 */ MCD_OPC_CheckField, 21, 1, 1, 252, 7, // Skip to: 40641 -/* 38597 */ MCD_OPC_Decode, 209, 1, 89, // Opcode: CMHIv1i64 -/* 38601 */ MCD_OPC_FilterValue, 14, 14, 0, // Skip to: 38619 -/* 38605 */ MCD_OPC_CheckPredicate, 0, 240, 7, // Skip to: 40641 -/* 38609 */ MCD_OPC_CheckField, 16, 6, 32, 234, 7, // Skip to: 40641 -/* 38615 */ MCD_OPC_Decode, 152, 18, 99, // Opcode: USQADDv1i64 -/* 38619 */ MCD_OPC_FilterValue, 15, 14, 0, // Skip to: 38637 -/* 38623 */ MCD_OPC_CheckPredicate, 0, 222, 7, // Skip to: 40641 -/* 38627 */ MCD_OPC_CheckField, 21, 1, 1, 216, 7, // Skip to: 40641 -/* 38633 */ MCD_OPC_Decode, 217, 1, 89, // Opcode: CMHSv1i64 -/* 38637 */ MCD_OPC_FilterValue, 17, 14, 0, // Skip to: 38655 -/* 38641 */ MCD_OPC_CheckPredicate, 0, 204, 7, // Skip to: 40641 -/* 38645 */ MCD_OPC_CheckField, 21, 1, 1, 198, 7, // Skip to: 40641 -/* 38651 */ MCD_OPC_Decode, 134, 18, 89, // Opcode: USHLv1i64 -/* 38655 */ MCD_OPC_FilterValue, 19, 14, 0, // Skip to: 38673 -/* 38659 */ MCD_OPC_CheckPredicate, 0, 186, 7, // Skip to: 40641 -/* 38663 */ MCD_OPC_CheckField, 21, 1, 1, 180, 7, // Skip to: 40641 -/* 38669 */ MCD_OPC_Decode, 178, 17, 89, // Opcode: UQSHLv1i64 -/* 38673 */ MCD_OPC_FilterValue, 21, 14, 0, // Skip to: 38691 -/* 38677 */ MCD_OPC_CheckPredicate, 0, 168, 7, // Skip to: 40641 -/* 38681 */ MCD_OPC_CheckField, 21, 1, 1, 162, 7, // Skip to: 40641 -/* 38687 */ MCD_OPC_Decode, 230, 17, 89, // Opcode: URSHLv1i64 -/* 38691 */ MCD_OPC_FilterValue, 23, 14, 0, // Skip to: 38709 -/* 38695 */ MCD_OPC_CheckPredicate, 0, 150, 7, // Skip to: 40641 -/* 38699 */ MCD_OPC_CheckField, 21, 1, 1, 144, 7, // Skip to: 40641 -/* 38705 */ MCD_OPC_Decode, 153, 17, 89, // Opcode: UQRSHLv1i64 -/* 38709 */ MCD_OPC_FilterValue, 30, 14, 0, // Skip to: 38727 -/* 38713 */ MCD_OPC_CheckPredicate, 0, 132, 7, // Skip to: 40641 -/* 38717 */ MCD_OPC_CheckField, 16, 6, 32, 126, 7, // Skip to: 40641 -/* 38723 */ MCD_OPC_Decode, 222, 11, 90, // Opcode: SQNEGv1i64 -/* 38727 */ MCD_OPC_FilterValue, 33, 14, 0, // Skip to: 38745 -/* 38731 */ MCD_OPC_CheckPredicate, 0, 114, 7, // Skip to: 40641 -/* 38735 */ MCD_OPC_CheckField, 21, 1, 1, 108, 7, // Skip to: 40641 -/* 38741 */ MCD_OPC_Decode, 176, 15, 89, // Opcode: SUBv1i64 -/* 38745 */ MCD_OPC_FilterValue, 34, 14, 0, // Skip to: 38763 -/* 38749 */ MCD_OPC_CheckPredicate, 0, 96, 7, // Skip to: 40641 -/* 38753 */ MCD_OPC_CheckField, 16, 6, 32, 90, 7, // Skip to: 40641 -/* 38759 */ MCD_OPC_Decode, 179, 1, 90, // Opcode: CMGEv1i64rz -/* 38763 */ MCD_OPC_FilterValue, 35, 14, 0, // Skip to: 38781 -/* 38767 */ MCD_OPC_CheckPredicate, 0, 78, 7, // Skip to: 40641 -/* 38771 */ MCD_OPC_CheckField, 21, 1, 1, 72, 7, // Skip to: 40641 -/* 38777 */ MCD_OPC_Decode, 162, 1, 89, // Opcode: CMEQv1i64 -/* 38781 */ MCD_OPC_FilterValue, 38, 14, 0, // Skip to: 38799 -/* 38785 */ MCD_OPC_CheckPredicate, 0, 60, 7, // Skip to: 40641 -/* 38789 */ MCD_OPC_CheckField, 16, 6, 32, 54, 7, // Skip to: 40641 -/* 38795 */ MCD_OPC_Decode, 225, 1, 90, // Opcode: CMLEv1i64rz -/* 38799 */ MCD_OPC_FilterValue, 42, 14, 0, // Skip to: 38817 -/* 38803 */ MCD_OPC_CheckPredicate, 0, 42, 7, // Skip to: 40641 -/* 38807 */ MCD_OPC_CheckField, 16, 6, 33, 36, 7, // Skip to: 40641 -/* 38813 */ MCD_OPC_Decode, 216, 3, 90, // Opcode: FCVTPUv1i64 -/* 38817 */ MCD_OPC_FilterValue, 46, 27, 0, // Skip to: 38848 -/* 38821 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38824 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38836 -/* 38828 */ MCD_OPC_CheckPredicate, 0, 17, 7, // Skip to: 40641 -/* 38832 */ MCD_OPC_Decode, 248, 8, 90, // Opcode: NEGv1i64 -/* 38836 */ MCD_OPC_FilterValue, 33, 9, 7, // Skip to: 40641 -/* 38840 */ MCD_OPC_CheckPredicate, 0, 5, 7, // Skip to: 40641 -/* 38844 */ MCD_OPC_Decode, 148, 4, 90, // Opcode: FCVTZUv1i64 -/* 38848 */ MCD_OPC_FilterValue, 50, 27, 0, // Skip to: 38879 -/* 38852 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38855 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38867 -/* 38859 */ MCD_OPC_CheckPredicate, 0, 242, 6, // Skip to: 40641 -/* 38863 */ MCD_OPC_Decode, 227, 2, 90, // Opcode: FCMGEv1i64rz -/* 38867 */ MCD_OPC_FilterValue, 48, 234, 6, // Skip to: 40641 -/* 38871 */ MCD_OPC_CheckPredicate, 0, 230, 6, // Skip to: 40641 -/* 38875 */ MCD_OPC_Decode, 189, 4, 95, // Opcode: FMINNMPv2i64p -/* 38879 */ MCD_OPC_FilterValue, 53, 14, 0, // Skip to: 38897 -/* 38883 */ MCD_OPC_CheckPredicate, 0, 218, 6, // Skip to: 40641 -/* 38887 */ MCD_OPC_CheckField, 21, 1, 1, 212, 6, // Skip to: 40641 -/* 38893 */ MCD_OPC_Decode, 181, 2, 89, // Opcode: FABD64 -/* 38897 */ MCD_OPC_FilterValue, 54, 27, 0, // Skip to: 38928 -/* 38901 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... -/* 38904 */ MCD_OPC_FilterValue, 32, 8, 0, // Skip to: 38916 -/* 38908 */ MCD_OPC_CheckPredicate, 0, 193, 6, // Skip to: 40641 -/* 38912 */ MCD_OPC_Decode, 245, 2, 90, // Opcode: FCMLEv1i64rz -/* 38916 */ MCD_OPC_FilterValue, 33, 185, 6, // Skip to: 40641 -/* 38920 */ MCD_OPC_CheckPredicate, 0, 181, 6, // Skip to: 40641 -/* 38924 */ MCD_OPC_Decode, 188, 5, 90, // Opcode: FRSQRTEv1i64 -/* 38928 */ MCD_OPC_FilterValue, 57, 14, 0, // Skip to: 38946 -/* 38932 */ MCD_OPC_CheckPredicate, 0, 169, 6, // Skip to: 40641 -/* 38936 */ MCD_OPC_CheckField, 21, 1, 1, 163, 6, // Skip to: 40641 -/* 38942 */ MCD_OPC_Decode, 235, 2, 89, // Opcode: FCMGT64 -/* 38946 */ MCD_OPC_FilterValue, 59, 14, 0, // Skip to: 38964 -/* 38950 */ MCD_OPC_CheckPredicate, 0, 151, 6, // Skip to: 40641 -/* 38954 */ MCD_OPC_CheckField, 21, 1, 1, 145, 6, // Skip to: 40641 -/* 38960 */ MCD_OPC_Decode, 196, 2, 89, // Opcode: FACGT64 -/* 38964 */ MCD_OPC_FilterValue, 62, 137, 6, // Skip to: 40641 -/* 38968 */ MCD_OPC_CheckPredicate, 0, 133, 6, // Skip to: 40641 -/* 38972 */ MCD_OPC_CheckField, 16, 6, 48, 127, 6, // Skip to: 40641 -/* 38978 */ MCD_OPC_Decode, 199, 4, 95, // Opcode: FMINPv2i64p -/* 38982 */ MCD_OPC_FilterValue, 12, 139, 1, // Skip to: 39381 -/* 38986 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 38989 */ MCD_OPC_FilterValue, 25, 55, 0, // Skip to: 39048 -/* 38993 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 38996 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39035 -/* 39000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 39003 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39022 -/* 39007 */ MCD_OPC_CheckPredicate, 0, 94, 6, // Skip to: 40641 -/* 39011 */ MCD_OPC_CheckField, 19, 1, 1, 88, 6, // Skip to: 40641 -/* 39017 */ MCD_OPC_Decode, 143, 12, 173, 2, // Opcode: SQSHLUb -/* 39022 */ MCD_OPC_FilterValue, 1, 79, 6, // Skip to: 40641 -/* 39026 */ MCD_OPC_CheckPredicate, 0, 75, 6, // Skip to: 40641 -/* 39030 */ MCD_OPC_Decode, 145, 12, 174, 2, // Opcode: SQSHLUh -/* 39035 */ MCD_OPC_FilterValue, 1, 66, 6, // Skip to: 40641 -/* 39039 */ MCD_OPC_CheckPredicate, 0, 62, 6, // Skip to: 40641 -/* 39043 */ MCD_OPC_Decode, 146, 12, 175, 2, // Opcode: SQSHLUs -/* 39048 */ MCD_OPC_FilterValue, 29, 55, 0, // Skip to: 39107 -/* 39052 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39055 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39094 -/* 39059 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 39062 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39081 -/* 39066 */ MCD_OPC_CheckPredicate, 0, 35, 6, // Skip to: 40641 -/* 39070 */ MCD_OPC_CheckField, 19, 1, 1, 29, 6, // Skip to: 40641 -/* 39076 */ MCD_OPC_Decode, 170, 17, 173, 2, // Opcode: UQSHLb -/* 39081 */ MCD_OPC_FilterValue, 1, 20, 6, // Skip to: 40641 -/* 39085 */ MCD_OPC_CheckPredicate, 0, 16, 6, // Skip to: 40641 -/* 39089 */ MCD_OPC_Decode, 172, 17, 174, 2, // Opcode: UQSHLh -/* 39094 */ MCD_OPC_FilterValue, 1, 7, 6, // Skip to: 40641 -/* 39098 */ MCD_OPC_CheckPredicate, 0, 3, 6, // Skip to: 40641 -/* 39102 */ MCD_OPC_Decode, 173, 17, 175, 2, // Opcode: UQSHLs -/* 39107 */ MCD_OPC_FilterValue, 33, 55, 0, // Skip to: 39166 -/* 39111 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39114 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39153 -/* 39118 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 39121 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39140 -/* 39125 */ MCD_OPC_CheckPredicate, 0, 232, 5, // Skip to: 40641 -/* 39129 */ MCD_OPC_CheckField, 19, 1, 1, 226, 5, // Skip to: 40641 -/* 39135 */ MCD_OPC_Decode, 185, 12, 176, 2, // Opcode: SQSHRUNb -/* 39140 */ MCD_OPC_FilterValue, 1, 217, 5, // Skip to: 40641 -/* 39144 */ MCD_OPC_CheckPredicate, 0, 213, 5, // Skip to: 40641 -/* 39148 */ MCD_OPC_Decode, 186, 12, 177, 2, // Opcode: SQSHRUNh -/* 39153 */ MCD_OPC_FilterValue, 1, 204, 5, // Skip to: 40641 -/* 39157 */ MCD_OPC_CheckPredicate, 0, 200, 5, // Skip to: 40641 -/* 39161 */ MCD_OPC_Decode, 187, 12, 178, 2, // Opcode: SQSHRUNs -/* 39166 */ MCD_OPC_FilterValue, 35, 55, 0, // Skip to: 39225 -/* 39170 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39173 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39212 -/* 39177 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 39180 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39199 -/* 39184 */ MCD_OPC_CheckPredicate, 0, 173, 5, // Skip to: 40641 -/* 39188 */ MCD_OPC_CheckField, 19, 1, 1, 167, 5, // Skip to: 40641 -/* 39194 */ MCD_OPC_Decode, 134, 12, 176, 2, // Opcode: SQRSHRUNb -/* 39199 */ MCD_OPC_FilterValue, 1, 158, 5, // Skip to: 40641 -/* 39203 */ MCD_OPC_CheckPredicate, 0, 154, 5, // Skip to: 40641 -/* 39207 */ MCD_OPC_Decode, 135, 12, 177, 2, // Opcode: SQRSHRUNh -/* 39212 */ MCD_OPC_FilterValue, 1, 145, 5, // Skip to: 40641 -/* 39216 */ MCD_OPC_CheckPredicate, 0, 141, 5, // Skip to: 40641 -/* 39220 */ MCD_OPC_Decode, 136, 12, 178, 2, // Opcode: SQRSHRUNs -/* 39225 */ MCD_OPC_FilterValue, 37, 55, 0, // Skip to: 39284 -/* 39229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39232 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39271 -/* 39236 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 39239 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39258 -/* 39243 */ MCD_OPC_CheckPredicate, 0, 114, 5, // Skip to: 40641 -/* 39247 */ MCD_OPC_CheckField, 19, 1, 1, 108, 5, // Skip to: 40641 -/* 39253 */ MCD_OPC_Decode, 192, 17, 176, 2, // Opcode: UQSHRNb -/* 39258 */ MCD_OPC_FilterValue, 1, 99, 5, // Skip to: 40641 -/* 39262 */ MCD_OPC_CheckPredicate, 0, 95, 5, // Skip to: 40641 -/* 39266 */ MCD_OPC_Decode, 193, 17, 177, 2, // Opcode: UQSHRNh -/* 39271 */ MCD_OPC_FilterValue, 1, 86, 5, // Skip to: 40641 -/* 39275 */ MCD_OPC_CheckPredicate, 0, 82, 5, // Skip to: 40641 -/* 39279 */ MCD_OPC_Decode, 194, 17, 178, 2, // Opcode: UQSHRNs -/* 39284 */ MCD_OPC_FilterValue, 39, 55, 0, // Skip to: 39343 -/* 39288 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... -/* 39291 */ MCD_OPC_FilterValue, 0, 35, 0, // Skip to: 39330 -/* 39295 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... -/* 39298 */ MCD_OPC_FilterValue, 0, 15, 0, // Skip to: 39317 -/* 39302 */ MCD_OPC_CheckPredicate, 0, 55, 5, // Skip to: 40641 -/* 39306 */ MCD_OPC_CheckField, 19, 1, 1, 49, 5, // Skip to: 40641 -/* 39312 */ MCD_OPC_Decode, 161, 17, 176, 2, // Opcode: UQRSHRNb -/* 39317 */ MCD_OPC_FilterValue, 1, 40, 5, // Skip to: 40641 -/* 39321 */ MCD_OPC_CheckPredicate, 0, 36, 5, // Skip to: 40641 -/* 39325 */ MCD_OPC_Decode, 162, 17, 177, 2, // Opcode: UQRSHRNh -/* 39330 */ MCD_OPC_FilterValue, 1, 27, 5, // Skip to: 40641 -/* 39334 */ MCD_OPC_CheckPredicate, 0, 23, 5, // Skip to: 40641 -/* 39338 */ MCD_OPC_Decode, 163, 17, 178, 2, // Opcode: UQRSHRNs -/* 39343 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 39362 -/* 39347 */ MCD_OPC_CheckPredicate, 0, 10, 5, // Skip to: 40641 -/* 39351 */ MCD_OPC_CheckField, 21, 1, 1, 4, 5, // Skip to: 40641 -/* 39357 */ MCD_OPC_Decode, 171, 16, 184, 2, // Opcode: UCVTFs -/* 39362 */ MCD_OPC_FilterValue, 63, 251, 4, // Skip to: 40641 -/* 39366 */ MCD_OPC_CheckPredicate, 0, 247, 4, // Skip to: 40641 -/* 39370 */ MCD_OPC_CheckField, 21, 1, 1, 241, 4, // Skip to: 40641 -/* 39376 */ MCD_OPC_Decode, 146, 4, 184, 2, // Opcode: FCVTZUs -/* 39381 */ MCD_OPC_FilterValue, 13, 133, 0, // Skip to: 39518 -/* 39385 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... -/* 39388 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 39401 -/* 39392 */ MCD_OPC_CheckPredicate, 0, 221, 4, // Skip to: 40641 -/* 39396 */ MCD_OPC_Decode, 141, 18, 166, 2, // Opcode: USHRd -/* 39401 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 39414 -/* 39405 */ MCD_OPC_CheckPredicate, 0, 208, 4, // Skip to: 40641 -/* 39409 */ MCD_OPC_Decode, 160, 18, 167, 2, // Opcode: USRAd -/* 39414 */ MCD_OPC_FilterValue, 9, 9, 0, // Skip to: 39427 -/* 39418 */ MCD_OPC_CheckPredicate, 0, 195, 4, // Skip to: 40641 -/* 39422 */ MCD_OPC_Decode, 237, 17, 166, 2, // Opcode: URSHRd -/* 39427 */ MCD_OPC_FilterValue, 13, 9, 0, // Skip to: 39440 -/* 39431 */ MCD_OPC_CheckPredicate, 0, 182, 4, // Skip to: 40641 -/* 39435 */ MCD_OPC_Decode, 247, 17, 167, 2, // Opcode: URSRAd -/* 39440 */ MCD_OPC_FilterValue, 17, 9, 0, // Skip to: 39453 -/* 39444 */ MCD_OPC_CheckPredicate, 0, 169, 4, // Skip to: 40641 -/* 39448 */ MCD_OPC_Decode, 229, 12, 167, 2, // Opcode: SRId -/* 39453 */ MCD_OPC_FilterValue, 21, 9, 0, // Skip to: 39466 -/* 39457 */ MCD_OPC_CheckPredicate, 0, 156, 4, // Skip to: 40641 -/* 39461 */ MCD_OPC_Decode, 196, 10, 187, 2, // Opcode: SLId -/* 39466 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 39479 -/* 39470 */ MCD_OPC_CheckPredicate, 0, 143, 4, // Skip to: 40641 -/* 39474 */ MCD_OPC_Decode, 144, 12, 172, 2, // Opcode: SQSHLUd -/* 39479 */ MCD_OPC_FilterValue, 29, 9, 0, // Skip to: 39492 -/* 39483 */ MCD_OPC_CheckPredicate, 0, 130, 4, // Skip to: 40641 -/* 39487 */ MCD_OPC_Decode, 171, 17, 172, 2, // Opcode: UQSHLd -/* 39492 */ MCD_OPC_FilterValue, 57, 9, 0, // Skip to: 39505 -/* 39496 */ MCD_OPC_CheckPredicate, 0, 117, 4, // Skip to: 40641 -/* 39500 */ MCD_OPC_Decode, 170, 16, 166, 2, // Opcode: UCVTFd -/* 39505 */ MCD_OPC_FilterValue, 63, 108, 4, // Skip to: 40641 -/* 39509 */ MCD_OPC_CheckPredicate, 0, 104, 4, // Skip to: 40641 -/* 39513 */ MCD_OPC_Decode, 145, 4, 166, 2, // Opcode: FCVTZUd -/* 39518 */ MCD_OPC_FilterValue, 14, 21, 0, // Skip to: 39543 -/* 39522 */ MCD_OPC_CheckPredicate, 0, 91, 4, // Skip to: 40641 -/* 39526 */ MCD_OPC_CheckField, 12, 4, 9, 85, 4, // Skip to: 40641 -/* 39532 */ MCD_OPC_CheckField, 10, 1, 0, 79, 4, // Skip to: 40641 -/* 39538 */ MCD_OPC_Decode, 241, 4, 179, 2, // Opcode: FMULXv1i32_indexed -/* 39543 */ MCD_OPC_FilterValue, 15, 70, 4, // Skip to: 40641 -/* 39547 */ MCD_OPC_CheckPredicate, 0, 66, 4, // Skip to: 40641 -/* 39551 */ MCD_OPC_CheckField, 21, 1, 0, 60, 4, // Skip to: 40641 -/* 39557 */ MCD_OPC_CheckField, 12, 4, 9, 54, 4, // Skip to: 40641 -/* 39563 */ MCD_OPC_CheckField, 10, 1, 0, 48, 4, // Skip to: 40641 -/* 39569 */ MCD_OPC_Decode, 242, 4, 180, 2, // Opcode: FMULXv1i64_indexed -/* 39574 */ MCD_OPC_FilterValue, 4, 145, 2, // Skip to: 40235 -/* 39578 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... -/* 39581 */ MCD_OPC_FilterValue, 0, 5, 0, // Skip to: 39590 -/* 39585 */ MCD_OPC_Decode, 224, 7, 188, 2, // Opcode: LDRQl -/* 39590 */ MCD_OPC_FilterValue, 2, 23, 4, // Skip to: 40641 -/* 39594 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... -/* 39597 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 39610 -/* 39601 */ MCD_OPC_CheckPredicate, 3, 12, 4, // Skip to: 40641 -/* 39605 */ MCD_OPC_Decode, 135, 10, 189, 2, // Opcode: SCVTFSXSri -/* 39610 */ MCD_OPC_FilterValue, 3, 9, 0, // Skip to: 39623 -/* 39614 */ MCD_OPC_CheckPredicate, 3, 255, 3, // Skip to: 40641 -/* 39618 */ MCD_OPC_Decode, 165, 16, 189, 2, // Opcode: UCVTFSXSri -/* 39623 */ MCD_OPC_FilterValue, 24, 9, 0, // Skip to: 39636 -/* 39627 */ MCD_OPC_CheckPredicate, 3, 242, 3, // Skip to: 40641 -/* 39631 */ MCD_OPC_Decode, 228, 3, 190, 2, // Opcode: FCVTZSSXSri -/* 39636 */ MCD_OPC_FilterValue, 25, 9, 0, // Skip to: 39649 -/* 39640 */ MCD_OPC_CheckPredicate, 3, 229, 3, // Skip to: 40641 -/* 39644 */ MCD_OPC_Decode, 129, 4, 190, 2, // Opcode: FCVTZUSXSri -/* 39649 */ MCD_OPC_FilterValue, 32, 15, 0, // Skip to: 39668 -/* 39653 */ MCD_OPC_CheckPredicate, 3, 216, 3, // Skip to: 40641 -/* 39657 */ MCD_OPC_CheckField, 10, 6, 0, 210, 3, // Skip to: 40641 -/* 39663 */ MCD_OPC_Decode, 183, 3, 191, 2, // Opcode: FCVTNSUXSr -/* 39668 */ MCD_OPC_FilterValue, 33, 15, 0, // Skip to: 39687 -/* 39672 */ MCD_OPC_CheckPredicate, 3, 197, 3, // Skip to: 40641 -/* 39676 */ MCD_OPC_CheckField, 10, 6, 0, 191, 3, // Skip to: 40641 -/* 39682 */ MCD_OPC_Decode, 192, 3, 191, 2, // Opcode: FCVTNUUXSr -/* 39687 */ MCD_OPC_FilterValue, 34, 15, 0, // Skip to: 39706 -/* 39691 */ MCD_OPC_CheckPredicate, 3, 178, 3, // Skip to: 40641 -/* 39695 */ MCD_OPC_CheckField, 10, 6, 0, 172, 3, // Skip to: 40641 -/* 39701 */ MCD_OPC_Decode, 139, 10, 192, 2, // Opcode: SCVTFUXSri -/* 39706 */ MCD_OPC_FilterValue, 35, 15, 0, // Skip to: 39725 -/* 39710 */ MCD_OPC_CheckPredicate, 3, 159, 3, // Skip to: 40641 -/* 39714 */ MCD_OPC_CheckField, 10, 6, 0, 153, 3, // Skip to: 40641 -/* 39720 */ MCD_OPC_Decode, 169, 16, 192, 2, // Opcode: UCVTFUXSri -/* 39725 */ MCD_OPC_FilterValue, 36, 15, 0, // Skip to: 39744 -/* 39729 */ MCD_OPC_CheckPredicate, 3, 140, 3, // Skip to: 40641 -/* 39733 */ MCD_OPC_CheckField, 10, 6, 0, 134, 3, // Skip to: 40641 -/* 39739 */ MCD_OPC_Decode, 139, 3, 191, 2, // Opcode: FCVTASUXSr -/* 39744 */ MCD_OPC_FilterValue, 37, 15, 0, // Skip to: 39763 -/* 39748 */ MCD_OPC_CheckPredicate, 3, 121, 3, // Skip to: 40641 -/* 39752 */ MCD_OPC_CheckField, 10, 6, 0, 115, 3, // Skip to: 40641 -/* 39758 */ MCD_OPC_Decode, 148, 3, 191, 2, // Opcode: FCVTAUUXSr -/* 39763 */ MCD_OPC_FilterValue, 40, 15, 0, // Skip to: 39782 -/* 39767 */ MCD_OPC_CheckPredicate, 3, 102, 3, // Skip to: 40641 -/* 39771 */ MCD_OPC_CheckField, 10, 6, 0, 96, 3, // Skip to: 40641 -/* 39777 */ MCD_OPC_Decode, 205, 3, 191, 2, // Opcode: FCVTPSUXSr -/* 39782 */ MCD_OPC_FilterValue, 41, 15, 0, // Skip to: 39801 -/* 39786 */ MCD_OPC_CheckPredicate, 3, 83, 3, // Skip to: 40641 -/* 39790 */ MCD_OPC_CheckField, 10, 6, 0, 77, 3, // Skip to: 40641 -/* 39796 */ MCD_OPC_Decode, 214, 3, 191, 2, // Opcode: FCVTPUUXSr -/* 39801 */ MCD_OPC_FilterValue, 48, 15, 0, // Skip to: 39820 -/* 39805 */ MCD_OPC_CheckPredicate, 3, 64, 3, // Skip to: 40641 -/* 39809 */ MCD_OPC_CheckField, 10, 6, 0, 58, 3, // Skip to: 40641 -/* 39815 */ MCD_OPC_Decode, 165, 3, 191, 2, // Opcode: FCVTMSUXSr -/* 39820 */ MCD_OPC_FilterValue, 49, 15, 0, // Skip to: 39839 -/* 39824 */ MCD_OPC_CheckPredicate, 3, 45, 3, // Skip to: 40641 -/* 39828 */ MCD_OPC_CheckField, 10, 6, 0, 39, 3, // Skip to: 40641 -/* 39834 */ MCD_OPC_Decode, 174, 3, 191, 2, // Opcode: FCVTMUUXSr -/* 39839 */ MCD_OPC_FilterValue, 56, 15, 0, // Skip to: 39858 -/* 39843 */ MCD_OPC_CheckPredicate, 3, 26, 3, // Skip to: 40641 -/* 39847 */ MCD_OPC_CheckField, 10, 6, 0, 20, 3, // Skip to: 40641 -/* 39853 */ MCD_OPC_Decode, 232, 3, 191, 2, // Opcode: FCVTZSUXSr -/* 39858 */ MCD_OPC_FilterValue, 57, 15, 0, // Skip to: 39877 -/* 39862 */ MCD_OPC_CheckPredicate, 3, 7, 3, // Skip to: 40641 -/* 39866 */ MCD_OPC_CheckField, 10, 6, 0, 1, 3, // Skip to: 40641 -/* 39872 */ MCD_OPC_Decode, 133, 4, 191, 2, // Opcode: FCVTZUUXSr -/* 39877 */ MCD_OPC_FilterValue, 66, 9, 0, // Skip to: 39890 -/* 39881 */ MCD_OPC_CheckPredicate, 3, 244, 2, // Skip to: 40641 -/* 39885 */ MCD_OPC_Decode, 134, 10, 193, 2, // Opcode: SCVTFSXDri -/* 39890 */ MCD_OPC_FilterValue, 67, 9, 0, // Skip to: 39903 -/* 39894 */ MCD_OPC_CheckPredicate, 3, 231, 2, // Skip to: 40641 -/* 39898 */ MCD_OPC_Decode, 164, 16, 193, 2, // Opcode: UCVTFSXDri -/* 39903 */ MCD_OPC_FilterValue, 88, 9, 0, // Skip to: 39916 -/* 39907 */ MCD_OPC_CheckPredicate, 3, 218, 2, // Skip to: 40641 -/* 39911 */ MCD_OPC_Decode, 227, 3, 194, 2, // Opcode: FCVTZSSXDri -/* 39916 */ MCD_OPC_FilterValue, 89, 9, 0, // Skip to: 39929 -/* 39920 */ MCD_OPC_CheckPredicate, 3, 205, 2, // Skip to: 40641 -/* 39924 */ MCD_OPC_Decode, 128, 4, 194, 2, // Opcode: FCVTZUSXDri -/* 39929 */ MCD_OPC_FilterValue, 96, 15, 0, // Skip to: 39948 -/* 39933 */ MCD_OPC_CheckPredicate, 3, 192, 2, // Skip to: 40641 -/* 39937 */ MCD_OPC_CheckField, 10, 6, 0, 186, 2, // Skip to: 40641 -/* 39943 */ MCD_OPC_Decode, 182, 3, 195, 2, // Opcode: FCVTNSUXDr -/* 39948 */ MCD_OPC_FilterValue, 97, 15, 0, // Skip to: 39967 -/* 39952 */ MCD_OPC_CheckPredicate, 3, 173, 2, // Skip to: 40641 -/* 39956 */ MCD_OPC_CheckField, 10, 6, 0, 167, 2, // Skip to: 40641 -/* 39962 */ MCD_OPC_Decode, 191, 3, 195, 2, // Opcode: FCVTNUUXDr -/* 39967 */ MCD_OPC_FilterValue, 98, 15, 0, // Skip to: 39986 -/* 39971 */ MCD_OPC_CheckPredicate, 3, 154, 2, // Skip to: 40641 -/* 39975 */ MCD_OPC_CheckField, 10, 6, 0, 148, 2, // Skip to: 40641 -/* 39981 */ MCD_OPC_Decode, 138, 10, 196, 2, // Opcode: SCVTFUXDri -/* 39986 */ MCD_OPC_FilterValue, 99, 15, 0, // Skip to: 40005 -/* 39990 */ MCD_OPC_CheckPredicate, 3, 135, 2, // Skip to: 40641 -/* 39994 */ MCD_OPC_CheckField, 10, 6, 0, 129, 2, // Skip to: 40641 -/* 40000 */ MCD_OPC_Decode, 168, 16, 196, 2, // Opcode: UCVTFUXDri -/* 40005 */ MCD_OPC_FilterValue, 100, 15, 0, // Skip to: 40024 -/* 40009 */ MCD_OPC_CheckPredicate, 3, 116, 2, // Skip to: 40641 -/* 40013 */ MCD_OPC_CheckField, 10, 6, 0, 110, 2, // Skip to: 40641 -/* 40019 */ MCD_OPC_Decode, 138, 3, 195, 2, // Opcode: FCVTASUXDr -/* 40024 */ MCD_OPC_FilterValue, 101, 15, 0, // Skip to: 40043 -/* 40028 */ MCD_OPC_CheckPredicate, 3, 97, 2, // Skip to: 40641 -/* 40032 */ MCD_OPC_CheckField, 10, 6, 0, 91, 2, // Skip to: 40641 -/* 40038 */ MCD_OPC_Decode, 147, 3, 195, 2, // Opcode: FCVTAUUXDr -/* 40043 */ MCD_OPC_FilterValue, 102, 15, 0, // Skip to: 40062 -/* 40047 */ MCD_OPC_CheckPredicate, 3, 78, 2, // Skip to: 40641 -/* 40051 */ MCD_OPC_CheckField, 10, 6, 0, 72, 2, // Skip to: 40641 -/* 40057 */ MCD_OPC_Decode, 223, 4, 195, 2, // Opcode: FMOVDXr -/* 40062 */ MCD_OPC_FilterValue, 103, 15, 0, // Skip to: 40081 -/* 40066 */ MCD_OPC_CheckPredicate, 3, 59, 2, // Skip to: 40641 -/* 40070 */ MCD_OPC_CheckField, 10, 6, 0, 53, 2, // Skip to: 40641 -/* 40076 */ MCD_OPC_Decode, 231, 4, 196, 2, // Opcode: FMOVXDr -/* 40081 */ MCD_OPC_FilterValue, 104, 15, 0, // Skip to: 40100 -/* 40085 */ MCD_OPC_CheckPredicate, 3, 40, 2, // Skip to: 40641 -/* 40089 */ MCD_OPC_CheckField, 10, 6, 0, 34, 2, // Skip to: 40641 -/* 40095 */ MCD_OPC_Decode, 204, 3, 195, 2, // Opcode: FCVTPSUXDr -/* 40100 */ MCD_OPC_FilterValue, 105, 15, 0, // Skip to: 40119 -/* 40104 */ MCD_OPC_CheckPredicate, 3, 21, 2, // Skip to: 40641 -/* 40108 */ MCD_OPC_CheckField, 10, 6, 0, 15, 2, // Skip to: 40641 -/* 40114 */ MCD_OPC_Decode, 213, 3, 195, 2, // Opcode: FCVTPUUXDr -/* 40119 */ MCD_OPC_FilterValue, 112, 15, 0, // Skip to: 40138 -/* 40123 */ MCD_OPC_CheckPredicate, 3, 2, 2, // Skip to: 40641 -/* 40127 */ MCD_OPC_CheckField, 10, 6, 0, 252, 1, // Skip to: 40641 -/* 40133 */ MCD_OPC_Decode, 164, 3, 195, 2, // Opcode: FCVTMSUXDr -/* 40138 */ MCD_OPC_FilterValue, 113, 15, 0, // Skip to: 40157 -/* 40142 */ MCD_OPC_CheckPredicate, 3, 239, 1, // Skip to: 40641 -/* 40146 */ MCD_OPC_CheckField, 10, 6, 0, 233, 1, // Skip to: 40641 -/* 40152 */ MCD_OPC_Decode, 173, 3, 195, 2, // Opcode: FCVTMUUXDr -/* 40157 */ MCD_OPC_FilterValue, 120, 15, 0, // Skip to: 40176 -/* 40161 */ MCD_OPC_CheckPredicate, 3, 220, 1, // Skip to: 40641 -/* 40165 */ MCD_OPC_CheckField, 10, 6, 0, 214, 1, // Skip to: 40641 -/* 40171 */ MCD_OPC_Decode, 231, 3, 195, 2, // Opcode: FCVTZSUXDr -/* 40176 */ MCD_OPC_FilterValue, 121, 15, 0, // Skip to: 40195 -/* 40180 */ MCD_OPC_CheckPredicate, 3, 201, 1, // Skip to: 40641 -/* 40184 */ MCD_OPC_CheckField, 10, 6, 0, 195, 1, // Skip to: 40641 -/* 40190 */ MCD_OPC_Decode, 132, 4, 195, 2, // Opcode: FCVTZUUXDr -/* 40195 */ MCD_OPC_FilterValue, 174, 1, 15, 0, // Skip to: 40215 -/* 40200 */ MCD_OPC_CheckPredicate, 3, 181, 1, // Skip to: 40641 -/* 40204 */ MCD_OPC_CheckField, 10, 6, 0, 175, 1, // Skip to: 40641 -/* 40210 */ MCD_OPC_Decode, 222, 4, 197, 2, // Opcode: FMOVDXHighr -/* 40215 */ MCD_OPC_FilterValue, 175, 1, 165, 1, // Skip to: 40641 -/* 40220 */ MCD_OPC_CheckPredicate, 3, 161, 1, // Skip to: 40641 -/* 40224 */ MCD_OPC_CheckField, 10, 6, 0, 155, 1, // Skip to: 40641 -/* 40230 */ MCD_OPC_Decode, 230, 4, 197, 2, // Opcode: FMOVXDHighr -/* 40235 */ MCD_OPC_FilterValue, 5, 199, 0, // Skip to: 40438 -/* 40239 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 40242 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 40331 -/* 40246 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 40249 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40264 -/* 40253 */ MCD_OPC_CheckField, 21, 1, 0, 126, 1, // Skip to: 40641 -/* 40259 */ MCD_OPC_Decode, 142, 15, 226, 1, // Opcode: STURSi -/* 40264 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40279 -/* 40268 */ MCD_OPC_CheckField, 21, 1, 0, 111, 1, // Skip to: 40641 -/* 40274 */ MCD_OPC_Decode, 245, 14, 226, 1, // Opcode: STRSpost -/* 40279 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40316 -/* 40283 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 40286 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40301 -/* 40290 */ MCD_OPC_CheckField, 21, 1, 1, 89, 1, // Skip to: 40641 -/* 40296 */ MCD_OPC_Decode, 247, 14, 198, 2, // Opcode: STRSroW -/* 40301 */ MCD_OPC_FilterValue, 3, 80, 1, // Skip to: 40641 -/* 40305 */ MCD_OPC_CheckField, 21, 1, 1, 74, 1, // Skip to: 40641 -/* 40311 */ MCD_OPC_Decode, 248, 14, 199, 2, // Opcode: STRSroX -/* 40316 */ MCD_OPC_FilterValue, 3, 65, 1, // Skip to: 40641 -/* 40320 */ MCD_OPC_CheckField, 21, 1, 0, 59, 1, // Skip to: 40641 -/* 40326 */ MCD_OPC_Decode, 246, 14, 226, 1, // Opcode: STRSpre -/* 40331 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 40420 -/* 40335 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 40338 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40353 -/* 40342 */ MCD_OPC_CheckField, 21, 1, 0, 37, 1, // Skip to: 40641 -/* 40348 */ MCD_OPC_Decode, 166, 8, 226, 1, // Opcode: LDURSi -/* 40353 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40368 -/* 40357 */ MCD_OPC_CheckField, 21, 1, 0, 22, 1, // Skip to: 40641 -/* 40363 */ MCD_OPC_Decode, 129, 8, 226, 1, // Opcode: LDRSpost -/* 40368 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40405 -/* 40372 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 40375 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40390 -/* 40379 */ MCD_OPC_CheckField, 21, 1, 1, 0, 1, // Skip to: 40641 -/* 40385 */ MCD_OPC_Decode, 131, 8, 198, 2, // Opcode: LDRSroW -/* 40390 */ MCD_OPC_FilterValue, 3, 247, 0, // Skip to: 40641 -/* 40394 */ MCD_OPC_CheckField, 21, 1, 1, 241, 0, // Skip to: 40641 -/* 40400 */ MCD_OPC_Decode, 132, 8, 199, 2, // Opcode: LDRSroX -/* 40405 */ MCD_OPC_FilterValue, 3, 232, 0, // Skip to: 40641 -/* 40409 */ MCD_OPC_CheckField, 21, 1, 0, 226, 0, // Skip to: 40641 -/* 40415 */ MCD_OPC_Decode, 130, 8, 226, 1, // Opcode: LDRSpre -/* 40420 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 40429 -/* 40424 */ MCD_OPC_Decode, 249, 14, 231, 1, // Opcode: STRSui -/* 40429 */ MCD_OPC_FilterValue, 5, 208, 0, // Skip to: 40641 -/* 40433 */ MCD_OPC_Decode, 133, 8, 231, 1, // Opcode: LDRSui -/* 40438 */ MCD_OPC_FilterValue, 7, 199, 0, // Skip to: 40641 -/* 40442 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... -/* 40445 */ MCD_OPC_FilterValue, 0, 85, 0, // Skip to: 40534 -/* 40449 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 40452 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40467 -/* 40456 */ MCD_OPC_CheckField, 21, 1, 0, 179, 0, // Skip to: 40641 -/* 40462 */ MCD_OPC_Decode, 138, 15, 226, 1, // Opcode: STURDi -/* 40467 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40482 -/* 40471 */ MCD_OPC_CheckField, 21, 1, 0, 164, 0, // Skip to: 40641 -/* 40477 */ MCD_OPC_Decode, 225, 14, 226, 1, // Opcode: STRDpost -/* 40482 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40519 -/* 40486 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 40489 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40504 -/* 40493 */ MCD_OPC_CheckField, 21, 1, 1, 142, 0, // Skip to: 40641 -/* 40499 */ MCD_OPC_Decode, 227, 14, 200, 2, // Opcode: STRDroW -/* 40504 */ MCD_OPC_FilterValue, 3, 133, 0, // Skip to: 40641 -/* 40508 */ MCD_OPC_CheckField, 21, 1, 1, 127, 0, // Skip to: 40641 -/* 40514 */ MCD_OPC_Decode, 228, 14, 201, 2, // Opcode: STRDroX -/* 40519 */ MCD_OPC_FilterValue, 3, 118, 0, // Skip to: 40641 -/* 40523 */ MCD_OPC_CheckField, 21, 1, 0, 112, 0, // Skip to: 40641 -/* 40529 */ MCD_OPC_Decode, 226, 14, 226, 1, // Opcode: STRDpre -/* 40534 */ MCD_OPC_FilterValue, 1, 85, 0, // Skip to: 40623 -/* 40538 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... -/* 40541 */ MCD_OPC_FilterValue, 0, 11, 0, // Skip to: 40556 -/* 40545 */ MCD_OPC_CheckField, 21, 1, 0, 90, 0, // Skip to: 40641 -/* 40551 */ MCD_OPC_Decode, 157, 8, 226, 1, // Opcode: LDURDi -/* 40556 */ MCD_OPC_FilterValue, 1, 11, 0, // Skip to: 40571 -/* 40560 */ MCD_OPC_CheckField, 21, 1, 0, 75, 0, // Skip to: 40641 -/* 40566 */ MCD_OPC_Decode, 209, 7, 226, 1, // Opcode: LDRDpost -/* 40571 */ MCD_OPC_FilterValue, 2, 33, 0, // Skip to: 40608 -/* 40575 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... -/* 40578 */ MCD_OPC_FilterValue, 2, 11, 0, // Skip to: 40593 -/* 40582 */ MCD_OPC_CheckField, 21, 1, 1, 53, 0, // Skip to: 40641 -/* 40588 */ MCD_OPC_Decode, 211, 7, 200, 2, // Opcode: LDRDroW -/* 40593 */ MCD_OPC_FilterValue, 3, 44, 0, // Skip to: 40641 -/* 40597 */ MCD_OPC_CheckField, 21, 1, 1, 38, 0, // Skip to: 40641 -/* 40603 */ MCD_OPC_Decode, 212, 7, 201, 2, // Opcode: LDRDroX -/* 40608 */ MCD_OPC_FilterValue, 3, 29, 0, // Skip to: 40641 -/* 40612 */ MCD_OPC_CheckField, 21, 1, 0, 23, 0, // Skip to: 40641 -/* 40618 */ MCD_OPC_Decode, 210, 7, 226, 1, // Opcode: LDRDpre -/* 40623 */ MCD_OPC_FilterValue, 4, 5, 0, // Skip to: 40632 -/* 40627 */ MCD_OPC_Decode, 229, 14, 231, 1, // Opcode: STRDui -/* 40632 */ MCD_OPC_FilterValue, 5, 5, 0, // Skip to: 40641 -/* 40636 */ MCD_OPC_Decode, 213, 7, 231, 1, // Opcode: LDRDui -/* 40641 */ MCD_OPC_Fail, +/* 3 */ MCD_OPC_FilterValue, 1, 215, 111, 0, // Skip to: 28639 +/* 8 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 11 */ MCD_OPC_FilterValue, 0, 120, 43, 0, // Skip to: 11144 +/* 16 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 19 */ MCD_OPC_FilterValue, 0, 209, 17, 0, // Skip to: 4585 +/* 24 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 27 */ MCD_OPC_FilterValue, 0, 22, 8, 0, // Skip to: 2102 +/* 32 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 35 */ MCD_OPC_FilterValue, 0, 67, 2, 0, // Skip to: 619 +/* 40 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 43 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 79 +/* 48 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 51 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 65 +/* 56 */ MCD_OPC_CheckPredicate, 0, 103, 83, 1, // Skip to: 86948 +/* 61 */ MCD_OPC_Decode, 185, 1, 0, // Opcode: ADD_ZPmZ_B +/* 65 */ MCD_OPC_FilterValue, 1, 94, 83, 1, // Skip to: 86948 +/* 70 */ MCD_OPC_CheckPredicate, 0, 89, 83, 1, // Skip to: 86948 +/* 75 */ MCD_OPC_Decode, 187, 1, 0, // Opcode: ADD_ZPmZ_H +/* 79 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 115 +/* 84 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 87 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 101 +/* 92 */ MCD_OPC_CheckPredicate, 0, 67, 83, 1, // Skip to: 86948 +/* 97 */ MCD_OPC_Decode, 247, 29, 0, // Opcode: SUB_ZPmZ_B +/* 101 */ MCD_OPC_FilterValue, 1, 58, 83, 1, // Skip to: 86948 +/* 106 */ MCD_OPC_CheckPredicate, 0, 53, 83, 1, // Skip to: 86948 +/* 111 */ MCD_OPC_Decode, 249, 29, 0, // Opcode: SUB_ZPmZ_H +/* 115 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 151 +/* 120 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 123 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 137 +/* 128 */ MCD_OPC_CheckPredicate, 0, 31, 83, 1, // Skip to: 86948 +/* 133 */ MCD_OPC_Decode, 221, 29, 0, // Opcode: SUBR_ZPmZ_B +/* 137 */ MCD_OPC_FilterValue, 1, 22, 83, 1, // Skip to: 86948 +/* 142 */ MCD_OPC_CheckPredicate, 0, 17, 83, 1, // Skip to: 86948 +/* 147 */ MCD_OPC_Decode, 223, 29, 0, // Opcode: SUBR_ZPmZ_H +/* 151 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 187 +/* 156 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 159 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 173 +/* 164 */ MCD_OPC_CheckPredicate, 0, 251, 82, 1, // Skip to: 86948 +/* 169 */ MCD_OPC_Decode, 196, 23, 0, // Opcode: SMAX_ZPmZ_B +/* 173 */ MCD_OPC_FilterValue, 1, 242, 82, 1, // Skip to: 86948 +/* 178 */ MCD_OPC_CheckPredicate, 0, 237, 82, 1, // Skip to: 86948 +/* 183 */ MCD_OPC_Decode, 198, 23, 0, // Opcode: SMAX_ZPmZ_H +/* 187 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 223 +/* 192 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 195 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 209 +/* 200 */ MCD_OPC_CheckPredicate, 0, 215, 82, 1, // Skip to: 86948 +/* 205 */ MCD_OPC_Decode, 252, 31, 0, // Opcode: UMAX_ZPmZ_B +/* 209 */ MCD_OPC_FilterValue, 1, 206, 82, 1, // Skip to: 86948 +/* 214 */ MCD_OPC_CheckPredicate, 0, 201, 82, 1, // Skip to: 86948 +/* 219 */ MCD_OPC_Decode, 254, 31, 0, // Opcode: UMAX_ZPmZ_H +/* 223 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 259 +/* 228 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 231 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 245 +/* 236 */ MCD_OPC_CheckPredicate, 0, 179, 82, 1, // Skip to: 86948 +/* 241 */ MCD_OPC_Decode, 226, 23, 0, // Opcode: SMIN_ZPmZ_B +/* 245 */ MCD_OPC_FilterValue, 1, 170, 82, 1, // Skip to: 86948 +/* 250 */ MCD_OPC_CheckPredicate, 0, 165, 82, 1, // Skip to: 86948 +/* 255 */ MCD_OPC_Decode, 228, 23, 0, // Opcode: SMIN_ZPmZ_H +/* 259 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 295 +/* 264 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 267 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 281 +/* 272 */ MCD_OPC_CheckPredicate, 0, 143, 82, 1, // Skip to: 86948 +/* 277 */ MCD_OPC_Decode, 153, 32, 0, // Opcode: UMIN_ZPmZ_B +/* 281 */ MCD_OPC_FilterValue, 1, 134, 82, 1, // Skip to: 86948 +/* 286 */ MCD_OPC_CheckPredicate, 0, 129, 82, 1, // Skip to: 86948 +/* 291 */ MCD_OPC_Decode, 155, 32, 0, // Opcode: UMIN_ZPmZ_H +/* 295 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 331 +/* 300 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 303 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 317 +/* 308 */ MCD_OPC_CheckPredicate, 0, 107, 82, 1, // Skip to: 86948 +/* 313 */ MCD_OPC_Decode, 136, 22, 0, // Opcode: SABD_ZPmZ_B +/* 317 */ MCD_OPC_FilterValue, 1, 98, 82, 1, // Skip to: 86948 +/* 322 */ MCD_OPC_CheckPredicate, 0, 93, 82, 1, // Skip to: 86948 +/* 327 */ MCD_OPC_Decode, 138, 22, 0, // Opcode: SABD_ZPmZ_H +/* 331 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 367 +/* 336 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 339 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 353 +/* 344 */ MCD_OPC_CheckPredicate, 0, 71, 82, 1, // Skip to: 86948 +/* 349 */ MCD_OPC_Decode, 254, 30, 0, // Opcode: UABD_ZPmZ_B +/* 353 */ MCD_OPC_FilterValue, 1, 62, 82, 1, // Skip to: 86948 +/* 358 */ MCD_OPC_CheckPredicate, 0, 57, 82, 1, // Skip to: 86948 +/* 363 */ MCD_OPC_Decode, 128, 31, 0, // Opcode: UABD_ZPmZ_H +/* 367 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 403 +/* 372 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 375 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 389 +/* 380 */ MCD_OPC_CheckPredicate, 0, 35, 82, 1, // Skip to: 86948 +/* 385 */ MCD_OPC_Decode, 153, 20, 0, // Opcode: MUL_ZPmZ_B +/* 389 */ MCD_OPC_FilterValue, 1, 26, 82, 1, // Skip to: 86948 +/* 394 */ MCD_OPC_CheckPredicate, 0, 21, 82, 1, // Skip to: 86948 +/* 399 */ MCD_OPC_Decode, 155, 20, 0, // Opcode: MUL_ZPmZ_H +/* 403 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 439 +/* 408 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 411 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 425 +/* 416 */ MCD_OPC_CheckPredicate, 0, 255, 81, 1, // Skip to: 86948 +/* 421 */ MCD_OPC_Decode, 134, 24, 0, // Opcode: SMULH_ZPmZ_B +/* 425 */ MCD_OPC_FilterValue, 1, 246, 81, 1, // Skip to: 86948 +/* 430 */ MCD_OPC_CheckPredicate, 0, 241, 81, 1, // Skip to: 86948 +/* 435 */ MCD_OPC_Decode, 136, 24, 0, // Opcode: SMULH_ZPmZ_H +/* 439 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 475 +/* 444 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 447 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 461 +/* 452 */ MCD_OPC_CheckPredicate, 0, 219, 81, 1, // Skip to: 86948 +/* 457 */ MCD_OPC_Decode, 188, 32, 0, // Opcode: UMULH_ZPmZ_B +/* 461 */ MCD_OPC_FilterValue, 1, 210, 81, 1, // Skip to: 86948 +/* 466 */ MCD_OPC_CheckPredicate, 0, 205, 81, 1, // Skip to: 86948 +/* 471 */ MCD_OPC_Decode, 190, 32, 0, // Opcode: UMULH_ZPmZ_H +/* 475 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 511 +/* 480 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 483 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 497 +/* 488 */ MCD_OPC_CheckPredicate, 0, 183, 81, 1, // Skip to: 86948 +/* 493 */ MCD_OPC_Decode, 212, 20, 0, // Opcode: ORR_ZPmZ_B +/* 497 */ MCD_OPC_FilterValue, 1, 174, 81, 1, // Skip to: 86948 +/* 502 */ MCD_OPC_CheckPredicate, 0, 169, 81, 1, // Skip to: 86948 +/* 507 */ MCD_OPC_Decode, 214, 20, 0, // Opcode: ORR_ZPmZ_H +/* 511 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 547 +/* 516 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 519 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 533 +/* 524 */ MCD_OPC_CheckPredicate, 0, 147, 81, 1, // Skip to: 86948 +/* 529 */ MCD_OPC_Decode, 240, 5, 0, // Opcode: EOR_ZPmZ_B +/* 533 */ MCD_OPC_FilterValue, 1, 138, 81, 1, // Skip to: 86948 +/* 538 */ MCD_OPC_CheckPredicate, 0, 133, 81, 1, // Skip to: 86948 +/* 543 */ MCD_OPC_Decode, 242, 5, 0, // Opcode: EOR_ZPmZ_H +/* 547 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 583 +/* 552 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 555 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 569 +/* 560 */ MCD_OPC_CheckPredicate, 0, 111, 81, 1, // Skip to: 86948 +/* 565 */ MCD_OPC_Decode, 247, 1, 0, // Opcode: AND_ZPmZ_B +/* 569 */ MCD_OPC_FilterValue, 1, 102, 81, 1, // Skip to: 86948 +/* 574 */ MCD_OPC_CheckPredicate, 0, 97, 81, 1, // Skip to: 86948 +/* 579 */ MCD_OPC_Decode, 249, 1, 0, // Opcode: AND_ZPmZ_H +/* 583 */ MCD_OPC_FilterValue, 27, 88, 81, 1, // Skip to: 86948 +/* 588 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 591 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 605 +/* 596 */ MCD_OPC_CheckPredicate, 0, 75, 81, 1, // Skip to: 86948 +/* 601 */ MCD_OPC_Decode, 182, 2, 0, // Opcode: BIC_ZPmZ_B +/* 605 */ MCD_OPC_FilterValue, 1, 66, 81, 1, // Skip to: 86948 +/* 610 */ MCD_OPC_CheckPredicate, 0, 61, 81, 1, // Skip to: 86948 +/* 615 */ MCD_OPC_Decode, 184, 2, 0, // Opcode: BIC_ZPmZ_H +/* 619 */ MCD_OPC_FilterValue, 1, 143, 1, 0, // Skip to: 1023 +/* 624 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 627 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 663 +/* 632 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 635 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 649 +/* 640 */ MCD_OPC_CheckPredicate, 0, 31, 81, 1, // Skip to: 86948 +/* 645 */ MCD_OPC_Decode, 169, 22, 1, // Opcode: SADDV_VPZ_B +/* 649 */ MCD_OPC_FilterValue, 1, 22, 81, 1, // Skip to: 86948 +/* 654 */ MCD_OPC_CheckPredicate, 0, 17, 81, 1, // Skip to: 86948 +/* 659 */ MCD_OPC_Decode, 170, 22, 1, // Opcode: SADDV_VPZ_H +/* 663 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 699 +/* 668 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 671 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 685 +/* 676 */ MCD_OPC_CheckPredicate, 0, 251, 80, 1, // Skip to: 86948 +/* 681 */ MCD_OPC_Decode, 159, 31, 1, // Opcode: UADDV_VPZ_B +/* 685 */ MCD_OPC_FilterValue, 1, 242, 80, 1, // Skip to: 86948 +/* 690 */ MCD_OPC_CheckPredicate, 0, 237, 80, 1, // Skip to: 86948 +/* 695 */ MCD_OPC_Decode, 161, 31, 1, // Opcode: UADDV_VPZ_H +/* 699 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 735 +/* 704 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 707 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 721 +/* 712 */ MCD_OPC_CheckPredicate, 0, 215, 80, 1, // Skip to: 86948 +/* 717 */ MCD_OPC_Decode, 183, 23, 2, // Opcode: SMAXV_VPZ_B +/* 721 */ MCD_OPC_FilterValue, 1, 206, 80, 1, // Skip to: 86948 +/* 726 */ MCD_OPC_CheckPredicate, 0, 201, 80, 1, // Skip to: 86948 +/* 731 */ MCD_OPC_Decode, 185, 23, 3, // Opcode: SMAXV_VPZ_H +/* 735 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 771 +/* 740 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 743 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 757 +/* 748 */ MCD_OPC_CheckPredicate, 0, 179, 80, 1, // Skip to: 86948 +/* 753 */ MCD_OPC_Decode, 239, 31, 2, // Opcode: UMAXV_VPZ_B +/* 757 */ MCD_OPC_FilterValue, 1, 170, 80, 1, // Skip to: 86948 +/* 762 */ MCD_OPC_CheckPredicate, 0, 165, 80, 1, // Skip to: 86948 +/* 767 */ MCD_OPC_Decode, 241, 31, 3, // Opcode: UMAXV_VPZ_H +/* 771 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 807 +/* 776 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 779 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 793 +/* 784 */ MCD_OPC_CheckPredicate, 0, 143, 80, 1, // Skip to: 86948 +/* 789 */ MCD_OPC_Decode, 213, 23, 2, // Opcode: SMINV_VPZ_B +/* 793 */ MCD_OPC_FilterValue, 1, 134, 80, 1, // Skip to: 86948 +/* 798 */ MCD_OPC_CheckPredicate, 0, 129, 80, 1, // Skip to: 86948 +/* 803 */ MCD_OPC_Decode, 215, 23, 3, // Opcode: SMINV_VPZ_H +/* 807 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 843 +/* 812 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 815 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 829 +/* 820 */ MCD_OPC_CheckPredicate, 0, 107, 80, 1, // Skip to: 86948 +/* 825 */ MCD_OPC_Decode, 140, 32, 2, // Opcode: UMINV_VPZ_B +/* 829 */ MCD_OPC_FilterValue, 1, 98, 80, 1, // Skip to: 86948 +/* 834 */ MCD_OPC_CheckPredicate, 0, 93, 80, 1, // Skip to: 86948 +/* 839 */ MCD_OPC_Decode, 142, 32, 3, // Opcode: UMINV_VPZ_H +/* 843 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 879 +/* 848 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 851 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 865 +/* 856 */ MCD_OPC_CheckPredicate, 0, 71, 80, 1, // Skip to: 86948 +/* 861 */ MCD_OPC_Decode, 251, 19, 4, // Opcode: MOVPRFX_ZPzZ_B +/* 865 */ MCD_OPC_FilterValue, 1, 62, 80, 1, // Skip to: 86948 +/* 870 */ MCD_OPC_CheckPredicate, 0, 57, 80, 1, // Skip to: 86948 +/* 875 */ MCD_OPC_Decode, 253, 19, 4, // Opcode: MOVPRFX_ZPzZ_H +/* 879 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 915 +/* 884 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 887 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 901 +/* 892 */ MCD_OPC_CheckPredicate, 0, 35, 80, 1, // Skip to: 86948 +/* 897 */ MCD_OPC_Decode, 247, 19, 5, // Opcode: MOVPRFX_ZPmZ_B +/* 901 */ MCD_OPC_FilterValue, 1, 26, 80, 1, // Skip to: 86948 +/* 906 */ MCD_OPC_CheckPredicate, 0, 21, 80, 1, // Skip to: 86948 +/* 911 */ MCD_OPC_Decode, 249, 19, 5, // Opcode: MOVPRFX_ZPmZ_H +/* 915 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 951 +/* 920 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 923 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 937 +/* 928 */ MCD_OPC_CheckPredicate, 0, 255, 79, 1, // Skip to: 86948 +/* 933 */ MCD_OPC_Decode, 223, 20, 2, // Opcode: ORV_VPZ_B +/* 937 */ MCD_OPC_FilterValue, 1, 246, 79, 1, // Skip to: 86948 +/* 942 */ MCD_OPC_CheckPredicate, 0, 241, 79, 1, // Skip to: 86948 +/* 947 */ MCD_OPC_Decode, 225, 20, 3, // Opcode: ORV_VPZ_H +/* 951 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 987 +/* 956 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 959 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 973 +/* 964 */ MCD_OPC_CheckPredicate, 0, 219, 79, 1, // Skip to: 86948 +/* 969 */ MCD_OPC_Decode, 228, 5, 2, // Opcode: EORV_VPZ_B +/* 973 */ MCD_OPC_FilterValue, 1, 210, 79, 1, // Skip to: 86948 +/* 978 */ MCD_OPC_CheckPredicate, 0, 205, 79, 1, // Skip to: 86948 +/* 983 */ MCD_OPC_Decode, 230, 5, 3, // Opcode: EORV_VPZ_H +/* 987 */ MCD_OPC_FilterValue, 26, 196, 79, 1, // Skip to: 86948 +/* 992 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 995 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1009 +/* 1000 */ MCD_OPC_CheckPredicate, 0, 183, 79, 1, // Skip to: 86948 +/* 1005 */ MCD_OPC_Decode, 235, 1, 2, // Opcode: ANDV_VPZ_B +/* 1009 */ MCD_OPC_FilterValue, 1, 174, 79, 1, // Skip to: 86948 +/* 1014 */ MCD_OPC_CheckPredicate, 0, 169, 79, 1, // Skip to: 86948 +/* 1019 */ MCD_OPC_Decode, 237, 1, 3, // Opcode: ANDV_VPZ_H +/* 1023 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 1059 +/* 1028 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1031 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1045 +/* 1036 */ MCD_OPC_CheckPredicate, 0, 147, 79, 1, // Skip to: 86948 +/* 1041 */ MCD_OPC_Decode, 205, 19, 6, // Opcode: MLA_ZPmZZ_B +/* 1045 */ MCD_OPC_FilterValue, 1, 138, 79, 1, // Skip to: 86948 +/* 1050 */ MCD_OPC_CheckPredicate, 0, 133, 79, 1, // Skip to: 86948 +/* 1055 */ MCD_OPC_Decode, 207, 19, 6, // Opcode: MLA_ZPmZZ_H +/* 1059 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 1095 +/* 1064 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1067 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1081 +/* 1072 */ MCD_OPC_CheckPredicate, 0, 111, 79, 1, // Skip to: 86948 +/* 1077 */ MCD_OPC_Decode, 219, 19, 6, // Opcode: MLS_ZPmZZ_B +/* 1081 */ MCD_OPC_FilterValue, 1, 102, 79, 1, // Skip to: 86948 +/* 1086 */ MCD_OPC_CheckPredicate, 0, 97, 79, 1, // Skip to: 86948 +/* 1091 */ MCD_OPC_Decode, 221, 19, 6, // Opcode: MLS_ZPmZZ_H +/* 1095 */ MCD_OPC_FilterValue, 4, 75, 2, 0, // Skip to: 1687 +/* 1100 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 1103 */ MCD_OPC_FilterValue, 0, 60, 0, 0, // Skip to: 1168 +/* 1108 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1111 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1154 +/* 1116 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 1119 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1140 +/* 1124 */ MCD_OPC_CheckPredicate, 0, 59, 79, 1, // Skip to: 86948 +/* 1129 */ MCD_OPC_CheckField, 8, 1, 1, 52, 79, 1, // Skip to: 86948 +/* 1136 */ MCD_OPC_Decode, 142, 2, 7, // Opcode: ASR_ZPmI_B +/* 1140 */ MCD_OPC_FilterValue, 1, 43, 79, 1, // Skip to: 86948 +/* 1145 */ MCD_OPC_CheckPredicate, 0, 38, 79, 1, // Skip to: 86948 +/* 1150 */ MCD_OPC_Decode, 144, 2, 8, // Opcode: ASR_ZPmI_H +/* 1154 */ MCD_OPC_FilterValue, 1, 29, 79, 1, // Skip to: 86948 +/* 1159 */ MCD_OPC_CheckPredicate, 0, 24, 79, 1, // Skip to: 86948 +/* 1164 */ MCD_OPC_Decode, 145, 2, 9, // Opcode: ASR_ZPmI_S +/* 1168 */ MCD_OPC_FilterValue, 1, 60, 0, 0, // Skip to: 1233 +/* 1173 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1176 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1219 +/* 1181 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 1184 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1205 +/* 1189 */ MCD_OPC_CheckPredicate, 0, 250, 78, 1, // Skip to: 86948 +/* 1194 */ MCD_OPC_CheckField, 8, 1, 1, 243, 78, 1, // Skip to: 86948 +/* 1201 */ MCD_OPC_Decode, 187, 19, 7, // Opcode: LSR_ZPmI_B +/* 1205 */ MCD_OPC_FilterValue, 1, 234, 78, 1, // Skip to: 86948 +/* 1210 */ MCD_OPC_CheckPredicate, 0, 229, 78, 1, // Skip to: 86948 +/* 1215 */ MCD_OPC_Decode, 189, 19, 8, // Opcode: LSR_ZPmI_H +/* 1219 */ MCD_OPC_FilterValue, 1, 220, 78, 1, // Skip to: 86948 +/* 1224 */ MCD_OPC_CheckPredicate, 0, 215, 78, 1, // Skip to: 86948 +/* 1229 */ MCD_OPC_Decode, 190, 19, 9, // Opcode: LSR_ZPmI_S +/* 1233 */ MCD_OPC_FilterValue, 3, 60, 0, 0, // Skip to: 1298 +/* 1238 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1241 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1284 +/* 1246 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 1249 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1270 +/* 1254 */ MCD_OPC_CheckPredicate, 0, 185, 78, 1, // Skip to: 86948 +/* 1259 */ MCD_OPC_CheckField, 8, 1, 1, 178, 78, 1, // Skip to: 86948 +/* 1266 */ MCD_OPC_Decode, 163, 19, 10, // Opcode: LSL_ZPmI_B +/* 1270 */ MCD_OPC_FilterValue, 1, 169, 78, 1, // Skip to: 86948 +/* 1275 */ MCD_OPC_CheckPredicate, 0, 164, 78, 1, // Skip to: 86948 +/* 1280 */ MCD_OPC_Decode, 165, 19, 11, // Opcode: LSL_ZPmI_H +/* 1284 */ MCD_OPC_FilterValue, 1, 155, 78, 1, // Skip to: 86948 +/* 1289 */ MCD_OPC_CheckPredicate, 0, 150, 78, 1, // Skip to: 86948 +/* 1294 */ MCD_OPC_Decode, 166, 19, 12, // Opcode: LSL_ZPmI_S +/* 1298 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 1363 +/* 1303 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1306 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 1349 +/* 1311 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 1314 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 1335 +/* 1319 */ MCD_OPC_CheckPredicate, 0, 120, 78, 1, // Skip to: 86948 +/* 1324 */ MCD_OPC_CheckField, 8, 1, 1, 113, 78, 1, // Skip to: 86948 +/* 1331 */ MCD_OPC_Decode, 254, 1, 7, // Opcode: ASRD_ZPmI_B +/* 1335 */ MCD_OPC_FilterValue, 1, 104, 78, 1, // Skip to: 86948 +/* 1340 */ MCD_OPC_CheckPredicate, 0, 99, 78, 1, // Skip to: 86948 +/* 1345 */ MCD_OPC_Decode, 128, 2, 8, // Opcode: ASRD_ZPmI_H +/* 1349 */ MCD_OPC_FilterValue, 1, 90, 78, 1, // Skip to: 86948 +/* 1354 */ MCD_OPC_CheckPredicate, 0, 85, 78, 1, // Skip to: 86948 +/* 1359 */ MCD_OPC_Decode, 129, 2, 9, // Opcode: ASRD_ZPmI_S +/* 1363 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 1399 +/* 1368 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1385 +/* 1376 */ MCD_OPC_CheckPredicate, 0, 63, 78, 1, // Skip to: 86948 +/* 1381 */ MCD_OPC_Decode, 146, 2, 0, // Opcode: ASR_ZPmZ_B +/* 1385 */ MCD_OPC_FilterValue, 1, 54, 78, 1, // Skip to: 86948 +/* 1390 */ MCD_OPC_CheckPredicate, 0, 49, 78, 1, // Skip to: 86948 +/* 1395 */ MCD_OPC_Decode, 148, 2, 0, // Opcode: ASR_ZPmZ_H +/* 1399 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 1435 +/* 1404 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1421 +/* 1412 */ MCD_OPC_CheckPredicate, 0, 27, 78, 1, // Skip to: 86948 +/* 1417 */ MCD_OPC_Decode, 191, 19, 0, // Opcode: LSR_ZPmZ_B +/* 1421 */ MCD_OPC_FilterValue, 1, 18, 78, 1, // Skip to: 86948 +/* 1426 */ MCD_OPC_CheckPredicate, 0, 13, 78, 1, // Skip to: 86948 +/* 1431 */ MCD_OPC_Decode, 193, 19, 0, // Opcode: LSR_ZPmZ_H +/* 1435 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 1471 +/* 1440 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1443 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1457 +/* 1448 */ MCD_OPC_CheckPredicate, 0, 247, 77, 1, // Skip to: 86948 +/* 1453 */ MCD_OPC_Decode, 167, 19, 0, // Opcode: LSL_ZPmZ_B +/* 1457 */ MCD_OPC_FilterValue, 1, 238, 77, 1, // Skip to: 86948 +/* 1462 */ MCD_OPC_CheckPredicate, 0, 233, 77, 1, // Skip to: 86948 +/* 1467 */ MCD_OPC_Decode, 169, 19, 0, // Opcode: LSL_ZPmZ_H +/* 1471 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 1507 +/* 1476 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1479 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1493 +/* 1484 */ MCD_OPC_CheckPredicate, 0, 211, 77, 1, // Skip to: 86948 +/* 1489 */ MCD_OPC_Decode, 130, 2, 0, // Opcode: ASRR_ZPmZ_B +/* 1493 */ MCD_OPC_FilterValue, 1, 202, 77, 1, // Skip to: 86948 +/* 1498 */ MCD_OPC_CheckPredicate, 0, 197, 77, 1, // Skip to: 86948 +/* 1503 */ MCD_OPC_Decode, 132, 2, 0, // Opcode: ASRR_ZPmZ_H +/* 1507 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 1543 +/* 1512 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1515 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1529 +/* 1520 */ MCD_OPC_CheckPredicate, 0, 175, 77, 1, // Skip to: 86948 +/* 1525 */ MCD_OPC_Decode, 175, 19, 0, // Opcode: LSRR_ZPmZ_B +/* 1529 */ MCD_OPC_FilterValue, 1, 166, 77, 1, // Skip to: 86948 +/* 1534 */ MCD_OPC_CheckPredicate, 0, 161, 77, 1, // Skip to: 86948 +/* 1539 */ MCD_OPC_Decode, 177, 19, 0, // Opcode: LSRR_ZPmZ_H +/* 1543 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 1579 +/* 1548 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1551 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1565 +/* 1556 */ MCD_OPC_CheckPredicate, 0, 139, 77, 1, // Skip to: 86948 +/* 1561 */ MCD_OPC_Decode, 151, 19, 0, // Opcode: LSLR_ZPmZ_B +/* 1565 */ MCD_OPC_FilterValue, 1, 130, 77, 1, // Skip to: 86948 +/* 1570 */ MCD_OPC_CheckPredicate, 0, 125, 77, 1, // Skip to: 86948 +/* 1575 */ MCD_OPC_Decode, 153, 19, 0, // Opcode: LSLR_ZPmZ_H +/* 1579 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1615 +/* 1584 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1587 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1601 +/* 1592 */ MCD_OPC_CheckPredicate, 0, 103, 77, 1, // Skip to: 86948 +/* 1597 */ MCD_OPC_Decode, 136, 2, 0, // Opcode: ASR_WIDE_ZPmZ_B +/* 1601 */ MCD_OPC_FilterValue, 1, 94, 77, 1, // Skip to: 86948 +/* 1606 */ MCD_OPC_CheckPredicate, 0, 89, 77, 1, // Skip to: 86948 +/* 1611 */ MCD_OPC_Decode, 137, 2, 0, // Opcode: ASR_WIDE_ZPmZ_H +/* 1615 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 1651 +/* 1620 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1623 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1637 +/* 1628 */ MCD_OPC_CheckPredicate, 0, 67, 77, 1, // Skip to: 86948 +/* 1633 */ MCD_OPC_Decode, 181, 19, 0, // Opcode: LSR_WIDE_ZPmZ_B +/* 1637 */ MCD_OPC_FilterValue, 1, 58, 77, 1, // Skip to: 86948 +/* 1642 */ MCD_OPC_CheckPredicate, 0, 53, 77, 1, // Skip to: 86948 +/* 1647 */ MCD_OPC_Decode, 182, 19, 0, // Opcode: LSR_WIDE_ZPmZ_H +/* 1651 */ MCD_OPC_FilterValue, 27, 44, 77, 1, // Skip to: 86948 +/* 1656 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1659 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1673 +/* 1664 */ MCD_OPC_CheckPredicate, 0, 31, 77, 1, // Skip to: 86948 +/* 1669 */ MCD_OPC_Decode, 157, 19, 0, // Opcode: LSL_WIDE_ZPmZ_B +/* 1673 */ MCD_OPC_FilterValue, 1, 22, 77, 1, // Skip to: 86948 +/* 1678 */ MCD_OPC_CheckPredicate, 0, 17, 77, 1, // Skip to: 86948 +/* 1683 */ MCD_OPC_Decode, 158, 19, 0, // Opcode: LSL_WIDE_ZPmZ_H +/* 1687 */ MCD_OPC_FilterValue, 5, 82, 1, 0, // Skip to: 2030 +/* 1692 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 1695 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 1716 +/* 1700 */ MCD_OPC_CheckPredicate, 0, 251, 76, 1, // Skip to: 86948 +/* 1705 */ MCD_OPC_CheckField, 22, 1, 1, 244, 76, 1, // Skip to: 86948 +/* 1712 */ MCD_OPC_Decode, 170, 30, 5, // Opcode: SXTB_ZPmZ_H +/* 1716 */ MCD_OPC_FilterValue, 17, 16, 0, 0, // Skip to: 1737 +/* 1721 */ MCD_OPC_CheckPredicate, 0, 230, 76, 1, // Skip to: 86948 +/* 1726 */ MCD_OPC_CheckField, 22, 1, 1, 223, 76, 1, // Skip to: 86948 +/* 1733 */ MCD_OPC_Decode, 183, 34, 5, // Opcode: UXTB_ZPmZ_H +/* 1737 */ MCD_OPC_FilterValue, 22, 30, 0, 0, // Skip to: 1772 +/* 1742 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1745 */ MCD_OPC_FilterValue, 0, 8, 0, 0, // Skip to: 1758 +/* 1750 */ MCD_OPC_CheckPredicate, 0, 201, 76, 1, // Skip to: 86948 +/* 1755 */ MCD_OPC_Decode, 126, 5, // Opcode: ABS_ZPmZ_B +/* 1758 */ MCD_OPC_FilterValue, 1, 193, 76, 1, // Skip to: 86948 +/* 1763 */ MCD_OPC_CheckPredicate, 0, 188, 76, 1, // Skip to: 86948 +/* 1768 */ MCD_OPC_Decode, 128, 1, 5, // Opcode: ABS_ZPmZ_H +/* 1772 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 1808 +/* 1777 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1780 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1794 +/* 1785 */ MCD_OPC_CheckPredicate, 0, 166, 76, 1, // Skip to: 86948 +/* 1790 */ MCD_OPC_Decode, 175, 20, 5, // Opcode: NEG_ZPmZ_B +/* 1794 */ MCD_OPC_FilterValue, 1, 157, 76, 1, // Skip to: 86948 +/* 1799 */ MCD_OPC_CheckPredicate, 0, 152, 76, 1, // Skip to: 86948 +/* 1804 */ MCD_OPC_Decode, 177, 20, 5, // Opcode: NEG_ZPmZ_H +/* 1808 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 1844 +/* 1813 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1816 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1830 +/* 1821 */ MCD_OPC_CheckPredicate, 0, 130, 76, 1, // Skip to: 86948 +/* 1826 */ MCD_OPC_Decode, 160, 3, 5, // Opcode: CLS_ZPmZ_B +/* 1830 */ MCD_OPC_FilterValue, 1, 121, 76, 1, // Skip to: 86948 +/* 1835 */ MCD_OPC_CheckPredicate, 0, 116, 76, 1, // Skip to: 86948 +/* 1840 */ MCD_OPC_Decode, 162, 3, 5, // Opcode: CLS_ZPmZ_H +/* 1844 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 1880 +/* 1849 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1852 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1866 +/* 1857 */ MCD_OPC_CheckPredicate, 0, 94, 76, 1, // Skip to: 86948 +/* 1862 */ MCD_OPC_Decode, 172, 3, 5, // Opcode: CLZ_ZPmZ_B +/* 1866 */ MCD_OPC_FilterValue, 1, 85, 76, 1, // Skip to: 86948 +/* 1871 */ MCD_OPC_CheckPredicate, 0, 80, 76, 1, // Skip to: 86948 +/* 1876 */ MCD_OPC_Decode, 174, 3, 5, // Opcode: CLZ_ZPmZ_H +/* 1880 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 1916 +/* 1885 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1888 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1902 +/* 1893 */ MCD_OPC_CheckPredicate, 0, 58, 76, 1, // Skip to: 86948 +/* 1898 */ MCD_OPC_Decode, 253, 4, 5, // Opcode: CNT_ZPmZ_B +/* 1902 */ MCD_OPC_FilterValue, 1, 49, 76, 1, // Skip to: 86948 +/* 1907 */ MCD_OPC_CheckPredicate, 0, 44, 76, 1, // Skip to: 86948 +/* 1912 */ MCD_OPC_Decode, 255, 4, 5, // Opcode: CNT_ZPmZ_H +/* 1916 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 1952 +/* 1921 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 1924 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 1938 +/* 1929 */ MCD_OPC_CheckPredicate, 0, 22, 76, 1, // Skip to: 86948 +/* 1934 */ MCD_OPC_Decode, 241, 4, 5, // Opcode: CNOT_ZPmZ_B +/* 1938 */ MCD_OPC_FilterValue, 1, 13, 76, 1, // Skip to: 86948 +/* 1943 */ MCD_OPC_CheckPredicate, 0, 8, 76, 1, // Skip to: 86948 +/* 1948 */ MCD_OPC_Decode, 243, 4, 5, // Opcode: CNOT_ZPmZ_H +/* 1952 */ MCD_OPC_FilterValue, 28, 16, 0, 0, // Skip to: 1973 +/* 1957 */ MCD_OPC_CheckPredicate, 0, 250, 75, 1, // Skip to: 86948 +/* 1962 */ MCD_OPC_CheckField, 22, 1, 1, 243, 75, 1, // Skip to: 86948 +/* 1969 */ MCD_OPC_Decode, 143, 6, 5, // Opcode: FABS_ZPmZ_H +/* 1973 */ MCD_OPC_FilterValue, 29, 16, 0, 0, // Skip to: 1994 +/* 1978 */ MCD_OPC_CheckPredicate, 0, 229, 75, 1, // Skip to: 86948 +/* 1983 */ MCD_OPC_CheckField, 22, 1, 1, 222, 75, 1, // Skip to: 86948 +/* 1990 */ MCD_OPC_Decode, 168, 11, 5, // Opcode: FNEG_ZPmZ_H +/* 1994 */ MCD_OPC_FilterValue, 30, 213, 75, 1, // Skip to: 86948 +/* 1999 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2002 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2016 +/* 2007 */ MCD_OPC_CheckPredicate, 0, 200, 75, 1, // Skip to: 86948 +/* 2012 */ MCD_OPC_Decode, 189, 20, 5, // Opcode: NOT_ZPmZ_B +/* 2016 */ MCD_OPC_FilterValue, 1, 191, 75, 1, // Skip to: 86948 +/* 2021 */ MCD_OPC_CheckPredicate, 0, 186, 75, 1, // Skip to: 86948 +/* 2026 */ MCD_OPC_Decode, 191, 20, 5, // Opcode: NOT_ZPmZ_H +/* 2030 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 2066 +/* 2035 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2038 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2052 +/* 2043 */ MCD_OPC_CheckPredicate, 0, 164, 75, 1, // Skip to: 86948 +/* 2048 */ MCD_OPC_Decode, 201, 19, 13, // Opcode: MAD_ZPmZZ_B +/* 2052 */ MCD_OPC_FilterValue, 1, 155, 75, 1, // Skip to: 86948 +/* 2057 */ MCD_OPC_CheckPredicate, 0, 150, 75, 1, // Skip to: 86948 +/* 2062 */ MCD_OPC_Decode, 203, 19, 13, // Opcode: MAD_ZPmZZ_H +/* 2066 */ MCD_OPC_FilterValue, 7, 141, 75, 1, // Skip to: 86948 +/* 2071 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2088 +/* 2079 */ MCD_OPC_CheckPredicate, 0, 128, 75, 1, // Skip to: 86948 +/* 2084 */ MCD_OPC_Decode, 140, 20, 13, // Opcode: MSB_ZPmZZ_B +/* 2088 */ MCD_OPC_FilterValue, 1, 119, 75, 1, // Skip to: 86948 +/* 2093 */ MCD_OPC_CheckPredicate, 0, 114, 75, 1, // Skip to: 86948 +/* 2098 */ MCD_OPC_Decode, 142, 20, 13, // Opcode: MSB_ZPmZZ_H +/* 2102 */ MCD_OPC_FilterValue, 1, 76, 8, 0, // Skip to: 4231 +/* 2107 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 2110 */ MCD_OPC_FilterValue, 0, 211, 2, 0, // Skip to: 2838 +/* 2115 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 2118 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 2154 +/* 2123 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2126 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2140 +/* 2131 */ MCD_OPC_CheckPredicate, 0, 76, 75, 1, // Skip to: 86948 +/* 2136 */ MCD_OPC_Decode, 188, 1, 0, // Opcode: ADD_ZPmZ_S +/* 2140 */ MCD_OPC_FilterValue, 1, 67, 75, 1, // Skip to: 86948 +/* 2145 */ MCD_OPC_CheckPredicate, 0, 62, 75, 1, // Skip to: 86948 +/* 2150 */ MCD_OPC_Decode, 186, 1, 0, // Opcode: ADD_ZPmZ_D +/* 2154 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 2190 +/* 2159 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2162 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2176 +/* 2167 */ MCD_OPC_CheckPredicate, 0, 40, 75, 1, // Skip to: 86948 +/* 2172 */ MCD_OPC_Decode, 250, 29, 0, // Opcode: SUB_ZPmZ_S +/* 2176 */ MCD_OPC_FilterValue, 1, 31, 75, 1, // Skip to: 86948 +/* 2181 */ MCD_OPC_CheckPredicate, 0, 26, 75, 1, // Skip to: 86948 +/* 2186 */ MCD_OPC_Decode, 248, 29, 0, // Opcode: SUB_ZPmZ_D +/* 2190 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 2226 +/* 2195 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2198 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2212 +/* 2203 */ MCD_OPC_CheckPredicate, 0, 4, 75, 1, // Skip to: 86948 +/* 2208 */ MCD_OPC_Decode, 224, 29, 0, // Opcode: SUBR_ZPmZ_S +/* 2212 */ MCD_OPC_FilterValue, 1, 251, 74, 1, // Skip to: 86948 +/* 2217 */ MCD_OPC_CheckPredicate, 0, 246, 74, 1, // Skip to: 86948 +/* 2222 */ MCD_OPC_Decode, 222, 29, 0, // Opcode: SUBR_ZPmZ_D +/* 2226 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2262 +/* 2231 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2234 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2248 +/* 2239 */ MCD_OPC_CheckPredicate, 0, 224, 74, 1, // Skip to: 86948 +/* 2244 */ MCD_OPC_Decode, 199, 23, 0, // Opcode: SMAX_ZPmZ_S +/* 2248 */ MCD_OPC_FilterValue, 1, 215, 74, 1, // Skip to: 86948 +/* 2253 */ MCD_OPC_CheckPredicate, 0, 210, 74, 1, // Skip to: 86948 +/* 2258 */ MCD_OPC_Decode, 197, 23, 0, // Opcode: SMAX_ZPmZ_D +/* 2262 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2298 +/* 2267 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2270 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2284 +/* 2275 */ MCD_OPC_CheckPredicate, 0, 188, 74, 1, // Skip to: 86948 +/* 2280 */ MCD_OPC_Decode, 255, 31, 0, // Opcode: UMAX_ZPmZ_S +/* 2284 */ MCD_OPC_FilterValue, 1, 179, 74, 1, // Skip to: 86948 +/* 2289 */ MCD_OPC_CheckPredicate, 0, 174, 74, 1, // Skip to: 86948 +/* 2294 */ MCD_OPC_Decode, 253, 31, 0, // Opcode: UMAX_ZPmZ_D +/* 2298 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 2334 +/* 2303 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2306 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2320 +/* 2311 */ MCD_OPC_CheckPredicate, 0, 152, 74, 1, // Skip to: 86948 +/* 2316 */ MCD_OPC_Decode, 229, 23, 0, // Opcode: SMIN_ZPmZ_S +/* 2320 */ MCD_OPC_FilterValue, 1, 143, 74, 1, // Skip to: 86948 +/* 2325 */ MCD_OPC_CheckPredicate, 0, 138, 74, 1, // Skip to: 86948 +/* 2330 */ MCD_OPC_Decode, 227, 23, 0, // Opcode: SMIN_ZPmZ_D +/* 2334 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 2370 +/* 2339 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2342 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2356 +/* 2347 */ MCD_OPC_CheckPredicate, 0, 116, 74, 1, // Skip to: 86948 +/* 2352 */ MCD_OPC_Decode, 156, 32, 0, // Opcode: UMIN_ZPmZ_S +/* 2356 */ MCD_OPC_FilterValue, 1, 107, 74, 1, // Skip to: 86948 +/* 2361 */ MCD_OPC_CheckPredicate, 0, 102, 74, 1, // Skip to: 86948 +/* 2366 */ MCD_OPC_Decode, 154, 32, 0, // Opcode: UMIN_ZPmZ_D +/* 2370 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 2406 +/* 2375 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2378 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2392 +/* 2383 */ MCD_OPC_CheckPredicate, 0, 80, 74, 1, // Skip to: 86948 +/* 2388 */ MCD_OPC_Decode, 139, 22, 0, // Opcode: SABD_ZPmZ_S +/* 2392 */ MCD_OPC_FilterValue, 1, 71, 74, 1, // Skip to: 86948 +/* 2397 */ MCD_OPC_CheckPredicate, 0, 66, 74, 1, // Skip to: 86948 +/* 2402 */ MCD_OPC_Decode, 137, 22, 0, // Opcode: SABD_ZPmZ_D +/* 2406 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 2442 +/* 2411 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2428 +/* 2419 */ MCD_OPC_CheckPredicate, 0, 44, 74, 1, // Skip to: 86948 +/* 2424 */ MCD_OPC_Decode, 129, 31, 0, // Opcode: UABD_ZPmZ_S +/* 2428 */ MCD_OPC_FilterValue, 1, 35, 74, 1, // Skip to: 86948 +/* 2433 */ MCD_OPC_CheckPredicate, 0, 30, 74, 1, // Skip to: 86948 +/* 2438 */ MCD_OPC_Decode, 255, 30, 0, // Opcode: UABD_ZPmZ_D +/* 2442 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 2478 +/* 2447 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2450 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2464 +/* 2455 */ MCD_OPC_CheckPredicate, 0, 8, 74, 1, // Skip to: 86948 +/* 2460 */ MCD_OPC_Decode, 156, 20, 0, // Opcode: MUL_ZPmZ_S +/* 2464 */ MCD_OPC_FilterValue, 1, 255, 73, 1, // Skip to: 86948 +/* 2469 */ MCD_OPC_CheckPredicate, 0, 250, 73, 1, // Skip to: 86948 +/* 2474 */ MCD_OPC_Decode, 154, 20, 0, // Opcode: MUL_ZPmZ_D +/* 2478 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 2514 +/* 2483 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2486 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2500 +/* 2491 */ MCD_OPC_CheckPredicate, 0, 228, 73, 1, // Skip to: 86948 +/* 2496 */ MCD_OPC_Decode, 137, 24, 0, // Opcode: SMULH_ZPmZ_S +/* 2500 */ MCD_OPC_FilterValue, 1, 219, 73, 1, // Skip to: 86948 +/* 2505 */ MCD_OPC_CheckPredicate, 0, 214, 73, 1, // Skip to: 86948 +/* 2510 */ MCD_OPC_Decode, 135, 24, 0, // Opcode: SMULH_ZPmZ_D +/* 2514 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 2550 +/* 2519 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2522 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2536 +/* 2527 */ MCD_OPC_CheckPredicate, 0, 192, 73, 1, // Skip to: 86948 +/* 2532 */ MCD_OPC_Decode, 191, 32, 0, // Opcode: UMULH_ZPmZ_S +/* 2536 */ MCD_OPC_FilterValue, 1, 183, 73, 1, // Skip to: 86948 +/* 2541 */ MCD_OPC_CheckPredicate, 0, 178, 73, 1, // Skip to: 86948 +/* 2546 */ MCD_OPC_Decode, 189, 32, 0, // Opcode: UMULH_ZPmZ_D +/* 2550 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 2586 +/* 2555 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2558 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2572 +/* 2563 */ MCD_OPC_CheckPredicate, 0, 156, 73, 1, // Skip to: 86948 +/* 2568 */ MCD_OPC_Decode, 224, 22, 0, // Opcode: SDIV_ZPmZ_S +/* 2572 */ MCD_OPC_FilterValue, 1, 147, 73, 1, // Skip to: 86948 +/* 2577 */ MCD_OPC_CheckPredicate, 0, 142, 73, 1, // Skip to: 86948 +/* 2582 */ MCD_OPC_Decode, 223, 22, 0, // Opcode: SDIV_ZPmZ_D +/* 2586 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 2622 +/* 2591 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2594 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2608 +/* 2599 */ MCD_OPC_CheckPredicate, 0, 120, 73, 1, // Skip to: 86948 +/* 2604 */ MCD_OPC_Decode, 211, 31, 0, // Opcode: UDIV_ZPmZ_S +/* 2608 */ MCD_OPC_FilterValue, 1, 111, 73, 1, // Skip to: 86948 +/* 2613 */ MCD_OPC_CheckPredicate, 0, 106, 73, 1, // Skip to: 86948 +/* 2618 */ MCD_OPC_Decode, 210, 31, 0, // Opcode: UDIV_ZPmZ_D +/* 2622 */ MCD_OPC_FilterValue, 22, 31, 0, 0, // Skip to: 2658 +/* 2627 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2630 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2644 +/* 2635 */ MCD_OPC_CheckPredicate, 0, 84, 73, 1, // Skip to: 86948 +/* 2640 */ MCD_OPC_Decode, 220, 22, 0, // Opcode: SDIVR_ZPmZ_S +/* 2644 */ MCD_OPC_FilterValue, 1, 75, 73, 1, // Skip to: 86948 +/* 2649 */ MCD_OPC_CheckPredicate, 0, 70, 73, 1, // Skip to: 86948 +/* 2654 */ MCD_OPC_Decode, 219, 22, 0, // Opcode: SDIVR_ZPmZ_D +/* 2658 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 2694 +/* 2663 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2666 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2680 +/* 2671 */ MCD_OPC_CheckPredicate, 0, 48, 73, 1, // Skip to: 86948 +/* 2676 */ MCD_OPC_Decode, 207, 31, 0, // Opcode: UDIVR_ZPmZ_S +/* 2680 */ MCD_OPC_FilterValue, 1, 39, 73, 1, // Skip to: 86948 +/* 2685 */ MCD_OPC_CheckPredicate, 0, 34, 73, 1, // Skip to: 86948 +/* 2690 */ MCD_OPC_Decode, 206, 31, 0, // Opcode: UDIVR_ZPmZ_D +/* 2694 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 2730 +/* 2699 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2702 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2716 +/* 2707 */ MCD_OPC_CheckPredicate, 0, 12, 73, 1, // Skip to: 86948 +/* 2712 */ MCD_OPC_Decode, 215, 20, 0, // Opcode: ORR_ZPmZ_S +/* 2716 */ MCD_OPC_FilterValue, 1, 3, 73, 1, // Skip to: 86948 +/* 2721 */ MCD_OPC_CheckPredicate, 0, 254, 72, 1, // Skip to: 86948 +/* 2726 */ MCD_OPC_Decode, 213, 20, 0, // Opcode: ORR_ZPmZ_D +/* 2730 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 2766 +/* 2735 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2738 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2752 +/* 2743 */ MCD_OPC_CheckPredicate, 0, 232, 72, 1, // Skip to: 86948 +/* 2748 */ MCD_OPC_Decode, 243, 5, 0, // Opcode: EOR_ZPmZ_S +/* 2752 */ MCD_OPC_FilterValue, 1, 223, 72, 1, // Skip to: 86948 +/* 2757 */ MCD_OPC_CheckPredicate, 0, 218, 72, 1, // Skip to: 86948 +/* 2762 */ MCD_OPC_Decode, 241, 5, 0, // Opcode: EOR_ZPmZ_D +/* 2766 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 2802 +/* 2771 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2774 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2788 +/* 2779 */ MCD_OPC_CheckPredicate, 0, 196, 72, 1, // Skip to: 86948 +/* 2784 */ MCD_OPC_Decode, 250, 1, 0, // Opcode: AND_ZPmZ_S +/* 2788 */ MCD_OPC_FilterValue, 1, 187, 72, 1, // Skip to: 86948 +/* 2793 */ MCD_OPC_CheckPredicate, 0, 182, 72, 1, // Skip to: 86948 +/* 2798 */ MCD_OPC_Decode, 248, 1, 0, // Opcode: AND_ZPmZ_D +/* 2802 */ MCD_OPC_FilterValue, 27, 173, 72, 1, // Skip to: 86948 +/* 2807 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2810 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2824 +/* 2815 */ MCD_OPC_CheckPredicate, 0, 160, 72, 1, // Skip to: 86948 +/* 2820 */ MCD_OPC_Decode, 185, 2, 0, // Opcode: BIC_ZPmZ_S +/* 2824 */ MCD_OPC_FilterValue, 1, 151, 72, 1, // Skip to: 86948 +/* 2829 */ MCD_OPC_CheckPredicate, 0, 146, 72, 1, // Skip to: 86948 +/* 2834 */ MCD_OPC_Decode, 183, 2, 0, // Opcode: BIC_ZPmZ_D +/* 2838 */ MCD_OPC_FilterValue, 1, 128, 1, 0, // Skip to: 3227 +/* 2843 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 2846 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 2867 +/* 2851 */ MCD_OPC_CheckPredicate, 0, 124, 72, 1, // Skip to: 86948 +/* 2856 */ MCD_OPC_CheckField, 22, 1, 0, 117, 72, 1, // Skip to: 86948 +/* 2863 */ MCD_OPC_Decode, 171, 22, 1, // Opcode: SADDV_VPZ_S +/* 2867 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 2903 +/* 2872 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2875 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2889 +/* 2880 */ MCD_OPC_CheckPredicate, 0, 95, 72, 1, // Skip to: 86948 +/* 2885 */ MCD_OPC_Decode, 162, 31, 1, // Opcode: UADDV_VPZ_S +/* 2889 */ MCD_OPC_FilterValue, 1, 86, 72, 1, // Skip to: 86948 +/* 2894 */ MCD_OPC_CheckPredicate, 0, 81, 72, 1, // Skip to: 86948 +/* 2899 */ MCD_OPC_Decode, 160, 31, 1, // Opcode: UADDV_VPZ_D +/* 2903 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 2939 +/* 2908 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2911 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2925 +/* 2916 */ MCD_OPC_CheckPredicate, 0, 59, 72, 1, // Skip to: 86948 +/* 2921 */ MCD_OPC_Decode, 186, 23, 14, // Opcode: SMAXV_VPZ_S +/* 2925 */ MCD_OPC_FilterValue, 1, 50, 72, 1, // Skip to: 86948 +/* 2930 */ MCD_OPC_CheckPredicate, 0, 45, 72, 1, // Skip to: 86948 +/* 2935 */ MCD_OPC_Decode, 184, 23, 1, // Opcode: SMAXV_VPZ_D +/* 2939 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 2975 +/* 2944 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2947 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2961 +/* 2952 */ MCD_OPC_CheckPredicate, 0, 23, 72, 1, // Skip to: 86948 +/* 2957 */ MCD_OPC_Decode, 242, 31, 14, // Opcode: UMAXV_VPZ_S +/* 2961 */ MCD_OPC_FilterValue, 1, 14, 72, 1, // Skip to: 86948 +/* 2966 */ MCD_OPC_CheckPredicate, 0, 9, 72, 1, // Skip to: 86948 +/* 2971 */ MCD_OPC_Decode, 240, 31, 1, // Opcode: UMAXV_VPZ_D +/* 2975 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 3011 +/* 2980 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 2983 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 2997 +/* 2988 */ MCD_OPC_CheckPredicate, 0, 243, 71, 1, // Skip to: 86948 +/* 2993 */ MCD_OPC_Decode, 216, 23, 14, // Opcode: SMINV_VPZ_S +/* 2997 */ MCD_OPC_FilterValue, 1, 234, 71, 1, // Skip to: 86948 +/* 3002 */ MCD_OPC_CheckPredicate, 0, 229, 71, 1, // Skip to: 86948 +/* 3007 */ MCD_OPC_Decode, 214, 23, 1, // Opcode: SMINV_VPZ_D +/* 3011 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 3047 +/* 3016 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3019 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3033 +/* 3024 */ MCD_OPC_CheckPredicate, 0, 207, 71, 1, // Skip to: 86948 +/* 3029 */ MCD_OPC_Decode, 143, 32, 14, // Opcode: UMINV_VPZ_S +/* 3033 */ MCD_OPC_FilterValue, 1, 198, 71, 1, // Skip to: 86948 +/* 3038 */ MCD_OPC_CheckPredicate, 0, 193, 71, 1, // Skip to: 86948 +/* 3043 */ MCD_OPC_Decode, 141, 32, 1, // Opcode: UMINV_VPZ_D +/* 3047 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3083 +/* 3052 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3055 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3069 +/* 3060 */ MCD_OPC_CheckPredicate, 0, 171, 71, 1, // Skip to: 86948 +/* 3065 */ MCD_OPC_Decode, 254, 19, 4, // Opcode: MOVPRFX_ZPzZ_S +/* 3069 */ MCD_OPC_FilterValue, 1, 162, 71, 1, // Skip to: 86948 +/* 3074 */ MCD_OPC_CheckPredicate, 0, 157, 71, 1, // Skip to: 86948 +/* 3079 */ MCD_OPC_Decode, 252, 19, 4, // Opcode: MOVPRFX_ZPzZ_D +/* 3083 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3119 +/* 3088 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3091 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3105 +/* 3096 */ MCD_OPC_CheckPredicate, 0, 135, 71, 1, // Skip to: 86948 +/* 3101 */ MCD_OPC_Decode, 250, 19, 5, // Opcode: MOVPRFX_ZPmZ_S +/* 3105 */ MCD_OPC_FilterValue, 1, 126, 71, 1, // Skip to: 86948 +/* 3110 */ MCD_OPC_CheckPredicate, 0, 121, 71, 1, // Skip to: 86948 +/* 3115 */ MCD_OPC_Decode, 248, 19, 5, // Opcode: MOVPRFX_ZPmZ_D +/* 3119 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 3155 +/* 3124 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3127 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3141 +/* 3132 */ MCD_OPC_CheckPredicate, 0, 99, 71, 1, // Skip to: 86948 +/* 3137 */ MCD_OPC_Decode, 226, 20, 14, // Opcode: ORV_VPZ_S +/* 3141 */ MCD_OPC_FilterValue, 1, 90, 71, 1, // Skip to: 86948 +/* 3146 */ MCD_OPC_CheckPredicate, 0, 85, 71, 1, // Skip to: 86948 +/* 3151 */ MCD_OPC_Decode, 224, 20, 1, // Opcode: ORV_VPZ_D +/* 3155 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 3191 +/* 3160 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3163 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3177 +/* 3168 */ MCD_OPC_CheckPredicate, 0, 63, 71, 1, // Skip to: 86948 +/* 3173 */ MCD_OPC_Decode, 231, 5, 14, // Opcode: EORV_VPZ_S +/* 3177 */ MCD_OPC_FilterValue, 1, 54, 71, 1, // Skip to: 86948 +/* 3182 */ MCD_OPC_CheckPredicate, 0, 49, 71, 1, // Skip to: 86948 +/* 3187 */ MCD_OPC_Decode, 229, 5, 1, // Opcode: EORV_VPZ_D +/* 3191 */ MCD_OPC_FilterValue, 26, 40, 71, 1, // Skip to: 86948 +/* 3196 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3199 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3213 +/* 3204 */ MCD_OPC_CheckPredicate, 0, 27, 71, 1, // Skip to: 86948 +/* 3209 */ MCD_OPC_Decode, 238, 1, 14, // Opcode: ANDV_VPZ_S +/* 3213 */ MCD_OPC_FilterValue, 1, 18, 71, 1, // Skip to: 86948 +/* 3218 */ MCD_OPC_CheckPredicate, 0, 13, 71, 1, // Skip to: 86948 +/* 3223 */ MCD_OPC_Decode, 236, 1, 1, // Opcode: ANDV_VPZ_D +/* 3227 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 3263 +/* 3232 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3235 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3249 +/* 3240 */ MCD_OPC_CheckPredicate, 0, 247, 70, 1, // Skip to: 86948 +/* 3245 */ MCD_OPC_Decode, 208, 19, 6, // Opcode: MLA_ZPmZZ_S +/* 3249 */ MCD_OPC_FilterValue, 1, 238, 70, 1, // Skip to: 86948 +/* 3254 */ MCD_OPC_CheckPredicate, 0, 233, 70, 1, // Skip to: 86948 +/* 3259 */ MCD_OPC_Decode, 206, 19, 6, // Opcode: MLA_ZPmZZ_D +/* 3263 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 3299 +/* 3268 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3271 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3285 +/* 3276 */ MCD_OPC_CheckPredicate, 0, 211, 70, 1, // Skip to: 86948 +/* 3281 */ MCD_OPC_Decode, 222, 19, 6, // Opcode: MLS_ZPmZZ_S +/* 3285 */ MCD_OPC_FilterValue, 1, 202, 70, 1, // Skip to: 86948 +/* 3290 */ MCD_OPC_CheckPredicate, 0, 197, 70, 1, // Skip to: 86948 +/* 3295 */ MCD_OPC_Decode, 220, 19, 6, // Opcode: MLS_ZPmZZ_D +/* 3299 */ MCD_OPC_FilterValue, 4, 82, 1, 0, // Skip to: 3642 +/* 3304 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 3307 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3321 +/* 3312 */ MCD_OPC_CheckPredicate, 0, 175, 70, 1, // Skip to: 86948 +/* 3317 */ MCD_OPC_Decode, 143, 2, 15, // Opcode: ASR_ZPmI_D +/* 3321 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 3335 +/* 3326 */ MCD_OPC_CheckPredicate, 0, 161, 70, 1, // Skip to: 86948 +/* 3331 */ MCD_OPC_Decode, 188, 19, 15, // Opcode: LSR_ZPmI_D +/* 3335 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 3349 +/* 3340 */ MCD_OPC_CheckPredicate, 0, 147, 70, 1, // Skip to: 86948 +/* 3345 */ MCD_OPC_Decode, 164, 19, 16, // Opcode: LSL_ZPmI_D +/* 3349 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 3363 +/* 3354 */ MCD_OPC_CheckPredicate, 0, 133, 70, 1, // Skip to: 86948 +/* 3359 */ MCD_OPC_Decode, 255, 1, 15, // Opcode: ASRD_ZPmI_D +/* 3363 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3399 +/* 3368 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3371 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3385 +/* 3376 */ MCD_OPC_CheckPredicate, 0, 111, 70, 1, // Skip to: 86948 +/* 3381 */ MCD_OPC_Decode, 149, 2, 0, // Opcode: ASR_ZPmZ_S +/* 3385 */ MCD_OPC_FilterValue, 1, 102, 70, 1, // Skip to: 86948 +/* 3390 */ MCD_OPC_CheckPredicate, 0, 97, 70, 1, // Skip to: 86948 +/* 3395 */ MCD_OPC_Decode, 147, 2, 0, // Opcode: ASR_ZPmZ_D +/* 3399 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3435 +/* 3404 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3407 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3421 +/* 3412 */ MCD_OPC_CheckPredicate, 0, 75, 70, 1, // Skip to: 86948 +/* 3417 */ MCD_OPC_Decode, 194, 19, 0, // Opcode: LSR_ZPmZ_S +/* 3421 */ MCD_OPC_FilterValue, 1, 66, 70, 1, // Skip to: 86948 +/* 3426 */ MCD_OPC_CheckPredicate, 0, 61, 70, 1, // Skip to: 86948 +/* 3431 */ MCD_OPC_Decode, 192, 19, 0, // Opcode: LSR_ZPmZ_D +/* 3435 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 3471 +/* 3440 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3443 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3457 +/* 3448 */ MCD_OPC_CheckPredicate, 0, 39, 70, 1, // Skip to: 86948 +/* 3453 */ MCD_OPC_Decode, 170, 19, 0, // Opcode: LSL_ZPmZ_S +/* 3457 */ MCD_OPC_FilterValue, 1, 30, 70, 1, // Skip to: 86948 +/* 3462 */ MCD_OPC_CheckPredicate, 0, 25, 70, 1, // Skip to: 86948 +/* 3467 */ MCD_OPC_Decode, 168, 19, 0, // Opcode: LSL_ZPmZ_D +/* 3471 */ MCD_OPC_FilterValue, 20, 31, 0, 0, // Skip to: 3507 +/* 3476 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3479 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3493 +/* 3484 */ MCD_OPC_CheckPredicate, 0, 3, 70, 1, // Skip to: 86948 +/* 3489 */ MCD_OPC_Decode, 133, 2, 0, // Opcode: ASRR_ZPmZ_S +/* 3493 */ MCD_OPC_FilterValue, 1, 250, 69, 1, // Skip to: 86948 +/* 3498 */ MCD_OPC_CheckPredicate, 0, 245, 69, 1, // Skip to: 86948 +/* 3503 */ MCD_OPC_Decode, 131, 2, 0, // Opcode: ASRR_ZPmZ_D +/* 3507 */ MCD_OPC_FilterValue, 21, 31, 0, 0, // Skip to: 3543 +/* 3512 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3515 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3529 +/* 3520 */ MCD_OPC_CheckPredicate, 0, 223, 69, 1, // Skip to: 86948 +/* 3525 */ MCD_OPC_Decode, 178, 19, 0, // Opcode: LSRR_ZPmZ_S +/* 3529 */ MCD_OPC_FilterValue, 1, 214, 69, 1, // Skip to: 86948 +/* 3534 */ MCD_OPC_CheckPredicate, 0, 209, 69, 1, // Skip to: 86948 +/* 3539 */ MCD_OPC_Decode, 176, 19, 0, // Opcode: LSRR_ZPmZ_D +/* 3543 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 3579 +/* 3548 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3551 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3565 +/* 3556 */ MCD_OPC_CheckPredicate, 0, 187, 69, 1, // Skip to: 86948 +/* 3561 */ MCD_OPC_Decode, 154, 19, 0, // Opcode: LSLR_ZPmZ_S +/* 3565 */ MCD_OPC_FilterValue, 1, 178, 69, 1, // Skip to: 86948 +/* 3570 */ MCD_OPC_CheckPredicate, 0, 173, 69, 1, // Skip to: 86948 +/* 3575 */ MCD_OPC_Decode, 152, 19, 0, // Opcode: LSLR_ZPmZ_D +/* 3579 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 3600 +/* 3584 */ MCD_OPC_CheckPredicate, 0, 159, 69, 1, // Skip to: 86948 +/* 3589 */ MCD_OPC_CheckField, 22, 1, 0, 152, 69, 1, // Skip to: 86948 +/* 3596 */ MCD_OPC_Decode, 138, 2, 0, // Opcode: ASR_WIDE_ZPmZ_S +/* 3600 */ MCD_OPC_FilterValue, 25, 16, 0, 0, // Skip to: 3621 +/* 3605 */ MCD_OPC_CheckPredicate, 0, 138, 69, 1, // Skip to: 86948 +/* 3610 */ MCD_OPC_CheckField, 22, 1, 0, 131, 69, 1, // Skip to: 86948 +/* 3617 */ MCD_OPC_Decode, 183, 19, 0, // Opcode: LSR_WIDE_ZPmZ_S +/* 3621 */ MCD_OPC_FilterValue, 27, 122, 69, 1, // Skip to: 86948 +/* 3626 */ MCD_OPC_CheckPredicate, 0, 117, 69, 1, // Skip to: 86948 +/* 3631 */ MCD_OPC_CheckField, 22, 1, 0, 110, 69, 1, // Skip to: 86948 +/* 3638 */ MCD_OPC_Decode, 159, 19, 0, // Opcode: LSL_WIDE_ZPmZ_S +/* 3642 */ MCD_OPC_FilterValue, 5, 0, 2, 0, // Skip to: 4159 +/* 3647 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 3650 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 3686 +/* 3655 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3658 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3672 +/* 3663 */ MCD_OPC_CheckPredicate, 0, 80, 69, 1, // Skip to: 86948 +/* 3668 */ MCD_OPC_Decode, 171, 30, 5, // Opcode: SXTB_ZPmZ_S +/* 3672 */ MCD_OPC_FilterValue, 1, 71, 69, 1, // Skip to: 86948 +/* 3677 */ MCD_OPC_CheckPredicate, 0, 66, 69, 1, // Skip to: 86948 +/* 3682 */ MCD_OPC_Decode, 169, 30, 5, // Opcode: SXTB_ZPmZ_D +/* 3686 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 3722 +/* 3691 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3694 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3708 +/* 3699 */ MCD_OPC_CheckPredicate, 0, 44, 69, 1, // Skip to: 86948 +/* 3704 */ MCD_OPC_Decode, 184, 34, 5, // Opcode: UXTB_ZPmZ_S +/* 3708 */ MCD_OPC_FilterValue, 1, 35, 69, 1, // Skip to: 86948 +/* 3713 */ MCD_OPC_CheckPredicate, 0, 30, 69, 1, // Skip to: 86948 +/* 3718 */ MCD_OPC_Decode, 182, 34, 5, // Opcode: UXTB_ZPmZ_D +/* 3722 */ MCD_OPC_FilterValue, 18, 31, 0, 0, // Skip to: 3758 +/* 3727 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3730 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3744 +/* 3735 */ MCD_OPC_CheckPredicate, 0, 8, 69, 1, // Skip to: 86948 +/* 3740 */ MCD_OPC_Decode, 173, 30, 5, // Opcode: SXTH_ZPmZ_S +/* 3744 */ MCD_OPC_FilterValue, 1, 255, 68, 1, // Skip to: 86948 +/* 3749 */ MCD_OPC_CheckPredicate, 0, 250, 68, 1, // Skip to: 86948 +/* 3754 */ MCD_OPC_Decode, 172, 30, 5, // Opcode: SXTH_ZPmZ_D +/* 3758 */ MCD_OPC_FilterValue, 19, 31, 0, 0, // Skip to: 3794 +/* 3763 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3766 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3780 +/* 3771 */ MCD_OPC_CheckPredicate, 0, 228, 68, 1, // Skip to: 86948 +/* 3776 */ MCD_OPC_Decode, 186, 34, 5, // Opcode: UXTH_ZPmZ_S +/* 3780 */ MCD_OPC_FilterValue, 1, 219, 68, 1, // Skip to: 86948 +/* 3785 */ MCD_OPC_CheckPredicate, 0, 214, 68, 1, // Skip to: 86948 +/* 3790 */ MCD_OPC_Decode, 185, 34, 5, // Opcode: UXTH_ZPmZ_D +/* 3794 */ MCD_OPC_FilterValue, 20, 16, 0, 0, // Skip to: 3815 +/* 3799 */ MCD_OPC_CheckPredicate, 0, 200, 68, 1, // Skip to: 86948 +/* 3804 */ MCD_OPC_CheckField, 22, 1, 1, 193, 68, 1, // Skip to: 86948 +/* 3811 */ MCD_OPC_Decode, 174, 30, 5, // Opcode: SXTW_ZPmZ_D +/* 3815 */ MCD_OPC_FilterValue, 21, 16, 0, 0, // Skip to: 3836 +/* 3820 */ MCD_OPC_CheckPredicate, 0, 179, 68, 1, // Skip to: 86948 +/* 3825 */ MCD_OPC_CheckField, 22, 1, 1, 172, 68, 1, // Skip to: 86948 +/* 3832 */ MCD_OPC_Decode, 187, 34, 5, // Opcode: UXTW_ZPmZ_D +/* 3836 */ MCD_OPC_FilterValue, 22, 30, 0, 0, // Skip to: 3871 +/* 3841 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3844 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3858 +/* 3849 */ MCD_OPC_CheckPredicate, 0, 150, 68, 1, // Skip to: 86948 +/* 3854 */ MCD_OPC_Decode, 129, 1, 5, // Opcode: ABS_ZPmZ_S +/* 3858 */ MCD_OPC_FilterValue, 1, 141, 68, 1, // Skip to: 86948 +/* 3863 */ MCD_OPC_CheckPredicate, 0, 136, 68, 1, // Skip to: 86948 +/* 3868 */ MCD_OPC_Decode, 127, 5, // Opcode: ABS_ZPmZ_D +/* 3871 */ MCD_OPC_FilterValue, 23, 31, 0, 0, // Skip to: 3907 +/* 3876 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3879 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3893 +/* 3884 */ MCD_OPC_CheckPredicate, 0, 115, 68, 1, // Skip to: 86948 +/* 3889 */ MCD_OPC_Decode, 178, 20, 5, // Opcode: NEG_ZPmZ_S +/* 3893 */ MCD_OPC_FilterValue, 1, 106, 68, 1, // Skip to: 86948 +/* 3898 */ MCD_OPC_CheckPredicate, 0, 101, 68, 1, // Skip to: 86948 +/* 3903 */ MCD_OPC_Decode, 176, 20, 5, // Opcode: NEG_ZPmZ_D +/* 3907 */ MCD_OPC_FilterValue, 24, 31, 0, 0, // Skip to: 3943 +/* 3912 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3915 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3929 +/* 3920 */ MCD_OPC_CheckPredicate, 0, 79, 68, 1, // Skip to: 86948 +/* 3925 */ MCD_OPC_Decode, 163, 3, 5, // Opcode: CLS_ZPmZ_S +/* 3929 */ MCD_OPC_FilterValue, 1, 70, 68, 1, // Skip to: 86948 +/* 3934 */ MCD_OPC_CheckPredicate, 0, 65, 68, 1, // Skip to: 86948 +/* 3939 */ MCD_OPC_Decode, 161, 3, 5, // Opcode: CLS_ZPmZ_D +/* 3943 */ MCD_OPC_FilterValue, 25, 31, 0, 0, // Skip to: 3979 +/* 3948 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3951 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 3965 +/* 3956 */ MCD_OPC_CheckPredicate, 0, 43, 68, 1, // Skip to: 86948 +/* 3961 */ MCD_OPC_Decode, 175, 3, 5, // Opcode: CLZ_ZPmZ_S +/* 3965 */ MCD_OPC_FilterValue, 1, 34, 68, 1, // Skip to: 86948 +/* 3970 */ MCD_OPC_CheckPredicate, 0, 29, 68, 1, // Skip to: 86948 +/* 3975 */ MCD_OPC_Decode, 173, 3, 5, // Opcode: CLZ_ZPmZ_D +/* 3979 */ MCD_OPC_FilterValue, 26, 31, 0, 0, // Skip to: 4015 +/* 3984 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 3987 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4001 +/* 3992 */ MCD_OPC_CheckPredicate, 0, 7, 68, 1, // Skip to: 86948 +/* 3997 */ MCD_OPC_Decode, 128, 5, 5, // Opcode: CNT_ZPmZ_S +/* 4001 */ MCD_OPC_FilterValue, 1, 254, 67, 1, // Skip to: 86948 +/* 4006 */ MCD_OPC_CheckPredicate, 0, 249, 67, 1, // Skip to: 86948 +/* 4011 */ MCD_OPC_Decode, 254, 4, 5, // Opcode: CNT_ZPmZ_D +/* 4015 */ MCD_OPC_FilterValue, 27, 31, 0, 0, // Skip to: 4051 +/* 4020 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4023 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4037 +/* 4028 */ MCD_OPC_CheckPredicate, 0, 227, 67, 1, // Skip to: 86948 +/* 4033 */ MCD_OPC_Decode, 244, 4, 5, // Opcode: CNOT_ZPmZ_S +/* 4037 */ MCD_OPC_FilterValue, 1, 218, 67, 1, // Skip to: 86948 +/* 4042 */ MCD_OPC_CheckPredicate, 0, 213, 67, 1, // Skip to: 86948 +/* 4047 */ MCD_OPC_Decode, 242, 4, 5, // Opcode: CNOT_ZPmZ_D +/* 4051 */ MCD_OPC_FilterValue, 28, 31, 0, 0, // Skip to: 4087 +/* 4056 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4059 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4073 +/* 4064 */ MCD_OPC_CheckPredicate, 0, 191, 67, 1, // Skip to: 86948 +/* 4069 */ MCD_OPC_Decode, 144, 6, 5, // Opcode: FABS_ZPmZ_S +/* 4073 */ MCD_OPC_FilterValue, 1, 182, 67, 1, // Skip to: 86948 +/* 4078 */ MCD_OPC_CheckPredicate, 0, 177, 67, 1, // Skip to: 86948 +/* 4083 */ MCD_OPC_Decode, 142, 6, 5, // Opcode: FABS_ZPmZ_D +/* 4087 */ MCD_OPC_FilterValue, 29, 31, 0, 0, // Skip to: 4123 +/* 4092 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4095 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4109 +/* 4100 */ MCD_OPC_CheckPredicate, 0, 155, 67, 1, // Skip to: 86948 +/* 4105 */ MCD_OPC_Decode, 169, 11, 5, // Opcode: FNEG_ZPmZ_S +/* 4109 */ MCD_OPC_FilterValue, 1, 146, 67, 1, // Skip to: 86948 +/* 4114 */ MCD_OPC_CheckPredicate, 0, 141, 67, 1, // Skip to: 86948 +/* 4119 */ MCD_OPC_Decode, 167, 11, 5, // Opcode: FNEG_ZPmZ_D +/* 4123 */ MCD_OPC_FilterValue, 30, 132, 67, 1, // Skip to: 86948 +/* 4128 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4131 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4145 +/* 4136 */ MCD_OPC_CheckPredicate, 0, 119, 67, 1, // Skip to: 86948 +/* 4141 */ MCD_OPC_Decode, 192, 20, 5, // Opcode: NOT_ZPmZ_S +/* 4145 */ MCD_OPC_FilterValue, 1, 110, 67, 1, // Skip to: 86948 +/* 4150 */ MCD_OPC_CheckPredicate, 0, 105, 67, 1, // Skip to: 86948 +/* 4155 */ MCD_OPC_Decode, 190, 20, 5, // Opcode: NOT_ZPmZ_D +/* 4159 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 4195 +/* 4164 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4167 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4181 +/* 4172 */ MCD_OPC_CheckPredicate, 0, 83, 67, 1, // Skip to: 86948 +/* 4177 */ MCD_OPC_Decode, 204, 19, 13, // Opcode: MAD_ZPmZZ_S +/* 4181 */ MCD_OPC_FilterValue, 1, 74, 67, 1, // Skip to: 86948 +/* 4186 */ MCD_OPC_CheckPredicate, 0, 69, 67, 1, // Skip to: 86948 +/* 4191 */ MCD_OPC_Decode, 202, 19, 13, // Opcode: MAD_ZPmZZ_D +/* 4195 */ MCD_OPC_FilterValue, 7, 60, 67, 1, // Skip to: 86948 +/* 4200 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4203 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4217 +/* 4208 */ MCD_OPC_CheckPredicate, 0, 47, 67, 1, // Skip to: 86948 +/* 4213 */ MCD_OPC_Decode, 143, 20, 13, // Opcode: MSB_ZPmZZ_S +/* 4217 */ MCD_OPC_FilterValue, 1, 38, 67, 1, // Skip to: 86948 +/* 4222 */ MCD_OPC_CheckPredicate, 0, 33, 67, 1, // Skip to: 86948 +/* 4227 */ MCD_OPC_Decode, 141, 20, 13, // Opcode: MSB_ZPmZZ_D +/* 4231 */ MCD_OPC_FilterValue, 2, 161, 0, 0, // Skip to: 4397 +/* 4236 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4239 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 4289 +/* 4244 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4247 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4268 +/* 4252 */ MCD_OPC_CheckPredicate, 0, 3, 67, 1, // Skip to: 86948 +/* 4257 */ MCD_OPC_CheckField, 18, 2, 0, 252, 66, 1, // Skip to: 86948 +/* 4264 */ MCD_OPC_Decode, 211, 20, 17, // Opcode: ORR_ZI +/* 4268 */ MCD_OPC_FilterValue, 1, 243, 66, 1, // Skip to: 86948 +/* 4273 */ MCD_OPC_CheckPredicate, 0, 238, 66, 1, // Skip to: 86948 +/* 4278 */ MCD_OPC_CheckField, 18, 2, 0, 231, 66, 1, // Skip to: 86948 +/* 4285 */ MCD_OPC_Decode, 239, 5, 17, // Opcode: EOR_ZI +/* 4289 */ MCD_OPC_FilterValue, 1, 222, 66, 1, // Skip to: 86948 +/* 4294 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 4297 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4333 +/* 4302 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4305 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4319 +/* 4310 */ MCD_OPC_CheckPredicate, 0, 201, 66, 1, // Skip to: 86948 +/* 4315 */ MCD_OPC_Decode, 145, 5, 18, // Opcode: CPY_ZPzI_B +/* 4319 */ MCD_OPC_FilterValue, 1, 192, 66, 1, // Skip to: 86948 +/* 4324 */ MCD_OPC_CheckPredicate, 0, 187, 66, 1, // Skip to: 86948 +/* 4329 */ MCD_OPC_Decode, 147, 5, 19, // Opcode: CPY_ZPzI_H +/* 4333 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 4369 +/* 4338 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4341 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4355 +/* 4346 */ MCD_OPC_CheckPredicate, 0, 165, 66, 1, // Skip to: 86948 +/* 4351 */ MCD_OPC_Decode, 133, 5, 20, // Opcode: CPY_ZPmI_B +/* 4355 */ MCD_OPC_FilterValue, 1, 156, 66, 1, // Skip to: 86948 +/* 4360 */ MCD_OPC_CheckPredicate, 0, 151, 66, 1, // Skip to: 86948 +/* 4365 */ MCD_OPC_Decode, 135, 5, 21, // Opcode: CPY_ZPmI_H +/* 4369 */ MCD_OPC_FilterValue, 3, 142, 66, 1, // Skip to: 86948 +/* 4374 */ MCD_OPC_CheckPredicate, 0, 137, 66, 1, // Skip to: 86948 +/* 4379 */ MCD_OPC_CheckField, 22, 1, 1, 130, 66, 1, // Skip to: 86948 +/* 4386 */ MCD_OPC_CheckField, 13, 1, 0, 123, 66, 1, // Skip to: 86948 +/* 4393 */ MCD_OPC_Decode, 212, 7, 22, // Opcode: FCPY_ZPmI_H +/* 4397 */ MCD_OPC_FilterValue, 3, 114, 66, 1, // Skip to: 86948 +/* 4402 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 4405 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 4455 +/* 4410 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4413 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4434 +/* 4418 */ MCD_OPC_CheckPredicate, 0, 93, 66, 1, // Skip to: 86948 +/* 4423 */ MCD_OPC_CheckField, 18, 2, 0, 86, 66, 1, // Skip to: 86948 +/* 4430 */ MCD_OPC_Decode, 246, 1, 17, // Opcode: AND_ZI +/* 4434 */ MCD_OPC_FilterValue, 1, 77, 66, 1, // Skip to: 86948 +/* 4439 */ MCD_OPC_CheckPredicate, 0, 72, 66, 1, // Skip to: 86948 +/* 4444 */ MCD_OPC_CheckField, 18, 2, 0, 65, 66, 1, // Skip to: 86948 +/* 4451 */ MCD_OPC_Decode, 194, 5, 17, // Opcode: DUPM_ZI +/* 4455 */ MCD_OPC_FilterValue, 1, 56, 66, 1, // Skip to: 86948 +/* 4460 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 4463 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 4499 +/* 4468 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4471 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4485 +/* 4476 */ MCD_OPC_CheckPredicate, 0, 35, 66, 1, // Skip to: 86948 +/* 4481 */ MCD_OPC_Decode, 148, 5, 23, // Opcode: CPY_ZPzI_S +/* 4485 */ MCD_OPC_FilterValue, 1, 26, 66, 1, // Skip to: 86948 +/* 4490 */ MCD_OPC_CheckPredicate, 0, 21, 66, 1, // Skip to: 86948 +/* 4495 */ MCD_OPC_Decode, 146, 5, 24, // Opcode: CPY_ZPzI_D +/* 4499 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 4535 +/* 4504 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4507 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4521 +/* 4512 */ MCD_OPC_CheckPredicate, 0, 255, 65, 1, // Skip to: 86948 +/* 4517 */ MCD_OPC_Decode, 136, 5, 25, // Opcode: CPY_ZPmI_S +/* 4521 */ MCD_OPC_FilterValue, 1, 246, 65, 1, // Skip to: 86948 +/* 4526 */ MCD_OPC_CheckPredicate, 0, 241, 65, 1, // Skip to: 86948 +/* 4531 */ MCD_OPC_Decode, 134, 5, 26, // Opcode: CPY_ZPmI_D +/* 4535 */ MCD_OPC_FilterValue, 3, 232, 65, 1, // Skip to: 86948 +/* 4540 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 4543 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 4564 +/* 4548 */ MCD_OPC_CheckPredicate, 0, 219, 65, 1, // Skip to: 86948 +/* 4553 */ MCD_OPC_CheckField, 13, 1, 0, 212, 65, 1, // Skip to: 86948 +/* 4560 */ MCD_OPC_Decode, 213, 7, 22, // Opcode: FCPY_ZPmI_S +/* 4564 */ MCD_OPC_FilterValue, 1, 203, 65, 1, // Skip to: 86948 +/* 4569 */ MCD_OPC_CheckPredicate, 0, 198, 65, 1, // Skip to: 86948 +/* 4574 */ MCD_OPC_CheckField, 13, 1, 0, 191, 65, 1, // Skip to: 86948 +/* 4581 */ MCD_OPC_Decode, 211, 7, 22, // Opcode: FCPY_ZPmI_D +/* 4585 */ MCD_OPC_FilterValue, 1, 182, 65, 1, // Skip to: 86948 +/* 4590 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 4593 */ MCD_OPC_FilterValue, 0, 105, 4, 0, // Skip to: 5727 +/* 4598 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 4601 */ MCD_OPC_FilterValue, 0, 129, 1, 0, // Skip to: 4991 +/* 4606 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 4609 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 4701 +/* 4614 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 4617 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4631 +/* 4622 */ MCD_OPC_CheckPredicate, 0, 145, 65, 1, // Skip to: 86948 +/* 4627 */ MCD_OPC_Decode, 189, 1, 27, // Opcode: ADD_ZZZ_B +/* 4631 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4645 +/* 4636 */ MCD_OPC_CheckPredicate, 0, 131, 65, 1, // Skip to: 86948 +/* 4641 */ MCD_OPC_Decode, 251, 29, 27, // Opcode: SUB_ZZZ_B +/* 4645 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4659 +/* 4650 */ MCD_OPC_CheckPredicate, 0, 117, 65, 1, // Skip to: 86948 +/* 4655 */ MCD_OPC_Decode, 168, 24, 27, // Opcode: SQADD_ZZZ_B +/* 4659 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4673 +/* 4664 */ MCD_OPC_CheckPredicate, 0, 103, 65, 1, // Skip to: 86948 +/* 4669 */ MCD_OPC_Decode, 207, 32, 27, // Opcode: UQADD_ZZZ_B +/* 4673 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4687 +/* 4678 */ MCD_OPC_CheckPredicate, 0, 89, 65, 1, // Skip to: 86948 +/* 4683 */ MCD_OPC_Decode, 150, 26, 27, // Opcode: SQSUB_ZZZ_B +/* 4687 */ MCD_OPC_FilterValue, 7, 80, 65, 1, // Skip to: 86948 +/* 4692 */ MCD_OPC_CheckPredicate, 0, 75, 65, 1, // Skip to: 86948 +/* 4697 */ MCD_OPC_Decode, 193, 33, 27, // Opcode: UQSUB_ZZZ_B +/* 4701 */ MCD_OPC_FilterValue, 1, 87, 0, 0, // Skip to: 4793 +/* 4706 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 4709 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4723 +/* 4714 */ MCD_OPC_CheckPredicate, 0, 53, 65, 1, // Skip to: 86948 +/* 4719 */ MCD_OPC_Decode, 191, 1, 27, // Opcode: ADD_ZZZ_H +/* 4723 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4737 +/* 4728 */ MCD_OPC_CheckPredicate, 0, 39, 65, 1, // Skip to: 86948 +/* 4733 */ MCD_OPC_Decode, 253, 29, 27, // Opcode: SUB_ZZZ_H +/* 4737 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4751 +/* 4742 */ MCD_OPC_CheckPredicate, 0, 25, 65, 1, // Skip to: 86948 +/* 4747 */ MCD_OPC_Decode, 170, 24, 27, // Opcode: SQADD_ZZZ_H +/* 4751 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4765 +/* 4756 */ MCD_OPC_CheckPredicate, 0, 11, 65, 1, // Skip to: 86948 +/* 4761 */ MCD_OPC_Decode, 209, 32, 27, // Opcode: UQADD_ZZZ_H +/* 4765 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4779 +/* 4770 */ MCD_OPC_CheckPredicate, 0, 253, 64, 1, // Skip to: 86948 +/* 4775 */ MCD_OPC_Decode, 152, 26, 27, // Opcode: SQSUB_ZZZ_H +/* 4779 */ MCD_OPC_FilterValue, 7, 244, 64, 1, // Skip to: 86948 +/* 4784 */ MCD_OPC_CheckPredicate, 0, 239, 64, 1, // Skip to: 86948 +/* 4789 */ MCD_OPC_Decode, 195, 33, 27, // Opcode: UQSUB_ZZZ_H +/* 4793 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 4885 +/* 4798 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 4801 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4815 +/* 4806 */ MCD_OPC_CheckPredicate, 0, 217, 64, 1, // Skip to: 86948 +/* 4811 */ MCD_OPC_Decode, 192, 1, 27, // Opcode: ADD_ZZZ_S +/* 4815 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4829 +/* 4820 */ MCD_OPC_CheckPredicate, 0, 203, 64, 1, // Skip to: 86948 +/* 4825 */ MCD_OPC_Decode, 254, 29, 27, // Opcode: SUB_ZZZ_S +/* 4829 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4843 +/* 4834 */ MCD_OPC_CheckPredicate, 0, 189, 64, 1, // Skip to: 86948 +/* 4839 */ MCD_OPC_Decode, 171, 24, 27, // Opcode: SQADD_ZZZ_S +/* 4843 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4857 +/* 4848 */ MCD_OPC_CheckPredicate, 0, 175, 64, 1, // Skip to: 86948 +/* 4853 */ MCD_OPC_Decode, 210, 32, 27, // Opcode: UQADD_ZZZ_S +/* 4857 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4871 +/* 4862 */ MCD_OPC_CheckPredicate, 0, 161, 64, 1, // Skip to: 86948 +/* 4867 */ MCD_OPC_Decode, 153, 26, 27, // Opcode: SQSUB_ZZZ_S +/* 4871 */ MCD_OPC_FilterValue, 7, 152, 64, 1, // Skip to: 86948 +/* 4876 */ MCD_OPC_CheckPredicate, 0, 147, 64, 1, // Skip to: 86948 +/* 4881 */ MCD_OPC_Decode, 196, 33, 27, // Opcode: UQSUB_ZZZ_S +/* 4885 */ MCD_OPC_FilterValue, 3, 87, 0, 0, // Skip to: 4977 +/* 4890 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 4893 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 4907 +/* 4898 */ MCD_OPC_CheckPredicate, 0, 125, 64, 1, // Skip to: 86948 +/* 4903 */ MCD_OPC_Decode, 190, 1, 27, // Opcode: ADD_ZZZ_D +/* 4907 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 4921 +/* 4912 */ MCD_OPC_CheckPredicate, 0, 111, 64, 1, // Skip to: 86948 +/* 4917 */ MCD_OPC_Decode, 252, 29, 27, // Opcode: SUB_ZZZ_D +/* 4921 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 4935 +/* 4926 */ MCD_OPC_CheckPredicate, 0, 97, 64, 1, // Skip to: 86948 +/* 4931 */ MCD_OPC_Decode, 169, 24, 27, // Opcode: SQADD_ZZZ_D +/* 4935 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 4949 +/* 4940 */ MCD_OPC_CheckPredicate, 0, 83, 64, 1, // Skip to: 86948 +/* 4945 */ MCD_OPC_Decode, 208, 32, 27, // Opcode: UQADD_ZZZ_D +/* 4949 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 4963 +/* 4954 */ MCD_OPC_CheckPredicate, 0, 69, 64, 1, // Skip to: 86948 +/* 4959 */ MCD_OPC_Decode, 151, 26, 27, // Opcode: SQSUB_ZZZ_D +/* 4963 */ MCD_OPC_FilterValue, 7, 60, 64, 1, // Skip to: 86948 +/* 4968 */ MCD_OPC_CheckPredicate, 0, 55, 64, 1, // Skip to: 86948 +/* 4973 */ MCD_OPC_Decode, 194, 33, 27, // Opcode: UQSUB_ZZZ_D +/* 4977 */ MCD_OPC_FilterValue, 4, 46, 64, 1, // Skip to: 86948 +/* 4982 */ MCD_OPC_CheckPredicate, 0, 41, 64, 1, // Skip to: 86948 +/* 4987 */ MCD_OPC_Decode, 252, 5, 28, // Opcode: EXT_ZZI +/* 4991 */ MCD_OPC_FilterValue, 1, 32, 64, 1, // Skip to: 86948 +/* 4996 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 4999 */ MCD_OPC_FilterValue, 0, 139, 0, 0, // Skip to: 5143 +/* 5004 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 5007 */ MCD_OPC_FilterValue, 0, 110, 0, 0, // Skip to: 5122 +/* 5012 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 5015 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 5101 +/* 5020 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 5023 */ MCD_OPC_FilterValue, 0, 52, 0, 0, // Skip to: 5080 +/* 5028 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 5031 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 5059 +/* 5036 */ MCD_OPC_CheckPredicate, 0, 243, 63, 1, // Skip to: 86948 +/* 5041 */ MCD_OPC_CheckField, 24, 2, 1, 236, 63, 1, // Skip to: 86948 +/* 5048 */ MCD_OPC_CheckField, 20, 1, 1, 229, 63, 1, // Skip to: 86948 +/* 5055 */ MCD_OPC_Decode, 206, 5, 29, // Opcode: DUP_ZZI_Q +/* 5059 */ MCD_OPC_FilterValue, 1, 220, 63, 1, // Skip to: 86948 +/* 5064 */ MCD_OPC_CheckPredicate, 0, 215, 63, 1, // Skip to: 86948 +/* 5069 */ MCD_OPC_CheckField, 24, 2, 1, 208, 63, 1, // Skip to: 86948 +/* 5076 */ MCD_OPC_Decode, 204, 5, 30, // Opcode: DUP_ZZI_D +/* 5080 */ MCD_OPC_FilterValue, 1, 199, 63, 1, // Skip to: 86948 +/* 5085 */ MCD_OPC_CheckPredicate, 0, 194, 63, 1, // Skip to: 86948 +/* 5090 */ MCD_OPC_CheckField, 24, 2, 1, 187, 63, 1, // Skip to: 86948 +/* 5097 */ MCD_OPC_Decode, 207, 5, 31, // Opcode: DUP_ZZI_S +/* 5101 */ MCD_OPC_FilterValue, 1, 178, 63, 1, // Skip to: 86948 +/* 5106 */ MCD_OPC_CheckPredicate, 0, 173, 63, 1, // Skip to: 86948 +/* 5111 */ MCD_OPC_CheckField, 24, 2, 1, 166, 63, 1, // Skip to: 86948 +/* 5118 */ MCD_OPC_Decode, 205, 5, 32, // Opcode: DUP_ZZI_H +/* 5122 */ MCD_OPC_FilterValue, 1, 157, 63, 1, // Skip to: 86948 +/* 5127 */ MCD_OPC_CheckPredicate, 0, 152, 63, 1, // Skip to: 86948 +/* 5132 */ MCD_OPC_CheckField, 24, 2, 1, 145, 63, 1, // Skip to: 86948 +/* 5139 */ MCD_OPC_Decode, 203, 5, 33, // Opcode: DUP_ZZI_B +/* 5143 */ MCD_OPC_FilterValue, 4, 115, 0, 0, // Skip to: 5263 +/* 5148 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5151 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5165 +/* 5156 */ MCD_OPC_CheckPredicate, 0, 123, 63, 1, // Skip to: 86948 +/* 5161 */ MCD_OPC_Decode, 251, 1, 27, // Opcode: AND_ZZZ +/* 5165 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 5179 +/* 5170 */ MCD_OPC_CheckPredicate, 0, 109, 63, 1, // Skip to: 86948 +/* 5175 */ MCD_OPC_Decode, 216, 20, 27, // Opcode: ORR_ZZZ +/* 5179 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 5193 +/* 5184 */ MCD_OPC_CheckPredicate, 0, 95, 63, 1, // Skip to: 86948 +/* 5189 */ MCD_OPC_Decode, 244, 5, 27, // Opcode: EOR_ZZZ +/* 5193 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 5207 +/* 5198 */ MCD_OPC_CheckPredicate, 0, 81, 63, 1, // Skip to: 86948 +/* 5203 */ MCD_OPC_Decode, 186, 2, 27, // Opcode: BIC_ZZZ +/* 5207 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5221 +/* 5212 */ MCD_OPC_CheckPredicate, 0, 67, 63, 1, // Skip to: 86948 +/* 5217 */ MCD_OPC_Decode, 177, 30, 27, // Opcode: TBL_ZZZ_B +/* 5221 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5235 +/* 5226 */ MCD_OPC_CheckPredicate, 0, 53, 63, 1, // Skip to: 86948 +/* 5231 */ MCD_OPC_Decode, 179, 30, 27, // Opcode: TBL_ZZZ_H +/* 5235 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5249 +/* 5240 */ MCD_OPC_CheckPredicate, 0, 39, 63, 1, // Skip to: 86948 +/* 5245 */ MCD_OPC_Decode, 180, 30, 27, // Opcode: TBL_ZZZ_S +/* 5249 */ MCD_OPC_FilterValue, 7, 30, 63, 1, // Skip to: 86948 +/* 5254 */ MCD_OPC_CheckPredicate, 0, 25, 63, 1, // Skip to: 86948 +/* 5259 */ MCD_OPC_Decode, 178, 30, 27, // Opcode: TBL_ZZZ_D +/* 5263 */ MCD_OPC_FilterValue, 6, 16, 63, 1, // Skip to: 86948 +/* 5268 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 5271 */ MCD_OPC_FilterValue, 0, 59, 0, 0, // Skip to: 5335 +/* 5276 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5279 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5293 +/* 5284 */ MCD_OPC_CheckPredicate, 0, 251, 62, 1, // Skip to: 86948 +/* 5289 */ MCD_OPC_Decode, 199, 5, 34, // Opcode: DUP_ZR_B +/* 5293 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5307 +/* 5298 */ MCD_OPC_CheckPredicate, 0, 237, 62, 1, // Skip to: 86948 +/* 5303 */ MCD_OPC_Decode, 201, 5, 34, // Opcode: DUP_ZR_H +/* 5307 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5321 +/* 5312 */ MCD_OPC_CheckPredicate, 0, 223, 62, 1, // Skip to: 86948 +/* 5317 */ MCD_OPC_Decode, 202, 5, 34, // Opcode: DUP_ZR_S +/* 5321 */ MCD_OPC_FilterValue, 7, 214, 62, 1, // Skip to: 86948 +/* 5326 */ MCD_OPC_CheckPredicate, 0, 209, 62, 1, // Skip to: 86948 +/* 5331 */ MCD_OPC_Decode, 200, 5, 35, // Opcode: DUP_ZR_D +/* 5335 */ MCD_OPC_FilterValue, 4, 59, 0, 0, // Skip to: 5399 +/* 5340 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5343 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5357 +/* 5348 */ MCD_OPC_CheckPredicate, 0, 187, 62, 1, // Skip to: 86948 +/* 5353 */ MCD_OPC_Decode, 146, 14, 36, // Opcode: INSR_ZR_B +/* 5357 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5371 +/* 5362 */ MCD_OPC_CheckPredicate, 0, 173, 62, 1, // Skip to: 86948 +/* 5367 */ MCD_OPC_Decode, 148, 14, 36, // Opcode: INSR_ZR_H +/* 5371 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5385 +/* 5376 */ MCD_OPC_CheckPredicate, 0, 159, 62, 1, // Skip to: 86948 +/* 5381 */ MCD_OPC_Decode, 149, 14, 36, // Opcode: INSR_ZR_S +/* 5385 */ MCD_OPC_FilterValue, 7, 150, 62, 1, // Skip to: 86948 +/* 5390 */ MCD_OPC_CheckPredicate, 0, 145, 62, 1, // Skip to: 86948 +/* 5395 */ MCD_OPC_Decode, 147, 14, 37, // Opcode: INSR_ZR_D +/* 5399 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 5449 +/* 5404 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5407 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5421 +/* 5412 */ MCD_OPC_CheckPredicate, 0, 123, 62, 1, // Skip to: 86948 +/* 5417 */ MCD_OPC_Decode, 139, 30, 38, // Opcode: SUNPKLO_ZZ_H +/* 5421 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5435 +/* 5426 */ MCD_OPC_CheckPredicate, 0, 109, 62, 1, // Skip to: 86948 +/* 5431 */ MCD_OPC_Decode, 140, 30, 38, // Opcode: SUNPKLO_ZZ_S +/* 5435 */ MCD_OPC_FilterValue, 7, 100, 62, 1, // Skip to: 86948 +/* 5440 */ MCD_OPC_CheckPredicate, 0, 95, 62, 1, // Skip to: 86948 +/* 5445 */ MCD_OPC_Decode, 138, 30, 38, // Opcode: SUNPKLO_ZZ_D +/* 5449 */ MCD_OPC_FilterValue, 17, 45, 0, 0, // Skip to: 5499 +/* 5454 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5457 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5471 +/* 5462 */ MCD_OPC_CheckPredicate, 0, 73, 62, 1, // Skip to: 86948 +/* 5467 */ MCD_OPC_Decode, 136, 30, 38, // Opcode: SUNPKHI_ZZ_H +/* 5471 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5485 +/* 5476 */ MCD_OPC_CheckPredicate, 0, 59, 62, 1, // Skip to: 86948 +/* 5481 */ MCD_OPC_Decode, 137, 30, 38, // Opcode: SUNPKHI_ZZ_S +/* 5485 */ MCD_OPC_FilterValue, 7, 50, 62, 1, // Skip to: 86948 +/* 5490 */ MCD_OPC_CheckPredicate, 0, 45, 62, 1, // Skip to: 86948 +/* 5495 */ MCD_OPC_Decode, 135, 30, 38, // Opcode: SUNPKHI_ZZ_D +/* 5499 */ MCD_OPC_FilterValue, 18, 45, 0, 0, // Skip to: 5549 +/* 5504 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5507 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5521 +/* 5512 */ MCD_OPC_CheckPredicate, 0, 23, 62, 1, // Skip to: 86948 +/* 5517 */ MCD_OPC_Decode, 180, 34, 38, // Opcode: UUNPKLO_ZZ_H +/* 5521 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5535 +/* 5526 */ MCD_OPC_CheckPredicate, 0, 9, 62, 1, // Skip to: 86948 +/* 5531 */ MCD_OPC_Decode, 181, 34, 38, // Opcode: UUNPKLO_ZZ_S +/* 5535 */ MCD_OPC_FilterValue, 7, 0, 62, 1, // Skip to: 86948 +/* 5540 */ MCD_OPC_CheckPredicate, 0, 251, 61, 1, // Skip to: 86948 +/* 5545 */ MCD_OPC_Decode, 179, 34, 38, // Opcode: UUNPKLO_ZZ_D +/* 5549 */ MCD_OPC_FilterValue, 19, 45, 0, 0, // Skip to: 5599 +/* 5554 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5557 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5571 +/* 5562 */ MCD_OPC_CheckPredicate, 0, 229, 61, 1, // Skip to: 86948 +/* 5567 */ MCD_OPC_Decode, 177, 34, 38, // Opcode: UUNPKHI_ZZ_H +/* 5571 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5585 +/* 5576 */ MCD_OPC_CheckPredicate, 0, 215, 61, 1, // Skip to: 86948 +/* 5581 */ MCD_OPC_Decode, 178, 34, 38, // Opcode: UUNPKHI_ZZ_S +/* 5585 */ MCD_OPC_FilterValue, 7, 206, 61, 1, // Skip to: 86948 +/* 5590 */ MCD_OPC_CheckPredicate, 0, 201, 61, 1, // Skip to: 86948 +/* 5595 */ MCD_OPC_Decode, 176, 34, 38, // Opcode: UUNPKHI_ZZ_D +/* 5599 */ MCD_OPC_FilterValue, 20, 59, 0, 0, // Skip to: 5663 +/* 5604 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5607 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5621 +/* 5612 */ MCD_OPC_CheckPredicate, 0, 179, 61, 1, // Skip to: 86948 +/* 5617 */ MCD_OPC_Decode, 150, 14, 39, // Opcode: INSR_ZV_B +/* 5621 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5635 +/* 5626 */ MCD_OPC_CheckPredicate, 0, 165, 61, 1, // Skip to: 86948 +/* 5631 */ MCD_OPC_Decode, 152, 14, 40, // Opcode: INSR_ZV_H +/* 5635 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5649 +/* 5640 */ MCD_OPC_CheckPredicate, 0, 151, 61, 1, // Skip to: 86948 +/* 5645 */ MCD_OPC_Decode, 153, 14, 41, // Opcode: INSR_ZV_S +/* 5649 */ MCD_OPC_FilterValue, 7, 142, 61, 1, // Skip to: 86948 +/* 5654 */ MCD_OPC_CheckPredicate, 0, 137, 61, 1, // Skip to: 86948 +/* 5659 */ MCD_OPC_Decode, 151, 14, 42, // Opcode: INSR_ZV_D +/* 5663 */ MCD_OPC_FilterValue, 24, 128, 61, 1, // Skip to: 86948 +/* 5668 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5671 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 5685 +/* 5676 */ MCD_OPC_CheckPredicate, 0, 115, 61, 1, // Skip to: 86948 +/* 5681 */ MCD_OPC_Decode, 227, 21, 38, // Opcode: REV_ZZ_B +/* 5685 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 5699 +/* 5690 */ MCD_OPC_CheckPredicate, 0, 101, 61, 1, // Skip to: 86948 +/* 5695 */ MCD_OPC_Decode, 229, 21, 38, // Opcode: REV_ZZ_H +/* 5699 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 5713 +/* 5704 */ MCD_OPC_CheckPredicate, 0, 87, 61, 1, // Skip to: 86948 +/* 5709 */ MCD_OPC_Decode, 230, 21, 38, // Opcode: REV_ZZ_S +/* 5713 */ MCD_OPC_FilterValue, 7, 78, 61, 1, // Skip to: 86948 +/* 5718 */ MCD_OPC_CheckPredicate, 0, 73, 61, 1, // Skip to: 86948 +/* 5723 */ MCD_OPC_Decode, 228, 21, 38, // Opcode: REV_ZZ_D +/* 5727 */ MCD_OPC_FilterValue, 1, 229, 6, 0, // Skip to: 7497 +/* 5732 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 5735 */ MCD_OPC_FilterValue, 0, 89, 0, 0, // Skip to: 5829 +/* 5740 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 5743 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5779 +/* 5748 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 5751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5765 +/* 5756 */ MCD_OPC_CheckPredicate, 0, 35, 61, 1, // Skip to: 86948 +/* 5761 */ MCD_OPC_Decode, 130, 14, 43, // Opcode: INDEX_II_B +/* 5765 */ MCD_OPC_FilterValue, 1, 26, 61, 1, // Skip to: 86948 +/* 5770 */ MCD_OPC_CheckPredicate, 0, 21, 61, 1, // Skip to: 86948 +/* 5775 */ MCD_OPC_Decode, 138, 14, 44, // Opcode: INDEX_RI_B +/* 5779 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5815 +/* 5784 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 5787 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5801 +/* 5792 */ MCD_OPC_CheckPredicate, 0, 255, 60, 1, // Skip to: 86948 +/* 5797 */ MCD_OPC_Decode, 134, 14, 45, // Opcode: INDEX_IR_B +/* 5801 */ MCD_OPC_FilterValue, 1, 246, 60, 1, // Skip to: 86948 +/* 5806 */ MCD_OPC_CheckPredicate, 0, 241, 60, 1, // Skip to: 86948 +/* 5811 */ MCD_OPC_Decode, 142, 14, 46, // Opcode: INDEX_RR_B +/* 5815 */ MCD_OPC_FilterValue, 2, 232, 60, 1, // Skip to: 86948 +/* 5820 */ MCD_OPC_CheckPredicate, 0, 227, 60, 1, // Skip to: 86948 +/* 5825 */ MCD_OPC_Decode, 166, 1, 47, // Opcode: ADDVL_XXI +/* 5829 */ MCD_OPC_FilterValue, 1, 89, 0, 0, // Skip to: 5923 +/* 5834 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 5837 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5873 +/* 5842 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 5845 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5859 +/* 5850 */ MCD_OPC_CheckPredicate, 0, 197, 60, 1, // Skip to: 86948 +/* 5855 */ MCD_OPC_Decode, 132, 14, 43, // Opcode: INDEX_II_H +/* 5859 */ MCD_OPC_FilterValue, 1, 188, 60, 1, // Skip to: 86948 +/* 5864 */ MCD_OPC_CheckPredicate, 0, 183, 60, 1, // Skip to: 86948 +/* 5869 */ MCD_OPC_Decode, 140, 14, 44, // Opcode: INDEX_RI_H +/* 5873 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 5909 +/* 5878 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 5881 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5895 +/* 5886 */ MCD_OPC_CheckPredicate, 0, 161, 60, 1, // Skip to: 86948 +/* 5891 */ MCD_OPC_Decode, 136, 14, 45, // Opcode: INDEX_IR_H +/* 5895 */ MCD_OPC_FilterValue, 1, 152, 60, 1, // Skip to: 86948 +/* 5900 */ MCD_OPC_CheckPredicate, 0, 147, 60, 1, // Skip to: 86948 +/* 5905 */ MCD_OPC_Decode, 144, 14, 46, // Opcode: INDEX_RR_H +/* 5909 */ MCD_OPC_FilterValue, 2, 138, 60, 1, // Skip to: 86948 +/* 5914 */ MCD_OPC_CheckPredicate, 0, 133, 60, 1, // Skip to: 86948 +/* 5919 */ MCD_OPC_Decode, 148, 1, 47, // Opcode: ADDPL_XXI +/* 5923 */ MCD_OPC_FilterValue, 2, 96, 0, 0, // Skip to: 6024 +/* 5928 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 5931 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 5967 +/* 5936 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 5939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5953 +/* 5944 */ MCD_OPC_CheckPredicate, 0, 103, 60, 1, // Skip to: 86948 +/* 5949 */ MCD_OPC_Decode, 133, 14, 43, // Opcode: INDEX_II_S +/* 5953 */ MCD_OPC_FilterValue, 1, 94, 60, 1, // Skip to: 86948 +/* 5958 */ MCD_OPC_CheckPredicate, 0, 89, 60, 1, // Skip to: 86948 +/* 5963 */ MCD_OPC_Decode, 141, 14, 44, // Opcode: INDEX_RI_S +/* 5967 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 6003 +/* 5972 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 5975 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 5989 +/* 5980 */ MCD_OPC_CheckPredicate, 0, 67, 60, 1, // Skip to: 86948 +/* 5985 */ MCD_OPC_Decode, 137, 14, 45, // Opcode: INDEX_IR_S +/* 5989 */ MCD_OPC_FilterValue, 1, 58, 60, 1, // Skip to: 86948 +/* 5994 */ MCD_OPC_CheckPredicate, 0, 53, 60, 1, // Skip to: 86948 +/* 5999 */ MCD_OPC_Decode, 145, 14, 46, // Opcode: INDEX_RR_S +/* 6003 */ MCD_OPC_FilterValue, 2, 44, 60, 1, // Skip to: 86948 +/* 6008 */ MCD_OPC_CheckPredicate, 0, 39, 60, 1, // Skip to: 86948 +/* 6013 */ MCD_OPC_CheckField, 16, 5, 31, 32, 60, 1, // Skip to: 86948 +/* 6020 */ MCD_OPC_Decode, 195, 21, 48, // Opcode: RDVLI_XI +/* 6024 */ MCD_OPC_FilterValue, 3, 59, 0, 0, // Skip to: 6088 +/* 6029 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 6032 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 6046 +/* 6037 */ MCD_OPC_CheckPredicate, 0, 10, 60, 1, // Skip to: 86948 +/* 6042 */ MCD_OPC_Decode, 131, 14, 43, // Opcode: INDEX_II_D +/* 6046 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 6060 +/* 6051 */ MCD_OPC_CheckPredicate, 0, 252, 59, 1, // Skip to: 86948 +/* 6056 */ MCD_OPC_Decode, 139, 14, 49, // Opcode: INDEX_RI_D +/* 6060 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 6074 +/* 6065 */ MCD_OPC_CheckPredicate, 0, 238, 59, 1, // Skip to: 86948 +/* 6070 */ MCD_OPC_Decode, 135, 14, 50, // Opcode: INDEX_IR_D +/* 6074 */ MCD_OPC_FilterValue, 3, 229, 59, 1, // Skip to: 86948 +/* 6079 */ MCD_OPC_CheckPredicate, 0, 224, 59, 1, // Skip to: 86948 +/* 6084 */ MCD_OPC_Decode, 143, 14, 51, // Opcode: INDEX_RR_D +/* 6088 */ MCD_OPC_FilterValue, 4, 134, 1, 0, // Skip to: 6483 +/* 6093 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 6096 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 6224 +/* 6101 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6104 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6132 +/* 6109 */ MCD_OPC_CheckPredicate, 0, 194, 59, 1, // Skip to: 86948 +/* 6114 */ MCD_OPC_CheckField, 9, 1, 0, 187, 59, 1, // Skip to: 86948 +/* 6121 */ MCD_OPC_CheckField, 4, 1, 0, 180, 59, 1, // Skip to: 86948 +/* 6128 */ MCD_OPC_Decode, 133, 35, 52, // Opcode: ZIP1_PPP_B +/* 6132 */ MCD_OPC_FilterValue, 1, 171, 59, 1, // Skip to: 86948 +/* 6137 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 6140 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6168 +/* 6145 */ MCD_OPC_CheckPredicate, 0, 158, 59, 1, // Skip to: 86948 +/* 6150 */ MCD_OPC_CheckField, 9, 1, 0, 151, 59, 1, // Skip to: 86948 +/* 6157 */ MCD_OPC_CheckField, 4, 1, 0, 144, 59, 1, // Skip to: 86948 +/* 6164 */ MCD_OPC_Decode, 176, 21, 53, // Opcode: PUNPKLO_PP +/* 6168 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 6196 +/* 6173 */ MCD_OPC_CheckPredicate, 0, 130, 59, 1, // Skip to: 86948 +/* 6178 */ MCD_OPC_CheckField, 9, 1, 0, 123, 59, 1, // Skip to: 86948 +/* 6185 */ MCD_OPC_CheckField, 4, 1, 0, 116, 59, 1, // Skip to: 86948 +/* 6192 */ MCD_OPC_Decode, 175, 21, 53, // Opcode: PUNPKHI_PP +/* 6196 */ MCD_OPC_FilterValue, 4, 107, 59, 1, // Skip to: 86948 +/* 6201 */ MCD_OPC_CheckPredicate, 0, 102, 59, 1, // Skip to: 86948 +/* 6206 */ MCD_OPC_CheckField, 9, 1, 0, 95, 59, 1, // Skip to: 86948 +/* 6213 */ MCD_OPC_CheckField, 4, 1, 0, 88, 59, 1, // Skip to: 86948 +/* 6220 */ MCD_OPC_Decode, 223, 21, 53, // Opcode: REV_PP_B +/* 6224 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6259 +/* 6229 */ MCD_OPC_CheckPredicate, 0, 74, 59, 1, // Skip to: 86948 +/* 6234 */ MCD_OPC_CheckField, 20, 1, 0, 67, 59, 1, // Skip to: 86948 +/* 6241 */ MCD_OPC_CheckField, 9, 1, 0, 60, 59, 1, // Skip to: 86948 +/* 6248 */ MCD_OPC_CheckField, 4, 1, 0, 53, 59, 1, // Skip to: 86948 +/* 6255 */ MCD_OPC_Decode, 148, 35, 52, // Opcode: ZIP2_PPP_B +/* 6259 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6294 +/* 6264 */ MCD_OPC_CheckPredicate, 0, 39, 59, 1, // Skip to: 86948 +/* 6269 */ MCD_OPC_CheckField, 20, 1, 0, 32, 59, 1, // Skip to: 86948 +/* 6276 */ MCD_OPC_CheckField, 9, 1, 0, 25, 59, 1, // Skip to: 86948 +/* 6283 */ MCD_OPC_CheckField, 4, 1, 0, 18, 59, 1, // Skip to: 86948 +/* 6290 */ MCD_OPC_Decode, 188, 34, 52, // Opcode: UZP1_PPP_B +/* 6294 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 6329 +/* 6299 */ MCD_OPC_CheckPredicate, 0, 4, 59, 1, // Skip to: 86948 +/* 6304 */ MCD_OPC_CheckField, 20, 1, 0, 253, 58, 1, // Skip to: 86948 +/* 6311 */ MCD_OPC_CheckField, 9, 1, 0, 246, 58, 1, // Skip to: 86948 +/* 6318 */ MCD_OPC_CheckField, 4, 1, 0, 239, 58, 1, // Skip to: 86948 +/* 6325 */ MCD_OPC_Decode, 203, 34, 52, // Opcode: UZP2_PPP_B +/* 6329 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 6364 +/* 6334 */ MCD_OPC_CheckPredicate, 0, 225, 58, 1, // Skip to: 86948 +/* 6339 */ MCD_OPC_CheckField, 20, 1, 0, 218, 58, 1, // Skip to: 86948 +/* 6346 */ MCD_OPC_CheckField, 9, 1, 0, 211, 58, 1, // Skip to: 86948 +/* 6353 */ MCD_OPC_CheckField, 4, 1, 0, 204, 58, 1, // Skip to: 86948 +/* 6360 */ MCD_OPC_Decode, 205, 30, 52, // Opcode: TRN1_PPP_B +/* 6364 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 6399 +/* 6369 */ MCD_OPC_CheckPredicate, 0, 190, 58, 1, // Skip to: 86948 +/* 6374 */ MCD_OPC_CheckField, 20, 1, 0, 183, 58, 1, // Skip to: 86948 +/* 6381 */ MCD_OPC_CheckField, 9, 1, 0, 176, 58, 1, // Skip to: 86948 +/* 6388 */ MCD_OPC_CheckField, 4, 1, 0, 169, 58, 1, // Skip to: 86948 +/* 6395 */ MCD_OPC_Decode, 220, 30, 52, // Opcode: TRN2_PPP_B +/* 6399 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6413 +/* 6404 */ MCD_OPC_CheckPredicate, 0, 155, 58, 1, // Skip to: 86948 +/* 6409 */ MCD_OPC_Decode, 137, 35, 27, // Opcode: ZIP1_ZZZ_B +/* 6413 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6427 +/* 6418 */ MCD_OPC_CheckPredicate, 0, 141, 58, 1, // Skip to: 86948 +/* 6423 */ MCD_OPC_Decode, 152, 35, 27, // Opcode: ZIP2_ZZZ_B +/* 6427 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 6441 +/* 6432 */ MCD_OPC_CheckPredicate, 0, 127, 58, 1, // Skip to: 86948 +/* 6437 */ MCD_OPC_Decode, 192, 34, 27, // Opcode: UZP1_ZZZ_B +/* 6441 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6455 +/* 6446 */ MCD_OPC_CheckPredicate, 0, 113, 58, 1, // Skip to: 86948 +/* 6451 */ MCD_OPC_Decode, 207, 34, 27, // Opcode: UZP2_ZZZ_B +/* 6455 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 6469 +/* 6460 */ MCD_OPC_CheckPredicate, 0, 99, 58, 1, // Skip to: 86948 +/* 6465 */ MCD_OPC_Decode, 209, 30, 27, // Opcode: TRN1_ZZZ_B +/* 6469 */ MCD_OPC_FilterValue, 13, 90, 58, 1, // Skip to: 86948 +/* 6474 */ MCD_OPC_CheckPredicate, 0, 85, 58, 1, // Skip to: 86948 +/* 6479 */ MCD_OPC_Decode, 224, 30, 27, // Opcode: TRN2_ZZZ_B +/* 6483 */ MCD_OPC_FilterValue, 5, 77, 1, 0, // Skip to: 6821 +/* 6488 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 6491 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 6562 +/* 6496 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6499 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6527 +/* 6504 */ MCD_OPC_CheckPredicate, 0, 55, 58, 1, // Skip to: 86948 +/* 6509 */ MCD_OPC_CheckField, 9, 1, 0, 48, 58, 1, // Skip to: 86948 +/* 6516 */ MCD_OPC_CheckField, 4, 1, 0, 41, 58, 1, // Skip to: 86948 +/* 6523 */ MCD_OPC_Decode, 135, 35, 52, // Opcode: ZIP1_PPP_H +/* 6527 */ MCD_OPC_FilterValue, 1, 32, 58, 1, // Skip to: 86948 +/* 6532 */ MCD_OPC_CheckPredicate, 0, 27, 58, 1, // Skip to: 86948 +/* 6537 */ MCD_OPC_CheckField, 16, 4, 4, 20, 58, 1, // Skip to: 86948 +/* 6544 */ MCD_OPC_CheckField, 9, 1, 0, 13, 58, 1, // Skip to: 86948 +/* 6551 */ MCD_OPC_CheckField, 4, 1, 0, 6, 58, 1, // Skip to: 86948 +/* 6558 */ MCD_OPC_Decode, 225, 21, 53, // Opcode: REV_PP_H +/* 6562 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6597 +/* 6567 */ MCD_OPC_CheckPredicate, 0, 248, 57, 1, // Skip to: 86948 +/* 6572 */ MCD_OPC_CheckField, 20, 1, 0, 241, 57, 1, // Skip to: 86948 +/* 6579 */ MCD_OPC_CheckField, 9, 1, 0, 234, 57, 1, // Skip to: 86948 +/* 6586 */ MCD_OPC_CheckField, 4, 1, 0, 227, 57, 1, // Skip to: 86948 +/* 6593 */ MCD_OPC_Decode, 150, 35, 52, // Opcode: ZIP2_PPP_H +/* 6597 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6632 +/* 6602 */ MCD_OPC_CheckPredicate, 0, 213, 57, 1, // Skip to: 86948 +/* 6607 */ MCD_OPC_CheckField, 20, 1, 0, 206, 57, 1, // Skip to: 86948 +/* 6614 */ MCD_OPC_CheckField, 9, 1, 0, 199, 57, 1, // Skip to: 86948 +/* 6621 */ MCD_OPC_CheckField, 4, 1, 0, 192, 57, 1, // Skip to: 86948 +/* 6628 */ MCD_OPC_Decode, 190, 34, 52, // Opcode: UZP1_PPP_H +/* 6632 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 6667 +/* 6637 */ MCD_OPC_CheckPredicate, 0, 178, 57, 1, // Skip to: 86948 +/* 6642 */ MCD_OPC_CheckField, 20, 1, 0, 171, 57, 1, // Skip to: 86948 +/* 6649 */ MCD_OPC_CheckField, 9, 1, 0, 164, 57, 1, // Skip to: 86948 +/* 6656 */ MCD_OPC_CheckField, 4, 1, 0, 157, 57, 1, // Skip to: 86948 +/* 6663 */ MCD_OPC_Decode, 205, 34, 52, // Opcode: UZP2_PPP_H +/* 6667 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 6702 +/* 6672 */ MCD_OPC_CheckPredicate, 0, 143, 57, 1, // Skip to: 86948 +/* 6677 */ MCD_OPC_CheckField, 20, 1, 0, 136, 57, 1, // Skip to: 86948 +/* 6684 */ MCD_OPC_CheckField, 9, 1, 0, 129, 57, 1, // Skip to: 86948 +/* 6691 */ MCD_OPC_CheckField, 4, 1, 0, 122, 57, 1, // Skip to: 86948 +/* 6698 */ MCD_OPC_Decode, 207, 30, 52, // Opcode: TRN1_PPP_H +/* 6702 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 6737 +/* 6707 */ MCD_OPC_CheckPredicate, 0, 108, 57, 1, // Skip to: 86948 +/* 6712 */ MCD_OPC_CheckField, 20, 1, 0, 101, 57, 1, // Skip to: 86948 +/* 6719 */ MCD_OPC_CheckField, 9, 1, 0, 94, 57, 1, // Skip to: 86948 +/* 6726 */ MCD_OPC_CheckField, 4, 1, 0, 87, 57, 1, // Skip to: 86948 +/* 6733 */ MCD_OPC_Decode, 222, 30, 52, // Opcode: TRN2_PPP_H +/* 6737 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 6751 +/* 6742 */ MCD_OPC_CheckPredicate, 0, 73, 57, 1, // Skip to: 86948 +/* 6747 */ MCD_OPC_Decode, 139, 35, 27, // Opcode: ZIP1_ZZZ_H +/* 6751 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 6765 +/* 6756 */ MCD_OPC_CheckPredicate, 0, 59, 57, 1, // Skip to: 86948 +/* 6761 */ MCD_OPC_Decode, 154, 35, 27, // Opcode: ZIP2_ZZZ_H +/* 6765 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 6779 +/* 6770 */ MCD_OPC_CheckPredicate, 0, 45, 57, 1, // Skip to: 86948 +/* 6775 */ MCD_OPC_Decode, 194, 34, 27, // Opcode: UZP1_ZZZ_H +/* 6779 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 6793 +/* 6784 */ MCD_OPC_CheckPredicate, 0, 31, 57, 1, // Skip to: 86948 +/* 6789 */ MCD_OPC_Decode, 209, 34, 27, // Opcode: UZP2_ZZZ_H +/* 6793 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 6807 +/* 6798 */ MCD_OPC_CheckPredicate, 0, 17, 57, 1, // Skip to: 86948 +/* 6803 */ MCD_OPC_Decode, 211, 30, 27, // Opcode: TRN1_ZZZ_H +/* 6807 */ MCD_OPC_FilterValue, 13, 8, 57, 1, // Skip to: 86948 +/* 6812 */ MCD_OPC_CheckPredicate, 0, 3, 57, 1, // Skip to: 86948 +/* 6817 */ MCD_OPC_Decode, 226, 30, 27, // Opcode: TRN2_ZZZ_H +/* 6821 */ MCD_OPC_FilterValue, 6, 77, 1, 0, // Skip to: 7159 +/* 6826 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 6829 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 6900 +/* 6834 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 6837 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 6865 +/* 6842 */ MCD_OPC_CheckPredicate, 0, 229, 56, 1, // Skip to: 86948 +/* 6847 */ MCD_OPC_CheckField, 9, 1, 0, 222, 56, 1, // Skip to: 86948 +/* 6854 */ MCD_OPC_CheckField, 4, 1, 0, 215, 56, 1, // Skip to: 86948 +/* 6861 */ MCD_OPC_Decode, 136, 35, 52, // Opcode: ZIP1_PPP_S +/* 6865 */ MCD_OPC_FilterValue, 1, 206, 56, 1, // Skip to: 86948 +/* 6870 */ MCD_OPC_CheckPredicate, 0, 201, 56, 1, // Skip to: 86948 +/* 6875 */ MCD_OPC_CheckField, 16, 4, 4, 194, 56, 1, // Skip to: 86948 +/* 6882 */ MCD_OPC_CheckField, 9, 1, 0, 187, 56, 1, // Skip to: 86948 +/* 6889 */ MCD_OPC_CheckField, 4, 1, 0, 180, 56, 1, // Skip to: 86948 +/* 6896 */ MCD_OPC_Decode, 226, 21, 53, // Opcode: REV_PP_S +/* 6900 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 6935 +/* 6905 */ MCD_OPC_CheckPredicate, 0, 166, 56, 1, // Skip to: 86948 +/* 6910 */ MCD_OPC_CheckField, 20, 1, 0, 159, 56, 1, // Skip to: 86948 +/* 6917 */ MCD_OPC_CheckField, 9, 1, 0, 152, 56, 1, // Skip to: 86948 +/* 6924 */ MCD_OPC_CheckField, 4, 1, 0, 145, 56, 1, // Skip to: 86948 +/* 6931 */ MCD_OPC_Decode, 151, 35, 52, // Opcode: ZIP2_PPP_S +/* 6935 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 6970 +/* 6940 */ MCD_OPC_CheckPredicate, 0, 131, 56, 1, // Skip to: 86948 +/* 6945 */ MCD_OPC_CheckField, 20, 1, 0, 124, 56, 1, // Skip to: 86948 +/* 6952 */ MCD_OPC_CheckField, 9, 1, 0, 117, 56, 1, // Skip to: 86948 +/* 6959 */ MCD_OPC_CheckField, 4, 1, 0, 110, 56, 1, // Skip to: 86948 +/* 6966 */ MCD_OPC_Decode, 191, 34, 52, // Opcode: UZP1_PPP_S +/* 6970 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 7005 +/* 6975 */ MCD_OPC_CheckPredicate, 0, 96, 56, 1, // Skip to: 86948 +/* 6980 */ MCD_OPC_CheckField, 20, 1, 0, 89, 56, 1, // Skip to: 86948 +/* 6987 */ MCD_OPC_CheckField, 9, 1, 0, 82, 56, 1, // Skip to: 86948 +/* 6994 */ MCD_OPC_CheckField, 4, 1, 0, 75, 56, 1, // Skip to: 86948 +/* 7001 */ MCD_OPC_Decode, 206, 34, 52, // Opcode: UZP2_PPP_S +/* 7005 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 7040 +/* 7010 */ MCD_OPC_CheckPredicate, 0, 61, 56, 1, // Skip to: 86948 +/* 7015 */ MCD_OPC_CheckField, 20, 1, 0, 54, 56, 1, // Skip to: 86948 +/* 7022 */ MCD_OPC_CheckField, 9, 1, 0, 47, 56, 1, // Skip to: 86948 +/* 7029 */ MCD_OPC_CheckField, 4, 1, 0, 40, 56, 1, // Skip to: 86948 +/* 7036 */ MCD_OPC_Decode, 208, 30, 52, // Opcode: TRN1_PPP_S +/* 7040 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 7075 +/* 7045 */ MCD_OPC_CheckPredicate, 0, 26, 56, 1, // Skip to: 86948 +/* 7050 */ MCD_OPC_CheckField, 20, 1, 0, 19, 56, 1, // Skip to: 86948 +/* 7057 */ MCD_OPC_CheckField, 9, 1, 0, 12, 56, 1, // Skip to: 86948 +/* 7064 */ MCD_OPC_CheckField, 4, 1, 0, 5, 56, 1, // Skip to: 86948 +/* 7071 */ MCD_OPC_Decode, 223, 30, 52, // Opcode: TRN2_PPP_S +/* 7075 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7089 +/* 7080 */ MCD_OPC_CheckPredicate, 0, 247, 55, 1, // Skip to: 86948 +/* 7085 */ MCD_OPC_Decode, 140, 35, 27, // Opcode: ZIP1_ZZZ_S +/* 7089 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 7103 +/* 7094 */ MCD_OPC_CheckPredicate, 0, 233, 55, 1, // Skip to: 86948 +/* 7099 */ MCD_OPC_Decode, 155, 35, 27, // Opcode: ZIP2_ZZZ_S +/* 7103 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7117 +/* 7108 */ MCD_OPC_CheckPredicate, 0, 219, 55, 1, // Skip to: 86948 +/* 7113 */ MCD_OPC_Decode, 195, 34, 27, // Opcode: UZP1_ZZZ_S +/* 7117 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 7131 +/* 7122 */ MCD_OPC_CheckPredicate, 0, 205, 55, 1, // Skip to: 86948 +/* 7127 */ MCD_OPC_Decode, 210, 34, 27, // Opcode: UZP2_ZZZ_S +/* 7131 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 7145 +/* 7136 */ MCD_OPC_CheckPredicate, 0, 191, 55, 1, // Skip to: 86948 +/* 7141 */ MCD_OPC_Decode, 212, 30, 27, // Opcode: TRN1_ZZZ_S +/* 7145 */ MCD_OPC_FilterValue, 13, 182, 55, 1, // Skip to: 86948 +/* 7150 */ MCD_OPC_CheckPredicate, 0, 177, 55, 1, // Skip to: 86948 +/* 7155 */ MCD_OPC_Decode, 227, 30, 27, // Opcode: TRN2_ZZZ_S +/* 7159 */ MCD_OPC_FilterValue, 7, 168, 55, 1, // Skip to: 86948 +/* 7164 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 7167 */ MCD_OPC_FilterValue, 0, 66, 0, 0, // Skip to: 7238 +/* 7172 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7175 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 7203 +/* 7180 */ MCD_OPC_CheckPredicate, 0, 147, 55, 1, // Skip to: 86948 +/* 7185 */ MCD_OPC_CheckField, 9, 1, 0, 140, 55, 1, // Skip to: 86948 +/* 7192 */ MCD_OPC_CheckField, 4, 1, 0, 133, 55, 1, // Skip to: 86948 +/* 7199 */ MCD_OPC_Decode, 134, 35, 52, // Opcode: ZIP1_PPP_D +/* 7203 */ MCD_OPC_FilterValue, 1, 124, 55, 1, // Skip to: 86948 +/* 7208 */ MCD_OPC_CheckPredicate, 0, 119, 55, 1, // Skip to: 86948 +/* 7213 */ MCD_OPC_CheckField, 16, 4, 4, 112, 55, 1, // Skip to: 86948 +/* 7220 */ MCD_OPC_CheckField, 9, 1, 0, 105, 55, 1, // Skip to: 86948 +/* 7227 */ MCD_OPC_CheckField, 4, 1, 0, 98, 55, 1, // Skip to: 86948 +/* 7234 */ MCD_OPC_Decode, 224, 21, 53, // Opcode: REV_PP_D +/* 7238 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 7273 +/* 7243 */ MCD_OPC_CheckPredicate, 0, 84, 55, 1, // Skip to: 86948 +/* 7248 */ MCD_OPC_CheckField, 20, 1, 0, 77, 55, 1, // Skip to: 86948 +/* 7255 */ MCD_OPC_CheckField, 9, 1, 0, 70, 55, 1, // Skip to: 86948 +/* 7262 */ MCD_OPC_CheckField, 4, 1, 0, 63, 55, 1, // Skip to: 86948 +/* 7269 */ MCD_OPC_Decode, 149, 35, 52, // Opcode: ZIP2_PPP_D +/* 7273 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 7308 +/* 7278 */ MCD_OPC_CheckPredicate, 0, 49, 55, 1, // Skip to: 86948 +/* 7283 */ MCD_OPC_CheckField, 20, 1, 0, 42, 55, 1, // Skip to: 86948 +/* 7290 */ MCD_OPC_CheckField, 9, 1, 0, 35, 55, 1, // Skip to: 86948 +/* 7297 */ MCD_OPC_CheckField, 4, 1, 0, 28, 55, 1, // Skip to: 86948 +/* 7304 */ MCD_OPC_Decode, 189, 34, 52, // Opcode: UZP1_PPP_D +/* 7308 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 7343 +/* 7313 */ MCD_OPC_CheckPredicate, 0, 14, 55, 1, // Skip to: 86948 +/* 7318 */ MCD_OPC_CheckField, 20, 1, 0, 7, 55, 1, // Skip to: 86948 +/* 7325 */ MCD_OPC_CheckField, 9, 1, 0, 0, 55, 1, // Skip to: 86948 +/* 7332 */ MCD_OPC_CheckField, 4, 1, 0, 249, 54, 1, // Skip to: 86948 +/* 7339 */ MCD_OPC_Decode, 204, 34, 52, // Opcode: UZP2_PPP_D +/* 7343 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 7378 +/* 7348 */ MCD_OPC_CheckPredicate, 0, 235, 54, 1, // Skip to: 86948 +/* 7353 */ MCD_OPC_CheckField, 20, 1, 0, 228, 54, 1, // Skip to: 86948 +/* 7360 */ MCD_OPC_CheckField, 9, 1, 0, 221, 54, 1, // Skip to: 86948 +/* 7367 */ MCD_OPC_CheckField, 4, 1, 0, 214, 54, 1, // Skip to: 86948 +/* 7374 */ MCD_OPC_Decode, 206, 30, 52, // Opcode: TRN1_PPP_D +/* 7378 */ MCD_OPC_FilterValue, 5, 30, 0, 0, // Skip to: 7413 +/* 7383 */ MCD_OPC_CheckPredicate, 0, 200, 54, 1, // Skip to: 86948 +/* 7388 */ MCD_OPC_CheckField, 20, 1, 0, 193, 54, 1, // Skip to: 86948 +/* 7395 */ MCD_OPC_CheckField, 9, 1, 0, 186, 54, 1, // Skip to: 86948 +/* 7402 */ MCD_OPC_CheckField, 4, 1, 0, 179, 54, 1, // Skip to: 86948 +/* 7409 */ MCD_OPC_Decode, 221, 30, 52, // Opcode: TRN2_PPP_D +/* 7413 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 7427 +/* 7418 */ MCD_OPC_CheckPredicate, 0, 165, 54, 1, // Skip to: 86948 +/* 7423 */ MCD_OPC_Decode, 138, 35, 27, // Opcode: ZIP1_ZZZ_D +/* 7427 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 7441 +/* 7432 */ MCD_OPC_CheckPredicate, 0, 151, 54, 1, // Skip to: 86948 +/* 7437 */ MCD_OPC_Decode, 153, 35, 27, // Opcode: ZIP2_ZZZ_D +/* 7441 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 7455 +/* 7446 */ MCD_OPC_CheckPredicate, 0, 137, 54, 1, // Skip to: 86948 +/* 7451 */ MCD_OPC_Decode, 193, 34, 27, // Opcode: UZP1_ZZZ_D +/* 7455 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 7469 +/* 7460 */ MCD_OPC_CheckPredicate, 0, 123, 54, 1, // Skip to: 86948 +/* 7465 */ MCD_OPC_Decode, 208, 34, 27, // Opcode: UZP2_ZZZ_D +/* 7469 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 7483 +/* 7474 */ MCD_OPC_CheckPredicate, 0, 109, 54, 1, // Skip to: 86948 +/* 7479 */ MCD_OPC_Decode, 210, 30, 27, // Opcode: TRN1_ZZZ_D +/* 7483 */ MCD_OPC_FilterValue, 13, 100, 54, 1, // Skip to: 86948 +/* 7488 */ MCD_OPC_CheckPredicate, 0, 95, 54, 1, // Skip to: 86948 +/* 7493 */ MCD_OPC_Decode, 225, 30, 27, // Opcode: TRN2_ZZZ_D +/* 7497 */ MCD_OPC_FilterValue, 2, 96, 9, 0, // Skip to: 9902 +/* 7502 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 7505 */ MCD_OPC_FilterValue, 0, 15, 2, 0, // Skip to: 8037 +/* 7510 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 7513 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 7549 +/* 7518 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7521 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7535 +/* 7526 */ MCD_OPC_CheckPredicate, 0, 57, 54, 1, // Skip to: 86948 +/* 7531 */ MCD_OPC_Decode, 139, 2, 27, // Opcode: ASR_WIDE_ZZZ_B +/* 7535 */ MCD_OPC_FilterValue, 1, 48, 54, 1, // Skip to: 86948 +/* 7540 */ MCD_OPC_CheckPredicate, 0, 43, 54, 1, // Skip to: 86948 +/* 7545 */ MCD_OPC_Decode, 140, 2, 27, // Opcode: ASR_WIDE_ZZZ_H +/* 7549 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 7585 +/* 7554 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7557 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7571 +/* 7562 */ MCD_OPC_CheckPredicate, 0, 21, 54, 1, // Skip to: 86948 +/* 7567 */ MCD_OPC_Decode, 184, 19, 27, // Opcode: LSR_WIDE_ZZZ_B +/* 7571 */ MCD_OPC_FilterValue, 1, 12, 54, 1, // Skip to: 86948 +/* 7576 */ MCD_OPC_CheckPredicate, 0, 7, 54, 1, // Skip to: 86948 +/* 7581 */ MCD_OPC_Decode, 185, 19, 27, // Opcode: LSR_WIDE_ZZZ_H +/* 7585 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 7621 +/* 7590 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7593 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7607 +/* 7598 */ MCD_OPC_CheckPredicate, 0, 241, 53, 1, // Skip to: 86948 +/* 7603 */ MCD_OPC_Decode, 160, 19, 27, // Opcode: LSL_WIDE_ZZZ_B +/* 7607 */ MCD_OPC_FilterValue, 1, 232, 53, 1, // Skip to: 86948 +/* 7612 */ MCD_OPC_CheckPredicate, 0, 227, 53, 1, // Skip to: 86948 +/* 7617 */ MCD_OPC_Decode, 161, 19, 27, // Opcode: LSL_WIDE_ZZZ_H +/* 7621 */ MCD_OPC_FilterValue, 4, 60, 0, 0, // Skip to: 7686 +/* 7626 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7629 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7672 +/* 7634 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7637 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7658 +/* 7642 */ MCD_OPC_CheckPredicate, 0, 197, 53, 1, // Skip to: 86948 +/* 7647 */ MCD_OPC_CheckField, 19, 1, 1, 190, 53, 1, // Skip to: 86948 +/* 7654 */ MCD_OPC_Decode, 150, 2, 54, // Opcode: ASR_ZZI_B +/* 7658 */ MCD_OPC_FilterValue, 1, 181, 53, 1, // Skip to: 86948 +/* 7663 */ MCD_OPC_CheckPredicate, 0, 176, 53, 1, // Skip to: 86948 +/* 7668 */ MCD_OPC_Decode, 152, 2, 55, // Opcode: ASR_ZZI_H +/* 7672 */ MCD_OPC_FilterValue, 1, 167, 53, 1, // Skip to: 86948 +/* 7677 */ MCD_OPC_CheckPredicate, 0, 162, 53, 1, // Skip to: 86948 +/* 7682 */ MCD_OPC_Decode, 153, 2, 56, // Opcode: ASR_ZZI_S +/* 7686 */ MCD_OPC_FilterValue, 5, 60, 0, 0, // Skip to: 7751 +/* 7691 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7694 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7737 +/* 7699 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7702 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7723 +/* 7707 */ MCD_OPC_CheckPredicate, 0, 132, 53, 1, // Skip to: 86948 +/* 7712 */ MCD_OPC_CheckField, 19, 1, 1, 125, 53, 1, // Skip to: 86948 +/* 7719 */ MCD_OPC_Decode, 195, 19, 54, // Opcode: LSR_ZZI_B +/* 7723 */ MCD_OPC_FilterValue, 1, 116, 53, 1, // Skip to: 86948 +/* 7728 */ MCD_OPC_CheckPredicate, 0, 111, 53, 1, // Skip to: 86948 +/* 7733 */ MCD_OPC_Decode, 197, 19, 55, // Opcode: LSR_ZZI_H +/* 7737 */ MCD_OPC_FilterValue, 1, 102, 53, 1, // Skip to: 86948 +/* 7742 */ MCD_OPC_CheckPredicate, 0, 97, 53, 1, // Skip to: 86948 +/* 7747 */ MCD_OPC_Decode, 198, 19, 56, // Opcode: LSR_ZZI_S +/* 7751 */ MCD_OPC_FilterValue, 7, 60, 0, 0, // Skip to: 7816 +/* 7756 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7759 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 7802 +/* 7764 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 7767 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 7788 +/* 7772 */ MCD_OPC_CheckPredicate, 0, 67, 53, 1, // Skip to: 86948 +/* 7777 */ MCD_OPC_CheckField, 19, 1, 1, 60, 53, 1, // Skip to: 86948 +/* 7784 */ MCD_OPC_Decode, 171, 19, 57, // Opcode: LSL_ZZI_B +/* 7788 */ MCD_OPC_FilterValue, 1, 51, 53, 1, // Skip to: 86948 +/* 7793 */ MCD_OPC_CheckPredicate, 0, 46, 53, 1, // Skip to: 86948 +/* 7798 */ MCD_OPC_Decode, 173, 19, 58, // Opcode: LSL_ZZI_H +/* 7802 */ MCD_OPC_FilterValue, 1, 37, 53, 1, // Skip to: 86948 +/* 7807 */ MCD_OPC_CheckPredicate, 0, 32, 53, 1, // Skip to: 86948 +/* 7812 */ MCD_OPC_Decode, 174, 19, 59, // Opcode: LSL_ZZI_S +/* 7816 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 7852 +/* 7821 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7824 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7838 +/* 7829 */ MCD_OPC_CheckPredicate, 0, 10, 53, 1, // Skip to: 86948 +/* 7834 */ MCD_OPC_Decode, 214, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_0 +/* 7838 */ MCD_OPC_FilterValue, 1, 1, 53, 1, // Skip to: 86948 +/* 7843 */ MCD_OPC_CheckPredicate, 0, 252, 52, 1, // Skip to: 86948 +/* 7848 */ MCD_OPC_Decode, 218, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_0 +/* 7852 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 7888 +/* 7857 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7860 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7874 +/* 7865 */ MCD_OPC_CheckPredicate, 0, 230, 52, 1, // Skip to: 86948 +/* 7870 */ MCD_OPC_Decode, 215, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_1 +/* 7874 */ MCD_OPC_FilterValue, 1, 221, 52, 1, // Skip to: 86948 +/* 7879 */ MCD_OPC_CheckPredicate, 0, 216, 52, 1, // Skip to: 86948 +/* 7884 */ MCD_OPC_Decode, 219, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_1 +/* 7888 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 7924 +/* 7893 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7896 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7910 +/* 7901 */ MCD_OPC_CheckPredicate, 0, 194, 52, 1, // Skip to: 86948 +/* 7906 */ MCD_OPC_Decode, 216, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_2 +/* 7910 */ MCD_OPC_FilterValue, 1, 185, 52, 1, // Skip to: 86948 +/* 7915 */ MCD_OPC_CheckPredicate, 0, 180, 52, 1, // Skip to: 86948 +/* 7920 */ MCD_OPC_Decode, 220, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_2 +/* 7924 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 7960 +/* 7929 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 7932 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 7946 +/* 7937 */ MCD_OPC_CheckPredicate, 0, 158, 52, 1, // Skip to: 86948 +/* 7942 */ MCD_OPC_Decode, 217, 1, 27, // Opcode: ADR_SXTW_ZZZ_D_3 +/* 7946 */ MCD_OPC_FilterValue, 1, 149, 52, 1, // Skip to: 86948 +/* 7951 */ MCD_OPC_CheckPredicate, 0, 144, 52, 1, // Skip to: 86948 +/* 7956 */ MCD_OPC_Decode, 221, 1, 27, // Opcode: ADR_UXTW_ZZZ_D_3 +/* 7960 */ MCD_OPC_FilterValue, 12, 16, 0, 0, // Skip to: 7981 +/* 7965 */ MCD_OPC_CheckPredicate, 0, 130, 52, 1, // Skip to: 86948 +/* 7970 */ MCD_OPC_CheckField, 22, 1, 1, 123, 52, 1, // Skip to: 86948 +/* 7977 */ MCD_OPC_Decode, 239, 12, 27, // Opcode: FTSSEL_ZZZ_H +/* 7981 */ MCD_OPC_FilterValue, 14, 23, 0, 0, // Skip to: 8009 +/* 7986 */ MCD_OPC_CheckPredicate, 0, 109, 52, 1, // Skip to: 86948 +/* 7991 */ MCD_OPC_CheckField, 22, 1, 1, 102, 52, 1, // Skip to: 86948 +/* 7998 */ MCD_OPC_CheckField, 16, 5, 0, 95, 52, 1, // Skip to: 86948 +/* 8005 */ MCD_OPC_Decode, 184, 9, 38, // Opcode: FEXPA_ZZ_H +/* 8009 */ MCD_OPC_FilterValue, 15, 86, 52, 1, // Skip to: 86948 +/* 8014 */ MCD_OPC_CheckPredicate, 0, 81, 52, 1, // Skip to: 86948 +/* 8019 */ MCD_OPC_CheckField, 22, 1, 0, 74, 52, 1, // Skip to: 86948 +/* 8026 */ MCD_OPC_CheckField, 16, 5, 0, 67, 52, 1, // Skip to: 86948 +/* 8033 */ MCD_OPC_Decode, 255, 19, 38, // Opcode: MOVPRFX_ZZ +/* 8037 */ MCD_OPC_FilterValue, 1, 82, 1, 0, // Skip to: 8380 +/* 8042 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 8045 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8066 +/* 8050 */ MCD_OPC_CheckPredicate, 0, 45, 52, 1, // Skip to: 86948 +/* 8055 */ MCD_OPC_CheckField, 22, 1, 0, 38, 52, 1, // Skip to: 86948 +/* 8062 */ MCD_OPC_Decode, 141, 2, 27, // Opcode: ASR_WIDE_ZZZ_S +/* 8066 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 8087 +/* 8071 */ MCD_OPC_CheckPredicate, 0, 24, 52, 1, // Skip to: 86948 +/* 8076 */ MCD_OPC_CheckField, 22, 1, 0, 17, 52, 1, // Skip to: 86948 +/* 8083 */ MCD_OPC_Decode, 186, 19, 27, // Opcode: LSR_WIDE_ZZZ_S +/* 8087 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 8108 +/* 8092 */ MCD_OPC_CheckPredicate, 0, 3, 52, 1, // Skip to: 86948 +/* 8097 */ MCD_OPC_CheckField, 22, 1, 0, 252, 51, 1, // Skip to: 86948 +/* 8104 */ MCD_OPC_Decode, 162, 19, 27, // Opcode: LSL_WIDE_ZZZ_S +/* 8108 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 8122 +/* 8113 */ MCD_OPC_CheckPredicate, 0, 238, 51, 1, // Skip to: 86948 +/* 8118 */ MCD_OPC_Decode, 151, 2, 60, // Opcode: ASR_ZZI_D +/* 8122 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 8136 +/* 8127 */ MCD_OPC_CheckPredicate, 0, 224, 51, 1, // Skip to: 86948 +/* 8132 */ MCD_OPC_Decode, 196, 19, 60, // Opcode: LSR_ZZI_D +/* 8136 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 8150 +/* 8141 */ MCD_OPC_CheckPredicate, 0, 210, 51, 1, // Skip to: 86948 +/* 8146 */ MCD_OPC_Decode, 172, 19, 61, // Opcode: LSL_ZZI_D +/* 8150 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 8186 +/* 8155 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8158 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8172 +/* 8163 */ MCD_OPC_CheckPredicate, 0, 188, 51, 1, // Skip to: 86948 +/* 8168 */ MCD_OPC_Decode, 210, 1, 27, // Opcode: ADR_LSL_ZZZ_S_0 +/* 8172 */ MCD_OPC_FilterValue, 1, 179, 51, 1, // Skip to: 86948 +/* 8177 */ MCD_OPC_CheckPredicate, 0, 174, 51, 1, // Skip to: 86948 +/* 8182 */ MCD_OPC_Decode, 206, 1, 27, // Opcode: ADR_LSL_ZZZ_D_0 +/* 8186 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 8222 +/* 8191 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8194 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8208 +/* 8199 */ MCD_OPC_CheckPredicate, 0, 152, 51, 1, // Skip to: 86948 +/* 8204 */ MCD_OPC_Decode, 211, 1, 27, // Opcode: ADR_LSL_ZZZ_S_1 +/* 8208 */ MCD_OPC_FilterValue, 1, 143, 51, 1, // Skip to: 86948 +/* 8213 */ MCD_OPC_CheckPredicate, 0, 138, 51, 1, // Skip to: 86948 +/* 8218 */ MCD_OPC_Decode, 207, 1, 27, // Opcode: ADR_LSL_ZZZ_D_1 +/* 8222 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 8258 +/* 8227 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8230 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8244 +/* 8235 */ MCD_OPC_CheckPredicate, 0, 116, 51, 1, // Skip to: 86948 +/* 8240 */ MCD_OPC_Decode, 212, 1, 27, // Opcode: ADR_LSL_ZZZ_S_2 +/* 8244 */ MCD_OPC_FilterValue, 1, 107, 51, 1, // Skip to: 86948 +/* 8249 */ MCD_OPC_CheckPredicate, 0, 102, 51, 1, // Skip to: 86948 +/* 8254 */ MCD_OPC_Decode, 208, 1, 27, // Opcode: ADR_LSL_ZZZ_D_2 +/* 8258 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 8294 +/* 8263 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8266 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8280 +/* 8271 */ MCD_OPC_CheckPredicate, 0, 80, 51, 1, // Skip to: 86948 +/* 8276 */ MCD_OPC_Decode, 213, 1, 27, // Opcode: ADR_LSL_ZZZ_S_3 +/* 8280 */ MCD_OPC_FilterValue, 1, 71, 51, 1, // Skip to: 86948 +/* 8285 */ MCD_OPC_CheckPredicate, 0, 66, 51, 1, // Skip to: 86948 +/* 8290 */ MCD_OPC_Decode, 209, 1, 27, // Opcode: ADR_LSL_ZZZ_D_3 +/* 8294 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 8330 +/* 8299 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8302 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8316 +/* 8307 */ MCD_OPC_CheckPredicate, 0, 44, 51, 1, // Skip to: 86948 +/* 8312 */ MCD_OPC_Decode, 240, 12, 27, // Opcode: FTSSEL_ZZZ_S +/* 8316 */ MCD_OPC_FilterValue, 1, 35, 51, 1, // Skip to: 86948 +/* 8321 */ MCD_OPC_CheckPredicate, 0, 30, 51, 1, // Skip to: 86948 +/* 8326 */ MCD_OPC_Decode, 238, 12, 27, // Opcode: FTSSEL_ZZZ_D +/* 8330 */ MCD_OPC_FilterValue, 14, 21, 51, 1, // Skip to: 86948 +/* 8335 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8338 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8359 +/* 8343 */ MCD_OPC_CheckPredicate, 0, 8, 51, 1, // Skip to: 86948 +/* 8348 */ MCD_OPC_CheckField, 16, 5, 0, 1, 51, 1, // Skip to: 86948 +/* 8355 */ MCD_OPC_Decode, 185, 9, 38, // Opcode: FEXPA_ZZ_S +/* 8359 */ MCD_OPC_FilterValue, 1, 248, 50, 1, // Skip to: 86948 +/* 8364 */ MCD_OPC_CheckPredicate, 0, 243, 50, 1, // Skip to: 86948 +/* 8369 */ MCD_OPC_CheckField, 16, 5, 0, 236, 50, 1, // Skip to: 86948 +/* 8376 */ MCD_OPC_Decode, 183, 9, 38, // Opcode: FEXPA_ZZ_D +/* 8380 */ MCD_OPC_FilterValue, 2, 179, 2, 0, // Skip to: 9076 +/* 8385 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 8388 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 8468 +/* 8393 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 8396 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8432 +/* 8401 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8404 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8418 +/* 8409 */ MCD_OPC_CheckPredicate, 0, 198, 50, 1, // Skip to: 86948 +/* 8414 */ MCD_OPC_Decode, 141, 5, 62, // Opcode: CPY_ZPmV_B +/* 8418 */ MCD_OPC_FilterValue, 1, 189, 50, 1, // Skip to: 86948 +/* 8423 */ MCD_OPC_CheckPredicate, 0, 184, 50, 1, // Skip to: 86948 +/* 8428 */ MCD_OPC_Decode, 143, 5, 63, // Opcode: CPY_ZPmV_H +/* 8432 */ MCD_OPC_FilterValue, 1, 175, 50, 1, // Skip to: 86948 +/* 8437 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8440 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8454 +/* 8445 */ MCD_OPC_CheckPredicate, 0, 162, 50, 1, // Skip to: 86948 +/* 8450 */ MCD_OPC_Decode, 163, 14, 64, // Opcode: LASTA_RPZ_B +/* 8454 */ MCD_OPC_FilterValue, 1, 153, 50, 1, // Skip to: 86948 +/* 8459 */ MCD_OPC_CheckPredicate, 0, 148, 50, 1, // Skip to: 86948 +/* 8464 */ MCD_OPC_Decode, 165, 14, 64, // Opcode: LASTA_RPZ_H +/* 8468 */ MCD_OPC_FilterValue, 1, 45, 0, 0, // Skip to: 8518 +/* 8473 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8476 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8497 +/* 8481 */ MCD_OPC_CheckPredicate, 0, 126, 50, 1, // Skip to: 86948 +/* 8486 */ MCD_OPC_CheckField, 13, 1, 1, 119, 50, 1, // Skip to: 86948 +/* 8493 */ MCD_OPC_Decode, 171, 14, 64, // Opcode: LASTB_RPZ_B +/* 8497 */ MCD_OPC_FilterValue, 1, 110, 50, 1, // Skip to: 86948 +/* 8502 */ MCD_OPC_CheckPredicate, 0, 105, 50, 1, // Skip to: 86948 +/* 8507 */ MCD_OPC_CheckField, 13, 1, 1, 98, 50, 1, // Skip to: 86948 +/* 8514 */ MCD_OPC_Decode, 173, 14, 64, // Opcode: LASTB_RPZ_H +/* 8518 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 8568 +/* 8523 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8526 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8547 +/* 8531 */ MCD_OPC_CheckPredicate, 0, 76, 50, 1, // Skip to: 86948 +/* 8536 */ MCD_OPC_CheckField, 13, 1, 0, 69, 50, 1, // Skip to: 86948 +/* 8543 */ MCD_OPC_Decode, 167, 14, 2, // Opcode: LASTA_VPZ_B +/* 8547 */ MCD_OPC_FilterValue, 1, 60, 50, 1, // Skip to: 86948 +/* 8552 */ MCD_OPC_CheckPredicate, 0, 55, 50, 1, // Skip to: 86948 +/* 8557 */ MCD_OPC_CheckField, 13, 1, 0, 48, 50, 1, // Skip to: 86948 +/* 8564 */ MCD_OPC_Decode, 169, 14, 3, // Opcode: LASTA_VPZ_H +/* 8568 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 8618 +/* 8573 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8576 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8597 +/* 8581 */ MCD_OPC_CheckPredicate, 0, 26, 50, 1, // Skip to: 86948 +/* 8586 */ MCD_OPC_CheckField, 13, 1, 0, 19, 50, 1, // Skip to: 86948 +/* 8593 */ MCD_OPC_Decode, 175, 14, 2, // Opcode: LASTB_VPZ_B +/* 8597 */ MCD_OPC_FilterValue, 1, 10, 50, 1, // Skip to: 86948 +/* 8602 */ MCD_OPC_CheckPredicate, 0, 5, 50, 1, // Skip to: 86948 +/* 8607 */ MCD_OPC_CheckField, 13, 1, 0, 254, 49, 1, // Skip to: 86948 +/* 8614 */ MCD_OPC_Decode, 177, 14, 3, // Opcode: LASTB_VPZ_H +/* 8618 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 8646 +/* 8623 */ MCD_OPC_CheckPredicate, 0, 240, 49, 1, // Skip to: 86948 +/* 8628 */ MCD_OPC_CheckField, 22, 1, 1, 233, 49, 1, // Skip to: 86948 +/* 8635 */ MCD_OPC_CheckField, 13, 1, 0, 226, 49, 1, // Skip to: 86948 +/* 8642 */ MCD_OPC_Decode, 216, 21, 5, // Opcode: REVB_ZPmZ_H +/* 8646 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 8696 +/* 8651 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8654 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8675 +/* 8659 */ MCD_OPC_CheckPredicate, 0, 204, 49, 1, // Skip to: 86948 +/* 8664 */ MCD_OPC_CheckField, 13, 1, 0, 197, 49, 1, // Skip to: 86948 +/* 8671 */ MCD_OPC_Decode, 186, 21, 5, // Opcode: RBIT_ZPmZ_B +/* 8675 */ MCD_OPC_FilterValue, 1, 188, 49, 1, // Skip to: 86948 +/* 8680 */ MCD_OPC_CheckPredicate, 0, 183, 49, 1, // Skip to: 86948 +/* 8685 */ MCD_OPC_CheckField, 13, 1, 0, 176, 49, 1, // Skip to: 86948 +/* 8692 */ MCD_OPC_Decode, 188, 21, 5, // Opcode: RBIT_ZPmZ_H +/* 8696 */ MCD_OPC_FilterValue, 8, 75, 0, 0, // Skip to: 8776 +/* 8701 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 8704 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 8740 +/* 8709 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8712 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8726 +/* 8717 */ MCD_OPC_CheckPredicate, 0, 146, 49, 1, // Skip to: 86948 +/* 8722 */ MCD_OPC_Decode, 141, 3, 0, // Opcode: CLASTA_ZPZ_B +/* 8726 */ MCD_OPC_FilterValue, 1, 137, 49, 1, // Skip to: 86948 +/* 8731 */ MCD_OPC_CheckPredicate, 0, 132, 49, 1, // Skip to: 86948 +/* 8736 */ MCD_OPC_Decode, 143, 3, 0, // Opcode: CLASTA_ZPZ_H +/* 8740 */ MCD_OPC_FilterValue, 1, 123, 49, 1, // Skip to: 86948 +/* 8745 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8748 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 8762 +/* 8753 */ MCD_OPC_CheckPredicate, 0, 110, 49, 1, // Skip to: 86948 +/* 8758 */ MCD_OPC_Decode, 137, 5, 65, // Opcode: CPY_ZPmR_B +/* 8762 */ MCD_OPC_FilterValue, 1, 101, 49, 1, // Skip to: 86948 +/* 8767 */ MCD_OPC_CheckPredicate, 0, 96, 49, 1, // Skip to: 86948 +/* 8772 */ MCD_OPC_Decode, 139, 5, 65, // Opcode: CPY_ZPmR_H +/* 8776 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 8826 +/* 8781 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8784 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8805 +/* 8789 */ MCD_OPC_CheckPredicate, 0, 74, 49, 1, // Skip to: 86948 +/* 8794 */ MCD_OPC_CheckField, 13, 1, 0, 67, 49, 1, // Skip to: 86948 +/* 8801 */ MCD_OPC_Decode, 153, 3, 0, // Opcode: CLASTB_ZPZ_B +/* 8805 */ MCD_OPC_FilterValue, 1, 58, 49, 1, // Skip to: 86948 +/* 8810 */ MCD_OPC_CheckPredicate, 0, 53, 49, 1, // Skip to: 86948 +/* 8815 */ MCD_OPC_CheckField, 13, 1, 0, 46, 49, 1, // Skip to: 86948 +/* 8822 */ MCD_OPC_Decode, 155, 3, 0, // Opcode: CLASTB_ZPZ_H +/* 8826 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 8876 +/* 8831 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8834 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8855 +/* 8839 */ MCD_OPC_CheckPredicate, 0, 24, 49, 1, // Skip to: 86948 +/* 8844 */ MCD_OPC_CheckField, 13, 1, 0, 17, 49, 1, // Skip to: 86948 +/* 8851 */ MCD_OPC_Decode, 137, 3, 66, // Opcode: CLASTA_VPZ_B +/* 8855 */ MCD_OPC_FilterValue, 1, 8, 49, 1, // Skip to: 86948 +/* 8860 */ MCD_OPC_CheckPredicate, 0, 3, 49, 1, // Skip to: 86948 +/* 8865 */ MCD_OPC_CheckField, 13, 1, 0, 252, 48, 1, // Skip to: 86948 +/* 8872 */ MCD_OPC_Decode, 139, 3, 67, // Opcode: CLASTA_VPZ_H +/* 8876 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 8926 +/* 8881 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8884 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8905 +/* 8889 */ MCD_OPC_CheckPredicate, 0, 230, 48, 1, // Skip to: 86948 +/* 8894 */ MCD_OPC_CheckField, 13, 1, 0, 223, 48, 1, // Skip to: 86948 +/* 8901 */ MCD_OPC_Decode, 149, 3, 66, // Opcode: CLASTB_VPZ_B +/* 8905 */ MCD_OPC_FilterValue, 1, 214, 48, 1, // Skip to: 86948 +/* 8910 */ MCD_OPC_CheckPredicate, 0, 209, 48, 1, // Skip to: 86948 +/* 8915 */ MCD_OPC_CheckField, 13, 1, 0, 202, 48, 1, // Skip to: 86948 +/* 8922 */ MCD_OPC_Decode, 151, 3, 67, // Opcode: CLASTB_VPZ_H +/* 8926 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 8976 +/* 8931 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8934 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 8955 +/* 8939 */ MCD_OPC_CheckPredicate, 0, 180, 48, 1, // Skip to: 86948 +/* 8944 */ MCD_OPC_CheckField, 13, 1, 0, 173, 48, 1, // Skip to: 86948 +/* 8951 */ MCD_OPC_Decode, 149, 24, 0, // Opcode: SPLICE_ZPZ_B +/* 8955 */ MCD_OPC_FilterValue, 1, 164, 48, 1, // Skip to: 86948 +/* 8960 */ MCD_OPC_CheckPredicate, 0, 159, 48, 1, // Skip to: 86948 +/* 8965 */ MCD_OPC_CheckField, 13, 1, 0, 152, 48, 1, // Skip to: 86948 +/* 8972 */ MCD_OPC_Decode, 151, 24, 0, // Opcode: SPLICE_ZPZ_H +/* 8976 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 9026 +/* 8981 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 8984 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9005 +/* 8989 */ MCD_OPC_CheckPredicate, 0, 130, 48, 1, // Skip to: 86948 +/* 8994 */ MCD_OPC_CheckField, 13, 1, 1, 123, 48, 1, // Skip to: 86948 +/* 9001 */ MCD_OPC_Decode, 133, 3, 68, // Opcode: CLASTA_RPZ_B +/* 9005 */ MCD_OPC_FilterValue, 1, 114, 48, 1, // Skip to: 86948 +/* 9010 */ MCD_OPC_CheckPredicate, 0, 109, 48, 1, // Skip to: 86948 +/* 9015 */ MCD_OPC_CheckField, 13, 1, 1, 102, 48, 1, // Skip to: 86948 +/* 9022 */ MCD_OPC_Decode, 135, 3, 68, // Opcode: CLASTA_RPZ_H +/* 9026 */ MCD_OPC_FilterValue, 17, 93, 48, 1, // Skip to: 86948 +/* 9031 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9034 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9055 +/* 9039 */ MCD_OPC_CheckPredicate, 0, 80, 48, 1, // Skip to: 86948 +/* 9044 */ MCD_OPC_CheckField, 13, 1, 1, 73, 48, 1, // Skip to: 86948 +/* 9051 */ MCD_OPC_Decode, 145, 3, 68, // Opcode: CLASTB_RPZ_B +/* 9055 */ MCD_OPC_FilterValue, 1, 64, 48, 1, // Skip to: 86948 +/* 9060 */ MCD_OPC_CheckPredicate, 0, 59, 48, 1, // Skip to: 86948 +/* 9065 */ MCD_OPC_CheckField, 13, 1, 1, 52, 48, 1, // Skip to: 86948 +/* 9072 */ MCD_OPC_Decode, 147, 3, 68, // Opcode: CLASTB_RPZ_H +/* 9076 */ MCD_OPC_FilterValue, 3, 43, 48, 1, // Skip to: 86948 +/* 9081 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 9084 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 9164 +/* 9089 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 9092 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9128 +/* 9097 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9114 +/* 9105 */ MCD_OPC_CheckPredicate, 0, 14, 48, 1, // Skip to: 86948 +/* 9110 */ MCD_OPC_Decode, 144, 5, 69, // Opcode: CPY_ZPmV_S +/* 9114 */ MCD_OPC_FilterValue, 1, 5, 48, 1, // Skip to: 86948 +/* 9119 */ MCD_OPC_CheckPredicate, 0, 0, 48, 1, // Skip to: 86948 +/* 9124 */ MCD_OPC_Decode, 142, 5, 70, // Opcode: CPY_ZPmV_D +/* 9128 */ MCD_OPC_FilterValue, 1, 247, 47, 1, // Skip to: 86948 +/* 9133 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9136 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9150 +/* 9141 */ MCD_OPC_CheckPredicate, 0, 234, 47, 1, // Skip to: 86948 +/* 9146 */ MCD_OPC_Decode, 166, 14, 64, // Opcode: LASTA_RPZ_S +/* 9150 */ MCD_OPC_FilterValue, 1, 225, 47, 1, // Skip to: 86948 +/* 9155 */ MCD_OPC_CheckPredicate, 0, 220, 47, 1, // Skip to: 86948 +/* 9160 */ MCD_OPC_Decode, 164, 14, 71, // Opcode: LASTA_RPZ_D +/* 9164 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 9244 +/* 9169 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 9172 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9208 +/* 9177 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9180 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9194 +/* 9185 */ MCD_OPC_CheckPredicate, 0, 190, 47, 1, // Skip to: 86948 +/* 9190 */ MCD_OPC_Decode, 132, 5, 4, // Opcode: COMPACT_ZPZ_S +/* 9194 */ MCD_OPC_FilterValue, 1, 181, 47, 1, // Skip to: 86948 +/* 9199 */ MCD_OPC_CheckPredicate, 0, 176, 47, 1, // Skip to: 86948 +/* 9204 */ MCD_OPC_Decode, 131, 5, 4, // Opcode: COMPACT_ZPZ_D +/* 9208 */ MCD_OPC_FilterValue, 1, 167, 47, 1, // Skip to: 86948 +/* 9213 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9216 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9230 +/* 9221 */ MCD_OPC_CheckPredicate, 0, 154, 47, 1, // Skip to: 86948 +/* 9226 */ MCD_OPC_Decode, 174, 14, 64, // Opcode: LASTB_RPZ_S +/* 9230 */ MCD_OPC_FilterValue, 1, 145, 47, 1, // Skip to: 86948 +/* 9235 */ MCD_OPC_CheckPredicate, 0, 140, 47, 1, // Skip to: 86948 +/* 9240 */ MCD_OPC_Decode, 172, 14, 71, // Opcode: LASTB_RPZ_D +/* 9244 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 9294 +/* 9249 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9252 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9273 +/* 9257 */ MCD_OPC_CheckPredicate, 0, 118, 47, 1, // Skip to: 86948 +/* 9262 */ MCD_OPC_CheckField, 13, 1, 0, 111, 47, 1, // Skip to: 86948 +/* 9269 */ MCD_OPC_Decode, 170, 14, 14, // Opcode: LASTA_VPZ_S +/* 9273 */ MCD_OPC_FilterValue, 1, 102, 47, 1, // Skip to: 86948 +/* 9278 */ MCD_OPC_CheckPredicate, 0, 97, 47, 1, // Skip to: 86948 +/* 9283 */ MCD_OPC_CheckField, 13, 1, 0, 90, 47, 1, // Skip to: 86948 +/* 9290 */ MCD_OPC_Decode, 168, 14, 1, // Opcode: LASTA_VPZ_D +/* 9294 */ MCD_OPC_FilterValue, 3, 45, 0, 0, // Skip to: 9344 +/* 9299 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9302 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9323 +/* 9307 */ MCD_OPC_CheckPredicate, 0, 68, 47, 1, // Skip to: 86948 +/* 9312 */ MCD_OPC_CheckField, 13, 1, 0, 61, 47, 1, // Skip to: 86948 +/* 9319 */ MCD_OPC_Decode, 178, 14, 14, // Opcode: LASTB_VPZ_S +/* 9323 */ MCD_OPC_FilterValue, 1, 52, 47, 1, // Skip to: 86948 +/* 9328 */ MCD_OPC_CheckPredicate, 0, 47, 47, 1, // Skip to: 86948 +/* 9333 */ MCD_OPC_CheckField, 13, 1, 0, 40, 47, 1, // Skip to: 86948 +/* 9340 */ MCD_OPC_Decode, 176, 14, 1, // Opcode: LASTB_VPZ_D +/* 9344 */ MCD_OPC_FilterValue, 4, 45, 0, 0, // Skip to: 9394 +/* 9349 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9352 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9373 +/* 9357 */ MCD_OPC_CheckPredicate, 0, 18, 47, 1, // Skip to: 86948 +/* 9362 */ MCD_OPC_CheckField, 13, 1, 0, 11, 47, 1, // Skip to: 86948 +/* 9369 */ MCD_OPC_Decode, 217, 21, 5, // Opcode: REVB_ZPmZ_S +/* 9373 */ MCD_OPC_FilterValue, 1, 2, 47, 1, // Skip to: 86948 +/* 9378 */ MCD_OPC_CheckPredicate, 0, 253, 46, 1, // Skip to: 86948 +/* 9383 */ MCD_OPC_CheckField, 13, 1, 0, 246, 46, 1, // Skip to: 86948 +/* 9390 */ MCD_OPC_Decode, 215, 21, 5, // Opcode: REVB_ZPmZ_D +/* 9394 */ MCD_OPC_FilterValue, 5, 45, 0, 0, // Skip to: 9444 +/* 9399 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9402 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9423 +/* 9407 */ MCD_OPC_CheckPredicate, 0, 224, 46, 1, // Skip to: 86948 +/* 9412 */ MCD_OPC_CheckField, 13, 1, 0, 217, 46, 1, // Skip to: 86948 +/* 9419 */ MCD_OPC_Decode, 219, 21, 5, // Opcode: REVH_ZPmZ_S +/* 9423 */ MCD_OPC_FilterValue, 1, 208, 46, 1, // Skip to: 86948 +/* 9428 */ MCD_OPC_CheckPredicate, 0, 203, 46, 1, // Skip to: 86948 +/* 9433 */ MCD_OPC_CheckField, 13, 1, 0, 196, 46, 1, // Skip to: 86948 +/* 9440 */ MCD_OPC_Decode, 218, 21, 5, // Opcode: REVH_ZPmZ_D +/* 9444 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 9472 +/* 9449 */ MCD_OPC_CheckPredicate, 0, 182, 46, 1, // Skip to: 86948 +/* 9454 */ MCD_OPC_CheckField, 22, 1, 1, 175, 46, 1, // Skip to: 86948 +/* 9461 */ MCD_OPC_CheckField, 13, 1, 0, 168, 46, 1, // Skip to: 86948 +/* 9468 */ MCD_OPC_Decode, 220, 21, 5, // Opcode: REVW_ZPmZ_D +/* 9472 */ MCD_OPC_FilterValue, 7, 45, 0, 0, // Skip to: 9522 +/* 9477 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9480 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9501 +/* 9485 */ MCD_OPC_CheckPredicate, 0, 146, 46, 1, // Skip to: 86948 +/* 9490 */ MCD_OPC_CheckField, 13, 1, 0, 139, 46, 1, // Skip to: 86948 +/* 9497 */ MCD_OPC_Decode, 189, 21, 5, // Opcode: RBIT_ZPmZ_S +/* 9501 */ MCD_OPC_FilterValue, 1, 130, 46, 1, // Skip to: 86948 +/* 9506 */ MCD_OPC_CheckPredicate, 0, 125, 46, 1, // Skip to: 86948 +/* 9511 */ MCD_OPC_CheckField, 13, 1, 0, 118, 46, 1, // Skip to: 86948 +/* 9518 */ MCD_OPC_Decode, 187, 21, 5, // Opcode: RBIT_ZPmZ_D +/* 9522 */ MCD_OPC_FilterValue, 8, 75, 0, 0, // Skip to: 9602 +/* 9527 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 9530 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 9566 +/* 9535 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9538 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9552 +/* 9543 */ MCD_OPC_CheckPredicate, 0, 88, 46, 1, // Skip to: 86948 +/* 9548 */ MCD_OPC_Decode, 144, 3, 0, // Opcode: CLASTA_ZPZ_S +/* 9552 */ MCD_OPC_FilterValue, 1, 79, 46, 1, // Skip to: 86948 +/* 9557 */ MCD_OPC_CheckPredicate, 0, 74, 46, 1, // Skip to: 86948 +/* 9562 */ MCD_OPC_Decode, 142, 3, 0, // Opcode: CLASTA_ZPZ_D +/* 9566 */ MCD_OPC_FilterValue, 1, 65, 46, 1, // Skip to: 86948 +/* 9571 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9574 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9588 +/* 9579 */ MCD_OPC_CheckPredicate, 0, 52, 46, 1, // Skip to: 86948 +/* 9584 */ MCD_OPC_Decode, 140, 5, 65, // Opcode: CPY_ZPmR_S +/* 9588 */ MCD_OPC_FilterValue, 1, 43, 46, 1, // Skip to: 86948 +/* 9593 */ MCD_OPC_CheckPredicate, 0, 38, 46, 1, // Skip to: 86948 +/* 9598 */ MCD_OPC_Decode, 138, 5, 72, // Opcode: CPY_ZPmR_D +/* 9602 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 9652 +/* 9607 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9610 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9631 +/* 9615 */ MCD_OPC_CheckPredicate, 0, 16, 46, 1, // Skip to: 86948 +/* 9620 */ MCD_OPC_CheckField, 13, 1, 0, 9, 46, 1, // Skip to: 86948 +/* 9627 */ MCD_OPC_Decode, 156, 3, 0, // Opcode: CLASTB_ZPZ_S +/* 9631 */ MCD_OPC_FilterValue, 1, 0, 46, 1, // Skip to: 86948 +/* 9636 */ MCD_OPC_CheckPredicate, 0, 251, 45, 1, // Skip to: 86948 +/* 9641 */ MCD_OPC_CheckField, 13, 1, 0, 244, 45, 1, // Skip to: 86948 +/* 9648 */ MCD_OPC_Decode, 154, 3, 0, // Opcode: CLASTB_ZPZ_D +/* 9652 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 9702 +/* 9657 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9660 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9681 +/* 9665 */ MCD_OPC_CheckPredicate, 0, 222, 45, 1, // Skip to: 86948 +/* 9670 */ MCD_OPC_CheckField, 13, 1, 0, 215, 45, 1, // Skip to: 86948 +/* 9677 */ MCD_OPC_Decode, 140, 3, 73, // Opcode: CLASTA_VPZ_S +/* 9681 */ MCD_OPC_FilterValue, 1, 206, 45, 1, // Skip to: 86948 +/* 9686 */ MCD_OPC_CheckPredicate, 0, 201, 45, 1, // Skip to: 86948 +/* 9691 */ MCD_OPC_CheckField, 13, 1, 0, 194, 45, 1, // Skip to: 86948 +/* 9698 */ MCD_OPC_Decode, 138, 3, 74, // Opcode: CLASTA_VPZ_D +/* 9702 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 9752 +/* 9707 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9710 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9731 +/* 9715 */ MCD_OPC_CheckPredicate, 0, 172, 45, 1, // Skip to: 86948 +/* 9720 */ MCD_OPC_CheckField, 13, 1, 0, 165, 45, 1, // Skip to: 86948 +/* 9727 */ MCD_OPC_Decode, 152, 3, 73, // Opcode: CLASTB_VPZ_S +/* 9731 */ MCD_OPC_FilterValue, 1, 156, 45, 1, // Skip to: 86948 +/* 9736 */ MCD_OPC_CheckPredicate, 0, 151, 45, 1, // Skip to: 86948 +/* 9741 */ MCD_OPC_CheckField, 13, 1, 0, 144, 45, 1, // Skip to: 86948 +/* 9748 */ MCD_OPC_Decode, 150, 3, 74, // Opcode: CLASTB_VPZ_D +/* 9752 */ MCD_OPC_FilterValue, 12, 45, 0, 0, // Skip to: 9802 +/* 9757 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9760 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9781 +/* 9765 */ MCD_OPC_CheckPredicate, 0, 122, 45, 1, // Skip to: 86948 +/* 9770 */ MCD_OPC_CheckField, 13, 1, 0, 115, 45, 1, // Skip to: 86948 +/* 9777 */ MCD_OPC_Decode, 152, 24, 0, // Opcode: SPLICE_ZPZ_S +/* 9781 */ MCD_OPC_FilterValue, 1, 106, 45, 1, // Skip to: 86948 +/* 9786 */ MCD_OPC_CheckPredicate, 0, 101, 45, 1, // Skip to: 86948 +/* 9791 */ MCD_OPC_CheckField, 13, 1, 0, 94, 45, 1, // Skip to: 86948 +/* 9798 */ MCD_OPC_Decode, 150, 24, 0, // Opcode: SPLICE_ZPZ_D +/* 9802 */ MCD_OPC_FilterValue, 16, 45, 0, 0, // Skip to: 9852 +/* 9807 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9810 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9831 +/* 9815 */ MCD_OPC_CheckPredicate, 0, 72, 45, 1, // Skip to: 86948 +/* 9820 */ MCD_OPC_CheckField, 13, 1, 1, 65, 45, 1, // Skip to: 86948 +/* 9827 */ MCD_OPC_Decode, 136, 3, 68, // Opcode: CLASTA_RPZ_S +/* 9831 */ MCD_OPC_FilterValue, 1, 56, 45, 1, // Skip to: 86948 +/* 9836 */ MCD_OPC_CheckPredicate, 0, 51, 45, 1, // Skip to: 86948 +/* 9841 */ MCD_OPC_CheckField, 13, 1, 1, 44, 45, 1, // Skip to: 86948 +/* 9848 */ MCD_OPC_Decode, 134, 3, 75, // Opcode: CLASTA_RPZ_D +/* 9852 */ MCD_OPC_FilterValue, 17, 35, 45, 1, // Skip to: 86948 +/* 9857 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 9860 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 9881 +/* 9865 */ MCD_OPC_CheckPredicate, 0, 22, 45, 1, // Skip to: 86948 +/* 9870 */ MCD_OPC_CheckField, 13, 1, 1, 15, 45, 1, // Skip to: 86948 +/* 9877 */ MCD_OPC_Decode, 148, 3, 68, // Opcode: CLASTB_RPZ_S +/* 9881 */ MCD_OPC_FilterValue, 1, 6, 45, 1, // Skip to: 86948 +/* 9886 */ MCD_OPC_CheckPredicate, 0, 1, 45, 1, // Skip to: 86948 +/* 9891 */ MCD_OPC_CheckField, 13, 1, 1, 250, 44, 1, // Skip to: 86948 +/* 9898 */ MCD_OPC_Decode, 146, 3, 75, // Opcode: CLASTB_RPZ_D +/* 9902 */ MCD_OPC_FilterValue, 3, 241, 44, 1, // Skip to: 86948 +/* 9907 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 9910 */ MCD_OPC_FilterValue, 0, 204, 0, 0, // Skip to: 10119 +/* 9915 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 9918 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 9954 +/* 9923 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 9926 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9940 +/* 9931 */ MCD_OPC_CheckPredicate, 0, 212, 44, 1, // Skip to: 86948 +/* 9936 */ MCD_OPC_Decode, 245, 4, 76, // Opcode: CNTB_XPiI +/* 9940 */ MCD_OPC_FilterValue, 1, 203, 44, 1, // Skip to: 86948 +/* 9945 */ MCD_OPC_CheckPredicate, 0, 198, 44, 1, // Skip to: 86948 +/* 9950 */ MCD_OPC_Decode, 244, 13, 77, // Opcode: INCB_XPiI +/* 9954 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 9975 +/* 9959 */ MCD_OPC_CheckPredicate, 0, 184, 44, 1, // Skip to: 86948 +/* 9964 */ MCD_OPC_CheckField, 20, 1, 1, 177, 44, 1, // Skip to: 86948 +/* 9971 */ MCD_OPC_Decode, 177, 5, 77, // Opcode: DECB_XPiI +/* 9975 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10011 +/* 9980 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 9983 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 9997 +/* 9988 */ MCD_OPC_CheckPredicate, 0, 155, 44, 1, // Skip to: 86948 +/* 9993 */ MCD_OPC_Decode, 254, 24, 77, // Opcode: SQINCB_XPiWdI +/* 9997 */ MCD_OPC_FilterValue, 1, 146, 44, 1, // Skip to: 86948 +/* 10002 */ MCD_OPC_CheckPredicate, 0, 141, 44, 1, // Skip to: 86948 +/* 10007 */ MCD_OPC_Decode, 253, 24, 77, // Opcode: SQINCB_XPiI +/* 10011 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10047 +/* 10016 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10019 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10033 +/* 10024 */ MCD_OPC_CheckPredicate, 0, 119, 44, 1, // Skip to: 86948 +/* 10029 */ MCD_OPC_Decode, 244, 32, 78, // Opcode: UQINCB_WPiI +/* 10033 */ MCD_OPC_FilterValue, 1, 110, 44, 1, // Skip to: 86948 +/* 10038 */ MCD_OPC_CheckPredicate, 0, 105, 44, 1, // Skip to: 86948 +/* 10043 */ MCD_OPC_Decode, 245, 32, 77, // Opcode: UQINCB_XPiI +/* 10047 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10083 +/* 10052 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10055 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10069 +/* 10060 */ MCD_OPC_CheckPredicate, 0, 83, 44, 1, // Skip to: 86948 +/* 10065 */ MCD_OPC_Decode, 184, 24, 77, // Opcode: SQDECB_XPiWdI +/* 10069 */ MCD_OPC_FilterValue, 1, 74, 44, 1, // Skip to: 86948 +/* 10074 */ MCD_OPC_CheckPredicate, 0, 69, 44, 1, // Skip to: 86948 +/* 10079 */ MCD_OPC_Decode, 183, 24, 77, // Opcode: SQDECB_XPiI +/* 10083 */ MCD_OPC_FilterValue, 15, 60, 44, 1, // Skip to: 86948 +/* 10088 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10091 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10105 +/* 10096 */ MCD_OPC_CheckPredicate, 0, 47, 44, 1, // Skip to: 86948 +/* 10101 */ MCD_OPC_Decode, 222, 32, 78, // Opcode: UQDECB_WPiI +/* 10105 */ MCD_OPC_FilterValue, 1, 38, 44, 1, // Skip to: 86948 +/* 10110 */ MCD_OPC_CheckPredicate, 0, 33, 44, 1, // Skip to: 86948 +/* 10115 */ MCD_OPC_Decode, 223, 32, 77, // Opcode: UQDECB_XPiI +/* 10119 */ MCD_OPC_FilterValue, 1, 62, 1, 0, // Skip to: 10442 +/* 10124 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 10127 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10163 +/* 10132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10135 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10149 +/* 10140 */ MCD_OPC_CheckPredicate, 0, 3, 44, 1, // Skip to: 86948 +/* 10145 */ MCD_OPC_Decode, 132, 25, 79, // Opcode: SQINCH_ZPiI +/* 10149 */ MCD_OPC_FilterValue, 1, 250, 43, 1, // Skip to: 86948 +/* 10154 */ MCD_OPC_CheckPredicate, 0, 245, 43, 1, // Skip to: 86948 +/* 10159 */ MCD_OPC_Decode, 248, 13, 79, // Opcode: INCH_ZPiI +/* 10163 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10199 +/* 10168 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10185 +/* 10176 */ MCD_OPC_CheckPredicate, 0, 223, 43, 1, // Skip to: 86948 +/* 10181 */ MCD_OPC_Decode, 251, 32, 79, // Opcode: UQINCH_ZPiI +/* 10185 */ MCD_OPC_FilterValue, 1, 214, 43, 1, // Skip to: 86948 +/* 10190 */ MCD_OPC_CheckPredicate, 0, 209, 43, 1, // Skip to: 86948 +/* 10195 */ MCD_OPC_Decode, 181, 5, 79, // Opcode: DECH_ZPiI +/* 10199 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10220 +/* 10204 */ MCD_OPC_CheckPredicate, 0, 195, 43, 1, // Skip to: 86948 +/* 10209 */ MCD_OPC_CheckField, 20, 1, 0, 188, 43, 1, // Skip to: 86948 +/* 10216 */ MCD_OPC_Decode, 190, 24, 79, // Opcode: SQDECH_ZPiI +/* 10220 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10241 +/* 10225 */ MCD_OPC_CheckPredicate, 0, 174, 43, 1, // Skip to: 86948 +/* 10230 */ MCD_OPC_CheckField, 20, 1, 0, 167, 43, 1, // Skip to: 86948 +/* 10237 */ MCD_OPC_Decode, 229, 32, 79, // Opcode: UQDECH_ZPiI +/* 10241 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10277 +/* 10246 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10249 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10263 +/* 10254 */ MCD_OPC_CheckPredicate, 0, 145, 43, 1, // Skip to: 86948 +/* 10259 */ MCD_OPC_Decode, 247, 4, 76, // Opcode: CNTH_XPiI +/* 10263 */ MCD_OPC_FilterValue, 1, 136, 43, 1, // Skip to: 86948 +/* 10268 */ MCD_OPC_CheckPredicate, 0, 131, 43, 1, // Skip to: 86948 +/* 10273 */ MCD_OPC_Decode, 247, 13, 77, // Opcode: INCH_XPiI +/* 10277 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10298 +/* 10282 */ MCD_OPC_CheckPredicate, 0, 117, 43, 1, // Skip to: 86948 +/* 10287 */ MCD_OPC_CheckField, 20, 1, 1, 110, 43, 1, // Skip to: 86948 +/* 10294 */ MCD_OPC_Decode, 180, 5, 77, // Opcode: DECH_XPiI +/* 10298 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10334 +/* 10303 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10306 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10320 +/* 10311 */ MCD_OPC_CheckPredicate, 0, 88, 43, 1, // Skip to: 86948 +/* 10316 */ MCD_OPC_Decode, 131, 25, 77, // Opcode: SQINCH_XPiWdI +/* 10320 */ MCD_OPC_FilterValue, 1, 79, 43, 1, // Skip to: 86948 +/* 10325 */ MCD_OPC_CheckPredicate, 0, 74, 43, 1, // Skip to: 86948 +/* 10330 */ MCD_OPC_Decode, 130, 25, 77, // Opcode: SQINCH_XPiI +/* 10334 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10370 +/* 10339 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10342 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10356 +/* 10347 */ MCD_OPC_CheckPredicate, 0, 52, 43, 1, // Skip to: 86948 +/* 10352 */ MCD_OPC_Decode, 249, 32, 78, // Opcode: UQINCH_WPiI +/* 10356 */ MCD_OPC_FilterValue, 1, 43, 43, 1, // Skip to: 86948 +/* 10361 */ MCD_OPC_CheckPredicate, 0, 38, 43, 1, // Skip to: 86948 +/* 10366 */ MCD_OPC_Decode, 250, 32, 77, // Opcode: UQINCH_XPiI +/* 10370 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10406 +/* 10375 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10378 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10392 +/* 10383 */ MCD_OPC_CheckPredicate, 0, 16, 43, 1, // Skip to: 86948 +/* 10388 */ MCD_OPC_Decode, 189, 24, 77, // Opcode: SQDECH_XPiWdI +/* 10392 */ MCD_OPC_FilterValue, 1, 7, 43, 1, // Skip to: 86948 +/* 10397 */ MCD_OPC_CheckPredicate, 0, 2, 43, 1, // Skip to: 86948 +/* 10402 */ MCD_OPC_Decode, 188, 24, 77, // Opcode: SQDECH_XPiI +/* 10406 */ MCD_OPC_FilterValue, 15, 249, 42, 1, // Skip to: 86948 +/* 10411 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10414 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10428 +/* 10419 */ MCD_OPC_CheckPredicate, 0, 236, 42, 1, // Skip to: 86948 +/* 10424 */ MCD_OPC_Decode, 227, 32, 78, // Opcode: UQDECH_WPiI +/* 10428 */ MCD_OPC_FilterValue, 1, 227, 42, 1, // Skip to: 86948 +/* 10433 */ MCD_OPC_CheckPredicate, 0, 222, 42, 1, // Skip to: 86948 +/* 10438 */ MCD_OPC_Decode, 228, 32, 77, // Opcode: UQDECH_XPiI +/* 10442 */ MCD_OPC_FilterValue, 2, 62, 1, 0, // Skip to: 10765 +/* 10447 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 10450 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10486 +/* 10455 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10458 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10472 +/* 10463 */ MCD_OPC_CheckPredicate, 0, 192, 42, 1, // Skip to: 86948 +/* 10468 */ MCD_OPC_Decode, 146, 25, 79, // Opcode: SQINCW_ZPiI +/* 10472 */ MCD_OPC_FilterValue, 1, 183, 42, 1, // Skip to: 86948 +/* 10477 */ MCD_OPC_CheckPredicate, 0, 178, 42, 1, // Skip to: 86948 +/* 10482 */ MCD_OPC_Decode, 129, 14, 79, // Opcode: INCW_ZPiI +/* 10486 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10522 +/* 10491 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10494 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10508 +/* 10499 */ MCD_OPC_CheckPredicate, 0, 156, 42, 1, // Skip to: 86948 +/* 10504 */ MCD_OPC_Decode, 137, 33, 79, // Opcode: UQINCW_ZPiI +/* 10508 */ MCD_OPC_FilterValue, 1, 147, 42, 1, // Skip to: 86948 +/* 10513 */ MCD_OPC_CheckPredicate, 0, 142, 42, 1, // Skip to: 86948 +/* 10518 */ MCD_OPC_Decode, 190, 5, 79, // Opcode: DECW_ZPiI +/* 10522 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10543 +/* 10527 */ MCD_OPC_CheckPredicate, 0, 128, 42, 1, // Skip to: 86948 +/* 10532 */ MCD_OPC_CheckField, 20, 1, 0, 121, 42, 1, // Skip to: 86948 +/* 10539 */ MCD_OPC_Decode, 204, 24, 79, // Opcode: SQDECW_ZPiI +/* 10543 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10564 +/* 10548 */ MCD_OPC_CheckPredicate, 0, 107, 42, 1, // Skip to: 86948 +/* 10553 */ MCD_OPC_CheckField, 20, 1, 0, 100, 42, 1, // Skip to: 86948 +/* 10560 */ MCD_OPC_Decode, 243, 32, 79, // Opcode: UQDECW_ZPiI +/* 10564 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10600 +/* 10569 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10572 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10586 +/* 10577 */ MCD_OPC_CheckPredicate, 0, 78, 42, 1, // Skip to: 86948 +/* 10582 */ MCD_OPC_Decode, 252, 4, 76, // Opcode: CNTW_XPiI +/* 10586 */ MCD_OPC_FilterValue, 1, 69, 42, 1, // Skip to: 86948 +/* 10591 */ MCD_OPC_CheckPredicate, 0, 64, 42, 1, // Skip to: 86948 +/* 10596 */ MCD_OPC_Decode, 128, 14, 77, // Opcode: INCW_XPiI +/* 10600 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10621 +/* 10605 */ MCD_OPC_CheckPredicate, 0, 50, 42, 1, // Skip to: 86948 +/* 10610 */ MCD_OPC_CheckField, 20, 1, 1, 43, 42, 1, // Skip to: 86948 +/* 10617 */ MCD_OPC_Decode, 189, 5, 77, // Opcode: DECW_XPiI +/* 10621 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10657 +/* 10626 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10629 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10643 +/* 10634 */ MCD_OPC_CheckPredicate, 0, 21, 42, 1, // Skip to: 86948 +/* 10639 */ MCD_OPC_Decode, 145, 25, 77, // Opcode: SQINCW_XPiWdI +/* 10643 */ MCD_OPC_FilterValue, 1, 12, 42, 1, // Skip to: 86948 +/* 10648 */ MCD_OPC_CheckPredicate, 0, 7, 42, 1, // Skip to: 86948 +/* 10653 */ MCD_OPC_Decode, 144, 25, 77, // Opcode: SQINCW_XPiI +/* 10657 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 10693 +/* 10662 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10665 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10679 +/* 10670 */ MCD_OPC_CheckPredicate, 0, 241, 41, 1, // Skip to: 86948 +/* 10675 */ MCD_OPC_Decode, 135, 33, 78, // Opcode: UQINCW_WPiI +/* 10679 */ MCD_OPC_FilterValue, 1, 232, 41, 1, // Skip to: 86948 +/* 10684 */ MCD_OPC_CheckPredicate, 0, 227, 41, 1, // Skip to: 86948 +/* 10689 */ MCD_OPC_Decode, 136, 33, 77, // Opcode: UQINCW_XPiI +/* 10693 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 10729 +/* 10698 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10701 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10715 +/* 10706 */ MCD_OPC_CheckPredicate, 0, 205, 41, 1, // Skip to: 86948 +/* 10711 */ MCD_OPC_Decode, 203, 24, 77, // Opcode: SQDECW_XPiWdI +/* 10715 */ MCD_OPC_FilterValue, 1, 196, 41, 1, // Skip to: 86948 +/* 10720 */ MCD_OPC_CheckPredicate, 0, 191, 41, 1, // Skip to: 86948 +/* 10725 */ MCD_OPC_Decode, 202, 24, 77, // Opcode: SQDECW_XPiI +/* 10729 */ MCD_OPC_FilterValue, 15, 182, 41, 1, // Skip to: 86948 +/* 10734 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10737 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10751 +/* 10742 */ MCD_OPC_CheckPredicate, 0, 169, 41, 1, // Skip to: 86948 +/* 10747 */ MCD_OPC_Decode, 241, 32, 78, // Opcode: UQDECW_WPiI +/* 10751 */ MCD_OPC_FilterValue, 1, 160, 41, 1, // Skip to: 86948 +/* 10756 */ MCD_OPC_CheckPredicate, 0, 155, 41, 1, // Skip to: 86948 +/* 10761 */ MCD_OPC_Decode, 242, 32, 77, // Opcode: UQDECW_XPiI +/* 10765 */ MCD_OPC_FilterValue, 3, 62, 1, 0, // Skip to: 11088 +/* 10770 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 10773 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 10809 +/* 10778 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10781 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10795 +/* 10786 */ MCD_OPC_CheckPredicate, 0, 125, 41, 1, // Skip to: 86948 +/* 10791 */ MCD_OPC_Decode, 129, 25, 79, // Opcode: SQINCD_ZPiI +/* 10795 */ MCD_OPC_FilterValue, 1, 116, 41, 1, // Skip to: 86948 +/* 10800 */ MCD_OPC_CheckPredicate, 0, 111, 41, 1, // Skip to: 86948 +/* 10805 */ MCD_OPC_Decode, 246, 13, 79, // Opcode: INCD_ZPiI +/* 10809 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 10845 +/* 10814 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10817 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10831 +/* 10822 */ MCD_OPC_CheckPredicate, 0, 89, 41, 1, // Skip to: 86948 +/* 10827 */ MCD_OPC_Decode, 248, 32, 79, // Opcode: UQINCD_ZPiI +/* 10831 */ MCD_OPC_FilterValue, 1, 80, 41, 1, // Skip to: 86948 +/* 10836 */ MCD_OPC_CheckPredicate, 0, 75, 41, 1, // Skip to: 86948 +/* 10841 */ MCD_OPC_Decode, 179, 5, 79, // Opcode: DECD_ZPiI +/* 10845 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 10866 +/* 10850 */ MCD_OPC_CheckPredicate, 0, 61, 41, 1, // Skip to: 86948 +/* 10855 */ MCD_OPC_CheckField, 20, 1, 0, 54, 41, 1, // Skip to: 86948 +/* 10862 */ MCD_OPC_Decode, 187, 24, 79, // Opcode: SQDECD_ZPiI +/* 10866 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 10887 +/* 10871 */ MCD_OPC_CheckPredicate, 0, 40, 41, 1, // Skip to: 86948 +/* 10876 */ MCD_OPC_CheckField, 20, 1, 0, 33, 41, 1, // Skip to: 86948 +/* 10883 */ MCD_OPC_Decode, 226, 32, 79, // Opcode: UQDECD_ZPiI +/* 10887 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 10923 +/* 10892 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10895 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10909 +/* 10900 */ MCD_OPC_CheckPredicate, 0, 11, 41, 1, // Skip to: 86948 +/* 10905 */ MCD_OPC_Decode, 246, 4, 76, // Opcode: CNTD_XPiI +/* 10909 */ MCD_OPC_FilterValue, 1, 2, 41, 1, // Skip to: 86948 +/* 10914 */ MCD_OPC_CheckPredicate, 0, 253, 40, 1, // Skip to: 86948 +/* 10919 */ MCD_OPC_Decode, 245, 13, 77, // Opcode: INCD_XPiI +/* 10923 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 10944 +/* 10928 */ MCD_OPC_CheckPredicate, 0, 239, 40, 1, // Skip to: 86948 +/* 10933 */ MCD_OPC_CheckField, 20, 1, 1, 232, 40, 1, // Skip to: 86948 +/* 10940 */ MCD_OPC_Decode, 178, 5, 77, // Opcode: DECD_XPiI +/* 10944 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 10980 +/* 10949 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10952 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 10966 +/* 10957 */ MCD_OPC_CheckPredicate, 0, 210, 40, 1, // Skip to: 86948 +/* 10962 */ MCD_OPC_Decode, 128, 25, 77, // Opcode: SQINCD_XPiWdI +/* 10966 */ MCD_OPC_FilterValue, 1, 201, 40, 1, // Skip to: 86948 +/* 10971 */ MCD_OPC_CheckPredicate, 0, 196, 40, 1, // Skip to: 86948 +/* 10976 */ MCD_OPC_Decode, 255, 24, 77, // Opcode: SQINCD_XPiI +/* 10980 */ MCD_OPC_FilterValue, 13, 31, 0, 0, // Skip to: 11016 +/* 10985 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 10988 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11002 +/* 10993 */ MCD_OPC_CheckPredicate, 0, 174, 40, 1, // Skip to: 86948 +/* 10998 */ MCD_OPC_Decode, 246, 32, 78, // Opcode: UQINCD_WPiI +/* 11002 */ MCD_OPC_FilterValue, 1, 165, 40, 1, // Skip to: 86948 +/* 11007 */ MCD_OPC_CheckPredicate, 0, 160, 40, 1, // Skip to: 86948 +/* 11012 */ MCD_OPC_Decode, 247, 32, 77, // Opcode: UQINCD_XPiI +/* 11016 */ MCD_OPC_FilterValue, 14, 31, 0, 0, // Skip to: 11052 +/* 11021 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 11024 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11038 +/* 11029 */ MCD_OPC_CheckPredicate, 0, 138, 40, 1, // Skip to: 86948 +/* 11034 */ MCD_OPC_Decode, 186, 24, 77, // Opcode: SQDECD_XPiWdI +/* 11038 */ MCD_OPC_FilterValue, 1, 129, 40, 1, // Skip to: 86948 +/* 11043 */ MCD_OPC_CheckPredicate, 0, 124, 40, 1, // Skip to: 86948 +/* 11048 */ MCD_OPC_Decode, 185, 24, 77, // Opcode: SQDECD_XPiI +/* 11052 */ MCD_OPC_FilterValue, 15, 115, 40, 1, // Skip to: 86948 +/* 11057 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 11060 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11074 +/* 11065 */ MCD_OPC_CheckPredicate, 0, 102, 40, 1, // Skip to: 86948 +/* 11070 */ MCD_OPC_Decode, 224, 32, 78, // Opcode: UQDECD_WPiI +/* 11074 */ MCD_OPC_FilterValue, 1, 93, 40, 1, // Skip to: 86948 +/* 11079 */ MCD_OPC_CheckPredicate, 0, 88, 40, 1, // Skip to: 86948 +/* 11084 */ MCD_OPC_Decode, 225, 32, 77, // Opcode: UQDECD_XPiI +/* 11088 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 11102 +/* 11093 */ MCD_OPC_CheckPredicate, 0, 74, 40, 1, // Skip to: 86948 +/* 11098 */ MCD_OPC_Decode, 234, 22, 80, // Opcode: SEL_ZPZZ_B +/* 11102 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 11116 +/* 11107 */ MCD_OPC_CheckPredicate, 0, 60, 40, 1, // Skip to: 86948 +/* 11112 */ MCD_OPC_Decode, 236, 22, 80, // Opcode: SEL_ZPZZ_H +/* 11116 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 11130 +/* 11121 */ MCD_OPC_CheckPredicate, 0, 46, 40, 1, // Skip to: 86948 +/* 11126 */ MCD_OPC_Decode, 237, 22, 80, // Opcode: SEL_ZPZZ_S +/* 11130 */ MCD_OPC_FilterValue, 7, 37, 40, 1, // Skip to: 86948 +/* 11135 */ MCD_OPC_CheckPredicate, 0, 32, 40, 1, // Skip to: 86948 +/* 11140 */ MCD_OPC_Decode, 235, 22, 80, // Opcode: SEL_ZPZZ_D +/* 11144 */ MCD_OPC_FilterValue, 1, 8, 23, 0, // Skip to: 17045 +/* 11149 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 11152 */ MCD_OPC_FilterValue, 0, 35, 1, 0, // Skip to: 11448 +/* 11157 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 11160 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11196 +/* 11165 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11182 +/* 11173 */ MCD_OPC_CheckPredicate, 0, 250, 39, 1, // Skip to: 86948 +/* 11178 */ MCD_OPC_Decode, 182, 4, 81, // Opcode: CMPHS_PPzZZ_B +/* 11182 */ MCD_OPC_FilterValue, 1, 241, 39, 1, // Skip to: 86948 +/* 11187 */ MCD_OPC_CheckPredicate, 0, 236, 39, 1, // Skip to: 86948 +/* 11192 */ MCD_OPC_Decode, 171, 4, 81, // Opcode: CMPHI_PPzZZ_B +/* 11196 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11232 +/* 11201 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11204 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11218 +/* 11209 */ MCD_OPC_CheckPredicate, 0, 214, 39, 1, // Skip to: 86948 +/* 11214 */ MCD_OPC_Decode, 142, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_B +/* 11218 */ MCD_OPC_FilterValue, 1, 205, 39, 1, // Skip to: 86948 +/* 11223 */ MCD_OPC_CheckPredicate, 0, 200, 39, 1, // Skip to: 86948 +/* 11228 */ MCD_OPC_Decode, 225, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_B +/* 11232 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 11268 +/* 11237 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11240 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11254 +/* 11245 */ MCD_OPC_CheckPredicate, 0, 178, 39, 1, // Skip to: 86948 +/* 11250 */ MCD_OPC_Decode, 153, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_B +/* 11254 */ MCD_OPC_FilterValue, 1, 169, 39, 1, // Skip to: 86948 +/* 11259 */ MCD_OPC_CheckPredicate, 0, 164, 39, 1, // Skip to: 86948 +/* 11264 */ MCD_OPC_Decode, 164, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_B +/* 11268 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 11304 +/* 11273 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11276 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11290 +/* 11281 */ MCD_OPC_CheckPredicate, 0, 142, 39, 1, // Skip to: 86948 +/* 11286 */ MCD_OPC_Decode, 214, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_B +/* 11290 */ MCD_OPC_FilterValue, 1, 133, 39, 1, // Skip to: 86948 +/* 11295 */ MCD_OPC_CheckPredicate, 0, 128, 39, 1, // Skip to: 86948 +/* 11300 */ MCD_OPC_Decode, 193, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_B +/* 11304 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 11340 +/* 11309 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11312 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11326 +/* 11317 */ MCD_OPC_CheckPredicate, 0, 106, 39, 1, // Skip to: 86948 +/* 11322 */ MCD_OPC_Decode, 149, 4, 81, // Opcode: CMPGE_PPzZZ_B +/* 11326 */ MCD_OPC_FilterValue, 1, 97, 39, 1, // Skip to: 86948 +/* 11331 */ MCD_OPC_CheckPredicate, 0, 92, 39, 1, // Skip to: 86948 +/* 11336 */ MCD_OPC_Decode, 160, 4, 81, // Opcode: CMPGT_PPzZZ_B +/* 11340 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 11376 +/* 11345 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11348 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11362 +/* 11353 */ MCD_OPC_CheckPredicate, 0, 70, 39, 1, // Skip to: 86948 +/* 11358 */ MCD_OPC_Decode, 138, 4, 81, // Opcode: CMPEQ_PPzZZ_B +/* 11362 */ MCD_OPC_FilterValue, 1, 61, 39, 1, // Skip to: 86948 +/* 11367 */ MCD_OPC_CheckPredicate, 0, 56, 39, 1, // Skip to: 86948 +/* 11372 */ MCD_OPC_Decode, 221, 4, 81, // Opcode: CMPNE_PPzZZ_B +/* 11376 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 11412 +/* 11381 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11384 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11398 +/* 11389 */ MCD_OPC_CheckPredicate, 0, 34, 39, 1, // Skip to: 86948 +/* 11394 */ MCD_OPC_Decode, 186, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_B +/* 11398 */ MCD_OPC_FilterValue, 1, 25, 39, 1, // Skip to: 86948 +/* 11403 */ MCD_OPC_CheckPredicate, 0, 20, 39, 1, // Skip to: 86948 +/* 11408 */ MCD_OPC_Decode, 175, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_B +/* 11412 */ MCD_OPC_FilterValue, 7, 11, 39, 1, // Skip to: 86948 +/* 11417 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11420 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11434 +/* 11425 */ MCD_OPC_CheckPredicate, 0, 254, 38, 1, // Skip to: 86948 +/* 11430 */ MCD_OPC_Decode, 200, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_B +/* 11434 */ MCD_OPC_FilterValue, 1, 245, 38, 1, // Skip to: 86948 +/* 11439 */ MCD_OPC_CheckPredicate, 0, 240, 38, 1, // Skip to: 86948 +/* 11444 */ MCD_OPC_Decode, 207, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_B +/* 11448 */ MCD_OPC_FilterValue, 1, 75, 0, 0, // Skip to: 11528 +/* 11453 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11456 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11492 +/* 11461 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 11464 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11478 +/* 11469 */ MCD_OPC_CheckPredicate, 0, 210, 38, 1, // Skip to: 86948 +/* 11474 */ MCD_OPC_Decode, 178, 4, 82, // Opcode: CMPHS_PPzZI_B +/* 11478 */ MCD_OPC_FilterValue, 1, 201, 38, 1, // Skip to: 86948 +/* 11483 */ MCD_OPC_CheckPredicate, 0, 196, 38, 1, // Skip to: 86948 +/* 11488 */ MCD_OPC_Decode, 196, 4, 82, // Opcode: CMPLO_PPzZI_B +/* 11492 */ MCD_OPC_FilterValue, 1, 187, 38, 1, // Skip to: 86948 +/* 11497 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 11500 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11514 +/* 11505 */ MCD_OPC_CheckPredicate, 0, 174, 38, 1, // Skip to: 86948 +/* 11510 */ MCD_OPC_Decode, 167, 4, 82, // Opcode: CMPHI_PPzZI_B +/* 11514 */ MCD_OPC_FilterValue, 1, 165, 38, 1, // Skip to: 86948 +/* 11519 */ MCD_OPC_CheckPredicate, 0, 160, 38, 1, // Skip to: 86948 +/* 11524 */ MCD_OPC_Decode, 203, 4, 82, // Opcode: CMPLS_PPzZI_B +/* 11528 */ MCD_OPC_FilterValue, 2, 35, 1, 0, // Skip to: 11824 +/* 11533 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 11536 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11572 +/* 11541 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11544 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11558 +/* 11549 */ MCD_OPC_CheckPredicate, 0, 130, 38, 1, // Skip to: 86948 +/* 11554 */ MCD_OPC_Decode, 184, 4, 81, // Opcode: CMPHS_PPzZZ_H +/* 11558 */ MCD_OPC_FilterValue, 1, 121, 38, 1, // Skip to: 86948 +/* 11563 */ MCD_OPC_CheckPredicate, 0, 116, 38, 1, // Skip to: 86948 +/* 11568 */ MCD_OPC_Decode, 173, 4, 81, // Opcode: CMPHI_PPzZZ_H +/* 11572 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11608 +/* 11577 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11580 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11594 +/* 11585 */ MCD_OPC_CheckPredicate, 0, 94, 38, 1, // Skip to: 86948 +/* 11590 */ MCD_OPC_Decode, 143, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_H +/* 11594 */ MCD_OPC_FilterValue, 1, 85, 38, 1, // Skip to: 86948 +/* 11599 */ MCD_OPC_CheckPredicate, 0, 80, 38, 1, // Skip to: 86948 +/* 11604 */ MCD_OPC_Decode, 226, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_H +/* 11608 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 11644 +/* 11613 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11616 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11630 +/* 11621 */ MCD_OPC_CheckPredicate, 0, 58, 38, 1, // Skip to: 86948 +/* 11626 */ MCD_OPC_Decode, 154, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_H +/* 11630 */ MCD_OPC_FilterValue, 1, 49, 38, 1, // Skip to: 86948 +/* 11635 */ MCD_OPC_CheckPredicate, 0, 44, 38, 1, // Skip to: 86948 +/* 11640 */ MCD_OPC_Decode, 165, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_H +/* 11644 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 11680 +/* 11649 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11652 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11666 +/* 11657 */ MCD_OPC_CheckPredicate, 0, 22, 38, 1, // Skip to: 86948 +/* 11662 */ MCD_OPC_Decode, 215, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_H +/* 11666 */ MCD_OPC_FilterValue, 1, 13, 38, 1, // Skip to: 86948 +/* 11671 */ MCD_OPC_CheckPredicate, 0, 8, 38, 1, // Skip to: 86948 +/* 11676 */ MCD_OPC_Decode, 194, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_H +/* 11680 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 11716 +/* 11685 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11688 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11702 +/* 11693 */ MCD_OPC_CheckPredicate, 0, 242, 37, 1, // Skip to: 86948 +/* 11698 */ MCD_OPC_Decode, 151, 4, 81, // Opcode: CMPGE_PPzZZ_H +/* 11702 */ MCD_OPC_FilterValue, 1, 233, 37, 1, // Skip to: 86948 +/* 11707 */ MCD_OPC_CheckPredicate, 0, 228, 37, 1, // Skip to: 86948 +/* 11712 */ MCD_OPC_Decode, 162, 4, 81, // Opcode: CMPGT_PPzZZ_H +/* 11716 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 11752 +/* 11721 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11738 +/* 11729 */ MCD_OPC_CheckPredicate, 0, 206, 37, 1, // Skip to: 86948 +/* 11734 */ MCD_OPC_Decode, 140, 4, 81, // Opcode: CMPEQ_PPzZZ_H +/* 11738 */ MCD_OPC_FilterValue, 1, 197, 37, 1, // Skip to: 86948 +/* 11743 */ MCD_OPC_CheckPredicate, 0, 192, 37, 1, // Skip to: 86948 +/* 11748 */ MCD_OPC_Decode, 223, 4, 81, // Opcode: CMPNE_PPzZZ_H +/* 11752 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 11788 +/* 11757 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11760 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11774 +/* 11765 */ MCD_OPC_CheckPredicate, 0, 170, 37, 1, // Skip to: 86948 +/* 11770 */ MCD_OPC_Decode, 187, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_H +/* 11774 */ MCD_OPC_FilterValue, 1, 161, 37, 1, // Skip to: 86948 +/* 11779 */ MCD_OPC_CheckPredicate, 0, 156, 37, 1, // Skip to: 86948 +/* 11784 */ MCD_OPC_Decode, 176, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_H +/* 11788 */ MCD_OPC_FilterValue, 7, 147, 37, 1, // Skip to: 86948 +/* 11793 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11796 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11810 +/* 11801 */ MCD_OPC_CheckPredicate, 0, 134, 37, 1, // Skip to: 86948 +/* 11806 */ MCD_OPC_Decode, 201, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_H +/* 11810 */ MCD_OPC_FilterValue, 1, 125, 37, 1, // Skip to: 86948 +/* 11815 */ MCD_OPC_CheckPredicate, 0, 120, 37, 1, // Skip to: 86948 +/* 11820 */ MCD_OPC_Decode, 208, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_H +/* 11824 */ MCD_OPC_FilterValue, 3, 75, 0, 0, // Skip to: 11904 +/* 11829 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11832 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11868 +/* 11837 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 11840 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11854 +/* 11845 */ MCD_OPC_CheckPredicate, 0, 90, 37, 1, // Skip to: 86948 +/* 11850 */ MCD_OPC_Decode, 180, 4, 82, // Opcode: CMPHS_PPzZI_H +/* 11854 */ MCD_OPC_FilterValue, 1, 81, 37, 1, // Skip to: 86948 +/* 11859 */ MCD_OPC_CheckPredicate, 0, 76, 37, 1, // Skip to: 86948 +/* 11864 */ MCD_OPC_Decode, 198, 4, 82, // Opcode: CMPLO_PPzZI_H +/* 11868 */ MCD_OPC_FilterValue, 1, 67, 37, 1, // Skip to: 86948 +/* 11873 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 11876 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11890 +/* 11881 */ MCD_OPC_CheckPredicate, 0, 54, 37, 1, // Skip to: 86948 +/* 11886 */ MCD_OPC_Decode, 169, 4, 82, // Opcode: CMPHI_PPzZI_H +/* 11890 */ MCD_OPC_FilterValue, 1, 45, 37, 1, // Skip to: 86948 +/* 11895 */ MCD_OPC_CheckPredicate, 0, 40, 37, 1, // Skip to: 86948 +/* 11900 */ MCD_OPC_Decode, 205, 4, 82, // Opcode: CMPLS_PPzZI_H +/* 11904 */ MCD_OPC_FilterValue, 4, 35, 1, 0, // Skip to: 12200 +/* 11909 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 11912 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 11948 +/* 11917 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11920 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11934 +/* 11925 */ MCD_OPC_CheckPredicate, 0, 10, 37, 1, // Skip to: 86948 +/* 11930 */ MCD_OPC_Decode, 185, 4, 81, // Opcode: CMPHS_PPzZZ_S +/* 11934 */ MCD_OPC_FilterValue, 1, 1, 37, 1, // Skip to: 86948 +/* 11939 */ MCD_OPC_CheckPredicate, 0, 252, 36, 1, // Skip to: 86948 +/* 11944 */ MCD_OPC_Decode, 174, 4, 81, // Opcode: CMPHI_PPzZZ_S +/* 11948 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 11984 +/* 11953 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11956 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 11970 +/* 11961 */ MCD_OPC_CheckPredicate, 0, 230, 36, 1, // Skip to: 86948 +/* 11966 */ MCD_OPC_Decode, 144, 4, 81, // Opcode: CMPEQ_WIDE_PPzZZ_S +/* 11970 */ MCD_OPC_FilterValue, 1, 221, 36, 1, // Skip to: 86948 +/* 11975 */ MCD_OPC_CheckPredicate, 0, 216, 36, 1, // Skip to: 86948 +/* 11980 */ MCD_OPC_Decode, 227, 4, 81, // Opcode: CMPNE_WIDE_PPzZZ_S +/* 11984 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 12020 +/* 11989 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 11992 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12006 +/* 11997 */ MCD_OPC_CheckPredicate, 0, 194, 36, 1, // Skip to: 86948 +/* 12002 */ MCD_OPC_Decode, 155, 4, 81, // Opcode: CMPGE_WIDE_PPzZZ_S +/* 12006 */ MCD_OPC_FilterValue, 1, 185, 36, 1, // Skip to: 86948 +/* 12011 */ MCD_OPC_CheckPredicate, 0, 180, 36, 1, // Skip to: 86948 +/* 12016 */ MCD_OPC_Decode, 166, 4, 81, // Opcode: CMPGT_WIDE_PPzZZ_S +/* 12020 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 12056 +/* 12025 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12028 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12042 +/* 12033 */ MCD_OPC_CheckPredicate, 0, 158, 36, 1, // Skip to: 86948 +/* 12038 */ MCD_OPC_Decode, 216, 4, 81, // Opcode: CMPLT_WIDE_PPzZZ_S +/* 12042 */ MCD_OPC_FilterValue, 1, 149, 36, 1, // Skip to: 86948 +/* 12047 */ MCD_OPC_CheckPredicate, 0, 144, 36, 1, // Skip to: 86948 +/* 12052 */ MCD_OPC_Decode, 195, 4, 81, // Opcode: CMPLE_WIDE_PPzZZ_S +/* 12056 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 12092 +/* 12061 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12064 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12078 +/* 12069 */ MCD_OPC_CheckPredicate, 0, 122, 36, 1, // Skip to: 86948 +/* 12074 */ MCD_OPC_Decode, 152, 4, 81, // Opcode: CMPGE_PPzZZ_S +/* 12078 */ MCD_OPC_FilterValue, 1, 113, 36, 1, // Skip to: 86948 +/* 12083 */ MCD_OPC_CheckPredicate, 0, 108, 36, 1, // Skip to: 86948 +/* 12088 */ MCD_OPC_Decode, 163, 4, 81, // Opcode: CMPGT_PPzZZ_S +/* 12092 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 12128 +/* 12097 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12100 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12114 +/* 12105 */ MCD_OPC_CheckPredicate, 0, 86, 36, 1, // Skip to: 86948 +/* 12110 */ MCD_OPC_Decode, 141, 4, 81, // Opcode: CMPEQ_PPzZZ_S +/* 12114 */ MCD_OPC_FilterValue, 1, 77, 36, 1, // Skip to: 86948 +/* 12119 */ MCD_OPC_CheckPredicate, 0, 72, 36, 1, // Skip to: 86948 +/* 12124 */ MCD_OPC_Decode, 224, 4, 81, // Opcode: CMPNE_PPzZZ_S +/* 12128 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 12164 +/* 12133 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12136 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12150 +/* 12141 */ MCD_OPC_CheckPredicate, 0, 50, 36, 1, // Skip to: 86948 +/* 12146 */ MCD_OPC_Decode, 188, 4, 81, // Opcode: CMPHS_WIDE_PPzZZ_S +/* 12150 */ MCD_OPC_FilterValue, 1, 41, 36, 1, // Skip to: 86948 +/* 12155 */ MCD_OPC_CheckPredicate, 0, 36, 36, 1, // Skip to: 86948 +/* 12160 */ MCD_OPC_Decode, 177, 4, 81, // Opcode: CMPHI_WIDE_PPzZZ_S +/* 12164 */ MCD_OPC_FilterValue, 7, 27, 36, 1, // Skip to: 86948 +/* 12169 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12172 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12186 +/* 12177 */ MCD_OPC_CheckPredicate, 0, 14, 36, 1, // Skip to: 86948 +/* 12182 */ MCD_OPC_Decode, 202, 4, 81, // Opcode: CMPLO_WIDE_PPzZZ_S +/* 12186 */ MCD_OPC_FilterValue, 1, 5, 36, 1, // Skip to: 86948 +/* 12191 */ MCD_OPC_CheckPredicate, 0, 0, 36, 1, // Skip to: 86948 +/* 12196 */ MCD_OPC_Decode, 209, 4, 81, // Opcode: CMPLS_WIDE_PPzZZ_S +/* 12200 */ MCD_OPC_FilterValue, 5, 75, 0, 0, // Skip to: 12280 +/* 12205 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12208 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12244 +/* 12213 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 12216 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12230 +/* 12221 */ MCD_OPC_CheckPredicate, 0, 226, 35, 1, // Skip to: 86948 +/* 12226 */ MCD_OPC_Decode, 181, 4, 82, // Opcode: CMPHS_PPzZI_S +/* 12230 */ MCD_OPC_FilterValue, 1, 217, 35, 1, // Skip to: 86948 +/* 12235 */ MCD_OPC_CheckPredicate, 0, 212, 35, 1, // Skip to: 86948 +/* 12240 */ MCD_OPC_Decode, 199, 4, 82, // Opcode: CMPLO_PPzZI_S +/* 12244 */ MCD_OPC_FilterValue, 1, 203, 35, 1, // Skip to: 86948 +/* 12249 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 12252 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12266 +/* 12257 */ MCD_OPC_CheckPredicate, 0, 190, 35, 1, // Skip to: 86948 +/* 12262 */ MCD_OPC_Decode, 170, 4, 82, // Opcode: CMPHI_PPzZI_S +/* 12266 */ MCD_OPC_FilterValue, 1, 181, 35, 1, // Skip to: 86948 +/* 12271 */ MCD_OPC_CheckPredicate, 0, 176, 35, 1, // Skip to: 86948 +/* 12276 */ MCD_OPC_Decode, 206, 4, 82, // Opcode: CMPLS_PPzZI_S +/* 12280 */ MCD_OPC_FilterValue, 6, 111, 0, 0, // Skip to: 12396 +/* 12285 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 12288 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12324 +/* 12293 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12296 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12310 +/* 12301 */ MCD_OPC_CheckPredicate, 0, 146, 35, 1, // Skip to: 86948 +/* 12306 */ MCD_OPC_Decode, 183, 4, 81, // Opcode: CMPHS_PPzZZ_D +/* 12310 */ MCD_OPC_FilterValue, 1, 137, 35, 1, // Skip to: 86948 +/* 12315 */ MCD_OPC_CheckPredicate, 0, 132, 35, 1, // Skip to: 86948 +/* 12320 */ MCD_OPC_Decode, 172, 4, 81, // Opcode: CMPHI_PPzZZ_D +/* 12324 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 12360 +/* 12329 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12332 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12346 +/* 12337 */ MCD_OPC_CheckPredicate, 0, 110, 35, 1, // Skip to: 86948 +/* 12342 */ MCD_OPC_Decode, 150, 4, 81, // Opcode: CMPGE_PPzZZ_D +/* 12346 */ MCD_OPC_FilterValue, 1, 101, 35, 1, // Skip to: 86948 +/* 12351 */ MCD_OPC_CheckPredicate, 0, 96, 35, 1, // Skip to: 86948 +/* 12356 */ MCD_OPC_Decode, 161, 4, 81, // Opcode: CMPGT_PPzZZ_D +/* 12360 */ MCD_OPC_FilterValue, 5, 87, 35, 1, // Skip to: 86948 +/* 12365 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12368 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12382 +/* 12373 */ MCD_OPC_CheckPredicate, 0, 74, 35, 1, // Skip to: 86948 +/* 12378 */ MCD_OPC_Decode, 139, 4, 81, // Opcode: CMPEQ_PPzZZ_D +/* 12382 */ MCD_OPC_FilterValue, 1, 65, 35, 1, // Skip to: 86948 +/* 12387 */ MCD_OPC_CheckPredicate, 0, 60, 35, 1, // Skip to: 86948 +/* 12392 */ MCD_OPC_Decode, 222, 4, 81, // Opcode: CMPNE_PPzZZ_D +/* 12396 */ MCD_OPC_FilterValue, 7, 75, 0, 0, // Skip to: 12476 +/* 12401 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12404 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12440 +/* 12409 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 12412 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12426 +/* 12417 */ MCD_OPC_CheckPredicate, 0, 30, 35, 1, // Skip to: 86948 +/* 12422 */ MCD_OPC_Decode, 179, 4, 82, // Opcode: CMPHS_PPzZI_D +/* 12426 */ MCD_OPC_FilterValue, 1, 21, 35, 1, // Skip to: 86948 +/* 12431 */ MCD_OPC_CheckPredicate, 0, 16, 35, 1, // Skip to: 86948 +/* 12436 */ MCD_OPC_Decode, 197, 4, 82, // Opcode: CMPLO_PPzZI_D +/* 12440 */ MCD_OPC_FilterValue, 1, 7, 35, 1, // Skip to: 86948 +/* 12445 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 12448 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12462 +/* 12453 */ MCD_OPC_CheckPredicate, 0, 250, 34, 1, // Skip to: 86948 +/* 12458 */ MCD_OPC_Decode, 168, 4, 82, // Opcode: CMPHI_PPzZI_D +/* 12462 */ MCD_OPC_FilterValue, 1, 241, 34, 1, // Skip to: 86948 +/* 12467 */ MCD_OPC_CheckPredicate, 0, 236, 34, 1, // Skip to: 86948 +/* 12472 */ MCD_OPC_Decode, 204, 4, 82, // Opcode: CMPLS_PPzZI_D +/* 12476 */ MCD_OPC_FilterValue, 8, 3, 2, 0, // Skip to: 12996 +/* 12481 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 12484 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 12564 +/* 12489 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12492 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 12528 +/* 12497 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 12500 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12514 +/* 12505 */ MCD_OPC_CheckPredicate, 0, 198, 34, 1, // Skip to: 86948 +/* 12510 */ MCD_OPC_Decode, 145, 4, 83, // Opcode: CMPGE_PPzZI_B +/* 12514 */ MCD_OPC_FilterValue, 1, 189, 34, 1, // Skip to: 86948 +/* 12519 */ MCD_OPC_CheckPredicate, 0, 184, 34, 1, // Skip to: 86948 +/* 12524 */ MCD_OPC_Decode, 210, 4, 83, // Opcode: CMPLT_PPzZI_B +/* 12528 */ MCD_OPC_FilterValue, 1, 175, 34, 1, // Skip to: 86948 +/* 12533 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 12536 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12550 +/* 12541 */ MCD_OPC_CheckPredicate, 0, 162, 34, 1, // Skip to: 86948 +/* 12546 */ MCD_OPC_Decode, 156, 4, 83, // Opcode: CMPGT_PPzZI_B +/* 12550 */ MCD_OPC_FilterValue, 1, 153, 34, 1, // Skip to: 86948 +/* 12555 */ MCD_OPC_CheckPredicate, 0, 148, 34, 1, // Skip to: 86948 +/* 12560 */ MCD_OPC_Decode, 189, 4, 83, // Opcode: CMPLE_PPzZI_B +/* 12564 */ MCD_OPC_FilterValue, 1, 162, 0, 0, // Skip to: 12731 +/* 12569 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12572 */ MCD_OPC_FilterValue, 0, 82, 0, 0, // Skip to: 12659 +/* 12577 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 12580 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 12638 +/* 12585 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12588 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12602 +/* 12593 */ MCD_OPC_CheckPredicate, 0, 110, 34, 1, // Skip to: 86948 +/* 12598 */ MCD_OPC_Decode, 245, 1, 84, // Opcode: AND_PPzPP +/* 12602 */ MCD_OPC_FilterValue, 1, 101, 34, 1, // Skip to: 86948 +/* 12607 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 12610 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12624 +/* 12615 */ MCD_OPC_CheckPredicate, 0, 88, 34, 1, // Skip to: 86948 +/* 12620 */ MCD_OPC_Decode, 211, 2, 85, // Opcode: BRKA_PPzP +/* 12624 */ MCD_OPC_FilterValue, 8, 79, 34, 1, // Skip to: 86948 +/* 12629 */ MCD_OPC_CheckPredicate, 0, 74, 34, 1, // Skip to: 86948 +/* 12634 */ MCD_OPC_Decode, 216, 2, 86, // Opcode: BRKN_PPzP +/* 12638 */ MCD_OPC_FilterValue, 1, 65, 34, 1, // Skip to: 86948 +/* 12643 */ MCD_OPC_CheckPredicate, 0, 60, 34, 1, // Skip to: 86948 +/* 12648 */ MCD_OPC_CheckField, 20, 1, 0, 53, 34, 1, // Skip to: 86948 +/* 12655 */ MCD_OPC_Decode, 238, 5, 84, // Opcode: EOR_PPzPP +/* 12659 */ MCD_OPC_FilterValue, 1, 44, 34, 1, // Skip to: 86948 +/* 12664 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 12667 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 12710 +/* 12672 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12675 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 12689 +/* 12680 */ MCD_OPC_CheckPredicate, 0, 23, 34, 1, // Skip to: 86948 +/* 12685 */ MCD_OPC_Decode, 181, 2, 84, // Opcode: BIC_PPzPP +/* 12689 */ MCD_OPC_FilterValue, 1, 14, 34, 1, // Skip to: 86948 +/* 12694 */ MCD_OPC_CheckPredicate, 0, 9, 34, 1, // Skip to: 86948 +/* 12699 */ MCD_OPC_CheckField, 16, 4, 0, 2, 34, 1, // Skip to: 86948 +/* 12706 */ MCD_OPC_Decode, 210, 2, 87, // Opcode: BRKA_PPmP +/* 12710 */ MCD_OPC_FilterValue, 1, 249, 33, 1, // Skip to: 86948 +/* 12715 */ MCD_OPC_CheckPredicate, 0, 244, 33, 1, // Skip to: 86948 +/* 12720 */ MCD_OPC_CheckField, 20, 1, 0, 237, 33, 1, // Skip to: 86948 +/* 12727 */ MCD_OPC_Decode, 233, 22, 84, // Opcode: SEL_PPPP +/* 12731 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 12781 +/* 12736 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12739 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12760 +/* 12744 */ MCD_OPC_CheckPredicate, 0, 215, 33, 1, // Skip to: 86948 +/* 12749 */ MCD_OPC_CheckField, 13, 1, 0, 208, 33, 1, // Skip to: 86948 +/* 12756 */ MCD_OPC_Decode, 134, 4, 83, // Opcode: CMPEQ_PPzZI_B +/* 12760 */ MCD_OPC_FilterValue, 1, 199, 33, 1, // Skip to: 86948 +/* 12765 */ MCD_OPC_CheckPredicate, 0, 194, 33, 1, // Skip to: 86948 +/* 12770 */ MCD_OPC_CheckField, 13, 1, 0, 187, 33, 1, // Skip to: 86948 +/* 12777 */ MCD_OPC_Decode, 217, 4, 83, // Opcode: CMPNE_PPzZI_B +/* 12781 */ MCD_OPC_FilterValue, 3, 178, 33, 1, // Skip to: 86948 +/* 12786 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 12789 */ MCD_OPC_FilterValue, 0, 174, 0, 0, // Skip to: 12968 +/* 12794 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 12797 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 12818 +/* 12802 */ MCD_OPC_CheckPredicate, 0, 157, 33, 1, // Skip to: 86948 +/* 12807 */ MCD_OPC_CheckField, 9, 1, 0, 150, 33, 1, // Skip to: 86948 +/* 12814 */ MCD_OPC_Decode, 218, 2, 84, // Opcode: BRKPA_PPzPP +/* 12818 */ MCD_OPC_FilterValue, 1, 141, 33, 1, // Skip to: 86948 +/* 12823 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 12826 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 12854 +/* 12831 */ MCD_OPC_CheckPredicate, 0, 128, 33, 1, // Skip to: 86948 +/* 12836 */ MCD_OPC_CheckField, 16, 4, 9, 121, 33, 1, // Skip to: 86948 +/* 12843 */ MCD_OPC_CheckField, 9, 1, 0, 114, 33, 1, // Skip to: 86948 +/* 12850 */ MCD_OPC_Decode, 249, 20, 88, // Opcode: PNEXT_B +/* 12854 */ MCD_OPC_FilterValue, 8, 31, 0, 0, // Skip to: 12890 +/* 12859 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 12862 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 12876 +/* 12867 */ MCD_OPC_CheckPredicate, 0, 92, 33, 1, // Skip to: 86948 +/* 12872 */ MCD_OPC_Decode, 171, 21, 89, // Opcode: PTRUE_B +/* 12876 */ MCD_OPC_FilterValue, 9, 83, 33, 1, // Skip to: 86948 +/* 12881 */ MCD_OPC_CheckPredicate, 0, 78, 33, 1, // Skip to: 86948 +/* 12886 */ MCD_OPC_Decode, 167, 21, 89, // Opcode: PTRUES_B +/* 12890 */ MCD_OPC_FilterValue, 9, 23, 0, 0, // Skip to: 12918 +/* 12895 */ MCD_OPC_CheckPredicate, 0, 64, 33, 1, // Skip to: 86948 +/* 12900 */ MCD_OPC_CheckField, 16, 4, 8, 57, 33, 1, // Skip to: 86948 +/* 12907 */ MCD_OPC_CheckField, 5, 5, 0, 50, 33, 1, // Skip to: 86948 +/* 12914 */ MCD_OPC_Decode, 242, 20, 90, // Opcode: PFALSE +/* 12918 */ MCD_OPC_FilterValue, 12, 41, 33, 1, // Skip to: 86948 +/* 12923 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 12926 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 12947 +/* 12931 */ MCD_OPC_CheckPredicate, 0, 28, 33, 1, // Skip to: 86948 +/* 12936 */ MCD_OPC_CheckField, 9, 1, 0, 21, 33, 1, // Skip to: 86948 +/* 12943 */ MCD_OPC_Decode, 194, 21, 53, // Opcode: RDFFR_PPz +/* 12947 */ MCD_OPC_FilterValue, 9, 12, 33, 1, // Skip to: 86948 +/* 12952 */ MCD_OPC_CheckPredicate, 0, 7, 33, 1, // Skip to: 86948 +/* 12957 */ MCD_OPC_CheckField, 5, 5, 0, 0, 33, 1, // Skip to: 86948 +/* 12964 */ MCD_OPC_Decode, 193, 21, 90, // Opcode: RDFFR_P +/* 12968 */ MCD_OPC_FilterValue, 1, 247, 32, 1, // Skip to: 86948 +/* 12973 */ MCD_OPC_CheckPredicate, 0, 242, 32, 1, // Skip to: 86948 +/* 12978 */ MCD_OPC_CheckField, 20, 1, 0, 235, 32, 1, // Skip to: 86948 +/* 12985 */ MCD_OPC_CheckField, 9, 1, 0, 228, 32, 1, // Skip to: 86948 +/* 12992 */ MCD_OPC_Decode, 220, 2, 84, // Opcode: BRKPB_PPzPP +/* 12996 */ MCD_OPC_FilterValue, 9, 126, 2, 0, // Skip to: 13639 +/* 13001 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 13004 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 13156 +/* 13009 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 13012 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 13048 +/* 13017 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13020 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13034 +/* 13025 */ MCD_OPC_CheckPredicate, 0, 190, 32, 1, // Skip to: 86948 +/* 13030 */ MCD_OPC_Decode, 242, 34, 91, // Opcode: WHILELT_PWW_B +/* 13034 */ MCD_OPC_FilterValue, 1, 181, 32, 1, // Skip to: 86948 +/* 13039 */ MCD_OPC_CheckPredicate, 0, 176, 32, 1, // Skip to: 86948 +/* 13044 */ MCD_OPC_Decode, 218, 34, 91, // Opcode: WHILELE_PWW_B +/* 13048 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 13084 +/* 13053 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13056 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13070 +/* 13061 */ MCD_OPC_CheckPredicate, 0, 154, 32, 1, // Skip to: 86948 +/* 13066 */ MCD_OPC_Decode, 226, 34, 91, // Opcode: WHILELO_PWW_B +/* 13070 */ MCD_OPC_FilterValue, 1, 145, 32, 1, // Skip to: 86948 +/* 13075 */ MCD_OPC_CheckPredicate, 0, 140, 32, 1, // Skip to: 86948 +/* 13080 */ MCD_OPC_Decode, 234, 34, 91, // Opcode: WHILELS_PWW_B +/* 13084 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 13120 +/* 13089 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13092 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13106 +/* 13097 */ MCD_OPC_CheckPredicate, 0, 118, 32, 1, // Skip to: 86948 +/* 13102 */ MCD_OPC_Decode, 246, 34, 92, // Opcode: WHILELT_PXX_B +/* 13106 */ MCD_OPC_FilterValue, 1, 109, 32, 1, // Skip to: 86948 +/* 13111 */ MCD_OPC_CheckPredicate, 0, 104, 32, 1, // Skip to: 86948 +/* 13116 */ MCD_OPC_Decode, 222, 34, 92, // Opcode: WHILELE_PXX_B +/* 13120 */ MCD_OPC_FilterValue, 7, 95, 32, 1, // Skip to: 86948 +/* 13125 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13128 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13142 +/* 13133 */ MCD_OPC_CheckPredicate, 0, 82, 32, 1, // Skip to: 86948 +/* 13138 */ MCD_OPC_Decode, 230, 34, 92, // Opcode: WHILELO_PXX_B +/* 13142 */ MCD_OPC_FilterValue, 1, 73, 32, 1, // Skip to: 86948 +/* 13147 */ MCD_OPC_CheckPredicate, 0, 68, 32, 1, // Skip to: 86948 +/* 13152 */ MCD_OPC_Decode, 238, 34, 92, // Opcode: WHILELS_PXX_B +/* 13156 */ MCD_OPC_FilterValue, 2, 253, 0, 0, // Skip to: 13414 +/* 13161 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 13164 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13185 +/* 13169 */ MCD_OPC_CheckPredicate, 0, 46, 32, 1, // Skip to: 86948 +/* 13174 */ MCD_OPC_CheckField, 9, 1, 0, 39, 32, 1, // Skip to: 86948 +/* 13181 */ MCD_OPC_Decode, 248, 4, 93, // Opcode: CNTP_XPP_B +/* 13185 */ MCD_OPC_FilterValue, 8, 52, 0, 0, // Skip to: 13242 +/* 13190 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 13193 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13207 +/* 13198 */ MCD_OPC_CheckPredicate, 0, 17, 32, 1, // Skip to: 86948 +/* 13203 */ MCD_OPC_Decode, 133, 25, 94, // Opcode: SQINCP_XPWd_B +/* 13207 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 13221 +/* 13212 */ MCD_OPC_CheckPredicate, 0, 3, 32, 1, // Skip to: 86948 +/* 13217 */ MCD_OPC_Decode, 137, 25, 94, // Opcode: SQINCP_XP_B +/* 13221 */ MCD_OPC_FilterValue, 8, 250, 31, 1, // Skip to: 86948 +/* 13226 */ MCD_OPC_CheckPredicate, 0, 245, 31, 1, // Skip to: 86948 +/* 13231 */ MCD_OPC_CheckField, 0, 5, 0, 238, 31, 1, // Skip to: 86948 +/* 13238 */ MCD_OPC_Decode, 250, 34, 95, // Opcode: WRFFR +/* 13242 */ MCD_OPC_FilterValue, 9, 31, 0, 0, // Skip to: 13278 +/* 13247 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 13250 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13264 +/* 13255 */ MCD_OPC_CheckPredicate, 0, 216, 31, 1, // Skip to: 86948 +/* 13260 */ MCD_OPC_Decode, 252, 32, 96, // Opcode: UQINCP_WP_B +/* 13264 */ MCD_OPC_FilterValue, 6, 207, 31, 1, // Skip to: 86948 +/* 13269 */ MCD_OPC_CheckPredicate, 0, 202, 31, 1, // Skip to: 86948 +/* 13274 */ MCD_OPC_Decode, 128, 33, 94, // Opcode: UQINCP_XP_B +/* 13278 */ MCD_OPC_FilterValue, 10, 31, 0, 0, // Skip to: 13314 +/* 13283 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 13286 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13300 +/* 13291 */ MCD_OPC_CheckPredicate, 0, 180, 31, 1, // Skip to: 86948 +/* 13296 */ MCD_OPC_Decode, 191, 24, 94, // Opcode: SQDECP_XPWd_B +/* 13300 */ MCD_OPC_FilterValue, 6, 171, 31, 1, // Skip to: 86948 +/* 13305 */ MCD_OPC_CheckPredicate, 0, 166, 31, 1, // Skip to: 86948 +/* 13310 */ MCD_OPC_Decode, 195, 24, 94, // Opcode: SQDECP_XP_B +/* 13314 */ MCD_OPC_FilterValue, 11, 31, 0, 0, // Skip to: 13350 +/* 13319 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 13322 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13336 +/* 13327 */ MCD_OPC_CheckPredicate, 0, 144, 31, 1, // Skip to: 86948 +/* 13332 */ MCD_OPC_Decode, 230, 32, 96, // Opcode: UQDECP_WP_B +/* 13336 */ MCD_OPC_FilterValue, 6, 135, 31, 1, // Skip to: 86948 +/* 13341 */ MCD_OPC_CheckPredicate, 0, 130, 31, 1, // Skip to: 86948 +/* 13346 */ MCD_OPC_Decode, 234, 32, 94, // Opcode: UQDECP_XP_B +/* 13350 */ MCD_OPC_FilterValue, 12, 38, 0, 0, // Skip to: 13393 +/* 13355 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 13358 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13372 +/* 13363 */ MCD_OPC_CheckPredicate, 0, 108, 31, 1, // Skip to: 86948 +/* 13368 */ MCD_OPC_Decode, 249, 13, 94, // Opcode: INCP_XP_B +/* 13372 */ MCD_OPC_FilterValue, 8, 99, 31, 1, // Skip to: 86948 +/* 13377 */ MCD_OPC_CheckPredicate, 0, 94, 31, 1, // Skip to: 86948 +/* 13382 */ MCD_OPC_CheckField, 0, 9, 0, 87, 31, 1, // Skip to: 86948 +/* 13389 */ MCD_OPC_Decode, 240, 22, 97, // Opcode: SETFFR +/* 13393 */ MCD_OPC_FilterValue, 13, 78, 31, 1, // Skip to: 86948 +/* 13398 */ MCD_OPC_CheckPredicate, 0, 73, 31, 1, // Skip to: 86948 +/* 13403 */ MCD_OPC_CheckField, 9, 5, 4, 66, 31, 1, // Skip to: 86948 +/* 13410 */ MCD_OPC_Decode, 182, 5, 94, // Opcode: DECP_XP_B +/* 13414 */ MCD_OPC_FilterValue, 3, 57, 31, 1, // Skip to: 86948 +/* 13419 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 13422 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13436 +/* 13427 */ MCD_OPC_CheckPredicate, 0, 44, 31, 1, // Skip to: 86948 +/* 13432 */ MCD_OPC_Decode, 181, 1, 98, // Opcode: ADD_ZI_B +/* 13436 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 13450 +/* 13441 */ MCD_OPC_CheckPredicate, 0, 30, 31, 1, // Skip to: 86948 +/* 13446 */ MCD_OPC_Decode, 243, 29, 98, // Opcode: SUB_ZI_B +/* 13450 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 13464 +/* 13455 */ MCD_OPC_CheckPredicate, 0, 16, 31, 1, // Skip to: 86948 +/* 13460 */ MCD_OPC_Decode, 217, 29, 98, // Opcode: SUBR_ZI_B +/* 13464 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 13478 +/* 13469 */ MCD_OPC_CheckPredicate, 0, 2, 31, 1, // Skip to: 86948 +/* 13474 */ MCD_OPC_Decode, 164, 24, 98, // Opcode: SQADD_ZI_B +/* 13478 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 13492 +/* 13483 */ MCD_OPC_CheckPredicate, 0, 244, 30, 1, // Skip to: 86948 +/* 13488 */ MCD_OPC_Decode, 203, 32, 98, // Opcode: UQADD_ZI_B +/* 13492 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 13506 +/* 13497 */ MCD_OPC_CheckPredicate, 0, 230, 30, 1, // Skip to: 86948 +/* 13502 */ MCD_OPC_Decode, 146, 26, 98, // Opcode: SQSUB_ZI_B +/* 13506 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 13520 +/* 13511 */ MCD_OPC_CheckPredicate, 0, 216, 30, 1, // Skip to: 86948 +/* 13516 */ MCD_OPC_Decode, 189, 33, 98, // Opcode: UQSUB_ZI_B +/* 13520 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 13541 +/* 13525 */ MCD_OPC_CheckPredicate, 0, 202, 30, 1, // Skip to: 86948 +/* 13530 */ MCD_OPC_CheckField, 13, 1, 0, 195, 30, 1, // Skip to: 86948 +/* 13537 */ MCD_OPC_Decode, 192, 23, 99, // Opcode: SMAX_ZI_B +/* 13541 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 13562 +/* 13546 */ MCD_OPC_CheckPredicate, 0, 181, 30, 1, // Skip to: 86948 +/* 13551 */ MCD_OPC_CheckField, 13, 1, 0, 174, 30, 1, // Skip to: 86948 +/* 13558 */ MCD_OPC_Decode, 248, 31, 100, // Opcode: UMAX_ZI_B +/* 13562 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 13583 +/* 13567 */ MCD_OPC_CheckPredicate, 0, 160, 30, 1, // Skip to: 86948 +/* 13572 */ MCD_OPC_CheckField, 13, 1, 0, 153, 30, 1, // Skip to: 86948 +/* 13579 */ MCD_OPC_Decode, 222, 23, 99, // Opcode: SMIN_ZI_B +/* 13583 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 13604 +/* 13588 */ MCD_OPC_CheckPredicate, 0, 139, 30, 1, // Skip to: 86948 +/* 13593 */ MCD_OPC_CheckField, 13, 1, 0, 132, 30, 1, // Skip to: 86948 +/* 13600 */ MCD_OPC_Decode, 149, 32, 100, // Opcode: UMIN_ZI_B +/* 13604 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 13625 +/* 13609 */ MCD_OPC_CheckPredicate, 0, 118, 30, 1, // Skip to: 86948 +/* 13614 */ MCD_OPC_CheckField, 13, 1, 0, 111, 30, 1, // Skip to: 86948 +/* 13621 */ MCD_OPC_Decode, 149, 20, 99, // Opcode: MUL_ZI_B +/* 13625 */ MCD_OPC_FilterValue, 24, 102, 30, 1, // Skip to: 86948 +/* 13630 */ MCD_OPC_CheckPredicate, 0, 97, 30, 1, // Skip to: 86948 +/* 13635 */ MCD_OPC_Decode, 195, 5, 101, // Opcode: DUP_ZI_B +/* 13639 */ MCD_OPC_FilterValue, 10, 208, 1, 0, // Skip to: 14108 +/* 13644 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 13647 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 13727 +/* 13652 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13655 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 13691 +/* 13660 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 13663 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13677 +/* 13668 */ MCD_OPC_CheckPredicate, 0, 59, 30, 1, // Skip to: 86948 +/* 13673 */ MCD_OPC_Decode, 147, 4, 83, // Opcode: CMPGE_PPzZI_H +/* 13677 */ MCD_OPC_FilterValue, 1, 50, 30, 1, // Skip to: 86948 +/* 13682 */ MCD_OPC_CheckPredicate, 0, 45, 30, 1, // Skip to: 86948 +/* 13687 */ MCD_OPC_Decode, 212, 4, 83, // Opcode: CMPLT_PPzZI_H +/* 13691 */ MCD_OPC_FilterValue, 1, 36, 30, 1, // Skip to: 86948 +/* 13696 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 13699 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13713 +/* 13704 */ MCD_OPC_CheckPredicate, 0, 23, 30, 1, // Skip to: 86948 +/* 13709 */ MCD_OPC_Decode, 158, 4, 83, // Opcode: CMPGT_PPzZI_H +/* 13713 */ MCD_OPC_FilterValue, 1, 14, 30, 1, // Skip to: 86948 +/* 13718 */ MCD_OPC_CheckPredicate, 0, 9, 30, 1, // Skip to: 86948 +/* 13723 */ MCD_OPC_Decode, 191, 4, 83, // Opcode: CMPLE_PPzZI_H +/* 13727 */ MCD_OPC_FilterValue, 1, 118, 0, 0, // Skip to: 13850 +/* 13732 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13735 */ MCD_OPC_FilterValue, 0, 82, 0, 0, // Skip to: 13822 +/* 13740 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 13743 */ MCD_OPC_FilterValue, 0, 53, 0, 0, // Skip to: 13801 +/* 13748 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13751 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13765 +/* 13756 */ MCD_OPC_CheckPredicate, 0, 227, 29, 1, // Skip to: 86948 +/* 13761 */ MCD_OPC_Decode, 234, 1, 84, // Opcode: ANDS_PPzPP +/* 13765 */ MCD_OPC_FilterValue, 1, 218, 29, 1, // Skip to: 86948 +/* 13770 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 13773 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 13787 +/* 13778 */ MCD_OPC_CheckPredicate, 0, 205, 29, 1, // Skip to: 86948 +/* 13783 */ MCD_OPC_Decode, 209, 2, 85, // Opcode: BRKAS_PPzP +/* 13787 */ MCD_OPC_FilterValue, 8, 196, 29, 1, // Skip to: 86948 +/* 13792 */ MCD_OPC_CheckPredicate, 0, 191, 29, 1, // Skip to: 86948 +/* 13797 */ MCD_OPC_Decode, 215, 2, 86, // Opcode: BRKNS_PPzP +/* 13801 */ MCD_OPC_FilterValue, 1, 182, 29, 1, // Skip to: 86948 +/* 13806 */ MCD_OPC_CheckPredicate, 0, 177, 29, 1, // Skip to: 86948 +/* 13811 */ MCD_OPC_CheckField, 20, 1, 0, 170, 29, 1, // Skip to: 86948 +/* 13818 */ MCD_OPC_Decode, 227, 5, 84, // Opcode: EORS_PPzPP +/* 13822 */ MCD_OPC_FilterValue, 1, 161, 29, 1, // Skip to: 86948 +/* 13827 */ MCD_OPC_CheckPredicate, 0, 156, 29, 1, // Skip to: 86948 +/* 13832 */ MCD_OPC_CheckField, 20, 1, 0, 149, 29, 1, // Skip to: 86948 +/* 13839 */ MCD_OPC_CheckField, 9, 1, 0, 142, 29, 1, // Skip to: 86948 +/* 13846 */ MCD_OPC_Decode, 176, 2, 84, // Opcode: BICS_PPzPP +/* 13850 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 13900 +/* 13855 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13858 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13879 +/* 13863 */ MCD_OPC_CheckPredicate, 0, 120, 29, 1, // Skip to: 86948 +/* 13868 */ MCD_OPC_CheckField, 13, 1, 0, 113, 29, 1, // Skip to: 86948 +/* 13875 */ MCD_OPC_Decode, 136, 4, 83, // Opcode: CMPEQ_PPzZI_H +/* 13879 */ MCD_OPC_FilterValue, 1, 104, 29, 1, // Skip to: 86948 +/* 13884 */ MCD_OPC_CheckPredicate, 0, 99, 29, 1, // Skip to: 86948 +/* 13889 */ MCD_OPC_CheckField, 13, 1, 0, 92, 29, 1, // Skip to: 86948 +/* 13896 */ MCD_OPC_Decode, 219, 4, 83, // Opcode: CMPNE_PPzZI_H +/* 13900 */ MCD_OPC_FilterValue, 3, 83, 29, 1, // Skip to: 86948 +/* 13905 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 13908 */ MCD_OPC_FilterValue, 0, 167, 0, 0, // Skip to: 14080 +/* 13913 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 13916 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 13937 +/* 13921 */ MCD_OPC_CheckPredicate, 0, 62, 29, 1, // Skip to: 86948 +/* 13926 */ MCD_OPC_CheckField, 9, 1, 0, 55, 29, 1, // Skip to: 86948 +/* 13933 */ MCD_OPC_Decode, 217, 2, 84, // Opcode: BRKPAS_PPzPP +/* 13937 */ MCD_OPC_FilterValue, 1, 46, 29, 1, // Skip to: 86948 +/* 13942 */ MCD_OPC_ExtractField, 16, 4, // Inst{19-16} ... +/* 13945 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 13973 +/* 13950 */ MCD_OPC_CheckPredicate, 0, 33, 29, 1, // Skip to: 86948 +/* 13955 */ MCD_OPC_CheckField, 9, 1, 0, 26, 29, 1, // Skip to: 86948 +/* 13962 */ MCD_OPC_CheckField, 0, 4, 0, 19, 29, 1, // Skip to: 86948 +/* 13969 */ MCD_OPC_Decode, 166, 21, 102, // Opcode: PTEST_PP +/* 13973 */ MCD_OPC_FilterValue, 8, 59, 0, 0, // Skip to: 14037 +/* 13978 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 13981 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14002 +/* 13986 */ MCD_OPC_CheckPredicate, 0, 253, 28, 1, // Skip to: 86948 +/* 13991 */ MCD_OPC_CheckField, 9, 1, 0, 246, 28, 1, // Skip to: 86948 +/* 13998 */ MCD_OPC_Decode, 163, 35, 88, // Opcode: anonymous_1349 +/* 14002 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 14016 +/* 14007 */ MCD_OPC_CheckPredicate, 0, 232, 28, 1, // Skip to: 86948 +/* 14012 */ MCD_OPC_Decode, 173, 21, 89, // Opcode: PTRUE_H +/* 14016 */ MCD_OPC_FilterValue, 12, 223, 28, 1, // Skip to: 86948 +/* 14021 */ MCD_OPC_CheckPredicate, 0, 218, 28, 1, // Skip to: 86948 +/* 14026 */ MCD_OPC_CheckField, 9, 1, 0, 211, 28, 1, // Skip to: 86948 +/* 14033 */ MCD_OPC_Decode, 192, 21, 53, // Opcode: RDFFRS_PPz +/* 14037 */ MCD_OPC_FilterValue, 9, 202, 28, 1, // Skip to: 86948 +/* 14042 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 14045 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 14066 +/* 14050 */ MCD_OPC_CheckPredicate, 0, 189, 28, 1, // Skip to: 86948 +/* 14055 */ MCD_OPC_CheckField, 9, 1, 0, 182, 28, 1, // Skip to: 86948 +/* 14062 */ MCD_OPC_Decode, 251, 20, 88, // Opcode: PNEXT_H +/* 14066 */ MCD_OPC_FilterValue, 8, 173, 28, 1, // Skip to: 86948 +/* 14071 */ MCD_OPC_CheckPredicate, 0, 168, 28, 1, // Skip to: 86948 +/* 14076 */ MCD_OPC_Decode, 169, 21, 89, // Opcode: PTRUES_H +/* 14080 */ MCD_OPC_FilterValue, 1, 159, 28, 1, // Skip to: 86948 +/* 14085 */ MCD_OPC_CheckPredicate, 0, 154, 28, 1, // Skip to: 86948 +/* 14090 */ MCD_OPC_CheckField, 20, 1, 0, 147, 28, 1, // Skip to: 86948 +/* 14097 */ MCD_OPC_CheckField, 9, 1, 0, 140, 28, 1, // Skip to: 86948 +/* 14104 */ MCD_OPC_Decode, 219, 2, 84, // Opcode: BRKPBS_PPzPP +/* 14108 */ MCD_OPC_FilterValue, 11, 190, 2, 0, // Skip to: 14815 +/* 14113 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 14116 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 14268 +/* 14121 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 14124 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 14160 +/* 14129 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 14132 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14146 +/* 14137 */ MCD_OPC_CheckPredicate, 0, 102, 28, 1, // Skip to: 86948 +/* 14142 */ MCD_OPC_Decode, 244, 34, 91, // Opcode: WHILELT_PWW_H +/* 14146 */ MCD_OPC_FilterValue, 1, 93, 28, 1, // Skip to: 86948 +/* 14151 */ MCD_OPC_CheckPredicate, 0, 88, 28, 1, // Skip to: 86948 +/* 14156 */ MCD_OPC_Decode, 220, 34, 91, // Opcode: WHILELE_PWW_H +/* 14160 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 14196 +/* 14165 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 14168 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14182 +/* 14173 */ MCD_OPC_CheckPredicate, 0, 66, 28, 1, // Skip to: 86948 +/* 14178 */ MCD_OPC_Decode, 228, 34, 91, // Opcode: WHILELO_PWW_H +/* 14182 */ MCD_OPC_FilterValue, 1, 57, 28, 1, // Skip to: 86948 +/* 14187 */ MCD_OPC_CheckPredicate, 0, 52, 28, 1, // Skip to: 86948 +/* 14192 */ MCD_OPC_Decode, 236, 34, 91, // Opcode: WHILELS_PWW_H +/* 14196 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 14232 +/* 14201 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 14204 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14218 +/* 14209 */ MCD_OPC_CheckPredicate, 0, 30, 28, 1, // Skip to: 86948 +/* 14214 */ MCD_OPC_Decode, 248, 34, 92, // Opcode: WHILELT_PXX_H +/* 14218 */ MCD_OPC_FilterValue, 1, 21, 28, 1, // Skip to: 86948 +/* 14223 */ MCD_OPC_CheckPredicate, 0, 16, 28, 1, // Skip to: 86948 +/* 14228 */ MCD_OPC_Decode, 224, 34, 92, // Opcode: WHILELE_PXX_H +/* 14232 */ MCD_OPC_FilterValue, 7, 7, 28, 1, // Skip to: 86948 +/* 14237 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 14240 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14254 +/* 14245 */ MCD_OPC_CheckPredicate, 0, 250, 27, 1, // Skip to: 86948 +/* 14250 */ MCD_OPC_Decode, 232, 34, 92, // Opcode: WHILELO_PXX_H +/* 14254 */ MCD_OPC_FilterValue, 1, 241, 27, 1, // Skip to: 86948 +/* 14259 */ MCD_OPC_CheckPredicate, 0, 236, 27, 1, // Skip to: 86948 +/* 14264 */ MCD_OPC_Decode, 240, 34, 92, // Opcode: WHILELS_PXX_H +/* 14268 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 14569 +/* 14273 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 14276 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 14297 +/* 14281 */ MCD_OPC_CheckPredicate, 0, 214, 27, 1, // Skip to: 86948 +/* 14286 */ MCD_OPC_CheckField, 9, 1, 0, 207, 27, 1, // Skip to: 86948 +/* 14293 */ MCD_OPC_Decode, 250, 4, 93, // Opcode: CNTP_XPP_H +/* 14297 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 14347 +/* 14302 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 14305 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14319 +/* 14310 */ MCD_OPC_CheckPredicate, 0, 185, 27, 1, // Skip to: 86948 +/* 14315 */ MCD_OPC_Decode, 142, 25, 103, // Opcode: SQINCP_ZP_H +/* 14319 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14333 +/* 14324 */ MCD_OPC_CheckPredicate, 0, 171, 27, 1, // Skip to: 86948 +/* 14329 */ MCD_OPC_Decode, 135, 25, 94, // Opcode: SQINCP_XPWd_H +/* 14333 */ MCD_OPC_FilterValue, 6, 162, 27, 1, // Skip to: 86948 +/* 14338 */ MCD_OPC_CheckPredicate, 0, 157, 27, 1, // Skip to: 86948 +/* 14343 */ MCD_OPC_Decode, 139, 25, 94, // Opcode: SQINCP_XP_H +/* 14347 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 14397 +/* 14352 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 14355 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14369 +/* 14360 */ MCD_OPC_CheckPredicate, 0, 135, 27, 1, // Skip to: 86948 +/* 14365 */ MCD_OPC_Decode, 133, 33, 103, // Opcode: UQINCP_ZP_H +/* 14369 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14383 +/* 14374 */ MCD_OPC_CheckPredicate, 0, 121, 27, 1, // Skip to: 86948 +/* 14379 */ MCD_OPC_Decode, 254, 32, 96, // Opcode: UQINCP_WP_H +/* 14383 */ MCD_OPC_FilterValue, 6, 112, 27, 1, // Skip to: 86948 +/* 14388 */ MCD_OPC_CheckPredicate, 0, 107, 27, 1, // Skip to: 86948 +/* 14393 */ MCD_OPC_Decode, 130, 33, 94, // Opcode: UQINCP_XP_H +/* 14397 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 14447 +/* 14402 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 14405 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14419 +/* 14410 */ MCD_OPC_CheckPredicate, 0, 85, 27, 1, // Skip to: 86948 +/* 14415 */ MCD_OPC_Decode, 200, 24, 103, // Opcode: SQDECP_ZP_H +/* 14419 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14433 +/* 14424 */ MCD_OPC_CheckPredicate, 0, 71, 27, 1, // Skip to: 86948 +/* 14429 */ MCD_OPC_Decode, 193, 24, 94, // Opcode: SQDECP_XPWd_H +/* 14433 */ MCD_OPC_FilterValue, 6, 62, 27, 1, // Skip to: 86948 +/* 14438 */ MCD_OPC_CheckPredicate, 0, 57, 27, 1, // Skip to: 86948 +/* 14443 */ MCD_OPC_Decode, 197, 24, 94, // Opcode: SQDECP_XP_H +/* 14447 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 14497 +/* 14452 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 14455 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14469 +/* 14460 */ MCD_OPC_CheckPredicate, 0, 35, 27, 1, // Skip to: 86948 +/* 14465 */ MCD_OPC_Decode, 239, 32, 103, // Opcode: UQDECP_ZP_H +/* 14469 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14483 +/* 14474 */ MCD_OPC_CheckPredicate, 0, 21, 27, 1, // Skip to: 86948 +/* 14479 */ MCD_OPC_Decode, 232, 32, 96, // Opcode: UQDECP_WP_H +/* 14483 */ MCD_OPC_FilterValue, 6, 12, 27, 1, // Skip to: 86948 +/* 14488 */ MCD_OPC_CheckPredicate, 0, 7, 27, 1, // Skip to: 86948 +/* 14493 */ MCD_OPC_Decode, 236, 32, 94, // Opcode: UQDECP_XP_H +/* 14497 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 14533 +/* 14502 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 14505 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14519 +/* 14510 */ MCD_OPC_CheckPredicate, 0, 241, 26, 1, // Skip to: 86948 +/* 14515 */ MCD_OPC_Decode, 254, 13, 103, // Opcode: INCP_ZP_H +/* 14519 */ MCD_OPC_FilterValue, 4, 232, 26, 1, // Skip to: 86948 +/* 14524 */ MCD_OPC_CheckPredicate, 0, 227, 26, 1, // Skip to: 86948 +/* 14529 */ MCD_OPC_Decode, 251, 13, 94, // Opcode: INCP_XP_H +/* 14533 */ MCD_OPC_FilterValue, 13, 218, 26, 1, // Skip to: 86948 +/* 14538 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 14541 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14555 +/* 14546 */ MCD_OPC_CheckPredicate, 0, 205, 26, 1, // Skip to: 86948 +/* 14551 */ MCD_OPC_Decode, 187, 5, 103, // Opcode: DECP_ZP_H +/* 14555 */ MCD_OPC_FilterValue, 4, 196, 26, 1, // Skip to: 86948 +/* 14560 */ MCD_OPC_CheckPredicate, 0, 191, 26, 1, // Skip to: 86948 +/* 14565 */ MCD_OPC_Decode, 184, 5, 94, // Opcode: DECP_XP_H +/* 14569 */ MCD_OPC_FilterValue, 3, 182, 26, 1, // Skip to: 86948 +/* 14574 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 14577 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14591 +/* 14582 */ MCD_OPC_CheckPredicate, 0, 169, 26, 1, // Skip to: 86948 +/* 14587 */ MCD_OPC_Decode, 183, 1, 104, // Opcode: ADD_ZI_H +/* 14591 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 14605 +/* 14596 */ MCD_OPC_CheckPredicate, 0, 155, 26, 1, // Skip to: 86948 +/* 14601 */ MCD_OPC_Decode, 245, 29, 104, // Opcode: SUB_ZI_H +/* 14605 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 14619 +/* 14610 */ MCD_OPC_CheckPredicate, 0, 141, 26, 1, // Skip to: 86948 +/* 14615 */ MCD_OPC_Decode, 219, 29, 104, // Opcode: SUBR_ZI_H +/* 14619 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 14633 +/* 14624 */ MCD_OPC_CheckPredicate, 0, 127, 26, 1, // Skip to: 86948 +/* 14629 */ MCD_OPC_Decode, 166, 24, 104, // Opcode: SQADD_ZI_H +/* 14633 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 14647 +/* 14638 */ MCD_OPC_CheckPredicate, 0, 113, 26, 1, // Skip to: 86948 +/* 14643 */ MCD_OPC_Decode, 205, 32, 104, // Opcode: UQADD_ZI_H +/* 14647 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 14661 +/* 14652 */ MCD_OPC_CheckPredicate, 0, 99, 26, 1, // Skip to: 86948 +/* 14657 */ MCD_OPC_Decode, 148, 26, 104, // Opcode: SQSUB_ZI_H +/* 14661 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 14675 +/* 14666 */ MCD_OPC_CheckPredicate, 0, 85, 26, 1, // Skip to: 86948 +/* 14671 */ MCD_OPC_Decode, 191, 33, 104, // Opcode: UQSUB_ZI_H +/* 14675 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 14696 +/* 14680 */ MCD_OPC_CheckPredicate, 0, 71, 26, 1, // Skip to: 86948 +/* 14685 */ MCD_OPC_CheckField, 13, 1, 0, 64, 26, 1, // Skip to: 86948 +/* 14692 */ MCD_OPC_Decode, 194, 23, 99, // Opcode: SMAX_ZI_H +/* 14696 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 14717 +/* 14701 */ MCD_OPC_CheckPredicate, 0, 50, 26, 1, // Skip to: 86948 +/* 14706 */ MCD_OPC_CheckField, 13, 1, 0, 43, 26, 1, // Skip to: 86948 +/* 14713 */ MCD_OPC_Decode, 250, 31, 100, // Opcode: UMAX_ZI_H +/* 14717 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 14738 +/* 14722 */ MCD_OPC_CheckPredicate, 0, 29, 26, 1, // Skip to: 86948 +/* 14727 */ MCD_OPC_CheckField, 13, 1, 0, 22, 26, 1, // Skip to: 86948 +/* 14734 */ MCD_OPC_Decode, 224, 23, 99, // Opcode: SMIN_ZI_H +/* 14738 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 14759 +/* 14743 */ MCD_OPC_CheckPredicate, 0, 8, 26, 1, // Skip to: 86948 +/* 14748 */ MCD_OPC_CheckField, 13, 1, 0, 1, 26, 1, // Skip to: 86948 +/* 14755 */ MCD_OPC_Decode, 151, 32, 100, // Opcode: UMIN_ZI_H +/* 14759 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 14780 +/* 14764 */ MCD_OPC_CheckPredicate, 0, 243, 25, 1, // Skip to: 86948 +/* 14769 */ MCD_OPC_CheckField, 13, 1, 0, 236, 25, 1, // Skip to: 86948 +/* 14776 */ MCD_OPC_Decode, 151, 20, 99, // Opcode: MUL_ZI_H +/* 14780 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 14794 +/* 14785 */ MCD_OPC_CheckPredicate, 0, 222, 25, 1, // Skip to: 86948 +/* 14790 */ MCD_OPC_Decode, 197, 5, 105, // Opcode: DUP_ZI_H +/* 14794 */ MCD_OPC_FilterValue, 25, 213, 25, 1, // Skip to: 86948 +/* 14799 */ MCD_OPC_CheckPredicate, 0, 208, 25, 1, // Skip to: 86948 +/* 14804 */ MCD_OPC_CheckField, 13, 1, 0, 201, 25, 1, // Skip to: 86948 +/* 14811 */ MCD_OPC_Decode, 181, 9, 106, // Opcode: FDUP_ZI_H +/* 14815 */ MCD_OPC_FilterValue, 12, 122, 1, 0, // Skip to: 15198 +/* 14820 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 14823 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 14903 +/* 14828 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 14831 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 14867 +/* 14836 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 14839 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14853 +/* 14844 */ MCD_OPC_CheckPredicate, 0, 163, 25, 1, // Skip to: 86948 +/* 14849 */ MCD_OPC_Decode, 148, 4, 83, // Opcode: CMPGE_PPzZI_S +/* 14853 */ MCD_OPC_FilterValue, 1, 154, 25, 1, // Skip to: 86948 +/* 14858 */ MCD_OPC_CheckPredicate, 0, 149, 25, 1, // Skip to: 86948 +/* 14863 */ MCD_OPC_Decode, 213, 4, 83, // Opcode: CMPLT_PPzZI_S +/* 14867 */ MCD_OPC_FilterValue, 1, 140, 25, 1, // Skip to: 86948 +/* 14872 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 14875 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14889 +/* 14880 */ MCD_OPC_CheckPredicate, 0, 127, 25, 1, // Skip to: 86948 +/* 14885 */ MCD_OPC_Decode, 159, 4, 83, // Opcode: CMPGT_PPzZI_S +/* 14889 */ MCD_OPC_FilterValue, 1, 118, 25, 1, // Skip to: 86948 +/* 14894 */ MCD_OPC_CheckPredicate, 0, 113, 25, 1, // Skip to: 86948 +/* 14899 */ MCD_OPC_Decode, 192, 4, 83, // Opcode: CMPLE_PPzZI_S +/* 14903 */ MCD_OPC_FilterValue, 1, 147, 0, 0, // Skip to: 15055 +/* 14908 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 14911 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 14983 +/* 14916 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 14919 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 14962 +/* 14924 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 14927 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 14941 +/* 14932 */ MCD_OPC_CheckPredicate, 0, 75, 25, 1, // Skip to: 86948 +/* 14937 */ MCD_OPC_Decode, 210, 20, 84, // Opcode: ORR_PPzPP +/* 14941 */ MCD_OPC_FilterValue, 1, 66, 25, 1, // Skip to: 86948 +/* 14946 */ MCD_OPC_CheckPredicate, 0, 61, 25, 1, // Skip to: 86948 +/* 14951 */ MCD_OPC_CheckField, 16, 4, 0, 54, 25, 1, // Skip to: 86948 +/* 14958 */ MCD_OPC_Decode, 214, 2, 85, // Opcode: BRKB_PPzP +/* 14962 */ MCD_OPC_FilterValue, 1, 45, 25, 1, // Skip to: 86948 +/* 14967 */ MCD_OPC_CheckPredicate, 0, 40, 25, 1, // Skip to: 86948 +/* 14972 */ MCD_OPC_CheckField, 20, 1, 0, 33, 25, 1, // Skip to: 86948 +/* 14979 */ MCD_OPC_Decode, 188, 20, 84, // Opcode: NOR_PPzPP +/* 14983 */ MCD_OPC_FilterValue, 1, 24, 25, 1, // Skip to: 86948 +/* 14988 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 14991 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 15034 +/* 14996 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 14999 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15013 +/* 15004 */ MCD_OPC_CheckPredicate, 0, 3, 25, 1, // Skip to: 86948 +/* 15009 */ MCD_OPC_Decode, 200, 20, 84, // Opcode: ORN_PPzPP +/* 15013 */ MCD_OPC_FilterValue, 1, 250, 24, 1, // Skip to: 86948 +/* 15018 */ MCD_OPC_CheckPredicate, 0, 245, 24, 1, // Skip to: 86948 +/* 15023 */ MCD_OPC_CheckField, 16, 4, 0, 238, 24, 1, // Skip to: 86948 +/* 15030 */ MCD_OPC_Decode, 213, 2, 87, // Opcode: BRKB_PPmP +/* 15034 */ MCD_OPC_FilterValue, 1, 229, 24, 1, // Skip to: 86948 +/* 15039 */ MCD_OPC_CheckPredicate, 0, 224, 24, 1, // Skip to: 86948 +/* 15044 */ MCD_OPC_CheckField, 20, 1, 0, 217, 24, 1, // Skip to: 86948 +/* 15051 */ MCD_OPC_Decode, 174, 20, 84, // Opcode: NAND_PPzPP +/* 15055 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 15105 +/* 15060 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 15063 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 15084 +/* 15068 */ MCD_OPC_CheckPredicate, 0, 195, 24, 1, // Skip to: 86948 +/* 15073 */ MCD_OPC_CheckField, 13, 1, 0, 188, 24, 1, // Skip to: 86948 +/* 15080 */ MCD_OPC_Decode, 137, 4, 83, // Opcode: CMPEQ_PPzZI_S +/* 15084 */ MCD_OPC_FilterValue, 1, 179, 24, 1, // Skip to: 86948 +/* 15089 */ MCD_OPC_CheckPredicate, 0, 174, 24, 1, // Skip to: 86948 +/* 15094 */ MCD_OPC_CheckField, 13, 1, 0, 167, 24, 1, // Skip to: 86948 +/* 15101 */ MCD_OPC_Decode, 220, 4, 83, // Opcode: CMPNE_PPzZI_S +/* 15105 */ MCD_OPC_FilterValue, 3, 158, 24, 1, // Skip to: 86948 +/* 15110 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 15113 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 15148 +/* 15118 */ MCD_OPC_CheckPredicate, 0, 145, 24, 1, // Skip to: 86948 +/* 15123 */ MCD_OPC_CheckField, 16, 5, 25, 138, 24, 1, // Skip to: 86948 +/* 15130 */ MCD_OPC_CheckField, 9, 1, 0, 131, 24, 1, // Skip to: 86948 +/* 15137 */ MCD_OPC_CheckField, 4, 1, 0, 124, 24, 1, // Skip to: 86948 +/* 15144 */ MCD_OPC_Decode, 252, 20, 88, // Opcode: PNEXT_S +/* 15148 */ MCD_OPC_FilterValue, 8, 115, 24, 1, // Skip to: 86948 +/* 15153 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15156 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 15177 +/* 15161 */ MCD_OPC_CheckPredicate, 0, 102, 24, 1, // Skip to: 86948 +/* 15166 */ MCD_OPC_CheckField, 4, 1, 0, 95, 24, 1, // Skip to: 86948 +/* 15173 */ MCD_OPC_Decode, 174, 21, 89, // Opcode: PTRUE_S +/* 15177 */ MCD_OPC_FilterValue, 25, 86, 24, 1, // Skip to: 86948 +/* 15182 */ MCD_OPC_CheckPredicate, 0, 81, 24, 1, // Skip to: 86948 +/* 15187 */ MCD_OPC_CheckField, 4, 1, 0, 74, 24, 1, // Skip to: 86948 +/* 15194 */ MCD_OPC_Decode, 170, 21, 89, // Opcode: PTRUES_S +/* 15198 */ MCD_OPC_FilterValue, 13, 226, 2, 0, // Skip to: 15941 +/* 15203 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 15206 */ MCD_OPC_FilterValue, 0, 183, 0, 0, // Skip to: 15394 +/* 15211 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 15214 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 15250 +/* 15219 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 15222 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15236 +/* 15227 */ MCD_OPC_CheckPredicate, 0, 36, 24, 1, // Skip to: 86948 +/* 15232 */ MCD_OPC_Decode, 245, 34, 91, // Opcode: WHILELT_PWW_S +/* 15236 */ MCD_OPC_FilterValue, 1, 27, 24, 1, // Skip to: 86948 +/* 15241 */ MCD_OPC_CheckPredicate, 0, 22, 24, 1, // Skip to: 86948 +/* 15246 */ MCD_OPC_Decode, 221, 34, 91, // Opcode: WHILELE_PWW_S +/* 15250 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 15286 +/* 15255 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 15258 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15272 +/* 15263 */ MCD_OPC_CheckPredicate, 0, 0, 24, 1, // Skip to: 86948 +/* 15268 */ MCD_OPC_Decode, 229, 34, 91, // Opcode: WHILELO_PWW_S +/* 15272 */ MCD_OPC_FilterValue, 1, 247, 23, 1, // Skip to: 86948 +/* 15277 */ MCD_OPC_CheckPredicate, 0, 242, 23, 1, // Skip to: 86948 +/* 15282 */ MCD_OPC_Decode, 237, 34, 91, // Opcode: WHILELS_PWW_S +/* 15286 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 15322 +/* 15291 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 15294 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15308 +/* 15299 */ MCD_OPC_CheckPredicate, 0, 220, 23, 1, // Skip to: 86948 +/* 15304 */ MCD_OPC_Decode, 249, 34, 92, // Opcode: WHILELT_PXX_S +/* 15308 */ MCD_OPC_FilterValue, 1, 211, 23, 1, // Skip to: 86948 +/* 15313 */ MCD_OPC_CheckPredicate, 0, 206, 23, 1, // Skip to: 86948 +/* 15318 */ MCD_OPC_Decode, 225, 34, 92, // Opcode: WHILELE_PXX_S +/* 15322 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 15358 +/* 15327 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 15330 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15344 +/* 15335 */ MCD_OPC_CheckPredicate, 0, 184, 23, 1, // Skip to: 86948 +/* 15340 */ MCD_OPC_Decode, 233, 34, 92, // Opcode: WHILELO_PXX_S +/* 15344 */ MCD_OPC_FilterValue, 1, 175, 23, 1, // Skip to: 86948 +/* 15349 */ MCD_OPC_CheckPredicate, 0, 170, 23, 1, // Skip to: 86948 +/* 15354 */ MCD_OPC_Decode, 241, 34, 92, // Opcode: WHILELS_PXX_S +/* 15358 */ MCD_OPC_FilterValue, 8, 161, 23, 1, // Skip to: 86948 +/* 15363 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 15366 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15380 +/* 15371 */ MCD_OPC_CheckPredicate, 0, 148, 23, 1, // Skip to: 86948 +/* 15376 */ MCD_OPC_Decode, 169, 5, 107, // Opcode: CTERMEQ_WW +/* 15380 */ MCD_OPC_FilterValue, 16, 139, 23, 1, // Skip to: 86948 +/* 15385 */ MCD_OPC_CheckPredicate, 0, 134, 23, 1, // Skip to: 86948 +/* 15390 */ MCD_OPC_Decode, 171, 5, 107, // Opcode: CTERMNE_WW +/* 15394 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 15695 +/* 15399 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15402 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 15423 +/* 15407 */ MCD_OPC_CheckPredicate, 0, 112, 23, 1, // Skip to: 86948 +/* 15412 */ MCD_OPC_CheckField, 9, 1, 0, 105, 23, 1, // Skip to: 86948 +/* 15419 */ MCD_OPC_Decode, 251, 4, 93, // Opcode: CNTP_XPP_S +/* 15423 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 15473 +/* 15428 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 15431 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15445 +/* 15436 */ MCD_OPC_CheckPredicate, 0, 83, 23, 1, // Skip to: 86948 +/* 15441 */ MCD_OPC_Decode, 143, 25, 103, // Opcode: SQINCP_ZP_S +/* 15445 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15459 +/* 15450 */ MCD_OPC_CheckPredicate, 0, 69, 23, 1, // Skip to: 86948 +/* 15455 */ MCD_OPC_Decode, 136, 25, 94, // Opcode: SQINCP_XPWd_S +/* 15459 */ MCD_OPC_FilterValue, 6, 60, 23, 1, // Skip to: 86948 +/* 15464 */ MCD_OPC_CheckPredicate, 0, 55, 23, 1, // Skip to: 86948 +/* 15469 */ MCD_OPC_Decode, 140, 25, 94, // Opcode: SQINCP_XP_S +/* 15473 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 15523 +/* 15478 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 15481 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15495 +/* 15486 */ MCD_OPC_CheckPredicate, 0, 33, 23, 1, // Skip to: 86948 +/* 15491 */ MCD_OPC_Decode, 134, 33, 103, // Opcode: UQINCP_ZP_S +/* 15495 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15509 +/* 15500 */ MCD_OPC_CheckPredicate, 0, 19, 23, 1, // Skip to: 86948 +/* 15505 */ MCD_OPC_Decode, 255, 32, 96, // Opcode: UQINCP_WP_S +/* 15509 */ MCD_OPC_FilterValue, 6, 10, 23, 1, // Skip to: 86948 +/* 15514 */ MCD_OPC_CheckPredicate, 0, 5, 23, 1, // Skip to: 86948 +/* 15519 */ MCD_OPC_Decode, 131, 33, 94, // Opcode: UQINCP_XP_S +/* 15523 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 15573 +/* 15528 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 15531 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15545 +/* 15536 */ MCD_OPC_CheckPredicate, 0, 239, 22, 1, // Skip to: 86948 +/* 15541 */ MCD_OPC_Decode, 201, 24, 103, // Opcode: SQDECP_ZP_S +/* 15545 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15559 +/* 15550 */ MCD_OPC_CheckPredicate, 0, 225, 22, 1, // Skip to: 86948 +/* 15555 */ MCD_OPC_Decode, 194, 24, 94, // Opcode: SQDECP_XPWd_S +/* 15559 */ MCD_OPC_FilterValue, 6, 216, 22, 1, // Skip to: 86948 +/* 15564 */ MCD_OPC_CheckPredicate, 0, 211, 22, 1, // Skip to: 86948 +/* 15569 */ MCD_OPC_Decode, 198, 24, 94, // Opcode: SQDECP_XP_S +/* 15573 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 15623 +/* 15578 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 15581 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15595 +/* 15586 */ MCD_OPC_CheckPredicate, 0, 189, 22, 1, // Skip to: 86948 +/* 15591 */ MCD_OPC_Decode, 240, 32, 103, // Opcode: UQDECP_ZP_S +/* 15595 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15609 +/* 15600 */ MCD_OPC_CheckPredicate, 0, 175, 22, 1, // Skip to: 86948 +/* 15605 */ MCD_OPC_Decode, 233, 32, 96, // Opcode: UQDECP_WP_S +/* 15609 */ MCD_OPC_FilterValue, 6, 166, 22, 1, // Skip to: 86948 +/* 15614 */ MCD_OPC_CheckPredicate, 0, 161, 22, 1, // Skip to: 86948 +/* 15619 */ MCD_OPC_Decode, 237, 32, 94, // Opcode: UQDECP_XP_S +/* 15623 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 15659 +/* 15628 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 15631 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15645 +/* 15636 */ MCD_OPC_CheckPredicate, 0, 139, 22, 1, // Skip to: 86948 +/* 15641 */ MCD_OPC_Decode, 255, 13, 103, // Opcode: INCP_ZP_S +/* 15645 */ MCD_OPC_FilterValue, 4, 130, 22, 1, // Skip to: 86948 +/* 15650 */ MCD_OPC_CheckPredicate, 0, 125, 22, 1, // Skip to: 86948 +/* 15655 */ MCD_OPC_Decode, 252, 13, 94, // Opcode: INCP_XP_S +/* 15659 */ MCD_OPC_FilterValue, 13, 116, 22, 1, // Skip to: 86948 +/* 15664 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 15667 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15681 +/* 15672 */ MCD_OPC_CheckPredicate, 0, 103, 22, 1, // Skip to: 86948 +/* 15677 */ MCD_OPC_Decode, 188, 5, 103, // Opcode: DECP_ZP_S +/* 15681 */ MCD_OPC_FilterValue, 4, 94, 22, 1, // Skip to: 86948 +/* 15686 */ MCD_OPC_CheckPredicate, 0, 89, 22, 1, // Skip to: 86948 +/* 15691 */ MCD_OPC_Decode, 185, 5, 94, // Opcode: DECP_XP_S +/* 15695 */ MCD_OPC_FilterValue, 3, 80, 22, 1, // Skip to: 86948 +/* 15700 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 15703 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15717 +/* 15708 */ MCD_OPC_CheckPredicate, 0, 67, 22, 1, // Skip to: 86948 +/* 15713 */ MCD_OPC_Decode, 184, 1, 108, // Opcode: ADD_ZI_S +/* 15717 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 15731 +/* 15722 */ MCD_OPC_CheckPredicate, 0, 53, 22, 1, // Skip to: 86948 +/* 15727 */ MCD_OPC_Decode, 246, 29, 108, // Opcode: SUB_ZI_S +/* 15731 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 15745 +/* 15736 */ MCD_OPC_CheckPredicate, 0, 39, 22, 1, // Skip to: 86948 +/* 15741 */ MCD_OPC_Decode, 220, 29, 108, // Opcode: SUBR_ZI_S +/* 15745 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 15759 +/* 15750 */ MCD_OPC_CheckPredicate, 0, 25, 22, 1, // Skip to: 86948 +/* 15755 */ MCD_OPC_Decode, 167, 24, 108, // Opcode: SQADD_ZI_S +/* 15759 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 15773 +/* 15764 */ MCD_OPC_CheckPredicate, 0, 11, 22, 1, // Skip to: 86948 +/* 15769 */ MCD_OPC_Decode, 206, 32, 108, // Opcode: UQADD_ZI_S +/* 15773 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 15787 +/* 15778 */ MCD_OPC_CheckPredicate, 0, 253, 21, 1, // Skip to: 86948 +/* 15783 */ MCD_OPC_Decode, 149, 26, 108, // Opcode: SQSUB_ZI_S +/* 15787 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 15801 +/* 15792 */ MCD_OPC_CheckPredicate, 0, 239, 21, 1, // Skip to: 86948 +/* 15797 */ MCD_OPC_Decode, 192, 33, 108, // Opcode: UQSUB_ZI_S +/* 15801 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 15822 +/* 15806 */ MCD_OPC_CheckPredicate, 0, 225, 21, 1, // Skip to: 86948 +/* 15811 */ MCD_OPC_CheckField, 13, 1, 0, 218, 21, 1, // Skip to: 86948 +/* 15818 */ MCD_OPC_Decode, 195, 23, 99, // Opcode: SMAX_ZI_S +/* 15822 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 15843 +/* 15827 */ MCD_OPC_CheckPredicate, 0, 204, 21, 1, // Skip to: 86948 +/* 15832 */ MCD_OPC_CheckField, 13, 1, 0, 197, 21, 1, // Skip to: 86948 +/* 15839 */ MCD_OPC_Decode, 251, 31, 100, // Opcode: UMAX_ZI_S +/* 15843 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 15864 +/* 15848 */ MCD_OPC_CheckPredicate, 0, 183, 21, 1, // Skip to: 86948 +/* 15853 */ MCD_OPC_CheckField, 13, 1, 0, 176, 21, 1, // Skip to: 86948 +/* 15860 */ MCD_OPC_Decode, 225, 23, 99, // Opcode: SMIN_ZI_S +/* 15864 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 15885 +/* 15869 */ MCD_OPC_CheckPredicate, 0, 162, 21, 1, // Skip to: 86948 +/* 15874 */ MCD_OPC_CheckField, 13, 1, 0, 155, 21, 1, // Skip to: 86948 +/* 15881 */ MCD_OPC_Decode, 152, 32, 100, // Opcode: UMIN_ZI_S +/* 15885 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 15906 +/* 15890 */ MCD_OPC_CheckPredicate, 0, 141, 21, 1, // Skip to: 86948 +/* 15895 */ MCD_OPC_CheckField, 13, 1, 0, 134, 21, 1, // Skip to: 86948 +/* 15902 */ MCD_OPC_Decode, 152, 20, 99, // Opcode: MUL_ZI_S +/* 15906 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 15920 +/* 15911 */ MCD_OPC_CheckPredicate, 0, 120, 21, 1, // Skip to: 86948 +/* 15916 */ MCD_OPC_Decode, 198, 5, 109, // Opcode: DUP_ZI_S +/* 15920 */ MCD_OPC_FilterValue, 25, 111, 21, 1, // Skip to: 86948 +/* 15925 */ MCD_OPC_CheckPredicate, 0, 106, 21, 1, // Skip to: 86948 +/* 15930 */ MCD_OPC_CheckField, 13, 1, 0, 99, 21, 1, // Skip to: 86948 +/* 15937 */ MCD_OPC_Decode, 182, 9, 106, // Opcode: FDUP_ZI_S +/* 15941 */ MCD_OPC_FilterValue, 14, 100, 1, 0, // Skip to: 16302 +/* 15946 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 15949 */ MCD_OPC_FilterValue, 0, 75, 0, 0, // Skip to: 16029 +/* 15954 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 15957 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 15993 +/* 15962 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 15965 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 15979 +/* 15970 */ MCD_OPC_CheckPredicate, 0, 61, 21, 1, // Skip to: 86948 +/* 15975 */ MCD_OPC_Decode, 146, 4, 83, // Opcode: CMPGE_PPzZI_D +/* 15979 */ MCD_OPC_FilterValue, 1, 52, 21, 1, // Skip to: 86948 +/* 15984 */ MCD_OPC_CheckPredicate, 0, 47, 21, 1, // Skip to: 86948 +/* 15989 */ MCD_OPC_Decode, 211, 4, 83, // Opcode: CMPLT_PPzZI_D +/* 15993 */ MCD_OPC_FilterValue, 1, 38, 21, 1, // Skip to: 86948 +/* 15998 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 16001 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16015 +/* 16006 */ MCD_OPC_CheckPredicate, 0, 25, 21, 1, // Skip to: 86948 +/* 16011 */ MCD_OPC_Decode, 157, 4, 83, // Opcode: CMPGT_PPzZI_D +/* 16015 */ MCD_OPC_FilterValue, 1, 16, 21, 1, // Skip to: 86948 +/* 16020 */ MCD_OPC_CheckPredicate, 0, 11, 21, 1, // Skip to: 86948 +/* 16025 */ MCD_OPC_Decode, 190, 4, 83, // Opcode: CMPLE_PPzZI_D +/* 16029 */ MCD_OPC_FilterValue, 1, 125, 0, 0, // Skip to: 16159 +/* 16034 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 16037 */ MCD_OPC_FilterValue, 0, 67, 0, 0, // Skip to: 16109 +/* 16042 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 16045 */ MCD_OPC_FilterValue, 0, 38, 0, 0, // Skip to: 16088 +/* 16050 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 16053 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16067 +/* 16058 */ MCD_OPC_CheckPredicate, 0, 229, 20, 1, // Skip to: 86948 +/* 16063 */ MCD_OPC_Decode, 203, 20, 84, // Opcode: ORRS_PPzPP +/* 16067 */ MCD_OPC_FilterValue, 1, 220, 20, 1, // Skip to: 86948 +/* 16072 */ MCD_OPC_CheckPredicate, 0, 215, 20, 1, // Skip to: 86948 +/* 16077 */ MCD_OPC_CheckField, 16, 4, 0, 208, 20, 1, // Skip to: 86948 +/* 16084 */ MCD_OPC_Decode, 212, 2, 85, // Opcode: BRKBS_PPzP +/* 16088 */ MCD_OPC_FilterValue, 1, 199, 20, 1, // Skip to: 86948 +/* 16093 */ MCD_OPC_CheckPredicate, 0, 194, 20, 1, // Skip to: 86948 +/* 16098 */ MCD_OPC_CheckField, 20, 1, 0, 187, 20, 1, // Skip to: 86948 +/* 16105 */ MCD_OPC_Decode, 187, 20, 84, // Opcode: NORS_PPzPP +/* 16109 */ MCD_OPC_FilterValue, 1, 178, 20, 1, // Skip to: 86948 +/* 16114 */ MCD_OPC_ExtractField, 9, 1, // Inst{9} ... +/* 16117 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16138 +/* 16122 */ MCD_OPC_CheckPredicate, 0, 165, 20, 1, // Skip to: 86948 +/* 16127 */ MCD_OPC_CheckField, 20, 1, 0, 158, 20, 1, // Skip to: 86948 +/* 16134 */ MCD_OPC_Decode, 195, 20, 84, // Opcode: ORNS_PPzPP +/* 16138 */ MCD_OPC_FilterValue, 1, 149, 20, 1, // Skip to: 86948 +/* 16143 */ MCD_OPC_CheckPredicate, 0, 144, 20, 1, // Skip to: 86948 +/* 16148 */ MCD_OPC_CheckField, 20, 1, 0, 137, 20, 1, // Skip to: 86948 +/* 16155 */ MCD_OPC_Decode, 173, 20, 84, // Opcode: NANDS_PPzPP +/* 16159 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 16209 +/* 16164 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 16167 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16188 +/* 16172 */ MCD_OPC_CheckPredicate, 0, 115, 20, 1, // Skip to: 86948 +/* 16177 */ MCD_OPC_CheckField, 13, 1, 0, 108, 20, 1, // Skip to: 86948 +/* 16184 */ MCD_OPC_Decode, 135, 4, 83, // Opcode: CMPEQ_PPzZI_D +/* 16188 */ MCD_OPC_FilterValue, 1, 99, 20, 1, // Skip to: 86948 +/* 16193 */ MCD_OPC_CheckPredicate, 0, 94, 20, 1, // Skip to: 86948 +/* 16198 */ MCD_OPC_CheckField, 13, 1, 0, 87, 20, 1, // Skip to: 86948 +/* 16205 */ MCD_OPC_Decode, 218, 4, 83, // Opcode: CMPNE_PPzZI_D +/* 16209 */ MCD_OPC_FilterValue, 3, 78, 20, 1, // Skip to: 86948 +/* 16214 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 16217 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 16252 +/* 16222 */ MCD_OPC_CheckPredicate, 0, 65, 20, 1, // Skip to: 86948 +/* 16227 */ MCD_OPC_CheckField, 16, 5, 25, 58, 20, 1, // Skip to: 86948 +/* 16234 */ MCD_OPC_CheckField, 9, 1, 0, 51, 20, 1, // Skip to: 86948 +/* 16241 */ MCD_OPC_CheckField, 4, 1, 0, 44, 20, 1, // Skip to: 86948 +/* 16248 */ MCD_OPC_Decode, 250, 20, 88, // Opcode: PNEXT_D +/* 16252 */ MCD_OPC_FilterValue, 8, 35, 20, 1, // Skip to: 86948 +/* 16257 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 16260 */ MCD_OPC_FilterValue, 24, 16, 0, 0, // Skip to: 16281 +/* 16265 */ MCD_OPC_CheckPredicate, 0, 22, 20, 1, // Skip to: 86948 +/* 16270 */ MCD_OPC_CheckField, 4, 1, 0, 15, 20, 1, // Skip to: 86948 +/* 16277 */ MCD_OPC_Decode, 172, 21, 89, // Opcode: PTRUE_D +/* 16281 */ MCD_OPC_FilterValue, 25, 6, 20, 1, // Skip to: 86948 +/* 16286 */ MCD_OPC_CheckPredicate, 0, 1, 20, 1, // Skip to: 86948 +/* 16291 */ MCD_OPC_CheckField, 4, 1, 0, 250, 19, 1, // Skip to: 86948 +/* 16298 */ MCD_OPC_Decode, 168, 21, 89, // Opcode: PTRUES_D +/* 16302 */ MCD_OPC_FilterValue, 15, 241, 19, 1, // Skip to: 86948 +/* 16307 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 16310 */ MCD_OPC_FilterValue, 0, 183, 0, 0, // Skip to: 16498 +/* 16315 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 16318 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 16354 +/* 16323 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 16326 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16340 +/* 16331 */ MCD_OPC_CheckPredicate, 0, 212, 19, 1, // Skip to: 86948 +/* 16336 */ MCD_OPC_Decode, 243, 34, 91, // Opcode: WHILELT_PWW_D +/* 16340 */ MCD_OPC_FilterValue, 1, 203, 19, 1, // Skip to: 86948 +/* 16345 */ MCD_OPC_CheckPredicate, 0, 198, 19, 1, // Skip to: 86948 +/* 16350 */ MCD_OPC_Decode, 219, 34, 91, // Opcode: WHILELE_PWW_D +/* 16354 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 16390 +/* 16359 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 16362 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16376 +/* 16367 */ MCD_OPC_CheckPredicate, 0, 176, 19, 1, // Skip to: 86948 +/* 16372 */ MCD_OPC_Decode, 227, 34, 91, // Opcode: WHILELO_PWW_D +/* 16376 */ MCD_OPC_FilterValue, 1, 167, 19, 1, // Skip to: 86948 +/* 16381 */ MCD_OPC_CheckPredicate, 0, 162, 19, 1, // Skip to: 86948 +/* 16386 */ MCD_OPC_Decode, 235, 34, 91, // Opcode: WHILELS_PWW_D +/* 16390 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 16426 +/* 16395 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 16398 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16412 +/* 16403 */ MCD_OPC_CheckPredicate, 0, 140, 19, 1, // Skip to: 86948 +/* 16408 */ MCD_OPC_Decode, 247, 34, 92, // Opcode: WHILELT_PXX_D +/* 16412 */ MCD_OPC_FilterValue, 1, 131, 19, 1, // Skip to: 86948 +/* 16417 */ MCD_OPC_CheckPredicate, 0, 126, 19, 1, // Skip to: 86948 +/* 16422 */ MCD_OPC_Decode, 223, 34, 92, // Opcode: WHILELE_PXX_D +/* 16426 */ MCD_OPC_FilterValue, 7, 31, 0, 0, // Skip to: 16462 +/* 16431 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 16434 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16448 +/* 16439 */ MCD_OPC_CheckPredicate, 0, 104, 19, 1, // Skip to: 86948 +/* 16444 */ MCD_OPC_Decode, 231, 34, 92, // Opcode: WHILELO_PXX_D +/* 16448 */ MCD_OPC_FilterValue, 1, 95, 19, 1, // Skip to: 86948 +/* 16453 */ MCD_OPC_CheckPredicate, 0, 90, 19, 1, // Skip to: 86948 +/* 16458 */ MCD_OPC_Decode, 239, 34, 92, // Opcode: WHILELS_PXX_D +/* 16462 */ MCD_OPC_FilterValue, 8, 81, 19, 1, // Skip to: 86948 +/* 16467 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 16470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16484 +/* 16475 */ MCD_OPC_CheckPredicate, 0, 68, 19, 1, // Skip to: 86948 +/* 16480 */ MCD_OPC_Decode, 170, 5, 110, // Opcode: CTERMEQ_XX +/* 16484 */ MCD_OPC_FilterValue, 16, 59, 19, 1, // Skip to: 86948 +/* 16489 */ MCD_OPC_CheckPredicate, 0, 54, 19, 1, // Skip to: 86948 +/* 16494 */ MCD_OPC_Decode, 172, 5, 110, // Opcode: CTERMNE_XX +/* 16498 */ MCD_OPC_FilterValue, 2, 40, 1, 0, // Skip to: 16799 +/* 16503 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 16506 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 16527 +/* 16511 */ MCD_OPC_CheckPredicate, 0, 32, 19, 1, // Skip to: 86948 +/* 16516 */ MCD_OPC_CheckField, 9, 1, 0, 25, 19, 1, // Skip to: 86948 +/* 16523 */ MCD_OPC_Decode, 249, 4, 93, // Opcode: CNTP_XPP_D +/* 16527 */ MCD_OPC_FilterValue, 8, 45, 0, 0, // Skip to: 16577 +/* 16532 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 16535 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16549 +/* 16540 */ MCD_OPC_CheckPredicate, 0, 3, 19, 1, // Skip to: 86948 +/* 16545 */ MCD_OPC_Decode, 141, 25, 103, // Opcode: SQINCP_ZP_D +/* 16549 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16563 +/* 16554 */ MCD_OPC_CheckPredicate, 0, 245, 18, 1, // Skip to: 86948 +/* 16559 */ MCD_OPC_Decode, 134, 25, 94, // Opcode: SQINCP_XPWd_D +/* 16563 */ MCD_OPC_FilterValue, 6, 236, 18, 1, // Skip to: 86948 +/* 16568 */ MCD_OPC_CheckPredicate, 0, 231, 18, 1, // Skip to: 86948 +/* 16573 */ MCD_OPC_Decode, 138, 25, 94, // Opcode: SQINCP_XP_D +/* 16577 */ MCD_OPC_FilterValue, 9, 45, 0, 0, // Skip to: 16627 +/* 16582 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 16585 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16599 +/* 16590 */ MCD_OPC_CheckPredicate, 0, 209, 18, 1, // Skip to: 86948 +/* 16595 */ MCD_OPC_Decode, 132, 33, 103, // Opcode: UQINCP_ZP_D +/* 16599 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16613 +/* 16604 */ MCD_OPC_CheckPredicate, 0, 195, 18, 1, // Skip to: 86948 +/* 16609 */ MCD_OPC_Decode, 253, 32, 96, // Opcode: UQINCP_WP_D +/* 16613 */ MCD_OPC_FilterValue, 6, 186, 18, 1, // Skip to: 86948 +/* 16618 */ MCD_OPC_CheckPredicate, 0, 181, 18, 1, // Skip to: 86948 +/* 16623 */ MCD_OPC_Decode, 129, 33, 94, // Opcode: UQINCP_XP_D +/* 16627 */ MCD_OPC_FilterValue, 10, 45, 0, 0, // Skip to: 16677 +/* 16632 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 16635 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16649 +/* 16640 */ MCD_OPC_CheckPredicate, 0, 159, 18, 1, // Skip to: 86948 +/* 16645 */ MCD_OPC_Decode, 199, 24, 103, // Opcode: SQDECP_ZP_D +/* 16649 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16663 +/* 16654 */ MCD_OPC_CheckPredicate, 0, 145, 18, 1, // Skip to: 86948 +/* 16659 */ MCD_OPC_Decode, 192, 24, 94, // Opcode: SQDECP_XPWd_D +/* 16663 */ MCD_OPC_FilterValue, 6, 136, 18, 1, // Skip to: 86948 +/* 16668 */ MCD_OPC_CheckPredicate, 0, 131, 18, 1, // Skip to: 86948 +/* 16673 */ MCD_OPC_Decode, 196, 24, 94, // Opcode: SQDECP_XP_D +/* 16677 */ MCD_OPC_FilterValue, 11, 45, 0, 0, // Skip to: 16727 +/* 16682 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 16685 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16699 +/* 16690 */ MCD_OPC_CheckPredicate, 0, 109, 18, 1, // Skip to: 86948 +/* 16695 */ MCD_OPC_Decode, 238, 32, 103, // Opcode: UQDECP_ZP_D +/* 16699 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16713 +/* 16704 */ MCD_OPC_CheckPredicate, 0, 95, 18, 1, // Skip to: 86948 +/* 16709 */ MCD_OPC_Decode, 231, 32, 96, // Opcode: UQDECP_WP_D +/* 16713 */ MCD_OPC_FilterValue, 6, 86, 18, 1, // Skip to: 86948 +/* 16718 */ MCD_OPC_CheckPredicate, 0, 81, 18, 1, // Skip to: 86948 +/* 16723 */ MCD_OPC_Decode, 235, 32, 94, // Opcode: UQDECP_XP_D +/* 16727 */ MCD_OPC_FilterValue, 12, 31, 0, 0, // Skip to: 16763 +/* 16732 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 16735 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16749 +/* 16740 */ MCD_OPC_CheckPredicate, 0, 59, 18, 1, // Skip to: 86948 +/* 16745 */ MCD_OPC_Decode, 253, 13, 103, // Opcode: INCP_ZP_D +/* 16749 */ MCD_OPC_FilterValue, 4, 50, 18, 1, // Skip to: 86948 +/* 16754 */ MCD_OPC_CheckPredicate, 0, 45, 18, 1, // Skip to: 86948 +/* 16759 */ MCD_OPC_Decode, 250, 13, 94, // Opcode: INCP_XP_D +/* 16763 */ MCD_OPC_FilterValue, 13, 36, 18, 1, // Skip to: 86948 +/* 16768 */ MCD_OPC_ExtractField, 9, 5, // Inst{13-9} ... +/* 16771 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16785 +/* 16776 */ MCD_OPC_CheckPredicate, 0, 23, 18, 1, // Skip to: 86948 +/* 16781 */ MCD_OPC_Decode, 186, 5, 103, // Opcode: DECP_ZP_D +/* 16785 */ MCD_OPC_FilterValue, 4, 14, 18, 1, // Skip to: 86948 +/* 16790 */ MCD_OPC_CheckPredicate, 0, 9, 18, 1, // Skip to: 86948 +/* 16795 */ MCD_OPC_Decode, 183, 5, 94, // Opcode: DECP_XP_D +/* 16799 */ MCD_OPC_FilterValue, 3, 0, 18, 1, // Skip to: 86948 +/* 16804 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 16807 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 16821 +/* 16812 */ MCD_OPC_CheckPredicate, 0, 243, 17, 1, // Skip to: 86948 +/* 16817 */ MCD_OPC_Decode, 182, 1, 111, // Opcode: ADD_ZI_D +/* 16821 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 16835 +/* 16826 */ MCD_OPC_CheckPredicate, 0, 229, 17, 1, // Skip to: 86948 +/* 16831 */ MCD_OPC_Decode, 244, 29, 111, // Opcode: SUB_ZI_D +/* 16835 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 16849 +/* 16840 */ MCD_OPC_CheckPredicate, 0, 215, 17, 1, // Skip to: 86948 +/* 16845 */ MCD_OPC_Decode, 218, 29, 111, // Opcode: SUBR_ZI_D +/* 16849 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 16863 +/* 16854 */ MCD_OPC_CheckPredicate, 0, 201, 17, 1, // Skip to: 86948 +/* 16859 */ MCD_OPC_Decode, 165, 24, 111, // Opcode: SQADD_ZI_D +/* 16863 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 16877 +/* 16868 */ MCD_OPC_CheckPredicate, 0, 187, 17, 1, // Skip to: 86948 +/* 16873 */ MCD_OPC_Decode, 204, 32, 111, // Opcode: UQADD_ZI_D +/* 16877 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 16891 +/* 16882 */ MCD_OPC_CheckPredicate, 0, 173, 17, 1, // Skip to: 86948 +/* 16887 */ MCD_OPC_Decode, 147, 26, 111, // Opcode: SQSUB_ZI_D +/* 16891 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 16905 +/* 16896 */ MCD_OPC_CheckPredicate, 0, 159, 17, 1, // Skip to: 86948 +/* 16901 */ MCD_OPC_Decode, 190, 33, 111, // Opcode: UQSUB_ZI_D +/* 16905 */ MCD_OPC_FilterValue, 8, 16, 0, 0, // Skip to: 16926 +/* 16910 */ MCD_OPC_CheckPredicate, 0, 145, 17, 1, // Skip to: 86948 +/* 16915 */ MCD_OPC_CheckField, 13, 1, 0, 138, 17, 1, // Skip to: 86948 +/* 16922 */ MCD_OPC_Decode, 193, 23, 99, // Opcode: SMAX_ZI_D +/* 16926 */ MCD_OPC_FilterValue, 9, 16, 0, 0, // Skip to: 16947 +/* 16931 */ MCD_OPC_CheckPredicate, 0, 124, 17, 1, // Skip to: 86948 +/* 16936 */ MCD_OPC_CheckField, 13, 1, 0, 117, 17, 1, // Skip to: 86948 +/* 16943 */ MCD_OPC_Decode, 249, 31, 100, // Opcode: UMAX_ZI_D +/* 16947 */ MCD_OPC_FilterValue, 10, 16, 0, 0, // Skip to: 16968 +/* 16952 */ MCD_OPC_CheckPredicate, 0, 103, 17, 1, // Skip to: 86948 +/* 16957 */ MCD_OPC_CheckField, 13, 1, 0, 96, 17, 1, // Skip to: 86948 +/* 16964 */ MCD_OPC_Decode, 223, 23, 99, // Opcode: SMIN_ZI_D +/* 16968 */ MCD_OPC_FilterValue, 11, 16, 0, 0, // Skip to: 16989 +/* 16973 */ MCD_OPC_CheckPredicate, 0, 82, 17, 1, // Skip to: 86948 +/* 16978 */ MCD_OPC_CheckField, 13, 1, 0, 75, 17, 1, // Skip to: 86948 +/* 16985 */ MCD_OPC_Decode, 150, 32, 100, // Opcode: UMIN_ZI_D +/* 16989 */ MCD_OPC_FilterValue, 16, 16, 0, 0, // Skip to: 17010 +/* 16994 */ MCD_OPC_CheckPredicate, 0, 61, 17, 1, // Skip to: 86948 +/* 16999 */ MCD_OPC_CheckField, 13, 1, 0, 54, 17, 1, // Skip to: 86948 +/* 17006 */ MCD_OPC_Decode, 150, 20, 99, // Opcode: MUL_ZI_D +/* 17010 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 17024 +/* 17015 */ MCD_OPC_CheckPredicate, 0, 40, 17, 1, // Skip to: 86948 +/* 17020 */ MCD_OPC_Decode, 196, 5, 112, // Opcode: DUP_ZI_D +/* 17024 */ MCD_OPC_FilterValue, 25, 31, 17, 1, // Skip to: 86948 +/* 17029 */ MCD_OPC_CheckPredicate, 0, 26, 17, 1, // Skip to: 86948 +/* 17034 */ MCD_OPC_CheckField, 13, 1, 0, 19, 17, 1, // Skip to: 86948 +/* 17041 */ MCD_OPC_Decode, 180, 9, 106, // Opcode: FDUP_ZI_D +/* 17045 */ MCD_OPC_FilterValue, 2, 147, 0, 0, // Skip to: 17197 +/* 17050 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 17053 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 17089 +/* 17058 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 17061 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17075 +/* 17066 */ MCD_OPC_CheckPredicate, 0, 245, 16, 1, // Skip to: 86948 +/* 17071 */ MCD_OPC_Decode, 228, 22, 113, // Opcode: SDOT_ZZZ_S +/* 17075 */ MCD_OPC_FilterValue, 1, 236, 16, 1, // Skip to: 86948 +/* 17080 */ MCD_OPC_CheckPredicate, 0, 231, 16, 1, // Skip to: 86948 +/* 17085 */ MCD_OPC_Decode, 215, 31, 113, // Opcode: UDOT_ZZZ_S +/* 17089 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 17125 +/* 17094 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 17097 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17111 +/* 17102 */ MCD_OPC_CheckPredicate, 0, 209, 16, 1, // Skip to: 86948 +/* 17107 */ MCD_OPC_Decode, 226, 22, 114, // Opcode: SDOT_ZZZI_S +/* 17111 */ MCD_OPC_FilterValue, 1, 200, 16, 1, // Skip to: 86948 +/* 17116 */ MCD_OPC_CheckPredicate, 0, 195, 16, 1, // Skip to: 86948 +/* 17121 */ MCD_OPC_Decode, 213, 31, 114, // Opcode: UDOT_ZZZI_S +/* 17125 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 17161 +/* 17130 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 17133 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17147 +/* 17138 */ MCD_OPC_CheckPredicate, 0, 173, 16, 1, // Skip to: 86948 +/* 17143 */ MCD_OPC_Decode, 227, 22, 113, // Opcode: SDOT_ZZZ_D +/* 17147 */ MCD_OPC_FilterValue, 1, 164, 16, 1, // Skip to: 86948 +/* 17152 */ MCD_OPC_CheckPredicate, 0, 159, 16, 1, // Skip to: 86948 +/* 17157 */ MCD_OPC_Decode, 214, 31, 113, // Opcode: UDOT_ZZZ_D +/* 17161 */ MCD_OPC_FilterValue, 7, 150, 16, 1, // Skip to: 86948 +/* 17166 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 17169 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17183 +/* 17174 */ MCD_OPC_CheckPredicate, 0, 137, 16, 1, // Skip to: 86948 +/* 17179 */ MCD_OPC_Decode, 225, 22, 115, // Opcode: SDOT_ZZZI_D +/* 17183 */ MCD_OPC_FilterValue, 1, 128, 16, 1, // Skip to: 86948 +/* 17188 */ MCD_OPC_CheckPredicate, 0, 123, 16, 1, // Skip to: 86948 +/* 17193 */ MCD_OPC_Decode, 212, 31, 115, // Opcode: UDOT_ZZZI_D +/* 17197 */ MCD_OPC_FilterValue, 3, 6, 17, 0, // Skip to: 21560 +/* 17202 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 17205 */ MCD_OPC_FilterValue, 0, 110, 0, 0, // Skip to: 17320 +/* 17210 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 17213 */ MCD_OPC_FilterValue, 0, 74, 0, 0, // Skip to: 17292 +/* 17218 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 17221 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 17242 +/* 17226 */ MCD_OPC_CheckPredicate, 0, 85, 16, 1, // Skip to: 86948 +/* 17231 */ MCD_OPC_CheckField, 22, 1, 1, 78, 16, 1, // Skip to: 86948 +/* 17238 */ MCD_OPC_Decode, 156, 7, 116, // Opcode: FCMLA_ZPmZZ_H +/* 17242 */ MCD_OPC_FilterValue, 1, 69, 16, 1, // Skip to: 86948 +/* 17247 */ MCD_OPC_ExtractField, 10, 5, // Inst{14-10} ... +/* 17250 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17264 +/* 17255 */ MCD_OPC_CheckPredicate, 0, 56, 16, 1, // Skip to: 86948 +/* 17260 */ MCD_OPC_Decode, 181, 10, 117, // Opcode: FMLA_ZZZI_H +/* 17264 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17278 +/* 17269 */ MCD_OPC_CheckPredicate, 0, 42, 16, 1, // Skip to: 86948 +/* 17274 */ MCD_OPC_Decode, 200, 10, 117, // Opcode: FMLS_ZZZI_H +/* 17278 */ MCD_OPC_FilterValue, 8, 33, 16, 1, // Skip to: 86948 +/* 17283 */ MCD_OPC_CheckPredicate, 0, 28, 16, 1, // Skip to: 86948 +/* 17288 */ MCD_OPC_Decode, 146, 11, 118, // Opcode: FMUL_ZZZI_H +/* 17292 */ MCD_OPC_FilterValue, 1, 19, 16, 1, // Skip to: 86948 +/* 17297 */ MCD_OPC_CheckPredicate, 0, 14, 16, 1, // Skip to: 86948 +/* 17302 */ MCD_OPC_CheckField, 17, 6, 32, 7, 16, 1, // Skip to: 86948 +/* 17309 */ MCD_OPC_CheckField, 13, 2, 0, 0, 16, 1, // Skip to: 86948 +/* 17316 */ MCD_OPC_Decode, 204, 6, 119, // Opcode: FCADD_ZPmZ_H +/* 17320 */ MCD_OPC_FilterValue, 1, 5, 1, 0, // Skip to: 17586 +/* 17325 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 17328 */ MCD_OPC_FilterValue, 0, 45, 0, 0, // Skip to: 17378 +/* 17333 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 17336 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17350 +/* 17341 */ MCD_OPC_CheckPredicate, 0, 226, 15, 1, // Skip to: 86948 +/* 17346 */ MCD_OPC_Decode, 157, 7, 116, // Opcode: FCMLA_ZPmZZ_S +/* 17350 */ MCD_OPC_FilterValue, 1, 217, 15, 1, // Skip to: 86948 +/* 17355 */ MCD_OPC_CheckPredicate, 0, 212, 15, 1, // Skip to: 86948 +/* 17360 */ MCD_OPC_CheckField, 17, 4, 0, 205, 15, 1, // Skip to: 86948 +/* 17367 */ MCD_OPC_CheckField, 13, 2, 0, 198, 15, 1, // Skip to: 86948 +/* 17374 */ MCD_OPC_Decode, 205, 6, 119, // Opcode: FCADD_ZPmZ_S +/* 17378 */ MCD_OPC_FilterValue, 1, 74, 0, 0, // Skip to: 17457 +/* 17383 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17386 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 17422 +/* 17391 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 17394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17408 +/* 17399 */ MCD_OPC_CheckPredicate, 0, 168, 15, 1, // Skip to: 86948 +/* 17404 */ MCD_OPC_Decode, 182, 10, 114, // Opcode: FMLA_ZZZI_S +/* 17408 */ MCD_OPC_FilterValue, 1, 159, 15, 1, // Skip to: 86948 +/* 17413 */ MCD_OPC_CheckPredicate, 0, 154, 15, 1, // Skip to: 86948 +/* 17418 */ MCD_OPC_Decode, 201, 10, 114, // Opcode: FMLS_ZZZI_S +/* 17422 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17436 +/* 17427 */ MCD_OPC_CheckPredicate, 0, 140, 15, 1, // Skip to: 86948 +/* 17432 */ MCD_OPC_Decode, 158, 7, 120, // Opcode: FCMLA_ZZZI_H +/* 17436 */ MCD_OPC_FilterValue, 2, 131, 15, 1, // Skip to: 86948 +/* 17441 */ MCD_OPC_CheckPredicate, 0, 126, 15, 1, // Skip to: 86948 +/* 17446 */ MCD_OPC_CheckField, 10, 2, 0, 119, 15, 1, // Skip to: 86948 +/* 17453 */ MCD_OPC_Decode, 147, 11, 121, // Opcode: FMUL_ZZZI_S +/* 17457 */ MCD_OPC_FilterValue, 2, 45, 0, 0, // Skip to: 17507 +/* 17462 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 17465 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17479 +/* 17470 */ MCD_OPC_CheckPredicate, 0, 97, 15, 1, // Skip to: 86948 +/* 17475 */ MCD_OPC_Decode, 155, 7, 116, // Opcode: FCMLA_ZPmZZ_D +/* 17479 */ MCD_OPC_FilterValue, 1, 88, 15, 1, // Skip to: 86948 +/* 17484 */ MCD_OPC_CheckPredicate, 0, 83, 15, 1, // Skip to: 86948 +/* 17489 */ MCD_OPC_CheckField, 17, 4, 0, 76, 15, 1, // Skip to: 86948 +/* 17496 */ MCD_OPC_CheckField, 13, 2, 0, 69, 15, 1, // Skip to: 86948 +/* 17503 */ MCD_OPC_Decode, 203, 6, 119, // Opcode: FCADD_ZPmZ_D +/* 17507 */ MCD_OPC_FilterValue, 3, 60, 15, 1, // Skip to: 86948 +/* 17512 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 17515 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 17551 +/* 17520 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 17523 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17537 +/* 17528 */ MCD_OPC_CheckPredicate, 0, 39, 15, 1, // Skip to: 86948 +/* 17533 */ MCD_OPC_Decode, 180, 10, 115, // Opcode: FMLA_ZZZI_D +/* 17537 */ MCD_OPC_FilterValue, 1, 30, 15, 1, // Skip to: 86948 +/* 17542 */ MCD_OPC_CheckPredicate, 0, 25, 15, 1, // Skip to: 86948 +/* 17547 */ MCD_OPC_Decode, 199, 10, 115, // Opcode: FMLS_ZZZI_D +/* 17551 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17565 +/* 17556 */ MCD_OPC_CheckPredicate, 0, 11, 15, 1, // Skip to: 86948 +/* 17561 */ MCD_OPC_Decode, 159, 7, 122, // Opcode: FCMLA_ZZZI_S +/* 17565 */ MCD_OPC_FilterValue, 2, 2, 15, 1, // Skip to: 86948 +/* 17570 */ MCD_OPC_CheckPredicate, 0, 253, 14, 1, // Skip to: 86948 +/* 17575 */ MCD_OPC_CheckField, 10, 2, 0, 246, 14, 1, // Skip to: 86948 +/* 17582 */ MCD_OPC_Decode, 145, 11, 123, // Opcode: FMUL_ZZZI_D +/* 17586 */ MCD_OPC_FilterValue, 2, 73, 5, 0, // Skip to: 18944 +/* 17591 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 17594 */ MCD_OPC_FilterValue, 0, 109, 0, 0, // Skip to: 17708 +/* 17599 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 17602 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 17694 +/* 17607 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 17610 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17624 +/* 17615 */ MCD_OPC_CheckPredicate, 0, 208, 14, 1, // Skip to: 86948 +/* 17620 */ MCD_OPC_Decode, 196, 6, 27, // Opcode: FADD_ZZZ_H +/* 17624 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 17638 +/* 17629 */ MCD_OPC_CheckPredicate, 0, 194, 14, 1, // Skip to: 86948 +/* 17634 */ MCD_OPC_Decode, 225, 12, 27, // Opcode: FSUB_ZZZ_H +/* 17638 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 17652 +/* 17643 */ MCD_OPC_CheckPredicate, 0, 180, 14, 1, // Skip to: 86948 +/* 17648 */ MCD_OPC_Decode, 149, 11, 27, // Opcode: FMUL_ZZZ_H +/* 17652 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 17666 +/* 17657 */ MCD_OPC_CheckPredicate, 0, 166, 14, 1, // Skip to: 86948 +/* 17662 */ MCD_OPC_Decode, 236, 12, 27, // Opcode: FTSMUL_ZZZ_H +/* 17666 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 17680 +/* 17671 */ MCD_OPC_CheckPredicate, 0, 152, 14, 1, // Skip to: 86948 +/* 17676 */ MCD_OPC_Decode, 211, 11, 27, // Opcode: FRECPS_ZZZ_H +/* 17680 */ MCD_OPC_FilterValue, 7, 143, 14, 1, // Skip to: 86948 +/* 17685 */ MCD_OPC_CheckPredicate, 0, 138, 14, 1, // Skip to: 86948 +/* 17690 */ MCD_OPC_Decode, 188, 12, 27, // Opcode: FRSQRTS_ZZZ_H +/* 17694 */ MCD_OPC_FilterValue, 3, 129, 14, 1, // Skip to: 86948 +/* 17699 */ MCD_OPC_CheckPredicate, 0, 124, 14, 1, // Skip to: 86948 +/* 17704 */ MCD_OPC_Decode, 178, 10, 6, // Opcode: FMLA_ZPmZZ_H +/* 17708 */ MCD_OPC_FilterValue, 1, 9, 1, 0, // Skip to: 17978 +/* 17713 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 17716 */ MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 17964 +/* 17721 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 17724 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17738 +/* 17729 */ MCD_OPC_CheckPredicate, 0, 94, 14, 1, // Skip to: 86948 +/* 17734 */ MCD_OPC_Decode, 187, 6, 3, // Opcode: FADDV_VPZ_H +/* 17738 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 17752 +/* 17743 */ MCD_OPC_CheckPredicate, 0, 80, 14, 1, // Skip to: 86948 +/* 17748 */ MCD_OPC_Decode, 207, 9, 3, // Opcode: FMAXNMV_VPZ_H +/* 17752 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 17766 +/* 17757 */ MCD_OPC_CheckPredicate, 0, 66, 14, 1, // Skip to: 86948 +/* 17762 */ MCD_OPC_Decode, 135, 10, 3, // Opcode: FMINNMV_VPZ_H +/* 17766 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 17780 +/* 17771 */ MCD_OPC_CheckPredicate, 0, 52, 14, 1, // Skip to: 86948 +/* 17776 */ MCD_OPC_Decode, 233, 9, 3, // Opcode: FMAXV_VPZ_H +/* 17780 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 17794 +/* 17785 */ MCD_OPC_CheckPredicate, 0, 38, 14, 1, // Skip to: 86948 +/* 17790 */ MCD_OPC_Decode, 161, 10, 3, // Opcode: FMINV_VPZ_H +/* 17794 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 17815 +/* 17799 */ MCD_OPC_CheckPredicate, 0, 24, 14, 1, // Skip to: 86948 +/* 17804 */ MCD_OPC_CheckField, 10, 3, 4, 17, 14, 1, // Skip to: 86948 +/* 17811 */ MCD_OPC_Decode, 197, 11, 38, // Opcode: FRECPE_ZZ_H +/* 17815 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 17836 +/* 17820 */ MCD_OPC_CheckPredicate, 0, 3, 14, 1, // Skip to: 86948 +/* 17825 */ MCD_OPC_CheckField, 10, 3, 4, 252, 13, 1, // Skip to: 86948 +/* 17832 */ MCD_OPC_Decode, 174, 12, 38, // Opcode: FRSQRTE_ZZ_H +/* 17836 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 17872 +/* 17841 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 17844 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17858 +/* 17849 */ MCD_OPC_CheckPredicate, 0, 230, 13, 1, // Skip to: 86948 +/* 17854 */ MCD_OPC_Decode, 243, 6, 124, // Opcode: FCMGE_PPzZ0_H +/* 17858 */ MCD_OPC_FilterValue, 1, 221, 13, 1, // Skip to: 86948 +/* 17863 */ MCD_OPC_CheckPredicate, 0, 216, 13, 1, // Skip to: 86948 +/* 17868 */ MCD_OPC_Decode, 137, 7, 124, // Opcode: FCMGT_PPzZ0_H +/* 17872 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 17908 +/* 17877 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 17880 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 17894 +/* 17885 */ MCD_OPC_CheckPredicate, 0, 194, 13, 1, // Skip to: 86948 +/* 17890 */ MCD_OPC_Decode, 180, 7, 124, // Opcode: FCMLT_PPzZ0_H +/* 17894 */ MCD_OPC_FilterValue, 1, 185, 13, 1, // Skip to: 86948 +/* 17899 */ MCD_OPC_CheckPredicate, 0, 180, 13, 1, // Skip to: 86948 +/* 17904 */ MCD_OPC_Decode, 169, 7, 124, // Opcode: FCMLE_PPzZ0_H +/* 17908 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 17929 +/* 17913 */ MCD_OPC_CheckPredicate, 0, 166, 13, 1, // Skip to: 86948 +/* 17918 */ MCD_OPC_CheckField, 4, 1, 0, 159, 13, 1, // Skip to: 86948 +/* 17925 */ MCD_OPC_Decode, 221, 6, 124, // Opcode: FCMEQ_PPzZ0_H +/* 17929 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 17950 +/* 17934 */ MCD_OPC_CheckPredicate, 0, 145, 13, 1, // Skip to: 86948 +/* 17939 */ MCD_OPC_CheckField, 4, 1, 0, 138, 13, 1, // Skip to: 86948 +/* 17946 */ MCD_OPC_Decode, 191, 7, 124, // Opcode: FCMNE_PPzZ0_H +/* 17950 */ MCD_OPC_FilterValue, 24, 129, 13, 1, // Skip to: 86948 +/* 17955 */ MCD_OPC_CheckPredicate, 0, 124, 13, 1, // Skip to: 86948 +/* 17960 */ MCD_OPC_Decode, 173, 6, 67, // Opcode: FADDA_VPZ_H +/* 17964 */ MCD_OPC_FilterValue, 3, 115, 13, 1, // Skip to: 86948 +/* 17969 */ MCD_OPC_CheckPredicate, 0, 110, 13, 1, // Skip to: 86948 +/* 17974 */ MCD_OPC_Decode, 197, 10, 6, // Opcode: FMLS_ZPmZZ_H +/* 17978 */ MCD_OPC_FilterValue, 2, 53, 0, 0, // Skip to: 18036 +/* 17983 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 17986 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18022 +/* 17991 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 17994 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18008 +/* 17999 */ MCD_OPC_CheckPredicate, 0, 80, 13, 1, // Skip to: 86948 +/* 18004 */ MCD_OPC_Decode, 246, 6, 81, // Opcode: FCMGE_PPzZZ_H +/* 18008 */ MCD_OPC_FilterValue, 1, 71, 13, 1, // Skip to: 86948 +/* 18013 */ MCD_OPC_CheckPredicate, 0, 66, 13, 1, // Skip to: 86948 +/* 18018 */ MCD_OPC_Decode, 140, 7, 81, // Opcode: FCMGT_PPzZZ_H +/* 18022 */ MCD_OPC_FilterValue, 3, 57, 13, 1, // Skip to: 86948 +/* 18027 */ MCD_OPC_CheckPredicate, 0, 52, 13, 1, // Skip to: 86948 +/* 18032 */ MCD_OPC_Decode, 182, 11, 6, // Opcode: FNMLA_ZPmZZ_H +/* 18036 */ MCD_OPC_FilterValue, 3, 53, 0, 0, // Skip to: 18094 +/* 18041 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 18044 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18080 +/* 18049 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 18052 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18066 +/* 18057 */ MCD_OPC_CheckPredicate, 0, 22, 13, 1, // Skip to: 86948 +/* 18062 */ MCD_OPC_Decode, 224, 6, 81, // Opcode: FCMEQ_PPzZZ_H +/* 18066 */ MCD_OPC_FilterValue, 1, 13, 13, 1, // Skip to: 86948 +/* 18071 */ MCD_OPC_CheckPredicate, 0, 8, 13, 1, // Skip to: 86948 +/* 18076 */ MCD_OPC_Decode, 194, 7, 81, // Opcode: FCMNE_PPzZZ_H +/* 18080 */ MCD_OPC_FilterValue, 3, 255, 12, 1, // Skip to: 86948 +/* 18085 */ MCD_OPC_CheckPredicate, 0, 250, 12, 1, // Skip to: 86948 +/* 18090 */ MCD_OPC_Decode, 185, 11, 6, // Opcode: FNMLS_ZPmZZ_H +/* 18094 */ MCD_OPC_FilterValue, 4, 164, 1, 0, // Skip to: 18519 +/* 18099 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 18102 */ MCD_OPC_FilterValue, 2, 142, 1, 0, // Skip to: 18505 +/* 18107 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 18110 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 18230 +/* 18115 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 18118 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18132 +/* 18123 */ MCD_OPC_CheckPredicate, 0, 212, 12, 1, // Skip to: 86948 +/* 18128 */ MCD_OPC_Decode, 193, 6, 0, // Opcode: FADD_ZPmZ_H +/* 18132 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18146 +/* 18137 */ MCD_OPC_CheckPredicate, 0, 198, 12, 1, // Skip to: 86948 +/* 18142 */ MCD_OPC_Decode, 222, 12, 0, // Opcode: FSUB_ZPmZ_H +/* 18146 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18160 +/* 18151 */ MCD_OPC_CheckPredicate, 0, 184, 12, 1, // Skip to: 86948 +/* 18156 */ MCD_OPC_Decode, 143, 11, 0, // Opcode: FMUL_ZPmZ_H +/* 18160 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 18174 +/* 18165 */ MCD_OPC_CheckPredicate, 0, 170, 12, 1, // Skip to: 86948 +/* 18170 */ MCD_OPC_Decode, 215, 12, 0, // Opcode: FSUBR_ZPmZ_H +/* 18174 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18188 +/* 18179 */ MCD_OPC_CheckPredicate, 0, 156, 12, 1, // Skip to: 86948 +/* 18184 */ MCD_OPC_Decode, 216, 9, 0, // Opcode: FMAXNM_ZPmZ_H +/* 18188 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 18202 +/* 18193 */ MCD_OPC_CheckPredicate, 0, 142, 12, 1, // Skip to: 86948 +/* 18198 */ MCD_OPC_Decode, 144, 10, 0, // Opcode: FMINNM_ZPmZ_H +/* 18202 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 18216 +/* 18207 */ MCD_OPC_CheckPredicate, 0, 128, 12, 1, // Skip to: 86948 +/* 18212 */ MCD_OPC_Decode, 242, 9, 0, // Opcode: FMAX_ZPmZ_H +/* 18216 */ MCD_OPC_FilterValue, 7, 119, 12, 1, // Skip to: 86948 +/* 18221 */ MCD_OPC_CheckPredicate, 0, 114, 12, 1, // Skip to: 86948 +/* 18226 */ MCD_OPC_Decode, 170, 10, 0, // Opcode: FMIN_ZPmZ_H +/* 18230 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 18308 +/* 18235 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 18238 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18252 +/* 18243 */ MCD_OPC_CheckPredicate, 0, 92, 12, 1, // Skip to: 86948 +/* 18248 */ MCD_OPC_Decode, 132, 6, 0, // Opcode: FABD_ZPmZ_H +/* 18252 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18266 +/* 18257 */ MCD_OPC_CheckPredicate, 0, 78, 12, 1, // Skip to: 86948 +/* 18262 */ MCD_OPC_Decode, 196, 12, 0, // Opcode: FSCALE_ZPmZ_H +/* 18266 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18280 +/* 18271 */ MCD_OPC_CheckPredicate, 0, 64, 12, 1, // Skip to: 86948 +/* 18276 */ MCD_OPC_Decode, 252, 10, 0, // Opcode: FMULX_ZPmZ_H +/* 18280 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18294 +/* 18285 */ MCD_OPC_CheckPredicate, 0, 50, 12, 1, // Skip to: 86948 +/* 18290 */ MCD_OPC_Decode, 169, 9, 0, // Opcode: FDIVR_ZPmZ_H +/* 18294 */ MCD_OPC_FilterValue, 5, 41, 12, 1, // Skip to: 86948 +/* 18299 */ MCD_OPC_CheckPredicate, 0, 36, 12, 1, // Skip to: 86948 +/* 18304 */ MCD_OPC_Decode, 173, 9, 0, // Opcode: FDIV_ZPmZ_H +/* 18308 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18329 +/* 18313 */ MCD_OPC_CheckPredicate, 0, 22, 12, 1, // Skip to: 86948 +/* 18318 */ MCD_OPC_CheckField, 10, 3, 0, 15, 12, 1, // Skip to: 86948 +/* 18325 */ MCD_OPC_Decode, 233, 12, 125, // Opcode: FTMAD_ZZI_H +/* 18329 */ MCD_OPC_FilterValue, 3, 6, 12, 1, // Skip to: 86948 +/* 18334 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 18337 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 18358 +/* 18342 */ MCD_OPC_CheckPredicate, 0, 249, 11, 1, // Skip to: 86948 +/* 18347 */ MCD_OPC_CheckField, 6, 4, 0, 242, 11, 1, // Skip to: 86948 +/* 18354 */ MCD_OPC_Decode, 190, 6, 126, // Opcode: FADD_ZPmI_H +/* 18358 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 18379 +/* 18363 */ MCD_OPC_CheckPredicate, 0, 228, 11, 1, // Skip to: 86948 +/* 18368 */ MCD_OPC_CheckField, 6, 4, 0, 221, 11, 1, // Skip to: 86948 +/* 18375 */ MCD_OPC_Decode, 219, 12, 126, // Opcode: FSUB_ZPmI_H +/* 18379 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18400 +/* 18384 */ MCD_OPC_CheckPredicate, 0, 207, 11, 1, // Skip to: 86948 +/* 18389 */ MCD_OPC_CheckField, 6, 4, 0, 200, 11, 1, // Skip to: 86948 +/* 18396 */ MCD_OPC_Decode, 140, 11, 126, // Opcode: FMUL_ZPmI_H +/* 18400 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 18421 +/* 18405 */ MCD_OPC_CheckPredicate, 0, 186, 11, 1, // Skip to: 86948 +/* 18410 */ MCD_OPC_CheckField, 6, 4, 0, 179, 11, 1, // Skip to: 86948 +/* 18417 */ MCD_OPC_Decode, 212, 12, 126, // Opcode: FSUBR_ZPmI_H +/* 18421 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 18442 +/* 18426 */ MCD_OPC_CheckPredicate, 0, 165, 11, 1, // Skip to: 86948 +/* 18431 */ MCD_OPC_CheckField, 6, 4, 0, 158, 11, 1, // Skip to: 86948 +/* 18438 */ MCD_OPC_Decode, 213, 9, 126, // Opcode: FMAXNM_ZPmI_H +/* 18442 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 18463 +/* 18447 */ MCD_OPC_CheckPredicate, 0, 144, 11, 1, // Skip to: 86948 +/* 18452 */ MCD_OPC_CheckField, 6, 4, 0, 137, 11, 1, // Skip to: 86948 +/* 18459 */ MCD_OPC_Decode, 141, 10, 126, // Opcode: FMINNM_ZPmI_H +/* 18463 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 18484 +/* 18468 */ MCD_OPC_CheckPredicate, 0, 123, 11, 1, // Skip to: 86948 +/* 18473 */ MCD_OPC_CheckField, 6, 4, 0, 116, 11, 1, // Skip to: 86948 +/* 18480 */ MCD_OPC_Decode, 239, 9, 126, // Opcode: FMAX_ZPmI_H +/* 18484 */ MCD_OPC_FilterValue, 7, 107, 11, 1, // Skip to: 86948 +/* 18489 */ MCD_OPC_CheckPredicate, 0, 102, 11, 1, // Skip to: 86948 +/* 18494 */ MCD_OPC_CheckField, 6, 4, 0, 95, 11, 1, // Skip to: 86948 +/* 18501 */ MCD_OPC_Decode, 167, 10, 126, // Opcode: FMIN_ZPmI_H +/* 18505 */ MCD_OPC_FilterValue, 3, 86, 11, 1, // Skip to: 86948 +/* 18510 */ MCD_OPC_CheckPredicate, 0, 81, 11, 1, // Skip to: 86948 +/* 18515 */ MCD_OPC_Decode, 191, 9, 6, // Opcode: FMAD_ZPmZZ_H +/* 18519 */ MCD_OPC_FilterValue, 5, 63, 1, 0, // Skip to: 18843 +/* 18524 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 18527 */ MCD_OPC_FilterValue, 2, 41, 1, 0, // Skip to: 18829 +/* 18532 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 18535 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18549 +/* 18540 */ MCD_OPC_CheckPredicate, 0, 51, 11, 1, // Skip to: 86948 +/* 18545 */ MCD_OPC_Decode, 133, 12, 5, // Opcode: FRINTN_ZPmZ_H +/* 18549 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18563 +/* 18554 */ MCD_OPC_CheckPredicate, 0, 37, 11, 1, // Skip to: 86948 +/* 18559 */ MCD_OPC_Decode, 144, 12, 5, // Opcode: FRINTP_ZPmZ_H +/* 18563 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 18577 +/* 18568 */ MCD_OPC_CheckPredicate, 0, 23, 11, 1, // Skip to: 86948 +/* 18573 */ MCD_OPC_Decode, 250, 11, 5, // Opcode: FRINTM_ZPmZ_H +/* 18577 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 18591 +/* 18582 */ MCD_OPC_CheckPredicate, 0, 9, 11, 1, // Skip to: 86948 +/* 18587 */ MCD_OPC_Decode, 166, 12, 5, // Opcode: FRINTZ_ZPmZ_H +/* 18591 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 18605 +/* 18596 */ MCD_OPC_CheckPredicate, 0, 251, 10, 1, // Skip to: 86948 +/* 18601 */ MCD_OPC_Decode, 228, 11, 5, // Opcode: FRINTA_ZPmZ_H +/* 18605 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 18619 +/* 18610 */ MCD_OPC_CheckPredicate, 0, 237, 10, 1, // Skip to: 86948 +/* 18615 */ MCD_OPC_Decode, 155, 12, 5, // Opcode: FRINTX_ZPmZ_H +/* 18619 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 18633 +/* 18624 */ MCD_OPC_CheckPredicate, 0, 223, 10, 1, // Skip to: 86948 +/* 18629 */ MCD_OPC_Decode, 239, 11, 5, // Opcode: FRINTI_ZPmZ_H +/* 18633 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 18647 +/* 18638 */ MCD_OPC_CheckPredicate, 0, 209, 10, 1, // Skip to: 86948 +/* 18643 */ MCD_OPC_Decode, 219, 11, 5, // Opcode: FRECPX_ZPmZ_H +/* 18647 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 18661 +/* 18652 */ MCD_OPC_CheckPredicate, 0, 195, 10, 1, // Skip to: 86948 +/* 18657 */ MCD_OPC_Decode, 202, 12, 5, // Opcode: FSQRT_ZPmZ_H +/* 18661 */ MCD_OPC_FilterValue, 18, 9, 0, 0, // Skip to: 18675 +/* 18666 */ MCD_OPC_CheckPredicate, 0, 181, 10, 1, // Skip to: 86948 +/* 18671 */ MCD_OPC_Decode, 199, 22, 5, // Opcode: SCVTF_ZPmZ_HtoH +/* 18675 */ MCD_OPC_FilterValue, 19, 9, 0, 0, // Skip to: 18689 +/* 18680 */ MCD_OPC_CheckPredicate, 0, 167, 10, 1, // Skip to: 86948 +/* 18685 */ MCD_OPC_Decode, 186, 31, 5, // Opcode: UCVTF_ZPmZ_HtoH +/* 18689 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 18703 +/* 18694 */ MCD_OPC_CheckPredicate, 0, 153, 10, 1, // Skip to: 86948 +/* 18699 */ MCD_OPC_Decode, 201, 22, 5, // Opcode: SCVTF_ZPmZ_StoH +/* 18703 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 18717 +/* 18708 */ MCD_OPC_CheckPredicate, 0, 139, 10, 1, // Skip to: 86948 +/* 18713 */ MCD_OPC_Decode, 188, 31, 5, // Opcode: UCVTF_ZPmZ_StoH +/* 18717 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 18731 +/* 18722 */ MCD_OPC_CheckPredicate, 0, 125, 10, 1, // Skip to: 86948 +/* 18727 */ MCD_OPC_Decode, 197, 22, 5, // Opcode: SCVTF_ZPmZ_DtoH +/* 18731 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 18745 +/* 18736 */ MCD_OPC_CheckPredicate, 0, 111, 10, 1, // Skip to: 86948 +/* 18741 */ MCD_OPC_Decode, 184, 31, 5, // Opcode: UCVTF_ZPmZ_DtoH +/* 18745 */ MCD_OPC_FilterValue, 26, 9, 0, 0, // Skip to: 18759 +/* 18750 */ MCD_OPC_CheckPredicate, 0, 97, 10, 1, // Skip to: 86948 +/* 18755 */ MCD_OPC_Decode, 233, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoH +/* 18759 */ MCD_OPC_FilterValue, 27, 9, 0, 0, // Skip to: 18773 +/* 18764 */ MCD_OPC_CheckPredicate, 0, 83, 10, 1, // Skip to: 86948 +/* 18769 */ MCD_OPC_Decode, 140, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoH +/* 18773 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 18787 +/* 18778 */ MCD_OPC_CheckPredicate, 0, 69, 10, 1, // Skip to: 86948 +/* 18783 */ MCD_OPC_Decode, 234, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoS +/* 18787 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 18801 +/* 18792 */ MCD_OPC_CheckPredicate, 0, 55, 10, 1, // Skip to: 86948 +/* 18797 */ MCD_OPC_Decode, 141, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoS +/* 18801 */ MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 18815 +/* 18806 */ MCD_OPC_CheckPredicate, 0, 41, 10, 1, // Skip to: 86948 +/* 18811 */ MCD_OPC_Decode, 232, 8, 5, // Opcode: FCVTZS_ZPmZ_HtoD +/* 18815 */ MCD_OPC_FilterValue, 31, 32, 10, 1, // Skip to: 86948 +/* 18820 */ MCD_OPC_CheckPredicate, 0, 27, 10, 1, // Skip to: 86948 +/* 18825 */ MCD_OPC_Decode, 139, 9, 5, // Opcode: FCVTZU_ZPmZ_HtoD +/* 18829 */ MCD_OPC_FilterValue, 3, 18, 10, 1, // Skip to: 86948 +/* 18834 */ MCD_OPC_CheckPredicate, 0, 13, 10, 1, // Skip to: 86948 +/* 18839 */ MCD_OPC_Decode, 240, 10, 6, // Opcode: FMSB_ZPmZZ_H +/* 18843 */ MCD_OPC_FilterValue, 6, 53, 0, 0, // Skip to: 18901 +/* 18848 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 18851 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 18887 +/* 18856 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 18859 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18873 +/* 18864 */ MCD_OPC_CheckPredicate, 0, 239, 9, 1, // Skip to: 86948 +/* 18869 */ MCD_OPC_Decode, 209, 7, 81, // Opcode: FCMUO_PPzZZ_H +/* 18873 */ MCD_OPC_FilterValue, 1, 230, 9, 1, // Skip to: 86948 +/* 18878 */ MCD_OPC_CheckPredicate, 0, 225, 9, 1, // Skip to: 86948 +/* 18883 */ MCD_OPC_Decode, 154, 6, 81, // Opcode: FACGE_PPzZZ_H +/* 18887 */ MCD_OPC_FilterValue, 3, 216, 9, 1, // Skip to: 86948 +/* 18892 */ MCD_OPC_CheckPredicate, 0, 211, 9, 1, // Skip to: 86948 +/* 18897 */ MCD_OPC_Decode, 179, 11, 6, // Opcode: FNMAD_ZPmZZ_H +/* 18901 */ MCD_OPC_FilterValue, 7, 202, 9, 1, // Skip to: 86948 +/* 18906 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 18909 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 18930 +/* 18914 */ MCD_OPC_CheckPredicate, 0, 189, 9, 1, // Skip to: 86948 +/* 18919 */ MCD_OPC_CheckField, 4, 1, 1, 182, 9, 1, // Skip to: 86948 +/* 18926 */ MCD_OPC_Decode, 165, 6, 81, // Opcode: FACGT_PPzZZ_H +/* 18930 */ MCD_OPC_FilterValue, 3, 173, 9, 1, // Skip to: 86948 +/* 18935 */ MCD_OPC_CheckPredicate, 0, 168, 9, 1, // Skip to: 86948 +/* 18940 */ MCD_OPC_Decode, 188, 11, 6, // Opcode: FNMSB_ZPmZZ_H +/* 18944 */ MCD_OPC_FilterValue, 3, 159, 9, 1, // Skip to: 86948 +/* 18949 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 18952 */ MCD_OPC_FilterValue, 0, 215, 0, 0, // Skip to: 19172 +/* 18957 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 18960 */ MCD_OPC_FilterValue, 0, 87, 0, 0, // Skip to: 19052 +/* 18965 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 18968 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 18982 +/* 18973 */ MCD_OPC_CheckPredicate, 0, 130, 9, 1, // Skip to: 86948 +/* 18978 */ MCD_OPC_Decode, 197, 6, 27, // Opcode: FADD_ZZZ_S +/* 18982 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 18996 +/* 18987 */ MCD_OPC_CheckPredicate, 0, 116, 9, 1, // Skip to: 86948 +/* 18992 */ MCD_OPC_Decode, 226, 12, 27, // Opcode: FSUB_ZZZ_S +/* 18996 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19010 +/* 19001 */ MCD_OPC_CheckPredicate, 0, 102, 9, 1, // Skip to: 86948 +/* 19006 */ MCD_OPC_Decode, 150, 11, 27, // Opcode: FMUL_ZZZ_S +/* 19010 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 19024 +/* 19015 */ MCD_OPC_CheckPredicate, 0, 88, 9, 1, // Skip to: 86948 +/* 19020 */ MCD_OPC_Decode, 237, 12, 27, // Opcode: FTSMUL_ZZZ_S +/* 19024 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19038 +/* 19029 */ MCD_OPC_CheckPredicate, 0, 74, 9, 1, // Skip to: 86948 +/* 19034 */ MCD_OPC_Decode, 212, 11, 27, // Opcode: FRECPS_ZZZ_S +/* 19038 */ MCD_OPC_FilterValue, 7, 65, 9, 1, // Skip to: 86948 +/* 19043 */ MCD_OPC_CheckPredicate, 0, 60, 9, 1, // Skip to: 86948 +/* 19048 */ MCD_OPC_Decode, 189, 12, 27, // Opcode: FRSQRTS_ZZZ_S +/* 19052 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19066 +/* 19057 */ MCD_OPC_CheckPredicate, 0, 46, 9, 1, // Skip to: 86948 +/* 19062 */ MCD_OPC_Decode, 179, 10, 6, // Opcode: FMLA_ZPmZZ_S +/* 19066 */ MCD_OPC_FilterValue, 2, 87, 0, 0, // Skip to: 19158 +/* 19071 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 19074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19088 +/* 19079 */ MCD_OPC_CheckPredicate, 0, 24, 9, 1, // Skip to: 86948 +/* 19084 */ MCD_OPC_Decode, 195, 6, 27, // Opcode: FADD_ZZZ_D +/* 19088 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19102 +/* 19093 */ MCD_OPC_CheckPredicate, 0, 10, 9, 1, // Skip to: 86948 +/* 19098 */ MCD_OPC_Decode, 224, 12, 27, // Opcode: FSUB_ZZZ_D +/* 19102 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19116 +/* 19107 */ MCD_OPC_CheckPredicate, 0, 252, 8, 1, // Skip to: 86948 +/* 19112 */ MCD_OPC_Decode, 148, 11, 27, // Opcode: FMUL_ZZZ_D +/* 19116 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 19130 +/* 19121 */ MCD_OPC_CheckPredicate, 0, 238, 8, 1, // Skip to: 86948 +/* 19126 */ MCD_OPC_Decode, 235, 12, 27, // Opcode: FTSMUL_ZZZ_D +/* 19130 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19144 +/* 19135 */ MCD_OPC_CheckPredicate, 0, 224, 8, 1, // Skip to: 86948 +/* 19140 */ MCD_OPC_Decode, 210, 11, 27, // Opcode: FRECPS_ZZZ_D +/* 19144 */ MCD_OPC_FilterValue, 7, 215, 8, 1, // Skip to: 86948 +/* 19149 */ MCD_OPC_CheckPredicate, 0, 210, 8, 1, // Skip to: 86948 +/* 19154 */ MCD_OPC_Decode, 187, 12, 27, // Opcode: FRSQRTS_ZZZ_D +/* 19158 */ MCD_OPC_FilterValue, 3, 201, 8, 1, // Skip to: 86948 +/* 19163 */ MCD_OPC_CheckPredicate, 0, 196, 8, 1, // Skip to: 86948 +/* 19168 */ MCD_OPC_Decode, 177, 10, 6, // Opcode: FMLA_ZPmZZ_D +/* 19172 */ MCD_OPC_FilterValue, 1, 15, 2, 0, // Skip to: 19704 +/* 19177 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 19180 */ MCD_OPC_FilterValue, 0, 243, 0, 0, // Skip to: 19428 +/* 19185 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 19188 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19202 +/* 19193 */ MCD_OPC_CheckPredicate, 0, 166, 8, 1, // Skip to: 86948 +/* 19198 */ MCD_OPC_Decode, 188, 6, 14, // Opcode: FADDV_VPZ_S +/* 19202 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 19216 +/* 19207 */ MCD_OPC_CheckPredicate, 0, 152, 8, 1, // Skip to: 86948 +/* 19212 */ MCD_OPC_Decode, 208, 9, 14, // Opcode: FMAXNMV_VPZ_S +/* 19216 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 19230 +/* 19221 */ MCD_OPC_CheckPredicate, 0, 138, 8, 1, // Skip to: 86948 +/* 19226 */ MCD_OPC_Decode, 136, 10, 14, // Opcode: FMINNMV_VPZ_S +/* 19230 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19244 +/* 19235 */ MCD_OPC_CheckPredicate, 0, 124, 8, 1, // Skip to: 86948 +/* 19240 */ MCD_OPC_Decode, 234, 9, 14, // Opcode: FMAXV_VPZ_S +/* 19244 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 19258 +/* 19249 */ MCD_OPC_CheckPredicate, 0, 110, 8, 1, // Skip to: 86948 +/* 19254 */ MCD_OPC_Decode, 162, 10, 14, // Opcode: FMINV_VPZ_S +/* 19258 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 19279 +/* 19263 */ MCD_OPC_CheckPredicate, 0, 96, 8, 1, // Skip to: 86948 +/* 19268 */ MCD_OPC_CheckField, 10, 3, 4, 89, 8, 1, // Skip to: 86948 +/* 19275 */ MCD_OPC_Decode, 198, 11, 38, // Opcode: FRECPE_ZZ_S +/* 19279 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 19300 +/* 19284 */ MCD_OPC_CheckPredicate, 0, 75, 8, 1, // Skip to: 86948 +/* 19289 */ MCD_OPC_CheckField, 10, 3, 4, 68, 8, 1, // Skip to: 86948 +/* 19296 */ MCD_OPC_Decode, 175, 12, 38, // Opcode: FRSQRTE_ZZ_S +/* 19300 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 19336 +/* 19305 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19308 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19322 +/* 19313 */ MCD_OPC_CheckPredicate, 0, 46, 8, 1, // Skip to: 86948 +/* 19318 */ MCD_OPC_Decode, 244, 6, 124, // Opcode: FCMGE_PPzZ0_S +/* 19322 */ MCD_OPC_FilterValue, 1, 37, 8, 1, // Skip to: 86948 +/* 19327 */ MCD_OPC_CheckPredicate, 0, 32, 8, 1, // Skip to: 86948 +/* 19332 */ MCD_OPC_Decode, 138, 7, 124, // Opcode: FCMGT_PPzZ0_S +/* 19336 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 19372 +/* 19341 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19344 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19358 +/* 19349 */ MCD_OPC_CheckPredicate, 0, 10, 8, 1, // Skip to: 86948 +/* 19354 */ MCD_OPC_Decode, 181, 7, 124, // Opcode: FCMLT_PPzZ0_S +/* 19358 */ MCD_OPC_FilterValue, 1, 1, 8, 1, // Skip to: 86948 +/* 19363 */ MCD_OPC_CheckPredicate, 0, 252, 7, 1, // Skip to: 86948 +/* 19368 */ MCD_OPC_Decode, 170, 7, 124, // Opcode: FCMLE_PPzZ0_S +/* 19372 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 19393 +/* 19377 */ MCD_OPC_CheckPredicate, 0, 238, 7, 1, // Skip to: 86948 +/* 19382 */ MCD_OPC_CheckField, 4, 1, 0, 231, 7, 1, // Skip to: 86948 +/* 19389 */ MCD_OPC_Decode, 222, 6, 124, // Opcode: FCMEQ_PPzZ0_S +/* 19393 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 19414 +/* 19398 */ MCD_OPC_CheckPredicate, 0, 217, 7, 1, // Skip to: 86948 +/* 19403 */ MCD_OPC_CheckField, 4, 1, 0, 210, 7, 1, // Skip to: 86948 +/* 19410 */ MCD_OPC_Decode, 192, 7, 124, // Opcode: FCMNE_PPzZ0_S +/* 19414 */ MCD_OPC_FilterValue, 24, 201, 7, 1, // Skip to: 86948 +/* 19419 */ MCD_OPC_CheckPredicate, 0, 196, 7, 1, // Skip to: 86948 +/* 19424 */ MCD_OPC_Decode, 174, 6, 73, // Opcode: FADDA_VPZ_S +/* 19428 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19442 +/* 19433 */ MCD_OPC_CheckPredicate, 0, 182, 7, 1, // Skip to: 86948 +/* 19438 */ MCD_OPC_Decode, 198, 10, 6, // Opcode: FMLS_ZPmZZ_S +/* 19442 */ MCD_OPC_FilterValue, 2, 243, 0, 0, // Skip to: 19690 +/* 19447 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 19450 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19464 +/* 19455 */ MCD_OPC_CheckPredicate, 0, 160, 7, 1, // Skip to: 86948 +/* 19460 */ MCD_OPC_Decode, 186, 6, 1, // Opcode: FADDV_VPZ_D +/* 19464 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 19478 +/* 19469 */ MCD_OPC_CheckPredicate, 0, 146, 7, 1, // Skip to: 86948 +/* 19474 */ MCD_OPC_Decode, 206, 9, 1, // Opcode: FMAXNMV_VPZ_D +/* 19478 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 19492 +/* 19483 */ MCD_OPC_CheckPredicate, 0, 132, 7, 1, // Skip to: 86948 +/* 19488 */ MCD_OPC_Decode, 134, 10, 1, // Opcode: FMINNMV_VPZ_D +/* 19492 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 19506 +/* 19497 */ MCD_OPC_CheckPredicate, 0, 118, 7, 1, // Skip to: 86948 +/* 19502 */ MCD_OPC_Decode, 232, 9, 1, // Opcode: FMAXV_VPZ_D +/* 19506 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 19520 +/* 19511 */ MCD_OPC_CheckPredicate, 0, 104, 7, 1, // Skip to: 86948 +/* 19516 */ MCD_OPC_Decode, 160, 10, 1, // Opcode: FMINV_VPZ_D +/* 19520 */ MCD_OPC_FilterValue, 14, 16, 0, 0, // Skip to: 19541 +/* 19525 */ MCD_OPC_CheckPredicate, 0, 90, 7, 1, // Skip to: 86948 +/* 19530 */ MCD_OPC_CheckField, 10, 3, 4, 83, 7, 1, // Skip to: 86948 +/* 19537 */ MCD_OPC_Decode, 196, 11, 38, // Opcode: FRECPE_ZZ_D +/* 19541 */ MCD_OPC_FilterValue, 15, 16, 0, 0, // Skip to: 19562 +/* 19546 */ MCD_OPC_CheckPredicate, 0, 69, 7, 1, // Skip to: 86948 +/* 19551 */ MCD_OPC_CheckField, 10, 3, 4, 62, 7, 1, // Skip to: 86948 +/* 19558 */ MCD_OPC_Decode, 173, 12, 38, // Opcode: FRSQRTE_ZZ_D +/* 19562 */ MCD_OPC_FilterValue, 16, 31, 0, 0, // Skip to: 19598 +/* 19567 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19570 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19584 +/* 19575 */ MCD_OPC_CheckPredicate, 0, 40, 7, 1, // Skip to: 86948 +/* 19580 */ MCD_OPC_Decode, 242, 6, 124, // Opcode: FCMGE_PPzZ0_D +/* 19584 */ MCD_OPC_FilterValue, 1, 31, 7, 1, // Skip to: 86948 +/* 19589 */ MCD_OPC_CheckPredicate, 0, 26, 7, 1, // Skip to: 86948 +/* 19594 */ MCD_OPC_Decode, 136, 7, 124, // Opcode: FCMGT_PPzZ0_D +/* 19598 */ MCD_OPC_FilterValue, 17, 31, 0, 0, // Skip to: 19634 +/* 19603 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19606 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19620 +/* 19611 */ MCD_OPC_CheckPredicate, 0, 4, 7, 1, // Skip to: 86948 +/* 19616 */ MCD_OPC_Decode, 179, 7, 124, // Opcode: FCMLT_PPzZ0_D +/* 19620 */ MCD_OPC_FilterValue, 1, 251, 6, 1, // Skip to: 86948 +/* 19625 */ MCD_OPC_CheckPredicate, 0, 246, 6, 1, // Skip to: 86948 +/* 19630 */ MCD_OPC_Decode, 168, 7, 124, // Opcode: FCMLE_PPzZ0_D +/* 19634 */ MCD_OPC_FilterValue, 18, 16, 0, 0, // Skip to: 19655 +/* 19639 */ MCD_OPC_CheckPredicate, 0, 232, 6, 1, // Skip to: 86948 +/* 19644 */ MCD_OPC_CheckField, 4, 1, 0, 225, 6, 1, // Skip to: 86948 +/* 19651 */ MCD_OPC_Decode, 220, 6, 124, // Opcode: FCMEQ_PPzZ0_D +/* 19655 */ MCD_OPC_FilterValue, 19, 16, 0, 0, // Skip to: 19676 +/* 19660 */ MCD_OPC_CheckPredicate, 0, 211, 6, 1, // Skip to: 86948 +/* 19665 */ MCD_OPC_CheckField, 4, 1, 0, 204, 6, 1, // Skip to: 86948 +/* 19672 */ MCD_OPC_Decode, 190, 7, 124, // Opcode: FCMNE_PPzZ0_D +/* 19676 */ MCD_OPC_FilterValue, 24, 195, 6, 1, // Skip to: 86948 +/* 19681 */ MCD_OPC_CheckPredicate, 0, 190, 6, 1, // Skip to: 86948 +/* 19686 */ MCD_OPC_Decode, 172, 6, 74, // Opcode: FADDA_VPZ_D +/* 19690 */ MCD_OPC_FilterValue, 3, 181, 6, 1, // Skip to: 86948 +/* 19695 */ MCD_OPC_CheckPredicate, 0, 176, 6, 1, // Skip to: 86948 +/* 19700 */ MCD_OPC_Decode, 196, 10, 6, // Opcode: FMLS_ZPmZZ_D +/* 19704 */ MCD_OPC_FilterValue, 2, 103, 0, 0, // Skip to: 19812 +/* 19709 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 19712 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 19748 +/* 19717 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19720 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19734 +/* 19725 */ MCD_OPC_CheckPredicate, 0, 146, 6, 1, // Skip to: 86948 +/* 19730 */ MCD_OPC_Decode, 247, 6, 81, // Opcode: FCMGE_PPzZZ_S +/* 19734 */ MCD_OPC_FilterValue, 1, 137, 6, 1, // Skip to: 86948 +/* 19739 */ MCD_OPC_CheckPredicate, 0, 132, 6, 1, // Skip to: 86948 +/* 19744 */ MCD_OPC_Decode, 141, 7, 81, // Opcode: FCMGT_PPzZZ_S +/* 19748 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19762 +/* 19753 */ MCD_OPC_CheckPredicate, 0, 118, 6, 1, // Skip to: 86948 +/* 19758 */ MCD_OPC_Decode, 183, 11, 6, // Opcode: FNMLA_ZPmZZ_S +/* 19762 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 19798 +/* 19767 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19770 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19784 +/* 19775 */ MCD_OPC_CheckPredicate, 0, 96, 6, 1, // Skip to: 86948 +/* 19780 */ MCD_OPC_Decode, 245, 6, 81, // Opcode: FCMGE_PPzZZ_D +/* 19784 */ MCD_OPC_FilterValue, 1, 87, 6, 1, // Skip to: 86948 +/* 19789 */ MCD_OPC_CheckPredicate, 0, 82, 6, 1, // Skip to: 86948 +/* 19794 */ MCD_OPC_Decode, 139, 7, 81, // Opcode: FCMGT_PPzZZ_D +/* 19798 */ MCD_OPC_FilterValue, 3, 73, 6, 1, // Skip to: 86948 +/* 19803 */ MCD_OPC_CheckPredicate, 0, 68, 6, 1, // Skip to: 86948 +/* 19808 */ MCD_OPC_Decode, 181, 11, 6, // Opcode: FNMLA_ZPmZZ_D +/* 19812 */ MCD_OPC_FilterValue, 3, 103, 0, 0, // Skip to: 19920 +/* 19817 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 19820 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 19856 +/* 19825 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19828 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19842 +/* 19833 */ MCD_OPC_CheckPredicate, 0, 38, 6, 1, // Skip to: 86948 +/* 19838 */ MCD_OPC_Decode, 225, 6, 81, // Opcode: FCMEQ_PPzZZ_S +/* 19842 */ MCD_OPC_FilterValue, 1, 29, 6, 1, // Skip to: 86948 +/* 19847 */ MCD_OPC_CheckPredicate, 0, 24, 6, 1, // Skip to: 86948 +/* 19852 */ MCD_OPC_Decode, 195, 7, 81, // Opcode: FCMNE_PPzZZ_S +/* 19856 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19870 +/* 19861 */ MCD_OPC_CheckPredicate, 0, 10, 6, 1, // Skip to: 86948 +/* 19866 */ MCD_OPC_Decode, 186, 11, 6, // Opcode: FNMLS_ZPmZZ_S +/* 19870 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 19906 +/* 19875 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 19878 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19892 +/* 19883 */ MCD_OPC_CheckPredicate, 0, 244, 5, 1, // Skip to: 86948 +/* 19888 */ MCD_OPC_Decode, 223, 6, 81, // Opcode: FCMEQ_PPzZZ_D +/* 19892 */ MCD_OPC_FilterValue, 1, 235, 5, 1, // Skip to: 86948 +/* 19897 */ MCD_OPC_CheckPredicate, 0, 230, 5, 1, // Skip to: 86948 +/* 19902 */ MCD_OPC_Decode, 193, 7, 81, // Opcode: FCMNE_PPzZZ_D +/* 19906 */ MCD_OPC_FilterValue, 3, 221, 5, 1, // Skip to: 86948 +/* 19911 */ MCD_OPC_CheckPredicate, 0, 216, 5, 1, // Skip to: 86948 +/* 19916 */ MCD_OPC_Decode, 184, 11, 6, // Opcode: FNMLS_ZPmZZ_D +/* 19920 */ MCD_OPC_FilterValue, 4, 69, 3, 0, // Skip to: 20762 +/* 19925 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 19928 */ MCD_OPC_FilterValue, 0, 142, 1, 0, // Skip to: 20331 +/* 19933 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 19936 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 20056 +/* 19941 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 19944 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 19958 +/* 19949 */ MCD_OPC_CheckPredicate, 0, 178, 5, 1, // Skip to: 86948 +/* 19954 */ MCD_OPC_Decode, 194, 6, 0, // Opcode: FADD_ZPmZ_S +/* 19958 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 19972 +/* 19963 */ MCD_OPC_CheckPredicate, 0, 164, 5, 1, // Skip to: 86948 +/* 19968 */ MCD_OPC_Decode, 223, 12, 0, // Opcode: FSUB_ZPmZ_S +/* 19972 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 19986 +/* 19977 */ MCD_OPC_CheckPredicate, 0, 150, 5, 1, // Skip to: 86948 +/* 19982 */ MCD_OPC_Decode, 144, 11, 0, // Opcode: FMUL_ZPmZ_S +/* 19986 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20000 +/* 19991 */ MCD_OPC_CheckPredicate, 0, 136, 5, 1, // Skip to: 86948 +/* 19996 */ MCD_OPC_Decode, 216, 12, 0, // Opcode: FSUBR_ZPmZ_S +/* 20000 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20014 +/* 20005 */ MCD_OPC_CheckPredicate, 0, 122, 5, 1, // Skip to: 86948 +/* 20010 */ MCD_OPC_Decode, 217, 9, 0, // Opcode: FMAXNM_ZPmZ_S +/* 20014 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 20028 +/* 20019 */ MCD_OPC_CheckPredicate, 0, 108, 5, 1, // Skip to: 86948 +/* 20024 */ MCD_OPC_Decode, 145, 10, 0, // Opcode: FMINNM_ZPmZ_S +/* 20028 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20042 +/* 20033 */ MCD_OPC_CheckPredicate, 0, 94, 5, 1, // Skip to: 86948 +/* 20038 */ MCD_OPC_Decode, 243, 9, 0, // Opcode: FMAX_ZPmZ_S +/* 20042 */ MCD_OPC_FilterValue, 7, 85, 5, 1, // Skip to: 86948 +/* 20047 */ MCD_OPC_CheckPredicate, 0, 80, 5, 1, // Skip to: 86948 +/* 20052 */ MCD_OPC_Decode, 171, 10, 0, // Opcode: FMIN_ZPmZ_S +/* 20056 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 20134 +/* 20061 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 20064 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20078 +/* 20069 */ MCD_OPC_CheckPredicate, 0, 58, 5, 1, // Skip to: 86948 +/* 20074 */ MCD_OPC_Decode, 133, 6, 0, // Opcode: FABD_ZPmZ_S +/* 20078 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20092 +/* 20083 */ MCD_OPC_CheckPredicate, 0, 44, 5, 1, // Skip to: 86948 +/* 20088 */ MCD_OPC_Decode, 197, 12, 0, // Opcode: FSCALE_ZPmZ_S +/* 20092 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20106 +/* 20097 */ MCD_OPC_CheckPredicate, 0, 30, 5, 1, // Skip to: 86948 +/* 20102 */ MCD_OPC_Decode, 253, 10, 0, // Opcode: FMULX_ZPmZ_S +/* 20106 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20120 +/* 20111 */ MCD_OPC_CheckPredicate, 0, 16, 5, 1, // Skip to: 86948 +/* 20116 */ MCD_OPC_Decode, 170, 9, 0, // Opcode: FDIVR_ZPmZ_S +/* 20120 */ MCD_OPC_FilterValue, 5, 7, 5, 1, // Skip to: 86948 +/* 20125 */ MCD_OPC_CheckPredicate, 0, 2, 5, 1, // Skip to: 86948 +/* 20130 */ MCD_OPC_Decode, 174, 9, 0, // Opcode: FDIV_ZPmZ_S +/* 20134 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20155 +/* 20139 */ MCD_OPC_CheckPredicate, 0, 244, 4, 1, // Skip to: 86948 +/* 20144 */ MCD_OPC_CheckField, 10, 3, 0, 237, 4, 1, // Skip to: 86948 +/* 20151 */ MCD_OPC_Decode, 234, 12, 125, // Opcode: FTMAD_ZZI_S +/* 20155 */ MCD_OPC_FilterValue, 3, 228, 4, 1, // Skip to: 86948 +/* 20160 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 20163 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 20184 +/* 20168 */ MCD_OPC_CheckPredicate, 0, 215, 4, 1, // Skip to: 86948 +/* 20173 */ MCD_OPC_CheckField, 6, 4, 0, 208, 4, 1, // Skip to: 86948 +/* 20180 */ MCD_OPC_Decode, 191, 6, 126, // Opcode: FADD_ZPmI_S +/* 20184 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 20205 +/* 20189 */ MCD_OPC_CheckPredicate, 0, 194, 4, 1, // Skip to: 86948 +/* 20194 */ MCD_OPC_CheckField, 6, 4, 0, 187, 4, 1, // Skip to: 86948 +/* 20201 */ MCD_OPC_Decode, 220, 12, 126, // Opcode: FSUB_ZPmI_S +/* 20205 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20226 +/* 20210 */ MCD_OPC_CheckPredicate, 0, 173, 4, 1, // Skip to: 86948 +/* 20215 */ MCD_OPC_CheckField, 6, 4, 0, 166, 4, 1, // Skip to: 86948 +/* 20222 */ MCD_OPC_Decode, 141, 11, 126, // Opcode: FMUL_ZPmI_S +/* 20226 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 20247 +/* 20231 */ MCD_OPC_CheckPredicate, 0, 152, 4, 1, // Skip to: 86948 +/* 20236 */ MCD_OPC_CheckField, 6, 4, 0, 145, 4, 1, // Skip to: 86948 +/* 20243 */ MCD_OPC_Decode, 213, 12, 126, // Opcode: FSUBR_ZPmI_S +/* 20247 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 20268 +/* 20252 */ MCD_OPC_CheckPredicate, 0, 131, 4, 1, // Skip to: 86948 +/* 20257 */ MCD_OPC_CheckField, 6, 4, 0, 124, 4, 1, // Skip to: 86948 +/* 20264 */ MCD_OPC_Decode, 214, 9, 126, // Opcode: FMAXNM_ZPmI_S +/* 20268 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 20289 +/* 20273 */ MCD_OPC_CheckPredicate, 0, 110, 4, 1, // Skip to: 86948 +/* 20278 */ MCD_OPC_CheckField, 6, 4, 0, 103, 4, 1, // Skip to: 86948 +/* 20285 */ MCD_OPC_Decode, 142, 10, 126, // Opcode: FMINNM_ZPmI_S +/* 20289 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 20310 +/* 20294 */ MCD_OPC_CheckPredicate, 0, 89, 4, 1, // Skip to: 86948 +/* 20299 */ MCD_OPC_CheckField, 6, 4, 0, 82, 4, 1, // Skip to: 86948 +/* 20306 */ MCD_OPC_Decode, 240, 9, 126, // Opcode: FMAX_ZPmI_S +/* 20310 */ MCD_OPC_FilterValue, 7, 73, 4, 1, // Skip to: 86948 +/* 20315 */ MCD_OPC_CheckPredicate, 0, 68, 4, 1, // Skip to: 86948 +/* 20320 */ MCD_OPC_CheckField, 6, 4, 0, 61, 4, 1, // Skip to: 86948 +/* 20327 */ MCD_OPC_Decode, 168, 10, 126, // Opcode: FMIN_ZPmI_S +/* 20331 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20345 +/* 20336 */ MCD_OPC_CheckPredicate, 0, 47, 4, 1, // Skip to: 86948 +/* 20341 */ MCD_OPC_Decode, 192, 9, 6, // Opcode: FMAD_ZPmZZ_S +/* 20345 */ MCD_OPC_FilterValue, 2, 142, 1, 0, // Skip to: 20748 +/* 20350 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 20353 */ MCD_OPC_FilterValue, 0, 115, 0, 0, // Skip to: 20473 +/* 20358 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 20361 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20375 +/* 20366 */ MCD_OPC_CheckPredicate, 0, 17, 4, 1, // Skip to: 86948 +/* 20371 */ MCD_OPC_Decode, 192, 6, 0, // Opcode: FADD_ZPmZ_D +/* 20375 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20389 +/* 20380 */ MCD_OPC_CheckPredicate, 0, 3, 4, 1, // Skip to: 86948 +/* 20385 */ MCD_OPC_Decode, 221, 12, 0, // Opcode: FSUB_ZPmZ_D +/* 20389 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20403 +/* 20394 */ MCD_OPC_CheckPredicate, 0, 245, 3, 1, // Skip to: 86948 +/* 20399 */ MCD_OPC_Decode, 142, 11, 0, // Opcode: FMUL_ZPmZ_D +/* 20403 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20417 +/* 20408 */ MCD_OPC_CheckPredicate, 0, 231, 3, 1, // Skip to: 86948 +/* 20413 */ MCD_OPC_Decode, 214, 12, 0, // Opcode: FSUBR_ZPmZ_D +/* 20417 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20431 +/* 20422 */ MCD_OPC_CheckPredicate, 0, 217, 3, 1, // Skip to: 86948 +/* 20427 */ MCD_OPC_Decode, 215, 9, 0, // Opcode: FMAXNM_ZPmZ_D +/* 20431 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 20445 +/* 20436 */ MCD_OPC_CheckPredicate, 0, 203, 3, 1, // Skip to: 86948 +/* 20441 */ MCD_OPC_Decode, 143, 10, 0, // Opcode: FMINNM_ZPmZ_D +/* 20445 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20459 +/* 20450 */ MCD_OPC_CheckPredicate, 0, 189, 3, 1, // Skip to: 86948 +/* 20455 */ MCD_OPC_Decode, 241, 9, 0, // Opcode: FMAX_ZPmZ_D +/* 20459 */ MCD_OPC_FilterValue, 7, 180, 3, 1, // Skip to: 86948 +/* 20464 */ MCD_OPC_CheckPredicate, 0, 175, 3, 1, // Skip to: 86948 +/* 20469 */ MCD_OPC_Decode, 169, 10, 0, // Opcode: FMIN_ZPmZ_D +/* 20473 */ MCD_OPC_FilterValue, 1, 73, 0, 0, // Skip to: 20551 +/* 20478 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 20481 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20495 +/* 20486 */ MCD_OPC_CheckPredicate, 0, 153, 3, 1, // Skip to: 86948 +/* 20491 */ MCD_OPC_Decode, 131, 6, 0, // Opcode: FABD_ZPmZ_D +/* 20495 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20509 +/* 20500 */ MCD_OPC_CheckPredicate, 0, 139, 3, 1, // Skip to: 86948 +/* 20505 */ MCD_OPC_Decode, 195, 12, 0, // Opcode: FSCALE_ZPmZ_D +/* 20509 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20523 +/* 20514 */ MCD_OPC_CheckPredicate, 0, 125, 3, 1, // Skip to: 86948 +/* 20519 */ MCD_OPC_Decode, 251, 10, 0, // Opcode: FMULX_ZPmZ_D +/* 20523 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20537 +/* 20528 */ MCD_OPC_CheckPredicate, 0, 111, 3, 1, // Skip to: 86948 +/* 20533 */ MCD_OPC_Decode, 168, 9, 0, // Opcode: FDIVR_ZPmZ_D +/* 20537 */ MCD_OPC_FilterValue, 5, 102, 3, 1, // Skip to: 86948 +/* 20542 */ MCD_OPC_CheckPredicate, 0, 97, 3, 1, // Skip to: 86948 +/* 20547 */ MCD_OPC_Decode, 172, 9, 0, // Opcode: FDIV_ZPmZ_D +/* 20551 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20572 +/* 20556 */ MCD_OPC_CheckPredicate, 0, 83, 3, 1, // Skip to: 86948 +/* 20561 */ MCD_OPC_CheckField, 10, 3, 0, 76, 3, 1, // Skip to: 86948 +/* 20568 */ MCD_OPC_Decode, 232, 12, 125, // Opcode: FTMAD_ZZI_D +/* 20572 */ MCD_OPC_FilterValue, 3, 67, 3, 1, // Skip to: 86948 +/* 20577 */ MCD_OPC_ExtractField, 16, 3, // Inst{18-16} ... +/* 20580 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 20601 +/* 20585 */ MCD_OPC_CheckPredicate, 0, 54, 3, 1, // Skip to: 86948 +/* 20590 */ MCD_OPC_CheckField, 6, 4, 0, 47, 3, 1, // Skip to: 86948 +/* 20597 */ MCD_OPC_Decode, 189, 6, 126, // Opcode: FADD_ZPmI_D +/* 20601 */ MCD_OPC_FilterValue, 1, 16, 0, 0, // Skip to: 20622 +/* 20606 */ MCD_OPC_CheckPredicate, 0, 33, 3, 1, // Skip to: 86948 +/* 20611 */ MCD_OPC_CheckField, 6, 4, 0, 26, 3, 1, // Skip to: 86948 +/* 20618 */ MCD_OPC_Decode, 218, 12, 126, // Opcode: FSUB_ZPmI_D +/* 20622 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 20643 +/* 20627 */ MCD_OPC_CheckPredicate, 0, 12, 3, 1, // Skip to: 86948 +/* 20632 */ MCD_OPC_CheckField, 6, 4, 0, 5, 3, 1, // Skip to: 86948 +/* 20639 */ MCD_OPC_Decode, 139, 11, 126, // Opcode: FMUL_ZPmI_D +/* 20643 */ MCD_OPC_FilterValue, 3, 16, 0, 0, // Skip to: 20664 +/* 20648 */ MCD_OPC_CheckPredicate, 0, 247, 2, 1, // Skip to: 86948 +/* 20653 */ MCD_OPC_CheckField, 6, 4, 0, 240, 2, 1, // Skip to: 86948 +/* 20660 */ MCD_OPC_Decode, 211, 12, 126, // Opcode: FSUBR_ZPmI_D +/* 20664 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 20685 +/* 20669 */ MCD_OPC_CheckPredicate, 0, 226, 2, 1, // Skip to: 86948 +/* 20674 */ MCD_OPC_CheckField, 6, 4, 0, 219, 2, 1, // Skip to: 86948 +/* 20681 */ MCD_OPC_Decode, 212, 9, 126, // Opcode: FMAXNM_ZPmI_D +/* 20685 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 20706 +/* 20690 */ MCD_OPC_CheckPredicate, 0, 205, 2, 1, // Skip to: 86948 +/* 20695 */ MCD_OPC_CheckField, 6, 4, 0, 198, 2, 1, // Skip to: 86948 +/* 20702 */ MCD_OPC_Decode, 140, 10, 126, // Opcode: FMINNM_ZPmI_D +/* 20706 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 20727 +/* 20711 */ MCD_OPC_CheckPredicate, 0, 184, 2, 1, // Skip to: 86948 +/* 20716 */ MCD_OPC_CheckField, 6, 4, 0, 177, 2, 1, // Skip to: 86948 +/* 20723 */ MCD_OPC_Decode, 238, 9, 126, // Opcode: FMAX_ZPmI_D +/* 20727 */ MCD_OPC_FilterValue, 7, 168, 2, 1, // Skip to: 86948 +/* 20732 */ MCD_OPC_CheckPredicate, 0, 163, 2, 1, // Skip to: 86948 +/* 20737 */ MCD_OPC_CheckField, 6, 4, 0, 156, 2, 1, // Skip to: 86948 +/* 20744 */ MCD_OPC_Decode, 166, 10, 126, // Opcode: FMIN_ZPmI_D +/* 20748 */ MCD_OPC_FilterValue, 3, 147, 2, 1, // Skip to: 86948 +/* 20753 */ MCD_OPC_CheckPredicate, 0, 142, 2, 1, // Skip to: 86948 +/* 20758 */ MCD_OPC_Decode, 190, 9, 6, // Opcode: FMAD_ZPmZZ_D +/* 20762 */ MCD_OPC_FilterValue, 5, 95, 2, 0, // Skip to: 21374 +/* 20767 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 20770 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 20988 +/* 20775 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 20778 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 20792 +/* 20783 */ MCD_OPC_CheckPredicate, 0, 112, 2, 1, // Skip to: 86948 +/* 20788 */ MCD_OPC_Decode, 134, 12, 5, // Opcode: FRINTN_ZPmZ_S +/* 20792 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 20806 +/* 20797 */ MCD_OPC_CheckPredicate, 0, 98, 2, 1, // Skip to: 86948 +/* 20802 */ MCD_OPC_Decode, 145, 12, 5, // Opcode: FRINTP_ZPmZ_S +/* 20806 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 20820 +/* 20811 */ MCD_OPC_CheckPredicate, 0, 84, 2, 1, // Skip to: 86948 +/* 20816 */ MCD_OPC_Decode, 251, 11, 5, // Opcode: FRINTM_ZPmZ_S +/* 20820 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 20834 +/* 20825 */ MCD_OPC_CheckPredicate, 0, 70, 2, 1, // Skip to: 86948 +/* 20830 */ MCD_OPC_Decode, 167, 12, 5, // Opcode: FRINTZ_ZPmZ_S +/* 20834 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 20848 +/* 20839 */ MCD_OPC_CheckPredicate, 0, 56, 2, 1, // Skip to: 86948 +/* 20844 */ MCD_OPC_Decode, 229, 11, 5, // Opcode: FRINTA_ZPmZ_S +/* 20848 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 20862 +/* 20853 */ MCD_OPC_CheckPredicate, 0, 42, 2, 1, // Skip to: 86948 +/* 20858 */ MCD_OPC_Decode, 156, 12, 5, // Opcode: FRINTX_ZPmZ_S +/* 20862 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 20876 +/* 20867 */ MCD_OPC_CheckPredicate, 0, 28, 2, 1, // Skip to: 86948 +/* 20872 */ MCD_OPC_Decode, 240, 11, 5, // Opcode: FRINTI_ZPmZ_S +/* 20876 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 20890 +/* 20881 */ MCD_OPC_CheckPredicate, 0, 14, 2, 1, // Skip to: 86948 +/* 20886 */ MCD_OPC_Decode, 165, 9, 5, // Opcode: FCVT_ZPmZ_StoH +/* 20890 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 20904 +/* 20895 */ MCD_OPC_CheckPredicate, 0, 0, 2, 1, // Skip to: 86948 +/* 20900 */ MCD_OPC_Decode, 163, 9, 5, // Opcode: FCVT_ZPmZ_HtoS +/* 20904 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 20918 +/* 20909 */ MCD_OPC_CheckPredicate, 0, 242, 1, 1, // Skip to: 86948 +/* 20914 */ MCD_OPC_Decode, 220, 11, 5, // Opcode: FRECPX_ZPmZ_S +/* 20918 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 20932 +/* 20923 */ MCD_OPC_CheckPredicate, 0, 228, 1, 1, // Skip to: 86948 +/* 20928 */ MCD_OPC_Decode, 203, 12, 5, // Opcode: FSQRT_ZPmZ_S +/* 20932 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 20946 +/* 20937 */ MCD_OPC_CheckPredicate, 0, 214, 1, 1, // Skip to: 86948 +/* 20942 */ MCD_OPC_Decode, 202, 22, 5, // Opcode: SCVTF_ZPmZ_StoS +/* 20946 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 20960 +/* 20951 */ MCD_OPC_CheckPredicate, 0, 200, 1, 1, // Skip to: 86948 +/* 20956 */ MCD_OPC_Decode, 189, 31, 5, // Opcode: UCVTF_ZPmZ_StoS +/* 20960 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 20974 +/* 20965 */ MCD_OPC_CheckPredicate, 0, 186, 1, 1, // Skip to: 86948 +/* 20970 */ MCD_OPC_Decode, 236, 8, 5, // Opcode: FCVTZS_ZPmZ_StoS +/* 20974 */ MCD_OPC_FilterValue, 29, 177, 1, 1, // Skip to: 86948 +/* 20979 */ MCD_OPC_CheckPredicate, 0, 172, 1, 1, // Skip to: 86948 +/* 20984 */ MCD_OPC_Decode, 143, 9, 5, // Opcode: FCVTZU_ZPmZ_StoS +/* 20988 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21002 +/* 20993 */ MCD_OPC_CheckPredicate, 0, 158, 1, 1, // Skip to: 86948 +/* 20998 */ MCD_OPC_Decode, 241, 10, 6, // Opcode: FMSB_ZPmZZ_S +/* 21002 */ MCD_OPC_FilterValue, 2, 97, 1, 0, // Skip to: 21360 +/* 21007 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 21010 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21024 +/* 21015 */ MCD_OPC_CheckPredicate, 0, 136, 1, 1, // Skip to: 86948 +/* 21020 */ MCD_OPC_Decode, 132, 12, 5, // Opcode: FRINTN_ZPmZ_D +/* 21024 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21038 +/* 21029 */ MCD_OPC_CheckPredicate, 0, 122, 1, 1, // Skip to: 86948 +/* 21034 */ MCD_OPC_Decode, 143, 12, 5, // Opcode: FRINTP_ZPmZ_D +/* 21038 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 21052 +/* 21043 */ MCD_OPC_CheckPredicate, 0, 108, 1, 1, // Skip to: 86948 +/* 21048 */ MCD_OPC_Decode, 249, 11, 5, // Opcode: FRINTM_ZPmZ_D +/* 21052 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 21066 +/* 21057 */ MCD_OPC_CheckPredicate, 0, 94, 1, 1, // Skip to: 86948 +/* 21062 */ MCD_OPC_Decode, 165, 12, 5, // Opcode: FRINTZ_ZPmZ_D +/* 21066 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 21080 +/* 21071 */ MCD_OPC_CheckPredicate, 0, 80, 1, 1, // Skip to: 86948 +/* 21076 */ MCD_OPC_Decode, 227, 11, 5, // Opcode: FRINTA_ZPmZ_D +/* 21080 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 21094 +/* 21085 */ MCD_OPC_CheckPredicate, 0, 66, 1, 1, // Skip to: 86948 +/* 21090 */ MCD_OPC_Decode, 154, 12, 5, // Opcode: FRINTX_ZPmZ_D +/* 21094 */ MCD_OPC_FilterValue, 7, 9, 0, 0, // Skip to: 21108 +/* 21099 */ MCD_OPC_CheckPredicate, 0, 52, 1, 1, // Skip to: 86948 +/* 21104 */ MCD_OPC_Decode, 238, 11, 5, // Opcode: FRINTI_ZPmZ_D +/* 21108 */ MCD_OPC_FilterValue, 8, 9, 0, 0, // Skip to: 21122 +/* 21113 */ MCD_OPC_CheckPredicate, 0, 38, 1, 1, // Skip to: 86948 +/* 21118 */ MCD_OPC_Decode, 160, 9, 5, // Opcode: FCVT_ZPmZ_DtoH +/* 21122 */ MCD_OPC_FilterValue, 9, 9, 0, 0, // Skip to: 21136 +/* 21127 */ MCD_OPC_CheckPredicate, 0, 24, 1, 1, // Skip to: 86948 +/* 21132 */ MCD_OPC_Decode, 162, 9, 5, // Opcode: FCVT_ZPmZ_HtoD +/* 21136 */ MCD_OPC_FilterValue, 10, 9, 0, 0, // Skip to: 21150 +/* 21141 */ MCD_OPC_CheckPredicate, 0, 10, 1, 1, // Skip to: 86948 +/* 21146 */ MCD_OPC_Decode, 161, 9, 5, // Opcode: FCVT_ZPmZ_DtoS +/* 21150 */ MCD_OPC_FilterValue, 11, 9, 0, 0, // Skip to: 21164 +/* 21155 */ MCD_OPC_CheckPredicate, 0, 252, 0, 1, // Skip to: 86948 +/* 21160 */ MCD_OPC_Decode, 164, 9, 5, // Opcode: FCVT_ZPmZ_StoD +/* 21164 */ MCD_OPC_FilterValue, 12, 9, 0, 0, // Skip to: 21178 +/* 21169 */ MCD_OPC_CheckPredicate, 0, 238, 0, 1, // Skip to: 86948 +/* 21174 */ MCD_OPC_Decode, 218, 11, 5, // Opcode: FRECPX_ZPmZ_D +/* 21178 */ MCD_OPC_FilterValue, 13, 9, 0, 0, // Skip to: 21192 +/* 21183 */ MCD_OPC_CheckPredicate, 0, 224, 0, 1, // Skip to: 86948 +/* 21188 */ MCD_OPC_Decode, 201, 12, 5, // Opcode: FSQRT_ZPmZ_D +/* 21192 */ MCD_OPC_FilterValue, 16, 9, 0, 0, // Skip to: 21206 +/* 21197 */ MCD_OPC_CheckPredicate, 0, 210, 0, 1, // Skip to: 86948 +/* 21202 */ MCD_OPC_Decode, 200, 22, 5, // Opcode: SCVTF_ZPmZ_StoD +/* 21206 */ MCD_OPC_FilterValue, 17, 9, 0, 0, // Skip to: 21220 +/* 21211 */ MCD_OPC_CheckPredicate, 0, 196, 0, 1, // Skip to: 86948 +/* 21216 */ MCD_OPC_Decode, 187, 31, 5, // Opcode: UCVTF_ZPmZ_StoD +/* 21220 */ MCD_OPC_FilterValue, 20, 9, 0, 0, // Skip to: 21234 +/* 21225 */ MCD_OPC_CheckPredicate, 0, 182, 0, 1, // Skip to: 86948 +/* 21230 */ MCD_OPC_Decode, 198, 22, 5, // Opcode: SCVTF_ZPmZ_DtoS +/* 21234 */ MCD_OPC_FilterValue, 21, 9, 0, 0, // Skip to: 21248 +/* 21239 */ MCD_OPC_CheckPredicate, 0, 168, 0, 1, // Skip to: 86948 +/* 21244 */ MCD_OPC_Decode, 185, 31, 5, // Opcode: UCVTF_ZPmZ_DtoS +/* 21248 */ MCD_OPC_FilterValue, 22, 9, 0, 0, // Skip to: 21262 +/* 21253 */ MCD_OPC_CheckPredicate, 0, 154, 0, 1, // Skip to: 86948 +/* 21258 */ MCD_OPC_Decode, 196, 22, 5, // Opcode: SCVTF_ZPmZ_DtoD +/* 21262 */ MCD_OPC_FilterValue, 23, 9, 0, 0, // Skip to: 21276 +/* 21267 */ MCD_OPC_CheckPredicate, 0, 140, 0, 1, // Skip to: 86948 +/* 21272 */ MCD_OPC_Decode, 183, 31, 5, // Opcode: UCVTF_ZPmZ_DtoD +/* 21276 */ MCD_OPC_FilterValue, 24, 9, 0, 0, // Skip to: 21290 +/* 21281 */ MCD_OPC_CheckPredicate, 0, 126, 0, 1, // Skip to: 86948 +/* 21286 */ MCD_OPC_Decode, 231, 8, 5, // Opcode: FCVTZS_ZPmZ_DtoS +/* 21290 */ MCD_OPC_FilterValue, 25, 9, 0, 0, // Skip to: 21304 +/* 21295 */ MCD_OPC_CheckPredicate, 0, 112, 0, 1, // Skip to: 86948 +/* 21300 */ MCD_OPC_Decode, 138, 9, 5, // Opcode: FCVTZU_ZPmZ_DtoS +/* 21304 */ MCD_OPC_FilterValue, 28, 9, 0, 0, // Skip to: 21318 +/* 21309 */ MCD_OPC_CheckPredicate, 0, 98, 0, 1, // Skip to: 86948 +/* 21314 */ MCD_OPC_Decode, 235, 8, 5, // Opcode: FCVTZS_ZPmZ_StoD +/* 21318 */ MCD_OPC_FilterValue, 29, 9, 0, 0, // Skip to: 21332 +/* 21323 */ MCD_OPC_CheckPredicate, 0, 84, 0, 1, // Skip to: 86948 +/* 21328 */ MCD_OPC_Decode, 142, 9, 5, // Opcode: FCVTZU_ZPmZ_StoD +/* 21332 */ MCD_OPC_FilterValue, 30, 9, 0, 0, // Skip to: 21346 +/* 21337 */ MCD_OPC_CheckPredicate, 0, 70, 0, 1, // Skip to: 86948 +/* 21342 */ MCD_OPC_Decode, 230, 8, 5, // Opcode: FCVTZS_ZPmZ_DtoD +/* 21346 */ MCD_OPC_FilterValue, 31, 61, 0, 1, // Skip to: 86948 +/* 21351 */ MCD_OPC_CheckPredicate, 0, 56, 0, 1, // Skip to: 86948 +/* 21356 */ MCD_OPC_Decode, 137, 9, 5, // Opcode: FCVTZU_ZPmZ_DtoD +/* 21360 */ MCD_OPC_FilterValue, 3, 47, 0, 1, // Skip to: 86948 +/* 21365 */ MCD_OPC_CheckPredicate, 0, 42, 0, 1, // Skip to: 86948 +/* 21370 */ MCD_OPC_Decode, 239, 10, 6, // Opcode: FMSB_ZPmZZ_D +/* 21374 */ MCD_OPC_FilterValue, 6, 103, 0, 0, // Skip to: 21482 +/* 21379 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 21382 */ MCD_OPC_FilterValue, 0, 31, 0, 0, // Skip to: 21418 +/* 21387 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 21390 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21404 +/* 21395 */ MCD_OPC_CheckPredicate, 0, 12, 0, 1, // Skip to: 86948 +/* 21400 */ MCD_OPC_Decode, 210, 7, 81, // Opcode: FCMUO_PPzZZ_S +/* 21404 */ MCD_OPC_FilterValue, 1, 3, 0, 1, // Skip to: 86948 +/* 21409 */ MCD_OPC_CheckPredicate, 0, 254, 255, 0, // Skip to: 86948 +/* 21414 */ MCD_OPC_Decode, 155, 6, 81, // Opcode: FACGE_PPzZZ_S +/* 21418 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21432 +/* 21423 */ MCD_OPC_CheckPredicate, 0, 240, 255, 0, // Skip to: 86948 +/* 21428 */ MCD_OPC_Decode, 180, 11, 6, // Opcode: FNMAD_ZPmZZ_S +/* 21432 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21468 +/* 21437 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 21440 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21454 +/* 21445 */ MCD_OPC_CheckPredicate, 0, 218, 255, 0, // Skip to: 86948 +/* 21450 */ MCD_OPC_Decode, 208, 7, 81, // Opcode: FCMUO_PPzZZ_D +/* 21454 */ MCD_OPC_FilterValue, 1, 209, 255, 0, // Skip to: 86948 +/* 21459 */ MCD_OPC_CheckPredicate, 0, 204, 255, 0, // Skip to: 86948 +/* 21464 */ MCD_OPC_Decode, 153, 6, 81, // Opcode: FACGE_PPzZZ_D +/* 21468 */ MCD_OPC_FilterValue, 3, 195, 255, 0, // Skip to: 86948 +/* 21473 */ MCD_OPC_CheckPredicate, 0, 190, 255, 0, // Skip to: 86948 +/* 21478 */ MCD_OPC_Decode, 178, 11, 6, // Opcode: FNMAD_ZPmZZ_D +/* 21482 */ MCD_OPC_FilterValue, 7, 181, 255, 0, // Skip to: 86948 +/* 21487 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 21490 */ MCD_OPC_FilterValue, 0, 16, 0, 0, // Skip to: 21511 +/* 21495 */ MCD_OPC_CheckPredicate, 0, 168, 255, 0, // Skip to: 86948 +/* 21500 */ MCD_OPC_CheckField, 4, 1, 1, 161, 255, 0, // Skip to: 86948 +/* 21507 */ MCD_OPC_Decode, 166, 6, 81, // Opcode: FACGT_PPzZZ_S +/* 21511 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 21525 +/* 21516 */ MCD_OPC_CheckPredicate, 0, 147, 255, 0, // Skip to: 86948 +/* 21521 */ MCD_OPC_Decode, 189, 11, 6, // Opcode: FNMSB_ZPmZZ_S +/* 21525 */ MCD_OPC_FilterValue, 2, 16, 0, 0, // Skip to: 21546 +/* 21530 */ MCD_OPC_CheckPredicate, 0, 133, 255, 0, // Skip to: 86948 +/* 21535 */ MCD_OPC_CheckField, 4, 1, 1, 126, 255, 0, // Skip to: 86948 +/* 21542 */ MCD_OPC_Decode, 164, 6, 81, // Opcode: FACGT_PPzZZ_D +/* 21546 */ MCD_OPC_FilterValue, 3, 117, 255, 0, // Skip to: 86948 +/* 21551 */ MCD_OPC_CheckPredicate, 0, 112, 255, 0, // Skip to: 86948 +/* 21556 */ MCD_OPC_Decode, 187, 11, 6, // Opcode: FNMSB_ZPmZZ_D +/* 21560 */ MCD_OPC_FilterValue, 4, 96, 6, 0, // Skip to: 23197 +/* 21565 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 21568 */ MCD_OPC_FilterValue, 0, 207, 0, 0, // Skip to: 21780 +/* 21573 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 21576 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 21620 +/* 21581 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21584 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21598 +/* 21589 */ MCD_OPC_CheckPredicate, 0, 74, 255, 0, // Skip to: 86948 +/* 21594 */ MCD_OPC_Decode, 145, 13, 127, // Opcode: GLD1SB_S_UXTW_REAL +/* 21598 */ MCD_OPC_FilterValue, 1, 65, 255, 0, // Skip to: 86948 +/* 21603 */ MCD_OPC_CheckPredicate, 0, 60, 255, 0, // Skip to: 86948 +/* 21608 */ MCD_OPC_CheckField, 4, 1, 0, 53, 255, 0, // Skip to: 86948 +/* 21615 */ MCD_OPC_Decode, 133, 21, 128, 1, // Opcode: PRFB_S_UXTW_SCALED +/* 21620 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 21664 +/* 21625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21628 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21642 +/* 21633 */ MCD_OPC_CheckPredicate, 0, 30, 255, 0, // Skip to: 86948 +/* 21638 */ MCD_OPC_Decode, 144, 13, 127, // Opcode: GLD1SB_S_SXTW_REAL +/* 21642 */ MCD_OPC_FilterValue, 1, 21, 255, 0, // Skip to: 86948 +/* 21647 */ MCD_OPC_CheckPredicate, 0, 16, 255, 0, // Skip to: 86948 +/* 21652 */ MCD_OPC_CheckField, 4, 1, 0, 9, 255, 0, // Skip to: 86948 +/* 21659 */ MCD_OPC_Decode, 132, 21, 128, 1, // Opcode: PRFB_S_SXTW_SCALED +/* 21664 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21700 +/* 21669 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21672 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21686 +/* 21677 */ MCD_OPC_CheckPredicate, 0, 242, 254, 0, // Skip to: 86948 +/* 21682 */ MCD_OPC_Decode, 156, 13, 127, // Opcode: GLD1SH_S_UXTW_REAL +/* 21686 */ MCD_OPC_FilterValue, 1, 233, 254, 0, // Skip to: 86948 +/* 21691 */ MCD_OPC_CheckPredicate, 0, 228, 254, 0, // Skip to: 86948 +/* 21696 */ MCD_OPC_Decode, 157, 13, 127, // Opcode: GLD1SH_S_UXTW_SCALED_REAL +/* 21700 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 21736 +/* 21705 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21708 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21722 +/* 21713 */ MCD_OPC_CheckPredicate, 0, 206, 254, 0, // Skip to: 86948 +/* 21718 */ MCD_OPC_Decode, 154, 13, 127, // Opcode: GLD1SH_S_SXTW_REAL +/* 21722 */ MCD_OPC_FilterValue, 1, 197, 254, 0, // Skip to: 86948 +/* 21727 */ MCD_OPC_CheckPredicate, 0, 192, 254, 0, // Skip to: 86948 +/* 21732 */ MCD_OPC_Decode, 155, 13, 127, // Opcode: GLD1SH_S_SXTW_SCALED_REAL +/* 21736 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 21758 +/* 21741 */ MCD_OPC_CheckPredicate, 0, 178, 254, 0, // Skip to: 86948 +/* 21746 */ MCD_OPC_CheckField, 4, 1, 0, 171, 254, 0, // Skip to: 86948 +/* 21753 */ MCD_OPC_Decode, 167, 18, 129, 1, // Opcode: LDR_PXI +/* 21758 */ MCD_OPC_FilterValue, 7, 161, 254, 0, // Skip to: 86948 +/* 21763 */ MCD_OPC_CheckPredicate, 0, 156, 254, 0, // Skip to: 86948 +/* 21768 */ MCD_OPC_CheckField, 4, 1, 0, 149, 254, 0, // Skip to: 86948 +/* 21775 */ MCD_OPC_Decode, 129, 21, 130, 1, // Opcode: PRFB_PRI +/* 21780 */ MCD_OPC_FilterValue, 1, 185, 0, 0, // Skip to: 21970 +/* 21785 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 21788 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 21832 +/* 21793 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21796 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21810 +/* 21801 */ MCD_OPC_CheckPredicate, 0, 118, 254, 0, // Skip to: 86948 +/* 21806 */ MCD_OPC_Decode, 209, 13, 127, // Opcode: GLDFF1SB_S_UXTW_REAL +/* 21810 */ MCD_OPC_FilterValue, 1, 109, 254, 0, // Skip to: 86948 +/* 21815 */ MCD_OPC_CheckPredicate, 0, 104, 254, 0, // Skip to: 86948 +/* 21820 */ MCD_OPC_CheckField, 4, 1, 0, 97, 254, 0, // Skip to: 86948 +/* 21827 */ MCD_OPC_Decode, 151, 21, 128, 1, // Opcode: PRFH_S_UXTW_SCALED +/* 21832 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 21876 +/* 21837 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21840 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21854 +/* 21845 */ MCD_OPC_CheckPredicate, 0, 74, 254, 0, // Skip to: 86948 +/* 21850 */ MCD_OPC_Decode, 208, 13, 127, // Opcode: GLDFF1SB_S_SXTW_REAL +/* 21854 */ MCD_OPC_FilterValue, 1, 65, 254, 0, // Skip to: 86948 +/* 21859 */ MCD_OPC_CheckPredicate, 0, 60, 254, 0, // Skip to: 86948 +/* 21864 */ MCD_OPC_CheckField, 4, 1, 0, 53, 254, 0, // Skip to: 86948 +/* 21871 */ MCD_OPC_Decode, 150, 21, 128, 1, // Opcode: PRFH_S_SXTW_SCALED +/* 21876 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 21912 +/* 21881 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21884 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21898 +/* 21889 */ MCD_OPC_CheckPredicate, 0, 30, 254, 0, // Skip to: 86948 +/* 21894 */ MCD_OPC_Decode, 220, 13, 127, // Opcode: GLDFF1SH_S_UXTW_REAL +/* 21898 */ MCD_OPC_FilterValue, 1, 21, 254, 0, // Skip to: 86948 +/* 21903 */ MCD_OPC_CheckPredicate, 0, 16, 254, 0, // Skip to: 86948 +/* 21908 */ MCD_OPC_Decode, 221, 13, 127, // Opcode: GLDFF1SH_S_UXTW_SCALED_REAL +/* 21912 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 21948 +/* 21917 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21920 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 21934 +/* 21925 */ MCD_OPC_CheckPredicate, 0, 250, 253, 0, // Skip to: 86948 +/* 21930 */ MCD_OPC_Decode, 218, 13, 127, // Opcode: GLDFF1SH_S_SXTW_REAL +/* 21934 */ MCD_OPC_FilterValue, 1, 241, 253, 0, // Skip to: 86948 +/* 21939 */ MCD_OPC_CheckPredicate, 0, 236, 253, 0, // Skip to: 86948 +/* 21944 */ MCD_OPC_Decode, 219, 13, 127, // Opcode: GLDFF1SH_S_SXTW_SCALED_REAL +/* 21948 */ MCD_OPC_FilterValue, 7, 227, 253, 0, // Skip to: 86948 +/* 21953 */ MCD_OPC_CheckPredicate, 0, 222, 253, 0, // Skip to: 86948 +/* 21958 */ MCD_OPC_CheckField, 4, 1, 0, 215, 253, 0, // Skip to: 86948 +/* 21965 */ MCD_OPC_Decode, 147, 21, 130, 1, // Opcode: PRFH_PRI +/* 21970 */ MCD_OPC_FilterValue, 2, 16, 1, 0, // Skip to: 22247 +/* 21975 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 21978 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 22022 +/* 21983 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 21986 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22000 +/* 21991 */ MCD_OPC_CheckPredicate, 0, 184, 253, 0, // Skip to: 86948 +/* 21996 */ MCD_OPC_Decode, 247, 12, 127, // Opcode: GLD1B_S_UXTW_REAL +/* 22000 */ MCD_OPC_FilterValue, 1, 175, 253, 0, // Skip to: 86948 +/* 22005 */ MCD_OPC_CheckPredicate, 0, 170, 253, 0, // Skip to: 86948 +/* 22010 */ MCD_OPC_CheckField, 4, 1, 0, 163, 253, 0, // Skip to: 86948 +/* 22017 */ MCD_OPC_Decode, 165, 21, 128, 1, // Opcode: PRFW_S_UXTW_SCALED +/* 22022 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 22066 +/* 22027 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22030 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22044 +/* 22035 */ MCD_OPC_CheckPredicate, 0, 140, 253, 0, // Skip to: 86948 +/* 22040 */ MCD_OPC_Decode, 246, 12, 127, // Opcode: GLD1B_S_SXTW_REAL +/* 22044 */ MCD_OPC_FilterValue, 1, 131, 253, 0, // Skip to: 86948 +/* 22049 */ MCD_OPC_CheckPredicate, 0, 126, 253, 0, // Skip to: 86948 +/* 22054 */ MCD_OPC_CheckField, 4, 1, 0, 119, 253, 0, // Skip to: 86948 +/* 22061 */ MCD_OPC_Decode, 164, 21, 128, 1, // Opcode: PRFW_S_SXTW_SCALED +/* 22066 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 22102 +/* 22071 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22074 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22088 +/* 22079 */ MCD_OPC_CheckPredicate, 0, 96, 253, 0, // Skip to: 86948 +/* 22084 */ MCD_OPC_Decode, 137, 13, 127, // Opcode: GLD1H_S_UXTW_REAL +/* 22088 */ MCD_OPC_FilterValue, 1, 87, 253, 0, // Skip to: 86948 +/* 22093 */ MCD_OPC_CheckPredicate, 0, 82, 253, 0, // Skip to: 86948 +/* 22098 */ MCD_OPC_Decode, 138, 13, 127, // Opcode: GLD1H_S_UXTW_SCALED_REAL +/* 22102 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 22138 +/* 22107 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22110 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22124 +/* 22115 */ MCD_OPC_CheckPredicate, 0, 60, 253, 0, // Skip to: 86948 +/* 22120 */ MCD_OPC_Decode, 135, 13, 127, // Opcode: GLD1H_S_SXTW_REAL +/* 22124 */ MCD_OPC_FilterValue, 1, 51, 253, 0, // Skip to: 86948 +/* 22129 */ MCD_OPC_CheckPredicate, 0, 46, 253, 0, // Skip to: 86948 +/* 22134 */ MCD_OPC_Decode, 136, 13, 127, // Opcode: GLD1H_S_SXTW_SCALED_REAL +/* 22138 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 22174 +/* 22143 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22146 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22160 +/* 22151 */ MCD_OPC_CheckPredicate, 0, 24, 253, 0, // Skip to: 86948 +/* 22156 */ MCD_OPC_Decode, 175, 13, 127, // Opcode: GLD1W_UXTW_REAL +/* 22160 */ MCD_OPC_FilterValue, 1, 15, 253, 0, // Skip to: 86948 +/* 22165 */ MCD_OPC_CheckPredicate, 0, 10, 253, 0, // Skip to: 86948 +/* 22170 */ MCD_OPC_Decode, 176, 13, 127, // Opcode: GLD1W_UXTW_SCALED_REAL +/* 22174 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 22210 +/* 22179 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22182 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22196 +/* 22187 */ MCD_OPC_CheckPredicate, 0, 244, 252, 0, // Skip to: 86948 +/* 22192 */ MCD_OPC_Decode, 173, 13, 127, // Opcode: GLD1W_SXTW_REAL +/* 22196 */ MCD_OPC_FilterValue, 1, 235, 252, 0, // Skip to: 86948 +/* 22201 */ MCD_OPC_CheckPredicate, 0, 230, 252, 0, // Skip to: 86948 +/* 22206 */ MCD_OPC_Decode, 174, 13, 127, // Opcode: GLD1W_SXTW_SCALED_REAL +/* 22210 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 22225 +/* 22215 */ MCD_OPC_CheckPredicate, 0, 216, 252, 0, // Skip to: 86948 +/* 22220 */ MCD_OPC_Decode, 168, 18, 131, 1, // Opcode: LDR_ZXI +/* 22225 */ MCD_OPC_FilterValue, 7, 206, 252, 0, // Skip to: 86948 +/* 22230 */ MCD_OPC_CheckPredicate, 0, 201, 252, 0, // Skip to: 86948 +/* 22235 */ MCD_OPC_CheckField, 4, 1, 0, 194, 252, 0, // Skip to: 86948 +/* 22242 */ MCD_OPC_Decode, 162, 21, 130, 1, // Opcode: PRFW_PRI +/* 22247 */ MCD_OPC_FilterValue, 3, 1, 1, 0, // Skip to: 22509 +/* 22252 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 22255 */ MCD_OPC_FilterValue, 0, 39, 0, 0, // Skip to: 22299 +/* 22260 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22263 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22277 +/* 22268 */ MCD_OPC_CheckPredicate, 0, 163, 252, 0, // Skip to: 86948 +/* 22273 */ MCD_OPC_Decode, 183, 13, 127, // Opcode: GLDFF1B_S_UXTW_REAL +/* 22277 */ MCD_OPC_FilterValue, 1, 154, 252, 0, // Skip to: 86948 +/* 22282 */ MCD_OPC_CheckPredicate, 0, 149, 252, 0, // Skip to: 86948 +/* 22287 */ MCD_OPC_CheckField, 4, 1, 0, 142, 252, 0, // Skip to: 86948 +/* 22294 */ MCD_OPC_Decode, 142, 21, 128, 1, // Opcode: PRFD_S_UXTW_SCALED +/* 22299 */ MCD_OPC_FilterValue, 1, 39, 0, 0, // Skip to: 22343 +/* 22304 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22307 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22321 +/* 22312 */ MCD_OPC_CheckPredicate, 0, 119, 252, 0, // Skip to: 86948 +/* 22317 */ MCD_OPC_Decode, 182, 13, 127, // Opcode: GLDFF1B_S_SXTW_REAL +/* 22321 */ MCD_OPC_FilterValue, 1, 110, 252, 0, // Skip to: 86948 +/* 22326 */ MCD_OPC_CheckPredicate, 0, 105, 252, 0, // Skip to: 86948 +/* 22331 */ MCD_OPC_CheckField, 4, 1, 0, 98, 252, 0, // Skip to: 86948 +/* 22338 */ MCD_OPC_Decode, 141, 21, 128, 1, // Opcode: PRFD_S_SXTW_SCALED +/* 22343 */ MCD_OPC_FilterValue, 2, 31, 0, 0, // Skip to: 22379 +/* 22348 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22351 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22365 +/* 22356 */ MCD_OPC_CheckPredicate, 0, 75, 252, 0, // Skip to: 86948 +/* 22361 */ MCD_OPC_Decode, 201, 13, 127, // Opcode: GLDFF1H_S_UXTW_REAL +/* 22365 */ MCD_OPC_FilterValue, 1, 66, 252, 0, // Skip to: 86948 +/* 22370 */ MCD_OPC_CheckPredicate, 0, 61, 252, 0, // Skip to: 86948 +/* 22375 */ MCD_OPC_Decode, 202, 13, 127, // Opcode: GLDFF1H_S_UXTW_SCALED_REAL +/* 22379 */ MCD_OPC_FilterValue, 3, 31, 0, 0, // Skip to: 22415 +/* 22384 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22387 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22401 +/* 22392 */ MCD_OPC_CheckPredicate, 0, 39, 252, 0, // Skip to: 86948 +/* 22397 */ MCD_OPC_Decode, 199, 13, 127, // Opcode: GLDFF1H_S_SXTW_REAL +/* 22401 */ MCD_OPC_FilterValue, 1, 30, 252, 0, // Skip to: 86948 +/* 22406 */ MCD_OPC_CheckPredicate, 0, 25, 252, 0, // Skip to: 86948 +/* 22411 */ MCD_OPC_Decode, 200, 13, 127, // Opcode: GLDFF1H_S_SXTW_SCALED_REAL +/* 22415 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 22451 +/* 22420 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22423 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22437 +/* 22428 */ MCD_OPC_CheckPredicate, 0, 3, 252, 0, // Skip to: 86948 +/* 22433 */ MCD_OPC_Decode, 239, 13, 127, // Opcode: GLDFF1W_UXTW_REAL +/* 22437 */ MCD_OPC_FilterValue, 1, 250, 251, 0, // Skip to: 86948 +/* 22442 */ MCD_OPC_CheckPredicate, 0, 245, 251, 0, // Skip to: 86948 +/* 22447 */ MCD_OPC_Decode, 240, 13, 127, // Opcode: GLDFF1W_UXTW_SCALED_REAL +/* 22451 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 22487 +/* 22456 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22459 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 22473 +/* 22464 */ MCD_OPC_CheckPredicate, 0, 223, 251, 0, // Skip to: 86948 +/* 22469 */ MCD_OPC_Decode, 237, 13, 127, // Opcode: GLDFF1W_SXTW_REAL +/* 22473 */ MCD_OPC_FilterValue, 1, 214, 251, 0, // Skip to: 86948 +/* 22478 */ MCD_OPC_CheckPredicate, 0, 209, 251, 0, // Skip to: 86948 +/* 22483 */ MCD_OPC_Decode, 238, 13, 127, // Opcode: GLDFF1W_SXTW_SCALED_REAL +/* 22487 */ MCD_OPC_FilterValue, 7, 200, 251, 0, // Skip to: 86948 +/* 22492 */ MCD_OPC_CheckPredicate, 0, 195, 251, 0, // Skip to: 86948 +/* 22497 */ MCD_OPC_CheckField, 4, 1, 0, 188, 251, 0, // Skip to: 86948 +/* 22504 */ MCD_OPC_Decode, 138, 21, 130, 1, // Opcode: PRFD_PRI +/* 22509 */ MCD_OPC_FilterValue, 4, 107, 0, 0, // Skip to: 22621 +/* 22514 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 22517 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22539 +/* 22522 */ MCD_OPC_CheckPredicate, 0, 165, 251, 0, // Skip to: 86948 +/* 22527 */ MCD_OPC_CheckField, 21, 1, 1, 158, 251, 0, // Skip to: 86948 +/* 22534 */ MCD_OPC_Decode, 143, 13, 132, 1, // Opcode: GLD1SB_S_IMM_REAL +/* 22539 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22554 +/* 22544 */ MCD_OPC_CheckPredicate, 0, 143, 251, 0, // Skip to: 86948 +/* 22549 */ MCD_OPC_Decode, 229, 14, 133, 1, // Opcode: LD1RB_IMM +/* 22554 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 22576 +/* 22559 */ MCD_OPC_CheckPredicate, 0, 128, 251, 0, // Skip to: 86948 +/* 22564 */ MCD_OPC_CheckField, 21, 1, 1, 121, 251, 0, // Skip to: 86948 +/* 22571 */ MCD_OPC_Decode, 153, 13, 132, 1, // Opcode: GLD1SH_S_IMM_REAL +/* 22576 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22591 +/* 22581 */ MCD_OPC_CheckPredicate, 0, 106, 251, 0, // Skip to: 86948 +/* 22586 */ MCD_OPC_Decode, 248, 14, 133, 1, // Opcode: LD1RSW_IMM +/* 22591 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22606 +/* 22596 */ MCD_OPC_CheckPredicate, 0, 91, 251, 0, // Skip to: 86948 +/* 22601 */ MCD_OPC_Decode, 246, 14, 133, 1, // Opcode: LD1RSH_D_IMM +/* 22606 */ MCD_OPC_FilterValue, 7, 81, 251, 0, // Skip to: 86948 +/* 22611 */ MCD_OPC_CheckPredicate, 0, 76, 251, 0, // Skip to: 86948 +/* 22616 */ MCD_OPC_Decode, 243, 14, 133, 1, // Opcode: LD1RSB_D_IMM +/* 22621 */ MCD_OPC_FilterValue, 5, 107, 0, 0, // Skip to: 22733 +/* 22626 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 22629 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22651 +/* 22634 */ MCD_OPC_CheckPredicate, 0, 53, 251, 0, // Skip to: 86948 +/* 22639 */ MCD_OPC_CheckField, 21, 1, 1, 46, 251, 0, // Skip to: 86948 +/* 22646 */ MCD_OPC_Decode, 207, 13, 132, 1, // Opcode: GLDFF1SB_S_IMM_REAL +/* 22651 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22666 +/* 22656 */ MCD_OPC_CheckPredicate, 0, 31, 251, 0, // Skip to: 86948 +/* 22661 */ MCD_OPC_Decode, 228, 14, 133, 1, // Opcode: LD1RB_H_IMM +/* 22666 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 22688 +/* 22671 */ MCD_OPC_CheckPredicate, 0, 16, 251, 0, // Skip to: 86948 +/* 22676 */ MCD_OPC_CheckField, 21, 1, 1, 9, 251, 0, // Skip to: 86948 +/* 22683 */ MCD_OPC_Decode, 217, 13, 132, 1, // Opcode: GLDFF1SH_S_IMM_REAL +/* 22688 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22703 +/* 22693 */ MCD_OPC_CheckPredicate, 0, 250, 250, 0, // Skip to: 86948 +/* 22698 */ MCD_OPC_Decode, 233, 14, 133, 1, // Opcode: LD1RH_IMM +/* 22703 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22718 +/* 22708 */ MCD_OPC_CheckPredicate, 0, 235, 250, 0, // Skip to: 86948 +/* 22713 */ MCD_OPC_Decode, 247, 14, 133, 1, // Opcode: LD1RSH_S_IMM +/* 22718 */ MCD_OPC_FilterValue, 7, 225, 250, 0, // Skip to: 86948 +/* 22723 */ MCD_OPC_CheckPredicate, 0, 220, 250, 0, // Skip to: 86948 +/* 22728 */ MCD_OPC_Decode, 245, 14, 133, 1, // Opcode: LD1RSB_S_IMM +/* 22733 */ MCD_OPC_FilterValue, 6, 227, 0, 0, // Skip to: 22965 +/* 22738 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 22741 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 22786 +/* 22746 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22749 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22771 +/* 22754 */ MCD_OPC_CheckPredicate, 0, 189, 250, 0, // Skip to: 86948 +/* 22759 */ MCD_OPC_CheckField, 4, 1, 0, 182, 250, 0, // Skip to: 86948 +/* 22766 */ MCD_OPC_Decode, 130, 21, 134, 1, // Opcode: PRFB_PRR +/* 22771 */ MCD_OPC_FilterValue, 1, 172, 250, 0, // Skip to: 86948 +/* 22776 */ MCD_OPC_CheckPredicate, 0, 167, 250, 0, // Skip to: 86948 +/* 22781 */ MCD_OPC_Decode, 245, 12, 132, 1, // Opcode: GLD1B_S_IMM_REAL +/* 22786 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 22801 +/* 22791 */ MCD_OPC_CheckPredicate, 0, 152, 250, 0, // Skip to: 86948 +/* 22796 */ MCD_OPC_Decode, 230, 14, 133, 1, // Opcode: LD1RB_S_IMM +/* 22801 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 22846 +/* 22806 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22809 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22831 +/* 22814 */ MCD_OPC_CheckPredicate, 0, 129, 250, 0, // Skip to: 86948 +/* 22819 */ MCD_OPC_CheckField, 4, 1, 0, 122, 250, 0, // Skip to: 86948 +/* 22826 */ MCD_OPC_Decode, 148, 21, 134, 1, // Opcode: PRFH_PRR +/* 22831 */ MCD_OPC_FilterValue, 1, 112, 250, 0, // Skip to: 86948 +/* 22836 */ MCD_OPC_CheckPredicate, 0, 107, 250, 0, // Skip to: 86948 +/* 22841 */ MCD_OPC_Decode, 134, 13, 132, 1, // Opcode: GLD1H_S_IMM_REAL +/* 22846 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 22861 +/* 22851 */ MCD_OPC_CheckPredicate, 0, 92, 250, 0, // Skip to: 86948 +/* 22856 */ MCD_OPC_Decode, 234, 14, 133, 1, // Opcode: LD1RH_S_IMM +/* 22861 */ MCD_OPC_FilterValue, 4, 40, 0, 0, // Skip to: 22906 +/* 22866 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22869 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 22891 +/* 22874 */ MCD_OPC_CheckPredicate, 0, 69, 250, 0, // Skip to: 86948 +/* 22879 */ MCD_OPC_CheckField, 4, 1, 0, 62, 250, 0, // Skip to: 86948 +/* 22886 */ MCD_OPC_Decode, 156, 21, 134, 1, // Opcode: PRFS_PRR +/* 22891 */ MCD_OPC_FilterValue, 1, 52, 250, 0, // Skip to: 86948 +/* 22896 */ MCD_OPC_CheckPredicate, 0, 47, 250, 0, // Skip to: 86948 +/* 22901 */ MCD_OPC_Decode, 172, 13, 132, 1, // Opcode: GLD1W_IMM_REAL +/* 22906 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 22921 +/* 22911 */ MCD_OPC_CheckPredicate, 0, 32, 250, 0, // Skip to: 86948 +/* 22916 */ MCD_OPC_Decode, 250, 14, 133, 1, // Opcode: LD1RW_IMM +/* 22921 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 22950 +/* 22926 */ MCD_OPC_CheckPredicate, 0, 17, 250, 0, // Skip to: 86948 +/* 22931 */ MCD_OPC_CheckField, 21, 1, 0, 10, 250, 0, // Skip to: 86948 +/* 22938 */ MCD_OPC_CheckField, 4, 1, 0, 3, 250, 0, // Skip to: 86948 +/* 22945 */ MCD_OPC_Decode, 139, 21, 134, 1, // Opcode: PRFD_PRR +/* 22950 */ MCD_OPC_FilterValue, 7, 249, 249, 0, // Skip to: 86948 +/* 22955 */ MCD_OPC_CheckPredicate, 0, 244, 249, 0, // Skip to: 86948 +/* 22960 */ MCD_OPC_Decode, 244, 14, 133, 1, // Opcode: LD1RSB_H_IMM +/* 22965 */ MCD_OPC_FilterValue, 7, 234, 249, 0, // Skip to: 86948 +/* 22970 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 22973 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 23018 +/* 22978 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 22981 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23003 +/* 22986 */ MCD_OPC_CheckPredicate, 0, 213, 249, 0, // Skip to: 86948 +/* 22991 */ MCD_OPC_CheckField, 4, 1, 0, 206, 249, 0, // Skip to: 86948 +/* 22998 */ MCD_OPC_Decode, 131, 21, 135, 1, // Opcode: PRFB_S_PZI +/* 23003 */ MCD_OPC_FilterValue, 1, 196, 249, 0, // Skip to: 86948 +/* 23008 */ MCD_OPC_CheckPredicate, 0, 191, 249, 0, // Skip to: 86948 +/* 23013 */ MCD_OPC_Decode, 181, 13, 132, 1, // Opcode: GLDFF1B_S_IMM_REAL +/* 23018 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 23033 +/* 23023 */ MCD_OPC_CheckPredicate, 0, 176, 249, 0, // Skip to: 86948 +/* 23028 */ MCD_OPC_Decode, 227, 14, 133, 1, // Opcode: LD1RB_D_IMM +/* 23033 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 23078 +/* 23038 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 23041 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23063 +/* 23046 */ MCD_OPC_CheckPredicate, 0, 153, 249, 0, // Skip to: 86948 +/* 23051 */ MCD_OPC_CheckField, 4, 1, 0, 146, 249, 0, // Skip to: 86948 +/* 23058 */ MCD_OPC_Decode, 149, 21, 135, 1, // Opcode: PRFH_S_PZI +/* 23063 */ MCD_OPC_FilterValue, 1, 136, 249, 0, // Skip to: 86948 +/* 23068 */ MCD_OPC_CheckPredicate, 0, 131, 249, 0, // Skip to: 86948 +/* 23073 */ MCD_OPC_Decode, 198, 13, 132, 1, // Opcode: GLDFF1H_S_IMM_REAL +/* 23078 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23093 +/* 23083 */ MCD_OPC_CheckPredicate, 0, 116, 249, 0, // Skip to: 86948 +/* 23088 */ MCD_OPC_Decode, 232, 14, 133, 1, // Opcode: LD1RH_D_IMM +/* 23093 */ MCD_OPC_FilterValue, 4, 40, 0, 0, // Skip to: 23138 +/* 23098 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 23101 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 23123 +/* 23106 */ MCD_OPC_CheckPredicate, 0, 93, 249, 0, // Skip to: 86948 +/* 23111 */ MCD_OPC_CheckField, 4, 1, 0, 86, 249, 0, // Skip to: 86948 +/* 23118 */ MCD_OPC_Decode, 163, 21, 135, 1, // Opcode: PRFW_S_PZI +/* 23123 */ MCD_OPC_FilterValue, 1, 76, 249, 0, // Skip to: 86948 +/* 23128 */ MCD_OPC_CheckPredicate, 0, 71, 249, 0, // Skip to: 86948 +/* 23133 */ MCD_OPC_Decode, 236, 13, 132, 1, // Opcode: GLDFF1W_IMM_REAL +/* 23138 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 23153 +/* 23143 */ MCD_OPC_CheckPredicate, 0, 56, 249, 0, // Skip to: 86948 +/* 23148 */ MCD_OPC_Decode, 249, 14, 133, 1, // Opcode: LD1RW_D_IMM +/* 23153 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 23182 +/* 23158 */ MCD_OPC_CheckPredicate, 0, 41, 249, 0, // Skip to: 86948 +/* 23163 */ MCD_OPC_CheckField, 21, 1, 0, 34, 249, 0, // Skip to: 86948 +/* 23170 */ MCD_OPC_CheckField, 4, 1, 0, 27, 249, 0, // Skip to: 86948 +/* 23177 */ MCD_OPC_Decode, 140, 21, 135, 1, // Opcode: PRFD_S_PZI +/* 23182 */ MCD_OPC_FilterValue, 7, 17, 249, 0, // Skip to: 86948 +/* 23187 */ MCD_OPC_CheckPredicate, 0, 12, 249, 0, // Skip to: 86948 +/* 23192 */ MCD_OPC_Decode, 231, 14, 133, 1, // Opcode: LD1RD_IMM +/* 23197 */ MCD_OPC_FilterValue, 5, 167, 7, 0, // Skip to: 25161 +/* 23202 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 23205 */ MCD_OPC_FilterValue, 0, 145, 0, 0, // Skip to: 23355 +/* 23210 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23213 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23228 +/* 23218 */ MCD_OPC_CheckPredicate, 0, 237, 248, 0, // Skip to: 86948 +/* 23223 */ MCD_OPC_Decode, 235, 14, 136, 1, // Opcode: LD1RQ_B +/* 23228 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 23250 +/* 23233 */ MCD_OPC_CheckPredicate, 0, 222, 248, 0, // Skip to: 86948 +/* 23238 */ MCD_OPC_CheckField, 20, 1, 0, 215, 248, 0, // Skip to: 86948 +/* 23245 */ MCD_OPC_Decode, 236, 14, 137, 1, // Opcode: LD1RQ_B_IMM +/* 23250 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23265 +/* 23255 */ MCD_OPC_CheckPredicate, 0, 200, 248, 0, // Skip to: 86948 +/* 23260 */ MCD_OPC_Decode, 179, 14, 136, 1, // Opcode: LD1B +/* 23265 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23280 +/* 23270 */ MCD_OPC_CheckPredicate, 0, 185, 248, 0, // Skip to: 86948 +/* 23275 */ MCD_OPC_Decode, 150, 17, 138, 1, // Opcode: LDFF1B_REAL +/* 23280 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23318 +/* 23285 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 23288 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23303 +/* 23293 */ MCD_OPC_CheckPredicate, 0, 162, 248, 0, // Skip to: 86948 +/* 23298 */ MCD_OPC_Decode, 184, 14, 137, 1, // Opcode: LD1B_IMM_REAL +/* 23303 */ MCD_OPC_FilterValue, 1, 152, 248, 0, // Skip to: 86948 +/* 23308 */ MCD_OPC_CheckPredicate, 0, 147, 248, 0, // Skip to: 86948 +/* 23313 */ MCD_OPC_Decode, 170, 17, 137, 1, // Opcode: LDNF1B_IMM_REAL +/* 23318 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23333 +/* 23323 */ MCD_OPC_CheckPredicate, 0, 132, 248, 0, // Skip to: 86948 +/* 23328 */ MCD_OPC_Decode, 190, 17, 136, 1, // Opcode: LDNT1B_ZRR +/* 23333 */ MCD_OPC_FilterValue, 7, 122, 248, 0, // Skip to: 86948 +/* 23338 */ MCD_OPC_CheckPredicate, 0, 117, 248, 0, // Skip to: 86948 +/* 23343 */ MCD_OPC_CheckField, 20, 1, 0, 110, 248, 0, // Skip to: 86948 +/* 23350 */ MCD_OPC_Decode, 189, 17, 137, 1, // Opcode: LDNT1B_ZRI +/* 23355 */ MCD_OPC_FilterValue, 1, 108, 0, 0, // Skip to: 23468 +/* 23360 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23363 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23378 +/* 23368 */ MCD_OPC_CheckPredicate, 0, 87, 248, 0, // Skip to: 86948 +/* 23373 */ MCD_OPC_Decode, 182, 14, 136, 1, // Opcode: LD1B_H +/* 23378 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23393 +/* 23383 */ MCD_OPC_CheckPredicate, 0, 72, 248, 0, // Skip to: 86948 +/* 23388 */ MCD_OPC_Decode, 149, 17, 138, 1, // Opcode: LDFF1B_H_REAL +/* 23393 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23431 +/* 23398 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 23401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23416 +/* 23406 */ MCD_OPC_CheckPredicate, 0, 49, 248, 0, // Skip to: 86948 +/* 23411 */ MCD_OPC_Decode, 183, 14, 137, 1, // Opcode: LD1B_H_IMM_REAL +/* 23416 */ MCD_OPC_FilterValue, 1, 39, 248, 0, // Skip to: 86948 +/* 23421 */ MCD_OPC_CheckPredicate, 0, 34, 248, 0, // Skip to: 86948 +/* 23426 */ MCD_OPC_Decode, 169, 17, 137, 1, // Opcode: LDNF1B_H_IMM_REAL +/* 23431 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23446 +/* 23436 */ MCD_OPC_CheckPredicate, 0, 19, 248, 0, // Skip to: 86948 +/* 23441 */ MCD_OPC_Decode, 195, 15, 139, 1, // Opcode: LD2B +/* 23446 */ MCD_OPC_FilterValue, 7, 9, 248, 0, // Skip to: 86948 +/* 23451 */ MCD_OPC_CheckPredicate, 0, 4, 248, 0, // Skip to: 86948 +/* 23456 */ MCD_OPC_CheckField, 20, 1, 0, 253, 247, 0, // Skip to: 86948 +/* 23463 */ MCD_OPC_Decode, 196, 15, 140, 1, // Opcode: LD2B_IMM +/* 23468 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 23581 +/* 23473 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23476 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23491 +/* 23481 */ MCD_OPC_CheckPredicate, 0, 230, 247, 0, // Skip to: 86948 +/* 23486 */ MCD_OPC_Decode, 185, 14, 136, 1, // Opcode: LD1B_S +/* 23491 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23506 +/* 23496 */ MCD_OPC_CheckPredicate, 0, 215, 247, 0, // Skip to: 86948 +/* 23501 */ MCD_OPC_Decode, 151, 17, 138, 1, // Opcode: LDFF1B_S_REAL +/* 23506 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23544 +/* 23511 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 23514 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23529 +/* 23519 */ MCD_OPC_CheckPredicate, 0, 192, 247, 0, // Skip to: 86948 +/* 23524 */ MCD_OPC_Decode, 186, 14, 137, 1, // Opcode: LD1B_S_IMM_REAL +/* 23529 */ MCD_OPC_FilterValue, 1, 182, 247, 0, // Skip to: 86948 +/* 23534 */ MCD_OPC_CheckPredicate, 0, 177, 247, 0, // Skip to: 86948 +/* 23539 */ MCD_OPC_Decode, 171, 17, 137, 1, // Opcode: LDNF1B_S_IMM_REAL +/* 23544 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23559 +/* 23549 */ MCD_OPC_CheckPredicate, 0, 162, 247, 0, // Skip to: 86948 +/* 23554 */ MCD_OPC_Decode, 241, 15, 141, 1, // Opcode: LD3B +/* 23559 */ MCD_OPC_FilterValue, 7, 152, 247, 0, // Skip to: 86948 +/* 23564 */ MCD_OPC_CheckPredicate, 0, 147, 247, 0, // Skip to: 86948 +/* 23569 */ MCD_OPC_CheckField, 20, 1, 0, 140, 247, 0, // Skip to: 86948 +/* 23576 */ MCD_OPC_Decode, 242, 15, 142, 1, // Opcode: LD3B_IMM +/* 23581 */ MCD_OPC_FilterValue, 3, 108, 0, 0, // Skip to: 23694 +/* 23586 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23589 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23604 +/* 23594 */ MCD_OPC_CheckPredicate, 0, 117, 247, 0, // Skip to: 86948 +/* 23599 */ MCD_OPC_Decode, 180, 14, 136, 1, // Opcode: LD1B_D +/* 23604 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23619 +/* 23609 */ MCD_OPC_CheckPredicate, 0, 102, 247, 0, // Skip to: 86948 +/* 23614 */ MCD_OPC_Decode, 148, 17, 138, 1, // Opcode: LDFF1B_D_REAL +/* 23619 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23657 +/* 23624 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 23627 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23642 +/* 23632 */ MCD_OPC_CheckPredicate, 0, 79, 247, 0, // Skip to: 86948 +/* 23637 */ MCD_OPC_Decode, 181, 14, 137, 1, // Opcode: LD1B_D_IMM_REAL +/* 23642 */ MCD_OPC_FilterValue, 1, 69, 247, 0, // Skip to: 86948 +/* 23647 */ MCD_OPC_CheckPredicate, 0, 64, 247, 0, // Skip to: 86948 +/* 23652 */ MCD_OPC_Decode, 168, 17, 137, 1, // Opcode: LDNF1B_D_IMM_REAL +/* 23657 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23672 +/* 23662 */ MCD_OPC_CheckPredicate, 0, 49, 247, 0, // Skip to: 86948 +/* 23667 */ MCD_OPC_Decode, 159, 16, 143, 1, // Opcode: LD4B +/* 23672 */ MCD_OPC_FilterValue, 7, 39, 247, 0, // Skip to: 86948 +/* 23677 */ MCD_OPC_CheckPredicate, 0, 34, 247, 0, // Skip to: 86948 +/* 23682 */ MCD_OPC_CheckField, 20, 1, 0, 27, 247, 0, // Skip to: 86948 +/* 23689 */ MCD_OPC_Decode, 160, 16, 144, 1, // Opcode: LD4B_IMM +/* 23694 */ MCD_OPC_FilterValue, 4, 145, 0, 0, // Skip to: 23844 +/* 23699 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23702 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23717 +/* 23707 */ MCD_OPC_CheckPredicate, 0, 4, 247, 0, // Skip to: 86948 +/* 23712 */ MCD_OPC_Decode, 239, 14, 136, 1, // Opcode: LD1RQ_H +/* 23717 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 23739 +/* 23722 */ MCD_OPC_CheckPredicate, 0, 245, 246, 0, // Skip to: 86948 +/* 23727 */ MCD_OPC_CheckField, 20, 1, 0, 238, 246, 0, // Skip to: 86948 +/* 23734 */ MCD_OPC_Decode, 240, 14, 137, 1, // Opcode: LD1RQ_H_IMM +/* 23739 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23754 +/* 23744 */ MCD_OPC_CheckPredicate, 0, 223, 246, 0, // Skip to: 86948 +/* 23749 */ MCD_OPC_Decode, 149, 15, 136, 1, // Opcode: LD1SW_D +/* 23754 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23769 +/* 23759 */ MCD_OPC_CheckPredicate, 0, 208, 246, 0, // Skip to: 86948 +/* 23764 */ MCD_OPC_Decode, 161, 17, 138, 1, // Opcode: LDFF1SW_D_REAL +/* 23769 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23807 +/* 23774 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 23777 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23792 +/* 23782 */ MCD_OPC_CheckPredicate, 0, 185, 246, 0, // Skip to: 86948 +/* 23787 */ MCD_OPC_Decode, 150, 15, 137, 1, // Opcode: LD1SW_D_IMM_REAL +/* 23792 */ MCD_OPC_FilterValue, 1, 175, 246, 0, // Skip to: 86948 +/* 23797 */ MCD_OPC_CheckPredicate, 0, 170, 246, 0, // Skip to: 86948 +/* 23802 */ MCD_OPC_Decode, 181, 17, 137, 1, // Opcode: LDNF1SW_D_IMM_REAL +/* 23807 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23822 +/* 23812 */ MCD_OPC_CheckPredicate, 0, 155, 246, 0, // Skip to: 86948 +/* 23817 */ MCD_OPC_Decode, 194, 17, 136, 1, // Opcode: LDNT1H_ZRR +/* 23822 */ MCD_OPC_FilterValue, 7, 145, 246, 0, // Skip to: 86948 +/* 23827 */ MCD_OPC_CheckPredicate, 0, 140, 246, 0, // Skip to: 86948 +/* 23832 */ MCD_OPC_CheckField, 20, 1, 0, 133, 246, 0, // Skip to: 86948 +/* 23839 */ MCD_OPC_Decode, 193, 17, 137, 1, // Opcode: LDNT1H_ZRI +/* 23844 */ MCD_OPC_FilterValue, 5, 108, 0, 0, // Skip to: 23957 +/* 23849 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23852 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23867 +/* 23857 */ MCD_OPC_CheckPredicate, 0, 110, 246, 0, // Skip to: 86948 +/* 23862 */ MCD_OPC_Decode, 205, 14, 136, 1, // Opcode: LD1H +/* 23867 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23882 +/* 23872 */ MCD_OPC_CheckPredicate, 0, 95, 246, 0, // Skip to: 86948 +/* 23877 */ MCD_OPC_Decode, 154, 17, 138, 1, // Opcode: LDFF1H_REAL +/* 23882 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 23920 +/* 23887 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 23890 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 23905 +/* 23895 */ MCD_OPC_CheckPredicate, 0, 72, 246, 0, // Skip to: 86948 +/* 23900 */ MCD_OPC_Decode, 208, 14, 137, 1, // Opcode: LD1H_IMM_REAL +/* 23905 */ MCD_OPC_FilterValue, 1, 62, 246, 0, // Skip to: 86948 +/* 23910 */ MCD_OPC_CheckPredicate, 0, 57, 246, 0, // Skip to: 86948 +/* 23915 */ MCD_OPC_Decode, 174, 17, 137, 1, // Opcode: LDNF1H_IMM_REAL +/* 23920 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 23935 +/* 23925 */ MCD_OPC_CheckPredicate, 0, 42, 246, 0, // Skip to: 86948 +/* 23930 */ MCD_OPC_Decode, 199, 15, 139, 1, // Opcode: LD2H +/* 23935 */ MCD_OPC_FilterValue, 7, 32, 246, 0, // Skip to: 86948 +/* 23940 */ MCD_OPC_CheckPredicate, 0, 27, 246, 0, // Skip to: 86948 +/* 23945 */ MCD_OPC_CheckField, 20, 1, 0, 20, 246, 0, // Skip to: 86948 +/* 23952 */ MCD_OPC_Decode, 200, 15, 140, 1, // Opcode: LD2H_IMM +/* 23957 */ MCD_OPC_FilterValue, 6, 108, 0, 0, // Skip to: 24070 +/* 23962 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 23965 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 23980 +/* 23970 */ MCD_OPC_CheckPredicate, 0, 253, 245, 0, // Skip to: 86948 +/* 23975 */ MCD_OPC_Decode, 209, 14, 136, 1, // Opcode: LD1H_S +/* 23980 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 23995 +/* 23985 */ MCD_OPC_CheckPredicate, 0, 238, 245, 0, // Skip to: 86948 +/* 23990 */ MCD_OPC_Decode, 155, 17, 138, 1, // Opcode: LDFF1H_S_REAL +/* 23995 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24033 +/* 24000 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24003 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24018 +/* 24008 */ MCD_OPC_CheckPredicate, 0, 215, 245, 0, // Skip to: 86948 +/* 24013 */ MCD_OPC_Decode, 210, 14, 137, 1, // Opcode: LD1H_S_IMM_REAL +/* 24018 */ MCD_OPC_FilterValue, 1, 205, 245, 0, // Skip to: 86948 +/* 24023 */ MCD_OPC_CheckPredicate, 0, 200, 245, 0, // Skip to: 86948 +/* 24028 */ MCD_OPC_Decode, 175, 17, 137, 1, // Opcode: LDNF1H_S_IMM_REAL +/* 24033 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24048 +/* 24038 */ MCD_OPC_CheckPredicate, 0, 185, 245, 0, // Skip to: 86948 +/* 24043 */ MCD_OPC_Decode, 245, 15, 141, 1, // Opcode: LD3H +/* 24048 */ MCD_OPC_FilterValue, 7, 175, 245, 0, // Skip to: 86948 +/* 24053 */ MCD_OPC_CheckPredicate, 0, 170, 245, 0, // Skip to: 86948 +/* 24058 */ MCD_OPC_CheckField, 20, 1, 0, 163, 245, 0, // Skip to: 86948 +/* 24065 */ MCD_OPC_Decode, 246, 15, 142, 1, // Opcode: LD3H_IMM +/* 24070 */ MCD_OPC_FilterValue, 7, 108, 0, 0, // Skip to: 24183 +/* 24075 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24078 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24093 +/* 24083 */ MCD_OPC_CheckPredicate, 0, 140, 245, 0, // Skip to: 86948 +/* 24088 */ MCD_OPC_Decode, 206, 14, 136, 1, // Opcode: LD1H_D +/* 24093 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24108 +/* 24098 */ MCD_OPC_CheckPredicate, 0, 125, 245, 0, // Skip to: 86948 +/* 24103 */ MCD_OPC_Decode, 153, 17, 138, 1, // Opcode: LDFF1H_D_REAL +/* 24108 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24146 +/* 24113 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24116 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24131 +/* 24121 */ MCD_OPC_CheckPredicate, 0, 102, 245, 0, // Skip to: 86948 +/* 24126 */ MCD_OPC_Decode, 207, 14, 137, 1, // Opcode: LD1H_D_IMM_REAL +/* 24131 */ MCD_OPC_FilterValue, 1, 92, 245, 0, // Skip to: 86948 +/* 24136 */ MCD_OPC_CheckPredicate, 0, 87, 245, 0, // Skip to: 86948 +/* 24141 */ MCD_OPC_Decode, 173, 17, 137, 1, // Opcode: LDNF1H_D_IMM_REAL +/* 24146 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24161 +/* 24151 */ MCD_OPC_CheckPredicate, 0, 72, 245, 0, // Skip to: 86948 +/* 24156 */ MCD_OPC_Decode, 177, 16, 143, 1, // Opcode: LD4H +/* 24161 */ MCD_OPC_FilterValue, 7, 62, 245, 0, // Skip to: 86948 +/* 24166 */ MCD_OPC_CheckPredicate, 0, 57, 245, 0, // Skip to: 86948 +/* 24171 */ MCD_OPC_CheckField, 20, 1, 0, 50, 245, 0, // Skip to: 86948 +/* 24178 */ MCD_OPC_Decode, 178, 16, 144, 1, // Opcode: LD4H_IMM +/* 24183 */ MCD_OPC_FilterValue, 8, 145, 0, 0, // Skip to: 24333 +/* 24188 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24191 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24206 +/* 24196 */ MCD_OPC_CheckPredicate, 0, 27, 245, 0, // Skip to: 86948 +/* 24201 */ MCD_OPC_Decode, 241, 14, 136, 1, // Opcode: LD1RQ_W +/* 24206 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24228 +/* 24211 */ MCD_OPC_CheckPredicate, 0, 12, 245, 0, // Skip to: 86948 +/* 24216 */ MCD_OPC_CheckField, 20, 1, 0, 5, 245, 0, // Skip to: 86948 +/* 24223 */ MCD_OPC_Decode, 242, 14, 137, 1, // Opcode: LD1RQ_W_IMM +/* 24228 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24243 +/* 24233 */ MCD_OPC_CheckPredicate, 0, 246, 244, 0, // Skip to: 86948 +/* 24238 */ MCD_OPC_Decode, 145, 15, 136, 1, // Opcode: LD1SH_D +/* 24243 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24258 +/* 24248 */ MCD_OPC_CheckPredicate, 0, 231, 244, 0, // Skip to: 86948 +/* 24253 */ MCD_OPC_Decode, 159, 17, 138, 1, // Opcode: LDFF1SH_D_REAL +/* 24258 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24296 +/* 24263 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24266 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24281 +/* 24271 */ MCD_OPC_CheckPredicate, 0, 208, 244, 0, // Skip to: 86948 +/* 24276 */ MCD_OPC_Decode, 146, 15, 137, 1, // Opcode: LD1SH_D_IMM_REAL +/* 24281 */ MCD_OPC_FilterValue, 1, 198, 244, 0, // Skip to: 86948 +/* 24286 */ MCD_OPC_CheckPredicate, 0, 193, 244, 0, // Skip to: 86948 +/* 24291 */ MCD_OPC_Decode, 179, 17, 137, 1, // Opcode: LDNF1SH_D_IMM_REAL +/* 24296 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24311 +/* 24301 */ MCD_OPC_CheckPredicate, 0, 178, 244, 0, // Skip to: 86948 +/* 24306 */ MCD_OPC_Decode, 196, 17, 136, 1, // Opcode: LDNT1W_ZRR +/* 24311 */ MCD_OPC_FilterValue, 7, 168, 244, 0, // Skip to: 86948 +/* 24316 */ MCD_OPC_CheckPredicate, 0, 163, 244, 0, // Skip to: 86948 +/* 24321 */ MCD_OPC_CheckField, 20, 1, 0, 156, 244, 0, // Skip to: 86948 +/* 24328 */ MCD_OPC_Decode, 195, 17, 137, 1, // Opcode: LDNT1W_ZRI +/* 24333 */ MCD_OPC_FilterValue, 9, 108, 0, 0, // Skip to: 24446 +/* 24338 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24341 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24356 +/* 24346 */ MCD_OPC_CheckPredicate, 0, 133, 244, 0, // Skip to: 86948 +/* 24351 */ MCD_OPC_Decode, 147, 15, 136, 1, // Opcode: LD1SH_S +/* 24356 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24371 +/* 24361 */ MCD_OPC_CheckPredicate, 0, 118, 244, 0, // Skip to: 86948 +/* 24366 */ MCD_OPC_Decode, 160, 17, 138, 1, // Opcode: LDFF1SH_S_REAL +/* 24371 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24409 +/* 24376 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24379 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24394 +/* 24384 */ MCD_OPC_CheckPredicate, 0, 95, 244, 0, // Skip to: 86948 +/* 24389 */ MCD_OPC_Decode, 148, 15, 137, 1, // Opcode: LD1SH_S_IMM_REAL +/* 24394 */ MCD_OPC_FilterValue, 1, 85, 244, 0, // Skip to: 86948 +/* 24399 */ MCD_OPC_CheckPredicate, 0, 80, 244, 0, // Skip to: 86948 +/* 24404 */ MCD_OPC_Decode, 180, 17, 137, 1, // Opcode: LDNF1SH_S_IMM_REAL +/* 24409 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24424 +/* 24414 */ MCD_OPC_CheckPredicate, 0, 65, 244, 0, // Skip to: 86948 +/* 24419 */ MCD_OPC_Decode, 231, 15, 139, 1, // Opcode: LD2W +/* 24424 */ MCD_OPC_FilterValue, 7, 55, 244, 0, // Skip to: 86948 +/* 24429 */ MCD_OPC_CheckPredicate, 0, 50, 244, 0, // Skip to: 86948 +/* 24434 */ MCD_OPC_CheckField, 20, 1, 0, 43, 244, 0, // Skip to: 86948 +/* 24441 */ MCD_OPC_Decode, 232, 15, 140, 1, // Opcode: LD2W_IMM +/* 24446 */ MCD_OPC_FilterValue, 10, 108, 0, 0, // Skip to: 24559 +/* 24451 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24454 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24469 +/* 24459 */ MCD_OPC_CheckPredicate, 0, 20, 244, 0, // Skip to: 86948 +/* 24464 */ MCD_OPC_Decode, 183, 15, 136, 1, // Opcode: LD1W +/* 24469 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24484 +/* 24474 */ MCD_OPC_CheckPredicate, 0, 5, 244, 0, // Skip to: 86948 +/* 24479 */ MCD_OPC_Decode, 163, 17, 138, 1, // Opcode: LDFF1W_REAL +/* 24484 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24522 +/* 24489 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24492 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24507 +/* 24497 */ MCD_OPC_CheckPredicate, 0, 238, 243, 0, // Skip to: 86948 +/* 24502 */ MCD_OPC_Decode, 186, 15, 137, 1, // Opcode: LD1W_IMM_REAL +/* 24507 */ MCD_OPC_FilterValue, 1, 228, 243, 0, // Skip to: 86948 +/* 24512 */ MCD_OPC_CheckPredicate, 0, 223, 243, 0, // Skip to: 86948 +/* 24517 */ MCD_OPC_Decode, 183, 17, 137, 1, // Opcode: LDNF1W_IMM_REAL +/* 24522 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24537 +/* 24527 */ MCD_OPC_CheckPredicate, 0, 208, 243, 0, // Skip to: 86948 +/* 24532 */ MCD_OPC_Decode, 149, 16, 141, 1, // Opcode: LD3W +/* 24537 */ MCD_OPC_FilterValue, 7, 198, 243, 0, // Skip to: 86948 +/* 24542 */ MCD_OPC_CheckPredicate, 0, 193, 243, 0, // Skip to: 86948 +/* 24547 */ MCD_OPC_CheckField, 20, 1, 0, 186, 243, 0, // Skip to: 86948 +/* 24554 */ MCD_OPC_Decode, 150, 16, 142, 1, // Opcode: LD3W_IMM +/* 24559 */ MCD_OPC_FilterValue, 11, 108, 0, 0, // Skip to: 24672 +/* 24564 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24567 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24582 +/* 24572 */ MCD_OPC_CheckPredicate, 0, 163, 243, 0, // Skip to: 86948 +/* 24577 */ MCD_OPC_Decode, 184, 15, 136, 1, // Opcode: LD1W_D +/* 24582 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24597 +/* 24587 */ MCD_OPC_CheckPredicate, 0, 148, 243, 0, // Skip to: 86948 +/* 24592 */ MCD_OPC_Decode, 162, 17, 138, 1, // Opcode: LDFF1W_D_REAL +/* 24597 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24635 +/* 24602 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24605 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24620 +/* 24610 */ MCD_OPC_CheckPredicate, 0, 125, 243, 0, // Skip to: 86948 +/* 24615 */ MCD_OPC_Decode, 185, 15, 137, 1, // Opcode: LD1W_D_IMM_REAL +/* 24620 */ MCD_OPC_FilterValue, 1, 115, 243, 0, // Skip to: 86948 +/* 24625 */ MCD_OPC_CheckPredicate, 0, 110, 243, 0, // Skip to: 86948 +/* 24630 */ MCD_OPC_Decode, 182, 17, 137, 1, // Opcode: LDNF1W_D_IMM_REAL +/* 24635 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24650 +/* 24640 */ MCD_OPC_CheckPredicate, 0, 95, 243, 0, // Skip to: 86948 +/* 24645 */ MCD_OPC_Decode, 195, 16, 143, 1, // Opcode: LD4W +/* 24650 */ MCD_OPC_FilterValue, 7, 85, 243, 0, // Skip to: 86948 +/* 24655 */ MCD_OPC_CheckPredicate, 0, 80, 243, 0, // Skip to: 86948 +/* 24660 */ MCD_OPC_CheckField, 20, 1, 0, 73, 243, 0, // Skip to: 86948 +/* 24667 */ MCD_OPC_Decode, 196, 16, 144, 1, // Opcode: LD4W_IMM +/* 24672 */ MCD_OPC_FilterValue, 12, 145, 0, 0, // Skip to: 24822 +/* 24677 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24680 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24695 +/* 24685 */ MCD_OPC_CheckPredicate, 0, 50, 243, 0, // Skip to: 86948 +/* 24690 */ MCD_OPC_Decode, 237, 14, 136, 1, // Opcode: LD1RQ_D +/* 24695 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 24717 +/* 24700 */ MCD_OPC_CheckPredicate, 0, 35, 243, 0, // Skip to: 86948 +/* 24705 */ MCD_OPC_CheckField, 20, 1, 0, 28, 243, 0, // Skip to: 86948 +/* 24712 */ MCD_OPC_Decode, 238, 14, 137, 1, // Opcode: LD1RQ_D_IMM +/* 24717 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24732 +/* 24722 */ MCD_OPC_CheckPredicate, 0, 13, 243, 0, // Skip to: 86948 +/* 24727 */ MCD_OPC_Decode, 139, 15, 136, 1, // Opcode: LD1SB_D +/* 24732 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24747 +/* 24737 */ MCD_OPC_CheckPredicate, 0, 254, 242, 0, // Skip to: 86948 +/* 24742 */ MCD_OPC_Decode, 156, 17, 138, 1, // Opcode: LDFF1SB_D_REAL +/* 24747 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24785 +/* 24752 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24755 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24770 +/* 24760 */ MCD_OPC_CheckPredicate, 0, 231, 242, 0, // Skip to: 86948 +/* 24765 */ MCD_OPC_Decode, 140, 15, 137, 1, // Opcode: LD1SB_D_IMM_REAL +/* 24770 */ MCD_OPC_FilterValue, 1, 221, 242, 0, // Skip to: 86948 +/* 24775 */ MCD_OPC_CheckPredicate, 0, 216, 242, 0, // Skip to: 86948 +/* 24780 */ MCD_OPC_Decode, 176, 17, 137, 1, // Opcode: LDNF1SB_D_IMM_REAL +/* 24785 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24800 +/* 24790 */ MCD_OPC_CheckPredicate, 0, 201, 242, 0, // Skip to: 86948 +/* 24795 */ MCD_OPC_Decode, 192, 17, 136, 1, // Opcode: LDNT1D_ZRR +/* 24800 */ MCD_OPC_FilterValue, 7, 191, 242, 0, // Skip to: 86948 +/* 24805 */ MCD_OPC_CheckPredicate, 0, 186, 242, 0, // Skip to: 86948 +/* 24810 */ MCD_OPC_CheckField, 20, 1, 0, 179, 242, 0, // Skip to: 86948 +/* 24817 */ MCD_OPC_Decode, 191, 17, 137, 1, // Opcode: LDNT1D_ZRI +/* 24822 */ MCD_OPC_FilterValue, 13, 108, 0, 0, // Skip to: 24935 +/* 24827 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24830 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24845 +/* 24835 */ MCD_OPC_CheckPredicate, 0, 156, 242, 0, // Skip to: 86948 +/* 24840 */ MCD_OPC_Decode, 143, 15, 136, 1, // Opcode: LD1SB_S +/* 24845 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24860 +/* 24850 */ MCD_OPC_CheckPredicate, 0, 141, 242, 0, // Skip to: 86948 +/* 24855 */ MCD_OPC_Decode, 158, 17, 138, 1, // Opcode: LDFF1SB_S_REAL +/* 24860 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 24898 +/* 24865 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24868 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24883 +/* 24873 */ MCD_OPC_CheckPredicate, 0, 118, 242, 0, // Skip to: 86948 +/* 24878 */ MCD_OPC_Decode, 144, 15, 137, 1, // Opcode: LD1SB_S_IMM_REAL +/* 24883 */ MCD_OPC_FilterValue, 1, 108, 242, 0, // Skip to: 86948 +/* 24888 */ MCD_OPC_CheckPredicate, 0, 103, 242, 0, // Skip to: 86948 +/* 24893 */ MCD_OPC_Decode, 178, 17, 137, 1, // Opcode: LDNF1SB_S_IMM_REAL +/* 24898 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 24913 +/* 24903 */ MCD_OPC_CheckPredicate, 0, 88, 242, 0, // Skip to: 86948 +/* 24908 */ MCD_OPC_Decode, 197, 15, 139, 1, // Opcode: LD2D +/* 24913 */ MCD_OPC_FilterValue, 7, 78, 242, 0, // Skip to: 86948 +/* 24918 */ MCD_OPC_CheckPredicate, 0, 73, 242, 0, // Skip to: 86948 +/* 24923 */ MCD_OPC_CheckField, 20, 1, 0, 66, 242, 0, // Skip to: 86948 +/* 24930 */ MCD_OPC_Decode, 198, 15, 140, 1, // Opcode: LD2D_IMM +/* 24935 */ MCD_OPC_FilterValue, 14, 108, 0, 0, // Skip to: 25048 +/* 24940 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 24943 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 24958 +/* 24948 */ MCD_OPC_CheckPredicate, 0, 43, 242, 0, // Skip to: 86948 +/* 24953 */ MCD_OPC_Decode, 141, 15, 136, 1, // Opcode: LD1SB_H +/* 24958 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 24973 +/* 24963 */ MCD_OPC_CheckPredicate, 0, 28, 242, 0, // Skip to: 86948 +/* 24968 */ MCD_OPC_Decode, 157, 17, 138, 1, // Opcode: LDFF1SB_H_REAL +/* 24973 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 25011 +/* 24978 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 24981 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 24996 +/* 24986 */ MCD_OPC_CheckPredicate, 0, 5, 242, 0, // Skip to: 86948 +/* 24991 */ MCD_OPC_Decode, 142, 15, 137, 1, // Opcode: LD1SB_H_IMM_REAL +/* 24996 */ MCD_OPC_FilterValue, 1, 251, 241, 0, // Skip to: 86948 +/* 25001 */ MCD_OPC_CheckPredicate, 0, 246, 241, 0, // Skip to: 86948 +/* 25006 */ MCD_OPC_Decode, 177, 17, 137, 1, // Opcode: LDNF1SB_H_IMM_REAL +/* 25011 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25026 +/* 25016 */ MCD_OPC_CheckPredicate, 0, 231, 241, 0, // Skip to: 86948 +/* 25021 */ MCD_OPC_Decode, 243, 15, 141, 1, // Opcode: LD3D +/* 25026 */ MCD_OPC_FilterValue, 7, 221, 241, 0, // Skip to: 86948 +/* 25031 */ MCD_OPC_CheckPredicate, 0, 216, 241, 0, // Skip to: 86948 +/* 25036 */ MCD_OPC_CheckField, 20, 1, 0, 209, 241, 0, // Skip to: 86948 +/* 25043 */ MCD_OPC_Decode, 244, 15, 142, 1, // Opcode: LD3D_IMM +/* 25048 */ MCD_OPC_FilterValue, 15, 199, 241, 0, // Skip to: 86948 +/* 25053 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25056 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 25071 +/* 25061 */ MCD_OPC_CheckPredicate, 0, 186, 241, 0, // Skip to: 86948 +/* 25066 */ MCD_OPC_Decode, 187, 14, 136, 1, // Opcode: LD1D +/* 25071 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 25086 +/* 25076 */ MCD_OPC_CheckPredicate, 0, 171, 241, 0, // Skip to: 86948 +/* 25081 */ MCD_OPC_Decode, 152, 17, 138, 1, // Opcode: LDFF1D_REAL +/* 25086 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 25124 +/* 25091 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 25094 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 25109 +/* 25099 */ MCD_OPC_CheckPredicate, 0, 148, 241, 0, // Skip to: 86948 +/* 25104 */ MCD_OPC_Decode, 188, 14, 137, 1, // Opcode: LD1D_IMM_REAL +/* 25109 */ MCD_OPC_FilterValue, 1, 138, 241, 0, // Skip to: 86948 +/* 25114 */ MCD_OPC_CheckPredicate, 0, 133, 241, 0, // Skip to: 86948 +/* 25119 */ MCD_OPC_Decode, 172, 17, 137, 1, // Opcode: LDNF1D_IMM_REAL +/* 25124 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25139 +/* 25129 */ MCD_OPC_CheckPredicate, 0, 118, 241, 0, // Skip to: 86948 +/* 25134 */ MCD_OPC_Decode, 161, 16, 143, 1, // Opcode: LD4D +/* 25139 */ MCD_OPC_FilterValue, 7, 108, 241, 0, // Skip to: 86948 +/* 25144 */ MCD_OPC_CheckPredicate, 0, 103, 241, 0, // Skip to: 86948 +/* 25149 */ MCD_OPC_CheckField, 20, 1, 0, 96, 241, 0, // Skip to: 86948 +/* 25156 */ MCD_OPC_Decode, 162, 16, 144, 1, // Opcode: LD4D_IMM +/* 25161 */ MCD_OPC_FilterValue, 6, 165, 6, 0, // Skip to: 26867 +/* 25166 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 25169 */ MCD_OPC_FilterValue, 0, 81, 0, 0, // Skip to: 25255 +/* 25174 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25177 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25191 +/* 25182 */ MCD_OPC_CheckPredicate, 0, 65, 241, 0, // Skip to: 86948 +/* 25187 */ MCD_OPC_Decode, 142, 13, 127, // Opcode: GLD1SB_D_UXTW_REAL +/* 25191 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25205 +/* 25196 */ MCD_OPC_CheckPredicate, 0, 51, 241, 0, // Skip to: 86948 +/* 25201 */ MCD_OPC_Decode, 206, 13, 127, // Opcode: GLDFF1SB_D_UXTW_REAL +/* 25205 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25219 +/* 25210 */ MCD_OPC_CheckPredicate, 0, 37, 241, 0, // Skip to: 86948 +/* 25215 */ MCD_OPC_Decode, 244, 12, 127, // Opcode: GLD1B_D_UXTW_REAL +/* 25219 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25233 +/* 25224 */ MCD_OPC_CheckPredicate, 0, 23, 241, 0, // Skip to: 86948 +/* 25229 */ MCD_OPC_Decode, 180, 13, 127, // Opcode: GLDFF1B_D_UXTW_REAL +/* 25233 */ MCD_OPC_FilterValue, 7, 14, 241, 0, // Skip to: 86948 +/* 25238 */ MCD_OPC_CheckPredicate, 0, 9, 241, 0, // Skip to: 86948 +/* 25243 */ MCD_OPC_CheckField, 4, 1, 0, 2, 241, 0, // Skip to: 86948 +/* 25250 */ MCD_OPC_Decode, 253, 20, 135, 1, // Opcode: PRFB_D_PZI +/* 25255 */ MCD_OPC_FilterValue, 1, 151, 0, 0, // Skip to: 25411 +/* 25260 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25263 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25285 +/* 25268 */ MCD_OPC_CheckPredicate, 0, 235, 240, 0, // Skip to: 86948 +/* 25273 */ MCD_OPC_CheckField, 4, 1, 0, 228, 240, 0, // Skip to: 86948 +/* 25280 */ MCD_OPC_Decode, 128, 21, 128, 1, // Opcode: PRFB_D_UXTW_SCALED +/* 25285 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 25307 +/* 25290 */ MCD_OPC_CheckPredicate, 0, 213, 240, 0, // Skip to: 86948 +/* 25295 */ MCD_OPC_CheckField, 4, 1, 0, 206, 240, 0, // Skip to: 86948 +/* 25302 */ MCD_OPC_Decode, 146, 21, 128, 1, // Opcode: PRFH_D_UXTW_SCALED +/* 25307 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 25329 +/* 25312 */ MCD_OPC_CheckPredicate, 0, 191, 240, 0, // Skip to: 86948 +/* 25317 */ MCD_OPC_CheckField, 4, 1, 0, 184, 240, 0, // Skip to: 86948 +/* 25324 */ MCD_OPC_Decode, 161, 21, 128, 1, // Opcode: PRFW_D_UXTW_SCALED +/* 25329 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 25351 +/* 25334 */ MCD_OPC_CheckPredicate, 0, 169, 240, 0, // Skip to: 86948 +/* 25339 */ MCD_OPC_CheckField, 4, 1, 0, 162, 240, 0, // Skip to: 86948 +/* 25346 */ MCD_OPC_Decode, 137, 21, 128, 1, // Opcode: PRFD_D_UXTW_SCALED +/* 25351 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 25366 +/* 25356 */ MCD_OPC_CheckPredicate, 0, 147, 240, 0, // Skip to: 86948 +/* 25361 */ MCD_OPC_Decode, 139, 13, 132, 1, // Opcode: GLD1SB_D_IMM_REAL +/* 25366 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 25381 +/* 25371 */ MCD_OPC_CheckPredicate, 0, 132, 240, 0, // Skip to: 86948 +/* 25376 */ MCD_OPC_Decode, 203, 13, 132, 1, // Opcode: GLDFF1SB_D_IMM_REAL +/* 25381 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25396 +/* 25386 */ MCD_OPC_CheckPredicate, 0, 117, 240, 0, // Skip to: 86948 +/* 25391 */ MCD_OPC_Decode, 241, 12, 132, 1, // Opcode: GLD1B_D_IMM_REAL +/* 25396 */ MCD_OPC_FilterValue, 7, 107, 240, 0, // Skip to: 86948 +/* 25401 */ MCD_OPC_CheckPredicate, 0, 102, 240, 0, // Skip to: 86948 +/* 25406 */ MCD_OPC_Decode, 177, 13, 132, 1, // Opcode: GLDFF1B_D_IMM_REAL +/* 25411 */ MCD_OPC_FilterValue, 2, 115, 0, 0, // Skip to: 25531 +/* 25416 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25419 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25433 +/* 25424 */ MCD_OPC_CheckPredicate, 0, 79, 240, 0, // Skip to: 86948 +/* 25429 */ MCD_OPC_Decode, 141, 13, 127, // Opcode: GLD1SB_D_SXTW_REAL +/* 25433 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25447 +/* 25438 */ MCD_OPC_CheckPredicate, 0, 65, 240, 0, // Skip to: 86948 +/* 25443 */ MCD_OPC_Decode, 205, 13, 127, // Opcode: GLDFF1SB_D_SXTW_REAL +/* 25447 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25461 +/* 25452 */ MCD_OPC_CheckPredicate, 0, 51, 240, 0, // Skip to: 86948 +/* 25457 */ MCD_OPC_Decode, 243, 12, 127, // Opcode: GLD1B_D_SXTW_REAL +/* 25461 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25475 +/* 25466 */ MCD_OPC_CheckPredicate, 0, 37, 240, 0, // Skip to: 86948 +/* 25471 */ MCD_OPC_Decode, 179, 13, 127, // Opcode: GLDFF1B_D_SXTW_REAL +/* 25475 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 25489 +/* 25480 */ MCD_OPC_CheckPredicate, 0, 23, 240, 0, // Skip to: 86948 +/* 25485 */ MCD_OPC_Decode, 140, 13, 127, // Opcode: GLD1SB_D_REAL +/* 25489 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 25503 +/* 25494 */ MCD_OPC_CheckPredicate, 0, 9, 240, 0, // Skip to: 86948 +/* 25499 */ MCD_OPC_Decode, 204, 13, 127, // Opcode: GLDFF1SB_D_REAL +/* 25503 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 25517 +/* 25508 */ MCD_OPC_CheckPredicate, 0, 251, 239, 0, // Skip to: 86948 +/* 25513 */ MCD_OPC_Decode, 242, 12, 127, // Opcode: GLD1B_D_REAL +/* 25517 */ MCD_OPC_FilterValue, 7, 242, 239, 0, // Skip to: 86948 +/* 25522 */ MCD_OPC_CheckPredicate, 0, 237, 239, 0, // Skip to: 86948 +/* 25527 */ MCD_OPC_Decode, 178, 13, 127, // Opcode: GLDFF1B_D_REAL +/* 25531 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 25715 +/* 25536 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25539 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 25561 +/* 25544 */ MCD_OPC_CheckPredicate, 0, 215, 239, 0, // Skip to: 86948 +/* 25549 */ MCD_OPC_CheckField, 4, 1, 0, 208, 239, 0, // Skip to: 86948 +/* 25556 */ MCD_OPC_Decode, 255, 20, 128, 1, // Opcode: PRFB_D_SXTW_SCALED +/* 25561 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 25583 +/* 25566 */ MCD_OPC_CheckPredicate, 0, 193, 239, 0, // Skip to: 86948 +/* 25571 */ MCD_OPC_CheckField, 4, 1, 0, 186, 239, 0, // Skip to: 86948 +/* 25578 */ MCD_OPC_Decode, 145, 21, 128, 1, // Opcode: PRFH_D_SXTW_SCALED +/* 25583 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 25605 +/* 25588 */ MCD_OPC_CheckPredicate, 0, 171, 239, 0, // Skip to: 86948 +/* 25593 */ MCD_OPC_CheckField, 4, 1, 0, 164, 239, 0, // Skip to: 86948 +/* 25600 */ MCD_OPC_Decode, 160, 21, 128, 1, // Opcode: PRFW_D_SXTW_SCALED +/* 25605 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 25627 +/* 25610 */ MCD_OPC_CheckPredicate, 0, 149, 239, 0, // Skip to: 86948 +/* 25615 */ MCD_OPC_CheckField, 4, 1, 0, 142, 239, 0, // Skip to: 86948 +/* 25622 */ MCD_OPC_Decode, 136, 21, 128, 1, // Opcode: PRFD_D_SXTW_SCALED +/* 25627 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 25649 +/* 25632 */ MCD_OPC_CheckPredicate, 0, 127, 239, 0, // Skip to: 86948 +/* 25637 */ MCD_OPC_CheckField, 4, 1, 0, 120, 239, 0, // Skip to: 86948 +/* 25644 */ MCD_OPC_Decode, 254, 20, 128, 1, // Opcode: PRFB_D_SCALED +/* 25649 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 25671 +/* 25654 */ MCD_OPC_CheckPredicate, 0, 105, 239, 0, // Skip to: 86948 +/* 25659 */ MCD_OPC_CheckField, 4, 1, 0, 98, 239, 0, // Skip to: 86948 +/* 25666 */ MCD_OPC_Decode, 144, 21, 128, 1, // Opcode: PRFH_D_SCALED +/* 25671 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 25693 +/* 25676 */ MCD_OPC_CheckPredicate, 0, 83, 239, 0, // Skip to: 86948 +/* 25681 */ MCD_OPC_CheckField, 4, 1, 0, 76, 239, 0, // Skip to: 86948 +/* 25688 */ MCD_OPC_Decode, 159, 21, 128, 1, // Opcode: PRFW_D_SCALED +/* 25693 */ MCD_OPC_FilterValue, 7, 66, 239, 0, // Skip to: 86948 +/* 25698 */ MCD_OPC_CheckPredicate, 0, 61, 239, 0, // Skip to: 86948 +/* 25703 */ MCD_OPC_CheckField, 4, 1, 0, 54, 239, 0, // Skip to: 86948 +/* 25710 */ MCD_OPC_Decode, 135, 21, 128, 1, // Opcode: PRFD_D_SCALED +/* 25715 */ MCD_OPC_FilterValue, 4, 81, 0, 0, // Skip to: 25801 +/* 25720 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25723 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25737 +/* 25728 */ MCD_OPC_CheckPredicate, 0, 31, 239, 0, // Skip to: 86948 +/* 25733 */ MCD_OPC_Decode, 151, 13, 127, // Opcode: GLD1SH_D_UXTW_REAL +/* 25737 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25751 +/* 25742 */ MCD_OPC_CheckPredicate, 0, 17, 239, 0, // Skip to: 86948 +/* 25747 */ MCD_OPC_Decode, 215, 13, 127, // Opcode: GLDFF1SH_D_UXTW_REAL +/* 25751 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25765 +/* 25756 */ MCD_OPC_CheckPredicate, 0, 3, 239, 0, // Skip to: 86948 +/* 25761 */ MCD_OPC_Decode, 132, 13, 127, // Opcode: GLD1H_D_UXTW_REAL +/* 25765 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25779 +/* 25770 */ MCD_OPC_CheckPredicate, 0, 245, 238, 0, // Skip to: 86948 +/* 25775 */ MCD_OPC_Decode, 196, 13, 127, // Opcode: GLDFF1H_D_UXTW_REAL +/* 25779 */ MCD_OPC_FilterValue, 7, 236, 238, 0, // Skip to: 86948 +/* 25784 */ MCD_OPC_CheckPredicate, 0, 231, 238, 0, // Skip to: 86948 +/* 25789 */ MCD_OPC_CheckField, 4, 1, 0, 224, 238, 0, // Skip to: 86948 +/* 25796 */ MCD_OPC_Decode, 143, 21, 135, 1, // Opcode: PRFH_D_PZI +/* 25801 */ MCD_OPC_FilterValue, 5, 119, 0, 0, // Skip to: 25925 +/* 25806 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25809 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25823 +/* 25814 */ MCD_OPC_CheckPredicate, 0, 201, 238, 0, // Skip to: 86948 +/* 25819 */ MCD_OPC_Decode, 152, 13, 127, // Opcode: GLD1SH_D_UXTW_SCALED_REAL +/* 25823 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25837 +/* 25828 */ MCD_OPC_CheckPredicate, 0, 187, 238, 0, // Skip to: 86948 +/* 25833 */ MCD_OPC_Decode, 216, 13, 127, // Opcode: GLDFF1SH_D_UXTW_SCALED_REAL +/* 25837 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25851 +/* 25842 */ MCD_OPC_CheckPredicate, 0, 173, 238, 0, // Skip to: 86948 +/* 25847 */ MCD_OPC_Decode, 133, 13, 127, // Opcode: GLD1H_D_UXTW_SCALED_REAL +/* 25851 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25865 +/* 25856 */ MCD_OPC_CheckPredicate, 0, 159, 238, 0, // Skip to: 86948 +/* 25861 */ MCD_OPC_Decode, 197, 13, 127, // Opcode: GLDFF1H_D_UXTW_SCALED_REAL +/* 25865 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 25880 +/* 25870 */ MCD_OPC_CheckPredicate, 0, 145, 238, 0, // Skip to: 86948 +/* 25875 */ MCD_OPC_Decode, 146, 13, 132, 1, // Opcode: GLD1SH_D_IMM_REAL +/* 25880 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 25895 +/* 25885 */ MCD_OPC_CheckPredicate, 0, 130, 238, 0, // Skip to: 86948 +/* 25890 */ MCD_OPC_Decode, 210, 13, 132, 1, // Opcode: GLDFF1SH_D_IMM_REAL +/* 25895 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 25910 +/* 25900 */ MCD_OPC_CheckPredicate, 0, 115, 238, 0, // Skip to: 86948 +/* 25905 */ MCD_OPC_Decode, 255, 12, 132, 1, // Opcode: GLD1H_D_IMM_REAL +/* 25910 */ MCD_OPC_FilterValue, 7, 105, 238, 0, // Skip to: 86948 +/* 25915 */ MCD_OPC_CheckPredicate, 0, 100, 238, 0, // Skip to: 86948 +/* 25920 */ MCD_OPC_Decode, 191, 13, 132, 1, // Opcode: GLDFF1H_D_IMM_REAL +/* 25925 */ MCD_OPC_FilterValue, 6, 115, 0, 0, // Skip to: 26045 +/* 25930 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 25933 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 25947 +/* 25938 */ MCD_OPC_CheckPredicate, 0, 77, 238, 0, // Skip to: 86948 +/* 25943 */ MCD_OPC_Decode, 149, 13, 127, // Opcode: GLD1SH_D_SXTW_REAL +/* 25947 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 25961 +/* 25952 */ MCD_OPC_CheckPredicate, 0, 63, 238, 0, // Skip to: 86948 +/* 25957 */ MCD_OPC_Decode, 213, 13, 127, // Opcode: GLDFF1SH_D_SXTW_REAL +/* 25961 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 25975 +/* 25966 */ MCD_OPC_CheckPredicate, 0, 49, 238, 0, // Skip to: 86948 +/* 25971 */ MCD_OPC_Decode, 130, 13, 127, // Opcode: GLD1H_D_SXTW_REAL +/* 25975 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 25989 +/* 25980 */ MCD_OPC_CheckPredicate, 0, 35, 238, 0, // Skip to: 86948 +/* 25985 */ MCD_OPC_Decode, 194, 13, 127, // Opcode: GLDFF1H_D_SXTW_REAL +/* 25989 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26003 +/* 25994 */ MCD_OPC_CheckPredicate, 0, 21, 238, 0, // Skip to: 86948 +/* 25999 */ MCD_OPC_Decode, 147, 13, 127, // Opcode: GLD1SH_D_REAL +/* 26003 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26017 +/* 26008 */ MCD_OPC_CheckPredicate, 0, 7, 238, 0, // Skip to: 86948 +/* 26013 */ MCD_OPC_Decode, 211, 13, 127, // Opcode: GLDFF1SH_D_REAL +/* 26017 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26031 +/* 26022 */ MCD_OPC_CheckPredicate, 0, 249, 237, 0, // Skip to: 86948 +/* 26027 */ MCD_OPC_Decode, 128, 13, 127, // Opcode: GLD1H_D_REAL +/* 26031 */ MCD_OPC_FilterValue, 7, 240, 237, 0, // Skip to: 86948 +/* 26036 */ MCD_OPC_CheckPredicate, 0, 235, 237, 0, // Skip to: 86948 +/* 26041 */ MCD_OPC_Decode, 192, 13, 127, // Opcode: GLDFF1H_D_REAL +/* 26045 */ MCD_OPC_FilterValue, 7, 115, 0, 0, // Skip to: 26165 +/* 26050 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26053 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26067 +/* 26058 */ MCD_OPC_CheckPredicate, 0, 213, 237, 0, // Skip to: 86948 +/* 26063 */ MCD_OPC_Decode, 150, 13, 127, // Opcode: GLD1SH_D_SXTW_SCALED_REAL +/* 26067 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26081 +/* 26072 */ MCD_OPC_CheckPredicate, 0, 199, 237, 0, // Skip to: 86948 +/* 26077 */ MCD_OPC_Decode, 214, 13, 127, // Opcode: GLDFF1SH_D_SXTW_SCALED_REAL +/* 26081 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26095 +/* 26086 */ MCD_OPC_CheckPredicate, 0, 185, 237, 0, // Skip to: 86948 +/* 26091 */ MCD_OPC_Decode, 131, 13, 127, // Opcode: GLD1H_D_SXTW_SCALED_REAL +/* 26095 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26109 +/* 26100 */ MCD_OPC_CheckPredicate, 0, 171, 237, 0, // Skip to: 86948 +/* 26105 */ MCD_OPC_Decode, 195, 13, 127, // Opcode: GLDFF1H_D_SXTW_SCALED_REAL +/* 26109 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26123 +/* 26114 */ MCD_OPC_CheckPredicate, 0, 157, 237, 0, // Skip to: 86948 +/* 26119 */ MCD_OPC_Decode, 148, 13, 127, // Opcode: GLD1SH_D_SCALED_REAL +/* 26123 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26137 +/* 26128 */ MCD_OPC_CheckPredicate, 0, 143, 237, 0, // Skip to: 86948 +/* 26133 */ MCD_OPC_Decode, 212, 13, 127, // Opcode: GLDFF1SH_D_SCALED_REAL +/* 26137 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26151 +/* 26142 */ MCD_OPC_CheckPredicate, 0, 129, 237, 0, // Skip to: 86948 +/* 26147 */ MCD_OPC_Decode, 129, 13, 127, // Opcode: GLD1H_D_SCALED_REAL +/* 26151 */ MCD_OPC_FilterValue, 7, 120, 237, 0, // Skip to: 86948 +/* 26156 */ MCD_OPC_CheckPredicate, 0, 115, 237, 0, // Skip to: 86948 +/* 26161 */ MCD_OPC_Decode, 193, 13, 127, // Opcode: GLDFF1H_D_SCALED_REAL +/* 26165 */ MCD_OPC_FilterValue, 8, 81, 0, 0, // Skip to: 26251 +/* 26170 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26173 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26187 +/* 26178 */ MCD_OPC_CheckPredicate, 0, 93, 237, 0, // Skip to: 86948 +/* 26183 */ MCD_OPC_Decode, 163, 13, 127, // Opcode: GLD1SW_D_UXTW_REAL +/* 26187 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26201 +/* 26192 */ MCD_OPC_CheckPredicate, 0, 79, 237, 0, // Skip to: 86948 +/* 26197 */ MCD_OPC_Decode, 227, 13, 127, // Opcode: GLDFF1SW_D_UXTW_REAL +/* 26201 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26215 +/* 26206 */ MCD_OPC_CheckPredicate, 0, 65, 237, 0, // Skip to: 86948 +/* 26211 */ MCD_OPC_Decode, 170, 13, 127, // Opcode: GLD1W_D_UXTW_REAL +/* 26215 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26229 +/* 26220 */ MCD_OPC_CheckPredicate, 0, 51, 237, 0, // Skip to: 86948 +/* 26225 */ MCD_OPC_Decode, 234, 13, 127, // Opcode: GLDFF1W_D_UXTW_REAL +/* 26229 */ MCD_OPC_FilterValue, 7, 42, 237, 0, // Skip to: 86948 +/* 26234 */ MCD_OPC_CheckPredicate, 0, 37, 237, 0, // Skip to: 86948 +/* 26239 */ MCD_OPC_CheckField, 4, 1, 0, 30, 237, 0, // Skip to: 86948 +/* 26246 */ MCD_OPC_Decode, 158, 21, 135, 1, // Opcode: PRFW_D_PZI +/* 26251 */ MCD_OPC_FilterValue, 9, 119, 0, 0, // Skip to: 26375 +/* 26256 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26259 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26273 +/* 26264 */ MCD_OPC_CheckPredicate, 0, 7, 237, 0, // Skip to: 86948 +/* 26269 */ MCD_OPC_Decode, 164, 13, 127, // Opcode: GLD1SW_D_UXTW_SCALED_REAL +/* 26273 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26287 +/* 26278 */ MCD_OPC_CheckPredicate, 0, 249, 236, 0, // Skip to: 86948 +/* 26283 */ MCD_OPC_Decode, 228, 13, 127, // Opcode: GLDFF1SW_D_UXTW_SCALED_REAL +/* 26287 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26301 +/* 26292 */ MCD_OPC_CheckPredicate, 0, 235, 236, 0, // Skip to: 86948 +/* 26297 */ MCD_OPC_Decode, 171, 13, 127, // Opcode: GLD1W_D_UXTW_SCALED_REAL +/* 26301 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26315 +/* 26306 */ MCD_OPC_CheckPredicate, 0, 221, 236, 0, // Skip to: 86948 +/* 26311 */ MCD_OPC_Decode, 235, 13, 127, // Opcode: GLDFF1W_D_UXTW_SCALED_REAL +/* 26315 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 26330 +/* 26320 */ MCD_OPC_CheckPredicate, 0, 207, 236, 0, // Skip to: 86948 +/* 26325 */ MCD_OPC_Decode, 158, 13, 132, 1, // Opcode: GLD1SW_D_IMM_REAL +/* 26330 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 26345 +/* 26335 */ MCD_OPC_CheckPredicate, 0, 192, 236, 0, // Skip to: 86948 +/* 26340 */ MCD_OPC_Decode, 222, 13, 132, 1, // Opcode: GLDFF1SW_D_IMM_REAL +/* 26345 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 26360 +/* 26350 */ MCD_OPC_CheckPredicate, 0, 177, 236, 0, // Skip to: 86948 +/* 26355 */ MCD_OPC_Decode, 165, 13, 132, 1, // Opcode: GLD1W_D_IMM_REAL +/* 26360 */ MCD_OPC_FilterValue, 7, 167, 236, 0, // Skip to: 86948 +/* 26365 */ MCD_OPC_CheckPredicate, 0, 162, 236, 0, // Skip to: 86948 +/* 26370 */ MCD_OPC_Decode, 229, 13, 132, 1, // Opcode: GLDFF1W_D_IMM_REAL +/* 26375 */ MCD_OPC_FilterValue, 10, 115, 0, 0, // Skip to: 26495 +/* 26380 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26383 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26397 +/* 26388 */ MCD_OPC_CheckPredicate, 0, 139, 236, 0, // Skip to: 86948 +/* 26393 */ MCD_OPC_Decode, 161, 13, 127, // Opcode: GLD1SW_D_SXTW_REAL +/* 26397 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26411 +/* 26402 */ MCD_OPC_CheckPredicate, 0, 125, 236, 0, // Skip to: 86948 +/* 26407 */ MCD_OPC_Decode, 225, 13, 127, // Opcode: GLDFF1SW_D_SXTW_REAL +/* 26411 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26425 +/* 26416 */ MCD_OPC_CheckPredicate, 0, 111, 236, 0, // Skip to: 86948 +/* 26421 */ MCD_OPC_Decode, 168, 13, 127, // Opcode: GLD1W_D_SXTW_REAL +/* 26425 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26439 +/* 26430 */ MCD_OPC_CheckPredicate, 0, 97, 236, 0, // Skip to: 86948 +/* 26435 */ MCD_OPC_Decode, 232, 13, 127, // Opcode: GLDFF1W_D_SXTW_REAL +/* 26439 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26453 +/* 26444 */ MCD_OPC_CheckPredicate, 0, 83, 236, 0, // Skip to: 86948 +/* 26449 */ MCD_OPC_Decode, 159, 13, 127, // Opcode: GLD1SW_D_REAL +/* 26453 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26467 +/* 26458 */ MCD_OPC_CheckPredicate, 0, 69, 236, 0, // Skip to: 86948 +/* 26463 */ MCD_OPC_Decode, 223, 13, 127, // Opcode: GLDFF1SW_D_REAL +/* 26467 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26481 +/* 26472 */ MCD_OPC_CheckPredicate, 0, 55, 236, 0, // Skip to: 86948 +/* 26477 */ MCD_OPC_Decode, 166, 13, 127, // Opcode: GLD1W_D_REAL +/* 26481 */ MCD_OPC_FilterValue, 7, 46, 236, 0, // Skip to: 86948 +/* 26486 */ MCD_OPC_CheckPredicate, 0, 41, 236, 0, // Skip to: 86948 +/* 26491 */ MCD_OPC_Decode, 230, 13, 127, // Opcode: GLDFF1W_D_REAL +/* 26495 */ MCD_OPC_FilterValue, 11, 115, 0, 0, // Skip to: 26615 +/* 26500 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26503 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 26517 +/* 26508 */ MCD_OPC_CheckPredicate, 0, 19, 236, 0, // Skip to: 86948 +/* 26513 */ MCD_OPC_Decode, 162, 13, 127, // Opcode: GLD1SW_D_SXTW_SCALED_REAL +/* 26517 */ MCD_OPC_FilterValue, 1, 9, 0, 0, // Skip to: 26531 +/* 26522 */ MCD_OPC_CheckPredicate, 0, 5, 236, 0, // Skip to: 86948 +/* 26527 */ MCD_OPC_Decode, 226, 13, 127, // Opcode: GLDFF1SW_D_SXTW_SCALED_REAL +/* 26531 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26545 +/* 26536 */ MCD_OPC_CheckPredicate, 0, 247, 235, 0, // Skip to: 86948 +/* 26541 */ MCD_OPC_Decode, 169, 13, 127, // Opcode: GLD1W_D_SXTW_SCALED_REAL +/* 26545 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26559 +/* 26550 */ MCD_OPC_CheckPredicate, 0, 233, 235, 0, // Skip to: 86948 +/* 26555 */ MCD_OPC_Decode, 233, 13, 127, // Opcode: GLDFF1W_D_SXTW_SCALED_REAL +/* 26559 */ MCD_OPC_FilterValue, 4, 9, 0, 0, // Skip to: 26573 +/* 26564 */ MCD_OPC_CheckPredicate, 0, 219, 235, 0, // Skip to: 86948 +/* 26569 */ MCD_OPC_Decode, 160, 13, 127, // Opcode: GLD1SW_D_SCALED_REAL +/* 26573 */ MCD_OPC_FilterValue, 5, 9, 0, 0, // Skip to: 26587 +/* 26578 */ MCD_OPC_CheckPredicate, 0, 205, 235, 0, // Skip to: 86948 +/* 26583 */ MCD_OPC_Decode, 224, 13, 127, // Opcode: GLDFF1SW_D_SCALED_REAL +/* 26587 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26601 +/* 26592 */ MCD_OPC_CheckPredicate, 0, 191, 235, 0, // Skip to: 86948 +/* 26597 */ MCD_OPC_Decode, 167, 13, 127, // Opcode: GLD1W_D_SCALED_REAL +/* 26601 */ MCD_OPC_FilterValue, 7, 182, 235, 0, // Skip to: 86948 +/* 26606 */ MCD_OPC_CheckPredicate, 0, 177, 235, 0, // Skip to: 86948 +/* 26611 */ MCD_OPC_Decode, 231, 13, 127, // Opcode: GLDFF1W_D_SCALED_REAL +/* 26615 */ MCD_OPC_FilterValue, 12, 53, 0, 0, // Skip to: 26673 +/* 26620 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26623 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26637 +/* 26628 */ MCD_OPC_CheckPredicate, 0, 155, 235, 0, // Skip to: 86948 +/* 26633 */ MCD_OPC_Decode, 253, 12, 127, // Opcode: GLD1D_UXTW_REAL +/* 26637 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26651 +/* 26642 */ MCD_OPC_CheckPredicate, 0, 141, 235, 0, // Skip to: 86948 +/* 26647 */ MCD_OPC_Decode, 189, 13, 127, // Opcode: GLDFF1D_UXTW_REAL +/* 26651 */ MCD_OPC_FilterValue, 7, 132, 235, 0, // Skip to: 86948 +/* 26656 */ MCD_OPC_CheckPredicate, 0, 127, 235, 0, // Skip to: 86948 +/* 26661 */ MCD_OPC_CheckField, 4, 1, 0, 120, 235, 0, // Skip to: 86948 +/* 26668 */ MCD_OPC_Decode, 134, 21, 135, 1, // Opcode: PRFD_D_PZI +/* 26673 */ MCD_OPC_FilterValue, 13, 61, 0, 0, // Skip to: 26739 +/* 26678 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26681 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26695 +/* 26686 */ MCD_OPC_CheckPredicate, 0, 97, 235, 0, // Skip to: 86948 +/* 26691 */ MCD_OPC_Decode, 254, 12, 127, // Opcode: GLD1D_UXTW_SCALED_REAL +/* 26695 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26709 +/* 26700 */ MCD_OPC_CheckPredicate, 0, 83, 235, 0, // Skip to: 86948 +/* 26705 */ MCD_OPC_Decode, 190, 13, 127, // Opcode: GLDFF1D_UXTW_SCALED_REAL +/* 26709 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 26724 +/* 26714 */ MCD_OPC_CheckPredicate, 0, 69, 235, 0, // Skip to: 86948 +/* 26719 */ MCD_OPC_Decode, 248, 12, 132, 1, // Opcode: GLD1D_IMM_REAL +/* 26724 */ MCD_OPC_FilterValue, 7, 59, 235, 0, // Skip to: 86948 +/* 26729 */ MCD_OPC_CheckPredicate, 0, 54, 235, 0, // Skip to: 86948 +/* 26734 */ MCD_OPC_Decode, 184, 13, 132, 1, // Opcode: GLDFF1D_IMM_REAL +/* 26739 */ MCD_OPC_FilterValue, 14, 59, 0, 0, // Skip to: 26803 +/* 26744 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26747 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26761 +/* 26752 */ MCD_OPC_CheckPredicate, 0, 31, 235, 0, // Skip to: 86948 +/* 26757 */ MCD_OPC_Decode, 251, 12, 127, // Opcode: GLD1D_SXTW_REAL +/* 26761 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26775 +/* 26766 */ MCD_OPC_CheckPredicate, 0, 17, 235, 0, // Skip to: 86948 +/* 26771 */ MCD_OPC_Decode, 187, 13, 127, // Opcode: GLDFF1D_SXTW_REAL +/* 26775 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26789 +/* 26780 */ MCD_OPC_CheckPredicate, 0, 3, 235, 0, // Skip to: 86948 +/* 26785 */ MCD_OPC_Decode, 249, 12, 127, // Opcode: GLD1D_REAL +/* 26789 */ MCD_OPC_FilterValue, 7, 250, 234, 0, // Skip to: 86948 +/* 26794 */ MCD_OPC_CheckPredicate, 0, 245, 234, 0, // Skip to: 86948 +/* 26799 */ MCD_OPC_Decode, 185, 13, 127, // Opcode: GLDFF1D_REAL +/* 26803 */ MCD_OPC_FilterValue, 15, 236, 234, 0, // Skip to: 86948 +/* 26808 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26811 */ MCD_OPC_FilterValue, 2, 9, 0, 0, // Skip to: 26825 +/* 26816 */ MCD_OPC_CheckPredicate, 0, 223, 234, 0, // Skip to: 86948 +/* 26821 */ MCD_OPC_Decode, 252, 12, 127, // Opcode: GLD1D_SXTW_SCALED_REAL +/* 26825 */ MCD_OPC_FilterValue, 3, 9, 0, 0, // Skip to: 26839 +/* 26830 */ MCD_OPC_CheckPredicate, 0, 209, 234, 0, // Skip to: 86948 +/* 26835 */ MCD_OPC_Decode, 188, 13, 127, // Opcode: GLDFF1D_SXTW_SCALED_REAL +/* 26839 */ MCD_OPC_FilterValue, 6, 9, 0, 0, // Skip to: 26853 +/* 26844 */ MCD_OPC_CheckPredicate, 0, 195, 234, 0, // Skip to: 86948 +/* 26849 */ MCD_OPC_Decode, 250, 12, 127, // Opcode: GLD1D_SCALED_REAL +/* 26853 */ MCD_OPC_FilterValue, 7, 186, 234, 0, // Skip to: 86948 +/* 26858 */ MCD_OPC_CheckPredicate, 0, 181, 234, 0, // Skip to: 86948 +/* 26863 */ MCD_OPC_Decode, 186, 13, 127, // Opcode: GLDFF1D_SCALED_REAL +/* 26867 */ MCD_OPC_FilterValue, 7, 172, 234, 0, // Skip to: 86948 +/* 26872 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 26875 */ MCD_OPC_FilterValue, 0, 210, 0, 0, // Skip to: 27090 +/* 26880 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 26883 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 26921 +/* 26888 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26891 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26906 +/* 26896 */ MCD_OPC_CheckPredicate, 0, 143, 234, 0, // Skip to: 86948 +/* 26901 */ MCD_OPC_Decode, 173, 27, 136, 1, // Opcode: ST1B +/* 26906 */ MCD_OPC_FilterValue, 1, 133, 234, 0, // Skip to: 86948 +/* 26911 */ MCD_OPC_CheckPredicate, 0, 128, 234, 0, // Skip to: 86948 +/* 26916 */ MCD_OPC_Decode, 176, 27, 136, 1, // Opcode: ST1B_H +/* 26921 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 26959 +/* 26926 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 26929 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 26944 +/* 26934 */ MCD_OPC_CheckPredicate, 0, 105, 234, 0, // Skip to: 86948 +/* 26939 */ MCD_OPC_Decode, 251, 28, 136, 1, // Opcode: STNT1B_ZRR +/* 26944 */ MCD_OPC_FilterValue, 1, 95, 234, 0, // Skip to: 86948 +/* 26949 */ MCD_OPC_CheckPredicate, 0, 90, 234, 0, // Skip to: 86948 +/* 26954 */ MCD_OPC_Decode, 137, 28, 139, 1, // Opcode: ST2B +/* 26959 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 26980 +/* 26964 */ MCD_OPC_CheckPredicate, 0, 75, 234, 0, // Skip to: 86948 +/* 26969 */ MCD_OPC_CheckField, 21, 1, 0, 68, 234, 0, // Skip to: 86948 +/* 26976 */ MCD_OPC_Decode, 254, 26, 127, // Opcode: SST1B_D_UXTW +/* 26980 */ MCD_OPC_FilterValue, 5, 16, 0, 0, // Skip to: 27001 +/* 26985 */ MCD_OPC_CheckPredicate, 0, 54, 234, 0, // Skip to: 86948 +/* 26990 */ MCD_OPC_CheckField, 21, 1, 0, 47, 234, 0, // Skip to: 86948 +/* 26997 */ MCD_OPC_Decode, 251, 26, 127, // Opcode: SST1B_D +/* 27001 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 27022 +/* 27006 */ MCD_OPC_CheckPredicate, 0, 33, 234, 0, // Skip to: 86948 +/* 27011 */ MCD_OPC_CheckField, 21, 1, 0, 26, 234, 0, // Skip to: 86948 +/* 27018 */ MCD_OPC_Decode, 253, 26, 127, // Opcode: SST1B_D_SXTW +/* 27022 */ MCD_OPC_FilterValue, 7, 17, 234, 0, // Skip to: 86948 +/* 27027 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 27030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27045 +/* 27035 */ MCD_OPC_CheckPredicate, 0, 4, 234, 0, // Skip to: 86948 +/* 27040 */ MCD_OPC_Decode, 178, 27, 137, 1, // Opcode: ST1B_IMM +/* 27045 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27060 +/* 27050 */ MCD_OPC_CheckPredicate, 0, 245, 233, 0, // Skip to: 86948 +/* 27055 */ MCD_OPC_Decode, 250, 28, 137, 1, // Opcode: STNT1B_ZRI +/* 27060 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27075 +/* 27065 */ MCD_OPC_CheckPredicate, 0, 230, 233, 0, // Skip to: 86948 +/* 27070 */ MCD_OPC_Decode, 177, 27, 137, 1, // Opcode: ST1B_H_IMM +/* 27075 */ MCD_OPC_FilterValue, 3, 220, 233, 0, // Skip to: 86948 +/* 27080 */ MCD_OPC_CheckPredicate, 0, 215, 233, 0, // Skip to: 86948 +/* 27085 */ MCD_OPC_Decode, 138, 28, 140, 1, // Opcode: ST2B_IMM +/* 27090 */ MCD_OPC_FilterValue, 1, 227, 0, 0, // Skip to: 27322 +/* 27095 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 27098 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 27136 +/* 27103 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27121 +/* 27111 */ MCD_OPC_CheckPredicate, 0, 184, 233, 0, // Skip to: 86948 +/* 27116 */ MCD_OPC_Decode, 179, 27, 136, 1, // Opcode: ST1B_S +/* 27121 */ MCD_OPC_FilterValue, 1, 174, 233, 0, // Skip to: 86948 +/* 27126 */ MCD_OPC_CheckPredicate, 0, 169, 233, 0, // Skip to: 86948 +/* 27131 */ MCD_OPC_Decode, 174, 27, 136, 1, // Opcode: ST1B_D +/* 27136 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27174 +/* 27141 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27144 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27159 +/* 27149 */ MCD_OPC_CheckPredicate, 0, 146, 233, 0, // Skip to: 86948 +/* 27154 */ MCD_OPC_Decode, 167, 28, 141, 1, // Opcode: ST3B +/* 27159 */ MCD_OPC_FilterValue, 1, 136, 233, 0, // Skip to: 86948 +/* 27164 */ MCD_OPC_CheckPredicate, 0, 131, 233, 0, // Skip to: 86948 +/* 27169 */ MCD_OPC_Decode, 197, 28, 143, 1, // Opcode: ST4B +/* 27174 */ MCD_OPC_FilterValue, 4, 16, 0, 0, // Skip to: 27195 +/* 27179 */ MCD_OPC_CheckPredicate, 0, 116, 233, 0, // Skip to: 86948 +/* 27184 */ MCD_OPC_CheckField, 21, 1, 0, 109, 233, 0, // Skip to: 86948 +/* 27191 */ MCD_OPC_Decode, 129, 27, 127, // Opcode: SST1B_S_UXTW +/* 27195 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 27233 +/* 27200 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27203 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27218 +/* 27208 */ MCD_OPC_CheckPredicate, 0, 87, 233, 0, // Skip to: 86948 +/* 27213 */ MCD_OPC_Decode, 252, 26, 132, 1, // Opcode: SST1B_D_IMM +/* 27218 */ MCD_OPC_FilterValue, 1, 77, 233, 0, // Skip to: 86948 +/* 27223 */ MCD_OPC_CheckPredicate, 0, 72, 233, 0, // Skip to: 86948 +/* 27228 */ MCD_OPC_Decode, 255, 26, 132, 1, // Opcode: SST1B_S_IMM +/* 27233 */ MCD_OPC_FilterValue, 6, 16, 0, 0, // Skip to: 27254 +/* 27238 */ MCD_OPC_CheckPredicate, 0, 57, 233, 0, // Skip to: 86948 +/* 27243 */ MCD_OPC_CheckField, 21, 1, 0, 50, 233, 0, // Skip to: 86948 +/* 27250 */ MCD_OPC_Decode, 128, 27, 127, // Opcode: SST1B_S_SXTW +/* 27254 */ MCD_OPC_FilterValue, 7, 41, 233, 0, // Skip to: 86948 +/* 27259 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 27262 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27277 +/* 27267 */ MCD_OPC_CheckPredicate, 0, 28, 233, 0, // Skip to: 86948 +/* 27272 */ MCD_OPC_Decode, 180, 27, 137, 1, // Opcode: ST1B_S_IMM +/* 27277 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27292 +/* 27282 */ MCD_OPC_CheckPredicate, 0, 13, 233, 0, // Skip to: 86948 +/* 27287 */ MCD_OPC_Decode, 168, 28, 142, 1, // Opcode: ST3B_IMM +/* 27292 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27307 +/* 27297 */ MCD_OPC_CheckPredicate, 0, 254, 232, 0, // Skip to: 86948 +/* 27302 */ MCD_OPC_Decode, 175, 27, 137, 1, // Opcode: ST1B_D_IMM +/* 27307 */ MCD_OPC_FilterValue, 3, 244, 232, 0, // Skip to: 86948 +/* 27312 */ MCD_OPC_CheckPredicate, 0, 239, 232, 0, // Skip to: 86948 +/* 27317 */ MCD_OPC_Decode, 198, 28, 144, 1, // Opcode: ST4B_IMM +/* 27322 */ MCD_OPC_FilterValue, 2, 224, 0, 0, // Skip to: 27551 +/* 27327 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 27330 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 27352 +/* 27335 */ MCD_OPC_CheckPredicate, 0, 216, 232, 0, // Skip to: 86948 +/* 27340 */ MCD_OPC_CheckField, 21, 1, 1, 209, 232, 0, // Skip to: 86948 +/* 27347 */ MCD_OPC_Decode, 199, 27, 136, 1, // Opcode: ST1H +/* 27352 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27390 +/* 27357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27375 +/* 27365 */ MCD_OPC_CheckPredicate, 0, 186, 232, 0, // Skip to: 86948 +/* 27370 */ MCD_OPC_Decode, 255, 28, 136, 1, // Opcode: STNT1H_ZRR +/* 27375 */ MCD_OPC_FilterValue, 1, 176, 232, 0, // Skip to: 86948 +/* 27380 */ MCD_OPC_CheckPredicate, 0, 171, 232, 0, // Skip to: 86948 +/* 27385 */ MCD_OPC_Decode, 141, 28, 139, 1, // Opcode: ST2H +/* 27390 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27426 +/* 27395 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27398 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27412 +/* 27403 */ MCD_OPC_CheckPredicate, 0, 148, 232, 0, // Skip to: 86948 +/* 27408 */ MCD_OPC_Decode, 142, 27, 127, // Opcode: SST1H_D_UXTW +/* 27412 */ MCD_OPC_FilterValue, 1, 139, 232, 0, // Skip to: 86948 +/* 27417 */ MCD_OPC_CheckPredicate, 0, 134, 232, 0, // Skip to: 86948 +/* 27422 */ MCD_OPC_Decode, 143, 27, 127, // Opcode: SST1H_D_UXTW_SCALED +/* 27426 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 27462 +/* 27431 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27434 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27448 +/* 27439 */ MCD_OPC_CheckPredicate, 0, 112, 232, 0, // Skip to: 86948 +/* 27444 */ MCD_OPC_Decode, 137, 27, 127, // Opcode: SST1H_D +/* 27448 */ MCD_OPC_FilterValue, 1, 103, 232, 0, // Skip to: 86948 +/* 27453 */ MCD_OPC_CheckPredicate, 0, 98, 232, 0, // Skip to: 86948 +/* 27458 */ MCD_OPC_Decode, 139, 27, 127, // Opcode: SST1H_D_SCALED +/* 27462 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27498 +/* 27467 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27470 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27484 +/* 27475 */ MCD_OPC_CheckPredicate, 0, 76, 232, 0, // Skip to: 86948 +/* 27480 */ MCD_OPC_Decode, 140, 27, 127, // Opcode: SST1H_D_SXTW +/* 27484 */ MCD_OPC_FilterValue, 1, 67, 232, 0, // Skip to: 86948 +/* 27489 */ MCD_OPC_CheckPredicate, 0, 62, 232, 0, // Skip to: 86948 +/* 27494 */ MCD_OPC_Decode, 141, 27, 127, // Opcode: SST1H_D_SXTW_SCALED +/* 27498 */ MCD_OPC_FilterValue, 7, 53, 232, 0, // Skip to: 86948 +/* 27503 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 27506 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27521 +/* 27511 */ MCD_OPC_CheckPredicate, 0, 40, 232, 0, // Skip to: 86948 +/* 27516 */ MCD_OPC_Decode, 254, 28, 137, 1, // Opcode: STNT1H_ZRI +/* 27521 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27536 +/* 27526 */ MCD_OPC_CheckPredicate, 0, 25, 232, 0, // Skip to: 86948 +/* 27531 */ MCD_OPC_Decode, 202, 27, 137, 1, // Opcode: ST1H_IMM +/* 27536 */ MCD_OPC_FilterValue, 3, 15, 232, 0, // Skip to: 86948 +/* 27541 */ MCD_OPC_CheckPredicate, 0, 10, 232, 0, // Skip to: 86948 +/* 27546 */ MCD_OPC_Decode, 142, 28, 140, 1, // Opcode: ST2H_IMM +/* 27551 */ MCD_OPC_FilterValue, 3, 1, 1, 0, // Skip to: 27813 +/* 27556 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 27559 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 27597 +/* 27564 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27567 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27582 +/* 27572 */ MCD_OPC_CheckPredicate, 0, 235, 231, 0, // Skip to: 86948 +/* 27577 */ MCD_OPC_Decode, 203, 27, 136, 1, // Opcode: ST1H_S +/* 27582 */ MCD_OPC_FilterValue, 1, 225, 231, 0, // Skip to: 86948 +/* 27587 */ MCD_OPC_CheckPredicate, 0, 220, 231, 0, // Skip to: 86948 +/* 27592 */ MCD_OPC_Decode, 200, 27, 136, 1, // Opcode: ST1H_D +/* 27597 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27635 +/* 27602 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27605 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27620 +/* 27610 */ MCD_OPC_CheckPredicate, 0, 197, 231, 0, // Skip to: 86948 +/* 27615 */ MCD_OPC_Decode, 171, 28, 141, 1, // Opcode: ST3H +/* 27620 */ MCD_OPC_FilterValue, 1, 187, 231, 0, // Skip to: 86948 +/* 27625 */ MCD_OPC_CheckPredicate, 0, 182, 231, 0, // Skip to: 86948 +/* 27630 */ MCD_OPC_Decode, 215, 28, 143, 1, // Opcode: ST4H +/* 27635 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27671 +/* 27640 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27643 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27657 +/* 27648 */ MCD_OPC_CheckPredicate, 0, 159, 231, 0, // Skip to: 86948 +/* 27653 */ MCD_OPC_Decode, 147, 27, 127, // Opcode: SST1H_S_UXTW +/* 27657 */ MCD_OPC_FilterValue, 1, 150, 231, 0, // Skip to: 86948 +/* 27662 */ MCD_OPC_CheckPredicate, 0, 145, 231, 0, // Skip to: 86948 +/* 27667 */ MCD_OPC_Decode, 148, 27, 127, // Opcode: SST1H_S_UXTW_SCALED +/* 27671 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 27709 +/* 27676 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27679 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27694 +/* 27684 */ MCD_OPC_CheckPredicate, 0, 123, 231, 0, // Skip to: 86948 +/* 27689 */ MCD_OPC_Decode, 138, 27, 132, 1, // Opcode: SST1H_D_IMM +/* 27694 */ MCD_OPC_FilterValue, 1, 113, 231, 0, // Skip to: 86948 +/* 27699 */ MCD_OPC_CheckPredicate, 0, 108, 231, 0, // Skip to: 86948 +/* 27704 */ MCD_OPC_Decode, 144, 27, 132, 1, // Opcode: SST1H_S_IMM +/* 27709 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27745 +/* 27714 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27717 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27731 +/* 27722 */ MCD_OPC_CheckPredicate, 0, 85, 231, 0, // Skip to: 86948 +/* 27727 */ MCD_OPC_Decode, 145, 27, 127, // Opcode: SST1H_S_SXTW +/* 27731 */ MCD_OPC_FilterValue, 1, 76, 231, 0, // Skip to: 86948 +/* 27736 */ MCD_OPC_CheckPredicate, 0, 71, 231, 0, // Skip to: 86948 +/* 27741 */ MCD_OPC_Decode, 146, 27, 127, // Opcode: SST1H_S_SXTW_SCALED +/* 27745 */ MCD_OPC_FilterValue, 7, 62, 231, 0, // Skip to: 86948 +/* 27750 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 27753 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27768 +/* 27758 */ MCD_OPC_CheckPredicate, 0, 49, 231, 0, // Skip to: 86948 +/* 27763 */ MCD_OPC_Decode, 204, 27, 137, 1, // Opcode: ST1H_S_IMM +/* 27768 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27783 +/* 27773 */ MCD_OPC_CheckPredicate, 0, 34, 231, 0, // Skip to: 86948 +/* 27778 */ MCD_OPC_Decode, 172, 28, 142, 1, // Opcode: ST3H_IMM +/* 27783 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 27798 +/* 27788 */ MCD_OPC_CheckPredicate, 0, 19, 231, 0, // Skip to: 86948 +/* 27793 */ MCD_OPC_Decode, 201, 27, 137, 1, // Opcode: ST1H_D_IMM +/* 27798 */ MCD_OPC_FilterValue, 3, 9, 231, 0, // Skip to: 86948 +/* 27803 */ MCD_OPC_CheckPredicate, 0, 4, 231, 0, // Skip to: 86948 +/* 27808 */ MCD_OPC_Decode, 216, 28, 144, 1, // Opcode: ST4H_IMM +/* 27813 */ MCD_OPC_FilterValue, 4, 187, 0, 0, // Skip to: 28005 +/* 27818 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 27821 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 27859 +/* 27826 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27829 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 27844 +/* 27834 */ MCD_OPC_CheckPredicate, 0, 229, 230, 0, // Skip to: 86948 +/* 27839 */ MCD_OPC_Decode, 129, 29, 136, 1, // Opcode: STNT1W_ZRR +/* 27844 */ MCD_OPC_FilterValue, 1, 219, 230, 0, // Skip to: 86948 +/* 27849 */ MCD_OPC_CheckPredicate, 0, 214, 230, 0, // Skip to: 86948 +/* 27854 */ MCD_OPC_Decode, 157, 28, 139, 1, // Opcode: ST2W +/* 27859 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 27895 +/* 27864 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27867 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27881 +/* 27872 */ MCD_OPC_CheckPredicate, 0, 191, 230, 0, // Skip to: 86948 +/* 27877 */ MCD_OPC_Decode, 154, 27, 127, // Opcode: SST1W_D_UXTW +/* 27881 */ MCD_OPC_FilterValue, 1, 182, 230, 0, // Skip to: 86948 +/* 27886 */ MCD_OPC_CheckPredicate, 0, 177, 230, 0, // Skip to: 86948 +/* 27891 */ MCD_OPC_Decode, 155, 27, 127, // Opcode: SST1W_D_UXTW_SCALED +/* 27895 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 27931 +/* 27900 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27903 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27917 +/* 27908 */ MCD_OPC_CheckPredicate, 0, 155, 230, 0, // Skip to: 86948 +/* 27913 */ MCD_OPC_Decode, 149, 27, 127, // Opcode: SST1W_D +/* 27917 */ MCD_OPC_FilterValue, 1, 146, 230, 0, // Skip to: 86948 +/* 27922 */ MCD_OPC_CheckPredicate, 0, 141, 230, 0, // Skip to: 86948 +/* 27927 */ MCD_OPC_Decode, 151, 27, 127, // Opcode: SST1W_D_SCALED +/* 27931 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 27967 +/* 27936 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 27939 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 27953 +/* 27944 */ MCD_OPC_CheckPredicate, 0, 119, 230, 0, // Skip to: 86948 +/* 27949 */ MCD_OPC_Decode, 152, 27, 127, // Opcode: SST1W_D_SXTW +/* 27953 */ MCD_OPC_FilterValue, 1, 110, 230, 0, // Skip to: 86948 +/* 27958 */ MCD_OPC_CheckPredicate, 0, 105, 230, 0, // Skip to: 86948 +/* 27963 */ MCD_OPC_Decode, 153, 27, 127, // Opcode: SST1W_D_SXTW_SCALED +/* 27967 */ MCD_OPC_FilterValue, 7, 96, 230, 0, // Skip to: 86948 +/* 27972 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 27975 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 27990 +/* 27980 */ MCD_OPC_CheckPredicate, 0, 83, 230, 0, // Skip to: 86948 +/* 27985 */ MCD_OPC_Decode, 128, 29, 137, 1, // Opcode: STNT1W_ZRI +/* 27990 */ MCD_OPC_FilterValue, 3, 73, 230, 0, // Skip to: 86948 +/* 27995 */ MCD_OPC_CheckPredicate, 0, 68, 230, 0, // Skip to: 86948 +/* 28000 */ MCD_OPC_Decode, 158, 28, 140, 1, // Opcode: ST2W_IMM +/* 28005 */ MCD_OPC_FilterValue, 5, 1, 1, 0, // Skip to: 28267 +/* 28010 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 28013 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 28051 +/* 28018 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28021 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28036 +/* 28026 */ MCD_OPC_CheckPredicate, 0, 37, 230, 0, // Skip to: 86948 +/* 28031 */ MCD_OPC_Decode, 253, 27, 136, 1, // Opcode: ST1W +/* 28036 */ MCD_OPC_FilterValue, 1, 27, 230, 0, // Skip to: 86948 +/* 28041 */ MCD_OPC_CheckPredicate, 0, 22, 230, 0, // Skip to: 86948 +/* 28046 */ MCD_OPC_Decode, 254, 27, 136, 1, // Opcode: ST1W_D +/* 28051 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28089 +/* 28056 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28059 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28074 +/* 28064 */ MCD_OPC_CheckPredicate, 0, 255, 229, 0, // Skip to: 86948 +/* 28069 */ MCD_OPC_Decode, 187, 28, 141, 1, // Opcode: ST3W +/* 28074 */ MCD_OPC_FilterValue, 1, 245, 229, 0, // Skip to: 86948 +/* 28079 */ MCD_OPC_CheckPredicate, 0, 240, 229, 0, // Skip to: 86948 +/* 28084 */ MCD_OPC_Decode, 217, 28, 143, 1, // Opcode: ST4W +/* 28089 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 28125 +/* 28094 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28097 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28111 +/* 28102 */ MCD_OPC_CheckPredicate, 0, 217, 229, 0, // Skip to: 86948 +/* 28107 */ MCD_OPC_Decode, 159, 27, 127, // Opcode: SST1W_UXTW +/* 28111 */ MCD_OPC_FilterValue, 1, 208, 229, 0, // Skip to: 86948 +/* 28116 */ MCD_OPC_CheckPredicate, 0, 203, 229, 0, // Skip to: 86948 +/* 28121 */ MCD_OPC_Decode, 160, 27, 127, // Opcode: SST1W_UXTW_SCALED +/* 28125 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 28163 +/* 28130 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28133 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28148 +/* 28138 */ MCD_OPC_CheckPredicate, 0, 181, 229, 0, // Skip to: 86948 +/* 28143 */ MCD_OPC_Decode, 150, 27, 132, 1, // Opcode: SST1W_D_IMM +/* 28148 */ MCD_OPC_FilterValue, 1, 171, 229, 0, // Skip to: 86948 +/* 28153 */ MCD_OPC_CheckPredicate, 0, 166, 229, 0, // Skip to: 86948 +/* 28158 */ MCD_OPC_Decode, 156, 27, 132, 1, // Opcode: SST1W_IMM +/* 28163 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 28199 +/* 28168 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28171 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28185 +/* 28176 */ MCD_OPC_CheckPredicate, 0, 143, 229, 0, // Skip to: 86948 +/* 28181 */ MCD_OPC_Decode, 157, 27, 127, // Opcode: SST1W_SXTW +/* 28185 */ MCD_OPC_FilterValue, 1, 134, 229, 0, // Skip to: 86948 +/* 28190 */ MCD_OPC_CheckPredicate, 0, 129, 229, 0, // Skip to: 86948 +/* 28195 */ MCD_OPC_Decode, 158, 27, 127, // Opcode: SST1W_SXTW_SCALED +/* 28199 */ MCD_OPC_FilterValue, 7, 120, 229, 0, // Skip to: 86948 +/* 28204 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 28207 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28222 +/* 28212 */ MCD_OPC_CheckPredicate, 0, 107, 229, 0, // Skip to: 86948 +/* 28217 */ MCD_OPC_Decode, 128, 28, 137, 1, // Opcode: ST1W_IMM +/* 28222 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28237 +/* 28227 */ MCD_OPC_CheckPredicate, 0, 92, 229, 0, // Skip to: 86948 +/* 28232 */ MCD_OPC_Decode, 188, 28, 142, 1, // Opcode: ST3W_IMM +/* 28237 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28252 +/* 28242 */ MCD_OPC_CheckPredicate, 0, 77, 229, 0, // Skip to: 86948 +/* 28247 */ MCD_OPC_Decode, 255, 27, 137, 1, // Opcode: ST1W_D_IMM +/* 28252 */ MCD_OPC_FilterValue, 3, 67, 229, 0, // Skip to: 86948 +/* 28257 */ MCD_OPC_CheckPredicate, 0, 62, 229, 0, // Skip to: 86948 +/* 28262 */ MCD_OPC_Decode, 218, 28, 144, 1, // Opcode: ST4W_IMM +/* 28267 */ MCD_OPC_FilterValue, 6, 224, 0, 0, // Skip to: 28496 +/* 28272 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 28275 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 28297 +/* 28280 */ MCD_OPC_CheckPredicate, 0, 39, 229, 0, // Skip to: 86948 +/* 28285 */ MCD_OPC_CheckField, 4, 1, 0, 32, 229, 0, // Skip to: 86948 +/* 28292 */ MCD_OPC_Decode, 190, 29, 129, 1, // Opcode: STR_PXI +/* 28297 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28312 +/* 28302 */ MCD_OPC_CheckPredicate, 0, 17, 229, 0, // Skip to: 86948 +/* 28307 */ MCD_OPC_Decode, 191, 29, 131, 1, // Opcode: STR_ZXI +/* 28312 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28350 +/* 28317 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28320 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28335 +/* 28325 */ MCD_OPC_CheckPredicate, 0, 250, 228, 0, // Skip to: 86948 +/* 28330 */ MCD_OPC_Decode, 253, 28, 136, 1, // Opcode: STNT1D_ZRR +/* 28335 */ MCD_OPC_FilterValue, 1, 240, 228, 0, // Skip to: 86948 +/* 28340 */ MCD_OPC_CheckPredicate, 0, 235, 228, 0, // Skip to: 86948 +/* 28345 */ MCD_OPC_Decode, 139, 28, 139, 1, // Opcode: ST2D +/* 28350 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 28386 +/* 28355 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28358 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28372 +/* 28363 */ MCD_OPC_CheckPredicate, 0, 212, 228, 0, // Skip to: 86948 +/* 28368 */ MCD_OPC_Decode, 135, 27, 127, // Opcode: SST1D_UXTW +/* 28372 */ MCD_OPC_FilterValue, 1, 203, 228, 0, // Skip to: 86948 +/* 28377 */ MCD_OPC_CheckPredicate, 0, 198, 228, 0, // Skip to: 86948 +/* 28382 */ MCD_OPC_Decode, 136, 27, 127, // Opcode: SST1D_UXTW_SCALED +/* 28386 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 28422 +/* 28391 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28394 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28408 +/* 28399 */ MCD_OPC_CheckPredicate, 0, 176, 228, 0, // Skip to: 86948 +/* 28404 */ MCD_OPC_Decode, 130, 27, 127, // Opcode: SST1D +/* 28408 */ MCD_OPC_FilterValue, 1, 167, 228, 0, // Skip to: 86948 +/* 28413 */ MCD_OPC_CheckPredicate, 0, 162, 228, 0, // Skip to: 86948 +/* 28418 */ MCD_OPC_Decode, 132, 27, 127, // Opcode: SST1D_SCALED +/* 28422 */ MCD_OPC_FilterValue, 6, 31, 0, 0, // Skip to: 28458 +/* 28427 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28430 */ MCD_OPC_FilterValue, 0, 9, 0, 0, // Skip to: 28444 +/* 28435 */ MCD_OPC_CheckPredicate, 0, 140, 228, 0, // Skip to: 86948 +/* 28440 */ MCD_OPC_Decode, 133, 27, 127, // Opcode: SST1D_SXTW +/* 28444 */ MCD_OPC_FilterValue, 1, 131, 228, 0, // Skip to: 86948 +/* 28449 */ MCD_OPC_CheckPredicate, 0, 126, 228, 0, // Skip to: 86948 +/* 28454 */ MCD_OPC_Decode, 134, 27, 127, // Opcode: SST1D_SXTW_SCALED +/* 28458 */ MCD_OPC_FilterValue, 7, 117, 228, 0, // Skip to: 86948 +/* 28463 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 28466 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28481 +/* 28471 */ MCD_OPC_CheckPredicate, 0, 104, 228, 0, // Skip to: 86948 +/* 28476 */ MCD_OPC_Decode, 252, 28, 137, 1, // Opcode: STNT1D_ZRI +/* 28481 */ MCD_OPC_FilterValue, 3, 94, 228, 0, // Skip to: 86948 +/* 28486 */ MCD_OPC_CheckPredicate, 0, 89, 228, 0, // Skip to: 86948 +/* 28491 */ MCD_OPC_Decode, 140, 28, 140, 1, // Opcode: ST2D_IMM +/* 28496 */ MCD_OPC_FilterValue, 7, 79, 228, 0, // Skip to: 86948 +/* 28501 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 28504 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 28526 +/* 28509 */ MCD_OPC_CheckPredicate, 0, 66, 228, 0, // Skip to: 86948 +/* 28514 */ MCD_OPC_CheckField, 21, 1, 1, 59, 228, 0, // Skip to: 86948 +/* 28521 */ MCD_OPC_Decode, 181, 27, 136, 1, // Opcode: ST1D +/* 28526 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28564 +/* 28531 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28534 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28549 +/* 28539 */ MCD_OPC_CheckPredicate, 0, 36, 228, 0, // Skip to: 86948 +/* 28544 */ MCD_OPC_Decode, 169, 28, 141, 1, // Opcode: ST3D +/* 28549 */ MCD_OPC_FilterValue, 1, 26, 228, 0, // Skip to: 86948 +/* 28554 */ MCD_OPC_CheckPredicate, 0, 21, 228, 0, // Skip to: 86948 +/* 28559 */ MCD_OPC_Decode, 199, 28, 143, 1, // Opcode: ST4D +/* 28564 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 28586 +/* 28569 */ MCD_OPC_CheckPredicate, 0, 6, 228, 0, // Skip to: 86948 +/* 28574 */ MCD_OPC_CheckField, 21, 1, 0, 255, 227, 0, // Skip to: 86948 +/* 28581 */ MCD_OPC_Decode, 131, 27, 132, 1, // Opcode: SST1D_IMM +/* 28586 */ MCD_OPC_FilterValue, 7, 245, 227, 0, // Skip to: 86948 +/* 28591 */ MCD_OPC_ExtractField, 20, 2, // Inst{21-20} ... +/* 28594 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 28609 +/* 28599 */ MCD_OPC_CheckPredicate, 0, 232, 227, 0, // Skip to: 86948 +/* 28604 */ MCD_OPC_Decode, 170, 28, 142, 1, // Opcode: ST3D_IMM +/* 28609 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 28624 +/* 28614 */ MCD_OPC_CheckPredicate, 0, 217, 227, 0, // Skip to: 86948 +/* 28619 */ MCD_OPC_Decode, 182, 27, 137, 1, // Opcode: ST1D_IMM +/* 28624 */ MCD_OPC_FilterValue, 3, 207, 227, 0, // Skip to: 86948 +/* 28629 */ MCD_OPC_CheckPredicate, 0, 202, 227, 0, // Skip to: 86948 +/* 28634 */ MCD_OPC_Decode, 200, 28, 144, 1, // Opcode: ST4D_IMM +/* 28639 */ MCD_OPC_FilterValue, 2, 20, 8, 0, // Skip to: 30712 +/* 28644 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 28647 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 29030 +/* 28652 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 28655 */ MCD_OPC_FilterValue, 0, 51, 1, 0, // Skip to: 28967 +/* 28660 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 28663 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 28691 +/* 28668 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 28671 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 28681 +/* 28676 */ MCD_OPC_Decode, 207, 29, 145, 1, // Opcode: STXRB +/* 28681 */ MCD_OPC_FilterValue, 1, 150, 227, 0, // Skip to: 86948 +/* 28686 */ MCD_OPC_Decode, 241, 28, 145, 1, // Opcode: STLXRB +/* 28691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 28729 +/* 28696 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 28699 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28714 +/* 28704 */ MCD_OPC_CheckPredicate, 1, 127, 227, 0, // Skip to: 86948 +/* 28709 */ MCD_OPC_Decode, 244, 2, 146, 1, // Opcode: CASPW +/* 28714 */ MCD_OPC_FilterValue, 63, 117, 227, 0, // Skip to: 86948 +/* 28719 */ MCD_OPC_CheckPredicate, 1, 112, 227, 0, // Skip to: 86948 +/* 28724 */ MCD_OPC_Decode, 242, 2, 146, 1, // Opcode: CASPLW +/* 28729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 28767 +/* 28734 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 28737 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 28752 +/* 28742 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 28747 */ MCD_OPC_Decode, 146, 19, 145, 1, // Opcode: LDXRB +/* 28752 */ MCD_OPC_FilterValue, 1, 79, 227, 0, // Skip to: 86948 +/* 28757 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 28762 */ MCD_OPC_Decode, 240, 16, 145, 1, // Opcode: LDAXRB +/* 28767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 28805 +/* 28772 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 28775 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28790 +/* 28780 */ MCD_OPC_CheckPredicate, 1, 51, 227, 0, // Skip to: 86948 +/* 28785 */ MCD_OPC_Decode, 240, 2, 146, 1, // Opcode: CASPAW +/* 28790 */ MCD_OPC_FilterValue, 63, 41, 227, 0, // Skip to: 86948 +/* 28795 */ MCD_OPC_CheckPredicate, 1, 36, 227, 0, // Skip to: 86948 +/* 28800 */ MCD_OPC_Decode, 238, 2, 146, 1, // Opcode: CASPALW +/* 28805 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 28848 +/* 28810 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 28813 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 28833 +/* 28818 */ MCD_OPC_CheckPredicate, 2, 13, 227, 0, // Skip to: 86948 +/* 28823 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 28828 */ MCD_OPC_Decode, 227, 28, 145, 1, // Opcode: STLLRB +/* 28833 */ MCD_OPC_FilterValue, 1, 254, 226, 0, // Skip to: 86948 +/* 28838 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 28843 */ MCD_OPC_Decode, 231, 28, 145, 1, // Opcode: STLRB +/* 28848 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 28886 +/* 28853 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 28856 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28871 +/* 28861 */ MCD_OPC_CheckPredicate, 1, 226, 226, 0, // Skip to: 86948 +/* 28866 */ MCD_OPC_Decode, 232, 2, 147, 1, // Opcode: CASB +/* 28871 */ MCD_OPC_FilterValue, 63, 216, 226, 0, // Skip to: 86948 +/* 28876 */ MCD_OPC_CheckPredicate, 1, 211, 226, 0, // Skip to: 86948 +/* 28881 */ MCD_OPC_Decode, 234, 2, 147, 1, // Opcode: CASLB +/* 28886 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 28929 +/* 28891 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 28894 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 28914 +/* 28899 */ MCD_OPC_CheckPredicate, 2, 188, 226, 0, // Skip to: 86948 +/* 28904 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 28909 */ MCD_OPC_Decode, 164, 17, 145, 1, // Opcode: LDLARB +/* 28914 */ MCD_OPC_FilterValue, 1, 173, 226, 0, // Skip to: 86948 +/* 28919 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 28924 */ MCD_OPC_Decode, 234, 16, 145, 1, // Opcode: LDARB +/* 28929 */ MCD_OPC_FilterValue, 7, 158, 226, 0, // Skip to: 86948 +/* 28934 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 28937 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 28952 +/* 28942 */ MCD_OPC_CheckPredicate, 1, 145, 226, 0, // Skip to: 86948 +/* 28947 */ MCD_OPC_Decode, 224, 2, 147, 1, // Opcode: CASAB +/* 28952 */ MCD_OPC_FilterValue, 63, 135, 226, 0, // Skip to: 86948 +/* 28957 */ MCD_OPC_CheckPredicate, 1, 130, 226, 0, // Skip to: 86948 +/* 28962 */ MCD_OPC_Decode, 226, 2, 147, 1, // Opcode: CASALB +/* 28967 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 28995 +/* 28972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 28975 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 28985 +/* 28980 */ MCD_OPC_Decode, 241, 1, 148, 1, // Opcode: ANDWrs +/* 28985 */ MCD_OPC_FilterValue, 1, 102, 226, 0, // Skip to: 86948 +/* 28990 */ MCD_OPC_Decode, 178, 2, 148, 1, // Opcode: BICWrs +/* 28995 */ MCD_OPC_FilterValue, 3, 92, 226, 0, // Skip to: 86948 +/* 29000 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29003 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29013 +/* 29008 */ MCD_OPC_Decode, 174, 1, 148, 1, // Opcode: ADDWrs +/* 29013 */ MCD_OPC_FilterValue, 1, 74, 226, 0, // Skip to: 86948 +/* 29018 */ MCD_OPC_CheckField, 22, 2, 0, 67, 226, 0, // Skip to: 86948 +/* 29025 */ MCD_OPC_Decode, 175, 1, 149, 1, // Opcode: ADDWrx +/* 29030 */ MCD_OPC_FilterValue, 1, 162, 0, 0, // Skip to: 29197 +/* 29035 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 29038 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 29086 +/* 29043 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 29046 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29056 +/* 29051 */ MCD_OPC_Decode, 248, 28, 150, 1, // Opcode: STNPWi +/* 29056 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29066 +/* 29061 */ MCD_OPC_Decode, 187, 17, 150, 1, // Opcode: LDNPWi +/* 29066 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 29076 +/* 29071 */ MCD_OPC_Decode, 140, 29, 150, 1, // Opcode: STPWpost +/* 29076 */ MCD_OPC_FilterValue, 3, 11, 226, 0, // Skip to: 86948 +/* 29081 */ MCD_OPC_Decode, 210, 17, 150, 1, // Opcode: LDPWpost +/* 29086 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 29134 +/* 29091 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 29094 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29104 +/* 29099 */ MCD_OPC_Decode, 139, 29, 150, 1, // Opcode: STPWi +/* 29104 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29114 +/* 29109 */ MCD_OPC_Decode, 209, 17, 150, 1, // Opcode: LDPWi +/* 29114 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 29124 +/* 29119 */ MCD_OPC_Decode, 141, 29, 150, 1, // Opcode: STPWpre +/* 29124 */ MCD_OPC_FilterValue, 3, 219, 225, 0, // Skip to: 86948 +/* 29129 */ MCD_OPC_Decode, 211, 17, 150, 1, // Opcode: LDPWpre +/* 29134 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29162 +/* 29139 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29142 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29152 +/* 29147 */ MCD_OPC_Decode, 206, 20, 148, 1, // Opcode: ORRWrs +/* 29152 */ MCD_OPC_FilterValue, 1, 191, 225, 0, // Skip to: 86948 +/* 29157 */ MCD_OPC_Decode, 197, 20, 148, 1, // Opcode: ORNWrs +/* 29162 */ MCD_OPC_FilterValue, 3, 181, 225, 0, // Skip to: 86948 +/* 29167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29170 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29180 +/* 29175 */ MCD_OPC_Decode, 159, 1, 148, 1, // Opcode: ADDSWrs +/* 29180 */ MCD_OPC_FilterValue, 1, 163, 225, 0, // Skip to: 86948 +/* 29185 */ MCD_OPC_CheckField, 22, 2, 0, 156, 225, 0, // Skip to: 86948 +/* 29192 */ MCD_OPC_Decode, 160, 1, 149, 1, // Opcode: ADDSWrx +/* 29197 */ MCD_OPC_FilterValue, 2, 122, 1, 0, // Skip to: 29580 +/* 29202 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 29205 */ MCD_OPC_FilterValue, 0, 51, 1, 0, // Skip to: 29517 +/* 29210 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 29213 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 29241 +/* 29218 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29221 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29231 +/* 29226 */ MCD_OPC_Decode, 208, 29, 145, 1, // Opcode: STXRH +/* 29231 */ MCD_OPC_FilterValue, 1, 112, 225, 0, // Skip to: 86948 +/* 29236 */ MCD_OPC_Decode, 242, 28, 145, 1, // Opcode: STLXRH +/* 29241 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 29279 +/* 29246 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 29249 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29264 +/* 29254 */ MCD_OPC_CheckPredicate, 1, 89, 225, 0, // Skip to: 86948 +/* 29259 */ MCD_OPC_Decode, 245, 2, 151, 1, // Opcode: CASPX +/* 29264 */ MCD_OPC_FilterValue, 63, 79, 225, 0, // Skip to: 86948 +/* 29269 */ MCD_OPC_CheckPredicate, 1, 74, 225, 0, // Skip to: 86948 +/* 29274 */ MCD_OPC_Decode, 243, 2, 151, 1, // Opcode: CASPLX +/* 29279 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 29317 +/* 29284 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29287 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 29302 +/* 29292 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29297 */ MCD_OPC_Decode, 147, 19, 145, 1, // Opcode: LDXRH +/* 29302 */ MCD_OPC_FilterValue, 1, 41, 225, 0, // Skip to: 86948 +/* 29307 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29312 */ MCD_OPC_Decode, 241, 16, 145, 1, // Opcode: LDAXRH +/* 29317 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 29355 +/* 29322 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 29325 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29340 +/* 29330 */ MCD_OPC_CheckPredicate, 1, 13, 225, 0, // Skip to: 86948 +/* 29335 */ MCD_OPC_Decode, 241, 2, 151, 1, // Opcode: CASPAX +/* 29340 */ MCD_OPC_FilterValue, 63, 3, 225, 0, // Skip to: 86948 +/* 29345 */ MCD_OPC_CheckPredicate, 1, 254, 224, 0, // Skip to: 86948 +/* 29350 */ MCD_OPC_Decode, 239, 2, 151, 1, // Opcode: CASPALX +/* 29355 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 29398 +/* 29360 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29363 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29383 +/* 29368 */ MCD_OPC_CheckPredicate, 2, 231, 224, 0, // Skip to: 86948 +/* 29373 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29378 */ MCD_OPC_Decode, 228, 28, 145, 1, // Opcode: STLLRH +/* 29383 */ MCD_OPC_FilterValue, 1, 216, 224, 0, // Skip to: 86948 +/* 29388 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29393 */ MCD_OPC_Decode, 232, 28, 145, 1, // Opcode: STLRH +/* 29398 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 29436 +/* 29403 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 29406 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29421 +/* 29411 */ MCD_OPC_CheckPredicate, 1, 188, 224, 0, // Skip to: 86948 +/* 29416 */ MCD_OPC_Decode, 233, 2, 147, 1, // Opcode: CASH +/* 29421 */ MCD_OPC_FilterValue, 63, 178, 224, 0, // Skip to: 86948 +/* 29426 */ MCD_OPC_CheckPredicate, 1, 173, 224, 0, // Skip to: 86948 +/* 29431 */ MCD_OPC_Decode, 235, 2, 147, 1, // Opcode: CASLH +/* 29436 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 29479 +/* 29441 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29444 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29464 +/* 29449 */ MCD_OPC_CheckPredicate, 2, 150, 224, 0, // Skip to: 86948 +/* 29454 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29459 */ MCD_OPC_Decode, 165, 17, 145, 1, // Opcode: LDLARH +/* 29464 */ MCD_OPC_FilterValue, 1, 135, 224, 0, // Skip to: 86948 +/* 29469 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29474 */ MCD_OPC_Decode, 235, 16, 145, 1, // Opcode: LDARH +/* 29479 */ MCD_OPC_FilterValue, 7, 120, 224, 0, // Skip to: 86948 +/* 29484 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 29487 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29502 +/* 29492 */ MCD_OPC_CheckPredicate, 1, 107, 224, 0, // Skip to: 86948 +/* 29497 */ MCD_OPC_Decode, 225, 2, 147, 1, // Opcode: CASAH +/* 29502 */ MCD_OPC_FilterValue, 63, 97, 224, 0, // Skip to: 86948 +/* 29507 */ MCD_OPC_CheckPredicate, 1, 92, 224, 0, // Skip to: 86948 +/* 29512 */ MCD_OPC_Decode, 227, 2, 147, 1, // Opcode: CASALH +/* 29517 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29545 +/* 29522 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29525 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29535 +/* 29530 */ MCD_OPC_Decode, 234, 5, 148, 1, // Opcode: EORWrs +/* 29535 */ MCD_OPC_FilterValue, 1, 64, 224, 0, // Skip to: 86948 +/* 29540 */ MCD_OPC_Decode, 223, 5, 148, 1, // Opcode: EONWrs +/* 29545 */ MCD_OPC_FilterValue, 3, 54, 224, 0, // Skip to: 86948 +/* 29550 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29553 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29563 +/* 29558 */ MCD_OPC_Decode, 236, 29, 148, 1, // Opcode: SUBWrs +/* 29563 */ MCD_OPC_FilterValue, 1, 36, 224, 0, // Skip to: 86948 +/* 29568 */ MCD_OPC_CheckField, 22, 2, 0, 29, 224, 0, // Skip to: 86948 +/* 29575 */ MCD_OPC_Decode, 237, 29, 149, 1, // Opcode: SUBWrx +/* 29580 */ MCD_OPC_FilterValue, 3, 111, 0, 0, // Skip to: 29696 +/* 29585 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 29588 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 29605 +/* 29593 */ MCD_OPC_CheckField, 22, 2, 3, 4, 224, 0, // Skip to: 86948 +/* 29600 */ MCD_OPC_Decode, 204, 17, 150, 1, // Opcode: LDPSWpost +/* 29605 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 29633 +/* 29610 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 29613 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 29623 +/* 29618 */ MCD_OPC_Decode, 203, 17, 150, 1, // Opcode: LDPSWi +/* 29623 */ MCD_OPC_FilterValue, 3, 232, 223, 0, // Skip to: 86948 +/* 29628 */ MCD_OPC_Decode, 205, 17, 150, 1, // Opcode: LDPSWpre +/* 29633 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 29661 +/* 29638 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29641 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29651 +/* 29646 */ MCD_OPC_Decode, 230, 1, 148, 1, // Opcode: ANDSWrs +/* 29651 */ MCD_OPC_FilterValue, 1, 204, 223, 0, // Skip to: 86948 +/* 29656 */ MCD_OPC_Decode, 173, 2, 148, 1, // Opcode: BICSWrs +/* 29661 */ MCD_OPC_FilterValue, 3, 194, 223, 0, // Skip to: 86948 +/* 29666 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 29669 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29679 +/* 29674 */ MCD_OPC_Decode, 227, 29, 148, 1, // Opcode: SUBSWrs +/* 29679 */ MCD_OPC_FilterValue, 1, 176, 223, 0, // Skip to: 86948 +/* 29684 */ MCD_OPC_CheckField, 22, 2, 0, 169, 223, 0, // Skip to: 86948 +/* 29691 */ MCD_OPC_Decode, 228, 29, 149, 1, // Opcode: SUBSWrx +/* 29696 */ MCD_OPC_FilterValue, 4, 115, 1, 0, // Skip to: 30072 +/* 29701 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 29704 */ MCD_OPC_FilterValue, 0, 31, 1, 0, // Skip to: 29996 +/* 29709 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 29712 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 29740 +/* 29717 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29720 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29730 +/* 29725 */ MCD_OPC_Decode, 209, 29, 145, 1, // Opcode: STXRW +/* 29730 */ MCD_OPC_FilterValue, 1, 125, 223, 0, // Skip to: 86948 +/* 29735 */ MCD_OPC_Decode, 243, 28, 145, 1, // Opcode: STLXRW +/* 29740 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 29768 +/* 29745 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29748 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29758 +/* 29753 */ MCD_OPC_Decode, 205, 29, 145, 1, // Opcode: STXPW +/* 29758 */ MCD_OPC_FilterValue, 1, 97, 223, 0, // Skip to: 86948 +/* 29763 */ MCD_OPC_Decode, 239, 28, 145, 1, // Opcode: STLXPW +/* 29768 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 29806 +/* 29773 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 29791 +/* 29781 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29786 */ MCD_OPC_Decode, 148, 19, 145, 1, // Opcode: LDXRW +/* 29791 */ MCD_OPC_FilterValue, 1, 64, 223, 0, // Skip to: 86948 +/* 29796 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29801 */ MCD_OPC_Decode, 242, 16, 145, 1, // Opcode: LDAXRW +/* 29806 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 29834 +/* 29811 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29814 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 29824 +/* 29819 */ MCD_OPC_Decode, 144, 19, 145, 1, // Opcode: LDXPW +/* 29824 */ MCD_OPC_FilterValue, 1, 31, 223, 0, // Skip to: 86948 +/* 29829 */ MCD_OPC_Decode, 238, 16, 145, 1, // Opcode: LDAXPW +/* 29834 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 29877 +/* 29839 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29842 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29862 +/* 29847 */ MCD_OPC_CheckPredicate, 2, 8, 223, 0, // Skip to: 86948 +/* 29852 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29857 */ MCD_OPC_Decode, 229, 28, 145, 1, // Opcode: STLLRW +/* 29862 */ MCD_OPC_FilterValue, 1, 249, 222, 0, // Skip to: 86948 +/* 29867 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29872 */ MCD_OPC_Decode, 233, 28, 145, 1, // Opcode: STLRW +/* 29877 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 29915 +/* 29882 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 29885 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29900 +/* 29890 */ MCD_OPC_CheckPredicate, 1, 221, 222, 0, // Skip to: 86948 +/* 29895 */ MCD_OPC_Decode, 246, 2, 147, 1, // Opcode: CASW +/* 29900 */ MCD_OPC_FilterValue, 63, 211, 222, 0, // Skip to: 86948 +/* 29905 */ MCD_OPC_CheckPredicate, 1, 206, 222, 0, // Skip to: 86948 +/* 29910 */ MCD_OPC_Decode, 236, 2, 147, 1, // Opcode: CASLW +/* 29915 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 29958 +/* 29920 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 29923 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 29943 +/* 29928 */ MCD_OPC_CheckPredicate, 2, 183, 222, 0, // Skip to: 86948 +/* 29933 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29938 */ MCD_OPC_Decode, 166, 17, 145, 1, // Opcode: LDLARW +/* 29943 */ MCD_OPC_FilterValue, 1, 168, 222, 0, // Skip to: 86948 +/* 29948 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 29953 */ MCD_OPC_Decode, 236, 16, 145, 1, // Opcode: LDARW +/* 29958 */ MCD_OPC_FilterValue, 7, 153, 222, 0, // Skip to: 86948 +/* 29963 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 29966 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 29981 +/* 29971 */ MCD_OPC_CheckPredicate, 1, 140, 222, 0, // Skip to: 86948 +/* 29976 */ MCD_OPC_Decode, 230, 2, 147, 1, // Opcode: CASAW +/* 29981 */ MCD_OPC_FilterValue, 63, 130, 222, 0, // Skip to: 86948 +/* 29986 */ MCD_OPC_CheckPredicate, 1, 125, 222, 0, // Skip to: 86948 +/* 29991 */ MCD_OPC_Decode, 228, 2, 147, 1, // Opcode: CASALW +/* 29996 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30024 +/* 30001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30004 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30014 +/* 30009 */ MCD_OPC_Decode, 244, 1, 148, 1, // Opcode: ANDXrs +/* 30014 */ MCD_OPC_FilterValue, 1, 97, 222, 0, // Skip to: 86948 +/* 30019 */ MCD_OPC_Decode, 180, 2, 148, 1, // Opcode: BICXrs +/* 30024 */ MCD_OPC_FilterValue, 3, 87, 222, 0, // Skip to: 86948 +/* 30029 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30032 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30042 +/* 30037 */ MCD_OPC_Decode, 178, 1, 148, 1, // Opcode: ADDXrs +/* 30042 */ MCD_OPC_FilterValue, 1, 69, 222, 0, // Skip to: 86948 +/* 30047 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 30050 */ MCD_OPC_FilterValue, 0, 61, 222, 0, // Skip to: 86948 +/* 30055 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30067 +/* 30062 */ MCD_OPC_Decode, 180, 1, 149, 1, // Opcode: ADDXrx64 +/* 30067 */ MCD_OPC_Decode, 179, 1, 149, 1, // Opcode: ADDXrx +/* 30072 */ MCD_OPC_FilterValue, 5, 175, 0, 0, // Skip to: 30252 +/* 30077 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 30080 */ MCD_OPC_FilterValue, 0, 43, 0, 0, // Skip to: 30128 +/* 30085 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 30088 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30098 +/* 30093 */ MCD_OPC_Decode, 249, 28, 150, 1, // Opcode: STNPXi +/* 30098 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 30108 +/* 30103 */ MCD_OPC_Decode, 188, 17, 150, 1, // Opcode: LDNPXi +/* 30108 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30118 +/* 30113 */ MCD_OPC_Decode, 143, 29, 150, 1, // Opcode: STPXpost +/* 30118 */ MCD_OPC_FilterValue, 3, 249, 221, 0, // Skip to: 86948 +/* 30123 */ MCD_OPC_Decode, 213, 17, 150, 1, // Opcode: LDPXpost +/* 30128 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 30176 +/* 30133 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 30136 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30146 +/* 30141 */ MCD_OPC_Decode, 142, 29, 150, 1, // Opcode: STPXi +/* 30146 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 30156 +/* 30151 */ MCD_OPC_Decode, 212, 17, 150, 1, // Opcode: LDPXi +/* 30156 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30166 +/* 30161 */ MCD_OPC_Decode, 144, 29, 150, 1, // Opcode: STPXpre +/* 30166 */ MCD_OPC_FilterValue, 3, 201, 221, 0, // Skip to: 86948 +/* 30171 */ MCD_OPC_Decode, 214, 17, 150, 1, // Opcode: LDPXpre +/* 30176 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30204 +/* 30181 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30184 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30194 +/* 30189 */ MCD_OPC_Decode, 209, 20, 148, 1, // Opcode: ORRXrs +/* 30194 */ MCD_OPC_FilterValue, 1, 173, 221, 0, // Skip to: 86948 +/* 30199 */ MCD_OPC_Decode, 199, 20, 148, 1, // Opcode: ORNXrs +/* 30204 */ MCD_OPC_FilterValue, 3, 163, 221, 0, // Skip to: 86948 +/* 30209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30212 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30222 +/* 30217 */ MCD_OPC_Decode, 163, 1, 148, 1, // Opcode: ADDSXrs +/* 30222 */ MCD_OPC_FilterValue, 1, 145, 221, 0, // Skip to: 86948 +/* 30227 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 30230 */ MCD_OPC_FilterValue, 0, 137, 221, 0, // Skip to: 86948 +/* 30235 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30247 +/* 30242 */ MCD_OPC_Decode, 165, 1, 149, 1, // Opcode: ADDSXrx64 +/* 30247 */ MCD_OPC_Decode, 164, 1, 149, 1, // Opcode: ADDSXrx +/* 30252 */ MCD_OPC_FilterValue, 6, 115, 1, 0, // Skip to: 30628 +/* 30257 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 30260 */ MCD_OPC_FilterValue, 0, 31, 1, 0, // Skip to: 30552 +/* 30265 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 30268 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 30296 +/* 30273 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30276 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30286 +/* 30281 */ MCD_OPC_Decode, 210, 29, 145, 1, // Opcode: STXRX +/* 30286 */ MCD_OPC_FilterValue, 1, 81, 221, 0, // Skip to: 86948 +/* 30291 */ MCD_OPC_Decode, 244, 28, 145, 1, // Opcode: STLXRX +/* 30296 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 30324 +/* 30301 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30304 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30314 +/* 30309 */ MCD_OPC_Decode, 206, 29, 145, 1, // Opcode: STXPX +/* 30314 */ MCD_OPC_FilterValue, 1, 53, 221, 0, // Skip to: 86948 +/* 30319 */ MCD_OPC_Decode, 240, 28, 145, 1, // Opcode: STLXPX +/* 30324 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 30362 +/* 30329 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30332 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 30347 +/* 30337 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 30342 */ MCD_OPC_Decode, 149, 19, 145, 1, // Opcode: LDXRX +/* 30347 */ MCD_OPC_FilterValue, 1, 20, 221, 0, // Skip to: 86948 +/* 30352 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 30357 */ MCD_OPC_Decode, 243, 16, 145, 1, // Opcode: LDAXRX +/* 30362 */ MCD_OPC_FilterValue, 3, 23, 0, 0, // Skip to: 30390 +/* 30367 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30370 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30380 +/* 30375 */ MCD_OPC_Decode, 145, 19, 145, 1, // Opcode: LDXPX +/* 30380 */ MCD_OPC_FilterValue, 1, 243, 220, 0, // Skip to: 86948 +/* 30385 */ MCD_OPC_Decode, 239, 16, 145, 1, // Opcode: LDAXPX +/* 30390 */ MCD_OPC_FilterValue, 4, 38, 0, 0, // Skip to: 30433 +/* 30395 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30398 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 30418 +/* 30403 */ MCD_OPC_CheckPredicate, 2, 220, 220, 0, // Skip to: 86948 +/* 30408 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 30413 */ MCD_OPC_Decode, 230, 28, 145, 1, // Opcode: STLLRX +/* 30418 */ MCD_OPC_FilterValue, 1, 205, 220, 0, // Skip to: 86948 +/* 30423 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 30428 */ MCD_OPC_Decode, 234, 28, 145, 1, // Opcode: STLRX +/* 30433 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 30471 +/* 30438 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 30441 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 30456 +/* 30446 */ MCD_OPC_CheckPredicate, 1, 177, 220, 0, // Skip to: 86948 +/* 30451 */ MCD_OPC_Decode, 247, 2, 152, 1, // Opcode: CASX +/* 30456 */ MCD_OPC_FilterValue, 63, 167, 220, 0, // Skip to: 86948 +/* 30461 */ MCD_OPC_CheckPredicate, 1, 162, 220, 0, // Skip to: 86948 +/* 30466 */ MCD_OPC_Decode, 237, 2, 152, 1, // Opcode: CASLX +/* 30471 */ MCD_OPC_FilterValue, 6, 38, 0, 0, // Skip to: 30514 +/* 30476 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 30479 */ MCD_OPC_FilterValue, 0, 15, 0, 0, // Skip to: 30499 +/* 30484 */ MCD_OPC_CheckPredicate, 2, 139, 220, 0, // Skip to: 86948 +/* 30489 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 30494 */ MCD_OPC_Decode, 167, 17, 145, 1, // Opcode: LDLARX +/* 30499 */ MCD_OPC_FilterValue, 1, 124, 220, 0, // Skip to: 86948 +/* 30504 */ MCD_OPC_SoftFail, 0, 128, 248, 125 /* 0x1f7c00 */, +/* 30509 */ MCD_OPC_Decode, 237, 16, 145, 1, // Opcode: LDARX +/* 30514 */ MCD_OPC_FilterValue, 7, 109, 220, 0, // Skip to: 86948 +/* 30519 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 30522 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 30537 +/* 30527 */ MCD_OPC_CheckPredicate, 1, 96, 220, 0, // Skip to: 86948 +/* 30532 */ MCD_OPC_Decode, 231, 2, 152, 1, // Opcode: CASAX +/* 30537 */ MCD_OPC_FilterValue, 63, 86, 220, 0, // Skip to: 86948 +/* 30542 */ MCD_OPC_CheckPredicate, 1, 81, 220, 0, // Skip to: 86948 +/* 30547 */ MCD_OPC_Decode, 229, 2, 152, 1, // Opcode: CASALX +/* 30552 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 30580 +/* 30557 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30560 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30570 +/* 30565 */ MCD_OPC_Decode, 237, 5, 148, 1, // Opcode: EORXrs +/* 30570 */ MCD_OPC_FilterValue, 1, 53, 220, 0, // Skip to: 86948 +/* 30575 */ MCD_OPC_Decode, 225, 5, 148, 1, // Opcode: EONXrs +/* 30580 */ MCD_OPC_FilterValue, 3, 43, 220, 0, // Skip to: 86948 +/* 30585 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30588 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 30598 +/* 30593 */ MCD_OPC_Decode, 240, 29, 148, 1, // Opcode: SUBXrs +/* 30598 */ MCD_OPC_FilterValue, 1, 25, 220, 0, // Skip to: 86948 +/* 30603 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 30606 */ MCD_OPC_FilterValue, 0, 17, 220, 0, // Skip to: 86948 +/* 30611 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30623 +/* 30618 */ MCD_OPC_Decode, 242, 29, 149, 1, // Opcode: SUBXrx64 +/* 30623 */ MCD_OPC_Decode, 241, 29, 149, 1, // Opcode: SUBXrx +/* 30628 */ MCD_OPC_FilterValue, 7, 251, 219, 0, // Skip to: 86948 +/* 30633 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 30636 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 30664 +/* 30641 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 30644 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30654 +/* 30649 */ MCD_OPC_Decode, 233, 1, 148, 1, // Opcode: ANDSXrs +/* 30654 */ MCD_OPC_FilterValue, 3, 225, 219, 0, // Skip to: 86948 +/* 30659 */ MCD_OPC_Decode, 231, 29, 148, 1, // Opcode: SUBSXrs +/* 30664 */ MCD_OPC_FilterValue, 1, 215, 219, 0, // Skip to: 86948 +/* 30669 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 30672 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 30682 +/* 30677 */ MCD_OPC_Decode, 175, 2, 148, 1, // Opcode: BICSXrs +/* 30682 */ MCD_OPC_FilterValue, 3, 197, 219, 0, // Skip to: 86948 +/* 30687 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 30690 */ MCD_OPC_FilterValue, 0, 189, 219, 0, // Skip to: 86948 +/* 30695 */ MCD_OPC_CheckField, 13, 2, 3, 5, 0, 0, // Skip to: 30707 +/* 30702 */ MCD_OPC_Decode, 233, 29, 149, 1, // Opcode: SUBSXrx64 +/* 30707 */ MCD_OPC_Decode, 232, 29, 149, 1, // Opcode: SUBSXrx +/* 30712 */ MCD_OPC_FilterValue, 3, 166, 145, 0, // Skip to: 68003 +/* 30717 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 30720 */ MCD_OPC_FilterValue, 0, 76, 3, 0, // Skip to: 31569 +/* 30725 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 30728 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 31111 +/* 30733 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 30736 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 30751 +/* 30741 */ MCD_OPC_CheckPredicate, 3, 138, 219, 0, // Skip to: 86948 +/* 30746 */ MCD_OPC_Decode, 211, 28, 153, 1, // Opcode: ST4Fourv8b +/* 30751 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 30766 +/* 30756 */ MCD_OPC_CheckPredicate, 3, 123, 219, 0, // Skip to: 86948 +/* 30761 */ MCD_OPC_Decode, 207, 28, 153, 1, // Opcode: ST4Fourv4h +/* 30766 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 30781 +/* 30771 */ MCD_OPC_CheckPredicate, 3, 108, 219, 0, // Skip to: 86948 +/* 30776 */ MCD_OPC_Decode, 205, 28, 153, 1, // Opcode: ST4Fourv2s +/* 30781 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 30796 +/* 30786 */ MCD_OPC_CheckPredicate, 3, 93, 219, 0, // Skip to: 86948 +/* 30791 */ MCD_OPC_Decode, 195, 27, 153, 1, // Opcode: ST1Fourv8b +/* 30796 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 30811 +/* 30801 */ MCD_OPC_CheckPredicate, 3, 78, 219, 0, // Skip to: 86948 +/* 30806 */ MCD_OPC_Decode, 191, 27, 153, 1, // Opcode: ST1Fourv4h +/* 30811 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 30826 +/* 30816 */ MCD_OPC_CheckPredicate, 3, 63, 219, 0, // Skip to: 86948 +/* 30821 */ MCD_OPC_Decode, 189, 27, 153, 1, // Opcode: ST1Fourv2s +/* 30826 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 30841 +/* 30831 */ MCD_OPC_CheckPredicate, 3, 48, 219, 0, // Skip to: 86948 +/* 30836 */ MCD_OPC_Decode, 185, 27, 153, 1, // Opcode: ST1Fourv1d +/* 30841 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 30856 +/* 30846 */ MCD_OPC_CheckPredicate, 3, 33, 219, 0, // Skip to: 86948 +/* 30851 */ MCD_OPC_Decode, 183, 28, 154, 1, // Opcode: ST3Threev8b +/* 30856 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 30871 +/* 30861 */ MCD_OPC_CheckPredicate, 3, 18, 219, 0, // Skip to: 86948 +/* 30866 */ MCD_OPC_Decode, 179, 28, 154, 1, // Opcode: ST3Threev4h +/* 30871 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 30886 +/* 30876 */ MCD_OPC_CheckPredicate, 3, 3, 219, 0, // Skip to: 86948 +/* 30881 */ MCD_OPC_Decode, 177, 28, 154, 1, // Opcode: ST3Threev2s +/* 30886 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 30901 +/* 30891 */ MCD_OPC_CheckPredicate, 3, 244, 218, 0, // Skip to: 86948 +/* 30896 */ MCD_OPC_Decode, 233, 27, 154, 1, // Opcode: ST1Threev8b +/* 30901 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 30916 +/* 30906 */ MCD_OPC_CheckPredicate, 3, 229, 218, 0, // Skip to: 86948 +/* 30911 */ MCD_OPC_Decode, 229, 27, 154, 1, // Opcode: ST1Threev4h +/* 30916 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 30931 +/* 30921 */ MCD_OPC_CheckPredicate, 3, 214, 218, 0, // Skip to: 86948 +/* 30926 */ MCD_OPC_Decode, 227, 27, 154, 1, // Opcode: ST1Threev2s +/* 30931 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 30946 +/* 30936 */ MCD_OPC_CheckPredicate, 3, 199, 218, 0, // Skip to: 86948 +/* 30941 */ MCD_OPC_Decode, 223, 27, 154, 1, // Opcode: ST1Threev1d +/* 30946 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 30961 +/* 30951 */ MCD_OPC_CheckPredicate, 3, 184, 218, 0, // Skip to: 86948 +/* 30956 */ MCD_OPC_Decode, 217, 27, 155, 1, // Opcode: ST1Onev8b +/* 30961 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 30976 +/* 30966 */ MCD_OPC_CheckPredicate, 3, 169, 218, 0, // Skip to: 86948 +/* 30971 */ MCD_OPC_Decode, 213, 27, 155, 1, // Opcode: ST1Onev4h +/* 30976 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 30991 +/* 30981 */ MCD_OPC_CheckPredicate, 3, 154, 218, 0, // Skip to: 86948 +/* 30986 */ MCD_OPC_Decode, 211, 27, 155, 1, // Opcode: ST1Onev2s +/* 30991 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31006 +/* 30996 */ MCD_OPC_CheckPredicate, 3, 139, 218, 0, // Skip to: 86948 +/* 31001 */ MCD_OPC_Decode, 207, 27, 155, 1, // Opcode: ST1Onev1d +/* 31006 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31021 +/* 31011 */ MCD_OPC_CheckPredicate, 3, 124, 218, 0, // Skip to: 86948 +/* 31016 */ MCD_OPC_Decode, 153, 28, 156, 1, // Opcode: ST2Twov8b +/* 31021 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31036 +/* 31026 */ MCD_OPC_CheckPredicate, 3, 109, 218, 0, // Skip to: 86948 +/* 31031 */ MCD_OPC_Decode, 149, 28, 156, 1, // Opcode: ST2Twov4h +/* 31036 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31051 +/* 31041 */ MCD_OPC_CheckPredicate, 3, 94, 218, 0, // Skip to: 86948 +/* 31046 */ MCD_OPC_Decode, 147, 28, 156, 1, // Opcode: ST2Twov2s +/* 31051 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31066 +/* 31056 */ MCD_OPC_CheckPredicate, 3, 79, 218, 0, // Skip to: 86948 +/* 31061 */ MCD_OPC_Decode, 249, 27, 156, 1, // Opcode: ST1Twov8b +/* 31066 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31081 +/* 31071 */ MCD_OPC_CheckPredicate, 3, 64, 218, 0, // Skip to: 86948 +/* 31076 */ MCD_OPC_Decode, 245, 27, 156, 1, // Opcode: ST1Twov4h +/* 31081 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31096 +/* 31086 */ MCD_OPC_CheckPredicate, 3, 49, 218, 0, // Skip to: 86948 +/* 31091 */ MCD_OPC_Decode, 243, 27, 156, 1, // Opcode: ST1Twov2s +/* 31096 */ MCD_OPC_FilterValue, 43, 39, 218, 0, // Skip to: 86948 +/* 31101 */ MCD_OPC_CheckPredicate, 3, 34, 218, 0, // Skip to: 86948 +/* 31106 */ MCD_OPC_Decode, 239, 27, 156, 1, // Opcode: ST1Twov1d +/* 31111 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 31121 +/* 31116 */ MCD_OPC_Decode, 247, 28, 150, 1, // Opcode: STNPSi +/* 31121 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 31549 +/* 31126 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 31129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31144 +/* 31134 */ MCD_OPC_CheckPredicate, 3, 1, 218, 0, // Skip to: 86948 +/* 31139 */ MCD_OPC_Decode, 201, 28, 157, 1, // Opcode: ST4Fourv16b +/* 31144 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 31159 +/* 31149 */ MCD_OPC_CheckPredicate, 3, 242, 217, 0, // Skip to: 86948 +/* 31154 */ MCD_OPC_Decode, 213, 28, 157, 1, // Opcode: ST4Fourv8h +/* 31159 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 31174 +/* 31164 */ MCD_OPC_CheckPredicate, 3, 227, 217, 0, // Skip to: 86948 +/* 31169 */ MCD_OPC_Decode, 209, 28, 157, 1, // Opcode: ST4Fourv4s +/* 31174 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 31189 +/* 31179 */ MCD_OPC_CheckPredicate, 3, 212, 217, 0, // Skip to: 86948 +/* 31184 */ MCD_OPC_Decode, 203, 28, 157, 1, // Opcode: ST4Fourv2d +/* 31189 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 31204 +/* 31194 */ MCD_OPC_CheckPredicate, 3, 197, 217, 0, // Skip to: 86948 +/* 31199 */ MCD_OPC_Decode, 183, 27, 157, 1, // Opcode: ST1Fourv16b +/* 31204 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 31219 +/* 31209 */ MCD_OPC_CheckPredicate, 3, 182, 217, 0, // Skip to: 86948 +/* 31214 */ MCD_OPC_Decode, 197, 27, 157, 1, // Opcode: ST1Fourv8h +/* 31219 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 31234 +/* 31224 */ MCD_OPC_CheckPredicate, 3, 167, 217, 0, // Skip to: 86948 +/* 31229 */ MCD_OPC_Decode, 193, 27, 157, 1, // Opcode: ST1Fourv4s +/* 31234 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 31249 +/* 31239 */ MCD_OPC_CheckPredicate, 3, 152, 217, 0, // Skip to: 86948 +/* 31244 */ MCD_OPC_Decode, 187, 27, 157, 1, // Opcode: ST1Fourv2d +/* 31249 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 31264 +/* 31254 */ MCD_OPC_CheckPredicate, 3, 137, 217, 0, // Skip to: 86948 +/* 31259 */ MCD_OPC_Decode, 173, 28, 158, 1, // Opcode: ST3Threev16b +/* 31264 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 31279 +/* 31269 */ MCD_OPC_CheckPredicate, 3, 122, 217, 0, // Skip to: 86948 +/* 31274 */ MCD_OPC_Decode, 185, 28, 158, 1, // Opcode: ST3Threev8h +/* 31279 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 31294 +/* 31284 */ MCD_OPC_CheckPredicate, 3, 107, 217, 0, // Skip to: 86948 +/* 31289 */ MCD_OPC_Decode, 181, 28, 158, 1, // Opcode: ST3Threev4s +/* 31294 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 31309 +/* 31299 */ MCD_OPC_CheckPredicate, 3, 92, 217, 0, // Skip to: 86948 +/* 31304 */ MCD_OPC_Decode, 175, 28, 158, 1, // Opcode: ST3Threev2d +/* 31309 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 31324 +/* 31314 */ MCD_OPC_CheckPredicate, 3, 77, 217, 0, // Skip to: 86948 +/* 31319 */ MCD_OPC_Decode, 221, 27, 158, 1, // Opcode: ST1Threev16b +/* 31324 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 31339 +/* 31329 */ MCD_OPC_CheckPredicate, 3, 62, 217, 0, // Skip to: 86948 +/* 31334 */ MCD_OPC_Decode, 235, 27, 158, 1, // Opcode: ST1Threev8h +/* 31339 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 31354 +/* 31344 */ MCD_OPC_CheckPredicate, 3, 47, 217, 0, // Skip to: 86948 +/* 31349 */ MCD_OPC_Decode, 231, 27, 158, 1, // Opcode: ST1Threev4s +/* 31354 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 31369 +/* 31359 */ MCD_OPC_CheckPredicate, 3, 32, 217, 0, // Skip to: 86948 +/* 31364 */ MCD_OPC_Decode, 225, 27, 158, 1, // Opcode: ST1Threev2d +/* 31369 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 31384 +/* 31374 */ MCD_OPC_CheckPredicate, 3, 17, 217, 0, // Skip to: 86948 +/* 31379 */ MCD_OPC_Decode, 205, 27, 159, 1, // Opcode: ST1Onev16b +/* 31384 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 31399 +/* 31389 */ MCD_OPC_CheckPredicate, 3, 2, 217, 0, // Skip to: 86948 +/* 31394 */ MCD_OPC_Decode, 219, 27, 159, 1, // Opcode: ST1Onev8h +/* 31399 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 31414 +/* 31404 */ MCD_OPC_CheckPredicate, 3, 243, 216, 0, // Skip to: 86948 +/* 31409 */ MCD_OPC_Decode, 215, 27, 159, 1, // Opcode: ST1Onev4s +/* 31414 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31429 +/* 31419 */ MCD_OPC_CheckPredicate, 3, 228, 216, 0, // Skip to: 86948 +/* 31424 */ MCD_OPC_Decode, 209, 27, 159, 1, // Opcode: ST1Onev2d +/* 31429 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31444 +/* 31434 */ MCD_OPC_CheckPredicate, 3, 213, 216, 0, // Skip to: 86948 +/* 31439 */ MCD_OPC_Decode, 143, 28, 160, 1, // Opcode: ST2Twov16b +/* 31444 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31459 +/* 31449 */ MCD_OPC_CheckPredicate, 3, 198, 216, 0, // Skip to: 86948 +/* 31454 */ MCD_OPC_Decode, 155, 28, 160, 1, // Opcode: ST2Twov8h +/* 31459 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31474 +/* 31464 */ MCD_OPC_CheckPredicate, 3, 183, 216, 0, // Skip to: 86948 +/* 31469 */ MCD_OPC_Decode, 151, 28, 160, 1, // Opcode: ST2Twov4s +/* 31474 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 31489 +/* 31479 */ MCD_OPC_CheckPredicate, 3, 168, 216, 0, // Skip to: 86948 +/* 31484 */ MCD_OPC_Decode, 145, 28, 160, 1, // Opcode: ST2Twov2d +/* 31489 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31504 +/* 31494 */ MCD_OPC_CheckPredicate, 3, 153, 216, 0, // Skip to: 86948 +/* 31499 */ MCD_OPC_Decode, 237, 27, 160, 1, // Opcode: ST1Twov16b +/* 31504 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31519 +/* 31509 */ MCD_OPC_CheckPredicate, 3, 138, 216, 0, // Skip to: 86948 +/* 31514 */ MCD_OPC_Decode, 251, 27, 160, 1, // Opcode: ST1Twov8h +/* 31519 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31534 +/* 31524 */ MCD_OPC_CheckPredicate, 3, 123, 216, 0, // Skip to: 86948 +/* 31529 */ MCD_OPC_Decode, 247, 27, 160, 1, // Opcode: ST1Twov4s +/* 31534 */ MCD_OPC_FilterValue, 43, 113, 216, 0, // Skip to: 86948 +/* 31539 */ MCD_OPC_CheckPredicate, 3, 108, 216, 0, // Skip to: 86948 +/* 31544 */ MCD_OPC_Decode, 241, 27, 160, 1, // Opcode: ST1Twov2d +/* 31549 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 31559 +/* 31554 */ MCD_OPC_Decode, 245, 28, 150, 1, // Opcode: STNPDi +/* 31559 */ MCD_OPC_FilterValue, 5, 88, 216, 0, // Skip to: 86948 +/* 31564 */ MCD_OPC_Decode, 246, 28, 150, 1, // Opcode: STNPQi +/* 31569 */ MCD_OPC_FilterValue, 1, 76, 3, 0, // Skip to: 32418 +/* 31574 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 31577 */ MCD_OPC_FilterValue, 0, 122, 1, 0, // Skip to: 31960 +/* 31582 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 31585 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31600 +/* 31590 */ MCD_OPC_CheckPredicate, 3, 57, 216, 0, // Skip to: 86948 +/* 31595 */ MCD_OPC_Decode, 173, 16, 153, 1, // Opcode: LD4Fourv8b +/* 31600 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 31615 +/* 31605 */ MCD_OPC_CheckPredicate, 3, 42, 216, 0, // Skip to: 86948 +/* 31610 */ MCD_OPC_Decode, 169, 16, 153, 1, // Opcode: LD4Fourv4h +/* 31615 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 31630 +/* 31620 */ MCD_OPC_CheckPredicate, 3, 27, 216, 0, // Skip to: 86948 +/* 31625 */ MCD_OPC_Decode, 167, 16, 153, 1, // Opcode: LD4Fourv2s +/* 31630 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 31645 +/* 31635 */ MCD_OPC_CheckPredicate, 3, 12, 216, 0, // Skip to: 86948 +/* 31640 */ MCD_OPC_Decode, 201, 14, 153, 1, // Opcode: LD1Fourv8b +/* 31645 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 31660 +/* 31650 */ MCD_OPC_CheckPredicate, 3, 253, 215, 0, // Skip to: 86948 +/* 31655 */ MCD_OPC_Decode, 197, 14, 153, 1, // Opcode: LD1Fourv4h +/* 31660 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 31675 +/* 31665 */ MCD_OPC_CheckPredicate, 3, 238, 215, 0, // Skip to: 86948 +/* 31670 */ MCD_OPC_Decode, 195, 14, 153, 1, // Opcode: LD1Fourv2s +/* 31675 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 31690 +/* 31680 */ MCD_OPC_CheckPredicate, 3, 223, 215, 0, // Skip to: 86948 +/* 31685 */ MCD_OPC_Decode, 191, 14, 153, 1, // Opcode: LD1Fourv1d +/* 31690 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 31705 +/* 31695 */ MCD_OPC_CheckPredicate, 3, 208, 215, 0, // Skip to: 86948 +/* 31700 */ MCD_OPC_Decode, 145, 16, 154, 1, // Opcode: LD3Threev8b +/* 31705 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 31720 +/* 31710 */ MCD_OPC_CheckPredicate, 3, 193, 215, 0, // Skip to: 86948 +/* 31715 */ MCD_OPC_Decode, 141, 16, 154, 1, // Opcode: LD3Threev4h +/* 31720 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 31735 +/* 31725 */ MCD_OPC_CheckPredicate, 3, 178, 215, 0, // Skip to: 86948 +/* 31730 */ MCD_OPC_Decode, 139, 16, 154, 1, // Opcode: LD3Threev2s +/* 31735 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 31750 +/* 31740 */ MCD_OPC_CheckPredicate, 3, 163, 215, 0, // Skip to: 86948 +/* 31745 */ MCD_OPC_Decode, 163, 15, 154, 1, // Opcode: LD1Threev8b +/* 31750 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 31765 +/* 31755 */ MCD_OPC_CheckPredicate, 3, 148, 215, 0, // Skip to: 86948 +/* 31760 */ MCD_OPC_Decode, 159, 15, 154, 1, // Opcode: LD1Threev4h +/* 31765 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 31780 +/* 31770 */ MCD_OPC_CheckPredicate, 3, 133, 215, 0, // Skip to: 86948 +/* 31775 */ MCD_OPC_Decode, 157, 15, 154, 1, // Opcode: LD1Threev2s +/* 31780 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 31795 +/* 31785 */ MCD_OPC_CheckPredicate, 3, 118, 215, 0, // Skip to: 86948 +/* 31790 */ MCD_OPC_Decode, 153, 15, 154, 1, // Opcode: LD1Threev1d +/* 31795 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 31810 +/* 31800 */ MCD_OPC_CheckPredicate, 3, 103, 215, 0, // Skip to: 86948 +/* 31805 */ MCD_OPC_Decode, 223, 14, 155, 1, // Opcode: LD1Onev8b +/* 31810 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 31825 +/* 31815 */ MCD_OPC_CheckPredicate, 3, 88, 215, 0, // Skip to: 86948 +/* 31820 */ MCD_OPC_Decode, 219, 14, 155, 1, // Opcode: LD1Onev4h +/* 31825 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 31840 +/* 31830 */ MCD_OPC_CheckPredicate, 3, 73, 215, 0, // Skip to: 86948 +/* 31835 */ MCD_OPC_Decode, 217, 14, 155, 1, // Opcode: LD1Onev2s +/* 31840 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 31855 +/* 31845 */ MCD_OPC_CheckPredicate, 3, 58, 215, 0, // Skip to: 86948 +/* 31850 */ MCD_OPC_Decode, 213, 14, 155, 1, // Opcode: LD1Onev1d +/* 31855 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 31870 +/* 31860 */ MCD_OPC_CheckPredicate, 3, 43, 215, 0, // Skip to: 86948 +/* 31865 */ MCD_OPC_Decode, 227, 15, 156, 1, // Opcode: LD2Twov8b +/* 31870 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 31885 +/* 31875 */ MCD_OPC_CheckPredicate, 3, 28, 215, 0, // Skip to: 86948 +/* 31880 */ MCD_OPC_Decode, 223, 15, 156, 1, // Opcode: LD2Twov4h +/* 31885 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 31900 +/* 31890 */ MCD_OPC_CheckPredicate, 3, 13, 215, 0, // Skip to: 86948 +/* 31895 */ MCD_OPC_Decode, 221, 15, 156, 1, // Opcode: LD2Twov2s +/* 31900 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 31915 +/* 31905 */ MCD_OPC_CheckPredicate, 3, 254, 214, 0, // Skip to: 86948 +/* 31910 */ MCD_OPC_Decode, 179, 15, 156, 1, // Opcode: LD1Twov8b +/* 31915 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 31930 +/* 31920 */ MCD_OPC_CheckPredicate, 3, 239, 214, 0, // Skip to: 86948 +/* 31925 */ MCD_OPC_Decode, 175, 15, 156, 1, // Opcode: LD1Twov4h +/* 31930 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 31945 +/* 31935 */ MCD_OPC_CheckPredicate, 3, 224, 214, 0, // Skip to: 86948 +/* 31940 */ MCD_OPC_Decode, 173, 15, 156, 1, // Opcode: LD1Twov2s +/* 31945 */ MCD_OPC_FilterValue, 43, 214, 214, 0, // Skip to: 86948 +/* 31950 */ MCD_OPC_CheckPredicate, 3, 209, 214, 0, // Skip to: 86948 +/* 31955 */ MCD_OPC_Decode, 169, 15, 156, 1, // Opcode: LD1Twov1d +/* 31960 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 31970 +/* 31965 */ MCD_OPC_Decode, 186, 17, 150, 1, // Opcode: LDNPSi +/* 31970 */ MCD_OPC_FilterValue, 2, 167, 1, 0, // Skip to: 32398 +/* 31975 */ MCD_OPC_ExtractField, 10, 12, // Inst{21-10} ... +/* 31978 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 31993 +/* 31983 */ MCD_OPC_CheckPredicate, 3, 176, 214, 0, // Skip to: 86948 +/* 31988 */ MCD_OPC_Decode, 163, 16, 157, 1, // Opcode: LD4Fourv16b +/* 31993 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 32008 +/* 31998 */ MCD_OPC_CheckPredicate, 3, 161, 214, 0, // Skip to: 86948 +/* 32003 */ MCD_OPC_Decode, 175, 16, 157, 1, // Opcode: LD4Fourv8h +/* 32008 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 32023 +/* 32013 */ MCD_OPC_CheckPredicate, 3, 146, 214, 0, // Skip to: 86948 +/* 32018 */ MCD_OPC_Decode, 171, 16, 157, 1, // Opcode: LD4Fourv4s +/* 32023 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 32038 +/* 32028 */ MCD_OPC_CheckPredicate, 3, 131, 214, 0, // Skip to: 86948 +/* 32033 */ MCD_OPC_Decode, 165, 16, 157, 1, // Opcode: LD4Fourv2d +/* 32038 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 32053 +/* 32043 */ MCD_OPC_CheckPredicate, 3, 116, 214, 0, // Skip to: 86948 +/* 32048 */ MCD_OPC_Decode, 189, 14, 157, 1, // Opcode: LD1Fourv16b +/* 32053 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 32068 +/* 32058 */ MCD_OPC_CheckPredicate, 3, 101, 214, 0, // Skip to: 86948 +/* 32063 */ MCD_OPC_Decode, 203, 14, 157, 1, // Opcode: LD1Fourv8h +/* 32068 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 32083 +/* 32073 */ MCD_OPC_CheckPredicate, 3, 86, 214, 0, // Skip to: 86948 +/* 32078 */ MCD_OPC_Decode, 199, 14, 157, 1, // Opcode: LD1Fourv4s +/* 32083 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 32098 +/* 32088 */ MCD_OPC_CheckPredicate, 3, 71, 214, 0, // Skip to: 86948 +/* 32093 */ MCD_OPC_Decode, 193, 14, 157, 1, // Opcode: LD1Fourv2d +/* 32098 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 32113 +/* 32103 */ MCD_OPC_CheckPredicate, 3, 56, 214, 0, // Skip to: 86948 +/* 32108 */ MCD_OPC_Decode, 135, 16, 158, 1, // Opcode: LD3Threev16b +/* 32113 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 32128 +/* 32118 */ MCD_OPC_CheckPredicate, 3, 41, 214, 0, // Skip to: 86948 +/* 32123 */ MCD_OPC_Decode, 147, 16, 158, 1, // Opcode: LD3Threev8h +/* 32128 */ MCD_OPC_FilterValue, 18, 10, 0, 0, // Skip to: 32143 +/* 32133 */ MCD_OPC_CheckPredicate, 3, 26, 214, 0, // Skip to: 86948 +/* 32138 */ MCD_OPC_Decode, 143, 16, 158, 1, // Opcode: LD3Threev4s +/* 32143 */ MCD_OPC_FilterValue, 19, 10, 0, 0, // Skip to: 32158 +/* 32148 */ MCD_OPC_CheckPredicate, 3, 11, 214, 0, // Skip to: 86948 +/* 32153 */ MCD_OPC_Decode, 137, 16, 158, 1, // Opcode: LD3Threev2d +/* 32158 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 32173 +/* 32163 */ MCD_OPC_CheckPredicate, 3, 252, 213, 0, // Skip to: 86948 +/* 32168 */ MCD_OPC_Decode, 151, 15, 158, 1, // Opcode: LD1Threev16b +/* 32173 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 32188 +/* 32178 */ MCD_OPC_CheckPredicate, 3, 237, 213, 0, // Skip to: 86948 +/* 32183 */ MCD_OPC_Decode, 165, 15, 158, 1, // Opcode: LD1Threev8h +/* 32188 */ MCD_OPC_FilterValue, 26, 10, 0, 0, // Skip to: 32203 +/* 32193 */ MCD_OPC_CheckPredicate, 3, 222, 213, 0, // Skip to: 86948 +/* 32198 */ MCD_OPC_Decode, 161, 15, 158, 1, // Opcode: LD1Threev4s +/* 32203 */ MCD_OPC_FilterValue, 27, 10, 0, 0, // Skip to: 32218 +/* 32208 */ MCD_OPC_CheckPredicate, 3, 207, 213, 0, // Skip to: 86948 +/* 32213 */ MCD_OPC_Decode, 155, 15, 158, 1, // Opcode: LD1Threev2d +/* 32218 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 32233 +/* 32223 */ MCD_OPC_CheckPredicate, 3, 192, 213, 0, // Skip to: 86948 +/* 32228 */ MCD_OPC_Decode, 211, 14, 159, 1, // Opcode: LD1Onev16b +/* 32233 */ MCD_OPC_FilterValue, 29, 10, 0, 0, // Skip to: 32248 +/* 32238 */ MCD_OPC_CheckPredicate, 3, 177, 213, 0, // Skip to: 86948 +/* 32243 */ MCD_OPC_Decode, 225, 14, 159, 1, // Opcode: LD1Onev8h +/* 32248 */ MCD_OPC_FilterValue, 30, 10, 0, 0, // Skip to: 32263 +/* 32253 */ MCD_OPC_CheckPredicate, 3, 162, 213, 0, // Skip to: 86948 +/* 32258 */ MCD_OPC_Decode, 221, 14, 159, 1, // Opcode: LD1Onev4s +/* 32263 */ MCD_OPC_FilterValue, 31, 10, 0, 0, // Skip to: 32278 +/* 32268 */ MCD_OPC_CheckPredicate, 3, 147, 213, 0, // Skip to: 86948 +/* 32273 */ MCD_OPC_Decode, 215, 14, 159, 1, // Opcode: LD1Onev2d +/* 32278 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 32293 +/* 32283 */ MCD_OPC_CheckPredicate, 3, 132, 213, 0, // Skip to: 86948 +/* 32288 */ MCD_OPC_Decode, 217, 15, 160, 1, // Opcode: LD2Twov16b +/* 32293 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 32308 +/* 32298 */ MCD_OPC_CheckPredicate, 3, 117, 213, 0, // Skip to: 86948 +/* 32303 */ MCD_OPC_Decode, 229, 15, 160, 1, // Opcode: LD2Twov8h +/* 32308 */ MCD_OPC_FilterValue, 34, 10, 0, 0, // Skip to: 32323 +/* 32313 */ MCD_OPC_CheckPredicate, 3, 102, 213, 0, // Skip to: 86948 +/* 32318 */ MCD_OPC_Decode, 225, 15, 160, 1, // Opcode: LD2Twov4s +/* 32323 */ MCD_OPC_FilterValue, 35, 10, 0, 0, // Skip to: 32338 +/* 32328 */ MCD_OPC_CheckPredicate, 3, 87, 213, 0, // Skip to: 86948 +/* 32333 */ MCD_OPC_Decode, 219, 15, 160, 1, // Opcode: LD2Twov2d +/* 32338 */ MCD_OPC_FilterValue, 40, 10, 0, 0, // Skip to: 32353 +/* 32343 */ MCD_OPC_CheckPredicate, 3, 72, 213, 0, // Skip to: 86948 +/* 32348 */ MCD_OPC_Decode, 167, 15, 160, 1, // Opcode: LD1Twov16b +/* 32353 */ MCD_OPC_FilterValue, 41, 10, 0, 0, // Skip to: 32368 +/* 32358 */ MCD_OPC_CheckPredicate, 3, 57, 213, 0, // Skip to: 86948 +/* 32363 */ MCD_OPC_Decode, 181, 15, 160, 1, // Opcode: LD1Twov8h +/* 32368 */ MCD_OPC_FilterValue, 42, 10, 0, 0, // Skip to: 32383 +/* 32373 */ MCD_OPC_CheckPredicate, 3, 42, 213, 0, // Skip to: 86948 +/* 32378 */ MCD_OPC_Decode, 177, 15, 160, 1, // Opcode: LD1Twov4s +/* 32383 */ MCD_OPC_FilterValue, 43, 32, 213, 0, // Skip to: 86948 +/* 32388 */ MCD_OPC_CheckPredicate, 3, 27, 213, 0, // Skip to: 86948 +/* 32393 */ MCD_OPC_Decode, 171, 15, 160, 1, // Opcode: LD1Twov2d +/* 32398 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 32408 +/* 32403 */ MCD_OPC_Decode, 184, 17, 150, 1, // Opcode: LDNPDi +/* 32408 */ MCD_OPC_FilterValue, 5, 7, 213, 0, // Skip to: 86948 +/* 32413 */ MCD_OPC_Decode, 185, 17, 150, 1, // Opcode: LDNPQi +/* 32418 */ MCD_OPC_FilterValue, 2, 191, 4, 0, // Skip to: 33638 +/* 32423 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 32426 */ MCD_OPC_FilterValue, 0, 41, 2, 0, // Skip to: 32984 +/* 32431 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 32434 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 32456 +/* 32439 */ MCD_OPC_CheckPredicate, 3, 232, 212, 0, // Skip to: 86948 +/* 32444 */ MCD_OPC_CheckField, 21, 1, 0, 225, 212, 0, // Skip to: 86948 +/* 32451 */ MCD_OPC_Decode, 212, 28, 161, 1, // Opcode: ST4Fourv8b_POST +/* 32456 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 32478 +/* 32461 */ MCD_OPC_CheckPredicate, 3, 210, 212, 0, // Skip to: 86948 +/* 32466 */ MCD_OPC_CheckField, 21, 1, 0, 203, 212, 0, // Skip to: 86948 +/* 32473 */ MCD_OPC_Decode, 208, 28, 161, 1, // Opcode: ST4Fourv4h_POST +/* 32478 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 32500 +/* 32483 */ MCD_OPC_CheckPredicate, 3, 188, 212, 0, // Skip to: 86948 +/* 32488 */ MCD_OPC_CheckField, 21, 1, 0, 181, 212, 0, // Skip to: 86948 +/* 32495 */ MCD_OPC_Decode, 206, 28, 161, 1, // Opcode: ST4Fourv2s_POST +/* 32500 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 32522 +/* 32505 */ MCD_OPC_CheckPredicate, 3, 166, 212, 0, // Skip to: 86948 +/* 32510 */ MCD_OPC_CheckField, 21, 1, 0, 159, 212, 0, // Skip to: 86948 +/* 32517 */ MCD_OPC_Decode, 196, 27, 161, 1, // Opcode: ST1Fourv8b_POST +/* 32522 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 32544 +/* 32527 */ MCD_OPC_CheckPredicate, 3, 144, 212, 0, // Skip to: 86948 +/* 32532 */ MCD_OPC_CheckField, 21, 1, 0, 137, 212, 0, // Skip to: 86948 +/* 32539 */ MCD_OPC_Decode, 192, 27, 161, 1, // Opcode: ST1Fourv4h_POST +/* 32544 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 32566 +/* 32549 */ MCD_OPC_CheckPredicate, 3, 122, 212, 0, // Skip to: 86948 +/* 32554 */ MCD_OPC_CheckField, 21, 1, 0, 115, 212, 0, // Skip to: 86948 +/* 32561 */ MCD_OPC_Decode, 190, 27, 161, 1, // Opcode: ST1Fourv2s_POST +/* 32566 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 32588 +/* 32571 */ MCD_OPC_CheckPredicate, 3, 100, 212, 0, // Skip to: 86948 +/* 32576 */ MCD_OPC_CheckField, 21, 1, 0, 93, 212, 0, // Skip to: 86948 +/* 32583 */ MCD_OPC_Decode, 186, 27, 161, 1, // Opcode: ST1Fourv1d_POST +/* 32588 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 32610 +/* 32593 */ MCD_OPC_CheckPredicate, 3, 78, 212, 0, // Skip to: 86948 +/* 32598 */ MCD_OPC_CheckField, 21, 1, 0, 71, 212, 0, // Skip to: 86948 +/* 32605 */ MCD_OPC_Decode, 184, 28, 162, 1, // Opcode: ST3Threev8b_POST +/* 32610 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 32632 +/* 32615 */ MCD_OPC_CheckPredicate, 3, 56, 212, 0, // Skip to: 86948 +/* 32620 */ MCD_OPC_CheckField, 21, 1, 0, 49, 212, 0, // Skip to: 86948 +/* 32627 */ MCD_OPC_Decode, 180, 28, 162, 1, // Opcode: ST3Threev4h_POST +/* 32632 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 32654 +/* 32637 */ MCD_OPC_CheckPredicate, 3, 34, 212, 0, // Skip to: 86948 +/* 32642 */ MCD_OPC_CheckField, 21, 1, 0, 27, 212, 0, // Skip to: 86948 +/* 32649 */ MCD_OPC_Decode, 178, 28, 162, 1, // Opcode: ST3Threev2s_POST +/* 32654 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 32676 +/* 32659 */ MCD_OPC_CheckPredicate, 3, 12, 212, 0, // Skip to: 86948 +/* 32664 */ MCD_OPC_CheckField, 21, 1, 0, 5, 212, 0, // Skip to: 86948 +/* 32671 */ MCD_OPC_Decode, 234, 27, 162, 1, // Opcode: ST1Threev8b_POST +/* 32676 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 32698 +/* 32681 */ MCD_OPC_CheckPredicate, 3, 246, 211, 0, // Skip to: 86948 +/* 32686 */ MCD_OPC_CheckField, 21, 1, 0, 239, 211, 0, // Skip to: 86948 +/* 32693 */ MCD_OPC_Decode, 230, 27, 162, 1, // Opcode: ST1Threev4h_POST +/* 32698 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 32720 +/* 32703 */ MCD_OPC_CheckPredicate, 3, 224, 211, 0, // Skip to: 86948 +/* 32708 */ MCD_OPC_CheckField, 21, 1, 0, 217, 211, 0, // Skip to: 86948 +/* 32715 */ MCD_OPC_Decode, 228, 27, 162, 1, // Opcode: ST1Threev2s_POST +/* 32720 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 32742 +/* 32725 */ MCD_OPC_CheckPredicate, 3, 202, 211, 0, // Skip to: 86948 +/* 32730 */ MCD_OPC_CheckField, 21, 1, 0, 195, 211, 0, // Skip to: 86948 +/* 32737 */ MCD_OPC_Decode, 224, 27, 162, 1, // Opcode: ST1Threev1d_POST +/* 32742 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 32764 +/* 32747 */ MCD_OPC_CheckPredicate, 3, 180, 211, 0, // Skip to: 86948 +/* 32752 */ MCD_OPC_CheckField, 21, 1, 0, 173, 211, 0, // Skip to: 86948 +/* 32759 */ MCD_OPC_Decode, 218, 27, 163, 1, // Opcode: ST1Onev8b_POST +/* 32764 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 32786 +/* 32769 */ MCD_OPC_CheckPredicate, 3, 158, 211, 0, // Skip to: 86948 +/* 32774 */ MCD_OPC_CheckField, 21, 1, 0, 151, 211, 0, // Skip to: 86948 +/* 32781 */ MCD_OPC_Decode, 214, 27, 163, 1, // Opcode: ST1Onev4h_POST +/* 32786 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 32808 +/* 32791 */ MCD_OPC_CheckPredicate, 3, 136, 211, 0, // Skip to: 86948 +/* 32796 */ MCD_OPC_CheckField, 21, 1, 0, 129, 211, 0, // Skip to: 86948 +/* 32803 */ MCD_OPC_Decode, 212, 27, 163, 1, // Opcode: ST1Onev2s_POST +/* 32808 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 32830 +/* 32813 */ MCD_OPC_CheckPredicate, 3, 114, 211, 0, // Skip to: 86948 +/* 32818 */ MCD_OPC_CheckField, 21, 1, 0, 107, 211, 0, // Skip to: 86948 +/* 32825 */ MCD_OPC_Decode, 208, 27, 163, 1, // Opcode: ST1Onev1d_POST +/* 32830 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 32852 +/* 32835 */ MCD_OPC_CheckPredicate, 3, 92, 211, 0, // Skip to: 86948 +/* 32840 */ MCD_OPC_CheckField, 21, 1, 0, 85, 211, 0, // Skip to: 86948 +/* 32847 */ MCD_OPC_Decode, 154, 28, 164, 1, // Opcode: ST2Twov8b_POST +/* 32852 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 32874 +/* 32857 */ MCD_OPC_CheckPredicate, 3, 70, 211, 0, // Skip to: 86948 +/* 32862 */ MCD_OPC_CheckField, 21, 1, 0, 63, 211, 0, // Skip to: 86948 +/* 32869 */ MCD_OPC_Decode, 150, 28, 164, 1, // Opcode: ST2Twov4h_POST +/* 32874 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 32896 +/* 32879 */ MCD_OPC_CheckPredicate, 3, 48, 211, 0, // Skip to: 86948 +/* 32884 */ MCD_OPC_CheckField, 21, 1, 0, 41, 211, 0, // Skip to: 86948 +/* 32891 */ MCD_OPC_Decode, 148, 28, 164, 1, // Opcode: ST2Twov2s_POST +/* 32896 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 32918 +/* 32901 */ MCD_OPC_CheckPredicate, 3, 26, 211, 0, // Skip to: 86948 +/* 32906 */ MCD_OPC_CheckField, 21, 1, 0, 19, 211, 0, // Skip to: 86948 +/* 32913 */ MCD_OPC_Decode, 250, 27, 164, 1, // Opcode: ST1Twov8b_POST +/* 32918 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 32940 +/* 32923 */ MCD_OPC_CheckPredicate, 3, 4, 211, 0, // Skip to: 86948 +/* 32928 */ MCD_OPC_CheckField, 21, 1, 0, 253, 210, 0, // Skip to: 86948 +/* 32935 */ MCD_OPC_Decode, 246, 27, 164, 1, // Opcode: ST1Twov4h_POST +/* 32940 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 32962 +/* 32945 */ MCD_OPC_CheckPredicate, 3, 238, 210, 0, // Skip to: 86948 +/* 32950 */ MCD_OPC_CheckField, 21, 1, 0, 231, 210, 0, // Skip to: 86948 +/* 32957 */ MCD_OPC_Decode, 244, 27, 164, 1, // Opcode: ST1Twov2s_POST +/* 32962 */ MCD_OPC_FilterValue, 43, 221, 210, 0, // Skip to: 86948 +/* 32967 */ MCD_OPC_CheckPredicate, 3, 216, 210, 0, // Skip to: 86948 +/* 32972 */ MCD_OPC_CheckField, 21, 1, 0, 209, 210, 0, // Skip to: 86948 +/* 32979 */ MCD_OPC_Decode, 240, 27, 164, 1, // Opcode: ST1Twov1d_POST +/* 32984 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 32994 +/* 32989 */ MCD_OPC_Decode, 137, 29, 150, 1, // Opcode: STPSpost +/* 32994 */ MCD_OPC_FilterValue, 2, 107, 2, 0, // Skip to: 33618 +/* 32999 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 33002 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33024 +/* 33007 */ MCD_OPC_CheckPredicate, 3, 176, 210, 0, // Skip to: 86948 +/* 33012 */ MCD_OPC_CheckField, 21, 1, 0, 169, 210, 0, // Skip to: 86948 +/* 33019 */ MCD_OPC_Decode, 202, 28, 165, 1, // Opcode: ST4Fourv16b_POST +/* 33024 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 33046 +/* 33029 */ MCD_OPC_CheckPredicate, 3, 154, 210, 0, // Skip to: 86948 +/* 33034 */ MCD_OPC_CheckField, 21, 1, 0, 147, 210, 0, // Skip to: 86948 +/* 33041 */ MCD_OPC_Decode, 214, 28, 165, 1, // Opcode: ST4Fourv8h_POST +/* 33046 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 33068 +/* 33051 */ MCD_OPC_CheckPredicate, 3, 132, 210, 0, // Skip to: 86948 +/* 33056 */ MCD_OPC_CheckField, 21, 1, 0, 125, 210, 0, // Skip to: 86948 +/* 33063 */ MCD_OPC_Decode, 210, 28, 165, 1, // Opcode: ST4Fourv4s_POST +/* 33068 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 33090 +/* 33073 */ MCD_OPC_CheckPredicate, 3, 110, 210, 0, // Skip to: 86948 +/* 33078 */ MCD_OPC_CheckField, 21, 1, 0, 103, 210, 0, // Skip to: 86948 +/* 33085 */ MCD_OPC_Decode, 204, 28, 165, 1, // Opcode: ST4Fourv2d_POST +/* 33090 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 33112 +/* 33095 */ MCD_OPC_CheckPredicate, 3, 88, 210, 0, // Skip to: 86948 +/* 33100 */ MCD_OPC_CheckField, 21, 1, 0, 81, 210, 0, // Skip to: 86948 +/* 33107 */ MCD_OPC_Decode, 184, 27, 165, 1, // Opcode: ST1Fourv16b_POST +/* 33112 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 33134 +/* 33117 */ MCD_OPC_CheckPredicate, 3, 66, 210, 0, // Skip to: 86948 +/* 33122 */ MCD_OPC_CheckField, 21, 1, 0, 59, 210, 0, // Skip to: 86948 +/* 33129 */ MCD_OPC_Decode, 198, 27, 165, 1, // Opcode: ST1Fourv8h_POST +/* 33134 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 33156 +/* 33139 */ MCD_OPC_CheckPredicate, 3, 44, 210, 0, // Skip to: 86948 +/* 33144 */ MCD_OPC_CheckField, 21, 1, 0, 37, 210, 0, // Skip to: 86948 +/* 33151 */ MCD_OPC_Decode, 194, 27, 165, 1, // Opcode: ST1Fourv4s_POST +/* 33156 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 33178 +/* 33161 */ MCD_OPC_CheckPredicate, 3, 22, 210, 0, // Skip to: 86948 +/* 33166 */ MCD_OPC_CheckField, 21, 1, 0, 15, 210, 0, // Skip to: 86948 +/* 33173 */ MCD_OPC_Decode, 188, 27, 165, 1, // Opcode: ST1Fourv2d_POST +/* 33178 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 33200 +/* 33183 */ MCD_OPC_CheckPredicate, 3, 0, 210, 0, // Skip to: 86948 +/* 33188 */ MCD_OPC_CheckField, 21, 1, 0, 249, 209, 0, // Skip to: 86948 +/* 33195 */ MCD_OPC_Decode, 174, 28, 166, 1, // Opcode: ST3Threev16b_POST +/* 33200 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 33222 +/* 33205 */ MCD_OPC_CheckPredicate, 3, 234, 209, 0, // Skip to: 86948 +/* 33210 */ MCD_OPC_CheckField, 21, 1, 0, 227, 209, 0, // Skip to: 86948 +/* 33217 */ MCD_OPC_Decode, 186, 28, 166, 1, // Opcode: ST3Threev8h_POST +/* 33222 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 33244 +/* 33227 */ MCD_OPC_CheckPredicate, 3, 212, 209, 0, // Skip to: 86948 +/* 33232 */ MCD_OPC_CheckField, 21, 1, 0, 205, 209, 0, // Skip to: 86948 +/* 33239 */ MCD_OPC_Decode, 182, 28, 166, 1, // Opcode: ST3Threev4s_POST +/* 33244 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 33266 +/* 33249 */ MCD_OPC_CheckPredicate, 3, 190, 209, 0, // Skip to: 86948 +/* 33254 */ MCD_OPC_CheckField, 21, 1, 0, 183, 209, 0, // Skip to: 86948 +/* 33261 */ MCD_OPC_Decode, 176, 28, 166, 1, // Opcode: ST3Threev2d_POST +/* 33266 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 33288 +/* 33271 */ MCD_OPC_CheckPredicate, 3, 168, 209, 0, // Skip to: 86948 +/* 33276 */ MCD_OPC_CheckField, 21, 1, 0, 161, 209, 0, // Skip to: 86948 +/* 33283 */ MCD_OPC_Decode, 222, 27, 166, 1, // Opcode: ST1Threev16b_POST +/* 33288 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 33310 +/* 33293 */ MCD_OPC_CheckPredicate, 3, 146, 209, 0, // Skip to: 86948 +/* 33298 */ MCD_OPC_CheckField, 21, 1, 0, 139, 209, 0, // Skip to: 86948 +/* 33305 */ MCD_OPC_Decode, 236, 27, 166, 1, // Opcode: ST1Threev8h_POST +/* 33310 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 33332 +/* 33315 */ MCD_OPC_CheckPredicate, 3, 124, 209, 0, // Skip to: 86948 +/* 33320 */ MCD_OPC_CheckField, 21, 1, 0, 117, 209, 0, // Skip to: 86948 +/* 33327 */ MCD_OPC_Decode, 232, 27, 166, 1, // Opcode: ST1Threev4s_POST +/* 33332 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 33354 +/* 33337 */ MCD_OPC_CheckPredicate, 3, 102, 209, 0, // Skip to: 86948 +/* 33342 */ MCD_OPC_CheckField, 21, 1, 0, 95, 209, 0, // Skip to: 86948 +/* 33349 */ MCD_OPC_Decode, 226, 27, 166, 1, // Opcode: ST1Threev2d_POST +/* 33354 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 33376 +/* 33359 */ MCD_OPC_CheckPredicate, 3, 80, 209, 0, // Skip to: 86948 +/* 33364 */ MCD_OPC_CheckField, 21, 1, 0, 73, 209, 0, // Skip to: 86948 +/* 33371 */ MCD_OPC_Decode, 206, 27, 167, 1, // Opcode: ST1Onev16b_POST +/* 33376 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 33398 +/* 33381 */ MCD_OPC_CheckPredicate, 3, 58, 209, 0, // Skip to: 86948 +/* 33386 */ MCD_OPC_CheckField, 21, 1, 0, 51, 209, 0, // Skip to: 86948 +/* 33393 */ MCD_OPC_Decode, 220, 27, 167, 1, // Opcode: ST1Onev8h_POST +/* 33398 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 33420 +/* 33403 */ MCD_OPC_CheckPredicate, 3, 36, 209, 0, // Skip to: 86948 +/* 33408 */ MCD_OPC_CheckField, 21, 1, 0, 29, 209, 0, // Skip to: 86948 +/* 33415 */ MCD_OPC_Decode, 216, 27, 167, 1, // Opcode: ST1Onev4s_POST +/* 33420 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 33442 +/* 33425 */ MCD_OPC_CheckPredicate, 3, 14, 209, 0, // Skip to: 86948 +/* 33430 */ MCD_OPC_CheckField, 21, 1, 0, 7, 209, 0, // Skip to: 86948 +/* 33437 */ MCD_OPC_Decode, 210, 27, 167, 1, // Opcode: ST1Onev2d_POST +/* 33442 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 33464 +/* 33447 */ MCD_OPC_CheckPredicate, 3, 248, 208, 0, // Skip to: 86948 +/* 33452 */ MCD_OPC_CheckField, 21, 1, 0, 241, 208, 0, // Skip to: 86948 +/* 33459 */ MCD_OPC_Decode, 144, 28, 168, 1, // Opcode: ST2Twov16b_POST +/* 33464 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 33486 +/* 33469 */ MCD_OPC_CheckPredicate, 3, 226, 208, 0, // Skip to: 86948 +/* 33474 */ MCD_OPC_CheckField, 21, 1, 0, 219, 208, 0, // Skip to: 86948 +/* 33481 */ MCD_OPC_Decode, 156, 28, 168, 1, // Opcode: ST2Twov8h_POST +/* 33486 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 33508 +/* 33491 */ MCD_OPC_CheckPredicate, 3, 204, 208, 0, // Skip to: 86948 +/* 33496 */ MCD_OPC_CheckField, 21, 1, 0, 197, 208, 0, // Skip to: 86948 +/* 33503 */ MCD_OPC_Decode, 152, 28, 168, 1, // Opcode: ST2Twov4s_POST +/* 33508 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 33530 +/* 33513 */ MCD_OPC_CheckPredicate, 3, 182, 208, 0, // Skip to: 86948 +/* 33518 */ MCD_OPC_CheckField, 21, 1, 0, 175, 208, 0, // Skip to: 86948 +/* 33525 */ MCD_OPC_Decode, 146, 28, 168, 1, // Opcode: ST2Twov2d_POST +/* 33530 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 33552 +/* 33535 */ MCD_OPC_CheckPredicate, 3, 160, 208, 0, // Skip to: 86948 +/* 33540 */ MCD_OPC_CheckField, 21, 1, 0, 153, 208, 0, // Skip to: 86948 +/* 33547 */ MCD_OPC_Decode, 238, 27, 168, 1, // Opcode: ST1Twov16b_POST +/* 33552 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 33574 +/* 33557 */ MCD_OPC_CheckPredicate, 3, 138, 208, 0, // Skip to: 86948 +/* 33562 */ MCD_OPC_CheckField, 21, 1, 0, 131, 208, 0, // Skip to: 86948 +/* 33569 */ MCD_OPC_Decode, 252, 27, 168, 1, // Opcode: ST1Twov8h_POST +/* 33574 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 33596 +/* 33579 */ MCD_OPC_CheckPredicate, 3, 116, 208, 0, // Skip to: 86948 +/* 33584 */ MCD_OPC_CheckField, 21, 1, 0, 109, 208, 0, // Skip to: 86948 +/* 33591 */ MCD_OPC_Decode, 248, 27, 168, 1, // Opcode: ST1Twov4s_POST +/* 33596 */ MCD_OPC_FilterValue, 43, 99, 208, 0, // Skip to: 86948 +/* 33601 */ MCD_OPC_CheckPredicate, 3, 94, 208, 0, // Skip to: 86948 +/* 33606 */ MCD_OPC_CheckField, 21, 1, 0, 87, 208, 0, // Skip to: 86948 +/* 33613 */ MCD_OPC_Decode, 242, 27, 168, 1, // Opcode: ST1Twov2d_POST +/* 33618 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 33628 +/* 33623 */ MCD_OPC_Decode, 131, 29, 150, 1, // Opcode: STPDpost +/* 33628 */ MCD_OPC_FilterValue, 5, 67, 208, 0, // Skip to: 86948 +/* 33633 */ MCD_OPC_Decode, 134, 29, 150, 1, // Opcode: STPQpost +/* 33638 */ MCD_OPC_FilterValue, 3, 191, 4, 0, // Skip to: 34858 +/* 33643 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 33646 */ MCD_OPC_FilterValue, 0, 41, 2, 0, // Skip to: 34204 +/* 33651 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 33654 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 33676 +/* 33659 */ MCD_OPC_CheckPredicate, 3, 36, 208, 0, // Skip to: 86948 +/* 33664 */ MCD_OPC_CheckField, 21, 1, 0, 29, 208, 0, // Skip to: 86948 +/* 33671 */ MCD_OPC_Decode, 174, 16, 161, 1, // Opcode: LD4Fourv8b_POST +/* 33676 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 33698 +/* 33681 */ MCD_OPC_CheckPredicate, 3, 14, 208, 0, // Skip to: 86948 +/* 33686 */ MCD_OPC_CheckField, 21, 1, 0, 7, 208, 0, // Skip to: 86948 +/* 33693 */ MCD_OPC_Decode, 170, 16, 161, 1, // Opcode: LD4Fourv4h_POST +/* 33698 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 33720 +/* 33703 */ MCD_OPC_CheckPredicate, 3, 248, 207, 0, // Skip to: 86948 +/* 33708 */ MCD_OPC_CheckField, 21, 1, 0, 241, 207, 0, // Skip to: 86948 +/* 33715 */ MCD_OPC_Decode, 168, 16, 161, 1, // Opcode: LD4Fourv2s_POST +/* 33720 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 33742 +/* 33725 */ MCD_OPC_CheckPredicate, 3, 226, 207, 0, // Skip to: 86948 +/* 33730 */ MCD_OPC_CheckField, 21, 1, 0, 219, 207, 0, // Skip to: 86948 +/* 33737 */ MCD_OPC_Decode, 202, 14, 161, 1, // Opcode: LD1Fourv8b_POST +/* 33742 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 33764 +/* 33747 */ MCD_OPC_CheckPredicate, 3, 204, 207, 0, // Skip to: 86948 +/* 33752 */ MCD_OPC_CheckField, 21, 1, 0, 197, 207, 0, // Skip to: 86948 +/* 33759 */ MCD_OPC_Decode, 198, 14, 161, 1, // Opcode: LD1Fourv4h_POST +/* 33764 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 33786 +/* 33769 */ MCD_OPC_CheckPredicate, 3, 182, 207, 0, // Skip to: 86948 +/* 33774 */ MCD_OPC_CheckField, 21, 1, 0, 175, 207, 0, // Skip to: 86948 +/* 33781 */ MCD_OPC_Decode, 196, 14, 161, 1, // Opcode: LD1Fourv2s_POST +/* 33786 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 33808 +/* 33791 */ MCD_OPC_CheckPredicate, 3, 160, 207, 0, // Skip to: 86948 +/* 33796 */ MCD_OPC_CheckField, 21, 1, 0, 153, 207, 0, // Skip to: 86948 +/* 33803 */ MCD_OPC_Decode, 192, 14, 161, 1, // Opcode: LD1Fourv1d_POST +/* 33808 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 33830 +/* 33813 */ MCD_OPC_CheckPredicate, 3, 138, 207, 0, // Skip to: 86948 +/* 33818 */ MCD_OPC_CheckField, 21, 1, 0, 131, 207, 0, // Skip to: 86948 +/* 33825 */ MCD_OPC_Decode, 146, 16, 162, 1, // Opcode: LD3Threev8b_POST +/* 33830 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 33852 +/* 33835 */ MCD_OPC_CheckPredicate, 3, 116, 207, 0, // Skip to: 86948 +/* 33840 */ MCD_OPC_CheckField, 21, 1, 0, 109, 207, 0, // Skip to: 86948 +/* 33847 */ MCD_OPC_Decode, 142, 16, 162, 1, // Opcode: LD3Threev4h_POST +/* 33852 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 33874 +/* 33857 */ MCD_OPC_CheckPredicate, 3, 94, 207, 0, // Skip to: 86948 +/* 33862 */ MCD_OPC_CheckField, 21, 1, 0, 87, 207, 0, // Skip to: 86948 +/* 33869 */ MCD_OPC_Decode, 140, 16, 162, 1, // Opcode: LD3Threev2s_POST +/* 33874 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 33896 +/* 33879 */ MCD_OPC_CheckPredicate, 3, 72, 207, 0, // Skip to: 86948 +/* 33884 */ MCD_OPC_CheckField, 21, 1, 0, 65, 207, 0, // Skip to: 86948 +/* 33891 */ MCD_OPC_Decode, 164, 15, 162, 1, // Opcode: LD1Threev8b_POST +/* 33896 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 33918 +/* 33901 */ MCD_OPC_CheckPredicate, 3, 50, 207, 0, // Skip to: 86948 +/* 33906 */ MCD_OPC_CheckField, 21, 1, 0, 43, 207, 0, // Skip to: 86948 +/* 33913 */ MCD_OPC_Decode, 160, 15, 162, 1, // Opcode: LD1Threev4h_POST +/* 33918 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 33940 +/* 33923 */ MCD_OPC_CheckPredicate, 3, 28, 207, 0, // Skip to: 86948 +/* 33928 */ MCD_OPC_CheckField, 21, 1, 0, 21, 207, 0, // Skip to: 86948 +/* 33935 */ MCD_OPC_Decode, 158, 15, 162, 1, // Opcode: LD1Threev2s_POST +/* 33940 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 33962 +/* 33945 */ MCD_OPC_CheckPredicate, 3, 6, 207, 0, // Skip to: 86948 +/* 33950 */ MCD_OPC_CheckField, 21, 1, 0, 255, 206, 0, // Skip to: 86948 +/* 33957 */ MCD_OPC_Decode, 154, 15, 162, 1, // Opcode: LD1Threev1d_POST +/* 33962 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 33984 +/* 33967 */ MCD_OPC_CheckPredicate, 3, 240, 206, 0, // Skip to: 86948 +/* 33972 */ MCD_OPC_CheckField, 21, 1, 0, 233, 206, 0, // Skip to: 86948 +/* 33979 */ MCD_OPC_Decode, 224, 14, 163, 1, // Opcode: LD1Onev8b_POST +/* 33984 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 34006 +/* 33989 */ MCD_OPC_CheckPredicate, 3, 218, 206, 0, // Skip to: 86948 +/* 33994 */ MCD_OPC_CheckField, 21, 1, 0, 211, 206, 0, // Skip to: 86948 +/* 34001 */ MCD_OPC_Decode, 220, 14, 163, 1, // Opcode: LD1Onev4h_POST +/* 34006 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 34028 +/* 34011 */ MCD_OPC_CheckPredicate, 3, 196, 206, 0, // Skip to: 86948 +/* 34016 */ MCD_OPC_CheckField, 21, 1, 0, 189, 206, 0, // Skip to: 86948 +/* 34023 */ MCD_OPC_Decode, 218, 14, 163, 1, // Opcode: LD1Onev2s_POST +/* 34028 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 34050 +/* 34033 */ MCD_OPC_CheckPredicate, 3, 174, 206, 0, // Skip to: 86948 +/* 34038 */ MCD_OPC_CheckField, 21, 1, 0, 167, 206, 0, // Skip to: 86948 +/* 34045 */ MCD_OPC_Decode, 214, 14, 163, 1, // Opcode: LD1Onev1d_POST +/* 34050 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 34072 +/* 34055 */ MCD_OPC_CheckPredicate, 3, 152, 206, 0, // Skip to: 86948 +/* 34060 */ MCD_OPC_CheckField, 21, 1, 0, 145, 206, 0, // Skip to: 86948 +/* 34067 */ MCD_OPC_Decode, 228, 15, 164, 1, // Opcode: LD2Twov8b_POST +/* 34072 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 34094 +/* 34077 */ MCD_OPC_CheckPredicate, 3, 130, 206, 0, // Skip to: 86948 +/* 34082 */ MCD_OPC_CheckField, 21, 1, 0, 123, 206, 0, // Skip to: 86948 +/* 34089 */ MCD_OPC_Decode, 224, 15, 164, 1, // Opcode: LD2Twov4h_POST +/* 34094 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 34116 +/* 34099 */ MCD_OPC_CheckPredicate, 3, 108, 206, 0, // Skip to: 86948 +/* 34104 */ MCD_OPC_CheckField, 21, 1, 0, 101, 206, 0, // Skip to: 86948 +/* 34111 */ MCD_OPC_Decode, 222, 15, 164, 1, // Opcode: LD2Twov2s_POST +/* 34116 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 34138 +/* 34121 */ MCD_OPC_CheckPredicate, 3, 86, 206, 0, // Skip to: 86948 +/* 34126 */ MCD_OPC_CheckField, 21, 1, 0, 79, 206, 0, // Skip to: 86948 +/* 34133 */ MCD_OPC_Decode, 180, 15, 164, 1, // Opcode: LD1Twov8b_POST +/* 34138 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 34160 +/* 34143 */ MCD_OPC_CheckPredicate, 3, 64, 206, 0, // Skip to: 86948 +/* 34148 */ MCD_OPC_CheckField, 21, 1, 0, 57, 206, 0, // Skip to: 86948 +/* 34155 */ MCD_OPC_Decode, 176, 15, 164, 1, // Opcode: LD1Twov4h_POST +/* 34160 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 34182 +/* 34165 */ MCD_OPC_CheckPredicate, 3, 42, 206, 0, // Skip to: 86948 +/* 34170 */ MCD_OPC_CheckField, 21, 1, 0, 35, 206, 0, // Skip to: 86948 +/* 34177 */ MCD_OPC_Decode, 174, 15, 164, 1, // Opcode: LD1Twov2s_POST +/* 34182 */ MCD_OPC_FilterValue, 43, 25, 206, 0, // Skip to: 86948 +/* 34187 */ MCD_OPC_CheckPredicate, 3, 20, 206, 0, // Skip to: 86948 +/* 34192 */ MCD_OPC_CheckField, 21, 1, 0, 13, 206, 0, // Skip to: 86948 +/* 34199 */ MCD_OPC_Decode, 170, 15, 164, 1, // Opcode: LD1Twov1d_POST +/* 34204 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 34214 +/* 34209 */ MCD_OPC_Decode, 207, 17, 150, 1, // Opcode: LDPSpost +/* 34214 */ MCD_OPC_FilterValue, 2, 107, 2, 0, // Skip to: 34838 +/* 34219 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 34222 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 34244 +/* 34227 */ MCD_OPC_CheckPredicate, 3, 236, 205, 0, // Skip to: 86948 +/* 34232 */ MCD_OPC_CheckField, 21, 1, 0, 229, 205, 0, // Skip to: 86948 +/* 34239 */ MCD_OPC_Decode, 164, 16, 165, 1, // Opcode: LD4Fourv16b_POST +/* 34244 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 34266 +/* 34249 */ MCD_OPC_CheckPredicate, 3, 214, 205, 0, // Skip to: 86948 +/* 34254 */ MCD_OPC_CheckField, 21, 1, 0, 207, 205, 0, // Skip to: 86948 +/* 34261 */ MCD_OPC_Decode, 176, 16, 165, 1, // Opcode: LD4Fourv8h_POST +/* 34266 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 34288 +/* 34271 */ MCD_OPC_CheckPredicate, 3, 192, 205, 0, // Skip to: 86948 +/* 34276 */ MCD_OPC_CheckField, 21, 1, 0, 185, 205, 0, // Skip to: 86948 +/* 34283 */ MCD_OPC_Decode, 172, 16, 165, 1, // Opcode: LD4Fourv4s_POST +/* 34288 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 34310 +/* 34293 */ MCD_OPC_CheckPredicate, 3, 170, 205, 0, // Skip to: 86948 +/* 34298 */ MCD_OPC_CheckField, 21, 1, 0, 163, 205, 0, // Skip to: 86948 +/* 34305 */ MCD_OPC_Decode, 166, 16, 165, 1, // Opcode: LD4Fourv2d_POST +/* 34310 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 34332 +/* 34315 */ MCD_OPC_CheckPredicate, 3, 148, 205, 0, // Skip to: 86948 +/* 34320 */ MCD_OPC_CheckField, 21, 1, 0, 141, 205, 0, // Skip to: 86948 +/* 34327 */ MCD_OPC_Decode, 190, 14, 165, 1, // Opcode: LD1Fourv16b_POST +/* 34332 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 34354 +/* 34337 */ MCD_OPC_CheckPredicate, 3, 126, 205, 0, // Skip to: 86948 +/* 34342 */ MCD_OPC_CheckField, 21, 1, 0, 119, 205, 0, // Skip to: 86948 +/* 34349 */ MCD_OPC_Decode, 204, 14, 165, 1, // Opcode: LD1Fourv8h_POST +/* 34354 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 34376 +/* 34359 */ MCD_OPC_CheckPredicate, 3, 104, 205, 0, // Skip to: 86948 +/* 34364 */ MCD_OPC_CheckField, 21, 1, 0, 97, 205, 0, // Skip to: 86948 +/* 34371 */ MCD_OPC_Decode, 200, 14, 165, 1, // Opcode: LD1Fourv4s_POST +/* 34376 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 34398 +/* 34381 */ MCD_OPC_CheckPredicate, 3, 82, 205, 0, // Skip to: 86948 +/* 34386 */ MCD_OPC_CheckField, 21, 1, 0, 75, 205, 0, // Skip to: 86948 +/* 34393 */ MCD_OPC_Decode, 194, 14, 165, 1, // Opcode: LD1Fourv2d_POST +/* 34398 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 34420 +/* 34403 */ MCD_OPC_CheckPredicate, 3, 60, 205, 0, // Skip to: 86948 +/* 34408 */ MCD_OPC_CheckField, 21, 1, 0, 53, 205, 0, // Skip to: 86948 +/* 34415 */ MCD_OPC_Decode, 136, 16, 166, 1, // Opcode: LD3Threev16b_POST +/* 34420 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 34442 +/* 34425 */ MCD_OPC_CheckPredicate, 3, 38, 205, 0, // Skip to: 86948 +/* 34430 */ MCD_OPC_CheckField, 21, 1, 0, 31, 205, 0, // Skip to: 86948 +/* 34437 */ MCD_OPC_Decode, 148, 16, 166, 1, // Opcode: LD3Threev8h_POST +/* 34442 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 34464 +/* 34447 */ MCD_OPC_CheckPredicate, 3, 16, 205, 0, // Skip to: 86948 +/* 34452 */ MCD_OPC_CheckField, 21, 1, 0, 9, 205, 0, // Skip to: 86948 +/* 34459 */ MCD_OPC_Decode, 144, 16, 166, 1, // Opcode: LD3Threev4s_POST +/* 34464 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 34486 +/* 34469 */ MCD_OPC_CheckPredicate, 3, 250, 204, 0, // Skip to: 86948 +/* 34474 */ MCD_OPC_CheckField, 21, 1, 0, 243, 204, 0, // Skip to: 86948 +/* 34481 */ MCD_OPC_Decode, 138, 16, 166, 1, // Opcode: LD3Threev2d_POST +/* 34486 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 34508 +/* 34491 */ MCD_OPC_CheckPredicate, 3, 228, 204, 0, // Skip to: 86948 +/* 34496 */ MCD_OPC_CheckField, 21, 1, 0, 221, 204, 0, // Skip to: 86948 +/* 34503 */ MCD_OPC_Decode, 152, 15, 166, 1, // Opcode: LD1Threev16b_POST +/* 34508 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 34530 +/* 34513 */ MCD_OPC_CheckPredicate, 3, 206, 204, 0, // Skip to: 86948 +/* 34518 */ MCD_OPC_CheckField, 21, 1, 0, 199, 204, 0, // Skip to: 86948 +/* 34525 */ MCD_OPC_Decode, 166, 15, 166, 1, // Opcode: LD1Threev8h_POST +/* 34530 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 34552 +/* 34535 */ MCD_OPC_CheckPredicate, 3, 184, 204, 0, // Skip to: 86948 +/* 34540 */ MCD_OPC_CheckField, 21, 1, 0, 177, 204, 0, // Skip to: 86948 +/* 34547 */ MCD_OPC_Decode, 162, 15, 166, 1, // Opcode: LD1Threev4s_POST +/* 34552 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 34574 +/* 34557 */ MCD_OPC_CheckPredicate, 3, 162, 204, 0, // Skip to: 86948 +/* 34562 */ MCD_OPC_CheckField, 21, 1, 0, 155, 204, 0, // Skip to: 86948 +/* 34569 */ MCD_OPC_Decode, 156, 15, 166, 1, // Opcode: LD1Threev2d_POST +/* 34574 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 34596 +/* 34579 */ MCD_OPC_CheckPredicate, 3, 140, 204, 0, // Skip to: 86948 +/* 34584 */ MCD_OPC_CheckField, 21, 1, 0, 133, 204, 0, // Skip to: 86948 +/* 34591 */ MCD_OPC_Decode, 212, 14, 167, 1, // Opcode: LD1Onev16b_POST +/* 34596 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 34618 +/* 34601 */ MCD_OPC_CheckPredicate, 3, 118, 204, 0, // Skip to: 86948 +/* 34606 */ MCD_OPC_CheckField, 21, 1, 0, 111, 204, 0, // Skip to: 86948 +/* 34613 */ MCD_OPC_Decode, 226, 14, 167, 1, // Opcode: LD1Onev8h_POST +/* 34618 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 34640 +/* 34623 */ MCD_OPC_CheckPredicate, 3, 96, 204, 0, // Skip to: 86948 +/* 34628 */ MCD_OPC_CheckField, 21, 1, 0, 89, 204, 0, // Skip to: 86948 +/* 34635 */ MCD_OPC_Decode, 222, 14, 167, 1, // Opcode: LD1Onev4s_POST +/* 34640 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 34662 +/* 34645 */ MCD_OPC_CheckPredicate, 3, 74, 204, 0, // Skip to: 86948 +/* 34650 */ MCD_OPC_CheckField, 21, 1, 0, 67, 204, 0, // Skip to: 86948 +/* 34657 */ MCD_OPC_Decode, 216, 14, 167, 1, // Opcode: LD1Onev2d_POST +/* 34662 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 34684 +/* 34667 */ MCD_OPC_CheckPredicate, 3, 52, 204, 0, // Skip to: 86948 +/* 34672 */ MCD_OPC_CheckField, 21, 1, 0, 45, 204, 0, // Skip to: 86948 +/* 34679 */ MCD_OPC_Decode, 218, 15, 168, 1, // Opcode: LD2Twov16b_POST +/* 34684 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 34706 +/* 34689 */ MCD_OPC_CheckPredicate, 3, 30, 204, 0, // Skip to: 86948 +/* 34694 */ MCD_OPC_CheckField, 21, 1, 0, 23, 204, 0, // Skip to: 86948 +/* 34701 */ MCD_OPC_Decode, 230, 15, 168, 1, // Opcode: LD2Twov8h_POST +/* 34706 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 34728 +/* 34711 */ MCD_OPC_CheckPredicate, 3, 8, 204, 0, // Skip to: 86948 +/* 34716 */ MCD_OPC_CheckField, 21, 1, 0, 1, 204, 0, // Skip to: 86948 +/* 34723 */ MCD_OPC_Decode, 226, 15, 168, 1, // Opcode: LD2Twov4s_POST +/* 34728 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 34750 +/* 34733 */ MCD_OPC_CheckPredicate, 3, 242, 203, 0, // Skip to: 86948 +/* 34738 */ MCD_OPC_CheckField, 21, 1, 0, 235, 203, 0, // Skip to: 86948 +/* 34745 */ MCD_OPC_Decode, 220, 15, 168, 1, // Opcode: LD2Twov2d_POST +/* 34750 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 34772 +/* 34755 */ MCD_OPC_CheckPredicate, 3, 220, 203, 0, // Skip to: 86948 +/* 34760 */ MCD_OPC_CheckField, 21, 1, 0, 213, 203, 0, // Skip to: 86948 +/* 34767 */ MCD_OPC_Decode, 168, 15, 168, 1, // Opcode: LD1Twov16b_POST +/* 34772 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 34794 +/* 34777 */ MCD_OPC_CheckPredicate, 3, 198, 203, 0, // Skip to: 86948 +/* 34782 */ MCD_OPC_CheckField, 21, 1, 0, 191, 203, 0, // Skip to: 86948 +/* 34789 */ MCD_OPC_Decode, 182, 15, 168, 1, // Opcode: LD1Twov8h_POST +/* 34794 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 34816 +/* 34799 */ MCD_OPC_CheckPredicate, 3, 176, 203, 0, // Skip to: 86948 +/* 34804 */ MCD_OPC_CheckField, 21, 1, 0, 169, 203, 0, // Skip to: 86948 +/* 34811 */ MCD_OPC_Decode, 178, 15, 168, 1, // Opcode: LD1Twov4s_POST +/* 34816 */ MCD_OPC_FilterValue, 43, 159, 203, 0, // Skip to: 86948 +/* 34821 */ MCD_OPC_CheckPredicate, 3, 154, 203, 0, // Skip to: 86948 +/* 34826 */ MCD_OPC_CheckField, 21, 1, 0, 147, 203, 0, // Skip to: 86948 +/* 34833 */ MCD_OPC_Decode, 172, 15, 168, 1, // Opcode: LD1Twov2d_POST +/* 34838 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 34848 +/* 34843 */ MCD_OPC_Decode, 198, 17, 150, 1, // Opcode: LDPDpost +/* 34848 */ MCD_OPC_FilterValue, 5, 127, 203, 0, // Skip to: 86948 +/* 34853 */ MCD_OPC_Decode, 201, 17, 150, 1, // Opcode: LDPQpost +/* 34858 */ MCD_OPC_FilterValue, 4, 239, 1, 0, // Skip to: 35358 +/* 34863 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 34866 */ MCD_OPC_FilterValue, 0, 193, 1, 0, // Skip to: 35320 +/* 34871 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... +/* 34874 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 34896 +/* 34879 */ MCD_OPC_CheckPredicate, 3, 96, 203, 0, // Skip to: 86948 +/* 34884 */ MCD_OPC_CheckField, 31, 1, 0, 89, 203, 0, // Skip to: 86948 +/* 34891 */ MCD_OPC_Decode, 135, 28, 169, 1, // Opcode: ST1i8 +/* 34896 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 34918 +/* 34901 */ MCD_OPC_CheckPredicate, 3, 74, 203, 0, // Skip to: 86948 +/* 34906 */ MCD_OPC_CheckField, 31, 1, 0, 67, 203, 0, // Skip to: 86948 +/* 34913 */ MCD_OPC_Decode, 195, 28, 170, 1, // Opcode: ST3i8 +/* 34918 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 34947 +/* 34923 */ MCD_OPC_CheckPredicate, 3, 52, 203, 0, // Skip to: 86948 +/* 34928 */ MCD_OPC_CheckField, 31, 1, 0, 45, 203, 0, // Skip to: 86948 +/* 34935 */ MCD_OPC_CheckField, 10, 1, 0, 38, 203, 0, // Skip to: 86948 +/* 34942 */ MCD_OPC_Decode, 129, 28, 171, 1, // Opcode: ST1i16 +/* 34947 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 34976 +/* 34952 */ MCD_OPC_CheckPredicate, 3, 23, 203, 0, // Skip to: 86948 +/* 34957 */ MCD_OPC_CheckField, 31, 1, 0, 16, 203, 0, // Skip to: 86948 +/* 34964 */ MCD_OPC_CheckField, 10, 1, 0, 9, 203, 0, // Skip to: 86948 +/* 34971 */ MCD_OPC_Decode, 189, 28, 172, 1, // Opcode: ST3i16 +/* 34976 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 35035 +/* 34981 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 34984 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35006 +/* 34989 */ MCD_OPC_CheckPredicate, 3, 242, 202, 0, // Skip to: 86948 +/* 34994 */ MCD_OPC_CheckField, 31, 1, 0, 235, 202, 0, // Skip to: 86948 +/* 35001 */ MCD_OPC_Decode, 131, 28, 173, 1, // Opcode: ST1i32 +/* 35006 */ MCD_OPC_FilterValue, 1, 225, 202, 0, // Skip to: 86948 +/* 35011 */ MCD_OPC_CheckPredicate, 3, 220, 202, 0, // Skip to: 86948 +/* 35016 */ MCD_OPC_CheckField, 31, 1, 0, 213, 202, 0, // Skip to: 86948 +/* 35023 */ MCD_OPC_CheckField, 12, 1, 0, 206, 202, 0, // Skip to: 86948 +/* 35030 */ MCD_OPC_Decode, 133, 28, 174, 1, // Opcode: ST1i64 +/* 35035 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 35094 +/* 35040 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 35043 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35065 +/* 35048 */ MCD_OPC_CheckPredicate, 3, 183, 202, 0, // Skip to: 86948 +/* 35053 */ MCD_OPC_CheckField, 31, 1, 0, 176, 202, 0, // Skip to: 86948 +/* 35060 */ MCD_OPC_Decode, 191, 28, 175, 1, // Opcode: ST3i32 +/* 35065 */ MCD_OPC_FilterValue, 1, 166, 202, 0, // Skip to: 86948 +/* 35070 */ MCD_OPC_CheckPredicate, 3, 161, 202, 0, // Skip to: 86948 +/* 35075 */ MCD_OPC_CheckField, 31, 1, 0, 154, 202, 0, // Skip to: 86948 +/* 35082 */ MCD_OPC_CheckField, 12, 1, 0, 147, 202, 0, // Skip to: 86948 +/* 35089 */ MCD_OPC_Decode, 193, 28, 176, 1, // Opcode: ST3i64 +/* 35094 */ MCD_OPC_FilterValue, 128, 2, 17, 0, 0, // Skip to: 35117 +/* 35100 */ MCD_OPC_CheckPredicate, 3, 131, 202, 0, // Skip to: 86948 +/* 35105 */ MCD_OPC_CheckField, 31, 1, 0, 124, 202, 0, // Skip to: 86948 +/* 35112 */ MCD_OPC_Decode, 165, 28, 177, 1, // Opcode: ST2i8 +/* 35117 */ MCD_OPC_FilterValue, 129, 2, 17, 0, 0, // Skip to: 35140 +/* 35123 */ MCD_OPC_CheckPredicate, 3, 108, 202, 0, // Skip to: 86948 +/* 35128 */ MCD_OPC_CheckField, 31, 1, 0, 101, 202, 0, // Skip to: 86948 +/* 35135 */ MCD_OPC_Decode, 225, 28, 178, 1, // Opcode: ST4i8 +/* 35140 */ MCD_OPC_FilterValue, 130, 2, 24, 0, 0, // Skip to: 35170 +/* 35146 */ MCD_OPC_CheckPredicate, 3, 85, 202, 0, // Skip to: 86948 +/* 35151 */ MCD_OPC_CheckField, 31, 1, 0, 78, 202, 0, // Skip to: 86948 +/* 35158 */ MCD_OPC_CheckField, 10, 1, 0, 71, 202, 0, // Skip to: 86948 +/* 35165 */ MCD_OPC_Decode, 159, 28, 179, 1, // Opcode: ST2i16 +/* 35170 */ MCD_OPC_FilterValue, 131, 2, 24, 0, 0, // Skip to: 35200 +/* 35176 */ MCD_OPC_CheckPredicate, 3, 55, 202, 0, // Skip to: 86948 +/* 35181 */ MCD_OPC_CheckField, 31, 1, 0, 48, 202, 0, // Skip to: 86948 +/* 35188 */ MCD_OPC_CheckField, 10, 1, 0, 41, 202, 0, // Skip to: 86948 +/* 35195 */ MCD_OPC_Decode, 219, 28, 180, 1, // Opcode: ST4i16 +/* 35200 */ MCD_OPC_FilterValue, 132, 2, 54, 0, 0, // Skip to: 35260 +/* 35206 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 35209 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35231 +/* 35214 */ MCD_OPC_CheckPredicate, 3, 17, 202, 0, // Skip to: 86948 +/* 35219 */ MCD_OPC_CheckField, 31, 1, 0, 10, 202, 0, // Skip to: 86948 +/* 35226 */ MCD_OPC_Decode, 161, 28, 181, 1, // Opcode: ST2i32 +/* 35231 */ MCD_OPC_FilterValue, 1, 0, 202, 0, // Skip to: 86948 +/* 35236 */ MCD_OPC_CheckPredicate, 3, 251, 201, 0, // Skip to: 86948 +/* 35241 */ MCD_OPC_CheckField, 31, 1, 0, 244, 201, 0, // Skip to: 86948 +/* 35248 */ MCD_OPC_CheckField, 12, 1, 0, 237, 201, 0, // Skip to: 86948 +/* 35255 */ MCD_OPC_Decode, 163, 28, 182, 1, // Opcode: ST2i64 +/* 35260 */ MCD_OPC_FilterValue, 133, 2, 226, 201, 0, // Skip to: 86948 +/* 35266 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 35269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35291 +/* 35274 */ MCD_OPC_CheckPredicate, 3, 213, 201, 0, // Skip to: 86948 +/* 35279 */ MCD_OPC_CheckField, 31, 1, 0, 206, 201, 0, // Skip to: 86948 +/* 35286 */ MCD_OPC_Decode, 221, 28, 183, 1, // Opcode: ST4i32 +/* 35291 */ MCD_OPC_FilterValue, 1, 196, 201, 0, // Skip to: 86948 +/* 35296 */ MCD_OPC_CheckPredicate, 3, 191, 201, 0, // Skip to: 86948 +/* 35301 */ MCD_OPC_CheckField, 31, 1, 0, 184, 201, 0, // Skip to: 86948 +/* 35308 */ MCD_OPC_CheckField, 12, 1, 0, 177, 201, 0, // Skip to: 86948 +/* 35315 */ MCD_OPC_Decode, 223, 28, 184, 1, // Opcode: ST4i64 +/* 35320 */ MCD_OPC_FilterValue, 1, 167, 201, 0, // Skip to: 86948 +/* 35325 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35328 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 35338 +/* 35333 */ MCD_OPC_Decode, 136, 29, 150, 1, // Opcode: STPSi +/* 35338 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 35348 +/* 35343 */ MCD_OPC_Decode, 130, 29, 150, 1, // Opcode: STPDi +/* 35348 */ MCD_OPC_FilterValue, 2, 139, 201, 0, // Skip to: 86948 +/* 35353 */ MCD_OPC_Decode, 133, 29, 150, 1, // Opcode: STPQi +/* 35358 */ MCD_OPC_FilterValue, 5, 113, 4, 0, // Skip to: 36500 +/* 35363 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 35366 */ MCD_OPC_FilterValue, 0, 67, 4, 0, // Skip to: 36462 +/* 35371 */ MCD_OPC_ExtractField, 13, 9, // Inst{21-13} ... +/* 35374 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35396 +/* 35379 */ MCD_OPC_CheckPredicate, 3, 108, 201, 0, // Skip to: 86948 +/* 35384 */ MCD_OPC_CheckField, 31, 1, 0, 101, 201, 0, // Skip to: 86948 +/* 35391 */ MCD_OPC_Decode, 193, 15, 185, 1, // Opcode: LD1i8 +/* 35396 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 35418 +/* 35401 */ MCD_OPC_CheckPredicate, 3, 86, 201, 0, // Skip to: 86948 +/* 35406 */ MCD_OPC_CheckField, 31, 1, 0, 79, 201, 0, // Skip to: 86948 +/* 35413 */ MCD_OPC_Decode, 157, 16, 186, 1, // Opcode: LD3i8 +/* 35418 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 35447 +/* 35423 */ MCD_OPC_CheckPredicate, 3, 64, 201, 0, // Skip to: 86948 +/* 35428 */ MCD_OPC_CheckField, 31, 1, 0, 57, 201, 0, // Skip to: 86948 +/* 35435 */ MCD_OPC_CheckField, 10, 1, 0, 50, 201, 0, // Skip to: 86948 +/* 35442 */ MCD_OPC_Decode, 187, 15, 187, 1, // Opcode: LD1i16 +/* 35447 */ MCD_OPC_FilterValue, 3, 24, 0, 0, // Skip to: 35476 +/* 35452 */ MCD_OPC_CheckPredicate, 3, 35, 201, 0, // Skip to: 86948 +/* 35457 */ MCD_OPC_CheckField, 31, 1, 0, 28, 201, 0, // Skip to: 86948 +/* 35464 */ MCD_OPC_CheckField, 10, 1, 0, 21, 201, 0, // Skip to: 86948 +/* 35471 */ MCD_OPC_Decode, 151, 16, 188, 1, // Opcode: LD3i16 +/* 35476 */ MCD_OPC_FilterValue, 4, 54, 0, 0, // Skip to: 35535 +/* 35481 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 35484 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35506 +/* 35489 */ MCD_OPC_CheckPredicate, 3, 254, 200, 0, // Skip to: 86948 +/* 35494 */ MCD_OPC_CheckField, 31, 1, 0, 247, 200, 0, // Skip to: 86948 +/* 35501 */ MCD_OPC_Decode, 189, 15, 189, 1, // Opcode: LD1i32 +/* 35506 */ MCD_OPC_FilterValue, 1, 237, 200, 0, // Skip to: 86948 +/* 35511 */ MCD_OPC_CheckPredicate, 3, 232, 200, 0, // Skip to: 86948 +/* 35516 */ MCD_OPC_CheckField, 31, 1, 0, 225, 200, 0, // Skip to: 86948 +/* 35523 */ MCD_OPC_CheckField, 12, 1, 0, 218, 200, 0, // Skip to: 86948 +/* 35530 */ MCD_OPC_Decode, 191, 15, 190, 1, // Opcode: LD1i64 +/* 35535 */ MCD_OPC_FilterValue, 5, 54, 0, 0, // Skip to: 35594 +/* 35540 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 35543 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 35565 +/* 35548 */ MCD_OPC_CheckPredicate, 3, 195, 200, 0, // Skip to: 86948 +/* 35553 */ MCD_OPC_CheckField, 31, 1, 0, 188, 200, 0, // Skip to: 86948 +/* 35560 */ MCD_OPC_Decode, 153, 16, 191, 1, // Opcode: LD3i32 +/* 35565 */ MCD_OPC_FilterValue, 1, 178, 200, 0, // Skip to: 86948 +/* 35570 */ MCD_OPC_CheckPredicate, 3, 173, 200, 0, // Skip to: 86948 +/* 35575 */ MCD_OPC_CheckField, 31, 1, 0, 166, 200, 0, // Skip to: 86948 +/* 35582 */ MCD_OPC_CheckField, 12, 1, 0, 159, 200, 0, // Skip to: 86948 +/* 35589 */ MCD_OPC_Decode, 155, 16, 192, 1, // Opcode: LD3i64 +/* 35594 */ MCD_OPC_FilterValue, 6, 155, 0, 0, // Skip to: 35754 +/* 35599 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 35602 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 35640 +/* 35607 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35610 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35625 +/* 35615 */ MCD_OPC_CheckPredicate, 3, 128, 200, 0, // Skip to: 86948 +/* 35620 */ MCD_OPC_Decode, 135, 15, 155, 1, // Opcode: LD1Rv8b +/* 35625 */ MCD_OPC_FilterValue, 1, 118, 200, 0, // Skip to: 86948 +/* 35630 */ MCD_OPC_CheckPredicate, 3, 113, 200, 0, // Skip to: 86948 +/* 35635 */ MCD_OPC_Decode, 251, 14, 159, 1, // Opcode: LD1Rv16b +/* 35640 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 35678 +/* 35645 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35648 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35663 +/* 35653 */ MCD_OPC_CheckPredicate, 3, 90, 200, 0, // Skip to: 86948 +/* 35658 */ MCD_OPC_Decode, 131, 15, 155, 1, // Opcode: LD1Rv4h +/* 35663 */ MCD_OPC_FilterValue, 1, 80, 200, 0, // Skip to: 86948 +/* 35668 */ MCD_OPC_CheckPredicate, 3, 75, 200, 0, // Skip to: 86948 +/* 35673 */ MCD_OPC_Decode, 137, 15, 159, 1, // Opcode: LD1Rv8h +/* 35678 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 35716 +/* 35683 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35686 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35701 +/* 35691 */ MCD_OPC_CheckPredicate, 3, 52, 200, 0, // Skip to: 86948 +/* 35696 */ MCD_OPC_Decode, 129, 15, 155, 1, // Opcode: LD1Rv2s +/* 35701 */ MCD_OPC_FilterValue, 1, 42, 200, 0, // Skip to: 86948 +/* 35706 */ MCD_OPC_CheckPredicate, 3, 37, 200, 0, // Skip to: 86948 +/* 35711 */ MCD_OPC_Decode, 133, 15, 159, 1, // Opcode: LD1Rv4s +/* 35716 */ MCD_OPC_FilterValue, 3, 27, 200, 0, // Skip to: 86948 +/* 35721 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35724 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35739 +/* 35729 */ MCD_OPC_CheckPredicate, 3, 14, 200, 0, // Skip to: 86948 +/* 35734 */ MCD_OPC_Decode, 253, 14, 155, 1, // Opcode: LD1Rv1d +/* 35739 */ MCD_OPC_FilterValue, 1, 4, 200, 0, // Skip to: 86948 +/* 35744 */ MCD_OPC_CheckPredicate, 3, 255, 199, 0, // Skip to: 86948 +/* 35749 */ MCD_OPC_Decode, 255, 14, 159, 1, // Opcode: LD1Rv2d +/* 35754 */ MCD_OPC_FilterValue, 7, 155, 0, 0, // Skip to: 35914 +/* 35759 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 35762 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 35800 +/* 35767 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35770 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35785 +/* 35775 */ MCD_OPC_CheckPredicate, 3, 224, 199, 0, // Skip to: 86948 +/* 35780 */ MCD_OPC_Decode, 131, 16, 154, 1, // Opcode: LD3Rv8b +/* 35785 */ MCD_OPC_FilterValue, 1, 214, 199, 0, // Skip to: 86948 +/* 35790 */ MCD_OPC_CheckPredicate, 3, 209, 199, 0, // Skip to: 86948 +/* 35795 */ MCD_OPC_Decode, 247, 15, 158, 1, // Opcode: LD3Rv16b +/* 35800 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 35838 +/* 35805 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35808 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35823 +/* 35813 */ MCD_OPC_CheckPredicate, 3, 186, 199, 0, // Skip to: 86948 +/* 35818 */ MCD_OPC_Decode, 255, 15, 154, 1, // Opcode: LD3Rv4h +/* 35823 */ MCD_OPC_FilterValue, 1, 176, 199, 0, // Skip to: 86948 +/* 35828 */ MCD_OPC_CheckPredicate, 3, 171, 199, 0, // Skip to: 86948 +/* 35833 */ MCD_OPC_Decode, 133, 16, 158, 1, // Opcode: LD3Rv8h +/* 35838 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 35876 +/* 35843 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35846 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35861 +/* 35851 */ MCD_OPC_CheckPredicate, 3, 148, 199, 0, // Skip to: 86948 +/* 35856 */ MCD_OPC_Decode, 253, 15, 154, 1, // Opcode: LD3Rv2s +/* 35861 */ MCD_OPC_FilterValue, 1, 138, 199, 0, // Skip to: 86948 +/* 35866 */ MCD_OPC_CheckPredicate, 3, 133, 199, 0, // Skip to: 86948 +/* 35871 */ MCD_OPC_Decode, 129, 16, 158, 1, // Opcode: LD3Rv4s +/* 35876 */ MCD_OPC_FilterValue, 3, 123, 199, 0, // Skip to: 86948 +/* 35881 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 35884 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 35899 +/* 35889 */ MCD_OPC_CheckPredicate, 3, 110, 199, 0, // Skip to: 86948 +/* 35894 */ MCD_OPC_Decode, 249, 15, 154, 1, // Opcode: LD3Rv1d +/* 35899 */ MCD_OPC_FilterValue, 1, 100, 199, 0, // Skip to: 86948 +/* 35904 */ MCD_OPC_CheckPredicate, 3, 95, 199, 0, // Skip to: 86948 +/* 35909 */ MCD_OPC_Decode, 251, 15, 158, 1, // Opcode: LD3Rv2d +/* 35914 */ MCD_OPC_FilterValue, 128, 2, 17, 0, 0, // Skip to: 35937 +/* 35920 */ MCD_OPC_CheckPredicate, 3, 79, 199, 0, // Skip to: 86948 +/* 35925 */ MCD_OPC_CheckField, 31, 1, 0, 72, 199, 0, // Skip to: 86948 +/* 35932 */ MCD_OPC_Decode, 239, 15, 193, 1, // Opcode: LD2i8 +/* 35937 */ MCD_OPC_FilterValue, 129, 2, 17, 0, 0, // Skip to: 35960 +/* 35943 */ MCD_OPC_CheckPredicate, 3, 56, 199, 0, // Skip to: 86948 +/* 35948 */ MCD_OPC_CheckField, 31, 1, 0, 49, 199, 0, // Skip to: 86948 +/* 35955 */ MCD_OPC_Decode, 203, 16, 194, 1, // Opcode: LD4i8 +/* 35960 */ MCD_OPC_FilterValue, 130, 2, 24, 0, 0, // Skip to: 35990 +/* 35966 */ MCD_OPC_CheckPredicate, 3, 33, 199, 0, // Skip to: 86948 +/* 35971 */ MCD_OPC_CheckField, 31, 1, 0, 26, 199, 0, // Skip to: 86948 +/* 35978 */ MCD_OPC_CheckField, 10, 1, 0, 19, 199, 0, // Skip to: 86948 +/* 35985 */ MCD_OPC_Decode, 233, 15, 195, 1, // Opcode: LD2i16 +/* 35990 */ MCD_OPC_FilterValue, 131, 2, 24, 0, 0, // Skip to: 36020 +/* 35996 */ MCD_OPC_CheckPredicate, 3, 3, 199, 0, // Skip to: 86948 +/* 36001 */ MCD_OPC_CheckField, 31, 1, 0, 252, 198, 0, // Skip to: 86948 +/* 36008 */ MCD_OPC_CheckField, 10, 1, 0, 245, 198, 0, // Skip to: 86948 +/* 36015 */ MCD_OPC_Decode, 197, 16, 196, 1, // Opcode: LD4i16 +/* 36020 */ MCD_OPC_FilterValue, 132, 2, 54, 0, 0, // Skip to: 36080 +/* 36026 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 36029 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36051 +/* 36034 */ MCD_OPC_CheckPredicate, 3, 221, 198, 0, // Skip to: 86948 +/* 36039 */ MCD_OPC_CheckField, 31, 1, 0, 214, 198, 0, // Skip to: 86948 +/* 36046 */ MCD_OPC_Decode, 235, 15, 197, 1, // Opcode: LD2i32 +/* 36051 */ MCD_OPC_FilterValue, 1, 204, 198, 0, // Skip to: 86948 +/* 36056 */ MCD_OPC_CheckPredicate, 3, 199, 198, 0, // Skip to: 86948 +/* 36061 */ MCD_OPC_CheckField, 31, 1, 0, 192, 198, 0, // Skip to: 86948 +/* 36068 */ MCD_OPC_CheckField, 12, 1, 0, 185, 198, 0, // Skip to: 86948 +/* 36075 */ MCD_OPC_Decode, 237, 15, 198, 1, // Opcode: LD2i64 +/* 36080 */ MCD_OPC_FilterValue, 133, 2, 54, 0, 0, // Skip to: 36140 +/* 36086 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 36089 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36111 +/* 36094 */ MCD_OPC_CheckPredicate, 3, 161, 198, 0, // Skip to: 86948 +/* 36099 */ MCD_OPC_CheckField, 31, 1, 0, 154, 198, 0, // Skip to: 86948 +/* 36106 */ MCD_OPC_Decode, 199, 16, 199, 1, // Opcode: LD4i32 +/* 36111 */ MCD_OPC_FilterValue, 1, 144, 198, 0, // Skip to: 86948 +/* 36116 */ MCD_OPC_CheckPredicate, 3, 139, 198, 0, // Skip to: 86948 +/* 36121 */ MCD_OPC_CheckField, 31, 1, 0, 132, 198, 0, // Skip to: 86948 +/* 36128 */ MCD_OPC_CheckField, 12, 1, 0, 125, 198, 0, // Skip to: 86948 +/* 36135 */ MCD_OPC_Decode, 201, 16, 200, 1, // Opcode: LD4i64 +/* 36140 */ MCD_OPC_FilterValue, 134, 2, 155, 0, 0, // Skip to: 36301 +/* 36146 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 36149 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 36187 +/* 36154 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36157 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36172 +/* 36162 */ MCD_OPC_CheckPredicate, 3, 93, 198, 0, // Skip to: 86948 +/* 36167 */ MCD_OPC_Decode, 213, 15, 156, 1, // Opcode: LD2Rv8b +/* 36172 */ MCD_OPC_FilterValue, 1, 83, 198, 0, // Skip to: 86948 +/* 36177 */ MCD_OPC_CheckPredicate, 3, 78, 198, 0, // Skip to: 86948 +/* 36182 */ MCD_OPC_Decode, 201, 15, 160, 1, // Opcode: LD2Rv16b +/* 36187 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 36225 +/* 36192 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36195 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36210 +/* 36200 */ MCD_OPC_CheckPredicate, 3, 55, 198, 0, // Skip to: 86948 +/* 36205 */ MCD_OPC_Decode, 209, 15, 156, 1, // Opcode: LD2Rv4h +/* 36210 */ MCD_OPC_FilterValue, 1, 45, 198, 0, // Skip to: 86948 +/* 36215 */ MCD_OPC_CheckPredicate, 3, 40, 198, 0, // Skip to: 86948 +/* 36220 */ MCD_OPC_Decode, 215, 15, 160, 1, // Opcode: LD2Rv8h +/* 36225 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 36263 +/* 36230 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36233 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36248 +/* 36238 */ MCD_OPC_CheckPredicate, 3, 17, 198, 0, // Skip to: 86948 +/* 36243 */ MCD_OPC_Decode, 207, 15, 156, 1, // Opcode: LD2Rv2s +/* 36248 */ MCD_OPC_FilterValue, 1, 7, 198, 0, // Skip to: 86948 +/* 36253 */ MCD_OPC_CheckPredicate, 3, 2, 198, 0, // Skip to: 86948 +/* 36258 */ MCD_OPC_Decode, 211, 15, 160, 1, // Opcode: LD2Rv4s +/* 36263 */ MCD_OPC_FilterValue, 3, 248, 197, 0, // Skip to: 86948 +/* 36268 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36271 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36286 +/* 36276 */ MCD_OPC_CheckPredicate, 3, 235, 197, 0, // Skip to: 86948 +/* 36281 */ MCD_OPC_Decode, 203, 15, 156, 1, // Opcode: LD2Rv1d +/* 36286 */ MCD_OPC_FilterValue, 1, 225, 197, 0, // Skip to: 86948 +/* 36291 */ MCD_OPC_CheckPredicate, 3, 220, 197, 0, // Skip to: 86948 +/* 36296 */ MCD_OPC_Decode, 205, 15, 160, 1, // Opcode: LD2Rv2d +/* 36301 */ MCD_OPC_FilterValue, 135, 2, 209, 197, 0, // Skip to: 86948 +/* 36307 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 36310 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 36348 +/* 36315 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36318 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36333 +/* 36323 */ MCD_OPC_CheckPredicate, 3, 188, 197, 0, // Skip to: 86948 +/* 36328 */ MCD_OPC_Decode, 191, 16, 153, 1, // Opcode: LD4Rv8b +/* 36333 */ MCD_OPC_FilterValue, 1, 178, 197, 0, // Skip to: 86948 +/* 36338 */ MCD_OPC_CheckPredicate, 3, 173, 197, 0, // Skip to: 86948 +/* 36343 */ MCD_OPC_Decode, 179, 16, 157, 1, // Opcode: LD4Rv16b +/* 36348 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 36386 +/* 36353 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36356 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36371 +/* 36361 */ MCD_OPC_CheckPredicate, 3, 150, 197, 0, // Skip to: 86948 +/* 36366 */ MCD_OPC_Decode, 187, 16, 153, 1, // Opcode: LD4Rv4h +/* 36371 */ MCD_OPC_FilterValue, 1, 140, 197, 0, // Skip to: 86948 +/* 36376 */ MCD_OPC_CheckPredicate, 3, 135, 197, 0, // Skip to: 86948 +/* 36381 */ MCD_OPC_Decode, 193, 16, 157, 1, // Opcode: LD4Rv8h +/* 36386 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 36424 +/* 36391 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36394 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36409 +/* 36399 */ MCD_OPC_CheckPredicate, 3, 112, 197, 0, // Skip to: 86948 +/* 36404 */ MCD_OPC_Decode, 185, 16, 153, 1, // Opcode: LD4Rv2s +/* 36409 */ MCD_OPC_FilterValue, 1, 102, 197, 0, // Skip to: 86948 +/* 36414 */ MCD_OPC_CheckPredicate, 3, 97, 197, 0, // Skip to: 86948 +/* 36419 */ MCD_OPC_Decode, 189, 16, 157, 1, // Opcode: LD4Rv4s +/* 36424 */ MCD_OPC_FilterValue, 3, 87, 197, 0, // Skip to: 86948 +/* 36429 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36432 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 36447 +/* 36437 */ MCD_OPC_CheckPredicate, 3, 74, 197, 0, // Skip to: 86948 +/* 36442 */ MCD_OPC_Decode, 181, 16, 153, 1, // Opcode: LD4Rv1d +/* 36447 */ MCD_OPC_FilterValue, 1, 64, 197, 0, // Skip to: 86948 +/* 36452 */ MCD_OPC_CheckPredicate, 3, 59, 197, 0, // Skip to: 86948 +/* 36457 */ MCD_OPC_Decode, 183, 16, 157, 1, // Opcode: LD4Rv2d +/* 36462 */ MCD_OPC_FilterValue, 1, 49, 197, 0, // Skip to: 86948 +/* 36467 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 36470 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 36480 +/* 36475 */ MCD_OPC_Decode, 206, 17, 150, 1, // Opcode: LDPSi +/* 36480 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 36490 +/* 36485 */ MCD_OPC_Decode, 197, 17, 150, 1, // Opcode: LDPDi +/* 36490 */ MCD_OPC_FilterValue, 2, 21, 197, 0, // Skip to: 86948 +/* 36495 */ MCD_OPC_Decode, 200, 17, 150, 1, // Opcode: LDPQi +/* 36500 */ MCD_OPC_FilterValue, 6, 25, 2, 0, // Skip to: 37042 +/* 36505 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 36508 */ MCD_OPC_FilterValue, 0, 235, 1, 0, // Skip to: 37004 +/* 36513 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 36516 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36568 +/* 36521 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36524 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36546 +/* 36529 */ MCD_OPC_CheckPredicate, 3, 238, 196, 0, // Skip to: 86948 +/* 36534 */ MCD_OPC_CheckField, 31, 1, 0, 231, 196, 0, // Skip to: 86948 +/* 36541 */ MCD_OPC_Decode, 136, 28, 201, 1, // Opcode: ST1i8_POST +/* 36546 */ MCD_OPC_FilterValue, 1, 221, 196, 0, // Skip to: 86948 +/* 36551 */ MCD_OPC_CheckPredicate, 3, 216, 196, 0, // Skip to: 86948 +/* 36556 */ MCD_OPC_CheckField, 31, 1, 0, 209, 196, 0, // Skip to: 86948 +/* 36563 */ MCD_OPC_Decode, 166, 28, 202, 1, // Opcode: ST2i8_POST +/* 36568 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 36620 +/* 36573 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36576 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36598 +/* 36581 */ MCD_OPC_CheckPredicate, 3, 186, 196, 0, // Skip to: 86948 +/* 36586 */ MCD_OPC_CheckField, 31, 1, 0, 179, 196, 0, // Skip to: 86948 +/* 36593 */ MCD_OPC_Decode, 196, 28, 203, 1, // Opcode: ST3i8_POST +/* 36598 */ MCD_OPC_FilterValue, 1, 169, 196, 0, // Skip to: 86948 +/* 36603 */ MCD_OPC_CheckPredicate, 3, 164, 196, 0, // Skip to: 86948 +/* 36608 */ MCD_OPC_CheckField, 31, 1, 0, 157, 196, 0, // Skip to: 86948 +/* 36615 */ MCD_OPC_Decode, 226, 28, 204, 1, // Opcode: ST4i8_POST +/* 36620 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 36686 +/* 36625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36628 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36657 +/* 36633 */ MCD_OPC_CheckPredicate, 3, 134, 196, 0, // Skip to: 86948 +/* 36638 */ MCD_OPC_CheckField, 31, 1, 0, 127, 196, 0, // Skip to: 86948 +/* 36645 */ MCD_OPC_CheckField, 10, 1, 0, 120, 196, 0, // Skip to: 86948 +/* 36652 */ MCD_OPC_Decode, 130, 28, 205, 1, // Opcode: ST1i16_POST +/* 36657 */ MCD_OPC_FilterValue, 1, 110, 196, 0, // Skip to: 86948 +/* 36662 */ MCD_OPC_CheckPredicate, 3, 105, 196, 0, // Skip to: 86948 +/* 36667 */ MCD_OPC_CheckField, 31, 1, 0, 98, 196, 0, // Skip to: 86948 +/* 36674 */ MCD_OPC_CheckField, 10, 1, 0, 91, 196, 0, // Skip to: 86948 +/* 36681 */ MCD_OPC_Decode, 160, 28, 206, 1, // Opcode: ST2i16_POST +/* 36686 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 36752 +/* 36691 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36694 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36723 +/* 36699 */ MCD_OPC_CheckPredicate, 3, 68, 196, 0, // Skip to: 86948 +/* 36704 */ MCD_OPC_CheckField, 31, 1, 0, 61, 196, 0, // Skip to: 86948 +/* 36711 */ MCD_OPC_CheckField, 10, 1, 0, 54, 196, 0, // Skip to: 86948 +/* 36718 */ MCD_OPC_Decode, 190, 28, 207, 1, // Opcode: ST3i16_POST +/* 36723 */ MCD_OPC_FilterValue, 1, 44, 196, 0, // Skip to: 86948 +/* 36728 */ MCD_OPC_CheckPredicate, 3, 39, 196, 0, // Skip to: 86948 +/* 36733 */ MCD_OPC_CheckField, 31, 1, 0, 32, 196, 0, // Skip to: 86948 +/* 36740 */ MCD_OPC_CheckField, 10, 1, 0, 25, 196, 0, // Skip to: 86948 +/* 36747 */ MCD_OPC_Decode, 220, 28, 208, 1, // Opcode: ST4i16_POST +/* 36752 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 36878 +/* 36757 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 36760 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36812 +/* 36765 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36768 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36790 +/* 36773 */ MCD_OPC_CheckPredicate, 3, 250, 195, 0, // Skip to: 86948 +/* 36778 */ MCD_OPC_CheckField, 31, 1, 0, 243, 195, 0, // Skip to: 86948 +/* 36785 */ MCD_OPC_Decode, 132, 28, 209, 1, // Opcode: ST1i32_POST +/* 36790 */ MCD_OPC_FilterValue, 1, 233, 195, 0, // Skip to: 86948 +/* 36795 */ MCD_OPC_CheckPredicate, 3, 228, 195, 0, // Skip to: 86948 +/* 36800 */ MCD_OPC_CheckField, 31, 1, 0, 221, 195, 0, // Skip to: 86948 +/* 36807 */ MCD_OPC_Decode, 162, 28, 210, 1, // Opcode: ST2i32_POST +/* 36812 */ MCD_OPC_FilterValue, 1, 211, 195, 0, // Skip to: 86948 +/* 36817 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36820 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36849 +/* 36825 */ MCD_OPC_CheckPredicate, 3, 198, 195, 0, // Skip to: 86948 +/* 36830 */ MCD_OPC_CheckField, 31, 1, 0, 191, 195, 0, // Skip to: 86948 +/* 36837 */ MCD_OPC_CheckField, 12, 1, 0, 184, 195, 0, // Skip to: 86948 +/* 36844 */ MCD_OPC_Decode, 134, 28, 211, 1, // Opcode: ST1i64_POST +/* 36849 */ MCD_OPC_FilterValue, 1, 174, 195, 0, // Skip to: 86948 +/* 36854 */ MCD_OPC_CheckPredicate, 3, 169, 195, 0, // Skip to: 86948 +/* 36859 */ MCD_OPC_CheckField, 31, 1, 0, 162, 195, 0, // Skip to: 86948 +/* 36866 */ MCD_OPC_CheckField, 12, 1, 0, 155, 195, 0, // Skip to: 86948 +/* 36873 */ MCD_OPC_Decode, 164, 28, 212, 1, // Opcode: ST2i64_POST +/* 36878 */ MCD_OPC_FilterValue, 5, 145, 195, 0, // Skip to: 86948 +/* 36883 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 36886 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 36938 +/* 36891 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36894 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 36916 +/* 36899 */ MCD_OPC_CheckPredicate, 3, 124, 195, 0, // Skip to: 86948 +/* 36904 */ MCD_OPC_CheckField, 31, 1, 0, 117, 195, 0, // Skip to: 86948 +/* 36911 */ MCD_OPC_Decode, 192, 28, 213, 1, // Opcode: ST3i32_POST +/* 36916 */ MCD_OPC_FilterValue, 1, 107, 195, 0, // Skip to: 86948 +/* 36921 */ MCD_OPC_CheckPredicate, 3, 102, 195, 0, // Skip to: 86948 +/* 36926 */ MCD_OPC_CheckField, 31, 1, 0, 95, 195, 0, // Skip to: 86948 +/* 36933 */ MCD_OPC_Decode, 222, 28, 214, 1, // Opcode: ST4i32_POST +/* 36938 */ MCD_OPC_FilterValue, 1, 85, 195, 0, // Skip to: 86948 +/* 36943 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 36946 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 36975 +/* 36951 */ MCD_OPC_CheckPredicate, 3, 72, 195, 0, // Skip to: 86948 +/* 36956 */ MCD_OPC_CheckField, 31, 1, 0, 65, 195, 0, // Skip to: 86948 +/* 36963 */ MCD_OPC_CheckField, 12, 1, 0, 58, 195, 0, // Skip to: 86948 +/* 36970 */ MCD_OPC_Decode, 194, 28, 215, 1, // Opcode: ST3i64_POST +/* 36975 */ MCD_OPC_FilterValue, 1, 48, 195, 0, // Skip to: 86948 +/* 36980 */ MCD_OPC_CheckPredicate, 3, 43, 195, 0, // Skip to: 86948 +/* 36985 */ MCD_OPC_CheckField, 31, 1, 0, 36, 195, 0, // Skip to: 86948 +/* 36992 */ MCD_OPC_CheckField, 12, 1, 0, 29, 195, 0, // Skip to: 86948 +/* 36999 */ MCD_OPC_Decode, 224, 28, 216, 1, // Opcode: ST4i64_POST +/* 37004 */ MCD_OPC_FilterValue, 1, 19, 195, 0, // Skip to: 86948 +/* 37009 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37012 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 37022 +/* 37017 */ MCD_OPC_Decode, 138, 29, 150, 1, // Opcode: STPSpre +/* 37022 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 37032 +/* 37027 */ MCD_OPC_Decode, 132, 29, 150, 1, // Opcode: STPDpre +/* 37032 */ MCD_OPC_FilterValue, 2, 247, 194, 0, // Skip to: 86948 +/* 37037 */ MCD_OPC_Decode, 135, 29, 150, 1, // Opcode: STPQpre +/* 37042 */ MCD_OPC_FilterValue, 7, 201, 4, 0, // Skip to: 38272 +/* 37047 */ MCD_OPC_ExtractField, 29, 1, // Inst{29} ... +/* 37050 */ MCD_OPC_FilterValue, 0, 155, 4, 0, // Skip to: 38234 +/* 37055 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 37058 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37110 +/* 37063 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37066 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37088 +/* 37071 */ MCD_OPC_CheckPredicate, 3, 208, 194, 0, // Skip to: 86948 +/* 37076 */ MCD_OPC_CheckField, 31, 1, 0, 201, 194, 0, // Skip to: 86948 +/* 37083 */ MCD_OPC_Decode, 194, 15, 217, 1, // Opcode: LD1i8_POST +/* 37088 */ MCD_OPC_FilterValue, 1, 191, 194, 0, // Skip to: 86948 +/* 37093 */ MCD_OPC_CheckPredicate, 3, 186, 194, 0, // Skip to: 86948 +/* 37098 */ MCD_OPC_CheckField, 31, 1, 0, 179, 194, 0, // Skip to: 86948 +/* 37105 */ MCD_OPC_Decode, 240, 15, 218, 1, // Opcode: LD2i8_POST +/* 37110 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 37162 +/* 37115 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37118 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37140 +/* 37123 */ MCD_OPC_CheckPredicate, 3, 156, 194, 0, // Skip to: 86948 +/* 37128 */ MCD_OPC_CheckField, 31, 1, 0, 149, 194, 0, // Skip to: 86948 +/* 37135 */ MCD_OPC_Decode, 158, 16, 219, 1, // Opcode: LD3i8_POST +/* 37140 */ MCD_OPC_FilterValue, 1, 139, 194, 0, // Skip to: 86948 +/* 37145 */ MCD_OPC_CheckPredicate, 3, 134, 194, 0, // Skip to: 86948 +/* 37150 */ MCD_OPC_CheckField, 31, 1, 0, 127, 194, 0, // Skip to: 86948 +/* 37157 */ MCD_OPC_Decode, 204, 16, 220, 1, // Opcode: LD4i8_POST +/* 37162 */ MCD_OPC_FilterValue, 2, 61, 0, 0, // Skip to: 37228 +/* 37167 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37170 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37199 +/* 37175 */ MCD_OPC_CheckPredicate, 3, 104, 194, 0, // Skip to: 86948 +/* 37180 */ MCD_OPC_CheckField, 31, 1, 0, 97, 194, 0, // Skip to: 86948 +/* 37187 */ MCD_OPC_CheckField, 10, 1, 0, 90, 194, 0, // Skip to: 86948 +/* 37194 */ MCD_OPC_Decode, 188, 15, 221, 1, // Opcode: LD1i16_POST +/* 37199 */ MCD_OPC_FilterValue, 1, 80, 194, 0, // Skip to: 86948 +/* 37204 */ MCD_OPC_CheckPredicate, 3, 75, 194, 0, // Skip to: 86948 +/* 37209 */ MCD_OPC_CheckField, 31, 1, 0, 68, 194, 0, // Skip to: 86948 +/* 37216 */ MCD_OPC_CheckField, 10, 1, 0, 61, 194, 0, // Skip to: 86948 +/* 37223 */ MCD_OPC_Decode, 234, 15, 222, 1, // Opcode: LD2i16_POST +/* 37228 */ MCD_OPC_FilterValue, 3, 61, 0, 0, // Skip to: 37294 +/* 37233 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37236 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37265 +/* 37241 */ MCD_OPC_CheckPredicate, 3, 38, 194, 0, // Skip to: 86948 +/* 37246 */ MCD_OPC_CheckField, 31, 1, 0, 31, 194, 0, // Skip to: 86948 +/* 37253 */ MCD_OPC_CheckField, 10, 1, 0, 24, 194, 0, // Skip to: 86948 +/* 37260 */ MCD_OPC_Decode, 152, 16, 223, 1, // Opcode: LD3i16_POST +/* 37265 */ MCD_OPC_FilterValue, 1, 14, 194, 0, // Skip to: 86948 +/* 37270 */ MCD_OPC_CheckPredicate, 3, 9, 194, 0, // Skip to: 86948 +/* 37275 */ MCD_OPC_CheckField, 31, 1, 0, 2, 194, 0, // Skip to: 86948 +/* 37282 */ MCD_OPC_CheckField, 10, 1, 0, 251, 193, 0, // Skip to: 86948 +/* 37289 */ MCD_OPC_Decode, 198, 16, 224, 1, // Opcode: LD4i16_POST +/* 37294 */ MCD_OPC_FilterValue, 4, 121, 0, 0, // Skip to: 37420 +/* 37299 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 37302 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37354 +/* 37307 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37310 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37332 +/* 37315 */ MCD_OPC_CheckPredicate, 3, 220, 193, 0, // Skip to: 86948 +/* 37320 */ MCD_OPC_CheckField, 31, 1, 0, 213, 193, 0, // Skip to: 86948 +/* 37327 */ MCD_OPC_Decode, 190, 15, 225, 1, // Opcode: LD1i32_POST +/* 37332 */ MCD_OPC_FilterValue, 1, 203, 193, 0, // Skip to: 86948 +/* 37337 */ MCD_OPC_CheckPredicate, 3, 198, 193, 0, // Skip to: 86948 +/* 37342 */ MCD_OPC_CheckField, 31, 1, 0, 191, 193, 0, // Skip to: 86948 +/* 37349 */ MCD_OPC_Decode, 236, 15, 226, 1, // Opcode: LD2i32_POST +/* 37354 */ MCD_OPC_FilterValue, 1, 181, 193, 0, // Skip to: 86948 +/* 37359 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37362 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37391 +/* 37367 */ MCD_OPC_CheckPredicate, 3, 168, 193, 0, // Skip to: 86948 +/* 37372 */ MCD_OPC_CheckField, 31, 1, 0, 161, 193, 0, // Skip to: 86948 +/* 37379 */ MCD_OPC_CheckField, 12, 1, 0, 154, 193, 0, // Skip to: 86948 +/* 37386 */ MCD_OPC_Decode, 192, 15, 227, 1, // Opcode: LD1i64_POST +/* 37391 */ MCD_OPC_FilterValue, 1, 144, 193, 0, // Skip to: 86948 +/* 37396 */ MCD_OPC_CheckPredicate, 3, 139, 193, 0, // Skip to: 86948 +/* 37401 */ MCD_OPC_CheckField, 31, 1, 0, 132, 193, 0, // Skip to: 86948 +/* 37408 */ MCD_OPC_CheckField, 12, 1, 0, 125, 193, 0, // Skip to: 86948 +/* 37415 */ MCD_OPC_Decode, 238, 15, 228, 1, // Opcode: LD2i64_POST +/* 37420 */ MCD_OPC_FilterValue, 5, 121, 0, 0, // Skip to: 37546 +/* 37425 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 37428 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 37480 +/* 37433 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37436 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 37458 +/* 37441 */ MCD_OPC_CheckPredicate, 3, 94, 193, 0, // Skip to: 86948 +/* 37446 */ MCD_OPC_CheckField, 31, 1, 0, 87, 193, 0, // Skip to: 86948 +/* 37453 */ MCD_OPC_Decode, 154, 16, 229, 1, // Opcode: LD3i32_POST +/* 37458 */ MCD_OPC_FilterValue, 1, 77, 193, 0, // Skip to: 86948 +/* 37463 */ MCD_OPC_CheckPredicate, 3, 72, 193, 0, // Skip to: 86948 +/* 37468 */ MCD_OPC_CheckField, 31, 1, 0, 65, 193, 0, // Skip to: 86948 +/* 37475 */ MCD_OPC_Decode, 200, 16, 230, 1, // Opcode: LD4i32_POST +/* 37480 */ MCD_OPC_FilterValue, 1, 55, 193, 0, // Skip to: 86948 +/* 37485 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37488 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 37517 +/* 37493 */ MCD_OPC_CheckPredicate, 3, 42, 193, 0, // Skip to: 86948 +/* 37498 */ MCD_OPC_CheckField, 31, 1, 0, 35, 193, 0, // Skip to: 86948 +/* 37505 */ MCD_OPC_CheckField, 12, 1, 0, 28, 193, 0, // Skip to: 86948 +/* 37512 */ MCD_OPC_Decode, 156, 16, 231, 1, // Opcode: LD3i64_POST +/* 37517 */ MCD_OPC_FilterValue, 1, 18, 193, 0, // Skip to: 86948 +/* 37522 */ MCD_OPC_CheckPredicate, 3, 13, 193, 0, // Skip to: 86948 +/* 37527 */ MCD_OPC_CheckField, 31, 1, 0, 6, 193, 0, // Skip to: 86948 +/* 37534 */ MCD_OPC_CheckField, 12, 1, 0, 255, 192, 0, // Skip to: 86948 +/* 37541 */ MCD_OPC_Decode, 202, 16, 232, 1, // Opcode: LD4i64_POST +/* 37546 */ MCD_OPC_FilterValue, 6, 83, 1, 0, // Skip to: 37890 +/* 37551 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 37554 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 37638 +/* 37559 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37562 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37600 +/* 37567 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37570 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37585 +/* 37575 */ MCD_OPC_CheckPredicate, 3, 216, 192, 0, // Skip to: 86948 +/* 37580 */ MCD_OPC_Decode, 136, 15, 163, 1, // Opcode: LD1Rv8b_POST +/* 37585 */ MCD_OPC_FilterValue, 1, 206, 192, 0, // Skip to: 86948 +/* 37590 */ MCD_OPC_CheckPredicate, 3, 201, 192, 0, // Skip to: 86948 +/* 37595 */ MCD_OPC_Decode, 252, 14, 167, 1, // Opcode: LD1Rv16b_POST +/* 37600 */ MCD_OPC_FilterValue, 1, 191, 192, 0, // Skip to: 86948 +/* 37605 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37608 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37623 +/* 37613 */ MCD_OPC_CheckPredicate, 3, 178, 192, 0, // Skip to: 86948 +/* 37618 */ MCD_OPC_Decode, 214, 15, 164, 1, // Opcode: LD2Rv8b_POST +/* 37623 */ MCD_OPC_FilterValue, 1, 168, 192, 0, // Skip to: 86948 +/* 37628 */ MCD_OPC_CheckPredicate, 3, 163, 192, 0, // Skip to: 86948 +/* 37633 */ MCD_OPC_Decode, 202, 15, 168, 1, // Opcode: LD2Rv16b_POST +/* 37638 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 37722 +/* 37643 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37646 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37684 +/* 37651 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37654 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37669 +/* 37659 */ MCD_OPC_CheckPredicate, 3, 132, 192, 0, // Skip to: 86948 +/* 37664 */ MCD_OPC_Decode, 132, 15, 163, 1, // Opcode: LD1Rv4h_POST +/* 37669 */ MCD_OPC_FilterValue, 1, 122, 192, 0, // Skip to: 86948 +/* 37674 */ MCD_OPC_CheckPredicate, 3, 117, 192, 0, // Skip to: 86948 +/* 37679 */ MCD_OPC_Decode, 138, 15, 167, 1, // Opcode: LD1Rv8h_POST +/* 37684 */ MCD_OPC_FilterValue, 1, 107, 192, 0, // Skip to: 86948 +/* 37689 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37692 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37707 +/* 37697 */ MCD_OPC_CheckPredicate, 3, 94, 192, 0, // Skip to: 86948 +/* 37702 */ MCD_OPC_Decode, 210, 15, 164, 1, // Opcode: LD2Rv4h_POST +/* 37707 */ MCD_OPC_FilterValue, 1, 84, 192, 0, // Skip to: 86948 +/* 37712 */ MCD_OPC_CheckPredicate, 3, 79, 192, 0, // Skip to: 86948 +/* 37717 */ MCD_OPC_Decode, 216, 15, 168, 1, // Opcode: LD2Rv8h_POST +/* 37722 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 37806 +/* 37727 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37730 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37768 +/* 37735 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37738 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37753 +/* 37743 */ MCD_OPC_CheckPredicate, 3, 48, 192, 0, // Skip to: 86948 +/* 37748 */ MCD_OPC_Decode, 130, 15, 163, 1, // Opcode: LD1Rv2s_POST +/* 37753 */ MCD_OPC_FilterValue, 1, 38, 192, 0, // Skip to: 86948 +/* 37758 */ MCD_OPC_CheckPredicate, 3, 33, 192, 0, // Skip to: 86948 +/* 37763 */ MCD_OPC_Decode, 134, 15, 167, 1, // Opcode: LD1Rv4s_POST +/* 37768 */ MCD_OPC_FilterValue, 1, 23, 192, 0, // Skip to: 86948 +/* 37773 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37791 +/* 37781 */ MCD_OPC_CheckPredicate, 3, 10, 192, 0, // Skip to: 86948 +/* 37786 */ MCD_OPC_Decode, 208, 15, 164, 1, // Opcode: LD2Rv2s_POST +/* 37791 */ MCD_OPC_FilterValue, 1, 0, 192, 0, // Skip to: 86948 +/* 37796 */ MCD_OPC_CheckPredicate, 3, 251, 191, 0, // Skip to: 86948 +/* 37801 */ MCD_OPC_Decode, 212, 15, 168, 1, // Opcode: LD2Rv4s_POST +/* 37806 */ MCD_OPC_FilterValue, 3, 241, 191, 0, // Skip to: 86948 +/* 37811 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37814 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37852 +/* 37819 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37822 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37837 +/* 37827 */ MCD_OPC_CheckPredicate, 3, 220, 191, 0, // Skip to: 86948 +/* 37832 */ MCD_OPC_Decode, 254, 14, 163, 1, // Opcode: LD1Rv1d_POST +/* 37837 */ MCD_OPC_FilterValue, 1, 210, 191, 0, // Skip to: 86948 +/* 37842 */ MCD_OPC_CheckPredicate, 3, 205, 191, 0, // Skip to: 86948 +/* 37847 */ MCD_OPC_Decode, 128, 15, 167, 1, // Opcode: LD1Rv2d_POST +/* 37852 */ MCD_OPC_FilterValue, 1, 195, 191, 0, // Skip to: 86948 +/* 37857 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37860 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37875 +/* 37865 */ MCD_OPC_CheckPredicate, 3, 182, 191, 0, // Skip to: 86948 +/* 37870 */ MCD_OPC_Decode, 204, 15, 164, 1, // Opcode: LD2Rv1d_POST +/* 37875 */ MCD_OPC_FilterValue, 1, 172, 191, 0, // Skip to: 86948 +/* 37880 */ MCD_OPC_CheckPredicate, 3, 167, 191, 0, // Skip to: 86948 +/* 37885 */ MCD_OPC_Decode, 206, 15, 168, 1, // Opcode: LD2Rv2d_POST +/* 37890 */ MCD_OPC_FilterValue, 7, 157, 191, 0, // Skip to: 86948 +/* 37895 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 37898 */ MCD_OPC_FilterValue, 0, 79, 0, 0, // Skip to: 37982 +/* 37903 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37906 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 37944 +/* 37911 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37929 +/* 37919 */ MCD_OPC_CheckPredicate, 3, 128, 191, 0, // Skip to: 86948 +/* 37924 */ MCD_OPC_Decode, 132, 16, 162, 1, // Opcode: LD3Rv8b_POST +/* 37929 */ MCD_OPC_FilterValue, 1, 118, 191, 0, // Skip to: 86948 +/* 37934 */ MCD_OPC_CheckPredicate, 3, 113, 191, 0, // Skip to: 86948 +/* 37939 */ MCD_OPC_Decode, 248, 15, 166, 1, // Opcode: LD3Rv16b_POST +/* 37944 */ MCD_OPC_FilterValue, 1, 103, 191, 0, // Skip to: 86948 +/* 37949 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37952 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 37967 +/* 37957 */ MCD_OPC_CheckPredicate, 3, 90, 191, 0, // Skip to: 86948 +/* 37962 */ MCD_OPC_Decode, 192, 16, 161, 1, // Opcode: LD4Rv8b_POST +/* 37967 */ MCD_OPC_FilterValue, 1, 80, 191, 0, // Skip to: 86948 +/* 37972 */ MCD_OPC_CheckPredicate, 3, 75, 191, 0, // Skip to: 86948 +/* 37977 */ MCD_OPC_Decode, 180, 16, 165, 1, // Opcode: LD4Rv16b_POST +/* 37982 */ MCD_OPC_FilterValue, 1, 79, 0, 0, // Skip to: 38066 +/* 37987 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 37990 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38028 +/* 37995 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 37998 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38013 +/* 38003 */ MCD_OPC_CheckPredicate, 3, 44, 191, 0, // Skip to: 86948 +/* 38008 */ MCD_OPC_Decode, 128, 16, 162, 1, // Opcode: LD3Rv4h_POST +/* 38013 */ MCD_OPC_FilterValue, 1, 34, 191, 0, // Skip to: 86948 +/* 38018 */ MCD_OPC_CheckPredicate, 3, 29, 191, 0, // Skip to: 86948 +/* 38023 */ MCD_OPC_Decode, 134, 16, 166, 1, // Opcode: LD3Rv8h_POST +/* 38028 */ MCD_OPC_FilterValue, 1, 19, 191, 0, // Skip to: 86948 +/* 38033 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 38036 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38051 +/* 38041 */ MCD_OPC_CheckPredicate, 3, 6, 191, 0, // Skip to: 86948 +/* 38046 */ MCD_OPC_Decode, 188, 16, 161, 1, // Opcode: LD4Rv4h_POST +/* 38051 */ MCD_OPC_FilterValue, 1, 252, 190, 0, // Skip to: 86948 +/* 38056 */ MCD_OPC_CheckPredicate, 3, 247, 190, 0, // Skip to: 86948 +/* 38061 */ MCD_OPC_Decode, 194, 16, 165, 1, // Opcode: LD4Rv8h_POST +/* 38066 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 38150 +/* 38071 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38074 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38112 +/* 38079 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 38082 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38097 +/* 38087 */ MCD_OPC_CheckPredicate, 3, 216, 190, 0, // Skip to: 86948 +/* 38092 */ MCD_OPC_Decode, 254, 15, 162, 1, // Opcode: LD3Rv2s_POST +/* 38097 */ MCD_OPC_FilterValue, 1, 206, 190, 0, // Skip to: 86948 +/* 38102 */ MCD_OPC_CheckPredicate, 3, 201, 190, 0, // Skip to: 86948 +/* 38107 */ MCD_OPC_Decode, 130, 16, 166, 1, // Opcode: LD3Rv4s_POST +/* 38112 */ MCD_OPC_FilterValue, 1, 191, 190, 0, // Skip to: 86948 +/* 38117 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 38120 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38135 +/* 38125 */ MCD_OPC_CheckPredicate, 3, 178, 190, 0, // Skip to: 86948 +/* 38130 */ MCD_OPC_Decode, 186, 16, 161, 1, // Opcode: LD4Rv2s_POST +/* 38135 */ MCD_OPC_FilterValue, 1, 168, 190, 0, // Skip to: 86948 +/* 38140 */ MCD_OPC_CheckPredicate, 3, 163, 190, 0, // Skip to: 86948 +/* 38145 */ MCD_OPC_Decode, 190, 16, 165, 1, // Opcode: LD4Rv4s_POST +/* 38150 */ MCD_OPC_FilterValue, 3, 153, 190, 0, // Skip to: 86948 +/* 38155 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38158 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38196 +/* 38163 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 38166 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38181 +/* 38171 */ MCD_OPC_CheckPredicate, 3, 132, 190, 0, // Skip to: 86948 +/* 38176 */ MCD_OPC_Decode, 250, 15, 162, 1, // Opcode: LD3Rv1d_POST +/* 38181 */ MCD_OPC_FilterValue, 1, 122, 190, 0, // Skip to: 86948 +/* 38186 */ MCD_OPC_CheckPredicate, 3, 117, 190, 0, // Skip to: 86948 +/* 38191 */ MCD_OPC_Decode, 252, 15, 166, 1, // Opcode: LD3Rv2d_POST +/* 38196 */ MCD_OPC_FilterValue, 1, 107, 190, 0, // Skip to: 86948 +/* 38201 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 38204 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38219 +/* 38209 */ MCD_OPC_CheckPredicate, 3, 94, 190, 0, // Skip to: 86948 +/* 38214 */ MCD_OPC_Decode, 182, 16, 161, 1, // Opcode: LD4Rv1d_POST +/* 38219 */ MCD_OPC_FilterValue, 1, 84, 190, 0, // Skip to: 86948 +/* 38224 */ MCD_OPC_CheckPredicate, 3, 79, 190, 0, // Skip to: 86948 +/* 38229 */ MCD_OPC_Decode, 184, 16, 165, 1, // Opcode: LD4Rv2d_POST +/* 38234 */ MCD_OPC_FilterValue, 1, 69, 190, 0, // Skip to: 86948 +/* 38239 */ MCD_OPC_ExtractField, 30, 2, // Inst{31-30} ... +/* 38242 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 38252 +/* 38247 */ MCD_OPC_Decode, 208, 17, 150, 1, // Opcode: LDPSpre +/* 38252 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 38262 +/* 38257 */ MCD_OPC_Decode, 199, 17, 150, 1, // Opcode: LDPDpre +/* 38262 */ MCD_OPC_FilterValue, 2, 41, 190, 0, // Skip to: 86948 +/* 38267 */ MCD_OPC_Decode, 202, 17, 150, 1, // Opcode: LDPQpre +/* 38272 */ MCD_OPC_FilterValue, 8, 6, 27, 0, // Skip to: 45195 +/* 38277 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 38280 */ MCD_OPC_FilterValue, 0, 189, 7, 0, // Skip to: 40266 +/* 38285 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 38288 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 38326 +/* 38293 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38296 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38311 +/* 38301 */ MCD_OPC_CheckPredicate, 3, 2, 190, 0, // Skip to: 86948 +/* 38306 */ MCD_OPC_Decode, 186, 30, 233, 1, // Opcode: TBLv8i8One +/* 38311 */ MCD_OPC_FilterValue, 1, 248, 189, 0, // Skip to: 86948 +/* 38316 */ MCD_OPC_CheckPredicate, 3, 243, 189, 0, // Skip to: 86948 +/* 38321 */ MCD_OPC_Decode, 168, 22, 234, 1, // Opcode: SADDLv8i8_v8i16 +/* 38326 */ MCD_OPC_FilterValue, 1, 86, 0, 0, // Skip to: 38417 +/* 38331 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38334 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 38402 +/* 38339 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 38342 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38387 +/* 38347 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 38350 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38372 +/* 38355 */ MCD_OPC_CheckPredicate, 3, 204, 189, 0, // Skip to: 86948 +/* 38360 */ MCD_OPC_CheckField, 18, 1, 1, 197, 189, 0, // Skip to: 86948 +/* 38367 */ MCD_OPC_Decode, 211, 5, 235, 1, // Opcode: DUPv2i32lane +/* 38372 */ MCD_OPC_FilterValue, 1, 187, 189, 0, // Skip to: 86948 +/* 38377 */ MCD_OPC_CheckPredicate, 3, 182, 189, 0, // Skip to: 86948 +/* 38382 */ MCD_OPC_Decode, 215, 5, 236, 1, // Opcode: DUPv4i16lane +/* 38387 */ MCD_OPC_FilterValue, 1, 172, 189, 0, // Skip to: 86948 +/* 38392 */ MCD_OPC_CheckPredicate, 3, 167, 189, 0, // Skip to: 86948 +/* 38397 */ MCD_OPC_Decode, 221, 5, 237, 1, // Opcode: DUPv8i8lane +/* 38402 */ MCD_OPC_FilterValue, 1, 157, 189, 0, // Skip to: 86948 +/* 38407 */ MCD_OPC_CheckPredicate, 3, 152, 189, 0, // Skip to: 86948 +/* 38412 */ MCD_OPC_Decode, 132, 23, 238, 1, // Opcode: SHADDv8i8 +/* 38417 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 38439 +/* 38422 */ MCD_OPC_CheckPredicate, 3, 137, 189, 0, // Skip to: 86948 +/* 38427 */ MCD_OPC_CheckField, 16, 6, 32, 130, 189, 0, // Skip to: 86948 +/* 38434 */ MCD_OPC_Decode, 214, 21, 239, 1, // Opcode: REV64v8i8 +/* 38439 */ MCD_OPC_FilterValue, 3, 86, 0, 0, // Skip to: 38530 +/* 38444 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38447 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 38515 +/* 38452 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 38455 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38500 +/* 38460 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 38463 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38485 +/* 38468 */ MCD_OPC_CheckPredicate, 3, 91, 189, 0, // Skip to: 86948 +/* 38473 */ MCD_OPC_CheckField, 18, 1, 1, 84, 189, 0, // Skip to: 86948 +/* 38480 */ MCD_OPC_Decode, 210, 5, 240, 1, // Opcode: DUPv2i32gpr +/* 38485 */ MCD_OPC_FilterValue, 1, 74, 189, 0, // Skip to: 86948 +/* 38490 */ MCD_OPC_CheckPredicate, 3, 69, 189, 0, // Skip to: 86948 +/* 38495 */ MCD_OPC_Decode, 214, 5, 240, 1, // Opcode: DUPv4i16gpr +/* 38500 */ MCD_OPC_FilterValue, 1, 59, 189, 0, // Skip to: 86948 +/* 38505 */ MCD_OPC_CheckPredicate, 3, 54, 189, 0, // Skip to: 86948 +/* 38510 */ MCD_OPC_Decode, 220, 5, 240, 1, // Opcode: DUPv8i8gpr +/* 38515 */ MCD_OPC_FilterValue, 1, 44, 189, 0, // Skip to: 86948 +/* 38520 */ MCD_OPC_CheckPredicate, 3, 39, 189, 0, // Skip to: 86948 +/* 38525 */ MCD_OPC_Decode, 182, 24, 238, 1, // Opcode: SQADDv8i8 +/* 38530 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 38568 +/* 38535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38538 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38553 +/* 38543 */ MCD_OPC_CheckPredicate, 3, 16, 189, 0, // Skip to: 86948 +/* 38548 */ MCD_OPC_Decode, 196, 30, 241, 1, // Opcode: TBXv8i8One +/* 38553 */ MCD_OPC_FilterValue, 1, 6, 189, 0, // Skip to: 86948 +/* 38558 */ MCD_OPC_CheckPredicate, 3, 1, 189, 0, // Skip to: 86948 +/* 38563 */ MCD_OPC_Decode, 177, 22, 242, 1, // Opcode: SADDWv8i8_v8i16 +/* 38568 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 38590 +/* 38573 */ MCD_OPC_CheckPredicate, 3, 242, 188, 0, // Skip to: 86948 +/* 38578 */ MCD_OPC_CheckField, 21, 1, 1, 235, 188, 0, // Skip to: 86948 +/* 38585 */ MCD_OPC_Decode, 188, 26, 238, 1, // Opcode: SRHADDv8i8 +/* 38590 */ MCD_OPC_FilterValue, 6, 40, 0, 0, // Skip to: 38635 +/* 38595 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38598 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38613 +/* 38603 */ MCD_OPC_CheckPredicate, 3, 212, 188, 0, // Skip to: 86948 +/* 38608 */ MCD_OPC_Decode, 202, 34, 238, 1, // Opcode: UZP1v8i8 +/* 38613 */ MCD_OPC_FilterValue, 1, 202, 188, 0, // Skip to: 86948 +/* 38618 */ MCD_OPC_CheckPredicate, 3, 197, 188, 0, // Skip to: 86948 +/* 38623 */ MCD_OPC_CheckField, 16, 5, 0, 190, 188, 0, // Skip to: 86948 +/* 38630 */ MCD_OPC_Decode, 203, 21, 239, 1, // Opcode: REV16v8i8 +/* 38635 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 38657 +/* 38640 */ MCD_OPC_CheckPredicate, 3, 175, 188, 0, // Skip to: 86948 +/* 38645 */ MCD_OPC_CheckField, 21, 1, 1, 168, 188, 0, // Skip to: 86948 +/* 38652 */ MCD_OPC_Decode, 253, 1, 238, 1, // Opcode: ANDv8i8 +/* 38657 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 38695 +/* 38662 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38665 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38680 +/* 38670 */ MCD_OPC_CheckPredicate, 3, 145, 188, 0, // Skip to: 86948 +/* 38675 */ MCD_OPC_Decode, 188, 30, 243, 1, // Opcode: TBLv8i8Two +/* 38680 */ MCD_OPC_FilterValue, 1, 135, 188, 0, // Skip to: 86948 +/* 38685 */ MCD_OPC_CheckPredicate, 3, 130, 188, 0, // Skip to: 86948 +/* 38690 */ MCD_OPC_Decode, 166, 27, 234, 1, // Opcode: SSUBLv8i8_v8i16 +/* 38695 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 38717 +/* 38700 */ MCD_OPC_CheckPredicate, 3, 115, 188, 0, // Skip to: 86948 +/* 38705 */ MCD_OPC_CheckField, 21, 1, 1, 108, 188, 0, // Skip to: 86948 +/* 38712 */ MCD_OPC_Decode, 158, 23, 238, 1, // Opcode: SHSUBv8i8 +/* 38717 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 38778 +/* 38722 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38725 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38740 +/* 38730 */ MCD_OPC_CheckPredicate, 3, 85, 188, 0, // Skip to: 86948 +/* 38735 */ MCD_OPC_Decode, 219, 30, 238, 1, // Opcode: TRN1v8i8 +/* 38740 */ MCD_OPC_FilterValue, 1, 75, 188, 0, // Skip to: 86948 +/* 38745 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 38748 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38763 +/* 38753 */ MCD_OPC_CheckPredicate, 3, 62, 188, 0, // Skip to: 86948 +/* 38758 */ MCD_OPC_Decode, 157, 22, 239, 1, // Opcode: SADDLPv8i8_v4i16 +/* 38763 */ MCD_OPC_FilterValue, 1, 52, 188, 0, // Skip to: 86948 +/* 38768 */ MCD_OPC_CheckPredicate, 3, 47, 188, 0, // Skip to: 86948 +/* 38773 */ MCD_OPC_Decode, 132, 35, 244, 1, // Opcode: XTNv8i8 +/* 38778 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 38846 +/* 38783 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38786 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 38831 +/* 38791 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 38794 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 38816 +/* 38799 */ MCD_OPC_CheckPredicate, 3, 16, 188, 0, // Skip to: 86948 +/* 38804 */ MCD_OPC_CheckField, 17, 1, 1, 9, 188, 0, // Skip to: 86948 +/* 38811 */ MCD_OPC_Decode, 128, 24, 245, 1, // Opcode: SMOVvi16to32 +/* 38816 */ MCD_OPC_FilterValue, 1, 255, 187, 0, // Skip to: 86948 +/* 38821 */ MCD_OPC_CheckPredicate, 3, 250, 187, 0, // Skip to: 86948 +/* 38826 */ MCD_OPC_Decode, 131, 24, 246, 1, // Opcode: SMOVvi8to32 +/* 38831 */ MCD_OPC_FilterValue, 1, 240, 187, 0, // Skip to: 86948 +/* 38836 */ MCD_OPC_CheckPredicate, 3, 235, 187, 0, // Skip to: 86948 +/* 38841 */ MCD_OPC_Decode, 164, 26, 238, 1, // Opcode: SQSUBv8i8 +/* 38846 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 38884 +/* 38851 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38854 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38869 +/* 38859 */ MCD_OPC_CheckPredicate, 3, 212, 187, 0, // Skip to: 86948 +/* 38864 */ MCD_OPC_Decode, 198, 30, 247, 1, // Opcode: TBXv8i8Two +/* 38869 */ MCD_OPC_FilterValue, 1, 202, 187, 0, // Skip to: 86948 +/* 38874 */ MCD_OPC_CheckPredicate, 3, 197, 187, 0, // Skip to: 86948 +/* 38879 */ MCD_OPC_Decode, 172, 27, 242, 1, // Opcode: SSUBWv8i8_v8i16 +/* 38884 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 38906 +/* 38889 */ MCD_OPC_CheckPredicate, 3, 182, 187, 0, // Skip to: 86948 +/* 38894 */ MCD_OPC_CheckField, 21, 1, 1, 175, 187, 0, // Skip to: 86948 +/* 38901 */ MCD_OPC_Decode, 228, 3, 238, 1, // Opcode: CMGTv8i8 +/* 38906 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 38967 +/* 38911 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38929 +/* 38919 */ MCD_OPC_CheckPredicate, 3, 152, 187, 0, // Skip to: 86948 +/* 38924 */ MCD_OPC_Decode, 147, 35, 238, 1, // Opcode: ZIP1v8i8 +/* 38929 */ MCD_OPC_FilterValue, 1, 142, 187, 0, // Skip to: 86948 +/* 38934 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 38937 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 38952 +/* 38942 */ MCD_OPC_CheckPredicate, 3, 129, 187, 0, // Skip to: 86948 +/* 38947 */ MCD_OPC_Decode, 151, 30, 248, 1, // Opcode: SUQADDv8i8 +/* 38952 */ MCD_OPC_FilterValue, 16, 119, 187, 0, // Skip to: 86948 +/* 38957 */ MCD_OPC_CheckPredicate, 3, 114, 187, 0, // Skip to: 86948 +/* 38962 */ MCD_OPC_Decode, 162, 22, 249, 1, // Opcode: SADDLVv8i8v +/* 38967 */ MCD_OPC_FilterValue, 15, 86, 0, 0, // Skip to: 39058 +/* 38972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 38975 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 39043 +/* 38980 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 38983 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 39028 +/* 38988 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 38991 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 39013 +/* 38996 */ MCD_OPC_CheckPredicate, 3, 75, 187, 0, // Skip to: 86948 +/* 39001 */ MCD_OPC_CheckField, 18, 1, 1, 68, 187, 0, // Skip to: 86948 +/* 39008 */ MCD_OPC_Decode, 184, 32, 250, 1, // Opcode: UMOVvi32 +/* 39013 */ MCD_OPC_FilterValue, 1, 58, 187, 0, // Skip to: 86948 +/* 39018 */ MCD_OPC_CheckPredicate, 3, 53, 187, 0, // Skip to: 86948 +/* 39023 */ MCD_OPC_Decode, 183, 32, 245, 1, // Opcode: UMOVvi16 +/* 39028 */ MCD_OPC_FilterValue, 1, 43, 187, 0, // Skip to: 86948 +/* 39033 */ MCD_OPC_CheckPredicate, 3, 38, 187, 0, // Skip to: 86948 +/* 39038 */ MCD_OPC_Decode, 186, 32, 246, 1, // Opcode: UMOVvi8 +/* 39043 */ MCD_OPC_FilterValue, 1, 28, 187, 0, // Skip to: 86948 +/* 39048 */ MCD_OPC_CheckPredicate, 3, 23, 187, 0, // Skip to: 86948 +/* 39053 */ MCD_OPC_Decode, 212, 3, 238, 1, // Opcode: CMGEv8i8 +/* 39058 */ MCD_OPC_FilterValue, 16, 33, 0, 0, // Skip to: 39096 +/* 39063 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39066 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39081 +/* 39071 */ MCD_OPC_CheckPredicate, 3, 0, 187, 0, // Skip to: 86948 +/* 39076 */ MCD_OPC_Decode, 187, 30, 251, 1, // Opcode: TBLv8i8Three +/* 39081 */ MCD_OPC_FilterValue, 1, 246, 186, 0, // Skip to: 86948 +/* 39086 */ MCD_OPC_CheckPredicate, 3, 241, 186, 0, // Skip to: 86948 +/* 39091 */ MCD_OPC_Decode, 147, 1, 252, 1, // Opcode: ADDHNv8i16_v8i8 +/* 39096 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 39118 +/* 39101 */ MCD_OPC_CheckPredicate, 3, 226, 186, 0, // Skip to: 86948 +/* 39106 */ MCD_OPC_CheckField, 21, 1, 1, 219, 186, 0, // Skip to: 86948 +/* 39113 */ MCD_OPC_Decode, 234, 26, 238, 1, // Opcode: SSHLv8i8 +/* 39118 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 39156 +/* 39123 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 39126 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39141 +/* 39131 */ MCD_OPC_CheckPredicate, 3, 196, 186, 0, // Skip to: 86948 +/* 39136 */ MCD_OPC_Decode, 169, 3, 239, 1, // Opcode: CLSv8i8 +/* 39141 */ MCD_OPC_FilterValue, 33, 186, 186, 0, // Skip to: 86948 +/* 39146 */ MCD_OPC_CheckPredicate, 3, 181, 186, 0, // Skip to: 86948 +/* 39151 */ MCD_OPC_Decode, 173, 26, 244, 1, // Opcode: SQXTNv8i8 +/* 39156 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 39178 +/* 39161 */ MCD_OPC_CheckPredicate, 3, 166, 186, 0, // Skip to: 86948 +/* 39166 */ MCD_OPC_CheckField, 21, 1, 1, 159, 186, 0, // Skip to: 86948 +/* 39173 */ MCD_OPC_Decode, 254, 25, 238, 1, // Opcode: SQSHLv8i8 +/* 39178 */ MCD_OPC_FilterValue, 20, 33, 0, 0, // Skip to: 39216 +/* 39183 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39186 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39201 +/* 39191 */ MCD_OPC_CheckPredicate, 3, 136, 186, 0, // Skip to: 86948 +/* 39196 */ MCD_OPC_Decode, 197, 30, 253, 1, // Opcode: TBXv8i8Three +/* 39201 */ MCD_OPC_FilterValue, 1, 126, 186, 0, // Skip to: 86948 +/* 39206 */ MCD_OPC_CheckPredicate, 3, 121, 186, 0, // Skip to: 86948 +/* 39211 */ MCD_OPC_Decode, 251, 21, 254, 1, // Opcode: SABALv8i8_v8i16 +/* 39216 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 39238 +/* 39221 */ MCD_OPC_CheckPredicate, 3, 106, 186, 0, // Skip to: 86948 +/* 39226 */ MCD_OPC_CheckField, 21, 1, 1, 99, 186, 0, // Skip to: 86948 +/* 39233 */ MCD_OPC_Decode, 204, 26, 238, 1, // Opcode: SRSHLv8i8 +/* 39238 */ MCD_OPC_FilterValue, 22, 40, 0, 0, // Skip to: 39283 +/* 39243 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39246 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39261 +/* 39251 */ MCD_OPC_CheckPredicate, 3, 76, 186, 0, // Skip to: 86948 +/* 39256 */ MCD_OPC_Decode, 217, 34, 238, 1, // Opcode: UZP2v8i8 +/* 39261 */ MCD_OPC_FilterValue, 1, 66, 186, 0, // Skip to: 86948 +/* 39266 */ MCD_OPC_CheckPredicate, 3, 61, 186, 0, // Skip to: 86948 +/* 39271 */ MCD_OPC_CheckField, 16, 5, 0, 54, 186, 0, // Skip to: 86948 +/* 39278 */ MCD_OPC_Decode, 130, 5, 239, 1, // Opcode: CNTv8i8 +/* 39283 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 39305 +/* 39288 */ MCD_OPC_CheckPredicate, 3, 39, 186, 0, // Skip to: 86948 +/* 39293 */ MCD_OPC_CheckField, 21, 1, 1, 32, 186, 0, // Skip to: 86948 +/* 39300 */ MCD_OPC_Decode, 204, 25, 238, 1, // Opcode: SQRSHLv8i8 +/* 39305 */ MCD_OPC_FilterValue, 24, 33, 0, 0, // Skip to: 39343 +/* 39310 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39328 +/* 39318 */ MCD_OPC_CheckPredicate, 3, 9, 186, 0, // Skip to: 86948 +/* 39323 */ MCD_OPC_Decode, 185, 30, 255, 1, // Opcode: TBLv8i8Four +/* 39328 */ MCD_OPC_FilterValue, 1, 255, 185, 0, // Skip to: 86948 +/* 39333 */ MCD_OPC_CheckPredicate, 3, 250, 185, 0, // Skip to: 86948 +/* 39338 */ MCD_OPC_Decode, 216, 29, 252, 1, // Opcode: SUBHNv8i16_v8i8 +/* 39343 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 39365 +/* 39348 */ MCD_OPC_CheckPredicate, 3, 235, 185, 0, // Skip to: 86948 +/* 39353 */ MCD_OPC_CheckField, 21, 1, 1, 228, 185, 0, // Skip to: 86948 +/* 39360 */ MCD_OPC_Decode, 205, 23, 238, 1, // Opcode: SMAXv8i8 +/* 39365 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 39426 +/* 39370 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39373 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39388 +/* 39378 */ MCD_OPC_CheckPredicate, 3, 205, 185, 0, // Skip to: 86948 +/* 39383 */ MCD_OPC_Decode, 234, 30, 238, 1, // Opcode: TRN2v8i8 +/* 39388 */ MCD_OPC_FilterValue, 1, 195, 185, 0, // Skip to: 86948 +/* 39393 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 39396 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39411 +/* 39401 */ MCD_OPC_CheckPredicate, 3, 182, 185, 0, // Skip to: 86948 +/* 39406 */ MCD_OPC_Decode, 151, 22, 248, 1, // Opcode: SADALPv8i8_v4i16 +/* 39411 */ MCD_OPC_FilterValue, 1, 172, 185, 0, // Skip to: 86948 +/* 39416 */ MCD_OPC_CheckPredicate, 3, 167, 185, 0, // Skip to: 86948 +/* 39421 */ MCD_OPC_Decode, 182, 8, 244, 1, // Opcode: FCVTNv4i16 +/* 39426 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 39448 +/* 39431 */ MCD_OPC_CheckPredicate, 3, 152, 185, 0, // Skip to: 86948 +/* 39436 */ MCD_OPC_CheckField, 21, 1, 1, 145, 185, 0, // Skip to: 86948 +/* 39443 */ MCD_OPC_Decode, 235, 23, 238, 1, // Opcode: SMINv8i8 +/* 39448 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 39486 +/* 39453 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39456 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39471 +/* 39461 */ MCD_OPC_CheckPredicate, 3, 122, 185, 0, // Skip to: 86948 +/* 39466 */ MCD_OPC_Decode, 195, 30, 128, 2, // Opcode: TBXv8i8Four +/* 39471 */ MCD_OPC_FilterValue, 1, 112, 185, 0, // Skip to: 86948 +/* 39476 */ MCD_OPC_CheckPredicate, 3, 107, 185, 0, // Skip to: 86948 +/* 39481 */ MCD_OPC_Decode, 135, 22, 234, 1, // Opcode: SABDLv8i8_v8i16 +/* 39486 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 39508 +/* 39491 */ MCD_OPC_CheckPredicate, 3, 92, 185, 0, // Skip to: 86948 +/* 39496 */ MCD_OPC_CheckField, 21, 1, 1, 85, 185, 0, // Skip to: 86948 +/* 39503 */ MCD_OPC_Decode, 145, 22, 238, 1, // Opcode: SABDv8i8 +/* 39508 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 39569 +/* 39513 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 39516 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39531 +/* 39521 */ MCD_OPC_CheckPredicate, 3, 62, 185, 0, // Skip to: 86948 +/* 39526 */ MCD_OPC_Decode, 162, 35, 238, 1, // Opcode: ZIP2v8i8 +/* 39531 */ MCD_OPC_FilterValue, 1, 52, 185, 0, // Skip to: 86948 +/* 39536 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 39539 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 39554 +/* 39544 */ MCD_OPC_CheckPredicate, 3, 39, 185, 0, // Skip to: 86948 +/* 39549 */ MCD_OPC_Decode, 163, 24, 239, 1, // Opcode: SQABSv8i8 +/* 39554 */ MCD_OPC_FilterValue, 1, 29, 185, 0, // Skip to: 86948 +/* 39559 */ MCD_OPC_CheckPredicate, 3, 24, 185, 0, // Skip to: 86948 +/* 39564 */ MCD_OPC_Decode, 250, 7, 129, 2, // Opcode: FCVTLv4i16 +/* 39569 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 39591 +/* 39574 */ MCD_OPC_CheckPredicate, 3, 9, 185, 0, // Skip to: 86948 +/* 39579 */ MCD_OPC_CheckField, 21, 1, 1, 2, 185, 0, // Skip to: 86948 +/* 39586 */ MCD_OPC_Decode, 129, 22, 130, 2, // Opcode: SABAv8i8 +/* 39591 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 39613 +/* 39596 */ MCD_OPC_CheckPredicate, 3, 243, 184, 0, // Skip to: 86948 +/* 39601 */ MCD_OPC_CheckField, 21, 1, 1, 236, 184, 0, // Skip to: 86948 +/* 39608 */ MCD_OPC_Decode, 245, 23, 254, 1, // Opcode: SMLALv8i8_v8i16 +/* 39613 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 39635 +/* 39618 */ MCD_OPC_CheckPredicate, 3, 221, 184, 0, // Skip to: 86948 +/* 39623 */ MCD_OPC_CheckField, 21, 1, 1, 214, 184, 0, // Skip to: 86948 +/* 39630 */ MCD_OPC_Decode, 201, 1, 238, 1, // Opcode: ADDv8i8 +/* 39635 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 39673 +/* 39640 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 39643 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39658 +/* 39648 */ MCD_OPC_CheckPredicate, 3, 191, 184, 0, // Skip to: 86948 +/* 39653 */ MCD_OPC_Decode, 229, 3, 239, 1, // Opcode: CMGTv8i8rz +/* 39658 */ MCD_OPC_FilterValue, 33, 181, 184, 0, // Skip to: 86948 +/* 39663 */ MCD_OPC_CheckPredicate, 3, 176, 184, 0, // Skip to: 86948 +/* 39668 */ MCD_OPC_Decode, 135, 12, 239, 1, // Opcode: FRINTNv2f32 +/* 39673 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 39695 +/* 39678 */ MCD_OPC_CheckPredicate, 3, 161, 184, 0, // Skip to: 86948 +/* 39683 */ MCD_OPC_CheckField, 21, 1, 1, 154, 184, 0, // Skip to: 86948 +/* 39690 */ MCD_OPC_Decode, 240, 4, 238, 1, // Opcode: CMTSTv8i8 +/* 39695 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 39717 +/* 39700 */ MCD_OPC_CheckPredicate, 3, 139, 184, 0, // Skip to: 86948 +/* 39705 */ MCD_OPC_CheckField, 21, 1, 1, 132, 184, 0, // Skip to: 86948 +/* 39712 */ MCD_OPC_Decode, 218, 19, 130, 2, // Opcode: MLAv8i8 +/* 39717 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 39755 +/* 39722 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 39725 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39740 +/* 39730 */ MCD_OPC_CheckPredicate, 3, 109, 184, 0, // Skip to: 86948 +/* 39735 */ MCD_OPC_Decode, 197, 3, 239, 1, // Opcode: CMEQv8i8rz +/* 39740 */ MCD_OPC_FilterValue, 33, 99, 184, 0, // Skip to: 86948 +/* 39745 */ MCD_OPC_CheckPredicate, 3, 94, 184, 0, // Skip to: 86948 +/* 39750 */ MCD_OPC_Decode, 252, 11, 239, 1, // Opcode: FRINTMv2f32 +/* 39755 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 39777 +/* 39760 */ MCD_OPC_CheckPredicate, 3, 79, 184, 0, // Skip to: 86948 +/* 39765 */ MCD_OPC_CheckField, 21, 1, 1, 72, 184, 0, // Skip to: 86948 +/* 39772 */ MCD_OPC_Decode, 166, 20, 238, 1, // Opcode: MULv8i8 +/* 39777 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 39799 +/* 39782 */ MCD_OPC_CheckPredicate, 3, 57, 184, 0, // Skip to: 86948 +/* 39787 */ MCD_OPC_CheckField, 21, 1, 1, 50, 184, 0, // Skip to: 86948 +/* 39794 */ MCD_OPC_Decode, 255, 23, 254, 1, // Opcode: SMLSLv8i8_v8i16 +/* 39799 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 39821 +/* 39804 */ MCD_OPC_CheckPredicate, 3, 35, 184, 0, // Skip to: 86948 +/* 39809 */ MCD_OPC_CheckField, 21, 1, 1, 28, 184, 0, // Skip to: 86948 +/* 39816 */ MCD_OPC_Decode, 182, 23, 238, 1, // Opcode: SMAXPv8i8 +/* 39821 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 39889 +/* 39826 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 39829 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39844 +/* 39834 */ MCD_OPC_CheckPredicate, 3, 5, 184, 0, // Skip to: 86948 +/* 39839 */ MCD_OPC_Decode, 133, 4, 239, 1, // Opcode: CMLTv8i8rz +/* 39844 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 39859 +/* 39849 */ MCD_OPC_CheckPredicate, 3, 246, 183, 0, // Skip to: 86948 +/* 39854 */ MCD_OPC_Decode, 162, 8, 239, 1, // Opcode: FCVTNSv2f32 +/* 39859 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 39874 +/* 39864 */ MCD_OPC_CheckPredicate, 3, 231, 183, 0, // Skip to: 86948 +/* 39869 */ MCD_OPC_Decode, 191, 23, 131, 2, // Opcode: SMAXVv8i8v +/* 39874 */ MCD_OPC_FilterValue, 49, 221, 183, 0, // Skip to: 86948 +/* 39879 */ MCD_OPC_CheckPredicate, 3, 216, 183, 0, // Skip to: 86948 +/* 39884 */ MCD_OPC_Decode, 221, 23, 131, 2, // Opcode: SMINVv8i8v +/* 39889 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 39911 +/* 39894 */ MCD_OPC_CheckPredicate, 3, 201, 183, 0, // Skip to: 86948 +/* 39899 */ MCD_OPC_CheckField, 21, 1, 1, 194, 183, 0, // Skip to: 86948 +/* 39906 */ MCD_OPC_Decode, 212, 23, 238, 1, // Opcode: SMINPv8i8 +/* 39911 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 39964 +/* 39916 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 39919 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 39934 +/* 39924 */ MCD_OPC_CheckPredicate, 3, 171, 183, 0, // Skip to: 86948 +/* 39929 */ MCD_OPC_Decode, 137, 1, 239, 1, // Opcode: ABSv8i8 +/* 39934 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 39949 +/* 39939 */ MCD_OPC_CheckPredicate, 3, 156, 183, 0, // Skip to: 86948 +/* 39944 */ MCD_OPC_Decode, 134, 8, 239, 1, // Opcode: FCVTMSv2f32 +/* 39949 */ MCD_OPC_FilterValue, 49, 146, 183, 0, // Skip to: 86948 +/* 39954 */ MCD_OPC_CheckPredicate, 3, 141, 183, 0, // Skip to: 86948 +/* 39959 */ MCD_OPC_Decode, 171, 1, 131, 2, // Opcode: ADDVv8i8v +/* 39964 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 39986 +/* 39969 */ MCD_OPC_CheckPredicate, 3, 126, 183, 0, // Skip to: 86948 +/* 39974 */ MCD_OPC_CheckField, 21, 1, 1, 119, 183, 0, // Skip to: 86948 +/* 39981 */ MCD_OPC_Decode, 156, 1, 238, 1, // Opcode: ADDPv8i8 +/* 39986 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 40008 +/* 39991 */ MCD_OPC_CheckPredicate, 3, 104, 183, 0, // Skip to: 86948 +/* 39996 */ MCD_OPC_CheckField, 21, 1, 1, 97, 183, 0, // Skip to: 86948 +/* 40003 */ MCD_OPC_Decode, 148, 24, 234, 1, // Opcode: SMULLv8i8_v8i16 +/* 40008 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 40030 +/* 40013 */ MCD_OPC_CheckPredicate, 3, 82, 183, 0, // Skip to: 86948 +/* 40018 */ MCD_OPC_CheckField, 21, 1, 1, 75, 183, 0, // Skip to: 86948 +/* 40025 */ MCD_OPC_Decode, 218, 9, 238, 1, // Opcode: FMAXNMv2f32 +/* 40030 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 40068 +/* 40035 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 40038 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 40053 +/* 40043 */ MCD_OPC_CheckPredicate, 3, 52, 183, 0, // Skip to: 86948 +/* 40048 */ MCD_OPC_Decode, 226, 7, 239, 1, // Opcode: FCVTASv2f32 +/* 40053 */ MCD_OPC_FilterValue, 48, 42, 183, 0, // Skip to: 86948 +/* 40058 */ MCD_OPC_CheckPredicate, 4, 37, 183, 0, // Skip to: 86948 +/* 40063 */ MCD_OPC_Decode, 209, 9, 249, 1, // Opcode: FMAXNMVv4i16v +/* 40068 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 40090 +/* 40073 */ MCD_OPC_CheckPredicate, 3, 22, 183, 0, // Skip to: 86948 +/* 40078 */ MCD_OPC_CheckField, 21, 1, 1, 15, 183, 0, // Skip to: 86948 +/* 40085 */ MCD_OPC_Decode, 186, 10, 130, 2, // Opcode: FMLAv2f32 +/* 40090 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 40112 +/* 40095 */ MCD_OPC_CheckPredicate, 3, 0, 183, 0, // Skip to: 86948 +/* 40100 */ MCD_OPC_CheckField, 21, 1, 1, 249, 182, 0, // Skip to: 86948 +/* 40107 */ MCD_OPC_Decode, 198, 6, 238, 1, // Opcode: FADDv2f32 +/* 40112 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 40134 +/* 40117 */ MCD_OPC_CheckPredicate, 3, 234, 182, 0, // Skip to: 86948 +/* 40122 */ MCD_OPC_CheckField, 16, 6, 33, 227, 182, 0, // Skip to: 86948 +/* 40129 */ MCD_OPC_Decode, 209, 22, 239, 1, // Opcode: SCVTFv2f32 +/* 40134 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 40156 +/* 40139 */ MCD_OPC_CheckPredicate, 3, 212, 182, 0, // Skip to: 86948 +/* 40144 */ MCD_OPC_CheckField, 21, 1, 1, 205, 182, 0, // Skip to: 86948 +/* 40151 */ MCD_OPC_Decode, 129, 11, 238, 1, // Opcode: FMULXv2f32 +/* 40156 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 40178 +/* 40161 */ MCD_OPC_CheckPredicate, 3, 190, 182, 0, // Skip to: 86948 +/* 40166 */ MCD_OPC_CheckField, 21, 1, 1, 183, 182, 0, // Skip to: 86948 +/* 40173 */ MCD_OPC_Decode, 246, 20, 234, 1, // Opcode: PMULLv8i8 +/* 40178 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 40200 +/* 40183 */ MCD_OPC_CheckPredicate, 3, 168, 182, 0, // Skip to: 86948 +/* 40188 */ MCD_OPC_CheckField, 21, 1, 1, 161, 182, 0, // Skip to: 86948 +/* 40195 */ MCD_OPC_Decode, 229, 6, 238, 1, // Opcode: FCMEQv2f32 +/* 40200 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 40222 +/* 40205 */ MCD_OPC_CheckPredicate, 3, 146, 182, 0, // Skip to: 86948 +/* 40210 */ MCD_OPC_CheckField, 21, 1, 1, 139, 182, 0, // Skip to: 86948 +/* 40217 */ MCD_OPC_Decode, 244, 9, 238, 1, // Opcode: FMAXv2f32 +/* 40222 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 40244 +/* 40227 */ MCD_OPC_CheckPredicate, 4, 124, 182, 0, // Skip to: 86948 +/* 40232 */ MCD_OPC_CheckField, 16, 6, 48, 117, 182, 0, // Skip to: 86948 +/* 40239 */ MCD_OPC_Decode, 235, 9, 249, 1, // Opcode: FMAXVv4i16v +/* 40244 */ MCD_OPC_FilterValue, 63, 107, 182, 0, // Skip to: 86948 +/* 40249 */ MCD_OPC_CheckPredicate, 3, 102, 182, 0, // Skip to: 86948 +/* 40254 */ MCD_OPC_CheckField, 21, 1, 1, 95, 182, 0, // Skip to: 86948 +/* 40261 */ MCD_OPC_Decode, 213, 11, 238, 1, // Opcode: FRECPSv2f32 +/* 40266 */ MCD_OPC_FilterValue, 1, 74, 5, 0, // Skip to: 41625 +/* 40271 */ MCD_OPC_ExtractField, 14, 2, // Inst{15-14} ... +/* 40274 */ MCD_OPC_FilterValue, 0, 135, 1, 0, // Skip to: 40670 +/* 40279 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 40282 */ MCD_OPC_FilterValue, 0, 199, 0, 0, // Skip to: 40486 +/* 40287 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 40290 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40305 +/* 40295 */ MCD_OPC_CheckPredicate, 3, 56, 182, 0, // Skip to: 86948 +/* 40300 */ MCD_OPC_Decode, 254, 5, 132, 2, // Opcode: EXTv8i8 +/* 40305 */ MCD_OPC_FilterValue, 1, 46, 182, 0, // Skip to: 86948 +/* 40310 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 40313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40328 +/* 40318 */ MCD_OPC_CheckPredicate, 3, 33, 182, 0, // Skip to: 86948 +/* 40323 */ MCD_OPC_Decode, 158, 31, 234, 1, // Opcode: UADDLv8i8_v8i16 +/* 40328 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40350 +/* 40333 */ MCD_OPC_CheckPredicate, 3, 18, 182, 0, // Skip to: 86948 +/* 40338 */ MCD_OPC_CheckField, 16, 5, 0, 11, 182, 0, // Skip to: 86948 +/* 40345 */ MCD_OPC_Decode, 208, 21, 239, 1, // Opcode: REV32v8i8 +/* 40350 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 40365 +/* 40355 */ MCD_OPC_CheckPredicate, 3, 252, 181, 0, // Skip to: 86948 +/* 40360 */ MCD_OPC_Decode, 168, 31, 242, 1, // Opcode: UADDWv8i8_v8i16 +/* 40365 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 40380 +/* 40370 */ MCD_OPC_CheckPredicate, 3, 237, 181, 0, // Skip to: 86948 +/* 40375 */ MCD_OPC_Decode, 169, 34, 234, 1, // Opcode: USUBLv8i8_v8i16 +/* 40380 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 40418 +/* 40385 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 40388 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40403 +/* 40393 */ MCD_OPC_CheckPredicate, 3, 214, 181, 0, // Skip to: 86948 +/* 40398 */ MCD_OPC_Decode, 147, 31, 239, 1, // Opcode: UADDLPv8i8_v4i16 +/* 40403 */ MCD_OPC_FilterValue, 1, 204, 181, 0, // Skip to: 86948 +/* 40408 */ MCD_OPC_CheckPredicate, 3, 199, 181, 0, // Skip to: 86948 +/* 40413 */ MCD_OPC_Decode, 182, 26, 244, 1, // Opcode: SQXTUNv8i8 +/* 40418 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 40433 +/* 40423 */ MCD_OPC_CheckPredicate, 3, 184, 181, 0, // Skip to: 86948 +/* 40428 */ MCD_OPC_Decode, 175, 34, 242, 1, // Opcode: USUBWv8i8_v8i16 +/* 40433 */ MCD_OPC_FilterValue, 7, 174, 181, 0, // Skip to: 86948 +/* 40438 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 40441 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 40456 +/* 40446 */ MCD_OPC_CheckPredicate, 3, 161, 181, 0, // Skip to: 86948 +/* 40451 */ MCD_OPC_Decode, 155, 34, 248, 1, // Opcode: USQADDv8i8 +/* 40456 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 40471 +/* 40461 */ MCD_OPC_CheckPredicate, 3, 146, 181, 0, // Skip to: 86948 +/* 40466 */ MCD_OPC_Decode, 138, 23, 129, 2, // Opcode: SHLLv8i8 +/* 40471 */ MCD_OPC_FilterValue, 16, 136, 181, 0, // Skip to: 86948 +/* 40476 */ MCD_OPC_CheckPredicate, 3, 131, 181, 0, // Skip to: 86948 +/* 40481 */ MCD_OPC_Decode, 152, 31, 249, 1, // Opcode: UADDLVv8i8v +/* 40486 */ MCD_OPC_FilterValue, 1, 121, 181, 0, // Skip to: 86948 +/* 40491 */ MCD_OPC_ExtractField, 11, 3, // Inst{13-11} ... +/* 40494 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 40516 +/* 40499 */ MCD_OPC_CheckPredicate, 3, 108, 181, 0, // Skip to: 86948 +/* 40504 */ MCD_OPC_CheckField, 21, 1, 1, 101, 181, 0, // Skip to: 86948 +/* 40511 */ MCD_OPC_Decode, 225, 31, 238, 1, // Opcode: UHADDv8i8 +/* 40516 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40538 +/* 40521 */ MCD_OPC_CheckPredicate, 3, 86, 181, 0, // Skip to: 86948 +/* 40526 */ MCD_OPC_CheckField, 21, 1, 1, 79, 181, 0, // Skip to: 86948 +/* 40533 */ MCD_OPC_Decode, 221, 32, 238, 1, // Opcode: UQADDv8i8 +/* 40538 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 40560 +/* 40543 */ MCD_OPC_CheckPredicate, 3, 64, 181, 0, // Skip to: 86948 +/* 40548 */ MCD_OPC_CheckField, 21, 1, 1, 57, 181, 0, // Skip to: 86948 +/* 40555 */ MCD_OPC_Decode, 224, 33, 238, 1, // Opcode: URHADDv8i8 +/* 40560 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 40582 +/* 40565 */ MCD_OPC_CheckPredicate, 3, 42, 181, 0, // Skip to: 86948 +/* 40570 */ MCD_OPC_CheckField, 21, 1, 1, 35, 181, 0, // Skip to: 86948 +/* 40577 */ MCD_OPC_Decode, 246, 5, 238, 1, // Opcode: EORv8i8 +/* 40582 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 40604 +/* 40587 */ MCD_OPC_CheckPredicate, 3, 20, 181, 0, // Skip to: 86948 +/* 40592 */ MCD_OPC_CheckField, 21, 1, 1, 13, 181, 0, // Skip to: 86948 +/* 40599 */ MCD_OPC_Decode, 231, 31, 238, 1, // Opcode: UHSUBv8i8 +/* 40604 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 40626 +/* 40609 */ MCD_OPC_CheckPredicate, 3, 254, 180, 0, // Skip to: 86948 +/* 40614 */ MCD_OPC_CheckField, 21, 1, 1, 247, 180, 0, // Skip to: 86948 +/* 40621 */ MCD_OPC_Decode, 207, 33, 238, 1, // Opcode: UQSUBv8i8 +/* 40626 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 40648 +/* 40631 */ MCD_OPC_CheckPredicate, 3, 232, 180, 0, // Skip to: 86948 +/* 40636 */ MCD_OPC_CheckField, 21, 1, 1, 225, 180, 0, // Skip to: 86948 +/* 40643 */ MCD_OPC_Decode, 237, 3, 238, 1, // Opcode: CMHIv8i8 +/* 40648 */ MCD_OPC_FilterValue, 7, 215, 180, 0, // Skip to: 86948 +/* 40653 */ MCD_OPC_CheckPredicate, 3, 210, 180, 0, // Skip to: 86948 +/* 40658 */ MCD_OPC_CheckField, 21, 1, 1, 203, 180, 0, // Skip to: 86948 +/* 40665 */ MCD_OPC_Decode, 245, 3, 238, 1, // Opcode: CMHSv8i8 +/* 40670 */ MCD_OPC_FilterValue, 1, 115, 1, 0, // Skip to: 41046 +/* 40675 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 40678 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 40700 +/* 40683 */ MCD_OPC_CheckPredicate, 3, 180, 180, 0, // Skip to: 86948 +/* 40688 */ MCD_OPC_CheckField, 21, 1, 1, 173, 180, 0, // Skip to: 86948 +/* 40695 */ MCD_OPC_Decode, 182, 21, 252, 1, // Opcode: RADDHNv8i16_v8i8 +/* 40700 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 40722 +/* 40705 */ MCD_OPC_CheckPredicate, 3, 158, 180, 0, // Skip to: 86948 +/* 40710 */ MCD_OPC_CheckField, 21, 1, 1, 151, 180, 0, // Skip to: 86948 +/* 40717 */ MCD_OPC_Decode, 136, 34, 238, 1, // Opcode: USHLv8i8 +/* 40722 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 40760 +/* 40727 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 40730 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 40745 +/* 40735 */ MCD_OPC_CheckPredicate, 3, 128, 180, 0, // Skip to: 86948 +/* 40740 */ MCD_OPC_Decode, 181, 3, 239, 1, // Opcode: CLZv8i8 +/* 40745 */ MCD_OPC_FilterValue, 33, 118, 180, 0, // Skip to: 86948 +/* 40750 */ MCD_OPC_CheckPredicate, 3, 113, 180, 0, // Skip to: 86948 +/* 40755 */ MCD_OPC_Decode, 216, 33, 244, 1, // Opcode: UQXTNv8i8 +/* 40760 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 40782 +/* 40765 */ MCD_OPC_CheckPredicate, 3, 98, 180, 0, // Skip to: 86948 +/* 40770 */ MCD_OPC_CheckField, 21, 1, 1, 91, 180, 0, // Skip to: 86948 +/* 40777 */ MCD_OPC_Decode, 178, 33, 238, 1, // Opcode: UQSHLv8i8 +/* 40782 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 40804 +/* 40787 */ MCD_OPC_CheckPredicate, 3, 76, 180, 0, // Skip to: 86948 +/* 40792 */ MCD_OPC_CheckField, 21, 1, 1, 69, 180, 0, // Skip to: 86948 +/* 40799 */ MCD_OPC_Decode, 241, 30, 254, 1, // Opcode: UABALv8i8_v8i16 +/* 40804 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 40826 +/* 40809 */ MCD_OPC_CheckPredicate, 3, 54, 180, 0, // Skip to: 86948 +/* 40814 */ MCD_OPC_CheckField, 21, 1, 1, 47, 180, 0, // Skip to: 86948 +/* 40821 */ MCD_OPC_Decode, 232, 33, 238, 1, // Opcode: URSHLv8i8 +/* 40826 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 40848 +/* 40831 */ MCD_OPC_CheckPredicate, 3, 32, 180, 0, // Skip to: 86948 +/* 40836 */ MCD_OPC_CheckField, 16, 6, 32, 25, 180, 0, // Skip to: 86948 +/* 40843 */ MCD_OPC_Decode, 194, 20, 239, 1, // Opcode: NOTv8i8 +/* 40848 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 40870 +/* 40853 */ MCD_OPC_CheckPredicate, 3, 10, 180, 0, // Skip to: 86948 +/* 40858 */ MCD_OPC_CheckField, 21, 1, 1, 3, 180, 0, // Skip to: 86948 +/* 40865 */ MCD_OPC_Decode, 148, 33, 238, 1, // Opcode: UQRSHLv8i8 +/* 40870 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 40892 +/* 40875 */ MCD_OPC_CheckPredicate, 3, 244, 179, 0, // Skip to: 86948 +/* 40880 */ MCD_OPC_CheckField, 21, 1, 1, 237, 179, 0, // Skip to: 86948 +/* 40887 */ MCD_OPC_Decode, 245, 21, 252, 1, // Opcode: RSUBHNv8i16_v8i8 +/* 40892 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 40914 +/* 40897 */ MCD_OPC_CheckPredicate, 3, 222, 179, 0, // Skip to: 86948 +/* 40902 */ MCD_OPC_CheckField, 21, 1, 1, 215, 179, 0, // Skip to: 86948 +/* 40909 */ MCD_OPC_Decode, 133, 32, 238, 1, // Opcode: UMAXv8i8 +/* 40914 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 40936 +/* 40919 */ MCD_OPC_CheckPredicate, 3, 200, 179, 0, // Skip to: 86948 +/* 40924 */ MCD_OPC_CheckField, 16, 6, 32, 193, 179, 0, // Skip to: 86948 +/* 40931 */ MCD_OPC_Decode, 141, 31, 248, 1, // Opcode: UADALPv8i8_v4i16 +/* 40936 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 40958 +/* 40941 */ MCD_OPC_CheckPredicate, 3, 178, 179, 0, // Skip to: 86948 +/* 40946 */ MCD_OPC_CheckField, 21, 1, 1, 171, 179, 0, // Skip to: 86948 +/* 40953 */ MCD_OPC_Decode, 162, 32, 238, 1, // Opcode: UMINv8i8 +/* 40958 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 40980 +/* 40963 */ MCD_OPC_CheckPredicate, 3, 156, 179, 0, // Skip to: 86948 +/* 40968 */ MCD_OPC_CheckField, 21, 1, 1, 149, 179, 0, // Skip to: 86948 +/* 40975 */ MCD_OPC_Decode, 253, 30, 234, 1, // Opcode: UABDLv8i8_v8i16 +/* 40980 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 41002 +/* 40985 */ MCD_OPC_CheckPredicate, 3, 134, 179, 0, // Skip to: 86948 +/* 40990 */ MCD_OPC_CheckField, 21, 1, 1, 127, 179, 0, // Skip to: 86948 +/* 40997 */ MCD_OPC_Decode, 135, 31, 238, 1, // Opcode: UABDv8i8 +/* 41002 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 41024 +/* 41007 */ MCD_OPC_CheckPredicate, 3, 112, 179, 0, // Skip to: 86948 +/* 41012 */ MCD_OPC_CheckField, 16, 6, 32, 105, 179, 0, // Skip to: 86948 +/* 41019 */ MCD_OPC_Decode, 157, 25, 239, 1, // Opcode: SQNEGv8i8 +/* 41024 */ MCD_OPC_FilterValue, 15, 95, 179, 0, // Skip to: 86948 +/* 41029 */ MCD_OPC_CheckPredicate, 3, 90, 179, 0, // Skip to: 86948 +/* 41034 */ MCD_OPC_CheckField, 21, 1, 1, 83, 179, 0, // Skip to: 86948 +/* 41041 */ MCD_OPC_Decode, 247, 30, 130, 2, // Opcode: UABAv8i8 +/* 41046 */ MCD_OPC_FilterValue, 2, 90, 1, 0, // Skip to: 41397 +/* 41051 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 41054 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41076 +/* 41059 */ MCD_OPC_CheckPredicate, 3, 60, 179, 0, // Skip to: 86948 +/* 41064 */ MCD_OPC_CheckField, 21, 1, 1, 53, 179, 0, // Skip to: 86948 +/* 41071 */ MCD_OPC_Decode, 172, 32, 254, 1, // Opcode: UMLALv8i8_v8i16 +/* 41076 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 41098 +/* 41081 */ MCD_OPC_CheckPredicate, 3, 38, 179, 0, // Skip to: 86948 +/* 41086 */ MCD_OPC_CheckField, 21, 1, 1, 31, 179, 0, // Skip to: 86948 +/* 41093 */ MCD_OPC_Decode, 134, 30, 238, 1, // Opcode: SUBv8i8 +/* 41098 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 41136 +/* 41103 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 41106 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41121 +/* 41111 */ MCD_OPC_CheckPredicate, 3, 8, 179, 0, // Skip to: 86948 +/* 41116 */ MCD_OPC_Decode, 213, 3, 239, 1, // Opcode: CMGEv8i8rz +/* 41121 */ MCD_OPC_FilterValue, 33, 254, 178, 0, // Skip to: 86948 +/* 41126 */ MCD_OPC_CheckPredicate, 3, 249, 178, 0, // Skip to: 86948 +/* 41131 */ MCD_OPC_Decode, 230, 11, 239, 1, // Opcode: FRINTAv2f32 +/* 41136 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 41158 +/* 41141 */ MCD_OPC_CheckPredicate, 3, 234, 178, 0, // Skip to: 86948 +/* 41146 */ MCD_OPC_CheckField, 21, 1, 1, 227, 178, 0, // Skip to: 86948 +/* 41153 */ MCD_OPC_Decode, 196, 3, 238, 1, // Opcode: CMEQv8i8 +/* 41158 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41180 +/* 41163 */ MCD_OPC_CheckPredicate, 3, 212, 178, 0, // Skip to: 86948 +/* 41168 */ MCD_OPC_CheckField, 21, 1, 1, 205, 178, 0, // Skip to: 86948 +/* 41175 */ MCD_OPC_Decode, 232, 19, 130, 2, // Opcode: MLSv8i8 +/* 41180 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 41218 +/* 41185 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 41188 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41203 +/* 41193 */ MCD_OPC_CheckPredicate, 3, 182, 178, 0, // Skip to: 86948 +/* 41198 */ MCD_OPC_Decode, 253, 3, 239, 1, // Opcode: CMLEv8i8rz +/* 41203 */ MCD_OPC_FilterValue, 33, 172, 178, 0, // Skip to: 86948 +/* 41208 */ MCD_OPC_CheckPredicate, 3, 167, 178, 0, // Skip to: 86948 +/* 41213 */ MCD_OPC_Decode, 157, 12, 239, 1, // Opcode: FRINTXv2f32 +/* 41218 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 41240 +/* 41223 */ MCD_OPC_CheckPredicate, 3, 152, 178, 0, // Skip to: 86948 +/* 41228 */ MCD_OPC_CheckField, 21, 1, 1, 145, 178, 0, // Skip to: 86948 +/* 41235 */ MCD_OPC_Decode, 248, 20, 238, 1, // Opcode: PMULv8i8 +/* 41240 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 41262 +/* 41245 */ MCD_OPC_CheckPredicate, 3, 130, 178, 0, // Skip to: 86948 +/* 41250 */ MCD_OPC_CheckField, 21, 1, 1, 123, 178, 0, // Skip to: 86948 +/* 41257 */ MCD_OPC_Decode, 182, 32, 254, 1, // Opcode: UMLSLv8i8_v8i16 +/* 41262 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 41284 +/* 41267 */ MCD_OPC_CheckPredicate, 3, 108, 178, 0, // Skip to: 86948 +/* 41272 */ MCD_OPC_CheckField, 21, 1, 1, 101, 178, 0, // Skip to: 86948 +/* 41279 */ MCD_OPC_Decode, 238, 31, 238, 1, // Opcode: UMAXPv8i8 +/* 41284 */ MCD_OPC_FilterValue, 10, 48, 0, 0, // Skip to: 41337 +/* 41289 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 41292 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 41307 +/* 41297 */ MCD_OPC_CheckPredicate, 3, 78, 178, 0, // Skip to: 86948 +/* 41302 */ MCD_OPC_Decode, 176, 8, 239, 1, // Opcode: FCVTNUv2f32 +/* 41307 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 41322 +/* 41312 */ MCD_OPC_CheckPredicate, 3, 63, 178, 0, // Skip to: 86948 +/* 41317 */ MCD_OPC_Decode, 247, 31, 131, 2, // Opcode: UMAXVv8i8v +/* 41322 */ MCD_OPC_FilterValue, 49, 53, 178, 0, // Skip to: 86948 +/* 41327 */ MCD_OPC_CheckPredicate, 3, 48, 178, 0, // Skip to: 86948 +/* 41332 */ MCD_OPC_Decode, 148, 32, 131, 2, // Opcode: UMINVv8i8v +/* 41337 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 41359 +/* 41342 */ MCD_OPC_CheckPredicate, 3, 33, 178, 0, // Skip to: 86948 +/* 41347 */ MCD_OPC_CheckField, 21, 1, 1, 26, 178, 0, // Skip to: 86948 +/* 41354 */ MCD_OPC_Decode, 139, 32, 238, 1, // Opcode: UMINPv8i8 +/* 41359 */ MCD_OPC_FilterValue, 14, 16, 178, 0, // Skip to: 86948 +/* 41364 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 41367 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 41382 +/* 41372 */ MCD_OPC_CheckPredicate, 3, 3, 178, 0, // Skip to: 86948 +/* 41377 */ MCD_OPC_Decode, 186, 20, 239, 1, // Opcode: NEGv8i8 +/* 41382 */ MCD_OPC_FilterValue, 33, 249, 177, 0, // Skip to: 86948 +/* 41387 */ MCD_OPC_CheckPredicate, 3, 244, 177, 0, // Skip to: 86948 +/* 41392 */ MCD_OPC_Decode, 148, 8, 239, 1, // Opcode: FCVTMUv2f32 +/* 41397 */ MCD_OPC_FilterValue, 3, 234, 177, 0, // Skip to: 86948 +/* 41402 */ MCD_OPC_ExtractField, 10, 4, // Inst{13-10} ... +/* 41405 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41427 +/* 41410 */ MCD_OPC_CheckPredicate, 3, 221, 177, 0, // Skip to: 86948 +/* 41415 */ MCD_OPC_CheckField, 21, 1, 1, 214, 177, 0, // Skip to: 86948 +/* 41422 */ MCD_OPC_Decode, 202, 32, 234, 1, // Opcode: UMULLv8i8_v8i16 +/* 41427 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 41449 +/* 41432 */ MCD_OPC_CheckPredicate, 3, 199, 177, 0, // Skip to: 86948 +/* 41437 */ MCD_OPC_CheckField, 21, 1, 1, 192, 177, 0, // Skip to: 86948 +/* 41444 */ MCD_OPC_Decode, 197, 9, 238, 1, // Opcode: FMAXNMPv2f32 +/* 41449 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 41471 +/* 41454 */ MCD_OPC_CheckPredicate, 3, 177, 177, 0, // Skip to: 86948 +/* 41459 */ MCD_OPC_CheckField, 16, 6, 33, 170, 177, 0, // Skip to: 86948 +/* 41466 */ MCD_OPC_Decode, 240, 7, 239, 1, // Opcode: FCVTAUv2f32 +/* 41471 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41493 +/* 41476 */ MCD_OPC_CheckPredicate, 3, 155, 177, 0, // Skip to: 86948 +/* 41481 */ MCD_OPC_CheckField, 21, 1, 1, 148, 177, 0, // Skip to: 86948 +/* 41488 */ MCD_OPC_Decode, 177, 6, 238, 1, // Opcode: FADDPv2f32 +/* 41493 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 41515 +/* 41498 */ MCD_OPC_CheckPredicate, 3, 133, 177, 0, // Skip to: 86948 +/* 41503 */ MCD_OPC_CheckField, 16, 6, 33, 126, 177, 0, // Skip to: 86948 +/* 41510 */ MCD_OPC_Decode, 196, 31, 239, 1, // Opcode: UCVTFv2f32 +/* 41515 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 41537 +/* 41520 */ MCD_OPC_CheckPredicate, 3, 111, 177, 0, // Skip to: 86948 +/* 41525 */ MCD_OPC_CheckField, 21, 1, 1, 104, 177, 0, // Skip to: 86948 +/* 41532 */ MCD_OPC_Decode, 154, 11, 238, 1, // Opcode: FMULv2f32 +/* 41537 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 41559 +/* 41542 */ MCD_OPC_CheckPredicate, 3, 89, 177, 0, // Skip to: 86948 +/* 41547 */ MCD_OPC_CheckField, 21, 1, 1, 82, 177, 0, // Skip to: 86948 +/* 41554 */ MCD_OPC_Decode, 251, 6, 238, 1, // Opcode: FCMGEv2f32 +/* 41559 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 41581 +/* 41564 */ MCD_OPC_CheckPredicate, 3, 67, 177, 0, // Skip to: 86948 +/* 41569 */ MCD_OPC_CheckField, 21, 1, 1, 60, 177, 0, // Skip to: 86948 +/* 41576 */ MCD_OPC_Decode, 156, 6, 238, 1, // Opcode: FACGEv2f32 +/* 41581 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 41603 +/* 41586 */ MCD_OPC_CheckPredicate, 3, 45, 177, 0, // Skip to: 86948 +/* 41591 */ MCD_OPC_CheckField, 21, 1, 1, 38, 177, 0, // Skip to: 86948 +/* 41598 */ MCD_OPC_Decode, 223, 9, 238, 1, // Opcode: FMAXPv2f32 +/* 41603 */ MCD_OPC_FilterValue, 15, 28, 177, 0, // Skip to: 86948 +/* 41608 */ MCD_OPC_CheckPredicate, 3, 23, 177, 0, // Skip to: 86948 +/* 41613 */ MCD_OPC_CheckField, 21, 1, 1, 16, 177, 0, // Skip to: 86948 +/* 41620 */ MCD_OPC_Decode, 175, 9, 238, 1, // Opcode: FDIVv2f32 +/* 41625 */ MCD_OPC_FilterValue, 2, 109, 8, 0, // Skip to: 43787 +/* 41630 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 41633 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 41671 +/* 41638 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 41641 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 41656 +/* 41646 */ MCD_OPC_CheckPredicate, 3, 241, 176, 0, // Skip to: 86948 +/* 41651 */ MCD_OPC_Decode, 182, 30, 133, 2, // Opcode: TBLv16i8One +/* 41656 */ MCD_OPC_FilterValue, 1, 231, 176, 0, // Skip to: 86948 +/* 41661 */ MCD_OPC_CheckPredicate, 3, 226, 176, 0, // Skip to: 86948 +/* 41666 */ MCD_OPC_Decode, 163, 22, 133, 2, // Opcode: SADDLv16i8_v8i16 +/* 41671 */ MCD_OPC_FilterValue, 1, 109, 0, 0, // Skip to: 41785 +/* 41676 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 41679 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 41770 +/* 41684 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 41687 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 41755 +/* 41692 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 41695 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 41740 +/* 41700 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 41703 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41725 +/* 41708 */ MCD_OPC_CheckPredicate, 3, 179, 176, 0, // Skip to: 86948 +/* 41713 */ MCD_OPC_CheckField, 19, 1, 1, 172, 176, 0, // Skip to: 86948 +/* 41720 */ MCD_OPC_Decode, 213, 5, 134, 2, // Opcode: DUPv2i64lane +/* 41725 */ MCD_OPC_FilterValue, 1, 162, 176, 0, // Skip to: 86948 +/* 41730 */ MCD_OPC_CheckPredicate, 3, 157, 176, 0, // Skip to: 86948 +/* 41735 */ MCD_OPC_Decode, 217, 5, 135, 2, // Opcode: DUPv4i32lane +/* 41740 */ MCD_OPC_FilterValue, 1, 147, 176, 0, // Skip to: 86948 +/* 41745 */ MCD_OPC_CheckPredicate, 3, 142, 176, 0, // Skip to: 86948 +/* 41750 */ MCD_OPC_Decode, 219, 5, 136, 2, // Opcode: DUPv8i16lane +/* 41755 */ MCD_OPC_FilterValue, 1, 132, 176, 0, // Skip to: 86948 +/* 41760 */ MCD_OPC_CheckPredicate, 3, 127, 176, 0, // Skip to: 86948 +/* 41765 */ MCD_OPC_Decode, 209, 5, 137, 2, // Opcode: DUPv16i8lane +/* 41770 */ MCD_OPC_FilterValue, 1, 117, 176, 0, // Skip to: 86948 +/* 41775 */ MCD_OPC_CheckPredicate, 3, 112, 176, 0, // Skip to: 86948 +/* 41780 */ MCD_OPC_Decode, 255, 22, 133, 2, // Opcode: SHADDv16i8 +/* 41785 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 41807 +/* 41790 */ MCD_OPC_CheckPredicate, 3, 97, 176, 0, // Skip to: 86948 +/* 41795 */ MCD_OPC_CheckField, 16, 6, 32, 90, 176, 0, // Skip to: 86948 +/* 41802 */ MCD_OPC_Decode, 209, 21, 138, 2, // Opcode: REV64v16i8 +/* 41807 */ MCD_OPC_FilterValue, 3, 109, 0, 0, // Skip to: 41921 +/* 41812 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 41815 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 41906 +/* 41820 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 41823 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 41891 +/* 41828 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 41831 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 41876 +/* 41836 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 41839 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 41861 +/* 41844 */ MCD_OPC_CheckPredicate, 3, 43, 176, 0, // Skip to: 86948 +/* 41849 */ MCD_OPC_CheckField, 19, 1, 1, 36, 176, 0, // Skip to: 86948 +/* 41856 */ MCD_OPC_Decode, 212, 5, 139, 2, // Opcode: DUPv2i64gpr +/* 41861 */ MCD_OPC_FilterValue, 1, 26, 176, 0, // Skip to: 86948 +/* 41866 */ MCD_OPC_CheckPredicate, 3, 21, 176, 0, // Skip to: 86948 +/* 41871 */ MCD_OPC_Decode, 216, 5, 140, 2, // Opcode: DUPv4i32gpr +/* 41876 */ MCD_OPC_FilterValue, 1, 11, 176, 0, // Skip to: 86948 +/* 41881 */ MCD_OPC_CheckPredicate, 3, 6, 176, 0, // Skip to: 86948 +/* 41886 */ MCD_OPC_Decode, 218, 5, 140, 2, // Opcode: DUPv8i16gpr +/* 41891 */ MCD_OPC_FilterValue, 1, 252, 175, 0, // Skip to: 86948 +/* 41896 */ MCD_OPC_CheckPredicate, 3, 247, 175, 0, // Skip to: 86948 +/* 41901 */ MCD_OPC_Decode, 208, 5, 140, 2, // Opcode: DUPv16i8gpr +/* 41906 */ MCD_OPC_FilterValue, 1, 237, 175, 0, // Skip to: 86948 +/* 41911 */ MCD_OPC_CheckPredicate, 3, 232, 175, 0, // Skip to: 86948 +/* 41916 */ MCD_OPC_Decode, 172, 24, 133, 2, // Opcode: SQADDv16i8 +/* 41921 */ MCD_OPC_FilterValue, 4, 33, 0, 0, // Skip to: 41959 +/* 41926 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 41929 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 41944 +/* 41934 */ MCD_OPC_CheckPredicate, 3, 209, 175, 0, // Skip to: 86948 +/* 41939 */ MCD_OPC_Decode, 192, 30, 141, 2, // Opcode: TBXv16i8One +/* 41944 */ MCD_OPC_FilterValue, 1, 199, 175, 0, // Skip to: 86948 +/* 41949 */ MCD_OPC_CheckPredicate, 3, 194, 175, 0, // Skip to: 86948 +/* 41954 */ MCD_OPC_Decode, 172, 22, 133, 2, // Opcode: SADDWv16i8_v8i16 +/* 41959 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 41981 +/* 41964 */ MCD_OPC_CheckPredicate, 3, 179, 175, 0, // Skip to: 86948 +/* 41969 */ MCD_OPC_CheckField, 21, 1, 1, 172, 175, 0, // Skip to: 86948 +/* 41976 */ MCD_OPC_Decode, 183, 26, 133, 2, // Opcode: SRHADDv16i8 +/* 41981 */ MCD_OPC_FilterValue, 6, 40, 0, 0, // Skip to: 42026 +/* 41986 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 41989 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42004 +/* 41994 */ MCD_OPC_CheckPredicate, 3, 149, 175, 0, // Skip to: 86948 +/* 41999 */ MCD_OPC_Decode, 196, 34, 133, 2, // Opcode: UZP1v16i8 +/* 42004 */ MCD_OPC_FilterValue, 1, 139, 175, 0, // Skip to: 86948 +/* 42009 */ MCD_OPC_CheckPredicate, 3, 134, 175, 0, // Skip to: 86948 +/* 42014 */ MCD_OPC_CheckField, 16, 5, 0, 127, 175, 0, // Skip to: 86948 +/* 42021 */ MCD_OPC_Decode, 202, 21, 138, 2, // Opcode: REV16v16i8 +/* 42026 */ MCD_OPC_FilterValue, 7, 109, 0, 0, // Skip to: 42140 +/* 42031 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42034 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 42125 +/* 42039 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 42042 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 42110 +/* 42047 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 42050 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 42095 +/* 42055 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 42058 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42080 +/* 42063 */ MCD_OPC_CheckPredicate, 3, 80, 175, 0, // Skip to: 86948 +/* 42068 */ MCD_OPC_CheckField, 19, 1, 1, 73, 175, 0, // Skip to: 86948 +/* 42075 */ MCD_OPC_Decode, 158, 14, 142, 2, // Opcode: INSvi64gpr +/* 42080 */ MCD_OPC_FilterValue, 1, 63, 175, 0, // Skip to: 86948 +/* 42085 */ MCD_OPC_CheckPredicate, 3, 58, 175, 0, // Skip to: 86948 +/* 42090 */ MCD_OPC_Decode, 156, 14, 143, 2, // Opcode: INSvi32gpr +/* 42095 */ MCD_OPC_FilterValue, 1, 48, 175, 0, // Skip to: 86948 +/* 42100 */ MCD_OPC_CheckPredicate, 3, 43, 175, 0, // Skip to: 86948 +/* 42105 */ MCD_OPC_Decode, 154, 14, 144, 2, // Opcode: INSvi16gpr +/* 42110 */ MCD_OPC_FilterValue, 1, 33, 175, 0, // Skip to: 86948 +/* 42115 */ MCD_OPC_CheckPredicate, 3, 28, 175, 0, // Skip to: 86948 +/* 42120 */ MCD_OPC_Decode, 160, 14, 145, 2, // Opcode: INSvi8gpr +/* 42125 */ MCD_OPC_FilterValue, 1, 18, 175, 0, // Skip to: 86948 +/* 42130 */ MCD_OPC_CheckPredicate, 3, 13, 175, 0, // Skip to: 86948 +/* 42135 */ MCD_OPC_Decode, 252, 1, 133, 2, // Opcode: ANDv16i8 +/* 42140 */ MCD_OPC_FilterValue, 8, 33, 0, 0, // Skip to: 42178 +/* 42145 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42148 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42163 +/* 42153 */ MCD_OPC_CheckPredicate, 3, 246, 174, 0, // Skip to: 86948 +/* 42158 */ MCD_OPC_Decode, 184, 30, 146, 2, // Opcode: TBLv16i8Two +/* 42163 */ MCD_OPC_FilterValue, 1, 236, 174, 0, // Skip to: 86948 +/* 42168 */ MCD_OPC_CheckPredicate, 3, 231, 174, 0, // Skip to: 86948 +/* 42173 */ MCD_OPC_Decode, 161, 27, 133, 2, // Opcode: SSUBLv16i8_v8i16 +/* 42178 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 42200 +/* 42183 */ MCD_OPC_CheckPredicate, 3, 216, 174, 0, // Skip to: 86948 +/* 42188 */ MCD_OPC_CheckField, 21, 1, 1, 209, 174, 0, // Skip to: 86948 +/* 42195 */ MCD_OPC_Decode, 153, 23, 133, 2, // Opcode: SHSUBv16i8 +/* 42200 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 42261 +/* 42205 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42208 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42223 +/* 42213 */ MCD_OPC_CheckPredicate, 3, 186, 174, 0, // Skip to: 86948 +/* 42218 */ MCD_OPC_Decode, 213, 30, 133, 2, // Opcode: TRN1v16i8 +/* 42223 */ MCD_OPC_FilterValue, 1, 176, 174, 0, // Skip to: 86948 +/* 42228 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 42231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42246 +/* 42236 */ MCD_OPC_CheckPredicate, 3, 163, 174, 0, // Skip to: 86948 +/* 42241 */ MCD_OPC_Decode, 152, 22, 138, 2, // Opcode: SADDLPv16i8_v8i16 +/* 42246 */ MCD_OPC_FilterValue, 1, 153, 174, 0, // Skip to: 86948 +/* 42251 */ MCD_OPC_CheckPredicate, 3, 148, 174, 0, // Skip to: 86948 +/* 42256 */ MCD_OPC_Decode, 255, 34, 147, 2, // Opcode: XTNv16i8 +/* 42261 */ MCD_OPC_FilterValue, 11, 86, 0, 0, // Skip to: 42352 +/* 42266 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42269 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 42337 +/* 42274 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 42277 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 42322 +/* 42282 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 42285 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42307 +/* 42290 */ MCD_OPC_CheckPredicate, 3, 109, 174, 0, // Skip to: 86948 +/* 42295 */ MCD_OPC_CheckField, 18, 1, 1, 102, 174, 0, // Skip to: 86948 +/* 42302 */ MCD_OPC_Decode, 130, 24, 148, 2, // Opcode: SMOVvi32to64 +/* 42307 */ MCD_OPC_FilterValue, 1, 92, 174, 0, // Skip to: 86948 +/* 42312 */ MCD_OPC_CheckPredicate, 3, 87, 174, 0, // Skip to: 86948 +/* 42317 */ MCD_OPC_Decode, 129, 24, 149, 2, // Opcode: SMOVvi16to64 +/* 42322 */ MCD_OPC_FilterValue, 1, 77, 174, 0, // Skip to: 86948 +/* 42327 */ MCD_OPC_CheckPredicate, 3, 72, 174, 0, // Skip to: 86948 +/* 42332 */ MCD_OPC_Decode, 132, 24, 150, 2, // Opcode: SMOVvi8to64 +/* 42337 */ MCD_OPC_FilterValue, 1, 62, 174, 0, // Skip to: 86948 +/* 42342 */ MCD_OPC_CheckPredicate, 3, 57, 174, 0, // Skip to: 86948 +/* 42347 */ MCD_OPC_Decode, 154, 26, 133, 2, // Opcode: SQSUBv16i8 +/* 42352 */ MCD_OPC_FilterValue, 12, 33, 0, 0, // Skip to: 42390 +/* 42357 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42375 +/* 42365 */ MCD_OPC_CheckPredicate, 3, 34, 174, 0, // Skip to: 86948 +/* 42370 */ MCD_OPC_Decode, 194, 30, 151, 2, // Opcode: TBXv16i8Two +/* 42375 */ MCD_OPC_FilterValue, 1, 24, 174, 0, // Skip to: 86948 +/* 42380 */ MCD_OPC_CheckPredicate, 3, 19, 174, 0, // Skip to: 86948 +/* 42385 */ MCD_OPC_Decode, 167, 27, 133, 2, // Opcode: SSUBWv16i8_v8i16 +/* 42390 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 42412 +/* 42395 */ MCD_OPC_CheckPredicate, 3, 4, 174, 0, // Skip to: 86948 +/* 42400 */ MCD_OPC_CheckField, 21, 1, 1, 253, 173, 0, // Skip to: 86948 +/* 42407 */ MCD_OPC_Decode, 214, 3, 133, 2, // Opcode: CMGTv16i8 +/* 42412 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 42473 +/* 42417 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42420 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42435 +/* 42425 */ MCD_OPC_CheckPredicate, 3, 230, 173, 0, // Skip to: 86948 +/* 42430 */ MCD_OPC_Decode, 141, 35, 133, 2, // Opcode: ZIP1v16i8 +/* 42435 */ MCD_OPC_FilterValue, 1, 220, 173, 0, // Skip to: 86948 +/* 42440 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 42443 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42458 +/* 42448 */ MCD_OPC_CheckPredicate, 3, 207, 173, 0, // Skip to: 86948 +/* 42453 */ MCD_OPC_Decode, 141, 30, 147, 2, // Opcode: SUQADDv16i8 +/* 42458 */ MCD_OPC_FilterValue, 16, 197, 173, 0, // Skip to: 86948 +/* 42463 */ MCD_OPC_CheckPredicate, 3, 192, 173, 0, // Skip to: 86948 +/* 42468 */ MCD_OPC_Decode, 158, 22, 152, 2, // Opcode: SADDLVv16i8v +/* 42473 */ MCD_OPC_FilterValue, 15, 40, 0, 0, // Skip to: 42518 +/* 42478 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42481 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 42503 +/* 42486 */ MCD_OPC_CheckPredicate, 3, 169, 173, 0, // Skip to: 86948 +/* 42491 */ MCD_OPC_CheckField, 16, 4, 8, 162, 173, 0, // Skip to: 86948 +/* 42498 */ MCD_OPC_Decode, 185, 32, 153, 2, // Opcode: UMOVvi64 +/* 42503 */ MCD_OPC_FilterValue, 1, 152, 173, 0, // Skip to: 86948 +/* 42508 */ MCD_OPC_CheckPredicate, 3, 147, 173, 0, // Skip to: 86948 +/* 42513 */ MCD_OPC_Decode, 198, 3, 133, 2, // Opcode: CMGEv16i8 +/* 42518 */ MCD_OPC_FilterValue, 16, 33, 0, 0, // Skip to: 42556 +/* 42523 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42526 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42541 +/* 42531 */ MCD_OPC_CheckPredicate, 3, 124, 173, 0, // Skip to: 86948 +/* 42536 */ MCD_OPC_Decode, 183, 30, 154, 2, // Opcode: TBLv16i8Three +/* 42541 */ MCD_OPC_FilterValue, 1, 114, 173, 0, // Skip to: 86948 +/* 42546 */ MCD_OPC_CheckPredicate, 3, 109, 173, 0, // Skip to: 86948 +/* 42551 */ MCD_OPC_Decode, 146, 1, 141, 2, // Opcode: ADDHNv8i16_v16i8 +/* 42556 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 42578 +/* 42561 */ MCD_OPC_CheckPredicate, 3, 94, 173, 0, // Skip to: 86948 +/* 42566 */ MCD_OPC_CheckField, 21, 1, 1, 87, 173, 0, // Skip to: 86948 +/* 42573 */ MCD_OPC_Decode, 227, 26, 133, 2, // Opcode: SSHLv16i8 +/* 42578 */ MCD_OPC_FilterValue, 18, 48, 0, 0, // Skip to: 42631 +/* 42583 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 42586 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 42601 +/* 42591 */ MCD_OPC_CheckPredicate, 3, 64, 173, 0, // Skip to: 86948 +/* 42596 */ MCD_OPC_Decode, 164, 3, 138, 2, // Opcode: CLSv16i8 +/* 42601 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 42616 +/* 42606 */ MCD_OPC_CheckPredicate, 3, 49, 173, 0, // Skip to: 86948 +/* 42611 */ MCD_OPC_Decode, 165, 26, 147, 2, // Opcode: SQXTNv16i8 +/* 42616 */ MCD_OPC_FilterValue, 40, 39, 173, 0, // Skip to: 86948 +/* 42621 */ MCD_OPC_CheckPredicate, 5, 34, 173, 0, // Skip to: 86948 +/* 42626 */ MCD_OPC_Decode, 223, 1, 147, 2, // Opcode: AESErr +/* 42631 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 42653 +/* 42636 */ MCD_OPC_CheckPredicate, 3, 19, 173, 0, // Skip to: 86948 +/* 42641 */ MCD_OPC_CheckField, 21, 1, 1, 12, 173, 0, // Skip to: 86948 +/* 42648 */ MCD_OPC_Decode, 238, 25, 133, 2, // Opcode: SQSHLv16i8 +/* 42653 */ MCD_OPC_FilterValue, 20, 33, 0, 0, // Skip to: 42691 +/* 42658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42676 +/* 42666 */ MCD_OPC_CheckPredicate, 3, 245, 172, 0, // Skip to: 86948 +/* 42671 */ MCD_OPC_Decode, 193, 30, 155, 2, // Opcode: TBXv16i8Three +/* 42676 */ MCD_OPC_FilterValue, 1, 235, 172, 0, // Skip to: 86948 +/* 42681 */ MCD_OPC_CheckPredicate, 3, 230, 172, 0, // Skip to: 86948 +/* 42686 */ MCD_OPC_Decode, 246, 21, 141, 2, // Opcode: SABALv16i8_v8i16 +/* 42691 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 42713 +/* 42696 */ MCD_OPC_CheckPredicate, 3, 215, 172, 0, // Skip to: 86948 +/* 42701 */ MCD_OPC_CheckField, 21, 1, 1, 208, 172, 0, // Skip to: 86948 +/* 42708 */ MCD_OPC_Decode, 197, 26, 133, 2, // Opcode: SRSHLv16i8 +/* 42713 */ MCD_OPC_FilterValue, 22, 56, 0, 0, // Skip to: 42774 +/* 42718 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42721 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42736 +/* 42726 */ MCD_OPC_CheckPredicate, 3, 185, 172, 0, // Skip to: 86948 +/* 42731 */ MCD_OPC_Decode, 211, 34, 133, 2, // Opcode: UZP2v16i8 +/* 42736 */ MCD_OPC_FilterValue, 1, 175, 172, 0, // Skip to: 86948 +/* 42741 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 42744 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42759 +/* 42749 */ MCD_OPC_CheckPredicate, 3, 162, 172, 0, // Skip to: 86948 +/* 42754 */ MCD_OPC_Decode, 129, 5, 138, 2, // Opcode: CNTv16i8 +/* 42759 */ MCD_OPC_FilterValue, 8, 152, 172, 0, // Skip to: 86948 +/* 42764 */ MCD_OPC_CheckPredicate, 5, 147, 172, 0, // Skip to: 86948 +/* 42769 */ MCD_OPC_Decode, 222, 1, 147, 2, // Opcode: AESDrr +/* 42774 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 42796 +/* 42779 */ MCD_OPC_CheckPredicate, 3, 132, 172, 0, // Skip to: 86948 +/* 42784 */ MCD_OPC_CheckField, 21, 1, 1, 125, 172, 0, // Skip to: 86948 +/* 42791 */ MCD_OPC_Decode, 194, 25, 133, 2, // Opcode: SQRSHLv16i8 +/* 42796 */ MCD_OPC_FilterValue, 24, 33, 0, 0, // Skip to: 42834 +/* 42801 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42804 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42819 +/* 42809 */ MCD_OPC_CheckPredicate, 3, 102, 172, 0, // Skip to: 86948 +/* 42814 */ MCD_OPC_Decode, 181, 30, 156, 2, // Opcode: TBLv16i8Four +/* 42819 */ MCD_OPC_FilterValue, 1, 92, 172, 0, // Skip to: 86948 +/* 42824 */ MCD_OPC_CheckPredicate, 3, 87, 172, 0, // Skip to: 86948 +/* 42829 */ MCD_OPC_Decode, 215, 29, 141, 2, // Opcode: SUBHNv8i16_v16i8 +/* 42834 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 42856 +/* 42839 */ MCD_OPC_CheckPredicate, 3, 72, 172, 0, // Skip to: 86948 +/* 42844 */ MCD_OPC_CheckField, 21, 1, 1, 65, 172, 0, // Skip to: 86948 +/* 42851 */ MCD_OPC_Decode, 200, 23, 133, 2, // Opcode: SMAXv16i8 +/* 42856 */ MCD_OPC_FilterValue, 26, 71, 0, 0, // Skip to: 42932 +/* 42861 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42864 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42879 +/* 42869 */ MCD_OPC_CheckPredicate, 3, 42, 172, 0, // Skip to: 86948 +/* 42874 */ MCD_OPC_Decode, 228, 30, 133, 2, // Opcode: TRN2v16i8 +/* 42879 */ MCD_OPC_FilterValue, 1, 32, 172, 0, // Skip to: 86948 +/* 42884 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 42887 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42902 +/* 42892 */ MCD_OPC_CheckPredicate, 3, 19, 172, 0, // Skip to: 86948 +/* 42897 */ MCD_OPC_Decode, 146, 22, 147, 2, // Opcode: SADALPv16i8_v8i16 +/* 42902 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 42917 +/* 42907 */ MCD_OPC_CheckPredicate, 3, 4, 172, 0, // Skip to: 86948 +/* 42912 */ MCD_OPC_Decode, 184, 8, 147, 2, // Opcode: FCVTNv8i16 +/* 42917 */ MCD_OPC_FilterValue, 8, 250, 171, 0, // Skip to: 86948 +/* 42922 */ MCD_OPC_CheckPredicate, 5, 245, 171, 0, // Skip to: 86948 +/* 42927 */ MCD_OPC_Decode, 226, 1, 138, 2, // Opcode: AESMCrr +/* 42932 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 42954 +/* 42937 */ MCD_OPC_CheckPredicate, 3, 230, 171, 0, // Skip to: 86948 +/* 42942 */ MCD_OPC_CheckField, 21, 1, 1, 223, 171, 0, // Skip to: 86948 +/* 42949 */ MCD_OPC_Decode, 230, 23, 133, 2, // Opcode: SMINv16i8 +/* 42954 */ MCD_OPC_FilterValue, 28, 33, 0, 0, // Skip to: 42992 +/* 42959 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 42962 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 42977 +/* 42967 */ MCD_OPC_CheckPredicate, 3, 200, 171, 0, // Skip to: 86948 +/* 42972 */ MCD_OPC_Decode, 191, 30, 157, 2, // Opcode: TBXv16i8Four +/* 42977 */ MCD_OPC_FilterValue, 1, 190, 171, 0, // Skip to: 86948 +/* 42982 */ MCD_OPC_CheckPredicate, 3, 185, 171, 0, // Skip to: 86948 +/* 42987 */ MCD_OPC_Decode, 130, 22, 133, 2, // Opcode: SABDLv16i8_v8i16 +/* 42992 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 43014 +/* 42997 */ MCD_OPC_CheckPredicate, 3, 170, 171, 0, // Skip to: 86948 +/* 43002 */ MCD_OPC_CheckField, 21, 1, 1, 163, 171, 0, // Skip to: 86948 +/* 43009 */ MCD_OPC_Decode, 140, 22, 133, 2, // Opcode: SABDv16i8 +/* 43014 */ MCD_OPC_FilterValue, 30, 71, 0, 0, // Skip to: 43090 +/* 43019 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 43022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43037 +/* 43027 */ MCD_OPC_CheckPredicate, 3, 140, 171, 0, // Skip to: 86948 +/* 43032 */ MCD_OPC_Decode, 156, 35, 133, 2, // Opcode: ZIP2v16i8 +/* 43037 */ MCD_OPC_FilterValue, 1, 130, 171, 0, // Skip to: 86948 +/* 43042 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 43045 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43060 +/* 43050 */ MCD_OPC_CheckPredicate, 3, 117, 171, 0, // Skip to: 86948 +/* 43055 */ MCD_OPC_Decode, 153, 24, 138, 2, // Opcode: SQABSv16i8 +/* 43060 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 43075 +/* 43065 */ MCD_OPC_CheckPredicate, 3, 102, 171, 0, // Skip to: 86948 +/* 43070 */ MCD_OPC_Decode, 252, 7, 138, 2, // Opcode: FCVTLv8i16 +/* 43075 */ MCD_OPC_FilterValue, 8, 92, 171, 0, // Skip to: 86948 +/* 43080 */ MCD_OPC_CheckPredicate, 5, 87, 171, 0, // Skip to: 86948 +/* 43085 */ MCD_OPC_Decode, 224, 1, 138, 2, // Opcode: AESIMCrr +/* 43090 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 43112 +/* 43095 */ MCD_OPC_CheckPredicate, 3, 72, 171, 0, // Skip to: 86948 +/* 43100 */ MCD_OPC_CheckField, 21, 1, 1, 65, 171, 0, // Skip to: 86948 +/* 43107 */ MCD_OPC_Decode, 252, 21, 141, 2, // Opcode: SABAv16i8 +/* 43112 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 43134 +/* 43117 */ MCD_OPC_CheckPredicate, 3, 50, 171, 0, // Skip to: 86948 +/* 43122 */ MCD_OPC_CheckField, 21, 1, 1, 43, 171, 0, // Skip to: 86948 +/* 43129 */ MCD_OPC_Decode, 236, 23, 141, 2, // Opcode: SMLALv16i8_v8i16 +/* 43134 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 43156 +/* 43139 */ MCD_OPC_CheckPredicate, 3, 28, 171, 0, // Skip to: 86948 +/* 43144 */ MCD_OPC_CheckField, 21, 1, 1, 21, 171, 0, // Skip to: 86948 +/* 43151 */ MCD_OPC_Decode, 194, 1, 133, 2, // Opcode: ADDv16i8 +/* 43156 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 43194 +/* 43161 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 43164 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43179 +/* 43169 */ MCD_OPC_CheckPredicate, 3, 254, 170, 0, // Skip to: 86948 +/* 43174 */ MCD_OPC_Decode, 215, 3, 138, 2, // Opcode: CMGTv16i8rz +/* 43179 */ MCD_OPC_FilterValue, 33, 244, 170, 0, // Skip to: 86948 +/* 43184 */ MCD_OPC_CheckPredicate, 3, 239, 170, 0, // Skip to: 86948 +/* 43189 */ MCD_OPC_Decode, 138, 12, 138, 2, // Opcode: FRINTNv4f32 +/* 43194 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 43216 +/* 43199 */ MCD_OPC_CheckPredicate, 3, 224, 170, 0, // Skip to: 86948 +/* 43204 */ MCD_OPC_CheckField, 21, 1, 1, 217, 170, 0, // Skip to: 86948 +/* 43211 */ MCD_OPC_Decode, 233, 4, 133, 2, // Opcode: CMTSTv16i8 +/* 43216 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 43238 +/* 43221 */ MCD_OPC_CheckPredicate, 3, 202, 170, 0, // Skip to: 86948 +/* 43226 */ MCD_OPC_CheckField, 21, 1, 1, 195, 170, 0, // Skip to: 86948 +/* 43233 */ MCD_OPC_Decode, 209, 19, 141, 2, // Opcode: MLAv16i8 +/* 43238 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 43276 +/* 43243 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 43246 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43261 +/* 43251 */ MCD_OPC_CheckPredicate, 3, 172, 170, 0, // Skip to: 86948 +/* 43256 */ MCD_OPC_Decode, 183, 3, 138, 2, // Opcode: CMEQv16i8rz +/* 43261 */ MCD_OPC_FilterValue, 33, 162, 170, 0, // Skip to: 86948 +/* 43266 */ MCD_OPC_CheckPredicate, 3, 157, 170, 0, // Skip to: 86948 +/* 43271 */ MCD_OPC_Decode, 255, 11, 138, 2, // Opcode: FRINTMv4f32 +/* 43276 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 43298 +/* 43281 */ MCD_OPC_CheckPredicate, 3, 142, 170, 0, // Skip to: 86948 +/* 43286 */ MCD_OPC_CheckField, 21, 1, 1, 135, 170, 0, // Skip to: 86948 +/* 43293 */ MCD_OPC_Decode, 157, 20, 133, 2, // Opcode: MULv16i8 +/* 43298 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 43320 +/* 43303 */ MCD_OPC_CheckPredicate, 3, 120, 170, 0, // Skip to: 86948 +/* 43308 */ MCD_OPC_CheckField, 21, 1, 1, 113, 170, 0, // Skip to: 86948 +/* 43315 */ MCD_OPC_Decode, 246, 23, 141, 2, // Opcode: SMLSLv16i8_v8i16 +/* 43320 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 43342 +/* 43325 */ MCD_OPC_CheckPredicate, 3, 98, 170, 0, // Skip to: 86948 +/* 43330 */ MCD_OPC_CheckField, 21, 1, 1, 91, 170, 0, // Skip to: 86948 +/* 43337 */ MCD_OPC_Decode, 177, 23, 133, 2, // Opcode: SMAXPv16i8 +/* 43342 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 43410 +/* 43347 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 43350 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43365 +/* 43355 */ MCD_OPC_CheckPredicate, 3, 68, 170, 0, // Skip to: 86948 +/* 43360 */ MCD_OPC_Decode, 254, 3, 138, 2, // Opcode: CMLTv16i8rz +/* 43365 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43380 +/* 43370 */ MCD_OPC_CheckPredicate, 3, 53, 170, 0, // Skip to: 86948 +/* 43375 */ MCD_OPC_Decode, 165, 8, 138, 2, // Opcode: FCVTNSv4f32 +/* 43380 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 43395 +/* 43385 */ MCD_OPC_CheckPredicate, 3, 38, 170, 0, // Skip to: 86948 +/* 43390 */ MCD_OPC_Decode, 187, 23, 158, 2, // Opcode: SMAXVv16i8v +/* 43395 */ MCD_OPC_FilterValue, 49, 28, 170, 0, // Skip to: 86948 +/* 43400 */ MCD_OPC_CheckPredicate, 3, 23, 170, 0, // Skip to: 86948 +/* 43405 */ MCD_OPC_Decode, 217, 23, 158, 2, // Opcode: SMINVv16i8v +/* 43410 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 43432 +/* 43415 */ MCD_OPC_CheckPredicate, 3, 8, 170, 0, // Skip to: 86948 +/* 43420 */ MCD_OPC_CheckField, 21, 1, 1, 1, 170, 0, // Skip to: 86948 +/* 43427 */ MCD_OPC_Decode, 207, 23, 133, 2, // Opcode: SMINPv16i8 +/* 43432 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 43485 +/* 43437 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 43440 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 43455 +/* 43445 */ MCD_OPC_CheckPredicate, 3, 234, 169, 0, // Skip to: 86948 +/* 43450 */ MCD_OPC_Decode, 130, 1, 138, 2, // Opcode: ABSv16i8 +/* 43455 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43470 +/* 43460 */ MCD_OPC_CheckPredicate, 3, 219, 169, 0, // Skip to: 86948 +/* 43465 */ MCD_OPC_Decode, 137, 8, 138, 2, // Opcode: FCVTMSv4f32 +/* 43470 */ MCD_OPC_FilterValue, 49, 209, 169, 0, // Skip to: 86948 +/* 43475 */ MCD_OPC_CheckPredicate, 3, 204, 169, 0, // Skip to: 86948 +/* 43480 */ MCD_OPC_Decode, 167, 1, 158, 2, // Opcode: ADDVv16i8v +/* 43485 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 43507 +/* 43490 */ MCD_OPC_CheckPredicate, 3, 189, 169, 0, // Skip to: 86948 +/* 43495 */ MCD_OPC_CheckField, 21, 1, 1, 182, 169, 0, // Skip to: 86948 +/* 43502 */ MCD_OPC_Decode, 149, 1, 133, 2, // Opcode: ADDPv16i8 +/* 43507 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 43529 +/* 43512 */ MCD_OPC_CheckPredicate, 3, 167, 169, 0, // Skip to: 86948 +/* 43517 */ MCD_OPC_CheckField, 21, 1, 1, 160, 169, 0, // Skip to: 86948 +/* 43524 */ MCD_OPC_Decode, 139, 24, 133, 2, // Opcode: SMULLv16i8_v8i16 +/* 43529 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 43551 +/* 43534 */ MCD_OPC_CheckPredicate, 3, 145, 169, 0, // Skip to: 86948 +/* 43539 */ MCD_OPC_CheckField, 21, 1, 1, 138, 169, 0, // Skip to: 86948 +/* 43546 */ MCD_OPC_Decode, 221, 9, 133, 2, // Opcode: FMAXNMv4f32 +/* 43551 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 43589 +/* 43556 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 43559 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 43574 +/* 43564 */ MCD_OPC_CheckPredicate, 3, 115, 169, 0, // Skip to: 86948 +/* 43569 */ MCD_OPC_Decode, 229, 7, 138, 2, // Opcode: FCVTASv4f32 +/* 43574 */ MCD_OPC_FilterValue, 48, 105, 169, 0, // Skip to: 86948 +/* 43579 */ MCD_OPC_CheckPredicate, 4, 100, 169, 0, // Skip to: 86948 +/* 43584 */ MCD_OPC_Decode, 211, 9, 152, 2, // Opcode: FMAXNMVv8i16v +/* 43589 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 43611 +/* 43594 */ MCD_OPC_CheckPredicate, 3, 85, 169, 0, // Skip to: 86948 +/* 43599 */ MCD_OPC_CheckField, 21, 1, 1, 78, 169, 0, // Skip to: 86948 +/* 43606 */ MCD_OPC_Decode, 191, 10, 141, 2, // Opcode: FMLAv4f32 +/* 43611 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 43633 +/* 43616 */ MCD_OPC_CheckPredicate, 3, 63, 169, 0, // Skip to: 86948 +/* 43621 */ MCD_OPC_CheckField, 21, 1, 1, 56, 169, 0, // Skip to: 86948 +/* 43628 */ MCD_OPC_Decode, 201, 6, 133, 2, // Opcode: FADDv4f32 +/* 43633 */ MCD_OPC_FilterValue, 54, 17, 0, 0, // Skip to: 43655 +/* 43638 */ MCD_OPC_CheckPredicate, 3, 41, 169, 0, // Skip to: 86948 +/* 43643 */ MCD_OPC_CheckField, 16, 6, 33, 34, 169, 0, // Skip to: 86948 +/* 43650 */ MCD_OPC_Decode, 214, 22, 138, 2, // Opcode: SCVTFv4f32 +/* 43655 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 43677 +/* 43660 */ MCD_OPC_CheckPredicate, 3, 19, 169, 0, // Skip to: 86948 +/* 43665 */ MCD_OPC_CheckField, 21, 1, 1, 12, 169, 0, // Skip to: 86948 +/* 43672 */ MCD_OPC_Decode, 134, 11, 133, 2, // Opcode: FMULXv4f32 +/* 43677 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 43699 +/* 43682 */ MCD_OPC_CheckPredicate, 3, 253, 168, 0, // Skip to: 86948 +/* 43687 */ MCD_OPC_CheckField, 21, 1, 1, 246, 168, 0, // Skip to: 86948 +/* 43694 */ MCD_OPC_Decode, 243, 20, 133, 2, // Opcode: PMULLv16i8 +/* 43699 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 43721 +/* 43704 */ MCD_OPC_CheckPredicate, 3, 231, 168, 0, // Skip to: 86948 +/* 43709 */ MCD_OPC_CheckField, 21, 1, 1, 224, 168, 0, // Skip to: 86948 +/* 43716 */ MCD_OPC_Decode, 234, 6, 133, 2, // Opcode: FCMEQv4f32 +/* 43721 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 43743 +/* 43726 */ MCD_OPC_CheckPredicate, 3, 209, 168, 0, // Skip to: 86948 +/* 43731 */ MCD_OPC_CheckField, 21, 1, 1, 202, 168, 0, // Skip to: 86948 +/* 43738 */ MCD_OPC_Decode, 247, 9, 133, 2, // Opcode: FMAXv4f32 +/* 43743 */ MCD_OPC_FilterValue, 62, 17, 0, 0, // Skip to: 43765 +/* 43748 */ MCD_OPC_CheckPredicate, 4, 187, 168, 0, // Skip to: 86948 +/* 43753 */ MCD_OPC_CheckField, 16, 6, 48, 180, 168, 0, // Skip to: 86948 +/* 43760 */ MCD_OPC_Decode, 237, 9, 152, 2, // Opcode: FMAXVv8i16v +/* 43765 */ MCD_OPC_FilterValue, 63, 170, 168, 0, // Skip to: 86948 +/* 43770 */ MCD_OPC_CheckPredicate, 3, 165, 168, 0, // Skip to: 86948 +/* 43775 */ MCD_OPC_CheckField, 21, 1, 1, 158, 168, 0, // Skip to: 86948 +/* 43782 */ MCD_OPC_Decode, 216, 11, 133, 2, // Opcode: FRECPSv4f32 +/* 43787 */ MCD_OPC_FilterValue, 3, 71, 5, 0, // Skip to: 45143 +/* 43792 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 43795 */ MCD_OPC_FilterValue, 0, 182, 2, 0, // Skip to: 44494 +/* 43800 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 43803 */ MCD_OPC_FilterValue, 0, 107, 1, 0, // Skip to: 44171 +/* 43808 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 43811 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43826 +/* 43816 */ MCD_OPC_CheckPredicate, 3, 119, 168, 0, // Skip to: 86948 +/* 43821 */ MCD_OPC_Decode, 253, 5, 159, 2, // Opcode: EXTv16i8 +/* 43826 */ MCD_OPC_FilterValue, 1, 109, 168, 0, // Skip to: 86948 +/* 43831 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 43834 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43849 +/* 43839 */ MCD_OPC_CheckPredicate, 3, 96, 168, 0, // Skip to: 86948 +/* 43844 */ MCD_OPC_Decode, 153, 31, 133, 2, // Opcode: UADDLv16i8_v8i16 +/* 43849 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 43871 +/* 43854 */ MCD_OPC_CheckPredicate, 3, 81, 168, 0, // Skip to: 86948 +/* 43859 */ MCD_OPC_CheckField, 16, 5, 0, 74, 168, 0, // Skip to: 86948 +/* 43866 */ MCD_OPC_Decode, 205, 21, 138, 2, // Opcode: REV32v16i8 +/* 43871 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 43886 +/* 43876 */ MCD_OPC_CheckPredicate, 3, 59, 168, 0, // Skip to: 86948 +/* 43881 */ MCD_OPC_Decode, 163, 31, 133, 2, // Opcode: UADDWv16i8_v8i16 +/* 43886 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 43901 +/* 43891 */ MCD_OPC_CheckPredicate, 3, 44, 168, 0, // Skip to: 86948 +/* 43896 */ MCD_OPC_Decode, 164, 34, 133, 2, // Opcode: USUBLv16i8_v8i16 +/* 43901 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 43939 +/* 43906 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 43909 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43924 +/* 43914 */ MCD_OPC_CheckPredicate, 3, 21, 168, 0, // Skip to: 86948 +/* 43919 */ MCD_OPC_Decode, 142, 31, 138, 2, // Opcode: UADDLPv16i8_v8i16 +/* 43924 */ MCD_OPC_FilterValue, 1, 11, 168, 0, // Skip to: 86948 +/* 43929 */ MCD_OPC_CheckPredicate, 3, 6, 168, 0, // Skip to: 86948 +/* 43934 */ MCD_OPC_Decode, 174, 26, 147, 2, // Opcode: SQXTUNv16i8 +/* 43939 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 43954 +/* 43944 */ MCD_OPC_CheckPredicate, 3, 247, 167, 0, // Skip to: 86948 +/* 43949 */ MCD_OPC_Decode, 170, 34, 133, 2, // Opcode: USUBWv16i8_v8i16 +/* 43954 */ MCD_OPC_FilterValue, 7, 48, 0, 0, // Skip to: 44007 +/* 43959 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 43962 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 43977 +/* 43967 */ MCD_OPC_CheckPredicate, 3, 224, 167, 0, // Skip to: 86948 +/* 43972 */ MCD_OPC_Decode, 145, 34, 147, 2, // Opcode: USQADDv16i8 +/* 43977 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 43992 +/* 43982 */ MCD_OPC_CheckPredicate, 3, 209, 167, 0, // Skip to: 86948 +/* 43987 */ MCD_OPC_Decode, 133, 23, 138, 2, // Opcode: SHLLv16i8 +/* 43992 */ MCD_OPC_FilterValue, 16, 199, 167, 0, // Skip to: 86948 +/* 43997 */ MCD_OPC_CheckPredicate, 3, 194, 167, 0, // Skip to: 86948 +/* 44002 */ MCD_OPC_Decode, 148, 31, 152, 2, // Opcode: UADDLVv16i8v +/* 44007 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 44022 +/* 44012 */ MCD_OPC_CheckPredicate, 3, 179, 167, 0, // Skip to: 86948 +/* 44017 */ MCD_OPC_Decode, 181, 21, 141, 2, // Opcode: RADDHNv8i16_v16i8 +/* 44022 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 44060 +/* 44027 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 44030 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 44045 +/* 44035 */ MCD_OPC_CheckPredicate, 3, 156, 167, 0, // Skip to: 86948 +/* 44040 */ MCD_OPC_Decode, 176, 3, 138, 2, // Opcode: CLZv16i8 +/* 44045 */ MCD_OPC_FilterValue, 1, 146, 167, 0, // Skip to: 86948 +/* 44050 */ MCD_OPC_CheckPredicate, 3, 141, 167, 0, // Skip to: 86948 +/* 44055 */ MCD_OPC_Decode, 208, 33, 147, 2, // Opcode: UQXTNv16i8 +/* 44060 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 44075 +/* 44065 */ MCD_OPC_CheckPredicate, 3, 126, 167, 0, // Skip to: 86948 +/* 44070 */ MCD_OPC_Decode, 236, 30, 141, 2, // Opcode: UABALv16i8_v8i16 +/* 44075 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 44097 +/* 44080 */ MCD_OPC_CheckPredicate, 3, 111, 167, 0, // Skip to: 86948 +/* 44085 */ MCD_OPC_CheckField, 16, 5, 0, 104, 167, 0, // Skip to: 86948 +/* 44092 */ MCD_OPC_Decode, 193, 20, 138, 2, // Opcode: NOTv16i8 +/* 44097 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 44112 +/* 44102 */ MCD_OPC_CheckPredicate, 3, 89, 167, 0, // Skip to: 86948 +/* 44107 */ MCD_OPC_Decode, 244, 21, 141, 2, // Opcode: RSUBHNv8i16_v16i8 +/* 44112 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 44134 +/* 44117 */ MCD_OPC_CheckPredicate, 3, 74, 167, 0, // Skip to: 86948 +/* 44122 */ MCD_OPC_CheckField, 16, 5, 0, 67, 167, 0, // Skip to: 86948 +/* 44129 */ MCD_OPC_Decode, 136, 31, 147, 2, // Opcode: UADALPv16i8_v8i16 +/* 44134 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 44149 +/* 44139 */ MCD_OPC_CheckPredicate, 3, 52, 167, 0, // Skip to: 86948 +/* 44144 */ MCD_OPC_Decode, 248, 30, 133, 2, // Opcode: UABDLv16i8_v8i16 +/* 44149 */ MCD_OPC_FilterValue, 15, 42, 167, 0, // Skip to: 86948 +/* 44154 */ MCD_OPC_CheckPredicate, 3, 37, 167, 0, // Skip to: 86948 +/* 44159 */ MCD_OPC_CheckField, 16, 5, 0, 30, 167, 0, // Skip to: 86948 +/* 44166 */ MCD_OPC_Decode, 147, 25, 138, 2, // Opcode: SQNEGv16i8 +/* 44171 */ MCD_OPC_FilterValue, 1, 20, 167, 0, // Skip to: 86948 +/* 44176 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 44179 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44201 +/* 44184 */ MCD_OPC_CheckPredicate, 3, 7, 167, 0, // Skip to: 86948 +/* 44189 */ MCD_OPC_CheckField, 21, 1, 1, 0, 167, 0, // Skip to: 86948 +/* 44196 */ MCD_OPC_Decode, 163, 32, 141, 2, // Opcode: UMLALv16i8_v8i16 +/* 44201 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 44239 +/* 44206 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 44209 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44224 +/* 44214 */ MCD_OPC_CheckPredicate, 3, 233, 166, 0, // Skip to: 86948 +/* 44219 */ MCD_OPC_Decode, 199, 3, 138, 2, // Opcode: CMGEv16i8rz +/* 44224 */ MCD_OPC_FilterValue, 33, 223, 166, 0, // Skip to: 86948 +/* 44229 */ MCD_OPC_CheckPredicate, 3, 218, 166, 0, // Skip to: 86948 +/* 44234 */ MCD_OPC_Decode, 233, 11, 138, 2, // Opcode: FRINTAv4f32 +/* 44239 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 44277 +/* 44244 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 44247 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44262 +/* 44252 */ MCD_OPC_CheckPredicate, 3, 195, 166, 0, // Skip to: 86948 +/* 44257 */ MCD_OPC_Decode, 246, 3, 138, 2, // Opcode: CMLEv16i8rz +/* 44262 */ MCD_OPC_FilterValue, 33, 185, 166, 0, // Skip to: 86948 +/* 44267 */ MCD_OPC_CheckPredicate, 3, 180, 166, 0, // Skip to: 86948 +/* 44272 */ MCD_OPC_Decode, 160, 12, 138, 2, // Opcode: FRINTXv4f32 +/* 44277 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 44299 +/* 44282 */ MCD_OPC_CheckPredicate, 3, 165, 166, 0, // Skip to: 86948 +/* 44287 */ MCD_OPC_CheckField, 21, 1, 1, 158, 166, 0, // Skip to: 86948 +/* 44294 */ MCD_OPC_Decode, 173, 32, 141, 2, // Opcode: UMLSLv16i8_v8i16 +/* 44299 */ MCD_OPC_FilterValue, 5, 48, 0, 0, // Skip to: 44352 +/* 44304 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 44307 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 44322 +/* 44312 */ MCD_OPC_CheckPredicate, 3, 135, 166, 0, // Skip to: 86948 +/* 44317 */ MCD_OPC_Decode, 179, 8, 138, 2, // Opcode: FCVTNUv4f32 +/* 44322 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 44337 +/* 44327 */ MCD_OPC_CheckPredicate, 3, 120, 166, 0, // Skip to: 86948 +/* 44332 */ MCD_OPC_Decode, 243, 31, 158, 2, // Opcode: UMAXVv16i8v +/* 44337 */ MCD_OPC_FilterValue, 49, 110, 166, 0, // Skip to: 86948 +/* 44342 */ MCD_OPC_CheckPredicate, 3, 105, 166, 0, // Skip to: 86948 +/* 44347 */ MCD_OPC_Decode, 144, 32, 158, 2, // Opcode: UMINVv16i8v +/* 44352 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 44390 +/* 44357 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 44360 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 44375 +/* 44365 */ MCD_OPC_CheckPredicate, 3, 82, 166, 0, // Skip to: 86948 +/* 44370 */ MCD_OPC_Decode, 179, 20, 138, 2, // Opcode: NEGv16i8 +/* 44375 */ MCD_OPC_FilterValue, 33, 72, 166, 0, // Skip to: 86948 +/* 44380 */ MCD_OPC_CheckPredicate, 3, 67, 166, 0, // Skip to: 86948 +/* 44385 */ MCD_OPC_Decode, 151, 8, 138, 2, // Opcode: FCVTMUv4f32 +/* 44390 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 44412 +/* 44395 */ MCD_OPC_CheckPredicate, 3, 52, 166, 0, // Skip to: 86948 +/* 44400 */ MCD_OPC_CheckField, 21, 1, 1, 45, 166, 0, // Skip to: 86948 +/* 44407 */ MCD_OPC_Decode, 193, 32, 133, 2, // Opcode: UMULLv16i8_v8i16 +/* 44412 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 44450 +/* 44417 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 44420 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 44435 +/* 44425 */ MCD_OPC_CheckPredicate, 3, 22, 166, 0, // Skip to: 86948 +/* 44430 */ MCD_OPC_Decode, 243, 7, 138, 2, // Opcode: FCVTAUv4f32 +/* 44435 */ MCD_OPC_FilterValue, 48, 12, 166, 0, // Skip to: 86948 +/* 44440 */ MCD_OPC_CheckPredicate, 3, 7, 166, 0, // Skip to: 86948 +/* 44445 */ MCD_OPC_Decode, 210, 9, 160, 2, // Opcode: FMAXNMVv4i32v +/* 44450 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 44472 +/* 44455 */ MCD_OPC_CheckPredicate, 3, 248, 165, 0, // Skip to: 86948 +/* 44460 */ MCD_OPC_CheckField, 16, 6, 33, 241, 165, 0, // Skip to: 86948 +/* 44467 */ MCD_OPC_Decode, 201, 31, 138, 2, // Opcode: UCVTFv4f32 +/* 44472 */ MCD_OPC_FilterValue, 15, 231, 165, 0, // Skip to: 86948 +/* 44477 */ MCD_OPC_CheckPredicate, 3, 226, 165, 0, // Skip to: 86948 +/* 44482 */ MCD_OPC_CheckField, 16, 6, 48, 219, 165, 0, // Skip to: 86948 +/* 44489 */ MCD_OPC_Decode, 236, 9, 160, 2, // Opcode: FMAXVv4i32v +/* 44494 */ MCD_OPC_FilterValue, 1, 209, 165, 0, // Skip to: 86948 +/* 44499 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 44502 */ MCD_OPC_FilterValue, 0, 86, 1, 0, // Skip to: 44849 +/* 44507 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 44510 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 44601 +/* 44515 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 44518 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 44586 +/* 44523 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 44526 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 44571 +/* 44531 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 44534 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44556 +/* 44539 */ MCD_OPC_CheckPredicate, 3, 164, 165, 0, // Skip to: 86948 +/* 44544 */ MCD_OPC_CheckField, 19, 1, 1, 157, 165, 0, // Skip to: 86948 +/* 44551 */ MCD_OPC_Decode, 159, 14, 161, 2, // Opcode: INSvi64lane +/* 44556 */ MCD_OPC_FilterValue, 1, 147, 165, 0, // Skip to: 86948 +/* 44561 */ MCD_OPC_CheckPredicate, 3, 142, 165, 0, // Skip to: 86948 +/* 44566 */ MCD_OPC_Decode, 157, 14, 162, 2, // Opcode: INSvi32lane +/* 44571 */ MCD_OPC_FilterValue, 1, 132, 165, 0, // Skip to: 86948 +/* 44576 */ MCD_OPC_CheckPredicate, 3, 127, 165, 0, // Skip to: 86948 +/* 44581 */ MCD_OPC_Decode, 155, 14, 163, 2, // Opcode: INSvi16lane +/* 44586 */ MCD_OPC_FilterValue, 1, 117, 165, 0, // Skip to: 86948 +/* 44591 */ MCD_OPC_CheckPredicate, 3, 112, 165, 0, // Skip to: 86948 +/* 44596 */ MCD_OPC_Decode, 161, 14, 164, 2, // Opcode: INSvi8lane +/* 44601 */ MCD_OPC_FilterValue, 1, 102, 165, 0, // Skip to: 86948 +/* 44606 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 44609 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 44624 +/* 44614 */ MCD_OPC_CheckPredicate, 3, 89, 165, 0, // Skip to: 86948 +/* 44619 */ MCD_OPC_Decode, 220, 31, 133, 2, // Opcode: UHADDv16i8 +/* 44624 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 44639 +/* 44629 */ MCD_OPC_CheckPredicate, 3, 74, 165, 0, // Skip to: 86948 +/* 44634 */ MCD_OPC_Decode, 211, 32, 133, 2, // Opcode: UQADDv16i8 +/* 44639 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 44654 +/* 44644 */ MCD_OPC_CheckPredicate, 3, 59, 165, 0, // Skip to: 86948 +/* 44649 */ MCD_OPC_Decode, 219, 33, 133, 2, // Opcode: URHADDv16i8 +/* 44654 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 44669 +/* 44659 */ MCD_OPC_CheckPredicate, 3, 44, 165, 0, // Skip to: 86948 +/* 44664 */ MCD_OPC_Decode, 245, 5, 133, 2, // Opcode: EORv16i8 +/* 44669 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 44684 +/* 44674 */ MCD_OPC_CheckPredicate, 3, 29, 165, 0, // Skip to: 86948 +/* 44679 */ MCD_OPC_Decode, 226, 31, 133, 2, // Opcode: UHSUBv16i8 +/* 44684 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 44699 +/* 44689 */ MCD_OPC_CheckPredicate, 3, 14, 165, 0, // Skip to: 86948 +/* 44694 */ MCD_OPC_Decode, 197, 33, 133, 2, // Opcode: UQSUBv16i8 +/* 44699 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 44714 +/* 44704 */ MCD_OPC_CheckPredicate, 3, 255, 164, 0, // Skip to: 86948 +/* 44709 */ MCD_OPC_Decode, 230, 3, 133, 2, // Opcode: CMHIv16i8 +/* 44714 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 44729 +/* 44719 */ MCD_OPC_CheckPredicate, 3, 240, 164, 0, // Skip to: 86948 +/* 44724 */ MCD_OPC_Decode, 238, 3, 133, 2, // Opcode: CMHSv16i8 +/* 44729 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 44744 +/* 44734 */ MCD_OPC_CheckPredicate, 3, 225, 164, 0, // Skip to: 86948 +/* 44739 */ MCD_OPC_Decode, 129, 34, 133, 2, // Opcode: USHLv16i8 +/* 44744 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 44759 +/* 44749 */ MCD_OPC_CheckPredicate, 3, 210, 164, 0, // Skip to: 86948 +/* 44754 */ MCD_OPC_Decode, 162, 33, 133, 2, // Opcode: UQSHLv16i8 +/* 44759 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 44774 +/* 44764 */ MCD_OPC_CheckPredicate, 3, 195, 164, 0, // Skip to: 86948 +/* 44769 */ MCD_OPC_Decode, 225, 33, 133, 2, // Opcode: URSHLv16i8 +/* 44774 */ MCD_OPC_FilterValue, 11, 10, 0, 0, // Skip to: 44789 +/* 44779 */ MCD_OPC_CheckPredicate, 3, 180, 164, 0, // Skip to: 86948 +/* 44784 */ MCD_OPC_Decode, 138, 33, 133, 2, // Opcode: UQRSHLv16i8 +/* 44789 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 44804 +/* 44794 */ MCD_OPC_CheckPredicate, 3, 165, 164, 0, // Skip to: 86948 +/* 44799 */ MCD_OPC_Decode, 128, 32, 133, 2, // Opcode: UMAXv16i8 +/* 44804 */ MCD_OPC_FilterValue, 13, 10, 0, 0, // Skip to: 44819 +/* 44809 */ MCD_OPC_CheckPredicate, 3, 150, 164, 0, // Skip to: 86948 +/* 44814 */ MCD_OPC_Decode, 157, 32, 133, 2, // Opcode: UMINv16i8 +/* 44819 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 44834 +/* 44824 */ MCD_OPC_CheckPredicate, 3, 135, 164, 0, // Skip to: 86948 +/* 44829 */ MCD_OPC_Decode, 130, 31, 133, 2, // Opcode: UABDv16i8 +/* 44834 */ MCD_OPC_FilterValue, 15, 125, 164, 0, // Skip to: 86948 +/* 44839 */ MCD_OPC_CheckPredicate, 3, 120, 164, 0, // Skip to: 86948 +/* 44844 */ MCD_OPC_Decode, 242, 30, 141, 2, // Opcode: UABAv16i8 +/* 44849 */ MCD_OPC_FilterValue, 1, 110, 164, 0, // Skip to: 86948 +/* 44854 */ MCD_OPC_ExtractField, 11, 4, // Inst{14-11} ... +/* 44857 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 44879 +/* 44862 */ MCD_OPC_CheckPredicate, 3, 97, 164, 0, // Skip to: 86948 +/* 44867 */ MCD_OPC_CheckField, 21, 1, 1, 90, 164, 0, // Skip to: 86948 +/* 44874 */ MCD_OPC_Decode, 255, 29, 133, 2, // Opcode: SUBv16i8 +/* 44879 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 44901 +/* 44884 */ MCD_OPC_CheckPredicate, 3, 75, 164, 0, // Skip to: 86948 +/* 44889 */ MCD_OPC_CheckField, 21, 1, 1, 68, 164, 0, // Skip to: 86948 +/* 44896 */ MCD_OPC_Decode, 182, 3, 133, 2, // Opcode: CMEQv16i8 +/* 44901 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 44923 +/* 44906 */ MCD_OPC_CheckPredicate, 3, 53, 164, 0, // Skip to: 86948 +/* 44911 */ MCD_OPC_CheckField, 21, 1, 1, 46, 164, 0, // Skip to: 86948 +/* 44918 */ MCD_OPC_Decode, 223, 19, 141, 2, // Opcode: MLSv16i8 +/* 44923 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 44945 +/* 44928 */ MCD_OPC_CheckPredicate, 3, 31, 164, 0, // Skip to: 86948 +/* 44933 */ MCD_OPC_CheckField, 21, 1, 1, 24, 164, 0, // Skip to: 86948 +/* 44940 */ MCD_OPC_Decode, 247, 20, 133, 2, // Opcode: PMULv16i8 +/* 44945 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 44967 +/* 44950 */ MCD_OPC_CheckPredicate, 3, 9, 164, 0, // Skip to: 86948 +/* 44955 */ MCD_OPC_CheckField, 21, 1, 1, 2, 164, 0, // Skip to: 86948 +/* 44962 */ MCD_OPC_Decode, 233, 31, 133, 2, // Opcode: UMAXPv16i8 +/* 44967 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 44989 +/* 44972 */ MCD_OPC_CheckPredicate, 3, 243, 163, 0, // Skip to: 86948 +/* 44977 */ MCD_OPC_CheckField, 21, 1, 1, 236, 163, 0, // Skip to: 86948 +/* 44984 */ MCD_OPC_Decode, 134, 32, 133, 2, // Opcode: UMINPv16i8 +/* 44989 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 45011 +/* 44994 */ MCD_OPC_CheckPredicate, 3, 221, 163, 0, // Skip to: 86948 +/* 44999 */ MCD_OPC_CheckField, 21, 1, 1, 214, 163, 0, // Skip to: 86948 +/* 45006 */ MCD_OPC_Decode, 203, 9, 133, 2, // Opcode: FMAXNMPv4f32 +/* 45011 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 45033 +/* 45016 */ MCD_OPC_CheckPredicate, 3, 199, 163, 0, // Skip to: 86948 +/* 45021 */ MCD_OPC_CheckField, 21, 1, 1, 192, 163, 0, // Skip to: 86948 +/* 45028 */ MCD_OPC_Decode, 183, 6, 133, 2, // Opcode: FADDPv4f32 +/* 45033 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 45055 +/* 45038 */ MCD_OPC_CheckPredicate, 3, 177, 163, 0, // Skip to: 86948 +/* 45043 */ MCD_OPC_CheckField, 21, 1, 1, 170, 163, 0, // Skip to: 86948 +/* 45050 */ MCD_OPC_Decode, 159, 11, 133, 2, // Opcode: FMULv4f32 +/* 45055 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 45077 +/* 45060 */ MCD_OPC_CheckPredicate, 3, 155, 163, 0, // Skip to: 86948 +/* 45065 */ MCD_OPC_CheckField, 21, 1, 1, 148, 163, 0, // Skip to: 86948 +/* 45072 */ MCD_OPC_Decode, 128, 7, 133, 2, // Opcode: FCMGEv4f32 +/* 45077 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 45099 +/* 45082 */ MCD_OPC_CheckPredicate, 3, 133, 163, 0, // Skip to: 86948 +/* 45087 */ MCD_OPC_CheckField, 21, 1, 1, 126, 163, 0, // Skip to: 86948 +/* 45094 */ MCD_OPC_Decode, 159, 6, 133, 2, // Opcode: FACGEv4f32 +/* 45099 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 45121 +/* 45104 */ MCD_OPC_CheckPredicate, 3, 111, 163, 0, // Skip to: 86948 +/* 45109 */ MCD_OPC_CheckField, 21, 1, 1, 104, 163, 0, // Skip to: 86948 +/* 45116 */ MCD_OPC_Decode, 229, 9, 133, 2, // Opcode: FMAXPv4f32 +/* 45121 */ MCD_OPC_FilterValue, 15, 94, 163, 0, // Skip to: 86948 +/* 45126 */ MCD_OPC_CheckPredicate, 3, 89, 163, 0, // Skip to: 86948 +/* 45131 */ MCD_OPC_CheckField, 21, 1, 1, 82, 163, 0, // Skip to: 86948 +/* 45138 */ MCD_OPC_Decode, 178, 9, 133, 2, // Opcode: FDIVv4f32 +/* 45143 */ MCD_OPC_FilterValue, 6, 72, 163, 0, // Skip to: 86948 +/* 45148 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45151 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 45173 +/* 45156 */ MCD_OPC_CheckPredicate, 6, 59, 163, 0, // Skip to: 86948 +/* 45161 */ MCD_OPC_CheckField, 15, 1, 0, 52, 163, 0, // Skip to: 86948 +/* 45168 */ MCD_OPC_Decode, 226, 5, 165, 2, // Opcode: EOR3 +/* 45173 */ MCD_OPC_FilterValue, 1, 42, 163, 0, // Skip to: 86948 +/* 45178 */ MCD_OPC_CheckPredicate, 6, 37, 163, 0, // Skip to: 86948 +/* 45183 */ MCD_OPC_CheckField, 15, 1, 0, 30, 163, 0, // Skip to: 86948 +/* 45190 */ MCD_OPC_Decode, 169, 2, 165, 2, // Opcode: BCAX +/* 45195 */ MCD_OPC_FilterValue, 9, 131, 26, 0, // Skip to: 51987 +/* 45200 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 45203 */ MCD_OPC_FilterValue, 0, 4, 6, 0, // Skip to: 46748 +/* 45208 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 45211 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 45233 +/* 45216 */ MCD_OPC_CheckPredicate, 3, 255, 162, 0, // Skip to: 86948 +/* 45221 */ MCD_OPC_CheckField, 21, 1, 1, 248, 162, 0, // Skip to: 86948 +/* 45228 */ MCD_OPC_Decode, 165, 22, 234, 1, // Opcode: SADDLv4i16_v4i32 +/* 45233 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 45271 +/* 45238 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45241 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45256 +/* 45246 */ MCD_OPC_CheckPredicate, 4, 225, 162, 0, // Skip to: 86948 +/* 45251 */ MCD_OPC_Decode, 220, 9, 238, 1, // Opcode: FMAXNMv4f16 +/* 45256 */ MCD_OPC_FilterValue, 1, 215, 162, 0, // Skip to: 86948 +/* 45261 */ MCD_OPC_CheckPredicate, 3, 210, 162, 0, // Skip to: 86948 +/* 45266 */ MCD_OPC_Decode, 129, 23, 238, 1, // Opcode: SHADDv4i16 +/* 45271 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 45293 +/* 45276 */ MCD_OPC_CheckPredicate, 3, 195, 162, 0, // Skip to: 86948 +/* 45281 */ MCD_OPC_CheckField, 16, 6, 32, 188, 162, 0, // Skip to: 86948 +/* 45288 */ MCD_OPC_Decode, 211, 21, 239, 1, // Opcode: REV64v4i16 +/* 45293 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 45331 +/* 45298 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45301 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45316 +/* 45306 */ MCD_OPC_CheckPredicate, 4, 165, 162, 0, // Skip to: 86948 +/* 45311 */ MCD_OPC_Decode, 190, 10, 130, 2, // Opcode: FMLAv4f16 +/* 45316 */ MCD_OPC_FilterValue, 1, 155, 162, 0, // Skip to: 86948 +/* 45321 */ MCD_OPC_CheckPredicate, 3, 150, 162, 0, // Skip to: 86948 +/* 45326 */ MCD_OPC_Decode, 179, 24, 238, 1, // Opcode: SQADDv4i16 +/* 45331 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 45353 +/* 45336 */ MCD_OPC_CheckPredicate, 3, 135, 162, 0, // Skip to: 86948 +/* 45341 */ MCD_OPC_CheckField, 21, 1, 1, 128, 162, 0, // Skip to: 86948 +/* 45348 */ MCD_OPC_Decode, 174, 22, 242, 1, // Opcode: SADDWv4i16_v4i32 +/* 45353 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 45391 +/* 45358 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45361 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45376 +/* 45366 */ MCD_OPC_CheckPredicate, 4, 105, 162, 0, // Skip to: 86948 +/* 45371 */ MCD_OPC_Decode, 200, 6, 238, 1, // Opcode: FADDv4f16 +/* 45376 */ MCD_OPC_FilterValue, 1, 95, 162, 0, // Skip to: 86948 +/* 45381 */ MCD_OPC_CheckPredicate, 3, 90, 162, 0, // Skip to: 86948 +/* 45386 */ MCD_OPC_Decode, 185, 26, 238, 1, // Opcode: SRHADDv4i16 +/* 45391 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 45413 +/* 45396 */ MCD_OPC_CheckPredicate, 3, 75, 162, 0, // Skip to: 86948 +/* 45401 */ MCD_OPC_CheckField, 21, 1, 0, 68, 162, 0, // Skip to: 86948 +/* 45408 */ MCD_OPC_Decode, 199, 34, 238, 1, // Opcode: UZP1v4i16 +/* 45413 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 45451 +/* 45418 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45421 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45436 +/* 45426 */ MCD_OPC_CheckPredicate, 4, 45, 162, 0, // Skip to: 86948 +/* 45431 */ MCD_OPC_Decode, 133, 11, 238, 1, // Opcode: FMULXv4f16 +/* 45436 */ MCD_OPC_FilterValue, 1, 35, 162, 0, // Skip to: 86948 +/* 45441 */ MCD_OPC_CheckPredicate, 3, 30, 162, 0, // Skip to: 86948 +/* 45446 */ MCD_OPC_Decode, 192, 2, 238, 1, // Opcode: BICv8i8 +/* 45451 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 45473 +/* 45456 */ MCD_OPC_CheckPredicate, 3, 15, 162, 0, // Skip to: 86948 +/* 45461 */ MCD_OPC_CheckField, 21, 1, 1, 8, 162, 0, // Skip to: 86948 +/* 45468 */ MCD_OPC_Decode, 163, 27, 234, 1, // Opcode: SSUBLv4i16_v4i32 +/* 45473 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 45511 +/* 45478 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45481 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45496 +/* 45486 */ MCD_OPC_CheckPredicate, 4, 241, 161, 0, // Skip to: 86948 +/* 45491 */ MCD_OPC_Decode, 233, 6, 238, 1, // Opcode: FCMEQv4f16 +/* 45496 */ MCD_OPC_FilterValue, 1, 231, 161, 0, // Skip to: 86948 +/* 45501 */ MCD_OPC_CheckPredicate, 3, 226, 161, 0, // Skip to: 86948 +/* 45506 */ MCD_OPC_Decode, 155, 23, 238, 1, // Opcode: SHSUBv4i16 +/* 45511 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 45572 +/* 45516 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45519 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45534 +/* 45524 */ MCD_OPC_CheckPredicate, 3, 203, 161, 0, // Skip to: 86948 +/* 45529 */ MCD_OPC_Decode, 216, 30, 238, 1, // Opcode: TRN1v4i16 +/* 45534 */ MCD_OPC_FilterValue, 1, 193, 161, 0, // Skip to: 86948 +/* 45539 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 45542 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45557 +/* 45547 */ MCD_OPC_CheckPredicate, 3, 180, 161, 0, // Skip to: 86948 +/* 45552 */ MCD_OPC_Decode, 154, 22, 239, 1, // Opcode: SADDLPv4i16_v2i32 +/* 45557 */ MCD_OPC_FilterValue, 1, 170, 161, 0, // Skip to: 86948 +/* 45562 */ MCD_OPC_CheckPredicate, 3, 165, 161, 0, // Skip to: 86948 +/* 45567 */ MCD_OPC_Decode, 129, 35, 244, 1, // Opcode: XTNv4i16 +/* 45572 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 45594 +/* 45577 */ MCD_OPC_CheckPredicate, 3, 150, 161, 0, // Skip to: 86948 +/* 45582 */ MCD_OPC_CheckField, 21, 1, 1, 143, 161, 0, // Skip to: 86948 +/* 45589 */ MCD_OPC_Decode, 161, 26, 238, 1, // Opcode: SQSUBv4i16 +/* 45594 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 45616 +/* 45599 */ MCD_OPC_CheckPredicate, 3, 128, 161, 0, // Skip to: 86948 +/* 45604 */ MCD_OPC_CheckField, 21, 1, 1, 121, 161, 0, // Skip to: 86948 +/* 45611 */ MCD_OPC_Decode, 169, 27, 242, 1, // Opcode: SSUBWv4i16_v4i32 +/* 45616 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 45654 +/* 45621 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45624 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45639 +/* 45629 */ MCD_OPC_CheckPredicate, 4, 98, 161, 0, // Skip to: 86948 +/* 45634 */ MCD_OPC_Decode, 246, 9, 238, 1, // Opcode: FMAXv4f16 +/* 45639 */ MCD_OPC_FilterValue, 1, 88, 161, 0, // Skip to: 86948 +/* 45644 */ MCD_OPC_CheckPredicate, 3, 83, 161, 0, // Skip to: 86948 +/* 45649 */ MCD_OPC_Decode, 222, 3, 238, 1, // Opcode: CMGTv4i16 +/* 45654 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 45715 +/* 45659 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45662 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45677 +/* 45667 */ MCD_OPC_CheckPredicate, 3, 60, 161, 0, // Skip to: 86948 +/* 45672 */ MCD_OPC_Decode, 144, 35, 238, 1, // Opcode: ZIP1v4i16 +/* 45677 */ MCD_OPC_FilterValue, 1, 50, 161, 0, // Skip to: 86948 +/* 45682 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 45685 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45700 +/* 45690 */ MCD_OPC_CheckPredicate, 3, 37, 161, 0, // Skip to: 86948 +/* 45695 */ MCD_OPC_Decode, 148, 30, 248, 1, // Opcode: SUQADDv4i16 +/* 45700 */ MCD_OPC_FilterValue, 16, 27, 161, 0, // Skip to: 86948 +/* 45705 */ MCD_OPC_CheckPredicate, 3, 22, 161, 0, // Skip to: 86948 +/* 45710 */ MCD_OPC_Decode, 159, 22, 166, 2, // Opcode: SADDLVv4i16v +/* 45715 */ MCD_OPC_FilterValue, 15, 33, 0, 0, // Skip to: 45753 +/* 45720 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45723 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 45738 +/* 45728 */ MCD_OPC_CheckPredicate, 4, 255, 160, 0, // Skip to: 86948 +/* 45733 */ MCD_OPC_Decode, 215, 11, 238, 1, // Opcode: FRECPSv4f16 +/* 45738 */ MCD_OPC_FilterValue, 1, 245, 160, 0, // Skip to: 86948 +/* 45743 */ MCD_OPC_CheckPredicate, 3, 240, 160, 0, // Skip to: 86948 +/* 45748 */ MCD_OPC_Decode, 206, 3, 238, 1, // Opcode: CMGEv4i16 +/* 45753 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 45775 +/* 45758 */ MCD_OPC_CheckPredicate, 3, 225, 160, 0, // Skip to: 86948 +/* 45763 */ MCD_OPC_CheckField, 21, 1, 1, 218, 160, 0, // Skip to: 86948 +/* 45770 */ MCD_OPC_Decode, 144, 1, 252, 1, // Opcode: ADDHNv4i32_v4i16 +/* 45775 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 45797 +/* 45780 */ MCD_OPC_CheckPredicate, 3, 203, 160, 0, // Skip to: 86948 +/* 45785 */ MCD_OPC_CheckField, 21, 1, 1, 196, 160, 0, // Skip to: 86948 +/* 45792 */ MCD_OPC_Decode, 231, 26, 238, 1, // Opcode: SSHLv4i16 +/* 45797 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 45835 +/* 45802 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 45805 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 45820 +/* 45810 */ MCD_OPC_CheckPredicate, 3, 173, 160, 0, // Skip to: 86948 +/* 45815 */ MCD_OPC_Decode, 166, 3, 239, 1, // Opcode: CLSv4i16 +/* 45820 */ MCD_OPC_FilterValue, 33, 163, 160, 0, // Skip to: 86948 +/* 45825 */ MCD_OPC_CheckPredicate, 3, 158, 160, 0, // Skip to: 86948 +/* 45830 */ MCD_OPC_Decode, 170, 26, 244, 1, // Opcode: SQXTNv4i16 +/* 45835 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 45857 +/* 45840 */ MCD_OPC_CheckPredicate, 3, 143, 160, 0, // Skip to: 86948 +/* 45845 */ MCD_OPC_CheckField, 21, 1, 1, 136, 160, 0, // Skip to: 86948 +/* 45852 */ MCD_OPC_Decode, 248, 25, 238, 1, // Opcode: SQSHLv4i16 +/* 45857 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 45879 +/* 45862 */ MCD_OPC_CheckPredicate, 3, 121, 160, 0, // Skip to: 86948 +/* 45867 */ MCD_OPC_CheckField, 21, 1, 1, 114, 160, 0, // Skip to: 86948 +/* 45874 */ MCD_OPC_Decode, 248, 21, 254, 1, // Opcode: SABALv4i16_v4i32 +/* 45879 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 45901 +/* 45884 */ MCD_OPC_CheckPredicate, 3, 99, 160, 0, // Skip to: 86948 +/* 45889 */ MCD_OPC_CheckField, 21, 1, 1, 92, 160, 0, // Skip to: 86948 +/* 45896 */ MCD_OPC_Decode, 201, 26, 238, 1, // Opcode: SRSHLv4i16 +/* 45901 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 45923 +/* 45906 */ MCD_OPC_CheckPredicate, 3, 77, 160, 0, // Skip to: 86948 +/* 45911 */ MCD_OPC_CheckField, 21, 1, 0, 70, 160, 0, // Skip to: 86948 +/* 45918 */ MCD_OPC_Decode, 214, 34, 238, 1, // Opcode: UZP2v4i16 +/* 45923 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 45945 +/* 45928 */ MCD_OPC_CheckPredicate, 3, 55, 160, 0, // Skip to: 86948 +/* 45933 */ MCD_OPC_CheckField, 21, 1, 1, 48, 160, 0, // Skip to: 86948 +/* 45940 */ MCD_OPC_Decode, 201, 25, 238, 1, // Opcode: SQRSHLv4i16 +/* 45945 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 45967 +/* 45950 */ MCD_OPC_CheckPredicate, 3, 33, 160, 0, // Skip to: 86948 +/* 45955 */ MCD_OPC_CheckField, 21, 1, 1, 26, 160, 0, // Skip to: 86948 +/* 45962 */ MCD_OPC_Decode, 213, 29, 252, 1, // Opcode: SUBHNv4i32_v4i16 +/* 45967 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 45989 +/* 45972 */ MCD_OPC_CheckPredicate, 3, 11, 160, 0, // Skip to: 86948 +/* 45977 */ MCD_OPC_CheckField, 21, 1, 1, 4, 160, 0, // Skip to: 86948 +/* 45984 */ MCD_OPC_Decode, 202, 23, 238, 1, // Opcode: SMAXv4i16 +/* 45989 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 46050 +/* 45994 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 45997 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46012 +/* 46002 */ MCD_OPC_CheckPredicate, 3, 237, 159, 0, // Skip to: 86948 +/* 46007 */ MCD_OPC_Decode, 231, 30, 238, 1, // Opcode: TRN2v4i16 +/* 46012 */ MCD_OPC_FilterValue, 1, 227, 159, 0, // Skip to: 86948 +/* 46017 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 46020 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46035 +/* 46025 */ MCD_OPC_CheckPredicate, 3, 214, 159, 0, // Skip to: 86948 +/* 46030 */ MCD_OPC_Decode, 148, 22, 248, 1, // Opcode: SADALPv4i16_v2i32 +/* 46035 */ MCD_OPC_FilterValue, 1, 204, 159, 0, // Skip to: 86948 +/* 46040 */ MCD_OPC_CheckPredicate, 3, 199, 159, 0, // Skip to: 86948 +/* 46045 */ MCD_OPC_Decode, 181, 8, 244, 1, // Opcode: FCVTNv2i32 +/* 46050 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 46072 +/* 46055 */ MCD_OPC_CheckPredicate, 3, 184, 159, 0, // Skip to: 86948 +/* 46060 */ MCD_OPC_CheckField, 21, 1, 1, 177, 159, 0, // Skip to: 86948 +/* 46067 */ MCD_OPC_Decode, 232, 23, 238, 1, // Opcode: SMINv4i16 +/* 46072 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 46094 +/* 46077 */ MCD_OPC_CheckPredicate, 3, 162, 159, 0, // Skip to: 86948 +/* 46082 */ MCD_OPC_CheckField, 21, 1, 1, 155, 159, 0, // Skip to: 86948 +/* 46089 */ MCD_OPC_Decode, 132, 22, 234, 1, // Opcode: SABDLv4i16_v4i32 +/* 46094 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 46116 +/* 46099 */ MCD_OPC_CheckPredicate, 3, 140, 159, 0, // Skip to: 86948 +/* 46104 */ MCD_OPC_CheckField, 21, 1, 1, 133, 159, 0, // Skip to: 86948 +/* 46111 */ MCD_OPC_Decode, 142, 22, 238, 1, // Opcode: SABDv4i16 +/* 46116 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 46177 +/* 46121 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 46124 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46139 +/* 46129 */ MCD_OPC_CheckPredicate, 3, 110, 159, 0, // Skip to: 86948 +/* 46134 */ MCD_OPC_Decode, 159, 35, 238, 1, // Opcode: ZIP2v4i16 +/* 46139 */ MCD_OPC_FilterValue, 1, 100, 159, 0, // Skip to: 86948 +/* 46144 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 46147 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46162 +/* 46152 */ MCD_OPC_CheckPredicate, 3, 87, 159, 0, // Skip to: 86948 +/* 46157 */ MCD_OPC_Decode, 160, 24, 239, 1, // Opcode: SQABSv4i16 +/* 46162 */ MCD_OPC_FilterValue, 1, 77, 159, 0, // Skip to: 86948 +/* 46167 */ MCD_OPC_CheckPredicate, 3, 72, 159, 0, // Skip to: 86948 +/* 46172 */ MCD_OPC_Decode, 249, 7, 129, 2, // Opcode: FCVTLv2i32 +/* 46177 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 46199 +/* 46182 */ MCD_OPC_CheckPredicate, 3, 57, 159, 0, // Skip to: 86948 +/* 46187 */ MCD_OPC_CheckField, 21, 1, 1, 50, 159, 0, // Skip to: 86948 +/* 46194 */ MCD_OPC_Decode, 254, 21, 130, 2, // Opcode: SABAv4i16 +/* 46199 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 46221 +/* 46204 */ MCD_OPC_CheckPredicate, 3, 35, 159, 0, // Skip to: 86948 +/* 46209 */ MCD_OPC_CheckField, 21, 1, 1, 28, 159, 0, // Skip to: 86948 +/* 46216 */ MCD_OPC_Decode, 240, 23, 254, 1, // Opcode: SMLALv4i16_v4i32 +/* 46221 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 46243 +/* 46226 */ MCD_OPC_CheckPredicate, 3, 13, 159, 0, // Skip to: 86948 +/* 46231 */ MCD_OPC_CheckField, 21, 1, 1, 6, 159, 0, // Skip to: 86948 +/* 46238 */ MCD_OPC_Decode, 198, 1, 238, 1, // Opcode: ADDv4i16 +/* 46243 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 46281 +/* 46248 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 46251 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46266 +/* 46256 */ MCD_OPC_CheckPredicate, 3, 239, 158, 0, // Skip to: 86948 +/* 46261 */ MCD_OPC_Decode, 223, 3, 239, 1, // Opcode: CMGTv4i16rz +/* 46266 */ MCD_OPC_FilterValue, 57, 229, 158, 0, // Skip to: 86948 +/* 46271 */ MCD_OPC_CheckPredicate, 4, 224, 158, 0, // Skip to: 86948 +/* 46276 */ MCD_OPC_Decode, 137, 12, 239, 1, // Opcode: FRINTNv4f16 +/* 46281 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 46303 +/* 46286 */ MCD_OPC_CheckPredicate, 3, 209, 158, 0, // Skip to: 86948 +/* 46291 */ MCD_OPC_CheckField, 21, 1, 1, 202, 158, 0, // Skip to: 86948 +/* 46298 */ MCD_OPC_Decode, 237, 4, 238, 1, // Opcode: CMTSTv4i16 +/* 46303 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 46325 +/* 46308 */ MCD_OPC_CheckPredicate, 3, 187, 158, 0, // Skip to: 86948 +/* 46313 */ MCD_OPC_CheckField, 21, 1, 1, 180, 158, 0, // Skip to: 86948 +/* 46320 */ MCD_OPC_Decode, 212, 24, 254, 1, // Opcode: SQDMLALv4i16_v4i32 +/* 46325 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 46347 +/* 46330 */ MCD_OPC_CheckPredicate, 3, 165, 158, 0, // Skip to: 86948 +/* 46335 */ MCD_OPC_CheckField, 21, 1, 1, 158, 158, 0, // Skip to: 86948 +/* 46342 */ MCD_OPC_Decode, 212, 19, 130, 2, // Opcode: MLAv4i16 +/* 46347 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 46385 +/* 46352 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 46355 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46370 +/* 46360 */ MCD_OPC_CheckPredicate, 3, 135, 158, 0, // Skip to: 86948 +/* 46365 */ MCD_OPC_Decode, 191, 3, 239, 1, // Opcode: CMEQv4i16rz +/* 46370 */ MCD_OPC_FilterValue, 57, 125, 158, 0, // Skip to: 86948 +/* 46375 */ MCD_OPC_CheckPredicate, 4, 120, 158, 0, // Skip to: 86948 +/* 46380 */ MCD_OPC_Decode, 254, 11, 239, 1, // Opcode: FRINTMv4f16 +/* 46385 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 46407 +/* 46390 */ MCD_OPC_CheckPredicate, 3, 105, 158, 0, // Skip to: 86948 +/* 46395 */ MCD_OPC_CheckField, 21, 1, 1, 98, 158, 0, // Skip to: 86948 +/* 46402 */ MCD_OPC_Decode, 160, 20, 238, 1, // Opcode: MULv4i16 +/* 46407 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 46429 +/* 46412 */ MCD_OPC_CheckPredicate, 3, 83, 158, 0, // Skip to: 86948 +/* 46417 */ MCD_OPC_CheckField, 21, 1, 1, 76, 158, 0, // Skip to: 86948 +/* 46424 */ MCD_OPC_Decode, 250, 23, 254, 1, // Opcode: SMLSLv4i16_v4i32 +/* 46429 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 46451 +/* 46434 */ MCD_OPC_CheckPredicate, 3, 61, 158, 0, // Skip to: 86948 +/* 46439 */ MCD_OPC_CheckField, 21, 1, 1, 54, 158, 0, // Skip to: 86948 +/* 46446 */ MCD_OPC_Decode, 179, 23, 238, 1, // Opcode: SMAXPv4i16 +/* 46451 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 46519 +/* 46456 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 46459 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46474 +/* 46464 */ MCD_OPC_CheckPredicate, 3, 31, 158, 0, // Skip to: 86948 +/* 46469 */ MCD_OPC_Decode, 130, 4, 239, 1, // Opcode: CMLTv4i16rz +/* 46474 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 46489 +/* 46479 */ MCD_OPC_CheckPredicate, 3, 16, 158, 0, // Skip to: 86948 +/* 46484 */ MCD_OPC_Decode, 188, 23, 249, 1, // Opcode: SMAXVv4i16v +/* 46489 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 46504 +/* 46494 */ MCD_OPC_CheckPredicate, 3, 1, 158, 0, // Skip to: 86948 +/* 46499 */ MCD_OPC_Decode, 218, 23, 249, 1, // Opcode: SMINVv4i16v +/* 46504 */ MCD_OPC_FilterValue, 57, 247, 157, 0, // Skip to: 86948 +/* 46509 */ MCD_OPC_CheckPredicate, 4, 242, 157, 0, // Skip to: 86948 +/* 46514 */ MCD_OPC_Decode, 164, 8, 239, 1, // Opcode: FCVTNSv4f16 +/* 46519 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 46541 +/* 46524 */ MCD_OPC_CheckPredicate, 3, 227, 157, 0, // Skip to: 86948 +/* 46529 */ MCD_OPC_CheckField, 21, 1, 1, 220, 157, 0, // Skip to: 86948 +/* 46536 */ MCD_OPC_Decode, 209, 23, 238, 1, // Opcode: SMINPv4i16 +/* 46541 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 46563 +/* 46546 */ MCD_OPC_CheckPredicate, 3, 205, 157, 0, // Skip to: 86948 +/* 46551 */ MCD_OPC_CheckField, 21, 1, 1, 198, 157, 0, // Skip to: 86948 +/* 46558 */ MCD_OPC_Decode, 224, 24, 254, 1, // Opcode: SQDMLSLv4i16_v4i32 +/* 46563 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 46585 +/* 46568 */ MCD_OPC_CheckPredicate, 3, 183, 157, 0, // Skip to: 86948 +/* 46573 */ MCD_OPC_CheckField, 21, 1, 1, 176, 157, 0, // Skip to: 86948 +/* 46580 */ MCD_OPC_Decode, 235, 24, 238, 1, // Opcode: SQDMULHv4i16 +/* 46585 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 46638 +/* 46590 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 46593 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 46608 +/* 46598 */ MCD_OPC_CheckPredicate, 3, 153, 157, 0, // Skip to: 86948 +/* 46603 */ MCD_OPC_Decode, 134, 1, 239, 1, // Opcode: ABSv4i16 +/* 46608 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 46623 +/* 46613 */ MCD_OPC_CheckPredicate, 3, 138, 157, 0, // Skip to: 86948 +/* 46618 */ MCD_OPC_Decode, 168, 1, 249, 1, // Opcode: ADDVv4i16v +/* 46623 */ MCD_OPC_FilterValue, 57, 128, 157, 0, // Skip to: 86948 +/* 46628 */ MCD_OPC_CheckPredicate, 4, 123, 157, 0, // Skip to: 86948 +/* 46633 */ MCD_OPC_Decode, 136, 8, 239, 1, // Opcode: FCVTMSv4f16 +/* 46638 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 46660 +/* 46643 */ MCD_OPC_CheckPredicate, 3, 108, 157, 0, // Skip to: 86948 +/* 46648 */ MCD_OPC_CheckField, 21, 1, 1, 101, 157, 0, // Skip to: 86948 +/* 46655 */ MCD_OPC_Decode, 153, 1, 238, 1, // Opcode: ADDPv4i16 +/* 46660 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 46682 +/* 46665 */ MCD_OPC_CheckPredicate, 3, 86, 157, 0, // Skip to: 86948 +/* 46670 */ MCD_OPC_CheckField, 21, 1, 1, 79, 157, 0, // Skip to: 86948 +/* 46677 */ MCD_OPC_Decode, 143, 24, 234, 1, // Opcode: SMULLv4i16_v4i32 +/* 46682 */ MCD_OPC_FilterValue, 50, 17, 0, 0, // Skip to: 46704 +/* 46687 */ MCD_OPC_CheckPredicate, 4, 64, 157, 0, // Skip to: 86948 +/* 46692 */ MCD_OPC_CheckField, 16, 6, 57, 57, 157, 0, // Skip to: 86948 +/* 46699 */ MCD_OPC_Decode, 228, 7, 239, 1, // Opcode: FCVTASv4f16 +/* 46704 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 46726 +/* 46709 */ MCD_OPC_CheckPredicate, 3, 42, 157, 0, // Skip to: 86948 +/* 46714 */ MCD_OPC_CheckField, 21, 1, 1, 35, 157, 0, // Skip to: 86948 +/* 46721 */ MCD_OPC_Decode, 248, 24, 234, 1, // Opcode: SQDMULLv4i16_v4i32 +/* 46726 */ MCD_OPC_FilterValue, 54, 25, 157, 0, // Skip to: 86948 +/* 46731 */ MCD_OPC_CheckPredicate, 4, 20, 157, 0, // Skip to: 86948 +/* 46736 */ MCD_OPC_CheckField, 16, 6, 57, 13, 157, 0, // Skip to: 86948 +/* 46743 */ MCD_OPC_Decode, 213, 22, 239, 1, // Opcode: SCVTFv4f16 +/* 46748 */ MCD_OPC_FilterValue, 1, 152, 5, 0, // Skip to: 48185 +/* 46753 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 46756 */ MCD_OPC_FilterValue, 0, 205, 0, 0, // Skip to: 46966 +/* 46761 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 46764 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 46786 +/* 46769 */ MCD_OPC_CheckPredicate, 3, 238, 156, 0, // Skip to: 86948 +/* 46774 */ MCD_OPC_CheckField, 21, 1, 1, 231, 156, 0, // Skip to: 86948 +/* 46781 */ MCD_OPC_Decode, 155, 31, 234, 1, // Opcode: UADDLv4i16_v4i32 +/* 46786 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 46824 +/* 46791 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 46794 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46809 +/* 46799 */ MCD_OPC_CheckPredicate, 4, 208, 156, 0, // Skip to: 86948 +/* 46804 */ MCD_OPC_Decode, 202, 9, 238, 1, // Opcode: FMAXNMPv4f16 +/* 46809 */ MCD_OPC_FilterValue, 1, 198, 156, 0, // Skip to: 86948 +/* 46814 */ MCD_OPC_CheckPredicate, 3, 193, 156, 0, // Skip to: 86948 +/* 46819 */ MCD_OPC_Decode, 222, 31, 238, 1, // Opcode: UHADDv4i16 +/* 46824 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 46846 +/* 46829 */ MCD_OPC_CheckPredicate, 3, 178, 156, 0, // Skip to: 86948 +/* 46834 */ MCD_OPC_CheckField, 16, 6, 32, 171, 156, 0, // Skip to: 86948 +/* 46841 */ MCD_OPC_Decode, 206, 21, 239, 1, // Opcode: REV32v4i16 +/* 46846 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 46868 +/* 46851 */ MCD_OPC_CheckPredicate, 3, 156, 156, 0, // Skip to: 86948 +/* 46856 */ MCD_OPC_CheckField, 21, 1, 1, 149, 156, 0, // Skip to: 86948 +/* 46863 */ MCD_OPC_Decode, 218, 32, 238, 1, // Opcode: UQADDv4i16 +/* 46868 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 46890 +/* 46873 */ MCD_OPC_CheckPredicate, 3, 134, 156, 0, // Skip to: 86948 +/* 46878 */ MCD_OPC_CheckField, 21, 1, 1, 127, 156, 0, // Skip to: 86948 +/* 46885 */ MCD_OPC_Decode, 165, 31, 242, 1, // Opcode: UADDWv4i16_v4i32 +/* 46890 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 46928 +/* 46895 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 46898 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46913 +/* 46903 */ MCD_OPC_CheckPredicate, 4, 104, 156, 0, // Skip to: 86948 +/* 46908 */ MCD_OPC_Decode, 182, 6, 238, 1, // Opcode: FADDPv4f16 +/* 46913 */ MCD_OPC_FilterValue, 1, 94, 156, 0, // Skip to: 86948 +/* 46918 */ MCD_OPC_CheckPredicate, 3, 89, 156, 0, // Skip to: 86948 +/* 46923 */ MCD_OPC_Decode, 221, 33, 238, 1, // Opcode: URHADDv4i16 +/* 46928 */ MCD_OPC_FilterValue, 7, 79, 156, 0, // Skip to: 86948 +/* 46933 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 46936 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 46951 +/* 46941 */ MCD_OPC_CheckPredicate, 4, 66, 156, 0, // Skip to: 86948 +/* 46946 */ MCD_OPC_Decode, 158, 11, 238, 1, // Opcode: FMULv4f16 +/* 46951 */ MCD_OPC_FilterValue, 1, 56, 156, 0, // Skip to: 86948 +/* 46956 */ MCD_OPC_CheckPredicate, 3, 51, 156, 0, // Skip to: 86948 +/* 46961 */ MCD_OPC_Decode, 222, 2, 130, 2, // Opcode: BSLv8i8 +/* 46966 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 47261 +/* 46971 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 46974 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 46996 +/* 46979 */ MCD_OPC_CheckPredicate, 3, 28, 156, 0, // Skip to: 86948 +/* 46984 */ MCD_OPC_CheckField, 21, 1, 1, 21, 156, 0, // Skip to: 86948 +/* 46991 */ MCD_OPC_Decode, 166, 34, 234, 1, // Opcode: USUBLv4i16_v4i32 +/* 46996 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 47034 +/* 47001 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 47004 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47019 +/* 47009 */ MCD_OPC_CheckPredicate, 4, 254, 155, 0, // Skip to: 86948 +/* 47014 */ MCD_OPC_Decode, 255, 6, 238, 1, // Opcode: FCMGEv4f16 +/* 47019 */ MCD_OPC_FilterValue, 1, 244, 155, 0, // Skip to: 86948 +/* 47024 */ MCD_OPC_CheckPredicate, 3, 239, 155, 0, // Skip to: 86948 +/* 47029 */ MCD_OPC_Decode, 228, 31, 238, 1, // Opcode: UHSUBv4i16 +/* 47034 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47072 +/* 47039 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47042 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47057 +/* 47047 */ MCD_OPC_CheckPredicate, 3, 216, 155, 0, // Skip to: 86948 +/* 47052 */ MCD_OPC_Decode, 144, 31, 239, 1, // Opcode: UADDLPv4i16_v2i32 +/* 47057 */ MCD_OPC_FilterValue, 33, 206, 155, 0, // Skip to: 86948 +/* 47062 */ MCD_OPC_CheckPredicate, 3, 201, 155, 0, // Skip to: 86948 +/* 47067 */ MCD_OPC_Decode, 179, 26, 244, 1, // Opcode: SQXTUNv4i16 +/* 47072 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 47110 +/* 47077 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 47080 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47095 +/* 47085 */ MCD_OPC_CheckPredicate, 4, 178, 155, 0, // Skip to: 86948 +/* 47090 */ MCD_OPC_Decode, 158, 6, 238, 1, // Opcode: FACGEv4f16 +/* 47095 */ MCD_OPC_FilterValue, 1, 168, 155, 0, // Skip to: 86948 +/* 47100 */ MCD_OPC_CheckPredicate, 3, 163, 155, 0, // Skip to: 86948 +/* 47105 */ MCD_OPC_Decode, 204, 33, 238, 1, // Opcode: UQSUBv4i16 +/* 47110 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47132 +/* 47115 */ MCD_OPC_CheckPredicate, 3, 148, 155, 0, // Skip to: 86948 +/* 47120 */ MCD_OPC_CheckField, 21, 1, 1, 141, 155, 0, // Skip to: 86948 +/* 47127 */ MCD_OPC_Decode, 172, 34, 242, 1, // Opcode: USUBWv4i16_v4i32 +/* 47132 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 47170 +/* 47137 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 47140 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47155 +/* 47145 */ MCD_OPC_CheckPredicate, 4, 118, 155, 0, // Skip to: 86948 +/* 47150 */ MCD_OPC_Decode, 228, 9, 238, 1, // Opcode: FMAXPv4f16 +/* 47155 */ MCD_OPC_FilterValue, 1, 108, 155, 0, // Skip to: 86948 +/* 47160 */ MCD_OPC_CheckPredicate, 3, 103, 155, 0, // Skip to: 86948 +/* 47165 */ MCD_OPC_Decode, 234, 3, 238, 1, // Opcode: CMHIv4i16 +/* 47170 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 47223 +/* 47175 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47178 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47193 +/* 47183 */ MCD_OPC_CheckPredicate, 3, 80, 155, 0, // Skip to: 86948 +/* 47188 */ MCD_OPC_Decode, 152, 34, 248, 1, // Opcode: USQADDv4i16 +/* 47193 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 47208 +/* 47198 */ MCD_OPC_CheckPredicate, 3, 65, 155, 0, // Skip to: 86948 +/* 47203 */ MCD_OPC_Decode, 135, 23, 129, 2, // Opcode: SHLLv4i16 +/* 47208 */ MCD_OPC_FilterValue, 48, 55, 155, 0, // Skip to: 86948 +/* 47213 */ MCD_OPC_CheckPredicate, 3, 50, 155, 0, // Skip to: 86948 +/* 47218 */ MCD_OPC_Decode, 149, 31, 166, 2, // Opcode: UADDLVv4i16v +/* 47223 */ MCD_OPC_FilterValue, 7, 40, 155, 0, // Skip to: 86948 +/* 47228 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 47231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47246 +/* 47236 */ MCD_OPC_CheckPredicate, 4, 27, 155, 0, // Skip to: 86948 +/* 47241 */ MCD_OPC_Decode, 177, 9, 238, 1, // Opcode: FDIVv4f16 +/* 47246 */ MCD_OPC_FilterValue, 1, 17, 155, 0, // Skip to: 86948 +/* 47251 */ MCD_OPC_CheckPredicate, 3, 12, 155, 0, // Skip to: 86948 +/* 47256 */ MCD_OPC_Decode, 242, 3, 238, 1, // Opcode: CMHSv4i16 +/* 47261 */ MCD_OPC_FilterValue, 2, 195, 0, 0, // Skip to: 47461 +/* 47266 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 47269 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47291 +/* 47274 */ MCD_OPC_CheckPredicate, 3, 245, 154, 0, // Skip to: 86948 +/* 47279 */ MCD_OPC_CheckField, 21, 1, 1, 238, 154, 0, // Skip to: 86948 +/* 47286 */ MCD_OPC_Decode, 179, 21, 252, 1, // Opcode: RADDHNv4i32_v4i16 +/* 47291 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47313 +/* 47296 */ MCD_OPC_CheckPredicate, 3, 223, 154, 0, // Skip to: 86948 +/* 47301 */ MCD_OPC_CheckField, 21, 1, 1, 216, 154, 0, // Skip to: 86948 +/* 47308 */ MCD_OPC_Decode, 133, 34, 238, 1, // Opcode: USHLv4i16 +/* 47313 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47351 +/* 47318 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47321 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47336 +/* 47326 */ MCD_OPC_CheckPredicate, 3, 193, 154, 0, // Skip to: 86948 +/* 47331 */ MCD_OPC_Decode, 178, 3, 239, 1, // Opcode: CLZv4i16 +/* 47336 */ MCD_OPC_FilterValue, 33, 183, 154, 0, // Skip to: 86948 +/* 47341 */ MCD_OPC_CheckPredicate, 3, 178, 154, 0, // Skip to: 86948 +/* 47346 */ MCD_OPC_Decode, 213, 33, 244, 1, // Opcode: UQXTNv4i16 +/* 47351 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47373 +/* 47356 */ MCD_OPC_CheckPredicate, 3, 163, 154, 0, // Skip to: 86948 +/* 47361 */ MCD_OPC_CheckField, 21, 1, 1, 156, 154, 0, // Skip to: 86948 +/* 47368 */ MCD_OPC_Decode, 172, 33, 238, 1, // Opcode: UQSHLv4i16 +/* 47373 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47395 +/* 47378 */ MCD_OPC_CheckPredicate, 3, 141, 154, 0, // Skip to: 86948 +/* 47383 */ MCD_OPC_CheckField, 21, 1, 1, 134, 154, 0, // Skip to: 86948 +/* 47390 */ MCD_OPC_Decode, 238, 30, 254, 1, // Opcode: UABALv4i16_v4i32 +/* 47395 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47417 +/* 47400 */ MCD_OPC_CheckPredicate, 3, 119, 154, 0, // Skip to: 86948 +/* 47405 */ MCD_OPC_CheckField, 21, 1, 1, 112, 154, 0, // Skip to: 86948 +/* 47412 */ MCD_OPC_Decode, 229, 33, 238, 1, // Opcode: URSHLv4i16 +/* 47417 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 47439 +/* 47422 */ MCD_OPC_CheckPredicate, 3, 97, 154, 0, // Skip to: 86948 +/* 47427 */ MCD_OPC_CheckField, 16, 6, 32, 90, 154, 0, // Skip to: 86948 +/* 47434 */ MCD_OPC_Decode, 191, 21, 239, 1, // Opcode: RBITv8i8 +/* 47439 */ MCD_OPC_FilterValue, 7, 80, 154, 0, // Skip to: 86948 +/* 47444 */ MCD_OPC_CheckPredicate, 3, 75, 154, 0, // Skip to: 86948 +/* 47449 */ MCD_OPC_CheckField, 21, 1, 1, 68, 154, 0, // Skip to: 86948 +/* 47456 */ MCD_OPC_Decode, 145, 33, 238, 1, // Opcode: UQRSHLv4i16 +/* 47461 */ MCD_OPC_FilterValue, 3, 195, 0, 0, // Skip to: 47661 +/* 47466 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 47469 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47491 +/* 47474 */ MCD_OPC_CheckPredicate, 3, 45, 154, 0, // Skip to: 86948 +/* 47479 */ MCD_OPC_CheckField, 21, 1, 1, 38, 154, 0, // Skip to: 86948 +/* 47486 */ MCD_OPC_Decode, 242, 21, 252, 1, // Opcode: RSUBHNv4i32_v4i16 +/* 47491 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47513 +/* 47496 */ MCD_OPC_CheckPredicate, 3, 23, 154, 0, // Skip to: 86948 +/* 47501 */ MCD_OPC_CheckField, 21, 1, 1, 16, 154, 0, // Skip to: 86948 +/* 47508 */ MCD_OPC_Decode, 130, 32, 238, 1, // Opcode: UMAXv4i16 +/* 47513 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47551 +/* 47518 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47521 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47536 +/* 47526 */ MCD_OPC_CheckPredicate, 3, 249, 153, 0, // Skip to: 86948 +/* 47531 */ MCD_OPC_Decode, 138, 31, 248, 1, // Opcode: UADALPv4i16_v2i32 +/* 47536 */ MCD_OPC_FilterValue, 33, 239, 153, 0, // Skip to: 86948 +/* 47541 */ MCD_OPC_CheckPredicate, 3, 234, 153, 0, // Skip to: 86948 +/* 47546 */ MCD_OPC_Decode, 216, 8, 244, 1, // Opcode: FCVTXNv2f32 +/* 47551 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47573 +/* 47556 */ MCD_OPC_CheckPredicate, 3, 219, 153, 0, // Skip to: 86948 +/* 47561 */ MCD_OPC_CheckField, 21, 1, 1, 212, 153, 0, // Skip to: 86948 +/* 47568 */ MCD_OPC_Decode, 159, 32, 238, 1, // Opcode: UMINv4i16 +/* 47573 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 47595 +/* 47578 */ MCD_OPC_CheckPredicate, 3, 197, 153, 0, // Skip to: 86948 +/* 47583 */ MCD_OPC_CheckField, 21, 1, 1, 190, 153, 0, // Skip to: 86948 +/* 47590 */ MCD_OPC_Decode, 250, 30, 234, 1, // Opcode: UABDLv4i16_v4i32 +/* 47595 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47617 +/* 47600 */ MCD_OPC_CheckPredicate, 3, 175, 153, 0, // Skip to: 86948 +/* 47605 */ MCD_OPC_CheckField, 21, 1, 1, 168, 153, 0, // Skip to: 86948 +/* 47612 */ MCD_OPC_Decode, 132, 31, 238, 1, // Opcode: UABDv4i16 +/* 47617 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 47639 +/* 47622 */ MCD_OPC_CheckPredicate, 3, 153, 153, 0, // Skip to: 86948 +/* 47627 */ MCD_OPC_CheckField, 16, 6, 32, 146, 153, 0, // Skip to: 86948 +/* 47634 */ MCD_OPC_Decode, 154, 25, 239, 1, // Opcode: SQNEGv4i16 +/* 47639 */ MCD_OPC_FilterValue, 7, 136, 153, 0, // Skip to: 86948 +/* 47644 */ MCD_OPC_CheckPredicate, 3, 131, 153, 0, // Skip to: 86948 +/* 47649 */ MCD_OPC_CheckField, 21, 1, 1, 124, 153, 0, // Skip to: 86948 +/* 47656 */ MCD_OPC_Decode, 244, 30, 130, 2, // Opcode: UABAv4i16 +/* 47661 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 47865 +/* 47666 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 47669 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47691 +/* 47674 */ MCD_OPC_CheckPredicate, 3, 101, 153, 0, // Skip to: 86948 +/* 47679 */ MCD_OPC_CheckField, 21, 1, 1, 94, 153, 0, // Skip to: 86948 +/* 47686 */ MCD_OPC_Decode, 167, 32, 254, 1, // Opcode: UMLALv4i16_v4i32 +/* 47691 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 47729 +/* 47696 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 47699 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47714 +/* 47704 */ MCD_OPC_CheckPredicate, 7, 71, 153, 0, // Skip to: 86948 +/* 47709 */ MCD_OPC_Decode, 164, 25, 130, 2, // Opcode: SQRDMLAHv4i16 +/* 47714 */ MCD_OPC_FilterValue, 1, 61, 153, 0, // Skip to: 86948 +/* 47719 */ MCD_OPC_CheckPredicate, 3, 56, 153, 0, // Skip to: 86948 +/* 47724 */ MCD_OPC_Decode, 131, 30, 238, 1, // Opcode: SUBv4i16 +/* 47729 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 47767 +/* 47734 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47737 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47752 +/* 47742 */ MCD_OPC_CheckPredicate, 3, 33, 153, 0, // Skip to: 86948 +/* 47747 */ MCD_OPC_Decode, 207, 3, 239, 1, // Opcode: CMGEv4i16rz +/* 47752 */ MCD_OPC_FilterValue, 57, 23, 153, 0, // Skip to: 86948 +/* 47757 */ MCD_OPC_CheckPredicate, 4, 18, 153, 0, // Skip to: 86948 +/* 47762 */ MCD_OPC_Decode, 232, 11, 239, 1, // Opcode: FRINTAv4f16 +/* 47767 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 47805 +/* 47772 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 47775 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 47790 +/* 47780 */ MCD_OPC_CheckPredicate, 7, 251, 152, 0, // Skip to: 86948 +/* 47785 */ MCD_OPC_Decode, 176, 25, 130, 2, // Opcode: SQRDMLSHv4i16 +/* 47790 */ MCD_OPC_FilterValue, 1, 241, 152, 0, // Skip to: 86948 +/* 47795 */ MCD_OPC_CheckPredicate, 3, 236, 152, 0, // Skip to: 86948 +/* 47800 */ MCD_OPC_Decode, 190, 3, 238, 1, // Opcode: CMEQv4i16 +/* 47805 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 47827 +/* 47810 */ MCD_OPC_CheckPredicate, 3, 221, 152, 0, // Skip to: 86948 +/* 47815 */ MCD_OPC_CheckField, 21, 1, 1, 214, 152, 0, // Skip to: 86948 +/* 47822 */ MCD_OPC_Decode, 226, 19, 130, 2, // Opcode: MLSv4i16 +/* 47827 */ MCD_OPC_FilterValue, 6, 204, 152, 0, // Skip to: 86948 +/* 47832 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47835 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 47850 +/* 47840 */ MCD_OPC_CheckPredicate, 3, 191, 152, 0, // Skip to: 86948 +/* 47845 */ MCD_OPC_Decode, 250, 3, 239, 1, // Opcode: CMLEv4i16rz +/* 47850 */ MCD_OPC_FilterValue, 57, 181, 152, 0, // Skip to: 86948 +/* 47855 */ MCD_OPC_CheckPredicate, 4, 176, 152, 0, // Skip to: 86948 +/* 47860 */ MCD_OPC_Decode, 159, 12, 239, 1, // Opcode: FRINTXv4f16 +/* 47865 */ MCD_OPC_FilterValue, 5, 182, 0, 0, // Skip to: 48052 +/* 47870 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 47873 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 47895 +/* 47878 */ MCD_OPC_CheckPredicate, 3, 153, 152, 0, // Skip to: 86948 +/* 47883 */ MCD_OPC_CheckField, 21, 1, 1, 146, 152, 0, // Skip to: 86948 +/* 47890 */ MCD_OPC_Decode, 177, 32, 254, 1, // Opcode: UMLSLv4i16_v4i32 +/* 47895 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 47917 +/* 47900 */ MCD_OPC_CheckPredicate, 3, 131, 152, 0, // Skip to: 86948 +/* 47905 */ MCD_OPC_CheckField, 21, 1, 1, 124, 152, 0, // Skip to: 86948 +/* 47912 */ MCD_OPC_Decode, 235, 31, 238, 1, // Opcode: UMAXPv4i16 +/* 47917 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 47970 +/* 47922 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 47925 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 47940 +/* 47930 */ MCD_OPC_CheckPredicate, 3, 101, 152, 0, // Skip to: 86948 +/* 47935 */ MCD_OPC_Decode, 244, 31, 249, 1, // Opcode: UMAXVv4i16v +/* 47940 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 47955 +/* 47945 */ MCD_OPC_CheckPredicate, 3, 86, 152, 0, // Skip to: 86948 +/* 47950 */ MCD_OPC_Decode, 145, 32, 249, 1, // Opcode: UMINVv4i16v +/* 47955 */ MCD_OPC_FilterValue, 57, 76, 152, 0, // Skip to: 86948 +/* 47960 */ MCD_OPC_CheckPredicate, 4, 71, 152, 0, // Skip to: 86948 +/* 47965 */ MCD_OPC_Decode, 178, 8, 239, 1, // Opcode: FCVTNUv4f16 +/* 47970 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 47992 +/* 47975 */ MCD_OPC_CheckPredicate, 3, 56, 152, 0, // Skip to: 86948 +/* 47980 */ MCD_OPC_CheckField, 21, 1, 1, 49, 152, 0, // Skip to: 86948 +/* 47987 */ MCD_OPC_Decode, 136, 32, 238, 1, // Opcode: UMINPv4i16 +/* 47992 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 48014 +/* 47997 */ MCD_OPC_CheckPredicate, 3, 34, 152, 0, // Skip to: 86948 +/* 48002 */ MCD_OPC_CheckField, 21, 1, 1, 27, 152, 0, // Skip to: 86948 +/* 48009 */ MCD_OPC_Decode, 188, 25, 238, 1, // Opcode: SQRDMULHv4i16 +/* 48014 */ MCD_OPC_FilterValue, 6, 17, 152, 0, // Skip to: 86948 +/* 48019 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 48022 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 48037 +/* 48027 */ MCD_OPC_CheckPredicate, 3, 4, 152, 0, // Skip to: 86948 +/* 48032 */ MCD_OPC_Decode, 183, 20, 239, 1, // Opcode: NEGv4i16 +/* 48037 */ MCD_OPC_FilterValue, 57, 250, 151, 0, // Skip to: 86948 +/* 48042 */ MCD_OPC_CheckPredicate, 4, 245, 151, 0, // Skip to: 86948 +/* 48047 */ MCD_OPC_Decode, 150, 8, 239, 1, // Opcode: FCVTMUv4f16 +/* 48052 */ MCD_OPC_FilterValue, 6, 99, 0, 0, // Skip to: 48156 +/* 48057 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 48060 */ MCD_OPC_FilterValue, 0, 69, 0, 0, // Skip to: 48134 +/* 48065 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 48068 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 48090 +/* 48073 */ MCD_OPC_CheckPredicate, 3, 214, 151, 0, // Skip to: 86948 +/* 48078 */ MCD_OPC_CheckField, 21, 1, 1, 207, 151, 0, // Skip to: 86948 +/* 48085 */ MCD_OPC_Decode, 197, 32, 234, 1, // Opcode: UMULLv4i16_v4i32 +/* 48090 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 48112 +/* 48095 */ MCD_OPC_CheckPredicate, 4, 192, 151, 0, // Skip to: 86948 +/* 48100 */ MCD_OPC_CheckField, 16, 6, 57, 185, 151, 0, // Skip to: 86948 +/* 48107 */ MCD_OPC_Decode, 242, 7, 239, 1, // Opcode: FCVTAUv4f16 +/* 48112 */ MCD_OPC_FilterValue, 3, 175, 151, 0, // Skip to: 86948 +/* 48117 */ MCD_OPC_CheckPredicate, 4, 170, 151, 0, // Skip to: 86948 +/* 48122 */ MCD_OPC_CheckField, 16, 6, 57, 163, 151, 0, // Skip to: 86948 +/* 48129 */ MCD_OPC_Decode, 200, 31, 239, 1, // Opcode: UCVTFv4f16 +/* 48134 */ MCD_OPC_FilterValue, 1, 153, 151, 0, // Skip to: 86948 +/* 48139 */ MCD_OPC_CheckPredicate, 8, 148, 151, 0, // Skip to: 86948 +/* 48144 */ MCD_OPC_CheckField, 21, 1, 0, 141, 151, 0, // Skip to: 86948 +/* 48151 */ MCD_OPC_Decode, 162, 7, 167, 2, // Opcode: FCMLAv4f16 +/* 48156 */ MCD_OPC_FilterValue, 7, 131, 151, 0, // Skip to: 86948 +/* 48161 */ MCD_OPC_CheckPredicate, 8, 126, 151, 0, // Skip to: 86948 +/* 48166 */ MCD_OPC_CheckField, 21, 1, 0, 119, 151, 0, // Skip to: 86948 +/* 48173 */ MCD_OPC_CheckField, 10, 2, 1, 112, 151, 0, // Skip to: 86948 +/* 48180 */ MCD_OPC_Decode, 208, 6, 168, 2, // Opcode: FCADDv4f16 +/* 48185 */ MCD_OPC_FilterValue, 2, 250, 6, 0, // Skip to: 49976 +/* 48190 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 48193 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 48215 +/* 48198 */ MCD_OPC_CheckPredicate, 3, 89, 151, 0, // Skip to: 86948 +/* 48203 */ MCD_OPC_CheckField, 21, 1, 1, 82, 151, 0, // Skip to: 86948 +/* 48210 */ MCD_OPC_Decode, 167, 22, 133, 2, // Opcode: SADDLv8i16_v4i32 +/* 48215 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 48253 +/* 48220 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48223 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48238 +/* 48228 */ MCD_OPC_CheckPredicate, 4, 59, 151, 0, // Skip to: 86948 +/* 48233 */ MCD_OPC_Decode, 222, 9, 133, 2, // Opcode: FMAXNMv8f16 +/* 48238 */ MCD_OPC_FilterValue, 1, 49, 151, 0, // Skip to: 86948 +/* 48243 */ MCD_OPC_CheckPredicate, 3, 44, 151, 0, // Skip to: 86948 +/* 48248 */ MCD_OPC_Decode, 131, 23, 133, 2, // Opcode: SHADDv8i16 +/* 48253 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 48275 +/* 48258 */ MCD_OPC_CheckPredicate, 3, 29, 151, 0, // Skip to: 86948 +/* 48263 */ MCD_OPC_CheckField, 16, 6, 32, 22, 151, 0, // Skip to: 86948 +/* 48270 */ MCD_OPC_Decode, 213, 21, 138, 2, // Opcode: REV64v8i16 +/* 48275 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 48313 +/* 48280 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48283 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48298 +/* 48288 */ MCD_OPC_CheckPredicate, 4, 255, 150, 0, // Skip to: 86948 +/* 48293 */ MCD_OPC_Decode, 194, 10, 141, 2, // Opcode: FMLAv8f16 +/* 48298 */ MCD_OPC_FilterValue, 1, 245, 150, 0, // Skip to: 86948 +/* 48303 */ MCD_OPC_CheckPredicate, 3, 240, 150, 0, // Skip to: 86948 +/* 48308 */ MCD_OPC_Decode, 181, 24, 133, 2, // Opcode: SQADDv8i16 +/* 48313 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 48335 +/* 48318 */ MCD_OPC_CheckPredicate, 3, 225, 150, 0, // Skip to: 86948 +/* 48323 */ MCD_OPC_CheckField, 21, 1, 1, 218, 150, 0, // Skip to: 86948 +/* 48330 */ MCD_OPC_Decode, 176, 22, 133, 2, // Opcode: SADDWv8i16_v4i32 +/* 48335 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 48373 +/* 48340 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48343 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48358 +/* 48348 */ MCD_OPC_CheckPredicate, 4, 195, 150, 0, // Skip to: 86948 +/* 48353 */ MCD_OPC_Decode, 202, 6, 133, 2, // Opcode: FADDv8f16 +/* 48358 */ MCD_OPC_FilterValue, 1, 185, 150, 0, // Skip to: 86948 +/* 48363 */ MCD_OPC_CheckPredicate, 3, 180, 150, 0, // Skip to: 86948 +/* 48368 */ MCD_OPC_Decode, 187, 26, 133, 2, // Opcode: SRHADDv8i16 +/* 48373 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 48395 +/* 48378 */ MCD_OPC_CheckPredicate, 3, 165, 150, 0, // Skip to: 86948 +/* 48383 */ MCD_OPC_CheckField, 21, 1, 0, 158, 150, 0, // Skip to: 86948 +/* 48390 */ MCD_OPC_Decode, 201, 34, 133, 2, // Opcode: UZP1v8i16 +/* 48395 */ MCD_OPC_FilterValue, 7, 33, 0, 0, // Skip to: 48433 +/* 48400 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48403 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48418 +/* 48408 */ MCD_OPC_CheckPredicate, 4, 135, 150, 0, // Skip to: 86948 +/* 48413 */ MCD_OPC_Decode, 137, 11, 133, 2, // Opcode: FMULXv8f16 +/* 48418 */ MCD_OPC_FilterValue, 1, 125, 150, 0, // Skip to: 86948 +/* 48423 */ MCD_OPC_CheckPredicate, 3, 120, 150, 0, // Skip to: 86948 +/* 48428 */ MCD_OPC_Decode, 187, 2, 133, 2, // Opcode: BICv16i8 +/* 48433 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 48455 +/* 48438 */ MCD_OPC_CheckPredicate, 3, 105, 150, 0, // Skip to: 86948 +/* 48443 */ MCD_OPC_CheckField, 21, 1, 1, 98, 150, 0, // Skip to: 86948 +/* 48450 */ MCD_OPC_Decode, 165, 27, 133, 2, // Opcode: SSUBLv8i16_v4i32 +/* 48455 */ MCD_OPC_FilterValue, 9, 33, 0, 0, // Skip to: 48493 +/* 48460 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48463 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48478 +/* 48468 */ MCD_OPC_CheckPredicate, 4, 75, 150, 0, // Skip to: 86948 +/* 48473 */ MCD_OPC_Decode, 237, 6, 133, 2, // Opcode: FCMEQv8f16 +/* 48478 */ MCD_OPC_FilterValue, 1, 65, 150, 0, // Skip to: 86948 +/* 48483 */ MCD_OPC_CheckPredicate, 3, 60, 150, 0, // Skip to: 86948 +/* 48488 */ MCD_OPC_Decode, 157, 23, 133, 2, // Opcode: SHSUBv8i16 +/* 48493 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 48554 +/* 48498 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48501 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48516 +/* 48506 */ MCD_OPC_CheckPredicate, 3, 37, 150, 0, // Skip to: 86948 +/* 48511 */ MCD_OPC_Decode, 218, 30, 133, 2, // Opcode: TRN1v8i16 +/* 48516 */ MCD_OPC_FilterValue, 1, 27, 150, 0, // Skip to: 86948 +/* 48521 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 48524 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48539 +/* 48529 */ MCD_OPC_CheckPredicate, 3, 14, 150, 0, // Skip to: 86948 +/* 48534 */ MCD_OPC_Decode, 156, 22, 138, 2, // Opcode: SADDLPv8i16_v4i32 +/* 48539 */ MCD_OPC_FilterValue, 1, 4, 150, 0, // Skip to: 86948 +/* 48544 */ MCD_OPC_CheckPredicate, 3, 255, 149, 0, // Skip to: 86948 +/* 48549 */ MCD_OPC_Decode, 131, 35, 147, 2, // Opcode: XTNv8i16 +/* 48554 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 48576 +/* 48559 */ MCD_OPC_CheckPredicate, 3, 240, 149, 0, // Skip to: 86948 +/* 48564 */ MCD_OPC_CheckField, 21, 1, 1, 233, 149, 0, // Skip to: 86948 +/* 48571 */ MCD_OPC_Decode, 163, 26, 133, 2, // Opcode: SQSUBv8i16 +/* 48576 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 48598 +/* 48581 */ MCD_OPC_CheckPredicate, 3, 218, 149, 0, // Skip to: 86948 +/* 48586 */ MCD_OPC_CheckField, 21, 1, 1, 211, 149, 0, // Skip to: 86948 +/* 48593 */ MCD_OPC_Decode, 171, 27, 133, 2, // Opcode: SSUBWv8i16_v4i32 +/* 48598 */ MCD_OPC_FilterValue, 13, 33, 0, 0, // Skip to: 48636 +/* 48603 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48606 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48621 +/* 48611 */ MCD_OPC_CheckPredicate, 4, 188, 149, 0, // Skip to: 86948 +/* 48616 */ MCD_OPC_Decode, 248, 9, 133, 2, // Opcode: FMAXv8f16 +/* 48621 */ MCD_OPC_FilterValue, 1, 178, 149, 0, // Skip to: 86948 +/* 48626 */ MCD_OPC_CheckPredicate, 3, 173, 149, 0, // Skip to: 86948 +/* 48631 */ MCD_OPC_Decode, 226, 3, 133, 2, // Opcode: CMGTv8i16 +/* 48636 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 48697 +/* 48641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48659 +/* 48649 */ MCD_OPC_CheckPredicate, 3, 150, 149, 0, // Skip to: 86948 +/* 48654 */ MCD_OPC_Decode, 146, 35, 133, 2, // Opcode: ZIP1v8i16 +/* 48659 */ MCD_OPC_FilterValue, 1, 140, 149, 0, // Skip to: 86948 +/* 48664 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 48667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48682 +/* 48672 */ MCD_OPC_CheckPredicate, 3, 127, 149, 0, // Skip to: 86948 +/* 48677 */ MCD_OPC_Decode, 150, 30, 147, 2, // Opcode: SUQADDv8i16 +/* 48682 */ MCD_OPC_FilterValue, 16, 117, 149, 0, // Skip to: 86948 +/* 48687 */ MCD_OPC_CheckPredicate, 3, 112, 149, 0, // Skip to: 86948 +/* 48692 */ MCD_OPC_Decode, 161, 22, 160, 2, // Opcode: SADDLVv8i16v +/* 48697 */ MCD_OPC_FilterValue, 15, 33, 0, 0, // Skip to: 48735 +/* 48702 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48720 +/* 48710 */ MCD_OPC_CheckPredicate, 4, 89, 149, 0, // Skip to: 86948 +/* 48715 */ MCD_OPC_Decode, 217, 11, 133, 2, // Opcode: FRECPSv8f16 +/* 48720 */ MCD_OPC_FilterValue, 1, 79, 149, 0, // Skip to: 86948 +/* 48725 */ MCD_OPC_CheckPredicate, 3, 74, 149, 0, // Skip to: 86948 +/* 48730 */ MCD_OPC_Decode, 210, 3, 133, 2, // Opcode: CMGEv8i16 +/* 48735 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 48757 +/* 48740 */ MCD_OPC_CheckPredicate, 3, 59, 149, 0, // Skip to: 86948 +/* 48745 */ MCD_OPC_CheckField, 21, 1, 1, 52, 149, 0, // Skip to: 86948 +/* 48752 */ MCD_OPC_Decode, 145, 1, 141, 2, // Opcode: ADDHNv4i32_v8i16 +/* 48757 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 48779 +/* 48762 */ MCD_OPC_CheckPredicate, 3, 37, 149, 0, // Skip to: 86948 +/* 48767 */ MCD_OPC_CheckField, 21, 1, 1, 30, 149, 0, // Skip to: 86948 +/* 48774 */ MCD_OPC_Decode, 233, 26, 133, 2, // Opcode: SSHLv8i16 +/* 48779 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 48817 +/* 48784 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 48787 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 48802 +/* 48792 */ MCD_OPC_CheckPredicate, 3, 7, 149, 0, // Skip to: 86948 +/* 48797 */ MCD_OPC_Decode, 168, 3, 138, 2, // Opcode: CLSv8i16 +/* 48802 */ MCD_OPC_FilterValue, 33, 253, 148, 0, // Skip to: 86948 +/* 48807 */ MCD_OPC_CheckPredicate, 3, 248, 148, 0, // Skip to: 86948 +/* 48812 */ MCD_OPC_Decode, 172, 26, 147, 2, // Opcode: SQXTNv8i16 +/* 48817 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 48839 +/* 48822 */ MCD_OPC_CheckPredicate, 3, 233, 148, 0, // Skip to: 86948 +/* 48827 */ MCD_OPC_CheckField, 21, 1, 1, 226, 148, 0, // Skip to: 86948 +/* 48834 */ MCD_OPC_Decode, 252, 25, 133, 2, // Opcode: SQSHLv8i16 +/* 48839 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 48861 +/* 48844 */ MCD_OPC_CheckPredicate, 3, 211, 148, 0, // Skip to: 86948 +/* 48849 */ MCD_OPC_CheckField, 21, 1, 1, 204, 148, 0, // Skip to: 86948 +/* 48856 */ MCD_OPC_Decode, 250, 21, 141, 2, // Opcode: SABALv8i16_v4i32 +/* 48861 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 48883 +/* 48866 */ MCD_OPC_CheckPredicate, 3, 189, 148, 0, // Skip to: 86948 +/* 48871 */ MCD_OPC_CheckField, 21, 1, 1, 182, 148, 0, // Skip to: 86948 +/* 48878 */ MCD_OPC_Decode, 203, 26, 133, 2, // Opcode: SRSHLv8i16 +/* 48883 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 48905 +/* 48888 */ MCD_OPC_CheckPredicate, 3, 167, 148, 0, // Skip to: 86948 +/* 48893 */ MCD_OPC_CheckField, 21, 1, 0, 160, 148, 0, // Skip to: 86948 +/* 48900 */ MCD_OPC_Decode, 216, 34, 133, 2, // Opcode: UZP2v8i16 +/* 48905 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 48927 +/* 48910 */ MCD_OPC_CheckPredicate, 3, 145, 148, 0, // Skip to: 86948 +/* 48915 */ MCD_OPC_CheckField, 21, 1, 1, 138, 148, 0, // Skip to: 86948 +/* 48922 */ MCD_OPC_Decode, 203, 25, 133, 2, // Opcode: SQRSHLv8i16 +/* 48927 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 48949 +/* 48932 */ MCD_OPC_CheckPredicate, 3, 123, 148, 0, // Skip to: 86948 +/* 48937 */ MCD_OPC_CheckField, 21, 1, 1, 116, 148, 0, // Skip to: 86948 +/* 48944 */ MCD_OPC_Decode, 214, 29, 141, 2, // Opcode: SUBHNv4i32_v8i16 +/* 48949 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 48971 +/* 48954 */ MCD_OPC_CheckPredicate, 3, 101, 148, 0, // Skip to: 86948 +/* 48959 */ MCD_OPC_CheckField, 21, 1, 1, 94, 148, 0, // Skip to: 86948 +/* 48966 */ MCD_OPC_Decode, 204, 23, 133, 2, // Opcode: SMAXv8i16 +/* 48971 */ MCD_OPC_FilterValue, 26, 56, 0, 0, // Skip to: 49032 +/* 48976 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 48979 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 48994 +/* 48984 */ MCD_OPC_CheckPredicate, 3, 71, 148, 0, // Skip to: 86948 +/* 48989 */ MCD_OPC_Decode, 233, 30, 133, 2, // Opcode: TRN2v8i16 +/* 48994 */ MCD_OPC_FilterValue, 1, 61, 148, 0, // Skip to: 86948 +/* 48999 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 49002 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49017 +/* 49007 */ MCD_OPC_CheckPredicate, 3, 48, 148, 0, // Skip to: 86948 +/* 49012 */ MCD_OPC_Decode, 150, 22, 147, 2, // Opcode: SADALPv8i16_v4i32 +/* 49017 */ MCD_OPC_FilterValue, 1, 38, 148, 0, // Skip to: 86948 +/* 49022 */ MCD_OPC_CheckPredicate, 3, 33, 148, 0, // Skip to: 86948 +/* 49027 */ MCD_OPC_Decode, 183, 8, 147, 2, // Opcode: FCVTNv4i32 +/* 49032 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 49054 +/* 49037 */ MCD_OPC_CheckPredicate, 3, 18, 148, 0, // Skip to: 86948 +/* 49042 */ MCD_OPC_CheckField, 21, 1, 1, 11, 148, 0, // Skip to: 86948 +/* 49049 */ MCD_OPC_Decode, 234, 23, 133, 2, // Opcode: SMINv8i16 +/* 49054 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 49076 +/* 49059 */ MCD_OPC_CheckPredicate, 3, 252, 147, 0, // Skip to: 86948 +/* 49064 */ MCD_OPC_CheckField, 21, 1, 1, 245, 147, 0, // Skip to: 86948 +/* 49071 */ MCD_OPC_Decode, 134, 22, 133, 2, // Opcode: SABDLv8i16_v4i32 +/* 49076 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 49098 +/* 49081 */ MCD_OPC_CheckPredicate, 3, 230, 147, 0, // Skip to: 86948 +/* 49086 */ MCD_OPC_CheckField, 21, 1, 1, 223, 147, 0, // Skip to: 86948 +/* 49093 */ MCD_OPC_Decode, 144, 22, 133, 2, // Opcode: SABDv8i16 +/* 49098 */ MCD_OPC_FilterValue, 30, 56, 0, 0, // Skip to: 49159 +/* 49103 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 49106 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49121 +/* 49111 */ MCD_OPC_CheckPredicate, 3, 200, 147, 0, // Skip to: 86948 +/* 49116 */ MCD_OPC_Decode, 161, 35, 133, 2, // Opcode: ZIP2v8i16 +/* 49121 */ MCD_OPC_FilterValue, 1, 190, 147, 0, // Skip to: 86948 +/* 49126 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 49129 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 49144 +/* 49134 */ MCD_OPC_CheckPredicate, 3, 177, 147, 0, // Skip to: 86948 +/* 49139 */ MCD_OPC_Decode, 162, 24, 138, 2, // Opcode: SQABSv8i16 +/* 49144 */ MCD_OPC_FilterValue, 1, 167, 147, 0, // Skip to: 86948 +/* 49149 */ MCD_OPC_CheckPredicate, 3, 162, 147, 0, // Skip to: 86948 +/* 49154 */ MCD_OPC_Decode, 251, 7, 138, 2, // Opcode: FCVTLv4i32 +/* 49159 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 49181 +/* 49164 */ MCD_OPC_CheckPredicate, 3, 147, 147, 0, // Skip to: 86948 +/* 49169 */ MCD_OPC_CheckField, 21, 1, 1, 140, 147, 0, // Skip to: 86948 +/* 49176 */ MCD_OPC_Decode, 128, 22, 141, 2, // Opcode: SABAv8i16 +/* 49181 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 49203 +/* 49186 */ MCD_OPC_CheckPredicate, 3, 125, 147, 0, // Skip to: 86948 +/* 49191 */ MCD_OPC_CheckField, 21, 1, 1, 118, 147, 0, // Skip to: 86948 +/* 49198 */ MCD_OPC_Decode, 244, 23, 141, 2, // Opcode: SMLALv8i16_v4i32 +/* 49203 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 49225 +/* 49208 */ MCD_OPC_CheckPredicate, 3, 103, 147, 0, // Skip to: 86948 +/* 49213 */ MCD_OPC_CheckField, 21, 1, 1, 96, 147, 0, // Skip to: 86948 +/* 49220 */ MCD_OPC_Decode, 200, 1, 133, 2, // Opcode: ADDv8i16 +/* 49225 */ MCD_OPC_FilterValue, 34, 48, 0, 0, // Skip to: 49278 +/* 49230 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 49233 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49248 +/* 49238 */ MCD_OPC_CheckPredicate, 3, 73, 147, 0, // Skip to: 86948 +/* 49243 */ MCD_OPC_Decode, 227, 3, 138, 2, // Opcode: CMGTv8i16rz +/* 49248 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49263 +/* 49253 */ MCD_OPC_CheckPredicate, 3, 58, 147, 0, // Skip to: 86948 +/* 49258 */ MCD_OPC_Decode, 136, 12, 138, 2, // Opcode: FRINTNv2f64 +/* 49263 */ MCD_OPC_FilterValue, 57, 48, 147, 0, // Skip to: 86948 +/* 49268 */ MCD_OPC_CheckPredicate, 4, 43, 147, 0, // Skip to: 86948 +/* 49273 */ MCD_OPC_Decode, 139, 12, 138, 2, // Opcode: FRINTNv8f16 +/* 49278 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 49300 +/* 49283 */ MCD_OPC_CheckPredicate, 3, 28, 147, 0, // Skip to: 86948 +/* 49288 */ MCD_OPC_CheckField, 21, 1, 1, 21, 147, 0, // Skip to: 86948 +/* 49295 */ MCD_OPC_Decode, 239, 4, 133, 2, // Opcode: CMTSTv8i16 +/* 49300 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 49322 +/* 49305 */ MCD_OPC_CheckPredicate, 3, 6, 147, 0, // Skip to: 86948 +/* 49310 */ MCD_OPC_CheckField, 21, 1, 1, 255, 146, 0, // Skip to: 86948 +/* 49317 */ MCD_OPC_Decode, 216, 24, 141, 2, // Opcode: SQDMLALv8i16_v4i32 +/* 49322 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 49344 +/* 49327 */ MCD_OPC_CheckPredicate, 3, 240, 146, 0, // Skip to: 86948 +/* 49332 */ MCD_OPC_CheckField, 21, 1, 1, 233, 146, 0, // Skip to: 86948 +/* 49339 */ MCD_OPC_Decode, 216, 19, 141, 2, // Opcode: MLAv8i16 +/* 49344 */ MCD_OPC_FilterValue, 38, 48, 0, 0, // Skip to: 49397 +/* 49349 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 49352 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49367 +/* 49357 */ MCD_OPC_CheckPredicate, 3, 210, 146, 0, // Skip to: 86948 +/* 49362 */ MCD_OPC_Decode, 195, 3, 138, 2, // Opcode: CMEQv8i16rz +/* 49367 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49382 +/* 49372 */ MCD_OPC_CheckPredicate, 3, 195, 146, 0, // Skip to: 86948 +/* 49377 */ MCD_OPC_Decode, 253, 11, 138, 2, // Opcode: FRINTMv2f64 +/* 49382 */ MCD_OPC_FilterValue, 57, 185, 146, 0, // Skip to: 86948 +/* 49387 */ MCD_OPC_CheckPredicate, 4, 180, 146, 0, // Skip to: 86948 +/* 49392 */ MCD_OPC_Decode, 128, 12, 138, 2, // Opcode: FRINTMv8f16 +/* 49397 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 49419 +/* 49402 */ MCD_OPC_CheckPredicate, 3, 165, 146, 0, // Skip to: 86948 +/* 49407 */ MCD_OPC_CheckField, 21, 1, 1, 158, 146, 0, // Skip to: 86948 +/* 49414 */ MCD_OPC_Decode, 164, 20, 133, 2, // Opcode: MULv8i16 +/* 49419 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 49441 +/* 49424 */ MCD_OPC_CheckPredicate, 3, 143, 146, 0, // Skip to: 86948 +/* 49429 */ MCD_OPC_CheckField, 21, 1, 1, 136, 146, 0, // Skip to: 86948 +/* 49436 */ MCD_OPC_Decode, 254, 23, 141, 2, // Opcode: SMLSLv8i16_v4i32 +/* 49441 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 49463 +/* 49446 */ MCD_OPC_CheckPredicate, 3, 121, 146, 0, // Skip to: 86948 +/* 49451 */ MCD_OPC_CheckField, 21, 1, 1, 114, 146, 0, // Skip to: 86948 +/* 49458 */ MCD_OPC_Decode, 181, 23, 133, 2, // Opcode: SMAXPv8i16 +/* 49463 */ MCD_OPC_FilterValue, 42, 78, 0, 0, // Skip to: 49546 +/* 49468 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 49471 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49486 +/* 49476 */ MCD_OPC_CheckPredicate, 3, 91, 146, 0, // Skip to: 86948 +/* 49481 */ MCD_OPC_Decode, 132, 4, 138, 2, // Opcode: CMLTv8i16rz +/* 49486 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49501 +/* 49491 */ MCD_OPC_CheckPredicate, 3, 76, 146, 0, // Skip to: 86948 +/* 49496 */ MCD_OPC_Decode, 163, 8, 138, 2, // Opcode: FCVTNSv2f64 +/* 49501 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 49516 +/* 49506 */ MCD_OPC_CheckPredicate, 3, 61, 146, 0, // Skip to: 86948 +/* 49511 */ MCD_OPC_Decode, 190, 23, 152, 2, // Opcode: SMAXVv8i16v +/* 49516 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 49531 +/* 49521 */ MCD_OPC_CheckPredicate, 3, 46, 146, 0, // Skip to: 86948 +/* 49526 */ MCD_OPC_Decode, 220, 23, 152, 2, // Opcode: SMINVv8i16v +/* 49531 */ MCD_OPC_FilterValue, 57, 36, 146, 0, // Skip to: 86948 +/* 49536 */ MCD_OPC_CheckPredicate, 4, 31, 146, 0, // Skip to: 86948 +/* 49541 */ MCD_OPC_Decode, 166, 8, 138, 2, // Opcode: FCVTNSv8f16 +/* 49546 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 49568 +/* 49551 */ MCD_OPC_CheckPredicate, 3, 16, 146, 0, // Skip to: 86948 +/* 49556 */ MCD_OPC_CheckField, 21, 1, 1, 9, 146, 0, // Skip to: 86948 +/* 49563 */ MCD_OPC_Decode, 211, 23, 133, 2, // Opcode: SMINPv8i16 +/* 49568 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 49590 +/* 49573 */ MCD_OPC_CheckPredicate, 3, 250, 145, 0, // Skip to: 86948 +/* 49578 */ MCD_OPC_CheckField, 21, 1, 1, 243, 145, 0, // Skip to: 86948 +/* 49585 */ MCD_OPC_Decode, 228, 24, 141, 2, // Opcode: SQDMLSLv8i16_v4i32 +/* 49590 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 49612 +/* 49595 */ MCD_OPC_CheckPredicate, 3, 228, 145, 0, // Skip to: 86948 +/* 49600 */ MCD_OPC_CheckField, 21, 1, 1, 221, 145, 0, // Skip to: 86948 +/* 49607 */ MCD_OPC_Decode, 239, 24, 133, 2, // Opcode: SQDMULHv8i16 +/* 49612 */ MCD_OPC_FilterValue, 46, 63, 0, 0, // Skip to: 49680 +/* 49617 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 49620 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 49635 +/* 49625 */ MCD_OPC_CheckPredicate, 3, 198, 145, 0, // Skip to: 86948 +/* 49630 */ MCD_OPC_Decode, 136, 1, 138, 2, // Opcode: ABSv8i16 +/* 49635 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49650 +/* 49640 */ MCD_OPC_CheckPredicate, 3, 183, 145, 0, // Skip to: 86948 +/* 49645 */ MCD_OPC_Decode, 135, 8, 138, 2, // Opcode: FCVTMSv2f64 +/* 49650 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 49665 +/* 49655 */ MCD_OPC_CheckPredicate, 3, 168, 145, 0, // Skip to: 86948 +/* 49660 */ MCD_OPC_Decode, 170, 1, 152, 2, // Opcode: ADDVv8i16v +/* 49665 */ MCD_OPC_FilterValue, 57, 158, 145, 0, // Skip to: 86948 +/* 49670 */ MCD_OPC_CheckPredicate, 4, 153, 145, 0, // Skip to: 86948 +/* 49675 */ MCD_OPC_Decode, 138, 8, 138, 2, // Opcode: FCVTMSv8f16 +/* 49680 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 49702 +/* 49685 */ MCD_OPC_CheckPredicate, 3, 138, 145, 0, // Skip to: 86948 +/* 49690 */ MCD_OPC_CheckField, 21, 1, 1, 131, 145, 0, // Skip to: 86948 +/* 49697 */ MCD_OPC_Decode, 155, 1, 133, 2, // Opcode: ADDPv8i16 +/* 49702 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 49724 +/* 49707 */ MCD_OPC_CheckPredicate, 3, 116, 145, 0, // Skip to: 86948 +/* 49712 */ MCD_OPC_CheckField, 21, 1, 1, 109, 145, 0, // Skip to: 86948 +/* 49719 */ MCD_OPC_Decode, 147, 24, 133, 2, // Opcode: SMULLv8i16_v4i32 +/* 49724 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 49746 +/* 49729 */ MCD_OPC_CheckPredicate, 3, 94, 145, 0, // Skip to: 86948 +/* 49734 */ MCD_OPC_CheckField, 21, 1, 1, 87, 145, 0, // Skip to: 86948 +/* 49741 */ MCD_OPC_Decode, 219, 9, 133, 2, // Opcode: FMAXNMv2f64 +/* 49746 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 49784 +/* 49751 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 49754 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49769 +/* 49759 */ MCD_OPC_CheckPredicate, 3, 64, 145, 0, // Skip to: 86948 +/* 49764 */ MCD_OPC_Decode, 227, 7, 138, 2, // Opcode: FCVTASv2f64 +/* 49769 */ MCD_OPC_FilterValue, 57, 54, 145, 0, // Skip to: 86948 +/* 49774 */ MCD_OPC_CheckPredicate, 4, 49, 145, 0, // Skip to: 86948 +/* 49779 */ MCD_OPC_Decode, 230, 7, 138, 2, // Opcode: FCVTASv8f16 +/* 49784 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 49806 +/* 49789 */ MCD_OPC_CheckPredicate, 3, 34, 145, 0, // Skip to: 86948 +/* 49794 */ MCD_OPC_CheckField, 21, 1, 1, 27, 145, 0, // Skip to: 86948 +/* 49801 */ MCD_OPC_Decode, 187, 10, 141, 2, // Opcode: FMLAv2f64 +/* 49806 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 49828 +/* 49811 */ MCD_OPC_CheckPredicate, 3, 12, 145, 0, // Skip to: 86948 +/* 49816 */ MCD_OPC_CheckField, 21, 1, 1, 5, 145, 0, // Skip to: 86948 +/* 49823 */ MCD_OPC_Decode, 252, 24, 133, 2, // Opcode: SQDMULLv8i16_v4i32 +/* 49828 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 49850 +/* 49833 */ MCD_OPC_CheckPredicate, 3, 246, 144, 0, // Skip to: 86948 +/* 49838 */ MCD_OPC_CheckField, 21, 1, 1, 239, 144, 0, // Skip to: 86948 +/* 49845 */ MCD_OPC_Decode, 199, 6, 133, 2, // Opcode: FADDv2f64 +/* 49850 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 49888 +/* 49855 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 49858 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 49873 +/* 49863 */ MCD_OPC_CheckPredicate, 3, 216, 144, 0, // Skip to: 86948 +/* 49868 */ MCD_OPC_Decode, 210, 22, 138, 2, // Opcode: SCVTFv2f64 +/* 49873 */ MCD_OPC_FilterValue, 57, 206, 144, 0, // Skip to: 86948 +/* 49878 */ MCD_OPC_CheckPredicate, 4, 201, 144, 0, // Skip to: 86948 +/* 49883 */ MCD_OPC_Decode, 217, 22, 138, 2, // Opcode: SCVTFv8f16 +/* 49888 */ MCD_OPC_FilterValue, 55, 17, 0, 0, // Skip to: 49910 +/* 49893 */ MCD_OPC_CheckPredicate, 3, 186, 144, 0, // Skip to: 86948 +/* 49898 */ MCD_OPC_CheckField, 21, 1, 1, 179, 144, 0, // Skip to: 86948 +/* 49905 */ MCD_OPC_Decode, 130, 11, 133, 2, // Opcode: FMULXv2f64 +/* 49910 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 49932 +/* 49915 */ MCD_OPC_CheckPredicate, 3, 164, 144, 0, // Skip to: 86948 +/* 49920 */ MCD_OPC_CheckField, 21, 1, 1, 157, 144, 0, // Skip to: 86948 +/* 49927 */ MCD_OPC_Decode, 230, 6, 133, 2, // Opcode: FCMEQv2f64 +/* 49932 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 49954 +/* 49937 */ MCD_OPC_CheckPredicate, 3, 142, 144, 0, // Skip to: 86948 +/* 49942 */ MCD_OPC_CheckField, 21, 1, 1, 135, 144, 0, // Skip to: 86948 +/* 49949 */ MCD_OPC_Decode, 245, 9, 133, 2, // Opcode: FMAXv2f64 +/* 49954 */ MCD_OPC_FilterValue, 63, 125, 144, 0, // Skip to: 86948 +/* 49959 */ MCD_OPC_CheckPredicate, 3, 120, 144, 0, // Skip to: 86948 +/* 49964 */ MCD_OPC_CheckField, 21, 1, 1, 113, 144, 0, // Skip to: 86948 +/* 49971 */ MCD_OPC_Decode, 214, 11, 133, 2, // Opcode: FRECPSv2f64 +/* 49976 */ MCD_OPC_FilterValue, 3, 134, 6, 0, // Skip to: 51651 +/* 49981 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 49984 */ MCD_OPC_FilterValue, 0, 205, 0, 0, // Skip to: 50194 +/* 49989 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 49992 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50014 +/* 49997 */ MCD_OPC_CheckPredicate, 3, 82, 144, 0, // Skip to: 86948 +/* 50002 */ MCD_OPC_CheckField, 21, 1, 1, 75, 144, 0, // Skip to: 86948 +/* 50009 */ MCD_OPC_Decode, 157, 31, 133, 2, // Opcode: UADDLv8i16_v4i32 +/* 50014 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50052 +/* 50019 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50022 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50037 +/* 50027 */ MCD_OPC_CheckPredicate, 4, 52, 144, 0, // Skip to: 86948 +/* 50032 */ MCD_OPC_Decode, 204, 9, 133, 2, // Opcode: FMAXNMPv8f16 +/* 50037 */ MCD_OPC_FilterValue, 1, 42, 144, 0, // Skip to: 86948 +/* 50042 */ MCD_OPC_CheckPredicate, 3, 37, 144, 0, // Skip to: 86948 +/* 50047 */ MCD_OPC_Decode, 224, 31, 133, 2, // Opcode: UHADDv8i16 +/* 50052 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 50074 +/* 50057 */ MCD_OPC_CheckPredicate, 3, 22, 144, 0, // Skip to: 86948 +/* 50062 */ MCD_OPC_CheckField, 16, 6, 32, 15, 144, 0, // Skip to: 86948 +/* 50069 */ MCD_OPC_Decode, 207, 21, 138, 2, // Opcode: REV32v8i16 +/* 50074 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50096 +/* 50079 */ MCD_OPC_CheckPredicate, 3, 0, 144, 0, // Skip to: 86948 +/* 50084 */ MCD_OPC_CheckField, 21, 1, 1, 249, 143, 0, // Skip to: 86948 +/* 50091 */ MCD_OPC_Decode, 220, 32, 133, 2, // Opcode: UQADDv8i16 +/* 50096 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50118 +/* 50101 */ MCD_OPC_CheckPredicate, 3, 234, 143, 0, // Skip to: 86948 +/* 50106 */ MCD_OPC_CheckField, 21, 1, 1, 227, 143, 0, // Skip to: 86948 +/* 50113 */ MCD_OPC_Decode, 167, 31, 133, 2, // Opcode: UADDWv8i16_v4i32 +/* 50118 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 50156 +/* 50123 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50126 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50141 +/* 50131 */ MCD_OPC_CheckPredicate, 4, 204, 143, 0, // Skip to: 86948 +/* 50136 */ MCD_OPC_Decode, 184, 6, 133, 2, // Opcode: FADDPv8f16 +/* 50141 */ MCD_OPC_FilterValue, 1, 194, 143, 0, // Skip to: 86948 +/* 50146 */ MCD_OPC_CheckPredicate, 3, 189, 143, 0, // Skip to: 86948 +/* 50151 */ MCD_OPC_Decode, 223, 33, 133, 2, // Opcode: URHADDv8i16 +/* 50156 */ MCD_OPC_FilterValue, 7, 179, 143, 0, // Skip to: 86948 +/* 50161 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50164 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50179 +/* 50169 */ MCD_OPC_CheckPredicate, 4, 166, 143, 0, // Skip to: 86948 +/* 50174 */ MCD_OPC_Decode, 162, 11, 133, 2, // Opcode: FMULv8f16 +/* 50179 */ MCD_OPC_FilterValue, 1, 156, 143, 0, // Skip to: 86948 +/* 50184 */ MCD_OPC_CheckPredicate, 3, 151, 143, 0, // Skip to: 86948 +/* 50189 */ MCD_OPC_Decode, 221, 2, 141, 2, // Opcode: BSLv16i8 +/* 50194 */ MCD_OPC_FilterValue, 1, 34, 1, 0, // Skip to: 50489 +/* 50199 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 50202 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50224 +/* 50207 */ MCD_OPC_CheckPredicate, 3, 128, 143, 0, // Skip to: 86948 +/* 50212 */ MCD_OPC_CheckField, 21, 1, 1, 121, 143, 0, // Skip to: 86948 +/* 50219 */ MCD_OPC_Decode, 168, 34, 133, 2, // Opcode: USUBLv8i16_v4i32 +/* 50224 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50262 +/* 50229 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50232 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50247 +/* 50237 */ MCD_OPC_CheckPredicate, 4, 98, 143, 0, // Skip to: 86948 +/* 50242 */ MCD_OPC_Decode, 131, 7, 133, 2, // Opcode: FCMGEv8f16 +/* 50247 */ MCD_OPC_FilterValue, 1, 88, 143, 0, // Skip to: 86948 +/* 50252 */ MCD_OPC_CheckPredicate, 3, 83, 143, 0, // Skip to: 86948 +/* 50257 */ MCD_OPC_Decode, 230, 31, 133, 2, // Opcode: UHSUBv8i16 +/* 50262 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50300 +/* 50267 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 50270 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50285 +/* 50275 */ MCD_OPC_CheckPredicate, 3, 60, 143, 0, // Skip to: 86948 +/* 50280 */ MCD_OPC_Decode, 146, 31, 138, 2, // Opcode: UADDLPv8i16_v4i32 +/* 50285 */ MCD_OPC_FilterValue, 33, 50, 143, 0, // Skip to: 86948 +/* 50290 */ MCD_OPC_CheckPredicate, 3, 45, 143, 0, // Skip to: 86948 +/* 50295 */ MCD_OPC_Decode, 181, 26, 147, 2, // Opcode: SQXTUNv8i16 +/* 50300 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 50338 +/* 50305 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50308 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50323 +/* 50313 */ MCD_OPC_CheckPredicate, 4, 22, 143, 0, // Skip to: 86948 +/* 50318 */ MCD_OPC_Decode, 160, 6, 133, 2, // Opcode: FACGEv8f16 +/* 50323 */ MCD_OPC_FilterValue, 1, 12, 143, 0, // Skip to: 86948 +/* 50328 */ MCD_OPC_CheckPredicate, 3, 7, 143, 0, // Skip to: 86948 +/* 50333 */ MCD_OPC_Decode, 206, 33, 133, 2, // Opcode: UQSUBv8i16 +/* 50338 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50360 +/* 50343 */ MCD_OPC_CheckPredicate, 3, 248, 142, 0, // Skip to: 86948 +/* 50348 */ MCD_OPC_CheckField, 21, 1, 1, 241, 142, 0, // Skip to: 86948 +/* 50355 */ MCD_OPC_Decode, 174, 34, 133, 2, // Opcode: USUBWv8i16_v4i32 +/* 50360 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 50398 +/* 50365 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50368 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50383 +/* 50373 */ MCD_OPC_CheckPredicate, 4, 218, 142, 0, // Skip to: 86948 +/* 50378 */ MCD_OPC_Decode, 230, 9, 133, 2, // Opcode: FMAXPv8f16 +/* 50383 */ MCD_OPC_FilterValue, 1, 208, 142, 0, // Skip to: 86948 +/* 50388 */ MCD_OPC_CheckPredicate, 3, 203, 142, 0, // Skip to: 86948 +/* 50393 */ MCD_OPC_Decode, 236, 3, 133, 2, // Opcode: CMHIv8i16 +/* 50398 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 50451 +/* 50403 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 50406 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50421 +/* 50411 */ MCD_OPC_CheckPredicate, 3, 180, 142, 0, // Skip to: 86948 +/* 50416 */ MCD_OPC_Decode, 154, 34, 147, 2, // Opcode: USQADDv8i16 +/* 50421 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 50436 +/* 50426 */ MCD_OPC_CheckPredicate, 3, 165, 142, 0, // Skip to: 86948 +/* 50431 */ MCD_OPC_Decode, 137, 23, 138, 2, // Opcode: SHLLv8i16 +/* 50436 */ MCD_OPC_FilterValue, 48, 155, 142, 0, // Skip to: 86948 +/* 50441 */ MCD_OPC_CheckPredicate, 3, 150, 142, 0, // Skip to: 86948 +/* 50446 */ MCD_OPC_Decode, 151, 31, 160, 2, // Opcode: UADDLVv8i16v +/* 50451 */ MCD_OPC_FilterValue, 7, 140, 142, 0, // Skip to: 86948 +/* 50456 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50459 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50474 +/* 50464 */ MCD_OPC_CheckPredicate, 4, 127, 142, 0, // Skip to: 86948 +/* 50469 */ MCD_OPC_Decode, 179, 9, 133, 2, // Opcode: FDIVv8f16 +/* 50474 */ MCD_OPC_FilterValue, 1, 117, 142, 0, // Skip to: 86948 +/* 50479 */ MCD_OPC_CheckPredicate, 3, 112, 142, 0, // Skip to: 86948 +/* 50484 */ MCD_OPC_Decode, 244, 3, 133, 2, // Opcode: CMHSv8i16 +/* 50489 */ MCD_OPC_FilterValue, 2, 195, 0, 0, // Skip to: 50689 +/* 50494 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 50497 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50519 +/* 50502 */ MCD_OPC_CheckPredicate, 3, 89, 142, 0, // Skip to: 86948 +/* 50507 */ MCD_OPC_CheckField, 21, 1, 1, 82, 142, 0, // Skip to: 86948 +/* 50514 */ MCD_OPC_Decode, 180, 21, 141, 2, // Opcode: RADDHNv4i32_v8i16 +/* 50519 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 50541 +/* 50524 */ MCD_OPC_CheckPredicate, 3, 67, 142, 0, // Skip to: 86948 +/* 50529 */ MCD_OPC_CheckField, 21, 1, 1, 60, 142, 0, // Skip to: 86948 +/* 50536 */ MCD_OPC_Decode, 135, 34, 133, 2, // Opcode: USHLv8i16 +/* 50541 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50579 +/* 50546 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 50549 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50564 +/* 50554 */ MCD_OPC_CheckPredicate, 3, 37, 142, 0, // Skip to: 86948 +/* 50559 */ MCD_OPC_Decode, 180, 3, 138, 2, // Opcode: CLZv8i16 +/* 50564 */ MCD_OPC_FilterValue, 33, 27, 142, 0, // Skip to: 86948 +/* 50569 */ MCD_OPC_CheckPredicate, 3, 22, 142, 0, // Skip to: 86948 +/* 50574 */ MCD_OPC_Decode, 215, 33, 147, 2, // Opcode: UQXTNv8i16 +/* 50579 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50601 +/* 50584 */ MCD_OPC_CheckPredicate, 3, 7, 142, 0, // Skip to: 86948 +/* 50589 */ MCD_OPC_CheckField, 21, 1, 1, 0, 142, 0, // Skip to: 86948 +/* 50596 */ MCD_OPC_Decode, 176, 33, 133, 2, // Opcode: UQSHLv8i16 +/* 50601 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50623 +/* 50606 */ MCD_OPC_CheckPredicate, 3, 241, 141, 0, // Skip to: 86948 +/* 50611 */ MCD_OPC_CheckField, 21, 1, 1, 234, 141, 0, // Skip to: 86948 +/* 50618 */ MCD_OPC_Decode, 240, 30, 141, 2, // Opcode: UABALv8i16_v4i32 +/* 50623 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 50645 +/* 50628 */ MCD_OPC_CheckPredicate, 3, 219, 141, 0, // Skip to: 86948 +/* 50633 */ MCD_OPC_CheckField, 21, 1, 1, 212, 141, 0, // Skip to: 86948 +/* 50640 */ MCD_OPC_Decode, 231, 33, 133, 2, // Opcode: URSHLv8i16 +/* 50645 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 50667 +/* 50650 */ MCD_OPC_CheckPredicate, 3, 197, 141, 0, // Skip to: 86948 +/* 50655 */ MCD_OPC_CheckField, 16, 6, 32, 190, 141, 0, // Skip to: 86948 +/* 50662 */ MCD_OPC_Decode, 190, 21, 138, 2, // Opcode: RBITv16i8 +/* 50667 */ MCD_OPC_FilterValue, 7, 180, 141, 0, // Skip to: 86948 +/* 50672 */ MCD_OPC_CheckPredicate, 3, 175, 141, 0, // Skip to: 86948 +/* 50677 */ MCD_OPC_CheckField, 21, 1, 1, 168, 141, 0, // Skip to: 86948 +/* 50684 */ MCD_OPC_Decode, 147, 33, 133, 2, // Opcode: UQRSHLv8i16 +/* 50689 */ MCD_OPC_FilterValue, 3, 195, 0, 0, // Skip to: 50889 +/* 50694 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 50697 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50719 +/* 50702 */ MCD_OPC_CheckPredicate, 3, 145, 141, 0, // Skip to: 86948 +/* 50707 */ MCD_OPC_CheckField, 21, 1, 1, 138, 141, 0, // Skip to: 86948 +/* 50714 */ MCD_OPC_Decode, 243, 21, 141, 2, // Opcode: RSUBHNv4i32_v8i16 +/* 50719 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 50741 +/* 50724 */ MCD_OPC_CheckPredicate, 3, 123, 141, 0, // Skip to: 86948 +/* 50729 */ MCD_OPC_CheckField, 21, 1, 1, 116, 141, 0, // Skip to: 86948 +/* 50736 */ MCD_OPC_Decode, 132, 32, 133, 2, // Opcode: UMAXv8i16 +/* 50741 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 50779 +/* 50746 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 50749 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50764 +/* 50754 */ MCD_OPC_CheckPredicate, 3, 93, 141, 0, // Skip to: 86948 +/* 50759 */ MCD_OPC_Decode, 140, 31, 147, 2, // Opcode: UADALPv8i16_v4i32 +/* 50764 */ MCD_OPC_FilterValue, 33, 83, 141, 0, // Skip to: 86948 +/* 50769 */ MCD_OPC_CheckPredicate, 3, 78, 141, 0, // Skip to: 86948 +/* 50774 */ MCD_OPC_Decode, 217, 8, 147, 2, // Opcode: FCVTXNv4f32 +/* 50779 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 50801 +/* 50784 */ MCD_OPC_CheckPredicate, 3, 63, 141, 0, // Skip to: 86948 +/* 50789 */ MCD_OPC_CheckField, 21, 1, 1, 56, 141, 0, // Skip to: 86948 +/* 50796 */ MCD_OPC_Decode, 161, 32, 133, 2, // Opcode: UMINv8i16 +/* 50801 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 50823 +/* 50806 */ MCD_OPC_CheckPredicate, 3, 41, 141, 0, // Skip to: 86948 +/* 50811 */ MCD_OPC_CheckField, 21, 1, 1, 34, 141, 0, // Skip to: 86948 +/* 50818 */ MCD_OPC_Decode, 252, 30, 133, 2, // Opcode: UABDLv8i16_v4i32 +/* 50823 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 50845 +/* 50828 */ MCD_OPC_CheckPredicate, 3, 19, 141, 0, // Skip to: 86948 +/* 50833 */ MCD_OPC_CheckField, 21, 1, 1, 12, 141, 0, // Skip to: 86948 +/* 50840 */ MCD_OPC_Decode, 134, 31, 133, 2, // Opcode: UABDv8i16 +/* 50845 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 50867 +/* 50850 */ MCD_OPC_CheckPredicate, 3, 253, 140, 0, // Skip to: 86948 +/* 50855 */ MCD_OPC_CheckField, 16, 6, 32, 246, 140, 0, // Skip to: 86948 +/* 50862 */ MCD_OPC_Decode, 156, 25, 138, 2, // Opcode: SQNEGv8i16 +/* 50867 */ MCD_OPC_FilterValue, 7, 236, 140, 0, // Skip to: 86948 +/* 50872 */ MCD_OPC_CheckPredicate, 3, 231, 140, 0, // Skip to: 86948 +/* 50877 */ MCD_OPC_CheckField, 21, 1, 1, 224, 140, 0, // Skip to: 86948 +/* 50884 */ MCD_OPC_Decode, 246, 30, 141, 2, // Opcode: UABAv8i16 +/* 50889 */ MCD_OPC_FilterValue, 4, 229, 0, 0, // Skip to: 51123 +/* 50894 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 50897 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 50919 +/* 50902 */ MCD_OPC_CheckPredicate, 3, 201, 140, 0, // Skip to: 86948 +/* 50907 */ MCD_OPC_CheckField, 21, 1, 1, 194, 140, 0, // Skip to: 86948 +/* 50914 */ MCD_OPC_Decode, 171, 32, 141, 2, // Opcode: UMLALv8i16_v4i32 +/* 50919 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 50957 +/* 50924 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 50927 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 50942 +/* 50932 */ MCD_OPC_CheckPredicate, 7, 171, 140, 0, // Skip to: 86948 +/* 50937 */ MCD_OPC_Decode, 168, 25, 141, 2, // Opcode: SQRDMLAHv8i16 +/* 50942 */ MCD_OPC_FilterValue, 1, 161, 140, 0, // Skip to: 86948 +/* 50947 */ MCD_OPC_CheckPredicate, 3, 156, 140, 0, // Skip to: 86948 +/* 50952 */ MCD_OPC_Decode, 133, 30, 133, 2, // Opcode: SUBv8i16 +/* 50957 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 51010 +/* 50962 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 50965 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 50980 +/* 50970 */ MCD_OPC_CheckPredicate, 3, 133, 140, 0, // Skip to: 86948 +/* 50975 */ MCD_OPC_Decode, 211, 3, 138, 2, // Opcode: CMGEv8i16rz +/* 50980 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 50995 +/* 50985 */ MCD_OPC_CheckPredicate, 3, 118, 140, 0, // Skip to: 86948 +/* 50990 */ MCD_OPC_Decode, 231, 11, 138, 2, // Opcode: FRINTAv2f64 +/* 50995 */ MCD_OPC_FilterValue, 57, 108, 140, 0, // Skip to: 86948 +/* 51000 */ MCD_OPC_CheckPredicate, 4, 103, 140, 0, // Skip to: 86948 +/* 51005 */ MCD_OPC_Decode, 234, 11, 138, 2, // Opcode: FRINTAv8f16 +/* 51010 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 51048 +/* 51015 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51018 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51033 +/* 51023 */ MCD_OPC_CheckPredicate, 7, 80, 140, 0, // Skip to: 86948 +/* 51028 */ MCD_OPC_Decode, 180, 25, 141, 2, // Opcode: SQRDMLSHv8i16 +/* 51033 */ MCD_OPC_FilterValue, 1, 70, 140, 0, // Skip to: 86948 +/* 51038 */ MCD_OPC_CheckPredicate, 3, 65, 140, 0, // Skip to: 86948 +/* 51043 */ MCD_OPC_Decode, 194, 3, 133, 2, // Opcode: CMEQv8i16 +/* 51048 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 51070 +/* 51053 */ MCD_OPC_CheckPredicate, 3, 50, 140, 0, // Skip to: 86948 +/* 51058 */ MCD_OPC_CheckField, 21, 1, 1, 43, 140, 0, // Skip to: 86948 +/* 51065 */ MCD_OPC_Decode, 230, 19, 141, 2, // Opcode: MLSv8i16 +/* 51070 */ MCD_OPC_FilterValue, 6, 33, 140, 0, // Skip to: 86948 +/* 51075 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 51078 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 51093 +/* 51083 */ MCD_OPC_CheckPredicate, 3, 20, 140, 0, // Skip to: 86948 +/* 51088 */ MCD_OPC_Decode, 252, 3, 138, 2, // Opcode: CMLEv8i16rz +/* 51093 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51108 +/* 51098 */ MCD_OPC_CheckPredicate, 3, 5, 140, 0, // Skip to: 86948 +/* 51103 */ MCD_OPC_Decode, 158, 12, 138, 2, // Opcode: FRINTXv2f64 +/* 51108 */ MCD_OPC_FilterValue, 57, 251, 139, 0, // Skip to: 86948 +/* 51113 */ MCD_OPC_CheckPredicate, 4, 246, 139, 0, // Skip to: 86948 +/* 51118 */ MCD_OPC_Decode, 161, 12, 138, 2, // Opcode: FRINTXv8f16 +/* 51123 */ MCD_OPC_FilterValue, 5, 212, 0, 0, // Skip to: 51340 +/* 51128 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 51131 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51153 +/* 51136 */ MCD_OPC_CheckPredicate, 3, 223, 139, 0, // Skip to: 86948 +/* 51141 */ MCD_OPC_CheckField, 21, 1, 1, 216, 139, 0, // Skip to: 86948 +/* 51148 */ MCD_OPC_Decode, 181, 32, 141, 2, // Opcode: UMLSLv8i16_v4i32 +/* 51153 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 51175 +/* 51158 */ MCD_OPC_CheckPredicate, 3, 201, 139, 0, // Skip to: 86948 +/* 51163 */ MCD_OPC_CheckField, 21, 1, 1, 194, 139, 0, // Skip to: 86948 +/* 51170 */ MCD_OPC_Decode, 237, 31, 133, 2, // Opcode: UMAXPv8i16 +/* 51175 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 51243 +/* 51180 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 51183 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51198 +/* 51188 */ MCD_OPC_CheckPredicate, 3, 171, 139, 0, // Skip to: 86948 +/* 51193 */ MCD_OPC_Decode, 177, 8, 138, 2, // Opcode: FCVTNUv2f64 +/* 51198 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 51213 +/* 51203 */ MCD_OPC_CheckPredicate, 3, 156, 139, 0, // Skip to: 86948 +/* 51208 */ MCD_OPC_Decode, 246, 31, 152, 2, // Opcode: UMAXVv8i16v +/* 51213 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 51228 +/* 51218 */ MCD_OPC_CheckPredicate, 3, 141, 139, 0, // Skip to: 86948 +/* 51223 */ MCD_OPC_Decode, 147, 32, 152, 2, // Opcode: UMINVv8i16v +/* 51228 */ MCD_OPC_FilterValue, 57, 131, 139, 0, // Skip to: 86948 +/* 51233 */ MCD_OPC_CheckPredicate, 4, 126, 139, 0, // Skip to: 86948 +/* 51238 */ MCD_OPC_Decode, 180, 8, 138, 2, // Opcode: FCVTNUv8f16 +/* 51243 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 51265 +/* 51248 */ MCD_OPC_CheckPredicate, 3, 111, 139, 0, // Skip to: 86948 +/* 51253 */ MCD_OPC_CheckField, 21, 1, 1, 104, 139, 0, // Skip to: 86948 +/* 51260 */ MCD_OPC_Decode, 138, 32, 133, 2, // Opcode: UMINPv8i16 +/* 51265 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 51287 +/* 51270 */ MCD_OPC_CheckPredicate, 3, 89, 139, 0, // Skip to: 86948 +/* 51275 */ MCD_OPC_CheckField, 21, 1, 1, 82, 139, 0, // Skip to: 86948 +/* 51282 */ MCD_OPC_Decode, 192, 25, 133, 2, // Opcode: SQRDMULHv8i16 +/* 51287 */ MCD_OPC_FilterValue, 6, 72, 139, 0, // Skip to: 86948 +/* 51292 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 51295 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 51310 +/* 51300 */ MCD_OPC_CheckPredicate, 3, 59, 139, 0, // Skip to: 86948 +/* 51305 */ MCD_OPC_Decode, 185, 20, 138, 2, // Opcode: NEGv8i16 +/* 51310 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51325 +/* 51315 */ MCD_OPC_CheckPredicate, 3, 44, 139, 0, // Skip to: 86948 +/* 51320 */ MCD_OPC_Decode, 149, 8, 138, 2, // Opcode: FCVTMUv2f64 +/* 51325 */ MCD_OPC_FilterValue, 57, 34, 139, 0, // Skip to: 86948 +/* 51330 */ MCD_OPC_CheckPredicate, 4, 29, 139, 0, // Skip to: 86948 +/* 51335 */ MCD_OPC_Decode, 152, 8, 138, 2, // Opcode: FCVTMUv8f16 +/* 51340 */ MCD_OPC_FilterValue, 6, 185, 0, 0, // Skip to: 51530 +/* 51345 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 51348 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 51454 +/* 51353 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 51356 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51378 +/* 51361 */ MCD_OPC_CheckPredicate, 3, 254, 138, 0, // Skip to: 86948 +/* 51366 */ MCD_OPC_CheckField, 21, 1, 1, 247, 138, 0, // Skip to: 86948 +/* 51373 */ MCD_OPC_Decode, 201, 32, 133, 2, // Opcode: UMULLv8i16_v4i32 +/* 51378 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 51416 +/* 51383 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 51386 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51401 +/* 51391 */ MCD_OPC_CheckPredicate, 3, 224, 138, 0, // Skip to: 86948 +/* 51396 */ MCD_OPC_Decode, 241, 7, 138, 2, // Opcode: FCVTAUv2f64 +/* 51401 */ MCD_OPC_FilterValue, 57, 214, 138, 0, // Skip to: 86948 +/* 51406 */ MCD_OPC_CheckPredicate, 4, 209, 138, 0, // Skip to: 86948 +/* 51411 */ MCD_OPC_Decode, 244, 7, 138, 2, // Opcode: FCVTAUv8f16 +/* 51416 */ MCD_OPC_FilterValue, 3, 199, 138, 0, // Skip to: 86948 +/* 51421 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 51424 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 51439 +/* 51429 */ MCD_OPC_CheckPredicate, 3, 186, 138, 0, // Skip to: 86948 +/* 51434 */ MCD_OPC_Decode, 197, 31, 138, 2, // Opcode: UCVTFv2f64 +/* 51439 */ MCD_OPC_FilterValue, 57, 176, 138, 0, // Skip to: 86948 +/* 51444 */ MCD_OPC_CheckPredicate, 4, 171, 138, 0, // Skip to: 86948 +/* 51449 */ MCD_OPC_Decode, 204, 31, 138, 2, // Opcode: UCVTFv8f16 +/* 51454 */ MCD_OPC_FilterValue, 1, 161, 138, 0, // Skip to: 86948 +/* 51459 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51462 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51477 +/* 51467 */ MCD_OPC_CheckPredicate, 8, 148, 138, 0, // Skip to: 86948 +/* 51472 */ MCD_OPC_Decode, 166, 7, 169, 2, // Opcode: FCMLAv8f16 +/* 51477 */ MCD_OPC_FilterValue, 1, 138, 138, 0, // Skip to: 86948 +/* 51482 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 51485 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51500 +/* 51490 */ MCD_OPC_CheckPredicate, 3, 125, 138, 0, // Skip to: 86948 +/* 51495 */ MCD_OPC_Decode, 198, 9, 133, 2, // Opcode: FMAXNMPv2f64 +/* 51500 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 51515 +/* 51505 */ MCD_OPC_CheckPredicate, 3, 110, 138, 0, // Skip to: 86948 +/* 51510 */ MCD_OPC_Decode, 178, 6, 133, 2, // Opcode: FADDPv2f64 +/* 51515 */ MCD_OPC_FilterValue, 3, 100, 138, 0, // Skip to: 86948 +/* 51520 */ MCD_OPC_CheckPredicate, 3, 95, 138, 0, // Skip to: 86948 +/* 51525 */ MCD_OPC_Decode, 155, 11, 133, 2, // Opcode: FMULv2f64 +/* 51530 */ MCD_OPC_FilterValue, 7, 85, 138, 0, // Skip to: 86948 +/* 51535 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 51538 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 51599 +/* 51543 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51546 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51561 +/* 51551 */ MCD_OPC_CheckPredicate, 8, 64, 138, 0, // Skip to: 86948 +/* 51556 */ MCD_OPC_Decode, 210, 6, 170, 2, // Opcode: FCADDv8f16 +/* 51561 */ MCD_OPC_FilterValue, 1, 54, 138, 0, // Skip to: 86948 +/* 51566 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 51569 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51584 +/* 51574 */ MCD_OPC_CheckPredicate, 3, 41, 138, 0, // Skip to: 86948 +/* 51579 */ MCD_OPC_Decode, 252, 6, 133, 2, // Opcode: FCMGEv2f64 +/* 51584 */ MCD_OPC_FilterValue, 1, 31, 138, 0, // Skip to: 86948 +/* 51589 */ MCD_OPC_CheckPredicate, 3, 26, 138, 0, // Skip to: 86948 +/* 51594 */ MCD_OPC_Decode, 224, 9, 133, 2, // Opcode: FMAXPv2f64 +/* 51599 */ MCD_OPC_FilterValue, 3, 16, 138, 0, // Skip to: 86948 +/* 51604 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 51607 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51629 +/* 51612 */ MCD_OPC_CheckPredicate, 3, 3, 138, 0, // Skip to: 86948 +/* 51617 */ MCD_OPC_CheckField, 21, 1, 1, 252, 137, 0, // Skip to: 86948 +/* 51624 */ MCD_OPC_Decode, 157, 6, 133, 2, // Opcode: FACGEv2f64 +/* 51629 */ MCD_OPC_FilterValue, 1, 242, 137, 0, // Skip to: 86948 +/* 51634 */ MCD_OPC_CheckPredicate, 3, 237, 137, 0, // Skip to: 86948 +/* 51639 */ MCD_OPC_CheckField, 21, 1, 1, 230, 137, 0, // Skip to: 86948 +/* 51646 */ MCD_OPC_Decode, 176, 9, 133, 2, // Opcode: FDIVv2f64 +/* 51651 */ MCD_OPC_FilterValue, 6, 220, 137, 0, // Skip to: 86948 +/* 51656 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 51659 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51681 +/* 51664 */ MCD_OPC_CheckPredicate, 9, 207, 137, 0, // Skip to: 86948 +/* 51669 */ MCD_OPC_CheckField, 21, 1, 0, 200, 137, 0, // Skip to: 86948 +/* 51676 */ MCD_OPC_Decode, 169, 23, 165, 2, // Opcode: SM3SS1 +/* 51681 */ MCD_OPC_FilterValue, 1, 190, 137, 0, // Skip to: 86948 +/* 51686 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 51689 */ MCD_OPC_FilterValue, 0, 77, 0, 0, // Skip to: 51771 +/* 51694 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 51697 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51742 +/* 51702 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51705 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51720 +/* 51710 */ MCD_OPC_CheckPredicate, 9, 161, 137, 0, // Skip to: 86948 +/* 51715 */ MCD_OPC_Decode, 170, 23, 171, 2, // Opcode: SM3TT1A +/* 51720 */ MCD_OPC_FilterValue, 1, 151, 137, 0, // Skip to: 86948 +/* 51725 */ MCD_OPC_CheckPredicate, 6, 146, 137, 0, // Skip to: 86948 +/* 51730 */ MCD_OPC_CheckField, 12, 2, 0, 139, 137, 0, // Skip to: 86948 +/* 51737 */ MCD_OPC_Decode, 251, 22, 141, 2, // Opcode: SHA512H +/* 51742 */ MCD_OPC_FilterValue, 1, 129, 137, 0, // Skip to: 86948 +/* 51747 */ MCD_OPC_CheckPredicate, 9, 124, 137, 0, // Skip to: 86948 +/* 51752 */ MCD_OPC_CheckField, 21, 1, 1, 117, 137, 0, // Skip to: 86948 +/* 51759 */ MCD_OPC_CheckField, 12, 2, 0, 110, 137, 0, // Skip to: 86948 +/* 51766 */ MCD_OPC_Decode, 167, 23, 141, 2, // Opcode: SM3PARTW1 +/* 51771 */ MCD_OPC_FilterValue, 1, 77, 0, 0, // Skip to: 51853 +/* 51776 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 51779 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51824 +/* 51784 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51787 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51802 +/* 51792 */ MCD_OPC_CheckPredicate, 9, 79, 137, 0, // Skip to: 86948 +/* 51797 */ MCD_OPC_Decode, 171, 23, 171, 2, // Opcode: SM3TT1B +/* 51802 */ MCD_OPC_FilterValue, 1, 69, 137, 0, // Skip to: 86948 +/* 51807 */ MCD_OPC_CheckPredicate, 6, 64, 137, 0, // Skip to: 86948 +/* 51812 */ MCD_OPC_CheckField, 12, 2, 0, 57, 137, 0, // Skip to: 86948 +/* 51819 */ MCD_OPC_Decode, 252, 22, 141, 2, // Opcode: SHA512H2 +/* 51824 */ MCD_OPC_FilterValue, 1, 47, 137, 0, // Skip to: 86948 +/* 51829 */ MCD_OPC_CheckPredicate, 9, 42, 137, 0, // Skip to: 86948 +/* 51834 */ MCD_OPC_CheckField, 21, 1, 1, 35, 137, 0, // Skip to: 86948 +/* 51841 */ MCD_OPC_CheckField, 12, 2, 0, 28, 137, 0, // Skip to: 86948 +/* 51848 */ MCD_OPC_Decode, 168, 23, 141, 2, // Opcode: SM3PARTW2 +/* 51853 */ MCD_OPC_FilterValue, 2, 77, 0, 0, // Skip to: 51935 +/* 51858 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 51861 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 51906 +/* 51866 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51869 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 51884 +/* 51874 */ MCD_OPC_CheckPredicate, 9, 253, 136, 0, // Skip to: 86948 +/* 51879 */ MCD_OPC_Decode, 172, 23, 171, 2, // Opcode: SM3TT2A +/* 51884 */ MCD_OPC_FilterValue, 1, 243, 136, 0, // Skip to: 86948 +/* 51889 */ MCD_OPC_CheckPredicate, 6, 238, 136, 0, // Skip to: 86948 +/* 51894 */ MCD_OPC_CheckField, 12, 2, 0, 231, 136, 0, // Skip to: 86948 +/* 51901 */ MCD_OPC_Decode, 254, 22, 141, 2, // Opcode: SHA512SU1 +/* 51906 */ MCD_OPC_FilterValue, 1, 221, 136, 0, // Skip to: 86948 +/* 51911 */ MCD_OPC_CheckPredicate, 9, 216, 136, 0, // Skip to: 86948 +/* 51916 */ MCD_OPC_CheckField, 21, 1, 1, 209, 136, 0, // Skip to: 86948 +/* 51923 */ MCD_OPC_CheckField, 12, 2, 0, 202, 136, 0, // Skip to: 86948 +/* 51930 */ MCD_OPC_Decode, 175, 23, 133, 2, // Opcode: SM4ENCKEY +/* 51935 */ MCD_OPC_FilterValue, 3, 192, 136, 0, // Skip to: 86948 +/* 51940 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 51943 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 51965 +/* 51948 */ MCD_OPC_CheckPredicate, 9, 179, 136, 0, // Skip to: 86948 +/* 51953 */ MCD_OPC_CheckField, 14, 1, 0, 172, 136, 0, // Skip to: 86948 +/* 51960 */ MCD_OPC_Decode, 173, 23, 171, 2, // Opcode: SM3TT2B +/* 51965 */ MCD_OPC_FilterValue, 1, 162, 136, 0, // Skip to: 86948 +/* 51970 */ MCD_OPC_CheckPredicate, 6, 157, 136, 0, // Skip to: 86948 +/* 51975 */ MCD_OPC_CheckField, 12, 3, 0, 150, 136, 0, // Skip to: 86948 +/* 51982 */ MCD_OPC_Decode, 183, 21, 133, 2, // Opcode: RAX1 +/* 51987 */ MCD_OPC_FilterValue, 10, 249, 23, 0, // Skip to: 58129 +/* 51992 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 51995 */ MCD_OPC_FilterValue, 0, 32, 6, 0, // Skip to: 53568 +/* 52000 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 52003 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 52025 +/* 52008 */ MCD_OPC_CheckPredicate, 3, 119, 136, 0, // Skip to: 86948 +/* 52013 */ MCD_OPC_CheckField, 21, 1, 1, 112, 136, 0, // Skip to: 86948 +/* 52020 */ MCD_OPC_Decode, 164, 22, 234, 1, // Opcode: SADDLv2i32_v2i64 +/* 52025 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 52047 +/* 52030 */ MCD_OPC_CheckPredicate, 3, 97, 136, 0, // Skip to: 86948 +/* 52035 */ MCD_OPC_CheckField, 21, 1, 1, 90, 136, 0, // Skip to: 86948 +/* 52042 */ MCD_OPC_Decode, 128, 23, 238, 1, // Opcode: SHADDv2i32 +/* 52047 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 52069 +/* 52052 */ MCD_OPC_CheckPredicate, 3, 75, 136, 0, // Skip to: 86948 +/* 52057 */ MCD_OPC_CheckField, 16, 6, 32, 68, 136, 0, // Skip to: 86948 +/* 52064 */ MCD_OPC_Decode, 210, 21, 239, 1, // Opcode: REV64v2i32 +/* 52069 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 52091 +/* 52074 */ MCD_OPC_CheckPredicate, 3, 53, 136, 0, // Skip to: 86948 +/* 52079 */ MCD_OPC_CheckField, 21, 1, 1, 46, 136, 0, // Skip to: 86948 +/* 52086 */ MCD_OPC_Decode, 177, 24, 238, 1, // Opcode: SQADDv2i32 +/* 52091 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 52113 +/* 52096 */ MCD_OPC_CheckPredicate, 3, 31, 136, 0, // Skip to: 86948 +/* 52101 */ MCD_OPC_CheckField, 21, 1, 1, 24, 136, 0, // Skip to: 86948 +/* 52108 */ MCD_OPC_Decode, 173, 22, 242, 1, // Opcode: SADDWv2i32_v2i64 +/* 52113 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 52135 +/* 52118 */ MCD_OPC_CheckPredicate, 3, 9, 136, 0, // Skip to: 86948 +/* 52123 */ MCD_OPC_CheckField, 21, 1, 1, 2, 136, 0, // Skip to: 86948 +/* 52130 */ MCD_OPC_Decode, 184, 26, 238, 1, // Opcode: SRHADDv2i32 +/* 52135 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 52157 +/* 52140 */ MCD_OPC_CheckPredicate, 3, 243, 135, 0, // Skip to: 86948 +/* 52145 */ MCD_OPC_CheckField, 21, 1, 0, 236, 135, 0, // Skip to: 86948 +/* 52152 */ MCD_OPC_Decode, 197, 34, 238, 1, // Opcode: UZP1v2i32 +/* 52157 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 52179 +/* 52162 */ MCD_OPC_CheckPredicate, 3, 221, 135, 0, // Skip to: 86948 +/* 52167 */ MCD_OPC_CheckField, 21, 1, 1, 214, 135, 0, // Skip to: 86948 +/* 52174 */ MCD_OPC_Decode, 222, 20, 238, 1, // Opcode: ORRv8i8 +/* 52179 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 52201 +/* 52184 */ MCD_OPC_CheckPredicate, 3, 199, 135, 0, // Skip to: 86948 +/* 52189 */ MCD_OPC_CheckField, 21, 1, 1, 192, 135, 0, // Skip to: 86948 +/* 52196 */ MCD_OPC_Decode, 162, 27, 234, 1, // Opcode: SSUBLv2i32_v2i64 +/* 52201 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 52223 +/* 52206 */ MCD_OPC_CheckPredicate, 3, 177, 135, 0, // Skip to: 86948 +/* 52211 */ MCD_OPC_CheckField, 21, 1, 1, 170, 135, 0, // Skip to: 86948 +/* 52218 */ MCD_OPC_Decode, 154, 23, 238, 1, // Opcode: SHSUBv2i32 +/* 52223 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 52284 +/* 52228 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 52231 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52246 +/* 52236 */ MCD_OPC_CheckPredicate, 3, 147, 135, 0, // Skip to: 86948 +/* 52241 */ MCD_OPC_Decode, 214, 30, 238, 1, // Opcode: TRN1v2i32 +/* 52246 */ MCD_OPC_FilterValue, 1, 137, 135, 0, // Skip to: 86948 +/* 52251 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 52254 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52269 +/* 52259 */ MCD_OPC_CheckPredicate, 3, 124, 135, 0, // Skip to: 86948 +/* 52264 */ MCD_OPC_Decode, 153, 22, 239, 1, // Opcode: SADDLPv2i32_v1i64 +/* 52269 */ MCD_OPC_FilterValue, 1, 114, 135, 0, // Skip to: 86948 +/* 52274 */ MCD_OPC_CheckPredicate, 3, 109, 135, 0, // Skip to: 86948 +/* 52279 */ MCD_OPC_Decode, 128, 35, 244, 1, // Opcode: XTNv2i32 +/* 52284 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 52306 +/* 52289 */ MCD_OPC_CheckPredicate, 3, 94, 135, 0, // Skip to: 86948 +/* 52294 */ MCD_OPC_CheckField, 21, 1, 1, 87, 135, 0, // Skip to: 86948 +/* 52301 */ MCD_OPC_Decode, 159, 26, 238, 1, // Opcode: SQSUBv2i32 +/* 52306 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 52328 +/* 52311 */ MCD_OPC_CheckPredicate, 3, 72, 135, 0, // Skip to: 86948 +/* 52316 */ MCD_OPC_CheckField, 21, 1, 1, 65, 135, 0, // Skip to: 86948 +/* 52323 */ MCD_OPC_Decode, 168, 27, 242, 1, // Opcode: SSUBWv2i32_v2i64 +/* 52328 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 52350 +/* 52333 */ MCD_OPC_CheckPredicate, 3, 50, 135, 0, // Skip to: 86948 +/* 52338 */ MCD_OPC_CheckField, 21, 1, 1, 43, 135, 0, // Skip to: 86948 +/* 52345 */ MCD_OPC_Decode, 218, 3, 238, 1, // Opcode: CMGTv2i32 +/* 52350 */ MCD_OPC_FilterValue, 14, 40, 0, 0, // Skip to: 52395 +/* 52355 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 52358 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52373 +/* 52363 */ MCD_OPC_CheckPredicate, 3, 20, 135, 0, // Skip to: 86948 +/* 52368 */ MCD_OPC_Decode, 142, 35, 238, 1, // Opcode: ZIP1v2i32 +/* 52373 */ MCD_OPC_FilterValue, 1, 10, 135, 0, // Skip to: 86948 +/* 52378 */ MCD_OPC_CheckPredicate, 3, 5, 135, 0, // Skip to: 86948 +/* 52383 */ MCD_OPC_CheckField, 16, 5, 0, 254, 134, 0, // Skip to: 86948 +/* 52390 */ MCD_OPC_Decode, 146, 30, 248, 1, // Opcode: SUQADDv2i32 +/* 52395 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 52417 +/* 52400 */ MCD_OPC_CheckPredicate, 3, 239, 134, 0, // Skip to: 86948 +/* 52405 */ MCD_OPC_CheckField, 21, 1, 1, 232, 134, 0, // Skip to: 86948 +/* 52412 */ MCD_OPC_Decode, 202, 3, 238, 1, // Opcode: CMGEv2i32 +/* 52417 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 52439 +/* 52422 */ MCD_OPC_CheckPredicate, 3, 217, 134, 0, // Skip to: 86948 +/* 52427 */ MCD_OPC_CheckField, 21, 1, 1, 210, 134, 0, // Skip to: 86948 +/* 52434 */ MCD_OPC_Decode, 142, 1, 252, 1, // Opcode: ADDHNv2i64_v2i32 +/* 52439 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 52461 +/* 52444 */ MCD_OPC_CheckPredicate, 3, 195, 134, 0, // Skip to: 86948 +/* 52449 */ MCD_OPC_CheckField, 21, 1, 1, 188, 134, 0, // Skip to: 86948 +/* 52456 */ MCD_OPC_Decode, 229, 26, 238, 1, // Opcode: SSHLv2i32 +/* 52461 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 52499 +/* 52466 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 52469 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 52484 +/* 52474 */ MCD_OPC_CheckPredicate, 3, 165, 134, 0, // Skip to: 86948 +/* 52479 */ MCD_OPC_Decode, 165, 3, 239, 1, // Opcode: CLSv2i32 +/* 52484 */ MCD_OPC_FilterValue, 33, 155, 134, 0, // Skip to: 86948 +/* 52489 */ MCD_OPC_CheckPredicate, 3, 150, 134, 0, // Skip to: 86948 +/* 52494 */ MCD_OPC_Decode, 169, 26, 244, 1, // Opcode: SQXTNv2i32 +/* 52499 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 52521 +/* 52504 */ MCD_OPC_CheckPredicate, 3, 135, 134, 0, // Skip to: 86948 +/* 52509 */ MCD_OPC_CheckField, 21, 1, 1, 128, 134, 0, // Skip to: 86948 +/* 52516 */ MCD_OPC_Decode, 244, 25, 238, 1, // Opcode: SQSHLv2i32 +/* 52521 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 52543 +/* 52526 */ MCD_OPC_CheckPredicate, 3, 113, 134, 0, // Skip to: 86948 +/* 52531 */ MCD_OPC_CheckField, 21, 1, 1, 106, 134, 0, // Skip to: 86948 +/* 52538 */ MCD_OPC_Decode, 247, 21, 254, 1, // Opcode: SABALv2i32_v2i64 +/* 52543 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 52565 +/* 52548 */ MCD_OPC_CheckPredicate, 3, 91, 134, 0, // Skip to: 86948 +/* 52553 */ MCD_OPC_CheckField, 21, 1, 1, 84, 134, 0, // Skip to: 86948 +/* 52560 */ MCD_OPC_Decode, 199, 26, 238, 1, // Opcode: SRSHLv2i32 +/* 52565 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 52587 +/* 52570 */ MCD_OPC_CheckPredicate, 3, 69, 134, 0, // Skip to: 86948 +/* 52575 */ MCD_OPC_CheckField, 21, 1, 0, 62, 134, 0, // Skip to: 86948 +/* 52582 */ MCD_OPC_Decode, 212, 34, 238, 1, // Opcode: UZP2v2i32 +/* 52587 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 52609 +/* 52592 */ MCD_OPC_CheckPredicate, 3, 47, 134, 0, // Skip to: 86948 +/* 52597 */ MCD_OPC_CheckField, 21, 1, 1, 40, 134, 0, // Skip to: 86948 +/* 52604 */ MCD_OPC_Decode, 199, 25, 238, 1, // Opcode: SQRSHLv2i32 +/* 52609 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 52631 +/* 52614 */ MCD_OPC_CheckPredicate, 3, 25, 134, 0, // Skip to: 86948 +/* 52619 */ MCD_OPC_CheckField, 21, 1, 1, 18, 134, 0, // Skip to: 86948 +/* 52626 */ MCD_OPC_Decode, 211, 29, 252, 1, // Opcode: SUBHNv2i64_v2i32 +/* 52631 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 52653 +/* 52636 */ MCD_OPC_CheckPredicate, 3, 3, 134, 0, // Skip to: 86948 +/* 52641 */ MCD_OPC_CheckField, 21, 1, 1, 252, 133, 0, // Skip to: 86948 +/* 52648 */ MCD_OPC_Decode, 201, 23, 238, 1, // Opcode: SMAXv2i32 +/* 52653 */ MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 52698 +/* 52658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 52661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52676 +/* 52666 */ MCD_OPC_CheckPredicate, 3, 229, 133, 0, // Skip to: 86948 +/* 52671 */ MCD_OPC_Decode, 229, 30, 238, 1, // Opcode: TRN2v2i32 +/* 52676 */ MCD_OPC_FilterValue, 1, 219, 133, 0, // Skip to: 86948 +/* 52681 */ MCD_OPC_CheckPredicate, 3, 214, 133, 0, // Skip to: 86948 +/* 52686 */ MCD_OPC_CheckField, 16, 5, 0, 207, 133, 0, // Skip to: 86948 +/* 52693 */ MCD_OPC_Decode, 147, 22, 248, 1, // Opcode: SADALPv2i32_v1i64 +/* 52698 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 52720 +/* 52703 */ MCD_OPC_CheckPredicate, 3, 192, 133, 0, // Skip to: 86948 +/* 52708 */ MCD_OPC_CheckField, 21, 1, 1, 185, 133, 0, // Skip to: 86948 +/* 52715 */ MCD_OPC_Decode, 231, 23, 238, 1, // Opcode: SMINv2i32 +/* 52720 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 52742 +/* 52725 */ MCD_OPC_CheckPredicate, 3, 170, 133, 0, // Skip to: 86948 +/* 52730 */ MCD_OPC_CheckField, 21, 1, 1, 163, 133, 0, // Skip to: 86948 +/* 52737 */ MCD_OPC_Decode, 131, 22, 234, 1, // Opcode: SABDLv2i32_v2i64 +/* 52742 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 52764 +/* 52747 */ MCD_OPC_CheckPredicate, 3, 148, 133, 0, // Skip to: 86948 +/* 52752 */ MCD_OPC_CheckField, 21, 1, 1, 141, 133, 0, // Skip to: 86948 +/* 52759 */ MCD_OPC_Decode, 141, 22, 238, 1, // Opcode: SABDv2i32 +/* 52764 */ MCD_OPC_FilterValue, 30, 40, 0, 0, // Skip to: 52809 +/* 52769 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 52772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52787 +/* 52777 */ MCD_OPC_CheckPredicate, 3, 118, 133, 0, // Skip to: 86948 +/* 52782 */ MCD_OPC_Decode, 157, 35, 238, 1, // Opcode: ZIP2v2i32 +/* 52787 */ MCD_OPC_FilterValue, 1, 108, 133, 0, // Skip to: 86948 +/* 52792 */ MCD_OPC_CheckPredicate, 3, 103, 133, 0, // Skip to: 86948 +/* 52797 */ MCD_OPC_CheckField, 16, 5, 0, 96, 133, 0, // Skip to: 86948 +/* 52804 */ MCD_OPC_Decode, 158, 24, 239, 1, // Opcode: SQABSv2i32 +/* 52809 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 52831 +/* 52814 */ MCD_OPC_CheckPredicate, 3, 81, 133, 0, // Skip to: 86948 +/* 52819 */ MCD_OPC_CheckField, 21, 1, 1, 74, 133, 0, // Skip to: 86948 +/* 52826 */ MCD_OPC_Decode, 253, 21, 130, 2, // Opcode: SABAv2i32 +/* 52831 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 52853 +/* 52836 */ MCD_OPC_CheckPredicate, 3, 59, 133, 0, // Skip to: 86948 +/* 52841 */ MCD_OPC_CheckField, 21, 1, 1, 52, 133, 0, // Skip to: 86948 +/* 52848 */ MCD_OPC_Decode, 238, 23, 254, 1, // Opcode: SMLALv2i32_v2i64 +/* 52853 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 52875 +/* 52858 */ MCD_OPC_CheckPredicate, 3, 37, 133, 0, // Skip to: 86948 +/* 52863 */ MCD_OPC_CheckField, 21, 1, 1, 30, 133, 0, // Skip to: 86948 +/* 52870 */ MCD_OPC_Decode, 196, 1, 238, 1, // Opcode: ADDv2i32 +/* 52875 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 52913 +/* 52880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 52883 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 52898 +/* 52888 */ MCD_OPC_CheckPredicate, 3, 7, 133, 0, // Skip to: 86948 +/* 52893 */ MCD_OPC_Decode, 219, 3, 239, 1, // Opcode: CMGTv2i32rz +/* 52898 */ MCD_OPC_FilterValue, 33, 253, 132, 0, // Skip to: 86948 +/* 52903 */ MCD_OPC_CheckPredicate, 3, 248, 132, 0, // Skip to: 86948 +/* 52908 */ MCD_OPC_Decode, 146, 12, 239, 1, // Opcode: FRINTPv2f32 +/* 52913 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 52935 +/* 52918 */ MCD_OPC_CheckPredicate, 3, 233, 132, 0, // Skip to: 86948 +/* 52923 */ MCD_OPC_CheckField, 21, 1, 1, 226, 132, 0, // Skip to: 86948 +/* 52930 */ MCD_OPC_Decode, 235, 4, 238, 1, // Opcode: CMTSTv2i32 +/* 52935 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 52957 +/* 52940 */ MCD_OPC_CheckPredicate, 3, 211, 132, 0, // Skip to: 86948 +/* 52945 */ MCD_OPC_CheckField, 21, 1, 1, 204, 132, 0, // Skip to: 86948 +/* 52952 */ MCD_OPC_Decode, 210, 24, 254, 1, // Opcode: SQDMLALv2i32_v2i64 +/* 52957 */ MCD_OPC_FilterValue, 37, 33, 0, 0, // Skip to: 52995 +/* 52962 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 52965 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 52980 +/* 52970 */ MCD_OPC_CheckPredicate, 10, 181, 132, 0, // Skip to: 86948 +/* 52975 */ MCD_OPC_Decode, 232, 22, 130, 2, // Opcode: SDOTv8i8 +/* 52980 */ MCD_OPC_FilterValue, 1, 171, 132, 0, // Skip to: 86948 +/* 52985 */ MCD_OPC_CheckPredicate, 3, 166, 132, 0, // Skip to: 86948 +/* 52990 */ MCD_OPC_Decode, 210, 19, 130, 2, // Opcode: MLAv2i32 +/* 52995 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 53033 +/* 53000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53018 +/* 53008 */ MCD_OPC_CheckPredicate, 3, 143, 132, 0, // Skip to: 86948 +/* 53013 */ MCD_OPC_Decode, 187, 3, 239, 1, // Opcode: CMEQv2i32rz +/* 53018 */ MCD_OPC_FilterValue, 33, 133, 132, 0, // Skip to: 86948 +/* 53023 */ MCD_OPC_CheckPredicate, 3, 128, 132, 0, // Skip to: 86948 +/* 53028 */ MCD_OPC_Decode, 168, 12, 239, 1, // Opcode: FRINTZv2f32 +/* 53033 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 53055 +/* 53038 */ MCD_OPC_CheckPredicate, 3, 113, 132, 0, // Skip to: 86948 +/* 53043 */ MCD_OPC_CheckField, 21, 1, 1, 106, 132, 0, // Skip to: 86948 +/* 53050 */ MCD_OPC_Decode, 158, 20, 238, 1, // Opcode: MULv2i32 +/* 53055 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 53077 +/* 53060 */ MCD_OPC_CheckPredicate, 3, 91, 132, 0, // Skip to: 86948 +/* 53065 */ MCD_OPC_CheckField, 21, 1, 1, 84, 132, 0, // Skip to: 86948 +/* 53072 */ MCD_OPC_Decode, 248, 23, 254, 1, // Opcode: SMLSLv2i32_v2i64 +/* 53077 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 53099 +/* 53082 */ MCD_OPC_CheckPredicate, 3, 69, 132, 0, // Skip to: 86948 +/* 53087 */ MCD_OPC_CheckField, 21, 1, 1, 62, 132, 0, // Skip to: 86948 +/* 53094 */ MCD_OPC_Decode, 178, 23, 238, 1, // Opcode: SMAXPv2i32 +/* 53099 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 53137 +/* 53104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53107 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53122 +/* 53112 */ MCD_OPC_CheckPredicate, 3, 39, 132, 0, // Skip to: 86948 +/* 53117 */ MCD_OPC_Decode, 128, 4, 239, 1, // Opcode: CMLTv2i32rz +/* 53122 */ MCD_OPC_FilterValue, 33, 29, 132, 0, // Skip to: 86948 +/* 53127 */ MCD_OPC_CheckPredicate, 3, 24, 132, 0, // Skip to: 86948 +/* 53132 */ MCD_OPC_Decode, 194, 8, 239, 1, // Opcode: FCVTPSv2f32 +/* 53137 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 53159 +/* 53142 */ MCD_OPC_CheckPredicate, 3, 9, 132, 0, // Skip to: 86948 +/* 53147 */ MCD_OPC_CheckField, 21, 1, 1, 2, 132, 0, // Skip to: 86948 +/* 53154 */ MCD_OPC_Decode, 208, 23, 238, 1, // Opcode: SMINPv2i32 +/* 53159 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 53181 +/* 53164 */ MCD_OPC_CheckPredicate, 3, 243, 131, 0, // Skip to: 86948 +/* 53169 */ MCD_OPC_CheckField, 21, 1, 1, 236, 131, 0, // Skip to: 86948 +/* 53176 */ MCD_OPC_Decode, 222, 24, 254, 1, // Opcode: SQDMLSLv2i32_v2i64 +/* 53181 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 53203 +/* 53186 */ MCD_OPC_CheckPredicate, 3, 221, 131, 0, // Skip to: 86948 +/* 53191 */ MCD_OPC_CheckField, 21, 1, 1, 214, 131, 0, // Skip to: 86948 +/* 53198 */ MCD_OPC_Decode, 233, 24, 238, 1, // Opcode: SQDMULHv2i32 +/* 53203 */ MCD_OPC_FilterValue, 46, 33, 0, 0, // Skip to: 53241 +/* 53208 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53211 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53226 +/* 53216 */ MCD_OPC_CheckPredicate, 3, 191, 131, 0, // Skip to: 86948 +/* 53221 */ MCD_OPC_Decode, 132, 1, 239, 1, // Opcode: ABSv2i32 +/* 53226 */ MCD_OPC_FilterValue, 33, 181, 131, 0, // Skip to: 86948 +/* 53231 */ MCD_OPC_CheckPredicate, 3, 176, 131, 0, // Skip to: 86948 +/* 53236 */ MCD_OPC_Decode, 243, 8, 239, 1, // Opcode: FCVTZSv2f32 +/* 53241 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 53263 +/* 53246 */ MCD_OPC_CheckPredicate, 3, 161, 131, 0, // Skip to: 86948 +/* 53251 */ MCD_OPC_CheckField, 21, 1, 1, 154, 131, 0, // Skip to: 86948 +/* 53258 */ MCD_OPC_Decode, 150, 1, 238, 1, // Opcode: ADDPv2i32 +/* 53263 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 53285 +/* 53268 */ MCD_OPC_CheckPredicate, 3, 139, 131, 0, // Skip to: 86948 +/* 53273 */ MCD_OPC_CheckField, 21, 1, 1, 132, 131, 0, // Skip to: 86948 +/* 53280 */ MCD_OPC_Decode, 141, 24, 234, 1, // Opcode: SMULLv2i32_v2i64 +/* 53285 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 53307 +/* 53290 */ MCD_OPC_CheckPredicate, 3, 117, 131, 0, // Skip to: 86948 +/* 53295 */ MCD_OPC_CheckField, 21, 1, 1, 110, 131, 0, // Skip to: 86948 +/* 53302 */ MCD_OPC_Decode, 146, 10, 238, 1, // Opcode: FMINNMv2f32 +/* 53307 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 53360 +/* 53312 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53315 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53330 +/* 53320 */ MCD_OPC_CheckPredicate, 3, 87, 131, 0, // Skip to: 86948 +/* 53325 */ MCD_OPC_Decode, 147, 7, 239, 1, // Opcode: FCMGTv2i32rz +/* 53330 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 53345 +/* 53335 */ MCD_OPC_CheckPredicate, 3, 72, 131, 0, // Skip to: 86948 +/* 53340 */ MCD_OPC_Decode, 217, 33, 239, 1, // Opcode: URECPEv2i32 +/* 53345 */ MCD_OPC_FilterValue, 48, 62, 131, 0, // Skip to: 86948 +/* 53350 */ MCD_OPC_CheckPredicate, 4, 57, 131, 0, // Skip to: 86948 +/* 53355 */ MCD_OPC_Decode, 137, 10, 249, 1, // Opcode: FMINNMVv4i16v +/* 53360 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 53382 +/* 53365 */ MCD_OPC_CheckPredicate, 3, 42, 131, 0, // Skip to: 86948 +/* 53370 */ MCD_OPC_CheckField, 21, 1, 1, 35, 131, 0, // Skip to: 86948 +/* 53377 */ MCD_OPC_Decode, 205, 10, 130, 2, // Opcode: FMLSv2f32 +/* 53382 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 53404 +/* 53387 */ MCD_OPC_CheckPredicate, 3, 20, 131, 0, // Skip to: 86948 +/* 53392 */ MCD_OPC_CheckField, 21, 1, 1, 13, 131, 0, // Skip to: 86948 +/* 53399 */ MCD_OPC_Decode, 246, 24, 234, 1, // Opcode: SQDMULLv2i32_v2i64 +/* 53404 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 53426 +/* 53409 */ MCD_OPC_CheckPredicate, 3, 254, 130, 0, // Skip to: 86948 +/* 53414 */ MCD_OPC_CheckField, 21, 1, 1, 247, 130, 0, // Skip to: 86948 +/* 53421 */ MCD_OPC_Decode, 227, 12, 238, 1, // Opcode: FSUBv2f32 +/* 53426 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 53464 +/* 53431 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53434 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53449 +/* 53439 */ MCD_OPC_CheckPredicate, 3, 224, 130, 0, // Skip to: 86948 +/* 53444 */ MCD_OPC_Decode, 231, 6, 239, 1, // Opcode: FCMEQv2i32rz +/* 53449 */ MCD_OPC_FilterValue, 33, 214, 130, 0, // Skip to: 86948 +/* 53454 */ MCD_OPC_CheckPredicate, 3, 209, 130, 0, // Skip to: 86948 +/* 53459 */ MCD_OPC_Decode, 202, 11, 239, 1, // Opcode: FRECPEv2f32 +/* 53464 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 53486 +/* 53469 */ MCD_OPC_CheckPredicate, 3, 194, 130, 0, // Skip to: 86948 +/* 53474 */ MCD_OPC_CheckField, 16, 6, 32, 187, 130, 0, // Skip to: 86948 +/* 53481 */ MCD_OPC_Decode, 185, 7, 239, 1, // Opcode: FCMLTv2i32rz +/* 53486 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 53508 +/* 53491 */ MCD_OPC_CheckPredicate, 3, 172, 130, 0, // Skip to: 86948 +/* 53496 */ MCD_OPC_CheckField, 21, 1, 1, 165, 130, 0, // Skip to: 86948 +/* 53503 */ MCD_OPC_Decode, 172, 10, 238, 1, // Opcode: FMINv2f32 +/* 53508 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 53546 +/* 53513 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53516 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53531 +/* 53521 */ MCD_OPC_CheckPredicate, 3, 142, 130, 0, // Skip to: 86948 +/* 53526 */ MCD_OPC_Decode, 145, 6, 239, 1, // Opcode: FABSv2f32 +/* 53531 */ MCD_OPC_FilterValue, 48, 132, 130, 0, // Skip to: 86948 +/* 53536 */ MCD_OPC_CheckPredicate, 4, 127, 130, 0, // Skip to: 86948 +/* 53541 */ MCD_OPC_Decode, 163, 10, 249, 1, // Opcode: FMINVv4i16v +/* 53546 */ MCD_OPC_FilterValue, 63, 117, 130, 0, // Skip to: 86948 +/* 53551 */ MCD_OPC_CheckPredicate, 3, 112, 130, 0, // Skip to: 86948 +/* 53556 */ MCD_OPC_CheckField, 21, 1, 1, 105, 130, 0, // Skip to: 86948 +/* 53563 */ MCD_OPC_Decode, 190, 12, 238, 1, // Opcode: FRSQRTSv2f32 +/* 53568 */ MCD_OPC_FilterValue, 1, 126, 5, 0, // Skip to: 54979 +/* 53573 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 53576 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 53716 +/* 53581 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 53584 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53606 +/* 53589 */ MCD_OPC_CheckPredicate, 3, 74, 130, 0, // Skip to: 86948 +/* 53594 */ MCD_OPC_CheckField, 21, 1, 1, 67, 130, 0, // Skip to: 86948 +/* 53601 */ MCD_OPC_Decode, 154, 31, 234, 1, // Opcode: UADDLv2i32_v2i64 +/* 53606 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53628 +/* 53611 */ MCD_OPC_CheckPredicate, 3, 52, 130, 0, // Skip to: 86948 +/* 53616 */ MCD_OPC_CheckField, 21, 1, 1, 45, 130, 0, // Skip to: 86948 +/* 53623 */ MCD_OPC_Decode, 221, 31, 238, 1, // Opcode: UHADDv2i32 +/* 53628 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 53650 +/* 53633 */ MCD_OPC_CheckPredicate, 3, 30, 130, 0, // Skip to: 86948 +/* 53638 */ MCD_OPC_CheckField, 21, 1, 1, 23, 130, 0, // Skip to: 86948 +/* 53645 */ MCD_OPC_Decode, 216, 32, 238, 1, // Opcode: UQADDv2i32 +/* 53650 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 53672 +/* 53655 */ MCD_OPC_CheckPredicate, 3, 8, 130, 0, // Skip to: 86948 +/* 53660 */ MCD_OPC_CheckField, 21, 1, 1, 1, 130, 0, // Skip to: 86948 +/* 53667 */ MCD_OPC_Decode, 164, 31, 242, 1, // Opcode: UADDWv2i32_v2i64 +/* 53672 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 53694 +/* 53677 */ MCD_OPC_CheckPredicate, 3, 242, 129, 0, // Skip to: 86948 +/* 53682 */ MCD_OPC_CheckField, 21, 1, 1, 235, 129, 0, // Skip to: 86948 +/* 53689 */ MCD_OPC_Decode, 220, 33, 238, 1, // Opcode: URHADDv2i32 +/* 53694 */ MCD_OPC_FilterValue, 7, 225, 129, 0, // Skip to: 86948 +/* 53699 */ MCD_OPC_CheckPredicate, 3, 220, 129, 0, // Skip to: 86948 +/* 53704 */ MCD_OPC_CheckField, 21, 1, 1, 213, 129, 0, // Skip to: 86948 +/* 53711 */ MCD_OPC_Decode, 196, 2, 130, 2, // Opcode: BITv8i8 +/* 53716 */ MCD_OPC_FilterValue, 1, 211, 0, 0, // Skip to: 53932 +/* 53721 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 53724 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53746 +/* 53729 */ MCD_OPC_CheckPredicate, 3, 190, 129, 0, // Skip to: 86948 +/* 53734 */ MCD_OPC_CheckField, 21, 1, 1, 183, 129, 0, // Skip to: 86948 +/* 53741 */ MCD_OPC_Decode, 165, 34, 234, 1, // Opcode: USUBLv2i32_v2i64 +/* 53746 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53768 +/* 53751 */ MCD_OPC_CheckPredicate, 3, 168, 129, 0, // Skip to: 86948 +/* 53756 */ MCD_OPC_CheckField, 21, 1, 1, 161, 129, 0, // Skip to: 86948 +/* 53763 */ MCD_OPC_Decode, 227, 31, 238, 1, // Opcode: UHSUBv2i32 +/* 53768 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 53806 +/* 53773 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53776 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53791 +/* 53781 */ MCD_OPC_CheckPredicate, 3, 138, 129, 0, // Skip to: 86948 +/* 53786 */ MCD_OPC_Decode, 143, 31, 239, 1, // Opcode: UADDLPv2i32_v1i64 +/* 53791 */ MCD_OPC_FilterValue, 33, 128, 129, 0, // Skip to: 86948 +/* 53796 */ MCD_OPC_CheckPredicate, 3, 123, 129, 0, // Skip to: 86948 +/* 53801 */ MCD_OPC_Decode, 178, 26, 244, 1, // Opcode: SQXTUNv2i32 +/* 53806 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 53828 +/* 53811 */ MCD_OPC_CheckPredicate, 3, 108, 129, 0, // Skip to: 86948 +/* 53816 */ MCD_OPC_CheckField, 21, 1, 1, 101, 129, 0, // Skip to: 86948 +/* 53823 */ MCD_OPC_Decode, 202, 33, 238, 1, // Opcode: UQSUBv2i32 +/* 53828 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 53850 +/* 53833 */ MCD_OPC_CheckPredicate, 3, 86, 129, 0, // Skip to: 86948 +/* 53838 */ MCD_OPC_CheckField, 21, 1, 1, 79, 129, 0, // Skip to: 86948 +/* 53845 */ MCD_OPC_Decode, 171, 34, 242, 1, // Opcode: USUBWv2i32_v2i64 +/* 53850 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 53872 +/* 53855 */ MCD_OPC_CheckPredicate, 3, 64, 129, 0, // Skip to: 86948 +/* 53860 */ MCD_OPC_CheckField, 21, 1, 1, 57, 129, 0, // Skip to: 86948 +/* 53867 */ MCD_OPC_Decode, 232, 3, 238, 1, // Opcode: CMHIv2i32 +/* 53872 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 53910 +/* 53877 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53880 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 53895 +/* 53885 */ MCD_OPC_CheckPredicate, 3, 34, 129, 0, // Skip to: 86948 +/* 53890 */ MCD_OPC_Decode, 150, 34, 248, 1, // Opcode: USQADDv2i32 +/* 53895 */ MCD_OPC_FilterValue, 33, 24, 129, 0, // Skip to: 86948 +/* 53900 */ MCD_OPC_CheckPredicate, 3, 19, 129, 0, // Skip to: 86948 +/* 53905 */ MCD_OPC_Decode, 134, 23, 129, 2, // Opcode: SHLLv2i32 +/* 53910 */ MCD_OPC_FilterValue, 7, 9, 129, 0, // Skip to: 86948 +/* 53915 */ MCD_OPC_CheckPredicate, 3, 4, 129, 0, // Skip to: 86948 +/* 53920 */ MCD_OPC_CheckField, 21, 1, 1, 253, 128, 0, // Skip to: 86948 +/* 53927 */ MCD_OPC_Decode, 240, 3, 238, 1, // Opcode: CMHSv2i32 +/* 53932 */ MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 54110 +/* 53937 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 53940 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 53962 +/* 53945 */ MCD_OPC_CheckPredicate, 3, 230, 128, 0, // Skip to: 86948 +/* 53950 */ MCD_OPC_CheckField, 21, 1, 1, 223, 128, 0, // Skip to: 86948 +/* 53957 */ MCD_OPC_Decode, 177, 21, 252, 1, // Opcode: RADDHNv2i64_v2i32 +/* 53962 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 53984 +/* 53967 */ MCD_OPC_CheckPredicate, 3, 208, 128, 0, // Skip to: 86948 +/* 53972 */ MCD_OPC_CheckField, 21, 1, 1, 201, 128, 0, // Skip to: 86948 +/* 53979 */ MCD_OPC_Decode, 131, 34, 238, 1, // Opcode: USHLv2i32 +/* 53984 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 54022 +/* 53989 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 53992 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54007 +/* 53997 */ MCD_OPC_CheckPredicate, 3, 178, 128, 0, // Skip to: 86948 +/* 54002 */ MCD_OPC_Decode, 177, 3, 239, 1, // Opcode: CLZv2i32 +/* 54007 */ MCD_OPC_FilterValue, 33, 168, 128, 0, // Skip to: 86948 +/* 54012 */ MCD_OPC_CheckPredicate, 3, 163, 128, 0, // Skip to: 86948 +/* 54017 */ MCD_OPC_Decode, 212, 33, 244, 1, // Opcode: UQXTNv2i32 +/* 54022 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54044 +/* 54027 */ MCD_OPC_CheckPredicate, 3, 148, 128, 0, // Skip to: 86948 +/* 54032 */ MCD_OPC_CheckField, 21, 1, 1, 141, 128, 0, // Skip to: 86948 +/* 54039 */ MCD_OPC_Decode, 168, 33, 238, 1, // Opcode: UQSHLv2i32 +/* 54044 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 54066 +/* 54049 */ MCD_OPC_CheckPredicate, 3, 126, 128, 0, // Skip to: 86948 +/* 54054 */ MCD_OPC_CheckField, 21, 1, 1, 119, 128, 0, // Skip to: 86948 +/* 54061 */ MCD_OPC_Decode, 237, 30, 254, 1, // Opcode: UABALv2i32_v2i64 +/* 54066 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54088 +/* 54071 */ MCD_OPC_CheckPredicate, 3, 104, 128, 0, // Skip to: 86948 +/* 54076 */ MCD_OPC_CheckField, 21, 1, 1, 97, 128, 0, // Skip to: 86948 +/* 54083 */ MCD_OPC_Decode, 227, 33, 238, 1, // Opcode: URSHLv2i32 +/* 54088 */ MCD_OPC_FilterValue, 7, 87, 128, 0, // Skip to: 86948 +/* 54093 */ MCD_OPC_CheckPredicate, 3, 82, 128, 0, // Skip to: 86948 +/* 54098 */ MCD_OPC_CheckField, 21, 1, 1, 75, 128, 0, // Skip to: 86948 +/* 54105 */ MCD_OPC_Decode, 143, 33, 238, 1, // Opcode: UQRSHLv2i32 +/* 54110 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 54294 +/* 54115 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 54118 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54140 +/* 54123 */ MCD_OPC_CheckPredicate, 3, 52, 128, 0, // Skip to: 86948 +/* 54128 */ MCD_OPC_CheckField, 21, 1, 1, 45, 128, 0, // Skip to: 86948 +/* 54135 */ MCD_OPC_Decode, 240, 21, 252, 1, // Opcode: RSUBHNv2i64_v2i32 +/* 54140 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 54162 +/* 54145 */ MCD_OPC_CheckPredicate, 3, 30, 128, 0, // Skip to: 86948 +/* 54150 */ MCD_OPC_CheckField, 21, 1, 1, 23, 128, 0, // Skip to: 86948 +/* 54157 */ MCD_OPC_Decode, 129, 32, 238, 1, // Opcode: UMAXv2i32 +/* 54162 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54184 +/* 54167 */ MCD_OPC_CheckPredicate, 3, 8, 128, 0, // Skip to: 86948 +/* 54172 */ MCD_OPC_CheckField, 16, 6, 32, 1, 128, 0, // Skip to: 86948 +/* 54179 */ MCD_OPC_Decode, 137, 31, 248, 1, // Opcode: UADALPv2i32_v1i64 +/* 54184 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54206 +/* 54189 */ MCD_OPC_CheckPredicate, 3, 242, 127, 0, // Skip to: 86948 +/* 54194 */ MCD_OPC_CheckField, 21, 1, 1, 235, 127, 0, // Skip to: 86948 +/* 54201 */ MCD_OPC_Decode, 158, 32, 238, 1, // Opcode: UMINv2i32 +/* 54206 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 54228 +/* 54211 */ MCD_OPC_CheckPredicate, 3, 220, 127, 0, // Skip to: 86948 +/* 54216 */ MCD_OPC_CheckField, 21, 1, 1, 213, 127, 0, // Skip to: 86948 +/* 54223 */ MCD_OPC_Decode, 249, 30, 234, 1, // Opcode: UABDLv2i32_v2i64 +/* 54228 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54250 +/* 54233 */ MCD_OPC_CheckPredicate, 3, 198, 127, 0, // Skip to: 86948 +/* 54238 */ MCD_OPC_CheckField, 21, 1, 1, 191, 127, 0, // Skip to: 86948 +/* 54245 */ MCD_OPC_Decode, 131, 31, 238, 1, // Opcode: UABDv2i32 +/* 54250 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 54272 +/* 54255 */ MCD_OPC_CheckPredicate, 3, 176, 127, 0, // Skip to: 86948 +/* 54260 */ MCD_OPC_CheckField, 16, 6, 32, 169, 127, 0, // Skip to: 86948 +/* 54267 */ MCD_OPC_Decode, 152, 25, 239, 1, // Opcode: SQNEGv2i32 +/* 54272 */ MCD_OPC_FilterValue, 7, 159, 127, 0, // Skip to: 86948 +/* 54277 */ MCD_OPC_CheckPredicate, 3, 154, 127, 0, // Skip to: 86948 +/* 54282 */ MCD_OPC_CheckField, 21, 1, 1, 147, 127, 0, // Skip to: 86948 +/* 54289 */ MCD_OPC_Decode, 243, 30, 130, 2, // Opcode: UABAv2i32 +/* 54294 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 54498 +/* 54299 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 54302 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54324 +/* 54307 */ MCD_OPC_CheckPredicate, 3, 124, 127, 0, // Skip to: 86948 +/* 54312 */ MCD_OPC_CheckField, 21, 1, 1, 117, 127, 0, // Skip to: 86948 +/* 54319 */ MCD_OPC_Decode, 165, 32, 254, 1, // Opcode: UMLALv2i32_v2i64 +/* 54324 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 54362 +/* 54329 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 54332 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54347 +/* 54337 */ MCD_OPC_CheckPredicate, 7, 94, 127, 0, // Skip to: 86948 +/* 54342 */ MCD_OPC_Decode, 162, 25, 130, 2, // Opcode: SQRDMLAHv2i32 +/* 54347 */ MCD_OPC_FilterValue, 1, 84, 127, 0, // Skip to: 86948 +/* 54352 */ MCD_OPC_CheckPredicate, 3, 79, 127, 0, // Skip to: 86948 +/* 54357 */ MCD_OPC_Decode, 129, 30, 238, 1, // Opcode: SUBv2i32 +/* 54362 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54384 +/* 54367 */ MCD_OPC_CheckPredicate, 3, 64, 127, 0, // Skip to: 86948 +/* 54372 */ MCD_OPC_CheckField, 16, 6, 32, 57, 127, 0, // Skip to: 86948 +/* 54379 */ MCD_OPC_Decode, 203, 3, 239, 1, // Opcode: CMGEv2i32rz +/* 54384 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 54422 +/* 54389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 54392 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54407 +/* 54397 */ MCD_OPC_CheckPredicate, 7, 34, 127, 0, // Skip to: 86948 +/* 54402 */ MCD_OPC_Decode, 174, 25, 130, 2, // Opcode: SQRDMLSHv2i32 +/* 54407 */ MCD_OPC_FilterValue, 1, 24, 127, 0, // Skip to: 86948 +/* 54412 */ MCD_OPC_CheckPredicate, 3, 19, 127, 0, // Skip to: 86948 +/* 54417 */ MCD_OPC_Decode, 186, 3, 238, 1, // Opcode: CMEQv2i32 +/* 54422 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 54460 +/* 54427 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 54430 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54445 +/* 54435 */ MCD_OPC_CheckPredicate, 10, 252, 126, 0, // Skip to: 86948 +/* 54440 */ MCD_OPC_Decode, 219, 31, 130, 2, // Opcode: UDOTv8i8 +/* 54445 */ MCD_OPC_FilterValue, 1, 242, 126, 0, // Skip to: 86948 +/* 54450 */ MCD_OPC_CheckPredicate, 3, 237, 126, 0, // Skip to: 86948 +/* 54455 */ MCD_OPC_Decode, 224, 19, 130, 2, // Opcode: MLSv2i32 +/* 54460 */ MCD_OPC_FilterValue, 6, 227, 126, 0, // Skip to: 86948 +/* 54465 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 54468 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54483 +/* 54473 */ MCD_OPC_CheckPredicate, 3, 214, 126, 0, // Skip to: 86948 +/* 54478 */ MCD_OPC_Decode, 248, 3, 239, 1, // Opcode: CMLEv2i32rz +/* 54483 */ MCD_OPC_FilterValue, 33, 204, 126, 0, // Skip to: 86948 +/* 54488 */ MCD_OPC_CheckPredicate, 3, 199, 126, 0, // Skip to: 86948 +/* 54493 */ MCD_OPC_Decode, 241, 11, 239, 1, // Opcode: FRINTIv2f32 +/* 54498 */ MCD_OPC_FilterValue, 5, 151, 0, 0, // Skip to: 54654 +/* 54503 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 54506 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54528 +/* 54511 */ MCD_OPC_CheckPredicate, 3, 176, 126, 0, // Skip to: 86948 +/* 54516 */ MCD_OPC_CheckField, 21, 1, 1, 169, 126, 0, // Skip to: 86948 +/* 54523 */ MCD_OPC_Decode, 175, 32, 254, 1, // Opcode: UMLSLv2i32_v2i64 +/* 54528 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 54550 +/* 54533 */ MCD_OPC_CheckPredicate, 3, 154, 126, 0, // Skip to: 86948 +/* 54538 */ MCD_OPC_CheckField, 21, 1, 1, 147, 126, 0, // Skip to: 86948 +/* 54545 */ MCD_OPC_Decode, 234, 31, 238, 1, // Opcode: UMAXPv2i32 +/* 54550 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 54572 +/* 54555 */ MCD_OPC_CheckPredicate, 3, 132, 126, 0, // Skip to: 86948 +/* 54560 */ MCD_OPC_CheckField, 16, 6, 33, 125, 126, 0, // Skip to: 86948 +/* 54567 */ MCD_OPC_Decode, 208, 8, 239, 1, // Opcode: FCVTPUv2f32 +/* 54572 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 54594 +/* 54577 */ MCD_OPC_CheckPredicate, 3, 110, 126, 0, // Skip to: 86948 +/* 54582 */ MCD_OPC_CheckField, 21, 1, 1, 103, 126, 0, // Skip to: 86948 +/* 54589 */ MCD_OPC_Decode, 135, 32, 238, 1, // Opcode: UMINPv2i32 +/* 54594 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 54616 +/* 54599 */ MCD_OPC_CheckPredicate, 3, 88, 126, 0, // Skip to: 86948 +/* 54604 */ MCD_OPC_CheckField, 21, 1, 1, 81, 126, 0, // Skip to: 86948 +/* 54611 */ MCD_OPC_Decode, 186, 25, 238, 1, // Opcode: SQRDMULHv2i32 +/* 54616 */ MCD_OPC_FilterValue, 6, 71, 126, 0, // Skip to: 86948 +/* 54621 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 54624 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54639 +/* 54629 */ MCD_OPC_CheckPredicate, 3, 58, 126, 0, // Skip to: 86948 +/* 54634 */ MCD_OPC_Decode, 181, 20, 239, 1, // Opcode: NEGv2i32 +/* 54639 */ MCD_OPC_FilterValue, 33, 48, 126, 0, // Skip to: 86948 +/* 54644 */ MCD_OPC_CheckPredicate, 3, 43, 126, 0, // Skip to: 86948 +/* 54649 */ MCD_OPC_Decode, 150, 9, 239, 1, // Opcode: FCVTZUv2f32 +/* 54654 */ MCD_OPC_FilterValue, 6, 170, 0, 0, // Skip to: 54829 +/* 54659 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 54662 */ MCD_OPC_FilterValue, 0, 101, 0, 0, // Skip to: 54768 +/* 54667 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 54670 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 54692 +/* 54675 */ MCD_OPC_CheckPredicate, 3, 12, 126, 0, // Skip to: 86948 +/* 54680 */ MCD_OPC_CheckField, 21, 1, 1, 5, 126, 0, // Skip to: 86948 +/* 54687 */ MCD_OPC_Decode, 195, 32, 234, 1, // Opcode: UMULLv2i32_v2i64 +/* 54692 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 54730 +/* 54697 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 54700 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54715 +/* 54705 */ MCD_OPC_CheckPredicate, 3, 238, 125, 0, // Skip to: 86948 +/* 54710 */ MCD_OPC_Decode, 253, 6, 239, 1, // Opcode: FCMGEv2i32rz +/* 54715 */ MCD_OPC_FilterValue, 33, 228, 125, 0, // Skip to: 86948 +/* 54720 */ MCD_OPC_CheckPredicate, 3, 223, 125, 0, // Skip to: 86948 +/* 54725 */ MCD_OPC_Decode, 241, 33, 239, 1, // Opcode: URSQRTEv2i32 +/* 54730 */ MCD_OPC_FilterValue, 3, 213, 125, 0, // Skip to: 86948 +/* 54735 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 54738 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 54753 +/* 54743 */ MCD_OPC_CheckPredicate, 3, 200, 125, 0, // Skip to: 86948 +/* 54748 */ MCD_OPC_Decode, 174, 7, 239, 1, // Opcode: FCMLEv2i32rz +/* 54753 */ MCD_OPC_FilterValue, 33, 190, 125, 0, // Skip to: 86948 +/* 54758 */ MCD_OPC_CheckPredicate, 3, 185, 125, 0, // Skip to: 86948 +/* 54763 */ MCD_OPC_Decode, 179, 12, 239, 1, // Opcode: FRSQRTEv2f32 +/* 54768 */ MCD_OPC_FilterValue, 1, 175, 125, 0, // Skip to: 86948 +/* 54773 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 54776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54791 +/* 54781 */ MCD_OPC_CheckPredicate, 11, 162, 125, 0, // Skip to: 86948 +/* 54786 */ MCD_OPC_Decode, 160, 7, 167, 2, // Opcode: FCMLAv2f32 +/* 54791 */ MCD_OPC_FilterValue, 1, 152, 125, 0, // Skip to: 86948 +/* 54796 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 54799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54814 +/* 54804 */ MCD_OPC_CheckPredicate, 3, 139, 125, 0, // Skip to: 86948 +/* 54809 */ MCD_OPC_Decode, 253, 9, 238, 1, // Opcode: FMINNMPv2f32 +/* 54814 */ MCD_OPC_FilterValue, 2, 129, 125, 0, // Skip to: 86948 +/* 54819 */ MCD_OPC_CheckPredicate, 3, 124, 125, 0, // Skip to: 86948 +/* 54824 */ MCD_OPC_Decode, 134, 6, 238, 1, // Opcode: FABDv2f32 +/* 54829 */ MCD_OPC_FilterValue, 7, 114, 125, 0, // Skip to: 86948 +/* 54834 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 54837 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 54898 +/* 54842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 54845 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54860 +/* 54850 */ MCD_OPC_CheckPredicate, 11, 93, 125, 0, // Skip to: 86948 +/* 54855 */ MCD_OPC_Decode, 206, 6, 168, 2, // Opcode: FCADDv2f32 +/* 54860 */ MCD_OPC_FilterValue, 1, 83, 125, 0, // Skip to: 86948 +/* 54865 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 54868 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 54883 +/* 54873 */ MCD_OPC_CheckPredicate, 3, 70, 125, 0, // Skip to: 86948 +/* 54878 */ MCD_OPC_Decode, 145, 7, 238, 1, // Opcode: FCMGTv2f32 +/* 54883 */ MCD_OPC_FilterValue, 1, 60, 125, 0, // Skip to: 86948 +/* 54888 */ MCD_OPC_CheckPredicate, 3, 55, 125, 0, // Skip to: 86948 +/* 54893 */ MCD_OPC_Decode, 151, 10, 238, 1, // Opcode: FMINPv2f32 +/* 54898 */ MCD_OPC_FilterValue, 2, 47, 0, 0, // Skip to: 54950 +/* 54903 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 54906 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 54928 +/* 54911 */ MCD_OPC_CheckPredicate, 3, 32, 125, 0, // Skip to: 86948 +/* 54916 */ MCD_OPC_CheckField, 12, 1, 1, 25, 125, 0, // Skip to: 86948 +/* 54923 */ MCD_OPC_Decode, 170, 11, 239, 1, // Opcode: FNEGv2f32 +/* 54928 */ MCD_OPC_FilterValue, 33, 15, 125, 0, // Skip to: 86948 +/* 54933 */ MCD_OPC_CheckPredicate, 3, 10, 125, 0, // Skip to: 86948 +/* 54938 */ MCD_OPC_CheckField, 12, 1, 1, 3, 125, 0, // Skip to: 86948 +/* 54945 */ MCD_OPC_Decode, 204, 12, 239, 1, // Opcode: FSQRTv2f32 +/* 54950 */ MCD_OPC_FilterValue, 3, 249, 124, 0, // Skip to: 86948 +/* 54955 */ MCD_OPC_CheckPredicate, 3, 244, 124, 0, // Skip to: 86948 +/* 54960 */ MCD_OPC_CheckField, 21, 1, 1, 237, 124, 0, // Skip to: 86948 +/* 54967 */ MCD_OPC_CheckField, 12, 1, 0, 230, 124, 0, // Skip to: 86948 +/* 54974 */ MCD_OPC_Decode, 167, 6, 238, 1, // Opcode: FACGTv2f32 +/* 54979 */ MCD_OPC_FilterValue, 2, 93, 6, 0, // Skip to: 56613 +/* 54984 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 54987 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 55009 +/* 54992 */ MCD_OPC_CheckPredicate, 3, 207, 124, 0, // Skip to: 86948 +/* 54997 */ MCD_OPC_CheckField, 21, 1, 1, 200, 124, 0, // Skip to: 86948 +/* 55004 */ MCD_OPC_Decode, 166, 22, 133, 2, // Opcode: SADDLv4i32_v2i64 +/* 55009 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 55031 +/* 55014 */ MCD_OPC_CheckPredicate, 3, 185, 124, 0, // Skip to: 86948 +/* 55019 */ MCD_OPC_CheckField, 21, 1, 1, 178, 124, 0, // Skip to: 86948 +/* 55026 */ MCD_OPC_Decode, 130, 23, 133, 2, // Opcode: SHADDv4i32 +/* 55031 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 55053 +/* 55036 */ MCD_OPC_CheckPredicate, 3, 163, 124, 0, // Skip to: 86948 +/* 55041 */ MCD_OPC_CheckField, 16, 6, 32, 156, 124, 0, // Skip to: 86948 +/* 55048 */ MCD_OPC_Decode, 212, 21, 138, 2, // Opcode: REV64v4i32 +/* 55053 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 55075 +/* 55058 */ MCD_OPC_CheckPredicate, 3, 141, 124, 0, // Skip to: 86948 +/* 55063 */ MCD_OPC_CheckField, 21, 1, 1, 134, 124, 0, // Skip to: 86948 +/* 55070 */ MCD_OPC_Decode, 180, 24, 133, 2, // Opcode: SQADDv4i32 +/* 55075 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 55097 +/* 55080 */ MCD_OPC_CheckPredicate, 3, 119, 124, 0, // Skip to: 86948 +/* 55085 */ MCD_OPC_CheckField, 21, 1, 1, 112, 124, 0, // Skip to: 86948 +/* 55092 */ MCD_OPC_Decode, 175, 22, 133, 2, // Opcode: SADDWv4i32_v2i64 +/* 55097 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 55119 +/* 55102 */ MCD_OPC_CheckPredicate, 3, 97, 124, 0, // Skip to: 86948 +/* 55107 */ MCD_OPC_CheckField, 21, 1, 1, 90, 124, 0, // Skip to: 86948 +/* 55114 */ MCD_OPC_Decode, 186, 26, 133, 2, // Opcode: SRHADDv4i32 +/* 55119 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 55141 +/* 55124 */ MCD_OPC_CheckPredicate, 3, 75, 124, 0, // Skip to: 86948 +/* 55129 */ MCD_OPC_CheckField, 21, 1, 0, 68, 124, 0, // Skip to: 86948 +/* 55136 */ MCD_OPC_Decode, 200, 34, 133, 2, // Opcode: UZP1v4i32 +/* 55141 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 55163 +/* 55146 */ MCD_OPC_CheckPredicate, 3, 53, 124, 0, // Skip to: 86948 +/* 55151 */ MCD_OPC_CheckField, 21, 1, 1, 46, 124, 0, // Skip to: 86948 +/* 55158 */ MCD_OPC_Decode, 217, 20, 133, 2, // Opcode: ORRv16i8 +/* 55163 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 55185 +/* 55168 */ MCD_OPC_CheckPredicate, 3, 31, 124, 0, // Skip to: 86948 +/* 55173 */ MCD_OPC_CheckField, 21, 1, 1, 24, 124, 0, // Skip to: 86948 +/* 55180 */ MCD_OPC_Decode, 164, 27, 133, 2, // Opcode: SSUBLv4i32_v2i64 +/* 55185 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 55207 +/* 55190 */ MCD_OPC_CheckPredicate, 3, 9, 124, 0, // Skip to: 86948 +/* 55195 */ MCD_OPC_CheckField, 21, 1, 1, 2, 124, 0, // Skip to: 86948 +/* 55202 */ MCD_OPC_Decode, 156, 23, 133, 2, // Opcode: SHSUBv4i32 +/* 55207 */ MCD_OPC_FilterValue, 10, 56, 0, 0, // Skip to: 55268 +/* 55212 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 55215 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55230 +/* 55220 */ MCD_OPC_CheckPredicate, 3, 235, 123, 0, // Skip to: 86948 +/* 55225 */ MCD_OPC_Decode, 217, 30, 133, 2, // Opcode: TRN1v4i32 +/* 55230 */ MCD_OPC_FilterValue, 1, 225, 123, 0, // Skip to: 86948 +/* 55235 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 55238 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55253 +/* 55243 */ MCD_OPC_CheckPredicate, 3, 212, 123, 0, // Skip to: 86948 +/* 55248 */ MCD_OPC_Decode, 155, 22, 138, 2, // Opcode: SADDLPv4i32_v2i64 +/* 55253 */ MCD_OPC_FilterValue, 1, 202, 123, 0, // Skip to: 86948 +/* 55258 */ MCD_OPC_CheckPredicate, 3, 197, 123, 0, // Skip to: 86948 +/* 55263 */ MCD_OPC_Decode, 130, 35, 147, 2, // Opcode: XTNv4i32 +/* 55268 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 55290 +/* 55273 */ MCD_OPC_CheckPredicate, 3, 182, 123, 0, // Skip to: 86948 +/* 55278 */ MCD_OPC_CheckField, 21, 1, 1, 175, 123, 0, // Skip to: 86948 +/* 55285 */ MCD_OPC_Decode, 162, 26, 133, 2, // Opcode: SQSUBv4i32 +/* 55290 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 55312 +/* 55295 */ MCD_OPC_CheckPredicate, 3, 160, 123, 0, // Skip to: 86948 +/* 55300 */ MCD_OPC_CheckField, 21, 1, 1, 153, 123, 0, // Skip to: 86948 +/* 55307 */ MCD_OPC_Decode, 170, 27, 133, 2, // Opcode: SSUBWv4i32_v2i64 +/* 55312 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 55334 +/* 55317 */ MCD_OPC_CheckPredicate, 3, 138, 123, 0, // Skip to: 86948 +/* 55322 */ MCD_OPC_CheckField, 21, 1, 1, 131, 123, 0, // Skip to: 86948 +/* 55329 */ MCD_OPC_Decode, 224, 3, 133, 2, // Opcode: CMGTv4i32 +/* 55334 */ MCD_OPC_FilterValue, 14, 56, 0, 0, // Skip to: 55395 +/* 55339 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 55342 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55357 +/* 55347 */ MCD_OPC_CheckPredicate, 3, 108, 123, 0, // Skip to: 86948 +/* 55352 */ MCD_OPC_Decode, 145, 35, 133, 2, // Opcode: ZIP1v4i32 +/* 55357 */ MCD_OPC_FilterValue, 1, 98, 123, 0, // Skip to: 86948 +/* 55362 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 55365 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55380 +/* 55370 */ MCD_OPC_CheckPredicate, 3, 85, 123, 0, // Skip to: 86948 +/* 55375 */ MCD_OPC_Decode, 149, 30, 147, 2, // Opcode: SUQADDv4i32 +/* 55380 */ MCD_OPC_FilterValue, 16, 75, 123, 0, // Skip to: 86948 +/* 55385 */ MCD_OPC_CheckPredicate, 3, 70, 123, 0, // Skip to: 86948 +/* 55390 */ MCD_OPC_Decode, 160, 22, 244, 1, // Opcode: SADDLVv4i32v +/* 55395 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 55417 +/* 55400 */ MCD_OPC_CheckPredicate, 3, 55, 123, 0, // Skip to: 86948 +/* 55405 */ MCD_OPC_CheckField, 21, 1, 1, 48, 123, 0, // Skip to: 86948 +/* 55412 */ MCD_OPC_Decode, 208, 3, 133, 2, // Opcode: CMGEv4i32 +/* 55417 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 55439 +/* 55422 */ MCD_OPC_CheckPredicate, 3, 33, 123, 0, // Skip to: 86948 +/* 55427 */ MCD_OPC_CheckField, 21, 1, 1, 26, 123, 0, // Skip to: 86948 +/* 55434 */ MCD_OPC_Decode, 143, 1, 141, 2, // Opcode: ADDHNv2i64_v4i32 +/* 55439 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 55461 +/* 55444 */ MCD_OPC_CheckPredicate, 3, 11, 123, 0, // Skip to: 86948 +/* 55449 */ MCD_OPC_CheckField, 21, 1, 1, 4, 123, 0, // Skip to: 86948 +/* 55456 */ MCD_OPC_Decode, 232, 26, 133, 2, // Opcode: SSHLv4i32 +/* 55461 */ MCD_OPC_FilterValue, 18, 33, 0, 0, // Skip to: 55499 +/* 55466 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 55469 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 55484 +/* 55474 */ MCD_OPC_CheckPredicate, 3, 237, 122, 0, // Skip to: 86948 +/* 55479 */ MCD_OPC_Decode, 167, 3, 138, 2, // Opcode: CLSv4i32 +/* 55484 */ MCD_OPC_FilterValue, 33, 227, 122, 0, // Skip to: 86948 +/* 55489 */ MCD_OPC_CheckPredicate, 3, 222, 122, 0, // Skip to: 86948 +/* 55494 */ MCD_OPC_Decode, 171, 26, 147, 2, // Opcode: SQXTNv4i32 +/* 55499 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 55521 +/* 55504 */ MCD_OPC_CheckPredicate, 3, 207, 122, 0, // Skip to: 86948 +/* 55509 */ MCD_OPC_CheckField, 21, 1, 1, 200, 122, 0, // Skip to: 86948 +/* 55516 */ MCD_OPC_Decode, 250, 25, 133, 2, // Opcode: SQSHLv4i32 +/* 55521 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 55543 +/* 55526 */ MCD_OPC_CheckPredicate, 3, 185, 122, 0, // Skip to: 86948 +/* 55531 */ MCD_OPC_CheckField, 21, 1, 1, 178, 122, 0, // Skip to: 86948 +/* 55538 */ MCD_OPC_Decode, 249, 21, 141, 2, // Opcode: SABALv4i32_v2i64 +/* 55543 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 55565 +/* 55548 */ MCD_OPC_CheckPredicate, 3, 163, 122, 0, // Skip to: 86948 +/* 55553 */ MCD_OPC_CheckField, 21, 1, 1, 156, 122, 0, // Skip to: 86948 +/* 55560 */ MCD_OPC_Decode, 202, 26, 133, 2, // Opcode: SRSHLv4i32 +/* 55565 */ MCD_OPC_FilterValue, 22, 17, 0, 0, // Skip to: 55587 +/* 55570 */ MCD_OPC_CheckPredicate, 3, 141, 122, 0, // Skip to: 86948 +/* 55575 */ MCD_OPC_CheckField, 21, 1, 0, 134, 122, 0, // Skip to: 86948 +/* 55582 */ MCD_OPC_Decode, 215, 34, 133, 2, // Opcode: UZP2v4i32 +/* 55587 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 55609 +/* 55592 */ MCD_OPC_CheckPredicate, 3, 119, 122, 0, // Skip to: 86948 +/* 55597 */ MCD_OPC_CheckField, 21, 1, 1, 112, 122, 0, // Skip to: 86948 +/* 55604 */ MCD_OPC_Decode, 202, 25, 133, 2, // Opcode: SQRSHLv4i32 +/* 55609 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 55631 +/* 55614 */ MCD_OPC_CheckPredicate, 3, 97, 122, 0, // Skip to: 86948 +/* 55619 */ MCD_OPC_CheckField, 21, 1, 1, 90, 122, 0, // Skip to: 86948 +/* 55626 */ MCD_OPC_Decode, 212, 29, 141, 2, // Opcode: SUBHNv2i64_v4i32 +/* 55631 */ MCD_OPC_FilterValue, 25, 17, 0, 0, // Skip to: 55653 +/* 55636 */ MCD_OPC_CheckPredicate, 3, 75, 122, 0, // Skip to: 86948 +/* 55641 */ MCD_OPC_CheckField, 21, 1, 1, 68, 122, 0, // Skip to: 86948 +/* 55648 */ MCD_OPC_Decode, 203, 23, 133, 2, // Opcode: SMAXv4i32 +/* 55653 */ MCD_OPC_FilterValue, 26, 40, 0, 0, // Skip to: 55698 +/* 55658 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 55661 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55676 +/* 55666 */ MCD_OPC_CheckPredicate, 3, 45, 122, 0, // Skip to: 86948 +/* 55671 */ MCD_OPC_Decode, 232, 30, 133, 2, // Opcode: TRN2v4i32 +/* 55676 */ MCD_OPC_FilterValue, 1, 35, 122, 0, // Skip to: 86948 +/* 55681 */ MCD_OPC_CheckPredicate, 3, 30, 122, 0, // Skip to: 86948 +/* 55686 */ MCD_OPC_CheckField, 16, 5, 0, 23, 122, 0, // Skip to: 86948 +/* 55693 */ MCD_OPC_Decode, 149, 22, 147, 2, // Opcode: SADALPv4i32_v2i64 +/* 55698 */ MCD_OPC_FilterValue, 27, 17, 0, 0, // Skip to: 55720 +/* 55703 */ MCD_OPC_CheckPredicate, 3, 8, 122, 0, // Skip to: 86948 +/* 55708 */ MCD_OPC_CheckField, 21, 1, 1, 1, 122, 0, // Skip to: 86948 +/* 55715 */ MCD_OPC_Decode, 233, 23, 133, 2, // Opcode: SMINv4i32 +/* 55720 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 55742 +/* 55725 */ MCD_OPC_CheckPredicate, 3, 242, 121, 0, // Skip to: 86948 +/* 55730 */ MCD_OPC_CheckField, 21, 1, 1, 235, 121, 0, // Skip to: 86948 +/* 55737 */ MCD_OPC_Decode, 133, 22, 133, 2, // Opcode: SABDLv4i32_v2i64 +/* 55742 */ MCD_OPC_FilterValue, 29, 17, 0, 0, // Skip to: 55764 +/* 55747 */ MCD_OPC_CheckPredicate, 3, 220, 121, 0, // Skip to: 86948 +/* 55752 */ MCD_OPC_CheckField, 21, 1, 1, 213, 121, 0, // Skip to: 86948 +/* 55759 */ MCD_OPC_Decode, 143, 22, 133, 2, // Opcode: SABDv4i32 +/* 55764 */ MCD_OPC_FilterValue, 30, 40, 0, 0, // Skip to: 55809 +/* 55769 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 55772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55787 +/* 55777 */ MCD_OPC_CheckPredicate, 3, 190, 121, 0, // Skip to: 86948 +/* 55782 */ MCD_OPC_Decode, 160, 35, 133, 2, // Opcode: ZIP2v4i32 +/* 55787 */ MCD_OPC_FilterValue, 1, 180, 121, 0, // Skip to: 86948 +/* 55792 */ MCD_OPC_CheckPredicate, 3, 175, 121, 0, // Skip to: 86948 +/* 55797 */ MCD_OPC_CheckField, 16, 5, 0, 168, 121, 0, // Skip to: 86948 +/* 55804 */ MCD_OPC_Decode, 161, 24, 138, 2, // Opcode: SQABSv4i32 +/* 55809 */ MCD_OPC_FilterValue, 31, 17, 0, 0, // Skip to: 55831 +/* 55814 */ MCD_OPC_CheckPredicate, 3, 153, 121, 0, // Skip to: 86948 +/* 55819 */ MCD_OPC_CheckField, 21, 1, 1, 146, 121, 0, // Skip to: 86948 +/* 55826 */ MCD_OPC_Decode, 255, 21, 141, 2, // Opcode: SABAv4i32 +/* 55831 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 55853 +/* 55836 */ MCD_OPC_CheckPredicate, 3, 131, 121, 0, // Skip to: 86948 +/* 55841 */ MCD_OPC_CheckField, 21, 1, 1, 124, 121, 0, // Skip to: 86948 +/* 55848 */ MCD_OPC_Decode, 242, 23, 141, 2, // Opcode: SMLALv4i32_v2i64 +/* 55853 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 55875 +/* 55858 */ MCD_OPC_CheckPredicate, 3, 109, 121, 0, // Skip to: 86948 +/* 55863 */ MCD_OPC_CheckField, 21, 1, 1, 102, 121, 0, // Skip to: 86948 +/* 55870 */ MCD_OPC_Decode, 199, 1, 133, 2, // Opcode: ADDv4i32 +/* 55875 */ MCD_OPC_FilterValue, 34, 33, 0, 0, // Skip to: 55913 +/* 55880 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 55883 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 55898 +/* 55888 */ MCD_OPC_CheckPredicate, 3, 79, 121, 0, // Skip to: 86948 +/* 55893 */ MCD_OPC_Decode, 225, 3, 138, 2, // Opcode: CMGTv4i32rz +/* 55898 */ MCD_OPC_FilterValue, 33, 69, 121, 0, // Skip to: 86948 +/* 55903 */ MCD_OPC_CheckPredicate, 3, 64, 121, 0, // Skip to: 86948 +/* 55908 */ MCD_OPC_Decode, 149, 12, 138, 2, // Opcode: FRINTPv4f32 +/* 55913 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 55935 +/* 55918 */ MCD_OPC_CheckPredicate, 3, 49, 121, 0, // Skip to: 86948 +/* 55923 */ MCD_OPC_CheckField, 21, 1, 1, 42, 121, 0, // Skip to: 86948 +/* 55930 */ MCD_OPC_Decode, 238, 4, 133, 2, // Opcode: CMTSTv4i32 +/* 55935 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 55957 +/* 55940 */ MCD_OPC_CheckPredicate, 3, 27, 121, 0, // Skip to: 86948 +/* 55945 */ MCD_OPC_CheckField, 21, 1, 1, 20, 121, 0, // Skip to: 86948 +/* 55952 */ MCD_OPC_Decode, 214, 24, 141, 2, // Opcode: SQDMLALv4i32_v2i64 +/* 55957 */ MCD_OPC_FilterValue, 37, 33, 0, 0, // Skip to: 55995 +/* 55962 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 55965 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 55980 +/* 55970 */ MCD_OPC_CheckPredicate, 10, 253, 120, 0, // Skip to: 86948 +/* 55975 */ MCD_OPC_Decode, 231, 22, 141, 2, // Opcode: SDOTv16i8 +/* 55980 */ MCD_OPC_FilterValue, 1, 243, 120, 0, // Skip to: 86948 +/* 55985 */ MCD_OPC_CheckPredicate, 3, 238, 120, 0, // Skip to: 86948 +/* 55990 */ MCD_OPC_Decode, 214, 19, 141, 2, // Opcode: MLAv4i32 +/* 55995 */ MCD_OPC_FilterValue, 38, 33, 0, 0, // Skip to: 56033 +/* 56000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56018 +/* 56008 */ MCD_OPC_CheckPredicate, 3, 215, 120, 0, // Skip to: 86948 +/* 56013 */ MCD_OPC_Decode, 193, 3, 138, 2, // Opcode: CMEQv4i32rz +/* 56018 */ MCD_OPC_FilterValue, 33, 205, 120, 0, // Skip to: 86948 +/* 56023 */ MCD_OPC_CheckPredicate, 3, 200, 120, 0, // Skip to: 86948 +/* 56028 */ MCD_OPC_Decode, 171, 12, 138, 2, // Opcode: FRINTZv4f32 +/* 56033 */ MCD_OPC_FilterValue, 39, 17, 0, 0, // Skip to: 56055 +/* 56038 */ MCD_OPC_CheckPredicate, 3, 185, 120, 0, // Skip to: 86948 +/* 56043 */ MCD_OPC_CheckField, 21, 1, 1, 178, 120, 0, // Skip to: 86948 +/* 56050 */ MCD_OPC_Decode, 162, 20, 133, 2, // Opcode: MULv4i32 +/* 56055 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 56077 +/* 56060 */ MCD_OPC_CheckPredicate, 3, 163, 120, 0, // Skip to: 86948 +/* 56065 */ MCD_OPC_CheckField, 21, 1, 1, 156, 120, 0, // Skip to: 86948 +/* 56072 */ MCD_OPC_Decode, 252, 23, 141, 2, // Opcode: SMLSLv4i32_v2i64 +/* 56077 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 56099 +/* 56082 */ MCD_OPC_CheckPredicate, 3, 141, 120, 0, // Skip to: 86948 +/* 56087 */ MCD_OPC_CheckField, 21, 1, 1, 134, 120, 0, // Skip to: 86948 +/* 56094 */ MCD_OPC_Decode, 180, 23, 133, 2, // Opcode: SMAXPv4i32 +/* 56099 */ MCD_OPC_FilterValue, 42, 63, 0, 0, // Skip to: 56167 +/* 56104 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56107 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56122 +/* 56112 */ MCD_OPC_CheckPredicate, 3, 111, 120, 0, // Skip to: 86948 +/* 56117 */ MCD_OPC_Decode, 131, 4, 138, 2, // Opcode: CMLTv4i32rz +/* 56122 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56137 +/* 56127 */ MCD_OPC_CheckPredicate, 3, 96, 120, 0, // Skip to: 86948 +/* 56132 */ MCD_OPC_Decode, 197, 8, 138, 2, // Opcode: FCVTPSv4f32 +/* 56137 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 56152 +/* 56142 */ MCD_OPC_CheckPredicate, 3, 81, 120, 0, // Skip to: 86948 +/* 56147 */ MCD_OPC_Decode, 189, 23, 160, 2, // Opcode: SMAXVv4i32v +/* 56152 */ MCD_OPC_FilterValue, 49, 71, 120, 0, // Skip to: 86948 +/* 56157 */ MCD_OPC_CheckPredicate, 3, 66, 120, 0, // Skip to: 86948 +/* 56162 */ MCD_OPC_Decode, 219, 23, 160, 2, // Opcode: SMINVv4i32v +/* 56167 */ MCD_OPC_FilterValue, 43, 17, 0, 0, // Skip to: 56189 +/* 56172 */ MCD_OPC_CheckPredicate, 3, 51, 120, 0, // Skip to: 86948 +/* 56177 */ MCD_OPC_CheckField, 21, 1, 1, 44, 120, 0, // Skip to: 86948 +/* 56184 */ MCD_OPC_Decode, 210, 23, 133, 2, // Opcode: SMINPv4i32 +/* 56189 */ MCD_OPC_FilterValue, 44, 17, 0, 0, // Skip to: 56211 +/* 56194 */ MCD_OPC_CheckPredicate, 3, 29, 120, 0, // Skip to: 86948 +/* 56199 */ MCD_OPC_CheckField, 21, 1, 1, 22, 120, 0, // Skip to: 86948 +/* 56206 */ MCD_OPC_Decode, 226, 24, 141, 2, // Opcode: SQDMLSLv4i32_v2i64 +/* 56211 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 56233 +/* 56216 */ MCD_OPC_CheckPredicate, 3, 7, 120, 0, // Skip to: 86948 +/* 56221 */ MCD_OPC_CheckField, 21, 1, 1, 0, 120, 0, // Skip to: 86948 +/* 56228 */ MCD_OPC_Decode, 237, 24, 133, 2, // Opcode: SQDMULHv4i32 +/* 56233 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 56286 +/* 56238 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56241 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56256 +/* 56246 */ MCD_OPC_CheckPredicate, 3, 233, 119, 0, // Skip to: 86948 +/* 56251 */ MCD_OPC_Decode, 135, 1, 138, 2, // Opcode: ABSv4i32 +/* 56256 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56271 +/* 56261 */ MCD_OPC_CheckPredicate, 3, 218, 119, 0, // Skip to: 86948 +/* 56266 */ MCD_OPC_Decode, 248, 8, 138, 2, // Opcode: FCVTZSv4f32 +/* 56271 */ MCD_OPC_FilterValue, 49, 208, 119, 0, // Skip to: 86948 +/* 56276 */ MCD_OPC_CheckPredicate, 3, 203, 119, 0, // Skip to: 86948 +/* 56281 */ MCD_OPC_Decode, 169, 1, 160, 2, // Opcode: ADDVv4i32v +/* 56286 */ MCD_OPC_FilterValue, 47, 17, 0, 0, // Skip to: 56308 +/* 56291 */ MCD_OPC_CheckPredicate, 3, 188, 119, 0, // Skip to: 86948 +/* 56296 */ MCD_OPC_CheckField, 21, 1, 1, 181, 119, 0, // Skip to: 86948 +/* 56303 */ MCD_OPC_Decode, 154, 1, 133, 2, // Opcode: ADDPv4i32 +/* 56308 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 56330 +/* 56313 */ MCD_OPC_CheckPredicate, 3, 166, 119, 0, // Skip to: 86948 +/* 56318 */ MCD_OPC_CheckField, 21, 1, 1, 159, 119, 0, // Skip to: 86948 +/* 56325 */ MCD_OPC_Decode, 145, 24, 133, 2, // Opcode: SMULLv4i32_v2i64 +/* 56330 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 56352 +/* 56335 */ MCD_OPC_CheckPredicate, 3, 144, 119, 0, // Skip to: 86948 +/* 56340 */ MCD_OPC_CheckField, 21, 1, 1, 137, 119, 0, // Skip to: 86948 +/* 56347 */ MCD_OPC_Decode, 149, 10, 133, 2, // Opcode: FMINNMv4f32 +/* 56352 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 56405 +/* 56357 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56360 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56375 +/* 56365 */ MCD_OPC_CheckPredicate, 3, 114, 119, 0, // Skip to: 86948 +/* 56370 */ MCD_OPC_Decode, 152, 7, 138, 2, // Opcode: FCMGTv4i32rz +/* 56375 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56390 +/* 56380 */ MCD_OPC_CheckPredicate, 3, 99, 119, 0, // Skip to: 86948 +/* 56385 */ MCD_OPC_Decode, 218, 33, 138, 2, // Opcode: URECPEv4i32 +/* 56390 */ MCD_OPC_FilterValue, 48, 89, 119, 0, // Skip to: 86948 +/* 56395 */ MCD_OPC_CheckPredicate, 4, 84, 119, 0, // Skip to: 86948 +/* 56400 */ MCD_OPC_Decode, 139, 10, 152, 2, // Opcode: FMINNMVv8i16v +/* 56405 */ MCD_OPC_FilterValue, 51, 17, 0, 0, // Skip to: 56427 +/* 56410 */ MCD_OPC_CheckPredicate, 3, 69, 119, 0, // Skip to: 86948 +/* 56415 */ MCD_OPC_CheckField, 21, 1, 1, 62, 119, 0, // Skip to: 86948 +/* 56422 */ MCD_OPC_Decode, 210, 10, 141, 2, // Opcode: FMLSv4f32 +/* 56427 */ MCD_OPC_FilterValue, 52, 17, 0, 0, // Skip to: 56449 +/* 56432 */ MCD_OPC_CheckPredicate, 3, 47, 119, 0, // Skip to: 86948 +/* 56437 */ MCD_OPC_CheckField, 21, 1, 1, 40, 119, 0, // Skip to: 86948 +/* 56444 */ MCD_OPC_Decode, 250, 24, 133, 2, // Opcode: SQDMULLv4i32_v2i64 +/* 56449 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 56471 +/* 56454 */ MCD_OPC_CheckPredicate, 3, 25, 119, 0, // Skip to: 86948 +/* 56459 */ MCD_OPC_CheckField, 21, 1, 1, 18, 119, 0, // Skip to: 86948 +/* 56466 */ MCD_OPC_Decode, 230, 12, 133, 2, // Opcode: FSUBv4f32 +/* 56471 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 56509 +/* 56476 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56479 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56494 +/* 56484 */ MCD_OPC_CheckPredicate, 3, 251, 118, 0, // Skip to: 86948 +/* 56489 */ MCD_OPC_Decode, 236, 6, 138, 2, // Opcode: FCMEQv4i32rz +/* 56494 */ MCD_OPC_FilterValue, 33, 241, 118, 0, // Skip to: 86948 +/* 56499 */ MCD_OPC_CheckPredicate, 3, 236, 118, 0, // Skip to: 86948 +/* 56504 */ MCD_OPC_Decode, 205, 11, 138, 2, // Opcode: FRECPEv4f32 +/* 56509 */ MCD_OPC_FilterValue, 58, 17, 0, 0, // Skip to: 56531 +/* 56514 */ MCD_OPC_CheckPredicate, 3, 221, 118, 0, // Skip to: 86948 +/* 56519 */ MCD_OPC_CheckField, 16, 6, 32, 214, 118, 0, // Skip to: 86948 +/* 56526 */ MCD_OPC_Decode, 188, 7, 138, 2, // Opcode: FCMLTv4i32rz +/* 56531 */ MCD_OPC_FilterValue, 61, 17, 0, 0, // Skip to: 56553 +/* 56536 */ MCD_OPC_CheckPredicate, 3, 199, 118, 0, // Skip to: 86948 +/* 56541 */ MCD_OPC_CheckField, 21, 1, 1, 192, 118, 0, // Skip to: 86948 +/* 56548 */ MCD_OPC_Decode, 175, 10, 133, 2, // Opcode: FMINv4f32 +/* 56553 */ MCD_OPC_FilterValue, 62, 33, 0, 0, // Skip to: 56591 +/* 56558 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56561 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56576 +/* 56566 */ MCD_OPC_CheckPredicate, 3, 169, 118, 0, // Skip to: 86948 +/* 56571 */ MCD_OPC_Decode, 148, 6, 138, 2, // Opcode: FABSv4f32 +/* 56576 */ MCD_OPC_FilterValue, 48, 159, 118, 0, // Skip to: 86948 +/* 56581 */ MCD_OPC_CheckPredicate, 4, 154, 118, 0, // Skip to: 86948 +/* 56586 */ MCD_OPC_Decode, 165, 10, 152, 2, // Opcode: FMINVv8i16v +/* 56591 */ MCD_OPC_FilterValue, 63, 144, 118, 0, // Skip to: 86948 +/* 56596 */ MCD_OPC_CheckPredicate, 3, 139, 118, 0, // Skip to: 86948 +/* 56601 */ MCD_OPC_CheckField, 21, 1, 1, 132, 118, 0, // Skip to: 86948 +/* 56608 */ MCD_OPC_Decode, 193, 12, 133, 2, // Opcode: FRSQRTSv4f32 +/* 56613 */ MCD_OPC_FilterValue, 3, 209, 5, 0, // Skip to: 58107 +/* 56618 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 56621 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 56761 +/* 56626 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 56629 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 56651 +/* 56634 */ MCD_OPC_CheckPredicate, 3, 101, 118, 0, // Skip to: 86948 +/* 56639 */ MCD_OPC_CheckField, 21, 1, 1, 94, 118, 0, // Skip to: 86948 +/* 56646 */ MCD_OPC_Decode, 156, 31, 133, 2, // Opcode: UADDLv4i32_v2i64 +/* 56651 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 56673 +/* 56656 */ MCD_OPC_CheckPredicate, 3, 79, 118, 0, // Skip to: 86948 +/* 56661 */ MCD_OPC_CheckField, 21, 1, 1, 72, 118, 0, // Skip to: 86948 +/* 56668 */ MCD_OPC_Decode, 223, 31, 133, 2, // Opcode: UHADDv4i32 +/* 56673 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 56695 +/* 56678 */ MCD_OPC_CheckPredicate, 3, 57, 118, 0, // Skip to: 86948 +/* 56683 */ MCD_OPC_CheckField, 21, 1, 1, 50, 118, 0, // Skip to: 86948 +/* 56690 */ MCD_OPC_Decode, 219, 32, 133, 2, // Opcode: UQADDv4i32 +/* 56695 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 56717 +/* 56700 */ MCD_OPC_CheckPredicate, 3, 35, 118, 0, // Skip to: 86948 +/* 56705 */ MCD_OPC_CheckField, 21, 1, 1, 28, 118, 0, // Skip to: 86948 +/* 56712 */ MCD_OPC_Decode, 166, 31, 133, 2, // Opcode: UADDWv4i32_v2i64 +/* 56717 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 56739 +/* 56722 */ MCD_OPC_CheckPredicate, 3, 13, 118, 0, // Skip to: 86948 +/* 56727 */ MCD_OPC_CheckField, 21, 1, 1, 6, 118, 0, // Skip to: 86948 +/* 56734 */ MCD_OPC_Decode, 222, 33, 133, 2, // Opcode: URHADDv4i32 +/* 56739 */ MCD_OPC_FilterValue, 7, 252, 117, 0, // Skip to: 86948 +/* 56744 */ MCD_OPC_CheckPredicate, 3, 247, 117, 0, // Skip to: 86948 +/* 56749 */ MCD_OPC_CheckField, 21, 1, 1, 240, 117, 0, // Skip to: 86948 +/* 56756 */ MCD_OPC_Decode, 195, 2, 141, 2, // Opcode: BITv16i8 +/* 56761 */ MCD_OPC_FilterValue, 1, 226, 0, 0, // Skip to: 56992 +/* 56766 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 56769 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 56791 +/* 56774 */ MCD_OPC_CheckPredicate, 3, 217, 117, 0, // Skip to: 86948 +/* 56779 */ MCD_OPC_CheckField, 21, 1, 1, 210, 117, 0, // Skip to: 86948 +/* 56786 */ MCD_OPC_Decode, 167, 34, 133, 2, // Opcode: USUBLv4i32_v2i64 +/* 56791 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 56813 +/* 56796 */ MCD_OPC_CheckPredicate, 3, 195, 117, 0, // Skip to: 86948 +/* 56801 */ MCD_OPC_CheckField, 21, 1, 1, 188, 117, 0, // Skip to: 86948 +/* 56808 */ MCD_OPC_Decode, 229, 31, 133, 2, // Opcode: UHSUBv4i32 +/* 56813 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 56851 +/* 56818 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56821 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56836 +/* 56826 */ MCD_OPC_CheckPredicate, 3, 165, 117, 0, // Skip to: 86948 +/* 56831 */ MCD_OPC_Decode, 145, 31, 138, 2, // Opcode: UADDLPv4i32_v2i64 +/* 56836 */ MCD_OPC_FilterValue, 33, 155, 117, 0, // Skip to: 86948 +/* 56841 */ MCD_OPC_CheckPredicate, 3, 150, 117, 0, // Skip to: 86948 +/* 56846 */ MCD_OPC_Decode, 180, 26, 147, 2, // Opcode: SQXTUNv4i32 +/* 56851 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 56873 +/* 56856 */ MCD_OPC_CheckPredicate, 3, 135, 117, 0, // Skip to: 86948 +/* 56861 */ MCD_OPC_CheckField, 21, 1, 1, 128, 117, 0, // Skip to: 86948 +/* 56868 */ MCD_OPC_Decode, 205, 33, 133, 2, // Opcode: UQSUBv4i32 +/* 56873 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 56895 +/* 56878 */ MCD_OPC_CheckPredicate, 3, 113, 117, 0, // Skip to: 86948 +/* 56883 */ MCD_OPC_CheckField, 21, 1, 1, 106, 117, 0, // Skip to: 86948 +/* 56890 */ MCD_OPC_Decode, 173, 34, 133, 2, // Opcode: USUBWv4i32_v2i64 +/* 56895 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 56917 +/* 56900 */ MCD_OPC_CheckPredicate, 3, 91, 117, 0, // Skip to: 86948 +/* 56905 */ MCD_OPC_CheckField, 21, 1, 1, 84, 117, 0, // Skip to: 86948 +/* 56912 */ MCD_OPC_Decode, 235, 3, 133, 2, // Opcode: CMHIv4i32 +/* 56917 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 56970 +/* 56922 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 56925 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 56940 +/* 56930 */ MCD_OPC_CheckPredicate, 3, 61, 117, 0, // Skip to: 86948 +/* 56935 */ MCD_OPC_Decode, 153, 34, 147, 2, // Opcode: USQADDv4i32 +/* 56940 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 56955 +/* 56945 */ MCD_OPC_CheckPredicate, 3, 46, 117, 0, // Skip to: 86948 +/* 56950 */ MCD_OPC_Decode, 136, 23, 138, 2, // Opcode: SHLLv4i32 +/* 56955 */ MCD_OPC_FilterValue, 48, 36, 117, 0, // Skip to: 86948 +/* 56960 */ MCD_OPC_CheckPredicate, 3, 31, 117, 0, // Skip to: 86948 +/* 56965 */ MCD_OPC_Decode, 150, 31, 244, 1, // Opcode: UADDLVv4i32v +/* 56970 */ MCD_OPC_FilterValue, 7, 21, 117, 0, // Skip to: 86948 +/* 56975 */ MCD_OPC_CheckPredicate, 3, 16, 117, 0, // Skip to: 86948 +/* 56980 */ MCD_OPC_CheckField, 21, 1, 1, 9, 117, 0, // Skip to: 86948 +/* 56987 */ MCD_OPC_Decode, 243, 3, 133, 2, // Opcode: CMHSv4i32 +/* 56992 */ MCD_OPC_FilterValue, 2, 173, 0, 0, // Skip to: 57170 +/* 56997 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 57000 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57022 +/* 57005 */ MCD_OPC_CheckPredicate, 3, 242, 116, 0, // Skip to: 86948 +/* 57010 */ MCD_OPC_CheckField, 21, 1, 1, 235, 116, 0, // Skip to: 86948 +/* 57017 */ MCD_OPC_Decode, 178, 21, 141, 2, // Opcode: RADDHNv2i64_v4i32 +/* 57022 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57044 +/* 57027 */ MCD_OPC_CheckPredicate, 3, 220, 116, 0, // Skip to: 86948 +/* 57032 */ MCD_OPC_CheckField, 21, 1, 1, 213, 116, 0, // Skip to: 86948 +/* 57039 */ MCD_OPC_Decode, 134, 34, 133, 2, // Opcode: USHLv4i32 +/* 57044 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 57082 +/* 57049 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 57052 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57067 +/* 57057 */ MCD_OPC_CheckPredicate, 3, 190, 116, 0, // Skip to: 86948 +/* 57062 */ MCD_OPC_Decode, 179, 3, 138, 2, // Opcode: CLZv4i32 +/* 57067 */ MCD_OPC_FilterValue, 33, 180, 116, 0, // Skip to: 86948 +/* 57072 */ MCD_OPC_CheckPredicate, 3, 175, 116, 0, // Skip to: 86948 +/* 57077 */ MCD_OPC_Decode, 214, 33, 147, 2, // Opcode: UQXTNv4i32 +/* 57082 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57104 +/* 57087 */ MCD_OPC_CheckPredicate, 3, 160, 116, 0, // Skip to: 86948 +/* 57092 */ MCD_OPC_CheckField, 21, 1, 1, 153, 116, 0, // Skip to: 86948 +/* 57099 */ MCD_OPC_Decode, 174, 33, 133, 2, // Opcode: UQSHLv4i32 +/* 57104 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 57126 +/* 57109 */ MCD_OPC_CheckPredicate, 3, 138, 116, 0, // Skip to: 86948 +/* 57114 */ MCD_OPC_CheckField, 21, 1, 1, 131, 116, 0, // Skip to: 86948 +/* 57121 */ MCD_OPC_Decode, 239, 30, 141, 2, // Opcode: UABALv4i32_v2i64 +/* 57126 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57148 +/* 57131 */ MCD_OPC_CheckPredicate, 3, 116, 116, 0, // Skip to: 86948 +/* 57136 */ MCD_OPC_CheckField, 21, 1, 1, 109, 116, 0, // Skip to: 86948 +/* 57143 */ MCD_OPC_Decode, 230, 33, 133, 2, // Opcode: URSHLv4i32 +/* 57148 */ MCD_OPC_FilterValue, 7, 99, 116, 0, // Skip to: 86948 +/* 57153 */ MCD_OPC_CheckPredicate, 3, 94, 116, 0, // Skip to: 86948 +/* 57158 */ MCD_OPC_CheckField, 21, 1, 1, 87, 116, 0, // Skip to: 86948 +/* 57165 */ MCD_OPC_Decode, 146, 33, 133, 2, // Opcode: UQRSHLv4i32 +/* 57170 */ MCD_OPC_FilterValue, 3, 179, 0, 0, // Skip to: 57354 +/* 57175 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 57178 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57200 +/* 57183 */ MCD_OPC_CheckPredicate, 3, 64, 116, 0, // Skip to: 86948 +/* 57188 */ MCD_OPC_CheckField, 21, 1, 1, 57, 116, 0, // Skip to: 86948 +/* 57195 */ MCD_OPC_Decode, 241, 21, 141, 2, // Opcode: RSUBHNv2i64_v4i32 +/* 57200 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57222 +/* 57205 */ MCD_OPC_CheckPredicate, 3, 42, 116, 0, // Skip to: 86948 +/* 57210 */ MCD_OPC_CheckField, 21, 1, 1, 35, 116, 0, // Skip to: 86948 +/* 57217 */ MCD_OPC_Decode, 131, 32, 133, 2, // Opcode: UMAXv4i32 +/* 57222 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 57244 +/* 57227 */ MCD_OPC_CheckPredicate, 3, 20, 116, 0, // Skip to: 86948 +/* 57232 */ MCD_OPC_CheckField, 16, 6, 32, 13, 116, 0, // Skip to: 86948 +/* 57239 */ MCD_OPC_Decode, 139, 31, 147, 2, // Opcode: UADALPv4i32_v2i64 +/* 57244 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57266 +/* 57249 */ MCD_OPC_CheckPredicate, 3, 254, 115, 0, // Skip to: 86948 +/* 57254 */ MCD_OPC_CheckField, 21, 1, 1, 247, 115, 0, // Skip to: 86948 +/* 57261 */ MCD_OPC_Decode, 160, 32, 133, 2, // Opcode: UMINv4i32 +/* 57266 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 57288 +/* 57271 */ MCD_OPC_CheckPredicate, 3, 232, 115, 0, // Skip to: 86948 +/* 57276 */ MCD_OPC_CheckField, 21, 1, 1, 225, 115, 0, // Skip to: 86948 +/* 57283 */ MCD_OPC_Decode, 251, 30, 133, 2, // Opcode: UABDLv4i32_v2i64 +/* 57288 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57310 +/* 57293 */ MCD_OPC_CheckPredicate, 3, 210, 115, 0, // Skip to: 86948 +/* 57298 */ MCD_OPC_CheckField, 21, 1, 1, 203, 115, 0, // Skip to: 86948 +/* 57305 */ MCD_OPC_Decode, 133, 31, 133, 2, // Opcode: UABDv4i32 +/* 57310 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 57332 +/* 57315 */ MCD_OPC_CheckPredicate, 3, 188, 115, 0, // Skip to: 86948 +/* 57320 */ MCD_OPC_CheckField, 16, 6, 32, 181, 115, 0, // Skip to: 86948 +/* 57327 */ MCD_OPC_Decode, 155, 25, 138, 2, // Opcode: SQNEGv4i32 +/* 57332 */ MCD_OPC_FilterValue, 7, 171, 115, 0, // Skip to: 86948 +/* 57337 */ MCD_OPC_CheckPredicate, 3, 166, 115, 0, // Skip to: 86948 +/* 57342 */ MCD_OPC_CheckField, 21, 1, 1, 159, 115, 0, // Skip to: 86948 +/* 57349 */ MCD_OPC_Decode, 245, 30, 141, 2, // Opcode: UABAv4i32 +/* 57354 */ MCD_OPC_FilterValue, 4, 199, 0, 0, // Skip to: 57558 +/* 57359 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 57362 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57384 +/* 57367 */ MCD_OPC_CheckPredicate, 3, 136, 115, 0, // Skip to: 86948 +/* 57372 */ MCD_OPC_CheckField, 21, 1, 1, 129, 115, 0, // Skip to: 86948 +/* 57379 */ MCD_OPC_Decode, 169, 32, 141, 2, // Opcode: UMLALv4i32_v2i64 +/* 57384 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 57422 +/* 57389 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 57392 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57407 +/* 57397 */ MCD_OPC_CheckPredicate, 7, 106, 115, 0, // Skip to: 86948 +/* 57402 */ MCD_OPC_Decode, 166, 25, 141, 2, // Opcode: SQRDMLAHv4i32 +/* 57407 */ MCD_OPC_FilterValue, 1, 96, 115, 0, // Skip to: 86948 +/* 57412 */ MCD_OPC_CheckPredicate, 3, 91, 115, 0, // Skip to: 86948 +/* 57417 */ MCD_OPC_Decode, 132, 30, 133, 2, // Opcode: SUBv4i32 +/* 57422 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 57444 +/* 57427 */ MCD_OPC_CheckPredicate, 3, 76, 115, 0, // Skip to: 86948 +/* 57432 */ MCD_OPC_CheckField, 16, 6, 32, 69, 115, 0, // Skip to: 86948 +/* 57439 */ MCD_OPC_Decode, 209, 3, 138, 2, // Opcode: CMGEv4i32rz +/* 57444 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 57482 +/* 57449 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 57452 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57467 +/* 57457 */ MCD_OPC_CheckPredicate, 7, 46, 115, 0, // Skip to: 86948 +/* 57462 */ MCD_OPC_Decode, 178, 25, 141, 2, // Opcode: SQRDMLSHv4i32 +/* 57467 */ MCD_OPC_FilterValue, 1, 36, 115, 0, // Skip to: 86948 +/* 57472 */ MCD_OPC_CheckPredicate, 3, 31, 115, 0, // Skip to: 86948 +/* 57477 */ MCD_OPC_Decode, 192, 3, 133, 2, // Opcode: CMEQv4i32 +/* 57482 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 57520 +/* 57487 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 57490 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57505 +/* 57495 */ MCD_OPC_CheckPredicate, 10, 8, 115, 0, // Skip to: 86948 +/* 57500 */ MCD_OPC_Decode, 218, 31, 141, 2, // Opcode: UDOTv16i8 +/* 57505 */ MCD_OPC_FilterValue, 1, 254, 114, 0, // Skip to: 86948 +/* 57510 */ MCD_OPC_CheckPredicate, 3, 249, 114, 0, // Skip to: 86948 +/* 57515 */ MCD_OPC_Decode, 228, 19, 141, 2, // Opcode: MLSv4i32 +/* 57520 */ MCD_OPC_FilterValue, 6, 239, 114, 0, // Skip to: 86948 +/* 57525 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 57528 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57543 +/* 57533 */ MCD_OPC_CheckPredicate, 3, 226, 114, 0, // Skip to: 86948 +/* 57538 */ MCD_OPC_Decode, 251, 3, 138, 2, // Opcode: CMLEv4i32rz +/* 57543 */ MCD_OPC_FilterValue, 33, 216, 114, 0, // Skip to: 86948 +/* 57548 */ MCD_OPC_CheckPredicate, 3, 211, 114, 0, // Skip to: 86948 +/* 57553 */ MCD_OPC_Decode, 244, 11, 138, 2, // Opcode: FRINTIv4f32 +/* 57558 */ MCD_OPC_FilterValue, 5, 182, 0, 0, // Skip to: 57745 +/* 57563 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 57566 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57588 +/* 57571 */ MCD_OPC_CheckPredicate, 3, 188, 114, 0, // Skip to: 86948 +/* 57576 */ MCD_OPC_CheckField, 21, 1, 1, 181, 114, 0, // Skip to: 86948 +/* 57583 */ MCD_OPC_Decode, 179, 32, 141, 2, // Opcode: UMLSLv4i32_v2i64 +/* 57588 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 57610 +/* 57593 */ MCD_OPC_CheckPredicate, 3, 166, 114, 0, // Skip to: 86948 +/* 57598 */ MCD_OPC_CheckField, 21, 1, 1, 159, 114, 0, // Skip to: 86948 +/* 57605 */ MCD_OPC_Decode, 236, 31, 133, 2, // Opcode: UMAXPv4i32 +/* 57610 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 57663 +/* 57615 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 57618 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 57633 +/* 57623 */ MCD_OPC_CheckPredicate, 3, 136, 114, 0, // Skip to: 86948 +/* 57628 */ MCD_OPC_Decode, 211, 8, 138, 2, // Opcode: FCVTPUv4f32 +/* 57633 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 57648 +/* 57638 */ MCD_OPC_CheckPredicate, 3, 121, 114, 0, // Skip to: 86948 +/* 57643 */ MCD_OPC_Decode, 245, 31, 160, 2, // Opcode: UMAXVv4i32v +/* 57648 */ MCD_OPC_FilterValue, 49, 111, 114, 0, // Skip to: 86948 +/* 57653 */ MCD_OPC_CheckPredicate, 3, 106, 114, 0, // Skip to: 86948 +/* 57658 */ MCD_OPC_Decode, 146, 32, 160, 2, // Opcode: UMINVv4i32v +/* 57663 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 57685 +/* 57668 */ MCD_OPC_CheckPredicate, 3, 91, 114, 0, // Skip to: 86948 +/* 57673 */ MCD_OPC_CheckField, 21, 1, 1, 84, 114, 0, // Skip to: 86948 +/* 57680 */ MCD_OPC_Decode, 137, 32, 133, 2, // Opcode: UMINPv4i32 +/* 57685 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 57707 +/* 57690 */ MCD_OPC_CheckPredicate, 3, 69, 114, 0, // Skip to: 86948 +/* 57695 */ MCD_OPC_CheckField, 21, 1, 1, 62, 114, 0, // Skip to: 86948 +/* 57702 */ MCD_OPC_Decode, 190, 25, 133, 2, // Opcode: SQRDMULHv4i32 +/* 57707 */ MCD_OPC_FilterValue, 6, 52, 114, 0, // Skip to: 86948 +/* 57712 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 57715 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57730 +/* 57720 */ MCD_OPC_CheckPredicate, 3, 39, 114, 0, // Skip to: 86948 +/* 57725 */ MCD_OPC_Decode, 184, 20, 138, 2, // Opcode: NEGv4i32 +/* 57730 */ MCD_OPC_FilterValue, 33, 29, 114, 0, // Skip to: 86948 +/* 57735 */ MCD_OPC_CheckPredicate, 3, 24, 114, 0, // Skip to: 86948 +/* 57740 */ MCD_OPC_Decode, 155, 9, 138, 2, // Opcode: FCVTZUv4f32 +/* 57745 */ MCD_OPC_FilterValue, 6, 185, 0, 0, // Skip to: 57935 +/* 57750 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 57753 */ MCD_OPC_FilterValue, 0, 116, 0, 0, // Skip to: 57874 +/* 57758 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 57761 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 57783 +/* 57766 */ MCD_OPC_CheckPredicate, 3, 249, 113, 0, // Skip to: 86948 +/* 57771 */ MCD_OPC_CheckField, 21, 1, 1, 242, 113, 0, // Skip to: 86948 +/* 57778 */ MCD_OPC_Decode, 199, 32, 133, 2, // Opcode: UMULLv4i32_v2i64 +/* 57783 */ MCD_OPC_FilterValue, 1, 48, 0, 0, // Skip to: 57836 +/* 57788 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 57791 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57806 +/* 57796 */ MCD_OPC_CheckPredicate, 3, 219, 113, 0, // Skip to: 86948 +/* 57801 */ MCD_OPC_Decode, 130, 7, 138, 2, // Opcode: FCMGEv4i32rz +/* 57806 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 57821 +/* 57811 */ MCD_OPC_CheckPredicate, 3, 204, 113, 0, // Skip to: 86948 +/* 57816 */ MCD_OPC_Decode, 242, 33, 138, 2, // Opcode: URSQRTEv4i32 +/* 57821 */ MCD_OPC_FilterValue, 48, 194, 113, 0, // Skip to: 86948 +/* 57826 */ MCD_OPC_CheckPredicate, 3, 189, 113, 0, // Skip to: 86948 +/* 57831 */ MCD_OPC_Decode, 138, 10, 160, 2, // Opcode: FMINNMVv4i32v +/* 57836 */ MCD_OPC_FilterValue, 3, 179, 113, 0, // Skip to: 86948 +/* 57841 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 57844 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 57859 +/* 57849 */ MCD_OPC_CheckPredicate, 3, 166, 113, 0, // Skip to: 86948 +/* 57854 */ MCD_OPC_Decode, 177, 7, 138, 2, // Opcode: FCMLEv4i32rz +/* 57859 */ MCD_OPC_FilterValue, 33, 156, 113, 0, // Skip to: 86948 +/* 57864 */ MCD_OPC_CheckPredicate, 3, 151, 113, 0, // Skip to: 86948 +/* 57869 */ MCD_OPC_Decode, 182, 12, 138, 2, // Opcode: FRSQRTEv4f32 +/* 57874 */ MCD_OPC_FilterValue, 1, 141, 113, 0, // Skip to: 86948 +/* 57879 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 57882 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57897 +/* 57887 */ MCD_OPC_CheckPredicate, 11, 128, 113, 0, // Skip to: 86948 +/* 57892 */ MCD_OPC_Decode, 164, 7, 169, 2, // Opcode: FCMLAv4f32 +/* 57897 */ MCD_OPC_FilterValue, 1, 118, 113, 0, // Skip to: 86948 +/* 57902 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 57905 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57920 +/* 57910 */ MCD_OPC_CheckPredicate, 3, 105, 113, 0, // Skip to: 86948 +/* 57915 */ MCD_OPC_Decode, 131, 10, 133, 2, // Opcode: FMINNMPv4f32 +/* 57920 */ MCD_OPC_FilterValue, 2, 95, 113, 0, // Skip to: 86948 +/* 57925 */ MCD_OPC_CheckPredicate, 3, 90, 113, 0, // Skip to: 86948 +/* 57930 */ MCD_OPC_Decode, 137, 6, 133, 2, // Opcode: FABDv4f32 +/* 57935 */ MCD_OPC_FilterValue, 7, 80, 113, 0, // Skip to: 86948 +/* 57940 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 57943 */ MCD_OPC_FilterValue, 1, 56, 0, 0, // Skip to: 58004 +/* 57948 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 57951 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57966 +/* 57956 */ MCD_OPC_CheckPredicate, 11, 59, 113, 0, // Skip to: 86948 +/* 57961 */ MCD_OPC_Decode, 209, 6, 170, 2, // Opcode: FCADDv4f32 +/* 57966 */ MCD_OPC_FilterValue, 1, 49, 113, 0, // Skip to: 86948 +/* 57971 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 57974 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 57989 +/* 57979 */ MCD_OPC_CheckPredicate, 3, 36, 113, 0, // Skip to: 86948 +/* 57984 */ MCD_OPC_Decode, 150, 7, 133, 2, // Opcode: FCMGTv4f32 +/* 57989 */ MCD_OPC_FilterValue, 1, 26, 113, 0, // Skip to: 86948 +/* 57994 */ MCD_OPC_CheckPredicate, 3, 21, 113, 0, // Skip to: 86948 +/* 57999 */ MCD_OPC_Decode, 157, 10, 133, 2, // Opcode: FMINPv4f32 +/* 58004 */ MCD_OPC_FilterValue, 2, 69, 0, 0, // Skip to: 58078 +/* 58009 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 58012 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 58034 +/* 58017 */ MCD_OPC_CheckPredicate, 3, 254, 112, 0, // Skip to: 86948 +/* 58022 */ MCD_OPC_CheckField, 12, 1, 1, 247, 112, 0, // Skip to: 86948 +/* 58029 */ MCD_OPC_Decode, 173, 11, 138, 2, // Opcode: FNEGv4f32 +/* 58034 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 58056 +/* 58039 */ MCD_OPC_CheckPredicate, 3, 232, 112, 0, // Skip to: 86948 +/* 58044 */ MCD_OPC_CheckField, 12, 1, 1, 225, 112, 0, // Skip to: 86948 +/* 58051 */ MCD_OPC_Decode, 207, 12, 138, 2, // Opcode: FSQRTv4f32 +/* 58056 */ MCD_OPC_FilterValue, 48, 215, 112, 0, // Skip to: 86948 +/* 58061 */ MCD_OPC_CheckPredicate, 3, 210, 112, 0, // Skip to: 86948 +/* 58066 */ MCD_OPC_CheckField, 12, 1, 1, 203, 112, 0, // Skip to: 86948 +/* 58073 */ MCD_OPC_Decode, 164, 10, 160, 2, // Opcode: FMINVv4i32v +/* 58078 */ MCD_OPC_FilterValue, 3, 193, 112, 0, // Skip to: 86948 +/* 58083 */ MCD_OPC_CheckPredicate, 3, 188, 112, 0, // Skip to: 86948 +/* 58088 */ MCD_OPC_CheckField, 21, 1, 1, 181, 112, 0, // Skip to: 86948 +/* 58095 */ MCD_OPC_CheckField, 12, 1, 0, 174, 112, 0, // Skip to: 86948 +/* 58102 */ MCD_OPC_Decode, 170, 6, 133, 2, // Opcode: FACGTv4f32 +/* 58107 */ MCD_OPC_FilterValue, 6, 164, 112, 0, // Skip to: 86948 +/* 58112 */ MCD_OPC_CheckPredicate, 6, 159, 112, 0, // Skip to: 86948 +/* 58117 */ MCD_OPC_CheckField, 21, 1, 0, 152, 112, 0, // Skip to: 86948 +/* 58124 */ MCD_OPC_Decode, 251, 34, 172, 2, // Opcode: XAR +/* 58129 */ MCD_OPC_FilterValue, 11, 14, 12, 0, // Skip to: 61220 +/* 58134 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 58137 */ MCD_OPC_FilterValue, 0, 154, 1, 0, // Skip to: 58552 +/* 58142 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 58145 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 58241 +/* 58150 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58153 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58175 +/* 58158 */ MCD_OPC_CheckPredicate, 4, 113, 112, 0, // Skip to: 86948 +/* 58163 */ MCD_OPC_CheckField, 21, 1, 0, 106, 112, 0, // Skip to: 86948 +/* 58170 */ MCD_OPC_Decode, 148, 10, 238, 1, // Opcode: FMINNMv4f16 +/* 58175 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58197 +/* 58180 */ MCD_OPC_CheckPredicate, 4, 91, 112, 0, // Skip to: 86948 +/* 58185 */ MCD_OPC_CheckField, 21, 1, 0, 84, 112, 0, // Skip to: 86948 +/* 58192 */ MCD_OPC_Decode, 130, 10, 238, 1, // Opcode: FMINNMPv4f16 +/* 58197 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58219 +/* 58202 */ MCD_OPC_CheckPredicate, 4, 69, 112, 0, // Skip to: 86948 +/* 58207 */ MCD_OPC_CheckField, 21, 1, 0, 62, 112, 0, // Skip to: 86948 +/* 58214 */ MCD_OPC_Decode, 150, 10, 133, 2, // Opcode: FMINNMv8f16 +/* 58219 */ MCD_OPC_FilterValue, 3, 52, 112, 0, // Skip to: 86948 +/* 58224 */ MCD_OPC_CheckPredicate, 4, 47, 112, 0, // Skip to: 86948 +/* 58229 */ MCD_OPC_CheckField, 21, 1, 0, 40, 112, 0, // Skip to: 86948 +/* 58236 */ MCD_OPC_Decode, 132, 10, 133, 2, // Opcode: FMINNMPv8f16 +/* 58241 */ MCD_OPC_FilterValue, 3, 85, 0, 0, // Skip to: 58331 +/* 58246 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58249 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58271 +/* 58254 */ MCD_OPC_CheckPredicate, 4, 17, 112, 0, // Skip to: 86948 +/* 58259 */ MCD_OPC_CheckField, 21, 1, 0, 10, 112, 0, // Skip to: 86948 +/* 58266 */ MCD_OPC_Decode, 209, 10, 130, 2, // Opcode: FMLSv4f16 +/* 58271 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 58309 +/* 58276 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 58279 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58294 +/* 58284 */ MCD_OPC_CheckPredicate, 4, 243, 111, 0, // Skip to: 86948 +/* 58289 */ MCD_OPC_Decode, 213, 10, 141, 2, // Opcode: FMLSv8f16 +/* 58294 */ MCD_OPC_FilterValue, 1, 233, 111, 0, // Skip to: 86948 +/* 58299 */ MCD_OPC_CheckPredicate, 3, 228, 111, 0, // Skip to: 86948 +/* 58304 */ MCD_OPC_Decode, 178, 24, 133, 2, // Opcode: SQADDv2i64 +/* 58309 */ MCD_OPC_FilterValue, 3, 218, 111, 0, // Skip to: 86948 +/* 58314 */ MCD_OPC_CheckPredicate, 3, 213, 111, 0, // Skip to: 86948 +/* 58319 */ MCD_OPC_CheckField, 21, 1, 1, 206, 111, 0, // Skip to: 86948 +/* 58326 */ MCD_OPC_Decode, 217, 32, 133, 2, // Opcode: UQADDv2i64 +/* 58331 */ MCD_OPC_FilterValue, 5, 91, 0, 0, // Skip to: 58427 +/* 58336 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58339 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58361 +/* 58344 */ MCD_OPC_CheckPredicate, 4, 183, 111, 0, // Skip to: 86948 +/* 58349 */ MCD_OPC_CheckField, 21, 1, 0, 176, 111, 0, // Skip to: 86948 +/* 58356 */ MCD_OPC_Decode, 229, 12, 238, 1, // Opcode: FSUBv4f16 +/* 58361 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58383 +/* 58366 */ MCD_OPC_CheckPredicate, 4, 161, 111, 0, // Skip to: 86948 +/* 58371 */ MCD_OPC_CheckField, 21, 1, 0, 154, 111, 0, // Skip to: 86948 +/* 58378 */ MCD_OPC_Decode, 136, 6, 238, 1, // Opcode: FABDv4f16 +/* 58383 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58405 +/* 58388 */ MCD_OPC_CheckPredicate, 4, 139, 111, 0, // Skip to: 86948 +/* 58393 */ MCD_OPC_CheckField, 21, 1, 0, 132, 111, 0, // Skip to: 86948 +/* 58400 */ MCD_OPC_Decode, 231, 12, 133, 2, // Opcode: FSUBv8f16 +/* 58405 */ MCD_OPC_FilterValue, 3, 122, 111, 0, // Skip to: 86948 +/* 58410 */ MCD_OPC_CheckPredicate, 4, 117, 111, 0, // Skip to: 86948 +/* 58415 */ MCD_OPC_CheckField, 21, 1, 0, 110, 111, 0, // Skip to: 86948 +/* 58422 */ MCD_OPC_Decode, 138, 6, 133, 2, // Opcode: FABDv8f16 +/* 58427 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 58456 +/* 58432 */ MCD_OPC_CheckPredicate, 3, 95, 111, 0, // Skip to: 86948 +/* 58437 */ MCD_OPC_CheckField, 29, 3, 2, 88, 111, 0, // Skip to: 86948 +/* 58444 */ MCD_OPC_CheckField, 21, 1, 0, 81, 111, 0, // Skip to: 86948 +/* 58451 */ MCD_OPC_Decode, 198, 34, 133, 2, // Opcode: UZP1v2i64 +/* 58456 */ MCD_OPC_FilterValue, 7, 71, 111, 0, // Skip to: 86948 +/* 58461 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58464 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58486 +/* 58469 */ MCD_OPC_CheckPredicate, 3, 58, 111, 0, // Skip to: 86948 +/* 58474 */ MCD_OPC_CheckField, 21, 1, 1, 51, 111, 0, // Skip to: 86948 +/* 58481 */ MCD_OPC_Decode, 202, 20, 238, 1, // Opcode: ORNv8i8 +/* 58486 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58508 +/* 58491 */ MCD_OPC_CheckPredicate, 3, 36, 111, 0, // Skip to: 86948 +/* 58496 */ MCD_OPC_CheckField, 21, 1, 1, 29, 111, 0, // Skip to: 86948 +/* 58503 */ MCD_OPC_Decode, 194, 2, 238, 1, // Opcode: BIFv8i8 +/* 58508 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58530 +/* 58513 */ MCD_OPC_CheckPredicate, 3, 14, 111, 0, // Skip to: 86948 +/* 58518 */ MCD_OPC_CheckField, 21, 1, 1, 7, 111, 0, // Skip to: 86948 +/* 58525 */ MCD_OPC_Decode, 201, 20, 133, 2, // Opcode: ORNv16i8 +/* 58530 */ MCD_OPC_FilterValue, 3, 253, 110, 0, // Skip to: 86948 +/* 58535 */ MCD_OPC_CheckPredicate, 3, 248, 110, 0, // Skip to: 86948 +/* 58540 */ MCD_OPC_CheckField, 21, 1, 1, 241, 110, 0, // Skip to: 86948 +/* 58547 */ MCD_OPC_Decode, 193, 2, 133, 2, // Opcode: BIFv16i8 +/* 58552 */ MCD_OPC_FilterValue, 1, 218, 1, 0, // Skip to: 59031 +/* 58557 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 58560 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 58612 +/* 58565 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58568 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58590 +/* 58573 */ MCD_OPC_CheckPredicate, 4, 210, 110, 0, // Skip to: 86948 +/* 58578 */ MCD_OPC_CheckField, 21, 1, 0, 203, 110, 0, // Skip to: 86948 +/* 58585 */ MCD_OPC_Decode, 149, 7, 238, 1, // Opcode: FCMGTv4f16 +/* 58590 */ MCD_OPC_FilterValue, 3, 193, 110, 0, // Skip to: 86948 +/* 58595 */ MCD_OPC_CheckPredicate, 4, 188, 110, 0, // Skip to: 86948 +/* 58600 */ MCD_OPC_CheckField, 21, 1, 0, 181, 110, 0, // Skip to: 86948 +/* 58607 */ MCD_OPC_Decode, 153, 7, 133, 2, // Opcode: FCMGTv8f16 +/* 58612 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 58641 +/* 58617 */ MCD_OPC_CheckPredicate, 3, 166, 110, 0, // Skip to: 86948 +/* 58622 */ MCD_OPC_CheckField, 29, 3, 2, 159, 110, 0, // Skip to: 86948 +/* 58629 */ MCD_OPC_CheckField, 21, 1, 0, 152, 110, 0, // Skip to: 86948 +/* 58636 */ MCD_OPC_Decode, 215, 30, 133, 2, // Opcode: TRN1v2i64 +/* 58641 */ MCD_OPC_FilterValue, 3, 85, 0, 0, // Skip to: 58731 +/* 58646 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58649 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58671 +/* 58654 */ MCD_OPC_CheckPredicate, 4, 129, 110, 0, // Skip to: 86948 +/* 58659 */ MCD_OPC_CheckField, 21, 1, 0, 122, 110, 0, // Skip to: 86948 +/* 58666 */ MCD_OPC_Decode, 169, 6, 238, 1, // Opcode: FACGTv4f16 +/* 58671 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58693 +/* 58676 */ MCD_OPC_CheckPredicate, 3, 107, 110, 0, // Skip to: 86948 +/* 58681 */ MCD_OPC_CheckField, 21, 1, 1, 100, 110, 0, // Skip to: 86948 +/* 58688 */ MCD_OPC_Decode, 160, 26, 133, 2, // Opcode: SQSUBv2i64 +/* 58693 */ MCD_OPC_FilterValue, 3, 90, 110, 0, // Skip to: 86948 +/* 58698 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 58701 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58716 +/* 58706 */ MCD_OPC_CheckPredicate, 4, 77, 110, 0, // Skip to: 86948 +/* 58711 */ MCD_OPC_Decode, 171, 6, 133, 2, // Opcode: FACGTv8f16 +/* 58716 */ MCD_OPC_FilterValue, 1, 67, 110, 0, // Skip to: 86948 +/* 58721 */ MCD_OPC_CheckPredicate, 3, 62, 110, 0, // Skip to: 86948 +/* 58726 */ MCD_OPC_Decode, 203, 33, 133, 2, // Opcode: UQSUBv2i64 +/* 58731 */ MCD_OPC_FilterValue, 5, 123, 0, 0, // Skip to: 58859 +/* 58736 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58739 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58761 +/* 58744 */ MCD_OPC_CheckPredicate, 4, 39, 110, 0, // Skip to: 86948 +/* 58749 */ MCD_OPC_CheckField, 21, 1, 0, 32, 110, 0, // Skip to: 86948 +/* 58756 */ MCD_OPC_Decode, 174, 10, 238, 1, // Opcode: FMINv4f16 +/* 58761 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 58783 +/* 58766 */ MCD_OPC_CheckPredicate, 4, 17, 110, 0, // Skip to: 86948 +/* 58771 */ MCD_OPC_CheckField, 21, 1, 0, 10, 110, 0, // Skip to: 86948 +/* 58778 */ MCD_OPC_Decode, 156, 10, 238, 1, // Opcode: FMINPv4f16 +/* 58783 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 58821 +/* 58788 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 58791 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58806 +/* 58796 */ MCD_OPC_CheckPredicate, 4, 243, 109, 0, // Skip to: 86948 +/* 58801 */ MCD_OPC_Decode, 176, 10, 133, 2, // Opcode: FMINv8f16 +/* 58806 */ MCD_OPC_FilterValue, 1, 233, 109, 0, // Skip to: 86948 +/* 58811 */ MCD_OPC_CheckPredicate, 3, 228, 109, 0, // Skip to: 86948 +/* 58816 */ MCD_OPC_Decode, 220, 3, 133, 2, // Opcode: CMGTv2i64 +/* 58821 */ MCD_OPC_FilterValue, 3, 218, 109, 0, // Skip to: 86948 +/* 58826 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 58829 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58844 +/* 58834 */ MCD_OPC_CheckPredicate, 4, 205, 109, 0, // Skip to: 86948 +/* 58839 */ MCD_OPC_Decode, 158, 10, 133, 2, // Opcode: FMINPv8f16 +/* 58844 */ MCD_OPC_FilterValue, 1, 195, 109, 0, // Skip to: 86948 +/* 58849 */ MCD_OPC_CheckPredicate, 3, 190, 109, 0, // Skip to: 86948 +/* 58854 */ MCD_OPC_Decode, 233, 3, 133, 2, // Opcode: CMHIv2i64 +/* 58859 */ MCD_OPC_FilterValue, 6, 77, 0, 0, // Skip to: 58941 +/* 58864 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 58867 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58889 +/* 58872 */ MCD_OPC_CheckPredicate, 3, 167, 109, 0, // Skip to: 86948 +/* 58877 */ MCD_OPC_CheckField, 29, 3, 2, 160, 109, 0, // Skip to: 86948 +/* 58884 */ MCD_OPC_Decode, 143, 35, 133, 2, // Opcode: ZIP1v2i64 +/* 58889 */ MCD_OPC_FilterValue, 1, 150, 109, 0, // Skip to: 86948 +/* 58894 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58897 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 58919 +/* 58902 */ MCD_OPC_CheckPredicate, 3, 137, 109, 0, // Skip to: 86948 +/* 58907 */ MCD_OPC_CheckField, 16, 5, 0, 130, 109, 0, // Skip to: 86948 +/* 58914 */ MCD_OPC_Decode, 147, 30, 147, 2, // Opcode: SUQADDv2i64 +/* 58919 */ MCD_OPC_FilterValue, 3, 120, 109, 0, // Skip to: 86948 +/* 58924 */ MCD_OPC_CheckPredicate, 3, 115, 109, 0, // Skip to: 86948 +/* 58929 */ MCD_OPC_CheckField, 16, 5, 0, 108, 109, 0, // Skip to: 86948 +/* 58936 */ MCD_OPC_Decode, 151, 34, 147, 2, // Opcode: USQADDv2i64 +/* 58941 */ MCD_OPC_FilterValue, 7, 98, 109, 0, // Skip to: 86948 +/* 58946 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 58949 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 58971 +/* 58954 */ MCD_OPC_CheckPredicate, 4, 85, 109, 0, // Skip to: 86948 +/* 58959 */ MCD_OPC_CheckField, 21, 1, 0, 78, 109, 0, // Skip to: 86948 +/* 58966 */ MCD_OPC_Decode, 192, 12, 238, 1, // Opcode: FRSQRTSv4f16 +/* 58971 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 59009 +/* 58976 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 58979 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 58994 +/* 58984 */ MCD_OPC_CheckPredicate, 4, 55, 109, 0, // Skip to: 86948 +/* 58989 */ MCD_OPC_Decode, 194, 12, 133, 2, // Opcode: FRSQRTSv8f16 +/* 58994 */ MCD_OPC_FilterValue, 1, 45, 109, 0, // Skip to: 86948 +/* 58999 */ MCD_OPC_CheckPredicate, 3, 40, 109, 0, // Skip to: 86948 +/* 59004 */ MCD_OPC_Decode, 204, 3, 133, 2, // Opcode: CMGEv2i64 +/* 59009 */ MCD_OPC_FilterValue, 3, 30, 109, 0, // Skip to: 86948 +/* 59014 */ MCD_OPC_CheckPredicate, 3, 25, 109, 0, // Skip to: 86948 +/* 59019 */ MCD_OPC_CheckField, 21, 1, 1, 18, 109, 0, // Skip to: 86948 +/* 59026 */ MCD_OPC_Decode, 241, 3, 133, 2, // Opcode: CMHSv2i64 +/* 59031 */ MCD_OPC_FilterValue, 2, 240, 0, 0, // Skip to: 59276 +/* 59036 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 59039 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 59091 +/* 59044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59047 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59069 +/* 59052 */ MCD_OPC_CheckPredicate, 3, 243, 108, 0, // Skip to: 86948 +/* 59057 */ MCD_OPC_CheckField, 21, 1, 1, 236, 108, 0, // Skip to: 86948 +/* 59064 */ MCD_OPC_Decode, 230, 26, 133, 2, // Opcode: SSHLv2i64 +/* 59069 */ MCD_OPC_FilterValue, 3, 226, 108, 0, // Skip to: 86948 +/* 59074 */ MCD_OPC_CheckPredicate, 3, 221, 108, 0, // Skip to: 86948 +/* 59079 */ MCD_OPC_CheckField, 21, 1, 1, 214, 108, 0, // Skip to: 86948 +/* 59086 */ MCD_OPC_Decode, 132, 34, 133, 2, // Opcode: USHLv2i64 +/* 59091 */ MCD_OPC_FilterValue, 3, 47, 0, 0, // Skip to: 59143 +/* 59096 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59099 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59121 +/* 59104 */ MCD_OPC_CheckPredicate, 3, 191, 108, 0, // Skip to: 86948 +/* 59109 */ MCD_OPC_CheckField, 21, 1, 1, 184, 108, 0, // Skip to: 86948 +/* 59116 */ MCD_OPC_Decode, 246, 25, 133, 2, // Opcode: SQSHLv2i64 +/* 59121 */ MCD_OPC_FilterValue, 3, 174, 108, 0, // Skip to: 86948 +/* 59126 */ MCD_OPC_CheckPredicate, 3, 169, 108, 0, // Skip to: 86948 +/* 59131 */ MCD_OPC_CheckField, 21, 1, 1, 162, 108, 0, // Skip to: 86948 +/* 59138 */ MCD_OPC_Decode, 170, 33, 133, 2, // Opcode: UQSHLv2i64 +/* 59143 */ MCD_OPC_FilterValue, 5, 47, 0, 0, // Skip to: 59195 +/* 59148 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59151 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59173 +/* 59156 */ MCD_OPC_CheckPredicate, 3, 139, 108, 0, // Skip to: 86948 +/* 59161 */ MCD_OPC_CheckField, 21, 1, 1, 132, 108, 0, // Skip to: 86948 +/* 59168 */ MCD_OPC_Decode, 200, 26, 133, 2, // Opcode: SRSHLv2i64 +/* 59173 */ MCD_OPC_FilterValue, 3, 122, 108, 0, // Skip to: 86948 +/* 59178 */ MCD_OPC_CheckPredicate, 3, 117, 108, 0, // Skip to: 86948 +/* 59183 */ MCD_OPC_CheckField, 21, 1, 1, 110, 108, 0, // Skip to: 86948 +/* 59190 */ MCD_OPC_Decode, 228, 33, 133, 2, // Opcode: URSHLv2i64 +/* 59195 */ MCD_OPC_FilterValue, 6, 24, 0, 0, // Skip to: 59224 +/* 59200 */ MCD_OPC_CheckPredicate, 3, 95, 108, 0, // Skip to: 86948 +/* 59205 */ MCD_OPC_CheckField, 29, 3, 2, 88, 108, 0, // Skip to: 86948 +/* 59212 */ MCD_OPC_CheckField, 21, 1, 0, 81, 108, 0, // Skip to: 86948 +/* 59219 */ MCD_OPC_Decode, 213, 34, 133, 2, // Opcode: UZP2v2i64 +/* 59224 */ MCD_OPC_FilterValue, 7, 71, 108, 0, // Skip to: 86948 +/* 59229 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59232 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59254 +/* 59237 */ MCD_OPC_CheckPredicate, 3, 58, 108, 0, // Skip to: 86948 +/* 59242 */ MCD_OPC_CheckField, 21, 1, 1, 51, 108, 0, // Skip to: 86948 +/* 59249 */ MCD_OPC_Decode, 200, 25, 133, 2, // Opcode: SQRSHLv2i64 +/* 59254 */ MCD_OPC_FilterValue, 3, 41, 108, 0, // Skip to: 86948 +/* 59259 */ MCD_OPC_CheckPredicate, 3, 36, 108, 0, // Skip to: 86948 +/* 59264 */ MCD_OPC_CheckField, 21, 1, 1, 29, 108, 0, // Skip to: 86948 +/* 59271 */ MCD_OPC_Decode, 144, 33, 133, 2, // Opcode: UQRSHLv2i64 +/* 59276 */ MCD_OPC_FilterValue, 3, 114, 0, 0, // Skip to: 59395 +/* 59281 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 59284 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 59313 +/* 59289 */ MCD_OPC_CheckPredicate, 3, 6, 108, 0, // Skip to: 86948 +/* 59294 */ MCD_OPC_CheckField, 29, 3, 2, 255, 107, 0, // Skip to: 86948 +/* 59301 */ MCD_OPC_CheckField, 21, 1, 0, 248, 107, 0, // Skip to: 86948 +/* 59308 */ MCD_OPC_Decode, 230, 30, 133, 2, // Opcode: TRN2v2i64 +/* 59313 */ MCD_OPC_FilterValue, 6, 238, 107, 0, // Skip to: 86948 +/* 59318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 59321 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 59343 +/* 59326 */ MCD_OPC_CheckPredicate, 3, 225, 107, 0, // Skip to: 86948 +/* 59331 */ MCD_OPC_CheckField, 29, 3, 2, 218, 107, 0, // Skip to: 86948 +/* 59338 */ MCD_OPC_Decode, 158, 35, 133, 2, // Opcode: ZIP2v2i64 +/* 59343 */ MCD_OPC_FilterValue, 1, 208, 107, 0, // Skip to: 86948 +/* 59348 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59351 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59373 +/* 59356 */ MCD_OPC_CheckPredicate, 3, 195, 107, 0, // Skip to: 86948 +/* 59361 */ MCD_OPC_CheckField, 16, 5, 0, 188, 107, 0, // Skip to: 86948 +/* 59368 */ MCD_OPC_Decode, 159, 24, 138, 2, // Opcode: SQABSv2i64 +/* 59373 */ MCD_OPC_FilterValue, 3, 178, 107, 0, // Skip to: 86948 +/* 59378 */ MCD_OPC_CheckPredicate, 3, 173, 107, 0, // Skip to: 86948 +/* 59383 */ MCD_OPC_CheckField, 16, 5, 0, 166, 107, 0, // Skip to: 86948 +/* 59390 */ MCD_OPC_Decode, 153, 25, 138, 2, // Opcode: SQNEGv2i64 +/* 59395 */ MCD_OPC_FilterValue, 4, 166, 1, 0, // Skip to: 59822 +/* 59400 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 59403 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 59432 +/* 59408 */ MCD_OPC_CheckPredicate, 6, 143, 107, 0, // Skip to: 86948 +/* 59413 */ MCD_OPC_CheckField, 29, 3, 6, 136, 107, 0, // Skip to: 86948 +/* 59420 */ MCD_OPC_CheckField, 16, 6, 0, 129, 107, 0, // Skip to: 86948 +/* 59427 */ MCD_OPC_Decode, 253, 22, 173, 2, // Opcode: SHA512SU0 +/* 59432 */ MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 59506 +/* 59437 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59440 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59462 +/* 59445 */ MCD_OPC_CheckPredicate, 3, 106, 107, 0, // Skip to: 86948 +/* 59450 */ MCD_OPC_CheckField, 21, 1, 1, 99, 107, 0, // Skip to: 86948 +/* 59457 */ MCD_OPC_Decode, 197, 1, 133, 2, // Opcode: ADDv2i64 +/* 59462 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 59484 +/* 59467 */ MCD_OPC_CheckPredicate, 3, 84, 107, 0, // Skip to: 86948 +/* 59472 */ MCD_OPC_CheckField, 21, 1, 1, 77, 107, 0, // Skip to: 86948 +/* 59479 */ MCD_OPC_Decode, 130, 30, 133, 2, // Opcode: SUBv2i64 +/* 59484 */ MCD_OPC_FilterValue, 6, 67, 107, 0, // Skip to: 86948 +/* 59489 */ MCD_OPC_CheckPredicate, 9, 62, 107, 0, // Skip to: 86948 +/* 59494 */ MCD_OPC_CheckField, 16, 6, 0, 55, 107, 0, // Skip to: 86948 +/* 59501 */ MCD_OPC_Decode, 174, 23, 173, 2, // Opcode: SM4E +/* 59506 */ MCD_OPC_FilterValue, 2, 101, 0, 0, // Skip to: 59612 +/* 59511 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 59514 */ MCD_OPC_FilterValue, 32, 33, 0, 0, // Skip to: 59552 +/* 59519 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59522 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 59537 +/* 59527 */ MCD_OPC_CheckPredicate, 3, 24, 107, 0, // Skip to: 86948 +/* 59532 */ MCD_OPC_Decode, 221, 3, 138, 2, // Opcode: CMGTv2i64rz +/* 59537 */ MCD_OPC_FilterValue, 3, 14, 107, 0, // Skip to: 86948 +/* 59542 */ MCD_OPC_CheckPredicate, 3, 9, 107, 0, // Skip to: 86948 +/* 59547 */ MCD_OPC_Decode, 205, 3, 138, 2, // Opcode: CMGEv2i64rz +/* 59552 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 59574 +/* 59557 */ MCD_OPC_CheckPredicate, 3, 250, 106, 0, // Skip to: 86948 +/* 59562 */ MCD_OPC_CheckField, 29, 3, 2, 243, 106, 0, // Skip to: 86948 +/* 59569 */ MCD_OPC_Decode, 147, 12, 138, 2, // Opcode: FRINTPv2f64 +/* 59574 */ MCD_OPC_FilterValue, 57, 233, 106, 0, // Skip to: 86948 +/* 59579 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59582 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 59597 +/* 59587 */ MCD_OPC_CheckPredicate, 4, 220, 106, 0, // Skip to: 86948 +/* 59592 */ MCD_OPC_Decode, 148, 12, 239, 1, // Opcode: FRINTPv4f16 +/* 59597 */ MCD_OPC_FilterValue, 2, 210, 106, 0, // Skip to: 86948 +/* 59602 */ MCD_OPC_CheckPredicate, 4, 205, 106, 0, // Skip to: 86948 +/* 59607 */ MCD_OPC_Decode, 150, 12, 138, 2, // Opcode: FRINTPv8f16 +/* 59612 */ MCD_OPC_FilterValue, 3, 47, 0, 0, // Skip to: 59664 +/* 59617 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59620 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59642 +/* 59625 */ MCD_OPC_CheckPredicate, 3, 182, 106, 0, // Skip to: 86948 +/* 59630 */ MCD_OPC_CheckField, 21, 1, 1, 175, 106, 0, // Skip to: 86948 +/* 59637 */ MCD_OPC_Decode, 236, 4, 133, 2, // Opcode: CMTSTv2i64 +/* 59642 */ MCD_OPC_FilterValue, 3, 165, 106, 0, // Skip to: 86948 +/* 59647 */ MCD_OPC_CheckPredicate, 3, 160, 106, 0, // Skip to: 86948 +/* 59652 */ MCD_OPC_CheckField, 21, 1, 1, 153, 106, 0, // Skip to: 86948 +/* 59659 */ MCD_OPC_Decode, 188, 3, 133, 2, // Opcode: CMEQv2i64 +/* 59664 */ MCD_OPC_FilterValue, 6, 143, 106, 0, // Skip to: 86948 +/* 59669 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59672 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 59694 +/* 59677 */ MCD_OPC_CheckPredicate, 4, 130, 106, 0, // Skip to: 86948 +/* 59682 */ MCD_OPC_CheckField, 16, 6, 57, 123, 106, 0, // Skip to: 86948 +/* 59689 */ MCD_OPC_Decode, 170, 12, 239, 1, // Opcode: FRINTZv4f16 +/* 59694 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 59716 +/* 59699 */ MCD_OPC_CheckPredicate, 4, 108, 106, 0, // Skip to: 86948 +/* 59704 */ MCD_OPC_CheckField, 16, 6, 57, 101, 106, 0, // Skip to: 86948 +/* 59711 */ MCD_OPC_Decode, 243, 11, 239, 1, // Opcode: FRINTIv4f16 +/* 59716 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 59769 +/* 59721 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 59724 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59739 +/* 59729 */ MCD_OPC_CheckPredicate, 3, 78, 106, 0, // Skip to: 86948 +/* 59734 */ MCD_OPC_Decode, 189, 3, 138, 2, // Opcode: CMEQv2i64rz +/* 59739 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59754 +/* 59744 */ MCD_OPC_CheckPredicate, 3, 63, 106, 0, // Skip to: 86948 +/* 59749 */ MCD_OPC_Decode, 169, 12, 138, 2, // Opcode: FRINTZv2f64 +/* 59754 */ MCD_OPC_FilterValue, 57, 53, 106, 0, // Skip to: 86948 +/* 59759 */ MCD_OPC_CheckPredicate, 4, 48, 106, 0, // Skip to: 86948 +/* 59764 */ MCD_OPC_Decode, 172, 12, 138, 2, // Opcode: FRINTZv8f16 +/* 59769 */ MCD_OPC_FilterValue, 3, 38, 106, 0, // Skip to: 86948 +/* 59774 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 59777 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59792 +/* 59782 */ MCD_OPC_CheckPredicate, 3, 25, 106, 0, // Skip to: 86948 +/* 59787 */ MCD_OPC_Decode, 249, 3, 138, 2, // Opcode: CMLEv2i64rz +/* 59792 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59807 +/* 59797 */ MCD_OPC_CheckPredicate, 3, 10, 106, 0, // Skip to: 86948 +/* 59802 */ MCD_OPC_Decode, 242, 11, 138, 2, // Opcode: FRINTIv2f64 +/* 59807 */ MCD_OPC_FilterValue, 57, 0, 106, 0, // Skip to: 86948 +/* 59812 */ MCD_OPC_CheckPredicate, 4, 251, 105, 0, // Skip to: 86948 +/* 59817 */ MCD_OPC_Decode, 245, 11, 138, 2, // Opcode: FRINTIv8f16 +/* 59822 */ MCD_OPC_FilterValue, 5, 93, 1, 0, // Skip to: 60176 +/* 59827 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 59830 */ MCD_OPC_FilterValue, 0, 47, 0, 0, // Skip to: 59882 +/* 59835 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 59838 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59860 +/* 59843 */ MCD_OPC_CheckPredicate, 4, 220, 105, 0, // Skip to: 86948 +/* 59848 */ MCD_OPC_CheckField, 16, 6, 57, 213, 105, 0, // Skip to: 86948 +/* 59855 */ MCD_OPC_Decode, 196, 8, 239, 1, // Opcode: FCVTPSv4f16 +/* 59860 */ MCD_OPC_FilterValue, 6, 203, 105, 0, // Skip to: 86948 +/* 59865 */ MCD_OPC_CheckPredicate, 4, 198, 105, 0, // Skip to: 86948 +/* 59870 */ MCD_OPC_CheckField, 16, 6, 57, 191, 105, 0, // Skip to: 86948 +/* 59877 */ MCD_OPC_Decode, 247, 8, 239, 1, // Opcode: FCVTZSv4f16 +/* 59882 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 59934 +/* 59887 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 59890 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 59912 +/* 59895 */ MCD_OPC_CheckPredicate, 4, 168, 105, 0, // Skip to: 86948 +/* 59900 */ MCD_OPC_CheckField, 16, 6, 57, 161, 105, 0, // Skip to: 86948 +/* 59907 */ MCD_OPC_Decode, 210, 8, 239, 1, // Opcode: FCVTPUv4f16 +/* 59912 */ MCD_OPC_FilterValue, 6, 151, 105, 0, // Skip to: 86948 +/* 59917 */ MCD_OPC_CheckPredicate, 4, 146, 105, 0, // Skip to: 86948 +/* 59922 */ MCD_OPC_CheckField, 16, 6, 57, 139, 105, 0, // Skip to: 86948 +/* 59929 */ MCD_OPC_Decode, 154, 9, 239, 1, // Opcode: FCVTZUv4f16 +/* 59934 */ MCD_OPC_FilterValue, 2, 131, 0, 0, // Skip to: 60070 +/* 59939 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 59942 */ MCD_OPC_FilterValue, 2, 48, 0, 0, // Skip to: 59995 +/* 59947 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 59950 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 59965 +/* 59955 */ MCD_OPC_CheckPredicate, 3, 108, 105, 0, // Skip to: 86948 +/* 59960 */ MCD_OPC_Decode, 129, 4, 138, 2, // Opcode: CMLTv2i64rz +/* 59965 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 59980 +/* 59970 */ MCD_OPC_CheckPredicate, 3, 93, 105, 0, // Skip to: 86948 +/* 59975 */ MCD_OPC_Decode, 195, 8, 138, 2, // Opcode: FCVTPSv2f64 +/* 59980 */ MCD_OPC_FilterValue, 57, 83, 105, 0, // Skip to: 86948 +/* 59985 */ MCD_OPC_CheckPredicate, 4, 78, 105, 0, // Skip to: 86948 +/* 59990 */ MCD_OPC_Decode, 198, 8, 138, 2, // Opcode: FCVTPSv8f16 +/* 59995 */ MCD_OPC_FilterValue, 6, 48, 0, 0, // Skip to: 60048 +/* 60000 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60003 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60018 +/* 60008 */ MCD_OPC_CheckPredicate, 3, 55, 105, 0, // Skip to: 86948 +/* 60013 */ MCD_OPC_Decode, 133, 1, 138, 2, // Opcode: ABSv2i64 +/* 60018 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 60033 +/* 60023 */ MCD_OPC_CheckPredicate, 3, 40, 105, 0, // Skip to: 86948 +/* 60028 */ MCD_OPC_Decode, 244, 8, 138, 2, // Opcode: FCVTZSv2f64 +/* 60033 */ MCD_OPC_FilterValue, 57, 30, 105, 0, // Skip to: 86948 +/* 60038 */ MCD_OPC_CheckPredicate, 4, 25, 105, 0, // Skip to: 86948 +/* 60043 */ MCD_OPC_Decode, 251, 8, 138, 2, // Opcode: FCVTZSv8f16 +/* 60048 */ MCD_OPC_FilterValue, 7, 15, 105, 0, // Skip to: 86948 +/* 60053 */ MCD_OPC_CheckPredicate, 3, 10, 105, 0, // Skip to: 86948 +/* 60058 */ MCD_OPC_CheckField, 21, 1, 1, 3, 105, 0, // Skip to: 86948 +/* 60065 */ MCD_OPC_Decode, 151, 1, 133, 2, // Opcode: ADDPv2i64 +/* 60070 */ MCD_OPC_FilterValue, 3, 249, 104, 0, // Skip to: 86948 +/* 60075 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60078 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 60100 +/* 60083 */ MCD_OPC_CheckPredicate, 3, 236, 104, 0, // Skip to: 86948 +/* 60088 */ MCD_OPC_CheckField, 10, 3, 6, 229, 104, 0, // Skip to: 86948 +/* 60095 */ MCD_OPC_Decode, 182, 20, 138, 2, // Opcode: NEGv2i64 +/* 60100 */ MCD_OPC_FilterValue, 33, 33, 0, 0, // Skip to: 60138 +/* 60105 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 60108 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60123 +/* 60113 */ MCD_OPC_CheckPredicate, 3, 206, 104, 0, // Skip to: 86948 +/* 60118 */ MCD_OPC_Decode, 209, 8, 138, 2, // Opcode: FCVTPUv2f64 +/* 60123 */ MCD_OPC_FilterValue, 6, 196, 104, 0, // Skip to: 86948 +/* 60128 */ MCD_OPC_CheckPredicate, 3, 191, 104, 0, // Skip to: 86948 +/* 60133 */ MCD_OPC_Decode, 151, 9, 138, 2, // Opcode: FCVTZUv2f64 +/* 60138 */ MCD_OPC_FilterValue, 57, 181, 104, 0, // Skip to: 86948 +/* 60143 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 60146 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60161 +/* 60151 */ MCD_OPC_CheckPredicate, 4, 168, 104, 0, // Skip to: 86948 +/* 60156 */ MCD_OPC_Decode, 212, 8, 138, 2, // Opcode: FCVTPUv8f16 +/* 60161 */ MCD_OPC_FilterValue, 6, 158, 104, 0, // Skip to: 86948 +/* 60166 */ MCD_OPC_CheckPredicate, 4, 153, 104, 0, // Skip to: 86948 +/* 60171 */ MCD_OPC_Decode, 158, 9, 138, 2, // Opcode: FCVTZUv8f16 +/* 60176 */ MCD_OPC_FilterValue, 6, 4, 2, 0, // Skip to: 60697 +/* 60181 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 60184 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 60252 +/* 60189 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 60192 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 60214 +/* 60197 */ MCD_OPC_CheckPredicate, 4, 122, 104, 0, // Skip to: 86948 +/* 60202 */ MCD_OPC_CheckField, 16, 6, 56, 115, 104, 0, // Skip to: 86948 +/* 60209 */ MCD_OPC_Decode, 151, 7, 239, 1, // Opcode: FCMGTv4i16rz +/* 60214 */ MCD_OPC_FilterValue, 6, 105, 104, 0, // Skip to: 86948 +/* 60219 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60222 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60237 +/* 60227 */ MCD_OPC_CheckPredicate, 4, 92, 104, 0, // Skip to: 86948 +/* 60232 */ MCD_OPC_Decode, 235, 6, 239, 1, // Opcode: FCMEQv4i16rz +/* 60237 */ MCD_OPC_FilterValue, 57, 82, 104, 0, // Skip to: 86948 +/* 60242 */ MCD_OPC_CheckPredicate, 4, 77, 104, 0, // Skip to: 86948 +/* 60247 */ MCD_OPC_Decode, 204, 11, 239, 1, // Opcode: FRECPEv4f16 +/* 60252 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 60320 +/* 60257 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 60260 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 60282 +/* 60265 */ MCD_OPC_CheckPredicate, 4, 54, 104, 0, // Skip to: 86948 +/* 60270 */ MCD_OPC_CheckField, 16, 6, 56, 47, 104, 0, // Skip to: 86948 +/* 60277 */ MCD_OPC_Decode, 129, 7, 239, 1, // Opcode: FCMGEv4i16rz +/* 60282 */ MCD_OPC_FilterValue, 6, 37, 104, 0, // Skip to: 86948 +/* 60287 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60290 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60305 +/* 60295 */ MCD_OPC_CheckPredicate, 4, 24, 104, 0, // Skip to: 86948 +/* 60300 */ MCD_OPC_Decode, 176, 7, 239, 1, // Opcode: FCMLEv4i16rz +/* 60305 */ MCD_OPC_FilterValue, 57, 14, 104, 0, // Skip to: 86948 +/* 60310 */ MCD_OPC_CheckPredicate, 4, 9, 104, 0, // Skip to: 86948 +/* 60315 */ MCD_OPC_Decode, 181, 12, 239, 1, // Opcode: FRSQRTEv4f16 +/* 60320 */ MCD_OPC_FilterValue, 2, 175, 0, 0, // Skip to: 60500 +/* 60325 */ MCD_OPC_ExtractField, 10, 3, // Inst{12-10} ... +/* 60328 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 60350 +/* 60333 */ MCD_OPC_CheckPredicate, 3, 242, 103, 0, // Skip to: 86948 +/* 60338 */ MCD_OPC_CheckField, 21, 1, 1, 235, 103, 0, // Skip to: 86948 +/* 60345 */ MCD_OPC_Decode, 147, 10, 133, 2, // Opcode: FMINNMv2f64 +/* 60350 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 60388 +/* 60355 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60358 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60373 +/* 60363 */ MCD_OPC_CheckPredicate, 3, 212, 103, 0, // Skip to: 86948 +/* 60368 */ MCD_OPC_Decode, 148, 7, 138, 2, // Opcode: FCMGTv2i64rz +/* 60373 */ MCD_OPC_FilterValue, 56, 202, 103, 0, // Skip to: 86948 +/* 60378 */ MCD_OPC_CheckPredicate, 4, 197, 103, 0, // Skip to: 86948 +/* 60383 */ MCD_OPC_Decode, 154, 7, 138, 2, // Opcode: FCMGTv8i16rz +/* 60388 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 60410 +/* 60393 */ MCD_OPC_CheckPredicate, 3, 182, 103, 0, // Skip to: 86948 +/* 60398 */ MCD_OPC_CheckField, 21, 1, 1, 175, 103, 0, // Skip to: 86948 +/* 60405 */ MCD_OPC_Decode, 206, 10, 141, 2, // Opcode: FMLSv2f64 +/* 60410 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 60432 +/* 60415 */ MCD_OPC_CheckPredicate, 3, 160, 103, 0, // Skip to: 86948 +/* 60420 */ MCD_OPC_CheckField, 21, 1, 1, 153, 103, 0, // Skip to: 86948 +/* 60427 */ MCD_OPC_Decode, 228, 12, 133, 2, // Opcode: FSUBv2f64 +/* 60432 */ MCD_OPC_FilterValue, 6, 143, 103, 0, // Skip to: 86948 +/* 60437 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60440 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 60455 +/* 60445 */ MCD_OPC_CheckPredicate, 3, 130, 103, 0, // Skip to: 86948 +/* 60450 */ MCD_OPC_Decode, 232, 6, 138, 2, // Opcode: FCMEQv2i64rz +/* 60455 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 60470 +/* 60460 */ MCD_OPC_CheckPredicate, 3, 115, 103, 0, // Skip to: 86948 +/* 60465 */ MCD_OPC_Decode, 203, 11, 138, 2, // Opcode: FRECPEv2f64 +/* 60470 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 60485 +/* 60475 */ MCD_OPC_CheckPredicate, 4, 100, 103, 0, // Skip to: 86948 +/* 60480 */ MCD_OPC_Decode, 238, 6, 138, 2, // Opcode: FCMEQv8i16rz +/* 60485 */ MCD_OPC_FilterValue, 57, 90, 103, 0, // Skip to: 86948 +/* 60490 */ MCD_OPC_CheckPredicate, 4, 85, 103, 0, // Skip to: 86948 +/* 60495 */ MCD_OPC_Decode, 206, 11, 138, 2, // Opcode: FRECPEv8f16 +/* 60500 */ MCD_OPC_FilterValue, 3, 75, 103, 0, // Skip to: 86948 +/* 60505 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 60508 */ MCD_OPC_FilterValue, 0, 123, 0, 0, // Skip to: 60636 +/* 60513 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60516 */ MCD_OPC_FilterValue, 32, 33, 0, 0, // Skip to: 60554 +/* 60521 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 60524 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 60539 +/* 60529 */ MCD_OPC_CheckPredicate, 3, 46, 103, 0, // Skip to: 86948 +/* 60534 */ MCD_OPC_Decode, 254, 6, 138, 2, // Opcode: FCMGEv2i64rz +/* 60539 */ MCD_OPC_FilterValue, 3, 36, 103, 0, // Skip to: 86948 +/* 60544 */ MCD_OPC_CheckPredicate, 3, 31, 103, 0, // Skip to: 86948 +/* 60549 */ MCD_OPC_Decode, 175, 7, 138, 2, // Opcode: FCMLEv2i64rz +/* 60554 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 60576 +/* 60559 */ MCD_OPC_CheckPredicate, 3, 16, 103, 0, // Skip to: 86948 +/* 60564 */ MCD_OPC_CheckField, 11, 2, 3, 9, 103, 0, // Skip to: 86948 +/* 60571 */ MCD_OPC_Decode, 180, 12, 138, 2, // Opcode: FRSQRTEv2f64 +/* 60576 */ MCD_OPC_FilterValue, 56, 33, 0, 0, // Skip to: 60614 +/* 60581 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 60584 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 60599 +/* 60589 */ MCD_OPC_CheckPredicate, 4, 242, 102, 0, // Skip to: 86948 +/* 60594 */ MCD_OPC_Decode, 132, 7, 138, 2, // Opcode: FCMGEv8i16rz +/* 60599 */ MCD_OPC_FilterValue, 3, 232, 102, 0, // Skip to: 86948 +/* 60604 */ MCD_OPC_CheckPredicate, 4, 227, 102, 0, // Skip to: 86948 +/* 60609 */ MCD_OPC_Decode, 178, 7, 138, 2, // Opcode: FCMLEv8i16rz +/* 60614 */ MCD_OPC_FilterValue, 57, 217, 102, 0, // Skip to: 86948 +/* 60619 */ MCD_OPC_CheckPredicate, 4, 212, 102, 0, // Skip to: 86948 +/* 60624 */ MCD_OPC_CheckField, 11, 2, 3, 205, 102, 0, // Skip to: 86948 +/* 60631 */ MCD_OPC_Decode, 183, 12, 138, 2, // Opcode: FRSQRTEv8f16 +/* 60636 */ MCD_OPC_FilterValue, 1, 195, 102, 0, // Skip to: 86948 +/* 60641 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 60644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 60659 +/* 60649 */ MCD_OPC_CheckPredicate, 11, 182, 102, 0, // Skip to: 86948 +/* 60654 */ MCD_OPC_Decode, 161, 7, 169, 2, // Opcode: FCMLAv2f64 +/* 60659 */ MCD_OPC_FilterValue, 1, 172, 102, 0, // Skip to: 86948 +/* 60664 */ MCD_OPC_ExtractField, 11, 2, // Inst{12-11} ... +/* 60667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 60682 +/* 60672 */ MCD_OPC_CheckPredicate, 3, 159, 102, 0, // Skip to: 86948 +/* 60677 */ MCD_OPC_Decode, 254, 9, 133, 2, // Opcode: FMINNMPv2f64 +/* 60682 */ MCD_OPC_FilterValue, 2, 149, 102, 0, // Skip to: 86948 +/* 60687 */ MCD_OPC_CheckPredicate, 3, 144, 102, 0, // Skip to: 86948 +/* 60692 */ MCD_OPC_Decode, 135, 6, 133, 2, // Opcode: FABDv2f64 +/* 60697 */ MCD_OPC_FilterValue, 7, 134, 102, 0, // Skip to: 86948 +/* 60702 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 60705 */ MCD_OPC_FilterValue, 0, 61, 0, 0, // Skip to: 60771 +/* 60710 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 60713 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 60742 +/* 60718 */ MCD_OPC_CheckPredicate, 5, 113, 102, 0, // Skip to: 86948 +/* 60723 */ MCD_OPC_CheckField, 21, 1, 1, 106, 102, 0, // Skip to: 86948 +/* 60730 */ MCD_OPC_CheckField, 12, 1, 0, 99, 102, 0, // Skip to: 86948 +/* 60737 */ MCD_OPC_Decode, 244, 20, 234, 1, // Opcode: PMULLv1i64 +/* 60742 */ MCD_OPC_FilterValue, 2, 89, 102, 0, // Skip to: 86948 +/* 60747 */ MCD_OPC_CheckPredicate, 5, 84, 102, 0, // Skip to: 86948 +/* 60752 */ MCD_OPC_CheckField, 21, 1, 1, 77, 102, 0, // Skip to: 86948 +/* 60759 */ MCD_OPC_CheckField, 12, 1, 0, 70, 102, 0, // Skip to: 86948 +/* 60766 */ MCD_OPC_Decode, 245, 20, 133, 2, // Opcode: PMULLv2i64 +/* 60771 */ MCD_OPC_FilterValue, 1, 93, 0, 0, // Skip to: 60869 +/* 60776 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 60779 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60801 +/* 60784 */ MCD_OPC_CheckPredicate, 11, 47, 102, 0, // Skip to: 86948 +/* 60789 */ MCD_OPC_CheckField, 29, 3, 3, 40, 102, 0, // Skip to: 86948 +/* 60796 */ MCD_OPC_Decode, 207, 6, 170, 2, // Opcode: FCADDv2f64 +/* 60801 */ MCD_OPC_FilterValue, 1, 30, 102, 0, // Skip to: 86948 +/* 60806 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 60809 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60831 +/* 60814 */ MCD_OPC_CheckPredicate, 3, 17, 102, 0, // Skip to: 86948 +/* 60819 */ MCD_OPC_CheckField, 29, 3, 3, 10, 102, 0, // Skip to: 86948 +/* 60826 */ MCD_OPC_Decode, 146, 7, 133, 2, // Opcode: FCMGTv2f64 +/* 60831 */ MCD_OPC_FilterValue, 1, 0, 102, 0, // Skip to: 86948 +/* 60836 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 60839 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60854 +/* 60844 */ MCD_OPC_CheckPredicate, 3, 243, 101, 0, // Skip to: 86948 +/* 60849 */ MCD_OPC_Decode, 173, 10, 133, 2, // Opcode: FMINv2f64 +/* 60854 */ MCD_OPC_FilterValue, 3, 233, 101, 0, // Skip to: 86948 +/* 60859 */ MCD_OPC_CheckPredicate, 3, 228, 101, 0, // Skip to: 86948 +/* 60864 */ MCD_OPC_Decode, 152, 10, 133, 2, // Opcode: FMINPv2f64 +/* 60869 */ MCD_OPC_FilterValue, 2, 24, 1, 0, // Skip to: 61154 +/* 60874 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 60877 */ MCD_OPC_FilterValue, 32, 63, 0, 0, // Skip to: 60945 +/* 60882 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 60885 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 60907 +/* 60890 */ MCD_OPC_CheckPredicate, 3, 197, 101, 0, // Skip to: 86948 +/* 60895 */ MCD_OPC_CheckField, 29, 3, 2, 190, 101, 0, // Skip to: 86948 +/* 60902 */ MCD_OPC_Decode, 186, 7, 138, 2, // Opcode: FCMLTv2i64rz +/* 60907 */ MCD_OPC_FilterValue, 1, 180, 101, 0, // Skip to: 86948 +/* 60912 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 60915 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 60930 +/* 60920 */ MCD_OPC_CheckPredicate, 3, 167, 101, 0, // Skip to: 86948 +/* 60925 */ MCD_OPC_Decode, 146, 6, 138, 2, // Opcode: FABSv2f64 +/* 60930 */ MCD_OPC_FilterValue, 3, 157, 101, 0, // Skip to: 86948 +/* 60935 */ MCD_OPC_CheckPredicate, 3, 152, 101, 0, // Skip to: 86948 +/* 60940 */ MCD_OPC_Decode, 171, 11, 138, 2, // Opcode: FNEGv2f64 +/* 60945 */ MCD_OPC_FilterValue, 33, 24, 0, 0, // Skip to: 60974 +/* 60950 */ MCD_OPC_CheckPredicate, 3, 137, 101, 0, // Skip to: 86948 +/* 60955 */ MCD_OPC_CheckField, 29, 3, 3, 130, 101, 0, // Skip to: 86948 +/* 60962 */ MCD_OPC_CheckField, 12, 1, 1, 123, 101, 0, // Skip to: 86948 +/* 60969 */ MCD_OPC_Decode, 205, 12, 138, 2, // Opcode: FSQRTv2f64 +/* 60974 */ MCD_OPC_FilterValue, 56, 123, 0, 0, // Skip to: 61102 +/* 60979 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 60982 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 61020 +/* 60987 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 60990 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61005 +/* 60995 */ MCD_OPC_CheckPredicate, 4, 92, 101, 0, // Skip to: 86948 +/* 61000 */ MCD_OPC_Decode, 187, 7, 239, 1, // Opcode: FCMLTv4i16rz +/* 61005 */ MCD_OPC_FilterValue, 1, 82, 101, 0, // Skip to: 86948 +/* 61010 */ MCD_OPC_CheckPredicate, 4, 77, 101, 0, // Skip to: 86948 +/* 61015 */ MCD_OPC_Decode, 147, 6, 239, 1, // Opcode: FABSv4f16 +/* 61020 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 61042 +/* 61025 */ MCD_OPC_CheckPredicate, 4, 62, 101, 0, // Skip to: 86948 +/* 61030 */ MCD_OPC_CheckField, 12, 1, 1, 55, 101, 0, // Skip to: 86948 +/* 61037 */ MCD_OPC_Decode, 172, 11, 239, 1, // Opcode: FNEGv4f16 +/* 61042 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 61080 +/* 61047 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 61050 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61065 +/* 61055 */ MCD_OPC_CheckPredicate, 4, 32, 101, 0, // Skip to: 86948 +/* 61060 */ MCD_OPC_Decode, 189, 7, 138, 2, // Opcode: FCMLTv8i16rz +/* 61065 */ MCD_OPC_FilterValue, 1, 22, 101, 0, // Skip to: 86948 +/* 61070 */ MCD_OPC_CheckPredicate, 4, 17, 101, 0, // Skip to: 86948 +/* 61075 */ MCD_OPC_Decode, 149, 6, 138, 2, // Opcode: FABSv8f16 +/* 61080 */ MCD_OPC_FilterValue, 3, 7, 101, 0, // Skip to: 86948 +/* 61085 */ MCD_OPC_CheckPredicate, 4, 2, 101, 0, // Skip to: 86948 +/* 61090 */ MCD_OPC_CheckField, 12, 1, 1, 251, 100, 0, // Skip to: 86948 +/* 61097 */ MCD_OPC_Decode, 174, 11, 138, 2, // Opcode: FNEGv8f16 +/* 61102 */ MCD_OPC_FilterValue, 57, 241, 100, 0, // Skip to: 86948 +/* 61107 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 61110 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 61132 +/* 61115 */ MCD_OPC_CheckPredicate, 4, 228, 100, 0, // Skip to: 86948 +/* 61120 */ MCD_OPC_CheckField, 12, 1, 1, 221, 100, 0, // Skip to: 86948 +/* 61127 */ MCD_OPC_Decode, 206, 12, 239, 1, // Opcode: FSQRTv4f16 +/* 61132 */ MCD_OPC_FilterValue, 3, 211, 100, 0, // Skip to: 86948 +/* 61137 */ MCD_OPC_CheckPredicate, 4, 206, 100, 0, // Skip to: 86948 +/* 61142 */ MCD_OPC_CheckField, 12, 1, 1, 199, 100, 0, // Skip to: 86948 +/* 61149 */ MCD_OPC_Decode, 208, 12, 138, 2, // Opcode: FSQRTv8f16 +/* 61154 */ MCD_OPC_FilterValue, 3, 189, 100, 0, // Skip to: 86948 +/* 61159 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 61162 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 61191 +/* 61167 */ MCD_OPC_CheckPredicate, 3, 176, 100, 0, // Skip to: 86948 +/* 61172 */ MCD_OPC_CheckField, 29, 3, 3, 169, 100, 0, // Skip to: 86948 +/* 61179 */ MCD_OPC_CheckField, 21, 1, 1, 162, 100, 0, // Skip to: 86948 +/* 61186 */ MCD_OPC_Decode, 168, 6, 133, 2, // Opcode: FACGTv2f64 +/* 61191 */ MCD_OPC_FilterValue, 1, 152, 100, 0, // Skip to: 86948 +/* 61196 */ MCD_OPC_CheckPredicate, 3, 147, 100, 0, // Skip to: 86948 +/* 61201 */ MCD_OPC_CheckField, 29, 3, 2, 140, 100, 0, // Skip to: 86948 +/* 61208 */ MCD_OPC_CheckField, 21, 1, 1, 133, 100, 0, // Skip to: 86948 +/* 61215 */ MCD_OPC_Decode, 191, 12, 133, 2, // Opcode: FRSQRTSv2f64 +/* 61220 */ MCD_OPC_FilterValue, 12, 94, 17, 0, // Skip to: 65671 +/* 61225 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 61228 */ MCD_OPC_FilterValue, 0, 66, 4, 0, // Skip to: 62323 +/* 61233 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 61236 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 61289 +/* 61241 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 61244 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61259 +/* 61249 */ MCD_OPC_CheckPredicate, 4, 94, 100, 0, // Skip to: 86948 +/* 61254 */ MCD_OPC_Decode, 192, 10, 174, 2, // Opcode: FMLAv4i16_indexed +/* 61259 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 61274 +/* 61264 */ MCD_OPC_CheckPredicate, 4, 79, 100, 0, // Skip to: 86948 +/* 61269 */ MCD_OPC_Decode, 211, 10, 174, 2, // Opcode: FMLSv4i16_indexed +/* 61274 */ MCD_OPC_FilterValue, 9, 69, 100, 0, // Skip to: 86948 +/* 61279 */ MCD_OPC_CheckPredicate, 4, 64, 100, 0, // Skip to: 86948 +/* 61284 */ MCD_OPC_Decode, 160, 11, 175, 2, // Opcode: FMULv4i16_indexed +/* 61289 */ MCD_OPC_FilterValue, 1, 54, 100, 0, // Skip to: 86948 +/* 61294 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 61297 */ MCD_OPC_FilterValue, 0, 41, 3, 0, // Skip to: 62111 +/* 61302 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 61305 */ MCD_OPC_FilterValue, 0, 143, 1, 0, // Skip to: 61709 +/* 61310 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 61313 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 61466 +/* 61318 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 61321 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 61428 +/* 61326 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 61329 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 61390 +/* 61334 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 61337 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61352 +/* 61342 */ MCD_OPC_CheckPredicate, 3, 1, 100, 0, // Skip to: 86948 +/* 61347 */ MCD_OPC_Decode, 236, 19, 176, 2, // Opcode: MOVIv2i32 +/* 61352 */ MCD_OPC_FilterValue, 1, 247, 99, 0, // Skip to: 86948 +/* 61357 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 61360 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61375 +/* 61365 */ MCD_OPC_CheckPredicate, 3, 234, 99, 0, // Skip to: 86948 +/* 61370 */ MCD_OPC_Decode, 242, 26, 177, 2, // Opcode: SSHRv8i8_shift +/* 61375 */ MCD_OPC_FilterValue, 1, 224, 99, 0, // Skip to: 86948 +/* 61380 */ MCD_OPC_CheckPredicate, 3, 219, 99, 0, // Skip to: 86948 +/* 61385 */ MCD_OPC_Decode, 212, 26, 177, 2, // Opcode: SRSHRv8i8_shift +/* 61390 */ MCD_OPC_FilterValue, 1, 209, 99, 0, // Skip to: 86948 +/* 61395 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 61398 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61413 +/* 61403 */ MCD_OPC_CheckPredicate, 3, 196, 99, 0, // Skip to: 86948 +/* 61408 */ MCD_OPC_Decode, 239, 26, 178, 2, // Opcode: SSHRv4i16_shift +/* 61413 */ MCD_OPC_FilterValue, 1, 186, 99, 0, // Skip to: 86948 +/* 61418 */ MCD_OPC_CheckPredicate, 3, 181, 99, 0, // Skip to: 86948 +/* 61423 */ MCD_OPC_Decode, 209, 26, 178, 2, // Opcode: SRSHRv4i16_shift +/* 61428 */ MCD_OPC_FilterValue, 1, 171, 99, 0, // Skip to: 86948 +/* 61433 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 61436 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61451 +/* 61441 */ MCD_OPC_CheckPredicate, 3, 158, 99, 0, // Skip to: 86948 +/* 61446 */ MCD_OPC_Decode, 237, 26, 179, 2, // Opcode: SSHRv2i32_shift +/* 61451 */ MCD_OPC_FilterValue, 1, 148, 99, 0, // Skip to: 86948 +/* 61456 */ MCD_OPC_CheckPredicate, 3, 143, 99, 0, // Skip to: 86948 +/* 61461 */ MCD_OPC_Decode, 207, 26, 179, 2, // Opcode: SRSHRv2i32_shift +/* 61466 */ MCD_OPC_FilterValue, 1, 133, 99, 0, // Skip to: 86948 +/* 61471 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 61474 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 61641 +/* 61479 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 61482 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 61573 +/* 61487 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 61490 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61505 +/* 61495 */ MCD_OPC_CheckPredicate, 3, 104, 99, 0, // Skip to: 86948 +/* 61500 */ MCD_OPC_Decode, 218, 20, 180, 2, // Opcode: ORRv2i32 +/* 61505 */ MCD_OPC_FilterValue, 1, 94, 99, 0, // Skip to: 86948 +/* 61510 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 61513 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61528 +/* 61518 */ MCD_OPC_CheckPredicate, 3, 81, 99, 0, // Skip to: 86948 +/* 61523 */ MCD_OPC_Decode, 250, 26, 181, 2, // Opcode: SSRAv8i8_shift +/* 61528 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61543 +/* 61533 */ MCD_OPC_CheckPredicate, 3, 66, 99, 0, // Skip to: 86948 +/* 61538 */ MCD_OPC_Decode, 220, 26, 181, 2, // Opcode: SRSRAv8i8_shift +/* 61543 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61558 +/* 61548 */ MCD_OPC_CheckPredicate, 3, 51, 99, 0, // Skip to: 86948 +/* 61553 */ MCD_OPC_Decode, 146, 23, 182, 2, // Opcode: SHLv8i8_shift +/* 61558 */ MCD_OPC_FilterValue, 3, 41, 99, 0, // Skip to: 86948 +/* 61563 */ MCD_OPC_CheckPredicate, 3, 36, 99, 0, // Skip to: 86948 +/* 61568 */ MCD_OPC_Decode, 255, 25, 182, 2, // Opcode: SQSHLv8i8_shift +/* 61573 */ MCD_OPC_FilterValue, 1, 26, 99, 0, // Skip to: 86948 +/* 61578 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 61581 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61596 +/* 61586 */ MCD_OPC_CheckPredicate, 3, 13, 99, 0, // Skip to: 86948 +/* 61591 */ MCD_OPC_Decode, 247, 26, 183, 2, // Opcode: SSRAv4i16_shift +/* 61596 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61611 +/* 61601 */ MCD_OPC_CheckPredicate, 3, 254, 98, 0, // Skip to: 86948 +/* 61606 */ MCD_OPC_Decode, 217, 26, 183, 2, // Opcode: SRSRAv4i16_shift +/* 61611 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61626 +/* 61616 */ MCD_OPC_CheckPredicate, 3, 239, 98, 0, // Skip to: 86948 +/* 61621 */ MCD_OPC_Decode, 143, 23, 184, 2, // Opcode: SHLv4i16_shift +/* 61626 */ MCD_OPC_FilterValue, 3, 229, 98, 0, // Skip to: 86948 +/* 61631 */ MCD_OPC_CheckPredicate, 3, 224, 98, 0, // Skip to: 86948 +/* 61636 */ MCD_OPC_Decode, 249, 25, 184, 2, // Opcode: SQSHLv4i16_shift +/* 61641 */ MCD_OPC_FilterValue, 1, 214, 98, 0, // Skip to: 86948 +/* 61646 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 61649 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61664 +/* 61654 */ MCD_OPC_CheckPredicate, 3, 201, 98, 0, // Skip to: 86948 +/* 61659 */ MCD_OPC_Decode, 245, 26, 185, 2, // Opcode: SSRAv2i32_shift +/* 61664 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 61679 +/* 61669 */ MCD_OPC_CheckPredicate, 3, 186, 98, 0, // Skip to: 86948 +/* 61674 */ MCD_OPC_Decode, 215, 26, 185, 2, // Opcode: SRSRAv2i32_shift +/* 61679 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 61694 +/* 61684 */ MCD_OPC_CheckPredicate, 3, 171, 98, 0, // Skip to: 86948 +/* 61689 */ MCD_OPC_Decode, 141, 23, 186, 2, // Opcode: SHLv2i32_shift +/* 61694 */ MCD_OPC_FilterValue, 3, 161, 98, 0, // Skip to: 86948 +/* 61699 */ MCD_OPC_CheckPredicate, 3, 156, 98, 0, // Skip to: 86948 +/* 61704 */ MCD_OPC_Decode, 245, 25, 186, 2, // Opcode: SQSHLv2i32_shift +/* 61709 */ MCD_OPC_FilterValue, 1, 146, 98, 0, // Skip to: 86948 +/* 61714 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 61717 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 61983 +/* 61722 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 61725 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 61878 +/* 61730 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 61733 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 61840 +/* 61738 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 61741 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 61802 +/* 61746 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 61749 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61764 +/* 61754 */ MCD_OPC_CheckPredicate, 3, 101, 98, 0, // Skip to: 86948 +/* 61759 */ MCD_OPC_Decode, 238, 19, 176, 2, // Opcode: MOVIv4i16 +/* 61764 */ MCD_OPC_FilterValue, 1, 91, 98, 0, // Skip to: 86948 +/* 61769 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 61772 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61787 +/* 61777 */ MCD_OPC_CheckPredicate, 3, 78, 98, 0, // Skip to: 86948 +/* 61782 */ MCD_OPC_Decode, 152, 23, 187, 2, // Opcode: SHRNv8i8_shift +/* 61787 */ MCD_OPC_FilterValue, 1, 68, 98, 0, // Skip to: 86948 +/* 61792 */ MCD_OPC_CheckPredicate, 3, 63, 98, 0, // Skip to: 86948 +/* 61797 */ MCD_OPC_Decode, 226, 26, 188, 2, // Opcode: SSHLLv8i8_shift +/* 61802 */ MCD_OPC_FilterValue, 1, 53, 98, 0, // Skip to: 86948 +/* 61807 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 61810 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61825 +/* 61815 */ MCD_OPC_CheckPredicate, 3, 40, 98, 0, // Skip to: 86948 +/* 61820 */ MCD_OPC_Decode, 149, 23, 189, 2, // Opcode: SHRNv4i16_shift +/* 61825 */ MCD_OPC_FilterValue, 1, 30, 98, 0, // Skip to: 86948 +/* 61830 */ MCD_OPC_CheckPredicate, 3, 25, 98, 0, // Skip to: 86948 +/* 61835 */ MCD_OPC_Decode, 223, 26, 190, 2, // Opcode: SSHLLv4i16_shift +/* 61840 */ MCD_OPC_FilterValue, 1, 15, 98, 0, // Skip to: 86948 +/* 61845 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 61848 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61863 +/* 61853 */ MCD_OPC_CheckPredicate, 3, 2, 98, 0, // Skip to: 86948 +/* 61858 */ MCD_OPC_Decode, 148, 23, 191, 2, // Opcode: SHRNv2i32_shift +/* 61863 */ MCD_OPC_FilterValue, 1, 248, 97, 0, // Skip to: 86948 +/* 61868 */ MCD_OPC_CheckPredicate, 3, 243, 97, 0, // Skip to: 86948 +/* 61873 */ MCD_OPC_Decode, 222, 26, 192, 2, // Opcode: SSHLLv2i32_shift +/* 61878 */ MCD_OPC_FilterValue, 1, 233, 97, 0, // Skip to: 86948 +/* 61883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 61886 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 61961 +/* 61891 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 61894 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 61939 +/* 61899 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 61902 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 61917 +/* 61907 */ MCD_OPC_CheckPredicate, 3, 204, 97, 0, // Skip to: 86948 +/* 61912 */ MCD_OPC_Decode, 219, 20, 180, 2, // Opcode: ORRv4i16 +/* 61917 */ MCD_OPC_FilterValue, 1, 194, 97, 0, // Skip to: 86948 +/* 61922 */ MCD_OPC_CheckPredicate, 3, 189, 97, 0, // Skip to: 86948 +/* 61927 */ MCD_OPC_CheckField, 13, 1, 0, 182, 97, 0, // Skip to: 86948 +/* 61934 */ MCD_OPC_Decode, 136, 26, 187, 2, // Opcode: SQSHRNv8i8_shift +/* 61939 */ MCD_OPC_FilterValue, 1, 172, 97, 0, // Skip to: 86948 +/* 61944 */ MCD_OPC_CheckPredicate, 3, 167, 97, 0, // Skip to: 86948 +/* 61949 */ MCD_OPC_CheckField, 13, 1, 0, 160, 97, 0, // Skip to: 86948 +/* 61956 */ MCD_OPC_Decode, 133, 26, 189, 2, // Opcode: SQSHRNv4i16_shift +/* 61961 */ MCD_OPC_FilterValue, 1, 150, 97, 0, // Skip to: 86948 +/* 61966 */ MCD_OPC_CheckPredicate, 3, 145, 97, 0, // Skip to: 86948 +/* 61971 */ MCD_OPC_CheckField, 13, 1, 0, 138, 97, 0, // Skip to: 86948 +/* 61978 */ MCD_OPC_Decode, 132, 26, 191, 2, // Opcode: SQSHRNv2i32_shift +/* 61983 */ MCD_OPC_FilterValue, 1, 128, 97, 0, // Skip to: 86948 +/* 61988 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 61991 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62013 +/* 61996 */ MCD_OPC_CheckPredicate, 3, 115, 97, 0, // Skip to: 86948 +/* 62001 */ MCD_OPC_CheckField, 19, 3, 0, 108, 97, 0, // Skip to: 86948 +/* 62008 */ MCD_OPC_Decode, 237, 19, 176, 2, // Opcode: MOVIv2s_msl +/* 62013 */ MCD_OPC_FilterValue, 1, 98, 97, 0, // Skip to: 86948 +/* 62018 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 62021 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 62089 +/* 62026 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62029 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62074 +/* 62034 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62037 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62059 +/* 62042 */ MCD_OPC_CheckPredicate, 3, 69, 97, 0, // Skip to: 86948 +/* 62047 */ MCD_OPC_CheckField, 19, 1, 0, 62, 97, 0, // Skip to: 86948 +/* 62054 */ MCD_OPC_Decode, 241, 19, 176, 2, // Opcode: MOVIv8b_ns +/* 62059 */ MCD_OPC_FilterValue, 1, 52, 97, 0, // Skip to: 86948 +/* 62064 */ MCD_OPC_CheckPredicate, 4, 47, 97, 0, // Skip to: 86948 +/* 62069 */ MCD_OPC_Decode, 215, 22, 178, 2, // Opcode: SCVTFv4i16_shift +/* 62074 */ MCD_OPC_FilterValue, 1, 37, 97, 0, // Skip to: 86948 +/* 62079 */ MCD_OPC_CheckPredicate, 3, 32, 97, 0, // Skip to: 86948 +/* 62084 */ MCD_OPC_Decode, 211, 22, 179, 2, // Opcode: SCVTFv2i32_shift +/* 62089 */ MCD_OPC_FilterValue, 1, 22, 97, 0, // Skip to: 86948 +/* 62094 */ MCD_OPC_CheckPredicate, 3, 17, 97, 0, // Skip to: 86948 +/* 62099 */ MCD_OPC_CheckField, 19, 3, 0, 10, 97, 0, // Skip to: 86948 +/* 62106 */ MCD_OPC_Decode, 234, 10, 176, 2, // Opcode: FMOVv2f32_ns +/* 62111 */ MCD_OPC_FilterValue, 1, 0, 97, 0, // Skip to: 86948 +/* 62116 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 62119 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 62187 +/* 62124 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62127 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62172 +/* 62132 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62135 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62157 +/* 62140 */ MCD_OPC_CheckPredicate, 3, 227, 96, 0, // Skip to: 86948 +/* 62145 */ MCD_OPC_CheckField, 19, 1, 1, 220, 96, 0, // Skip to: 86948 +/* 62152 */ MCD_OPC_Decode, 239, 21, 187, 2, // Opcode: RSHRNv8i8_shift +/* 62157 */ MCD_OPC_FilterValue, 1, 210, 96, 0, // Skip to: 86948 +/* 62162 */ MCD_OPC_CheckPredicate, 3, 205, 96, 0, // Skip to: 86948 +/* 62167 */ MCD_OPC_Decode, 236, 21, 189, 2, // Opcode: RSHRNv4i16_shift +/* 62172 */ MCD_OPC_FilterValue, 1, 195, 96, 0, // Skip to: 86948 +/* 62177 */ MCD_OPC_CheckPredicate, 3, 190, 96, 0, // Skip to: 86948 +/* 62182 */ MCD_OPC_Decode, 235, 21, 191, 2, // Opcode: RSHRNv2i32_shift +/* 62187 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 62255 +/* 62192 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62195 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62240 +/* 62200 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62203 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62225 +/* 62208 */ MCD_OPC_CheckPredicate, 3, 159, 96, 0, // Skip to: 86948 +/* 62213 */ MCD_OPC_CheckField, 19, 1, 1, 152, 96, 0, // Skip to: 86948 +/* 62220 */ MCD_OPC_Decode, 213, 25, 187, 2, // Opcode: SQRSHRNv8i8_shift +/* 62225 */ MCD_OPC_FilterValue, 1, 142, 96, 0, // Skip to: 86948 +/* 62230 */ MCD_OPC_CheckPredicate, 3, 137, 96, 0, // Skip to: 86948 +/* 62235 */ MCD_OPC_Decode, 210, 25, 189, 2, // Opcode: SQRSHRNv4i16_shift +/* 62240 */ MCD_OPC_FilterValue, 1, 127, 96, 0, // Skip to: 86948 +/* 62245 */ MCD_OPC_CheckPredicate, 3, 122, 96, 0, // Skip to: 86948 +/* 62250 */ MCD_OPC_Decode, 209, 25, 191, 2, // Opcode: SQRSHRNv2i32_shift +/* 62255 */ MCD_OPC_FilterValue, 15, 112, 96, 0, // Skip to: 86948 +/* 62260 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62263 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 62308 +/* 62268 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62271 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62293 +/* 62276 */ MCD_OPC_CheckPredicate, 4, 91, 96, 0, // Skip to: 86948 +/* 62281 */ MCD_OPC_CheckField, 19, 1, 0, 84, 96, 0, // Skip to: 86948 +/* 62288 */ MCD_OPC_Decode, 236, 10, 176, 2, // Opcode: FMOVv4f16_ns +/* 62293 */ MCD_OPC_FilterValue, 1, 74, 96, 0, // Skip to: 86948 +/* 62298 */ MCD_OPC_CheckPredicate, 4, 69, 96, 0, // Skip to: 86948 +/* 62303 */ MCD_OPC_Decode, 249, 8, 178, 2, // Opcode: FCVTZSv4i16_shift +/* 62308 */ MCD_OPC_FilterValue, 1, 59, 96, 0, // Skip to: 86948 +/* 62313 */ MCD_OPC_CheckPredicate, 3, 54, 96, 0, // Skip to: 86948 +/* 62318 */ MCD_OPC_Decode, 245, 8, 179, 2, // Opcode: FCVTZSv2i32_shift +/* 62323 */ MCD_OPC_FilterValue, 1, 93, 4, 0, // Skip to: 63445 +/* 62328 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 62331 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 62353 +/* 62336 */ MCD_OPC_CheckPredicate, 4, 31, 96, 0, // Skip to: 86948 +/* 62341 */ MCD_OPC_CheckField, 12, 4, 9, 24, 96, 0, // Skip to: 86948 +/* 62348 */ MCD_OPC_Decode, 135, 11, 175, 2, // Opcode: FMULXv4i16_indexed +/* 62353 */ MCD_OPC_FilterValue, 1, 14, 96, 0, // Skip to: 86948 +/* 62358 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 62361 */ MCD_OPC_FilterValue, 0, 122, 3, 0, // Skip to: 63256 +/* 62366 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 62369 */ MCD_OPC_FilterValue, 0, 233, 1, 0, // Skip to: 62863 +/* 62374 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 62377 */ MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 62620 +/* 62382 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62385 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 62552 +/* 62390 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62393 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 62484 +/* 62398 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 62401 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62416 +/* 62406 */ MCD_OPC_CheckPredicate, 3, 217, 95, 0, // Skip to: 86948 +/* 62411 */ MCD_OPC_Decode, 167, 20, 176, 2, // Opcode: MVNIv2i32 +/* 62416 */ MCD_OPC_FilterValue, 1, 207, 95, 0, // Skip to: 86948 +/* 62421 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 62424 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62439 +/* 62429 */ MCD_OPC_CheckPredicate, 3, 194, 95, 0, // Skip to: 86948 +/* 62434 */ MCD_OPC_Decode, 144, 34, 177, 2, // Opcode: USHRv8i8_shift +/* 62439 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62454 +/* 62444 */ MCD_OPC_CheckPredicate, 3, 179, 95, 0, // Skip to: 86948 +/* 62449 */ MCD_OPC_Decode, 240, 33, 177, 2, // Opcode: URSHRv8i8_shift +/* 62454 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62469 +/* 62459 */ MCD_OPC_CheckPredicate, 3, 164, 95, 0, // Skip to: 86948 +/* 62464 */ MCD_OPC_Decode, 196, 26, 181, 2, // Opcode: SRIv8i8_shift +/* 62469 */ MCD_OPC_FilterValue, 3, 154, 95, 0, // Skip to: 86948 +/* 62474 */ MCD_OPC_CheckPredicate, 3, 149, 95, 0, // Skip to: 86948 +/* 62479 */ MCD_OPC_Decode, 233, 25, 182, 2, // Opcode: SQSHLUv8i8_shift +/* 62484 */ MCD_OPC_FilterValue, 1, 139, 95, 0, // Skip to: 86948 +/* 62489 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 62492 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62507 +/* 62497 */ MCD_OPC_CheckPredicate, 3, 126, 95, 0, // Skip to: 86948 +/* 62502 */ MCD_OPC_Decode, 141, 34, 178, 2, // Opcode: USHRv4i16_shift +/* 62507 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62522 +/* 62512 */ MCD_OPC_CheckPredicate, 3, 111, 95, 0, // Skip to: 86948 +/* 62517 */ MCD_OPC_Decode, 237, 33, 178, 2, // Opcode: URSHRv4i16_shift +/* 62522 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62537 +/* 62527 */ MCD_OPC_CheckPredicate, 3, 96, 95, 0, // Skip to: 86948 +/* 62532 */ MCD_OPC_Decode, 193, 26, 183, 2, // Opcode: SRIv4i16_shift +/* 62537 */ MCD_OPC_FilterValue, 3, 86, 95, 0, // Skip to: 86948 +/* 62542 */ MCD_OPC_CheckPredicate, 3, 81, 95, 0, // Skip to: 86948 +/* 62547 */ MCD_OPC_Decode, 230, 25, 184, 2, // Opcode: SQSHLUv4i16_shift +/* 62552 */ MCD_OPC_FilterValue, 1, 71, 95, 0, // Skip to: 86948 +/* 62557 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 62560 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62575 +/* 62565 */ MCD_OPC_CheckPredicate, 3, 58, 95, 0, // Skip to: 86948 +/* 62570 */ MCD_OPC_Decode, 139, 34, 179, 2, // Opcode: USHRv2i32_shift +/* 62575 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62590 +/* 62580 */ MCD_OPC_CheckPredicate, 3, 43, 95, 0, // Skip to: 86948 +/* 62585 */ MCD_OPC_Decode, 235, 33, 179, 2, // Opcode: URSHRv2i32_shift +/* 62590 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62605 +/* 62595 */ MCD_OPC_CheckPredicate, 3, 28, 95, 0, // Skip to: 86948 +/* 62600 */ MCD_OPC_Decode, 191, 26, 185, 2, // Opcode: SRIv2i32_shift +/* 62605 */ MCD_OPC_FilterValue, 3, 18, 95, 0, // Skip to: 86948 +/* 62610 */ MCD_OPC_CheckPredicate, 3, 13, 95, 0, // Skip to: 86948 +/* 62615 */ MCD_OPC_Decode, 228, 25, 186, 2, // Opcode: SQSHLUv2i32_shift +/* 62620 */ MCD_OPC_FilterValue, 1, 3, 95, 0, // Skip to: 86948 +/* 62625 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62628 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 62795 +/* 62633 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62636 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 62727 +/* 62641 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 62644 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62659 +/* 62649 */ MCD_OPC_CheckPredicate, 3, 230, 94, 0, // Skip to: 86948 +/* 62654 */ MCD_OPC_Decode, 188, 2, 180, 2, // Opcode: BICv2i32 +/* 62659 */ MCD_OPC_FilterValue, 1, 220, 94, 0, // Skip to: 86948 +/* 62664 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 62667 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62682 +/* 62672 */ MCD_OPC_CheckPredicate, 3, 207, 94, 0, // Skip to: 86948 +/* 62677 */ MCD_OPC_Decode, 163, 34, 181, 2, // Opcode: USRAv8i8_shift +/* 62682 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62697 +/* 62687 */ MCD_OPC_CheckPredicate, 3, 192, 94, 0, // Skip to: 86948 +/* 62692 */ MCD_OPC_Decode, 250, 33, 181, 2, // Opcode: URSRAv8i8_shift +/* 62697 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62712 +/* 62702 */ MCD_OPC_CheckPredicate, 3, 177, 94, 0, // Skip to: 86948 +/* 62707 */ MCD_OPC_Decode, 166, 23, 193, 2, // Opcode: SLIv8i8_shift +/* 62712 */ MCD_OPC_FilterValue, 3, 167, 94, 0, // Skip to: 86948 +/* 62717 */ MCD_OPC_CheckPredicate, 3, 162, 94, 0, // Skip to: 86948 +/* 62722 */ MCD_OPC_Decode, 179, 33, 182, 2, // Opcode: UQSHLv8i8_shift +/* 62727 */ MCD_OPC_FilterValue, 1, 152, 94, 0, // Skip to: 86948 +/* 62732 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 62735 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62750 +/* 62740 */ MCD_OPC_CheckPredicate, 3, 139, 94, 0, // Skip to: 86948 +/* 62745 */ MCD_OPC_Decode, 160, 34, 183, 2, // Opcode: USRAv4i16_shift +/* 62750 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62765 +/* 62755 */ MCD_OPC_CheckPredicate, 3, 124, 94, 0, // Skip to: 86948 +/* 62760 */ MCD_OPC_Decode, 247, 33, 183, 2, // Opcode: URSRAv4i16_shift +/* 62765 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62780 +/* 62770 */ MCD_OPC_CheckPredicate, 3, 109, 94, 0, // Skip to: 86948 +/* 62775 */ MCD_OPC_Decode, 163, 23, 194, 2, // Opcode: SLIv4i16_shift +/* 62780 */ MCD_OPC_FilterValue, 3, 99, 94, 0, // Skip to: 86948 +/* 62785 */ MCD_OPC_CheckPredicate, 3, 94, 94, 0, // Skip to: 86948 +/* 62790 */ MCD_OPC_Decode, 173, 33, 184, 2, // Opcode: UQSHLv4i16_shift +/* 62795 */ MCD_OPC_FilterValue, 1, 84, 94, 0, // Skip to: 86948 +/* 62800 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 62803 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62818 +/* 62808 */ MCD_OPC_CheckPredicate, 3, 71, 94, 0, // Skip to: 86948 +/* 62813 */ MCD_OPC_Decode, 158, 34, 185, 2, // Opcode: USRAv2i32_shift +/* 62818 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 62833 +/* 62823 */ MCD_OPC_CheckPredicate, 3, 56, 94, 0, // Skip to: 86948 +/* 62828 */ MCD_OPC_Decode, 245, 33, 185, 2, // Opcode: URSRAv2i32_shift +/* 62833 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 62848 +/* 62838 */ MCD_OPC_CheckPredicate, 3, 41, 94, 0, // Skip to: 86948 +/* 62843 */ MCD_OPC_Decode, 161, 23, 195, 2, // Opcode: SLIv2i32_shift +/* 62848 */ MCD_OPC_FilterValue, 3, 31, 94, 0, // Skip to: 86948 +/* 62853 */ MCD_OPC_CheckPredicate, 3, 26, 94, 0, // Skip to: 86948 +/* 62858 */ MCD_OPC_Decode, 169, 33, 186, 2, // Opcode: UQSHLv2i32_shift +/* 62863 */ MCD_OPC_FilterValue, 1, 16, 94, 0, // Skip to: 86948 +/* 62868 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 62871 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 63137 +/* 62876 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 62879 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 63032 +/* 62884 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 62887 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 62994 +/* 62892 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 62895 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 62956 +/* 62900 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 62903 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62918 +/* 62908 */ MCD_OPC_CheckPredicate, 3, 227, 93, 0, // Skip to: 86948 +/* 62913 */ MCD_OPC_Decode, 169, 20, 176, 2, // Opcode: MVNIv4i16 +/* 62918 */ MCD_OPC_FilterValue, 1, 217, 93, 0, // Skip to: 86948 +/* 62923 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 62926 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62941 +/* 62931 */ MCD_OPC_CheckPredicate, 3, 204, 93, 0, // Skip to: 86948 +/* 62936 */ MCD_OPC_Decode, 145, 26, 187, 2, // Opcode: SQSHRUNv8i8_shift +/* 62941 */ MCD_OPC_FilterValue, 1, 194, 93, 0, // Skip to: 86948 +/* 62946 */ MCD_OPC_CheckPredicate, 3, 189, 93, 0, // Skip to: 86948 +/* 62951 */ MCD_OPC_Decode, 128, 34, 188, 2, // Opcode: USHLLv8i8_shift +/* 62956 */ MCD_OPC_FilterValue, 1, 179, 93, 0, // Skip to: 86948 +/* 62961 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 62964 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 62979 +/* 62969 */ MCD_OPC_CheckPredicate, 3, 166, 93, 0, // Skip to: 86948 +/* 62974 */ MCD_OPC_Decode, 142, 26, 189, 2, // Opcode: SQSHRUNv4i16_shift +/* 62979 */ MCD_OPC_FilterValue, 1, 156, 93, 0, // Skip to: 86948 +/* 62984 */ MCD_OPC_CheckPredicate, 3, 151, 93, 0, // Skip to: 86948 +/* 62989 */ MCD_OPC_Decode, 253, 33, 190, 2, // Opcode: USHLLv4i16_shift +/* 62994 */ MCD_OPC_FilterValue, 1, 141, 93, 0, // Skip to: 86948 +/* 62999 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 63002 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63017 +/* 63007 */ MCD_OPC_CheckPredicate, 3, 128, 93, 0, // Skip to: 86948 +/* 63012 */ MCD_OPC_Decode, 141, 26, 191, 2, // Opcode: SQSHRUNv2i32_shift +/* 63017 */ MCD_OPC_FilterValue, 1, 118, 93, 0, // Skip to: 86948 +/* 63022 */ MCD_OPC_CheckPredicate, 3, 113, 93, 0, // Skip to: 86948 +/* 63027 */ MCD_OPC_Decode, 252, 33, 192, 2, // Opcode: USHLLv2i32_shift +/* 63032 */ MCD_OPC_FilterValue, 1, 103, 93, 0, // Skip to: 86948 +/* 63037 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63040 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 63115 +/* 63045 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63048 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63093 +/* 63053 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 63056 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63071 +/* 63061 */ MCD_OPC_CheckPredicate, 3, 74, 93, 0, // Skip to: 86948 +/* 63066 */ MCD_OPC_Decode, 189, 2, 180, 2, // Opcode: BICv4i16 +/* 63071 */ MCD_OPC_FilterValue, 1, 64, 93, 0, // Skip to: 86948 +/* 63076 */ MCD_OPC_CheckPredicate, 3, 59, 93, 0, // Skip to: 86948 +/* 63081 */ MCD_OPC_CheckField, 13, 1, 0, 52, 93, 0, // Skip to: 86948 +/* 63088 */ MCD_OPC_Decode, 188, 33, 187, 2, // Opcode: UQSHRNv8i8_shift +/* 63093 */ MCD_OPC_FilterValue, 1, 42, 93, 0, // Skip to: 86948 +/* 63098 */ MCD_OPC_CheckPredicate, 3, 37, 93, 0, // Skip to: 86948 +/* 63103 */ MCD_OPC_CheckField, 13, 1, 0, 30, 93, 0, // Skip to: 86948 +/* 63110 */ MCD_OPC_Decode, 185, 33, 189, 2, // Opcode: UQSHRNv4i16_shift +/* 63115 */ MCD_OPC_FilterValue, 1, 20, 93, 0, // Skip to: 86948 +/* 63120 */ MCD_OPC_CheckPredicate, 3, 15, 93, 0, // Skip to: 86948 +/* 63125 */ MCD_OPC_CheckField, 13, 1, 0, 8, 93, 0, // Skip to: 86948 +/* 63132 */ MCD_OPC_Decode, 184, 33, 191, 2, // Opcode: UQSHRNv2i32_shift +/* 63137 */ MCD_OPC_FilterValue, 1, 254, 92, 0, // Skip to: 86948 +/* 63142 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 63145 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63167 +/* 63150 */ MCD_OPC_CheckPredicate, 3, 241, 92, 0, // Skip to: 86948 +/* 63155 */ MCD_OPC_CheckField, 19, 3, 0, 234, 92, 0, // Skip to: 86948 +/* 63162 */ MCD_OPC_Decode, 168, 20, 176, 2, // Opcode: MVNIv2s_msl +/* 63167 */ MCD_OPC_FilterValue, 1, 224, 92, 0, // Skip to: 86948 +/* 63172 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63175 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 63234 +/* 63180 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63183 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 63212 +/* 63188 */ MCD_OPC_CheckPredicate, 3, 203, 92, 0, // Skip to: 86948 +/* 63193 */ MCD_OPC_CheckField, 19, 1, 0, 196, 92, 0, // Skip to: 86948 +/* 63200 */ MCD_OPC_CheckField, 12, 1, 0, 189, 92, 0, // Skip to: 86948 +/* 63207 */ MCD_OPC_Decode, 233, 19, 176, 2, // Opcode: MOVID +/* 63212 */ MCD_OPC_FilterValue, 1, 179, 92, 0, // Skip to: 86948 +/* 63217 */ MCD_OPC_CheckPredicate, 4, 174, 92, 0, // Skip to: 86948 +/* 63222 */ MCD_OPC_CheckField, 12, 1, 0, 167, 92, 0, // Skip to: 86948 +/* 63229 */ MCD_OPC_Decode, 202, 31, 178, 2, // Opcode: UCVTFv4i16_shift +/* 63234 */ MCD_OPC_FilterValue, 1, 157, 92, 0, // Skip to: 86948 +/* 63239 */ MCD_OPC_CheckPredicate, 3, 152, 92, 0, // Skip to: 86948 +/* 63244 */ MCD_OPC_CheckField, 12, 1, 0, 145, 92, 0, // Skip to: 86948 +/* 63251 */ MCD_OPC_Decode, 198, 31, 179, 2, // Opcode: UCVTFv2i32_shift +/* 63256 */ MCD_OPC_FilterValue, 1, 135, 92, 0, // Skip to: 86948 +/* 63261 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 63264 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 63332 +/* 63269 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63272 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63317 +/* 63277 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63280 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63302 +/* 63285 */ MCD_OPC_CheckPredicate, 3, 106, 92, 0, // Skip to: 86948 +/* 63290 */ MCD_OPC_CheckField, 19, 1, 1, 99, 92, 0, // Skip to: 86948 +/* 63297 */ MCD_OPC_Decode, 222, 25, 187, 2, // Opcode: SQRSHRUNv8i8_shift +/* 63302 */ MCD_OPC_FilterValue, 1, 89, 92, 0, // Skip to: 86948 +/* 63307 */ MCD_OPC_CheckPredicate, 3, 84, 92, 0, // Skip to: 86948 +/* 63312 */ MCD_OPC_Decode, 219, 25, 189, 2, // Opcode: SQRSHRUNv4i16_shift +/* 63317 */ MCD_OPC_FilterValue, 1, 74, 92, 0, // Skip to: 86948 +/* 63322 */ MCD_OPC_CheckPredicate, 3, 69, 92, 0, // Skip to: 86948 +/* 63327 */ MCD_OPC_Decode, 218, 25, 191, 2, // Opcode: SQRSHRUNv2i32_shift +/* 63332 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 63400 +/* 63337 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63340 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 63385 +/* 63345 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63348 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63370 +/* 63353 */ MCD_OPC_CheckPredicate, 3, 38, 92, 0, // Skip to: 86948 +/* 63358 */ MCD_OPC_CheckField, 19, 1, 1, 31, 92, 0, // Skip to: 86948 +/* 63365 */ MCD_OPC_Decode, 157, 33, 187, 2, // Opcode: UQRSHRNv8i8_shift +/* 63370 */ MCD_OPC_FilterValue, 1, 21, 92, 0, // Skip to: 86948 +/* 63375 */ MCD_OPC_CheckPredicate, 3, 16, 92, 0, // Skip to: 86948 +/* 63380 */ MCD_OPC_Decode, 154, 33, 189, 2, // Opcode: UQRSHRNv4i16_shift +/* 63385 */ MCD_OPC_FilterValue, 1, 6, 92, 0, // Skip to: 86948 +/* 63390 */ MCD_OPC_CheckPredicate, 3, 1, 92, 0, // Skip to: 86948 +/* 63395 */ MCD_OPC_Decode, 153, 33, 191, 2, // Opcode: UQRSHRNv2i32_shift +/* 63400 */ MCD_OPC_FilterValue, 15, 247, 91, 0, // Skip to: 86948 +/* 63405 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 63430 +/* 63413 */ MCD_OPC_CheckPredicate, 4, 234, 91, 0, // Skip to: 86948 +/* 63418 */ MCD_OPC_CheckField, 20, 1, 1, 227, 91, 0, // Skip to: 86948 +/* 63425 */ MCD_OPC_Decode, 156, 9, 178, 2, // Opcode: FCVTZUv4i16_shift +/* 63430 */ MCD_OPC_FilterValue, 1, 217, 91, 0, // Skip to: 86948 +/* 63435 */ MCD_OPC_CheckPredicate, 3, 212, 91, 0, // Skip to: 86948 +/* 63440 */ MCD_OPC_Decode, 152, 9, 179, 2, // Opcode: FCVTZUv2i32_shift +/* 63445 */ MCD_OPC_FilterValue, 2, 66, 4, 0, // Skip to: 64540 +/* 63450 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 63453 */ MCD_OPC_FilterValue, 0, 48, 0, 0, // Skip to: 63506 +/* 63458 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 63461 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63476 +/* 63466 */ MCD_OPC_CheckPredicate, 4, 181, 91, 0, // Skip to: 86948 +/* 63471 */ MCD_OPC_Decode, 195, 10, 196, 2, // Opcode: FMLAv8i16_indexed +/* 63476 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 63491 +/* 63481 */ MCD_OPC_CheckPredicate, 4, 166, 91, 0, // Skip to: 86948 +/* 63486 */ MCD_OPC_Decode, 214, 10, 196, 2, // Opcode: FMLSv8i16_indexed +/* 63491 */ MCD_OPC_FilterValue, 9, 156, 91, 0, // Skip to: 86948 +/* 63496 */ MCD_OPC_CheckPredicate, 4, 151, 91, 0, // Skip to: 86948 +/* 63501 */ MCD_OPC_Decode, 163, 11, 197, 2, // Opcode: FMULv8i16_indexed +/* 63506 */ MCD_OPC_FilterValue, 1, 141, 91, 0, // Skip to: 86948 +/* 63511 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 63514 */ MCD_OPC_FilterValue, 0, 41, 3, 0, // Skip to: 64328 +/* 63519 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 63522 */ MCD_OPC_FilterValue, 0, 143, 1, 0, // Skip to: 63926 +/* 63527 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 63530 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 63683 +/* 63535 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63538 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 63645 +/* 63543 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63546 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 63607 +/* 63551 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 63554 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63569 +/* 63559 */ MCD_OPC_CheckPredicate, 3, 88, 91, 0, // Skip to: 86948 +/* 63564 */ MCD_OPC_Decode, 239, 19, 176, 2, // Opcode: MOVIv4i32 +/* 63569 */ MCD_OPC_FilterValue, 1, 78, 91, 0, // Skip to: 86948 +/* 63574 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 63577 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63592 +/* 63582 */ MCD_OPC_CheckPredicate, 3, 65, 91, 0, // Skip to: 86948 +/* 63587 */ MCD_OPC_Decode, 236, 26, 198, 2, // Opcode: SSHRv16i8_shift +/* 63592 */ MCD_OPC_FilterValue, 1, 55, 91, 0, // Skip to: 86948 +/* 63597 */ MCD_OPC_CheckPredicate, 3, 50, 91, 0, // Skip to: 86948 +/* 63602 */ MCD_OPC_Decode, 206, 26, 198, 2, // Opcode: SRSHRv16i8_shift +/* 63607 */ MCD_OPC_FilterValue, 1, 40, 91, 0, // Skip to: 86948 +/* 63612 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 63615 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63630 +/* 63620 */ MCD_OPC_CheckPredicate, 3, 27, 91, 0, // Skip to: 86948 +/* 63625 */ MCD_OPC_Decode, 241, 26, 199, 2, // Opcode: SSHRv8i16_shift +/* 63630 */ MCD_OPC_FilterValue, 1, 17, 91, 0, // Skip to: 86948 +/* 63635 */ MCD_OPC_CheckPredicate, 3, 12, 91, 0, // Skip to: 86948 +/* 63640 */ MCD_OPC_Decode, 211, 26, 199, 2, // Opcode: SRSHRv8i16_shift +/* 63645 */ MCD_OPC_FilterValue, 1, 2, 91, 0, // Skip to: 86948 +/* 63650 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 63653 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63668 +/* 63658 */ MCD_OPC_CheckPredicate, 3, 245, 90, 0, // Skip to: 86948 +/* 63663 */ MCD_OPC_Decode, 240, 26, 200, 2, // Opcode: SSHRv4i32_shift +/* 63668 */ MCD_OPC_FilterValue, 1, 235, 90, 0, // Skip to: 86948 +/* 63673 */ MCD_OPC_CheckPredicate, 3, 230, 90, 0, // Skip to: 86948 +/* 63678 */ MCD_OPC_Decode, 210, 26, 200, 2, // Opcode: SRSHRv4i32_shift +/* 63683 */ MCD_OPC_FilterValue, 1, 220, 90, 0, // Skip to: 86948 +/* 63688 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63691 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 63858 +/* 63696 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63699 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 63790 +/* 63704 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 63707 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63722 +/* 63712 */ MCD_OPC_CheckPredicate, 3, 191, 90, 0, // Skip to: 86948 +/* 63717 */ MCD_OPC_Decode, 220, 20, 180, 2, // Opcode: ORRv4i32 +/* 63722 */ MCD_OPC_FilterValue, 1, 181, 90, 0, // Skip to: 86948 +/* 63727 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 63730 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63745 +/* 63735 */ MCD_OPC_CheckPredicate, 3, 168, 90, 0, // Skip to: 86948 +/* 63740 */ MCD_OPC_Decode, 244, 26, 201, 2, // Opcode: SSRAv16i8_shift +/* 63745 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63760 +/* 63750 */ MCD_OPC_CheckPredicate, 3, 153, 90, 0, // Skip to: 86948 +/* 63755 */ MCD_OPC_Decode, 214, 26, 201, 2, // Opcode: SRSRAv16i8_shift +/* 63760 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63775 +/* 63765 */ MCD_OPC_CheckPredicate, 3, 138, 90, 0, // Skip to: 86948 +/* 63770 */ MCD_OPC_Decode, 140, 23, 202, 2, // Opcode: SHLv16i8_shift +/* 63775 */ MCD_OPC_FilterValue, 3, 128, 90, 0, // Skip to: 86948 +/* 63780 */ MCD_OPC_CheckPredicate, 3, 123, 90, 0, // Skip to: 86948 +/* 63785 */ MCD_OPC_Decode, 239, 25, 202, 2, // Opcode: SQSHLv16i8_shift +/* 63790 */ MCD_OPC_FilterValue, 1, 113, 90, 0, // Skip to: 86948 +/* 63795 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 63798 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63813 +/* 63803 */ MCD_OPC_CheckPredicate, 3, 100, 90, 0, // Skip to: 86948 +/* 63808 */ MCD_OPC_Decode, 249, 26, 203, 2, // Opcode: SSRAv8i16_shift +/* 63813 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63828 +/* 63818 */ MCD_OPC_CheckPredicate, 3, 85, 90, 0, // Skip to: 86948 +/* 63823 */ MCD_OPC_Decode, 219, 26, 203, 2, // Opcode: SRSRAv8i16_shift +/* 63828 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63843 +/* 63833 */ MCD_OPC_CheckPredicate, 3, 70, 90, 0, // Skip to: 86948 +/* 63838 */ MCD_OPC_Decode, 145, 23, 204, 2, // Opcode: SHLv8i16_shift +/* 63843 */ MCD_OPC_FilterValue, 3, 60, 90, 0, // Skip to: 86948 +/* 63848 */ MCD_OPC_CheckPredicate, 3, 55, 90, 0, // Skip to: 86948 +/* 63853 */ MCD_OPC_Decode, 253, 25, 204, 2, // Opcode: SQSHLv8i16_shift +/* 63858 */ MCD_OPC_FilterValue, 1, 45, 90, 0, // Skip to: 86948 +/* 63863 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 63866 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63881 +/* 63871 */ MCD_OPC_CheckPredicate, 3, 32, 90, 0, // Skip to: 86948 +/* 63876 */ MCD_OPC_Decode, 248, 26, 205, 2, // Opcode: SSRAv4i32_shift +/* 63881 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 63896 +/* 63886 */ MCD_OPC_CheckPredicate, 3, 17, 90, 0, // Skip to: 86948 +/* 63891 */ MCD_OPC_Decode, 218, 26, 205, 2, // Opcode: SRSRAv4i32_shift +/* 63896 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 63911 +/* 63901 */ MCD_OPC_CheckPredicate, 3, 2, 90, 0, // Skip to: 86948 +/* 63906 */ MCD_OPC_Decode, 144, 23, 206, 2, // Opcode: SHLv4i32_shift +/* 63911 */ MCD_OPC_FilterValue, 3, 248, 89, 0, // Skip to: 86948 +/* 63916 */ MCD_OPC_CheckPredicate, 3, 243, 89, 0, // Skip to: 86948 +/* 63921 */ MCD_OPC_Decode, 251, 25, 206, 2, // Opcode: SQSHLv4i32_shift +/* 63926 */ MCD_OPC_FilterValue, 1, 233, 89, 0, // Skip to: 86948 +/* 63931 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 63934 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 64200 +/* 63939 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 63942 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 64095 +/* 63947 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 63950 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 64057 +/* 63955 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 63958 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 64019 +/* 63963 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 63966 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 63981 +/* 63971 */ MCD_OPC_CheckPredicate, 3, 188, 89, 0, // Skip to: 86948 +/* 63976 */ MCD_OPC_Decode, 242, 19, 176, 2, // Opcode: MOVIv8i16 +/* 63981 */ MCD_OPC_FilterValue, 1, 178, 89, 0, // Skip to: 86948 +/* 63986 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 63989 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64004 +/* 63994 */ MCD_OPC_CheckPredicate, 3, 165, 89, 0, // Skip to: 86948 +/* 63999 */ MCD_OPC_Decode, 147, 23, 207, 2, // Opcode: SHRNv16i8_shift +/* 64004 */ MCD_OPC_FilterValue, 1, 155, 89, 0, // Skip to: 86948 +/* 64009 */ MCD_OPC_CheckPredicate, 3, 150, 89, 0, // Skip to: 86948 +/* 64014 */ MCD_OPC_Decode, 221, 26, 202, 2, // Opcode: SSHLLv16i8_shift +/* 64019 */ MCD_OPC_FilterValue, 1, 140, 89, 0, // Skip to: 86948 +/* 64024 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 64027 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64042 +/* 64032 */ MCD_OPC_CheckPredicate, 3, 127, 89, 0, // Skip to: 86948 +/* 64037 */ MCD_OPC_Decode, 151, 23, 208, 2, // Opcode: SHRNv8i16_shift +/* 64042 */ MCD_OPC_FilterValue, 1, 117, 89, 0, // Skip to: 86948 +/* 64047 */ MCD_OPC_CheckPredicate, 3, 112, 89, 0, // Skip to: 86948 +/* 64052 */ MCD_OPC_Decode, 225, 26, 204, 2, // Opcode: SSHLLv8i16_shift +/* 64057 */ MCD_OPC_FilterValue, 1, 102, 89, 0, // Skip to: 86948 +/* 64062 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 64065 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64080 +/* 64070 */ MCD_OPC_CheckPredicate, 3, 89, 89, 0, // Skip to: 86948 +/* 64075 */ MCD_OPC_Decode, 150, 23, 209, 2, // Opcode: SHRNv4i32_shift +/* 64080 */ MCD_OPC_FilterValue, 1, 79, 89, 0, // Skip to: 86948 +/* 64085 */ MCD_OPC_CheckPredicate, 3, 74, 89, 0, // Skip to: 86948 +/* 64090 */ MCD_OPC_Decode, 224, 26, 206, 2, // Opcode: SSHLLv4i32_shift +/* 64095 */ MCD_OPC_FilterValue, 1, 64, 89, 0, // Skip to: 86948 +/* 64100 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64103 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 64178 +/* 64108 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64111 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64156 +/* 64116 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 64119 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64134 +/* 64124 */ MCD_OPC_CheckPredicate, 3, 35, 89, 0, // Skip to: 86948 +/* 64129 */ MCD_OPC_Decode, 221, 20, 180, 2, // Opcode: ORRv8i16 +/* 64134 */ MCD_OPC_FilterValue, 1, 25, 89, 0, // Skip to: 86948 +/* 64139 */ MCD_OPC_CheckPredicate, 3, 20, 89, 0, // Skip to: 86948 +/* 64144 */ MCD_OPC_CheckField, 13, 1, 0, 13, 89, 0, // Skip to: 86948 +/* 64151 */ MCD_OPC_Decode, 131, 26, 207, 2, // Opcode: SQSHRNv16i8_shift +/* 64156 */ MCD_OPC_FilterValue, 1, 3, 89, 0, // Skip to: 86948 +/* 64161 */ MCD_OPC_CheckPredicate, 3, 254, 88, 0, // Skip to: 86948 +/* 64166 */ MCD_OPC_CheckField, 13, 1, 0, 247, 88, 0, // Skip to: 86948 +/* 64173 */ MCD_OPC_Decode, 135, 26, 208, 2, // Opcode: SQSHRNv8i16_shift +/* 64178 */ MCD_OPC_FilterValue, 1, 237, 88, 0, // Skip to: 86948 +/* 64183 */ MCD_OPC_CheckPredicate, 3, 232, 88, 0, // Skip to: 86948 +/* 64188 */ MCD_OPC_CheckField, 13, 1, 0, 225, 88, 0, // Skip to: 86948 +/* 64195 */ MCD_OPC_Decode, 134, 26, 209, 2, // Opcode: SQSHRNv4i32_shift +/* 64200 */ MCD_OPC_FilterValue, 1, 215, 88, 0, // Skip to: 86948 +/* 64205 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 64208 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64230 +/* 64213 */ MCD_OPC_CheckPredicate, 3, 202, 88, 0, // Skip to: 86948 +/* 64218 */ MCD_OPC_CheckField, 19, 3, 0, 195, 88, 0, // Skip to: 86948 +/* 64225 */ MCD_OPC_Decode, 240, 19, 176, 2, // Opcode: MOVIv4s_msl +/* 64230 */ MCD_OPC_FilterValue, 1, 185, 88, 0, // Skip to: 86948 +/* 64235 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 64238 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 64306 +/* 64243 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64246 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64291 +/* 64251 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64254 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64276 +/* 64259 */ MCD_OPC_CheckPredicate, 3, 156, 88, 0, // Skip to: 86948 +/* 64264 */ MCD_OPC_CheckField, 19, 1, 0, 149, 88, 0, // Skip to: 86948 +/* 64271 */ MCD_OPC_Decode, 234, 19, 176, 2, // Opcode: MOVIv16b_ns +/* 64276 */ MCD_OPC_FilterValue, 1, 139, 88, 0, // Skip to: 86948 +/* 64281 */ MCD_OPC_CheckPredicate, 4, 134, 88, 0, // Skip to: 86948 +/* 64286 */ MCD_OPC_Decode, 218, 22, 199, 2, // Opcode: SCVTFv8i16_shift +/* 64291 */ MCD_OPC_FilterValue, 1, 124, 88, 0, // Skip to: 86948 +/* 64296 */ MCD_OPC_CheckPredicate, 3, 119, 88, 0, // Skip to: 86948 +/* 64301 */ MCD_OPC_Decode, 216, 22, 200, 2, // Opcode: SCVTFv4i32_shift +/* 64306 */ MCD_OPC_FilterValue, 1, 109, 88, 0, // Skip to: 86948 +/* 64311 */ MCD_OPC_CheckPredicate, 3, 104, 88, 0, // Skip to: 86948 +/* 64316 */ MCD_OPC_CheckField, 19, 3, 0, 97, 88, 0, // Skip to: 86948 +/* 64323 */ MCD_OPC_Decode, 237, 10, 176, 2, // Opcode: FMOVv4f32_ns +/* 64328 */ MCD_OPC_FilterValue, 1, 87, 88, 0, // Skip to: 86948 +/* 64333 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 64336 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 64404 +/* 64341 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64344 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64389 +/* 64349 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64352 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64374 +/* 64357 */ MCD_OPC_CheckPredicate, 3, 58, 88, 0, // Skip to: 86948 +/* 64362 */ MCD_OPC_CheckField, 19, 1, 1, 51, 88, 0, // Skip to: 86948 +/* 64369 */ MCD_OPC_Decode, 234, 21, 207, 2, // Opcode: RSHRNv16i8_shift +/* 64374 */ MCD_OPC_FilterValue, 1, 41, 88, 0, // Skip to: 86948 +/* 64379 */ MCD_OPC_CheckPredicate, 3, 36, 88, 0, // Skip to: 86948 +/* 64384 */ MCD_OPC_Decode, 238, 21, 208, 2, // Opcode: RSHRNv8i16_shift +/* 64389 */ MCD_OPC_FilterValue, 1, 26, 88, 0, // Skip to: 86948 +/* 64394 */ MCD_OPC_CheckPredicate, 3, 21, 88, 0, // Skip to: 86948 +/* 64399 */ MCD_OPC_Decode, 237, 21, 209, 2, // Opcode: RSHRNv4i32_shift +/* 64404 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 64472 +/* 64409 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64412 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64457 +/* 64417 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64420 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64442 +/* 64425 */ MCD_OPC_CheckPredicate, 3, 246, 87, 0, // Skip to: 86948 +/* 64430 */ MCD_OPC_CheckField, 19, 1, 1, 239, 87, 0, // Skip to: 86948 +/* 64437 */ MCD_OPC_Decode, 208, 25, 207, 2, // Opcode: SQRSHRNv16i8_shift +/* 64442 */ MCD_OPC_FilterValue, 1, 229, 87, 0, // Skip to: 86948 +/* 64447 */ MCD_OPC_CheckPredicate, 3, 224, 87, 0, // Skip to: 86948 +/* 64452 */ MCD_OPC_Decode, 212, 25, 208, 2, // Opcode: SQRSHRNv8i16_shift +/* 64457 */ MCD_OPC_FilterValue, 1, 214, 87, 0, // Skip to: 86948 +/* 64462 */ MCD_OPC_CheckPredicate, 3, 209, 87, 0, // Skip to: 86948 +/* 64467 */ MCD_OPC_Decode, 211, 25, 209, 2, // Opcode: SQRSHRNv4i32_shift +/* 64472 */ MCD_OPC_FilterValue, 15, 199, 87, 0, // Skip to: 86948 +/* 64477 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64480 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 64525 +/* 64485 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64488 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64510 +/* 64493 */ MCD_OPC_CheckPredicate, 4, 178, 87, 0, // Skip to: 86948 +/* 64498 */ MCD_OPC_CheckField, 19, 1, 0, 171, 87, 0, // Skip to: 86948 +/* 64505 */ MCD_OPC_Decode, 238, 10, 176, 2, // Opcode: FMOVv8f16_ns +/* 64510 */ MCD_OPC_FilterValue, 1, 161, 87, 0, // Skip to: 86948 +/* 64515 */ MCD_OPC_CheckPredicate, 4, 156, 87, 0, // Skip to: 86948 +/* 64520 */ MCD_OPC_Decode, 252, 8, 199, 2, // Opcode: FCVTZSv8i16_shift +/* 64525 */ MCD_OPC_FilterValue, 1, 146, 87, 0, // Skip to: 86948 +/* 64530 */ MCD_OPC_CheckPredicate, 3, 141, 87, 0, // Skip to: 86948 +/* 64535 */ MCD_OPC_Decode, 250, 8, 200, 2, // Opcode: FCVTZSv4i32_shift +/* 64540 */ MCD_OPC_FilterValue, 3, 131, 87, 0, // Skip to: 86948 +/* 64545 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 64548 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 64570 +/* 64553 */ MCD_OPC_CheckPredicate, 4, 118, 87, 0, // Skip to: 86948 +/* 64558 */ MCD_OPC_CheckField, 12, 4, 9, 111, 87, 0, // Skip to: 86948 +/* 64565 */ MCD_OPC_Decode, 138, 11, 197, 2, // Opcode: FMULXv8i16_indexed +/* 64570 */ MCD_OPC_FilterValue, 1, 101, 87, 0, // Skip to: 86948 +/* 64575 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 64578 */ MCD_OPC_FilterValue, 0, 131, 3, 0, // Skip to: 65482 +/* 64583 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 64586 */ MCD_OPC_FilterValue, 0, 233, 1, 0, // Skip to: 65080 +/* 64591 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 64594 */ MCD_OPC_FilterValue, 0, 238, 0, 0, // Skip to: 64837 +/* 64599 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64602 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 64769 +/* 64607 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64610 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 64701 +/* 64615 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 64618 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64633 +/* 64623 */ MCD_OPC_CheckPredicate, 3, 48, 87, 0, // Skip to: 86948 +/* 64628 */ MCD_OPC_Decode, 170, 20, 176, 2, // Opcode: MVNIv4i32 +/* 64633 */ MCD_OPC_FilterValue, 1, 38, 87, 0, // Skip to: 86948 +/* 64638 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 64641 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64656 +/* 64646 */ MCD_OPC_CheckPredicate, 3, 25, 87, 0, // Skip to: 86948 +/* 64651 */ MCD_OPC_Decode, 138, 34, 198, 2, // Opcode: USHRv16i8_shift +/* 64656 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64671 +/* 64661 */ MCD_OPC_CheckPredicate, 3, 10, 87, 0, // Skip to: 86948 +/* 64666 */ MCD_OPC_Decode, 234, 33, 198, 2, // Opcode: URSHRv16i8_shift +/* 64671 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64686 +/* 64676 */ MCD_OPC_CheckPredicate, 3, 251, 86, 0, // Skip to: 86948 +/* 64681 */ MCD_OPC_Decode, 190, 26, 201, 2, // Opcode: SRIv16i8_shift +/* 64686 */ MCD_OPC_FilterValue, 3, 241, 86, 0, // Skip to: 86948 +/* 64691 */ MCD_OPC_CheckPredicate, 3, 236, 86, 0, // Skip to: 86948 +/* 64696 */ MCD_OPC_Decode, 227, 25, 202, 2, // Opcode: SQSHLUv16i8_shift +/* 64701 */ MCD_OPC_FilterValue, 1, 226, 86, 0, // Skip to: 86948 +/* 64706 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 64709 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64724 +/* 64714 */ MCD_OPC_CheckPredicate, 3, 213, 86, 0, // Skip to: 86948 +/* 64719 */ MCD_OPC_Decode, 143, 34, 199, 2, // Opcode: USHRv8i16_shift +/* 64724 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64739 +/* 64729 */ MCD_OPC_CheckPredicate, 3, 198, 86, 0, // Skip to: 86948 +/* 64734 */ MCD_OPC_Decode, 239, 33, 199, 2, // Opcode: URSHRv8i16_shift +/* 64739 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64754 +/* 64744 */ MCD_OPC_CheckPredicate, 3, 183, 86, 0, // Skip to: 86948 +/* 64749 */ MCD_OPC_Decode, 195, 26, 203, 2, // Opcode: SRIv8i16_shift +/* 64754 */ MCD_OPC_FilterValue, 3, 173, 86, 0, // Skip to: 86948 +/* 64759 */ MCD_OPC_CheckPredicate, 3, 168, 86, 0, // Skip to: 86948 +/* 64764 */ MCD_OPC_Decode, 232, 25, 204, 2, // Opcode: SQSHLUv8i16_shift +/* 64769 */ MCD_OPC_FilterValue, 1, 158, 86, 0, // Skip to: 86948 +/* 64774 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 64777 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64792 +/* 64782 */ MCD_OPC_CheckPredicate, 3, 145, 86, 0, // Skip to: 86948 +/* 64787 */ MCD_OPC_Decode, 142, 34, 200, 2, // Opcode: USHRv4i32_shift +/* 64792 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64807 +/* 64797 */ MCD_OPC_CheckPredicate, 3, 130, 86, 0, // Skip to: 86948 +/* 64802 */ MCD_OPC_Decode, 238, 33, 200, 2, // Opcode: URSHRv4i32_shift +/* 64807 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64822 +/* 64812 */ MCD_OPC_CheckPredicate, 3, 115, 86, 0, // Skip to: 86948 +/* 64817 */ MCD_OPC_Decode, 194, 26, 205, 2, // Opcode: SRIv4i32_shift +/* 64822 */ MCD_OPC_FilterValue, 3, 105, 86, 0, // Skip to: 86948 +/* 64827 */ MCD_OPC_CheckPredicate, 3, 100, 86, 0, // Skip to: 86948 +/* 64832 */ MCD_OPC_Decode, 231, 25, 206, 2, // Opcode: SQSHLUv4i32_shift +/* 64837 */ MCD_OPC_FilterValue, 1, 90, 86, 0, // Skip to: 86948 +/* 64842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 64845 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 65012 +/* 64850 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 64853 */ MCD_OPC_FilterValue, 0, 86, 0, 0, // Skip to: 64944 +/* 64858 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 64861 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64876 +/* 64866 */ MCD_OPC_CheckPredicate, 3, 61, 86, 0, // Skip to: 86948 +/* 64871 */ MCD_OPC_Decode, 190, 2, 180, 2, // Opcode: BICv4i32 +/* 64876 */ MCD_OPC_FilterValue, 1, 51, 86, 0, // Skip to: 86948 +/* 64881 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 64884 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64899 +/* 64889 */ MCD_OPC_CheckPredicate, 3, 38, 86, 0, // Skip to: 86948 +/* 64894 */ MCD_OPC_Decode, 157, 34, 201, 2, // Opcode: USRAv16i8_shift +/* 64899 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64914 +/* 64904 */ MCD_OPC_CheckPredicate, 3, 23, 86, 0, // Skip to: 86948 +/* 64909 */ MCD_OPC_Decode, 244, 33, 201, 2, // Opcode: URSRAv16i8_shift +/* 64914 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64929 +/* 64919 */ MCD_OPC_CheckPredicate, 3, 8, 86, 0, // Skip to: 86948 +/* 64924 */ MCD_OPC_Decode, 160, 23, 210, 2, // Opcode: SLIv16i8_shift +/* 64929 */ MCD_OPC_FilterValue, 3, 254, 85, 0, // Skip to: 86948 +/* 64934 */ MCD_OPC_CheckPredicate, 3, 249, 85, 0, // Skip to: 86948 +/* 64939 */ MCD_OPC_Decode, 163, 33, 202, 2, // Opcode: UQSHLv16i8_shift +/* 64944 */ MCD_OPC_FilterValue, 1, 239, 85, 0, // Skip to: 86948 +/* 64949 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 64952 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 64967 +/* 64957 */ MCD_OPC_CheckPredicate, 3, 226, 85, 0, // Skip to: 86948 +/* 64962 */ MCD_OPC_Decode, 162, 34, 203, 2, // Opcode: USRAv8i16_shift +/* 64967 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 64982 +/* 64972 */ MCD_OPC_CheckPredicate, 3, 211, 85, 0, // Skip to: 86948 +/* 64977 */ MCD_OPC_Decode, 249, 33, 203, 2, // Opcode: URSRAv8i16_shift +/* 64982 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 64997 +/* 64987 */ MCD_OPC_CheckPredicate, 3, 196, 85, 0, // Skip to: 86948 +/* 64992 */ MCD_OPC_Decode, 165, 23, 211, 2, // Opcode: SLIv8i16_shift +/* 64997 */ MCD_OPC_FilterValue, 3, 186, 85, 0, // Skip to: 86948 +/* 65002 */ MCD_OPC_CheckPredicate, 3, 181, 85, 0, // Skip to: 86948 +/* 65007 */ MCD_OPC_Decode, 177, 33, 204, 2, // Opcode: UQSHLv8i16_shift +/* 65012 */ MCD_OPC_FilterValue, 1, 171, 85, 0, // Skip to: 86948 +/* 65017 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 65020 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65035 +/* 65025 */ MCD_OPC_CheckPredicate, 3, 158, 85, 0, // Skip to: 86948 +/* 65030 */ MCD_OPC_Decode, 161, 34, 205, 2, // Opcode: USRAv4i32_shift +/* 65035 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 65050 +/* 65040 */ MCD_OPC_CheckPredicate, 3, 143, 85, 0, // Skip to: 86948 +/* 65045 */ MCD_OPC_Decode, 248, 33, 205, 2, // Opcode: URSRAv4i32_shift +/* 65050 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 65065 +/* 65055 */ MCD_OPC_CheckPredicate, 3, 128, 85, 0, // Skip to: 86948 +/* 65060 */ MCD_OPC_Decode, 164, 23, 212, 2, // Opcode: SLIv4i32_shift +/* 65065 */ MCD_OPC_FilterValue, 3, 118, 85, 0, // Skip to: 86948 +/* 65070 */ MCD_OPC_CheckPredicate, 3, 113, 85, 0, // Skip to: 86948 +/* 65075 */ MCD_OPC_Decode, 175, 33, 206, 2, // Opcode: UQSHLv4i32_shift +/* 65080 */ MCD_OPC_FilterValue, 1, 103, 85, 0, // Skip to: 86948 +/* 65085 */ MCD_OPC_ExtractField, 14, 1, // Inst{14} ... +/* 65088 */ MCD_OPC_FilterValue, 0, 5, 1, 0, // Skip to: 65354 +/* 65093 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 65096 */ MCD_OPC_FilterValue, 0, 148, 0, 0, // Skip to: 65249 +/* 65101 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 65104 */ MCD_OPC_FilterValue, 0, 102, 0, 0, // Skip to: 65211 +/* 65109 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 65112 */ MCD_OPC_FilterValue, 0, 56, 0, 0, // Skip to: 65173 +/* 65117 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 65120 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65135 +/* 65125 */ MCD_OPC_CheckPredicate, 3, 58, 85, 0, // Skip to: 86948 +/* 65130 */ MCD_OPC_Decode, 172, 20, 176, 2, // Opcode: MVNIv8i16 +/* 65135 */ MCD_OPC_FilterValue, 1, 48, 85, 0, // Skip to: 86948 +/* 65140 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 65143 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65158 +/* 65148 */ MCD_OPC_CheckPredicate, 3, 35, 85, 0, // Skip to: 86948 +/* 65153 */ MCD_OPC_Decode, 140, 26, 207, 2, // Opcode: SQSHRUNv16i8_shift +/* 65158 */ MCD_OPC_FilterValue, 1, 25, 85, 0, // Skip to: 86948 +/* 65163 */ MCD_OPC_CheckPredicate, 3, 20, 85, 0, // Skip to: 86948 +/* 65168 */ MCD_OPC_Decode, 251, 33, 202, 2, // Opcode: USHLLv16i8_shift +/* 65173 */ MCD_OPC_FilterValue, 1, 10, 85, 0, // Skip to: 86948 +/* 65178 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 65181 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65196 +/* 65186 */ MCD_OPC_CheckPredicate, 3, 253, 84, 0, // Skip to: 86948 +/* 65191 */ MCD_OPC_Decode, 144, 26, 208, 2, // Opcode: SQSHRUNv8i16_shift +/* 65196 */ MCD_OPC_FilterValue, 1, 243, 84, 0, // Skip to: 86948 +/* 65201 */ MCD_OPC_CheckPredicate, 3, 238, 84, 0, // Skip to: 86948 +/* 65206 */ MCD_OPC_Decode, 255, 33, 204, 2, // Opcode: USHLLv8i16_shift +/* 65211 */ MCD_OPC_FilterValue, 1, 228, 84, 0, // Skip to: 86948 +/* 65216 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 65219 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65234 +/* 65224 */ MCD_OPC_CheckPredicate, 3, 215, 84, 0, // Skip to: 86948 +/* 65229 */ MCD_OPC_Decode, 143, 26, 209, 2, // Opcode: SQSHRUNv4i32_shift +/* 65234 */ MCD_OPC_FilterValue, 1, 205, 84, 0, // Skip to: 86948 +/* 65239 */ MCD_OPC_CheckPredicate, 3, 200, 84, 0, // Skip to: 86948 +/* 65244 */ MCD_OPC_Decode, 254, 33, 206, 2, // Opcode: USHLLv4i32_shift +/* 65249 */ MCD_OPC_FilterValue, 1, 190, 84, 0, // Skip to: 86948 +/* 65254 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 65257 */ MCD_OPC_FilterValue, 0, 70, 0, 0, // Skip to: 65332 +/* 65262 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 65265 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65310 +/* 65270 */ MCD_OPC_ExtractField, 19, 1, // Inst{19} ... +/* 65273 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 65288 +/* 65278 */ MCD_OPC_CheckPredicate, 3, 161, 84, 0, // Skip to: 86948 +/* 65283 */ MCD_OPC_Decode, 191, 2, 180, 2, // Opcode: BICv8i16 +/* 65288 */ MCD_OPC_FilterValue, 1, 151, 84, 0, // Skip to: 86948 +/* 65293 */ MCD_OPC_CheckPredicate, 3, 146, 84, 0, // Skip to: 86948 +/* 65298 */ MCD_OPC_CheckField, 13, 1, 0, 139, 84, 0, // Skip to: 86948 +/* 65305 */ MCD_OPC_Decode, 183, 33, 207, 2, // Opcode: UQSHRNv16i8_shift +/* 65310 */ MCD_OPC_FilterValue, 1, 129, 84, 0, // Skip to: 86948 +/* 65315 */ MCD_OPC_CheckPredicate, 3, 124, 84, 0, // Skip to: 86948 +/* 65320 */ MCD_OPC_CheckField, 13, 1, 0, 117, 84, 0, // Skip to: 86948 +/* 65327 */ MCD_OPC_Decode, 187, 33, 208, 2, // Opcode: UQSHRNv8i16_shift +/* 65332 */ MCD_OPC_FilterValue, 1, 107, 84, 0, // Skip to: 86948 +/* 65337 */ MCD_OPC_CheckPredicate, 3, 102, 84, 0, // Skip to: 86948 +/* 65342 */ MCD_OPC_CheckField, 13, 1, 0, 95, 84, 0, // Skip to: 86948 +/* 65349 */ MCD_OPC_Decode, 186, 33, 209, 2, // Opcode: UQSHRNv4i32_shift +/* 65354 */ MCD_OPC_FilterValue, 1, 85, 84, 0, // Skip to: 86948 +/* 65359 */ MCD_OPC_ExtractField, 13, 1, // Inst{13} ... +/* 65362 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65384 +/* 65367 */ MCD_OPC_CheckPredicate, 3, 72, 84, 0, // Skip to: 86948 +/* 65372 */ MCD_OPC_CheckField, 19, 3, 0, 65, 84, 0, // Skip to: 86948 +/* 65379 */ MCD_OPC_Decode, 171, 20, 176, 2, // Opcode: MVNIv4s_msl +/* 65384 */ MCD_OPC_FilterValue, 1, 55, 84, 0, // Skip to: 86948 +/* 65389 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 65392 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 65460 +/* 65397 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 65400 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65445 +/* 65405 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 65408 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65430 +/* 65413 */ MCD_OPC_CheckPredicate, 3, 26, 84, 0, // Skip to: 86948 +/* 65418 */ MCD_OPC_CheckField, 19, 1, 0, 19, 84, 0, // Skip to: 86948 +/* 65425 */ MCD_OPC_Decode, 235, 19, 176, 2, // Opcode: MOVIv2d_ns +/* 65430 */ MCD_OPC_FilterValue, 1, 9, 84, 0, // Skip to: 86948 +/* 65435 */ MCD_OPC_CheckPredicate, 4, 4, 84, 0, // Skip to: 86948 +/* 65440 */ MCD_OPC_Decode, 205, 31, 199, 2, // Opcode: UCVTFv8i16_shift +/* 65445 */ MCD_OPC_FilterValue, 1, 250, 83, 0, // Skip to: 86948 +/* 65450 */ MCD_OPC_CheckPredicate, 3, 245, 83, 0, // Skip to: 86948 +/* 65455 */ MCD_OPC_Decode, 203, 31, 200, 2, // Opcode: UCVTFv4i32_shift +/* 65460 */ MCD_OPC_FilterValue, 1, 235, 83, 0, // Skip to: 86948 +/* 65465 */ MCD_OPC_CheckPredicate, 3, 230, 83, 0, // Skip to: 86948 +/* 65470 */ MCD_OPC_CheckField, 19, 3, 0, 223, 83, 0, // Skip to: 86948 +/* 65477 */ MCD_OPC_Decode, 235, 10, 176, 2, // Opcode: FMOVv2f64_ns +/* 65482 */ MCD_OPC_FilterValue, 1, 213, 83, 0, // Skip to: 86948 +/* 65487 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 65490 */ MCD_OPC_FilterValue, 8, 63, 0, 0, // Skip to: 65558 +/* 65495 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 65498 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65543 +/* 65503 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 65506 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65528 +/* 65511 */ MCD_OPC_CheckPredicate, 3, 184, 83, 0, // Skip to: 86948 +/* 65516 */ MCD_OPC_CheckField, 19, 1, 1, 177, 83, 0, // Skip to: 86948 +/* 65523 */ MCD_OPC_Decode, 217, 25, 207, 2, // Opcode: SQRSHRUNv16i8_shift +/* 65528 */ MCD_OPC_FilterValue, 1, 167, 83, 0, // Skip to: 86948 +/* 65533 */ MCD_OPC_CheckPredicate, 3, 162, 83, 0, // Skip to: 86948 +/* 65538 */ MCD_OPC_Decode, 221, 25, 208, 2, // Opcode: SQRSHRUNv8i16_shift +/* 65543 */ MCD_OPC_FilterValue, 1, 152, 83, 0, // Skip to: 86948 +/* 65548 */ MCD_OPC_CheckPredicate, 3, 147, 83, 0, // Skip to: 86948 +/* 65553 */ MCD_OPC_Decode, 220, 25, 209, 2, // Opcode: SQRSHRUNv4i32_shift +/* 65558 */ MCD_OPC_FilterValue, 9, 63, 0, 0, // Skip to: 65626 +/* 65563 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 65566 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 65611 +/* 65571 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 65574 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65596 +/* 65579 */ MCD_OPC_CheckPredicate, 3, 116, 83, 0, // Skip to: 86948 +/* 65584 */ MCD_OPC_CheckField, 19, 1, 1, 109, 83, 0, // Skip to: 86948 +/* 65591 */ MCD_OPC_Decode, 152, 33, 207, 2, // Opcode: UQRSHRNv16i8_shift +/* 65596 */ MCD_OPC_FilterValue, 1, 99, 83, 0, // Skip to: 86948 +/* 65601 */ MCD_OPC_CheckPredicate, 3, 94, 83, 0, // Skip to: 86948 +/* 65606 */ MCD_OPC_Decode, 156, 33, 208, 2, // Opcode: UQRSHRNv8i16_shift +/* 65611 */ MCD_OPC_FilterValue, 1, 84, 83, 0, // Skip to: 86948 +/* 65616 */ MCD_OPC_CheckPredicate, 3, 79, 83, 0, // Skip to: 86948 +/* 65621 */ MCD_OPC_Decode, 155, 33, 209, 2, // Opcode: UQRSHRNv4i32_shift +/* 65626 */ MCD_OPC_FilterValue, 15, 69, 83, 0, // Skip to: 86948 +/* 65631 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 65634 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65656 +/* 65639 */ MCD_OPC_CheckPredicate, 4, 56, 83, 0, // Skip to: 86948 +/* 65644 */ MCD_OPC_CheckField, 20, 1, 1, 49, 83, 0, // Skip to: 86948 +/* 65651 */ MCD_OPC_Decode, 159, 9, 199, 2, // Opcode: FCVTZUv8i16_shift +/* 65656 */ MCD_OPC_FilterValue, 1, 39, 83, 0, // Skip to: 86948 +/* 65661 */ MCD_OPC_CheckPredicate, 3, 34, 83, 0, // Skip to: 86948 +/* 65666 */ MCD_OPC_Decode, 157, 9, 200, 2, // Opcode: FCVTZUv4i32_shift +/* 65671 */ MCD_OPC_FilterValue, 13, 96, 4, 0, // Skip to: 66796 +/* 65676 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 65679 */ MCD_OPC_FilterValue, 0, 201, 0, 0, // Skip to: 65885 +/* 65684 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 65687 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 65709 +/* 65692 */ MCD_OPC_CheckPredicate, 3, 3, 83, 0, // Skip to: 86948 +/* 65697 */ MCD_OPC_CheckField, 10, 1, 0, 252, 82, 0, // Skip to: 86948 +/* 65704 */ MCD_OPC_Decode, 239, 23, 213, 2, // Opcode: SMLALv4i16_indexed +/* 65709 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 65731 +/* 65714 */ MCD_OPC_CheckPredicate, 3, 237, 82, 0, // Skip to: 86948 +/* 65719 */ MCD_OPC_CheckField, 10, 1, 0, 230, 82, 0, // Skip to: 86948 +/* 65726 */ MCD_OPC_Decode, 211, 24, 213, 2, // Opcode: SQDMLALv4i16_indexed +/* 65731 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 65753 +/* 65736 */ MCD_OPC_CheckPredicate, 3, 215, 82, 0, // Skip to: 86948 +/* 65741 */ MCD_OPC_CheckField, 10, 1, 0, 208, 82, 0, // Skip to: 86948 +/* 65748 */ MCD_OPC_Decode, 249, 23, 213, 2, // Opcode: SMLSLv4i16_indexed +/* 65753 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 65775 +/* 65758 */ MCD_OPC_CheckPredicate, 3, 193, 82, 0, // Skip to: 86948 +/* 65763 */ MCD_OPC_CheckField, 10, 1, 0, 186, 82, 0, // Skip to: 86948 +/* 65770 */ MCD_OPC_Decode, 223, 24, 213, 2, // Opcode: SQDMLSLv4i16_indexed +/* 65775 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 65797 +/* 65780 */ MCD_OPC_CheckPredicate, 3, 171, 82, 0, // Skip to: 86948 +/* 65785 */ MCD_OPC_CheckField, 10, 1, 0, 164, 82, 0, // Skip to: 86948 +/* 65792 */ MCD_OPC_Decode, 161, 20, 175, 2, // Opcode: MULv4i16_indexed +/* 65797 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 65819 +/* 65802 */ MCD_OPC_CheckPredicate, 3, 149, 82, 0, // Skip to: 86948 +/* 65807 */ MCD_OPC_CheckField, 10, 1, 0, 142, 82, 0, // Skip to: 86948 +/* 65814 */ MCD_OPC_Decode, 142, 24, 214, 2, // Opcode: SMULLv4i16_indexed +/* 65819 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 65841 +/* 65824 */ MCD_OPC_CheckPredicate, 3, 127, 82, 0, // Skip to: 86948 +/* 65829 */ MCD_OPC_CheckField, 10, 1, 0, 120, 82, 0, // Skip to: 86948 +/* 65836 */ MCD_OPC_Decode, 247, 24, 214, 2, // Opcode: SQDMULLv4i16_indexed +/* 65841 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 65863 +/* 65846 */ MCD_OPC_CheckPredicate, 3, 105, 82, 0, // Skip to: 86948 +/* 65851 */ MCD_OPC_CheckField, 10, 1, 0, 98, 82, 0, // Skip to: 86948 +/* 65858 */ MCD_OPC_Decode, 236, 24, 175, 2, // Opcode: SQDMULHv4i16_indexed +/* 65863 */ MCD_OPC_FilterValue, 13, 88, 82, 0, // Skip to: 86948 +/* 65868 */ MCD_OPC_CheckPredicate, 3, 83, 82, 0, // Skip to: 86948 +/* 65873 */ MCD_OPC_CheckField, 10, 1, 0, 76, 82, 0, // Skip to: 86948 +/* 65880 */ MCD_OPC_Decode, 189, 25, 175, 2, // Opcode: SQRDMULHv4i16_indexed +/* 65885 */ MCD_OPC_FilterValue, 1, 203, 0, 0, // Skip to: 66093 +/* 65890 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 65893 */ MCD_OPC_FilterValue, 0, 113, 0, 0, // Skip to: 66011 +/* 65898 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 65901 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 65923 +/* 65906 */ MCD_OPC_CheckPredicate, 3, 45, 82, 0, // Skip to: 86948 +/* 65911 */ MCD_OPC_CheckField, 10, 1, 0, 38, 82, 0, // Skip to: 86948 +/* 65918 */ MCD_OPC_Decode, 213, 19, 174, 2, // Opcode: MLAv4i16_indexed +/* 65923 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 65945 +/* 65928 */ MCD_OPC_CheckPredicate, 3, 23, 82, 0, // Skip to: 86948 +/* 65933 */ MCD_OPC_CheckField, 10, 1, 0, 16, 82, 0, // Skip to: 86948 +/* 65940 */ MCD_OPC_Decode, 166, 32, 213, 2, // Opcode: UMLALv4i16_indexed +/* 65945 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 65967 +/* 65950 */ MCD_OPC_CheckPredicate, 3, 1, 82, 0, // Skip to: 86948 +/* 65955 */ MCD_OPC_CheckField, 10, 1, 0, 250, 81, 0, // Skip to: 86948 +/* 65962 */ MCD_OPC_Decode, 227, 19, 174, 2, // Opcode: MLSv4i16_indexed +/* 65967 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 65989 +/* 65972 */ MCD_OPC_CheckPredicate, 3, 235, 81, 0, // Skip to: 86948 +/* 65977 */ MCD_OPC_CheckField, 10, 1, 0, 228, 81, 0, // Skip to: 86948 +/* 65984 */ MCD_OPC_Decode, 176, 32, 213, 2, // Opcode: UMLSLv4i16_indexed +/* 65989 */ MCD_OPC_FilterValue, 5, 218, 81, 0, // Skip to: 86948 +/* 65994 */ MCD_OPC_CheckPredicate, 3, 213, 81, 0, // Skip to: 86948 +/* 65999 */ MCD_OPC_CheckField, 10, 1, 0, 206, 81, 0, // Skip to: 86948 +/* 66006 */ MCD_OPC_Decode, 196, 32, 214, 2, // Opcode: UMULLv4i16_indexed +/* 66011 */ MCD_OPC_FilterValue, 1, 196, 81, 0, // Skip to: 86948 +/* 66016 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 66019 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 66041 +/* 66024 */ MCD_OPC_CheckPredicate, 8, 183, 81, 0, // Skip to: 86948 +/* 66029 */ MCD_OPC_CheckField, 10, 2, 0, 176, 81, 0, // Skip to: 86948 +/* 66036 */ MCD_OPC_Decode, 163, 7, 215, 2, // Opcode: FCMLAv4f16_indexed +/* 66041 */ MCD_OPC_FilterValue, 1, 166, 81, 0, // Skip to: 86948 +/* 66046 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 66049 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 66071 +/* 66054 */ MCD_OPC_CheckPredicate, 7, 153, 81, 0, // Skip to: 86948 +/* 66059 */ MCD_OPC_CheckField, 10, 1, 0, 146, 81, 0, // Skip to: 86948 +/* 66066 */ MCD_OPC_Decode, 165, 25, 174, 2, // Opcode: SQRDMLAHv4i16_indexed +/* 66071 */ MCD_OPC_FilterValue, 3, 136, 81, 0, // Skip to: 86948 +/* 66076 */ MCD_OPC_CheckPredicate, 7, 131, 81, 0, // Skip to: 86948 +/* 66081 */ MCD_OPC_CheckField, 10, 1, 0, 124, 81, 0, // Skip to: 86948 +/* 66088 */ MCD_OPC_Decode, 177, 25, 174, 2, // Opcode: SQRDMLSHv4i16_indexed +/* 66093 */ MCD_OPC_FilterValue, 2, 124, 1, 0, // Skip to: 66478 +/* 66098 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 66101 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 66123 +/* 66106 */ MCD_OPC_CheckPredicate, 3, 101, 81, 0, // Skip to: 86948 +/* 66111 */ MCD_OPC_CheckField, 10, 2, 1, 94, 81, 0, // Skip to: 86948 +/* 66118 */ MCD_OPC_Decode, 238, 26, 216, 2, // Opcode: SSHRv2i64_shift +/* 66123 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 66145 +/* 66128 */ MCD_OPC_CheckPredicate, 3, 79, 81, 0, // Skip to: 86948 +/* 66133 */ MCD_OPC_CheckField, 10, 2, 1, 72, 81, 0, // Skip to: 86948 +/* 66140 */ MCD_OPC_Decode, 246, 26, 217, 2, // Opcode: SSRAv2i64_shift +/* 66145 */ MCD_OPC_FilterValue, 2, 40, 0, 0, // Skip to: 66190 +/* 66150 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 66153 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66168 +/* 66158 */ MCD_OPC_CheckPredicate, 3, 49, 81, 0, // Skip to: 86948 +/* 66163 */ MCD_OPC_Decode, 243, 23, 196, 2, // Opcode: SMLALv8i16_indexed +/* 66168 */ MCD_OPC_FilterValue, 1, 39, 81, 0, // Skip to: 86948 +/* 66173 */ MCD_OPC_CheckPredicate, 3, 34, 81, 0, // Skip to: 86948 +/* 66178 */ MCD_OPC_CheckField, 11, 1, 0, 27, 81, 0, // Skip to: 86948 +/* 66185 */ MCD_OPC_Decode, 208, 26, 216, 2, // Opcode: SRSHRv2i64_shift +/* 66190 */ MCD_OPC_FilterValue, 3, 40, 0, 0, // Skip to: 66235 +/* 66195 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 66198 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66213 +/* 66203 */ MCD_OPC_CheckPredicate, 3, 4, 81, 0, // Skip to: 86948 +/* 66208 */ MCD_OPC_Decode, 215, 24, 196, 2, // Opcode: SQDMLALv8i16_indexed +/* 66213 */ MCD_OPC_FilterValue, 1, 250, 80, 0, // Skip to: 86948 +/* 66218 */ MCD_OPC_CheckPredicate, 3, 245, 80, 0, // Skip to: 86948 +/* 66223 */ MCD_OPC_CheckField, 11, 1, 0, 238, 80, 0, // Skip to: 86948 +/* 66230 */ MCD_OPC_Decode, 216, 26, 217, 2, // Opcode: SRSRAv2i64_shift +/* 66235 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 66257 +/* 66240 */ MCD_OPC_CheckPredicate, 3, 223, 80, 0, // Skip to: 86948 +/* 66245 */ MCD_OPC_CheckField, 10, 2, 1, 216, 80, 0, // Skip to: 86948 +/* 66252 */ MCD_OPC_Decode, 142, 23, 218, 2, // Opcode: SHLv2i64_shift +/* 66257 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 66279 +/* 66262 */ MCD_OPC_CheckPredicate, 3, 201, 80, 0, // Skip to: 86948 +/* 66267 */ MCD_OPC_CheckField, 10, 1, 0, 194, 80, 0, // Skip to: 86948 +/* 66274 */ MCD_OPC_Decode, 253, 23, 196, 2, // Opcode: SMLSLv8i16_indexed +/* 66279 */ MCD_OPC_FilterValue, 7, 40, 0, 0, // Skip to: 66324 +/* 66284 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 66287 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66302 +/* 66292 */ MCD_OPC_CheckPredicate, 3, 171, 80, 0, // Skip to: 86948 +/* 66297 */ MCD_OPC_Decode, 227, 24, 196, 2, // Opcode: SQDMLSLv8i16_indexed +/* 66302 */ MCD_OPC_FilterValue, 1, 161, 80, 0, // Skip to: 86948 +/* 66307 */ MCD_OPC_CheckPredicate, 3, 156, 80, 0, // Skip to: 86948 +/* 66312 */ MCD_OPC_CheckField, 11, 1, 0, 149, 80, 0, // Skip to: 86948 +/* 66319 */ MCD_OPC_Decode, 247, 25, 218, 2, // Opcode: SQSHLv2i64_shift +/* 66324 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 66346 +/* 66329 */ MCD_OPC_CheckPredicate, 3, 134, 80, 0, // Skip to: 86948 +/* 66334 */ MCD_OPC_CheckField, 10, 1, 0, 127, 80, 0, // Skip to: 86948 +/* 66341 */ MCD_OPC_Decode, 165, 20, 197, 2, // Opcode: MULv8i16_indexed +/* 66346 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 66368 +/* 66351 */ MCD_OPC_CheckPredicate, 3, 112, 80, 0, // Skip to: 86948 +/* 66356 */ MCD_OPC_CheckField, 10, 1, 0, 105, 80, 0, // Skip to: 86948 +/* 66363 */ MCD_OPC_Decode, 146, 24, 197, 2, // Opcode: SMULLv8i16_indexed +/* 66368 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 66390 +/* 66373 */ MCD_OPC_CheckPredicate, 3, 90, 80, 0, // Skip to: 86948 +/* 66378 */ MCD_OPC_CheckField, 10, 1, 0, 83, 80, 0, // Skip to: 86948 +/* 66385 */ MCD_OPC_Decode, 251, 24, 197, 2, // Opcode: SQDMULLv8i16_indexed +/* 66390 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 66412 +/* 66395 */ MCD_OPC_CheckPredicate, 3, 68, 80, 0, // Skip to: 86948 +/* 66400 */ MCD_OPC_CheckField, 10, 1, 0, 61, 80, 0, // Skip to: 86948 +/* 66407 */ MCD_OPC_Decode, 240, 24, 197, 2, // Opcode: SQDMULHv8i16_indexed +/* 66412 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 66434 +/* 66417 */ MCD_OPC_CheckPredicate, 3, 46, 80, 0, // Skip to: 86948 +/* 66422 */ MCD_OPC_CheckField, 10, 1, 0, 39, 80, 0, // Skip to: 86948 +/* 66429 */ MCD_OPC_Decode, 193, 25, 197, 2, // Opcode: SQRDMULHv8i16_indexed +/* 66434 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 66456 +/* 66439 */ MCD_OPC_CheckPredicate, 3, 24, 80, 0, // Skip to: 86948 +/* 66444 */ MCD_OPC_CheckField, 10, 2, 1, 17, 80, 0, // Skip to: 86948 +/* 66451 */ MCD_OPC_Decode, 212, 22, 216, 2, // Opcode: SCVTFv2i64_shift +/* 66456 */ MCD_OPC_FilterValue, 15, 7, 80, 0, // Skip to: 86948 +/* 66461 */ MCD_OPC_CheckPredicate, 3, 2, 80, 0, // Skip to: 86948 +/* 66466 */ MCD_OPC_CheckField, 10, 2, 3, 251, 79, 0, // Skip to: 86948 +/* 66473 */ MCD_OPC_Decode, 246, 8, 216, 2, // Opcode: FCVTZSv2i64_shift +/* 66478 */ MCD_OPC_FilterValue, 3, 241, 79, 0, // Skip to: 86948 +/* 66483 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 66486 */ MCD_OPC_FilterValue, 0, 147, 0, 0, // Skip to: 66638 +/* 66491 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 66494 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 66577 +/* 66499 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 66502 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66517 +/* 66507 */ MCD_OPC_CheckPredicate, 3, 212, 79, 0, // Skip to: 86948 +/* 66512 */ MCD_OPC_Decode, 217, 19, 196, 2, // Opcode: MLAv8i16_indexed +/* 66517 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 66532 +/* 66522 */ MCD_OPC_CheckPredicate, 3, 197, 79, 0, // Skip to: 86948 +/* 66527 */ MCD_OPC_Decode, 170, 32, 196, 2, // Opcode: UMLALv8i16_indexed +/* 66532 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66547 +/* 66537 */ MCD_OPC_CheckPredicate, 3, 182, 79, 0, // Skip to: 86948 +/* 66542 */ MCD_OPC_Decode, 231, 19, 196, 2, // Opcode: MLSv8i16_indexed +/* 66547 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 66562 +/* 66552 */ MCD_OPC_CheckPredicate, 3, 167, 79, 0, // Skip to: 86948 +/* 66557 */ MCD_OPC_Decode, 180, 32, 196, 2, // Opcode: UMLSLv8i16_indexed +/* 66562 */ MCD_OPC_FilterValue, 5, 157, 79, 0, // Skip to: 86948 +/* 66567 */ MCD_OPC_CheckPredicate, 3, 152, 79, 0, // Skip to: 86948 +/* 66572 */ MCD_OPC_Decode, 200, 32, 197, 2, // Opcode: UMULLv8i16_indexed +/* 66577 */ MCD_OPC_FilterValue, 1, 142, 79, 0, // Skip to: 86948 +/* 66582 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 66585 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66600 +/* 66590 */ MCD_OPC_CheckPredicate, 8, 129, 79, 0, // Skip to: 86948 +/* 66595 */ MCD_OPC_Decode, 167, 7, 219, 2, // Opcode: FCMLAv8f16_indexed +/* 66600 */ MCD_OPC_FilterValue, 1, 119, 79, 0, // Skip to: 86948 +/* 66605 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 66608 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66623 +/* 66613 */ MCD_OPC_CheckPredicate, 7, 106, 79, 0, // Skip to: 86948 +/* 66618 */ MCD_OPC_Decode, 169, 25, 196, 2, // Opcode: SQRDMLAHv8i16_indexed +/* 66623 */ MCD_OPC_FilterValue, 3, 96, 79, 0, // Skip to: 86948 +/* 66628 */ MCD_OPC_CheckPredicate, 7, 91, 79, 0, // Skip to: 86948 +/* 66633 */ MCD_OPC_Decode, 181, 25, 196, 2, // Opcode: SQRDMLSHv8i16_indexed +/* 66638 */ MCD_OPC_FilterValue, 1, 81, 79, 0, // Skip to: 86948 +/* 66643 */ MCD_OPC_ExtractField, 11, 5, // Inst{15-11} ... +/* 66646 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 66661 +/* 66651 */ MCD_OPC_CheckPredicate, 3, 68, 79, 0, // Skip to: 86948 +/* 66656 */ MCD_OPC_Decode, 140, 34, 216, 2, // Opcode: USHRv2i64_shift +/* 66661 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 66676 +/* 66666 */ MCD_OPC_CheckPredicate, 3, 53, 79, 0, // Skip to: 86948 +/* 66671 */ MCD_OPC_Decode, 159, 34, 217, 2, // Opcode: USRAv2i64_shift +/* 66676 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 66691 +/* 66681 */ MCD_OPC_CheckPredicate, 3, 38, 79, 0, // Skip to: 86948 +/* 66686 */ MCD_OPC_Decode, 236, 33, 216, 2, // Opcode: URSHRv2i64_shift +/* 66691 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 66706 +/* 66696 */ MCD_OPC_CheckPredicate, 3, 23, 79, 0, // Skip to: 86948 +/* 66701 */ MCD_OPC_Decode, 246, 33, 217, 2, // Opcode: URSRAv2i64_shift +/* 66706 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 66721 +/* 66711 */ MCD_OPC_CheckPredicate, 3, 8, 79, 0, // Skip to: 86948 +/* 66716 */ MCD_OPC_Decode, 192, 26, 217, 2, // Opcode: SRIv2i64_shift +/* 66721 */ MCD_OPC_FilterValue, 10, 10, 0, 0, // Skip to: 66736 +/* 66726 */ MCD_OPC_CheckPredicate, 3, 249, 78, 0, // Skip to: 86948 +/* 66731 */ MCD_OPC_Decode, 162, 23, 220, 2, // Opcode: SLIv2i64_shift +/* 66736 */ MCD_OPC_FilterValue, 12, 10, 0, 0, // Skip to: 66751 +/* 66741 */ MCD_OPC_CheckPredicate, 3, 234, 78, 0, // Skip to: 86948 +/* 66746 */ MCD_OPC_Decode, 229, 25, 218, 2, // Opcode: SQSHLUv2i64_shift +/* 66751 */ MCD_OPC_FilterValue, 14, 10, 0, 0, // Skip to: 66766 +/* 66756 */ MCD_OPC_CheckPredicate, 3, 219, 78, 0, // Skip to: 86948 +/* 66761 */ MCD_OPC_Decode, 171, 33, 218, 2, // Opcode: UQSHLv2i64_shift +/* 66766 */ MCD_OPC_FilterValue, 28, 10, 0, 0, // Skip to: 66781 +/* 66771 */ MCD_OPC_CheckPredicate, 3, 204, 78, 0, // Skip to: 86948 +/* 66776 */ MCD_OPC_Decode, 199, 31, 216, 2, // Opcode: UCVTFv2i64_shift +/* 66781 */ MCD_OPC_FilterValue, 31, 194, 78, 0, // Skip to: 86948 +/* 66786 */ MCD_OPC_CheckPredicate, 3, 189, 78, 0, // Skip to: 86948 +/* 66791 */ MCD_OPC_Decode, 153, 9, 216, 2, // Opcode: FCVTZUv2i64_shift +/* 66796 */ MCD_OPC_FilterValue, 14, 32, 4, 0, // Skip to: 67857 +/* 66801 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 66804 */ MCD_OPC_FilterValue, 0, 33, 1, 0, // Skip to: 67098 +/* 66809 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 66812 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 66834 +/* 66817 */ MCD_OPC_CheckPredicate, 3, 158, 78, 0, // Skip to: 86948 +/* 66822 */ MCD_OPC_CheckField, 10, 1, 0, 151, 78, 0, // Skip to: 86948 +/* 66829 */ MCD_OPC_Decode, 188, 10, 221, 2, // Opcode: FMLAv2i32_indexed +/* 66834 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 66856 +/* 66839 */ MCD_OPC_CheckPredicate, 3, 136, 78, 0, // Skip to: 86948 +/* 66844 */ MCD_OPC_CheckField, 10, 1, 0, 129, 78, 0, // Skip to: 86948 +/* 66851 */ MCD_OPC_Decode, 237, 23, 222, 2, // Opcode: SMLALv2i32_indexed +/* 66856 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 66878 +/* 66861 */ MCD_OPC_CheckPredicate, 3, 114, 78, 0, // Skip to: 86948 +/* 66866 */ MCD_OPC_CheckField, 10, 1, 0, 107, 78, 0, // Skip to: 86948 +/* 66873 */ MCD_OPC_Decode, 209, 24, 222, 2, // Opcode: SQDMLALv2i32_indexed +/* 66878 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 66900 +/* 66883 */ MCD_OPC_CheckPredicate, 3, 92, 78, 0, // Skip to: 86948 +/* 66888 */ MCD_OPC_CheckField, 10, 1, 0, 85, 78, 0, // Skip to: 86948 +/* 66895 */ MCD_OPC_Decode, 207, 10, 221, 2, // Opcode: FMLSv2i32_indexed +/* 66900 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 66922 +/* 66905 */ MCD_OPC_CheckPredicate, 3, 70, 78, 0, // Skip to: 86948 +/* 66910 */ MCD_OPC_CheckField, 10, 1, 0, 63, 78, 0, // Skip to: 86948 +/* 66917 */ MCD_OPC_Decode, 247, 23, 222, 2, // Opcode: SMLSLv2i32_indexed +/* 66922 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 66944 +/* 66927 */ MCD_OPC_CheckPredicate, 3, 48, 78, 0, // Skip to: 86948 +/* 66932 */ MCD_OPC_CheckField, 10, 1, 0, 41, 78, 0, // Skip to: 86948 +/* 66939 */ MCD_OPC_Decode, 221, 24, 222, 2, // Opcode: SQDMLSLv2i32_indexed +/* 66944 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 66966 +/* 66949 */ MCD_OPC_CheckPredicate, 3, 26, 78, 0, // Skip to: 86948 +/* 66954 */ MCD_OPC_CheckField, 10, 1, 0, 19, 78, 0, // Skip to: 86948 +/* 66961 */ MCD_OPC_Decode, 159, 20, 223, 2, // Opcode: MULv2i32_indexed +/* 66966 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 66988 +/* 66971 */ MCD_OPC_CheckPredicate, 3, 4, 78, 0, // Skip to: 86948 +/* 66976 */ MCD_OPC_CheckField, 10, 1, 0, 253, 77, 0, // Skip to: 86948 +/* 66983 */ MCD_OPC_Decode, 156, 11, 223, 2, // Opcode: FMULv2i32_indexed +/* 66988 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67010 +/* 66993 */ MCD_OPC_CheckPredicate, 3, 238, 77, 0, // Skip to: 86948 +/* 66998 */ MCD_OPC_CheckField, 10, 1, 0, 231, 77, 0, // Skip to: 86948 +/* 67005 */ MCD_OPC_Decode, 140, 24, 224, 2, // Opcode: SMULLv2i32_indexed +/* 67010 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 67032 +/* 67015 */ MCD_OPC_CheckPredicate, 3, 216, 77, 0, // Skip to: 86948 +/* 67020 */ MCD_OPC_CheckField, 10, 1, 0, 209, 77, 0, // Skip to: 86948 +/* 67027 */ MCD_OPC_Decode, 245, 24, 224, 2, // Opcode: SQDMULLv2i32_indexed +/* 67032 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 67054 +/* 67037 */ MCD_OPC_CheckPredicate, 3, 194, 77, 0, // Skip to: 86948 +/* 67042 */ MCD_OPC_CheckField, 10, 1, 0, 187, 77, 0, // Skip to: 86948 +/* 67049 */ MCD_OPC_Decode, 234, 24, 223, 2, // Opcode: SQDMULHv2i32_indexed +/* 67054 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67076 +/* 67059 */ MCD_OPC_CheckPredicate, 3, 172, 77, 0, // Skip to: 86948 +/* 67064 */ MCD_OPC_CheckField, 10, 1, 0, 165, 77, 0, // Skip to: 86948 +/* 67071 */ MCD_OPC_Decode, 187, 25, 223, 2, // Opcode: SQRDMULHv2i32_indexed +/* 67076 */ MCD_OPC_FilterValue, 14, 155, 77, 0, // Skip to: 86948 +/* 67081 */ MCD_OPC_CheckPredicate, 10, 150, 77, 0, // Skip to: 86948 +/* 67086 */ MCD_OPC_CheckField, 10, 1, 0, 143, 77, 0, // Skip to: 86948 +/* 67093 */ MCD_OPC_Decode, 230, 22, 221, 2, // Opcode: SDOTlanev8i8 +/* 67098 */ MCD_OPC_FilterValue, 1, 201, 0, 0, // Skip to: 67304 +/* 67103 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 67106 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67128 +/* 67111 */ MCD_OPC_CheckPredicate, 3, 120, 77, 0, // Skip to: 86948 +/* 67116 */ MCD_OPC_CheckField, 10, 1, 0, 113, 77, 0, // Skip to: 86948 +/* 67123 */ MCD_OPC_Decode, 211, 19, 221, 2, // Opcode: MLAv2i32_indexed +/* 67128 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67150 +/* 67133 */ MCD_OPC_CheckPredicate, 3, 98, 77, 0, // Skip to: 86948 +/* 67138 */ MCD_OPC_CheckField, 10, 1, 0, 91, 77, 0, // Skip to: 86948 +/* 67145 */ MCD_OPC_Decode, 164, 32, 222, 2, // Opcode: UMLALv2i32_indexed +/* 67150 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 67172 +/* 67155 */ MCD_OPC_CheckPredicate, 3, 76, 77, 0, // Skip to: 86948 +/* 67160 */ MCD_OPC_CheckField, 10, 1, 0, 69, 77, 0, // Skip to: 86948 +/* 67167 */ MCD_OPC_Decode, 225, 19, 221, 2, // Opcode: MLSv2i32_indexed +/* 67172 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 67194 +/* 67177 */ MCD_OPC_CheckPredicate, 3, 54, 77, 0, // Skip to: 86948 +/* 67182 */ MCD_OPC_CheckField, 10, 1, 0, 47, 77, 0, // Skip to: 86948 +/* 67189 */ MCD_OPC_Decode, 174, 32, 222, 2, // Opcode: UMLSLv2i32_indexed +/* 67194 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 67216 +/* 67199 */ MCD_OPC_CheckPredicate, 3, 32, 77, 0, // Skip to: 86948 +/* 67204 */ MCD_OPC_CheckField, 10, 1, 0, 25, 77, 0, // Skip to: 86948 +/* 67211 */ MCD_OPC_Decode, 131, 11, 223, 2, // Opcode: FMULXv2i32_indexed +/* 67216 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67238 +/* 67221 */ MCD_OPC_CheckPredicate, 3, 10, 77, 0, // Skip to: 86948 +/* 67226 */ MCD_OPC_CheckField, 10, 1, 0, 3, 77, 0, // Skip to: 86948 +/* 67233 */ MCD_OPC_Decode, 194, 32, 224, 2, // Opcode: UMULLv2i32_indexed +/* 67238 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67260 +/* 67243 */ MCD_OPC_CheckPredicate, 7, 244, 76, 0, // Skip to: 86948 +/* 67248 */ MCD_OPC_CheckField, 10, 1, 0, 237, 76, 0, // Skip to: 86948 +/* 67255 */ MCD_OPC_Decode, 163, 25, 221, 2, // Opcode: SQRDMLAHv2i32_indexed +/* 67260 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 67282 +/* 67265 */ MCD_OPC_CheckPredicate, 10, 222, 76, 0, // Skip to: 86948 +/* 67270 */ MCD_OPC_CheckField, 10, 1, 0, 215, 76, 0, // Skip to: 86948 +/* 67277 */ MCD_OPC_Decode, 217, 31, 221, 2, // Opcode: UDOTlanev8i8 +/* 67282 */ MCD_OPC_FilterValue, 15, 205, 76, 0, // Skip to: 86948 +/* 67287 */ MCD_OPC_CheckPredicate, 7, 200, 76, 0, // Skip to: 86948 +/* 67292 */ MCD_OPC_CheckField, 10, 1, 0, 193, 76, 0, // Skip to: 86948 +/* 67299 */ MCD_OPC_Decode, 175, 25, 221, 2, // Opcode: SQRDMLSHv2i32_indexed +/* 67304 */ MCD_OPC_FilterValue, 2, 33, 1, 0, // Skip to: 67598 +/* 67309 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 67312 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 67334 +/* 67317 */ MCD_OPC_CheckPredicate, 3, 170, 76, 0, // Skip to: 86948 +/* 67322 */ MCD_OPC_CheckField, 10, 1, 0, 163, 76, 0, // Skip to: 86948 +/* 67329 */ MCD_OPC_Decode, 193, 10, 225, 2, // Opcode: FMLAv4i32_indexed +/* 67334 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67356 +/* 67339 */ MCD_OPC_CheckPredicate, 3, 148, 76, 0, // Skip to: 86948 +/* 67344 */ MCD_OPC_CheckField, 10, 1, 0, 141, 76, 0, // Skip to: 86948 +/* 67351 */ MCD_OPC_Decode, 241, 23, 225, 2, // Opcode: SMLALv4i32_indexed +/* 67356 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 67378 +/* 67361 */ MCD_OPC_CheckPredicate, 3, 126, 76, 0, // Skip to: 86948 +/* 67366 */ MCD_OPC_CheckField, 10, 1, 0, 119, 76, 0, // Skip to: 86948 +/* 67373 */ MCD_OPC_Decode, 213, 24, 225, 2, // Opcode: SQDMLALv4i32_indexed +/* 67378 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 67400 +/* 67383 */ MCD_OPC_CheckPredicate, 3, 104, 76, 0, // Skip to: 86948 +/* 67388 */ MCD_OPC_CheckField, 10, 1, 0, 97, 76, 0, // Skip to: 86948 +/* 67395 */ MCD_OPC_Decode, 212, 10, 225, 2, // Opcode: FMLSv4i32_indexed +/* 67400 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 67422 +/* 67405 */ MCD_OPC_CheckPredicate, 3, 82, 76, 0, // Skip to: 86948 +/* 67410 */ MCD_OPC_CheckField, 10, 1, 0, 75, 76, 0, // Skip to: 86948 +/* 67417 */ MCD_OPC_Decode, 251, 23, 225, 2, // Opcode: SMLSLv4i32_indexed +/* 67422 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 67444 +/* 67427 */ MCD_OPC_CheckPredicate, 3, 60, 76, 0, // Skip to: 86948 +/* 67432 */ MCD_OPC_CheckField, 10, 1, 0, 53, 76, 0, // Skip to: 86948 +/* 67439 */ MCD_OPC_Decode, 225, 24, 225, 2, // Opcode: SQDMLSLv4i32_indexed +/* 67444 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 67466 +/* 67449 */ MCD_OPC_CheckPredicate, 3, 38, 76, 0, // Skip to: 86948 +/* 67454 */ MCD_OPC_CheckField, 10, 1, 0, 31, 76, 0, // Skip to: 86948 +/* 67461 */ MCD_OPC_Decode, 163, 20, 226, 2, // Opcode: MULv4i32_indexed +/* 67466 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 67488 +/* 67471 */ MCD_OPC_CheckPredicate, 3, 16, 76, 0, // Skip to: 86948 +/* 67476 */ MCD_OPC_CheckField, 10, 1, 0, 9, 76, 0, // Skip to: 86948 +/* 67483 */ MCD_OPC_Decode, 161, 11, 226, 2, // Opcode: FMULv4i32_indexed +/* 67488 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 67510 +/* 67493 */ MCD_OPC_CheckPredicate, 3, 250, 75, 0, // Skip to: 86948 +/* 67498 */ MCD_OPC_CheckField, 10, 1, 0, 243, 75, 0, // Skip to: 86948 +/* 67505 */ MCD_OPC_Decode, 144, 24, 226, 2, // Opcode: SMULLv4i32_indexed +/* 67510 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 67532 +/* 67515 */ MCD_OPC_CheckPredicate, 3, 228, 75, 0, // Skip to: 86948 +/* 67520 */ MCD_OPC_CheckField, 10, 1, 0, 221, 75, 0, // Skip to: 86948 +/* 67527 */ MCD_OPC_Decode, 249, 24, 226, 2, // Opcode: SQDMULLv4i32_indexed +/* 67532 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 67554 +/* 67537 */ MCD_OPC_CheckPredicate, 3, 206, 75, 0, // Skip to: 86948 +/* 67542 */ MCD_OPC_CheckField, 10, 1, 0, 199, 75, 0, // Skip to: 86948 +/* 67549 */ MCD_OPC_Decode, 238, 24, 226, 2, // Opcode: SQDMULHv4i32_indexed +/* 67554 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 67576 +/* 67559 */ MCD_OPC_CheckPredicate, 3, 184, 75, 0, // Skip to: 86948 +/* 67564 */ MCD_OPC_CheckField, 10, 1, 0, 177, 75, 0, // Skip to: 86948 +/* 67571 */ MCD_OPC_Decode, 191, 25, 226, 2, // Opcode: SQRDMULHv4i32_indexed +/* 67576 */ MCD_OPC_FilterValue, 14, 167, 75, 0, // Skip to: 86948 +/* 67581 */ MCD_OPC_CheckPredicate, 10, 162, 75, 0, // Skip to: 86948 +/* 67586 */ MCD_OPC_CheckField, 10, 1, 0, 155, 75, 0, // Skip to: 86948 +/* 67593 */ MCD_OPC_Decode, 229, 22, 225, 2, // Opcode: SDOTlanev16i8 +/* 67598 */ MCD_OPC_FilterValue, 3, 145, 75, 0, // Skip to: 86948 +/* 67603 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 67606 */ MCD_OPC_FilterValue, 0, 135, 0, 0, // Skip to: 67746 +/* 67611 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 67614 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67636 +/* 67619 */ MCD_OPC_CheckPredicate, 3, 124, 75, 0, // Skip to: 86948 +/* 67624 */ MCD_OPC_CheckField, 10, 1, 0, 117, 75, 0, // Skip to: 86948 +/* 67631 */ MCD_OPC_Decode, 215, 19, 225, 2, // Opcode: MLAv4i32_indexed +/* 67636 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 67658 +/* 67641 */ MCD_OPC_CheckPredicate, 3, 102, 75, 0, // Skip to: 86948 +/* 67646 */ MCD_OPC_CheckField, 10, 1, 0, 95, 75, 0, // Skip to: 86948 +/* 67653 */ MCD_OPC_Decode, 168, 32, 225, 2, // Opcode: UMLALv4i32_indexed +/* 67658 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67680 +/* 67663 */ MCD_OPC_CheckPredicate, 3, 80, 75, 0, // Skip to: 86948 +/* 67668 */ MCD_OPC_CheckField, 10, 1, 0, 73, 75, 0, // Skip to: 86948 +/* 67675 */ MCD_OPC_Decode, 229, 19, 225, 2, // Opcode: MLSv4i32_indexed +/* 67680 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 67702 +/* 67685 */ MCD_OPC_CheckPredicate, 3, 58, 75, 0, // Skip to: 86948 +/* 67690 */ MCD_OPC_CheckField, 10, 1, 0, 51, 75, 0, // Skip to: 86948 +/* 67697 */ MCD_OPC_Decode, 178, 32, 225, 2, // Opcode: UMLSLv4i32_indexed +/* 67702 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 67724 +/* 67707 */ MCD_OPC_CheckPredicate, 3, 36, 75, 0, // Skip to: 86948 +/* 67712 */ MCD_OPC_CheckField, 10, 1, 0, 29, 75, 0, // Skip to: 86948 +/* 67719 */ MCD_OPC_Decode, 198, 32, 226, 2, // Opcode: UMULLv4i32_indexed +/* 67724 */ MCD_OPC_FilterValue, 7, 19, 75, 0, // Skip to: 86948 +/* 67729 */ MCD_OPC_CheckPredicate, 10, 14, 75, 0, // Skip to: 86948 +/* 67734 */ MCD_OPC_CheckField, 10, 1, 0, 7, 75, 0, // Skip to: 86948 +/* 67741 */ MCD_OPC_Decode, 216, 31, 225, 2, // Opcode: UDOTlanev16i8 +/* 67746 */ MCD_OPC_FilterValue, 1, 253, 74, 0, // Skip to: 86948 +/* 67751 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 67754 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 67783 +/* 67759 */ MCD_OPC_CheckPredicate, 11, 240, 74, 0, // Skip to: 86948 +/* 67764 */ MCD_OPC_CheckField, 21, 1, 0, 233, 74, 0, // Skip to: 86948 +/* 67771 */ MCD_OPC_CheckField, 10, 1, 0, 226, 74, 0, // Skip to: 86948 +/* 67778 */ MCD_OPC_Decode, 165, 7, 227, 2, // Opcode: FCMLAv4f32_indexed +/* 67783 */ MCD_OPC_FilterValue, 1, 216, 74, 0, // Skip to: 86948 +/* 67788 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 67791 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 67813 +/* 67796 */ MCD_OPC_CheckPredicate, 3, 203, 74, 0, // Skip to: 86948 +/* 67801 */ MCD_OPC_CheckField, 10, 1, 0, 196, 74, 0, // Skip to: 86948 +/* 67808 */ MCD_OPC_Decode, 136, 11, 226, 2, // Opcode: FMULXv4i32_indexed +/* 67813 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 67835 +/* 67818 */ MCD_OPC_CheckPredicate, 7, 181, 74, 0, // Skip to: 86948 +/* 67823 */ MCD_OPC_CheckField, 10, 1, 0, 174, 74, 0, // Skip to: 86948 +/* 67830 */ MCD_OPC_Decode, 167, 25, 225, 2, // Opcode: SQRDMLAHv4i32_indexed +/* 67835 */ MCD_OPC_FilterValue, 3, 164, 74, 0, // Skip to: 86948 +/* 67840 */ MCD_OPC_CheckPredicate, 7, 159, 74, 0, // Skip to: 86948 +/* 67845 */ MCD_OPC_CheckField, 10, 1, 0, 152, 74, 0, // Skip to: 86948 +/* 67852 */ MCD_OPC_Decode, 179, 25, 225, 2, // Opcode: SQRDMLSHv4i32_indexed +/* 67857 */ MCD_OPC_FilterValue, 15, 142, 74, 0, // Skip to: 86948 +/* 67862 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 67865 */ MCD_OPC_FilterValue, 1, 31, 0, 0, // Skip to: 67901 +/* 67870 */ MCD_OPC_CheckPredicate, 3, 129, 74, 0, // Skip to: 86948 +/* 67875 */ MCD_OPC_CheckField, 29, 3, 2, 122, 74, 0, // Skip to: 86948 +/* 67882 */ MCD_OPC_CheckField, 21, 1, 0, 115, 74, 0, // Skip to: 86948 +/* 67889 */ MCD_OPC_CheckField, 10, 1, 0, 108, 74, 0, // Skip to: 86948 +/* 67896 */ MCD_OPC_Decode, 189, 10, 228, 2, // Opcode: FMLAv2i64_indexed +/* 67901 */ MCD_OPC_FilterValue, 5, 31, 0, 0, // Skip to: 67937 +/* 67906 */ MCD_OPC_CheckPredicate, 3, 93, 74, 0, // Skip to: 86948 +/* 67911 */ MCD_OPC_CheckField, 29, 3, 2, 86, 74, 0, // Skip to: 86948 +/* 67918 */ MCD_OPC_CheckField, 21, 1, 0, 79, 74, 0, // Skip to: 86948 +/* 67925 */ MCD_OPC_CheckField, 10, 1, 0, 72, 74, 0, // Skip to: 86948 +/* 67932 */ MCD_OPC_Decode, 208, 10, 228, 2, // Opcode: FMLSv2i64_indexed +/* 67937 */ MCD_OPC_FilterValue, 9, 62, 74, 0, // Skip to: 86948 +/* 67942 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 67945 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 67974 +/* 67950 */ MCD_OPC_CheckPredicate, 3, 49, 74, 0, // Skip to: 86948 +/* 67955 */ MCD_OPC_CheckField, 21, 1, 0, 42, 74, 0, // Skip to: 86948 +/* 67962 */ MCD_OPC_CheckField, 10, 1, 0, 35, 74, 0, // Skip to: 86948 +/* 67969 */ MCD_OPC_Decode, 157, 11, 229, 2, // Opcode: FMULv2i64_indexed +/* 67974 */ MCD_OPC_FilterValue, 3, 25, 74, 0, // Skip to: 86948 +/* 67979 */ MCD_OPC_CheckPredicate, 3, 20, 74, 0, // Skip to: 86948 +/* 67984 */ MCD_OPC_CheckField, 21, 1, 0, 13, 74, 0, // Skip to: 86948 +/* 67991 */ MCD_OPC_CheckField, 10, 1, 0, 6, 74, 0, // Skip to: 86948 +/* 67998 */ MCD_OPC_Decode, 132, 11, 229, 2, // Opcode: FMULXv2i64_indexed +/* 68003 */ MCD_OPC_FilterValue, 4, 5, 2, 0, // Skip to: 68525 +/* 68008 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 68011 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 68039 +/* 68016 */ MCD_OPC_ExtractField, 31, 1, // Inst{31} ... +/* 68019 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68029 +/* 68024 */ MCD_OPC_Decode, 204, 1, 230, 2, // Opcode: ADR +/* 68029 */ MCD_OPC_FilterValue, 1, 226, 73, 0, // Skip to: 86948 +/* 68034 */ MCD_OPC_Decode, 205, 1, 230, 2, // Opcode: ADRP +/* 68039 */ MCD_OPC_FilterValue, 1, 83, 0, 0, // Skip to: 68127 +/* 68044 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 68047 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68057 +/* 68052 */ MCD_OPC_Decode, 172, 1, 231, 2, // Opcode: ADDWri +/* 68057 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68067 +/* 68062 */ MCD_OPC_Decode, 157, 1, 231, 2, // Opcode: ADDSWri +/* 68067 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68077 +/* 68072 */ MCD_OPC_Decode, 234, 29, 231, 2, // Opcode: SUBWri +/* 68077 */ MCD_OPC_FilterValue, 3, 5, 0, 0, // Skip to: 68087 +/* 68082 */ MCD_OPC_Decode, 225, 29, 231, 2, // Opcode: SUBSWri +/* 68087 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 68097 +/* 68092 */ MCD_OPC_Decode, 176, 1, 231, 2, // Opcode: ADDXri +/* 68097 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 68107 +/* 68102 */ MCD_OPC_Decode, 161, 1, 231, 2, // Opcode: ADDSXri +/* 68107 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 68117 +/* 68112 */ MCD_OPC_Decode, 238, 29, 231, 2, // Opcode: SUBXri +/* 68117 */ MCD_OPC_FilterValue, 7, 138, 73, 0, // Skip to: 86948 +/* 68122 */ MCD_OPC_Decode, 229, 29, 231, 2, // Opcode: SUBSXri +/* 68127 */ MCD_OPC_FilterValue, 2, 226, 0, 0, // Skip to: 68358 +/* 68132 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 68135 */ MCD_OPC_FilterValue, 0, 30, 0, 0, // Skip to: 68170 +/* 68140 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 68143 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68160 +/* 68148 */ MCD_OPC_CheckField, 22, 1, 0, 105, 73, 0, // Skip to: 86948 +/* 68155 */ MCD_OPC_Decode, 239, 1, 232, 2, // Opcode: ANDWri +/* 68160 */ MCD_OPC_FilterValue, 1, 95, 73, 0, // Skip to: 86948 +/* 68165 */ MCD_OPC_Decode, 245, 19, 233, 2, // Opcode: MOVNWi +/* 68170 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 68187 +/* 68175 */ MCD_OPC_CheckField, 22, 2, 0, 78, 73, 0, // Skip to: 86948 +/* 68182 */ MCD_OPC_Decode, 204, 20, 232, 2, // Opcode: ORRWri +/* 68187 */ MCD_OPC_FilterValue, 2, 30, 0, 0, // Skip to: 68222 +/* 68192 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 68195 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68212 +/* 68200 */ MCD_OPC_CheckField, 22, 1, 0, 53, 73, 0, // Skip to: 86948 +/* 68207 */ MCD_OPC_Decode, 232, 5, 232, 2, // Opcode: EORWri +/* 68212 */ MCD_OPC_FilterValue, 1, 43, 73, 0, // Skip to: 86948 +/* 68217 */ MCD_OPC_Decode, 128, 20, 233, 2, // Opcode: MOVZWi +/* 68222 */ MCD_OPC_FilterValue, 3, 30, 0, 0, // Skip to: 68257 +/* 68227 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 68230 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68247 +/* 68235 */ MCD_OPC_CheckField, 22, 1, 0, 18, 73, 0, // Skip to: 86948 +/* 68242 */ MCD_OPC_Decode, 228, 1, 232, 2, // Opcode: ANDSWri +/* 68247 */ MCD_OPC_FilterValue, 1, 8, 73, 0, // Skip to: 86948 +/* 68252 */ MCD_OPC_Decode, 243, 19, 233, 2, // Opcode: MOVKWi +/* 68257 */ MCD_OPC_FilterValue, 4, 23, 0, 0, // Skip to: 68285 +/* 68262 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 68265 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68275 +/* 68270 */ MCD_OPC_Decode, 242, 1, 232, 2, // Opcode: ANDXri +/* 68275 */ MCD_OPC_FilterValue, 1, 236, 72, 0, // Skip to: 86948 +/* 68280 */ MCD_OPC_Decode, 246, 19, 233, 2, // Opcode: MOVNXi +/* 68285 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 68302 +/* 68290 */ MCD_OPC_CheckField, 23, 1, 0, 219, 72, 0, // Skip to: 86948 +/* 68297 */ MCD_OPC_Decode, 207, 20, 232, 2, // Opcode: ORRXri +/* 68302 */ MCD_OPC_FilterValue, 6, 23, 0, 0, // Skip to: 68330 +/* 68307 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 68310 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68320 +/* 68315 */ MCD_OPC_Decode, 235, 5, 232, 2, // Opcode: EORXri +/* 68320 */ MCD_OPC_FilterValue, 1, 191, 72, 0, // Skip to: 86948 +/* 68325 */ MCD_OPC_Decode, 129, 20, 233, 2, // Opcode: MOVZXi +/* 68330 */ MCD_OPC_FilterValue, 7, 181, 72, 0, // Skip to: 86948 +/* 68335 */ MCD_OPC_ExtractField, 23, 1, // Inst{23} ... +/* 68338 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68348 +/* 68343 */ MCD_OPC_Decode, 231, 1, 232, 2, // Opcode: ANDSXri +/* 68348 */ MCD_OPC_FilterValue, 1, 163, 72, 0, // Skip to: 86948 +/* 68353 */ MCD_OPC_Decode, 244, 19, 233, 2, // Opcode: MOVKXi +/* 68358 */ MCD_OPC_FilterValue, 3, 153, 72, 0, // Skip to: 86948 +/* 68363 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 68366 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 68408 +/* 68371 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 68374 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 68391 +/* 68379 */ MCD_OPC_CheckField, 15, 1, 0, 130, 72, 0, // Skip to: 86948 +/* 68386 */ MCD_OPC_Decode, 182, 22, 234, 2, // Opcode: SBFMWri +/* 68391 */ MCD_OPC_FilterValue, 4, 120, 72, 0, // Skip to: 86948 +/* 68396 */ MCD_OPC_CheckField, 15, 1, 0, 113, 72, 0, // Skip to: 86948 +/* 68403 */ MCD_OPC_Decode, 250, 5, 235, 2, // Opcode: EXTRWrri +/* 68408 */ MCD_OPC_FilterValue, 1, 19, 0, 0, // Skip to: 68432 +/* 68413 */ MCD_OPC_CheckField, 21, 3, 0, 96, 72, 0, // Skip to: 86948 +/* 68420 */ MCD_OPC_CheckField, 15, 1, 0, 89, 72, 0, // Skip to: 86948 +/* 68427 */ MCD_OPC_Decode, 170, 2, 236, 2, // Opcode: BFMWri +/* 68432 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 68456 +/* 68437 */ MCD_OPC_CheckField, 21, 3, 0, 72, 72, 0, // Skip to: 86948 +/* 68444 */ MCD_OPC_CheckField, 15, 1, 0, 65, 72, 0, // Skip to: 86948 +/* 68451 */ MCD_OPC_Decode, 169, 31, 234, 2, // Opcode: UBFMWri +/* 68456 */ MCD_OPC_FilterValue, 4, 30, 0, 0, // Skip to: 68491 +/* 68461 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 68464 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68474 +/* 68469 */ MCD_OPC_Decode, 183, 22, 237, 2, // Opcode: SBFMXri +/* 68474 */ MCD_OPC_FilterValue, 3, 37, 72, 0, // Skip to: 86948 +/* 68479 */ MCD_OPC_CheckField, 21, 1, 0, 30, 72, 0, // Skip to: 86948 +/* 68486 */ MCD_OPC_Decode, 251, 5, 238, 2, // Opcode: EXTRXrri +/* 68491 */ MCD_OPC_FilterValue, 5, 12, 0, 0, // Skip to: 68508 +/* 68496 */ MCD_OPC_CheckField, 22, 2, 1, 13, 72, 0, // Skip to: 86948 +/* 68503 */ MCD_OPC_Decode, 171, 2, 239, 2, // Opcode: BFMXri +/* 68508 */ MCD_OPC_FilterValue, 6, 3, 72, 0, // Skip to: 86948 +/* 68513 */ MCD_OPC_CheckField, 22, 2, 1, 252, 71, 0, // Skip to: 86948 +/* 68520 */ MCD_OPC_Decode, 170, 31, 237, 2, // Opcode: UBFMXri +/* 68525 */ MCD_OPC_FilterValue, 5, 218, 3, 0, // Skip to: 69516 +/* 68530 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 68533 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68543 +/* 68538 */ MCD_OPC_Decode, 168, 2, 240, 2, // Opcode: B +/* 68543 */ MCD_OPC_FilterValue, 1, 43, 0, 0, // Skip to: 68591 +/* 68548 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 68551 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68561 +/* 68556 */ MCD_OPC_Decode, 250, 2, 241, 2, // Opcode: CBZW +/* 68561 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68571 +/* 68566 */ MCD_OPC_Decode, 248, 2, 241, 2, // Opcode: CBNZW +/* 68571 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68581 +/* 68576 */ MCD_OPC_Decode, 199, 30, 242, 2, // Opcode: TBZW +/* 68581 */ MCD_OPC_FilterValue, 3, 186, 71, 0, // Skip to: 86948 +/* 68586 */ MCD_OPC_Decode, 189, 30, 242, 2, // Opcode: TBNZW +/* 68591 */ MCD_OPC_FilterValue, 2, 19, 0, 0, // Skip to: 68615 +/* 68596 */ MCD_OPC_CheckField, 24, 2, 0, 169, 71, 0, // Skip to: 86948 +/* 68603 */ MCD_OPC_CheckField, 4, 1, 0, 162, 71, 0, // Skip to: 86948 +/* 68610 */ MCD_OPC_Decode, 223, 2, 243, 2, // Opcode: Bcc +/* 68615 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 68625 +/* 68620 */ MCD_OPC_Decode, 197, 2, 240, 2, // Opcode: BL +/* 68625 */ MCD_OPC_FilterValue, 5, 43, 0, 0, // Skip to: 68673 +/* 68630 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 68633 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 68643 +/* 68638 */ MCD_OPC_Decode, 251, 2, 244, 2, // Opcode: CBZX +/* 68643 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68653 +/* 68648 */ MCD_OPC_Decode, 249, 2, 244, 2, // Opcode: CBNZX +/* 68653 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68663 +/* 68658 */ MCD_OPC_Decode, 200, 30, 242, 2, // Opcode: TBZX +/* 68663 */ MCD_OPC_FilterValue, 3, 104, 71, 0, // Skip to: 86948 +/* 68668 */ MCD_OPC_Decode, 190, 30, 242, 2, // Opcode: TBNZX +/* 68673 */ MCD_OPC_FilterValue, 6, 94, 71, 0, // Skip to: 86948 +/* 68678 */ MCD_OPC_ExtractField, 21, 5, // Inst{25-21} ... +/* 68681 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 68719 +/* 68686 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 68689 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68699 +/* 68694 */ MCD_OPC_Decode, 152, 30, 245, 2, // Opcode: SVC +/* 68699 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68709 +/* 68704 */ MCD_OPC_Decode, 243, 13, 245, 2, // Opcode: HVC +/* 68709 */ MCD_OPC_FilterValue, 3, 58, 71, 0, // Skip to: 86948 +/* 68714 */ MCD_OPC_Decode, 206, 23, 245, 2, // Opcode: SMC +/* 68719 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 68736 +/* 68724 */ MCD_OPC_CheckField, 0, 5, 0, 41, 71, 0, // Skip to: 86948 +/* 68731 */ MCD_OPC_Decode, 208, 2, 245, 2, // Opcode: BRK +/* 68736 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 68753 +/* 68741 */ MCD_OPC_CheckField, 0, 5, 0, 24, 71, 0, // Skip to: 86948 +/* 68748 */ MCD_OPC_Decode, 242, 13, 245, 2, // Opcode: HLT +/* 68753 */ MCD_OPC_FilterValue, 5, 33, 0, 0, // Skip to: 68791 +/* 68758 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 68761 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 68771 +/* 68766 */ MCD_OPC_Decode, 174, 5, 245, 2, // Opcode: DCPS1 +/* 68771 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 68781 +/* 68776 */ MCD_OPC_Decode, 175, 5, 245, 2, // Opcode: DCPS2 +/* 68781 */ MCD_OPC_FilterValue, 3, 242, 70, 0, // Skip to: 86948 +/* 68786 */ MCD_OPC_Decode, 176, 5, 245, 2, // Opcode: DCPS3 +/* 68791 */ MCD_OPC_FilterValue, 8, 77, 1, 0, // Skip to: 69129 +/* 68796 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... +/* 68799 */ MCD_OPC_FilterValue, 159, 128, 1, 9, 0, 0, // Skip to: 68815 +/* 68806 */ MCD_OPC_CheckPredicate, 12, 163, 0, 0, // Skip to: 68974 +/* 68811 */ MCD_OPC_Decode, 132, 3, 97, // Opcode: CFINV +/* 68815 */ MCD_OPC_FilterValue, 255, 193, 12, 4, 0, 0, // Skip to: 68826 +/* 68822 */ MCD_OPC_Decode, 254, 34, 97, // Opcode: XPACLRI +/* 68826 */ MCD_OPC_FilterValue, 159, 194, 12, 4, 0, 0, // Skip to: 68837 +/* 68833 */ MCD_OPC_Decode, 233, 20, 97, // Opcode: PACIA1716 +/* 68837 */ MCD_OPC_FilterValue, 223, 194, 12, 4, 0, 0, // Skip to: 68848 +/* 68844 */ MCD_OPC_Decode, 237, 20, 97, // Opcode: PACIB1716 +/* 68848 */ MCD_OPC_FilterValue, 159, 195, 12, 4, 0, 0, // Skip to: 68859 +/* 68855 */ MCD_OPC_Decode, 159, 2, 97, // Opcode: AUTIA1716 +/* 68859 */ MCD_OPC_FilterValue, 223, 195, 12, 4, 0, 0, // Skip to: 68870 +/* 68866 */ MCD_OPC_Decode, 163, 2, 97, // Opcode: AUTIB1716 +/* 68870 */ MCD_OPC_FilterValue, 223, 196, 12, 9, 0, 0, // Skip to: 68886 +/* 68877 */ MCD_OPC_CheckPredicate, 12, 92, 0, 0, // Skip to: 68974 +/* 68882 */ MCD_OPC_Decode, 235, 30, 97, // Opcode: TSB +/* 68886 */ MCD_OPC_FilterValue, 159, 198, 12, 4, 0, 0, // Skip to: 68897 +/* 68893 */ MCD_OPC_Decode, 235, 20, 97, // Opcode: PACIAZ +/* 68897 */ MCD_OPC_FilterValue, 191, 198, 12, 4, 0, 0, // Skip to: 68908 +/* 68904 */ MCD_OPC_Decode, 234, 20, 97, // Opcode: PACIASP +/* 68908 */ MCD_OPC_FilterValue, 223, 198, 12, 4, 0, 0, // Skip to: 68919 +/* 68915 */ MCD_OPC_Decode, 239, 20, 97, // Opcode: PACIBZ +/* 68919 */ MCD_OPC_FilterValue, 255, 198, 12, 4, 0, 0, // Skip to: 68930 +/* 68926 */ MCD_OPC_Decode, 238, 20, 97, // Opcode: PACIBSP +/* 68930 */ MCD_OPC_FilterValue, 159, 199, 12, 4, 0, 0, // Skip to: 68941 +/* 68937 */ MCD_OPC_Decode, 161, 2, 97, // Opcode: AUTIAZ +/* 68941 */ MCD_OPC_FilterValue, 191, 199, 12, 4, 0, 0, // Skip to: 68952 +/* 68948 */ MCD_OPC_Decode, 160, 2, 97, // Opcode: AUTIASP +/* 68952 */ MCD_OPC_FilterValue, 223, 199, 12, 4, 0, 0, // Skip to: 68963 +/* 68959 */ MCD_OPC_Decode, 165, 2, 97, // Opcode: AUTIBZ +/* 68963 */ MCD_OPC_FilterValue, 255, 199, 12, 4, 0, 0, // Skip to: 68974 +/* 68970 */ MCD_OPC_Decode, 164, 2, 97, // Opcode: AUTIBSP +/* 68974 */ MCD_OPC_ExtractField, 0, 8, // Inst{7-0} ... +/* 68977 */ MCD_OPC_FilterValue, 95, 12, 0, 0, // Skip to: 68994 +/* 68982 */ MCD_OPC_CheckField, 12, 9, 51, 59, 0, 0, // Skip to: 69048 +/* 68989 */ MCD_OPC_Decode, 157, 3, 246, 2, // Opcode: CLREX +/* 68994 */ MCD_OPC_FilterValue, 159, 1, 12, 0, 0, // Skip to: 69012 +/* 69000 */ MCD_OPC_CheckField, 12, 9, 51, 41, 0, 0, // Skip to: 69048 +/* 69007 */ MCD_OPC_Decode, 193, 5, 246, 2, // Opcode: DSB +/* 69012 */ MCD_OPC_FilterValue, 191, 1, 12, 0, 0, // Skip to: 69030 +/* 69018 */ MCD_OPC_CheckField, 12, 9, 51, 23, 0, 0, // Skip to: 69048 +/* 69025 */ MCD_OPC_Decode, 191, 5, 246, 2, // Opcode: DMB +/* 69030 */ MCD_OPC_FilterValue, 223, 1, 12, 0, 0, // Skip to: 69048 +/* 69036 */ MCD_OPC_CheckField, 12, 9, 51, 5, 0, 0, // Skip to: 69048 +/* 69043 */ MCD_OPC_Decode, 162, 14, 246, 2, // Opcode: ISB +/* 69048 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 69051 */ MCD_OPC_FilterValue, 31, 56, 0, 0, // Skip to: 69112 +/* 69056 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 69059 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 69076 +/* 69064 */ MCD_OPC_CheckField, 16, 5, 3, 41, 0, 0, // Skip to: 69112 +/* 69071 */ MCD_OPC_Decode, 241, 13, 247, 2, // Opcode: HINT +/* 69076 */ MCD_OPC_FilterValue, 4, 31, 0, 0, // Skip to: 69112 +/* 69081 */ MCD_OPC_ExtractField, 19, 2, // Inst{20-19} ... +/* 69084 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 69112 +/* 69089 */ MCD_OPC_CheckField, 9, 3, 0, 8, 0, 0, // Skip to: 69104 +/* 69096 */ MCD_OPC_TryDecode, 145, 20, 248, 2, 0, 0, 0, // Opcode: MSRpstateImm1, skip to: 69104 +/* 69104 */ MCD_OPC_TryDecode, 146, 20, 248, 2, 0, 0, 0, // Opcode: MSRpstateImm4, skip to: 69112 +/* 69112 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, 0, // Skip to: 69124 +/* 69119 */ MCD_OPC_Decode, 176, 30, 249, 2, // Opcode: SYSxt +/* 69124 */ MCD_OPC_Decode, 144, 20, 250, 2, // Opcode: MSR +/* 69129 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 69151 +/* 69134 */ MCD_OPC_CheckField, 19, 2, 1, 5, 0, 0, // Skip to: 69146 +/* 69141 */ MCD_OPC_Decode, 175, 30, 251, 2, // Opcode: SYSLxt +/* 69146 */ MCD_OPC_Decode, 139, 20, 252, 2, // Opcode: MRS +/* 69151 */ MCD_OPC_FilterValue, 16, 67, 0, 0, // Skip to: 69223 +/* 69156 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 69159 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69177 +/* 69165 */ MCD_OPC_CheckField, 0, 5, 0, 112, 69, 0, // Skip to: 86948 +/* 69172 */ MCD_OPC_Decode, 203, 2, 253, 2, // Opcode: BR +/* 69177 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69200 +/* 69183 */ MCD_OPC_CheckPredicate, 13, 96, 69, 0, // Skip to: 86948 +/* 69188 */ MCD_OPC_CheckField, 0, 5, 31, 89, 69, 0, // Skip to: 86948 +/* 69195 */ MCD_OPC_Decode, 205, 2, 253, 2, // Opcode: BRAAZ +/* 69200 */ MCD_OPC_FilterValue, 195, 15, 78, 69, 0, // Skip to: 86948 +/* 69206 */ MCD_OPC_CheckPredicate, 13, 73, 69, 0, // Skip to: 86948 +/* 69211 */ MCD_OPC_CheckField, 0, 5, 31, 66, 69, 0, // Skip to: 86948 +/* 69218 */ MCD_OPC_Decode, 207, 2, 253, 2, // Opcode: BRABZ +/* 69223 */ MCD_OPC_FilterValue, 17, 67, 0, 0, // Skip to: 69295 +/* 69228 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 69231 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69249 +/* 69237 */ MCD_OPC_CheckField, 0, 5, 0, 40, 69, 0, // Skip to: 86948 +/* 69244 */ MCD_OPC_Decode, 198, 2, 253, 2, // Opcode: BLR +/* 69249 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69272 +/* 69255 */ MCD_OPC_CheckPredicate, 13, 24, 69, 0, // Skip to: 86948 +/* 69260 */ MCD_OPC_CheckField, 0, 5, 31, 17, 69, 0, // Skip to: 86948 +/* 69267 */ MCD_OPC_Decode, 200, 2, 253, 2, // Opcode: BLRAAZ +/* 69272 */ MCD_OPC_FilterValue, 195, 15, 6, 69, 0, // Skip to: 86948 +/* 69278 */ MCD_OPC_CheckPredicate, 13, 1, 69, 0, // Skip to: 86948 +/* 69283 */ MCD_OPC_CheckField, 0, 5, 31, 250, 68, 0, // Skip to: 86948 +/* 69290 */ MCD_OPC_Decode, 202, 2, 253, 2, // Opcode: BLRABZ +/* 69295 */ MCD_OPC_FilterValue, 18, 67, 0, 0, // Skip to: 69367 +/* 69300 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 69303 */ MCD_OPC_FilterValue, 192, 15, 12, 0, 0, // Skip to: 69321 +/* 69309 */ MCD_OPC_CheckField, 0, 5, 0, 224, 68, 0, // Skip to: 86948 +/* 69316 */ MCD_OPC_Decode, 196, 21, 253, 2, // Opcode: RET +/* 69321 */ MCD_OPC_FilterValue, 194, 15, 17, 0, 0, // Skip to: 69344 +/* 69327 */ MCD_OPC_CheckPredicate, 13, 208, 68, 0, // Skip to: 86948 +/* 69332 */ MCD_OPC_CheckField, 0, 10, 255, 7, 200, 68, 0, // Skip to: 86948 +/* 69340 */ MCD_OPC_Decode, 197, 21, 97, // Opcode: RETAA +/* 69344 */ MCD_OPC_FilterValue, 195, 15, 190, 68, 0, // Skip to: 86948 +/* 69350 */ MCD_OPC_CheckPredicate, 13, 185, 68, 0, // Skip to: 86948 +/* 69355 */ MCD_OPC_CheckField, 0, 10, 255, 7, 177, 68, 0, // Skip to: 86948 +/* 69363 */ MCD_OPC_Decode, 198, 21, 97, // Opcode: RETAB +/* 69367 */ MCD_OPC_FilterValue, 20, 46, 0, 0, // Skip to: 69418 +/* 69372 */ MCD_OPC_ExtractField, 0, 21, // Inst{20-0} ... +/* 69375 */ MCD_OPC_FilterValue, 224, 135, 124, 4, 0, 0, // Skip to: 69386 +/* 69382 */ MCD_OPC_Decode, 247, 5, 97, // Opcode: ERET +/* 69386 */ MCD_OPC_FilterValue, 255, 151, 124, 9, 0, 0, // Skip to: 69402 +/* 69393 */ MCD_OPC_CheckPredicate, 13, 142, 68, 0, // Skip to: 86948 +/* 69398 */ MCD_OPC_Decode, 248, 5, 97, // Opcode: ERETAA +/* 69402 */ MCD_OPC_FilterValue, 255, 159, 124, 131, 68, 0, // Skip to: 86948 +/* 69409 */ MCD_OPC_CheckPredicate, 13, 126, 68, 0, // Skip to: 86948 +/* 69414 */ MCD_OPC_Decode, 249, 5, 97, // Opcode: ERETAB +/* 69418 */ MCD_OPC_FilterValue, 21, 13, 0, 0, // Skip to: 69436 +/* 69423 */ MCD_OPC_CheckField, 0, 21, 224, 135, 124, 108, 68, 0, // Skip to: 86948 +/* 69432 */ MCD_OPC_Decode, 192, 5, 97, // Opcode: DRPS +/* 69436 */ MCD_OPC_FilterValue, 24, 35, 0, 0, // Skip to: 69476 +/* 69441 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 69444 */ MCD_OPC_FilterValue, 194, 15, 10, 0, 0, // Skip to: 69460 +/* 69450 */ MCD_OPC_CheckPredicate, 13, 85, 68, 0, // Skip to: 86948 +/* 69455 */ MCD_OPC_Decode, 204, 2, 254, 2, // Opcode: BRAA +/* 69460 */ MCD_OPC_FilterValue, 195, 15, 74, 68, 0, // Skip to: 86948 +/* 69466 */ MCD_OPC_CheckPredicate, 13, 69, 68, 0, // Skip to: 86948 +/* 69471 */ MCD_OPC_Decode, 206, 2, 254, 2, // Opcode: BRAB +/* 69476 */ MCD_OPC_FilterValue, 25, 59, 68, 0, // Skip to: 86948 +/* 69481 */ MCD_OPC_ExtractField, 10, 11, // Inst{20-10} ... +/* 69484 */ MCD_OPC_FilterValue, 194, 15, 10, 0, 0, // Skip to: 69500 +/* 69490 */ MCD_OPC_CheckPredicate, 13, 45, 68, 0, // Skip to: 86948 +/* 69495 */ MCD_OPC_Decode, 199, 2, 254, 2, // Opcode: BLRAA +/* 69500 */ MCD_OPC_FilterValue, 195, 15, 34, 68, 0, // Skip to: 86948 +/* 69506 */ MCD_OPC_CheckPredicate, 13, 29, 68, 0, // Skip to: 86948 +/* 69511 */ MCD_OPC_Decode, 201, 2, 254, 2, // Opcode: BLRAB +/* 69516 */ MCD_OPC_FilterValue, 6, 115, 24, 0, // Skip to: 75780 +/* 69521 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 69524 */ MCD_OPC_FilterValue, 0, 180, 1, 0, // Skip to: 69965 +/* 69529 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 69532 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 69542 +/* 69537 */ MCD_OPC_Decode, 155, 18, 241, 2, // Opcode: LDRWl +/* 69542 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 69638 +/* 69547 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 69550 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 69572 +/* 69555 */ MCD_OPC_CheckPredicate, 12, 236, 67, 0, // Skip to: 86948 +/* 69560 */ MCD_OPC_CheckField, 10, 2, 0, 229, 67, 0, // Skip to: 86948 +/* 69567 */ MCD_OPC_Decode, 235, 28, 255, 2, // Opcode: STLURBi +/* 69572 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 69594 +/* 69577 */ MCD_OPC_CheckPredicate, 12, 214, 67, 0, // Skip to: 86948 +/* 69582 */ MCD_OPC_CheckField, 10, 2, 0, 207, 67, 0, // Skip to: 86948 +/* 69589 */ MCD_OPC_Decode, 225, 16, 255, 2, // Opcode: LDAPURBi +/* 69594 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 69616 +/* 69599 */ MCD_OPC_CheckPredicate, 12, 192, 67, 0, // Skip to: 86948 +/* 69604 */ MCD_OPC_CheckField, 10, 2, 0, 185, 67, 0, // Skip to: 86948 +/* 69611 */ MCD_OPC_Decode, 228, 16, 255, 2, // Opcode: LDAPURSBXi +/* 69616 */ MCD_OPC_FilterValue, 6, 175, 67, 0, // Skip to: 86948 +/* 69621 */ MCD_OPC_CheckPredicate, 12, 170, 67, 0, // Skip to: 86948 +/* 69626 */ MCD_OPC_CheckField, 10, 2, 0, 163, 67, 0, // Skip to: 86948 +/* 69633 */ MCD_OPC_Decode, 227, 16, 255, 2, // Opcode: LDAPURSBWi +/* 69638 */ MCD_OPC_FilterValue, 2, 24, 1, 0, // Skip to: 69923 +/* 69643 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 69646 */ MCD_OPC_FilterValue, 0, 78, 0, 0, // Skip to: 69729 +/* 69651 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 69654 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69671 +/* 69659 */ MCD_OPC_CheckField, 12, 4, 0, 130, 67, 0, // Skip to: 86948 +/* 69666 */ MCD_OPC_Decode, 140, 1, 128, 3, // Opcode: ADCWr +/* 69671 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 69681 +/* 69676 */ MCD_OPC_Decode, 161, 5, 129, 3, // Opcode: CSELWr +/* 69681 */ MCD_OPC_FilterValue, 6, 110, 67, 0, // Skip to: 86948 +/* 69686 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 69689 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 69699 +/* 69694 */ MCD_OPC_Decode, 155, 19, 128, 3, // Opcode: LSLVWr +/* 69699 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 69714 +/* 69704 */ MCD_OPC_CheckPredicate, 14, 87, 67, 0, // Skip to: 86948 +/* 69709 */ MCD_OPC_Decode, 153, 5, 128, 3, // Opcode: CRC32Brr +/* 69714 */ MCD_OPC_FilterValue, 5, 77, 67, 0, // Skip to: 86948 +/* 69719 */ MCD_OPC_CheckPredicate, 14, 72, 67, 0, // Skip to: 86948 +/* 69724 */ MCD_OPC_Decode, 154, 5, 128, 3, // Opcode: CRC32CBrr +/* 69729 */ MCD_OPC_FilterValue, 1, 61, 0, 0, // Skip to: 69795 +/* 69734 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 69737 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 69747 +/* 69742 */ MCD_OPC_Decode, 163, 5, 129, 3, // Opcode: CSINCWr +/* 69747 */ MCD_OPC_FilterValue, 6, 44, 67, 0, // Skip to: 86948 +/* 69752 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 69755 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 69765 +/* 69760 */ MCD_OPC_Decode, 179, 19, 128, 3, // Opcode: LSRVWr +/* 69765 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 69780 +/* 69770 */ MCD_OPC_CheckPredicate, 14, 21, 67, 0, // Skip to: 86948 +/* 69775 */ MCD_OPC_Decode, 158, 5, 128, 3, // Opcode: CRC32Hrr +/* 69780 */ MCD_OPC_FilterValue, 5, 11, 67, 0, // Skip to: 86948 +/* 69785 */ MCD_OPC_CheckPredicate, 14, 6, 67, 0, // Skip to: 86948 +/* 69790 */ MCD_OPC_Decode, 155, 5, 128, 3, // Opcode: CRC32CHrr +/* 69795 */ MCD_OPC_FilterValue, 2, 81, 0, 0, // Skip to: 69881 +/* 69800 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 69803 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69820 +/* 69808 */ MCD_OPC_CheckField, 21, 3, 6, 237, 66, 0, // Skip to: 86948 +/* 69815 */ MCD_OPC_Decode, 208, 31, 128, 3, // Opcode: UDIVWr +/* 69820 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 69837 +/* 69825 */ MCD_OPC_CheckField, 21, 3, 6, 220, 66, 0, // Skip to: 86948 +/* 69832 */ MCD_OPC_Decode, 134, 2, 128, 3, // Opcode: ASRVWr +/* 69837 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 69859 +/* 69842 */ MCD_OPC_CheckPredicate, 14, 205, 66, 0, // Skip to: 86948 +/* 69847 */ MCD_OPC_CheckField, 21, 3, 6, 198, 66, 0, // Skip to: 86948 +/* 69854 */ MCD_OPC_Decode, 159, 5, 128, 3, // Opcode: CRC32Wrr +/* 69859 */ MCD_OPC_FilterValue, 5, 188, 66, 0, // Skip to: 86948 +/* 69864 */ MCD_OPC_CheckPredicate, 14, 183, 66, 0, // Skip to: 86948 +/* 69869 */ MCD_OPC_CheckField, 21, 3, 6, 176, 66, 0, // Skip to: 86948 +/* 69876 */ MCD_OPC_Decode, 156, 5, 128, 3, // Opcode: CRC32CWrr +/* 69881 */ MCD_OPC_FilterValue, 3, 166, 66, 0, // Skip to: 86948 +/* 69886 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 69889 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69906 +/* 69894 */ MCD_OPC_CheckField, 21, 3, 6, 151, 66, 0, // Skip to: 86948 +/* 69901 */ MCD_OPC_Decode, 221, 22, 128, 3, // Opcode: SDIVWr +/* 69906 */ MCD_OPC_FilterValue, 2, 141, 66, 0, // Skip to: 86948 +/* 69911 */ MCD_OPC_CheckField, 21, 3, 6, 134, 66, 0, // Skip to: 86948 +/* 69918 */ MCD_OPC_Decode, 232, 21, 128, 3, // Opcode: RORVWr +/* 69923 */ MCD_OPC_FilterValue, 3, 124, 66, 0, // Skip to: 86948 +/* 69928 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 69931 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 69948 +/* 69936 */ MCD_OPC_CheckField, 21, 3, 0, 109, 66, 0, // Skip to: 86948 +/* 69943 */ MCD_OPC_Decode, 199, 19, 130, 3, // Opcode: MADDWrrr +/* 69948 */ MCD_OPC_FilterValue, 1, 99, 66, 0, // Skip to: 86948 +/* 69953 */ MCD_OPC_CheckField, 21, 3, 0, 92, 66, 0, // Skip to: 86948 +/* 69960 */ MCD_OPC_Decode, 147, 20, 130, 3, // Opcode: MSUBWrrr +/* 69965 */ MCD_OPC_FilterValue, 1, 176, 4, 0, // Skip to: 71170 +/* 69970 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 69973 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 70222 +/* 69978 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 69981 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70142 +/* 69986 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 69989 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 69999 +/* 69994 */ MCD_OPC_Decode, 196, 29, 255, 2, // Opcode: STURBBi +/* 69999 */ MCD_OPC_FilterValue, 1, 48, 66, 0, // Skip to: 86948 +/* 70004 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 70007 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70022 +/* 70012 */ MCD_OPC_CheckPredicate, 1, 35, 66, 0, // Skip to: 86948 +/* 70017 */ MCD_OPC_Decode, 213, 16, 131, 3, // Opcode: LDADDB +/* 70022 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70037 +/* 70027 */ MCD_OPC_CheckPredicate, 1, 20, 66, 0, // Skip to: 86948 +/* 70032 */ MCD_OPC_Decode, 252, 16, 131, 3, // Opcode: LDCLRB +/* 70037 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70052 +/* 70042 */ MCD_OPC_CheckPredicate, 1, 5, 66, 0, // Skip to: 86948 +/* 70047 */ MCD_OPC_Decode, 140, 17, 131, 3, // Opcode: LDEORB +/* 70052 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70067 +/* 70057 */ MCD_OPC_CheckPredicate, 1, 246, 65, 0, // Skip to: 86948 +/* 70062 */ MCD_OPC_Decode, 177, 18, 131, 3, // Opcode: LDSETB +/* 70067 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70082 +/* 70072 */ MCD_OPC_CheckPredicate, 1, 231, 65, 0, // Skip to: 86948 +/* 70077 */ MCD_OPC_Decode, 193, 18, 131, 3, // Opcode: LDSMAXB +/* 70082 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70097 +/* 70087 */ MCD_OPC_CheckPredicate, 1, 216, 65, 0, // Skip to: 86948 +/* 70092 */ MCD_OPC_Decode, 209, 18, 131, 3, // Opcode: LDSMINB +/* 70097 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70112 +/* 70102 */ MCD_OPC_CheckPredicate, 1, 201, 65, 0, // Skip to: 86948 +/* 70107 */ MCD_OPC_Decode, 234, 18, 131, 3, // Opcode: LDUMAXB +/* 70112 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70127 +/* 70117 */ MCD_OPC_CheckPredicate, 1, 186, 65, 0, // Skip to: 86948 +/* 70122 */ MCD_OPC_Decode, 250, 18, 131, 3, // Opcode: LDUMINB +/* 70127 */ MCD_OPC_FilterValue, 8, 176, 65, 0, // Skip to: 86948 +/* 70132 */ MCD_OPC_CheckPredicate, 1, 171, 65, 0, // Skip to: 86948 +/* 70137 */ MCD_OPC_Decode, 161, 30, 131, 3, // Opcode: SWPB +/* 70142 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70159 +/* 70147 */ MCD_OPC_CheckField, 21, 1, 0, 154, 65, 0, // Skip to: 86948 +/* 70154 */ MCD_OPC_Decode, 145, 29, 255, 2, // Opcode: STRBBpost +/* 70159 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70205 +/* 70164 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70167 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70177 +/* 70172 */ MCD_OPC_Decode, 192, 29, 255, 2, // Opcode: STTRBi +/* 70177 */ MCD_OPC_FilterValue, 1, 126, 65, 0, // Skip to: 86948 +/* 70182 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 70185 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70195 +/* 70190 */ MCD_OPC_Decode, 147, 29, 132, 3, // Opcode: STRBBroW +/* 70195 */ MCD_OPC_FilterValue, 3, 108, 65, 0, // Skip to: 86948 +/* 70200 */ MCD_OPC_Decode, 148, 29, 133, 3, // Opcode: STRBBroX +/* 70205 */ MCD_OPC_FilterValue, 3, 98, 65, 0, // Skip to: 86948 +/* 70210 */ MCD_OPC_CheckField, 21, 1, 0, 91, 65, 0, // Skip to: 86948 +/* 70217 */ MCD_OPC_Decode, 146, 29, 255, 2, // Opcode: STRBBpre +/* 70222 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 70471 +/* 70227 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 70230 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70391 +/* 70235 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70238 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70248 +/* 70243 */ MCD_OPC_Decode, 130, 19, 255, 2, // Opcode: LDURBBi +/* 70248 */ MCD_OPC_FilterValue, 1, 55, 65, 0, // Skip to: 86948 +/* 70253 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 70256 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70271 +/* 70261 */ MCD_OPC_CheckPredicate, 1, 42, 65, 0, // Skip to: 86948 +/* 70266 */ MCD_OPC_Decode, 215, 16, 131, 3, // Opcode: LDADDLB +/* 70271 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70286 +/* 70276 */ MCD_OPC_CheckPredicate, 1, 27, 65, 0, // Skip to: 86948 +/* 70281 */ MCD_OPC_Decode, 254, 16, 131, 3, // Opcode: LDCLRLB +/* 70286 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70301 +/* 70291 */ MCD_OPC_CheckPredicate, 1, 12, 65, 0, // Skip to: 86948 +/* 70296 */ MCD_OPC_Decode, 142, 17, 131, 3, // Opcode: LDEORLB +/* 70301 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70316 +/* 70306 */ MCD_OPC_CheckPredicate, 1, 253, 64, 0, // Skip to: 86948 +/* 70311 */ MCD_OPC_Decode, 179, 18, 131, 3, // Opcode: LDSETLB +/* 70316 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70331 +/* 70321 */ MCD_OPC_CheckPredicate, 1, 238, 64, 0, // Skip to: 86948 +/* 70326 */ MCD_OPC_Decode, 195, 18, 131, 3, // Opcode: LDSMAXLB +/* 70331 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70346 +/* 70336 */ MCD_OPC_CheckPredicate, 1, 223, 64, 0, // Skip to: 86948 +/* 70341 */ MCD_OPC_Decode, 211, 18, 131, 3, // Opcode: LDSMINLB +/* 70346 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70361 +/* 70351 */ MCD_OPC_CheckPredicate, 1, 208, 64, 0, // Skip to: 86948 +/* 70356 */ MCD_OPC_Decode, 236, 18, 131, 3, // Opcode: LDUMAXLB +/* 70361 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70376 +/* 70366 */ MCD_OPC_CheckPredicate, 1, 193, 64, 0, // Skip to: 86948 +/* 70371 */ MCD_OPC_Decode, 252, 18, 131, 3, // Opcode: LDUMINLB +/* 70376 */ MCD_OPC_FilterValue, 8, 183, 64, 0, // Skip to: 86948 +/* 70381 */ MCD_OPC_CheckPredicate, 1, 178, 64, 0, // Skip to: 86948 +/* 70386 */ MCD_OPC_Decode, 163, 30, 131, 3, // Opcode: SWPLB +/* 70391 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70408 +/* 70396 */ MCD_OPC_CheckField, 21, 1, 0, 161, 64, 0, // Skip to: 86948 +/* 70403 */ MCD_OPC_Decode, 219, 17, 255, 2, // Opcode: LDRBBpost +/* 70408 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70454 +/* 70413 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70416 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70426 +/* 70421 */ MCD_OPC_Decode, 217, 18, 255, 2, // Opcode: LDTRBi +/* 70426 */ MCD_OPC_FilterValue, 1, 133, 64, 0, // Skip to: 86948 +/* 70431 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 70434 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70444 +/* 70439 */ MCD_OPC_Decode, 221, 17, 132, 3, // Opcode: LDRBBroW +/* 70444 */ MCD_OPC_FilterValue, 3, 115, 64, 0, // Skip to: 86948 +/* 70449 */ MCD_OPC_Decode, 222, 17, 133, 3, // Opcode: LDRBBroX +/* 70454 */ MCD_OPC_FilterValue, 3, 105, 64, 0, // Skip to: 86948 +/* 70459 */ MCD_OPC_CheckField, 21, 1, 0, 98, 64, 0, // Skip to: 86948 +/* 70466 */ MCD_OPC_Decode, 220, 17, 255, 2, // Opcode: LDRBBpre +/* 70471 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 70742 +/* 70476 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 70479 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 70662 +/* 70484 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70487 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70497 +/* 70492 */ MCD_OPC_Decode, 137, 19, 255, 2, // Opcode: LDURSBXi +/* 70497 */ MCD_OPC_FilterValue, 1, 62, 64, 0, // Skip to: 86948 +/* 70502 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 70505 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70520 +/* 70510 */ MCD_OPC_CheckPredicate, 1, 49, 64, 0, // Skip to: 86948 +/* 70515 */ MCD_OPC_Decode, 205, 16, 131, 3, // Opcode: LDADDAB +/* 70520 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70535 +/* 70525 */ MCD_OPC_CheckPredicate, 1, 34, 64, 0, // Skip to: 86948 +/* 70530 */ MCD_OPC_Decode, 244, 16, 131, 3, // Opcode: LDCLRAB +/* 70535 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70550 +/* 70540 */ MCD_OPC_CheckPredicate, 1, 19, 64, 0, // Skip to: 86948 +/* 70545 */ MCD_OPC_Decode, 132, 17, 131, 3, // Opcode: LDEORAB +/* 70550 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70565 +/* 70555 */ MCD_OPC_CheckPredicate, 1, 4, 64, 0, // Skip to: 86948 +/* 70560 */ MCD_OPC_Decode, 169, 18, 131, 3, // Opcode: LDSETAB +/* 70565 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70580 +/* 70570 */ MCD_OPC_CheckPredicate, 1, 245, 63, 0, // Skip to: 86948 +/* 70575 */ MCD_OPC_Decode, 185, 18, 131, 3, // Opcode: LDSMAXAB +/* 70580 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70595 +/* 70585 */ MCD_OPC_CheckPredicate, 1, 230, 63, 0, // Skip to: 86948 +/* 70590 */ MCD_OPC_Decode, 201, 18, 131, 3, // Opcode: LDSMINAB +/* 70595 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70610 +/* 70600 */ MCD_OPC_CheckPredicate, 1, 215, 63, 0, // Skip to: 86948 +/* 70605 */ MCD_OPC_Decode, 226, 18, 131, 3, // Opcode: LDUMAXAB +/* 70610 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70625 +/* 70615 */ MCD_OPC_CheckPredicate, 1, 200, 63, 0, // Skip to: 86948 +/* 70620 */ MCD_OPC_Decode, 242, 18, 131, 3, // Opcode: LDUMINAB +/* 70625 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 70640 +/* 70630 */ MCD_OPC_CheckPredicate, 1, 185, 63, 0, // Skip to: 86948 +/* 70635 */ MCD_OPC_Decode, 153, 30, 131, 3, // Opcode: SWPAB +/* 70640 */ MCD_OPC_FilterValue, 12, 175, 63, 0, // Skip to: 86948 +/* 70645 */ MCD_OPC_CheckPredicate, 15, 170, 63, 0, // Skip to: 86948 +/* 70650 */ MCD_OPC_CheckField, 16, 5, 31, 163, 63, 0, // Skip to: 86948 +/* 70657 */ MCD_OPC_Decode, 221, 16, 134, 3, // Opcode: LDAPRB +/* 70662 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70679 +/* 70667 */ MCD_OPC_CheckField, 21, 1, 0, 146, 63, 0, // Skip to: 86948 +/* 70674 */ MCD_OPC_Decode, 128, 18, 255, 2, // Opcode: LDRSBXpost +/* 70679 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70725 +/* 70684 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70687 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70697 +/* 70692 */ MCD_OPC_Decode, 220, 18, 255, 2, // Opcode: LDTRSBXi +/* 70697 */ MCD_OPC_FilterValue, 1, 118, 63, 0, // Skip to: 86948 +/* 70702 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 70705 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70715 +/* 70710 */ MCD_OPC_Decode, 130, 18, 135, 3, // Opcode: LDRSBXroW +/* 70715 */ MCD_OPC_FilterValue, 3, 100, 63, 0, // Skip to: 86948 +/* 70720 */ MCD_OPC_Decode, 131, 18, 136, 3, // Opcode: LDRSBXroX +/* 70725 */ MCD_OPC_FilterValue, 3, 90, 63, 0, // Skip to: 86948 +/* 70730 */ MCD_OPC_CheckField, 21, 1, 0, 83, 63, 0, // Skip to: 86948 +/* 70737 */ MCD_OPC_Decode, 129, 18, 255, 2, // Opcode: LDRSBXpre +/* 70742 */ MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 70991 +/* 70747 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 70750 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 70911 +/* 70755 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70758 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70768 +/* 70763 */ MCD_OPC_Decode, 136, 19, 255, 2, // Opcode: LDURSBWi +/* 70768 */ MCD_OPC_FilterValue, 1, 47, 63, 0, // Skip to: 86948 +/* 70773 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 70776 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 70791 +/* 70781 */ MCD_OPC_CheckPredicate, 1, 34, 63, 0, // Skip to: 86948 +/* 70786 */ MCD_OPC_Decode, 207, 16, 131, 3, // Opcode: LDADDALB +/* 70791 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 70806 +/* 70796 */ MCD_OPC_CheckPredicate, 1, 19, 63, 0, // Skip to: 86948 +/* 70801 */ MCD_OPC_Decode, 246, 16, 131, 3, // Opcode: LDCLRALB +/* 70806 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 70821 +/* 70811 */ MCD_OPC_CheckPredicate, 1, 4, 63, 0, // Skip to: 86948 +/* 70816 */ MCD_OPC_Decode, 134, 17, 131, 3, // Opcode: LDEORALB +/* 70821 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 70836 +/* 70826 */ MCD_OPC_CheckPredicate, 1, 245, 62, 0, // Skip to: 86948 +/* 70831 */ MCD_OPC_Decode, 171, 18, 131, 3, // Opcode: LDSETALB +/* 70836 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 70851 +/* 70841 */ MCD_OPC_CheckPredicate, 1, 230, 62, 0, // Skip to: 86948 +/* 70846 */ MCD_OPC_Decode, 187, 18, 131, 3, // Opcode: LDSMAXALB +/* 70851 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 70866 +/* 70856 */ MCD_OPC_CheckPredicate, 1, 215, 62, 0, // Skip to: 86948 +/* 70861 */ MCD_OPC_Decode, 203, 18, 131, 3, // Opcode: LDSMINALB +/* 70866 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 70881 +/* 70871 */ MCD_OPC_CheckPredicate, 1, 200, 62, 0, // Skip to: 86948 +/* 70876 */ MCD_OPC_Decode, 228, 18, 131, 3, // Opcode: LDUMAXALB +/* 70881 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 70896 +/* 70886 */ MCD_OPC_CheckPredicate, 1, 185, 62, 0, // Skip to: 86948 +/* 70891 */ MCD_OPC_Decode, 244, 18, 131, 3, // Opcode: LDUMINALB +/* 70896 */ MCD_OPC_FilterValue, 8, 175, 62, 0, // Skip to: 86948 +/* 70901 */ MCD_OPC_CheckPredicate, 1, 170, 62, 0, // Skip to: 86948 +/* 70906 */ MCD_OPC_Decode, 155, 30, 131, 3, // Opcode: SWPALB +/* 70911 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 70928 +/* 70916 */ MCD_OPC_CheckField, 21, 1, 0, 153, 62, 0, // Skip to: 86948 +/* 70923 */ MCD_OPC_Decode, 251, 17, 255, 2, // Opcode: LDRSBWpost +/* 70928 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 70974 +/* 70933 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 70936 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 70946 +/* 70941 */ MCD_OPC_Decode, 219, 18, 255, 2, // Opcode: LDTRSBWi +/* 70946 */ MCD_OPC_FilterValue, 1, 125, 62, 0, // Skip to: 86948 +/* 70951 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 70954 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 70964 +/* 70959 */ MCD_OPC_Decode, 253, 17, 132, 3, // Opcode: LDRSBWroW +/* 70964 */ MCD_OPC_FilterValue, 3, 107, 62, 0, // Skip to: 86948 +/* 70969 */ MCD_OPC_Decode, 254, 17, 133, 3, // Opcode: LDRSBWroX +/* 70974 */ MCD_OPC_FilterValue, 3, 97, 62, 0, // Skip to: 86948 +/* 70979 */ MCD_OPC_CheckField, 21, 1, 0, 90, 62, 0, // Skip to: 86948 +/* 70986 */ MCD_OPC_Decode, 252, 17, 255, 2, // Opcode: LDRSBWpre +/* 70991 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71001 +/* 70996 */ MCD_OPC_Decode, 149, 29, 137, 3, // Opcode: STRBBui +/* 71001 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 71011 +/* 71006 */ MCD_OPC_Decode, 223, 17, 137, 3, // Opcode: LDRBBui +/* 71011 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 71021 +/* 71016 */ MCD_OPC_Decode, 132, 18, 137, 3, // Opcode: LDRSBXui +/* 71021 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 71031 +/* 71026 */ MCD_OPC_Decode, 255, 17, 137, 3, // Opcode: LDRSBWui +/* 71031 */ MCD_OPC_FilterValue, 8, 78, 0, 0, // Skip to: 71114 +/* 71036 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 71039 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 71056 +/* 71044 */ MCD_OPC_CheckField, 21, 1, 0, 25, 62, 0, // Skip to: 86948 +/* 71051 */ MCD_OPC_Decode, 138, 1, 128, 3, // Opcode: ADCSWr +/* 71056 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 71085 +/* 71061 */ MCD_OPC_CheckPredicate, 12, 10, 62, 0, // Skip to: 86948 +/* 71066 */ MCD_OPC_CheckField, 16, 6, 0, 3, 62, 0, // Skip to: 86948 +/* 71073 */ MCD_OPC_CheckField, 0, 5, 13, 252, 61, 0, // Skip to: 86948 +/* 71080 */ MCD_OPC_Decode, 239, 22, 138, 3, // Opcode: SETF8 +/* 71085 */ MCD_OPC_FilterValue, 18, 242, 61, 0, // Skip to: 86948 +/* 71090 */ MCD_OPC_CheckPredicate, 12, 237, 61, 0, // Skip to: 86948 +/* 71095 */ MCD_OPC_CheckField, 16, 6, 0, 230, 61, 0, // Skip to: 86948 +/* 71102 */ MCD_OPC_CheckField, 0, 5, 13, 223, 61, 0, // Skip to: 86948 +/* 71109 */ MCD_OPC_Decode, 238, 22, 138, 3, // Opcode: SETF16 +/* 71114 */ MCD_OPC_FilterValue, 9, 213, 61, 0, // Skip to: 86948 +/* 71119 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 71122 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 71146 +/* 71127 */ MCD_OPC_CheckField, 21, 1, 0, 198, 61, 0, // Skip to: 86948 +/* 71134 */ MCD_OPC_CheckField, 4, 1, 0, 191, 61, 0, // Skip to: 86948 +/* 71141 */ MCD_OPC_Decode, 253, 2, 139, 3, // Opcode: CCMNWr +/* 71146 */ MCD_OPC_FilterValue, 2, 181, 61, 0, // Skip to: 86948 +/* 71151 */ MCD_OPC_CheckField, 21, 1, 0, 174, 61, 0, // Skip to: 86948 +/* 71158 */ MCD_OPC_CheckField, 4, 1, 0, 167, 61, 0, // Skip to: 86948 +/* 71165 */ MCD_OPC_Decode, 252, 2, 140, 3, // Opcode: CCMNWi +/* 71170 */ MCD_OPC_FilterValue, 2, 244, 0, 0, // Skip to: 71419 +/* 71175 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 71178 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71188 +/* 71183 */ MCD_OPC_Decode, 161, 18, 244, 2, // Opcode: LDRXl +/* 71188 */ MCD_OPC_FilterValue, 1, 91, 0, 0, // Skip to: 71284 +/* 71193 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 71196 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 71218 +/* 71201 */ MCD_OPC_CheckPredicate, 12, 126, 61, 0, // Skip to: 86948 +/* 71206 */ MCD_OPC_CheckField, 10, 2, 0, 119, 61, 0, // Skip to: 86948 +/* 71213 */ MCD_OPC_Decode, 236, 28, 255, 2, // Opcode: STLURHi +/* 71218 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 71240 +/* 71223 */ MCD_OPC_CheckPredicate, 12, 104, 61, 0, // Skip to: 86948 +/* 71228 */ MCD_OPC_CheckField, 10, 2, 0, 97, 61, 0, // Skip to: 86948 +/* 71235 */ MCD_OPC_Decode, 226, 16, 255, 2, // Opcode: LDAPURHi +/* 71240 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 71262 +/* 71245 */ MCD_OPC_CheckPredicate, 12, 82, 61, 0, // Skip to: 86948 +/* 71250 */ MCD_OPC_CheckField, 10, 2, 0, 75, 61, 0, // Skip to: 86948 +/* 71257 */ MCD_OPC_Decode, 230, 16, 255, 2, // Opcode: LDAPURSHXi +/* 71262 */ MCD_OPC_FilterValue, 6, 65, 61, 0, // Skip to: 86948 +/* 71267 */ MCD_OPC_CheckPredicate, 12, 60, 61, 0, // Skip to: 86948 +/* 71272 */ MCD_OPC_CheckField, 10, 2, 0, 53, 61, 0, // Skip to: 86948 +/* 71279 */ MCD_OPC_Decode, 229, 16, 255, 2, // Opcode: LDAPURSHWi +/* 71284 */ MCD_OPC_FilterValue, 2, 43, 61, 0, // Skip to: 86948 +/* 71289 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 71292 */ MCD_OPC_FilterValue, 0, 58, 0, 0, // Skip to: 71355 +/* 71297 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 71300 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 71317 +/* 71305 */ MCD_OPC_CheckField, 12, 4, 0, 20, 61, 0, // Skip to: 86948 +/* 71312 */ MCD_OPC_Decode, 180, 22, 128, 3, // Opcode: SBCWr +/* 71317 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71327 +/* 71322 */ MCD_OPC_Decode, 165, 5, 129, 3, // Opcode: CSINVWr +/* 71327 */ MCD_OPC_FilterValue, 6, 0, 61, 0, // Skip to: 86948 +/* 71332 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 71335 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71345 +/* 71340 */ MCD_OPC_Decode, 184, 21, 141, 3, // Opcode: RBITWr +/* 71345 */ MCD_OPC_FilterValue, 1, 238, 60, 0, // Skip to: 86948 +/* 71350 */ MCD_OPC_Decode, 170, 3, 141, 3, // Opcode: CLZWr +/* 71355 */ MCD_OPC_FilterValue, 1, 41, 0, 0, // Skip to: 71401 +/* 71360 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 71363 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 71373 +/* 71368 */ MCD_OPC_Decode, 167, 5, 129, 3, // Opcode: CSNEGWr +/* 71373 */ MCD_OPC_FilterValue, 6, 210, 60, 0, // Skip to: 86948 +/* 71378 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 71381 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71391 +/* 71386 */ MCD_OPC_Decode, 200, 21, 141, 3, // Opcode: REV16Wr +/* 71391 */ MCD_OPC_FilterValue, 1, 192, 60, 0, // Skip to: 86948 +/* 71396 */ MCD_OPC_Decode, 158, 3, 141, 3, // Opcode: CLSWr +/* 71401 */ MCD_OPC_FilterValue, 2, 182, 60, 0, // Skip to: 86948 +/* 71406 */ MCD_OPC_CheckField, 12, 12, 128, 24, 174, 60, 0, // Skip to: 86948 +/* 71414 */ MCD_OPC_Decode, 221, 21, 141, 3, // Opcode: REVWr +/* 71419 */ MCD_OPC_FilterValue, 3, 117, 4, 0, // Skip to: 72565 +/* 71424 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 71427 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 71676 +/* 71432 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 71435 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 71596 +/* 71440 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 71443 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71453 +/* 71448 */ MCD_OPC_Decode, 199, 29, 255, 2, // Opcode: STURHHi +/* 71453 */ MCD_OPC_FilterValue, 1, 130, 60, 0, // Skip to: 86948 +/* 71458 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 71461 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71476 +/* 71466 */ MCD_OPC_CheckPredicate, 1, 117, 60, 0, // Skip to: 86948 +/* 71471 */ MCD_OPC_Decode, 214, 16, 131, 3, // Opcode: LDADDH +/* 71476 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71491 +/* 71481 */ MCD_OPC_CheckPredicate, 1, 102, 60, 0, // Skip to: 86948 +/* 71486 */ MCD_OPC_Decode, 253, 16, 131, 3, // Opcode: LDCLRH +/* 71491 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 71506 +/* 71496 */ MCD_OPC_CheckPredicate, 1, 87, 60, 0, // Skip to: 86948 +/* 71501 */ MCD_OPC_Decode, 141, 17, 131, 3, // Opcode: LDEORH +/* 71506 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 71521 +/* 71511 */ MCD_OPC_CheckPredicate, 1, 72, 60, 0, // Skip to: 86948 +/* 71516 */ MCD_OPC_Decode, 178, 18, 131, 3, // Opcode: LDSETH +/* 71521 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 71536 +/* 71526 */ MCD_OPC_CheckPredicate, 1, 57, 60, 0, // Skip to: 86948 +/* 71531 */ MCD_OPC_Decode, 194, 18, 131, 3, // Opcode: LDSMAXH +/* 71536 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 71551 +/* 71541 */ MCD_OPC_CheckPredicate, 1, 42, 60, 0, // Skip to: 86948 +/* 71546 */ MCD_OPC_Decode, 210, 18, 131, 3, // Opcode: LDSMINH +/* 71551 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 71566 +/* 71556 */ MCD_OPC_CheckPredicate, 1, 27, 60, 0, // Skip to: 86948 +/* 71561 */ MCD_OPC_Decode, 235, 18, 131, 3, // Opcode: LDUMAXH +/* 71566 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 71581 +/* 71571 */ MCD_OPC_CheckPredicate, 1, 12, 60, 0, // Skip to: 86948 +/* 71576 */ MCD_OPC_Decode, 251, 18, 131, 3, // Opcode: LDUMINH +/* 71581 */ MCD_OPC_FilterValue, 8, 2, 60, 0, // Skip to: 86948 +/* 71586 */ MCD_OPC_CheckPredicate, 1, 253, 59, 0, // Skip to: 86948 +/* 71591 */ MCD_OPC_Decode, 162, 30, 131, 3, // Opcode: SWPH +/* 71596 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 71613 +/* 71601 */ MCD_OPC_CheckField, 21, 1, 0, 236, 59, 0, // Skip to: 86948 +/* 71608 */ MCD_OPC_Decode, 160, 29, 255, 2, // Opcode: STRHHpost +/* 71613 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 71659 +/* 71618 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 71621 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71631 +/* 71626 */ MCD_OPC_Decode, 193, 29, 255, 2, // Opcode: STTRHi +/* 71631 */ MCD_OPC_FilterValue, 1, 208, 59, 0, // Skip to: 86948 +/* 71636 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 71639 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 71649 +/* 71644 */ MCD_OPC_Decode, 162, 29, 132, 3, // Opcode: STRHHroW +/* 71649 */ MCD_OPC_FilterValue, 3, 190, 59, 0, // Skip to: 86948 +/* 71654 */ MCD_OPC_Decode, 163, 29, 133, 3, // Opcode: STRHHroX +/* 71659 */ MCD_OPC_FilterValue, 3, 180, 59, 0, // Skip to: 86948 +/* 71664 */ MCD_OPC_CheckField, 21, 1, 0, 173, 59, 0, // Skip to: 86948 +/* 71671 */ MCD_OPC_Decode, 161, 29, 255, 2, // Opcode: STRHHpre +/* 71676 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 71925 +/* 71681 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 71684 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 71845 +/* 71689 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 71692 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71702 +/* 71697 */ MCD_OPC_Decode, 133, 19, 255, 2, // Opcode: LDURHHi +/* 71702 */ MCD_OPC_FilterValue, 1, 137, 59, 0, // Skip to: 86948 +/* 71707 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 71710 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71725 +/* 71715 */ MCD_OPC_CheckPredicate, 1, 124, 59, 0, // Skip to: 86948 +/* 71720 */ MCD_OPC_Decode, 216, 16, 131, 3, // Opcode: LDADDLH +/* 71725 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71740 +/* 71730 */ MCD_OPC_CheckPredicate, 1, 109, 59, 0, // Skip to: 86948 +/* 71735 */ MCD_OPC_Decode, 255, 16, 131, 3, // Opcode: LDCLRLH +/* 71740 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 71755 +/* 71745 */ MCD_OPC_CheckPredicate, 1, 94, 59, 0, // Skip to: 86948 +/* 71750 */ MCD_OPC_Decode, 143, 17, 131, 3, // Opcode: LDEORLH +/* 71755 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 71770 +/* 71760 */ MCD_OPC_CheckPredicate, 1, 79, 59, 0, // Skip to: 86948 +/* 71765 */ MCD_OPC_Decode, 180, 18, 131, 3, // Opcode: LDSETLH +/* 71770 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 71785 +/* 71775 */ MCD_OPC_CheckPredicate, 1, 64, 59, 0, // Skip to: 86948 +/* 71780 */ MCD_OPC_Decode, 196, 18, 131, 3, // Opcode: LDSMAXLH +/* 71785 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 71800 +/* 71790 */ MCD_OPC_CheckPredicate, 1, 49, 59, 0, // Skip to: 86948 +/* 71795 */ MCD_OPC_Decode, 212, 18, 131, 3, // Opcode: LDSMINLH +/* 71800 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 71815 +/* 71805 */ MCD_OPC_CheckPredicate, 1, 34, 59, 0, // Skip to: 86948 +/* 71810 */ MCD_OPC_Decode, 237, 18, 131, 3, // Opcode: LDUMAXLH +/* 71815 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 71830 +/* 71820 */ MCD_OPC_CheckPredicate, 1, 19, 59, 0, // Skip to: 86948 +/* 71825 */ MCD_OPC_Decode, 253, 18, 131, 3, // Opcode: LDUMINLH +/* 71830 */ MCD_OPC_FilterValue, 8, 9, 59, 0, // Skip to: 86948 +/* 71835 */ MCD_OPC_CheckPredicate, 1, 4, 59, 0, // Skip to: 86948 +/* 71840 */ MCD_OPC_Decode, 164, 30, 131, 3, // Opcode: SWPLH +/* 71845 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 71862 +/* 71850 */ MCD_OPC_CheckField, 21, 1, 0, 243, 58, 0, // Skip to: 86948 +/* 71857 */ MCD_OPC_Decode, 235, 17, 255, 2, // Opcode: LDRHHpost +/* 71862 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 71908 +/* 71867 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 71870 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71880 +/* 71875 */ MCD_OPC_Decode, 218, 18, 255, 2, // Opcode: LDTRHi +/* 71880 */ MCD_OPC_FilterValue, 1, 215, 58, 0, // Skip to: 86948 +/* 71885 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 71888 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 71898 +/* 71893 */ MCD_OPC_Decode, 237, 17, 132, 3, // Opcode: LDRHHroW +/* 71898 */ MCD_OPC_FilterValue, 3, 197, 58, 0, // Skip to: 86948 +/* 71903 */ MCD_OPC_Decode, 238, 17, 133, 3, // Opcode: LDRHHroX +/* 71908 */ MCD_OPC_FilterValue, 3, 187, 58, 0, // Skip to: 86948 +/* 71913 */ MCD_OPC_CheckField, 21, 1, 0, 180, 58, 0, // Skip to: 86948 +/* 71920 */ MCD_OPC_Decode, 236, 17, 255, 2, // Opcode: LDRHHpre +/* 71925 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 72196 +/* 71930 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 71933 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 72116 +/* 71938 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 71941 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 71951 +/* 71946 */ MCD_OPC_Decode, 139, 19, 255, 2, // Opcode: LDURSHXi +/* 71951 */ MCD_OPC_FilterValue, 1, 144, 58, 0, // Skip to: 86948 +/* 71956 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 71959 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 71974 +/* 71964 */ MCD_OPC_CheckPredicate, 1, 131, 58, 0, // Skip to: 86948 +/* 71969 */ MCD_OPC_Decode, 206, 16, 131, 3, // Opcode: LDADDAH +/* 71974 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 71989 +/* 71979 */ MCD_OPC_CheckPredicate, 1, 116, 58, 0, // Skip to: 86948 +/* 71984 */ MCD_OPC_Decode, 245, 16, 131, 3, // Opcode: LDCLRAH +/* 71989 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 72004 +/* 71994 */ MCD_OPC_CheckPredicate, 1, 101, 58, 0, // Skip to: 86948 +/* 71999 */ MCD_OPC_Decode, 133, 17, 131, 3, // Opcode: LDEORAH +/* 72004 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 72019 +/* 72009 */ MCD_OPC_CheckPredicate, 1, 86, 58, 0, // Skip to: 86948 +/* 72014 */ MCD_OPC_Decode, 170, 18, 131, 3, // Opcode: LDSETAH +/* 72019 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 72034 +/* 72024 */ MCD_OPC_CheckPredicate, 1, 71, 58, 0, // Skip to: 86948 +/* 72029 */ MCD_OPC_Decode, 186, 18, 131, 3, // Opcode: LDSMAXAH +/* 72034 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 72049 +/* 72039 */ MCD_OPC_CheckPredicate, 1, 56, 58, 0, // Skip to: 86948 +/* 72044 */ MCD_OPC_Decode, 202, 18, 131, 3, // Opcode: LDSMINAH +/* 72049 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 72064 +/* 72054 */ MCD_OPC_CheckPredicate, 1, 41, 58, 0, // Skip to: 86948 +/* 72059 */ MCD_OPC_Decode, 227, 18, 131, 3, // Opcode: LDUMAXAH +/* 72064 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 72079 +/* 72069 */ MCD_OPC_CheckPredicate, 1, 26, 58, 0, // Skip to: 86948 +/* 72074 */ MCD_OPC_Decode, 243, 18, 131, 3, // Opcode: LDUMINAH +/* 72079 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 72094 +/* 72084 */ MCD_OPC_CheckPredicate, 1, 11, 58, 0, // Skip to: 86948 +/* 72089 */ MCD_OPC_Decode, 154, 30, 131, 3, // Opcode: SWPAH +/* 72094 */ MCD_OPC_FilterValue, 12, 1, 58, 0, // Skip to: 86948 +/* 72099 */ MCD_OPC_CheckPredicate, 15, 252, 57, 0, // Skip to: 86948 +/* 72104 */ MCD_OPC_CheckField, 16, 5, 31, 245, 57, 0, // Skip to: 86948 +/* 72111 */ MCD_OPC_Decode, 222, 16, 134, 3, // Opcode: LDAPRH +/* 72116 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 72133 +/* 72121 */ MCD_OPC_CheckField, 21, 1, 0, 228, 57, 0, // Skip to: 86948 +/* 72128 */ MCD_OPC_Decode, 138, 18, 255, 2, // Opcode: LDRSHXpost +/* 72133 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 72179 +/* 72138 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 72141 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72151 +/* 72146 */ MCD_OPC_Decode, 222, 18, 255, 2, // Opcode: LDTRSHXi +/* 72151 */ MCD_OPC_FilterValue, 1, 200, 57, 0, // Skip to: 86948 +/* 72156 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 72159 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72169 +/* 72164 */ MCD_OPC_Decode, 140, 18, 135, 3, // Opcode: LDRSHXroW +/* 72169 */ MCD_OPC_FilterValue, 3, 182, 57, 0, // Skip to: 86948 +/* 72174 */ MCD_OPC_Decode, 141, 18, 136, 3, // Opcode: LDRSHXroX +/* 72179 */ MCD_OPC_FilterValue, 3, 172, 57, 0, // Skip to: 86948 +/* 72184 */ MCD_OPC_CheckField, 21, 1, 0, 165, 57, 0, // Skip to: 86948 +/* 72191 */ MCD_OPC_Decode, 139, 18, 255, 2, // Opcode: LDRSHXpre +/* 72196 */ MCD_OPC_FilterValue, 3, 244, 0, 0, // Skip to: 72445 +/* 72201 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 72204 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 72365 +/* 72209 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 72212 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72222 +/* 72217 */ MCD_OPC_Decode, 138, 19, 255, 2, // Opcode: LDURSHWi +/* 72222 */ MCD_OPC_FilterValue, 1, 129, 57, 0, // Skip to: 86948 +/* 72227 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 72230 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 72245 +/* 72235 */ MCD_OPC_CheckPredicate, 1, 116, 57, 0, // Skip to: 86948 +/* 72240 */ MCD_OPC_Decode, 208, 16, 131, 3, // Opcode: LDADDALH +/* 72245 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 72260 +/* 72250 */ MCD_OPC_CheckPredicate, 1, 101, 57, 0, // Skip to: 86948 +/* 72255 */ MCD_OPC_Decode, 247, 16, 131, 3, // Opcode: LDCLRALH +/* 72260 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 72275 +/* 72265 */ MCD_OPC_CheckPredicate, 1, 86, 57, 0, // Skip to: 86948 +/* 72270 */ MCD_OPC_Decode, 135, 17, 131, 3, // Opcode: LDEORALH +/* 72275 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 72290 +/* 72280 */ MCD_OPC_CheckPredicate, 1, 71, 57, 0, // Skip to: 86948 +/* 72285 */ MCD_OPC_Decode, 172, 18, 131, 3, // Opcode: LDSETALH +/* 72290 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 72305 +/* 72295 */ MCD_OPC_CheckPredicate, 1, 56, 57, 0, // Skip to: 86948 +/* 72300 */ MCD_OPC_Decode, 188, 18, 131, 3, // Opcode: LDSMAXALH +/* 72305 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 72320 +/* 72310 */ MCD_OPC_CheckPredicate, 1, 41, 57, 0, // Skip to: 86948 +/* 72315 */ MCD_OPC_Decode, 204, 18, 131, 3, // Opcode: LDSMINALH +/* 72320 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 72335 +/* 72325 */ MCD_OPC_CheckPredicate, 1, 26, 57, 0, // Skip to: 86948 +/* 72330 */ MCD_OPC_Decode, 229, 18, 131, 3, // Opcode: LDUMAXALH +/* 72335 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 72350 +/* 72340 */ MCD_OPC_CheckPredicate, 1, 11, 57, 0, // Skip to: 86948 +/* 72345 */ MCD_OPC_Decode, 245, 18, 131, 3, // Opcode: LDUMINALH +/* 72350 */ MCD_OPC_FilterValue, 8, 1, 57, 0, // Skip to: 86948 +/* 72355 */ MCD_OPC_CheckPredicate, 1, 252, 56, 0, // Skip to: 86948 +/* 72360 */ MCD_OPC_Decode, 156, 30, 131, 3, // Opcode: SWPALH +/* 72365 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 72382 +/* 72370 */ MCD_OPC_CheckField, 21, 1, 0, 235, 56, 0, // Skip to: 86948 +/* 72377 */ MCD_OPC_Decode, 133, 18, 255, 2, // Opcode: LDRSHWpost +/* 72382 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 72428 +/* 72387 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 72390 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72400 +/* 72395 */ MCD_OPC_Decode, 221, 18, 255, 2, // Opcode: LDTRSHWi +/* 72400 */ MCD_OPC_FilterValue, 1, 207, 56, 0, // Skip to: 86948 +/* 72405 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 72408 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72418 +/* 72413 */ MCD_OPC_Decode, 135, 18, 132, 3, // Opcode: LDRSHWroW +/* 72418 */ MCD_OPC_FilterValue, 3, 189, 56, 0, // Skip to: 86948 +/* 72423 */ MCD_OPC_Decode, 136, 18, 133, 3, // Opcode: LDRSHWroX +/* 72428 */ MCD_OPC_FilterValue, 3, 179, 56, 0, // Skip to: 86948 +/* 72433 */ MCD_OPC_CheckField, 21, 1, 0, 172, 56, 0, // Skip to: 86948 +/* 72440 */ MCD_OPC_Decode, 134, 18, 255, 2, // Opcode: LDRSHWpre +/* 72445 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72455 +/* 72450 */ MCD_OPC_Decode, 164, 29, 137, 3, // Opcode: STRHHui +/* 72455 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 72465 +/* 72460 */ MCD_OPC_Decode, 239, 17, 137, 3, // Opcode: LDRHHui +/* 72465 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 72475 +/* 72470 */ MCD_OPC_Decode, 142, 18, 137, 3, // Opcode: LDRSHXui +/* 72475 */ MCD_OPC_FilterValue, 7, 5, 0, 0, // Skip to: 72485 +/* 72480 */ MCD_OPC_Decode, 137, 18, 137, 3, // Opcode: LDRSHWui +/* 72485 */ MCD_OPC_FilterValue, 8, 19, 0, 0, // Skip to: 72509 +/* 72490 */ MCD_OPC_CheckField, 21, 1, 0, 115, 56, 0, // Skip to: 86948 +/* 72497 */ MCD_OPC_CheckField, 10, 6, 0, 108, 56, 0, // Skip to: 86948 +/* 72504 */ MCD_OPC_Decode, 178, 22, 128, 3, // Opcode: SBCSWr +/* 72509 */ MCD_OPC_FilterValue, 9, 98, 56, 0, // Skip to: 86948 +/* 72514 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 72517 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 72541 +/* 72522 */ MCD_OPC_CheckField, 21, 1, 0, 83, 56, 0, // Skip to: 86948 +/* 72529 */ MCD_OPC_CheckField, 4, 1, 0, 76, 56, 0, // Skip to: 86948 +/* 72536 */ MCD_OPC_Decode, 129, 3, 139, 3, // Opcode: CCMPWr +/* 72541 */ MCD_OPC_FilterValue, 2, 66, 56, 0, // Skip to: 86948 +/* 72546 */ MCD_OPC_CheckField, 21, 1, 0, 59, 56, 0, // Skip to: 86948 +/* 72553 */ MCD_OPC_CheckField, 4, 1, 0, 52, 56, 0, // Skip to: 86948 +/* 72560 */ MCD_OPC_Decode, 128, 3, 140, 3, // Opcode: CCMPWi +/* 72565 */ MCD_OPC_FilterValue, 4, 196, 1, 0, // Skip to: 73022 +/* 72570 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 72573 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72583 +/* 72578 */ MCD_OPC_Decode, 143, 18, 244, 2, // Opcode: LDRSWl +/* 72583 */ MCD_OPC_FilterValue, 1, 69, 0, 0, // Skip to: 72657 +/* 72588 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 72591 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 72613 +/* 72596 */ MCD_OPC_CheckPredicate, 12, 11, 56, 0, // Skip to: 86948 +/* 72601 */ MCD_OPC_CheckField, 10, 2, 0, 4, 56, 0, // Skip to: 86948 +/* 72608 */ MCD_OPC_Decode, 237, 28, 255, 2, // Opcode: STLURWi +/* 72613 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 72635 +/* 72618 */ MCD_OPC_CheckPredicate, 12, 245, 55, 0, // Skip to: 86948 +/* 72623 */ MCD_OPC_CheckField, 10, 2, 0, 238, 55, 0, // Skip to: 86948 +/* 72630 */ MCD_OPC_Decode, 233, 16, 255, 2, // Opcode: LDAPURi +/* 72635 */ MCD_OPC_FilterValue, 4, 228, 55, 0, // Skip to: 86948 +/* 72640 */ MCD_OPC_CheckPredicate, 12, 223, 55, 0, // Skip to: 86948 +/* 72645 */ MCD_OPC_CheckField, 10, 2, 0, 216, 55, 0, // Skip to: 86948 +/* 72652 */ MCD_OPC_Decode, 231, 16, 255, 2, // Opcode: LDAPURSWi +/* 72657 */ MCD_OPC_FilterValue, 2, 234, 0, 0, // Skip to: 72896 +/* 72662 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 72665 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 72733 +/* 72670 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 72673 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72690 +/* 72678 */ MCD_OPC_CheckField, 12, 4, 0, 183, 55, 0, // Skip to: 86948 +/* 72685 */ MCD_OPC_Decode, 141, 1, 142, 3, // Opcode: ADCXr +/* 72690 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72700 +/* 72695 */ MCD_OPC_Decode, 162, 5, 143, 3, // Opcode: CSELXr +/* 72700 */ MCD_OPC_FilterValue, 6, 163, 55, 0, // Skip to: 86948 +/* 72705 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 72708 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 72718 +/* 72713 */ MCD_OPC_Decode, 156, 19, 142, 3, // Opcode: LSLVXr +/* 72718 */ MCD_OPC_FilterValue, 3, 145, 55, 0, // Skip to: 86948 +/* 72723 */ MCD_OPC_CheckPredicate, 13, 140, 55, 0, // Skip to: 86948 +/* 72728 */ MCD_OPC_Decode, 231, 20, 144, 3, // Opcode: PACGA +/* 72733 */ MCD_OPC_FilterValue, 1, 30, 0, 0, // Skip to: 72768 +/* 72738 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 72741 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 72751 +/* 72746 */ MCD_OPC_Decode, 164, 5, 143, 3, // Opcode: CSINCXr +/* 72751 */ MCD_OPC_FilterValue, 6, 112, 55, 0, // Skip to: 86948 +/* 72756 */ MCD_OPC_CheckField, 12, 4, 2, 105, 55, 0, // Skip to: 86948 +/* 72763 */ MCD_OPC_Decode, 180, 19, 142, 3, // Opcode: LSRVXr +/* 72768 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 72810 +/* 72773 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 72776 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72793 +/* 72781 */ MCD_OPC_CheckField, 21, 3, 6, 80, 55, 0, // Skip to: 86948 +/* 72788 */ MCD_OPC_Decode, 209, 31, 142, 3, // Opcode: UDIVXr +/* 72793 */ MCD_OPC_FilterValue, 2, 70, 55, 0, // Skip to: 86948 +/* 72798 */ MCD_OPC_CheckField, 21, 3, 6, 63, 55, 0, // Skip to: 86948 +/* 72805 */ MCD_OPC_Decode, 135, 2, 142, 3, // Opcode: ASRVXr +/* 72810 */ MCD_OPC_FilterValue, 3, 53, 55, 0, // Skip to: 86948 +/* 72815 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 72818 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 72835 +/* 72823 */ MCD_OPC_CheckField, 21, 3, 6, 38, 55, 0, // Skip to: 86948 +/* 72830 */ MCD_OPC_Decode, 222, 22, 142, 3, // Opcode: SDIVXr +/* 72835 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 72852 +/* 72840 */ MCD_OPC_CheckField, 21, 3, 6, 21, 55, 0, // Skip to: 86948 +/* 72847 */ MCD_OPC_Decode, 233, 21, 142, 3, // Opcode: RORVXr +/* 72852 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 72874 +/* 72857 */ MCD_OPC_CheckPredicate, 14, 6, 55, 0, // Skip to: 86948 +/* 72862 */ MCD_OPC_CheckField, 21, 3, 6, 255, 54, 0, // Skip to: 86948 +/* 72869 */ MCD_OPC_Decode, 160, 5, 145, 3, // Opcode: CRC32Xrr +/* 72874 */ MCD_OPC_FilterValue, 5, 245, 54, 0, // Skip to: 86948 +/* 72879 */ MCD_OPC_CheckPredicate, 14, 240, 54, 0, // Skip to: 86948 +/* 72884 */ MCD_OPC_CheckField, 21, 3, 6, 233, 54, 0, // Skip to: 86948 +/* 72891 */ MCD_OPC_Decode, 157, 5, 145, 3, // Opcode: CRC32CXrr +/* 72896 */ MCD_OPC_FilterValue, 3, 223, 54, 0, // Skip to: 86948 +/* 72901 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 72904 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 72932 +/* 72909 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 72912 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72922 +/* 72917 */ MCD_OPC_Decode, 200, 19, 146, 3, // Opcode: MADDXrrr +/* 72922 */ MCD_OPC_FilterValue, 1, 197, 54, 0, // Skip to: 86948 +/* 72927 */ MCD_OPC_Decode, 148, 20, 146, 3, // Opcode: MSUBXrrr +/* 72932 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 72960 +/* 72937 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 72940 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72950 +/* 72945 */ MCD_OPC_Decode, 176, 23, 147, 3, // Opcode: SMADDLrrr +/* 72950 */ MCD_OPC_FilterValue, 1, 169, 54, 0, // Skip to: 86948 +/* 72955 */ MCD_OPC_Decode, 133, 24, 147, 3, // Opcode: SMSUBLrrr +/* 72960 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 72977 +/* 72965 */ MCD_OPC_CheckField, 15, 1, 0, 152, 54, 0, // Skip to: 86948 +/* 72972 */ MCD_OPC_Decode, 138, 24, 142, 3, // Opcode: SMULHrr +/* 72977 */ MCD_OPC_FilterValue, 5, 23, 0, 0, // Skip to: 73005 +/* 72982 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 72985 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 72995 +/* 72990 */ MCD_OPC_Decode, 232, 31, 147, 3, // Opcode: UMADDLrrr +/* 72995 */ MCD_OPC_FilterValue, 1, 124, 54, 0, // Skip to: 86948 +/* 73000 */ MCD_OPC_Decode, 187, 32, 147, 3, // Opcode: UMSUBLrrr +/* 73005 */ MCD_OPC_FilterValue, 6, 114, 54, 0, // Skip to: 86948 +/* 73010 */ MCD_OPC_CheckField, 15, 1, 0, 107, 54, 0, // Skip to: 86948 +/* 73017 */ MCD_OPC_Decode, 192, 32, 142, 3, // Opcode: UMULHrr +/* 73022 */ MCD_OPC_FilterValue, 5, 101, 4, 0, // Skip to: 74152 +/* 73027 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 73030 */ MCD_OPC_FilterValue, 0, 244, 0, 0, // Skip to: 73279 +/* 73035 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 73038 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 73199 +/* 73043 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 73046 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73056 +/* 73051 */ MCD_OPC_Decode, 203, 29, 255, 2, // Opcode: STURWi +/* 73056 */ MCD_OPC_FilterValue, 1, 63, 54, 0, // Skip to: 86948 +/* 73061 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 73064 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73079 +/* 73069 */ MCD_OPC_CheckPredicate, 1, 50, 54, 0, // Skip to: 86948 +/* 73074 */ MCD_OPC_Decode, 219, 16, 131, 3, // Opcode: LDADDW +/* 73079 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73094 +/* 73084 */ MCD_OPC_CheckPredicate, 1, 35, 54, 0, // Skip to: 86948 +/* 73089 */ MCD_OPC_Decode, 130, 17, 131, 3, // Opcode: LDCLRW +/* 73094 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73109 +/* 73099 */ MCD_OPC_CheckPredicate, 1, 20, 54, 0, // Skip to: 86948 +/* 73104 */ MCD_OPC_Decode, 146, 17, 131, 3, // Opcode: LDEORW +/* 73109 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73124 +/* 73114 */ MCD_OPC_CheckPredicate, 1, 5, 54, 0, // Skip to: 86948 +/* 73119 */ MCD_OPC_Decode, 183, 18, 131, 3, // Opcode: LDSETW +/* 73124 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73139 +/* 73129 */ MCD_OPC_CheckPredicate, 1, 246, 53, 0, // Skip to: 86948 +/* 73134 */ MCD_OPC_Decode, 199, 18, 131, 3, // Opcode: LDSMAXW +/* 73139 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73154 +/* 73144 */ MCD_OPC_CheckPredicate, 1, 231, 53, 0, // Skip to: 86948 +/* 73149 */ MCD_OPC_Decode, 215, 18, 131, 3, // Opcode: LDSMINW +/* 73154 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73169 +/* 73159 */ MCD_OPC_CheckPredicate, 1, 216, 53, 0, // Skip to: 86948 +/* 73164 */ MCD_OPC_Decode, 240, 18, 131, 3, // Opcode: LDUMAXW +/* 73169 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73184 +/* 73174 */ MCD_OPC_CheckPredicate, 1, 201, 53, 0, // Skip to: 86948 +/* 73179 */ MCD_OPC_Decode, 128, 19, 131, 3, // Opcode: LDUMINW +/* 73184 */ MCD_OPC_FilterValue, 8, 191, 53, 0, // Skip to: 86948 +/* 73189 */ MCD_OPC_CheckPredicate, 1, 186, 53, 0, // Skip to: 86948 +/* 73194 */ MCD_OPC_Decode, 167, 30, 131, 3, // Opcode: SWPW +/* 73199 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73216 +/* 73204 */ MCD_OPC_CheckField, 21, 1, 0, 169, 53, 0, // Skip to: 86948 +/* 73211 */ MCD_OPC_Decode, 180, 29, 255, 2, // Opcode: STRWpost +/* 73216 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73262 +/* 73221 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 73224 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73234 +/* 73229 */ MCD_OPC_Decode, 194, 29, 255, 2, // Opcode: STTRWi +/* 73234 */ MCD_OPC_FilterValue, 1, 141, 53, 0, // Skip to: 86948 +/* 73239 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 73242 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73252 +/* 73247 */ MCD_OPC_Decode, 182, 29, 132, 3, // Opcode: STRWroW +/* 73252 */ MCD_OPC_FilterValue, 3, 123, 53, 0, // Skip to: 86948 +/* 73257 */ MCD_OPC_Decode, 183, 29, 133, 3, // Opcode: STRWroX +/* 73262 */ MCD_OPC_FilterValue, 3, 113, 53, 0, // Skip to: 86948 +/* 73267 */ MCD_OPC_CheckField, 21, 1, 0, 106, 53, 0, // Skip to: 86948 +/* 73274 */ MCD_OPC_Decode, 181, 29, 255, 2, // Opcode: STRWpre +/* 73279 */ MCD_OPC_FilterValue, 1, 244, 0, 0, // Skip to: 73528 +/* 73284 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 73287 */ MCD_OPC_FilterValue, 0, 156, 0, 0, // Skip to: 73448 +/* 73292 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 73295 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73305 +/* 73300 */ MCD_OPC_Decode, 142, 19, 255, 2, // Opcode: LDURWi +/* 73305 */ MCD_OPC_FilterValue, 1, 70, 53, 0, // Skip to: 86948 +/* 73310 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 73313 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73328 +/* 73318 */ MCD_OPC_CheckPredicate, 1, 57, 53, 0, // Skip to: 86948 +/* 73323 */ MCD_OPC_Decode, 217, 16, 131, 3, // Opcode: LDADDLW +/* 73328 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73343 +/* 73333 */ MCD_OPC_CheckPredicate, 1, 42, 53, 0, // Skip to: 86948 +/* 73338 */ MCD_OPC_Decode, 128, 17, 131, 3, // Opcode: LDCLRLW +/* 73343 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73358 +/* 73348 */ MCD_OPC_CheckPredicate, 1, 27, 53, 0, // Skip to: 86948 +/* 73353 */ MCD_OPC_Decode, 144, 17, 131, 3, // Opcode: LDEORLW +/* 73358 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73373 +/* 73363 */ MCD_OPC_CheckPredicate, 1, 12, 53, 0, // Skip to: 86948 +/* 73368 */ MCD_OPC_Decode, 181, 18, 131, 3, // Opcode: LDSETLW +/* 73373 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73388 +/* 73378 */ MCD_OPC_CheckPredicate, 1, 253, 52, 0, // Skip to: 86948 +/* 73383 */ MCD_OPC_Decode, 197, 18, 131, 3, // Opcode: LDSMAXLW +/* 73388 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73403 +/* 73393 */ MCD_OPC_CheckPredicate, 1, 238, 52, 0, // Skip to: 86948 +/* 73398 */ MCD_OPC_Decode, 213, 18, 131, 3, // Opcode: LDSMINLW +/* 73403 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73418 +/* 73408 */ MCD_OPC_CheckPredicate, 1, 223, 52, 0, // Skip to: 86948 +/* 73413 */ MCD_OPC_Decode, 238, 18, 131, 3, // Opcode: LDUMAXLW +/* 73418 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73433 +/* 73423 */ MCD_OPC_CheckPredicate, 1, 208, 52, 0, // Skip to: 86948 +/* 73428 */ MCD_OPC_Decode, 254, 18, 131, 3, // Opcode: LDUMINLW +/* 73433 */ MCD_OPC_FilterValue, 8, 198, 52, 0, // Skip to: 86948 +/* 73438 */ MCD_OPC_CheckPredicate, 1, 193, 52, 0, // Skip to: 86948 +/* 73443 */ MCD_OPC_Decode, 165, 30, 131, 3, // Opcode: SWPLW +/* 73448 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73465 +/* 73453 */ MCD_OPC_CheckField, 21, 1, 0, 176, 52, 0, // Skip to: 86948 +/* 73460 */ MCD_OPC_Decode, 156, 18, 255, 2, // Opcode: LDRWpost +/* 73465 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73511 +/* 73470 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 73473 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73483 +/* 73478 */ MCD_OPC_Decode, 224, 18, 255, 2, // Opcode: LDTRWi +/* 73483 */ MCD_OPC_FilterValue, 1, 148, 52, 0, // Skip to: 86948 +/* 73488 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 73491 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73501 +/* 73496 */ MCD_OPC_Decode, 158, 18, 132, 3, // Opcode: LDRWroW +/* 73501 */ MCD_OPC_FilterValue, 3, 130, 52, 0, // Skip to: 86948 +/* 73506 */ MCD_OPC_Decode, 159, 18, 133, 3, // Opcode: LDRWroX +/* 73511 */ MCD_OPC_FilterValue, 3, 120, 52, 0, // Skip to: 86948 +/* 73516 */ MCD_OPC_CheckField, 21, 1, 0, 113, 52, 0, // Skip to: 86948 +/* 73523 */ MCD_OPC_Decode, 157, 18, 255, 2, // Opcode: LDRWpre +/* 73528 */ MCD_OPC_FilterValue, 2, 10, 1, 0, // Skip to: 73799 +/* 73533 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 73536 */ MCD_OPC_FilterValue, 0, 178, 0, 0, // Skip to: 73719 +/* 73541 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 73544 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73554 +/* 73549 */ MCD_OPC_Decode, 140, 19, 255, 2, // Opcode: LDURSWi +/* 73554 */ MCD_OPC_FilterValue, 1, 77, 52, 0, // Skip to: 86948 +/* 73559 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 73562 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 73577 +/* 73567 */ MCD_OPC_CheckPredicate, 1, 64, 52, 0, // Skip to: 86948 +/* 73572 */ MCD_OPC_Decode, 211, 16, 131, 3, // Opcode: LDADDAW +/* 73577 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 73592 +/* 73582 */ MCD_OPC_CheckPredicate, 1, 49, 52, 0, // Skip to: 86948 +/* 73587 */ MCD_OPC_Decode, 250, 16, 131, 3, // Opcode: LDCLRAW +/* 73592 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 73607 +/* 73597 */ MCD_OPC_CheckPredicate, 1, 34, 52, 0, // Skip to: 86948 +/* 73602 */ MCD_OPC_Decode, 138, 17, 131, 3, // Opcode: LDEORAW +/* 73607 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 73622 +/* 73612 */ MCD_OPC_CheckPredicate, 1, 19, 52, 0, // Skip to: 86948 +/* 73617 */ MCD_OPC_Decode, 175, 18, 131, 3, // Opcode: LDSETAW +/* 73622 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 73637 +/* 73627 */ MCD_OPC_CheckPredicate, 1, 4, 52, 0, // Skip to: 86948 +/* 73632 */ MCD_OPC_Decode, 191, 18, 131, 3, // Opcode: LDSMAXAW +/* 73637 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 73652 +/* 73642 */ MCD_OPC_CheckPredicate, 1, 245, 51, 0, // Skip to: 86948 +/* 73647 */ MCD_OPC_Decode, 207, 18, 131, 3, // Opcode: LDSMINAW +/* 73652 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 73667 +/* 73657 */ MCD_OPC_CheckPredicate, 1, 230, 51, 0, // Skip to: 86948 +/* 73662 */ MCD_OPC_Decode, 232, 18, 131, 3, // Opcode: LDUMAXAW +/* 73667 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 73682 +/* 73672 */ MCD_OPC_CheckPredicate, 1, 215, 51, 0, // Skip to: 86948 +/* 73677 */ MCD_OPC_Decode, 248, 18, 131, 3, // Opcode: LDUMINAW +/* 73682 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 73697 +/* 73687 */ MCD_OPC_CheckPredicate, 1, 200, 51, 0, // Skip to: 86948 +/* 73692 */ MCD_OPC_Decode, 159, 30, 131, 3, // Opcode: SWPAW +/* 73697 */ MCD_OPC_FilterValue, 12, 190, 51, 0, // Skip to: 86948 +/* 73702 */ MCD_OPC_CheckPredicate, 15, 185, 51, 0, // Skip to: 86948 +/* 73707 */ MCD_OPC_CheckField, 16, 5, 31, 178, 51, 0, // Skip to: 86948 +/* 73714 */ MCD_OPC_Decode, 223, 16, 134, 3, // Opcode: LDAPRW +/* 73719 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 73736 +/* 73724 */ MCD_OPC_CheckField, 21, 1, 0, 161, 51, 0, // Skip to: 86948 +/* 73731 */ MCD_OPC_Decode, 144, 18, 255, 2, // Opcode: LDRSWpost +/* 73736 */ MCD_OPC_FilterValue, 2, 41, 0, 0, // Skip to: 73782 +/* 73741 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 73744 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 73754 +/* 73749 */ MCD_OPC_Decode, 223, 18, 255, 2, // Opcode: LDTRSWi +/* 73754 */ MCD_OPC_FilterValue, 1, 133, 51, 0, // Skip to: 86948 +/* 73759 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 73762 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 73772 +/* 73767 */ MCD_OPC_Decode, 146, 18, 135, 3, // Opcode: LDRSWroW +/* 73772 */ MCD_OPC_FilterValue, 3, 115, 51, 0, // Skip to: 86948 +/* 73777 */ MCD_OPC_Decode, 147, 18, 136, 3, // Opcode: LDRSWroX +/* 73782 */ MCD_OPC_FilterValue, 3, 105, 51, 0, // Skip to: 86948 +/* 73787 */ MCD_OPC_CheckField, 21, 1, 0, 98, 51, 0, // Skip to: 86948 +/* 73794 */ MCD_OPC_Decode, 145, 18, 255, 2, // Opcode: LDRSWpre +/* 73799 */ MCD_OPC_FilterValue, 3, 201, 0, 0, // Skip to: 74005 +/* 73804 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 73807 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 73829 +/* 73812 */ MCD_OPC_CheckPredicate, 1, 75, 51, 0, // Skip to: 86948 +/* 73817 */ MCD_OPC_CheckField, 21, 1, 1, 68, 51, 0, // Skip to: 86948 +/* 73824 */ MCD_OPC_Decode, 209, 16, 131, 3, // Opcode: LDADDALW +/* 73829 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 73851 +/* 73834 */ MCD_OPC_CheckPredicate, 1, 53, 51, 0, // Skip to: 86948 +/* 73839 */ MCD_OPC_CheckField, 21, 1, 1, 46, 51, 0, // Skip to: 86948 +/* 73846 */ MCD_OPC_Decode, 248, 16, 131, 3, // Opcode: LDCLRALW +/* 73851 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 73873 +/* 73856 */ MCD_OPC_CheckPredicate, 1, 31, 51, 0, // Skip to: 86948 +/* 73861 */ MCD_OPC_CheckField, 21, 1, 1, 24, 51, 0, // Skip to: 86948 +/* 73868 */ MCD_OPC_Decode, 136, 17, 131, 3, // Opcode: LDEORALW +/* 73873 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 73895 +/* 73878 */ MCD_OPC_CheckPredicate, 1, 9, 51, 0, // Skip to: 86948 +/* 73883 */ MCD_OPC_CheckField, 21, 1, 1, 2, 51, 0, // Skip to: 86948 +/* 73890 */ MCD_OPC_Decode, 173, 18, 131, 3, // Opcode: LDSETALW +/* 73895 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 73917 +/* 73900 */ MCD_OPC_CheckPredicate, 1, 243, 50, 0, // Skip to: 86948 +/* 73905 */ MCD_OPC_CheckField, 21, 1, 1, 236, 50, 0, // Skip to: 86948 +/* 73912 */ MCD_OPC_Decode, 189, 18, 131, 3, // Opcode: LDSMAXALW +/* 73917 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 73939 +/* 73922 */ MCD_OPC_CheckPredicate, 1, 221, 50, 0, // Skip to: 86948 +/* 73927 */ MCD_OPC_CheckField, 21, 1, 1, 214, 50, 0, // Skip to: 86948 +/* 73934 */ MCD_OPC_Decode, 205, 18, 131, 3, // Opcode: LDSMINALW +/* 73939 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 73961 +/* 73944 */ MCD_OPC_CheckPredicate, 1, 199, 50, 0, // Skip to: 86948 +/* 73949 */ MCD_OPC_CheckField, 21, 1, 1, 192, 50, 0, // Skip to: 86948 +/* 73956 */ MCD_OPC_Decode, 230, 18, 131, 3, // Opcode: LDUMAXALW +/* 73961 */ MCD_OPC_FilterValue, 28, 17, 0, 0, // Skip to: 73983 +/* 73966 */ MCD_OPC_CheckPredicate, 1, 177, 50, 0, // Skip to: 86948 +/* 73971 */ MCD_OPC_CheckField, 21, 1, 1, 170, 50, 0, // Skip to: 86948 +/* 73978 */ MCD_OPC_Decode, 246, 18, 131, 3, // Opcode: LDUMINALW +/* 73983 */ MCD_OPC_FilterValue, 32, 160, 50, 0, // Skip to: 86948 +/* 73988 */ MCD_OPC_CheckPredicate, 1, 155, 50, 0, // Skip to: 86948 +/* 73993 */ MCD_OPC_CheckField, 21, 1, 1, 148, 50, 0, // Skip to: 86948 +/* 74000 */ MCD_OPC_Decode, 157, 30, 131, 3, // Opcode: SWPALW +/* 74005 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74015 +/* 74010 */ MCD_OPC_Decode, 184, 29, 137, 3, // Opcode: STRWui +/* 74015 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 74025 +/* 74020 */ MCD_OPC_Decode, 160, 18, 137, 3, // Opcode: LDRWui +/* 74025 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 74035 +/* 74030 */ MCD_OPC_Decode, 148, 18, 137, 3, // Opcode: LDRSWui +/* 74035 */ MCD_OPC_FilterValue, 8, 56, 0, 0, // Skip to: 74096 +/* 74040 */ MCD_OPC_ExtractField, 10, 5, // Inst{14-10} ... +/* 74043 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 74067 +/* 74048 */ MCD_OPC_CheckField, 21, 1, 0, 93, 50, 0, // Skip to: 86948 +/* 74055 */ MCD_OPC_CheckField, 15, 1, 0, 86, 50, 0, // Skip to: 86948 +/* 74062 */ MCD_OPC_Decode, 139, 1, 142, 3, // Opcode: ADCSXr +/* 74067 */ MCD_OPC_FilterValue, 1, 76, 50, 0, // Skip to: 86948 +/* 74072 */ MCD_OPC_CheckPredicate, 12, 71, 50, 0, // Skip to: 86948 +/* 74077 */ MCD_OPC_CheckField, 21, 1, 0, 64, 50, 0, // Skip to: 86948 +/* 74084 */ MCD_OPC_CheckField, 4, 1, 0, 57, 50, 0, // Skip to: 86948 +/* 74091 */ MCD_OPC_Decode, 231, 21, 148, 3, // Opcode: RMIF +/* 74096 */ MCD_OPC_FilterValue, 9, 47, 50, 0, // Skip to: 86948 +/* 74101 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 74104 */ MCD_OPC_FilterValue, 0, 19, 0, 0, // Skip to: 74128 +/* 74109 */ MCD_OPC_CheckField, 21, 1, 0, 32, 50, 0, // Skip to: 86948 +/* 74116 */ MCD_OPC_CheckField, 4, 1, 0, 25, 50, 0, // Skip to: 86948 +/* 74123 */ MCD_OPC_Decode, 255, 2, 149, 3, // Opcode: CCMNXr +/* 74128 */ MCD_OPC_FilterValue, 2, 15, 50, 0, // Skip to: 86948 +/* 74133 */ MCD_OPC_CheckField, 21, 1, 0, 8, 50, 0, // Skip to: 86948 +/* 74140 */ MCD_OPC_CheckField, 4, 1, 0, 1, 50, 0, // Skip to: 86948 +/* 74147 */ MCD_OPC_Decode, 254, 2, 150, 3, // Opcode: CCMNXi +/* 74152 */ MCD_OPC_FilterValue, 6, 56, 2, 0, // Skip to: 74725 +/* 74157 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 74160 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74170 +/* 74165 */ MCD_OPC_Decode, 152, 21, 151, 3, // Opcode: PRFMl +/* 74170 */ MCD_OPC_FilterValue, 1, 47, 0, 0, // Skip to: 74222 +/* 74175 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 74178 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 74200 +/* 74183 */ MCD_OPC_CheckPredicate, 12, 216, 49, 0, // Skip to: 86948 +/* 74188 */ MCD_OPC_CheckField, 10, 2, 0, 209, 49, 0, // Skip to: 86948 +/* 74195 */ MCD_OPC_Decode, 238, 28, 255, 2, // Opcode: STLURXi +/* 74200 */ MCD_OPC_FilterValue, 2, 199, 49, 0, // Skip to: 86948 +/* 74205 */ MCD_OPC_CheckPredicate, 12, 194, 49, 0, // Skip to: 86948 +/* 74210 */ MCD_OPC_CheckField, 10, 2, 0, 187, 49, 0, // Skip to: 86948 +/* 74217 */ MCD_OPC_Decode, 232, 16, 255, 2, // Opcode: LDAPURXi +/* 74222 */ MCD_OPC_FilterValue, 2, 177, 49, 0, // Skip to: 86948 +/* 74227 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 74230 */ MCD_OPC_FilterValue, 0, 154, 0, 0, // Skip to: 74389 +/* 74235 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 74238 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 74255 +/* 74243 */ MCD_OPC_CheckField, 12, 4, 0, 154, 49, 0, // Skip to: 86948 +/* 74250 */ MCD_OPC_Decode, 181, 22, 142, 3, // Opcode: SBCXr +/* 74255 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74265 +/* 74260 */ MCD_OPC_Decode, 166, 5, 143, 3, // Opcode: CSINVXr +/* 74265 */ MCD_OPC_FilterValue, 6, 134, 49, 0, // Skip to: 86948 +/* 74270 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 74273 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74283 +/* 74278 */ MCD_OPC_Decode, 185, 21, 152, 3, // Opcode: RBITXr +/* 74283 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 74293 +/* 74288 */ MCD_OPC_Decode, 171, 3, 152, 3, // Opcode: CLZXr +/* 74293 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 74308 +/* 74298 */ MCD_OPC_CheckPredicate, 13, 101, 49, 0, // Skip to: 86948 +/* 74303 */ MCD_OPC_Decode, 232, 20, 153, 3, // Opcode: PACIA +/* 74308 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 74323 +/* 74313 */ MCD_OPC_CheckPredicate, 13, 86, 49, 0, // Skip to: 86948 +/* 74318 */ MCD_OPC_Decode, 158, 2, 153, 3, // Opcode: AUTIA +/* 74323 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 74345 +/* 74328 */ MCD_OPC_CheckPredicate, 13, 71, 49, 0, // Skip to: 86948 +/* 74333 */ MCD_OPC_CheckField, 5, 5, 31, 64, 49, 0, // Skip to: 86948 +/* 74340 */ MCD_OPC_Decode, 240, 20, 154, 3, // Opcode: PACIZA +/* 74345 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 74367 +/* 74350 */ MCD_OPC_CheckPredicate, 13, 49, 49, 0, // Skip to: 86948 +/* 74355 */ MCD_OPC_CheckField, 5, 5, 31, 42, 49, 0, // Skip to: 86948 +/* 74362 */ MCD_OPC_Decode, 166, 2, 154, 3, // Opcode: AUTIZA +/* 74367 */ MCD_OPC_FilterValue, 20, 32, 49, 0, // Skip to: 86948 +/* 74372 */ MCD_OPC_CheckPredicate, 13, 27, 49, 0, // Skip to: 86948 +/* 74377 */ MCD_OPC_CheckField, 5, 5, 31, 20, 49, 0, // Skip to: 86948 +/* 74384 */ MCD_OPC_Decode, 253, 34, 154, 3, // Opcode: XPACI +/* 74389 */ MCD_OPC_FilterValue, 1, 137, 0, 0, // Skip to: 74531 +/* 74394 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 74397 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 74407 +/* 74402 */ MCD_OPC_Decode, 168, 5, 143, 3, // Opcode: CSNEGXr +/* 74407 */ MCD_OPC_FilterValue, 6, 248, 48, 0, // Skip to: 86948 +/* 74412 */ MCD_OPC_ExtractField, 12, 9, // Inst{20-12} ... +/* 74415 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74425 +/* 74420 */ MCD_OPC_Decode, 201, 21, 152, 3, // Opcode: REV16Xr +/* 74425 */ MCD_OPC_FilterValue, 1, 5, 0, 0, // Skip to: 74435 +/* 74430 */ MCD_OPC_Decode, 159, 3, 152, 3, // Opcode: CLSXr +/* 74435 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 74450 +/* 74440 */ MCD_OPC_CheckPredicate, 13, 215, 48, 0, // Skip to: 86948 +/* 74445 */ MCD_OPC_Decode, 236, 20, 153, 3, // Opcode: PACIB +/* 74450 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 74465 +/* 74455 */ MCD_OPC_CheckPredicate, 13, 200, 48, 0, // Skip to: 86948 +/* 74460 */ MCD_OPC_Decode, 162, 2, 153, 3, // Opcode: AUTIB +/* 74465 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 74487 +/* 74470 */ MCD_OPC_CheckPredicate, 13, 185, 48, 0, // Skip to: 86948 +/* 74475 */ MCD_OPC_CheckField, 5, 5, 31, 178, 48, 0, // Skip to: 86948 +/* 74482 */ MCD_OPC_Decode, 241, 20, 154, 3, // Opcode: PACIZB +/* 74487 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 74509 +/* 74492 */ MCD_OPC_CheckPredicate, 13, 163, 48, 0, // Skip to: 86948 +/* 74497 */ MCD_OPC_CheckField, 5, 5, 31, 156, 48, 0, // Skip to: 86948 +/* 74504 */ MCD_OPC_Decode, 167, 2, 154, 3, // Opcode: AUTIZB +/* 74509 */ MCD_OPC_FilterValue, 20, 146, 48, 0, // Skip to: 86948 +/* 74514 */ MCD_OPC_CheckPredicate, 13, 141, 48, 0, // Skip to: 86948 +/* 74519 */ MCD_OPC_CheckField, 5, 5, 31, 134, 48, 0, // Skip to: 86948 +/* 74526 */ MCD_OPC_Decode, 252, 34, 154, 3, // Opcode: XPACD +/* 74531 */ MCD_OPC_FilterValue, 2, 92, 0, 0, // Skip to: 74628 +/* 74536 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 74539 */ MCD_OPC_FilterValue, 128, 24, 5, 0, 0, // Skip to: 74550 +/* 74545 */ MCD_OPC_Decode, 204, 21, 152, 3, // Opcode: REV32Xr +/* 74550 */ MCD_OPC_FilterValue, 144, 24, 10, 0, 0, // Skip to: 74566 +/* 74556 */ MCD_OPC_CheckPredicate, 13, 99, 48, 0, // Skip to: 86948 +/* 74561 */ MCD_OPC_Decode, 227, 20, 153, 3, // Opcode: PACDA +/* 74566 */ MCD_OPC_FilterValue, 145, 24, 10, 0, 0, // Skip to: 74582 +/* 74572 */ MCD_OPC_CheckPredicate, 13, 83, 48, 0, // Skip to: 86948 +/* 74577 */ MCD_OPC_Decode, 154, 2, 153, 3, // Opcode: AUTDA +/* 74582 */ MCD_OPC_FilterValue, 146, 24, 17, 0, 0, // Skip to: 74605 +/* 74588 */ MCD_OPC_CheckPredicate, 13, 67, 48, 0, // Skip to: 86948 +/* 74593 */ MCD_OPC_CheckField, 5, 5, 31, 60, 48, 0, // Skip to: 86948 +/* 74600 */ MCD_OPC_Decode, 229, 20, 154, 3, // Opcode: PACDZA +/* 74605 */ MCD_OPC_FilterValue, 147, 24, 49, 48, 0, // Skip to: 86948 +/* 74611 */ MCD_OPC_CheckPredicate, 13, 44, 48, 0, // Skip to: 86948 +/* 74616 */ MCD_OPC_CheckField, 5, 5, 31, 37, 48, 0, // Skip to: 86948 +/* 74623 */ MCD_OPC_Decode, 156, 2, 154, 3, // Opcode: AUTDZA +/* 74628 */ MCD_OPC_FilterValue, 3, 27, 48, 0, // Skip to: 86948 +/* 74633 */ MCD_OPC_ExtractField, 12, 12, // Inst{23-12} ... +/* 74636 */ MCD_OPC_FilterValue, 128, 24, 5, 0, 0, // Skip to: 74647 +/* 74642 */ MCD_OPC_Decode, 222, 21, 152, 3, // Opcode: REVXr +/* 74647 */ MCD_OPC_FilterValue, 144, 24, 10, 0, 0, // Skip to: 74663 +/* 74653 */ MCD_OPC_CheckPredicate, 13, 2, 48, 0, // Skip to: 86948 +/* 74658 */ MCD_OPC_Decode, 228, 20, 153, 3, // Opcode: PACDB +/* 74663 */ MCD_OPC_FilterValue, 145, 24, 10, 0, 0, // Skip to: 74679 +/* 74669 */ MCD_OPC_CheckPredicate, 13, 242, 47, 0, // Skip to: 86948 +/* 74674 */ MCD_OPC_Decode, 155, 2, 153, 3, // Opcode: AUTDB +/* 74679 */ MCD_OPC_FilterValue, 146, 24, 17, 0, 0, // Skip to: 74702 +/* 74685 */ MCD_OPC_CheckPredicate, 13, 226, 47, 0, // Skip to: 86948 +/* 74690 */ MCD_OPC_CheckField, 5, 5, 31, 219, 47, 0, // Skip to: 86948 +/* 74697 */ MCD_OPC_Decode, 230, 20, 154, 3, // Opcode: PACDZB +/* 74702 */ MCD_OPC_FilterValue, 147, 24, 208, 47, 0, // Skip to: 86948 +/* 74708 */ MCD_OPC_CheckPredicate, 13, 203, 47, 0, // Skip to: 86948 +/* 74713 */ MCD_OPC_CheckField, 5, 5, 31, 196, 47, 0, // Skip to: 86948 +/* 74720 */ MCD_OPC_Decode, 157, 2, 154, 3, // Opcode: AUTDZB +/* 74725 */ MCD_OPC_FilterValue, 7, 186, 47, 0, // Skip to: 86948 +/* 74730 */ MCD_OPC_ExtractField, 23, 3, // Inst{25-23} ... +/* 74733 */ MCD_OPC_FilterValue, 0, 247, 1, 0, // Skip to: 75241 +/* 74738 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 74741 */ MCD_OPC_FilterValue, 0, 53, 1, 0, // Skip to: 75055 +/* 74746 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 74749 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 74759 +/* 74754 */ MCD_OPC_Decode, 204, 29, 255, 2, // Opcode: STURXi +/* 74759 */ MCD_OPC_FilterValue, 1, 138, 0, 0, // Skip to: 74902 +/* 74764 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 74767 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 74782 +/* 74772 */ MCD_OPC_CheckPredicate, 1, 139, 47, 0, // Skip to: 86948 +/* 74777 */ MCD_OPC_Decode, 220, 16, 155, 3, // Opcode: LDADDX +/* 74782 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 74797 +/* 74787 */ MCD_OPC_CheckPredicate, 1, 124, 47, 0, // Skip to: 86948 +/* 74792 */ MCD_OPC_Decode, 131, 17, 155, 3, // Opcode: LDCLRX +/* 74797 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 74812 +/* 74802 */ MCD_OPC_CheckPredicate, 1, 109, 47, 0, // Skip to: 86948 +/* 74807 */ MCD_OPC_Decode, 147, 17, 155, 3, // Opcode: LDEORX +/* 74812 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 74827 +/* 74817 */ MCD_OPC_CheckPredicate, 1, 94, 47, 0, // Skip to: 86948 +/* 74822 */ MCD_OPC_Decode, 184, 18, 155, 3, // Opcode: LDSETX +/* 74827 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 74842 +/* 74832 */ MCD_OPC_CheckPredicate, 1, 79, 47, 0, // Skip to: 86948 +/* 74837 */ MCD_OPC_Decode, 200, 18, 155, 3, // Opcode: LDSMAXX +/* 74842 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 74857 +/* 74847 */ MCD_OPC_CheckPredicate, 1, 64, 47, 0, // Skip to: 86948 +/* 74852 */ MCD_OPC_Decode, 216, 18, 155, 3, // Opcode: LDSMINX +/* 74857 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 74872 +/* 74862 */ MCD_OPC_CheckPredicate, 1, 49, 47, 0, // Skip to: 86948 +/* 74867 */ MCD_OPC_Decode, 241, 18, 155, 3, // Opcode: LDUMAXX +/* 74872 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 74887 +/* 74877 */ MCD_OPC_CheckPredicate, 1, 34, 47, 0, // Skip to: 86948 +/* 74882 */ MCD_OPC_Decode, 129, 19, 155, 3, // Opcode: LDUMINX +/* 74887 */ MCD_OPC_FilterValue, 8, 24, 47, 0, // Skip to: 86948 +/* 74892 */ MCD_OPC_CheckPredicate, 1, 19, 47, 0, // Skip to: 86948 +/* 74897 */ MCD_OPC_Decode, 168, 30, 155, 3, // Opcode: SWPX +/* 74902 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 74912 +/* 74907 */ MCD_OPC_Decode, 143, 19, 255, 2, // Opcode: LDURXi +/* 74912 */ MCD_OPC_FilterValue, 3, 255, 46, 0, // Skip to: 86948 +/* 74917 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 74920 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 74935 +/* 74925 */ MCD_OPC_CheckPredicate, 1, 242, 46, 0, // Skip to: 86948 +/* 74930 */ MCD_OPC_Decode, 218, 16, 155, 3, // Opcode: LDADDLX +/* 74935 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 74950 +/* 74940 */ MCD_OPC_CheckPredicate, 1, 227, 46, 0, // Skip to: 86948 +/* 74945 */ MCD_OPC_Decode, 129, 17, 155, 3, // Opcode: LDCLRLX +/* 74950 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 74965 +/* 74955 */ MCD_OPC_CheckPredicate, 1, 212, 46, 0, // Skip to: 86948 +/* 74960 */ MCD_OPC_Decode, 145, 17, 155, 3, // Opcode: LDEORLX +/* 74965 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 74980 +/* 74970 */ MCD_OPC_CheckPredicate, 1, 197, 46, 0, // Skip to: 86948 +/* 74975 */ MCD_OPC_Decode, 182, 18, 155, 3, // Opcode: LDSETLX +/* 74980 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 74995 +/* 74985 */ MCD_OPC_CheckPredicate, 1, 182, 46, 0, // Skip to: 86948 +/* 74990 */ MCD_OPC_Decode, 198, 18, 155, 3, // Opcode: LDSMAXLX +/* 74995 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75010 +/* 75000 */ MCD_OPC_CheckPredicate, 1, 167, 46, 0, // Skip to: 86948 +/* 75005 */ MCD_OPC_Decode, 214, 18, 155, 3, // Opcode: LDSMINLX +/* 75010 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75025 +/* 75015 */ MCD_OPC_CheckPredicate, 1, 152, 46, 0, // Skip to: 86948 +/* 75020 */ MCD_OPC_Decode, 239, 18, 155, 3, // Opcode: LDUMAXLX +/* 75025 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75040 +/* 75030 */ MCD_OPC_CheckPredicate, 1, 137, 46, 0, // Skip to: 86948 +/* 75035 */ MCD_OPC_Decode, 255, 18, 155, 3, // Opcode: LDUMINLX +/* 75040 */ MCD_OPC_FilterValue, 8, 127, 46, 0, // Skip to: 86948 +/* 75045 */ MCD_OPC_CheckPredicate, 1, 122, 46, 0, // Skip to: 86948 +/* 75050 */ MCD_OPC_Decode, 166, 30, 155, 3, // Opcode: SWPLX +/* 75055 */ MCD_OPC_FilterValue, 1, 46, 0, 0, // Skip to: 75106 +/* 75060 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 75063 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 75091 +/* 75068 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 75071 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75081 +/* 75076 */ MCD_OPC_Decode, 185, 29, 255, 2, // Opcode: STRXpost +/* 75081 */ MCD_OPC_FilterValue, 1, 86, 46, 0, // Skip to: 86948 +/* 75086 */ MCD_OPC_Decode, 162, 18, 255, 2, // Opcode: LDRXpost +/* 75091 */ MCD_OPC_FilterValue, 1, 76, 46, 0, // Skip to: 86948 +/* 75096 */ MCD_OPC_CheckPredicate, 13, 71, 46, 0, // Skip to: 86948 +/* 75101 */ MCD_OPC_Decode, 215, 17, 156, 3, // Opcode: LDRAAindexed +/* 75106 */ MCD_OPC_FilterValue, 2, 79, 0, 0, // Skip to: 75190 +/* 75111 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 75114 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75124 +/* 75119 */ MCD_OPC_Decode, 195, 29, 255, 2, // Opcode: STTRXi +/* 75124 */ MCD_OPC_FilterValue, 1, 23, 0, 0, // Skip to: 75152 +/* 75129 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 75132 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75142 +/* 75137 */ MCD_OPC_Decode, 187, 29, 135, 3, // Opcode: STRXroW +/* 75142 */ MCD_OPC_FilterValue, 3, 25, 46, 0, // Skip to: 86948 +/* 75147 */ MCD_OPC_Decode, 188, 29, 136, 3, // Opcode: STRXroX +/* 75152 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75162 +/* 75157 */ MCD_OPC_Decode, 225, 18, 255, 2, // Opcode: LDTRXi +/* 75162 */ MCD_OPC_FilterValue, 3, 5, 46, 0, // Skip to: 86948 +/* 75167 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 75170 */ MCD_OPC_FilterValue, 2, 5, 0, 0, // Skip to: 75180 +/* 75175 */ MCD_OPC_Decode, 164, 18, 135, 3, // Opcode: LDRXroW +/* 75180 */ MCD_OPC_FilterValue, 3, 243, 45, 0, // Skip to: 86948 +/* 75185 */ MCD_OPC_Decode, 165, 18, 136, 3, // Opcode: LDRXroX +/* 75190 */ MCD_OPC_FilterValue, 3, 233, 45, 0, // Skip to: 86948 +/* 75195 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 75198 */ MCD_OPC_FilterValue, 0, 23, 0, 0, // Skip to: 75226 +/* 75203 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 75206 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75216 +/* 75211 */ MCD_OPC_Decode, 186, 29, 255, 2, // Opcode: STRXpre +/* 75216 */ MCD_OPC_FilterValue, 1, 207, 45, 0, // Skip to: 86948 +/* 75221 */ MCD_OPC_Decode, 163, 18, 255, 2, // Opcode: LDRXpre +/* 75226 */ MCD_OPC_FilterValue, 1, 197, 45, 0, // Skip to: 86948 +/* 75231 */ MCD_OPC_CheckPredicate, 13, 192, 45, 0, // Skip to: 86948 +/* 75236 */ MCD_OPC_Decode, 216, 17, 157, 3, // Opcode: LDRAAwriteback +/* 75241 */ MCD_OPC_FilterValue, 1, 159, 1, 0, // Skip to: 75661 +/* 75246 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 75249 */ MCD_OPC_FilterValue, 0, 65, 1, 0, // Skip to: 75575 +/* 75254 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 75257 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75267 +/* 75262 */ MCD_OPC_Decode, 157, 21, 255, 2, // Opcode: PRFUMi +/* 75267 */ MCD_OPC_FilterValue, 1, 160, 0, 0, // Skip to: 75432 +/* 75272 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 75275 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75290 +/* 75280 */ MCD_OPC_CheckPredicate, 1, 143, 45, 0, // Skip to: 86948 +/* 75285 */ MCD_OPC_Decode, 212, 16, 155, 3, // Opcode: LDADDAX +/* 75290 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75305 +/* 75295 */ MCD_OPC_CheckPredicate, 1, 128, 45, 0, // Skip to: 86948 +/* 75300 */ MCD_OPC_Decode, 251, 16, 155, 3, // Opcode: LDCLRAX +/* 75305 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75320 +/* 75310 */ MCD_OPC_CheckPredicate, 1, 113, 45, 0, // Skip to: 86948 +/* 75315 */ MCD_OPC_Decode, 139, 17, 155, 3, // Opcode: LDEORAX +/* 75320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75335 +/* 75325 */ MCD_OPC_CheckPredicate, 1, 98, 45, 0, // Skip to: 86948 +/* 75330 */ MCD_OPC_Decode, 176, 18, 155, 3, // Opcode: LDSETAX +/* 75335 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75350 +/* 75340 */ MCD_OPC_CheckPredicate, 1, 83, 45, 0, // Skip to: 86948 +/* 75345 */ MCD_OPC_Decode, 192, 18, 155, 3, // Opcode: LDSMAXAX +/* 75350 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75365 +/* 75355 */ MCD_OPC_CheckPredicate, 1, 68, 45, 0, // Skip to: 86948 +/* 75360 */ MCD_OPC_Decode, 208, 18, 155, 3, // Opcode: LDSMINAX +/* 75365 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75380 +/* 75370 */ MCD_OPC_CheckPredicate, 1, 53, 45, 0, // Skip to: 86948 +/* 75375 */ MCD_OPC_Decode, 233, 18, 155, 3, // Opcode: LDUMAXAX +/* 75380 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75395 +/* 75385 */ MCD_OPC_CheckPredicate, 1, 38, 45, 0, // Skip to: 86948 +/* 75390 */ MCD_OPC_Decode, 249, 18, 155, 3, // Opcode: LDUMINAX +/* 75395 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 75410 +/* 75400 */ MCD_OPC_CheckPredicate, 1, 23, 45, 0, // Skip to: 86948 +/* 75405 */ MCD_OPC_Decode, 160, 30, 155, 3, // Opcode: SWPAX +/* 75410 */ MCD_OPC_FilterValue, 12, 13, 45, 0, // Skip to: 86948 +/* 75415 */ MCD_OPC_CheckPredicate, 15, 8, 45, 0, // Skip to: 86948 +/* 75420 */ MCD_OPC_CheckField, 16, 5, 31, 1, 45, 0, // Skip to: 86948 +/* 75427 */ MCD_OPC_Decode, 224, 16, 153, 3, // Opcode: LDAPRX +/* 75432 */ MCD_OPC_FilterValue, 3, 247, 44, 0, // Skip to: 86948 +/* 75437 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 75440 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75455 +/* 75445 */ MCD_OPC_CheckPredicate, 1, 234, 44, 0, // Skip to: 86948 +/* 75450 */ MCD_OPC_Decode, 210, 16, 155, 3, // Opcode: LDADDALX +/* 75455 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75470 +/* 75460 */ MCD_OPC_CheckPredicate, 1, 219, 44, 0, // Skip to: 86948 +/* 75465 */ MCD_OPC_Decode, 249, 16, 155, 3, // Opcode: LDCLRALX +/* 75470 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75485 +/* 75475 */ MCD_OPC_CheckPredicate, 1, 204, 44, 0, // Skip to: 86948 +/* 75480 */ MCD_OPC_Decode, 137, 17, 155, 3, // Opcode: LDEORALX +/* 75485 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75500 +/* 75490 */ MCD_OPC_CheckPredicate, 1, 189, 44, 0, // Skip to: 86948 +/* 75495 */ MCD_OPC_Decode, 174, 18, 155, 3, // Opcode: LDSETALX +/* 75500 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75515 +/* 75505 */ MCD_OPC_CheckPredicate, 1, 174, 44, 0, // Skip to: 86948 +/* 75510 */ MCD_OPC_Decode, 190, 18, 155, 3, // Opcode: LDSMAXALX +/* 75515 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75530 +/* 75520 */ MCD_OPC_CheckPredicate, 1, 159, 44, 0, // Skip to: 86948 +/* 75525 */ MCD_OPC_Decode, 206, 18, 155, 3, // Opcode: LDSMINALX +/* 75530 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 75545 +/* 75535 */ MCD_OPC_CheckPredicate, 1, 144, 44, 0, // Skip to: 86948 +/* 75540 */ MCD_OPC_Decode, 231, 18, 155, 3, // Opcode: LDUMAXALX +/* 75545 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75560 +/* 75550 */ MCD_OPC_CheckPredicate, 1, 129, 44, 0, // Skip to: 86948 +/* 75555 */ MCD_OPC_Decode, 247, 18, 155, 3, // Opcode: LDUMINALX +/* 75560 */ MCD_OPC_FilterValue, 8, 119, 44, 0, // Skip to: 86948 +/* 75565 */ MCD_OPC_CheckPredicate, 1, 114, 44, 0, // Skip to: 86948 +/* 75570 */ MCD_OPC_Decode, 158, 30, 155, 3, // Opcode: SWPALX +/* 75575 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 75597 +/* 75580 */ MCD_OPC_CheckPredicate, 13, 99, 44, 0, // Skip to: 86948 +/* 75585 */ MCD_OPC_CheckField, 21, 1, 1, 92, 44, 0, // Skip to: 86948 +/* 75592 */ MCD_OPC_Decode, 217, 17, 156, 3, // Opcode: LDRABindexed +/* 75597 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 75639 +/* 75602 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 75605 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 75622 +/* 75610 */ MCD_OPC_CheckField, 21, 2, 1, 67, 44, 0, // Skip to: 86948 +/* 75617 */ MCD_OPC_Decode, 153, 21, 158, 3, // Opcode: PRFMroW +/* 75622 */ MCD_OPC_FilterValue, 3, 57, 44, 0, // Skip to: 86948 +/* 75627 */ MCD_OPC_CheckField, 21, 2, 1, 50, 44, 0, // Skip to: 86948 +/* 75634 */ MCD_OPC_Decode, 154, 21, 159, 3, // Opcode: PRFMroX +/* 75639 */ MCD_OPC_FilterValue, 3, 40, 44, 0, // Skip to: 86948 +/* 75644 */ MCD_OPC_CheckPredicate, 13, 35, 44, 0, // Skip to: 86948 +/* 75649 */ MCD_OPC_CheckField, 21, 1, 1, 28, 44, 0, // Skip to: 86948 +/* 75656 */ MCD_OPC_Decode, 218, 17, 157, 3, // Opcode: LDRABwriteback +/* 75661 */ MCD_OPC_FilterValue, 2, 23, 0, 0, // Skip to: 75689 +/* 75666 */ MCD_OPC_ExtractField, 22, 1, // Inst{22} ... +/* 75669 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75679 +/* 75674 */ MCD_OPC_Decode, 189, 29, 137, 3, // Opcode: STRXui +/* 75679 */ MCD_OPC_FilterValue, 1, 0, 44, 0, // Skip to: 86948 +/* 75684 */ MCD_OPC_Decode, 166, 18, 137, 3, // Opcode: LDRXui +/* 75689 */ MCD_OPC_FilterValue, 3, 12, 0, 0, // Skip to: 75706 +/* 75694 */ MCD_OPC_CheckField, 22, 1, 0, 239, 43, 0, // Skip to: 86948 +/* 75701 */ MCD_OPC_Decode, 155, 21, 137, 3, // Opcode: PRFMui +/* 75706 */ MCD_OPC_FilterValue, 4, 229, 43, 0, // Skip to: 86948 +/* 75711 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 75714 */ MCD_OPC_FilterValue, 0, 37, 0, 0, // Skip to: 75756 +/* 75719 */ MCD_OPC_ExtractField, 21, 2, // Inst{22-21} ... +/* 75722 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 75739 +/* 75727 */ MCD_OPC_CheckField, 12, 4, 0, 206, 43, 0, // Skip to: 86948 +/* 75734 */ MCD_OPC_Decode, 179, 22, 142, 3, // Opcode: SBCSXr +/* 75739 */ MCD_OPC_FilterValue, 2, 196, 43, 0, // Skip to: 86948 +/* 75744 */ MCD_OPC_CheckField, 4, 1, 0, 189, 43, 0, // Skip to: 86948 +/* 75751 */ MCD_OPC_Decode, 131, 3, 149, 3, // Opcode: CCMPXr +/* 75756 */ MCD_OPC_FilterValue, 2, 179, 43, 0, // Skip to: 86948 +/* 75761 */ MCD_OPC_CheckField, 21, 2, 2, 172, 43, 0, // Skip to: 86948 +/* 75768 */ MCD_OPC_CheckField, 4, 1, 0, 165, 43, 0, // Skip to: 86948 +/* 75775 */ MCD_OPC_Decode, 130, 3, 150, 3, // Opcode: CCMPXi +/* 75780 */ MCD_OPC_FilterValue, 7, 155, 43, 0, // Skip to: 86948 +/* 75785 */ MCD_OPC_ExtractField, 29, 3, // Inst{31-29} ... +/* 75788 */ MCD_OPC_FilterValue, 0, 103, 10, 0, // Skip to: 78456 +/* 75793 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 75796 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 75806 +/* 75801 */ MCD_OPC_Decode, 149, 18, 160, 3, // Opcode: LDRSl +/* 75806 */ MCD_OPC_FilterValue, 2, 105, 9, 0, // Skip to: 78220 +/* 75811 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 75814 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 75882 +/* 75819 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... +/* 75822 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 75837 +/* 75827 */ MCD_OPC_CheckPredicate, 16, 108, 43, 0, // Skip to: 86948 +/* 75832 */ MCD_OPC_Decode, 186, 22, 161, 3, // Opcode: SCVTFSWSri +/* 75837 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 75852 +/* 75842 */ MCD_OPC_CheckPredicate, 16, 93, 43, 0, // Skip to: 86948 +/* 75847 */ MCD_OPC_Decode, 173, 31, 161, 3, // Opcode: UCVTFSWSri +/* 75852 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 75867 +/* 75857 */ MCD_OPC_CheckPredicate, 16, 78, 43, 0, // Skip to: 86948 +/* 75862 */ MCD_OPC_Decode, 220, 8, 162, 3, // Opcode: FCVTZSSWSri +/* 75867 */ MCD_OPC_FilterValue, 51, 68, 43, 0, // Skip to: 86948 +/* 75872 */ MCD_OPC_CheckPredicate, 16, 63, 43, 0, // Skip to: 86948 +/* 75877 */ MCD_OPC_Decode, 255, 8, 162, 3, // Opcode: FCVTZUSWSri +/* 75882 */ MCD_OPC_FilterValue, 1, 222, 2, 0, // Skip to: 76621 +/* 75887 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 75890 */ MCD_OPC_FilterValue, 0, 18, 2, 0, // Skip to: 76425 +/* 75895 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 75898 */ MCD_OPC_FilterValue, 0, 244, 1, 0, // Skip to: 76403 +/* 75903 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 75906 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 76124 +/* 75911 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 75914 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 75929 +/* 75919 */ MCD_OPC_CheckPredicate, 16, 16, 43, 0, // Skip to: 86948 +/* 75924 */ MCD_OPC_Decode, 155, 8, 163, 3, // Opcode: FCVTNSUWSr +/* 75929 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 75944 +/* 75934 */ MCD_OPC_CheckPredicate, 16, 1, 43, 0, // Skip to: 86948 +/* 75939 */ MCD_OPC_Decode, 169, 8, 163, 3, // Opcode: FCVTNUUWSr +/* 75944 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 75959 +/* 75949 */ MCD_OPC_CheckPredicate, 16, 242, 42, 0, // Skip to: 86948 +/* 75954 */ MCD_OPC_Decode, 192, 22, 164, 3, // Opcode: SCVTFUWSri +/* 75959 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 75974 +/* 75964 */ MCD_OPC_CheckPredicate, 16, 227, 42, 0, // Skip to: 86948 +/* 75969 */ MCD_OPC_Decode, 179, 31, 164, 3, // Opcode: UCVTFUWSri +/* 75974 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 75989 +/* 75979 */ MCD_OPC_CheckPredicate, 16, 212, 42, 0, // Skip to: 86948 +/* 75984 */ MCD_OPC_Decode, 219, 7, 163, 3, // Opcode: FCVTASUWSr +/* 75989 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76004 +/* 75994 */ MCD_OPC_CheckPredicate, 16, 197, 42, 0, // Skip to: 86948 +/* 75999 */ MCD_OPC_Decode, 233, 7, 163, 3, // Opcode: FCVTAUUWSr +/* 76004 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76019 +/* 76009 */ MCD_OPC_CheckPredicate, 16, 182, 42, 0, // Skip to: 86948 +/* 76014 */ MCD_OPC_Decode, 226, 10, 163, 3, // Opcode: FMOVSWr +/* 76019 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76034 +/* 76024 */ MCD_OPC_CheckPredicate, 16, 167, 42, 0, // Skip to: 86948 +/* 76029 */ MCD_OPC_Decode, 230, 10, 164, 3, // Opcode: FMOVWSr +/* 76034 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76049 +/* 76039 */ MCD_OPC_CheckPredicate, 16, 152, 42, 0, // Skip to: 86948 +/* 76044 */ MCD_OPC_Decode, 187, 8, 163, 3, // Opcode: FCVTPSUWSr +/* 76049 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 76064 +/* 76054 */ MCD_OPC_CheckPredicate, 16, 137, 42, 0, // Skip to: 86948 +/* 76059 */ MCD_OPC_Decode, 201, 8, 163, 3, // Opcode: FCVTPUUWSr +/* 76064 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76079 +/* 76069 */ MCD_OPC_CheckPredicate, 16, 122, 42, 0, // Skip to: 86948 +/* 76074 */ MCD_OPC_Decode, 255, 7, 163, 3, // Opcode: FCVTMSUWSr +/* 76079 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 76094 +/* 76084 */ MCD_OPC_CheckPredicate, 16, 107, 42, 0, // Skip to: 86948 +/* 76089 */ MCD_OPC_Decode, 141, 8, 163, 3, // Opcode: FCVTMUUWSr +/* 76094 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 76109 +/* 76099 */ MCD_OPC_CheckPredicate, 16, 92, 42, 0, // Skip to: 86948 +/* 76104 */ MCD_OPC_Decode, 226, 8, 163, 3, // Opcode: FCVTZSUWSr +/* 76109 */ MCD_OPC_FilterValue, 25, 82, 42, 0, // Skip to: 86948 +/* 76114 */ MCD_OPC_CheckPredicate, 16, 77, 42, 0, // Skip to: 86948 +/* 76119 */ MCD_OPC_Decode, 133, 9, 163, 3, // Opcode: FCVTZUUWSr +/* 76124 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 76192 +/* 76129 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 76132 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76147 +/* 76137 */ MCD_OPC_CheckPredicate, 16, 54, 42, 0, // Skip to: 86948 +/* 76142 */ MCD_OPC_Decode, 207, 7, 165, 3, // Opcode: FCMPSrr +/* 76147 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76162 +/* 76152 */ MCD_OPC_CheckPredicate, 16, 39, 42, 0, // Skip to: 86948 +/* 76157 */ MCD_OPC_Decode, 206, 7, 166, 3, // Opcode: FCMPSri +/* 76162 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76177 +/* 76167 */ MCD_OPC_CheckPredicate, 16, 24, 42, 0, // Skip to: 86948 +/* 76172 */ MCD_OPC_Decode, 203, 7, 165, 3, // Opcode: FCMPESrr +/* 76177 */ MCD_OPC_FilterValue, 24, 14, 42, 0, // Skip to: 86948 +/* 76182 */ MCD_OPC_CheckPredicate, 16, 9, 42, 0, // Skip to: 86948 +/* 76187 */ MCD_OPC_Decode, 202, 7, 166, 3, // Opcode: FCMPESri +/* 76192 */ MCD_OPC_FilterValue, 2, 93, 0, 0, // Skip to: 76290 +/* 76197 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 76200 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76215 +/* 76205 */ MCD_OPC_CheckPredicate, 16, 242, 41, 0, // Skip to: 86948 +/* 76210 */ MCD_OPC_Decode, 228, 10, 167, 3, // Opcode: FMOVSr +/* 76215 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76230 +/* 76220 */ MCD_OPC_CheckPredicate, 16, 227, 41, 0, // Skip to: 86948 +/* 76225 */ MCD_OPC_Decode, 166, 11, 167, 3, // Opcode: FNEGSr +/* 76230 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76245 +/* 76235 */ MCD_OPC_CheckPredicate, 16, 212, 41, 0, // Skip to: 86948 +/* 76240 */ MCD_OPC_Decode, 131, 12, 167, 3, // Opcode: FRINTNSr +/* 76245 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76260 +/* 76250 */ MCD_OPC_CheckPredicate, 16, 197, 41, 0, // Skip to: 86948 +/* 76255 */ MCD_OPC_Decode, 248, 11, 167, 3, // Opcode: FRINTMSr +/* 76260 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76275 +/* 76265 */ MCD_OPC_CheckPredicate, 16, 182, 41, 0, // Skip to: 86948 +/* 76270 */ MCD_OPC_Decode, 226, 11, 167, 3, // Opcode: FRINTASr +/* 76275 */ MCD_OPC_FilterValue, 7, 172, 41, 0, // Skip to: 86948 +/* 76280 */ MCD_OPC_CheckPredicate, 16, 167, 41, 0, // Skip to: 86948 +/* 76285 */ MCD_OPC_Decode, 153, 12, 167, 3, // Opcode: FRINTXSr +/* 76290 */ MCD_OPC_FilterValue, 6, 157, 41, 0, // Skip to: 86948 +/* 76295 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 76298 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76313 +/* 76303 */ MCD_OPC_CheckPredicate, 16, 144, 41, 0, // Skip to: 86948 +/* 76308 */ MCD_OPC_Decode, 141, 6, 167, 3, // Opcode: FABSSr +/* 76313 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76328 +/* 76318 */ MCD_OPC_CheckPredicate, 16, 129, 41, 0, // Skip to: 86948 +/* 76323 */ MCD_OPC_Decode, 200, 12, 167, 3, // Opcode: FSQRTSr +/* 76328 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76343 +/* 76333 */ MCD_OPC_CheckPredicate, 16, 114, 41, 0, // Skip to: 86948 +/* 76338 */ MCD_OPC_Decode, 246, 7, 168, 3, // Opcode: FCVTDSr +/* 76343 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76358 +/* 76348 */ MCD_OPC_CheckPredicate, 16, 99, 41, 0, // Skip to: 86948 +/* 76353 */ MCD_OPC_Decode, 248, 7, 169, 3, // Opcode: FCVTHSr +/* 76358 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76373 +/* 76363 */ MCD_OPC_CheckPredicate, 16, 84, 41, 0, // Skip to: 86948 +/* 76368 */ MCD_OPC_Decode, 142, 12, 167, 3, // Opcode: FRINTPSr +/* 76373 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76388 +/* 76378 */ MCD_OPC_CheckPredicate, 16, 69, 41, 0, // Skip to: 86948 +/* 76383 */ MCD_OPC_Decode, 164, 12, 167, 3, // Opcode: FRINTZSr +/* 76388 */ MCD_OPC_FilterValue, 7, 59, 41, 0, // Skip to: 86948 +/* 76393 */ MCD_OPC_CheckPredicate, 16, 54, 41, 0, // Skip to: 86948 +/* 76398 */ MCD_OPC_Decode, 237, 11, 167, 3, // Opcode: FRINTISr +/* 76403 */ MCD_OPC_FilterValue, 1, 44, 41, 0, // Skip to: 86948 +/* 76408 */ MCD_OPC_CheckPredicate, 16, 39, 41, 0, // Skip to: 86948 +/* 76413 */ MCD_OPC_CheckField, 5, 5, 0, 32, 41, 0, // Skip to: 86948 +/* 76420 */ MCD_OPC_Decode, 227, 10, 170, 3, // Opcode: FMOVSi +/* 76425 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 76463 +/* 76430 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 76433 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76448 +/* 76438 */ MCD_OPC_CheckPredicate, 16, 9, 41, 0, // Skip to: 86948 +/* 76443 */ MCD_OPC_Decode, 216, 6, 171, 3, // Opcode: FCCMPSrr +/* 76448 */ MCD_OPC_FilterValue, 1, 255, 40, 0, // Skip to: 86948 +/* 76453 */ MCD_OPC_CheckPredicate, 16, 250, 40, 0, // Skip to: 86948 +/* 76458 */ MCD_OPC_Decode, 214, 6, 171, 3, // Opcode: FCCMPESrr +/* 76463 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 76606 +/* 76468 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 76471 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76486 +/* 76476 */ MCD_OPC_CheckPredicate, 16, 227, 40, 0, // Skip to: 86948 +/* 76481 */ MCD_OPC_Decode, 247, 10, 172, 3, // Opcode: FMULSrr +/* 76486 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76501 +/* 76491 */ MCD_OPC_CheckPredicate, 16, 212, 40, 0, // Skip to: 86948 +/* 76496 */ MCD_OPC_Decode, 171, 9, 172, 3, // Opcode: FDIVSrr +/* 76501 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76516 +/* 76506 */ MCD_OPC_CheckPredicate, 16, 197, 40, 0, // Skip to: 86948 +/* 76511 */ MCD_OPC_Decode, 185, 6, 172, 3, // Opcode: FADDSrr +/* 76516 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76531 +/* 76521 */ MCD_OPC_CheckPredicate, 16, 182, 40, 0, // Skip to: 86948 +/* 76526 */ MCD_OPC_Decode, 217, 12, 172, 3, // Opcode: FSUBSrr +/* 76531 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76546 +/* 76536 */ MCD_OPC_CheckPredicate, 16, 167, 40, 0, // Skip to: 86948 +/* 76541 */ MCD_OPC_Decode, 231, 9, 172, 3, // Opcode: FMAXSrr +/* 76546 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76561 +/* 76551 */ MCD_OPC_CheckPredicate, 16, 152, 40, 0, // Skip to: 86948 +/* 76556 */ MCD_OPC_Decode, 159, 10, 172, 3, // Opcode: FMINSrr +/* 76561 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 76576 +/* 76566 */ MCD_OPC_CheckPredicate, 16, 137, 40, 0, // Skip to: 86948 +/* 76571 */ MCD_OPC_Decode, 205, 9, 172, 3, // Opcode: FMAXNMSrr +/* 76576 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76591 +/* 76581 */ MCD_OPC_CheckPredicate, 16, 122, 40, 0, // Skip to: 86948 +/* 76586 */ MCD_OPC_Decode, 133, 10, 172, 3, // Opcode: FMINNMSrr +/* 76591 */ MCD_OPC_FilterValue, 8, 112, 40, 0, // Skip to: 86948 +/* 76596 */ MCD_OPC_CheckPredicate, 16, 107, 40, 0, // Skip to: 86948 +/* 76601 */ MCD_OPC_Decode, 195, 11, 172, 3, // Opcode: FNMULSrr +/* 76606 */ MCD_OPC_FilterValue, 3, 97, 40, 0, // Skip to: 86948 +/* 76611 */ MCD_OPC_CheckPredicate, 16, 92, 40, 0, // Skip to: 86948 +/* 76616 */ MCD_OPC_Decode, 216, 7, 173, 3, // Opcode: FCSELSrrr +/* 76621 */ MCD_OPC_FilterValue, 2, 63, 0, 0, // Skip to: 76689 +/* 76626 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... +/* 76629 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76644 +/* 76634 */ MCD_OPC_CheckPredicate, 16, 69, 40, 0, // Skip to: 86948 +/* 76639 */ MCD_OPC_Decode, 184, 22, 174, 3, // Opcode: SCVTFSWDri +/* 76644 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 76659 +/* 76649 */ MCD_OPC_CheckPredicate, 16, 54, 40, 0, // Skip to: 86948 +/* 76654 */ MCD_OPC_Decode, 171, 31, 174, 3, // Opcode: UCVTFSWDri +/* 76659 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 76674 +/* 76664 */ MCD_OPC_CheckPredicate, 16, 39, 40, 0, // Skip to: 86948 +/* 76669 */ MCD_OPC_Decode, 218, 8, 175, 3, // Opcode: FCVTZSSWDri +/* 76674 */ MCD_OPC_FilterValue, 51, 29, 40, 0, // Skip to: 86948 +/* 76679 */ MCD_OPC_CheckPredicate, 16, 24, 40, 0, // Skip to: 86948 +/* 76684 */ MCD_OPC_Decode, 253, 8, 175, 3, // Opcode: FCVTZUSWDri +/* 76689 */ MCD_OPC_FilterValue, 3, 207, 2, 0, // Skip to: 77413 +/* 76694 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 76697 */ MCD_OPC_FilterValue, 0, 3, 2, 0, // Skip to: 77217 +/* 76702 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 76705 */ MCD_OPC_FilterValue, 0, 229, 1, 0, // Skip to: 77195 +/* 76710 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 76713 */ MCD_OPC_FilterValue, 0, 198, 0, 0, // Skip to: 76916 +/* 76718 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 76721 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76736 +/* 76726 */ MCD_OPC_CheckPredicate, 16, 233, 39, 0, // Skip to: 86948 +/* 76731 */ MCD_OPC_Decode, 153, 8, 176, 3, // Opcode: FCVTNSUWDr +/* 76736 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 76751 +/* 76741 */ MCD_OPC_CheckPredicate, 16, 218, 39, 0, // Skip to: 86948 +/* 76746 */ MCD_OPC_Decode, 167, 8, 176, 3, // Opcode: FCVTNUUWDr +/* 76751 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 76766 +/* 76756 */ MCD_OPC_CheckPredicate, 16, 203, 39, 0, // Skip to: 86948 +/* 76761 */ MCD_OPC_Decode, 190, 22, 240, 1, // Opcode: SCVTFUWDri +/* 76766 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 76781 +/* 76771 */ MCD_OPC_CheckPredicate, 16, 188, 39, 0, // Skip to: 86948 +/* 76776 */ MCD_OPC_Decode, 177, 31, 240, 1, // Opcode: UCVTFUWDri +/* 76781 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 76796 +/* 76786 */ MCD_OPC_CheckPredicate, 16, 173, 39, 0, // Skip to: 86948 +/* 76791 */ MCD_OPC_Decode, 217, 7, 176, 3, // Opcode: FCVTASUWDr +/* 76796 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 76811 +/* 76801 */ MCD_OPC_CheckPredicate, 16, 158, 39, 0, // Skip to: 86948 +/* 76806 */ MCD_OPC_Decode, 231, 7, 176, 3, // Opcode: FCVTAUUWDr +/* 76811 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76826 +/* 76816 */ MCD_OPC_CheckPredicate, 16, 143, 39, 0, // Skip to: 86948 +/* 76821 */ MCD_OPC_Decode, 185, 8, 176, 3, // Opcode: FCVTPSUWDr +/* 76826 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 76841 +/* 76831 */ MCD_OPC_CheckPredicate, 16, 128, 39, 0, // Skip to: 86948 +/* 76836 */ MCD_OPC_Decode, 199, 8, 176, 3, // Opcode: FCVTPUUWDr +/* 76841 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76856 +/* 76846 */ MCD_OPC_CheckPredicate, 16, 113, 39, 0, // Skip to: 86948 +/* 76851 */ MCD_OPC_Decode, 253, 7, 176, 3, // Opcode: FCVTMSUWDr +/* 76856 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 76871 +/* 76861 */ MCD_OPC_CheckPredicate, 16, 98, 39, 0, // Skip to: 86948 +/* 76866 */ MCD_OPC_Decode, 139, 8, 176, 3, // Opcode: FCVTMUUWDr +/* 76871 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 76886 +/* 76876 */ MCD_OPC_CheckPredicate, 16, 83, 39, 0, // Skip to: 86948 +/* 76881 */ MCD_OPC_Decode, 224, 8, 176, 3, // Opcode: FCVTZSUWDr +/* 76886 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 76901 +/* 76891 */ MCD_OPC_CheckPredicate, 16, 68, 39, 0, // Skip to: 86948 +/* 76896 */ MCD_OPC_Decode, 131, 9, 176, 3, // Opcode: FCVTZUUWDr +/* 76901 */ MCD_OPC_FilterValue, 30, 58, 39, 0, // Skip to: 86948 +/* 76906 */ MCD_OPC_CheckPredicate, 17, 53, 39, 0, // Skip to: 86948 +/* 76911 */ MCD_OPC_Decode, 186, 9, 176, 3, // Opcode: FJCVTZS +/* 76916 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 76984 +/* 76921 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 76924 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 76939 +/* 76929 */ MCD_OPC_CheckPredicate, 16, 30, 39, 0, // Skip to: 86948 +/* 76934 */ MCD_OPC_Decode, 197, 7, 177, 3, // Opcode: FCMPDrr +/* 76939 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 76954 +/* 76944 */ MCD_OPC_CheckPredicate, 16, 15, 39, 0, // Skip to: 86948 +/* 76949 */ MCD_OPC_Decode, 196, 7, 178, 3, // Opcode: FCMPDri +/* 76954 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 76969 +/* 76959 */ MCD_OPC_CheckPredicate, 16, 0, 39, 0, // Skip to: 86948 +/* 76964 */ MCD_OPC_Decode, 199, 7, 177, 3, // Opcode: FCMPEDrr +/* 76969 */ MCD_OPC_FilterValue, 24, 246, 38, 0, // Skip to: 86948 +/* 76974 */ MCD_OPC_CheckPredicate, 16, 241, 38, 0, // Skip to: 86948 +/* 76979 */ MCD_OPC_Decode, 198, 7, 178, 3, // Opcode: FCMPEDri +/* 76984 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 77097 +/* 76989 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 76992 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77007 +/* 76997 */ MCD_OPC_CheckPredicate, 16, 218, 38, 0, // Skip to: 86948 +/* 77002 */ MCD_OPC_Decode, 219, 10, 239, 1, // Opcode: FMOVDr +/* 77007 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77022 +/* 77012 */ MCD_OPC_CheckPredicate, 16, 203, 38, 0, // Skip to: 86948 +/* 77017 */ MCD_OPC_Decode, 164, 11, 239, 1, // Opcode: FNEGDr +/* 77022 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77037 +/* 77027 */ MCD_OPC_CheckPredicate, 16, 188, 38, 0, // Skip to: 86948 +/* 77032 */ MCD_OPC_Decode, 213, 8, 166, 2, // Opcode: FCVTSDr +/* 77037 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77052 +/* 77042 */ MCD_OPC_CheckPredicate, 16, 173, 38, 0, // Skip to: 86948 +/* 77047 */ MCD_OPC_Decode, 129, 12, 239, 1, // Opcode: FRINTNDr +/* 77052 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77067 +/* 77057 */ MCD_OPC_CheckPredicate, 16, 158, 38, 0, // Skip to: 86948 +/* 77062 */ MCD_OPC_Decode, 246, 11, 239, 1, // Opcode: FRINTMDr +/* 77067 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77082 +/* 77072 */ MCD_OPC_CheckPredicate, 16, 143, 38, 0, // Skip to: 86948 +/* 77077 */ MCD_OPC_Decode, 224, 11, 239, 1, // Opcode: FRINTADr +/* 77082 */ MCD_OPC_FilterValue, 7, 133, 38, 0, // Skip to: 86948 +/* 77087 */ MCD_OPC_CheckPredicate, 16, 128, 38, 0, // Skip to: 86948 +/* 77092 */ MCD_OPC_Decode, 151, 12, 239, 1, // Opcode: FRINTXDr +/* 77097 */ MCD_OPC_FilterValue, 6, 118, 38, 0, // Skip to: 86948 +/* 77102 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 77105 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77120 +/* 77110 */ MCD_OPC_CheckPredicate, 16, 105, 38, 0, // Skip to: 86948 +/* 77115 */ MCD_OPC_Decode, 139, 6, 239, 1, // Opcode: FABSDr +/* 77120 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77135 +/* 77125 */ MCD_OPC_CheckPredicate, 16, 90, 38, 0, // Skip to: 86948 +/* 77130 */ MCD_OPC_Decode, 198, 12, 239, 1, // Opcode: FSQRTDr +/* 77135 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77150 +/* 77140 */ MCD_OPC_CheckPredicate, 16, 75, 38, 0, // Skip to: 86948 +/* 77145 */ MCD_OPC_Decode, 247, 7, 249, 1, // Opcode: FCVTHDr +/* 77150 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77165 +/* 77155 */ MCD_OPC_CheckPredicate, 16, 60, 38, 0, // Skip to: 86948 +/* 77160 */ MCD_OPC_Decode, 140, 12, 239, 1, // Opcode: FRINTPDr +/* 77165 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77180 +/* 77170 */ MCD_OPC_CheckPredicate, 16, 45, 38, 0, // Skip to: 86948 +/* 77175 */ MCD_OPC_Decode, 162, 12, 239, 1, // Opcode: FRINTZDr +/* 77180 */ MCD_OPC_FilterValue, 7, 35, 38, 0, // Skip to: 86948 +/* 77185 */ MCD_OPC_CheckPredicate, 16, 30, 38, 0, // Skip to: 86948 +/* 77190 */ MCD_OPC_Decode, 235, 11, 239, 1, // Opcode: FRINTIDr +/* 77195 */ MCD_OPC_FilterValue, 1, 20, 38, 0, // Skip to: 86948 +/* 77200 */ MCD_OPC_CheckPredicate, 16, 15, 38, 0, // Skip to: 86948 +/* 77205 */ MCD_OPC_CheckField, 5, 5, 0, 8, 38, 0, // Skip to: 86948 +/* 77212 */ MCD_OPC_Decode, 218, 10, 179, 3, // Opcode: FMOVDi +/* 77217 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 77255 +/* 77222 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 77225 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77240 +/* 77230 */ MCD_OPC_CheckPredicate, 16, 241, 37, 0, // Skip to: 86948 +/* 77235 */ MCD_OPC_Decode, 211, 6, 180, 3, // Opcode: FCCMPDrr +/* 77240 */ MCD_OPC_FilterValue, 1, 231, 37, 0, // Skip to: 86948 +/* 77245 */ MCD_OPC_CheckPredicate, 16, 226, 37, 0, // Skip to: 86948 +/* 77250 */ MCD_OPC_Decode, 212, 6, 180, 3, // Opcode: FCCMPEDrr +/* 77255 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 77398 +/* 77260 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 77263 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77278 +/* 77268 */ MCD_OPC_CheckPredicate, 16, 203, 37, 0, // Skip to: 86948 +/* 77273 */ MCD_OPC_Decode, 245, 10, 238, 1, // Opcode: FMULDrr +/* 77278 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77293 +/* 77283 */ MCD_OPC_CheckPredicate, 16, 188, 37, 0, // Skip to: 86948 +/* 77288 */ MCD_OPC_Decode, 166, 9, 238, 1, // Opcode: FDIVDrr +/* 77293 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77308 +/* 77298 */ MCD_OPC_CheckPredicate, 16, 173, 37, 0, // Skip to: 86948 +/* 77303 */ MCD_OPC_Decode, 175, 6, 238, 1, // Opcode: FADDDrr +/* 77308 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77323 +/* 77313 */ MCD_OPC_CheckPredicate, 16, 158, 37, 0, // Skip to: 86948 +/* 77318 */ MCD_OPC_Decode, 209, 12, 238, 1, // Opcode: FSUBDrr +/* 77323 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77338 +/* 77328 */ MCD_OPC_CheckPredicate, 16, 143, 37, 0, // Skip to: 86948 +/* 77333 */ MCD_OPC_Decode, 193, 9, 238, 1, // Opcode: FMAXDrr +/* 77338 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77353 +/* 77343 */ MCD_OPC_CheckPredicate, 16, 128, 37, 0, // Skip to: 86948 +/* 77348 */ MCD_OPC_Decode, 249, 9, 238, 1, // Opcode: FMINDrr +/* 77353 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77368 +/* 77358 */ MCD_OPC_CheckPredicate, 16, 113, 37, 0, // Skip to: 86948 +/* 77363 */ MCD_OPC_Decode, 195, 9, 238, 1, // Opcode: FMAXNMDrr +/* 77368 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77383 +/* 77373 */ MCD_OPC_CheckPredicate, 16, 98, 37, 0, // Skip to: 86948 +/* 77378 */ MCD_OPC_Decode, 251, 9, 238, 1, // Opcode: FMINNMDrr +/* 77383 */ MCD_OPC_FilterValue, 8, 88, 37, 0, // Skip to: 86948 +/* 77388 */ MCD_OPC_CheckPredicate, 16, 83, 37, 0, // Skip to: 86948 +/* 77393 */ MCD_OPC_Decode, 193, 11, 238, 1, // Opcode: FNMULDrr +/* 77398 */ MCD_OPC_FilterValue, 3, 73, 37, 0, // Skip to: 86948 +/* 77403 */ MCD_OPC_CheckPredicate, 16, 68, 37, 0, // Skip to: 86948 +/* 77408 */ MCD_OPC_Decode, 214, 7, 181, 3, // Opcode: FCSELDrrr +/* 77413 */ MCD_OPC_FilterValue, 6, 63, 0, 0, // Skip to: 77481 +/* 77418 */ MCD_OPC_ExtractField, 15, 6, // Inst{20-15} ... +/* 77421 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77436 +/* 77426 */ MCD_OPC_CheckPredicate, 18, 45, 37, 0, // Skip to: 86948 +/* 77431 */ MCD_OPC_Decode, 185, 22, 182, 3, // Opcode: SCVTFSWHri +/* 77436 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77451 +/* 77441 */ MCD_OPC_CheckPredicate, 18, 30, 37, 0, // Skip to: 86948 +/* 77446 */ MCD_OPC_Decode, 172, 31, 182, 3, // Opcode: UCVTFSWHri +/* 77451 */ MCD_OPC_FilterValue, 49, 10, 0, 0, // Skip to: 77466 +/* 77456 */ MCD_OPC_CheckPredicate, 18, 15, 37, 0, // Skip to: 86948 +/* 77461 */ MCD_OPC_Decode, 219, 8, 183, 3, // Opcode: FCVTZSSWHri +/* 77466 */ MCD_OPC_FilterValue, 51, 5, 37, 0, // Skip to: 86948 +/* 77471 */ MCD_OPC_CheckPredicate, 18, 0, 37, 0, // Skip to: 86948 +/* 77476 */ MCD_OPC_Decode, 254, 8, 183, 3, // Opcode: FCVTZUSWHri +/* 77481 */ MCD_OPC_FilterValue, 7, 246, 36, 0, // Skip to: 86948 +/* 77486 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 77489 */ MCD_OPC_FilterValue, 0, 18, 2, 0, // Skip to: 78024 +/* 77494 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ... +/* 77497 */ MCD_OPC_FilterValue, 0, 244, 1, 0, // Skip to: 78002 +/* 77502 */ MCD_OPC_ExtractField, 13, 3, // Inst{15-13} ... +/* 77505 */ MCD_OPC_FilterValue, 0, 213, 0, 0, // Skip to: 77723 +/* 77510 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 77513 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77528 +/* 77518 */ MCD_OPC_CheckPredicate, 18, 209, 36, 0, // Skip to: 86948 +/* 77523 */ MCD_OPC_Decode, 154, 8, 184, 3, // Opcode: FCVTNSUWHr +/* 77528 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77543 +/* 77533 */ MCD_OPC_CheckPredicate, 18, 194, 36, 0, // Skip to: 86948 +/* 77538 */ MCD_OPC_Decode, 168, 8, 184, 3, // Opcode: FCVTNUUWHr +/* 77543 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77558 +/* 77548 */ MCD_OPC_CheckPredicate, 18, 179, 36, 0, // Skip to: 86948 +/* 77553 */ MCD_OPC_Decode, 191, 22, 185, 3, // Opcode: SCVTFUWHri +/* 77558 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 77573 +/* 77563 */ MCD_OPC_CheckPredicate, 18, 164, 36, 0, // Skip to: 86948 +/* 77568 */ MCD_OPC_Decode, 178, 31, 185, 3, // Opcode: UCVTFUWHri +/* 77573 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77588 +/* 77578 */ MCD_OPC_CheckPredicate, 18, 149, 36, 0, // Skip to: 86948 +/* 77583 */ MCD_OPC_Decode, 218, 7, 184, 3, // Opcode: FCVTASUWHr +/* 77588 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77603 +/* 77593 */ MCD_OPC_CheckPredicate, 18, 134, 36, 0, // Skip to: 86948 +/* 77598 */ MCD_OPC_Decode, 232, 7, 184, 3, // Opcode: FCVTAUUWHr +/* 77603 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77618 +/* 77608 */ MCD_OPC_CheckPredicate, 18, 119, 36, 0, // Skip to: 86948 +/* 77613 */ MCD_OPC_Decode, 221, 10, 184, 3, // Opcode: FMOVHWr +/* 77618 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 77633 +/* 77623 */ MCD_OPC_CheckPredicate, 18, 104, 36, 0, // Skip to: 86948 +/* 77628 */ MCD_OPC_Decode, 229, 10, 185, 3, // Opcode: FMOVWHr +/* 77633 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 77648 +/* 77638 */ MCD_OPC_CheckPredicate, 18, 89, 36, 0, // Skip to: 86948 +/* 77643 */ MCD_OPC_Decode, 186, 8, 184, 3, // Opcode: FCVTPSUWHr +/* 77648 */ MCD_OPC_FilterValue, 9, 10, 0, 0, // Skip to: 77663 +/* 77653 */ MCD_OPC_CheckPredicate, 18, 74, 36, 0, // Skip to: 86948 +/* 77658 */ MCD_OPC_Decode, 200, 8, 184, 3, // Opcode: FCVTPUUWHr +/* 77663 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 77678 +/* 77668 */ MCD_OPC_CheckPredicate, 18, 59, 36, 0, // Skip to: 86948 +/* 77673 */ MCD_OPC_Decode, 254, 7, 184, 3, // Opcode: FCVTMSUWHr +/* 77678 */ MCD_OPC_FilterValue, 17, 10, 0, 0, // Skip to: 77693 +/* 77683 */ MCD_OPC_CheckPredicate, 18, 44, 36, 0, // Skip to: 86948 +/* 77688 */ MCD_OPC_Decode, 140, 8, 184, 3, // Opcode: FCVTMUUWHr +/* 77693 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 77708 +/* 77698 */ MCD_OPC_CheckPredicate, 18, 29, 36, 0, // Skip to: 86948 +/* 77703 */ MCD_OPC_Decode, 225, 8, 184, 3, // Opcode: FCVTZSUWHr +/* 77708 */ MCD_OPC_FilterValue, 25, 19, 36, 0, // Skip to: 86948 +/* 77713 */ MCD_OPC_CheckPredicate, 18, 14, 36, 0, // Skip to: 86948 +/* 77718 */ MCD_OPC_Decode, 132, 9, 184, 3, // Opcode: FCVTZUUWHr +/* 77723 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 77791 +/* 77728 */ MCD_OPC_ExtractField, 0, 5, // Inst{4-0} ... +/* 77731 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77746 +/* 77736 */ MCD_OPC_CheckPredicate, 18, 247, 35, 0, // Skip to: 86948 +/* 77741 */ MCD_OPC_Decode, 205, 7, 186, 3, // Opcode: FCMPHrr +/* 77746 */ MCD_OPC_FilterValue, 8, 10, 0, 0, // Skip to: 77761 +/* 77751 */ MCD_OPC_CheckPredicate, 18, 232, 35, 0, // Skip to: 86948 +/* 77756 */ MCD_OPC_Decode, 204, 7, 187, 3, // Opcode: FCMPHri +/* 77761 */ MCD_OPC_FilterValue, 16, 10, 0, 0, // Skip to: 77776 +/* 77766 */ MCD_OPC_CheckPredicate, 18, 217, 35, 0, // Skip to: 86948 +/* 77771 */ MCD_OPC_Decode, 201, 7, 186, 3, // Opcode: FCMPEHrr +/* 77776 */ MCD_OPC_FilterValue, 24, 207, 35, 0, // Skip to: 86948 +/* 77781 */ MCD_OPC_CheckPredicate, 18, 202, 35, 0, // Skip to: 86948 +/* 77786 */ MCD_OPC_Decode, 200, 7, 187, 3, // Opcode: FCMPEHri +/* 77791 */ MCD_OPC_FilterValue, 2, 108, 0, 0, // Skip to: 77904 +/* 77796 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 77799 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77814 +/* 77804 */ MCD_OPC_CheckPredicate, 18, 179, 35, 0, // Skip to: 86948 +/* 77809 */ MCD_OPC_Decode, 224, 10, 188, 3, // Opcode: FMOVHr +/* 77814 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77829 +/* 77819 */ MCD_OPC_CheckPredicate, 18, 164, 35, 0, // Skip to: 86948 +/* 77824 */ MCD_OPC_Decode, 165, 11, 188, 3, // Opcode: FNEGHr +/* 77829 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77844 +/* 77834 */ MCD_OPC_CheckPredicate, 16, 149, 35, 0, // Skip to: 86948 +/* 77839 */ MCD_OPC_Decode, 214, 8, 189, 3, // Opcode: FCVTSHr +/* 77844 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77859 +/* 77849 */ MCD_OPC_CheckPredicate, 18, 134, 35, 0, // Skip to: 86948 +/* 77854 */ MCD_OPC_Decode, 130, 12, 188, 3, // Opcode: FRINTNHr +/* 77859 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77874 +/* 77864 */ MCD_OPC_CheckPredicate, 18, 119, 35, 0, // Skip to: 86948 +/* 77869 */ MCD_OPC_Decode, 247, 11, 188, 3, // Opcode: FRINTMHr +/* 77874 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 77889 +/* 77879 */ MCD_OPC_CheckPredicate, 18, 104, 35, 0, // Skip to: 86948 +/* 77884 */ MCD_OPC_Decode, 225, 11, 188, 3, // Opcode: FRINTAHr +/* 77889 */ MCD_OPC_FilterValue, 7, 94, 35, 0, // Skip to: 86948 +/* 77894 */ MCD_OPC_CheckPredicate, 18, 89, 35, 0, // Skip to: 86948 +/* 77899 */ MCD_OPC_Decode, 152, 12, 188, 3, // Opcode: FRINTXHr +/* 77904 */ MCD_OPC_FilterValue, 6, 79, 35, 0, // Skip to: 86948 +/* 77909 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ... +/* 77912 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 77927 +/* 77917 */ MCD_OPC_CheckPredicate, 18, 66, 35, 0, // Skip to: 86948 +/* 77922 */ MCD_OPC_Decode, 140, 6, 188, 3, // Opcode: FABSHr +/* 77927 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 77942 +/* 77932 */ MCD_OPC_CheckPredicate, 18, 51, 35, 0, // Skip to: 86948 +/* 77937 */ MCD_OPC_Decode, 199, 12, 188, 3, // Opcode: FSQRTHr +/* 77942 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 77957 +/* 77947 */ MCD_OPC_CheckPredicate, 16, 36, 35, 0, // Skip to: 86948 +/* 77952 */ MCD_OPC_Decode, 245, 7, 190, 3, // Opcode: FCVTDHr +/* 77957 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 77972 +/* 77962 */ MCD_OPC_CheckPredicate, 18, 21, 35, 0, // Skip to: 86948 +/* 77967 */ MCD_OPC_Decode, 141, 12, 188, 3, // Opcode: FRINTPHr +/* 77972 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 77987 +/* 77977 */ MCD_OPC_CheckPredicate, 18, 6, 35, 0, // Skip to: 86948 +/* 77982 */ MCD_OPC_Decode, 163, 12, 188, 3, // Opcode: FRINTZHr +/* 77987 */ MCD_OPC_FilterValue, 7, 252, 34, 0, // Skip to: 86948 +/* 77992 */ MCD_OPC_CheckPredicate, 18, 247, 34, 0, // Skip to: 86948 +/* 77997 */ MCD_OPC_Decode, 236, 11, 188, 3, // Opcode: FRINTIHr +/* 78002 */ MCD_OPC_FilterValue, 1, 237, 34, 0, // Skip to: 86948 +/* 78007 */ MCD_OPC_CheckPredicate, 18, 232, 34, 0, // Skip to: 86948 +/* 78012 */ MCD_OPC_CheckField, 5, 5, 0, 225, 34, 0, // Skip to: 86948 +/* 78019 */ MCD_OPC_Decode, 223, 10, 191, 3, // Opcode: FMOVHi +/* 78024 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 78062 +/* 78029 */ MCD_OPC_ExtractField, 4, 1, // Inst{4} ... +/* 78032 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78047 +/* 78037 */ MCD_OPC_CheckPredicate, 18, 202, 34, 0, // Skip to: 86948 +/* 78042 */ MCD_OPC_Decode, 215, 6, 192, 3, // Opcode: FCCMPHrr +/* 78047 */ MCD_OPC_FilterValue, 1, 192, 34, 0, // Skip to: 86948 +/* 78052 */ MCD_OPC_CheckPredicate, 18, 187, 34, 0, // Skip to: 86948 +/* 78057 */ MCD_OPC_Decode, 213, 6, 192, 3, // Opcode: FCCMPEHrr +/* 78062 */ MCD_OPC_FilterValue, 2, 138, 0, 0, // Skip to: 78205 +/* 78067 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 78070 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78085 +/* 78075 */ MCD_OPC_CheckPredicate, 18, 164, 34, 0, // Skip to: 86948 +/* 78080 */ MCD_OPC_Decode, 246, 10, 193, 3, // Opcode: FMULHrr +/* 78085 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 78100 +/* 78090 */ MCD_OPC_CheckPredicate, 18, 149, 34, 0, // Skip to: 86948 +/* 78095 */ MCD_OPC_Decode, 167, 9, 193, 3, // Opcode: FDIVHrr +/* 78100 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 78115 +/* 78105 */ MCD_OPC_CheckPredicate, 18, 134, 34, 0, // Skip to: 86948 +/* 78110 */ MCD_OPC_Decode, 176, 6, 193, 3, // Opcode: FADDHrr +/* 78115 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 78130 +/* 78120 */ MCD_OPC_CheckPredicate, 18, 119, 34, 0, // Skip to: 86948 +/* 78125 */ MCD_OPC_Decode, 210, 12, 193, 3, // Opcode: FSUBHrr +/* 78130 */ MCD_OPC_FilterValue, 4, 10, 0, 0, // Skip to: 78145 +/* 78135 */ MCD_OPC_CheckPredicate, 18, 104, 34, 0, // Skip to: 86948 +/* 78140 */ MCD_OPC_Decode, 194, 9, 193, 3, // Opcode: FMAXHrr +/* 78145 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 78160 +/* 78150 */ MCD_OPC_CheckPredicate, 18, 89, 34, 0, // Skip to: 86948 +/* 78155 */ MCD_OPC_Decode, 250, 9, 193, 3, // Opcode: FMINHrr +/* 78160 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 78175 +/* 78165 */ MCD_OPC_CheckPredicate, 18, 74, 34, 0, // Skip to: 86948 +/* 78170 */ MCD_OPC_Decode, 196, 9, 193, 3, // Opcode: FMAXNMHrr +/* 78175 */ MCD_OPC_FilterValue, 7, 10, 0, 0, // Skip to: 78190 +/* 78180 */ MCD_OPC_CheckPredicate, 18, 59, 34, 0, // Skip to: 86948 +/* 78185 */ MCD_OPC_Decode, 252, 9, 193, 3, // Opcode: FMINNMHrr +/* 78190 */ MCD_OPC_FilterValue, 8, 49, 34, 0, // Skip to: 86948 +/* 78195 */ MCD_OPC_CheckPredicate, 18, 44, 34, 0, // Skip to: 86948 +/* 78200 */ MCD_OPC_Decode, 194, 11, 193, 3, // Opcode: FNMULHrr +/* 78205 */ MCD_OPC_FilterValue, 3, 34, 34, 0, // Skip to: 86948 +/* 78210 */ MCD_OPC_CheckPredicate, 18, 29, 34, 0, // Skip to: 86948 +/* 78215 */ MCD_OPC_Decode, 215, 7, 194, 3, // Opcode: FCSELHrrr +/* 78220 */ MCD_OPC_FilterValue, 3, 19, 34, 0, // Skip to: 86948 +/* 78225 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 78228 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 78266 +/* 78233 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 78236 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78251 +/* 78241 */ MCD_OPC_CheckPredicate, 16, 254, 33, 0, // Skip to: 86948 +/* 78246 */ MCD_OPC_Decode, 189, 9, 195, 3, // Opcode: FMADDSrrr +/* 78251 */ MCD_OPC_FilterValue, 1, 244, 33, 0, // Skip to: 86948 +/* 78256 */ MCD_OPC_CheckPredicate, 16, 239, 33, 0, // Skip to: 86948 +/* 78261 */ MCD_OPC_Decode, 244, 10, 195, 3, // Opcode: FMSUBSrrr +/* 78266 */ MCD_OPC_FilterValue, 1, 33, 0, 0, // Skip to: 78304 +/* 78271 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 78274 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78289 +/* 78279 */ MCD_OPC_CheckPredicate, 16, 216, 33, 0, // Skip to: 86948 +/* 78284 */ MCD_OPC_Decode, 177, 11, 195, 3, // Opcode: FNMADDSrrr +/* 78289 */ MCD_OPC_FilterValue, 1, 206, 33, 0, // Skip to: 86948 +/* 78294 */ MCD_OPC_CheckPredicate, 16, 201, 33, 0, // Skip to: 86948 +/* 78299 */ MCD_OPC_Decode, 192, 11, 195, 3, // Opcode: FNMSUBSrrr +/* 78304 */ MCD_OPC_FilterValue, 2, 33, 0, 0, // Skip to: 78342 +/* 78309 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 78312 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78327 +/* 78317 */ MCD_OPC_CheckPredicate, 16, 178, 33, 0, // Skip to: 86948 +/* 78322 */ MCD_OPC_Decode, 187, 9, 196, 3, // Opcode: FMADDDrrr +/* 78327 */ MCD_OPC_FilterValue, 1, 168, 33, 0, // Skip to: 86948 +/* 78332 */ MCD_OPC_CheckPredicate, 16, 163, 33, 0, // Skip to: 86948 +/* 78337 */ MCD_OPC_Decode, 242, 10, 196, 3, // Opcode: FMSUBDrrr +/* 78342 */ MCD_OPC_FilterValue, 3, 33, 0, 0, // Skip to: 78380 +/* 78347 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 78350 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78365 +/* 78355 */ MCD_OPC_CheckPredicate, 16, 140, 33, 0, // Skip to: 86948 +/* 78360 */ MCD_OPC_Decode, 175, 11, 196, 3, // Opcode: FNMADDDrrr +/* 78365 */ MCD_OPC_FilterValue, 1, 130, 33, 0, // Skip to: 86948 +/* 78370 */ MCD_OPC_CheckPredicate, 16, 125, 33, 0, // Skip to: 86948 +/* 78375 */ MCD_OPC_Decode, 190, 11, 196, 3, // Opcode: FNMSUBDrrr +/* 78380 */ MCD_OPC_FilterValue, 6, 33, 0, 0, // Skip to: 78418 +/* 78385 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 78388 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78403 +/* 78393 */ MCD_OPC_CheckPredicate, 18, 102, 33, 0, // Skip to: 86948 +/* 78398 */ MCD_OPC_Decode, 188, 9, 197, 3, // Opcode: FMADDHrrr +/* 78403 */ MCD_OPC_FilterValue, 1, 92, 33, 0, // Skip to: 86948 +/* 78408 */ MCD_OPC_CheckPredicate, 18, 87, 33, 0, // Skip to: 86948 +/* 78413 */ MCD_OPC_Decode, 243, 10, 197, 3, // Opcode: FMSUBHrrr +/* 78418 */ MCD_OPC_FilterValue, 7, 77, 33, 0, // Skip to: 86948 +/* 78423 */ MCD_OPC_ExtractField, 15, 1, // Inst{15} ... +/* 78426 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 78441 +/* 78431 */ MCD_OPC_CheckPredicate, 18, 64, 33, 0, // Skip to: 86948 +/* 78436 */ MCD_OPC_Decode, 176, 11, 197, 3, // Opcode: FNMADDHrrr +/* 78441 */ MCD_OPC_FilterValue, 1, 54, 33, 0, // Skip to: 86948 +/* 78446 */ MCD_OPC_CheckPredicate, 18, 49, 33, 0, // Skip to: 86948 +/* 78451 */ MCD_OPC_Decode, 191, 11, 197, 3, // Opcode: FNMSUBHrrr +/* 78456 */ MCD_OPC_FilterValue, 1, 191, 1, 0, // Skip to: 78908 +/* 78461 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 78464 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 78565 +/* 78469 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 78472 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78489 +/* 78477 */ MCD_OPC_CheckField, 21, 1, 0, 16, 33, 0, // Skip to: 86948 +/* 78484 */ MCD_OPC_Decode, 197, 29, 255, 2, // Opcode: STURBi +/* 78489 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78506 +/* 78494 */ MCD_OPC_CheckField, 21, 1, 0, 255, 32, 0, // Skip to: 86948 +/* 78501 */ MCD_OPC_Decode, 150, 29, 255, 2, // Opcode: STRBpost +/* 78506 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78548 +/* 78511 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 78514 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78531 +/* 78519 */ MCD_OPC_CheckField, 21, 1, 1, 230, 32, 0, // Skip to: 86948 +/* 78526 */ MCD_OPC_Decode, 152, 29, 198, 3, // Opcode: STRBroW +/* 78531 */ MCD_OPC_FilterValue, 3, 220, 32, 0, // Skip to: 86948 +/* 78536 */ MCD_OPC_CheckField, 21, 1, 1, 213, 32, 0, // Skip to: 86948 +/* 78543 */ MCD_OPC_Decode, 153, 29, 199, 3, // Opcode: STRBroX +/* 78548 */ MCD_OPC_FilterValue, 3, 203, 32, 0, // Skip to: 86948 +/* 78553 */ MCD_OPC_CheckField, 21, 1, 0, 196, 32, 0, // Skip to: 86948 +/* 78560 */ MCD_OPC_Decode, 151, 29, 255, 2, // Opcode: STRBpre +/* 78565 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 78666 +/* 78570 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 78573 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78590 +/* 78578 */ MCD_OPC_CheckField, 21, 1, 0, 171, 32, 0, // Skip to: 86948 +/* 78585 */ MCD_OPC_Decode, 131, 19, 255, 2, // Opcode: LDURBi +/* 78590 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78607 +/* 78595 */ MCD_OPC_CheckField, 21, 1, 0, 154, 32, 0, // Skip to: 86948 +/* 78602 */ MCD_OPC_Decode, 224, 17, 255, 2, // Opcode: LDRBpost +/* 78607 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78649 +/* 78612 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 78615 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78632 +/* 78620 */ MCD_OPC_CheckField, 21, 1, 1, 129, 32, 0, // Skip to: 86948 +/* 78627 */ MCD_OPC_Decode, 226, 17, 198, 3, // Opcode: LDRBroW +/* 78632 */ MCD_OPC_FilterValue, 3, 119, 32, 0, // Skip to: 86948 +/* 78637 */ MCD_OPC_CheckField, 21, 1, 1, 112, 32, 0, // Skip to: 86948 +/* 78644 */ MCD_OPC_Decode, 227, 17, 199, 3, // Opcode: LDRBroX +/* 78649 */ MCD_OPC_FilterValue, 3, 102, 32, 0, // Skip to: 86948 +/* 78654 */ MCD_OPC_CheckField, 21, 1, 0, 95, 32, 0, // Skip to: 86948 +/* 78661 */ MCD_OPC_Decode, 225, 17, 255, 2, // Opcode: LDRBpre +/* 78666 */ MCD_OPC_FilterValue, 2, 96, 0, 0, // Skip to: 78767 +/* 78671 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 78674 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78691 +/* 78679 */ MCD_OPC_CheckField, 21, 1, 0, 70, 32, 0, // Skip to: 86948 +/* 78686 */ MCD_OPC_Decode, 201, 29, 255, 2, // Opcode: STURQi +/* 78691 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78708 +/* 78696 */ MCD_OPC_CheckField, 21, 1, 0, 53, 32, 0, // Skip to: 86948 +/* 78703 */ MCD_OPC_Decode, 170, 29, 255, 2, // Opcode: STRQpost +/* 78708 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78750 +/* 78713 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 78716 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78733 +/* 78721 */ MCD_OPC_CheckField, 21, 1, 1, 28, 32, 0, // Skip to: 86948 +/* 78728 */ MCD_OPC_Decode, 172, 29, 200, 3, // Opcode: STRQroW +/* 78733 */ MCD_OPC_FilterValue, 3, 18, 32, 0, // Skip to: 86948 +/* 78738 */ MCD_OPC_CheckField, 21, 1, 1, 11, 32, 0, // Skip to: 86948 +/* 78745 */ MCD_OPC_Decode, 173, 29, 201, 3, // Opcode: STRQroX +/* 78750 */ MCD_OPC_FilterValue, 3, 1, 32, 0, // Skip to: 86948 +/* 78755 */ MCD_OPC_CheckField, 21, 1, 0, 250, 31, 0, // Skip to: 86948 +/* 78762 */ MCD_OPC_Decode, 171, 29, 255, 2, // Opcode: STRQpre +/* 78767 */ MCD_OPC_FilterValue, 3, 96, 0, 0, // Skip to: 78868 +/* 78772 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 78775 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 78792 +/* 78780 */ MCD_OPC_CheckField, 21, 1, 0, 225, 31, 0, // Skip to: 86948 +/* 78787 */ MCD_OPC_Decode, 135, 19, 255, 2, // Opcode: LDURQi +/* 78792 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 78809 +/* 78797 */ MCD_OPC_CheckField, 21, 1, 0, 208, 31, 0, // Skip to: 86948 +/* 78804 */ MCD_OPC_Decode, 246, 17, 255, 2, // Opcode: LDRQpost +/* 78809 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 78851 +/* 78814 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 78817 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 78834 +/* 78822 */ MCD_OPC_CheckField, 21, 1, 1, 183, 31, 0, // Skip to: 86948 +/* 78829 */ MCD_OPC_Decode, 248, 17, 200, 3, // Opcode: LDRQroW +/* 78834 */ MCD_OPC_FilterValue, 3, 173, 31, 0, // Skip to: 86948 +/* 78839 */ MCD_OPC_CheckField, 21, 1, 1, 166, 31, 0, // Skip to: 86948 +/* 78846 */ MCD_OPC_Decode, 249, 17, 201, 3, // Opcode: LDRQroX +/* 78851 */ MCD_OPC_FilterValue, 3, 156, 31, 0, // Skip to: 86948 +/* 78856 */ MCD_OPC_CheckField, 21, 1, 0, 149, 31, 0, // Skip to: 86948 +/* 78863 */ MCD_OPC_Decode, 247, 17, 255, 2, // Opcode: LDRQpre +/* 78868 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 78878 +/* 78873 */ MCD_OPC_Decode, 154, 29, 137, 3, // Opcode: STRBui +/* 78878 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 78888 +/* 78883 */ MCD_OPC_Decode, 228, 17, 137, 3, // Opcode: LDRBui +/* 78888 */ MCD_OPC_FilterValue, 6, 5, 0, 0, // Skip to: 78898 +/* 78893 */ MCD_OPC_Decode, 174, 29, 137, 3, // Opcode: STRQui +/* 78898 */ MCD_OPC_FilterValue, 7, 109, 31, 0, // Skip to: 86948 +/* 78903 */ MCD_OPC_Decode, 250, 17, 137, 3, // Opcode: LDRQui +/* 78908 */ MCD_OPC_FilterValue, 2, 63, 12, 0, // Skip to: 82048 +/* 78913 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 78916 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 78926 +/* 78921 */ MCD_OPC_Decode, 229, 17, 202, 3, // Opcode: LDRDl +/* 78926 */ MCD_OPC_FilterValue, 2, 254, 7, 0, // Skip to: 80977 +/* 78931 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 78934 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 78956 +/* 78939 */ MCD_OPC_CheckPredicate, 19, 68, 31, 0, // Skip to: 86948 +/* 78944 */ MCD_OPC_CheckField, 21, 3, 0, 61, 31, 0, // Skip to: 86948 +/* 78951 */ MCD_OPC_Decode, 241, 22, 203, 3, // Opcode: SHA1Crrr +/* 78956 */ MCD_OPC_FilterValue, 1, 114, 0, 0, // Skip to: 79075 +/* 78961 */ MCD_OPC_ExtractField, 16, 1, // Inst{16} ... +/* 78964 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 79053 +/* 78969 */ MCD_OPC_ExtractField, 17, 1, // Inst{17} ... +/* 78972 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 79031 +/* 78977 */ MCD_OPC_ExtractField, 18, 1, // Inst{18} ... +/* 78980 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 79009 +/* 78985 */ MCD_OPC_CheckPredicate, 3, 22, 31, 0, // Skip to: 86948 +/* 78990 */ MCD_OPC_CheckField, 21, 3, 0, 15, 31, 0, // Skip to: 86948 +/* 78997 */ MCD_OPC_CheckField, 19, 1, 1, 8, 31, 0, // Skip to: 86948 +/* 79004 */ MCD_OPC_Decode, 151, 5, 204, 3, // Opcode: CPYi64 +/* 79009 */ MCD_OPC_FilterValue, 1, 254, 30, 0, // Skip to: 86948 +/* 79014 */ MCD_OPC_CheckPredicate, 3, 249, 30, 0, // Skip to: 86948 +/* 79019 */ MCD_OPC_CheckField, 21, 3, 0, 242, 30, 0, // Skip to: 86948 +/* 79026 */ MCD_OPC_Decode, 150, 5, 205, 3, // Opcode: CPYi32 +/* 79031 */ MCD_OPC_FilterValue, 1, 232, 30, 0, // Skip to: 86948 +/* 79036 */ MCD_OPC_CheckPredicate, 3, 227, 30, 0, // Skip to: 86948 +/* 79041 */ MCD_OPC_CheckField, 21, 3, 0, 220, 30, 0, // Skip to: 86948 +/* 79048 */ MCD_OPC_Decode, 149, 5, 206, 3, // Opcode: CPYi16 +/* 79053 */ MCD_OPC_FilterValue, 1, 210, 30, 0, // Skip to: 86948 +/* 79058 */ MCD_OPC_CheckPredicate, 3, 205, 30, 0, // Skip to: 86948 +/* 79063 */ MCD_OPC_CheckField, 21, 3, 0, 198, 30, 0, // Skip to: 86948 +/* 79070 */ MCD_OPC_Decode, 152, 5, 207, 3, // Opcode: CPYi8 +/* 79075 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 79097 +/* 79080 */ MCD_OPC_CheckPredicate, 19, 183, 30, 0, // Skip to: 86948 +/* 79085 */ MCD_OPC_CheckField, 16, 8, 40, 176, 30, 0, // Skip to: 86948 +/* 79092 */ MCD_OPC_Decode, 242, 22, 167, 3, // Opcode: SHA1Hrr +/* 79097 */ MCD_OPC_FilterValue, 3, 63, 0, 0, // Skip to: 79165 +/* 79102 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 79105 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79120 +/* 79110 */ MCD_OPC_CheckPredicate, 3, 153, 30, 0, // Skip to: 86948 +/* 79115 */ MCD_OPC_Decode, 176, 24, 208, 3, // Opcode: SQADDv1i8 +/* 79120 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79135 +/* 79125 */ MCD_OPC_CheckPredicate, 3, 138, 30, 0, // Skip to: 86948 +/* 79130 */ MCD_OPC_Decode, 173, 24, 193, 3, // Opcode: SQADDv1i16 +/* 79135 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79150 +/* 79140 */ MCD_OPC_CheckPredicate, 3, 123, 30, 0, // Skip to: 86948 +/* 79145 */ MCD_OPC_Decode, 174, 24, 172, 3, // Opcode: SQADDv1i32 +/* 79150 */ MCD_OPC_FilterValue, 7, 113, 30, 0, // Skip to: 86948 +/* 79155 */ MCD_OPC_CheckPredicate, 3, 108, 30, 0, // Skip to: 86948 +/* 79160 */ MCD_OPC_Decode, 175, 24, 238, 1, // Opcode: SQADDv1i64 +/* 79165 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 79187 +/* 79170 */ MCD_OPC_CheckPredicate, 19, 93, 30, 0, // Skip to: 86948 +/* 79175 */ MCD_OPC_CheckField, 21, 3, 0, 86, 30, 0, // Skip to: 86948 +/* 79182 */ MCD_OPC_Decode, 244, 22, 203, 3, // Opcode: SHA1Prrr +/* 79187 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 79209 +/* 79192 */ MCD_OPC_CheckPredicate, 19, 71, 30, 0, // Skip to: 86948 +/* 79197 */ MCD_OPC_CheckField, 16, 8, 40, 64, 30, 0, // Skip to: 86948 +/* 79204 */ MCD_OPC_Decode, 246, 22, 147, 2, // Opcode: SHA1SU1rr +/* 79209 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 79231 +/* 79214 */ MCD_OPC_CheckPredicate, 4, 49, 30, 0, // Skip to: 86948 +/* 79219 */ MCD_OPC_CheckField, 21, 3, 2, 42, 30, 0, // Skip to: 86948 +/* 79226 */ MCD_OPC_Decode, 248, 10, 193, 3, // Opcode: FMULX16 +/* 79231 */ MCD_OPC_FilterValue, 8, 17, 0, 0, // Skip to: 79253 +/* 79236 */ MCD_OPC_CheckPredicate, 19, 27, 30, 0, // Skip to: 86948 +/* 79241 */ MCD_OPC_CheckField, 21, 3, 0, 20, 30, 0, // Skip to: 86948 +/* 79248 */ MCD_OPC_Decode, 243, 22, 203, 3, // Opcode: SHA1Mrrr +/* 79253 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 79275 +/* 79258 */ MCD_OPC_CheckPredicate, 4, 5, 30, 0, // Skip to: 86948 +/* 79263 */ MCD_OPC_CheckField, 21, 3, 2, 254, 29, 0, // Skip to: 86948 +/* 79270 */ MCD_OPC_Decode, 217, 6, 193, 3, // Opcode: FCMEQ16 +/* 79275 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 79297 +/* 79280 */ MCD_OPC_CheckPredicate, 19, 239, 29, 0, // Skip to: 86948 +/* 79285 */ MCD_OPC_CheckField, 16, 8, 40, 232, 29, 0, // Skip to: 86948 +/* 79292 */ MCD_OPC_Decode, 249, 22, 147, 2, // Opcode: SHA256SU0rr +/* 79297 */ MCD_OPC_FilterValue, 11, 63, 0, 0, // Skip to: 79365 +/* 79302 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 79305 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79320 +/* 79310 */ MCD_OPC_CheckPredicate, 3, 209, 29, 0, // Skip to: 86948 +/* 79315 */ MCD_OPC_Decode, 158, 26, 208, 3, // Opcode: SQSUBv1i8 +/* 79320 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79335 +/* 79325 */ MCD_OPC_CheckPredicate, 3, 194, 29, 0, // Skip to: 86948 +/* 79330 */ MCD_OPC_Decode, 155, 26, 193, 3, // Opcode: SQSUBv1i16 +/* 79335 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79350 +/* 79340 */ MCD_OPC_CheckPredicate, 3, 179, 29, 0, // Skip to: 86948 +/* 79345 */ MCD_OPC_Decode, 156, 26, 172, 3, // Opcode: SQSUBv1i32 +/* 79350 */ MCD_OPC_FilterValue, 7, 169, 29, 0, // Skip to: 86948 +/* 79355 */ MCD_OPC_CheckPredicate, 3, 164, 29, 0, // Skip to: 86948 +/* 79360 */ MCD_OPC_Decode, 157, 26, 238, 1, // Opcode: SQSUBv1i64 +/* 79365 */ MCD_OPC_FilterValue, 12, 17, 0, 0, // Skip to: 79387 +/* 79370 */ MCD_OPC_CheckPredicate, 19, 149, 29, 0, // Skip to: 86948 +/* 79375 */ MCD_OPC_CheckField, 21, 3, 0, 142, 29, 0, // Skip to: 86948 +/* 79382 */ MCD_OPC_Decode, 245, 22, 141, 2, // Opcode: SHA1SU0rrr +/* 79387 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 79409 +/* 79392 */ MCD_OPC_CheckPredicate, 3, 127, 29, 0, // Skip to: 86948 +/* 79397 */ MCD_OPC_CheckField, 21, 3, 7, 120, 29, 0, // Skip to: 86948 +/* 79404 */ MCD_OPC_Decode, 216, 3, 238, 1, // Opcode: CMGTv1i64 +/* 79409 */ MCD_OPC_FilterValue, 14, 65, 0, 0, // Skip to: 79479 +/* 79414 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 79417 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 79432 +/* 79422 */ MCD_OPC_CheckPredicate, 3, 97, 29, 0, // Skip to: 86948 +/* 79427 */ MCD_OPC_Decode, 145, 30, 209, 3, // Opcode: SUQADDv1i8 +/* 79432 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 79447 +/* 79437 */ MCD_OPC_CheckPredicate, 3, 82, 29, 0, // Skip to: 86948 +/* 79442 */ MCD_OPC_Decode, 142, 30, 210, 3, // Opcode: SUQADDv1i16 +/* 79447 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 79463 +/* 79453 */ MCD_OPC_CheckPredicate, 3, 66, 29, 0, // Skip to: 86948 +/* 79458 */ MCD_OPC_Decode, 143, 30, 211, 3, // Opcode: SUQADDv1i32 +/* 79463 */ MCD_OPC_FilterValue, 224, 1, 55, 29, 0, // Skip to: 86948 +/* 79469 */ MCD_OPC_CheckPredicate, 3, 50, 29, 0, // Skip to: 86948 +/* 79474 */ MCD_OPC_Decode, 144, 30, 248, 1, // Opcode: SUQADDv1i64 +/* 79479 */ MCD_OPC_FilterValue, 15, 48, 0, 0, // Skip to: 79532 +/* 79484 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 79487 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 79502 +/* 79492 */ MCD_OPC_CheckPredicate, 4, 27, 29, 0, // Skip to: 86948 +/* 79497 */ MCD_OPC_Decode, 207, 11, 193, 3, // Opcode: FRECPS16 +/* 79502 */ MCD_OPC_FilterValue, 6, 10, 0, 0, // Skip to: 79517 +/* 79507 */ MCD_OPC_CheckPredicate, 4, 12, 29, 0, // Skip to: 86948 +/* 79512 */ MCD_OPC_Decode, 184, 12, 193, 3, // Opcode: FRSQRTS16 +/* 79517 */ MCD_OPC_FilterValue, 7, 2, 29, 0, // Skip to: 86948 +/* 79522 */ MCD_OPC_CheckPredicate, 3, 253, 28, 0, // Skip to: 86948 +/* 79527 */ MCD_OPC_Decode, 200, 3, 238, 1, // Opcode: CMGEv1i64 +/* 79532 */ MCD_OPC_FilterValue, 16, 17, 0, 0, // Skip to: 79554 +/* 79537 */ MCD_OPC_CheckPredicate, 19, 238, 28, 0, // Skip to: 86948 +/* 79542 */ MCD_OPC_CheckField, 21, 3, 0, 231, 28, 0, // Skip to: 86948 +/* 79549 */ MCD_OPC_Decode, 248, 22, 141, 2, // Opcode: SHA256Hrrr +/* 79554 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 79576 +/* 79559 */ MCD_OPC_CheckPredicate, 3, 216, 28, 0, // Skip to: 86948 +/* 79564 */ MCD_OPC_CheckField, 21, 3, 7, 209, 28, 0, // Skip to: 86948 +/* 79571 */ MCD_OPC_Decode, 228, 26, 238, 1, // Opcode: SSHLv1i64 +/* 79576 */ MCD_OPC_FilterValue, 18, 49, 0, 0, // Skip to: 79630 +/* 79581 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 79584 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 79599 +/* 79589 */ MCD_OPC_CheckPredicate, 3, 186, 28, 0, // Skip to: 86948 +/* 79594 */ MCD_OPC_Decode, 168, 26, 212, 3, // Opcode: SQXTNv1i8 +/* 79599 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 79614 +/* 79604 */ MCD_OPC_CheckPredicate, 3, 171, 28, 0, // Skip to: 86948 +/* 79609 */ MCD_OPC_Decode, 166, 26, 169, 3, // Opcode: SQXTNv1i16 +/* 79614 */ MCD_OPC_FilterValue, 161, 1, 160, 28, 0, // Skip to: 86948 +/* 79620 */ MCD_OPC_CheckPredicate, 3, 155, 28, 0, // Skip to: 86948 +/* 79625 */ MCD_OPC_Decode, 167, 26, 166, 2, // Opcode: SQXTNv1i32 +/* 79630 */ MCD_OPC_FilterValue, 19, 63, 0, 0, // Skip to: 79698 +/* 79635 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 79638 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79653 +/* 79643 */ MCD_OPC_CheckPredicate, 3, 132, 28, 0, // Skip to: 86948 +/* 79648 */ MCD_OPC_Decode, 243, 25, 208, 3, // Opcode: SQSHLv1i8 +/* 79653 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79668 +/* 79658 */ MCD_OPC_CheckPredicate, 3, 117, 28, 0, // Skip to: 86948 +/* 79663 */ MCD_OPC_Decode, 240, 25, 193, 3, // Opcode: SQSHLv1i16 +/* 79668 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79683 +/* 79673 */ MCD_OPC_CheckPredicate, 3, 102, 28, 0, // Skip to: 86948 +/* 79678 */ MCD_OPC_Decode, 241, 25, 172, 3, // Opcode: SQSHLv1i32 +/* 79683 */ MCD_OPC_FilterValue, 7, 92, 28, 0, // Skip to: 86948 +/* 79688 */ MCD_OPC_CheckPredicate, 3, 87, 28, 0, // Skip to: 86948 +/* 79693 */ MCD_OPC_Decode, 242, 25, 238, 1, // Opcode: SQSHLv1i64 +/* 79698 */ MCD_OPC_FilterValue, 20, 17, 0, 0, // Skip to: 79720 +/* 79703 */ MCD_OPC_CheckPredicate, 19, 72, 28, 0, // Skip to: 86948 +/* 79708 */ MCD_OPC_CheckField, 21, 3, 0, 65, 28, 0, // Skip to: 86948 +/* 79715 */ MCD_OPC_Decode, 247, 22, 141, 2, // Opcode: SHA256H2rrr +/* 79720 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 79742 +/* 79725 */ MCD_OPC_CheckPredicate, 3, 50, 28, 0, // Skip to: 86948 +/* 79730 */ MCD_OPC_CheckField, 21, 3, 7, 43, 28, 0, // Skip to: 86948 +/* 79737 */ MCD_OPC_Decode, 198, 26, 238, 1, // Opcode: SRSHLv1i64 +/* 79742 */ MCD_OPC_FilterValue, 23, 63, 0, 0, // Skip to: 79810 +/* 79747 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 79750 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 79765 +/* 79755 */ MCD_OPC_CheckPredicate, 3, 20, 28, 0, // Skip to: 86948 +/* 79760 */ MCD_OPC_Decode, 198, 25, 208, 3, // Opcode: SQRSHLv1i8 +/* 79765 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79780 +/* 79770 */ MCD_OPC_CheckPredicate, 3, 5, 28, 0, // Skip to: 86948 +/* 79775 */ MCD_OPC_Decode, 195, 25, 193, 3, // Opcode: SQRSHLv1i16 +/* 79780 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 79795 +/* 79785 */ MCD_OPC_CheckPredicate, 3, 246, 27, 0, // Skip to: 86948 +/* 79790 */ MCD_OPC_Decode, 196, 25, 172, 3, // Opcode: SQRSHLv1i32 +/* 79795 */ MCD_OPC_FilterValue, 7, 236, 27, 0, // Skip to: 86948 +/* 79800 */ MCD_OPC_CheckPredicate, 3, 231, 27, 0, // Skip to: 86948 +/* 79805 */ MCD_OPC_Decode, 197, 25, 238, 1, // Opcode: SQRSHLv1i64 +/* 79810 */ MCD_OPC_FilterValue, 24, 17, 0, 0, // Skip to: 79832 +/* 79815 */ MCD_OPC_CheckPredicate, 19, 216, 27, 0, // Skip to: 86948 +/* 79820 */ MCD_OPC_CheckField, 21, 3, 0, 209, 27, 0, // Skip to: 86948 +/* 79827 */ MCD_OPC_Decode, 250, 22, 141, 2, // Opcode: SHA256SU1rrr +/* 79832 */ MCD_OPC_FilterValue, 30, 65, 0, 0, // Skip to: 79902 +/* 79837 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 79840 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 79855 +/* 79845 */ MCD_OPC_CheckPredicate, 3, 186, 27, 0, // Skip to: 86948 +/* 79850 */ MCD_OPC_Decode, 157, 24, 213, 3, // Opcode: SQABSv1i8 +/* 79855 */ MCD_OPC_FilterValue, 96, 10, 0, 0, // Skip to: 79870 +/* 79860 */ MCD_OPC_CheckPredicate, 3, 171, 27, 0, // Skip to: 86948 +/* 79865 */ MCD_OPC_Decode, 154, 24, 188, 3, // Opcode: SQABSv1i16 +/* 79870 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 79886 +/* 79876 */ MCD_OPC_CheckPredicate, 3, 155, 27, 0, // Skip to: 86948 +/* 79881 */ MCD_OPC_Decode, 155, 24, 167, 3, // Opcode: SQABSv1i32 +/* 79886 */ MCD_OPC_FilterValue, 224, 1, 144, 27, 0, // Skip to: 86948 +/* 79892 */ MCD_OPC_CheckPredicate, 3, 139, 27, 0, // Skip to: 86948 +/* 79897 */ MCD_OPC_Decode, 156, 24, 239, 1, // Opcode: SQABSv1i64 +/* 79902 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 79924 +/* 79907 */ MCD_OPC_CheckPredicate, 3, 124, 27, 0, // Skip to: 86948 +/* 79912 */ MCD_OPC_CheckField, 21, 3, 7, 117, 27, 0, // Skip to: 86948 +/* 79919 */ MCD_OPC_Decode, 195, 1, 238, 1, // Opcode: ADDv1i64 +/* 79924 */ MCD_OPC_FilterValue, 34, 18, 0, 0, // Skip to: 79947 +/* 79929 */ MCD_OPC_CheckPredicate, 3, 102, 27, 0, // Skip to: 86948 +/* 79934 */ MCD_OPC_CheckField, 16, 8, 224, 1, 94, 27, 0, // Skip to: 86948 +/* 79942 */ MCD_OPC_Decode, 217, 3, 239, 1, // Opcode: CMGTv1i64rz +/* 79947 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 79969 +/* 79952 */ MCD_OPC_CheckPredicate, 3, 79, 27, 0, // Skip to: 86948 +/* 79957 */ MCD_OPC_CheckField, 21, 3, 7, 72, 27, 0, // Skip to: 86948 +/* 79964 */ MCD_OPC_Decode, 234, 4, 238, 1, // Opcode: CMTSTv1i64 +/* 79969 */ MCD_OPC_FilterValue, 36, 33, 0, 0, // Skip to: 80007 +/* 79974 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 79977 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 79992 +/* 79982 */ MCD_OPC_CheckPredicate, 3, 49, 27, 0, // Skip to: 86948 +/* 79987 */ MCD_OPC_Decode, 205, 24, 214, 3, // Opcode: SQDMLALi16 +/* 79992 */ MCD_OPC_FilterValue, 5, 39, 27, 0, // Skip to: 86948 +/* 79997 */ MCD_OPC_CheckPredicate, 3, 34, 27, 0, // Skip to: 86948 +/* 80002 */ MCD_OPC_Decode, 206, 24, 215, 3, // Opcode: SQDMLALi32 +/* 80007 */ MCD_OPC_FilterValue, 38, 18, 0, 0, // Skip to: 80030 +/* 80012 */ MCD_OPC_CheckPredicate, 3, 19, 27, 0, // Skip to: 86948 +/* 80017 */ MCD_OPC_CheckField, 16, 8, 224, 1, 11, 27, 0, // Skip to: 86948 +/* 80025 */ MCD_OPC_Decode, 185, 3, 239, 1, // Opcode: CMEQv1i64rz +/* 80030 */ MCD_OPC_FilterValue, 42, 112, 0, 0, // Skip to: 80147 +/* 80035 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 80038 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80053 +/* 80043 */ MCD_OPC_CheckPredicate, 3, 244, 26, 0, // Skip to: 86948 +/* 80048 */ MCD_OPC_Decode, 160, 8, 167, 3, // Opcode: FCVTNSv1i32 +/* 80053 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80068 +/* 80058 */ MCD_OPC_CheckPredicate, 3, 229, 26, 0, // Skip to: 86948 +/* 80063 */ MCD_OPC_Decode, 161, 8, 239, 1, // Opcode: FCVTNSv1i64 +/* 80068 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80083 +/* 80073 */ MCD_OPC_CheckPredicate, 4, 214, 26, 0, // Skip to: 86948 +/* 80078 */ MCD_OPC_Decode, 159, 8, 188, 3, // Opcode: FCVTNSv1f16 +/* 80083 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80099 +/* 80089 */ MCD_OPC_CheckPredicate, 3, 198, 26, 0, // Skip to: 86948 +/* 80094 */ MCD_OPC_Decode, 192, 8, 167, 3, // Opcode: FCVTPSv1i32 +/* 80099 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80115 +/* 80105 */ MCD_OPC_CheckPredicate, 3, 182, 26, 0, // Skip to: 86948 +/* 80110 */ MCD_OPC_Decode, 255, 3, 239, 1, // Opcode: CMLTv1i64rz +/* 80115 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80131 +/* 80121 */ MCD_OPC_CheckPredicate, 3, 166, 26, 0, // Skip to: 86948 +/* 80126 */ MCD_OPC_Decode, 193, 8, 239, 1, // Opcode: FCVTPSv1i64 +/* 80131 */ MCD_OPC_FilterValue, 249, 1, 155, 26, 0, // Skip to: 86948 +/* 80137 */ MCD_OPC_CheckPredicate, 4, 150, 26, 0, // Skip to: 86948 +/* 80142 */ MCD_OPC_Decode, 191, 8, 188, 3, // Opcode: FCVTPSv1f16 +/* 80147 */ MCD_OPC_FilterValue, 44, 33, 0, 0, // Skip to: 80185 +/* 80152 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 80155 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80170 +/* 80160 */ MCD_OPC_CheckPredicate, 3, 127, 26, 0, // Skip to: 86948 +/* 80165 */ MCD_OPC_Decode, 217, 24, 214, 3, // Opcode: SQDMLSLi16 +/* 80170 */ MCD_OPC_FilterValue, 5, 117, 26, 0, // Skip to: 86948 +/* 80175 */ MCD_OPC_CheckPredicate, 3, 112, 26, 0, // Skip to: 86948 +/* 80180 */ MCD_OPC_Decode, 218, 24, 215, 3, // Opcode: SQDMLSLi32 +/* 80185 */ MCD_OPC_FilterValue, 45, 33, 0, 0, // Skip to: 80223 +/* 80190 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 80193 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80208 +/* 80198 */ MCD_OPC_CheckPredicate, 3, 89, 26, 0, // Skip to: 86948 +/* 80203 */ MCD_OPC_Decode, 229, 24, 193, 3, // Opcode: SQDMULHv1i16 +/* 80208 */ MCD_OPC_FilterValue, 5, 79, 26, 0, // Skip to: 86948 +/* 80213 */ MCD_OPC_CheckPredicate, 3, 74, 26, 0, // Skip to: 86948 +/* 80218 */ MCD_OPC_Decode, 231, 24, 172, 3, // Opcode: SQDMULHv1i32 +/* 80223 */ MCD_OPC_FilterValue, 46, 128, 0, 0, // Skip to: 80356 +/* 80228 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 80231 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80246 +/* 80236 */ MCD_OPC_CheckPredicate, 3, 51, 26, 0, // Skip to: 86948 +/* 80241 */ MCD_OPC_Decode, 132, 8, 167, 3, // Opcode: FCVTMSv1i32 +/* 80246 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80261 +/* 80251 */ MCD_OPC_CheckPredicate, 3, 36, 26, 0, // Skip to: 86948 +/* 80256 */ MCD_OPC_Decode, 133, 8, 239, 1, // Opcode: FCVTMSv1i64 +/* 80261 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80276 +/* 80266 */ MCD_OPC_CheckPredicate, 4, 21, 26, 0, // Skip to: 86948 +/* 80271 */ MCD_OPC_Decode, 131, 8, 188, 3, // Opcode: FCVTMSv1f16 +/* 80276 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80292 +/* 80282 */ MCD_OPC_CheckPredicate, 3, 5, 26, 0, // Skip to: 86948 +/* 80287 */ MCD_OPC_Decode, 241, 8, 167, 3, // Opcode: FCVTZSv1i32 +/* 80292 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80308 +/* 80298 */ MCD_OPC_CheckPredicate, 3, 245, 25, 0, // Skip to: 86948 +/* 80303 */ MCD_OPC_Decode, 131, 1, 239, 1, // Opcode: ABSv1i64 +/* 80308 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80324 +/* 80314 */ MCD_OPC_CheckPredicate, 3, 229, 25, 0, // Skip to: 86948 +/* 80319 */ MCD_OPC_Decode, 242, 8, 239, 1, // Opcode: FCVTZSv1i64 +/* 80324 */ MCD_OPC_FilterValue, 241, 1, 10, 0, 0, // Skip to: 80340 +/* 80330 */ MCD_OPC_CheckPredicate, 3, 213, 25, 0, // Skip to: 86948 +/* 80335 */ MCD_OPC_Decode, 152, 1, 244, 1, // Opcode: ADDPv2i64p +/* 80340 */ MCD_OPC_FilterValue, 249, 1, 202, 25, 0, // Skip to: 86948 +/* 80346 */ MCD_OPC_CheckPredicate, 4, 197, 25, 0, // Skip to: 86948 +/* 80351 */ MCD_OPC_Decode, 240, 8, 188, 3, // Opcode: FCVTZSv1f16 +/* 80356 */ MCD_OPC_FilterValue, 50, 127, 0, 0, // Skip to: 80488 +/* 80361 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 80364 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80379 +/* 80369 */ MCD_OPC_CheckPredicate, 3, 174, 25, 0, // Skip to: 86948 +/* 80374 */ MCD_OPC_Decode, 224, 7, 167, 3, // Opcode: FCVTASv1i32 +/* 80379 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80394 +/* 80384 */ MCD_OPC_CheckPredicate, 4, 159, 25, 0, // Skip to: 86948 +/* 80389 */ MCD_OPC_Decode, 199, 9, 249, 1, // Opcode: FMAXNMPv2i16p +/* 80394 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80409 +/* 80399 */ MCD_OPC_CheckPredicate, 3, 144, 25, 0, // Skip to: 86948 +/* 80404 */ MCD_OPC_Decode, 225, 7, 239, 1, // Opcode: FCVTASv1i64 +/* 80409 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80424 +/* 80414 */ MCD_OPC_CheckPredicate, 4, 129, 25, 0, // Skip to: 86948 +/* 80419 */ MCD_OPC_Decode, 223, 7, 188, 3, // Opcode: FCVTASv1f16 +/* 80424 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80440 +/* 80430 */ MCD_OPC_CheckPredicate, 3, 113, 25, 0, // Skip to: 86948 +/* 80435 */ MCD_OPC_Decode, 143, 7, 167, 3, // Opcode: FCMGTv1i32rz +/* 80440 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 80456 +/* 80446 */ MCD_OPC_CheckPredicate, 4, 97, 25, 0, // Skip to: 86948 +/* 80451 */ MCD_OPC_Decode, 255, 9, 249, 1, // Opcode: FMINNMPv2i16p +/* 80456 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80472 +/* 80462 */ MCD_OPC_CheckPredicate, 3, 81, 25, 0, // Skip to: 86948 +/* 80467 */ MCD_OPC_Decode, 144, 7, 239, 1, // Opcode: FCMGTv1i64rz +/* 80472 */ MCD_OPC_FilterValue, 248, 1, 70, 25, 0, // Skip to: 86948 +/* 80478 */ MCD_OPC_CheckPredicate, 4, 65, 25, 0, // Skip to: 86948 +/* 80483 */ MCD_OPC_Decode, 142, 7, 188, 3, // Opcode: FCMGTv1i16rz +/* 80488 */ MCD_OPC_FilterValue, 52, 33, 0, 0, // Skip to: 80526 +/* 80493 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 80496 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80511 +/* 80501 */ MCD_OPC_CheckPredicate, 3, 42, 25, 0, // Skip to: 86948 +/* 80506 */ MCD_OPC_Decode, 241, 24, 216, 3, // Opcode: SQDMULLi16 +/* 80511 */ MCD_OPC_FilterValue, 5, 32, 25, 0, // Skip to: 86948 +/* 80516 */ MCD_OPC_CheckPredicate, 3, 27, 25, 0, // Skip to: 86948 +/* 80521 */ MCD_OPC_Decode, 242, 24, 217, 3, // Opcode: SQDMULLi32 +/* 80526 */ MCD_OPC_FilterValue, 54, 159, 0, 0, // Skip to: 80690 +/* 80531 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 80534 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 80549 +/* 80539 */ MCD_OPC_CheckPredicate, 3, 4, 25, 0, // Skip to: 86948 +/* 80544 */ MCD_OPC_Decode, 207, 22, 167, 3, // Opcode: SCVTFv1i32 +/* 80549 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80564 +/* 80554 */ MCD_OPC_CheckPredicate, 4, 245, 24, 0, // Skip to: 86948 +/* 80559 */ MCD_OPC_Decode, 179, 6, 249, 1, // Opcode: FADDPv2i16p +/* 80564 */ MCD_OPC_FilterValue, 97, 10, 0, 0, // Skip to: 80579 +/* 80569 */ MCD_OPC_CheckPredicate, 3, 230, 24, 0, // Skip to: 86948 +/* 80574 */ MCD_OPC_Decode, 208, 22, 239, 1, // Opcode: SCVTFv1i64 +/* 80579 */ MCD_OPC_FilterValue, 121, 10, 0, 0, // Skip to: 80594 +/* 80584 */ MCD_OPC_CheckPredicate, 4, 215, 24, 0, // Skip to: 86948 +/* 80589 */ MCD_OPC_Decode, 206, 22, 188, 3, // Opcode: SCVTFv1i16 +/* 80594 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80610 +/* 80600 */ MCD_OPC_CheckPredicate, 3, 199, 24, 0, // Skip to: 86948 +/* 80605 */ MCD_OPC_Decode, 227, 6, 167, 3, // Opcode: FCMEQv1i32rz +/* 80610 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80626 +/* 80616 */ MCD_OPC_CheckPredicate, 3, 183, 24, 0, // Skip to: 86948 +/* 80621 */ MCD_OPC_Decode, 200, 11, 167, 3, // Opcode: FRECPEv1i32 +/* 80626 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80642 +/* 80632 */ MCD_OPC_CheckPredicate, 3, 167, 24, 0, // Skip to: 86948 +/* 80637 */ MCD_OPC_Decode, 228, 6, 239, 1, // Opcode: FCMEQv1i64rz +/* 80642 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80658 +/* 80648 */ MCD_OPC_CheckPredicate, 3, 151, 24, 0, // Skip to: 86948 +/* 80653 */ MCD_OPC_Decode, 201, 11, 239, 1, // Opcode: FRECPEv1i64 +/* 80658 */ MCD_OPC_FilterValue, 248, 1, 10, 0, 0, // Skip to: 80674 +/* 80664 */ MCD_OPC_CheckPredicate, 4, 135, 24, 0, // Skip to: 86948 +/* 80669 */ MCD_OPC_Decode, 226, 6, 188, 3, // Opcode: FCMEQv1i16rz +/* 80674 */ MCD_OPC_FilterValue, 249, 1, 124, 24, 0, // Skip to: 86948 +/* 80680 */ MCD_OPC_CheckPredicate, 4, 119, 24, 0, // Skip to: 86948 +/* 80685 */ MCD_OPC_Decode, 199, 11, 188, 3, // Opcode: FRECPEv1f16 +/* 80690 */ MCD_OPC_FilterValue, 55, 33, 0, 0, // Skip to: 80728 +/* 80695 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 80698 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80713 +/* 80703 */ MCD_OPC_CheckPredicate, 3, 96, 24, 0, // Skip to: 86948 +/* 80708 */ MCD_OPC_Decode, 249, 10, 172, 3, // Opcode: FMULX32 +/* 80713 */ MCD_OPC_FilterValue, 3, 86, 24, 0, // Skip to: 86948 +/* 80718 */ MCD_OPC_CheckPredicate, 3, 81, 24, 0, // Skip to: 86948 +/* 80723 */ MCD_OPC_Decode, 250, 10, 238, 1, // Opcode: FMULX64 +/* 80728 */ MCD_OPC_FilterValue, 57, 33, 0, 0, // Skip to: 80766 +/* 80733 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 80736 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80751 +/* 80741 */ MCD_OPC_CheckPredicate, 3, 58, 24, 0, // Skip to: 86948 +/* 80746 */ MCD_OPC_Decode, 218, 6, 172, 3, // Opcode: FCMEQ32 +/* 80751 */ MCD_OPC_FilterValue, 3, 48, 24, 0, // Skip to: 86948 +/* 80756 */ MCD_OPC_CheckPredicate, 3, 43, 24, 0, // Skip to: 86948 +/* 80761 */ MCD_OPC_Decode, 219, 6, 238, 1, // Opcode: FCMEQ64 +/* 80766 */ MCD_OPC_FilterValue, 58, 51, 0, 0, // Skip to: 80822 +/* 80771 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 80774 */ MCD_OPC_FilterValue, 160, 1, 10, 0, 0, // Skip to: 80790 +/* 80780 */ MCD_OPC_CheckPredicate, 3, 19, 24, 0, // Skip to: 86948 +/* 80785 */ MCD_OPC_Decode, 183, 7, 167, 3, // Opcode: FCMLTv1i32rz +/* 80790 */ MCD_OPC_FilterValue, 224, 1, 10, 0, 0, // Skip to: 80806 +/* 80796 */ MCD_OPC_CheckPredicate, 3, 3, 24, 0, // Skip to: 86948 +/* 80801 */ MCD_OPC_Decode, 184, 7, 239, 1, // Opcode: FCMLTv1i64rz +/* 80806 */ MCD_OPC_FilterValue, 248, 1, 248, 23, 0, // Skip to: 86948 +/* 80812 */ MCD_OPC_CheckPredicate, 4, 243, 23, 0, // Skip to: 86948 +/* 80817 */ MCD_OPC_Decode, 182, 7, 188, 3, // Opcode: FCMLTv1i16rz +/* 80822 */ MCD_OPC_FilterValue, 62, 82, 0, 0, // Skip to: 80909 +/* 80827 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 80830 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 80845 +/* 80835 */ MCD_OPC_CheckPredicate, 4, 220, 23, 0, // Skip to: 86948 +/* 80840 */ MCD_OPC_Decode, 225, 9, 249, 1, // Opcode: FMAXPv2i16p +/* 80845 */ MCD_OPC_FilterValue, 161, 1, 10, 0, 0, // Skip to: 80861 +/* 80851 */ MCD_OPC_CheckPredicate, 3, 204, 23, 0, // Skip to: 86948 +/* 80856 */ MCD_OPC_Decode, 222, 11, 167, 3, // Opcode: FRECPXv1i32 +/* 80861 */ MCD_OPC_FilterValue, 176, 1, 10, 0, 0, // Skip to: 80877 +/* 80867 */ MCD_OPC_CheckPredicate, 4, 188, 23, 0, // Skip to: 86948 +/* 80872 */ MCD_OPC_Decode, 153, 10, 249, 1, // Opcode: FMINPv2i16p +/* 80877 */ MCD_OPC_FilterValue, 225, 1, 10, 0, 0, // Skip to: 80893 +/* 80883 */ MCD_OPC_CheckPredicate, 3, 172, 23, 0, // Skip to: 86948 +/* 80888 */ MCD_OPC_Decode, 223, 11, 239, 1, // Opcode: FRECPXv1i64 +/* 80893 */ MCD_OPC_FilterValue, 249, 1, 161, 23, 0, // Skip to: 86948 +/* 80899 */ MCD_OPC_CheckPredicate, 4, 156, 23, 0, // Skip to: 86948 +/* 80904 */ MCD_OPC_Decode, 221, 11, 188, 3, // Opcode: FRECPXv1f16 +/* 80909 */ MCD_OPC_FilterValue, 63, 146, 23, 0, // Skip to: 86948 +/* 80914 */ MCD_OPC_ExtractField, 21, 3, // Inst{23-21} ... +/* 80917 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 80932 +/* 80922 */ MCD_OPC_CheckPredicate, 3, 133, 23, 0, // Skip to: 86948 +/* 80927 */ MCD_OPC_Decode, 208, 11, 172, 3, // Opcode: FRECPS32 +/* 80932 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 80947 +/* 80937 */ MCD_OPC_CheckPredicate, 3, 118, 23, 0, // Skip to: 86948 +/* 80942 */ MCD_OPC_Decode, 209, 11, 238, 1, // Opcode: FRECPS64 +/* 80947 */ MCD_OPC_FilterValue, 5, 10, 0, 0, // Skip to: 80962 +/* 80952 */ MCD_OPC_CheckPredicate, 3, 103, 23, 0, // Skip to: 86948 +/* 80957 */ MCD_OPC_Decode, 185, 12, 172, 3, // Opcode: FRSQRTS32 +/* 80962 */ MCD_OPC_FilterValue, 7, 93, 23, 0, // Skip to: 86948 +/* 80967 */ MCD_OPC_CheckPredicate, 3, 88, 23, 0, // Skip to: 86948 +/* 80972 */ MCD_OPC_Decode, 186, 12, 238, 1, // Opcode: FRSQRTS64 +/* 80977 */ MCD_OPC_FilterValue, 3, 78, 23, 0, // Skip to: 86948 +/* 80982 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 80985 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81014 +/* 80990 */ MCD_OPC_CheckPredicate, 3, 65, 23, 0, // Skip to: 86948 +/* 80995 */ MCD_OPC_CheckField, 22, 2, 1, 58, 23, 0, // Skip to: 86948 +/* 81002 */ MCD_OPC_CheckField, 10, 2, 1, 51, 23, 0, // Skip to: 86948 +/* 81009 */ MCD_OPC_Decode, 235, 26, 218, 3, // Opcode: SSHRd +/* 81014 */ MCD_OPC_FilterValue, 1, 98, 0, 0, // Skip to: 81117 +/* 81019 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81022 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81044 +/* 81027 */ MCD_OPC_CheckPredicate, 4, 28, 23, 0, // Skip to: 86948 +/* 81032 */ MCD_OPC_CheckField, 10, 1, 0, 21, 23, 0, // Skip to: 86948 +/* 81039 */ MCD_OPC_Decode, 183, 10, 219, 3, // Opcode: FMLAv1i16_indexed +/* 81044 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81066 +/* 81049 */ MCD_OPC_CheckPredicate, 3, 6, 23, 0, // Skip to: 86948 +/* 81054 */ MCD_OPC_CheckField, 10, 2, 1, 255, 22, 0, // Skip to: 86948 +/* 81061 */ MCD_OPC_Decode, 243, 26, 220, 3, // Opcode: SSRAd +/* 81066 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81088 +/* 81071 */ MCD_OPC_CheckPredicate, 3, 240, 22, 0, // Skip to: 86948 +/* 81076 */ MCD_OPC_CheckField, 10, 1, 0, 233, 22, 0, // Skip to: 86948 +/* 81083 */ MCD_OPC_Decode, 184, 10, 221, 3, // Opcode: FMLAv1i32_indexed +/* 81088 */ MCD_OPC_FilterValue, 3, 223, 22, 0, // Skip to: 86948 +/* 81093 */ MCD_OPC_CheckPredicate, 3, 218, 22, 0, // Skip to: 86948 +/* 81098 */ MCD_OPC_CheckField, 21, 1, 0, 211, 22, 0, // Skip to: 86948 +/* 81105 */ MCD_OPC_CheckField, 10, 1, 0, 204, 22, 0, // Skip to: 86948 +/* 81112 */ MCD_OPC_Decode, 185, 10, 222, 3, // Opcode: FMLAv1i64_indexed +/* 81117 */ MCD_OPC_FilterValue, 2, 24, 0, 0, // Skip to: 81146 +/* 81122 */ MCD_OPC_CheckPredicate, 3, 189, 22, 0, // Skip to: 86948 +/* 81127 */ MCD_OPC_CheckField, 22, 2, 1, 182, 22, 0, // Skip to: 86948 +/* 81134 */ MCD_OPC_CheckField, 10, 2, 1, 175, 22, 0, // Skip to: 86948 +/* 81141 */ MCD_OPC_Decode, 205, 26, 218, 3, // Opcode: SRSHRd +/* 81146 */ MCD_OPC_FilterValue, 3, 70, 0, 0, // Skip to: 81221 +/* 81151 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 81154 */ MCD_OPC_FilterValue, 0, 33, 0, 0, // Skip to: 81192 +/* 81159 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81162 */ MCD_OPC_FilterValue, 1, 10, 0, 0, // Skip to: 81177 +/* 81167 */ MCD_OPC_CheckPredicate, 3, 144, 22, 0, // Skip to: 86948 +/* 81172 */ MCD_OPC_Decode, 207, 24, 223, 3, // Opcode: SQDMLALv1i32_indexed +/* 81177 */ MCD_OPC_FilterValue, 2, 134, 22, 0, // Skip to: 86948 +/* 81182 */ MCD_OPC_CheckPredicate, 3, 129, 22, 0, // Skip to: 86948 +/* 81187 */ MCD_OPC_Decode, 208, 24, 224, 3, // Opcode: SQDMLALv1i64_indexed +/* 81192 */ MCD_OPC_FilterValue, 1, 119, 22, 0, // Skip to: 86948 +/* 81197 */ MCD_OPC_CheckPredicate, 3, 114, 22, 0, // Skip to: 86948 +/* 81202 */ MCD_OPC_CheckField, 22, 2, 1, 107, 22, 0, // Skip to: 86948 +/* 81209 */ MCD_OPC_CheckField, 11, 1, 0, 100, 22, 0, // Skip to: 86948 +/* 81216 */ MCD_OPC_Decode, 213, 26, 220, 3, // Opcode: SRSRAd +/* 81221 */ MCD_OPC_FilterValue, 5, 98, 0, 0, // Skip to: 81324 +/* 81226 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81229 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81251 +/* 81234 */ MCD_OPC_CheckPredicate, 4, 77, 22, 0, // Skip to: 86948 +/* 81239 */ MCD_OPC_CheckField, 10, 1, 0, 70, 22, 0, // Skip to: 86948 +/* 81246 */ MCD_OPC_Decode, 202, 10, 219, 3, // Opcode: FMLSv1i16_indexed +/* 81251 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81273 +/* 81256 */ MCD_OPC_CheckPredicate, 3, 55, 22, 0, // Skip to: 86948 +/* 81261 */ MCD_OPC_CheckField, 10, 2, 1, 48, 22, 0, // Skip to: 86948 +/* 81268 */ MCD_OPC_Decode, 139, 23, 225, 3, // Opcode: SHLd +/* 81273 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81295 +/* 81278 */ MCD_OPC_CheckPredicate, 3, 33, 22, 0, // Skip to: 86948 +/* 81283 */ MCD_OPC_CheckField, 10, 1, 0, 26, 22, 0, // Skip to: 86948 +/* 81290 */ MCD_OPC_Decode, 203, 10, 221, 3, // Opcode: FMLSv1i32_indexed +/* 81295 */ MCD_OPC_FilterValue, 3, 16, 22, 0, // Skip to: 86948 +/* 81300 */ MCD_OPC_CheckPredicate, 3, 11, 22, 0, // Skip to: 86948 +/* 81305 */ MCD_OPC_CheckField, 21, 1, 0, 4, 22, 0, // Skip to: 86948 +/* 81312 */ MCD_OPC_CheckField, 10, 1, 0, 253, 21, 0, // Skip to: 86948 +/* 81319 */ MCD_OPC_Decode, 204, 10, 222, 3, // Opcode: FMLSv1i64_indexed +/* 81324 */ MCD_OPC_FilterValue, 7, 159, 0, 0, // Skip to: 81488 +/* 81329 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81332 */ MCD_OPC_FilterValue, 0, 84, 0, 0, // Skip to: 81421 +/* 81337 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 81340 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 81399 +/* 81345 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 81348 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81377 +/* 81353 */ MCD_OPC_CheckPredicate, 3, 214, 21, 0, // Skip to: 86948 +/* 81358 */ MCD_OPC_CheckField, 19, 1, 1, 207, 21, 0, // Skip to: 86948 +/* 81365 */ MCD_OPC_CheckField, 10, 2, 1, 200, 21, 0, // Skip to: 86948 +/* 81372 */ MCD_OPC_Decode, 234, 25, 226, 3, // Opcode: SQSHLb +/* 81377 */ MCD_OPC_FilterValue, 1, 190, 21, 0, // Skip to: 86948 +/* 81382 */ MCD_OPC_CheckPredicate, 3, 185, 21, 0, // Skip to: 86948 +/* 81387 */ MCD_OPC_CheckField, 10, 2, 1, 178, 21, 0, // Skip to: 86948 +/* 81394 */ MCD_OPC_Decode, 236, 25, 227, 3, // Opcode: SQSHLh +/* 81399 */ MCD_OPC_FilterValue, 1, 168, 21, 0, // Skip to: 86948 +/* 81404 */ MCD_OPC_CheckPredicate, 3, 163, 21, 0, // Skip to: 86948 +/* 81409 */ MCD_OPC_CheckField, 10, 2, 1, 156, 21, 0, // Skip to: 86948 +/* 81416 */ MCD_OPC_Decode, 237, 25, 228, 3, // Opcode: SQSHLs +/* 81421 */ MCD_OPC_FilterValue, 1, 40, 0, 0, // Skip to: 81466 +/* 81426 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 81429 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 81444 +/* 81434 */ MCD_OPC_CheckPredicate, 3, 133, 21, 0, // Skip to: 86948 +/* 81439 */ MCD_OPC_Decode, 219, 24, 223, 3, // Opcode: SQDMLSLv1i32_indexed +/* 81444 */ MCD_OPC_FilterValue, 1, 123, 21, 0, // Skip to: 86948 +/* 81449 */ MCD_OPC_CheckPredicate, 3, 118, 21, 0, // Skip to: 86948 +/* 81454 */ MCD_OPC_CheckField, 11, 1, 0, 111, 21, 0, // Skip to: 86948 +/* 81461 */ MCD_OPC_Decode, 235, 25, 225, 3, // Opcode: SQSHLd +/* 81466 */ MCD_OPC_FilterValue, 2, 101, 21, 0, // Skip to: 86948 +/* 81471 */ MCD_OPC_CheckPredicate, 3, 96, 21, 0, // Skip to: 86948 +/* 81476 */ MCD_OPC_CheckField, 10, 1, 0, 89, 21, 0, // Skip to: 86948 +/* 81483 */ MCD_OPC_Decode, 220, 24, 224, 3, // Opcode: SQDMLSLv1i64_indexed +/* 81488 */ MCD_OPC_FilterValue, 9, 221, 0, 0, // Skip to: 81714 +/* 81493 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81496 */ MCD_OPC_FilterValue, 0, 162, 0, 0, // Skip to: 81663 +/* 81501 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 81504 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 81519 +/* 81509 */ MCD_OPC_CheckPredicate, 4, 58, 21, 0, // Skip to: 86948 +/* 81514 */ MCD_OPC_Decode, 151, 11, 229, 3, // Opcode: FMULv1i16_indexed +/* 81519 */ MCD_OPC_FilterValue, 1, 48, 21, 0, // Skip to: 86948 +/* 81524 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 81527 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 81595 +/* 81532 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 81535 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 81580 +/* 81540 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 81543 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81565 +/* 81548 */ MCD_OPC_CheckPredicate, 3, 19, 21, 0, // Skip to: 86948 +/* 81553 */ MCD_OPC_CheckField, 19, 1, 1, 12, 21, 0, // Skip to: 86948 +/* 81560 */ MCD_OPC_Decode, 128, 26, 230, 3, // Opcode: SQSHRNb +/* 81565 */ MCD_OPC_FilterValue, 1, 2, 21, 0, // Skip to: 86948 +/* 81570 */ MCD_OPC_CheckPredicate, 3, 253, 20, 0, // Skip to: 86948 +/* 81575 */ MCD_OPC_Decode, 129, 26, 231, 3, // Opcode: SQSHRNh +/* 81580 */ MCD_OPC_FilterValue, 1, 243, 20, 0, // Skip to: 86948 +/* 81585 */ MCD_OPC_CheckPredicate, 3, 238, 20, 0, // Skip to: 86948 +/* 81590 */ MCD_OPC_Decode, 130, 26, 232, 3, // Opcode: SQSHRNs +/* 81595 */ MCD_OPC_FilterValue, 1, 228, 20, 0, // Skip to: 86948 +/* 81600 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 81603 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 81648 +/* 81608 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 81611 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 81633 +/* 81616 */ MCD_OPC_CheckPredicate, 3, 207, 20, 0, // Skip to: 86948 +/* 81621 */ MCD_OPC_CheckField, 19, 1, 1, 200, 20, 0, // Skip to: 86948 +/* 81628 */ MCD_OPC_Decode, 205, 25, 230, 3, // Opcode: SQRSHRNb +/* 81633 */ MCD_OPC_FilterValue, 1, 190, 20, 0, // Skip to: 86948 +/* 81638 */ MCD_OPC_CheckPredicate, 3, 185, 20, 0, // Skip to: 86948 +/* 81643 */ MCD_OPC_Decode, 206, 25, 231, 3, // Opcode: SQRSHRNh +/* 81648 */ MCD_OPC_FilterValue, 1, 175, 20, 0, // Skip to: 86948 +/* 81653 */ MCD_OPC_CheckPredicate, 3, 170, 20, 0, // Skip to: 86948 +/* 81658 */ MCD_OPC_Decode, 207, 25, 232, 3, // Opcode: SQRSHRNs +/* 81663 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 81685 +/* 81668 */ MCD_OPC_CheckPredicate, 3, 155, 20, 0, // Skip to: 86948 +/* 81673 */ MCD_OPC_CheckField, 10, 1, 0, 148, 20, 0, // Skip to: 86948 +/* 81680 */ MCD_OPC_Decode, 152, 11, 233, 3, // Opcode: FMULv1i32_indexed +/* 81685 */ MCD_OPC_FilterValue, 3, 138, 20, 0, // Skip to: 86948 +/* 81690 */ MCD_OPC_CheckPredicate, 3, 133, 20, 0, // Skip to: 86948 +/* 81695 */ MCD_OPC_CheckField, 21, 1, 0, 126, 20, 0, // Skip to: 86948 +/* 81702 */ MCD_OPC_CheckField, 10, 1, 0, 119, 20, 0, // Skip to: 86948 +/* 81709 */ MCD_OPC_Decode, 153, 11, 234, 3, // Opcode: FMULv1i64_indexed +/* 81714 */ MCD_OPC_FilterValue, 11, 47, 0, 0, // Skip to: 81766 +/* 81719 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81722 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81744 +/* 81727 */ MCD_OPC_CheckPredicate, 3, 96, 20, 0, // Skip to: 86948 +/* 81732 */ MCD_OPC_CheckField, 10, 1, 0, 89, 20, 0, // Skip to: 86948 +/* 81739 */ MCD_OPC_Decode, 243, 24, 235, 3, // Opcode: SQDMULLv1i32_indexed +/* 81744 */ MCD_OPC_FilterValue, 2, 79, 20, 0, // Skip to: 86948 +/* 81749 */ MCD_OPC_CheckPredicate, 3, 74, 20, 0, // Skip to: 86948 +/* 81754 */ MCD_OPC_CheckField, 10, 1, 0, 67, 20, 0, // Skip to: 86948 +/* 81761 */ MCD_OPC_Decode, 244, 24, 236, 3, // Opcode: SQDMULLv1i64_indexed +/* 81766 */ MCD_OPC_FilterValue, 12, 47, 0, 0, // Skip to: 81818 +/* 81771 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81774 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81796 +/* 81779 */ MCD_OPC_CheckPredicate, 3, 44, 20, 0, // Skip to: 86948 +/* 81784 */ MCD_OPC_CheckField, 10, 1, 0, 37, 20, 0, // Skip to: 86948 +/* 81791 */ MCD_OPC_Decode, 230, 24, 229, 3, // Opcode: SQDMULHv1i16_indexed +/* 81796 */ MCD_OPC_FilterValue, 2, 27, 20, 0, // Skip to: 86948 +/* 81801 */ MCD_OPC_CheckPredicate, 3, 22, 20, 0, // Skip to: 86948 +/* 81806 */ MCD_OPC_CheckField, 10, 1, 0, 15, 20, 0, // Skip to: 86948 +/* 81813 */ MCD_OPC_Decode, 232, 24, 233, 3, // Opcode: SQDMULHv1i32_indexed +/* 81818 */ MCD_OPC_FilterValue, 13, 47, 0, 0, // Skip to: 81870 +/* 81823 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81826 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 81848 +/* 81831 */ MCD_OPC_CheckPredicate, 3, 248, 19, 0, // Skip to: 86948 +/* 81836 */ MCD_OPC_CheckField, 10, 1, 0, 241, 19, 0, // Skip to: 86948 +/* 81843 */ MCD_OPC_Decode, 183, 25, 229, 3, // Opcode: SQRDMULHv1i16_indexed +/* 81848 */ MCD_OPC_FilterValue, 2, 231, 19, 0, // Skip to: 86948 +/* 81853 */ MCD_OPC_CheckPredicate, 3, 226, 19, 0, // Skip to: 86948 +/* 81858 */ MCD_OPC_CheckField, 10, 1, 0, 219, 19, 0, // Skip to: 86948 +/* 81865 */ MCD_OPC_Decode, 185, 25, 233, 3, // Opcode: SQRDMULHv1i32_indexed +/* 81870 */ MCD_OPC_FilterValue, 14, 84, 0, 0, // Skip to: 81959 +/* 81875 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81878 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 81937 +/* 81883 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 81886 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 81915 +/* 81891 */ MCD_OPC_CheckPredicate, 4, 188, 19, 0, // Skip to: 86948 +/* 81896 */ MCD_OPC_CheckField, 20, 1, 1, 181, 19, 0, // Skip to: 86948 +/* 81903 */ MCD_OPC_CheckField, 10, 2, 1, 174, 19, 0, // Skip to: 86948 +/* 81910 */ MCD_OPC_Decode, 204, 22, 237, 3, // Opcode: SCVTFh +/* 81915 */ MCD_OPC_FilterValue, 1, 164, 19, 0, // Skip to: 86948 +/* 81920 */ MCD_OPC_CheckPredicate, 3, 159, 19, 0, // Skip to: 86948 +/* 81925 */ MCD_OPC_CheckField, 10, 2, 1, 152, 19, 0, // Skip to: 86948 +/* 81932 */ MCD_OPC_Decode, 205, 22, 238, 3, // Opcode: SCVTFs +/* 81937 */ MCD_OPC_FilterValue, 1, 142, 19, 0, // Skip to: 86948 +/* 81942 */ MCD_OPC_CheckPredicate, 3, 137, 19, 0, // Skip to: 86948 +/* 81947 */ MCD_OPC_CheckField, 10, 2, 1, 130, 19, 0, // Skip to: 86948 +/* 81954 */ MCD_OPC_Decode, 203, 22, 218, 3, // Opcode: SCVTFd +/* 81959 */ MCD_OPC_FilterValue, 15, 120, 19, 0, // Skip to: 86948 +/* 81964 */ MCD_OPC_ExtractField, 22, 2, // Inst{23-22} ... +/* 81967 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 82026 +/* 81972 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 81975 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 82004 +/* 81980 */ MCD_OPC_CheckPredicate, 4, 99, 19, 0, // Skip to: 86948 +/* 81985 */ MCD_OPC_CheckField, 20, 1, 1, 92, 19, 0, // Skip to: 86948 +/* 81992 */ MCD_OPC_CheckField, 10, 2, 3, 85, 19, 0, // Skip to: 86948 +/* 81999 */ MCD_OPC_Decode, 238, 8, 237, 3, // Opcode: FCVTZSh +/* 82004 */ MCD_OPC_FilterValue, 1, 75, 19, 0, // Skip to: 86948 +/* 82009 */ MCD_OPC_CheckPredicate, 3, 70, 19, 0, // Skip to: 86948 +/* 82014 */ MCD_OPC_CheckField, 10, 2, 3, 63, 19, 0, // Skip to: 86948 +/* 82021 */ MCD_OPC_Decode, 239, 8, 238, 3, // Opcode: FCVTZSs +/* 82026 */ MCD_OPC_FilterValue, 1, 53, 19, 0, // Skip to: 86948 +/* 82031 */ MCD_OPC_CheckPredicate, 3, 48, 19, 0, // Skip to: 86948 +/* 82036 */ MCD_OPC_CheckField, 10, 2, 3, 41, 19, 0, // Skip to: 86948 +/* 82043 */ MCD_OPC_Decode, 237, 8, 218, 3, // Opcode: FCVTZSd +/* 82048 */ MCD_OPC_FilterValue, 3, 213, 12, 0, // Skip to: 85338 +/* 82053 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 82056 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 82157 +/* 82061 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 82064 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 82081 +/* 82069 */ MCD_OPC_CheckField, 21, 1, 0, 8, 19, 0, // Skip to: 86948 +/* 82076 */ MCD_OPC_Decode, 200, 29, 255, 2, // Opcode: STURHi +/* 82081 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 82098 +/* 82086 */ MCD_OPC_CheckField, 21, 1, 0, 247, 18, 0, // Skip to: 86948 +/* 82093 */ MCD_OPC_Decode, 165, 29, 255, 2, // Opcode: STRHpost +/* 82098 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 82140 +/* 82103 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 82106 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 82123 +/* 82111 */ MCD_OPC_CheckField, 21, 1, 1, 222, 18, 0, // Skip to: 86948 +/* 82118 */ MCD_OPC_Decode, 167, 29, 239, 3, // Opcode: STRHroW +/* 82123 */ MCD_OPC_FilterValue, 3, 212, 18, 0, // Skip to: 86948 +/* 82128 */ MCD_OPC_CheckField, 21, 1, 1, 205, 18, 0, // Skip to: 86948 +/* 82135 */ MCD_OPC_Decode, 168, 29, 240, 3, // Opcode: STRHroX +/* 82140 */ MCD_OPC_FilterValue, 3, 195, 18, 0, // Skip to: 86948 +/* 82145 */ MCD_OPC_CheckField, 21, 1, 0, 188, 18, 0, // Skip to: 86948 +/* 82152 */ MCD_OPC_Decode, 166, 29, 255, 2, // Opcode: STRHpre +/* 82157 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 82258 +/* 82162 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 82165 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 82182 +/* 82170 */ MCD_OPC_CheckField, 21, 1, 0, 163, 18, 0, // Skip to: 86948 +/* 82177 */ MCD_OPC_Decode, 134, 19, 255, 2, // Opcode: LDURHi +/* 82182 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 82199 +/* 82187 */ MCD_OPC_CheckField, 21, 1, 0, 146, 18, 0, // Skip to: 86948 +/* 82194 */ MCD_OPC_Decode, 240, 17, 255, 2, // Opcode: LDRHpost +/* 82199 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 82241 +/* 82204 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 82207 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 82224 +/* 82212 */ MCD_OPC_CheckField, 21, 1, 1, 121, 18, 0, // Skip to: 86948 +/* 82219 */ MCD_OPC_Decode, 242, 17, 239, 3, // Opcode: LDRHroW +/* 82224 */ MCD_OPC_FilterValue, 3, 111, 18, 0, // Skip to: 86948 +/* 82229 */ MCD_OPC_CheckField, 21, 1, 1, 104, 18, 0, // Skip to: 86948 +/* 82236 */ MCD_OPC_Decode, 243, 17, 240, 3, // Opcode: LDRHroX +/* 82241 */ MCD_OPC_FilterValue, 3, 94, 18, 0, // Skip to: 86948 +/* 82246 */ MCD_OPC_CheckField, 21, 1, 0, 87, 18, 0, // Skip to: 86948 +/* 82253 */ MCD_OPC_Decode, 241, 17, 255, 2, // Opcode: LDRHpre +/* 82258 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 82268 +/* 82263 */ MCD_OPC_Decode, 169, 29, 137, 3, // Opcode: STRHui +/* 82268 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 82278 +/* 82273 */ MCD_OPC_Decode, 244, 17, 137, 3, // Opcode: LDRHui +/* 82278 */ MCD_OPC_FilterValue, 8, 109, 1, 0, // Skip to: 82648 +/* 82283 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 82286 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 82308 +/* 82291 */ MCD_OPC_CheckPredicate, 3, 44, 18, 0, // Skip to: 86948 +/* 82296 */ MCD_OPC_CheckField, 21, 1, 1, 37, 18, 0, // Skip to: 86948 +/* 82303 */ MCD_OPC_Decode, 215, 32, 208, 3, // Opcode: UQADDv1i8 +/* 82308 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 82330 +/* 82313 */ MCD_OPC_CheckPredicate, 3, 22, 18, 0, // Skip to: 86948 +/* 82318 */ MCD_OPC_CheckField, 16, 6, 33, 15, 18, 0, // Skip to: 86948 +/* 82325 */ MCD_OPC_Decode, 177, 26, 212, 3, // Opcode: SQXTUNv1i8 +/* 82330 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 82352 +/* 82335 */ MCD_OPC_CheckPredicate, 3, 0, 18, 0, // Skip to: 86948 +/* 82340 */ MCD_OPC_CheckField, 21, 1, 1, 249, 17, 0, // Skip to: 86948 +/* 82347 */ MCD_OPC_Decode, 201, 33, 208, 3, // Opcode: UQSUBv1i8 +/* 82352 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 82374 +/* 82357 */ MCD_OPC_CheckPredicate, 3, 234, 17, 0, // Skip to: 86948 +/* 82362 */ MCD_OPC_CheckField, 16, 6, 32, 227, 17, 0, // Skip to: 86948 +/* 82369 */ MCD_OPC_Decode, 149, 34, 209, 3, // Opcode: USQADDv1i8 +/* 82374 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 82396 +/* 82379 */ MCD_OPC_CheckPredicate, 3, 212, 17, 0, // Skip to: 86948 +/* 82384 */ MCD_OPC_CheckField, 16, 6, 33, 205, 17, 0, // Skip to: 86948 +/* 82391 */ MCD_OPC_Decode, 211, 33, 212, 3, // Opcode: UQXTNv1i8 +/* 82396 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 82418 +/* 82401 */ MCD_OPC_CheckPredicate, 3, 190, 17, 0, // Skip to: 86948 +/* 82406 */ MCD_OPC_CheckField, 21, 1, 1, 183, 17, 0, // Skip to: 86948 +/* 82413 */ MCD_OPC_Decode, 167, 33, 208, 3, // Opcode: UQSHLv1i8 +/* 82418 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 82440 +/* 82423 */ MCD_OPC_CheckPredicate, 3, 168, 17, 0, // Skip to: 86948 +/* 82428 */ MCD_OPC_CheckField, 21, 1, 1, 161, 17, 0, // Skip to: 86948 +/* 82435 */ MCD_OPC_Decode, 142, 33, 208, 3, // Opcode: UQRSHLv1i8 +/* 82440 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 82462 +/* 82445 */ MCD_OPC_CheckPredicate, 3, 146, 17, 0, // Skip to: 86948 +/* 82450 */ MCD_OPC_CheckField, 16, 6, 32, 139, 17, 0, // Skip to: 86948 +/* 82457 */ MCD_OPC_Decode, 151, 25, 213, 3, // Opcode: SQNEGv1i8 +/* 82462 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 82484 +/* 82467 */ MCD_OPC_CheckPredicate, 3, 124, 17, 0, // Skip to: 86948 +/* 82472 */ MCD_OPC_CheckField, 16, 6, 33, 117, 17, 0, // Skip to: 86948 +/* 82479 */ MCD_OPC_Decode, 174, 8, 167, 3, // Opcode: FCVTNUv1i32 +/* 82484 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 82506 +/* 82489 */ MCD_OPC_CheckPredicate, 3, 102, 17, 0, // Skip to: 86948 +/* 82494 */ MCD_OPC_CheckField, 16, 6, 33, 95, 17, 0, // Skip to: 86948 +/* 82501 */ MCD_OPC_Decode, 146, 8, 167, 3, // Opcode: FCVTMUv1i32 +/* 82506 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 82544 +/* 82511 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 82514 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82529 +/* 82519 */ MCD_OPC_CheckPredicate, 3, 72, 17, 0, // Skip to: 86948 +/* 82524 */ MCD_OPC_Decode, 238, 7, 167, 3, // Opcode: FCVTAUv1i32 +/* 82529 */ MCD_OPC_FilterValue, 48, 62, 17, 0, // Skip to: 86948 +/* 82534 */ MCD_OPC_CheckPredicate, 3, 57, 17, 0, // Skip to: 86948 +/* 82539 */ MCD_OPC_Decode, 200, 9, 166, 2, // Opcode: FMAXNMPv2i32p +/* 82544 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 82582 +/* 82549 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 82552 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82567 +/* 82557 */ MCD_OPC_CheckPredicate, 3, 34, 17, 0, // Skip to: 86948 +/* 82562 */ MCD_OPC_Decode, 194, 31, 167, 3, // Opcode: UCVTFv1i32 +/* 82567 */ MCD_OPC_FilterValue, 48, 24, 17, 0, // Skip to: 86948 +/* 82572 */ MCD_OPC_CheckPredicate, 3, 19, 17, 0, // Skip to: 86948 +/* 82577 */ MCD_OPC_Decode, 180, 6, 166, 2, // Opcode: FADDPv2i32p +/* 82582 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 82604 +/* 82587 */ MCD_OPC_CheckPredicate, 3, 4, 17, 0, // Skip to: 86948 +/* 82592 */ MCD_OPC_CheckField, 21, 1, 1, 253, 16, 0, // Skip to: 86948 +/* 82599 */ MCD_OPC_Decode, 240, 6, 172, 3, // Opcode: FCMGE32 +/* 82604 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 82626 +/* 82609 */ MCD_OPC_CheckPredicate, 3, 238, 16, 0, // Skip to: 86948 +/* 82614 */ MCD_OPC_CheckField, 21, 1, 1, 231, 16, 0, // Skip to: 86948 +/* 82621 */ MCD_OPC_Decode, 151, 6, 172, 3, // Opcode: FACGE32 +/* 82626 */ MCD_OPC_FilterValue, 62, 221, 16, 0, // Skip to: 86948 +/* 82631 */ MCD_OPC_CheckPredicate, 3, 216, 16, 0, // Skip to: 86948 +/* 82636 */ MCD_OPC_CheckField, 16, 6, 48, 209, 16, 0, // Skip to: 86948 +/* 82643 */ MCD_OPC_Decode, 226, 9, 166, 2, // Opcode: FMAXPv2i32p +/* 82648 */ MCD_OPC_FilterValue, 9, 41, 2, 0, // Skip to: 83206 +/* 82653 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 82656 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 82678 +/* 82661 */ MCD_OPC_CheckPredicate, 3, 186, 16, 0, // Skip to: 86948 +/* 82666 */ MCD_OPC_CheckField, 21, 1, 1, 179, 16, 0, // Skip to: 86948 +/* 82673 */ MCD_OPC_Decode, 212, 32, 193, 3, // Opcode: UQADDv1i16 +/* 82678 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 82700 +/* 82683 */ MCD_OPC_CheckPredicate, 4, 164, 16, 0, // Skip to: 86948 +/* 82688 */ MCD_OPC_CheckField, 21, 1, 0, 157, 16, 0, // Skip to: 86948 +/* 82695 */ MCD_OPC_Decode, 239, 6, 193, 3, // Opcode: FCMGE16 +/* 82700 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 82722 +/* 82705 */ MCD_OPC_CheckPredicate, 3, 142, 16, 0, // Skip to: 86948 +/* 82710 */ MCD_OPC_CheckField, 16, 6, 33, 135, 16, 0, // Skip to: 86948 +/* 82717 */ MCD_OPC_Decode, 175, 26, 169, 3, // Opcode: SQXTUNv1i16 +/* 82722 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 82760 +/* 82727 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 82730 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 82745 +/* 82735 */ MCD_OPC_CheckPredicate, 4, 112, 16, 0, // Skip to: 86948 +/* 82740 */ MCD_OPC_Decode, 150, 6, 193, 3, // Opcode: FACGE16 +/* 82745 */ MCD_OPC_FilterValue, 1, 102, 16, 0, // Skip to: 86948 +/* 82750 */ MCD_OPC_CheckPredicate, 3, 97, 16, 0, // Skip to: 86948 +/* 82755 */ MCD_OPC_Decode, 198, 33, 193, 3, // Opcode: UQSUBv1i16 +/* 82760 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 82782 +/* 82765 */ MCD_OPC_CheckPredicate, 3, 82, 16, 0, // Skip to: 86948 +/* 82770 */ MCD_OPC_CheckField, 16, 6, 32, 75, 16, 0, // Skip to: 86948 +/* 82777 */ MCD_OPC_Decode, 146, 34, 210, 3, // Opcode: USQADDv1i16 +/* 82782 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 82804 +/* 82787 */ MCD_OPC_CheckPredicate, 3, 60, 16, 0, // Skip to: 86948 +/* 82792 */ MCD_OPC_CheckField, 16, 6, 33, 53, 16, 0, // Skip to: 86948 +/* 82799 */ MCD_OPC_Decode, 209, 33, 169, 3, // Opcode: UQXTNv1i16 +/* 82804 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 82826 +/* 82809 */ MCD_OPC_CheckPredicate, 3, 38, 16, 0, // Skip to: 86948 +/* 82814 */ MCD_OPC_CheckField, 21, 1, 1, 31, 16, 0, // Skip to: 86948 +/* 82821 */ MCD_OPC_Decode, 164, 33, 193, 3, // Opcode: UQSHLv1i16 +/* 82826 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 82848 +/* 82831 */ MCD_OPC_CheckPredicate, 3, 16, 16, 0, // Skip to: 86948 +/* 82836 */ MCD_OPC_CheckField, 21, 1, 1, 9, 16, 0, // Skip to: 86948 +/* 82843 */ MCD_OPC_Decode, 139, 33, 193, 3, // Opcode: UQRSHLv1i16 +/* 82848 */ MCD_OPC_FilterValue, 26, 17, 0, 0, // Skip to: 82870 +/* 82853 */ MCD_OPC_CheckPredicate, 3, 250, 15, 0, // Skip to: 86948 +/* 82858 */ MCD_OPC_CheckField, 16, 6, 33, 243, 15, 0, // Skip to: 86948 +/* 82865 */ MCD_OPC_Decode, 215, 8, 166, 2, // Opcode: FCVTXNv1i64 +/* 82870 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 82892 +/* 82875 */ MCD_OPC_CheckPredicate, 3, 228, 15, 0, // Skip to: 86948 +/* 82880 */ MCD_OPC_CheckField, 16, 6, 32, 221, 15, 0, // Skip to: 86948 +/* 82887 */ MCD_OPC_Decode, 148, 25, 188, 3, // Opcode: SQNEGv1i16 +/* 82892 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 82914 +/* 82897 */ MCD_OPC_CheckPredicate, 20, 206, 15, 0, // Skip to: 86948 +/* 82902 */ MCD_OPC_CheckField, 21, 1, 0, 199, 15, 0, // Skip to: 86948 +/* 82909 */ MCD_OPC_Decode, 160, 25, 241, 3, // Opcode: SQRDMLAHv1i16 +/* 82914 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 82936 +/* 82919 */ MCD_OPC_CheckPredicate, 20, 184, 15, 0, // Skip to: 86948 +/* 82924 */ MCD_OPC_CheckField, 21, 1, 0, 177, 15, 0, // Skip to: 86948 +/* 82931 */ MCD_OPC_Decode, 172, 25, 241, 3, // Opcode: SQRDMLSHv1i16 +/* 82936 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 82974 +/* 82941 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 82944 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 82959 +/* 82949 */ MCD_OPC_CheckPredicate, 3, 154, 15, 0, // Skip to: 86948 +/* 82954 */ MCD_OPC_Decode, 175, 8, 239, 1, // Opcode: FCVTNUv1i64 +/* 82959 */ MCD_OPC_FilterValue, 57, 144, 15, 0, // Skip to: 86948 +/* 82964 */ MCD_OPC_CheckPredicate, 4, 139, 15, 0, // Skip to: 86948 +/* 82969 */ MCD_OPC_Decode, 173, 8, 188, 3, // Opcode: FCVTNUv1f16 +/* 82974 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 82996 +/* 82979 */ MCD_OPC_CheckPredicate, 3, 124, 15, 0, // Skip to: 86948 +/* 82984 */ MCD_OPC_CheckField, 21, 1, 1, 117, 15, 0, // Skip to: 86948 +/* 82991 */ MCD_OPC_Decode, 182, 25, 193, 3, // Opcode: SQRDMULHv1i16 +/* 82996 */ MCD_OPC_FilterValue, 46, 33, 0, 0, // Skip to: 83034 +/* 83001 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 83004 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83019 +/* 83009 */ MCD_OPC_CheckPredicate, 3, 94, 15, 0, // Skip to: 86948 +/* 83014 */ MCD_OPC_Decode, 147, 8, 239, 1, // Opcode: FCVTMUv1i64 +/* 83019 */ MCD_OPC_FilterValue, 57, 84, 15, 0, // Skip to: 86948 +/* 83024 */ MCD_OPC_CheckPredicate, 4, 79, 15, 0, // Skip to: 86948 +/* 83029 */ MCD_OPC_Decode, 145, 8, 188, 3, // Opcode: FCVTMUv1f16 +/* 83034 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 83087 +/* 83039 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 83042 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83057 +/* 83047 */ MCD_OPC_CheckPredicate, 3, 56, 15, 0, // Skip to: 86948 +/* 83052 */ MCD_OPC_Decode, 239, 7, 239, 1, // Opcode: FCVTAUv1i64 +/* 83057 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 83072 +/* 83062 */ MCD_OPC_CheckPredicate, 3, 41, 15, 0, // Skip to: 86948 +/* 83067 */ MCD_OPC_Decode, 201, 9, 244, 1, // Opcode: FMAXNMPv2i64p +/* 83072 */ MCD_OPC_FilterValue, 57, 31, 15, 0, // Skip to: 86948 +/* 83077 */ MCD_OPC_CheckPredicate, 4, 26, 15, 0, // Skip to: 86948 +/* 83082 */ MCD_OPC_Decode, 237, 7, 188, 3, // Opcode: FCVTAUv1f16 +/* 83087 */ MCD_OPC_FilterValue, 54, 48, 0, 0, // Skip to: 83140 +/* 83092 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 83095 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 83110 +/* 83100 */ MCD_OPC_CheckPredicate, 3, 3, 15, 0, // Skip to: 86948 +/* 83105 */ MCD_OPC_Decode, 195, 31, 239, 1, // Opcode: UCVTFv1i64 +/* 83110 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 83125 +/* 83115 */ MCD_OPC_CheckPredicate, 3, 244, 14, 0, // Skip to: 86948 +/* 83120 */ MCD_OPC_Decode, 181, 6, 244, 1, // Opcode: FADDPv2i64p +/* 83125 */ MCD_OPC_FilterValue, 57, 234, 14, 0, // Skip to: 86948 +/* 83130 */ MCD_OPC_CheckPredicate, 4, 229, 14, 0, // Skip to: 86948 +/* 83135 */ MCD_OPC_Decode, 193, 31, 188, 3, // Opcode: UCVTFv1i16 +/* 83140 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 83162 +/* 83145 */ MCD_OPC_CheckPredicate, 3, 214, 14, 0, // Skip to: 86948 +/* 83150 */ MCD_OPC_CheckField, 21, 1, 1, 207, 14, 0, // Skip to: 86948 +/* 83157 */ MCD_OPC_Decode, 241, 6, 238, 1, // Opcode: FCMGE64 +/* 83162 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 83184 +/* 83167 */ MCD_OPC_CheckPredicate, 3, 192, 14, 0, // Skip to: 86948 +/* 83172 */ MCD_OPC_CheckField, 21, 1, 1, 185, 14, 0, // Skip to: 86948 +/* 83179 */ MCD_OPC_Decode, 152, 6, 238, 1, // Opcode: FACGE64 +/* 83184 */ MCD_OPC_FilterValue, 62, 175, 14, 0, // Skip to: 86948 +/* 83189 */ MCD_OPC_CheckPredicate, 3, 170, 14, 0, // Skip to: 86948 +/* 83194 */ MCD_OPC_CheckField, 16, 6, 48, 163, 14, 0, // Skip to: 86948 +/* 83201 */ MCD_OPC_Decode, 227, 9, 244, 1, // Opcode: FMAXPv2i64p +/* 83206 */ MCD_OPC_FilterValue, 10, 197, 1, 0, // Skip to: 83664 +/* 83211 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 83214 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 83236 +/* 83219 */ MCD_OPC_CheckPredicate, 3, 140, 14, 0, // Skip to: 86948 +/* 83224 */ MCD_OPC_CheckField, 21, 1, 1, 133, 14, 0, // Skip to: 86948 +/* 83231 */ MCD_OPC_Decode, 213, 32, 172, 3, // Opcode: UQADDv1i32 +/* 83236 */ MCD_OPC_FilterValue, 10, 17, 0, 0, // Skip to: 83258 +/* 83241 */ MCD_OPC_CheckPredicate, 3, 118, 14, 0, // Skip to: 86948 +/* 83246 */ MCD_OPC_CheckField, 16, 6, 33, 111, 14, 0, // Skip to: 86948 +/* 83253 */ MCD_OPC_Decode, 176, 26, 166, 2, // Opcode: SQXTUNv1i32 +/* 83258 */ MCD_OPC_FilterValue, 11, 17, 0, 0, // Skip to: 83280 +/* 83263 */ MCD_OPC_CheckPredicate, 3, 96, 14, 0, // Skip to: 86948 +/* 83268 */ MCD_OPC_CheckField, 21, 1, 1, 89, 14, 0, // Skip to: 86948 +/* 83275 */ MCD_OPC_Decode, 199, 33, 172, 3, // Opcode: UQSUBv1i32 +/* 83280 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 83302 +/* 83285 */ MCD_OPC_CheckPredicate, 3, 74, 14, 0, // Skip to: 86948 +/* 83290 */ MCD_OPC_CheckField, 16, 6, 32, 67, 14, 0, // Skip to: 86948 +/* 83297 */ MCD_OPC_Decode, 147, 34, 211, 3, // Opcode: USQADDv1i32 +/* 83302 */ MCD_OPC_FilterValue, 18, 17, 0, 0, // Skip to: 83324 +/* 83307 */ MCD_OPC_CheckPredicate, 3, 52, 14, 0, // Skip to: 86948 +/* 83312 */ MCD_OPC_CheckField, 16, 6, 33, 45, 14, 0, // Skip to: 86948 +/* 83319 */ MCD_OPC_Decode, 210, 33, 166, 2, // Opcode: UQXTNv1i32 +/* 83324 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 83346 +/* 83329 */ MCD_OPC_CheckPredicate, 3, 30, 14, 0, // Skip to: 86948 +/* 83334 */ MCD_OPC_CheckField, 21, 1, 1, 23, 14, 0, // Skip to: 86948 +/* 83341 */ MCD_OPC_Decode, 165, 33, 172, 3, // Opcode: UQSHLv1i32 +/* 83346 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 83368 +/* 83351 */ MCD_OPC_CheckPredicate, 3, 8, 14, 0, // Skip to: 86948 +/* 83356 */ MCD_OPC_CheckField, 21, 1, 1, 1, 14, 0, // Skip to: 86948 +/* 83363 */ MCD_OPC_Decode, 140, 33, 172, 3, // Opcode: UQRSHLv1i32 +/* 83368 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 83390 +/* 83373 */ MCD_OPC_CheckPredicate, 3, 242, 13, 0, // Skip to: 86948 +/* 83378 */ MCD_OPC_CheckField, 16, 6, 32, 235, 13, 0, // Skip to: 86948 +/* 83385 */ MCD_OPC_Decode, 149, 25, 167, 3, // Opcode: SQNEGv1i32 +/* 83390 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 83412 +/* 83395 */ MCD_OPC_CheckPredicate, 20, 220, 13, 0, // Skip to: 86948 +/* 83400 */ MCD_OPC_CheckField, 21, 1, 0, 213, 13, 0, // Skip to: 86948 +/* 83407 */ MCD_OPC_Decode, 161, 25, 242, 3, // Opcode: SQRDMLAHv1i32 +/* 83412 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 83434 +/* 83417 */ MCD_OPC_CheckPredicate, 20, 198, 13, 0, // Skip to: 86948 +/* 83422 */ MCD_OPC_CheckField, 21, 1, 0, 191, 13, 0, // Skip to: 86948 +/* 83429 */ MCD_OPC_Decode, 173, 25, 242, 3, // Opcode: SQRDMLSHv1i32 +/* 83434 */ MCD_OPC_FilterValue, 42, 17, 0, 0, // Skip to: 83456 +/* 83439 */ MCD_OPC_CheckPredicate, 3, 176, 13, 0, // Skip to: 86948 +/* 83444 */ MCD_OPC_CheckField, 16, 6, 33, 169, 13, 0, // Skip to: 86948 +/* 83451 */ MCD_OPC_Decode, 206, 8, 167, 3, // Opcode: FCVTPUv1i32 +/* 83456 */ MCD_OPC_FilterValue, 45, 17, 0, 0, // Skip to: 83478 +/* 83461 */ MCD_OPC_CheckPredicate, 3, 154, 13, 0, // Skip to: 86948 +/* 83466 */ MCD_OPC_CheckField, 21, 1, 1, 147, 13, 0, // Skip to: 86948 +/* 83473 */ MCD_OPC_Decode, 184, 25, 172, 3, // Opcode: SQRDMULHv1i32 +/* 83478 */ MCD_OPC_FilterValue, 46, 17, 0, 0, // Skip to: 83500 +/* 83483 */ MCD_OPC_CheckPredicate, 3, 132, 13, 0, // Skip to: 86948 +/* 83488 */ MCD_OPC_CheckField, 16, 6, 33, 125, 13, 0, // Skip to: 86948 +/* 83495 */ MCD_OPC_Decode, 148, 9, 167, 3, // Opcode: FCVTZUv1i32 +/* 83500 */ MCD_OPC_FilterValue, 50, 33, 0, 0, // Skip to: 83538 +/* 83505 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 83508 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 83523 +/* 83513 */ MCD_OPC_CheckPredicate, 3, 102, 13, 0, // Skip to: 86948 +/* 83518 */ MCD_OPC_Decode, 249, 6, 167, 3, // Opcode: FCMGEv1i32rz +/* 83523 */ MCD_OPC_FilterValue, 48, 92, 13, 0, // Skip to: 86948 +/* 83528 */ MCD_OPC_CheckPredicate, 3, 87, 13, 0, // Skip to: 86948 +/* 83533 */ MCD_OPC_Decode, 128, 10, 166, 2, // Opcode: FMINNMPv2i32p +/* 83538 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 83560 +/* 83543 */ MCD_OPC_CheckPredicate, 3, 72, 13, 0, // Skip to: 86948 +/* 83548 */ MCD_OPC_CheckField, 21, 1, 1, 65, 13, 0, // Skip to: 86948 +/* 83555 */ MCD_OPC_Decode, 129, 6, 172, 3, // Opcode: FABD32 +/* 83560 */ MCD_OPC_FilterValue, 54, 33, 0, 0, // Skip to: 83598 +/* 83565 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 83568 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 83583 +/* 83573 */ MCD_OPC_CheckPredicate, 3, 42, 13, 0, // Skip to: 86948 +/* 83578 */ MCD_OPC_Decode, 172, 7, 167, 3, // Opcode: FCMLEv1i32rz +/* 83583 */ MCD_OPC_FilterValue, 33, 32, 13, 0, // Skip to: 86948 +/* 83588 */ MCD_OPC_CheckPredicate, 3, 27, 13, 0, // Skip to: 86948 +/* 83593 */ MCD_OPC_Decode, 177, 12, 167, 3, // Opcode: FRSQRTEv1i32 +/* 83598 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 83620 +/* 83603 */ MCD_OPC_CheckPredicate, 3, 12, 13, 0, // Skip to: 86948 +/* 83608 */ MCD_OPC_CheckField, 21, 1, 1, 5, 13, 0, // Skip to: 86948 +/* 83615 */ MCD_OPC_Decode, 134, 7, 172, 3, // Opcode: FCMGT32 +/* 83620 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 83642 +/* 83625 */ MCD_OPC_CheckPredicate, 3, 246, 12, 0, // Skip to: 86948 +/* 83630 */ MCD_OPC_CheckField, 21, 1, 1, 239, 12, 0, // Skip to: 86948 +/* 83637 */ MCD_OPC_Decode, 162, 6, 172, 3, // Opcode: FACGT32 +/* 83642 */ MCD_OPC_FilterValue, 62, 229, 12, 0, // Skip to: 86948 +/* 83647 */ MCD_OPC_CheckPredicate, 3, 224, 12, 0, // Skip to: 86948 +/* 83652 */ MCD_OPC_CheckField, 16, 6, 48, 217, 12, 0, // Skip to: 86948 +/* 83659 */ MCD_OPC_Decode, 154, 10, 166, 2, // Opcode: FMINPv2i32p +/* 83664 */ MCD_OPC_FilterValue, 11, 159, 2, 0, // Skip to: 84340 +/* 83669 */ MCD_OPC_ExtractField, 10, 6, // Inst{15-10} ... +/* 83672 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 83694 +/* 83677 */ MCD_OPC_CheckPredicate, 3, 194, 12, 0, // Skip to: 86948 +/* 83682 */ MCD_OPC_CheckField, 21, 1, 1, 187, 12, 0, // Skip to: 86948 +/* 83689 */ MCD_OPC_Decode, 214, 32, 238, 1, // Opcode: UQADDv1i64 +/* 83694 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 83716 +/* 83699 */ MCD_OPC_CheckPredicate, 4, 172, 12, 0, // Skip to: 86948 +/* 83704 */ MCD_OPC_CheckField, 21, 1, 0, 165, 12, 0, // Skip to: 86948 +/* 83711 */ MCD_OPC_Decode, 128, 6, 193, 3, // Opcode: FABD16 +/* 83716 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 83738 +/* 83721 */ MCD_OPC_CheckPredicate, 4, 150, 12, 0, // Skip to: 86948 +/* 83726 */ MCD_OPC_CheckField, 21, 1, 0, 143, 12, 0, // Skip to: 86948 +/* 83733 */ MCD_OPC_Decode, 133, 7, 193, 3, // Opcode: FCMGT16 +/* 83738 */ MCD_OPC_FilterValue, 11, 33, 0, 0, // Skip to: 83776 +/* 83743 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 83746 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 83761 +/* 83751 */ MCD_OPC_CheckPredicate, 4, 120, 12, 0, // Skip to: 86948 +/* 83756 */ MCD_OPC_Decode, 161, 6, 193, 3, // Opcode: FACGT16 +/* 83761 */ MCD_OPC_FilterValue, 1, 110, 12, 0, // Skip to: 86948 +/* 83766 */ MCD_OPC_CheckPredicate, 3, 105, 12, 0, // Skip to: 86948 +/* 83771 */ MCD_OPC_Decode, 200, 33, 238, 1, // Opcode: UQSUBv1i64 +/* 83776 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 83798 +/* 83781 */ MCD_OPC_CheckPredicate, 3, 90, 12, 0, // Skip to: 86948 +/* 83786 */ MCD_OPC_CheckField, 21, 1, 1, 83, 12, 0, // Skip to: 86948 +/* 83793 */ MCD_OPC_Decode, 231, 3, 238, 1, // Opcode: CMHIv1i64 +/* 83798 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 83820 +/* 83803 */ MCD_OPC_CheckPredicate, 3, 68, 12, 0, // Skip to: 86948 +/* 83808 */ MCD_OPC_CheckField, 16, 6, 32, 61, 12, 0, // Skip to: 86948 +/* 83815 */ MCD_OPC_Decode, 148, 34, 248, 1, // Opcode: USQADDv1i64 +/* 83820 */ MCD_OPC_FilterValue, 15, 17, 0, 0, // Skip to: 83842 +/* 83825 */ MCD_OPC_CheckPredicate, 3, 46, 12, 0, // Skip to: 86948 +/* 83830 */ MCD_OPC_CheckField, 21, 1, 1, 39, 12, 0, // Skip to: 86948 +/* 83837 */ MCD_OPC_Decode, 239, 3, 238, 1, // Opcode: CMHSv1i64 +/* 83842 */ MCD_OPC_FilterValue, 17, 17, 0, 0, // Skip to: 83864 +/* 83847 */ MCD_OPC_CheckPredicate, 3, 24, 12, 0, // Skip to: 86948 +/* 83852 */ MCD_OPC_CheckField, 21, 1, 1, 17, 12, 0, // Skip to: 86948 +/* 83859 */ MCD_OPC_Decode, 130, 34, 238, 1, // Opcode: USHLv1i64 +/* 83864 */ MCD_OPC_FilterValue, 19, 17, 0, 0, // Skip to: 83886 +/* 83869 */ MCD_OPC_CheckPredicate, 3, 2, 12, 0, // Skip to: 86948 +/* 83874 */ MCD_OPC_CheckField, 21, 1, 1, 251, 11, 0, // Skip to: 86948 +/* 83881 */ MCD_OPC_Decode, 166, 33, 238, 1, // Opcode: UQSHLv1i64 +/* 83886 */ MCD_OPC_FilterValue, 21, 17, 0, 0, // Skip to: 83908 +/* 83891 */ MCD_OPC_CheckPredicate, 3, 236, 11, 0, // Skip to: 86948 +/* 83896 */ MCD_OPC_CheckField, 21, 1, 1, 229, 11, 0, // Skip to: 86948 +/* 83903 */ MCD_OPC_Decode, 226, 33, 238, 1, // Opcode: URSHLv1i64 +/* 83908 */ MCD_OPC_FilterValue, 23, 17, 0, 0, // Skip to: 83930 +/* 83913 */ MCD_OPC_CheckPredicate, 3, 214, 11, 0, // Skip to: 86948 +/* 83918 */ MCD_OPC_CheckField, 21, 1, 1, 207, 11, 0, // Skip to: 86948 +/* 83925 */ MCD_OPC_Decode, 141, 33, 238, 1, // Opcode: UQRSHLv1i64 +/* 83930 */ MCD_OPC_FilterValue, 30, 17, 0, 0, // Skip to: 83952 +/* 83935 */ MCD_OPC_CheckPredicate, 3, 192, 11, 0, // Skip to: 86948 +/* 83940 */ MCD_OPC_CheckField, 16, 6, 32, 185, 11, 0, // Skip to: 86948 +/* 83947 */ MCD_OPC_Decode, 150, 25, 239, 1, // Opcode: SQNEGv1i64 +/* 83952 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 83974 +/* 83957 */ MCD_OPC_CheckPredicate, 3, 170, 11, 0, // Skip to: 86948 +/* 83962 */ MCD_OPC_CheckField, 21, 1, 1, 163, 11, 0, // Skip to: 86948 +/* 83969 */ MCD_OPC_Decode, 128, 30, 238, 1, // Opcode: SUBv1i64 +/* 83974 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 83996 +/* 83979 */ MCD_OPC_CheckPredicate, 3, 148, 11, 0, // Skip to: 86948 +/* 83984 */ MCD_OPC_CheckField, 16, 6, 32, 141, 11, 0, // Skip to: 86948 +/* 83991 */ MCD_OPC_Decode, 201, 3, 239, 1, // Opcode: CMGEv1i64rz +/* 83996 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 84018 +/* 84001 */ MCD_OPC_CheckPredicate, 3, 126, 11, 0, // Skip to: 86948 +/* 84006 */ MCD_OPC_CheckField, 21, 1, 1, 119, 11, 0, // Skip to: 86948 +/* 84013 */ MCD_OPC_Decode, 184, 3, 238, 1, // Opcode: CMEQv1i64 +/* 84018 */ MCD_OPC_FilterValue, 38, 17, 0, 0, // Skip to: 84040 +/* 84023 */ MCD_OPC_CheckPredicate, 3, 104, 11, 0, // Skip to: 86948 +/* 84028 */ MCD_OPC_CheckField, 16, 6, 32, 97, 11, 0, // Skip to: 86948 +/* 84035 */ MCD_OPC_Decode, 247, 3, 239, 1, // Opcode: CMLEv1i64rz +/* 84040 */ MCD_OPC_FilterValue, 42, 33, 0, 0, // Skip to: 84078 +/* 84045 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 84048 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84063 +/* 84053 */ MCD_OPC_CheckPredicate, 3, 74, 11, 0, // Skip to: 86948 +/* 84058 */ MCD_OPC_Decode, 207, 8, 239, 1, // Opcode: FCVTPUv1i64 +/* 84063 */ MCD_OPC_FilterValue, 57, 64, 11, 0, // Skip to: 86948 +/* 84068 */ MCD_OPC_CheckPredicate, 4, 59, 11, 0, // Skip to: 86948 +/* 84073 */ MCD_OPC_Decode, 205, 8, 188, 3, // Opcode: FCVTPUv1f16 +/* 84078 */ MCD_OPC_FilterValue, 46, 48, 0, 0, // Skip to: 84131 +/* 84083 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 84086 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84101 +/* 84091 */ MCD_OPC_CheckPredicate, 3, 36, 11, 0, // Skip to: 86948 +/* 84096 */ MCD_OPC_Decode, 180, 20, 239, 1, // Opcode: NEGv1i64 +/* 84101 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84116 +/* 84106 */ MCD_OPC_CheckPredicate, 3, 21, 11, 0, // Skip to: 86948 +/* 84111 */ MCD_OPC_Decode, 149, 9, 239, 1, // Opcode: FCVTZUv1i64 +/* 84116 */ MCD_OPC_FilterValue, 57, 11, 11, 0, // Skip to: 86948 +/* 84121 */ MCD_OPC_CheckPredicate, 4, 6, 11, 0, // Skip to: 86948 +/* 84126 */ MCD_OPC_Decode, 147, 9, 188, 3, // Opcode: FCVTZUv1f16 +/* 84131 */ MCD_OPC_FilterValue, 50, 48, 0, 0, // Skip to: 84184 +/* 84136 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 84139 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84154 +/* 84144 */ MCD_OPC_CheckPredicate, 3, 239, 10, 0, // Skip to: 86948 +/* 84149 */ MCD_OPC_Decode, 250, 6, 239, 1, // Opcode: FCMGEv1i64rz +/* 84154 */ MCD_OPC_FilterValue, 48, 10, 0, 0, // Skip to: 84169 +/* 84159 */ MCD_OPC_CheckPredicate, 3, 224, 10, 0, // Skip to: 86948 +/* 84164 */ MCD_OPC_Decode, 129, 10, 244, 1, // Opcode: FMINNMPv2i64p +/* 84169 */ MCD_OPC_FilterValue, 56, 214, 10, 0, // Skip to: 86948 +/* 84174 */ MCD_OPC_CheckPredicate, 4, 209, 10, 0, // Skip to: 86948 +/* 84179 */ MCD_OPC_Decode, 248, 6, 188, 3, // Opcode: FCMGEv1i16rz +/* 84184 */ MCD_OPC_FilterValue, 53, 17, 0, 0, // Skip to: 84206 +/* 84189 */ MCD_OPC_CheckPredicate, 3, 194, 10, 0, // Skip to: 86948 +/* 84194 */ MCD_OPC_CheckField, 21, 1, 1, 187, 10, 0, // Skip to: 86948 +/* 84201 */ MCD_OPC_Decode, 130, 6, 238, 1, // Opcode: FABD64 +/* 84206 */ MCD_OPC_FilterValue, 54, 63, 0, 0, // Skip to: 84274 +/* 84211 */ MCD_OPC_ExtractField, 16, 6, // Inst{21-16} ... +/* 84214 */ MCD_OPC_FilterValue, 32, 10, 0, 0, // Skip to: 84229 +/* 84219 */ MCD_OPC_CheckPredicate, 3, 164, 10, 0, // Skip to: 86948 +/* 84224 */ MCD_OPC_Decode, 173, 7, 239, 1, // Opcode: FCMLEv1i64rz +/* 84229 */ MCD_OPC_FilterValue, 33, 10, 0, 0, // Skip to: 84244 +/* 84234 */ MCD_OPC_CheckPredicate, 3, 149, 10, 0, // Skip to: 86948 +/* 84239 */ MCD_OPC_Decode, 178, 12, 239, 1, // Opcode: FRSQRTEv1i64 +/* 84244 */ MCD_OPC_FilterValue, 56, 10, 0, 0, // Skip to: 84259 +/* 84249 */ MCD_OPC_CheckPredicate, 4, 134, 10, 0, // Skip to: 86948 +/* 84254 */ MCD_OPC_Decode, 171, 7, 188, 3, // Opcode: FCMLEv1i16rz +/* 84259 */ MCD_OPC_FilterValue, 57, 124, 10, 0, // Skip to: 86948 +/* 84264 */ MCD_OPC_CheckPredicate, 4, 119, 10, 0, // Skip to: 86948 +/* 84269 */ MCD_OPC_Decode, 176, 12, 188, 3, // Opcode: FRSQRTEv1f16 +/* 84274 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 84296 +/* 84279 */ MCD_OPC_CheckPredicate, 3, 104, 10, 0, // Skip to: 86948 +/* 84284 */ MCD_OPC_CheckField, 21, 1, 1, 97, 10, 0, // Skip to: 86948 +/* 84291 */ MCD_OPC_Decode, 135, 7, 238, 1, // Opcode: FCMGT64 +/* 84296 */ MCD_OPC_FilterValue, 59, 17, 0, 0, // Skip to: 84318 +/* 84301 */ MCD_OPC_CheckPredicate, 3, 82, 10, 0, // Skip to: 86948 +/* 84306 */ MCD_OPC_CheckField, 21, 1, 1, 75, 10, 0, // Skip to: 86948 +/* 84313 */ MCD_OPC_Decode, 163, 6, 238, 1, // Opcode: FACGT64 +/* 84318 */ MCD_OPC_FilterValue, 62, 65, 10, 0, // Skip to: 86948 +/* 84323 */ MCD_OPC_CheckPredicate, 3, 60, 10, 0, // Skip to: 86948 +/* 84328 */ MCD_OPC_CheckField, 16, 6, 48, 53, 10, 0, // Skip to: 86948 +/* 84335 */ MCD_OPC_Decode, 155, 10, 244, 1, // Opcode: FMINPv2i64p +/* 84340 */ MCD_OPC_FilterValue, 12, 98, 2, 0, // Skip to: 84955 +/* 84345 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 84348 */ MCD_OPC_FilterValue, 6, 84, 0, 0, // Skip to: 84437 +/* 84353 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84356 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 84415 +/* 84361 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 84364 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84393 +/* 84369 */ MCD_OPC_CheckPredicate, 3, 14, 10, 0, // Skip to: 86948 +/* 84374 */ MCD_OPC_CheckField, 19, 1, 1, 7, 10, 0, // Skip to: 86948 +/* 84381 */ MCD_OPC_CheckField, 10, 2, 1, 0, 10, 0, // Skip to: 86948 +/* 84388 */ MCD_OPC_Decode, 223, 25, 226, 3, // Opcode: SQSHLUb +/* 84393 */ MCD_OPC_FilterValue, 1, 246, 9, 0, // Skip to: 86948 +/* 84398 */ MCD_OPC_CheckPredicate, 3, 241, 9, 0, // Skip to: 86948 +/* 84403 */ MCD_OPC_CheckField, 10, 2, 1, 234, 9, 0, // Skip to: 86948 +/* 84410 */ MCD_OPC_Decode, 225, 25, 227, 3, // Opcode: SQSHLUh +/* 84415 */ MCD_OPC_FilterValue, 1, 224, 9, 0, // Skip to: 86948 +/* 84420 */ MCD_OPC_CheckPredicate, 3, 219, 9, 0, // Skip to: 86948 +/* 84425 */ MCD_OPC_CheckField, 10, 2, 1, 212, 9, 0, // Skip to: 86948 +/* 84432 */ MCD_OPC_Decode, 226, 25, 228, 3, // Opcode: SQSHLUs +/* 84437 */ MCD_OPC_FilterValue, 7, 84, 0, 0, // Skip to: 84526 +/* 84442 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84445 */ MCD_OPC_FilterValue, 0, 54, 0, 0, // Skip to: 84504 +/* 84450 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 84453 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84482 +/* 84458 */ MCD_OPC_CheckPredicate, 3, 181, 9, 0, // Skip to: 86948 +/* 84463 */ MCD_OPC_CheckField, 19, 1, 1, 174, 9, 0, // Skip to: 86948 +/* 84470 */ MCD_OPC_CheckField, 10, 2, 1, 167, 9, 0, // Skip to: 86948 +/* 84477 */ MCD_OPC_Decode, 158, 33, 226, 3, // Opcode: UQSHLb +/* 84482 */ MCD_OPC_FilterValue, 1, 157, 9, 0, // Skip to: 86948 +/* 84487 */ MCD_OPC_CheckPredicate, 3, 152, 9, 0, // Skip to: 86948 +/* 84492 */ MCD_OPC_CheckField, 10, 2, 1, 145, 9, 0, // Skip to: 86948 +/* 84499 */ MCD_OPC_Decode, 160, 33, 227, 3, // Opcode: UQSHLh +/* 84504 */ MCD_OPC_FilterValue, 1, 135, 9, 0, // Skip to: 86948 +/* 84509 */ MCD_OPC_CheckPredicate, 3, 130, 9, 0, // Skip to: 86948 +/* 84514 */ MCD_OPC_CheckField, 10, 2, 1, 123, 9, 0, // Skip to: 86948 +/* 84521 */ MCD_OPC_Decode, 161, 33, 228, 3, // Opcode: UQSHLs +/* 84526 */ MCD_OPC_FilterValue, 8, 139, 0, 0, // Skip to: 84670 +/* 84531 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 84534 */ MCD_OPC_FilterValue, 1, 63, 0, 0, // Skip to: 84602 +/* 84539 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84542 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84587 +/* 84547 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 84550 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84572 +/* 84555 */ MCD_OPC_CheckPredicate, 3, 84, 9, 0, // Skip to: 86948 +/* 84560 */ MCD_OPC_CheckField, 19, 1, 1, 77, 9, 0, // Skip to: 86948 +/* 84567 */ MCD_OPC_Decode, 137, 26, 230, 3, // Opcode: SQSHRUNb +/* 84572 */ MCD_OPC_FilterValue, 1, 67, 9, 0, // Skip to: 86948 +/* 84577 */ MCD_OPC_CheckPredicate, 3, 62, 9, 0, // Skip to: 86948 +/* 84582 */ MCD_OPC_Decode, 138, 26, 231, 3, // Opcode: SQSHRUNh +/* 84587 */ MCD_OPC_FilterValue, 1, 52, 9, 0, // Skip to: 86948 +/* 84592 */ MCD_OPC_CheckPredicate, 3, 47, 9, 0, // Skip to: 86948 +/* 84597 */ MCD_OPC_Decode, 139, 26, 232, 3, // Opcode: SQSHRUNs +/* 84602 */ MCD_OPC_FilterValue, 3, 37, 9, 0, // Skip to: 86948 +/* 84607 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84610 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84655 +/* 84615 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 84618 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84640 +/* 84623 */ MCD_OPC_CheckPredicate, 3, 16, 9, 0, // Skip to: 86948 +/* 84628 */ MCD_OPC_CheckField, 19, 1, 1, 9, 9, 0, // Skip to: 86948 +/* 84635 */ MCD_OPC_Decode, 214, 25, 230, 3, // Opcode: SQRSHRUNb +/* 84640 */ MCD_OPC_FilterValue, 1, 255, 8, 0, // Skip to: 86948 +/* 84645 */ MCD_OPC_CheckPredicate, 3, 250, 8, 0, // Skip to: 86948 +/* 84650 */ MCD_OPC_Decode, 215, 25, 231, 3, // Opcode: SQRSHRUNh +/* 84655 */ MCD_OPC_FilterValue, 1, 240, 8, 0, // Skip to: 86948 +/* 84660 */ MCD_OPC_CheckPredicate, 3, 235, 8, 0, // Skip to: 86948 +/* 84665 */ MCD_OPC_Decode, 216, 25, 232, 3, // Opcode: SQRSHRUNs +/* 84670 */ MCD_OPC_FilterValue, 9, 162, 0, 0, // Skip to: 84837 +/* 84675 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 84678 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 84693 +/* 84683 */ MCD_OPC_CheckPredicate, 4, 212, 8, 0, // Skip to: 86948 +/* 84688 */ MCD_OPC_Decode, 254, 10, 229, 3, // Opcode: FMULXv1i16_indexed +/* 84693 */ MCD_OPC_FilterValue, 1, 202, 8, 0, // Skip to: 86948 +/* 84698 */ MCD_OPC_ExtractField, 11, 1, // Inst{11} ... +/* 84701 */ MCD_OPC_FilterValue, 0, 63, 0, 0, // Skip to: 84769 +/* 84706 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84709 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84754 +/* 84714 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 84717 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84739 +/* 84722 */ MCD_OPC_CheckPredicate, 3, 173, 8, 0, // Skip to: 86948 +/* 84727 */ MCD_OPC_CheckField, 19, 1, 1, 166, 8, 0, // Skip to: 86948 +/* 84734 */ MCD_OPC_Decode, 180, 33, 230, 3, // Opcode: UQSHRNb +/* 84739 */ MCD_OPC_FilterValue, 1, 156, 8, 0, // Skip to: 86948 +/* 84744 */ MCD_OPC_CheckPredicate, 3, 151, 8, 0, // Skip to: 86948 +/* 84749 */ MCD_OPC_Decode, 181, 33, 231, 3, // Opcode: UQSHRNh +/* 84754 */ MCD_OPC_FilterValue, 1, 141, 8, 0, // Skip to: 86948 +/* 84759 */ MCD_OPC_CheckPredicate, 3, 136, 8, 0, // Skip to: 86948 +/* 84764 */ MCD_OPC_Decode, 182, 33, 232, 3, // Opcode: UQSHRNs +/* 84769 */ MCD_OPC_FilterValue, 1, 126, 8, 0, // Skip to: 86948 +/* 84774 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84777 */ MCD_OPC_FilterValue, 0, 40, 0, 0, // Skip to: 84822 +/* 84782 */ MCD_OPC_ExtractField, 20, 1, // Inst{20} ... +/* 84785 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84807 +/* 84790 */ MCD_OPC_CheckPredicate, 3, 105, 8, 0, // Skip to: 86948 +/* 84795 */ MCD_OPC_CheckField, 19, 1, 1, 98, 8, 0, // Skip to: 86948 +/* 84802 */ MCD_OPC_Decode, 149, 33, 230, 3, // Opcode: UQRSHRNb +/* 84807 */ MCD_OPC_FilterValue, 1, 88, 8, 0, // Skip to: 86948 +/* 84812 */ MCD_OPC_CheckPredicate, 3, 83, 8, 0, // Skip to: 86948 +/* 84817 */ MCD_OPC_Decode, 150, 33, 231, 3, // Opcode: UQRSHRNh +/* 84822 */ MCD_OPC_FilterValue, 1, 73, 8, 0, // Skip to: 86948 +/* 84827 */ MCD_OPC_CheckPredicate, 3, 68, 8, 0, // Skip to: 86948 +/* 84832 */ MCD_OPC_Decode, 151, 33, 232, 3, // Opcode: UQRSHRNs +/* 84837 */ MCD_OPC_FilterValue, 14, 54, 0, 0, // Skip to: 84896 +/* 84842 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84845 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84874 +/* 84850 */ MCD_OPC_CheckPredicate, 4, 45, 8, 0, // Skip to: 86948 +/* 84855 */ MCD_OPC_CheckField, 20, 1, 1, 38, 8, 0, // Skip to: 86948 +/* 84862 */ MCD_OPC_CheckField, 10, 2, 1, 31, 8, 0, // Skip to: 86948 +/* 84869 */ MCD_OPC_Decode, 191, 31, 237, 3, // Opcode: UCVTFh +/* 84874 */ MCD_OPC_FilterValue, 1, 21, 8, 0, // Skip to: 86948 +/* 84879 */ MCD_OPC_CheckPredicate, 3, 16, 8, 0, // Skip to: 86948 +/* 84884 */ MCD_OPC_CheckField, 10, 2, 1, 9, 8, 0, // Skip to: 86948 +/* 84891 */ MCD_OPC_Decode, 192, 31, 238, 3, // Opcode: UCVTFs +/* 84896 */ MCD_OPC_FilterValue, 15, 255, 7, 0, // Skip to: 86948 +/* 84901 */ MCD_OPC_ExtractField, 21, 1, // Inst{21} ... +/* 84904 */ MCD_OPC_FilterValue, 0, 24, 0, 0, // Skip to: 84933 +/* 84909 */ MCD_OPC_CheckPredicate, 4, 242, 7, 0, // Skip to: 86948 +/* 84914 */ MCD_OPC_CheckField, 20, 1, 1, 235, 7, 0, // Skip to: 86948 +/* 84921 */ MCD_OPC_CheckField, 10, 2, 3, 228, 7, 0, // Skip to: 86948 +/* 84928 */ MCD_OPC_Decode, 145, 9, 237, 3, // Opcode: FCVTZUh +/* 84933 */ MCD_OPC_FilterValue, 1, 218, 7, 0, // Skip to: 86948 +/* 84938 */ MCD_OPC_CheckPredicate, 3, 213, 7, 0, // Skip to: 86948 +/* 84943 */ MCD_OPC_CheckField, 10, 2, 3, 206, 7, 0, // Skip to: 86948 +/* 84950 */ MCD_OPC_Decode, 146, 9, 238, 3, // Opcode: FCVTZUs +/* 84955 */ MCD_OPC_FilterValue, 13, 12, 1, 0, // Skip to: 85228 +/* 84960 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 84963 */ MCD_OPC_FilterValue, 0, 17, 0, 0, // Skip to: 84985 +/* 84968 */ MCD_OPC_CheckPredicate, 3, 183, 7, 0, // Skip to: 86948 +/* 84973 */ MCD_OPC_CheckField, 10, 2, 1, 176, 7, 0, // Skip to: 86948 +/* 84980 */ MCD_OPC_Decode, 137, 34, 218, 3, // Opcode: USHRd +/* 84985 */ MCD_OPC_FilterValue, 1, 17, 0, 0, // Skip to: 85007 +/* 84990 */ MCD_OPC_CheckPredicate, 3, 161, 7, 0, // Skip to: 86948 +/* 84995 */ MCD_OPC_CheckField, 10, 2, 1, 154, 7, 0, // Skip to: 86948 +/* 85002 */ MCD_OPC_Decode, 156, 34, 220, 3, // Opcode: USRAd +/* 85007 */ MCD_OPC_FilterValue, 2, 17, 0, 0, // Skip to: 85029 +/* 85012 */ MCD_OPC_CheckPredicate, 3, 139, 7, 0, // Skip to: 86948 +/* 85017 */ MCD_OPC_CheckField, 10, 2, 1, 132, 7, 0, // Skip to: 86948 +/* 85024 */ MCD_OPC_Decode, 233, 33, 218, 3, // Opcode: URSHRd +/* 85029 */ MCD_OPC_FilterValue, 3, 17, 0, 0, // Skip to: 85051 +/* 85034 */ MCD_OPC_CheckPredicate, 3, 117, 7, 0, // Skip to: 86948 +/* 85039 */ MCD_OPC_CheckField, 10, 2, 1, 110, 7, 0, // Skip to: 86948 +/* 85046 */ MCD_OPC_Decode, 243, 33, 220, 3, // Opcode: URSRAd +/* 85051 */ MCD_OPC_FilterValue, 4, 17, 0, 0, // Skip to: 85073 +/* 85056 */ MCD_OPC_CheckPredicate, 3, 95, 7, 0, // Skip to: 86948 +/* 85061 */ MCD_OPC_CheckField, 10, 2, 1, 88, 7, 0, // Skip to: 86948 +/* 85068 */ MCD_OPC_Decode, 189, 26, 220, 3, // Opcode: SRId +/* 85073 */ MCD_OPC_FilterValue, 5, 17, 0, 0, // Skip to: 85095 +/* 85078 */ MCD_OPC_CheckPredicate, 3, 73, 7, 0, // Skip to: 86948 +/* 85083 */ MCD_OPC_CheckField, 10, 2, 1, 66, 7, 0, // Skip to: 86948 +/* 85090 */ MCD_OPC_Decode, 159, 23, 243, 3, // Opcode: SLId +/* 85095 */ MCD_OPC_FilterValue, 6, 17, 0, 0, // Skip to: 85117 +/* 85100 */ MCD_OPC_CheckPredicate, 3, 51, 7, 0, // Skip to: 86948 +/* 85105 */ MCD_OPC_CheckField, 10, 2, 1, 44, 7, 0, // Skip to: 86948 +/* 85112 */ MCD_OPC_Decode, 224, 25, 225, 3, // Opcode: SQSHLUd +/* 85117 */ MCD_OPC_FilterValue, 7, 17, 0, 0, // Skip to: 85139 +/* 85122 */ MCD_OPC_CheckPredicate, 3, 29, 7, 0, // Skip to: 86948 +/* 85127 */ MCD_OPC_CheckField, 10, 2, 1, 22, 7, 0, // Skip to: 86948 +/* 85134 */ MCD_OPC_Decode, 159, 33, 225, 3, // Opcode: UQSHLd +/* 85139 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 85161 +/* 85144 */ MCD_OPC_CheckPredicate, 7, 7, 7, 0, // Skip to: 86948 +/* 85149 */ MCD_OPC_CheckField, 10, 1, 0, 0, 7, 0, // Skip to: 86948 +/* 85156 */ MCD_OPC_Decode, 158, 25, 219, 3, // Opcode: SQRDMLAHi16_indexed +/* 85161 */ MCD_OPC_FilterValue, 14, 17, 0, 0, // Skip to: 85183 +/* 85166 */ MCD_OPC_CheckPredicate, 3, 241, 6, 0, // Skip to: 86948 +/* 85171 */ MCD_OPC_CheckField, 10, 2, 1, 234, 6, 0, // Skip to: 86948 +/* 85178 */ MCD_OPC_Decode, 190, 31, 218, 3, // Opcode: UCVTFd +/* 85183 */ MCD_OPC_FilterValue, 15, 224, 6, 0, // Skip to: 86948 +/* 85188 */ MCD_OPC_ExtractField, 10, 1, // Inst{10} ... +/* 85191 */ MCD_OPC_FilterValue, 0, 10, 0, 0, // Skip to: 85206 +/* 85196 */ MCD_OPC_CheckPredicate, 7, 211, 6, 0, // Skip to: 86948 +/* 85201 */ MCD_OPC_Decode, 170, 25, 219, 3, // Opcode: SQRDMLSHi16_indexed +/* 85206 */ MCD_OPC_FilterValue, 1, 201, 6, 0, // Skip to: 86948 +/* 85211 */ MCD_OPC_CheckPredicate, 3, 196, 6, 0, // Skip to: 86948 +/* 85216 */ MCD_OPC_CheckField, 11, 1, 1, 189, 6, 0, // Skip to: 86948 +/* 85223 */ MCD_OPC_Decode, 144, 9, 218, 3, // Opcode: FCVTZUd +/* 85228 */ MCD_OPC_FilterValue, 14, 69, 0, 0, // Skip to: 85302 +/* 85233 */ MCD_OPC_ExtractField, 12, 4, // Inst{15-12} ... +/* 85236 */ MCD_OPC_FilterValue, 9, 17, 0, 0, // Skip to: 85258 +/* 85241 */ MCD_OPC_CheckPredicate, 3, 166, 6, 0, // Skip to: 86948 +/* 85246 */ MCD_OPC_CheckField, 10, 1, 0, 159, 6, 0, // Skip to: 86948 +/* 85253 */ MCD_OPC_Decode, 255, 10, 233, 3, // Opcode: FMULXv1i32_indexed +/* 85258 */ MCD_OPC_FilterValue, 13, 17, 0, 0, // Skip to: 85280 +/* 85263 */ MCD_OPC_CheckPredicate, 7, 144, 6, 0, // Skip to: 86948 +/* 85268 */ MCD_OPC_CheckField, 10, 1, 0, 137, 6, 0, // Skip to: 86948 +/* 85275 */ MCD_OPC_Decode, 159, 25, 221, 3, // Opcode: SQRDMLAHi32_indexed +/* 85280 */ MCD_OPC_FilterValue, 15, 127, 6, 0, // Skip to: 86948 +/* 85285 */ MCD_OPC_CheckPredicate, 7, 122, 6, 0, // Skip to: 86948 +/* 85290 */ MCD_OPC_CheckField, 10, 1, 0, 115, 6, 0, // Skip to: 86948 +/* 85297 */ MCD_OPC_Decode, 171, 25, 221, 3, // Opcode: SQRDMLSHi32_indexed +/* 85302 */ MCD_OPC_FilterValue, 15, 105, 6, 0, // Skip to: 86948 +/* 85307 */ MCD_OPC_CheckPredicate, 3, 100, 6, 0, // Skip to: 86948 +/* 85312 */ MCD_OPC_CheckField, 21, 1, 0, 93, 6, 0, // Skip to: 86948 +/* 85319 */ MCD_OPC_CheckField, 12, 4, 9, 86, 6, 0, // Skip to: 86948 +/* 85326 */ MCD_OPC_CheckField, 10, 1, 0, 79, 6, 0, // Skip to: 86948 +/* 85333 */ MCD_OPC_Decode, 128, 11, 234, 3, // Opcode: FMULXv1i64_indexed +/* 85338 */ MCD_OPC_FilterValue, 4, 121, 4, 0, // Skip to: 86488 +/* 85343 */ MCD_OPC_ExtractField, 24, 2, // Inst{25-24} ... +/* 85346 */ MCD_OPC_FilterValue, 0, 5, 0, 0, // Skip to: 85356 +/* 85351 */ MCD_OPC_Decode, 245, 17, 244, 3, // Opcode: LDRQl +/* 85356 */ MCD_OPC_FilterValue, 2, 51, 6, 0, // Skip to: 86948 +/* 85361 */ MCD_OPC_ExtractField, 16, 8, // Inst{23-16} ... +/* 85364 */ MCD_OPC_FilterValue, 2, 10, 0, 0, // Skip to: 85379 +/* 85369 */ MCD_OPC_CheckPredicate, 16, 38, 6, 0, // Skip to: 86948 +/* 85374 */ MCD_OPC_Decode, 189, 22, 245, 3, // Opcode: SCVTFSXSri +/* 85379 */ MCD_OPC_FilterValue, 3, 10, 0, 0, // Skip to: 85394 +/* 85384 */ MCD_OPC_CheckPredicate, 16, 23, 6, 0, // Skip to: 86948 +/* 85389 */ MCD_OPC_Decode, 176, 31, 245, 3, // Opcode: UCVTFSXSri +/* 85394 */ MCD_OPC_FilterValue, 24, 10, 0, 0, // Skip to: 85409 +/* 85399 */ MCD_OPC_CheckPredicate, 16, 8, 6, 0, // Skip to: 86948 +/* 85404 */ MCD_OPC_Decode, 223, 8, 246, 3, // Opcode: FCVTZSSXSri +/* 85409 */ MCD_OPC_FilterValue, 25, 10, 0, 0, // Skip to: 85424 +/* 85414 */ MCD_OPC_CheckPredicate, 16, 249, 5, 0, // Skip to: 86948 +/* 85419 */ MCD_OPC_Decode, 130, 9, 246, 3, // Opcode: FCVTZUSXSri +/* 85424 */ MCD_OPC_FilterValue, 32, 17, 0, 0, // Skip to: 85446 +/* 85429 */ MCD_OPC_CheckPredicate, 16, 234, 5, 0, // Skip to: 86948 +/* 85434 */ MCD_OPC_CheckField, 10, 6, 0, 227, 5, 0, // Skip to: 86948 +/* 85441 */ MCD_OPC_Decode, 158, 8, 247, 3, // Opcode: FCVTNSUXSr +/* 85446 */ MCD_OPC_FilterValue, 33, 17, 0, 0, // Skip to: 85468 +/* 85451 */ MCD_OPC_CheckPredicate, 16, 212, 5, 0, // Skip to: 86948 +/* 85456 */ MCD_OPC_CheckField, 10, 6, 0, 205, 5, 0, // Skip to: 86948 +/* 85463 */ MCD_OPC_Decode, 172, 8, 247, 3, // Opcode: FCVTNUUXSr +/* 85468 */ MCD_OPC_FilterValue, 34, 17, 0, 0, // Skip to: 85490 +/* 85473 */ MCD_OPC_CheckPredicate, 16, 190, 5, 0, // Skip to: 86948 +/* 85478 */ MCD_OPC_CheckField, 10, 6, 0, 183, 5, 0, // Skip to: 86948 +/* 85485 */ MCD_OPC_Decode, 195, 22, 248, 3, // Opcode: SCVTFUXSri +/* 85490 */ MCD_OPC_FilterValue, 35, 17, 0, 0, // Skip to: 85512 +/* 85495 */ MCD_OPC_CheckPredicate, 16, 168, 5, 0, // Skip to: 86948 +/* 85500 */ MCD_OPC_CheckField, 10, 6, 0, 161, 5, 0, // Skip to: 86948 +/* 85507 */ MCD_OPC_Decode, 182, 31, 248, 3, // Opcode: UCVTFUXSri +/* 85512 */ MCD_OPC_FilterValue, 36, 17, 0, 0, // Skip to: 85534 +/* 85517 */ MCD_OPC_CheckPredicate, 16, 146, 5, 0, // Skip to: 86948 +/* 85522 */ MCD_OPC_CheckField, 10, 6, 0, 139, 5, 0, // Skip to: 86948 +/* 85529 */ MCD_OPC_Decode, 222, 7, 247, 3, // Opcode: FCVTASUXSr +/* 85534 */ MCD_OPC_FilterValue, 37, 17, 0, 0, // Skip to: 85556 +/* 85539 */ MCD_OPC_CheckPredicate, 16, 124, 5, 0, // Skip to: 86948 +/* 85544 */ MCD_OPC_CheckField, 10, 6, 0, 117, 5, 0, // Skip to: 86948 +/* 85551 */ MCD_OPC_Decode, 236, 7, 247, 3, // Opcode: FCVTAUUXSr +/* 85556 */ MCD_OPC_FilterValue, 40, 17, 0, 0, // Skip to: 85578 +/* 85561 */ MCD_OPC_CheckPredicate, 16, 102, 5, 0, // Skip to: 86948 +/* 85566 */ MCD_OPC_CheckField, 10, 6, 0, 95, 5, 0, // Skip to: 86948 +/* 85573 */ MCD_OPC_Decode, 190, 8, 247, 3, // Opcode: FCVTPSUXSr +/* 85578 */ MCD_OPC_FilterValue, 41, 17, 0, 0, // Skip to: 85600 +/* 85583 */ MCD_OPC_CheckPredicate, 16, 80, 5, 0, // Skip to: 86948 +/* 85588 */ MCD_OPC_CheckField, 10, 6, 0, 73, 5, 0, // Skip to: 86948 +/* 85595 */ MCD_OPC_Decode, 204, 8, 247, 3, // Opcode: FCVTPUUXSr +/* 85600 */ MCD_OPC_FilterValue, 48, 17, 0, 0, // Skip to: 85622 +/* 85605 */ MCD_OPC_CheckPredicate, 16, 58, 5, 0, // Skip to: 86948 +/* 85610 */ MCD_OPC_CheckField, 10, 6, 0, 51, 5, 0, // Skip to: 86948 +/* 85617 */ MCD_OPC_Decode, 130, 8, 247, 3, // Opcode: FCVTMSUXSr +/* 85622 */ MCD_OPC_FilterValue, 49, 17, 0, 0, // Skip to: 85644 +/* 85627 */ MCD_OPC_CheckPredicate, 16, 36, 5, 0, // Skip to: 86948 +/* 85632 */ MCD_OPC_CheckField, 10, 6, 0, 29, 5, 0, // Skip to: 86948 +/* 85639 */ MCD_OPC_Decode, 144, 8, 247, 3, // Opcode: FCVTMUUXSr +/* 85644 */ MCD_OPC_FilterValue, 56, 17, 0, 0, // Skip to: 85666 +/* 85649 */ MCD_OPC_CheckPredicate, 16, 14, 5, 0, // Skip to: 86948 +/* 85654 */ MCD_OPC_CheckField, 10, 6, 0, 7, 5, 0, // Skip to: 86948 +/* 85661 */ MCD_OPC_Decode, 229, 8, 247, 3, // Opcode: FCVTZSUXSr +/* 85666 */ MCD_OPC_FilterValue, 57, 17, 0, 0, // Skip to: 85688 +/* 85671 */ MCD_OPC_CheckPredicate, 16, 248, 4, 0, // Skip to: 86948 +/* 85676 */ MCD_OPC_CheckField, 10, 6, 0, 241, 4, 0, // Skip to: 86948 +/* 85683 */ MCD_OPC_Decode, 136, 9, 247, 3, // Opcode: FCVTZUUXSr +/* 85688 */ MCD_OPC_FilterValue, 66, 10, 0, 0, // Skip to: 85703 +/* 85693 */ MCD_OPC_CheckPredicate, 16, 226, 4, 0, // Skip to: 86948 +/* 85698 */ MCD_OPC_Decode, 187, 22, 249, 3, // Opcode: SCVTFSXDri +/* 85703 */ MCD_OPC_FilterValue, 67, 10, 0, 0, // Skip to: 85718 +/* 85708 */ MCD_OPC_CheckPredicate, 16, 211, 4, 0, // Skip to: 86948 +/* 85713 */ MCD_OPC_Decode, 174, 31, 249, 3, // Opcode: UCVTFSXDri +/* 85718 */ MCD_OPC_FilterValue, 88, 10, 0, 0, // Skip to: 85733 +/* 85723 */ MCD_OPC_CheckPredicate, 16, 196, 4, 0, // Skip to: 86948 +/* 85728 */ MCD_OPC_Decode, 221, 8, 250, 3, // Opcode: FCVTZSSXDri +/* 85733 */ MCD_OPC_FilterValue, 89, 10, 0, 0, // Skip to: 85748 +/* 85738 */ MCD_OPC_CheckPredicate, 16, 181, 4, 0, // Skip to: 86948 +/* 85743 */ MCD_OPC_Decode, 128, 9, 250, 3, // Opcode: FCVTZUSXDri +/* 85748 */ MCD_OPC_FilterValue, 96, 17, 0, 0, // Skip to: 85770 +/* 85753 */ MCD_OPC_CheckPredicate, 16, 166, 4, 0, // Skip to: 86948 +/* 85758 */ MCD_OPC_CheckField, 10, 6, 0, 159, 4, 0, // Skip to: 86948 +/* 85765 */ MCD_OPC_Decode, 156, 8, 251, 3, // Opcode: FCVTNSUXDr +/* 85770 */ MCD_OPC_FilterValue, 97, 17, 0, 0, // Skip to: 85792 +/* 85775 */ MCD_OPC_CheckPredicate, 16, 144, 4, 0, // Skip to: 86948 +/* 85780 */ MCD_OPC_CheckField, 10, 6, 0, 137, 4, 0, // Skip to: 86948 +/* 85787 */ MCD_OPC_Decode, 170, 8, 251, 3, // Opcode: FCVTNUUXDr +/* 85792 */ MCD_OPC_FilterValue, 98, 17, 0, 0, // Skip to: 85814 +/* 85797 */ MCD_OPC_CheckPredicate, 16, 122, 4, 0, // Skip to: 86948 +/* 85802 */ MCD_OPC_CheckField, 10, 6, 0, 115, 4, 0, // Skip to: 86948 +/* 85809 */ MCD_OPC_Decode, 193, 22, 252, 3, // Opcode: SCVTFUXDri +/* 85814 */ MCD_OPC_FilterValue, 99, 17, 0, 0, // Skip to: 85836 +/* 85819 */ MCD_OPC_CheckPredicate, 16, 100, 4, 0, // Skip to: 86948 +/* 85824 */ MCD_OPC_CheckField, 10, 6, 0, 93, 4, 0, // Skip to: 86948 +/* 85831 */ MCD_OPC_Decode, 180, 31, 252, 3, // Opcode: UCVTFUXDri +/* 85836 */ MCD_OPC_FilterValue, 100, 17, 0, 0, // Skip to: 85858 +/* 85841 */ MCD_OPC_CheckPredicate, 16, 78, 4, 0, // Skip to: 86948 +/* 85846 */ MCD_OPC_CheckField, 10, 6, 0, 71, 4, 0, // Skip to: 86948 +/* 85853 */ MCD_OPC_Decode, 220, 7, 251, 3, // Opcode: FCVTASUXDr +/* 85858 */ MCD_OPC_FilterValue, 101, 17, 0, 0, // Skip to: 85880 +/* 85863 */ MCD_OPC_CheckPredicate, 16, 56, 4, 0, // Skip to: 86948 +/* 85868 */ MCD_OPC_CheckField, 10, 6, 0, 49, 4, 0, // Skip to: 86948 +/* 85875 */ MCD_OPC_Decode, 234, 7, 251, 3, // Opcode: FCVTAUUXDr +/* 85880 */ MCD_OPC_FilterValue, 102, 17, 0, 0, // Skip to: 85902 +/* 85885 */ MCD_OPC_CheckPredicate, 16, 34, 4, 0, // Skip to: 86948 +/* 85890 */ MCD_OPC_CheckField, 10, 6, 0, 27, 4, 0, // Skip to: 86948 +/* 85897 */ MCD_OPC_Decode, 217, 10, 251, 3, // Opcode: FMOVDXr +/* 85902 */ MCD_OPC_FilterValue, 103, 17, 0, 0, // Skip to: 85924 +/* 85907 */ MCD_OPC_CheckPredicate, 16, 12, 4, 0, // Skip to: 86948 +/* 85912 */ MCD_OPC_CheckField, 10, 6, 0, 5, 4, 0, // Skip to: 86948 +/* 85919 */ MCD_OPC_Decode, 232, 10, 252, 3, // Opcode: FMOVXDr +/* 85924 */ MCD_OPC_FilterValue, 104, 17, 0, 0, // Skip to: 85946 +/* 85929 */ MCD_OPC_CheckPredicate, 16, 246, 3, 0, // Skip to: 86948 +/* 85934 */ MCD_OPC_CheckField, 10, 6, 0, 239, 3, 0, // Skip to: 86948 +/* 85941 */ MCD_OPC_Decode, 188, 8, 251, 3, // Opcode: FCVTPSUXDr +/* 85946 */ MCD_OPC_FilterValue, 105, 17, 0, 0, // Skip to: 85968 +/* 85951 */ MCD_OPC_CheckPredicate, 16, 224, 3, 0, // Skip to: 86948 +/* 85956 */ MCD_OPC_CheckField, 10, 6, 0, 217, 3, 0, // Skip to: 86948 +/* 85963 */ MCD_OPC_Decode, 202, 8, 251, 3, // Opcode: FCVTPUUXDr +/* 85968 */ MCD_OPC_FilterValue, 112, 17, 0, 0, // Skip to: 85990 +/* 85973 */ MCD_OPC_CheckPredicate, 16, 202, 3, 0, // Skip to: 86948 +/* 85978 */ MCD_OPC_CheckField, 10, 6, 0, 195, 3, 0, // Skip to: 86948 +/* 85985 */ MCD_OPC_Decode, 128, 8, 251, 3, // Opcode: FCVTMSUXDr +/* 85990 */ MCD_OPC_FilterValue, 113, 17, 0, 0, // Skip to: 86012 +/* 85995 */ MCD_OPC_CheckPredicate, 16, 180, 3, 0, // Skip to: 86948 +/* 86000 */ MCD_OPC_CheckField, 10, 6, 0, 173, 3, 0, // Skip to: 86948 +/* 86007 */ MCD_OPC_Decode, 142, 8, 251, 3, // Opcode: FCVTMUUXDr +/* 86012 */ MCD_OPC_FilterValue, 120, 17, 0, 0, // Skip to: 86034 +/* 86017 */ MCD_OPC_CheckPredicate, 16, 158, 3, 0, // Skip to: 86948 +/* 86022 */ MCD_OPC_CheckField, 10, 6, 0, 151, 3, 0, // Skip to: 86948 +/* 86029 */ MCD_OPC_Decode, 227, 8, 251, 3, // Opcode: FCVTZSUXDr +/* 86034 */ MCD_OPC_FilterValue, 121, 17, 0, 0, // Skip to: 86056 +/* 86039 */ MCD_OPC_CheckPredicate, 16, 136, 3, 0, // Skip to: 86948 +/* 86044 */ MCD_OPC_CheckField, 10, 6, 0, 129, 3, 0, // Skip to: 86948 +/* 86051 */ MCD_OPC_Decode, 134, 9, 251, 3, // Opcode: FCVTZUUXDr +/* 86056 */ MCD_OPC_FilterValue, 174, 1, 17, 0, 0, // Skip to: 86079 +/* 86062 */ MCD_OPC_CheckPredicate, 16, 113, 3, 0, // Skip to: 86948 +/* 86067 */ MCD_OPC_CheckField, 10, 6, 0, 106, 3, 0, // Skip to: 86948 +/* 86074 */ MCD_OPC_Decode, 216, 10, 253, 3, // Opcode: FMOVDXHighr +/* 86079 */ MCD_OPC_FilterValue, 175, 1, 17, 0, 0, // Skip to: 86102 +/* 86085 */ MCD_OPC_CheckPredicate, 16, 90, 3, 0, // Skip to: 86948 +/* 86090 */ MCD_OPC_CheckField, 10, 6, 0, 83, 3, 0, // Skip to: 86948 +/* 86097 */ MCD_OPC_Decode, 231, 10, 253, 3, // Opcode: FMOVXDHighr +/* 86102 */ MCD_OPC_FilterValue, 194, 1, 10, 0, 0, // Skip to: 86118 +/* 86108 */ MCD_OPC_CheckPredicate, 18, 67, 3, 0, // Skip to: 86948 +/* 86113 */ MCD_OPC_Decode, 188, 22, 254, 3, // Opcode: SCVTFSXHri +/* 86118 */ MCD_OPC_FilterValue, 195, 1, 10, 0, 0, // Skip to: 86134 +/* 86124 */ MCD_OPC_CheckPredicate, 18, 51, 3, 0, // Skip to: 86948 +/* 86129 */ MCD_OPC_Decode, 175, 31, 254, 3, // Opcode: UCVTFSXHri +/* 86134 */ MCD_OPC_FilterValue, 216, 1, 10, 0, 0, // Skip to: 86150 +/* 86140 */ MCD_OPC_CheckPredicate, 18, 35, 3, 0, // Skip to: 86948 +/* 86145 */ MCD_OPC_Decode, 222, 8, 255, 3, // Opcode: FCVTZSSXHri +/* 86150 */ MCD_OPC_FilterValue, 217, 1, 10, 0, 0, // Skip to: 86166 +/* 86156 */ MCD_OPC_CheckPredicate, 18, 19, 3, 0, // Skip to: 86948 +/* 86161 */ MCD_OPC_Decode, 129, 9, 255, 3, // Opcode: FCVTZUSXHri +/* 86166 */ MCD_OPC_FilterValue, 224, 1, 17, 0, 0, // Skip to: 86189 +/* 86172 */ MCD_OPC_CheckPredicate, 18, 3, 3, 0, // Skip to: 86948 +/* 86177 */ MCD_OPC_CheckField, 10, 6, 0, 252, 2, 0, // Skip to: 86948 +/* 86184 */ MCD_OPC_Decode, 157, 8, 128, 4, // Opcode: FCVTNSUXHr +/* 86189 */ MCD_OPC_FilterValue, 225, 1, 17, 0, 0, // Skip to: 86212 +/* 86195 */ MCD_OPC_CheckPredicate, 18, 236, 2, 0, // Skip to: 86948 +/* 86200 */ MCD_OPC_CheckField, 10, 6, 0, 229, 2, 0, // Skip to: 86948 +/* 86207 */ MCD_OPC_Decode, 171, 8, 128, 4, // Opcode: FCVTNUUXHr +/* 86212 */ MCD_OPC_FilterValue, 226, 1, 17, 0, 0, // Skip to: 86235 +/* 86218 */ MCD_OPC_CheckPredicate, 18, 213, 2, 0, // Skip to: 86948 +/* 86223 */ MCD_OPC_CheckField, 10, 6, 0, 206, 2, 0, // Skip to: 86948 +/* 86230 */ MCD_OPC_Decode, 194, 22, 129, 4, // Opcode: SCVTFUXHri +/* 86235 */ MCD_OPC_FilterValue, 227, 1, 17, 0, 0, // Skip to: 86258 +/* 86241 */ MCD_OPC_CheckPredicate, 18, 190, 2, 0, // Skip to: 86948 +/* 86246 */ MCD_OPC_CheckField, 10, 6, 0, 183, 2, 0, // Skip to: 86948 +/* 86253 */ MCD_OPC_Decode, 181, 31, 129, 4, // Opcode: UCVTFUXHri +/* 86258 */ MCD_OPC_FilterValue, 228, 1, 17, 0, 0, // Skip to: 86281 +/* 86264 */ MCD_OPC_CheckPredicate, 18, 167, 2, 0, // Skip to: 86948 +/* 86269 */ MCD_OPC_CheckField, 10, 6, 0, 160, 2, 0, // Skip to: 86948 +/* 86276 */ MCD_OPC_Decode, 221, 7, 128, 4, // Opcode: FCVTASUXHr +/* 86281 */ MCD_OPC_FilterValue, 229, 1, 17, 0, 0, // Skip to: 86304 +/* 86287 */ MCD_OPC_CheckPredicate, 18, 144, 2, 0, // Skip to: 86948 +/* 86292 */ MCD_OPC_CheckField, 10, 6, 0, 137, 2, 0, // Skip to: 86948 +/* 86299 */ MCD_OPC_Decode, 235, 7, 128, 4, // Opcode: FCVTAUUXHr +/* 86304 */ MCD_OPC_FilterValue, 230, 1, 17, 0, 0, // Skip to: 86327 +/* 86310 */ MCD_OPC_CheckPredicate, 18, 121, 2, 0, // Skip to: 86948 +/* 86315 */ MCD_OPC_CheckField, 10, 6, 0, 114, 2, 0, // Skip to: 86948 +/* 86322 */ MCD_OPC_Decode, 222, 10, 128, 4, // Opcode: FMOVHXr +/* 86327 */ MCD_OPC_FilterValue, 231, 1, 17, 0, 0, // Skip to: 86350 +/* 86333 */ MCD_OPC_CheckPredicate, 18, 98, 2, 0, // Skip to: 86948 +/* 86338 */ MCD_OPC_CheckField, 10, 6, 0, 91, 2, 0, // Skip to: 86948 +/* 86345 */ MCD_OPC_Decode, 233, 10, 129, 4, // Opcode: FMOVXHr +/* 86350 */ MCD_OPC_FilterValue, 232, 1, 17, 0, 0, // Skip to: 86373 +/* 86356 */ MCD_OPC_CheckPredicate, 18, 75, 2, 0, // Skip to: 86948 +/* 86361 */ MCD_OPC_CheckField, 10, 6, 0, 68, 2, 0, // Skip to: 86948 +/* 86368 */ MCD_OPC_Decode, 189, 8, 128, 4, // Opcode: FCVTPSUXHr +/* 86373 */ MCD_OPC_FilterValue, 233, 1, 17, 0, 0, // Skip to: 86396 +/* 86379 */ MCD_OPC_CheckPredicate, 18, 52, 2, 0, // Skip to: 86948 +/* 86384 */ MCD_OPC_CheckField, 10, 6, 0, 45, 2, 0, // Skip to: 86948 +/* 86391 */ MCD_OPC_Decode, 203, 8, 128, 4, // Opcode: FCVTPUUXHr +/* 86396 */ MCD_OPC_FilterValue, 240, 1, 17, 0, 0, // Skip to: 86419 +/* 86402 */ MCD_OPC_CheckPredicate, 18, 29, 2, 0, // Skip to: 86948 +/* 86407 */ MCD_OPC_CheckField, 10, 6, 0, 22, 2, 0, // Skip to: 86948 +/* 86414 */ MCD_OPC_Decode, 129, 8, 128, 4, // Opcode: FCVTMSUXHr +/* 86419 */ MCD_OPC_FilterValue, 241, 1, 17, 0, 0, // Skip to: 86442 +/* 86425 */ MCD_OPC_CheckPredicate, 18, 6, 2, 0, // Skip to: 86948 +/* 86430 */ MCD_OPC_CheckField, 10, 6, 0, 255, 1, 0, // Skip to: 86948 +/* 86437 */ MCD_OPC_Decode, 143, 8, 128, 4, // Opcode: FCVTMUUXHr +/* 86442 */ MCD_OPC_FilterValue, 248, 1, 17, 0, 0, // Skip to: 86465 +/* 86448 */ MCD_OPC_CheckPredicate, 18, 239, 1, 0, // Skip to: 86948 +/* 86453 */ MCD_OPC_CheckField, 10, 6, 0, 232, 1, 0, // Skip to: 86948 +/* 86460 */ MCD_OPC_Decode, 228, 8, 128, 4, // Opcode: FCVTZSUXHr +/* 86465 */ MCD_OPC_FilterValue, 249, 1, 221, 1, 0, // Skip to: 86948 +/* 86471 */ MCD_OPC_CheckPredicate, 18, 216, 1, 0, // Skip to: 86948 +/* 86476 */ MCD_OPC_CheckField, 10, 6, 0, 209, 1, 0, // Skip to: 86948 +/* 86483 */ MCD_OPC_Decode, 135, 9, 128, 4, // Opcode: FCVTZUUXHr +/* 86488 */ MCD_OPC_FilterValue, 5, 225, 0, 0, // Skip to: 86718 +/* 86493 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 86496 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 86597 +/* 86501 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 86504 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86521 +/* 86509 */ MCD_OPC_CheckField, 21, 1, 0, 176, 1, 0, // Skip to: 86948 +/* 86516 */ MCD_OPC_Decode, 202, 29, 255, 2, // Opcode: STURSi +/* 86521 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86538 +/* 86526 */ MCD_OPC_CheckField, 21, 1, 0, 159, 1, 0, // Skip to: 86948 +/* 86533 */ MCD_OPC_Decode, 175, 29, 255, 2, // Opcode: STRSpost +/* 86538 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86580 +/* 86543 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 86546 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86563 +/* 86551 */ MCD_OPC_CheckField, 21, 1, 1, 134, 1, 0, // Skip to: 86948 +/* 86558 */ MCD_OPC_Decode, 177, 29, 130, 4, // Opcode: STRSroW +/* 86563 */ MCD_OPC_FilterValue, 3, 124, 1, 0, // Skip to: 86948 +/* 86568 */ MCD_OPC_CheckField, 21, 1, 1, 117, 1, 0, // Skip to: 86948 +/* 86575 */ MCD_OPC_Decode, 178, 29, 131, 4, // Opcode: STRSroX +/* 86580 */ MCD_OPC_FilterValue, 3, 107, 1, 0, // Skip to: 86948 +/* 86585 */ MCD_OPC_CheckField, 21, 1, 0, 100, 1, 0, // Skip to: 86948 +/* 86592 */ MCD_OPC_Decode, 176, 29, 255, 2, // Opcode: STRSpre +/* 86597 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 86698 +/* 86602 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 86605 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86622 +/* 86610 */ MCD_OPC_CheckField, 21, 1, 0, 75, 1, 0, // Skip to: 86948 +/* 86617 */ MCD_OPC_Decode, 141, 19, 255, 2, // Opcode: LDURSi +/* 86622 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86639 +/* 86627 */ MCD_OPC_CheckField, 21, 1, 0, 58, 1, 0, // Skip to: 86948 +/* 86634 */ MCD_OPC_Decode, 150, 18, 255, 2, // Opcode: LDRSpost +/* 86639 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86681 +/* 86644 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 86647 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86664 +/* 86652 */ MCD_OPC_CheckField, 21, 1, 1, 33, 1, 0, // Skip to: 86948 +/* 86659 */ MCD_OPC_Decode, 152, 18, 130, 4, // Opcode: LDRSroW +/* 86664 */ MCD_OPC_FilterValue, 3, 23, 1, 0, // Skip to: 86948 +/* 86669 */ MCD_OPC_CheckField, 21, 1, 1, 16, 1, 0, // Skip to: 86948 +/* 86676 */ MCD_OPC_Decode, 153, 18, 131, 4, // Opcode: LDRSroX +/* 86681 */ MCD_OPC_FilterValue, 3, 6, 1, 0, // Skip to: 86948 +/* 86686 */ MCD_OPC_CheckField, 21, 1, 0, 255, 0, 0, // Skip to: 86948 +/* 86693 */ MCD_OPC_Decode, 151, 18, 255, 2, // Opcode: LDRSpre +/* 86698 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 86708 +/* 86703 */ MCD_OPC_Decode, 179, 29, 137, 3, // Opcode: STRSui +/* 86708 */ MCD_OPC_FilterValue, 5, 235, 0, 0, // Skip to: 86948 +/* 86713 */ MCD_OPC_Decode, 154, 18, 137, 3, // Opcode: LDRSui +/* 86718 */ MCD_OPC_FilterValue, 7, 225, 0, 0, // Skip to: 86948 +/* 86723 */ MCD_OPC_ExtractField, 22, 4, // Inst{25-22} ... +/* 86726 */ MCD_OPC_FilterValue, 0, 96, 0, 0, // Skip to: 86827 +/* 86731 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 86734 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86751 +/* 86739 */ MCD_OPC_CheckField, 21, 1, 0, 202, 0, 0, // Skip to: 86948 +/* 86746 */ MCD_OPC_Decode, 198, 29, 255, 2, // Opcode: STURDi +/* 86751 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86768 +/* 86756 */ MCD_OPC_CheckField, 21, 1, 0, 185, 0, 0, // Skip to: 86948 +/* 86763 */ MCD_OPC_Decode, 155, 29, 255, 2, // Opcode: STRDpost +/* 86768 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86810 +/* 86773 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 86776 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86793 +/* 86781 */ MCD_OPC_CheckField, 21, 1, 1, 160, 0, 0, // Skip to: 86948 +/* 86788 */ MCD_OPC_Decode, 157, 29, 132, 4, // Opcode: STRDroW +/* 86793 */ MCD_OPC_FilterValue, 3, 150, 0, 0, // Skip to: 86948 +/* 86798 */ MCD_OPC_CheckField, 21, 1, 1, 143, 0, 0, // Skip to: 86948 +/* 86805 */ MCD_OPC_Decode, 158, 29, 133, 4, // Opcode: STRDroX +/* 86810 */ MCD_OPC_FilterValue, 3, 133, 0, 0, // Skip to: 86948 +/* 86815 */ MCD_OPC_CheckField, 21, 1, 0, 126, 0, 0, // Skip to: 86948 +/* 86822 */ MCD_OPC_Decode, 156, 29, 255, 2, // Opcode: STRDpre +/* 86827 */ MCD_OPC_FilterValue, 1, 96, 0, 0, // Skip to: 86928 +/* 86832 */ MCD_OPC_ExtractField, 10, 2, // Inst{11-10} ... +/* 86835 */ MCD_OPC_FilterValue, 0, 12, 0, 0, // Skip to: 86852 +/* 86840 */ MCD_OPC_CheckField, 21, 1, 0, 101, 0, 0, // Skip to: 86948 +/* 86847 */ MCD_OPC_Decode, 132, 19, 255, 2, // Opcode: LDURDi +/* 86852 */ MCD_OPC_FilterValue, 1, 12, 0, 0, // Skip to: 86869 +/* 86857 */ MCD_OPC_CheckField, 21, 1, 0, 84, 0, 0, // Skip to: 86948 +/* 86864 */ MCD_OPC_Decode, 230, 17, 255, 2, // Opcode: LDRDpost +/* 86869 */ MCD_OPC_FilterValue, 2, 37, 0, 0, // Skip to: 86911 +/* 86874 */ MCD_OPC_ExtractField, 13, 2, // Inst{14-13} ... +/* 86877 */ MCD_OPC_FilterValue, 2, 12, 0, 0, // Skip to: 86894 +/* 86882 */ MCD_OPC_CheckField, 21, 1, 1, 59, 0, 0, // Skip to: 86948 +/* 86889 */ MCD_OPC_Decode, 232, 17, 132, 4, // Opcode: LDRDroW +/* 86894 */ MCD_OPC_FilterValue, 3, 49, 0, 0, // Skip to: 86948 +/* 86899 */ MCD_OPC_CheckField, 21, 1, 1, 42, 0, 0, // Skip to: 86948 +/* 86906 */ MCD_OPC_Decode, 233, 17, 133, 4, // Opcode: LDRDroX +/* 86911 */ MCD_OPC_FilterValue, 3, 32, 0, 0, // Skip to: 86948 +/* 86916 */ MCD_OPC_CheckField, 21, 1, 0, 25, 0, 0, // Skip to: 86948 +/* 86923 */ MCD_OPC_Decode, 231, 17, 255, 2, // Opcode: LDRDpre +/* 86928 */ MCD_OPC_FilterValue, 4, 5, 0, 0, // Skip to: 86938 +/* 86933 */ MCD_OPC_Decode, 159, 29, 137, 3, // Opcode: STRDui +/* 86938 */ MCD_OPC_FilterValue, 5, 5, 0, 0, // Skip to: 86948 +/* 86943 */ MCD_OPC_Decode, 234, 17, 137, 3, // Opcode: LDRDui +/* 86948 */ MCD_OPC_Fail, 0 }; -static bool getbool(uint64_t b) -{ - return b != 0; -} - -static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) +static bool checkDecoderPredicate(unsigned Idx, MCInst *MI) { switch (Idx) { - default: // llvm_unreachable("Invalid index!"); + default: /* llvm_unreachable("Invalid index!");*/ case 0: - return getbool((Bits & AArch64_FeatureNEON)); + return (AArch64_getFeatureBits(AArch64_FeatureSVE)); case 1: - return getbool((Bits & AArch64_FeatureCrypto)); + return (AArch64_getFeatureBits(AArch64_FeatureLSE)); case 2: - return getbool((Bits & AArch64_FeatureCRC)); + return (AArch64_getFeatureBits(AArch64_HasV8_1aOps)); case 3: - return getbool((Bits & AArch64_FeatureFPARMv8)); + return (AArch64_getFeatureBits(AArch64_FeatureNEON)); + case 4: + return (AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureFullFP16)); + case 5: + return (AArch64_getFeatureBits(AArch64_FeatureAES)); + case 6: + return (AArch64_getFeatureBits(AArch64_FeatureSHA3)); + case 7: + return (AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureRDM)); + case 8: + return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureNEON) && AArch64_getFeatureBits(AArch64_FeatureFullFP16)); + case 9: + return (AArch64_getFeatureBits(AArch64_FeatureSM4)); + case 10: + return (AArch64_getFeatureBits(AArch64_FeatureDotProd)); + case 11: + return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureNEON)); + case 12: + return (AArch64_getFeatureBits(AArch64_HasV8_4aOps)); + case 13: + return (AArch64_getFeatureBits(AArch64_HasV8_3aOps)); + case 14: + return (AArch64_getFeatureBits(AArch64_FeatureCRC)); + case 15: + return (AArch64_getFeatureBits(AArch64_FeatureRCPC)); + case 16: + return (AArch64_getFeatureBits(AArch64_FeatureFPARMv8)); + case 17: + return (AArch64_getFeatureBits(AArch64_HasV8_3aOps) && AArch64_getFeatureBits(AArch64_FeatureFPARMv8)); + case 18: + return (AArch64_getFeatureBits(AArch64_FeatureFullFP16)); + case 19: + return (AArch64_getFeatureBits(AArch64_FeatureSHA2)); + case 20: + return (AArch64_getFeatureBits(AArch64_FeatureRDM)); } } -#define DecodeToMCInst(fname,fieldname, InsnType) \ +#define DecodeToMCInst(fname, fieldname, InsnType) \ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \ - uint64_t Address, const void *Decoder) \ + uint64_t Address, bool *Decoder) \ { \ InsnType tmp; \ switch (Idx) { \ - default: \ + default: /* llvm_unreachable("Invalid index!");*/ \ case 0: \ - if (!Check(&S, DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 1: \ - if (!Check(&S, DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 2: \ - if (!Check(&S, DecodeAddSubERegInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 3: \ - if (!Check(&S, DecodePairLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 4: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 5: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 6: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 7: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 8: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 9: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 10: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 11: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 12: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 13: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 14: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 15: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 16: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 5, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 17: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSVELogicalImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 18: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 19: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 20: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 21: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 22: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 8); \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ return S; \ case 23: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 24: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 25: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 26: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 27: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 28: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ + tmp |= fieldname(insn, 16, 5) << 3; \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ return S; \ case 29: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 22, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 30: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 20, 1) << 0; \ + tmp |= fieldname(insn, 22, 2) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 31: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 2) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 32: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 18, 3) << 0; \ + tmp |= fieldname(insn, 22, 2) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 33: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 17, 4) << 0; \ + tmp |= fieldname(insn, 22, 2) << 4; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 34: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 35: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 36: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 37: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 38: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 39: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 40: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 41: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 42: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 43: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 44: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 45: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 46: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 47: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 6); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ return S; \ case 48: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 6); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ return S; \ case 49: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 50: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 51: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 52: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 53: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 54: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 55: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 56: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 57: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 58: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 59: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 60: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 61: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 16, 5) << 0; \ + tmp |= fieldname(insn, 22, 1) << 5; \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 62: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 63: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 64: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 65: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 66: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 67: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 68: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 69: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 70: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 71: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 10, 3) << 0; \ - tmp |= fieldname(insn, 30, 1) << 3; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 72: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 73: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 74: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 75: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 2) << 0; \ - tmp |= fieldname(insn, 30, 1) << 2; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 76: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 77: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 78: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 79: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSVEIncDecImm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 80: \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 81: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 30, 1) << 1; \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 82: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 7); \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ return S; \ case 83: \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 30, 1); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 5))) { return MCDisassembler_Fail; } \ return S; \ case 84: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 85: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 86: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 87: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 88: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 89: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 90: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 91: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 92: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 93: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 94: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 95: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 96: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 97: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ return S; \ case 98: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 99: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 8); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 100: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 101: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 8))) { return MCDisassembler_Fail; } \ return S; \ case 102: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 10, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 103: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 104: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 105: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 16))) { return MCDisassembler_Fail; } \ return S; \ case 106: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 8); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 107: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 108: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 109: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 32))) { return MCDisassembler_Fail; } \ return S; \ case 110: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 111: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 112: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 9); \ + if (!Check(&S, DecodeImm8OptLsl(MI, tmp, Address, Decoder, 64))) { return MCDisassembler_Fail; } \ return S; \ case 113: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 114: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 19, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 115: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 116: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 117: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 118: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 19, 2) << 0; \ + tmp |= fieldname(insn, 22, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 119: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 120: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 121: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeZPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 122: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 123: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeZPR_4bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 124: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 125: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 126: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 127: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 128: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ + tmp = fieldname(insn, 0, 4); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 129: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + if (!Check(&S, DecodePPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 16, 6) << 3; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 9))) { return MCDisassembler_Fail; } \ return S; \ case 130: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 6))) { return MCDisassembler_Fail; } \ return S; \ case 131: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 16, 6) << 3; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 9))) { return MCDisassembler_Fail; } \ return S; \ case 132: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 133: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 134: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 135: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 136: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 137: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 138: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPRRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 139: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 140: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPR2RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 14, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 141: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPR3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 142: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPR3RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 143: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeZPR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64commonRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 144: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeZPR4RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 3); \ + if (!Check(&S, DecodePPR_3bRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 4))) { return MCDisassembler_Fail; } \ return S; \ case 145: \ - if (!Check(&S, DecodeModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeExclusiveLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 146: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeWSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 147: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 148: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeThreeAddrSRegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 149: \ - if (!Check(&S, DecodeModImmTiedInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeAddSubERegInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 150: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePairLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 151: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeXSeqPairsClassRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 152: \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 153: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 154: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 155: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 156: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 157: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 158: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 159: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 160: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 161: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 162: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 163: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 164: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeDDRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 165: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 166: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 167: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 168: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 169: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 170: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 171: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 172: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 173: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 174: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 175: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 176: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 177: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 178: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 179: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 180: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 181: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 182: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 183: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 184: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 185: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 186: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 187: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 188: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 189: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 190: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 191: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 192: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 193: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 194: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 195: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 196: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 1); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 197: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 1); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 198: \ - if (!Check(&S, DecodeAdrInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 199: \ - if (!Check(&S, DecodeBaseAddSubImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 200: \ - if (!Check(&S, DecodeLogicalImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 201: \ - if (!Check(&S, DecodeMoveImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 202: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 203: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 204: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 205: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 206: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 207: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 208: \ - if (!Check(&S, DecodeUnconditionalBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 209: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 210: \ - if (!Check(&S, DecodeTestAndBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 211: \ - tmp = fieldname(insn, 0, 4); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 212: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 213: \ - tmp = fieldname(insn, 5, 16); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 214: \ - tmp = fieldname(insn, 8, 4); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 215: \ - tmp = fieldname(insn, 5, 7); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 216: \ - if (!Check(&S, DecodeSystemPStateInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 217: \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 8, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 218: \ - tmp = fieldname(insn, 5, 16); \ - if (!Check(&S, DecodeMSRSystemRegister(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 219: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 8, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 3); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 220: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 16); \ - if (!Check(&S, DecodeMRSSystemRegister(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 10, 3) << 0; \ + tmp |= fieldname(insn, 30, 1) << 3; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 221: \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 222: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 223: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 224: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 2) << 0; \ + tmp |= fieldname(insn, 30, 1) << 2; \ MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 225: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 226: \ - if (!Check(&S, DecodeSignedLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 227: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 228: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 229: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 230: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + tmp |= fieldname(insn, 30, 1) << 1; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 231: \ - if (!Check(&S, DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 232: \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 30, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 233: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 234: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 235: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 236: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 237: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 238: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 239: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 240: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 241: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 242: \ tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 243: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 244: \ tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 245: \ tmp = fieldname(insn, 0, 5); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 246: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 247: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 248: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 249: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 250: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 251: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 252: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 253: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 254: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 255: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 256: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 8); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 257: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 258: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 259: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 260: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 261: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 262: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 263: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 264: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 265: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 13, 8); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 266: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 4); \ - MCOperand_CreateImm0(MI, tmp); \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 267: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 12, 4); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 268: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 269: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 270: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 271: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 10, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 272: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 273: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 274: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 275: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 276: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 277: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 278: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 20, 1); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 279: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 19, 2); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 280: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 18, 3); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 281: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 17, 4); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 282: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 283: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 284: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 285: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeQQQQRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 286: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 287: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 288: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 289: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 14, 1); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 290: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 291: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 3); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 292: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 4); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 293: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 294: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 295: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 296: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 297: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 1); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 298: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 2; \ - tmp |= fieldname(insn, 20, 2) << 0; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 1); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 299: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 2); \ MCOperand_CreateImm0(MI, tmp); \ return S; \ case 300: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 301: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 302: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 303: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ return S; \ case 304: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 3); \ - if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeModImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 305: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 306: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 307: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 11, 1) << 1; \ - tmp |= fieldname(insn, 21, 1) << 0; \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 308: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 11, 1); \ - MCOperand_CreateImm0(MI, tmp); \ + if (!Check(&S, DecodeModImmTiedInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ case 309: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 310: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 311: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 312: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 313: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 314: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 315: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 316: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 317: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 318: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 319: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 320: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 321: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 322: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 323: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 324: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 310: \ + case 325: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 326: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 327: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 328: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 329: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 330: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 331: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 332: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 333: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 334: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 335: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR16ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 336: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR32ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 337: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR64ImmNarrow(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 338: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 339: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 340: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 341: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 342: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 343: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 21, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 344: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 345: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 346: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 347: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 348: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 349: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 1; \ tmp |= fieldname(insn, 21, 1) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 311: \ + case 350: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 351: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 352: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 353: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 354: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 355: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 13, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 356: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 357: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 358: \ + if (!Check(&S, DecodeAdrInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 359: \ + if (!Check(&S, DecodeBaseAddSubImm(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 360: \ + if (!Check(&S, DecodeLogicalImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 361: \ + if (!Check(&S, DecodeMoveImmInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 362: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 363: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 364: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 365: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 366: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 367: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 10, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 368: \ + if (!Check(&S, DecodeUnconditionalBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 369: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 370: \ + if (!Check(&S, DecodeTestAndBranch(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 371: \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 372: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 373: \ + tmp = fieldname(insn, 5, 16); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 374: \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 375: \ + tmp = fieldname(insn, 5, 7); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 376: \ + if (!Check(&S, DecodeSystemPStateInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 377: \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 378: \ + tmp = fieldname(insn, 5, 16); \ + if (!Check(&S, DecodeMSRSystemRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 379: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 8, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 380: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 16); \ + if (!Check(&S, DecodeMRSSystemRegister(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 381: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 382: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 383: \ + if (!Check(&S, DecodeSignedLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 384: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 385: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 386: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 387: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 388: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 389: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 390: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 391: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 392: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 393: \ + if (!Check(&S, DecodeUnsignedLdStInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 394: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 395: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 396: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 397: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 398: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 399: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 400: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 401: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 402: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 403: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 404: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 15, 6); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 405: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 406: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 407: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 408: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 409: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 410: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 411: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 412: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 9) << 0; \ + tmp |= fieldname(insn, 22, 1) << 9; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 10))) { return MCDisassembler_Fail; } \ + return S; \ + case 413: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 9) << 0; \ + tmp |= fieldname(insn, 22, 1) << 9; \ + if (!Check(&S, DecodeSImm(MI, tmp, Address, Decoder, 10))) { return MCDisassembler_Fail; } \ + return S; \ + case 414: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 415: \ + tmp = fieldname(insn, 0, 5); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 416: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 417: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 418: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 419: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 420: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 421: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 422: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 423: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 424: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 425: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 426: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 427: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 428: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 429: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 430: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 431: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 432: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 433: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 434: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 435: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 436: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 437: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 438: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 439: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFixedPointScaleImm32(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 440: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 441: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 442: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 443: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 444: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 445: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 446: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 447: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 13, 8); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 448: \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 449: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 450: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 12, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 451: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 452: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 453: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 454: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 455: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 456: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 457: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 458: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 19); \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 459: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 460: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 20, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 461: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 19, 2); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 462: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 18, 3); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 463: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 17, 4); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 464: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 465: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 466: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 467: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 468: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 469: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 470: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 471: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 472: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 473: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 474: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 475: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 4); \ - if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 11, 1) << 2; \ tmp |= fieldname(insn, 20, 2) << 0; \ MCOperand_CreateImm0(MI, tmp); \ return S; \ - case 312: \ + case 476: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - return S; \ - case 313: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - return S; \ - case 314: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = 0; \ - tmp |= fieldname(insn, 12, 1) << 0; \ - tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - return S; \ - case 315: \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ - tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 6); \ - if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeVecShiftR64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 316: \ + case 477: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 478: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 479: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 480: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 481: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 482: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftL8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 483: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftL16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 484: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftL32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 485: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 486: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR8RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 3); \ + if (!Check(&S, DecodeVecShiftR8Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 487: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 488: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 489: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 490: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 11, 1); \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 491: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeFPR128_loRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 2; \ + tmp |= fieldname(insn, 20, 2) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 492: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 11, 1) << 1; \ + tmp |= fieldname(insn, 21, 1) << 0; \ + MCOperand_CreateImm0(MI, tmp); \ + return S; \ + case 493: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 4); \ + if (!Check(&S, DecodeVecShiftR16Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 494: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeVecShiftR32Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 495: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 496: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = 0; \ + tmp |= fieldname(insn, 12, 1) << 0; \ + tmp |= fieldname(insn, 15, 1) << 1; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 497: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 498: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 499: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 16, 6); \ + if (!Check(&S, DecodeVecShiftL64Imm(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 500: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR128RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 19); \ - if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodePCRelLabel19(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 317: \ + case 501: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 318: \ + case 502: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 319: \ + case 503: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 320: \ + case 504: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 321: \ + case 505: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 322: \ + case 506: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 10, 6); \ - if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 323: \ + case 507: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 324: \ + case 508: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 325: \ - if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \ + case 509: \ + if (!Check(&S, DecodeFMOVLaneInstruction(MI, insn, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 326: \ + case 510: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 511: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 10, 6); \ + if (!Check(&S, DecodeFixedPointScaleImm64(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 512: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 513: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR16RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + return S; \ + case 514: \ + tmp = fieldname(insn, 0, 5); \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ + tmp = fieldname(insn, 5, 5); \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 327: \ + case 515: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 328: \ + case 516: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR32RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ - case 329: \ + case 517: \ tmp = fieldname(insn, 0, 5); \ - if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeFPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 5, 5); \ - if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64spRegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = fieldname(insn, 16, 5); \ - if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeGPR64RegisterClass(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ tmp = 0; \ tmp |= fieldname(insn, 12, 1) << 0; \ tmp |= fieldname(insn, 15, 1) << 1; \ - if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \ + if (!Check(&S, DecodeMemExtend(MI, tmp, Address, Decoder))) { return MCDisassembler_Fail; } \ return S; \ } \ } #define DecodeInstruction(fname, fieldname, decoder, InsnType) \ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ - InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \ + InsnType insn, uint64_t Address) \ { \ - uint64_t Bits = getFeatureBits(feature); \ - const uint8_t *Ptr = DecodeTable; \ - uint32_t CurFieldValue = 0, ExpectedValue; \ - DecodeStatus S = MCDisassembler_Success; \ unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \ InsnType Val, FieldValue, PositiveMask, NegativeMask; \ - bool Pred, Fail; \ - for (;;) { \ + bool Pred, Fail, DecodeComplete = true; \ + uint32_t ExpectedValue; \ + const uint8_t *Ptr = DecodeTable; \ + uint32_t CurFieldValue = 0; \ + DecodeStatus S = MCDisassembler_Success; \ + while (true) { \ switch (*Ptr) { \ default: \ return MCDisassembler_Fail; \ @@ -12677,14 +22450,18 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ Start = *++Ptr; \ Len = *++Ptr; \ ++Ptr; \ - CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \ + CurFieldValue = fieldname(insn, Start, Len); \ break; \ } \ case MCD_OPC_FilterValue: { \ - Val = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the field value. */ \ + Val = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the filter operation. */ \ if (Val != CurFieldValue) \ Ptr += NumToSkip; \ break; \ @@ -12693,37 +22470,75 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ Start = *++Ptr; \ Len = *++Ptr; \ FieldValue = fieldname(insn, Start, Len); \ - ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \ + /* Decode the field value. */ \ + ExpectedValue = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* If the actual and expected values don't match, skip. */ \ if (ExpectedValue != FieldValue) \ Ptr += NumToSkip; \ break; \ } \ case MCD_OPC_CheckPredicate: { \ - PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \ + /* Decode the Predicate Index value. */ \ + PIdx = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ NumToSkip = *Ptr++; \ NumToSkip |= (*Ptr++) << 8; \ - Pred = checkDecoderPredicate(PIdx, Bits); \ - if (!Pred) \ + NumToSkip |= (*Ptr++) << 16; \ + /* Check the predicate. */ \ + if (!(Pred = checkDecoderPredicate(PIdx, MI))) \ Ptr += NumToSkip; \ (void)Pred; \ break; \ } \ case MCD_OPC_Decode: { \ - Opc = (unsigned)decodeULEB128(++Ptr, &Len); \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ + MCInst_clear(MI); \ MCInst_setOpcode(MI, Opc); \ - return decoder(S, DecodeIdx, insn, MI, Address, MRI); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + /* assert(DecodeComplete); */ \ + return S; \ + } \ + case MCD_OPC_TryDecode: { \ + /* Decode the Opcode value. */ \ + Opc = decodeULEB128(++Ptr, &Len); \ + Ptr += Len; \ + DecodeIdx = decodeULEB128(Ptr, &Len); \ + Ptr += Len; \ + /* NumToSkip is a plain 24-bit integer. */ \ + NumToSkip = *Ptr++; \ + NumToSkip |= (*Ptr++) << 8; \ + NumToSkip |= (*Ptr++) << 16; \ + /* Perform the decode operation. */ \ + MCInst_setOpcode(MI, Opc); \ + S = decoder(S, DecodeIdx, insn, MI, Address, &DecodeComplete); \ + if (DecodeComplete) { \ + /* Decoding complete. */ \ + return S; \ + } else { \ + /* assert(S == MCDisassembler_Fail); */ \ + /* If the decoding was incomplete, skip. */ \ + Ptr += NumToSkip; \ + /* Reset decode status. This also drops a SoftFail status that could be */ \ + /* set before the decode attempt. */ \ + S = MCDisassembler_Success; \ + } \ + break; \ } \ case MCD_OPC_SoftFail: { \ - PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \ + /* Decode the mask values. */ \ + PositiveMask = decodeULEB128(++Ptr, &Len); \ Ptr += Len; \ - NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \ + NegativeMask = decodeULEB128(Ptr, &Len); \ Ptr += Len; \ Fail = (insn & PositiveMask) || (~insn & NegativeMask); \ if (Fail) \ @@ -12735,8 +22550,12 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ } \ } \ } \ + /* llvm_unreachable("bogosity detected in disassembler state machine!");*/ \ } -FieldFromInstruction(fieldFromInstruction, uint32_t) -DecodeToMCInst(decodeToMCInst, fieldFromInstruction, uint32_t) -DecodeInstruction(decodeInstruction, fieldFromInstruction, decodeToMCInst, uint32_t) + + +FieldFromInstruction(fieldFromInstruction_4, uint32_t) +DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t) +DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t) + diff --git a/arch/AArch64/AArch64GenInstrInfo.inc b/arch/AArch64/AArch64GenInstrInfo.inc index d3c87b9cf..65c912005 100644 --- a/arch/AArch64/AArch64GenInstrInfo.inc +++ b/arch/AArch64/AArch64GenInstrInfo.inc @@ -1,2411 +1,9478 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Target Instruction Enum Values *| + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Target Instruction Enum Values and Descriptors *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - #ifdef GET_INSTRINFO_ENUM #undef GET_INSTRINFO_ENUM enum { - AArch64_PHI = 0, - AArch64_INLINEASM = 1, - AArch64_CFI_INSTRUCTION = 2, - AArch64_EH_LABEL = 3, - AArch64_GC_LABEL = 4, - AArch64_KILL = 5, - AArch64_EXTRACT_SUBREG = 6, - AArch64_INSERT_SUBREG = 7, - AArch64_IMPLICIT_DEF = 8, - AArch64_SUBREG_TO_REG = 9, - AArch64_COPY_TO_REGCLASS = 10, - AArch64_DBG_VALUE = 11, - AArch64_REG_SEQUENCE = 12, - AArch64_COPY = 13, - AArch64_BUNDLE = 14, - AArch64_LIFETIME_START = 15, - AArch64_LIFETIME_END = 16, - AArch64_STACKMAP = 17, - AArch64_PATCHPOINT = 18, - AArch64_LOAD_STACK_GUARD = 19, - AArch64_STATEPOINT = 20, - AArch64_FRAME_ALLOC = 21, - AArch64_ABSv16i8 = 22, - AArch64_ABSv1i64 = 23, - AArch64_ABSv2i32 = 24, - AArch64_ABSv2i64 = 25, - AArch64_ABSv4i16 = 26, - AArch64_ABSv4i32 = 27, - AArch64_ABSv8i16 = 28, - AArch64_ABSv8i8 = 29, - AArch64_ADCSWr = 30, - AArch64_ADCSXr = 31, - AArch64_ADCWr = 32, - AArch64_ADCXr = 33, - AArch64_ADDHNv2i64_v2i32 = 34, - AArch64_ADDHNv2i64_v4i32 = 35, - AArch64_ADDHNv4i32_v4i16 = 36, - AArch64_ADDHNv4i32_v8i16 = 37, - AArch64_ADDHNv8i16_v16i8 = 38, - AArch64_ADDHNv8i16_v8i8 = 39, - AArch64_ADDPv16i8 = 40, - AArch64_ADDPv2i32 = 41, - AArch64_ADDPv2i64 = 42, - AArch64_ADDPv2i64p = 43, - AArch64_ADDPv4i16 = 44, - AArch64_ADDPv4i32 = 45, - AArch64_ADDPv8i16 = 46, - AArch64_ADDPv8i8 = 47, - AArch64_ADDSWri = 48, - AArch64_ADDSWrr = 49, - AArch64_ADDSWrs = 50, - AArch64_ADDSWrx = 51, - AArch64_ADDSXri = 52, - AArch64_ADDSXrr = 53, - AArch64_ADDSXrs = 54, - AArch64_ADDSXrx = 55, - AArch64_ADDSXrx64 = 56, - AArch64_ADDVv16i8v = 57, - AArch64_ADDVv4i16v = 58, - AArch64_ADDVv4i32v = 59, - AArch64_ADDVv8i16v = 60, - AArch64_ADDVv8i8v = 61, - AArch64_ADDWri = 62, - AArch64_ADDWrr = 63, - AArch64_ADDWrs = 64, - AArch64_ADDWrx = 65, - AArch64_ADDXri = 66, - AArch64_ADDXrr = 67, - AArch64_ADDXrs = 68, - AArch64_ADDXrx = 69, - AArch64_ADDXrx64 = 70, - AArch64_ADDv16i8 = 71, - AArch64_ADDv1i64 = 72, - AArch64_ADDv2i32 = 73, - AArch64_ADDv2i64 = 74, - AArch64_ADDv4i16 = 75, - AArch64_ADDv4i32 = 76, - AArch64_ADDv8i16 = 77, - AArch64_ADDv8i8 = 78, - AArch64_ADJCALLSTACKDOWN = 79, - AArch64_ADJCALLSTACKUP = 80, - AArch64_ADR = 81, - AArch64_ADRP = 82, - AArch64_AESDrr = 83, - AArch64_AESErr = 84, - AArch64_AESIMCrr = 85, - AArch64_AESMCrr = 86, - AArch64_ANDSWri = 87, - AArch64_ANDSWrr = 88, - AArch64_ANDSWrs = 89, - AArch64_ANDSXri = 90, - AArch64_ANDSXrr = 91, - AArch64_ANDSXrs = 92, - AArch64_ANDWri = 93, - AArch64_ANDWrr = 94, - AArch64_ANDWrs = 95, - AArch64_ANDXri = 96, - AArch64_ANDXrr = 97, - AArch64_ANDXrs = 98, - AArch64_ANDv16i8 = 99, - AArch64_ANDv8i8 = 100, - AArch64_ASRVWr = 101, - AArch64_ASRVXr = 102, - AArch64_B = 103, - AArch64_BFMWri = 104, - AArch64_BFMXri = 105, - AArch64_BICSWrr = 106, - AArch64_BICSWrs = 107, - AArch64_BICSXrr = 108, - AArch64_BICSXrs = 109, - AArch64_BICWrr = 110, - AArch64_BICWrs = 111, - AArch64_BICXrr = 112, - AArch64_BICXrs = 113, - AArch64_BICv16i8 = 114, - AArch64_BICv2i32 = 115, - AArch64_BICv4i16 = 116, - AArch64_BICv4i32 = 117, - AArch64_BICv8i16 = 118, - AArch64_BICv8i8 = 119, - AArch64_BIFv16i8 = 120, - AArch64_BIFv8i8 = 121, - AArch64_BITv16i8 = 122, - AArch64_BITv8i8 = 123, - AArch64_BL = 124, - AArch64_BLR = 125, - AArch64_BR = 126, - AArch64_BRK = 127, - AArch64_BSLv16i8 = 128, - AArch64_BSLv8i8 = 129, - AArch64_Bcc = 130, - AArch64_CBNZW = 131, - AArch64_CBNZX = 132, - AArch64_CBZW = 133, - AArch64_CBZX = 134, - AArch64_CCMNWi = 135, - AArch64_CCMNWr = 136, - AArch64_CCMNXi = 137, - AArch64_CCMNXr = 138, - AArch64_CCMPWi = 139, - AArch64_CCMPWr = 140, - AArch64_CCMPXi = 141, - AArch64_CCMPXr = 142, - AArch64_CLREX = 143, - AArch64_CLSWr = 144, - AArch64_CLSXr = 145, - AArch64_CLSv16i8 = 146, - AArch64_CLSv2i32 = 147, - AArch64_CLSv4i16 = 148, - AArch64_CLSv4i32 = 149, - AArch64_CLSv8i16 = 150, - AArch64_CLSv8i8 = 151, - AArch64_CLZWr = 152, - AArch64_CLZXr = 153, - AArch64_CLZv16i8 = 154, - AArch64_CLZv2i32 = 155, - AArch64_CLZv4i16 = 156, - AArch64_CLZv4i32 = 157, - AArch64_CLZv8i16 = 158, - AArch64_CLZv8i8 = 159, - AArch64_CMEQv16i8 = 160, - AArch64_CMEQv16i8rz = 161, - AArch64_CMEQv1i64 = 162, - AArch64_CMEQv1i64rz = 163, - AArch64_CMEQv2i32 = 164, - AArch64_CMEQv2i32rz = 165, - AArch64_CMEQv2i64 = 166, - AArch64_CMEQv2i64rz = 167, - AArch64_CMEQv4i16 = 168, - AArch64_CMEQv4i16rz = 169, - AArch64_CMEQv4i32 = 170, - AArch64_CMEQv4i32rz = 171, - AArch64_CMEQv8i16 = 172, - AArch64_CMEQv8i16rz = 173, - AArch64_CMEQv8i8 = 174, - AArch64_CMEQv8i8rz = 175, - AArch64_CMGEv16i8 = 176, - AArch64_CMGEv16i8rz = 177, - AArch64_CMGEv1i64 = 178, - AArch64_CMGEv1i64rz = 179, - AArch64_CMGEv2i32 = 180, - AArch64_CMGEv2i32rz = 181, - AArch64_CMGEv2i64 = 182, - AArch64_CMGEv2i64rz = 183, - AArch64_CMGEv4i16 = 184, - AArch64_CMGEv4i16rz = 185, - AArch64_CMGEv4i32 = 186, - AArch64_CMGEv4i32rz = 187, - AArch64_CMGEv8i16 = 188, - AArch64_CMGEv8i16rz = 189, - AArch64_CMGEv8i8 = 190, - AArch64_CMGEv8i8rz = 191, - AArch64_CMGTv16i8 = 192, - AArch64_CMGTv16i8rz = 193, - AArch64_CMGTv1i64 = 194, - AArch64_CMGTv1i64rz = 195, - AArch64_CMGTv2i32 = 196, - AArch64_CMGTv2i32rz = 197, - AArch64_CMGTv2i64 = 198, - AArch64_CMGTv2i64rz = 199, - AArch64_CMGTv4i16 = 200, - AArch64_CMGTv4i16rz = 201, - AArch64_CMGTv4i32 = 202, - AArch64_CMGTv4i32rz = 203, - AArch64_CMGTv8i16 = 204, - AArch64_CMGTv8i16rz = 205, - AArch64_CMGTv8i8 = 206, - AArch64_CMGTv8i8rz = 207, - AArch64_CMHIv16i8 = 208, - AArch64_CMHIv1i64 = 209, - AArch64_CMHIv2i32 = 210, - AArch64_CMHIv2i64 = 211, - AArch64_CMHIv4i16 = 212, - AArch64_CMHIv4i32 = 213, - AArch64_CMHIv8i16 = 214, - AArch64_CMHIv8i8 = 215, - AArch64_CMHSv16i8 = 216, - AArch64_CMHSv1i64 = 217, - AArch64_CMHSv2i32 = 218, - AArch64_CMHSv2i64 = 219, - AArch64_CMHSv4i16 = 220, - AArch64_CMHSv4i32 = 221, - AArch64_CMHSv8i16 = 222, - AArch64_CMHSv8i8 = 223, - AArch64_CMLEv16i8rz = 224, - AArch64_CMLEv1i64rz = 225, - AArch64_CMLEv2i32rz = 226, - AArch64_CMLEv2i64rz = 227, - AArch64_CMLEv4i16rz = 228, - AArch64_CMLEv4i32rz = 229, - AArch64_CMLEv8i16rz = 230, - AArch64_CMLEv8i8rz = 231, - AArch64_CMLTv16i8rz = 232, - AArch64_CMLTv1i64rz = 233, - AArch64_CMLTv2i32rz = 234, - AArch64_CMLTv2i64rz = 235, - AArch64_CMLTv4i16rz = 236, - AArch64_CMLTv4i32rz = 237, - AArch64_CMLTv8i16rz = 238, - AArch64_CMLTv8i8rz = 239, - AArch64_CMTSTv16i8 = 240, - AArch64_CMTSTv1i64 = 241, - AArch64_CMTSTv2i32 = 242, - AArch64_CMTSTv2i64 = 243, - AArch64_CMTSTv4i16 = 244, - AArch64_CMTSTv4i32 = 245, - AArch64_CMTSTv8i16 = 246, - AArch64_CMTSTv8i8 = 247, - AArch64_CNTv16i8 = 248, - AArch64_CNTv8i8 = 249, - AArch64_CPYi16 = 250, - AArch64_CPYi32 = 251, - AArch64_CPYi64 = 252, - AArch64_CPYi8 = 253, - AArch64_CRC32Brr = 254, - AArch64_CRC32CBrr = 255, - AArch64_CRC32CHrr = 256, - AArch64_CRC32CWrr = 257, - AArch64_CRC32CXrr = 258, - AArch64_CRC32Hrr = 259, - AArch64_CRC32Wrr = 260, - AArch64_CRC32Xrr = 261, - AArch64_CSELWr = 262, - AArch64_CSELXr = 263, - AArch64_CSINCWr = 264, - AArch64_CSINCXr = 265, - AArch64_CSINVWr = 266, - AArch64_CSINVXr = 267, - AArch64_CSNEGWr = 268, - AArch64_CSNEGXr = 269, - AArch64_DCPS1 = 270, - AArch64_DCPS2 = 271, - AArch64_DCPS3 = 272, - AArch64_DMB = 273, - AArch64_DRPS = 274, - AArch64_DSB = 275, - AArch64_DUPv16i8gpr = 276, - AArch64_DUPv16i8lane = 277, - AArch64_DUPv2i32gpr = 278, - AArch64_DUPv2i32lane = 279, - AArch64_DUPv2i64gpr = 280, - AArch64_DUPv2i64lane = 281, - AArch64_DUPv4i16gpr = 282, - AArch64_DUPv4i16lane = 283, - AArch64_DUPv4i32gpr = 284, - AArch64_DUPv4i32lane = 285, - AArch64_DUPv8i16gpr = 286, - AArch64_DUPv8i16lane = 287, - AArch64_DUPv8i8gpr = 288, - AArch64_DUPv8i8lane = 289, - AArch64_EONWrr = 290, - AArch64_EONWrs = 291, - AArch64_EONXrr = 292, - AArch64_EONXrs = 293, - AArch64_EORWri = 294, - AArch64_EORWrr = 295, - AArch64_EORWrs = 296, - AArch64_EORXri = 297, - AArch64_EORXrr = 298, - AArch64_EORXrs = 299, - AArch64_EORv16i8 = 300, - AArch64_EORv8i8 = 301, - AArch64_ERET = 302, - AArch64_EXTRWrri = 303, - AArch64_EXTRXrri = 304, - AArch64_EXTv16i8 = 305, - AArch64_EXTv8i8 = 306, - AArch64_F128CSEL = 307, - AArch64_FABD32 = 308, - AArch64_FABD64 = 309, - AArch64_FABDv2f32 = 310, - AArch64_FABDv2f64 = 311, - AArch64_FABDv4f32 = 312, - AArch64_FABSDr = 313, - AArch64_FABSSr = 314, - AArch64_FABSv2f32 = 315, - AArch64_FABSv2f64 = 316, - AArch64_FABSv4f32 = 317, - AArch64_FACGE32 = 318, - AArch64_FACGE64 = 319, - AArch64_FACGEv2f32 = 320, - AArch64_FACGEv2f64 = 321, - AArch64_FACGEv4f32 = 322, - AArch64_FACGT32 = 323, - AArch64_FACGT64 = 324, - AArch64_FACGTv2f32 = 325, - AArch64_FACGTv2f64 = 326, - AArch64_FACGTv4f32 = 327, - AArch64_FADDDrr = 328, - AArch64_FADDPv2f32 = 329, - AArch64_FADDPv2f64 = 330, - AArch64_FADDPv2i32p = 331, - AArch64_FADDPv2i64p = 332, - AArch64_FADDPv4f32 = 333, - AArch64_FADDSrr = 334, - AArch64_FADDv2f32 = 335, - AArch64_FADDv2f64 = 336, - AArch64_FADDv4f32 = 337, - AArch64_FCCMPDrr = 338, - AArch64_FCCMPEDrr = 339, - AArch64_FCCMPESrr = 340, - AArch64_FCCMPSrr = 341, - AArch64_FCMEQ32 = 342, - AArch64_FCMEQ64 = 343, - AArch64_FCMEQv1i32rz = 344, - AArch64_FCMEQv1i64rz = 345, - AArch64_FCMEQv2f32 = 346, - AArch64_FCMEQv2f64 = 347, - AArch64_FCMEQv2i32rz = 348, - AArch64_FCMEQv2i64rz = 349, - AArch64_FCMEQv4f32 = 350, - AArch64_FCMEQv4i32rz = 351, - AArch64_FCMGE32 = 352, - AArch64_FCMGE64 = 353, - AArch64_FCMGEv1i32rz = 354, - AArch64_FCMGEv1i64rz = 355, - AArch64_FCMGEv2f32 = 356, - AArch64_FCMGEv2f64 = 357, - AArch64_FCMGEv2i32rz = 358, - AArch64_FCMGEv2i64rz = 359, - AArch64_FCMGEv4f32 = 360, - AArch64_FCMGEv4i32rz = 361, - AArch64_FCMGT32 = 362, - AArch64_FCMGT64 = 363, - AArch64_FCMGTv1i32rz = 364, - AArch64_FCMGTv1i64rz = 365, - AArch64_FCMGTv2f32 = 366, - AArch64_FCMGTv2f64 = 367, - AArch64_FCMGTv2i32rz = 368, - AArch64_FCMGTv2i64rz = 369, - AArch64_FCMGTv4f32 = 370, - AArch64_FCMGTv4i32rz = 371, - AArch64_FCMLEv1i32rz = 372, - AArch64_FCMLEv1i64rz = 373, - AArch64_FCMLEv2i32rz = 374, - AArch64_FCMLEv2i64rz = 375, - AArch64_FCMLEv4i32rz = 376, - AArch64_FCMLTv1i32rz = 377, - AArch64_FCMLTv1i64rz = 378, - AArch64_FCMLTv2i32rz = 379, - AArch64_FCMLTv2i64rz = 380, - AArch64_FCMLTv4i32rz = 381, - AArch64_FCMPDri = 382, - AArch64_FCMPDrr = 383, - AArch64_FCMPEDri = 384, - AArch64_FCMPEDrr = 385, - AArch64_FCMPESri = 386, - AArch64_FCMPESrr = 387, - AArch64_FCMPSri = 388, - AArch64_FCMPSrr = 389, - AArch64_FCSELDrrr = 390, - AArch64_FCSELSrrr = 391, - AArch64_FCVTASUWDr = 392, - AArch64_FCVTASUWSr = 393, - AArch64_FCVTASUXDr = 394, - AArch64_FCVTASUXSr = 395, - AArch64_FCVTASv1i32 = 396, - AArch64_FCVTASv1i64 = 397, - AArch64_FCVTASv2f32 = 398, - AArch64_FCVTASv2f64 = 399, - AArch64_FCVTASv4f32 = 400, - AArch64_FCVTAUUWDr = 401, - AArch64_FCVTAUUWSr = 402, - AArch64_FCVTAUUXDr = 403, - AArch64_FCVTAUUXSr = 404, - AArch64_FCVTAUv1i32 = 405, - AArch64_FCVTAUv1i64 = 406, - AArch64_FCVTAUv2f32 = 407, - AArch64_FCVTAUv2f64 = 408, - AArch64_FCVTAUv4f32 = 409, - AArch64_FCVTDHr = 410, - AArch64_FCVTDSr = 411, - AArch64_FCVTHDr = 412, - AArch64_FCVTHSr = 413, - AArch64_FCVTLv2i32 = 414, - AArch64_FCVTLv4i16 = 415, - AArch64_FCVTLv4i32 = 416, - AArch64_FCVTLv8i16 = 417, - AArch64_FCVTMSUWDr = 418, - AArch64_FCVTMSUWSr = 419, - AArch64_FCVTMSUXDr = 420, - AArch64_FCVTMSUXSr = 421, - AArch64_FCVTMSv1i32 = 422, - AArch64_FCVTMSv1i64 = 423, - AArch64_FCVTMSv2f32 = 424, - AArch64_FCVTMSv2f64 = 425, - AArch64_FCVTMSv4f32 = 426, - AArch64_FCVTMUUWDr = 427, - AArch64_FCVTMUUWSr = 428, - AArch64_FCVTMUUXDr = 429, - AArch64_FCVTMUUXSr = 430, - AArch64_FCVTMUv1i32 = 431, - AArch64_FCVTMUv1i64 = 432, - AArch64_FCVTMUv2f32 = 433, - AArch64_FCVTMUv2f64 = 434, - AArch64_FCVTMUv4f32 = 435, - AArch64_FCVTNSUWDr = 436, - AArch64_FCVTNSUWSr = 437, - AArch64_FCVTNSUXDr = 438, - AArch64_FCVTNSUXSr = 439, - AArch64_FCVTNSv1i32 = 440, - AArch64_FCVTNSv1i64 = 441, - AArch64_FCVTNSv2f32 = 442, - AArch64_FCVTNSv2f64 = 443, - AArch64_FCVTNSv4f32 = 444, - AArch64_FCVTNUUWDr = 445, - AArch64_FCVTNUUWSr = 446, - AArch64_FCVTNUUXDr = 447, - AArch64_FCVTNUUXSr = 448, - AArch64_FCVTNUv1i32 = 449, - AArch64_FCVTNUv1i64 = 450, - AArch64_FCVTNUv2f32 = 451, - AArch64_FCVTNUv2f64 = 452, - AArch64_FCVTNUv4f32 = 453, - AArch64_FCVTNv2i32 = 454, - AArch64_FCVTNv4i16 = 455, - AArch64_FCVTNv4i32 = 456, - AArch64_FCVTNv8i16 = 457, - AArch64_FCVTPSUWDr = 458, - AArch64_FCVTPSUWSr = 459, - AArch64_FCVTPSUXDr = 460, - AArch64_FCVTPSUXSr = 461, - AArch64_FCVTPSv1i32 = 462, - AArch64_FCVTPSv1i64 = 463, - AArch64_FCVTPSv2f32 = 464, - AArch64_FCVTPSv2f64 = 465, - AArch64_FCVTPSv4f32 = 466, - AArch64_FCVTPUUWDr = 467, - AArch64_FCVTPUUWSr = 468, - AArch64_FCVTPUUXDr = 469, - AArch64_FCVTPUUXSr = 470, - AArch64_FCVTPUv1i32 = 471, - AArch64_FCVTPUv1i64 = 472, - AArch64_FCVTPUv2f32 = 473, - AArch64_FCVTPUv2f64 = 474, - AArch64_FCVTPUv4f32 = 475, - AArch64_FCVTSDr = 476, - AArch64_FCVTSHr = 477, - AArch64_FCVTXNv1i64 = 478, - AArch64_FCVTXNv2f32 = 479, - AArch64_FCVTXNv4f32 = 480, - AArch64_FCVTZSSWDri = 481, - AArch64_FCVTZSSWSri = 482, - AArch64_FCVTZSSXDri = 483, - AArch64_FCVTZSSXSri = 484, - AArch64_FCVTZSUWDr = 485, - AArch64_FCVTZSUWSr = 486, - AArch64_FCVTZSUXDr = 487, - AArch64_FCVTZSUXSr = 488, - AArch64_FCVTZS_IntSWDri = 489, - AArch64_FCVTZS_IntSWSri = 490, - AArch64_FCVTZS_IntSXDri = 491, - AArch64_FCVTZS_IntSXSri = 492, - AArch64_FCVTZS_IntUWDr = 493, - AArch64_FCVTZS_IntUWSr = 494, - AArch64_FCVTZS_IntUXDr = 495, - AArch64_FCVTZS_IntUXSr = 496, - AArch64_FCVTZS_Intv2f32 = 497, - AArch64_FCVTZS_Intv2f64 = 498, - AArch64_FCVTZS_Intv4f32 = 499, - AArch64_FCVTZSd = 500, - AArch64_FCVTZSs = 501, - AArch64_FCVTZSv1i32 = 502, - AArch64_FCVTZSv1i64 = 503, - AArch64_FCVTZSv2f32 = 504, - AArch64_FCVTZSv2f64 = 505, - AArch64_FCVTZSv2i32_shift = 506, - AArch64_FCVTZSv2i64_shift = 507, - AArch64_FCVTZSv4f32 = 508, - AArch64_FCVTZSv4i32_shift = 509, - AArch64_FCVTZUSWDri = 510, - AArch64_FCVTZUSWSri = 511, - AArch64_FCVTZUSXDri = 512, - AArch64_FCVTZUSXSri = 513, - AArch64_FCVTZUUWDr = 514, - AArch64_FCVTZUUWSr = 515, - AArch64_FCVTZUUXDr = 516, - AArch64_FCVTZUUXSr = 517, - AArch64_FCVTZU_IntSWDri = 518, - AArch64_FCVTZU_IntSWSri = 519, - AArch64_FCVTZU_IntSXDri = 520, - AArch64_FCVTZU_IntSXSri = 521, - AArch64_FCVTZU_IntUWDr = 522, - AArch64_FCVTZU_IntUWSr = 523, - AArch64_FCVTZU_IntUXDr = 524, - AArch64_FCVTZU_IntUXSr = 525, - AArch64_FCVTZU_Intv2f32 = 526, - AArch64_FCVTZU_Intv2f64 = 527, - AArch64_FCVTZU_Intv4f32 = 528, - AArch64_FCVTZUd = 529, - AArch64_FCVTZUs = 530, - AArch64_FCVTZUv1i32 = 531, - AArch64_FCVTZUv1i64 = 532, - AArch64_FCVTZUv2f32 = 533, - AArch64_FCVTZUv2f64 = 534, - AArch64_FCVTZUv2i32_shift = 535, - AArch64_FCVTZUv2i64_shift = 536, - AArch64_FCVTZUv4f32 = 537, - AArch64_FCVTZUv4i32_shift = 538, - AArch64_FDIVDrr = 539, - AArch64_FDIVSrr = 540, - AArch64_FDIVv2f32 = 541, - AArch64_FDIVv2f64 = 542, - AArch64_FDIVv4f32 = 543, - AArch64_FMADDDrrr = 544, - AArch64_FMADDSrrr = 545, - AArch64_FMAXDrr = 546, - AArch64_FMAXNMDrr = 547, - AArch64_FMAXNMPv2f32 = 548, - AArch64_FMAXNMPv2f64 = 549, - AArch64_FMAXNMPv2i32p = 550, - AArch64_FMAXNMPv2i64p = 551, - AArch64_FMAXNMPv4f32 = 552, - AArch64_FMAXNMSrr = 553, - AArch64_FMAXNMVv4i32v = 554, - AArch64_FMAXNMv2f32 = 555, - AArch64_FMAXNMv2f64 = 556, - AArch64_FMAXNMv4f32 = 557, - AArch64_FMAXPv2f32 = 558, - AArch64_FMAXPv2f64 = 559, - AArch64_FMAXPv2i32p = 560, - AArch64_FMAXPv2i64p = 561, - AArch64_FMAXPv4f32 = 562, - AArch64_FMAXSrr = 563, - AArch64_FMAXVv4i32v = 564, - AArch64_FMAXv2f32 = 565, - AArch64_FMAXv2f64 = 566, - AArch64_FMAXv4f32 = 567, - AArch64_FMINDrr = 568, - AArch64_FMINNMDrr = 569, - AArch64_FMINNMPv2f32 = 570, - AArch64_FMINNMPv2f64 = 571, - AArch64_FMINNMPv2i32p = 572, - AArch64_FMINNMPv2i64p = 573, - AArch64_FMINNMPv4f32 = 574, - AArch64_FMINNMSrr = 575, - AArch64_FMINNMVv4i32v = 576, - AArch64_FMINNMv2f32 = 577, - AArch64_FMINNMv2f64 = 578, - AArch64_FMINNMv4f32 = 579, - AArch64_FMINPv2f32 = 580, - AArch64_FMINPv2f64 = 581, - AArch64_FMINPv2i32p = 582, - AArch64_FMINPv2i64p = 583, - AArch64_FMINPv4f32 = 584, - AArch64_FMINSrr = 585, - AArch64_FMINVv4i32v = 586, - AArch64_FMINv2f32 = 587, - AArch64_FMINv2f64 = 588, - AArch64_FMINv4f32 = 589, - AArch64_FMLAv1i32_indexed = 590, - AArch64_FMLAv1i64_indexed = 591, - AArch64_FMLAv2f32 = 592, - AArch64_FMLAv2f64 = 593, - AArch64_FMLAv2i32_indexed = 594, - AArch64_FMLAv2i64_indexed = 595, - AArch64_FMLAv4f32 = 596, - AArch64_FMLAv4i32_indexed = 597, - AArch64_FMLSv1i32_indexed = 598, - AArch64_FMLSv1i64_indexed = 599, - AArch64_FMLSv2f32 = 600, - AArch64_FMLSv2f64 = 601, - AArch64_FMLSv2i32_indexed = 602, - AArch64_FMLSv2i64_indexed = 603, - AArch64_FMLSv4f32 = 604, - AArch64_FMLSv4i32_indexed = 605, - AArch64_FMOVDXHighr = 606, - AArch64_FMOVDXr = 607, - AArch64_FMOVDi = 608, - AArch64_FMOVDr = 609, - AArch64_FMOVSWr = 610, - AArch64_FMOVSi = 611, - AArch64_FMOVSr = 612, - AArch64_FMOVWSr = 613, - AArch64_FMOVXDHighr = 614, - AArch64_FMOVXDr = 615, - AArch64_FMOVv2f32_ns = 616, - AArch64_FMOVv2f64_ns = 617, - AArch64_FMOVv4f32_ns = 618, - AArch64_FMSUBDrrr = 619, - AArch64_FMSUBSrrr = 620, - AArch64_FMULDrr = 621, - AArch64_FMULSrr = 622, - AArch64_FMULX32 = 623, - AArch64_FMULX64 = 624, - AArch64_FMULXv1i32_indexed = 625, - AArch64_FMULXv1i64_indexed = 626, - AArch64_FMULXv2f32 = 627, - AArch64_FMULXv2f64 = 628, - AArch64_FMULXv2i32_indexed = 629, - AArch64_FMULXv2i64_indexed = 630, - AArch64_FMULXv4f32 = 631, - AArch64_FMULXv4i32_indexed = 632, - AArch64_FMULv1i32_indexed = 633, - AArch64_FMULv1i64_indexed = 634, - AArch64_FMULv2f32 = 635, - AArch64_FMULv2f64 = 636, - AArch64_FMULv2i32_indexed = 637, - AArch64_FMULv2i64_indexed = 638, - AArch64_FMULv4f32 = 639, - AArch64_FMULv4i32_indexed = 640, - AArch64_FNEGDr = 641, - AArch64_FNEGSr = 642, - AArch64_FNEGv2f32 = 643, - AArch64_FNEGv2f64 = 644, - AArch64_FNEGv4f32 = 645, - AArch64_FNMADDDrrr = 646, - AArch64_FNMADDSrrr = 647, - AArch64_FNMSUBDrrr = 648, - AArch64_FNMSUBSrrr = 649, - AArch64_FNMULDrr = 650, - AArch64_FNMULSrr = 651, - AArch64_FRECPEv1i32 = 652, - AArch64_FRECPEv1i64 = 653, - AArch64_FRECPEv2f32 = 654, - AArch64_FRECPEv2f64 = 655, - AArch64_FRECPEv4f32 = 656, - AArch64_FRECPS32 = 657, - AArch64_FRECPS64 = 658, - AArch64_FRECPSv2f32 = 659, - AArch64_FRECPSv2f64 = 660, - AArch64_FRECPSv4f32 = 661, - AArch64_FRECPXv1i32 = 662, - AArch64_FRECPXv1i64 = 663, - AArch64_FRINTADr = 664, - AArch64_FRINTASr = 665, - AArch64_FRINTAv2f32 = 666, - AArch64_FRINTAv2f64 = 667, - AArch64_FRINTAv4f32 = 668, - AArch64_FRINTIDr = 669, - AArch64_FRINTISr = 670, - AArch64_FRINTIv2f32 = 671, - AArch64_FRINTIv2f64 = 672, - AArch64_FRINTIv4f32 = 673, - AArch64_FRINTMDr = 674, - AArch64_FRINTMSr = 675, - AArch64_FRINTMv2f32 = 676, - AArch64_FRINTMv2f64 = 677, - AArch64_FRINTMv4f32 = 678, - AArch64_FRINTNDr = 679, - AArch64_FRINTNSr = 680, - AArch64_FRINTNv2f32 = 681, - AArch64_FRINTNv2f64 = 682, - AArch64_FRINTNv4f32 = 683, - AArch64_FRINTPDr = 684, - AArch64_FRINTPSr = 685, - AArch64_FRINTPv2f32 = 686, - AArch64_FRINTPv2f64 = 687, - AArch64_FRINTPv4f32 = 688, - AArch64_FRINTXDr = 689, - AArch64_FRINTXSr = 690, - AArch64_FRINTXv2f32 = 691, - AArch64_FRINTXv2f64 = 692, - AArch64_FRINTXv4f32 = 693, - AArch64_FRINTZDr = 694, - AArch64_FRINTZSr = 695, - AArch64_FRINTZv2f32 = 696, - AArch64_FRINTZv2f64 = 697, - AArch64_FRINTZv4f32 = 698, - AArch64_FRSQRTEv1i32 = 699, - AArch64_FRSQRTEv1i64 = 700, - AArch64_FRSQRTEv2f32 = 701, - AArch64_FRSQRTEv2f64 = 702, - AArch64_FRSQRTEv4f32 = 703, - AArch64_FRSQRTS32 = 704, - AArch64_FRSQRTS64 = 705, - AArch64_FRSQRTSv2f32 = 706, - AArch64_FRSQRTSv2f64 = 707, - AArch64_FRSQRTSv4f32 = 708, - AArch64_FSQRTDr = 709, - AArch64_FSQRTSr = 710, - AArch64_FSQRTv2f32 = 711, - AArch64_FSQRTv2f64 = 712, - AArch64_FSQRTv4f32 = 713, - AArch64_FSUBDrr = 714, - AArch64_FSUBSrr = 715, - AArch64_FSUBv2f32 = 716, - AArch64_FSUBv2f64 = 717, - AArch64_FSUBv4f32 = 718, - AArch64_HINT = 719, - AArch64_HLT = 720, - AArch64_HVC = 721, - AArch64_INSvi16gpr = 722, - AArch64_INSvi16lane = 723, - AArch64_INSvi32gpr = 724, - AArch64_INSvi32lane = 725, - AArch64_INSvi64gpr = 726, - AArch64_INSvi64lane = 727, - AArch64_INSvi8gpr = 728, - AArch64_INSvi8lane = 729, - AArch64_ISB = 730, - AArch64_LD1Fourv16b = 731, - AArch64_LD1Fourv16b_POST = 732, - AArch64_LD1Fourv1d = 733, - AArch64_LD1Fourv1d_POST = 734, - AArch64_LD1Fourv2d = 735, - AArch64_LD1Fourv2d_POST = 736, - AArch64_LD1Fourv2s = 737, - AArch64_LD1Fourv2s_POST = 738, - AArch64_LD1Fourv4h = 739, - AArch64_LD1Fourv4h_POST = 740, - AArch64_LD1Fourv4s = 741, - AArch64_LD1Fourv4s_POST = 742, - AArch64_LD1Fourv8b = 743, - AArch64_LD1Fourv8b_POST = 744, - AArch64_LD1Fourv8h = 745, - AArch64_LD1Fourv8h_POST = 746, - AArch64_LD1Onev16b = 747, - AArch64_LD1Onev16b_POST = 748, - AArch64_LD1Onev1d = 749, - AArch64_LD1Onev1d_POST = 750, - AArch64_LD1Onev2d = 751, - AArch64_LD1Onev2d_POST = 752, - AArch64_LD1Onev2s = 753, - AArch64_LD1Onev2s_POST = 754, - AArch64_LD1Onev4h = 755, - AArch64_LD1Onev4h_POST = 756, - AArch64_LD1Onev4s = 757, - AArch64_LD1Onev4s_POST = 758, - AArch64_LD1Onev8b = 759, - AArch64_LD1Onev8b_POST = 760, - AArch64_LD1Onev8h = 761, - AArch64_LD1Onev8h_POST = 762, - AArch64_LD1Rv16b = 763, - AArch64_LD1Rv16b_POST = 764, - AArch64_LD1Rv1d = 765, - AArch64_LD1Rv1d_POST = 766, - AArch64_LD1Rv2d = 767, - AArch64_LD1Rv2d_POST = 768, - AArch64_LD1Rv2s = 769, - AArch64_LD1Rv2s_POST = 770, - AArch64_LD1Rv4h = 771, - AArch64_LD1Rv4h_POST = 772, - AArch64_LD1Rv4s = 773, - AArch64_LD1Rv4s_POST = 774, - AArch64_LD1Rv8b = 775, - AArch64_LD1Rv8b_POST = 776, - AArch64_LD1Rv8h = 777, - AArch64_LD1Rv8h_POST = 778, - AArch64_LD1Threev16b = 779, - AArch64_LD1Threev16b_POST = 780, - AArch64_LD1Threev1d = 781, - AArch64_LD1Threev1d_POST = 782, - AArch64_LD1Threev2d = 783, - AArch64_LD1Threev2d_POST = 784, - AArch64_LD1Threev2s = 785, - AArch64_LD1Threev2s_POST = 786, - AArch64_LD1Threev4h = 787, - AArch64_LD1Threev4h_POST = 788, - AArch64_LD1Threev4s = 789, - AArch64_LD1Threev4s_POST = 790, - AArch64_LD1Threev8b = 791, - AArch64_LD1Threev8b_POST = 792, - AArch64_LD1Threev8h = 793, - AArch64_LD1Threev8h_POST = 794, - AArch64_LD1Twov16b = 795, - AArch64_LD1Twov16b_POST = 796, - AArch64_LD1Twov1d = 797, - AArch64_LD1Twov1d_POST = 798, - AArch64_LD1Twov2d = 799, - AArch64_LD1Twov2d_POST = 800, - AArch64_LD1Twov2s = 801, - AArch64_LD1Twov2s_POST = 802, - AArch64_LD1Twov4h = 803, - AArch64_LD1Twov4h_POST = 804, - AArch64_LD1Twov4s = 805, - AArch64_LD1Twov4s_POST = 806, - AArch64_LD1Twov8b = 807, - AArch64_LD1Twov8b_POST = 808, - AArch64_LD1Twov8h = 809, - AArch64_LD1Twov8h_POST = 810, - AArch64_LD1i16 = 811, - AArch64_LD1i16_POST = 812, - AArch64_LD1i32 = 813, - AArch64_LD1i32_POST = 814, - AArch64_LD1i64 = 815, - AArch64_LD1i64_POST = 816, - AArch64_LD1i8 = 817, - AArch64_LD1i8_POST = 818, - AArch64_LD2Rv16b = 819, - AArch64_LD2Rv16b_POST = 820, - AArch64_LD2Rv1d = 821, - AArch64_LD2Rv1d_POST = 822, - AArch64_LD2Rv2d = 823, - AArch64_LD2Rv2d_POST = 824, - AArch64_LD2Rv2s = 825, - AArch64_LD2Rv2s_POST = 826, - AArch64_LD2Rv4h = 827, - AArch64_LD2Rv4h_POST = 828, - AArch64_LD2Rv4s = 829, - AArch64_LD2Rv4s_POST = 830, - AArch64_LD2Rv8b = 831, - AArch64_LD2Rv8b_POST = 832, - AArch64_LD2Rv8h = 833, - AArch64_LD2Rv8h_POST = 834, - AArch64_LD2Twov16b = 835, - AArch64_LD2Twov16b_POST = 836, - AArch64_LD2Twov2d = 837, - AArch64_LD2Twov2d_POST = 838, - AArch64_LD2Twov2s = 839, - AArch64_LD2Twov2s_POST = 840, - AArch64_LD2Twov4h = 841, - AArch64_LD2Twov4h_POST = 842, - AArch64_LD2Twov4s = 843, - AArch64_LD2Twov4s_POST = 844, - AArch64_LD2Twov8b = 845, - AArch64_LD2Twov8b_POST = 846, - AArch64_LD2Twov8h = 847, - AArch64_LD2Twov8h_POST = 848, - AArch64_LD2i16 = 849, - AArch64_LD2i16_POST = 850, - AArch64_LD2i32 = 851, - AArch64_LD2i32_POST = 852, - AArch64_LD2i64 = 853, - AArch64_LD2i64_POST = 854, - AArch64_LD2i8 = 855, - AArch64_LD2i8_POST = 856, - AArch64_LD3Rv16b = 857, - AArch64_LD3Rv16b_POST = 858, - AArch64_LD3Rv1d = 859, - AArch64_LD3Rv1d_POST = 860, - AArch64_LD3Rv2d = 861, - AArch64_LD3Rv2d_POST = 862, - AArch64_LD3Rv2s = 863, - AArch64_LD3Rv2s_POST = 864, - AArch64_LD3Rv4h = 865, - AArch64_LD3Rv4h_POST = 866, - AArch64_LD3Rv4s = 867, - AArch64_LD3Rv4s_POST = 868, - AArch64_LD3Rv8b = 869, - AArch64_LD3Rv8b_POST = 870, - AArch64_LD3Rv8h = 871, - AArch64_LD3Rv8h_POST = 872, - AArch64_LD3Threev16b = 873, - AArch64_LD3Threev16b_POST = 874, - AArch64_LD3Threev2d = 875, - AArch64_LD3Threev2d_POST = 876, - AArch64_LD3Threev2s = 877, - AArch64_LD3Threev2s_POST = 878, - AArch64_LD3Threev4h = 879, - AArch64_LD3Threev4h_POST = 880, - AArch64_LD3Threev4s = 881, - AArch64_LD3Threev4s_POST = 882, - AArch64_LD3Threev8b = 883, - AArch64_LD3Threev8b_POST = 884, - AArch64_LD3Threev8h = 885, - AArch64_LD3Threev8h_POST = 886, - AArch64_LD3i16 = 887, - AArch64_LD3i16_POST = 888, - AArch64_LD3i32 = 889, - AArch64_LD3i32_POST = 890, - AArch64_LD3i64 = 891, - AArch64_LD3i64_POST = 892, - AArch64_LD3i8 = 893, - AArch64_LD3i8_POST = 894, - AArch64_LD4Fourv16b = 895, - AArch64_LD4Fourv16b_POST = 896, - AArch64_LD4Fourv2d = 897, - AArch64_LD4Fourv2d_POST = 898, - AArch64_LD4Fourv2s = 899, - AArch64_LD4Fourv2s_POST = 900, - AArch64_LD4Fourv4h = 901, - AArch64_LD4Fourv4h_POST = 902, - AArch64_LD4Fourv4s = 903, - AArch64_LD4Fourv4s_POST = 904, - AArch64_LD4Fourv8b = 905, - AArch64_LD4Fourv8b_POST = 906, - AArch64_LD4Fourv8h = 907, - AArch64_LD4Fourv8h_POST = 908, - AArch64_LD4Rv16b = 909, - AArch64_LD4Rv16b_POST = 910, - AArch64_LD4Rv1d = 911, - AArch64_LD4Rv1d_POST = 912, - AArch64_LD4Rv2d = 913, - AArch64_LD4Rv2d_POST = 914, - AArch64_LD4Rv2s = 915, - AArch64_LD4Rv2s_POST = 916, - AArch64_LD4Rv4h = 917, - AArch64_LD4Rv4h_POST = 918, - AArch64_LD4Rv4s = 919, - AArch64_LD4Rv4s_POST = 920, - AArch64_LD4Rv8b = 921, - AArch64_LD4Rv8b_POST = 922, - AArch64_LD4Rv8h = 923, - AArch64_LD4Rv8h_POST = 924, - AArch64_LD4i16 = 925, - AArch64_LD4i16_POST = 926, - AArch64_LD4i32 = 927, - AArch64_LD4i32_POST = 928, - AArch64_LD4i64 = 929, - AArch64_LD4i64_POST = 930, - AArch64_LD4i8 = 931, - AArch64_LD4i8_POST = 932, - AArch64_LDARB = 933, - AArch64_LDARH = 934, - AArch64_LDARW = 935, - AArch64_LDARX = 936, - AArch64_LDAXPW = 937, - AArch64_LDAXPX = 938, - AArch64_LDAXRB = 939, - AArch64_LDAXRH = 940, - AArch64_LDAXRW = 941, - AArch64_LDAXRX = 942, - AArch64_LDNPDi = 943, - AArch64_LDNPQi = 944, - AArch64_LDNPSi = 945, - AArch64_LDNPWi = 946, - AArch64_LDNPXi = 947, - AArch64_LDPDi = 948, - AArch64_LDPDpost = 949, - AArch64_LDPDpre = 950, - AArch64_LDPQi = 951, - AArch64_LDPQpost = 952, - AArch64_LDPQpre = 953, - AArch64_LDPSWi = 954, - AArch64_LDPSWpost = 955, - AArch64_LDPSWpre = 956, - AArch64_LDPSi = 957, - AArch64_LDPSpost = 958, - AArch64_LDPSpre = 959, - AArch64_LDPWi = 960, - AArch64_LDPWpost = 961, - AArch64_LDPWpre = 962, - AArch64_LDPXi = 963, - AArch64_LDPXpost = 964, - AArch64_LDPXpre = 965, - AArch64_LDRBBpost = 966, - AArch64_LDRBBpre = 967, - AArch64_LDRBBroW = 968, - AArch64_LDRBBroX = 969, - AArch64_LDRBBui = 970, - AArch64_LDRBpost = 971, - AArch64_LDRBpre = 972, - AArch64_LDRBroW = 973, - AArch64_LDRBroX = 974, - AArch64_LDRBui = 975, - AArch64_LDRDl = 976, - AArch64_LDRDpost = 977, - AArch64_LDRDpre = 978, - AArch64_LDRDroW = 979, - AArch64_LDRDroX = 980, - AArch64_LDRDui = 981, - AArch64_LDRHHpost = 982, - AArch64_LDRHHpre = 983, - AArch64_LDRHHroW = 984, - AArch64_LDRHHroX = 985, - AArch64_LDRHHui = 986, - AArch64_LDRHpost = 987, - AArch64_LDRHpre = 988, - AArch64_LDRHroW = 989, - AArch64_LDRHroX = 990, - AArch64_LDRHui = 991, - AArch64_LDRQl = 992, - AArch64_LDRQpost = 993, - AArch64_LDRQpre = 994, - AArch64_LDRQroW = 995, - AArch64_LDRQroX = 996, - AArch64_LDRQui = 997, - AArch64_LDRSBWpost = 998, - AArch64_LDRSBWpre = 999, - AArch64_LDRSBWroW = 1000, - AArch64_LDRSBWroX = 1001, - AArch64_LDRSBWui = 1002, - AArch64_LDRSBXpost = 1003, - AArch64_LDRSBXpre = 1004, - AArch64_LDRSBXroW = 1005, - AArch64_LDRSBXroX = 1006, - AArch64_LDRSBXui = 1007, - AArch64_LDRSHWpost = 1008, - AArch64_LDRSHWpre = 1009, - AArch64_LDRSHWroW = 1010, - AArch64_LDRSHWroX = 1011, - AArch64_LDRSHWui = 1012, - AArch64_LDRSHXpost = 1013, - AArch64_LDRSHXpre = 1014, - AArch64_LDRSHXroW = 1015, - AArch64_LDRSHXroX = 1016, - AArch64_LDRSHXui = 1017, - AArch64_LDRSWl = 1018, - AArch64_LDRSWpost = 1019, - AArch64_LDRSWpre = 1020, - AArch64_LDRSWroW = 1021, - AArch64_LDRSWroX = 1022, - AArch64_LDRSWui = 1023, - AArch64_LDRSl = 1024, - AArch64_LDRSpost = 1025, - AArch64_LDRSpre = 1026, - AArch64_LDRSroW = 1027, - AArch64_LDRSroX = 1028, - AArch64_LDRSui = 1029, - AArch64_LDRWl = 1030, - AArch64_LDRWpost = 1031, - AArch64_LDRWpre = 1032, - AArch64_LDRWroW = 1033, - AArch64_LDRWroX = 1034, - AArch64_LDRWui = 1035, - AArch64_LDRXl = 1036, - AArch64_LDRXpost = 1037, - AArch64_LDRXpre = 1038, - AArch64_LDRXroW = 1039, - AArch64_LDRXroX = 1040, - AArch64_LDRXui = 1041, - AArch64_LDTRBi = 1042, - AArch64_LDTRHi = 1043, - AArch64_LDTRSBWi = 1044, - AArch64_LDTRSBXi = 1045, - AArch64_LDTRSHWi = 1046, - AArch64_LDTRSHXi = 1047, - AArch64_LDTRSWi = 1048, - AArch64_LDTRWi = 1049, - AArch64_LDTRXi = 1050, - AArch64_LDURBBi = 1051, - AArch64_LDURBi = 1052, - AArch64_LDURDi = 1053, - AArch64_LDURHHi = 1054, - AArch64_LDURHi = 1055, - AArch64_LDURQi = 1056, - AArch64_LDURSBWi = 1057, - AArch64_LDURSBXi = 1058, - AArch64_LDURSHWi = 1059, - AArch64_LDURSHXi = 1060, - AArch64_LDURSWi = 1061, - AArch64_LDURSi = 1062, - AArch64_LDURWi = 1063, - AArch64_LDURXi = 1064, - AArch64_LDXPW = 1065, - AArch64_LDXPX = 1066, - AArch64_LDXRB = 1067, - AArch64_LDXRH = 1068, - AArch64_LDXRW = 1069, - AArch64_LDXRX = 1070, - AArch64_LOADgot = 1071, - AArch64_LSLVWr = 1072, - AArch64_LSLVXr = 1073, - AArch64_LSRVWr = 1074, - AArch64_LSRVXr = 1075, - AArch64_MADDWrrr = 1076, - AArch64_MADDXrrr = 1077, - AArch64_MLAv16i8 = 1078, - AArch64_MLAv2i32 = 1079, - AArch64_MLAv2i32_indexed = 1080, - AArch64_MLAv4i16 = 1081, - AArch64_MLAv4i16_indexed = 1082, - AArch64_MLAv4i32 = 1083, - AArch64_MLAv4i32_indexed = 1084, - AArch64_MLAv8i16 = 1085, - AArch64_MLAv8i16_indexed = 1086, - AArch64_MLAv8i8 = 1087, - AArch64_MLSv16i8 = 1088, - AArch64_MLSv2i32 = 1089, - AArch64_MLSv2i32_indexed = 1090, - AArch64_MLSv4i16 = 1091, - AArch64_MLSv4i16_indexed = 1092, - AArch64_MLSv4i32 = 1093, - AArch64_MLSv4i32_indexed = 1094, - AArch64_MLSv8i16 = 1095, - AArch64_MLSv8i16_indexed = 1096, - AArch64_MLSv8i8 = 1097, - AArch64_MOVID = 1098, - AArch64_MOVIv16b_ns = 1099, - AArch64_MOVIv2d_ns = 1100, - AArch64_MOVIv2i32 = 1101, - AArch64_MOVIv2s_msl = 1102, - AArch64_MOVIv4i16 = 1103, - AArch64_MOVIv4i32 = 1104, - AArch64_MOVIv4s_msl = 1105, - AArch64_MOVIv8b_ns = 1106, - AArch64_MOVIv8i16 = 1107, - AArch64_MOVKWi = 1108, - AArch64_MOVKXi = 1109, - AArch64_MOVNWi = 1110, - AArch64_MOVNXi = 1111, - AArch64_MOVZWi = 1112, - AArch64_MOVZXi = 1113, - AArch64_MOVaddr = 1114, - AArch64_MOVaddrBA = 1115, - AArch64_MOVaddrCP = 1116, - AArch64_MOVaddrEXT = 1117, - AArch64_MOVaddrJT = 1118, - AArch64_MOVaddrTLS = 1119, - AArch64_MOVi32imm = 1120, - AArch64_MOVi64imm = 1121, - AArch64_MRS = 1122, - AArch64_MSR = 1123, - AArch64_MSRpstate = 1124, - AArch64_MSUBWrrr = 1125, - AArch64_MSUBXrrr = 1126, - AArch64_MULv16i8 = 1127, - AArch64_MULv2i32 = 1128, - AArch64_MULv2i32_indexed = 1129, - AArch64_MULv4i16 = 1130, - AArch64_MULv4i16_indexed = 1131, - AArch64_MULv4i32 = 1132, - AArch64_MULv4i32_indexed = 1133, - AArch64_MULv8i16 = 1134, - AArch64_MULv8i16_indexed = 1135, - AArch64_MULv8i8 = 1136, - AArch64_MVNIv2i32 = 1137, - AArch64_MVNIv2s_msl = 1138, - AArch64_MVNIv4i16 = 1139, - AArch64_MVNIv4i32 = 1140, - AArch64_MVNIv4s_msl = 1141, - AArch64_MVNIv8i16 = 1142, - AArch64_NEGv16i8 = 1143, - AArch64_NEGv1i64 = 1144, - AArch64_NEGv2i32 = 1145, - AArch64_NEGv2i64 = 1146, - AArch64_NEGv4i16 = 1147, - AArch64_NEGv4i32 = 1148, - AArch64_NEGv8i16 = 1149, - AArch64_NEGv8i8 = 1150, - AArch64_NOTv16i8 = 1151, - AArch64_NOTv8i8 = 1152, - AArch64_ORNWrr = 1153, - AArch64_ORNWrs = 1154, - AArch64_ORNXrr = 1155, - AArch64_ORNXrs = 1156, - AArch64_ORNv16i8 = 1157, - AArch64_ORNv8i8 = 1158, - AArch64_ORRWri = 1159, - AArch64_ORRWrr = 1160, - AArch64_ORRWrs = 1161, - AArch64_ORRXri = 1162, - AArch64_ORRXrr = 1163, - AArch64_ORRXrs = 1164, - AArch64_ORRv16i8 = 1165, - AArch64_ORRv2i32 = 1166, - AArch64_ORRv4i16 = 1167, - AArch64_ORRv4i32 = 1168, - AArch64_ORRv8i16 = 1169, - AArch64_ORRv8i8 = 1170, - AArch64_PMULLv16i8 = 1171, - AArch64_PMULLv1i64 = 1172, - AArch64_PMULLv2i64 = 1173, - AArch64_PMULLv8i8 = 1174, - AArch64_PMULv16i8 = 1175, - AArch64_PMULv8i8 = 1176, - AArch64_PRFMl = 1177, - AArch64_PRFMroW = 1178, - AArch64_PRFMroX = 1179, - AArch64_PRFMui = 1180, - AArch64_PRFUMi = 1181, - AArch64_RADDHNv2i64_v2i32 = 1182, - AArch64_RADDHNv2i64_v4i32 = 1183, - AArch64_RADDHNv4i32_v4i16 = 1184, - AArch64_RADDHNv4i32_v8i16 = 1185, - AArch64_RADDHNv8i16_v16i8 = 1186, - AArch64_RADDHNv8i16_v8i8 = 1187, - AArch64_RBITWr = 1188, - AArch64_RBITXr = 1189, - AArch64_RBITv16i8 = 1190, - AArch64_RBITv8i8 = 1191, - AArch64_RET = 1192, - AArch64_RET_ReallyLR = 1193, - AArch64_REV16Wr = 1194, - AArch64_REV16Xr = 1195, - AArch64_REV16v16i8 = 1196, - AArch64_REV16v8i8 = 1197, - AArch64_REV32Xr = 1198, - AArch64_REV32v16i8 = 1199, - AArch64_REV32v4i16 = 1200, - AArch64_REV32v8i16 = 1201, - AArch64_REV32v8i8 = 1202, - AArch64_REV64v16i8 = 1203, - AArch64_REV64v2i32 = 1204, - AArch64_REV64v4i16 = 1205, - AArch64_REV64v4i32 = 1206, - AArch64_REV64v8i16 = 1207, - AArch64_REV64v8i8 = 1208, - AArch64_REVWr = 1209, - AArch64_REVXr = 1210, - AArch64_RORVWr = 1211, - AArch64_RORVXr = 1212, - AArch64_RSHRNv16i8_shift = 1213, - AArch64_RSHRNv2i32_shift = 1214, - AArch64_RSHRNv4i16_shift = 1215, - AArch64_RSHRNv4i32_shift = 1216, - AArch64_RSHRNv8i16_shift = 1217, - AArch64_RSHRNv8i8_shift = 1218, - AArch64_RSUBHNv2i64_v2i32 = 1219, - AArch64_RSUBHNv2i64_v4i32 = 1220, - AArch64_RSUBHNv4i32_v4i16 = 1221, - AArch64_RSUBHNv4i32_v8i16 = 1222, - AArch64_RSUBHNv8i16_v16i8 = 1223, - AArch64_RSUBHNv8i16_v8i8 = 1224, - AArch64_SABALv16i8_v8i16 = 1225, - AArch64_SABALv2i32_v2i64 = 1226, - AArch64_SABALv4i16_v4i32 = 1227, - AArch64_SABALv4i32_v2i64 = 1228, - AArch64_SABALv8i16_v4i32 = 1229, - AArch64_SABALv8i8_v8i16 = 1230, - AArch64_SABAv16i8 = 1231, - AArch64_SABAv2i32 = 1232, - AArch64_SABAv4i16 = 1233, - AArch64_SABAv4i32 = 1234, - AArch64_SABAv8i16 = 1235, - AArch64_SABAv8i8 = 1236, - AArch64_SABDLv16i8_v8i16 = 1237, - AArch64_SABDLv2i32_v2i64 = 1238, - AArch64_SABDLv4i16_v4i32 = 1239, - AArch64_SABDLv4i32_v2i64 = 1240, - AArch64_SABDLv8i16_v4i32 = 1241, - AArch64_SABDLv8i8_v8i16 = 1242, - AArch64_SABDv16i8 = 1243, - AArch64_SABDv2i32 = 1244, - AArch64_SABDv4i16 = 1245, - AArch64_SABDv4i32 = 1246, - AArch64_SABDv8i16 = 1247, - AArch64_SABDv8i8 = 1248, - AArch64_SADALPv16i8_v8i16 = 1249, - AArch64_SADALPv2i32_v1i64 = 1250, - AArch64_SADALPv4i16_v2i32 = 1251, - AArch64_SADALPv4i32_v2i64 = 1252, - AArch64_SADALPv8i16_v4i32 = 1253, - AArch64_SADALPv8i8_v4i16 = 1254, - AArch64_SADDLPv16i8_v8i16 = 1255, - AArch64_SADDLPv2i32_v1i64 = 1256, - AArch64_SADDLPv4i16_v2i32 = 1257, - AArch64_SADDLPv4i32_v2i64 = 1258, - AArch64_SADDLPv8i16_v4i32 = 1259, - AArch64_SADDLPv8i8_v4i16 = 1260, - AArch64_SADDLVv16i8v = 1261, - AArch64_SADDLVv4i16v = 1262, - AArch64_SADDLVv4i32v = 1263, - AArch64_SADDLVv8i16v = 1264, - AArch64_SADDLVv8i8v = 1265, - AArch64_SADDLv16i8_v8i16 = 1266, - AArch64_SADDLv2i32_v2i64 = 1267, - AArch64_SADDLv4i16_v4i32 = 1268, - AArch64_SADDLv4i32_v2i64 = 1269, - AArch64_SADDLv8i16_v4i32 = 1270, - AArch64_SADDLv8i8_v8i16 = 1271, - AArch64_SADDWv16i8_v8i16 = 1272, - AArch64_SADDWv2i32_v2i64 = 1273, - AArch64_SADDWv4i16_v4i32 = 1274, - AArch64_SADDWv4i32_v2i64 = 1275, - AArch64_SADDWv8i16_v4i32 = 1276, - AArch64_SADDWv8i8_v8i16 = 1277, - AArch64_SBCSWr = 1278, - AArch64_SBCSXr = 1279, - AArch64_SBCWr = 1280, - AArch64_SBCXr = 1281, - AArch64_SBFMWri = 1282, - AArch64_SBFMXri = 1283, - AArch64_SCVTFSWDri = 1284, - AArch64_SCVTFSWSri = 1285, - AArch64_SCVTFSXDri = 1286, - AArch64_SCVTFSXSri = 1287, - AArch64_SCVTFUWDri = 1288, - AArch64_SCVTFUWSri = 1289, - AArch64_SCVTFUXDri = 1290, - AArch64_SCVTFUXSri = 1291, - AArch64_SCVTFd = 1292, - AArch64_SCVTFs = 1293, - AArch64_SCVTFv1i32 = 1294, - AArch64_SCVTFv1i64 = 1295, - AArch64_SCVTFv2f32 = 1296, - AArch64_SCVTFv2f64 = 1297, - AArch64_SCVTFv2i32_shift = 1298, - AArch64_SCVTFv2i64_shift = 1299, - AArch64_SCVTFv4f32 = 1300, - AArch64_SCVTFv4i32_shift = 1301, - AArch64_SDIVWr = 1302, - AArch64_SDIVXr = 1303, - AArch64_SDIV_IntWr = 1304, - AArch64_SDIV_IntXr = 1305, - AArch64_SHA1Crrr = 1306, - AArch64_SHA1Hrr = 1307, - AArch64_SHA1Mrrr = 1308, - AArch64_SHA1Prrr = 1309, - AArch64_SHA1SU0rrr = 1310, - AArch64_SHA1SU1rr = 1311, - AArch64_SHA256H2rrr = 1312, - AArch64_SHA256Hrrr = 1313, - AArch64_SHA256SU0rr = 1314, - AArch64_SHA256SU1rrr = 1315, - AArch64_SHADDv16i8 = 1316, - AArch64_SHADDv2i32 = 1317, - AArch64_SHADDv4i16 = 1318, - AArch64_SHADDv4i32 = 1319, - AArch64_SHADDv8i16 = 1320, - AArch64_SHADDv8i8 = 1321, - AArch64_SHLLv16i8 = 1322, - AArch64_SHLLv2i32 = 1323, - AArch64_SHLLv4i16 = 1324, - AArch64_SHLLv4i32 = 1325, - AArch64_SHLLv8i16 = 1326, - AArch64_SHLLv8i8 = 1327, - AArch64_SHLd = 1328, - AArch64_SHLv16i8_shift = 1329, - AArch64_SHLv2i32_shift = 1330, - AArch64_SHLv2i64_shift = 1331, - AArch64_SHLv4i16_shift = 1332, - AArch64_SHLv4i32_shift = 1333, - AArch64_SHLv8i16_shift = 1334, - AArch64_SHLv8i8_shift = 1335, - AArch64_SHRNv16i8_shift = 1336, - AArch64_SHRNv2i32_shift = 1337, - AArch64_SHRNv4i16_shift = 1338, - AArch64_SHRNv4i32_shift = 1339, - AArch64_SHRNv8i16_shift = 1340, - AArch64_SHRNv8i8_shift = 1341, - AArch64_SHSUBv16i8 = 1342, - AArch64_SHSUBv2i32 = 1343, - AArch64_SHSUBv4i16 = 1344, - AArch64_SHSUBv4i32 = 1345, - AArch64_SHSUBv8i16 = 1346, - AArch64_SHSUBv8i8 = 1347, - AArch64_SLId = 1348, - AArch64_SLIv16i8_shift = 1349, - AArch64_SLIv2i32_shift = 1350, - AArch64_SLIv2i64_shift = 1351, - AArch64_SLIv4i16_shift = 1352, - AArch64_SLIv4i32_shift = 1353, - AArch64_SLIv8i16_shift = 1354, - AArch64_SLIv8i8_shift = 1355, - AArch64_SMADDLrrr = 1356, - AArch64_SMAXPv16i8 = 1357, - AArch64_SMAXPv2i32 = 1358, - AArch64_SMAXPv4i16 = 1359, - AArch64_SMAXPv4i32 = 1360, - AArch64_SMAXPv8i16 = 1361, - AArch64_SMAXPv8i8 = 1362, - AArch64_SMAXVv16i8v = 1363, - AArch64_SMAXVv4i16v = 1364, - AArch64_SMAXVv4i32v = 1365, - AArch64_SMAXVv8i16v = 1366, - AArch64_SMAXVv8i8v = 1367, - AArch64_SMAXv16i8 = 1368, - AArch64_SMAXv2i32 = 1369, - AArch64_SMAXv4i16 = 1370, - AArch64_SMAXv4i32 = 1371, - AArch64_SMAXv8i16 = 1372, - AArch64_SMAXv8i8 = 1373, - AArch64_SMC = 1374, - AArch64_SMINPv16i8 = 1375, - AArch64_SMINPv2i32 = 1376, - AArch64_SMINPv4i16 = 1377, - AArch64_SMINPv4i32 = 1378, - AArch64_SMINPv8i16 = 1379, - AArch64_SMINPv8i8 = 1380, - AArch64_SMINVv16i8v = 1381, - AArch64_SMINVv4i16v = 1382, - AArch64_SMINVv4i32v = 1383, - AArch64_SMINVv8i16v = 1384, - AArch64_SMINVv8i8v = 1385, - AArch64_SMINv16i8 = 1386, - AArch64_SMINv2i32 = 1387, - AArch64_SMINv4i16 = 1388, - AArch64_SMINv4i32 = 1389, - AArch64_SMINv8i16 = 1390, - AArch64_SMINv8i8 = 1391, - AArch64_SMLALv16i8_v8i16 = 1392, - AArch64_SMLALv2i32_indexed = 1393, - AArch64_SMLALv2i32_v2i64 = 1394, - AArch64_SMLALv4i16_indexed = 1395, - AArch64_SMLALv4i16_v4i32 = 1396, - AArch64_SMLALv4i32_indexed = 1397, - AArch64_SMLALv4i32_v2i64 = 1398, - AArch64_SMLALv8i16_indexed = 1399, - AArch64_SMLALv8i16_v4i32 = 1400, - AArch64_SMLALv8i8_v8i16 = 1401, - AArch64_SMLSLv16i8_v8i16 = 1402, - AArch64_SMLSLv2i32_indexed = 1403, - AArch64_SMLSLv2i32_v2i64 = 1404, - AArch64_SMLSLv4i16_indexed = 1405, - AArch64_SMLSLv4i16_v4i32 = 1406, - AArch64_SMLSLv4i32_indexed = 1407, - AArch64_SMLSLv4i32_v2i64 = 1408, - AArch64_SMLSLv8i16_indexed = 1409, - AArch64_SMLSLv8i16_v4i32 = 1410, - AArch64_SMLSLv8i8_v8i16 = 1411, - AArch64_SMOVvi16to32 = 1412, - AArch64_SMOVvi16to64 = 1413, - AArch64_SMOVvi32to64 = 1414, - AArch64_SMOVvi8to32 = 1415, - AArch64_SMOVvi8to64 = 1416, - AArch64_SMSUBLrrr = 1417, - AArch64_SMULHrr = 1418, - AArch64_SMULLv16i8_v8i16 = 1419, - AArch64_SMULLv2i32_indexed = 1420, - AArch64_SMULLv2i32_v2i64 = 1421, - AArch64_SMULLv4i16_indexed = 1422, - AArch64_SMULLv4i16_v4i32 = 1423, - AArch64_SMULLv4i32_indexed = 1424, - AArch64_SMULLv4i32_v2i64 = 1425, - AArch64_SMULLv8i16_indexed = 1426, - AArch64_SMULLv8i16_v4i32 = 1427, - AArch64_SMULLv8i8_v8i16 = 1428, - AArch64_SQABSv16i8 = 1429, - AArch64_SQABSv1i16 = 1430, - AArch64_SQABSv1i32 = 1431, - AArch64_SQABSv1i64 = 1432, - AArch64_SQABSv1i8 = 1433, - AArch64_SQABSv2i32 = 1434, - AArch64_SQABSv2i64 = 1435, - AArch64_SQABSv4i16 = 1436, - AArch64_SQABSv4i32 = 1437, - AArch64_SQABSv8i16 = 1438, - AArch64_SQABSv8i8 = 1439, - AArch64_SQADDv16i8 = 1440, - AArch64_SQADDv1i16 = 1441, - AArch64_SQADDv1i32 = 1442, - AArch64_SQADDv1i64 = 1443, - AArch64_SQADDv1i8 = 1444, - AArch64_SQADDv2i32 = 1445, - AArch64_SQADDv2i64 = 1446, - AArch64_SQADDv4i16 = 1447, - AArch64_SQADDv4i32 = 1448, - AArch64_SQADDv8i16 = 1449, - AArch64_SQADDv8i8 = 1450, - AArch64_SQDMLALi16 = 1451, - AArch64_SQDMLALi32 = 1452, - AArch64_SQDMLALv1i32_indexed = 1453, - AArch64_SQDMLALv1i64_indexed = 1454, - AArch64_SQDMLALv2i32_indexed = 1455, - AArch64_SQDMLALv2i32_v2i64 = 1456, - AArch64_SQDMLALv4i16_indexed = 1457, - AArch64_SQDMLALv4i16_v4i32 = 1458, - AArch64_SQDMLALv4i32_indexed = 1459, - AArch64_SQDMLALv4i32_v2i64 = 1460, - AArch64_SQDMLALv8i16_indexed = 1461, - AArch64_SQDMLALv8i16_v4i32 = 1462, - AArch64_SQDMLSLi16 = 1463, - AArch64_SQDMLSLi32 = 1464, - AArch64_SQDMLSLv1i32_indexed = 1465, - AArch64_SQDMLSLv1i64_indexed = 1466, - AArch64_SQDMLSLv2i32_indexed = 1467, - AArch64_SQDMLSLv2i32_v2i64 = 1468, - AArch64_SQDMLSLv4i16_indexed = 1469, - AArch64_SQDMLSLv4i16_v4i32 = 1470, - AArch64_SQDMLSLv4i32_indexed = 1471, - AArch64_SQDMLSLv4i32_v2i64 = 1472, - AArch64_SQDMLSLv8i16_indexed = 1473, - AArch64_SQDMLSLv8i16_v4i32 = 1474, - AArch64_SQDMULHv1i16 = 1475, - AArch64_SQDMULHv1i16_indexed = 1476, - AArch64_SQDMULHv1i32 = 1477, - AArch64_SQDMULHv1i32_indexed = 1478, - AArch64_SQDMULHv2i32 = 1479, - AArch64_SQDMULHv2i32_indexed = 1480, - AArch64_SQDMULHv4i16 = 1481, - AArch64_SQDMULHv4i16_indexed = 1482, - AArch64_SQDMULHv4i32 = 1483, - AArch64_SQDMULHv4i32_indexed = 1484, - AArch64_SQDMULHv8i16 = 1485, - AArch64_SQDMULHv8i16_indexed = 1486, - AArch64_SQDMULLi16 = 1487, - AArch64_SQDMULLi32 = 1488, - AArch64_SQDMULLv1i32_indexed = 1489, - AArch64_SQDMULLv1i64_indexed = 1490, - AArch64_SQDMULLv2i32_indexed = 1491, - AArch64_SQDMULLv2i32_v2i64 = 1492, - AArch64_SQDMULLv4i16_indexed = 1493, - AArch64_SQDMULLv4i16_v4i32 = 1494, - AArch64_SQDMULLv4i32_indexed = 1495, - AArch64_SQDMULLv4i32_v2i64 = 1496, - AArch64_SQDMULLv8i16_indexed = 1497, - AArch64_SQDMULLv8i16_v4i32 = 1498, - AArch64_SQNEGv16i8 = 1499, - AArch64_SQNEGv1i16 = 1500, - AArch64_SQNEGv1i32 = 1501, - AArch64_SQNEGv1i64 = 1502, - AArch64_SQNEGv1i8 = 1503, - AArch64_SQNEGv2i32 = 1504, - AArch64_SQNEGv2i64 = 1505, - AArch64_SQNEGv4i16 = 1506, - AArch64_SQNEGv4i32 = 1507, - AArch64_SQNEGv8i16 = 1508, - AArch64_SQNEGv8i8 = 1509, - AArch64_SQRDMULHv1i16 = 1510, - AArch64_SQRDMULHv1i16_indexed = 1511, - AArch64_SQRDMULHv1i32 = 1512, - AArch64_SQRDMULHv1i32_indexed = 1513, - AArch64_SQRDMULHv2i32 = 1514, - AArch64_SQRDMULHv2i32_indexed = 1515, - AArch64_SQRDMULHv4i16 = 1516, - AArch64_SQRDMULHv4i16_indexed = 1517, - AArch64_SQRDMULHv4i32 = 1518, - AArch64_SQRDMULHv4i32_indexed = 1519, - AArch64_SQRDMULHv8i16 = 1520, - AArch64_SQRDMULHv8i16_indexed = 1521, - AArch64_SQRSHLv16i8 = 1522, - AArch64_SQRSHLv1i16 = 1523, - AArch64_SQRSHLv1i32 = 1524, - AArch64_SQRSHLv1i64 = 1525, - AArch64_SQRSHLv1i8 = 1526, - AArch64_SQRSHLv2i32 = 1527, - AArch64_SQRSHLv2i64 = 1528, - AArch64_SQRSHLv4i16 = 1529, - AArch64_SQRSHLv4i32 = 1530, - AArch64_SQRSHLv8i16 = 1531, - AArch64_SQRSHLv8i8 = 1532, - AArch64_SQRSHRNb = 1533, - AArch64_SQRSHRNh = 1534, - AArch64_SQRSHRNs = 1535, - AArch64_SQRSHRNv16i8_shift = 1536, - AArch64_SQRSHRNv2i32_shift = 1537, - AArch64_SQRSHRNv4i16_shift = 1538, - AArch64_SQRSHRNv4i32_shift = 1539, - AArch64_SQRSHRNv8i16_shift = 1540, - AArch64_SQRSHRNv8i8_shift = 1541, - AArch64_SQRSHRUNb = 1542, - AArch64_SQRSHRUNh = 1543, - AArch64_SQRSHRUNs = 1544, - AArch64_SQRSHRUNv16i8_shift = 1545, - AArch64_SQRSHRUNv2i32_shift = 1546, - AArch64_SQRSHRUNv4i16_shift = 1547, - AArch64_SQRSHRUNv4i32_shift = 1548, - AArch64_SQRSHRUNv8i16_shift = 1549, - AArch64_SQRSHRUNv8i8_shift = 1550, - AArch64_SQSHLUb = 1551, - AArch64_SQSHLUd = 1552, - AArch64_SQSHLUh = 1553, - AArch64_SQSHLUs = 1554, - AArch64_SQSHLUv16i8_shift = 1555, - AArch64_SQSHLUv2i32_shift = 1556, - AArch64_SQSHLUv2i64_shift = 1557, - AArch64_SQSHLUv4i16_shift = 1558, - AArch64_SQSHLUv4i32_shift = 1559, - AArch64_SQSHLUv8i16_shift = 1560, - AArch64_SQSHLUv8i8_shift = 1561, - AArch64_SQSHLb = 1562, - AArch64_SQSHLd = 1563, - AArch64_SQSHLh = 1564, - AArch64_SQSHLs = 1565, - AArch64_SQSHLv16i8 = 1566, - AArch64_SQSHLv16i8_shift = 1567, - AArch64_SQSHLv1i16 = 1568, - AArch64_SQSHLv1i32 = 1569, - AArch64_SQSHLv1i64 = 1570, - AArch64_SQSHLv1i8 = 1571, - AArch64_SQSHLv2i32 = 1572, - AArch64_SQSHLv2i32_shift = 1573, - AArch64_SQSHLv2i64 = 1574, - AArch64_SQSHLv2i64_shift = 1575, - AArch64_SQSHLv4i16 = 1576, - AArch64_SQSHLv4i16_shift = 1577, - AArch64_SQSHLv4i32 = 1578, - AArch64_SQSHLv4i32_shift = 1579, - AArch64_SQSHLv8i16 = 1580, - AArch64_SQSHLv8i16_shift = 1581, - AArch64_SQSHLv8i8 = 1582, - AArch64_SQSHLv8i8_shift = 1583, - AArch64_SQSHRNb = 1584, - AArch64_SQSHRNh = 1585, - AArch64_SQSHRNs = 1586, - AArch64_SQSHRNv16i8_shift = 1587, - AArch64_SQSHRNv2i32_shift = 1588, - AArch64_SQSHRNv4i16_shift = 1589, - AArch64_SQSHRNv4i32_shift = 1590, - AArch64_SQSHRNv8i16_shift = 1591, - AArch64_SQSHRNv8i8_shift = 1592, - AArch64_SQSHRUNb = 1593, - AArch64_SQSHRUNh = 1594, - AArch64_SQSHRUNs = 1595, - AArch64_SQSHRUNv16i8_shift = 1596, - AArch64_SQSHRUNv2i32_shift = 1597, - AArch64_SQSHRUNv4i16_shift = 1598, - AArch64_SQSHRUNv4i32_shift = 1599, - AArch64_SQSHRUNv8i16_shift = 1600, - AArch64_SQSHRUNv8i8_shift = 1601, - AArch64_SQSUBv16i8 = 1602, - AArch64_SQSUBv1i16 = 1603, - AArch64_SQSUBv1i32 = 1604, - AArch64_SQSUBv1i64 = 1605, - AArch64_SQSUBv1i8 = 1606, - AArch64_SQSUBv2i32 = 1607, - AArch64_SQSUBv2i64 = 1608, - AArch64_SQSUBv4i16 = 1609, - AArch64_SQSUBv4i32 = 1610, - AArch64_SQSUBv8i16 = 1611, - AArch64_SQSUBv8i8 = 1612, - AArch64_SQXTNv16i8 = 1613, - AArch64_SQXTNv1i16 = 1614, - AArch64_SQXTNv1i32 = 1615, - AArch64_SQXTNv1i8 = 1616, - AArch64_SQXTNv2i32 = 1617, - AArch64_SQXTNv4i16 = 1618, - AArch64_SQXTNv4i32 = 1619, - AArch64_SQXTNv8i16 = 1620, - AArch64_SQXTNv8i8 = 1621, - AArch64_SQXTUNv16i8 = 1622, - AArch64_SQXTUNv1i16 = 1623, - AArch64_SQXTUNv1i32 = 1624, - AArch64_SQXTUNv1i8 = 1625, - AArch64_SQXTUNv2i32 = 1626, - AArch64_SQXTUNv4i16 = 1627, - AArch64_SQXTUNv4i32 = 1628, - AArch64_SQXTUNv8i16 = 1629, - AArch64_SQXTUNv8i8 = 1630, - AArch64_SRHADDv16i8 = 1631, - AArch64_SRHADDv2i32 = 1632, - AArch64_SRHADDv4i16 = 1633, - AArch64_SRHADDv4i32 = 1634, - AArch64_SRHADDv8i16 = 1635, - AArch64_SRHADDv8i8 = 1636, - AArch64_SRId = 1637, - AArch64_SRIv16i8_shift = 1638, - AArch64_SRIv2i32_shift = 1639, - AArch64_SRIv2i64_shift = 1640, - AArch64_SRIv4i16_shift = 1641, - AArch64_SRIv4i32_shift = 1642, - AArch64_SRIv8i16_shift = 1643, - AArch64_SRIv8i8_shift = 1644, - AArch64_SRSHLv16i8 = 1645, - AArch64_SRSHLv1i64 = 1646, - AArch64_SRSHLv2i32 = 1647, - AArch64_SRSHLv2i64 = 1648, - AArch64_SRSHLv4i16 = 1649, - AArch64_SRSHLv4i32 = 1650, - AArch64_SRSHLv8i16 = 1651, - AArch64_SRSHLv8i8 = 1652, - AArch64_SRSHRd = 1653, - AArch64_SRSHRv16i8_shift = 1654, - AArch64_SRSHRv2i32_shift = 1655, - AArch64_SRSHRv2i64_shift = 1656, - AArch64_SRSHRv4i16_shift = 1657, - AArch64_SRSHRv4i32_shift = 1658, - AArch64_SRSHRv8i16_shift = 1659, - AArch64_SRSHRv8i8_shift = 1660, - AArch64_SRSRAd = 1661, - AArch64_SRSRAv16i8_shift = 1662, - AArch64_SRSRAv2i32_shift = 1663, - AArch64_SRSRAv2i64_shift = 1664, - AArch64_SRSRAv4i16_shift = 1665, - AArch64_SRSRAv4i32_shift = 1666, - AArch64_SRSRAv8i16_shift = 1667, - AArch64_SRSRAv8i8_shift = 1668, - AArch64_SSHLLv16i8_shift = 1669, - AArch64_SSHLLv2i32_shift = 1670, - AArch64_SSHLLv4i16_shift = 1671, - AArch64_SSHLLv4i32_shift = 1672, - AArch64_SSHLLv8i16_shift = 1673, - AArch64_SSHLLv8i8_shift = 1674, - AArch64_SSHLv16i8 = 1675, - AArch64_SSHLv1i64 = 1676, - AArch64_SSHLv2i32 = 1677, - AArch64_SSHLv2i64 = 1678, - AArch64_SSHLv4i16 = 1679, - AArch64_SSHLv4i32 = 1680, - AArch64_SSHLv8i16 = 1681, - AArch64_SSHLv8i8 = 1682, - AArch64_SSHRd = 1683, - AArch64_SSHRv16i8_shift = 1684, - AArch64_SSHRv2i32_shift = 1685, - AArch64_SSHRv2i64_shift = 1686, - AArch64_SSHRv4i16_shift = 1687, - AArch64_SSHRv4i32_shift = 1688, - AArch64_SSHRv8i16_shift = 1689, - AArch64_SSHRv8i8_shift = 1690, - AArch64_SSRAd = 1691, - AArch64_SSRAv16i8_shift = 1692, - AArch64_SSRAv2i32_shift = 1693, - AArch64_SSRAv2i64_shift = 1694, - AArch64_SSRAv4i16_shift = 1695, - AArch64_SSRAv4i32_shift = 1696, - AArch64_SSRAv8i16_shift = 1697, - AArch64_SSRAv8i8_shift = 1698, - AArch64_SSUBLv16i8_v8i16 = 1699, - AArch64_SSUBLv2i32_v2i64 = 1700, - AArch64_SSUBLv4i16_v4i32 = 1701, - AArch64_SSUBLv4i32_v2i64 = 1702, - AArch64_SSUBLv8i16_v4i32 = 1703, - AArch64_SSUBLv8i8_v8i16 = 1704, - AArch64_SSUBWv16i8_v8i16 = 1705, - AArch64_SSUBWv2i32_v2i64 = 1706, - AArch64_SSUBWv4i16_v4i32 = 1707, - AArch64_SSUBWv4i32_v2i64 = 1708, - AArch64_SSUBWv8i16_v4i32 = 1709, - AArch64_SSUBWv8i8_v8i16 = 1710, - AArch64_ST1Fourv16b = 1711, - AArch64_ST1Fourv16b_POST = 1712, - AArch64_ST1Fourv1d = 1713, - AArch64_ST1Fourv1d_POST = 1714, - AArch64_ST1Fourv2d = 1715, - AArch64_ST1Fourv2d_POST = 1716, - AArch64_ST1Fourv2s = 1717, - AArch64_ST1Fourv2s_POST = 1718, - AArch64_ST1Fourv4h = 1719, - AArch64_ST1Fourv4h_POST = 1720, - AArch64_ST1Fourv4s = 1721, - AArch64_ST1Fourv4s_POST = 1722, - AArch64_ST1Fourv8b = 1723, - AArch64_ST1Fourv8b_POST = 1724, - AArch64_ST1Fourv8h = 1725, - AArch64_ST1Fourv8h_POST = 1726, - AArch64_ST1Onev16b = 1727, - AArch64_ST1Onev16b_POST = 1728, - AArch64_ST1Onev1d = 1729, - AArch64_ST1Onev1d_POST = 1730, - AArch64_ST1Onev2d = 1731, - AArch64_ST1Onev2d_POST = 1732, - AArch64_ST1Onev2s = 1733, - AArch64_ST1Onev2s_POST = 1734, - AArch64_ST1Onev4h = 1735, - AArch64_ST1Onev4h_POST = 1736, - AArch64_ST1Onev4s = 1737, - AArch64_ST1Onev4s_POST = 1738, - AArch64_ST1Onev8b = 1739, - AArch64_ST1Onev8b_POST = 1740, - AArch64_ST1Onev8h = 1741, - AArch64_ST1Onev8h_POST = 1742, - AArch64_ST1Threev16b = 1743, - AArch64_ST1Threev16b_POST = 1744, - AArch64_ST1Threev1d = 1745, - AArch64_ST1Threev1d_POST = 1746, - AArch64_ST1Threev2d = 1747, - AArch64_ST1Threev2d_POST = 1748, - AArch64_ST1Threev2s = 1749, - AArch64_ST1Threev2s_POST = 1750, - AArch64_ST1Threev4h = 1751, - AArch64_ST1Threev4h_POST = 1752, - AArch64_ST1Threev4s = 1753, - AArch64_ST1Threev4s_POST = 1754, - AArch64_ST1Threev8b = 1755, - AArch64_ST1Threev8b_POST = 1756, - AArch64_ST1Threev8h = 1757, - AArch64_ST1Threev8h_POST = 1758, - AArch64_ST1Twov16b = 1759, - AArch64_ST1Twov16b_POST = 1760, - AArch64_ST1Twov1d = 1761, - AArch64_ST1Twov1d_POST = 1762, - AArch64_ST1Twov2d = 1763, - AArch64_ST1Twov2d_POST = 1764, - AArch64_ST1Twov2s = 1765, - AArch64_ST1Twov2s_POST = 1766, - AArch64_ST1Twov4h = 1767, - AArch64_ST1Twov4h_POST = 1768, - AArch64_ST1Twov4s = 1769, - AArch64_ST1Twov4s_POST = 1770, - AArch64_ST1Twov8b = 1771, - AArch64_ST1Twov8b_POST = 1772, - AArch64_ST1Twov8h = 1773, - AArch64_ST1Twov8h_POST = 1774, - AArch64_ST1i16 = 1775, - AArch64_ST1i16_POST = 1776, - AArch64_ST1i32 = 1777, - AArch64_ST1i32_POST = 1778, - AArch64_ST1i64 = 1779, - AArch64_ST1i64_POST = 1780, - AArch64_ST1i8 = 1781, - AArch64_ST1i8_POST = 1782, - AArch64_ST2Twov16b = 1783, - AArch64_ST2Twov16b_POST = 1784, - AArch64_ST2Twov2d = 1785, - AArch64_ST2Twov2d_POST = 1786, - AArch64_ST2Twov2s = 1787, - AArch64_ST2Twov2s_POST = 1788, - AArch64_ST2Twov4h = 1789, - AArch64_ST2Twov4h_POST = 1790, - AArch64_ST2Twov4s = 1791, - AArch64_ST2Twov4s_POST = 1792, - AArch64_ST2Twov8b = 1793, - AArch64_ST2Twov8b_POST = 1794, - AArch64_ST2Twov8h = 1795, - AArch64_ST2Twov8h_POST = 1796, - AArch64_ST2i16 = 1797, - AArch64_ST2i16_POST = 1798, - AArch64_ST2i32 = 1799, - AArch64_ST2i32_POST = 1800, - AArch64_ST2i64 = 1801, - AArch64_ST2i64_POST = 1802, - AArch64_ST2i8 = 1803, - AArch64_ST2i8_POST = 1804, - AArch64_ST3Threev16b = 1805, - AArch64_ST3Threev16b_POST = 1806, - AArch64_ST3Threev2d = 1807, - AArch64_ST3Threev2d_POST = 1808, - AArch64_ST3Threev2s = 1809, - AArch64_ST3Threev2s_POST = 1810, - AArch64_ST3Threev4h = 1811, - AArch64_ST3Threev4h_POST = 1812, - AArch64_ST3Threev4s = 1813, - AArch64_ST3Threev4s_POST = 1814, - AArch64_ST3Threev8b = 1815, - AArch64_ST3Threev8b_POST = 1816, - AArch64_ST3Threev8h = 1817, - AArch64_ST3Threev8h_POST = 1818, - AArch64_ST3i16 = 1819, - AArch64_ST3i16_POST = 1820, - AArch64_ST3i32 = 1821, - AArch64_ST3i32_POST = 1822, - AArch64_ST3i64 = 1823, - AArch64_ST3i64_POST = 1824, - AArch64_ST3i8 = 1825, - AArch64_ST3i8_POST = 1826, - AArch64_ST4Fourv16b = 1827, - AArch64_ST4Fourv16b_POST = 1828, - AArch64_ST4Fourv2d = 1829, - AArch64_ST4Fourv2d_POST = 1830, - AArch64_ST4Fourv2s = 1831, - AArch64_ST4Fourv2s_POST = 1832, - AArch64_ST4Fourv4h = 1833, - AArch64_ST4Fourv4h_POST = 1834, - AArch64_ST4Fourv4s = 1835, - AArch64_ST4Fourv4s_POST = 1836, - AArch64_ST4Fourv8b = 1837, - AArch64_ST4Fourv8b_POST = 1838, - AArch64_ST4Fourv8h = 1839, - AArch64_ST4Fourv8h_POST = 1840, - AArch64_ST4i16 = 1841, - AArch64_ST4i16_POST = 1842, - AArch64_ST4i32 = 1843, - AArch64_ST4i32_POST = 1844, - AArch64_ST4i64 = 1845, - AArch64_ST4i64_POST = 1846, - AArch64_ST4i8 = 1847, - AArch64_ST4i8_POST = 1848, - AArch64_STLRB = 1849, - AArch64_STLRH = 1850, - AArch64_STLRW = 1851, - AArch64_STLRX = 1852, - AArch64_STLXPW = 1853, - AArch64_STLXPX = 1854, - AArch64_STLXRB = 1855, - AArch64_STLXRH = 1856, - AArch64_STLXRW = 1857, - AArch64_STLXRX = 1858, - AArch64_STNPDi = 1859, - AArch64_STNPQi = 1860, - AArch64_STNPSi = 1861, - AArch64_STNPWi = 1862, - AArch64_STNPXi = 1863, - AArch64_STPDi = 1864, - AArch64_STPDpost = 1865, - AArch64_STPDpre = 1866, - AArch64_STPQi = 1867, - AArch64_STPQpost = 1868, - AArch64_STPQpre = 1869, - AArch64_STPSi = 1870, - AArch64_STPSpost = 1871, - AArch64_STPSpre = 1872, - AArch64_STPWi = 1873, - AArch64_STPWpost = 1874, - AArch64_STPWpre = 1875, - AArch64_STPXi = 1876, - AArch64_STPXpost = 1877, - AArch64_STPXpre = 1878, - AArch64_STRBBpost = 1879, - AArch64_STRBBpre = 1880, - AArch64_STRBBroW = 1881, - AArch64_STRBBroX = 1882, - AArch64_STRBBui = 1883, - AArch64_STRBpost = 1884, - AArch64_STRBpre = 1885, - AArch64_STRBroW = 1886, - AArch64_STRBroX = 1887, - AArch64_STRBui = 1888, - AArch64_STRDpost = 1889, - AArch64_STRDpre = 1890, - AArch64_STRDroW = 1891, - AArch64_STRDroX = 1892, - AArch64_STRDui = 1893, - AArch64_STRHHpost = 1894, - AArch64_STRHHpre = 1895, - AArch64_STRHHroW = 1896, - AArch64_STRHHroX = 1897, - AArch64_STRHHui = 1898, - AArch64_STRHpost = 1899, - AArch64_STRHpre = 1900, - AArch64_STRHroW = 1901, - AArch64_STRHroX = 1902, - AArch64_STRHui = 1903, - AArch64_STRQpost = 1904, - AArch64_STRQpre = 1905, - AArch64_STRQroW = 1906, - AArch64_STRQroX = 1907, - AArch64_STRQui = 1908, - AArch64_STRSpost = 1909, - AArch64_STRSpre = 1910, - AArch64_STRSroW = 1911, - AArch64_STRSroX = 1912, - AArch64_STRSui = 1913, - AArch64_STRWpost = 1914, - AArch64_STRWpre = 1915, - AArch64_STRWroW = 1916, - AArch64_STRWroX = 1917, - AArch64_STRWui = 1918, - AArch64_STRXpost = 1919, - AArch64_STRXpre = 1920, - AArch64_STRXroW = 1921, - AArch64_STRXroX = 1922, - AArch64_STRXui = 1923, - AArch64_STTRBi = 1924, - AArch64_STTRHi = 1925, - AArch64_STTRWi = 1926, - AArch64_STTRXi = 1927, - AArch64_STURBBi = 1928, - AArch64_STURBi = 1929, - AArch64_STURDi = 1930, - AArch64_STURHHi = 1931, - AArch64_STURHi = 1932, - AArch64_STURQi = 1933, - AArch64_STURSi = 1934, - AArch64_STURWi = 1935, - AArch64_STURXi = 1936, - AArch64_STXPW = 1937, - AArch64_STXPX = 1938, - AArch64_STXRB = 1939, - AArch64_STXRH = 1940, - AArch64_STXRW = 1941, - AArch64_STXRX = 1942, - AArch64_SUBHNv2i64_v2i32 = 1943, - AArch64_SUBHNv2i64_v4i32 = 1944, - AArch64_SUBHNv4i32_v4i16 = 1945, - AArch64_SUBHNv4i32_v8i16 = 1946, - AArch64_SUBHNv8i16_v16i8 = 1947, - AArch64_SUBHNv8i16_v8i8 = 1948, - AArch64_SUBSWri = 1949, - AArch64_SUBSWrr = 1950, - AArch64_SUBSWrs = 1951, - AArch64_SUBSWrx = 1952, - AArch64_SUBSXri = 1953, - AArch64_SUBSXrr = 1954, - AArch64_SUBSXrs = 1955, - AArch64_SUBSXrx = 1956, - AArch64_SUBSXrx64 = 1957, - AArch64_SUBWri = 1958, - AArch64_SUBWrr = 1959, - AArch64_SUBWrs = 1960, - AArch64_SUBWrx = 1961, - AArch64_SUBXri = 1962, - AArch64_SUBXrr = 1963, - AArch64_SUBXrs = 1964, - AArch64_SUBXrx = 1965, - AArch64_SUBXrx64 = 1966, - AArch64_SUBv16i8 = 1967, - AArch64_SUBv1i64 = 1968, - AArch64_SUBv2i32 = 1969, - AArch64_SUBv2i64 = 1970, - AArch64_SUBv4i16 = 1971, - AArch64_SUBv4i32 = 1972, - AArch64_SUBv8i16 = 1973, - AArch64_SUBv8i8 = 1974, - AArch64_SUQADDv16i8 = 1975, - AArch64_SUQADDv1i16 = 1976, - AArch64_SUQADDv1i32 = 1977, - AArch64_SUQADDv1i64 = 1978, - AArch64_SUQADDv1i8 = 1979, - AArch64_SUQADDv2i32 = 1980, - AArch64_SUQADDv2i64 = 1981, - AArch64_SUQADDv4i16 = 1982, - AArch64_SUQADDv4i32 = 1983, - AArch64_SUQADDv8i16 = 1984, - AArch64_SUQADDv8i8 = 1985, - AArch64_SVC = 1986, - AArch64_SYSLxt = 1987, - AArch64_SYSxt = 1988, - AArch64_TBLv16i8Four = 1989, - AArch64_TBLv16i8One = 1990, - AArch64_TBLv16i8Three = 1991, - AArch64_TBLv16i8Two = 1992, - AArch64_TBLv8i8Four = 1993, - AArch64_TBLv8i8One = 1994, - AArch64_TBLv8i8Three = 1995, - AArch64_TBLv8i8Two = 1996, - AArch64_TBNZW = 1997, - AArch64_TBNZX = 1998, - AArch64_TBXv16i8Four = 1999, - AArch64_TBXv16i8One = 2000, - AArch64_TBXv16i8Three = 2001, - AArch64_TBXv16i8Two = 2002, - AArch64_TBXv8i8Four = 2003, - AArch64_TBXv8i8One = 2004, - AArch64_TBXv8i8Three = 2005, - AArch64_TBXv8i8Two = 2006, - AArch64_TBZW = 2007, - AArch64_TBZX = 2008, - AArch64_TCRETURNdi = 2009, - AArch64_TCRETURNri = 2010, - AArch64_TLSDESCCALL = 2011, - AArch64_TLSDESC_BLR = 2012, - AArch64_TRN1v16i8 = 2013, - AArch64_TRN1v2i32 = 2014, - AArch64_TRN1v2i64 = 2015, - AArch64_TRN1v4i16 = 2016, - AArch64_TRN1v4i32 = 2017, - AArch64_TRN1v8i16 = 2018, - AArch64_TRN1v8i8 = 2019, - AArch64_TRN2v16i8 = 2020, - AArch64_TRN2v2i32 = 2021, - AArch64_TRN2v2i64 = 2022, - AArch64_TRN2v4i16 = 2023, - AArch64_TRN2v4i32 = 2024, - AArch64_TRN2v8i16 = 2025, - AArch64_TRN2v8i8 = 2026, - AArch64_UABALv16i8_v8i16 = 2027, - AArch64_UABALv2i32_v2i64 = 2028, - AArch64_UABALv4i16_v4i32 = 2029, - AArch64_UABALv4i32_v2i64 = 2030, - AArch64_UABALv8i16_v4i32 = 2031, - AArch64_UABALv8i8_v8i16 = 2032, - AArch64_UABAv16i8 = 2033, - AArch64_UABAv2i32 = 2034, - AArch64_UABAv4i16 = 2035, - AArch64_UABAv4i32 = 2036, - AArch64_UABAv8i16 = 2037, - AArch64_UABAv8i8 = 2038, - AArch64_UABDLv16i8_v8i16 = 2039, - AArch64_UABDLv2i32_v2i64 = 2040, - AArch64_UABDLv4i16_v4i32 = 2041, - AArch64_UABDLv4i32_v2i64 = 2042, - AArch64_UABDLv8i16_v4i32 = 2043, - AArch64_UABDLv8i8_v8i16 = 2044, - AArch64_UABDv16i8 = 2045, - AArch64_UABDv2i32 = 2046, - AArch64_UABDv4i16 = 2047, - AArch64_UABDv4i32 = 2048, - AArch64_UABDv8i16 = 2049, - AArch64_UABDv8i8 = 2050, - AArch64_UADALPv16i8_v8i16 = 2051, - AArch64_UADALPv2i32_v1i64 = 2052, - AArch64_UADALPv4i16_v2i32 = 2053, - AArch64_UADALPv4i32_v2i64 = 2054, - AArch64_UADALPv8i16_v4i32 = 2055, - AArch64_UADALPv8i8_v4i16 = 2056, - AArch64_UADDLPv16i8_v8i16 = 2057, - AArch64_UADDLPv2i32_v1i64 = 2058, - AArch64_UADDLPv4i16_v2i32 = 2059, - AArch64_UADDLPv4i32_v2i64 = 2060, - AArch64_UADDLPv8i16_v4i32 = 2061, - AArch64_UADDLPv8i8_v4i16 = 2062, - AArch64_UADDLVv16i8v = 2063, - AArch64_UADDLVv4i16v = 2064, - AArch64_UADDLVv4i32v = 2065, - AArch64_UADDLVv8i16v = 2066, - AArch64_UADDLVv8i8v = 2067, - AArch64_UADDLv16i8_v8i16 = 2068, - AArch64_UADDLv2i32_v2i64 = 2069, - AArch64_UADDLv4i16_v4i32 = 2070, - AArch64_UADDLv4i32_v2i64 = 2071, - AArch64_UADDLv8i16_v4i32 = 2072, - AArch64_UADDLv8i8_v8i16 = 2073, - AArch64_UADDWv16i8_v8i16 = 2074, - AArch64_UADDWv2i32_v2i64 = 2075, - AArch64_UADDWv4i16_v4i32 = 2076, - AArch64_UADDWv4i32_v2i64 = 2077, - AArch64_UADDWv8i16_v4i32 = 2078, - AArch64_UADDWv8i8_v8i16 = 2079, - AArch64_UBFMWri = 2080, - AArch64_UBFMXri = 2081, - AArch64_UCVTFSWDri = 2082, - AArch64_UCVTFSWSri = 2083, - AArch64_UCVTFSXDri = 2084, - AArch64_UCVTFSXSri = 2085, - AArch64_UCVTFUWDri = 2086, - AArch64_UCVTFUWSri = 2087, - AArch64_UCVTFUXDri = 2088, - AArch64_UCVTFUXSri = 2089, - AArch64_UCVTFd = 2090, - AArch64_UCVTFs = 2091, - AArch64_UCVTFv1i32 = 2092, - AArch64_UCVTFv1i64 = 2093, - AArch64_UCVTFv2f32 = 2094, - AArch64_UCVTFv2f64 = 2095, - AArch64_UCVTFv2i32_shift = 2096, - AArch64_UCVTFv2i64_shift = 2097, - AArch64_UCVTFv4f32 = 2098, - AArch64_UCVTFv4i32_shift = 2099, - AArch64_UDIVWr = 2100, - AArch64_UDIVXr = 2101, - AArch64_UDIV_IntWr = 2102, - AArch64_UDIV_IntXr = 2103, - AArch64_UHADDv16i8 = 2104, - AArch64_UHADDv2i32 = 2105, - AArch64_UHADDv4i16 = 2106, - AArch64_UHADDv4i32 = 2107, - AArch64_UHADDv8i16 = 2108, - AArch64_UHADDv8i8 = 2109, - AArch64_UHSUBv16i8 = 2110, - AArch64_UHSUBv2i32 = 2111, - AArch64_UHSUBv4i16 = 2112, - AArch64_UHSUBv4i32 = 2113, - AArch64_UHSUBv8i16 = 2114, - AArch64_UHSUBv8i8 = 2115, - AArch64_UMADDLrrr = 2116, - AArch64_UMAXPv16i8 = 2117, - AArch64_UMAXPv2i32 = 2118, - AArch64_UMAXPv4i16 = 2119, - AArch64_UMAXPv4i32 = 2120, - AArch64_UMAXPv8i16 = 2121, - AArch64_UMAXPv8i8 = 2122, - AArch64_UMAXVv16i8v = 2123, - AArch64_UMAXVv4i16v = 2124, - AArch64_UMAXVv4i32v = 2125, - AArch64_UMAXVv8i16v = 2126, - AArch64_UMAXVv8i8v = 2127, - AArch64_UMAXv16i8 = 2128, - AArch64_UMAXv2i32 = 2129, - AArch64_UMAXv4i16 = 2130, - AArch64_UMAXv4i32 = 2131, - AArch64_UMAXv8i16 = 2132, - AArch64_UMAXv8i8 = 2133, - AArch64_UMINPv16i8 = 2134, - AArch64_UMINPv2i32 = 2135, - AArch64_UMINPv4i16 = 2136, - AArch64_UMINPv4i32 = 2137, - AArch64_UMINPv8i16 = 2138, - AArch64_UMINPv8i8 = 2139, - AArch64_UMINVv16i8v = 2140, - AArch64_UMINVv4i16v = 2141, - AArch64_UMINVv4i32v = 2142, - AArch64_UMINVv8i16v = 2143, - AArch64_UMINVv8i8v = 2144, - AArch64_UMINv16i8 = 2145, - AArch64_UMINv2i32 = 2146, - AArch64_UMINv4i16 = 2147, - AArch64_UMINv4i32 = 2148, - AArch64_UMINv8i16 = 2149, - AArch64_UMINv8i8 = 2150, - AArch64_UMLALv16i8_v8i16 = 2151, - AArch64_UMLALv2i32_indexed = 2152, - AArch64_UMLALv2i32_v2i64 = 2153, - AArch64_UMLALv4i16_indexed = 2154, - AArch64_UMLALv4i16_v4i32 = 2155, - AArch64_UMLALv4i32_indexed = 2156, - AArch64_UMLALv4i32_v2i64 = 2157, - AArch64_UMLALv8i16_indexed = 2158, - AArch64_UMLALv8i16_v4i32 = 2159, - AArch64_UMLALv8i8_v8i16 = 2160, - AArch64_UMLSLv16i8_v8i16 = 2161, - AArch64_UMLSLv2i32_indexed = 2162, - AArch64_UMLSLv2i32_v2i64 = 2163, - AArch64_UMLSLv4i16_indexed = 2164, - AArch64_UMLSLv4i16_v4i32 = 2165, - AArch64_UMLSLv4i32_indexed = 2166, - AArch64_UMLSLv4i32_v2i64 = 2167, - AArch64_UMLSLv8i16_indexed = 2168, - AArch64_UMLSLv8i16_v4i32 = 2169, - AArch64_UMLSLv8i8_v8i16 = 2170, - AArch64_UMOVvi16 = 2171, - AArch64_UMOVvi32 = 2172, - AArch64_UMOVvi64 = 2173, - AArch64_UMOVvi8 = 2174, - AArch64_UMSUBLrrr = 2175, - AArch64_UMULHrr = 2176, - AArch64_UMULLv16i8_v8i16 = 2177, - AArch64_UMULLv2i32_indexed = 2178, - AArch64_UMULLv2i32_v2i64 = 2179, - AArch64_UMULLv4i16_indexed = 2180, - AArch64_UMULLv4i16_v4i32 = 2181, - AArch64_UMULLv4i32_indexed = 2182, - AArch64_UMULLv4i32_v2i64 = 2183, - AArch64_UMULLv8i16_indexed = 2184, - AArch64_UMULLv8i16_v4i32 = 2185, - AArch64_UMULLv8i8_v8i16 = 2186, - AArch64_UQADDv16i8 = 2187, - AArch64_UQADDv1i16 = 2188, - AArch64_UQADDv1i32 = 2189, - AArch64_UQADDv1i64 = 2190, - AArch64_UQADDv1i8 = 2191, - AArch64_UQADDv2i32 = 2192, - AArch64_UQADDv2i64 = 2193, - AArch64_UQADDv4i16 = 2194, - AArch64_UQADDv4i32 = 2195, - AArch64_UQADDv8i16 = 2196, - AArch64_UQADDv8i8 = 2197, - AArch64_UQRSHLv16i8 = 2198, - AArch64_UQRSHLv1i16 = 2199, - AArch64_UQRSHLv1i32 = 2200, - AArch64_UQRSHLv1i64 = 2201, - AArch64_UQRSHLv1i8 = 2202, - AArch64_UQRSHLv2i32 = 2203, - AArch64_UQRSHLv2i64 = 2204, - AArch64_UQRSHLv4i16 = 2205, - AArch64_UQRSHLv4i32 = 2206, - AArch64_UQRSHLv8i16 = 2207, - AArch64_UQRSHLv8i8 = 2208, - AArch64_UQRSHRNb = 2209, - AArch64_UQRSHRNh = 2210, - AArch64_UQRSHRNs = 2211, - AArch64_UQRSHRNv16i8_shift = 2212, - AArch64_UQRSHRNv2i32_shift = 2213, - AArch64_UQRSHRNv4i16_shift = 2214, - AArch64_UQRSHRNv4i32_shift = 2215, - AArch64_UQRSHRNv8i16_shift = 2216, - AArch64_UQRSHRNv8i8_shift = 2217, - AArch64_UQSHLb = 2218, - AArch64_UQSHLd = 2219, - AArch64_UQSHLh = 2220, - AArch64_UQSHLs = 2221, - AArch64_UQSHLv16i8 = 2222, - AArch64_UQSHLv16i8_shift = 2223, - AArch64_UQSHLv1i16 = 2224, - AArch64_UQSHLv1i32 = 2225, - AArch64_UQSHLv1i64 = 2226, - AArch64_UQSHLv1i8 = 2227, - AArch64_UQSHLv2i32 = 2228, - AArch64_UQSHLv2i32_shift = 2229, - AArch64_UQSHLv2i64 = 2230, - AArch64_UQSHLv2i64_shift = 2231, - AArch64_UQSHLv4i16 = 2232, - AArch64_UQSHLv4i16_shift = 2233, - AArch64_UQSHLv4i32 = 2234, - AArch64_UQSHLv4i32_shift = 2235, - AArch64_UQSHLv8i16 = 2236, - AArch64_UQSHLv8i16_shift = 2237, - AArch64_UQSHLv8i8 = 2238, - AArch64_UQSHLv8i8_shift = 2239, - AArch64_UQSHRNb = 2240, - AArch64_UQSHRNh = 2241, - AArch64_UQSHRNs = 2242, - AArch64_UQSHRNv16i8_shift = 2243, - AArch64_UQSHRNv2i32_shift = 2244, - AArch64_UQSHRNv4i16_shift = 2245, - AArch64_UQSHRNv4i32_shift = 2246, - AArch64_UQSHRNv8i16_shift = 2247, - AArch64_UQSHRNv8i8_shift = 2248, - AArch64_UQSUBv16i8 = 2249, - AArch64_UQSUBv1i16 = 2250, - AArch64_UQSUBv1i32 = 2251, - AArch64_UQSUBv1i64 = 2252, - AArch64_UQSUBv1i8 = 2253, - AArch64_UQSUBv2i32 = 2254, - AArch64_UQSUBv2i64 = 2255, - AArch64_UQSUBv4i16 = 2256, - AArch64_UQSUBv4i32 = 2257, - AArch64_UQSUBv8i16 = 2258, - AArch64_UQSUBv8i8 = 2259, - AArch64_UQXTNv16i8 = 2260, - AArch64_UQXTNv1i16 = 2261, - AArch64_UQXTNv1i32 = 2262, - AArch64_UQXTNv1i8 = 2263, - AArch64_UQXTNv2i32 = 2264, - AArch64_UQXTNv4i16 = 2265, - AArch64_UQXTNv4i32 = 2266, - AArch64_UQXTNv8i16 = 2267, - AArch64_UQXTNv8i8 = 2268, - AArch64_URECPEv2i32 = 2269, - AArch64_URECPEv4i32 = 2270, - AArch64_URHADDv16i8 = 2271, - AArch64_URHADDv2i32 = 2272, - AArch64_URHADDv4i16 = 2273, - AArch64_URHADDv4i32 = 2274, - AArch64_URHADDv8i16 = 2275, - AArch64_URHADDv8i8 = 2276, - AArch64_URSHLv16i8 = 2277, - AArch64_URSHLv1i64 = 2278, - AArch64_URSHLv2i32 = 2279, - AArch64_URSHLv2i64 = 2280, - AArch64_URSHLv4i16 = 2281, - AArch64_URSHLv4i32 = 2282, - AArch64_URSHLv8i16 = 2283, - AArch64_URSHLv8i8 = 2284, - AArch64_URSHRd = 2285, - AArch64_URSHRv16i8_shift = 2286, - AArch64_URSHRv2i32_shift = 2287, - AArch64_URSHRv2i64_shift = 2288, - AArch64_URSHRv4i16_shift = 2289, - AArch64_URSHRv4i32_shift = 2290, - AArch64_URSHRv8i16_shift = 2291, - AArch64_URSHRv8i8_shift = 2292, - AArch64_URSQRTEv2i32 = 2293, - AArch64_URSQRTEv4i32 = 2294, - AArch64_URSRAd = 2295, - AArch64_URSRAv16i8_shift = 2296, - AArch64_URSRAv2i32_shift = 2297, - AArch64_URSRAv2i64_shift = 2298, - AArch64_URSRAv4i16_shift = 2299, - AArch64_URSRAv4i32_shift = 2300, - AArch64_URSRAv8i16_shift = 2301, - AArch64_URSRAv8i8_shift = 2302, - AArch64_USHLLv16i8_shift = 2303, - AArch64_USHLLv2i32_shift = 2304, - AArch64_USHLLv4i16_shift = 2305, - AArch64_USHLLv4i32_shift = 2306, - AArch64_USHLLv8i16_shift = 2307, - AArch64_USHLLv8i8_shift = 2308, - AArch64_USHLv16i8 = 2309, - AArch64_USHLv1i64 = 2310, - AArch64_USHLv2i32 = 2311, - AArch64_USHLv2i64 = 2312, - AArch64_USHLv4i16 = 2313, - AArch64_USHLv4i32 = 2314, - AArch64_USHLv8i16 = 2315, - AArch64_USHLv8i8 = 2316, - AArch64_USHRd = 2317, - AArch64_USHRv16i8_shift = 2318, - AArch64_USHRv2i32_shift = 2319, - AArch64_USHRv2i64_shift = 2320, - AArch64_USHRv4i16_shift = 2321, - AArch64_USHRv4i32_shift = 2322, - AArch64_USHRv8i16_shift = 2323, - AArch64_USHRv8i8_shift = 2324, - AArch64_USQADDv16i8 = 2325, - AArch64_USQADDv1i16 = 2326, - AArch64_USQADDv1i32 = 2327, - AArch64_USQADDv1i64 = 2328, - AArch64_USQADDv1i8 = 2329, - AArch64_USQADDv2i32 = 2330, - AArch64_USQADDv2i64 = 2331, - AArch64_USQADDv4i16 = 2332, - AArch64_USQADDv4i32 = 2333, - AArch64_USQADDv8i16 = 2334, - AArch64_USQADDv8i8 = 2335, - AArch64_USRAd = 2336, - AArch64_USRAv16i8_shift = 2337, - AArch64_USRAv2i32_shift = 2338, - AArch64_USRAv2i64_shift = 2339, - AArch64_USRAv4i16_shift = 2340, - AArch64_USRAv4i32_shift = 2341, - AArch64_USRAv8i16_shift = 2342, - AArch64_USRAv8i8_shift = 2343, - AArch64_USUBLv16i8_v8i16 = 2344, - AArch64_USUBLv2i32_v2i64 = 2345, - AArch64_USUBLv4i16_v4i32 = 2346, - AArch64_USUBLv4i32_v2i64 = 2347, - AArch64_USUBLv8i16_v4i32 = 2348, - AArch64_USUBLv8i8_v8i16 = 2349, - AArch64_USUBWv16i8_v8i16 = 2350, - AArch64_USUBWv2i32_v2i64 = 2351, - AArch64_USUBWv4i16_v4i32 = 2352, - AArch64_USUBWv4i32_v2i64 = 2353, - AArch64_USUBWv8i16_v4i32 = 2354, - AArch64_USUBWv8i8_v8i16 = 2355, - AArch64_UZP1v16i8 = 2356, - AArch64_UZP1v2i32 = 2357, - AArch64_UZP1v2i64 = 2358, - AArch64_UZP1v4i16 = 2359, - AArch64_UZP1v4i32 = 2360, - AArch64_UZP1v8i16 = 2361, - AArch64_UZP1v8i8 = 2362, - AArch64_UZP2v16i8 = 2363, - AArch64_UZP2v2i32 = 2364, - AArch64_UZP2v2i64 = 2365, - AArch64_UZP2v4i16 = 2366, - AArch64_UZP2v4i32 = 2367, - AArch64_UZP2v8i16 = 2368, - AArch64_UZP2v8i8 = 2369, - AArch64_XTNv16i8 = 2370, - AArch64_XTNv2i32 = 2371, - AArch64_XTNv4i16 = 2372, - AArch64_XTNv4i32 = 2373, - AArch64_XTNv8i16 = 2374, - AArch64_XTNv8i8 = 2375, - AArch64_ZIP1v16i8 = 2376, - AArch64_ZIP1v2i32 = 2377, - AArch64_ZIP1v2i64 = 2378, - AArch64_ZIP1v4i16 = 2379, - AArch64_ZIP1v4i32 = 2380, - AArch64_ZIP1v8i16 = 2381, - AArch64_ZIP1v8i8 = 2382, - AArch64_ZIP2v16i8 = 2383, - AArch64_ZIP2v2i32 = 2384, - AArch64_ZIP2v2i64 = 2385, - AArch64_ZIP2v4i16 = 2386, - AArch64_ZIP2v4i32 = 2387, - AArch64_ZIP2v8i16 = 2388, - AArch64_ZIP2v8i8 = 2389, - AArch64_INSTRUCTION_LIST_END = 2390 + AArch64_PHI = 0, + AArch64_INLINEASM = 1, + AArch64_CFI_INSTRUCTION = 2, + AArch64_EH_LABEL = 3, + AArch64_GC_LABEL = 4, + AArch64_ANNOTATION_LABEL = 5, + AArch64_KILL = 6, + AArch64_EXTRACT_SUBREG = 7, + AArch64_INSERT_SUBREG = 8, + AArch64_IMPLICIT_DEF = 9, + AArch64_SUBREG_TO_REG = 10, + AArch64_COPY_TO_REGCLASS = 11, + AArch64_DBG_VALUE = 12, + AArch64_DBG_LABEL = 13, + AArch64_REG_SEQUENCE = 14, + AArch64_COPY = 15, + AArch64_BUNDLE = 16, + AArch64_LIFETIME_START = 17, + AArch64_LIFETIME_END = 18, + AArch64_STACKMAP = 19, + AArch64_FENTRY_CALL = 20, + AArch64_PATCHPOINT = 21, + AArch64_LOAD_STACK_GUARD = 22, + AArch64_STATEPOINT = 23, + AArch64_LOCAL_ESCAPE = 24, + AArch64_FAULTING_OP = 25, + AArch64_PATCHABLE_OP = 26, + AArch64_PATCHABLE_FUNCTION_ENTER = 27, + AArch64_PATCHABLE_RET = 28, + AArch64_PATCHABLE_FUNCTION_EXIT = 29, + AArch64_PATCHABLE_TAIL_CALL = 30, + AArch64_PATCHABLE_EVENT_CALL = 31, + AArch64_PATCHABLE_TYPED_EVENT_CALL = 32, + AArch64_ICALL_BRANCH_FUNNEL = 33, + AArch64_G_ADD = 34, + AArch64_G_SUB = 35, + AArch64_G_MUL = 36, + AArch64_G_SDIV = 37, + AArch64_G_UDIV = 38, + AArch64_G_SREM = 39, + AArch64_G_UREM = 40, + AArch64_G_AND = 41, + AArch64_G_OR = 42, + AArch64_G_XOR = 43, + AArch64_G_IMPLICIT_DEF = 44, + AArch64_G_PHI = 45, + AArch64_G_FRAME_INDEX = 46, + AArch64_G_GLOBAL_VALUE = 47, + AArch64_G_EXTRACT = 48, + AArch64_G_UNMERGE_VALUES = 49, + AArch64_G_INSERT = 50, + AArch64_G_MERGE_VALUES = 51, + AArch64_G_PTRTOINT = 52, + AArch64_G_INTTOPTR = 53, + AArch64_G_BITCAST = 54, + AArch64_G_LOAD = 55, + AArch64_G_SEXTLOAD = 56, + AArch64_G_ZEXTLOAD = 57, + AArch64_G_STORE = 58, + AArch64_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 59, + AArch64_G_ATOMIC_CMPXCHG = 60, + AArch64_G_ATOMICRMW_XCHG = 61, + AArch64_G_ATOMICRMW_ADD = 62, + AArch64_G_ATOMICRMW_SUB = 63, + AArch64_G_ATOMICRMW_AND = 64, + AArch64_G_ATOMICRMW_NAND = 65, + AArch64_G_ATOMICRMW_OR = 66, + AArch64_G_ATOMICRMW_XOR = 67, + AArch64_G_ATOMICRMW_MAX = 68, + AArch64_G_ATOMICRMW_MIN = 69, + AArch64_G_ATOMICRMW_UMAX = 70, + AArch64_G_ATOMICRMW_UMIN = 71, + AArch64_G_BRCOND = 72, + AArch64_G_BRINDIRECT = 73, + AArch64_G_INTRINSIC = 74, + AArch64_G_INTRINSIC_W_SIDE_EFFECTS = 75, + AArch64_G_ANYEXT = 76, + AArch64_G_TRUNC = 77, + AArch64_G_CONSTANT = 78, + AArch64_G_FCONSTANT = 79, + AArch64_G_VASTART = 80, + AArch64_G_VAARG = 81, + AArch64_G_SEXT = 82, + AArch64_G_ZEXT = 83, + AArch64_G_SHL = 84, + AArch64_G_LSHR = 85, + AArch64_G_ASHR = 86, + AArch64_G_ICMP = 87, + AArch64_G_FCMP = 88, + AArch64_G_SELECT = 89, + AArch64_G_UADDE = 90, + AArch64_G_USUBE = 91, + AArch64_G_SADDO = 92, + AArch64_G_SSUBO = 93, + AArch64_G_UMULO = 94, + AArch64_G_SMULO = 95, + AArch64_G_UMULH = 96, + AArch64_G_SMULH = 97, + AArch64_G_FADD = 98, + AArch64_G_FSUB = 99, + AArch64_G_FMUL = 100, + AArch64_G_FMA = 101, + AArch64_G_FDIV = 102, + AArch64_G_FREM = 103, + AArch64_G_FPOW = 104, + AArch64_G_FEXP = 105, + AArch64_G_FEXP2 = 106, + AArch64_G_FLOG = 107, + AArch64_G_FLOG2 = 108, + AArch64_G_FNEG = 109, + AArch64_G_FPEXT = 110, + AArch64_G_FPTRUNC = 111, + AArch64_G_FPTOSI = 112, + AArch64_G_FPTOUI = 113, + AArch64_G_SITOFP = 114, + AArch64_G_UITOFP = 115, + AArch64_G_FABS = 116, + AArch64_G_GEP = 117, + AArch64_G_PTR_MASK = 118, + AArch64_G_BR = 119, + AArch64_G_INSERT_VECTOR_ELT = 120, + AArch64_G_EXTRACT_VECTOR_ELT = 121, + AArch64_G_SHUFFLE_VECTOR = 122, + AArch64_G_BSWAP = 123, + AArch64_G_ADDRSPACE_CAST = 124, + AArch64_G_BLOCK_ADDR = 125, + AArch64_ABS_ZPmZ_B = 126, + AArch64_ABS_ZPmZ_D = 127, + AArch64_ABS_ZPmZ_H = 128, + AArch64_ABS_ZPmZ_S = 129, + AArch64_ABSv16i8 = 130, + AArch64_ABSv1i64 = 131, + AArch64_ABSv2i32 = 132, + AArch64_ABSv2i64 = 133, + AArch64_ABSv4i16 = 134, + AArch64_ABSv4i32 = 135, + AArch64_ABSv8i16 = 136, + AArch64_ABSv8i8 = 137, + AArch64_ADCSWr = 138, + AArch64_ADCSXr = 139, + AArch64_ADCWr = 140, + AArch64_ADCXr = 141, + AArch64_ADDHNv2i64_v2i32 = 142, + AArch64_ADDHNv2i64_v4i32 = 143, + AArch64_ADDHNv4i32_v4i16 = 144, + AArch64_ADDHNv4i32_v8i16 = 145, + AArch64_ADDHNv8i16_v16i8 = 146, + AArch64_ADDHNv8i16_v8i8 = 147, + AArch64_ADDPL_XXI = 148, + AArch64_ADDPv16i8 = 149, + AArch64_ADDPv2i32 = 150, + AArch64_ADDPv2i64 = 151, + AArch64_ADDPv2i64p = 152, + AArch64_ADDPv4i16 = 153, + AArch64_ADDPv4i32 = 154, + AArch64_ADDPv8i16 = 155, + AArch64_ADDPv8i8 = 156, + AArch64_ADDSWri = 157, + AArch64_ADDSWrr = 158, + AArch64_ADDSWrs = 159, + AArch64_ADDSWrx = 160, + AArch64_ADDSXri = 161, + AArch64_ADDSXrr = 162, + AArch64_ADDSXrs = 163, + AArch64_ADDSXrx = 164, + AArch64_ADDSXrx64 = 165, + AArch64_ADDVL_XXI = 166, + AArch64_ADDVv16i8v = 167, + AArch64_ADDVv4i16v = 168, + AArch64_ADDVv4i32v = 169, + AArch64_ADDVv8i16v = 170, + AArch64_ADDVv8i8v = 171, + AArch64_ADDWri = 172, + AArch64_ADDWrr = 173, + AArch64_ADDWrs = 174, + AArch64_ADDWrx = 175, + AArch64_ADDXri = 176, + AArch64_ADDXrr = 177, + AArch64_ADDXrs = 178, + AArch64_ADDXrx = 179, + AArch64_ADDXrx64 = 180, + AArch64_ADD_ZI_B = 181, + AArch64_ADD_ZI_D = 182, + AArch64_ADD_ZI_H = 183, + AArch64_ADD_ZI_S = 184, + AArch64_ADD_ZPmZ_B = 185, + AArch64_ADD_ZPmZ_D = 186, + AArch64_ADD_ZPmZ_H = 187, + AArch64_ADD_ZPmZ_S = 188, + AArch64_ADD_ZZZ_B = 189, + AArch64_ADD_ZZZ_D = 190, + AArch64_ADD_ZZZ_H = 191, + AArch64_ADD_ZZZ_S = 192, + AArch64_ADDlowTLS = 193, + AArch64_ADDv16i8 = 194, + AArch64_ADDv1i64 = 195, + AArch64_ADDv2i32 = 196, + AArch64_ADDv2i64 = 197, + AArch64_ADDv4i16 = 198, + AArch64_ADDv4i32 = 199, + AArch64_ADDv8i16 = 200, + AArch64_ADDv8i8 = 201, + AArch64_ADJCALLSTACKDOWN = 202, + AArch64_ADJCALLSTACKUP = 203, + AArch64_ADR = 204, + AArch64_ADRP = 205, + AArch64_ADR_LSL_ZZZ_D_0 = 206, + AArch64_ADR_LSL_ZZZ_D_1 = 207, + AArch64_ADR_LSL_ZZZ_D_2 = 208, + AArch64_ADR_LSL_ZZZ_D_3 = 209, + AArch64_ADR_LSL_ZZZ_S_0 = 210, + AArch64_ADR_LSL_ZZZ_S_1 = 211, + AArch64_ADR_LSL_ZZZ_S_2 = 212, + AArch64_ADR_LSL_ZZZ_S_3 = 213, + AArch64_ADR_SXTW_ZZZ_D_0 = 214, + AArch64_ADR_SXTW_ZZZ_D_1 = 215, + AArch64_ADR_SXTW_ZZZ_D_2 = 216, + AArch64_ADR_SXTW_ZZZ_D_3 = 217, + AArch64_ADR_UXTW_ZZZ_D_0 = 218, + AArch64_ADR_UXTW_ZZZ_D_1 = 219, + AArch64_ADR_UXTW_ZZZ_D_2 = 220, + AArch64_ADR_UXTW_ZZZ_D_3 = 221, + AArch64_AESDrr = 222, + AArch64_AESErr = 223, + AArch64_AESIMCrr = 224, + AArch64_AESIMCrrTied = 225, + AArch64_AESMCrr = 226, + AArch64_AESMCrrTied = 227, + AArch64_ANDSWri = 228, + AArch64_ANDSWrr = 229, + AArch64_ANDSWrs = 230, + AArch64_ANDSXri = 231, + AArch64_ANDSXrr = 232, + AArch64_ANDSXrs = 233, + AArch64_ANDS_PPzPP = 234, + AArch64_ANDV_VPZ_B = 235, + AArch64_ANDV_VPZ_D = 236, + AArch64_ANDV_VPZ_H = 237, + AArch64_ANDV_VPZ_S = 238, + AArch64_ANDWri = 239, + AArch64_ANDWrr = 240, + AArch64_ANDWrs = 241, + AArch64_ANDXri = 242, + AArch64_ANDXrr = 243, + AArch64_ANDXrs = 244, + AArch64_AND_PPzPP = 245, + AArch64_AND_ZI = 246, + AArch64_AND_ZPmZ_B = 247, + AArch64_AND_ZPmZ_D = 248, + AArch64_AND_ZPmZ_H = 249, + AArch64_AND_ZPmZ_S = 250, + AArch64_AND_ZZZ = 251, + AArch64_ANDv16i8 = 252, + AArch64_ANDv8i8 = 253, + AArch64_ASRD_ZPmI_B = 254, + AArch64_ASRD_ZPmI_D = 255, + AArch64_ASRD_ZPmI_H = 256, + AArch64_ASRD_ZPmI_S = 257, + AArch64_ASRR_ZPmZ_B = 258, + AArch64_ASRR_ZPmZ_D = 259, + AArch64_ASRR_ZPmZ_H = 260, + AArch64_ASRR_ZPmZ_S = 261, + AArch64_ASRVWr = 262, + AArch64_ASRVXr = 263, + AArch64_ASR_WIDE_ZPmZ_B = 264, + AArch64_ASR_WIDE_ZPmZ_H = 265, + AArch64_ASR_WIDE_ZPmZ_S = 266, + AArch64_ASR_WIDE_ZZZ_B = 267, + AArch64_ASR_WIDE_ZZZ_H = 268, + AArch64_ASR_WIDE_ZZZ_S = 269, + AArch64_ASR_ZPmI_B = 270, + AArch64_ASR_ZPmI_D = 271, + AArch64_ASR_ZPmI_H = 272, + AArch64_ASR_ZPmI_S = 273, + AArch64_ASR_ZPmZ_B = 274, + AArch64_ASR_ZPmZ_D = 275, + AArch64_ASR_ZPmZ_H = 276, + AArch64_ASR_ZPmZ_S = 277, + AArch64_ASR_ZZI_B = 278, + AArch64_ASR_ZZI_D = 279, + AArch64_ASR_ZZI_H = 280, + AArch64_ASR_ZZI_S = 281, + AArch64_AUTDA = 282, + AArch64_AUTDB = 283, + AArch64_AUTDZA = 284, + AArch64_AUTDZB = 285, + AArch64_AUTIA = 286, + AArch64_AUTIA1716 = 287, + AArch64_AUTIASP = 288, + AArch64_AUTIAZ = 289, + AArch64_AUTIB = 290, + AArch64_AUTIB1716 = 291, + AArch64_AUTIBSP = 292, + AArch64_AUTIBZ = 293, + AArch64_AUTIZA = 294, + AArch64_AUTIZB = 295, + AArch64_B = 296, + AArch64_BCAX = 297, + AArch64_BFMWri = 298, + AArch64_BFMXri = 299, + AArch64_BICSWrr = 300, + AArch64_BICSWrs = 301, + AArch64_BICSXrr = 302, + AArch64_BICSXrs = 303, + AArch64_BICS_PPzPP = 304, + AArch64_BICWrr = 305, + AArch64_BICWrs = 306, + AArch64_BICXrr = 307, + AArch64_BICXrs = 308, + AArch64_BIC_PPzPP = 309, + AArch64_BIC_ZPmZ_B = 310, + AArch64_BIC_ZPmZ_D = 311, + AArch64_BIC_ZPmZ_H = 312, + AArch64_BIC_ZPmZ_S = 313, + AArch64_BIC_ZZZ = 314, + AArch64_BICv16i8 = 315, + AArch64_BICv2i32 = 316, + AArch64_BICv4i16 = 317, + AArch64_BICv4i32 = 318, + AArch64_BICv8i16 = 319, + AArch64_BICv8i8 = 320, + AArch64_BIFv16i8 = 321, + AArch64_BIFv8i8 = 322, + AArch64_BITv16i8 = 323, + AArch64_BITv8i8 = 324, + AArch64_BL = 325, + AArch64_BLR = 326, + AArch64_BLRAA = 327, + AArch64_BLRAAZ = 328, + AArch64_BLRAB = 329, + AArch64_BLRABZ = 330, + AArch64_BR = 331, + AArch64_BRAA = 332, + AArch64_BRAAZ = 333, + AArch64_BRAB = 334, + AArch64_BRABZ = 335, + AArch64_BRK = 336, + AArch64_BRKAS_PPzP = 337, + AArch64_BRKA_PPmP = 338, + AArch64_BRKA_PPzP = 339, + AArch64_BRKBS_PPzP = 340, + AArch64_BRKB_PPmP = 341, + AArch64_BRKB_PPzP = 342, + AArch64_BRKNS_PPzP = 343, + AArch64_BRKN_PPzP = 344, + AArch64_BRKPAS_PPzPP = 345, + AArch64_BRKPA_PPzPP = 346, + AArch64_BRKPBS_PPzPP = 347, + AArch64_BRKPB_PPzPP = 348, + AArch64_BSLv16i8 = 349, + AArch64_BSLv8i8 = 350, + AArch64_Bcc = 351, + AArch64_CASAB = 352, + AArch64_CASAH = 353, + AArch64_CASALB = 354, + AArch64_CASALH = 355, + AArch64_CASALW = 356, + AArch64_CASALX = 357, + AArch64_CASAW = 358, + AArch64_CASAX = 359, + AArch64_CASB = 360, + AArch64_CASH = 361, + AArch64_CASLB = 362, + AArch64_CASLH = 363, + AArch64_CASLW = 364, + AArch64_CASLX = 365, + AArch64_CASPALW = 366, + AArch64_CASPALX = 367, + AArch64_CASPAW = 368, + AArch64_CASPAX = 369, + AArch64_CASPLW = 370, + AArch64_CASPLX = 371, + AArch64_CASPW = 372, + AArch64_CASPX = 373, + AArch64_CASW = 374, + AArch64_CASX = 375, + AArch64_CBNZW = 376, + AArch64_CBNZX = 377, + AArch64_CBZW = 378, + AArch64_CBZX = 379, + AArch64_CCMNWi = 380, + AArch64_CCMNWr = 381, + AArch64_CCMNXi = 382, + AArch64_CCMNXr = 383, + AArch64_CCMPWi = 384, + AArch64_CCMPWr = 385, + AArch64_CCMPXi = 386, + AArch64_CCMPXr = 387, + AArch64_CFINV = 388, + AArch64_CLASTA_RPZ_B = 389, + AArch64_CLASTA_RPZ_D = 390, + AArch64_CLASTA_RPZ_H = 391, + AArch64_CLASTA_RPZ_S = 392, + AArch64_CLASTA_VPZ_B = 393, + AArch64_CLASTA_VPZ_D = 394, + AArch64_CLASTA_VPZ_H = 395, + AArch64_CLASTA_VPZ_S = 396, + AArch64_CLASTA_ZPZ_B = 397, + AArch64_CLASTA_ZPZ_D = 398, + AArch64_CLASTA_ZPZ_H = 399, + AArch64_CLASTA_ZPZ_S = 400, + AArch64_CLASTB_RPZ_B = 401, + AArch64_CLASTB_RPZ_D = 402, + AArch64_CLASTB_RPZ_H = 403, + AArch64_CLASTB_RPZ_S = 404, + AArch64_CLASTB_VPZ_B = 405, + AArch64_CLASTB_VPZ_D = 406, + AArch64_CLASTB_VPZ_H = 407, + AArch64_CLASTB_VPZ_S = 408, + AArch64_CLASTB_ZPZ_B = 409, + AArch64_CLASTB_ZPZ_D = 410, + AArch64_CLASTB_ZPZ_H = 411, + AArch64_CLASTB_ZPZ_S = 412, + AArch64_CLREX = 413, + AArch64_CLSWr = 414, + AArch64_CLSXr = 415, + AArch64_CLS_ZPmZ_B = 416, + AArch64_CLS_ZPmZ_D = 417, + AArch64_CLS_ZPmZ_H = 418, + AArch64_CLS_ZPmZ_S = 419, + AArch64_CLSv16i8 = 420, + AArch64_CLSv2i32 = 421, + AArch64_CLSv4i16 = 422, + AArch64_CLSv4i32 = 423, + AArch64_CLSv8i16 = 424, + AArch64_CLSv8i8 = 425, + AArch64_CLZWr = 426, + AArch64_CLZXr = 427, + AArch64_CLZ_ZPmZ_B = 428, + AArch64_CLZ_ZPmZ_D = 429, + AArch64_CLZ_ZPmZ_H = 430, + AArch64_CLZ_ZPmZ_S = 431, + AArch64_CLZv16i8 = 432, + AArch64_CLZv2i32 = 433, + AArch64_CLZv4i16 = 434, + AArch64_CLZv4i32 = 435, + AArch64_CLZv8i16 = 436, + AArch64_CLZv8i8 = 437, + AArch64_CMEQv16i8 = 438, + AArch64_CMEQv16i8rz = 439, + AArch64_CMEQv1i64 = 440, + AArch64_CMEQv1i64rz = 441, + AArch64_CMEQv2i32 = 442, + AArch64_CMEQv2i32rz = 443, + AArch64_CMEQv2i64 = 444, + AArch64_CMEQv2i64rz = 445, + AArch64_CMEQv4i16 = 446, + AArch64_CMEQv4i16rz = 447, + AArch64_CMEQv4i32 = 448, + AArch64_CMEQv4i32rz = 449, + AArch64_CMEQv8i16 = 450, + AArch64_CMEQv8i16rz = 451, + AArch64_CMEQv8i8 = 452, + AArch64_CMEQv8i8rz = 453, + AArch64_CMGEv16i8 = 454, + AArch64_CMGEv16i8rz = 455, + AArch64_CMGEv1i64 = 456, + AArch64_CMGEv1i64rz = 457, + AArch64_CMGEv2i32 = 458, + AArch64_CMGEv2i32rz = 459, + AArch64_CMGEv2i64 = 460, + AArch64_CMGEv2i64rz = 461, + AArch64_CMGEv4i16 = 462, + AArch64_CMGEv4i16rz = 463, + AArch64_CMGEv4i32 = 464, + AArch64_CMGEv4i32rz = 465, + AArch64_CMGEv8i16 = 466, + AArch64_CMGEv8i16rz = 467, + AArch64_CMGEv8i8 = 468, + AArch64_CMGEv8i8rz = 469, + AArch64_CMGTv16i8 = 470, + AArch64_CMGTv16i8rz = 471, + AArch64_CMGTv1i64 = 472, + AArch64_CMGTv1i64rz = 473, + AArch64_CMGTv2i32 = 474, + AArch64_CMGTv2i32rz = 475, + AArch64_CMGTv2i64 = 476, + AArch64_CMGTv2i64rz = 477, + AArch64_CMGTv4i16 = 478, + AArch64_CMGTv4i16rz = 479, + AArch64_CMGTv4i32 = 480, + AArch64_CMGTv4i32rz = 481, + AArch64_CMGTv8i16 = 482, + AArch64_CMGTv8i16rz = 483, + AArch64_CMGTv8i8 = 484, + AArch64_CMGTv8i8rz = 485, + AArch64_CMHIv16i8 = 486, + AArch64_CMHIv1i64 = 487, + AArch64_CMHIv2i32 = 488, + AArch64_CMHIv2i64 = 489, + AArch64_CMHIv4i16 = 490, + AArch64_CMHIv4i32 = 491, + AArch64_CMHIv8i16 = 492, + AArch64_CMHIv8i8 = 493, + AArch64_CMHSv16i8 = 494, + AArch64_CMHSv1i64 = 495, + AArch64_CMHSv2i32 = 496, + AArch64_CMHSv2i64 = 497, + AArch64_CMHSv4i16 = 498, + AArch64_CMHSv4i32 = 499, + AArch64_CMHSv8i16 = 500, + AArch64_CMHSv8i8 = 501, + AArch64_CMLEv16i8rz = 502, + AArch64_CMLEv1i64rz = 503, + AArch64_CMLEv2i32rz = 504, + AArch64_CMLEv2i64rz = 505, + AArch64_CMLEv4i16rz = 506, + AArch64_CMLEv4i32rz = 507, + AArch64_CMLEv8i16rz = 508, + AArch64_CMLEv8i8rz = 509, + AArch64_CMLTv16i8rz = 510, + AArch64_CMLTv1i64rz = 511, + AArch64_CMLTv2i32rz = 512, + AArch64_CMLTv2i64rz = 513, + AArch64_CMLTv4i16rz = 514, + AArch64_CMLTv4i32rz = 515, + AArch64_CMLTv8i16rz = 516, + AArch64_CMLTv8i8rz = 517, + AArch64_CMPEQ_PPzZI_B = 518, + AArch64_CMPEQ_PPzZI_D = 519, + AArch64_CMPEQ_PPzZI_H = 520, + AArch64_CMPEQ_PPzZI_S = 521, + AArch64_CMPEQ_PPzZZ_B = 522, + AArch64_CMPEQ_PPzZZ_D = 523, + AArch64_CMPEQ_PPzZZ_H = 524, + AArch64_CMPEQ_PPzZZ_S = 525, + AArch64_CMPEQ_WIDE_PPzZZ_B = 526, + AArch64_CMPEQ_WIDE_PPzZZ_H = 527, + AArch64_CMPEQ_WIDE_PPzZZ_S = 528, + AArch64_CMPGE_PPzZI_B = 529, + AArch64_CMPGE_PPzZI_D = 530, + AArch64_CMPGE_PPzZI_H = 531, + AArch64_CMPGE_PPzZI_S = 532, + AArch64_CMPGE_PPzZZ_B = 533, + AArch64_CMPGE_PPzZZ_D = 534, + AArch64_CMPGE_PPzZZ_H = 535, + AArch64_CMPGE_PPzZZ_S = 536, + AArch64_CMPGE_WIDE_PPzZZ_B = 537, + AArch64_CMPGE_WIDE_PPzZZ_H = 538, + AArch64_CMPGE_WIDE_PPzZZ_S = 539, + AArch64_CMPGT_PPzZI_B = 540, + AArch64_CMPGT_PPzZI_D = 541, + AArch64_CMPGT_PPzZI_H = 542, + AArch64_CMPGT_PPzZI_S = 543, + AArch64_CMPGT_PPzZZ_B = 544, + AArch64_CMPGT_PPzZZ_D = 545, + AArch64_CMPGT_PPzZZ_H = 546, + AArch64_CMPGT_PPzZZ_S = 547, + AArch64_CMPGT_WIDE_PPzZZ_B = 548, + AArch64_CMPGT_WIDE_PPzZZ_H = 549, + AArch64_CMPGT_WIDE_PPzZZ_S = 550, + AArch64_CMPHI_PPzZI_B = 551, + AArch64_CMPHI_PPzZI_D = 552, + AArch64_CMPHI_PPzZI_H = 553, + AArch64_CMPHI_PPzZI_S = 554, + AArch64_CMPHI_PPzZZ_B = 555, + AArch64_CMPHI_PPzZZ_D = 556, + AArch64_CMPHI_PPzZZ_H = 557, + AArch64_CMPHI_PPzZZ_S = 558, + AArch64_CMPHI_WIDE_PPzZZ_B = 559, + AArch64_CMPHI_WIDE_PPzZZ_H = 560, + AArch64_CMPHI_WIDE_PPzZZ_S = 561, + AArch64_CMPHS_PPzZI_B = 562, + AArch64_CMPHS_PPzZI_D = 563, + AArch64_CMPHS_PPzZI_H = 564, + AArch64_CMPHS_PPzZI_S = 565, + AArch64_CMPHS_PPzZZ_B = 566, + AArch64_CMPHS_PPzZZ_D = 567, + AArch64_CMPHS_PPzZZ_H = 568, + AArch64_CMPHS_PPzZZ_S = 569, + AArch64_CMPHS_WIDE_PPzZZ_B = 570, + AArch64_CMPHS_WIDE_PPzZZ_H = 571, + AArch64_CMPHS_WIDE_PPzZZ_S = 572, + AArch64_CMPLE_PPzZI_B = 573, + AArch64_CMPLE_PPzZI_D = 574, + AArch64_CMPLE_PPzZI_H = 575, + AArch64_CMPLE_PPzZI_S = 576, + AArch64_CMPLE_WIDE_PPzZZ_B = 577, + AArch64_CMPLE_WIDE_PPzZZ_H = 578, + AArch64_CMPLE_WIDE_PPzZZ_S = 579, + AArch64_CMPLO_PPzZI_B = 580, + AArch64_CMPLO_PPzZI_D = 581, + AArch64_CMPLO_PPzZI_H = 582, + AArch64_CMPLO_PPzZI_S = 583, + AArch64_CMPLO_WIDE_PPzZZ_B = 584, + AArch64_CMPLO_WIDE_PPzZZ_H = 585, + AArch64_CMPLO_WIDE_PPzZZ_S = 586, + AArch64_CMPLS_PPzZI_B = 587, + AArch64_CMPLS_PPzZI_D = 588, + AArch64_CMPLS_PPzZI_H = 589, + AArch64_CMPLS_PPzZI_S = 590, + AArch64_CMPLS_WIDE_PPzZZ_B = 591, + AArch64_CMPLS_WIDE_PPzZZ_H = 592, + AArch64_CMPLS_WIDE_PPzZZ_S = 593, + AArch64_CMPLT_PPzZI_B = 594, + AArch64_CMPLT_PPzZI_D = 595, + AArch64_CMPLT_PPzZI_H = 596, + AArch64_CMPLT_PPzZI_S = 597, + AArch64_CMPLT_WIDE_PPzZZ_B = 598, + AArch64_CMPLT_WIDE_PPzZZ_H = 599, + AArch64_CMPLT_WIDE_PPzZZ_S = 600, + AArch64_CMPNE_PPzZI_B = 601, + AArch64_CMPNE_PPzZI_D = 602, + AArch64_CMPNE_PPzZI_H = 603, + AArch64_CMPNE_PPzZI_S = 604, + AArch64_CMPNE_PPzZZ_B = 605, + AArch64_CMPNE_PPzZZ_D = 606, + AArch64_CMPNE_PPzZZ_H = 607, + AArch64_CMPNE_PPzZZ_S = 608, + AArch64_CMPNE_WIDE_PPzZZ_B = 609, + AArch64_CMPNE_WIDE_PPzZZ_H = 610, + AArch64_CMPNE_WIDE_PPzZZ_S = 611, + AArch64_CMP_SWAP_128 = 612, + AArch64_CMP_SWAP_16 = 613, + AArch64_CMP_SWAP_32 = 614, + AArch64_CMP_SWAP_64 = 615, + AArch64_CMP_SWAP_8 = 616, + AArch64_CMTSTv16i8 = 617, + AArch64_CMTSTv1i64 = 618, + AArch64_CMTSTv2i32 = 619, + AArch64_CMTSTv2i64 = 620, + AArch64_CMTSTv4i16 = 621, + AArch64_CMTSTv4i32 = 622, + AArch64_CMTSTv8i16 = 623, + AArch64_CMTSTv8i8 = 624, + AArch64_CNOT_ZPmZ_B = 625, + AArch64_CNOT_ZPmZ_D = 626, + AArch64_CNOT_ZPmZ_H = 627, + AArch64_CNOT_ZPmZ_S = 628, + AArch64_CNTB_XPiI = 629, + AArch64_CNTD_XPiI = 630, + AArch64_CNTH_XPiI = 631, + AArch64_CNTP_XPP_B = 632, + AArch64_CNTP_XPP_D = 633, + AArch64_CNTP_XPP_H = 634, + AArch64_CNTP_XPP_S = 635, + AArch64_CNTW_XPiI = 636, + AArch64_CNT_ZPmZ_B = 637, + AArch64_CNT_ZPmZ_D = 638, + AArch64_CNT_ZPmZ_H = 639, + AArch64_CNT_ZPmZ_S = 640, + AArch64_CNTv16i8 = 641, + AArch64_CNTv8i8 = 642, + AArch64_COMPACT_ZPZ_D = 643, + AArch64_COMPACT_ZPZ_S = 644, + AArch64_CPY_ZPmI_B = 645, + AArch64_CPY_ZPmI_D = 646, + AArch64_CPY_ZPmI_H = 647, + AArch64_CPY_ZPmI_S = 648, + AArch64_CPY_ZPmR_B = 649, + AArch64_CPY_ZPmR_D = 650, + AArch64_CPY_ZPmR_H = 651, + AArch64_CPY_ZPmR_S = 652, + AArch64_CPY_ZPmV_B = 653, + AArch64_CPY_ZPmV_D = 654, + AArch64_CPY_ZPmV_H = 655, + AArch64_CPY_ZPmV_S = 656, + AArch64_CPY_ZPzI_B = 657, + AArch64_CPY_ZPzI_D = 658, + AArch64_CPY_ZPzI_H = 659, + AArch64_CPY_ZPzI_S = 660, + AArch64_CPYi16 = 661, + AArch64_CPYi32 = 662, + AArch64_CPYi64 = 663, + AArch64_CPYi8 = 664, + AArch64_CRC32Brr = 665, + AArch64_CRC32CBrr = 666, + AArch64_CRC32CHrr = 667, + AArch64_CRC32CWrr = 668, + AArch64_CRC32CXrr = 669, + AArch64_CRC32Hrr = 670, + AArch64_CRC32Wrr = 671, + AArch64_CRC32Xrr = 672, + AArch64_CSELWr = 673, + AArch64_CSELXr = 674, + AArch64_CSINCWr = 675, + AArch64_CSINCXr = 676, + AArch64_CSINVWr = 677, + AArch64_CSINVXr = 678, + AArch64_CSNEGWr = 679, + AArch64_CSNEGXr = 680, + AArch64_CTERMEQ_WW = 681, + AArch64_CTERMEQ_XX = 682, + AArch64_CTERMNE_WW = 683, + AArch64_CTERMNE_XX = 684, + AArch64_CompilerBarrier = 685, + AArch64_DCPS1 = 686, + AArch64_DCPS2 = 687, + AArch64_DCPS3 = 688, + AArch64_DECB_XPiI = 689, + AArch64_DECD_XPiI = 690, + AArch64_DECD_ZPiI = 691, + AArch64_DECH_XPiI = 692, + AArch64_DECH_ZPiI = 693, + AArch64_DECP_XP_B = 694, + AArch64_DECP_XP_D = 695, + AArch64_DECP_XP_H = 696, + AArch64_DECP_XP_S = 697, + AArch64_DECP_ZP_D = 698, + AArch64_DECP_ZP_H = 699, + AArch64_DECP_ZP_S = 700, + AArch64_DECW_XPiI = 701, + AArch64_DECW_ZPiI = 702, + AArch64_DMB = 703, + AArch64_DRPS = 704, + AArch64_DSB = 705, + AArch64_DUPM_ZI = 706, + AArch64_DUP_ZI_B = 707, + AArch64_DUP_ZI_D = 708, + AArch64_DUP_ZI_H = 709, + AArch64_DUP_ZI_S = 710, + AArch64_DUP_ZR_B = 711, + AArch64_DUP_ZR_D = 712, + AArch64_DUP_ZR_H = 713, + AArch64_DUP_ZR_S = 714, + AArch64_DUP_ZZI_B = 715, + AArch64_DUP_ZZI_D = 716, + AArch64_DUP_ZZI_H = 717, + AArch64_DUP_ZZI_Q = 718, + AArch64_DUP_ZZI_S = 719, + AArch64_DUPv16i8gpr = 720, + AArch64_DUPv16i8lane = 721, + AArch64_DUPv2i32gpr = 722, + AArch64_DUPv2i32lane = 723, + AArch64_DUPv2i64gpr = 724, + AArch64_DUPv2i64lane = 725, + AArch64_DUPv4i16gpr = 726, + AArch64_DUPv4i16lane = 727, + AArch64_DUPv4i32gpr = 728, + AArch64_DUPv4i32lane = 729, + AArch64_DUPv8i16gpr = 730, + AArch64_DUPv8i16lane = 731, + AArch64_DUPv8i8gpr = 732, + AArch64_DUPv8i8lane = 733, + AArch64_EONWrr = 734, + AArch64_EONWrs = 735, + AArch64_EONXrr = 736, + AArch64_EONXrs = 737, + AArch64_EOR3 = 738, + AArch64_EORS_PPzPP = 739, + AArch64_EORV_VPZ_B = 740, + AArch64_EORV_VPZ_D = 741, + AArch64_EORV_VPZ_H = 742, + AArch64_EORV_VPZ_S = 743, + AArch64_EORWri = 744, + AArch64_EORWrr = 745, + AArch64_EORWrs = 746, + AArch64_EORXri = 747, + AArch64_EORXrr = 748, + AArch64_EORXrs = 749, + AArch64_EOR_PPzPP = 750, + AArch64_EOR_ZI = 751, + AArch64_EOR_ZPmZ_B = 752, + AArch64_EOR_ZPmZ_D = 753, + AArch64_EOR_ZPmZ_H = 754, + AArch64_EOR_ZPmZ_S = 755, + AArch64_EOR_ZZZ = 756, + AArch64_EORv16i8 = 757, + AArch64_EORv8i8 = 758, + AArch64_ERET = 759, + AArch64_ERETAA = 760, + AArch64_ERETAB = 761, + AArch64_EXTRWrri = 762, + AArch64_EXTRXrri = 763, + AArch64_EXT_ZZI = 764, + AArch64_EXTv16i8 = 765, + AArch64_EXTv8i8 = 766, + AArch64_F128CSEL = 767, + AArch64_FABD16 = 768, + AArch64_FABD32 = 769, + AArch64_FABD64 = 770, + AArch64_FABD_ZPmZ_D = 771, + AArch64_FABD_ZPmZ_H = 772, + AArch64_FABD_ZPmZ_S = 773, + AArch64_FABDv2f32 = 774, + AArch64_FABDv2f64 = 775, + AArch64_FABDv4f16 = 776, + AArch64_FABDv4f32 = 777, + AArch64_FABDv8f16 = 778, + AArch64_FABSDr = 779, + AArch64_FABSHr = 780, + AArch64_FABSSr = 781, + AArch64_FABS_ZPmZ_D = 782, + AArch64_FABS_ZPmZ_H = 783, + AArch64_FABS_ZPmZ_S = 784, + AArch64_FABSv2f32 = 785, + AArch64_FABSv2f64 = 786, + AArch64_FABSv4f16 = 787, + AArch64_FABSv4f32 = 788, + AArch64_FABSv8f16 = 789, + AArch64_FACGE16 = 790, + AArch64_FACGE32 = 791, + AArch64_FACGE64 = 792, + AArch64_FACGE_PPzZZ_D = 793, + AArch64_FACGE_PPzZZ_H = 794, + AArch64_FACGE_PPzZZ_S = 795, + AArch64_FACGEv2f32 = 796, + AArch64_FACGEv2f64 = 797, + AArch64_FACGEv4f16 = 798, + AArch64_FACGEv4f32 = 799, + AArch64_FACGEv8f16 = 800, + AArch64_FACGT16 = 801, + AArch64_FACGT32 = 802, + AArch64_FACGT64 = 803, + AArch64_FACGT_PPzZZ_D = 804, + AArch64_FACGT_PPzZZ_H = 805, + AArch64_FACGT_PPzZZ_S = 806, + AArch64_FACGTv2f32 = 807, + AArch64_FACGTv2f64 = 808, + AArch64_FACGTv4f16 = 809, + AArch64_FACGTv4f32 = 810, + AArch64_FACGTv8f16 = 811, + AArch64_FADDA_VPZ_D = 812, + AArch64_FADDA_VPZ_H = 813, + AArch64_FADDA_VPZ_S = 814, + AArch64_FADDDrr = 815, + AArch64_FADDHrr = 816, + AArch64_FADDPv2f32 = 817, + AArch64_FADDPv2f64 = 818, + AArch64_FADDPv2i16p = 819, + AArch64_FADDPv2i32p = 820, + AArch64_FADDPv2i64p = 821, + AArch64_FADDPv4f16 = 822, + AArch64_FADDPv4f32 = 823, + AArch64_FADDPv8f16 = 824, + AArch64_FADDSrr = 825, + AArch64_FADDV_VPZ_D = 826, + AArch64_FADDV_VPZ_H = 827, + AArch64_FADDV_VPZ_S = 828, + AArch64_FADD_ZPmI_D = 829, + AArch64_FADD_ZPmI_H = 830, + AArch64_FADD_ZPmI_S = 831, + AArch64_FADD_ZPmZ_D = 832, + AArch64_FADD_ZPmZ_H = 833, + AArch64_FADD_ZPmZ_S = 834, + AArch64_FADD_ZZZ_D = 835, + AArch64_FADD_ZZZ_H = 836, + AArch64_FADD_ZZZ_S = 837, + AArch64_FADDv2f32 = 838, + AArch64_FADDv2f64 = 839, + AArch64_FADDv4f16 = 840, + AArch64_FADDv4f32 = 841, + AArch64_FADDv8f16 = 842, + AArch64_FCADD_ZPmZ_D = 843, + AArch64_FCADD_ZPmZ_H = 844, + AArch64_FCADD_ZPmZ_S = 845, + AArch64_FCADDv2f32 = 846, + AArch64_FCADDv2f64 = 847, + AArch64_FCADDv4f16 = 848, + AArch64_FCADDv4f32 = 849, + AArch64_FCADDv8f16 = 850, + AArch64_FCCMPDrr = 851, + AArch64_FCCMPEDrr = 852, + AArch64_FCCMPEHrr = 853, + AArch64_FCCMPESrr = 854, + AArch64_FCCMPHrr = 855, + AArch64_FCCMPSrr = 856, + AArch64_FCMEQ16 = 857, + AArch64_FCMEQ32 = 858, + AArch64_FCMEQ64 = 859, + AArch64_FCMEQ_PPzZ0_D = 860, + AArch64_FCMEQ_PPzZ0_H = 861, + AArch64_FCMEQ_PPzZ0_S = 862, + AArch64_FCMEQ_PPzZZ_D = 863, + AArch64_FCMEQ_PPzZZ_H = 864, + AArch64_FCMEQ_PPzZZ_S = 865, + AArch64_FCMEQv1i16rz = 866, + AArch64_FCMEQv1i32rz = 867, + AArch64_FCMEQv1i64rz = 868, + AArch64_FCMEQv2f32 = 869, + AArch64_FCMEQv2f64 = 870, + AArch64_FCMEQv2i32rz = 871, + AArch64_FCMEQv2i64rz = 872, + AArch64_FCMEQv4f16 = 873, + AArch64_FCMEQv4f32 = 874, + AArch64_FCMEQv4i16rz = 875, + AArch64_FCMEQv4i32rz = 876, + AArch64_FCMEQv8f16 = 877, + AArch64_FCMEQv8i16rz = 878, + AArch64_FCMGE16 = 879, + AArch64_FCMGE32 = 880, + AArch64_FCMGE64 = 881, + AArch64_FCMGE_PPzZ0_D = 882, + AArch64_FCMGE_PPzZ0_H = 883, + AArch64_FCMGE_PPzZ0_S = 884, + AArch64_FCMGE_PPzZZ_D = 885, + AArch64_FCMGE_PPzZZ_H = 886, + AArch64_FCMGE_PPzZZ_S = 887, + AArch64_FCMGEv1i16rz = 888, + AArch64_FCMGEv1i32rz = 889, + AArch64_FCMGEv1i64rz = 890, + AArch64_FCMGEv2f32 = 891, + AArch64_FCMGEv2f64 = 892, + AArch64_FCMGEv2i32rz = 893, + AArch64_FCMGEv2i64rz = 894, + AArch64_FCMGEv4f16 = 895, + AArch64_FCMGEv4f32 = 896, + AArch64_FCMGEv4i16rz = 897, + AArch64_FCMGEv4i32rz = 898, + AArch64_FCMGEv8f16 = 899, + AArch64_FCMGEv8i16rz = 900, + AArch64_FCMGT16 = 901, + AArch64_FCMGT32 = 902, + AArch64_FCMGT64 = 903, + AArch64_FCMGT_PPzZ0_D = 904, + AArch64_FCMGT_PPzZ0_H = 905, + AArch64_FCMGT_PPzZ0_S = 906, + AArch64_FCMGT_PPzZZ_D = 907, + AArch64_FCMGT_PPzZZ_H = 908, + AArch64_FCMGT_PPzZZ_S = 909, + AArch64_FCMGTv1i16rz = 910, + AArch64_FCMGTv1i32rz = 911, + AArch64_FCMGTv1i64rz = 912, + AArch64_FCMGTv2f32 = 913, + AArch64_FCMGTv2f64 = 914, + AArch64_FCMGTv2i32rz = 915, + AArch64_FCMGTv2i64rz = 916, + AArch64_FCMGTv4f16 = 917, + AArch64_FCMGTv4f32 = 918, + AArch64_FCMGTv4i16rz = 919, + AArch64_FCMGTv4i32rz = 920, + AArch64_FCMGTv8f16 = 921, + AArch64_FCMGTv8i16rz = 922, + AArch64_FCMLA_ZPmZZ_D = 923, + AArch64_FCMLA_ZPmZZ_H = 924, + AArch64_FCMLA_ZPmZZ_S = 925, + AArch64_FCMLA_ZZZI_H = 926, + AArch64_FCMLA_ZZZI_S = 927, + AArch64_FCMLAv2f32 = 928, + AArch64_FCMLAv2f64 = 929, + AArch64_FCMLAv4f16 = 930, + AArch64_FCMLAv4f16_indexed = 931, + AArch64_FCMLAv4f32 = 932, + AArch64_FCMLAv4f32_indexed = 933, + AArch64_FCMLAv8f16 = 934, + AArch64_FCMLAv8f16_indexed = 935, + AArch64_FCMLE_PPzZ0_D = 936, + AArch64_FCMLE_PPzZ0_H = 937, + AArch64_FCMLE_PPzZ0_S = 938, + AArch64_FCMLEv1i16rz = 939, + AArch64_FCMLEv1i32rz = 940, + AArch64_FCMLEv1i64rz = 941, + AArch64_FCMLEv2i32rz = 942, + AArch64_FCMLEv2i64rz = 943, + AArch64_FCMLEv4i16rz = 944, + AArch64_FCMLEv4i32rz = 945, + AArch64_FCMLEv8i16rz = 946, + AArch64_FCMLT_PPzZ0_D = 947, + AArch64_FCMLT_PPzZ0_H = 948, + AArch64_FCMLT_PPzZ0_S = 949, + AArch64_FCMLTv1i16rz = 950, + AArch64_FCMLTv1i32rz = 951, + AArch64_FCMLTv1i64rz = 952, + AArch64_FCMLTv2i32rz = 953, + AArch64_FCMLTv2i64rz = 954, + AArch64_FCMLTv4i16rz = 955, + AArch64_FCMLTv4i32rz = 956, + AArch64_FCMLTv8i16rz = 957, + AArch64_FCMNE_PPzZ0_D = 958, + AArch64_FCMNE_PPzZ0_H = 959, + AArch64_FCMNE_PPzZ0_S = 960, + AArch64_FCMNE_PPzZZ_D = 961, + AArch64_FCMNE_PPzZZ_H = 962, + AArch64_FCMNE_PPzZZ_S = 963, + AArch64_FCMPDri = 964, + AArch64_FCMPDrr = 965, + AArch64_FCMPEDri = 966, + AArch64_FCMPEDrr = 967, + AArch64_FCMPEHri = 968, + AArch64_FCMPEHrr = 969, + AArch64_FCMPESri = 970, + AArch64_FCMPESrr = 971, + AArch64_FCMPHri = 972, + AArch64_FCMPHrr = 973, + AArch64_FCMPSri = 974, + AArch64_FCMPSrr = 975, + AArch64_FCMUO_PPzZZ_D = 976, + AArch64_FCMUO_PPzZZ_H = 977, + AArch64_FCMUO_PPzZZ_S = 978, + AArch64_FCPY_ZPmI_D = 979, + AArch64_FCPY_ZPmI_H = 980, + AArch64_FCPY_ZPmI_S = 981, + AArch64_FCSELDrrr = 982, + AArch64_FCSELHrrr = 983, + AArch64_FCSELSrrr = 984, + AArch64_FCVTASUWDr = 985, + AArch64_FCVTASUWHr = 986, + AArch64_FCVTASUWSr = 987, + AArch64_FCVTASUXDr = 988, + AArch64_FCVTASUXHr = 989, + AArch64_FCVTASUXSr = 990, + AArch64_FCVTASv1f16 = 991, + AArch64_FCVTASv1i32 = 992, + AArch64_FCVTASv1i64 = 993, + AArch64_FCVTASv2f32 = 994, + AArch64_FCVTASv2f64 = 995, + AArch64_FCVTASv4f16 = 996, + AArch64_FCVTASv4f32 = 997, + AArch64_FCVTASv8f16 = 998, + AArch64_FCVTAUUWDr = 999, + AArch64_FCVTAUUWHr = 1000, + AArch64_FCVTAUUWSr = 1001, + AArch64_FCVTAUUXDr = 1002, + AArch64_FCVTAUUXHr = 1003, + AArch64_FCVTAUUXSr = 1004, + AArch64_FCVTAUv1f16 = 1005, + AArch64_FCVTAUv1i32 = 1006, + AArch64_FCVTAUv1i64 = 1007, + AArch64_FCVTAUv2f32 = 1008, + AArch64_FCVTAUv2f64 = 1009, + AArch64_FCVTAUv4f16 = 1010, + AArch64_FCVTAUv4f32 = 1011, + AArch64_FCVTAUv8f16 = 1012, + AArch64_FCVTDHr = 1013, + AArch64_FCVTDSr = 1014, + AArch64_FCVTHDr = 1015, + AArch64_FCVTHSr = 1016, + AArch64_FCVTLv2i32 = 1017, + AArch64_FCVTLv4i16 = 1018, + AArch64_FCVTLv4i32 = 1019, + AArch64_FCVTLv8i16 = 1020, + AArch64_FCVTMSUWDr = 1021, + AArch64_FCVTMSUWHr = 1022, + AArch64_FCVTMSUWSr = 1023, + AArch64_FCVTMSUXDr = 1024, + AArch64_FCVTMSUXHr = 1025, + AArch64_FCVTMSUXSr = 1026, + AArch64_FCVTMSv1f16 = 1027, + AArch64_FCVTMSv1i32 = 1028, + AArch64_FCVTMSv1i64 = 1029, + AArch64_FCVTMSv2f32 = 1030, + AArch64_FCVTMSv2f64 = 1031, + AArch64_FCVTMSv4f16 = 1032, + AArch64_FCVTMSv4f32 = 1033, + AArch64_FCVTMSv8f16 = 1034, + AArch64_FCVTMUUWDr = 1035, + AArch64_FCVTMUUWHr = 1036, + AArch64_FCVTMUUWSr = 1037, + AArch64_FCVTMUUXDr = 1038, + AArch64_FCVTMUUXHr = 1039, + AArch64_FCVTMUUXSr = 1040, + AArch64_FCVTMUv1f16 = 1041, + AArch64_FCVTMUv1i32 = 1042, + AArch64_FCVTMUv1i64 = 1043, + AArch64_FCVTMUv2f32 = 1044, + AArch64_FCVTMUv2f64 = 1045, + AArch64_FCVTMUv4f16 = 1046, + AArch64_FCVTMUv4f32 = 1047, + AArch64_FCVTMUv8f16 = 1048, + AArch64_FCVTNSUWDr = 1049, + AArch64_FCVTNSUWHr = 1050, + AArch64_FCVTNSUWSr = 1051, + AArch64_FCVTNSUXDr = 1052, + AArch64_FCVTNSUXHr = 1053, + AArch64_FCVTNSUXSr = 1054, + AArch64_FCVTNSv1f16 = 1055, + AArch64_FCVTNSv1i32 = 1056, + AArch64_FCVTNSv1i64 = 1057, + AArch64_FCVTNSv2f32 = 1058, + AArch64_FCVTNSv2f64 = 1059, + AArch64_FCVTNSv4f16 = 1060, + AArch64_FCVTNSv4f32 = 1061, + AArch64_FCVTNSv8f16 = 1062, + AArch64_FCVTNUUWDr = 1063, + AArch64_FCVTNUUWHr = 1064, + AArch64_FCVTNUUWSr = 1065, + AArch64_FCVTNUUXDr = 1066, + AArch64_FCVTNUUXHr = 1067, + AArch64_FCVTNUUXSr = 1068, + AArch64_FCVTNUv1f16 = 1069, + AArch64_FCVTNUv1i32 = 1070, + AArch64_FCVTNUv1i64 = 1071, + AArch64_FCVTNUv2f32 = 1072, + AArch64_FCVTNUv2f64 = 1073, + AArch64_FCVTNUv4f16 = 1074, + AArch64_FCVTNUv4f32 = 1075, + AArch64_FCVTNUv8f16 = 1076, + AArch64_FCVTNv2i32 = 1077, + AArch64_FCVTNv4i16 = 1078, + AArch64_FCVTNv4i32 = 1079, + AArch64_FCVTNv8i16 = 1080, + AArch64_FCVTPSUWDr = 1081, + AArch64_FCVTPSUWHr = 1082, + AArch64_FCVTPSUWSr = 1083, + AArch64_FCVTPSUXDr = 1084, + AArch64_FCVTPSUXHr = 1085, + AArch64_FCVTPSUXSr = 1086, + AArch64_FCVTPSv1f16 = 1087, + AArch64_FCVTPSv1i32 = 1088, + AArch64_FCVTPSv1i64 = 1089, + AArch64_FCVTPSv2f32 = 1090, + AArch64_FCVTPSv2f64 = 1091, + AArch64_FCVTPSv4f16 = 1092, + AArch64_FCVTPSv4f32 = 1093, + AArch64_FCVTPSv8f16 = 1094, + AArch64_FCVTPUUWDr = 1095, + AArch64_FCVTPUUWHr = 1096, + AArch64_FCVTPUUWSr = 1097, + AArch64_FCVTPUUXDr = 1098, + AArch64_FCVTPUUXHr = 1099, + AArch64_FCVTPUUXSr = 1100, + AArch64_FCVTPUv1f16 = 1101, + AArch64_FCVTPUv1i32 = 1102, + AArch64_FCVTPUv1i64 = 1103, + AArch64_FCVTPUv2f32 = 1104, + AArch64_FCVTPUv2f64 = 1105, + AArch64_FCVTPUv4f16 = 1106, + AArch64_FCVTPUv4f32 = 1107, + AArch64_FCVTPUv8f16 = 1108, + AArch64_FCVTSDr = 1109, + AArch64_FCVTSHr = 1110, + AArch64_FCVTXNv1i64 = 1111, + AArch64_FCVTXNv2f32 = 1112, + AArch64_FCVTXNv4f32 = 1113, + AArch64_FCVTZSSWDri = 1114, + AArch64_FCVTZSSWHri = 1115, + AArch64_FCVTZSSWSri = 1116, + AArch64_FCVTZSSXDri = 1117, + AArch64_FCVTZSSXHri = 1118, + AArch64_FCVTZSSXSri = 1119, + AArch64_FCVTZSUWDr = 1120, + AArch64_FCVTZSUWHr = 1121, + AArch64_FCVTZSUWSr = 1122, + AArch64_FCVTZSUXDr = 1123, + AArch64_FCVTZSUXHr = 1124, + AArch64_FCVTZSUXSr = 1125, + AArch64_FCVTZS_ZPmZ_DtoD = 1126, + AArch64_FCVTZS_ZPmZ_DtoS = 1127, + AArch64_FCVTZS_ZPmZ_HtoD = 1128, + AArch64_FCVTZS_ZPmZ_HtoH = 1129, + AArch64_FCVTZS_ZPmZ_HtoS = 1130, + AArch64_FCVTZS_ZPmZ_StoD = 1131, + AArch64_FCVTZS_ZPmZ_StoS = 1132, + AArch64_FCVTZSd = 1133, + AArch64_FCVTZSh = 1134, + AArch64_FCVTZSs = 1135, + AArch64_FCVTZSv1f16 = 1136, + AArch64_FCVTZSv1i32 = 1137, + AArch64_FCVTZSv1i64 = 1138, + AArch64_FCVTZSv2f32 = 1139, + AArch64_FCVTZSv2f64 = 1140, + AArch64_FCVTZSv2i32_shift = 1141, + AArch64_FCVTZSv2i64_shift = 1142, + AArch64_FCVTZSv4f16 = 1143, + AArch64_FCVTZSv4f32 = 1144, + AArch64_FCVTZSv4i16_shift = 1145, + AArch64_FCVTZSv4i32_shift = 1146, + AArch64_FCVTZSv8f16 = 1147, + AArch64_FCVTZSv8i16_shift = 1148, + AArch64_FCVTZUSWDri = 1149, + AArch64_FCVTZUSWHri = 1150, + AArch64_FCVTZUSWSri = 1151, + AArch64_FCVTZUSXDri = 1152, + AArch64_FCVTZUSXHri = 1153, + AArch64_FCVTZUSXSri = 1154, + AArch64_FCVTZUUWDr = 1155, + AArch64_FCVTZUUWHr = 1156, + AArch64_FCVTZUUWSr = 1157, + AArch64_FCVTZUUXDr = 1158, + AArch64_FCVTZUUXHr = 1159, + AArch64_FCVTZUUXSr = 1160, + AArch64_FCVTZU_ZPmZ_DtoD = 1161, + AArch64_FCVTZU_ZPmZ_DtoS = 1162, + AArch64_FCVTZU_ZPmZ_HtoD = 1163, + AArch64_FCVTZU_ZPmZ_HtoH = 1164, + AArch64_FCVTZU_ZPmZ_HtoS = 1165, + AArch64_FCVTZU_ZPmZ_StoD = 1166, + AArch64_FCVTZU_ZPmZ_StoS = 1167, + AArch64_FCVTZUd = 1168, + AArch64_FCVTZUh = 1169, + AArch64_FCVTZUs = 1170, + AArch64_FCVTZUv1f16 = 1171, + AArch64_FCVTZUv1i32 = 1172, + AArch64_FCVTZUv1i64 = 1173, + AArch64_FCVTZUv2f32 = 1174, + AArch64_FCVTZUv2f64 = 1175, + AArch64_FCVTZUv2i32_shift = 1176, + AArch64_FCVTZUv2i64_shift = 1177, + AArch64_FCVTZUv4f16 = 1178, + AArch64_FCVTZUv4f32 = 1179, + AArch64_FCVTZUv4i16_shift = 1180, + AArch64_FCVTZUv4i32_shift = 1181, + AArch64_FCVTZUv8f16 = 1182, + AArch64_FCVTZUv8i16_shift = 1183, + AArch64_FCVT_ZPmZ_DtoH = 1184, + AArch64_FCVT_ZPmZ_DtoS = 1185, + AArch64_FCVT_ZPmZ_HtoD = 1186, + AArch64_FCVT_ZPmZ_HtoS = 1187, + AArch64_FCVT_ZPmZ_StoD = 1188, + AArch64_FCVT_ZPmZ_StoH = 1189, + AArch64_FDIVDrr = 1190, + AArch64_FDIVHrr = 1191, + AArch64_FDIVR_ZPmZ_D = 1192, + AArch64_FDIVR_ZPmZ_H = 1193, + AArch64_FDIVR_ZPmZ_S = 1194, + AArch64_FDIVSrr = 1195, + AArch64_FDIV_ZPmZ_D = 1196, + AArch64_FDIV_ZPmZ_H = 1197, + AArch64_FDIV_ZPmZ_S = 1198, + AArch64_FDIVv2f32 = 1199, + AArch64_FDIVv2f64 = 1200, + AArch64_FDIVv4f16 = 1201, + AArch64_FDIVv4f32 = 1202, + AArch64_FDIVv8f16 = 1203, + AArch64_FDUP_ZI_D = 1204, + AArch64_FDUP_ZI_H = 1205, + AArch64_FDUP_ZI_S = 1206, + AArch64_FEXPA_ZZ_D = 1207, + AArch64_FEXPA_ZZ_H = 1208, + AArch64_FEXPA_ZZ_S = 1209, + AArch64_FJCVTZS = 1210, + AArch64_FMADDDrrr = 1211, + AArch64_FMADDHrrr = 1212, + AArch64_FMADDSrrr = 1213, + AArch64_FMAD_ZPmZZ_D = 1214, + AArch64_FMAD_ZPmZZ_H = 1215, + AArch64_FMAD_ZPmZZ_S = 1216, + AArch64_FMAXDrr = 1217, + AArch64_FMAXHrr = 1218, + AArch64_FMAXNMDrr = 1219, + AArch64_FMAXNMHrr = 1220, + AArch64_FMAXNMPv2f32 = 1221, + AArch64_FMAXNMPv2f64 = 1222, + AArch64_FMAXNMPv2i16p = 1223, + AArch64_FMAXNMPv2i32p = 1224, + AArch64_FMAXNMPv2i64p = 1225, + AArch64_FMAXNMPv4f16 = 1226, + AArch64_FMAXNMPv4f32 = 1227, + AArch64_FMAXNMPv8f16 = 1228, + AArch64_FMAXNMSrr = 1229, + AArch64_FMAXNMV_VPZ_D = 1230, + AArch64_FMAXNMV_VPZ_H = 1231, + AArch64_FMAXNMV_VPZ_S = 1232, + AArch64_FMAXNMVv4i16v = 1233, + AArch64_FMAXNMVv4i32v = 1234, + AArch64_FMAXNMVv8i16v = 1235, + AArch64_FMAXNM_ZPmI_D = 1236, + AArch64_FMAXNM_ZPmI_H = 1237, + AArch64_FMAXNM_ZPmI_S = 1238, + AArch64_FMAXNM_ZPmZ_D = 1239, + AArch64_FMAXNM_ZPmZ_H = 1240, + AArch64_FMAXNM_ZPmZ_S = 1241, + AArch64_FMAXNMv2f32 = 1242, + AArch64_FMAXNMv2f64 = 1243, + AArch64_FMAXNMv4f16 = 1244, + AArch64_FMAXNMv4f32 = 1245, + AArch64_FMAXNMv8f16 = 1246, + AArch64_FMAXPv2f32 = 1247, + AArch64_FMAXPv2f64 = 1248, + AArch64_FMAXPv2i16p = 1249, + AArch64_FMAXPv2i32p = 1250, + AArch64_FMAXPv2i64p = 1251, + AArch64_FMAXPv4f16 = 1252, + AArch64_FMAXPv4f32 = 1253, + AArch64_FMAXPv8f16 = 1254, + AArch64_FMAXSrr = 1255, + AArch64_FMAXV_VPZ_D = 1256, + AArch64_FMAXV_VPZ_H = 1257, + AArch64_FMAXV_VPZ_S = 1258, + AArch64_FMAXVv4i16v = 1259, + AArch64_FMAXVv4i32v = 1260, + AArch64_FMAXVv8i16v = 1261, + AArch64_FMAX_ZPmI_D = 1262, + AArch64_FMAX_ZPmI_H = 1263, + AArch64_FMAX_ZPmI_S = 1264, + AArch64_FMAX_ZPmZ_D = 1265, + AArch64_FMAX_ZPmZ_H = 1266, + AArch64_FMAX_ZPmZ_S = 1267, + AArch64_FMAXv2f32 = 1268, + AArch64_FMAXv2f64 = 1269, + AArch64_FMAXv4f16 = 1270, + AArch64_FMAXv4f32 = 1271, + AArch64_FMAXv8f16 = 1272, + AArch64_FMINDrr = 1273, + AArch64_FMINHrr = 1274, + AArch64_FMINNMDrr = 1275, + AArch64_FMINNMHrr = 1276, + AArch64_FMINNMPv2f32 = 1277, + AArch64_FMINNMPv2f64 = 1278, + AArch64_FMINNMPv2i16p = 1279, + AArch64_FMINNMPv2i32p = 1280, + AArch64_FMINNMPv2i64p = 1281, + AArch64_FMINNMPv4f16 = 1282, + AArch64_FMINNMPv4f32 = 1283, + AArch64_FMINNMPv8f16 = 1284, + AArch64_FMINNMSrr = 1285, + AArch64_FMINNMV_VPZ_D = 1286, + AArch64_FMINNMV_VPZ_H = 1287, + AArch64_FMINNMV_VPZ_S = 1288, + AArch64_FMINNMVv4i16v = 1289, + AArch64_FMINNMVv4i32v = 1290, + AArch64_FMINNMVv8i16v = 1291, + AArch64_FMINNM_ZPmI_D = 1292, + AArch64_FMINNM_ZPmI_H = 1293, + AArch64_FMINNM_ZPmI_S = 1294, + AArch64_FMINNM_ZPmZ_D = 1295, + AArch64_FMINNM_ZPmZ_H = 1296, + AArch64_FMINNM_ZPmZ_S = 1297, + AArch64_FMINNMv2f32 = 1298, + AArch64_FMINNMv2f64 = 1299, + AArch64_FMINNMv4f16 = 1300, + AArch64_FMINNMv4f32 = 1301, + AArch64_FMINNMv8f16 = 1302, + AArch64_FMINPv2f32 = 1303, + AArch64_FMINPv2f64 = 1304, + AArch64_FMINPv2i16p = 1305, + AArch64_FMINPv2i32p = 1306, + AArch64_FMINPv2i64p = 1307, + AArch64_FMINPv4f16 = 1308, + AArch64_FMINPv4f32 = 1309, + AArch64_FMINPv8f16 = 1310, + AArch64_FMINSrr = 1311, + AArch64_FMINV_VPZ_D = 1312, + AArch64_FMINV_VPZ_H = 1313, + AArch64_FMINV_VPZ_S = 1314, + AArch64_FMINVv4i16v = 1315, + AArch64_FMINVv4i32v = 1316, + AArch64_FMINVv8i16v = 1317, + AArch64_FMIN_ZPmI_D = 1318, + AArch64_FMIN_ZPmI_H = 1319, + AArch64_FMIN_ZPmI_S = 1320, + AArch64_FMIN_ZPmZ_D = 1321, + AArch64_FMIN_ZPmZ_H = 1322, + AArch64_FMIN_ZPmZ_S = 1323, + AArch64_FMINv2f32 = 1324, + AArch64_FMINv2f64 = 1325, + AArch64_FMINv4f16 = 1326, + AArch64_FMINv4f32 = 1327, + AArch64_FMINv8f16 = 1328, + AArch64_FMLA_ZPmZZ_D = 1329, + AArch64_FMLA_ZPmZZ_H = 1330, + AArch64_FMLA_ZPmZZ_S = 1331, + AArch64_FMLA_ZZZI_D = 1332, + AArch64_FMLA_ZZZI_H = 1333, + AArch64_FMLA_ZZZI_S = 1334, + AArch64_FMLAv1i16_indexed = 1335, + AArch64_FMLAv1i32_indexed = 1336, + AArch64_FMLAv1i64_indexed = 1337, + AArch64_FMLAv2f32 = 1338, + AArch64_FMLAv2f64 = 1339, + AArch64_FMLAv2i32_indexed = 1340, + AArch64_FMLAv2i64_indexed = 1341, + AArch64_FMLAv4f16 = 1342, + AArch64_FMLAv4f32 = 1343, + AArch64_FMLAv4i16_indexed = 1344, + AArch64_FMLAv4i32_indexed = 1345, + AArch64_FMLAv8f16 = 1346, + AArch64_FMLAv8i16_indexed = 1347, + AArch64_FMLS_ZPmZZ_D = 1348, + AArch64_FMLS_ZPmZZ_H = 1349, + AArch64_FMLS_ZPmZZ_S = 1350, + AArch64_FMLS_ZZZI_D = 1351, + AArch64_FMLS_ZZZI_H = 1352, + AArch64_FMLS_ZZZI_S = 1353, + AArch64_FMLSv1i16_indexed = 1354, + AArch64_FMLSv1i32_indexed = 1355, + AArch64_FMLSv1i64_indexed = 1356, + AArch64_FMLSv2f32 = 1357, + AArch64_FMLSv2f64 = 1358, + AArch64_FMLSv2i32_indexed = 1359, + AArch64_FMLSv2i64_indexed = 1360, + AArch64_FMLSv4f16 = 1361, + AArch64_FMLSv4f32 = 1362, + AArch64_FMLSv4i16_indexed = 1363, + AArch64_FMLSv4i32_indexed = 1364, + AArch64_FMLSv8f16 = 1365, + AArch64_FMLSv8i16_indexed = 1366, + AArch64_FMOVD0 = 1367, + AArch64_FMOVDXHighr = 1368, + AArch64_FMOVDXr = 1369, + AArch64_FMOVDi = 1370, + AArch64_FMOVDr = 1371, + AArch64_FMOVH0 = 1372, + AArch64_FMOVHWr = 1373, + AArch64_FMOVHXr = 1374, + AArch64_FMOVHi = 1375, + AArch64_FMOVHr = 1376, + AArch64_FMOVS0 = 1377, + AArch64_FMOVSWr = 1378, + AArch64_FMOVSi = 1379, + AArch64_FMOVSr = 1380, + AArch64_FMOVWHr = 1381, + AArch64_FMOVWSr = 1382, + AArch64_FMOVXDHighr = 1383, + AArch64_FMOVXDr = 1384, + AArch64_FMOVXHr = 1385, + AArch64_FMOVv2f32_ns = 1386, + AArch64_FMOVv2f64_ns = 1387, + AArch64_FMOVv4f16_ns = 1388, + AArch64_FMOVv4f32_ns = 1389, + AArch64_FMOVv8f16_ns = 1390, + AArch64_FMSB_ZPmZZ_D = 1391, + AArch64_FMSB_ZPmZZ_H = 1392, + AArch64_FMSB_ZPmZZ_S = 1393, + AArch64_FMSUBDrrr = 1394, + AArch64_FMSUBHrrr = 1395, + AArch64_FMSUBSrrr = 1396, + AArch64_FMULDrr = 1397, + AArch64_FMULHrr = 1398, + AArch64_FMULSrr = 1399, + AArch64_FMULX16 = 1400, + AArch64_FMULX32 = 1401, + AArch64_FMULX64 = 1402, + AArch64_FMULX_ZPmZ_D = 1403, + AArch64_FMULX_ZPmZ_H = 1404, + AArch64_FMULX_ZPmZ_S = 1405, + AArch64_FMULXv1i16_indexed = 1406, + AArch64_FMULXv1i32_indexed = 1407, + AArch64_FMULXv1i64_indexed = 1408, + AArch64_FMULXv2f32 = 1409, + AArch64_FMULXv2f64 = 1410, + AArch64_FMULXv2i32_indexed = 1411, + AArch64_FMULXv2i64_indexed = 1412, + AArch64_FMULXv4f16 = 1413, + AArch64_FMULXv4f32 = 1414, + AArch64_FMULXv4i16_indexed = 1415, + AArch64_FMULXv4i32_indexed = 1416, + AArch64_FMULXv8f16 = 1417, + AArch64_FMULXv8i16_indexed = 1418, + AArch64_FMUL_ZPmI_D = 1419, + AArch64_FMUL_ZPmI_H = 1420, + AArch64_FMUL_ZPmI_S = 1421, + AArch64_FMUL_ZPmZ_D = 1422, + AArch64_FMUL_ZPmZ_H = 1423, + AArch64_FMUL_ZPmZ_S = 1424, + AArch64_FMUL_ZZZI_D = 1425, + AArch64_FMUL_ZZZI_H = 1426, + AArch64_FMUL_ZZZI_S = 1427, + AArch64_FMUL_ZZZ_D = 1428, + AArch64_FMUL_ZZZ_H = 1429, + AArch64_FMUL_ZZZ_S = 1430, + AArch64_FMULv1i16_indexed = 1431, + AArch64_FMULv1i32_indexed = 1432, + AArch64_FMULv1i64_indexed = 1433, + AArch64_FMULv2f32 = 1434, + AArch64_FMULv2f64 = 1435, + AArch64_FMULv2i32_indexed = 1436, + AArch64_FMULv2i64_indexed = 1437, + AArch64_FMULv4f16 = 1438, + AArch64_FMULv4f32 = 1439, + AArch64_FMULv4i16_indexed = 1440, + AArch64_FMULv4i32_indexed = 1441, + AArch64_FMULv8f16 = 1442, + AArch64_FMULv8i16_indexed = 1443, + AArch64_FNEGDr = 1444, + AArch64_FNEGHr = 1445, + AArch64_FNEGSr = 1446, + AArch64_FNEG_ZPmZ_D = 1447, + AArch64_FNEG_ZPmZ_H = 1448, + AArch64_FNEG_ZPmZ_S = 1449, + AArch64_FNEGv2f32 = 1450, + AArch64_FNEGv2f64 = 1451, + AArch64_FNEGv4f16 = 1452, + AArch64_FNEGv4f32 = 1453, + AArch64_FNEGv8f16 = 1454, + AArch64_FNMADDDrrr = 1455, + AArch64_FNMADDHrrr = 1456, + AArch64_FNMADDSrrr = 1457, + AArch64_FNMAD_ZPmZZ_D = 1458, + AArch64_FNMAD_ZPmZZ_H = 1459, + AArch64_FNMAD_ZPmZZ_S = 1460, + AArch64_FNMLA_ZPmZZ_D = 1461, + AArch64_FNMLA_ZPmZZ_H = 1462, + AArch64_FNMLA_ZPmZZ_S = 1463, + AArch64_FNMLS_ZPmZZ_D = 1464, + AArch64_FNMLS_ZPmZZ_H = 1465, + AArch64_FNMLS_ZPmZZ_S = 1466, + AArch64_FNMSB_ZPmZZ_D = 1467, + AArch64_FNMSB_ZPmZZ_H = 1468, + AArch64_FNMSB_ZPmZZ_S = 1469, + AArch64_FNMSUBDrrr = 1470, + AArch64_FNMSUBHrrr = 1471, + AArch64_FNMSUBSrrr = 1472, + AArch64_FNMULDrr = 1473, + AArch64_FNMULHrr = 1474, + AArch64_FNMULSrr = 1475, + AArch64_FRECPE_ZZ_D = 1476, + AArch64_FRECPE_ZZ_H = 1477, + AArch64_FRECPE_ZZ_S = 1478, + AArch64_FRECPEv1f16 = 1479, + AArch64_FRECPEv1i32 = 1480, + AArch64_FRECPEv1i64 = 1481, + AArch64_FRECPEv2f32 = 1482, + AArch64_FRECPEv2f64 = 1483, + AArch64_FRECPEv4f16 = 1484, + AArch64_FRECPEv4f32 = 1485, + AArch64_FRECPEv8f16 = 1486, + AArch64_FRECPS16 = 1487, + AArch64_FRECPS32 = 1488, + AArch64_FRECPS64 = 1489, + AArch64_FRECPS_ZZZ_D = 1490, + AArch64_FRECPS_ZZZ_H = 1491, + AArch64_FRECPS_ZZZ_S = 1492, + AArch64_FRECPSv2f32 = 1493, + AArch64_FRECPSv2f64 = 1494, + AArch64_FRECPSv4f16 = 1495, + AArch64_FRECPSv4f32 = 1496, + AArch64_FRECPSv8f16 = 1497, + AArch64_FRECPX_ZPmZ_D = 1498, + AArch64_FRECPX_ZPmZ_H = 1499, + AArch64_FRECPX_ZPmZ_S = 1500, + AArch64_FRECPXv1f16 = 1501, + AArch64_FRECPXv1i32 = 1502, + AArch64_FRECPXv1i64 = 1503, + AArch64_FRINTADr = 1504, + AArch64_FRINTAHr = 1505, + AArch64_FRINTASr = 1506, + AArch64_FRINTA_ZPmZ_D = 1507, + AArch64_FRINTA_ZPmZ_H = 1508, + AArch64_FRINTA_ZPmZ_S = 1509, + AArch64_FRINTAv2f32 = 1510, + AArch64_FRINTAv2f64 = 1511, + AArch64_FRINTAv4f16 = 1512, + AArch64_FRINTAv4f32 = 1513, + AArch64_FRINTAv8f16 = 1514, + AArch64_FRINTIDr = 1515, + AArch64_FRINTIHr = 1516, + AArch64_FRINTISr = 1517, + AArch64_FRINTI_ZPmZ_D = 1518, + AArch64_FRINTI_ZPmZ_H = 1519, + AArch64_FRINTI_ZPmZ_S = 1520, + AArch64_FRINTIv2f32 = 1521, + AArch64_FRINTIv2f64 = 1522, + AArch64_FRINTIv4f16 = 1523, + AArch64_FRINTIv4f32 = 1524, + AArch64_FRINTIv8f16 = 1525, + AArch64_FRINTMDr = 1526, + AArch64_FRINTMHr = 1527, + AArch64_FRINTMSr = 1528, + AArch64_FRINTM_ZPmZ_D = 1529, + AArch64_FRINTM_ZPmZ_H = 1530, + AArch64_FRINTM_ZPmZ_S = 1531, + AArch64_FRINTMv2f32 = 1532, + AArch64_FRINTMv2f64 = 1533, + AArch64_FRINTMv4f16 = 1534, + AArch64_FRINTMv4f32 = 1535, + AArch64_FRINTMv8f16 = 1536, + AArch64_FRINTNDr = 1537, + AArch64_FRINTNHr = 1538, + AArch64_FRINTNSr = 1539, + AArch64_FRINTN_ZPmZ_D = 1540, + AArch64_FRINTN_ZPmZ_H = 1541, + AArch64_FRINTN_ZPmZ_S = 1542, + AArch64_FRINTNv2f32 = 1543, + AArch64_FRINTNv2f64 = 1544, + AArch64_FRINTNv4f16 = 1545, + AArch64_FRINTNv4f32 = 1546, + AArch64_FRINTNv8f16 = 1547, + AArch64_FRINTPDr = 1548, + AArch64_FRINTPHr = 1549, + AArch64_FRINTPSr = 1550, + AArch64_FRINTP_ZPmZ_D = 1551, + AArch64_FRINTP_ZPmZ_H = 1552, + AArch64_FRINTP_ZPmZ_S = 1553, + AArch64_FRINTPv2f32 = 1554, + AArch64_FRINTPv2f64 = 1555, + AArch64_FRINTPv4f16 = 1556, + AArch64_FRINTPv4f32 = 1557, + AArch64_FRINTPv8f16 = 1558, + AArch64_FRINTXDr = 1559, + AArch64_FRINTXHr = 1560, + AArch64_FRINTXSr = 1561, + AArch64_FRINTX_ZPmZ_D = 1562, + AArch64_FRINTX_ZPmZ_H = 1563, + AArch64_FRINTX_ZPmZ_S = 1564, + AArch64_FRINTXv2f32 = 1565, + AArch64_FRINTXv2f64 = 1566, + AArch64_FRINTXv4f16 = 1567, + AArch64_FRINTXv4f32 = 1568, + AArch64_FRINTXv8f16 = 1569, + AArch64_FRINTZDr = 1570, + AArch64_FRINTZHr = 1571, + AArch64_FRINTZSr = 1572, + AArch64_FRINTZ_ZPmZ_D = 1573, + AArch64_FRINTZ_ZPmZ_H = 1574, + AArch64_FRINTZ_ZPmZ_S = 1575, + AArch64_FRINTZv2f32 = 1576, + AArch64_FRINTZv2f64 = 1577, + AArch64_FRINTZv4f16 = 1578, + AArch64_FRINTZv4f32 = 1579, + AArch64_FRINTZv8f16 = 1580, + AArch64_FRSQRTE_ZZ_D = 1581, + AArch64_FRSQRTE_ZZ_H = 1582, + AArch64_FRSQRTE_ZZ_S = 1583, + AArch64_FRSQRTEv1f16 = 1584, + AArch64_FRSQRTEv1i32 = 1585, + AArch64_FRSQRTEv1i64 = 1586, + AArch64_FRSQRTEv2f32 = 1587, + AArch64_FRSQRTEv2f64 = 1588, + AArch64_FRSQRTEv4f16 = 1589, + AArch64_FRSQRTEv4f32 = 1590, + AArch64_FRSQRTEv8f16 = 1591, + AArch64_FRSQRTS16 = 1592, + AArch64_FRSQRTS32 = 1593, + AArch64_FRSQRTS64 = 1594, + AArch64_FRSQRTS_ZZZ_D = 1595, + AArch64_FRSQRTS_ZZZ_H = 1596, + AArch64_FRSQRTS_ZZZ_S = 1597, + AArch64_FRSQRTSv2f32 = 1598, + AArch64_FRSQRTSv2f64 = 1599, + AArch64_FRSQRTSv4f16 = 1600, + AArch64_FRSQRTSv4f32 = 1601, + AArch64_FRSQRTSv8f16 = 1602, + AArch64_FSCALE_ZPmZ_D = 1603, + AArch64_FSCALE_ZPmZ_H = 1604, + AArch64_FSCALE_ZPmZ_S = 1605, + AArch64_FSQRTDr = 1606, + AArch64_FSQRTHr = 1607, + AArch64_FSQRTSr = 1608, + AArch64_FSQRT_ZPmZ_D = 1609, + AArch64_FSQRT_ZPmZ_H = 1610, + AArch64_FSQRT_ZPmZ_S = 1611, + AArch64_FSQRTv2f32 = 1612, + AArch64_FSQRTv2f64 = 1613, + AArch64_FSQRTv4f16 = 1614, + AArch64_FSQRTv4f32 = 1615, + AArch64_FSQRTv8f16 = 1616, + AArch64_FSUBDrr = 1617, + AArch64_FSUBHrr = 1618, + AArch64_FSUBR_ZPmI_D = 1619, + AArch64_FSUBR_ZPmI_H = 1620, + AArch64_FSUBR_ZPmI_S = 1621, + AArch64_FSUBR_ZPmZ_D = 1622, + AArch64_FSUBR_ZPmZ_H = 1623, + AArch64_FSUBR_ZPmZ_S = 1624, + AArch64_FSUBSrr = 1625, + AArch64_FSUB_ZPmI_D = 1626, + AArch64_FSUB_ZPmI_H = 1627, + AArch64_FSUB_ZPmI_S = 1628, + AArch64_FSUB_ZPmZ_D = 1629, + AArch64_FSUB_ZPmZ_H = 1630, + AArch64_FSUB_ZPmZ_S = 1631, + AArch64_FSUB_ZZZ_D = 1632, + AArch64_FSUB_ZZZ_H = 1633, + AArch64_FSUB_ZZZ_S = 1634, + AArch64_FSUBv2f32 = 1635, + AArch64_FSUBv2f64 = 1636, + AArch64_FSUBv4f16 = 1637, + AArch64_FSUBv4f32 = 1638, + AArch64_FSUBv8f16 = 1639, + AArch64_FTMAD_ZZI_D = 1640, + AArch64_FTMAD_ZZI_H = 1641, + AArch64_FTMAD_ZZI_S = 1642, + AArch64_FTSMUL_ZZZ_D = 1643, + AArch64_FTSMUL_ZZZ_H = 1644, + AArch64_FTSMUL_ZZZ_S = 1645, + AArch64_FTSSEL_ZZZ_D = 1646, + AArch64_FTSSEL_ZZZ_H = 1647, + AArch64_FTSSEL_ZZZ_S = 1648, + AArch64_GLD1B_D_IMM_REAL = 1649, + AArch64_GLD1B_D_REAL = 1650, + AArch64_GLD1B_D_SXTW_REAL = 1651, + AArch64_GLD1B_D_UXTW_REAL = 1652, + AArch64_GLD1B_S_IMM_REAL = 1653, + AArch64_GLD1B_S_SXTW_REAL = 1654, + AArch64_GLD1B_S_UXTW_REAL = 1655, + AArch64_GLD1D_IMM_REAL = 1656, + AArch64_GLD1D_REAL = 1657, + AArch64_GLD1D_SCALED_REAL = 1658, + AArch64_GLD1D_SXTW_REAL = 1659, + AArch64_GLD1D_SXTW_SCALED_REAL = 1660, + AArch64_GLD1D_UXTW_REAL = 1661, + AArch64_GLD1D_UXTW_SCALED_REAL = 1662, + AArch64_GLD1H_D_IMM_REAL = 1663, + AArch64_GLD1H_D_REAL = 1664, + AArch64_GLD1H_D_SCALED_REAL = 1665, + AArch64_GLD1H_D_SXTW_REAL = 1666, + AArch64_GLD1H_D_SXTW_SCALED_REAL = 1667, + AArch64_GLD1H_D_UXTW_REAL = 1668, + AArch64_GLD1H_D_UXTW_SCALED_REAL = 1669, + AArch64_GLD1H_S_IMM_REAL = 1670, + AArch64_GLD1H_S_SXTW_REAL = 1671, + AArch64_GLD1H_S_SXTW_SCALED_REAL = 1672, + AArch64_GLD1H_S_UXTW_REAL = 1673, + AArch64_GLD1H_S_UXTW_SCALED_REAL = 1674, + AArch64_GLD1SB_D_IMM_REAL = 1675, + AArch64_GLD1SB_D_REAL = 1676, + AArch64_GLD1SB_D_SXTW_REAL = 1677, + AArch64_GLD1SB_D_UXTW_REAL = 1678, + AArch64_GLD1SB_S_IMM_REAL = 1679, + AArch64_GLD1SB_S_SXTW_REAL = 1680, + AArch64_GLD1SB_S_UXTW_REAL = 1681, + AArch64_GLD1SH_D_IMM_REAL = 1682, + AArch64_GLD1SH_D_REAL = 1683, + AArch64_GLD1SH_D_SCALED_REAL = 1684, + AArch64_GLD1SH_D_SXTW_REAL = 1685, + AArch64_GLD1SH_D_SXTW_SCALED_REAL = 1686, + AArch64_GLD1SH_D_UXTW_REAL = 1687, + AArch64_GLD1SH_D_UXTW_SCALED_REAL = 1688, + AArch64_GLD1SH_S_IMM_REAL = 1689, + AArch64_GLD1SH_S_SXTW_REAL = 1690, + AArch64_GLD1SH_S_SXTW_SCALED_REAL = 1691, + AArch64_GLD1SH_S_UXTW_REAL = 1692, + AArch64_GLD1SH_S_UXTW_SCALED_REAL = 1693, + AArch64_GLD1SW_D_IMM_REAL = 1694, + AArch64_GLD1SW_D_REAL = 1695, + AArch64_GLD1SW_D_SCALED_REAL = 1696, + AArch64_GLD1SW_D_SXTW_REAL = 1697, + AArch64_GLD1SW_D_SXTW_SCALED_REAL = 1698, + AArch64_GLD1SW_D_UXTW_REAL = 1699, + AArch64_GLD1SW_D_UXTW_SCALED_REAL = 1700, + AArch64_GLD1W_D_IMM_REAL = 1701, + AArch64_GLD1W_D_REAL = 1702, + AArch64_GLD1W_D_SCALED_REAL = 1703, + AArch64_GLD1W_D_SXTW_REAL = 1704, + AArch64_GLD1W_D_SXTW_SCALED_REAL = 1705, + AArch64_GLD1W_D_UXTW_REAL = 1706, + AArch64_GLD1W_D_UXTW_SCALED_REAL = 1707, + AArch64_GLD1W_IMM_REAL = 1708, + AArch64_GLD1W_SXTW_REAL = 1709, + AArch64_GLD1W_SXTW_SCALED_REAL = 1710, + AArch64_GLD1W_UXTW_REAL = 1711, + AArch64_GLD1W_UXTW_SCALED_REAL = 1712, + AArch64_GLDFF1B_D_IMM_REAL = 1713, + AArch64_GLDFF1B_D_REAL = 1714, + AArch64_GLDFF1B_D_SXTW_REAL = 1715, + AArch64_GLDFF1B_D_UXTW_REAL = 1716, + AArch64_GLDFF1B_S_IMM_REAL = 1717, + AArch64_GLDFF1B_S_SXTW_REAL = 1718, + AArch64_GLDFF1B_S_UXTW_REAL = 1719, + AArch64_GLDFF1D_IMM_REAL = 1720, + AArch64_GLDFF1D_REAL = 1721, + AArch64_GLDFF1D_SCALED_REAL = 1722, + AArch64_GLDFF1D_SXTW_REAL = 1723, + AArch64_GLDFF1D_SXTW_SCALED_REAL = 1724, + AArch64_GLDFF1D_UXTW_REAL = 1725, + AArch64_GLDFF1D_UXTW_SCALED_REAL = 1726, + AArch64_GLDFF1H_D_IMM_REAL = 1727, + AArch64_GLDFF1H_D_REAL = 1728, + AArch64_GLDFF1H_D_SCALED_REAL = 1729, + AArch64_GLDFF1H_D_SXTW_REAL = 1730, + AArch64_GLDFF1H_D_SXTW_SCALED_REAL = 1731, + AArch64_GLDFF1H_D_UXTW_REAL = 1732, + AArch64_GLDFF1H_D_UXTW_SCALED_REAL = 1733, + AArch64_GLDFF1H_S_IMM_REAL = 1734, + AArch64_GLDFF1H_S_SXTW_REAL = 1735, + AArch64_GLDFF1H_S_SXTW_SCALED_REAL = 1736, + AArch64_GLDFF1H_S_UXTW_REAL = 1737, + AArch64_GLDFF1H_S_UXTW_SCALED_REAL = 1738, + AArch64_GLDFF1SB_D_IMM_REAL = 1739, + AArch64_GLDFF1SB_D_REAL = 1740, + AArch64_GLDFF1SB_D_SXTW_REAL = 1741, + AArch64_GLDFF1SB_D_UXTW_REAL = 1742, + AArch64_GLDFF1SB_S_IMM_REAL = 1743, + AArch64_GLDFF1SB_S_SXTW_REAL = 1744, + AArch64_GLDFF1SB_S_UXTW_REAL = 1745, + AArch64_GLDFF1SH_D_IMM_REAL = 1746, + AArch64_GLDFF1SH_D_REAL = 1747, + AArch64_GLDFF1SH_D_SCALED_REAL = 1748, + AArch64_GLDFF1SH_D_SXTW_REAL = 1749, + AArch64_GLDFF1SH_D_SXTW_SCALED_REAL = 1750, + AArch64_GLDFF1SH_D_UXTW_REAL = 1751, + AArch64_GLDFF1SH_D_UXTW_SCALED_REAL = 1752, + AArch64_GLDFF1SH_S_IMM_REAL = 1753, + AArch64_GLDFF1SH_S_SXTW_REAL = 1754, + AArch64_GLDFF1SH_S_SXTW_SCALED_REAL = 1755, + AArch64_GLDFF1SH_S_UXTW_REAL = 1756, + AArch64_GLDFF1SH_S_UXTW_SCALED_REAL = 1757, + AArch64_GLDFF1SW_D_IMM_REAL = 1758, + AArch64_GLDFF1SW_D_REAL = 1759, + AArch64_GLDFF1SW_D_SCALED_REAL = 1760, + AArch64_GLDFF1SW_D_SXTW_REAL = 1761, + AArch64_GLDFF1SW_D_SXTW_SCALED_REAL = 1762, + AArch64_GLDFF1SW_D_UXTW_REAL = 1763, + AArch64_GLDFF1SW_D_UXTW_SCALED_REAL = 1764, + AArch64_GLDFF1W_D_IMM_REAL = 1765, + AArch64_GLDFF1W_D_REAL = 1766, + AArch64_GLDFF1W_D_SCALED_REAL = 1767, + AArch64_GLDFF1W_D_SXTW_REAL = 1768, + AArch64_GLDFF1W_D_SXTW_SCALED_REAL = 1769, + AArch64_GLDFF1W_D_UXTW_REAL = 1770, + AArch64_GLDFF1W_D_UXTW_SCALED_REAL = 1771, + AArch64_GLDFF1W_IMM_REAL = 1772, + AArch64_GLDFF1W_SXTW_REAL = 1773, + AArch64_GLDFF1W_SXTW_SCALED_REAL = 1774, + AArch64_GLDFF1W_UXTW_REAL = 1775, + AArch64_GLDFF1W_UXTW_SCALED_REAL = 1776, + AArch64_HINT = 1777, + AArch64_HLT = 1778, + AArch64_HVC = 1779, + AArch64_INCB_XPiI = 1780, + AArch64_INCD_XPiI = 1781, + AArch64_INCD_ZPiI = 1782, + AArch64_INCH_XPiI = 1783, + AArch64_INCH_ZPiI = 1784, + AArch64_INCP_XP_B = 1785, + AArch64_INCP_XP_D = 1786, + AArch64_INCP_XP_H = 1787, + AArch64_INCP_XP_S = 1788, + AArch64_INCP_ZP_D = 1789, + AArch64_INCP_ZP_H = 1790, + AArch64_INCP_ZP_S = 1791, + AArch64_INCW_XPiI = 1792, + AArch64_INCW_ZPiI = 1793, + AArch64_INDEX_II_B = 1794, + AArch64_INDEX_II_D = 1795, + AArch64_INDEX_II_H = 1796, + AArch64_INDEX_II_S = 1797, + AArch64_INDEX_IR_B = 1798, + AArch64_INDEX_IR_D = 1799, + AArch64_INDEX_IR_H = 1800, + AArch64_INDEX_IR_S = 1801, + AArch64_INDEX_RI_B = 1802, + AArch64_INDEX_RI_D = 1803, + AArch64_INDEX_RI_H = 1804, + AArch64_INDEX_RI_S = 1805, + AArch64_INDEX_RR_B = 1806, + AArch64_INDEX_RR_D = 1807, + AArch64_INDEX_RR_H = 1808, + AArch64_INDEX_RR_S = 1809, + AArch64_INSR_ZR_B = 1810, + AArch64_INSR_ZR_D = 1811, + AArch64_INSR_ZR_H = 1812, + AArch64_INSR_ZR_S = 1813, + AArch64_INSR_ZV_B = 1814, + AArch64_INSR_ZV_D = 1815, + AArch64_INSR_ZV_H = 1816, + AArch64_INSR_ZV_S = 1817, + AArch64_INSvi16gpr = 1818, + AArch64_INSvi16lane = 1819, + AArch64_INSvi32gpr = 1820, + AArch64_INSvi32lane = 1821, + AArch64_INSvi64gpr = 1822, + AArch64_INSvi64lane = 1823, + AArch64_INSvi8gpr = 1824, + AArch64_INSvi8lane = 1825, + AArch64_ISB = 1826, + AArch64_LASTA_RPZ_B = 1827, + AArch64_LASTA_RPZ_D = 1828, + AArch64_LASTA_RPZ_H = 1829, + AArch64_LASTA_RPZ_S = 1830, + AArch64_LASTA_VPZ_B = 1831, + AArch64_LASTA_VPZ_D = 1832, + AArch64_LASTA_VPZ_H = 1833, + AArch64_LASTA_VPZ_S = 1834, + AArch64_LASTB_RPZ_B = 1835, + AArch64_LASTB_RPZ_D = 1836, + AArch64_LASTB_RPZ_H = 1837, + AArch64_LASTB_RPZ_S = 1838, + AArch64_LASTB_VPZ_B = 1839, + AArch64_LASTB_VPZ_D = 1840, + AArch64_LASTB_VPZ_H = 1841, + AArch64_LASTB_VPZ_S = 1842, + AArch64_LD1B = 1843, + AArch64_LD1B_D = 1844, + AArch64_LD1B_D_IMM_REAL = 1845, + AArch64_LD1B_H = 1846, + AArch64_LD1B_H_IMM_REAL = 1847, + AArch64_LD1B_IMM_REAL = 1848, + AArch64_LD1B_S = 1849, + AArch64_LD1B_S_IMM_REAL = 1850, + AArch64_LD1D = 1851, + AArch64_LD1D_IMM_REAL = 1852, + AArch64_LD1Fourv16b = 1853, + AArch64_LD1Fourv16b_POST = 1854, + AArch64_LD1Fourv1d = 1855, + AArch64_LD1Fourv1d_POST = 1856, + AArch64_LD1Fourv2d = 1857, + AArch64_LD1Fourv2d_POST = 1858, + AArch64_LD1Fourv2s = 1859, + AArch64_LD1Fourv2s_POST = 1860, + AArch64_LD1Fourv4h = 1861, + AArch64_LD1Fourv4h_POST = 1862, + AArch64_LD1Fourv4s = 1863, + AArch64_LD1Fourv4s_POST = 1864, + AArch64_LD1Fourv8b = 1865, + AArch64_LD1Fourv8b_POST = 1866, + AArch64_LD1Fourv8h = 1867, + AArch64_LD1Fourv8h_POST = 1868, + AArch64_LD1H = 1869, + AArch64_LD1H_D = 1870, + AArch64_LD1H_D_IMM_REAL = 1871, + AArch64_LD1H_IMM_REAL = 1872, + AArch64_LD1H_S = 1873, + AArch64_LD1H_S_IMM_REAL = 1874, + AArch64_LD1Onev16b = 1875, + AArch64_LD1Onev16b_POST = 1876, + AArch64_LD1Onev1d = 1877, + AArch64_LD1Onev1d_POST = 1878, + AArch64_LD1Onev2d = 1879, + AArch64_LD1Onev2d_POST = 1880, + AArch64_LD1Onev2s = 1881, + AArch64_LD1Onev2s_POST = 1882, + AArch64_LD1Onev4h = 1883, + AArch64_LD1Onev4h_POST = 1884, + AArch64_LD1Onev4s = 1885, + AArch64_LD1Onev4s_POST = 1886, + AArch64_LD1Onev8b = 1887, + AArch64_LD1Onev8b_POST = 1888, + AArch64_LD1Onev8h = 1889, + AArch64_LD1Onev8h_POST = 1890, + AArch64_LD1RB_D_IMM = 1891, + AArch64_LD1RB_H_IMM = 1892, + AArch64_LD1RB_IMM = 1893, + AArch64_LD1RB_S_IMM = 1894, + AArch64_LD1RD_IMM = 1895, + AArch64_LD1RH_D_IMM = 1896, + AArch64_LD1RH_IMM = 1897, + AArch64_LD1RH_S_IMM = 1898, + AArch64_LD1RQ_B = 1899, + AArch64_LD1RQ_B_IMM = 1900, + AArch64_LD1RQ_D = 1901, + AArch64_LD1RQ_D_IMM = 1902, + AArch64_LD1RQ_H = 1903, + AArch64_LD1RQ_H_IMM = 1904, + AArch64_LD1RQ_W = 1905, + AArch64_LD1RQ_W_IMM = 1906, + AArch64_LD1RSB_D_IMM = 1907, + AArch64_LD1RSB_H_IMM = 1908, + AArch64_LD1RSB_S_IMM = 1909, + AArch64_LD1RSH_D_IMM = 1910, + AArch64_LD1RSH_S_IMM = 1911, + AArch64_LD1RSW_IMM = 1912, + AArch64_LD1RW_D_IMM = 1913, + AArch64_LD1RW_IMM = 1914, + AArch64_LD1Rv16b = 1915, + AArch64_LD1Rv16b_POST = 1916, + AArch64_LD1Rv1d = 1917, + AArch64_LD1Rv1d_POST = 1918, + AArch64_LD1Rv2d = 1919, + AArch64_LD1Rv2d_POST = 1920, + AArch64_LD1Rv2s = 1921, + AArch64_LD1Rv2s_POST = 1922, + AArch64_LD1Rv4h = 1923, + AArch64_LD1Rv4h_POST = 1924, + AArch64_LD1Rv4s = 1925, + AArch64_LD1Rv4s_POST = 1926, + AArch64_LD1Rv8b = 1927, + AArch64_LD1Rv8b_POST = 1928, + AArch64_LD1Rv8h = 1929, + AArch64_LD1Rv8h_POST = 1930, + AArch64_LD1SB_D = 1931, + AArch64_LD1SB_D_IMM_REAL = 1932, + AArch64_LD1SB_H = 1933, + AArch64_LD1SB_H_IMM_REAL = 1934, + AArch64_LD1SB_S = 1935, + AArch64_LD1SB_S_IMM_REAL = 1936, + AArch64_LD1SH_D = 1937, + AArch64_LD1SH_D_IMM_REAL = 1938, + AArch64_LD1SH_S = 1939, + AArch64_LD1SH_S_IMM_REAL = 1940, + AArch64_LD1SW_D = 1941, + AArch64_LD1SW_D_IMM_REAL = 1942, + AArch64_LD1Threev16b = 1943, + AArch64_LD1Threev16b_POST = 1944, + AArch64_LD1Threev1d = 1945, + AArch64_LD1Threev1d_POST = 1946, + AArch64_LD1Threev2d = 1947, + AArch64_LD1Threev2d_POST = 1948, + AArch64_LD1Threev2s = 1949, + AArch64_LD1Threev2s_POST = 1950, + AArch64_LD1Threev4h = 1951, + AArch64_LD1Threev4h_POST = 1952, + AArch64_LD1Threev4s = 1953, + AArch64_LD1Threev4s_POST = 1954, + AArch64_LD1Threev8b = 1955, + AArch64_LD1Threev8b_POST = 1956, + AArch64_LD1Threev8h = 1957, + AArch64_LD1Threev8h_POST = 1958, + AArch64_LD1Twov16b = 1959, + AArch64_LD1Twov16b_POST = 1960, + AArch64_LD1Twov1d = 1961, + AArch64_LD1Twov1d_POST = 1962, + AArch64_LD1Twov2d = 1963, + AArch64_LD1Twov2d_POST = 1964, + AArch64_LD1Twov2s = 1965, + AArch64_LD1Twov2s_POST = 1966, + AArch64_LD1Twov4h = 1967, + AArch64_LD1Twov4h_POST = 1968, + AArch64_LD1Twov4s = 1969, + AArch64_LD1Twov4s_POST = 1970, + AArch64_LD1Twov8b = 1971, + AArch64_LD1Twov8b_POST = 1972, + AArch64_LD1Twov8h = 1973, + AArch64_LD1Twov8h_POST = 1974, + AArch64_LD1W = 1975, + AArch64_LD1W_D = 1976, + AArch64_LD1W_D_IMM_REAL = 1977, + AArch64_LD1W_IMM_REAL = 1978, + AArch64_LD1i16 = 1979, + AArch64_LD1i16_POST = 1980, + AArch64_LD1i32 = 1981, + AArch64_LD1i32_POST = 1982, + AArch64_LD1i64 = 1983, + AArch64_LD1i64_POST = 1984, + AArch64_LD1i8 = 1985, + AArch64_LD1i8_POST = 1986, + AArch64_LD2B = 1987, + AArch64_LD2B_IMM = 1988, + AArch64_LD2D = 1989, + AArch64_LD2D_IMM = 1990, + AArch64_LD2H = 1991, + AArch64_LD2H_IMM = 1992, + AArch64_LD2Rv16b = 1993, + AArch64_LD2Rv16b_POST = 1994, + AArch64_LD2Rv1d = 1995, + AArch64_LD2Rv1d_POST = 1996, + AArch64_LD2Rv2d = 1997, + AArch64_LD2Rv2d_POST = 1998, + AArch64_LD2Rv2s = 1999, + AArch64_LD2Rv2s_POST = 2000, + AArch64_LD2Rv4h = 2001, + AArch64_LD2Rv4h_POST = 2002, + AArch64_LD2Rv4s = 2003, + AArch64_LD2Rv4s_POST = 2004, + AArch64_LD2Rv8b = 2005, + AArch64_LD2Rv8b_POST = 2006, + AArch64_LD2Rv8h = 2007, + AArch64_LD2Rv8h_POST = 2008, + AArch64_LD2Twov16b = 2009, + AArch64_LD2Twov16b_POST = 2010, + AArch64_LD2Twov2d = 2011, + AArch64_LD2Twov2d_POST = 2012, + AArch64_LD2Twov2s = 2013, + AArch64_LD2Twov2s_POST = 2014, + AArch64_LD2Twov4h = 2015, + AArch64_LD2Twov4h_POST = 2016, + AArch64_LD2Twov4s = 2017, + AArch64_LD2Twov4s_POST = 2018, + AArch64_LD2Twov8b = 2019, + AArch64_LD2Twov8b_POST = 2020, + AArch64_LD2Twov8h = 2021, + AArch64_LD2Twov8h_POST = 2022, + AArch64_LD2W = 2023, + AArch64_LD2W_IMM = 2024, + AArch64_LD2i16 = 2025, + AArch64_LD2i16_POST = 2026, + AArch64_LD2i32 = 2027, + AArch64_LD2i32_POST = 2028, + AArch64_LD2i64 = 2029, + AArch64_LD2i64_POST = 2030, + AArch64_LD2i8 = 2031, + AArch64_LD2i8_POST = 2032, + AArch64_LD3B = 2033, + AArch64_LD3B_IMM = 2034, + AArch64_LD3D = 2035, + AArch64_LD3D_IMM = 2036, + AArch64_LD3H = 2037, + AArch64_LD3H_IMM = 2038, + AArch64_LD3Rv16b = 2039, + AArch64_LD3Rv16b_POST = 2040, + AArch64_LD3Rv1d = 2041, + AArch64_LD3Rv1d_POST = 2042, + AArch64_LD3Rv2d = 2043, + AArch64_LD3Rv2d_POST = 2044, + AArch64_LD3Rv2s = 2045, + AArch64_LD3Rv2s_POST = 2046, + AArch64_LD3Rv4h = 2047, + AArch64_LD3Rv4h_POST = 2048, + AArch64_LD3Rv4s = 2049, + AArch64_LD3Rv4s_POST = 2050, + AArch64_LD3Rv8b = 2051, + AArch64_LD3Rv8b_POST = 2052, + AArch64_LD3Rv8h = 2053, + AArch64_LD3Rv8h_POST = 2054, + AArch64_LD3Threev16b = 2055, + AArch64_LD3Threev16b_POST = 2056, + AArch64_LD3Threev2d = 2057, + AArch64_LD3Threev2d_POST = 2058, + AArch64_LD3Threev2s = 2059, + AArch64_LD3Threev2s_POST = 2060, + AArch64_LD3Threev4h = 2061, + AArch64_LD3Threev4h_POST = 2062, + AArch64_LD3Threev4s = 2063, + AArch64_LD3Threev4s_POST = 2064, + AArch64_LD3Threev8b = 2065, + AArch64_LD3Threev8b_POST = 2066, + AArch64_LD3Threev8h = 2067, + AArch64_LD3Threev8h_POST = 2068, + AArch64_LD3W = 2069, + AArch64_LD3W_IMM = 2070, + AArch64_LD3i16 = 2071, + AArch64_LD3i16_POST = 2072, + AArch64_LD3i32 = 2073, + AArch64_LD3i32_POST = 2074, + AArch64_LD3i64 = 2075, + AArch64_LD3i64_POST = 2076, + AArch64_LD3i8 = 2077, + AArch64_LD3i8_POST = 2078, + AArch64_LD4B = 2079, + AArch64_LD4B_IMM = 2080, + AArch64_LD4D = 2081, + AArch64_LD4D_IMM = 2082, + AArch64_LD4Fourv16b = 2083, + AArch64_LD4Fourv16b_POST = 2084, + AArch64_LD4Fourv2d = 2085, + AArch64_LD4Fourv2d_POST = 2086, + AArch64_LD4Fourv2s = 2087, + AArch64_LD4Fourv2s_POST = 2088, + AArch64_LD4Fourv4h = 2089, + AArch64_LD4Fourv4h_POST = 2090, + AArch64_LD4Fourv4s = 2091, + AArch64_LD4Fourv4s_POST = 2092, + AArch64_LD4Fourv8b = 2093, + AArch64_LD4Fourv8b_POST = 2094, + AArch64_LD4Fourv8h = 2095, + AArch64_LD4Fourv8h_POST = 2096, + AArch64_LD4H = 2097, + AArch64_LD4H_IMM = 2098, + AArch64_LD4Rv16b = 2099, + AArch64_LD4Rv16b_POST = 2100, + AArch64_LD4Rv1d = 2101, + AArch64_LD4Rv1d_POST = 2102, + AArch64_LD4Rv2d = 2103, + AArch64_LD4Rv2d_POST = 2104, + AArch64_LD4Rv2s = 2105, + AArch64_LD4Rv2s_POST = 2106, + AArch64_LD4Rv4h = 2107, + AArch64_LD4Rv4h_POST = 2108, + AArch64_LD4Rv4s = 2109, + AArch64_LD4Rv4s_POST = 2110, + AArch64_LD4Rv8b = 2111, + AArch64_LD4Rv8b_POST = 2112, + AArch64_LD4Rv8h = 2113, + AArch64_LD4Rv8h_POST = 2114, + AArch64_LD4W = 2115, + AArch64_LD4W_IMM = 2116, + AArch64_LD4i16 = 2117, + AArch64_LD4i16_POST = 2118, + AArch64_LD4i32 = 2119, + AArch64_LD4i32_POST = 2120, + AArch64_LD4i64 = 2121, + AArch64_LD4i64_POST = 2122, + AArch64_LD4i8 = 2123, + AArch64_LD4i8_POST = 2124, + AArch64_LDADDAB = 2125, + AArch64_LDADDAH = 2126, + AArch64_LDADDALB = 2127, + AArch64_LDADDALH = 2128, + AArch64_LDADDALW = 2129, + AArch64_LDADDALX = 2130, + AArch64_LDADDAW = 2131, + AArch64_LDADDAX = 2132, + AArch64_LDADDB = 2133, + AArch64_LDADDH = 2134, + AArch64_LDADDLB = 2135, + AArch64_LDADDLH = 2136, + AArch64_LDADDLW = 2137, + AArch64_LDADDLX = 2138, + AArch64_LDADDW = 2139, + AArch64_LDADDX = 2140, + AArch64_LDAPRB = 2141, + AArch64_LDAPRH = 2142, + AArch64_LDAPRW = 2143, + AArch64_LDAPRX = 2144, + AArch64_LDAPURBi = 2145, + AArch64_LDAPURHi = 2146, + AArch64_LDAPURSBWi = 2147, + AArch64_LDAPURSBXi = 2148, + AArch64_LDAPURSHWi = 2149, + AArch64_LDAPURSHXi = 2150, + AArch64_LDAPURSWi = 2151, + AArch64_LDAPURXi = 2152, + AArch64_LDAPURi = 2153, + AArch64_LDARB = 2154, + AArch64_LDARH = 2155, + AArch64_LDARW = 2156, + AArch64_LDARX = 2157, + AArch64_LDAXPW = 2158, + AArch64_LDAXPX = 2159, + AArch64_LDAXRB = 2160, + AArch64_LDAXRH = 2161, + AArch64_LDAXRW = 2162, + AArch64_LDAXRX = 2163, + AArch64_LDCLRAB = 2164, + AArch64_LDCLRAH = 2165, + AArch64_LDCLRALB = 2166, + AArch64_LDCLRALH = 2167, + AArch64_LDCLRALW = 2168, + AArch64_LDCLRALX = 2169, + AArch64_LDCLRAW = 2170, + AArch64_LDCLRAX = 2171, + AArch64_LDCLRB = 2172, + AArch64_LDCLRH = 2173, + AArch64_LDCLRLB = 2174, + AArch64_LDCLRLH = 2175, + AArch64_LDCLRLW = 2176, + AArch64_LDCLRLX = 2177, + AArch64_LDCLRW = 2178, + AArch64_LDCLRX = 2179, + AArch64_LDEORAB = 2180, + AArch64_LDEORAH = 2181, + AArch64_LDEORALB = 2182, + AArch64_LDEORALH = 2183, + AArch64_LDEORALW = 2184, + AArch64_LDEORALX = 2185, + AArch64_LDEORAW = 2186, + AArch64_LDEORAX = 2187, + AArch64_LDEORB = 2188, + AArch64_LDEORH = 2189, + AArch64_LDEORLB = 2190, + AArch64_LDEORLH = 2191, + AArch64_LDEORLW = 2192, + AArch64_LDEORLX = 2193, + AArch64_LDEORW = 2194, + AArch64_LDEORX = 2195, + AArch64_LDFF1B_D_REAL = 2196, + AArch64_LDFF1B_H_REAL = 2197, + AArch64_LDFF1B_REAL = 2198, + AArch64_LDFF1B_S_REAL = 2199, + AArch64_LDFF1D_REAL = 2200, + AArch64_LDFF1H_D_REAL = 2201, + AArch64_LDFF1H_REAL = 2202, + AArch64_LDFF1H_S_REAL = 2203, + AArch64_LDFF1SB_D_REAL = 2204, + AArch64_LDFF1SB_H_REAL = 2205, + AArch64_LDFF1SB_S_REAL = 2206, + AArch64_LDFF1SH_D_REAL = 2207, + AArch64_LDFF1SH_S_REAL = 2208, + AArch64_LDFF1SW_D_REAL = 2209, + AArch64_LDFF1W_D_REAL = 2210, + AArch64_LDFF1W_REAL = 2211, + AArch64_LDLARB = 2212, + AArch64_LDLARH = 2213, + AArch64_LDLARW = 2214, + AArch64_LDLARX = 2215, + AArch64_LDNF1B_D_IMM_REAL = 2216, + AArch64_LDNF1B_H_IMM_REAL = 2217, + AArch64_LDNF1B_IMM_REAL = 2218, + AArch64_LDNF1B_S_IMM_REAL = 2219, + AArch64_LDNF1D_IMM_REAL = 2220, + AArch64_LDNF1H_D_IMM_REAL = 2221, + AArch64_LDNF1H_IMM_REAL = 2222, + AArch64_LDNF1H_S_IMM_REAL = 2223, + AArch64_LDNF1SB_D_IMM_REAL = 2224, + AArch64_LDNF1SB_H_IMM_REAL = 2225, + AArch64_LDNF1SB_S_IMM_REAL = 2226, + AArch64_LDNF1SH_D_IMM_REAL = 2227, + AArch64_LDNF1SH_S_IMM_REAL = 2228, + AArch64_LDNF1SW_D_IMM_REAL = 2229, + AArch64_LDNF1W_D_IMM_REAL = 2230, + AArch64_LDNF1W_IMM_REAL = 2231, + AArch64_LDNPDi = 2232, + AArch64_LDNPQi = 2233, + AArch64_LDNPSi = 2234, + AArch64_LDNPWi = 2235, + AArch64_LDNPXi = 2236, + AArch64_LDNT1B_ZRI = 2237, + AArch64_LDNT1B_ZRR = 2238, + AArch64_LDNT1D_ZRI = 2239, + AArch64_LDNT1D_ZRR = 2240, + AArch64_LDNT1H_ZRI = 2241, + AArch64_LDNT1H_ZRR = 2242, + AArch64_LDNT1W_ZRI = 2243, + AArch64_LDNT1W_ZRR = 2244, + AArch64_LDPDi = 2245, + AArch64_LDPDpost = 2246, + AArch64_LDPDpre = 2247, + AArch64_LDPQi = 2248, + AArch64_LDPQpost = 2249, + AArch64_LDPQpre = 2250, + AArch64_LDPSWi = 2251, + AArch64_LDPSWpost = 2252, + AArch64_LDPSWpre = 2253, + AArch64_LDPSi = 2254, + AArch64_LDPSpost = 2255, + AArch64_LDPSpre = 2256, + AArch64_LDPWi = 2257, + AArch64_LDPWpost = 2258, + AArch64_LDPWpre = 2259, + AArch64_LDPXi = 2260, + AArch64_LDPXpost = 2261, + AArch64_LDPXpre = 2262, + AArch64_LDRAAindexed = 2263, + AArch64_LDRAAwriteback = 2264, + AArch64_LDRABindexed = 2265, + AArch64_LDRABwriteback = 2266, + AArch64_LDRBBpost = 2267, + AArch64_LDRBBpre = 2268, + AArch64_LDRBBroW = 2269, + AArch64_LDRBBroX = 2270, + AArch64_LDRBBui = 2271, + AArch64_LDRBpost = 2272, + AArch64_LDRBpre = 2273, + AArch64_LDRBroW = 2274, + AArch64_LDRBroX = 2275, + AArch64_LDRBui = 2276, + AArch64_LDRDl = 2277, + AArch64_LDRDpost = 2278, + AArch64_LDRDpre = 2279, + AArch64_LDRDroW = 2280, + AArch64_LDRDroX = 2281, + AArch64_LDRDui = 2282, + AArch64_LDRHHpost = 2283, + AArch64_LDRHHpre = 2284, + AArch64_LDRHHroW = 2285, + AArch64_LDRHHroX = 2286, + AArch64_LDRHHui = 2287, + AArch64_LDRHpost = 2288, + AArch64_LDRHpre = 2289, + AArch64_LDRHroW = 2290, + AArch64_LDRHroX = 2291, + AArch64_LDRHui = 2292, + AArch64_LDRQl = 2293, + AArch64_LDRQpost = 2294, + AArch64_LDRQpre = 2295, + AArch64_LDRQroW = 2296, + AArch64_LDRQroX = 2297, + AArch64_LDRQui = 2298, + AArch64_LDRSBWpost = 2299, + AArch64_LDRSBWpre = 2300, + AArch64_LDRSBWroW = 2301, + AArch64_LDRSBWroX = 2302, + AArch64_LDRSBWui = 2303, + AArch64_LDRSBXpost = 2304, + AArch64_LDRSBXpre = 2305, + AArch64_LDRSBXroW = 2306, + AArch64_LDRSBXroX = 2307, + AArch64_LDRSBXui = 2308, + AArch64_LDRSHWpost = 2309, + AArch64_LDRSHWpre = 2310, + AArch64_LDRSHWroW = 2311, + AArch64_LDRSHWroX = 2312, + AArch64_LDRSHWui = 2313, + AArch64_LDRSHXpost = 2314, + AArch64_LDRSHXpre = 2315, + AArch64_LDRSHXroW = 2316, + AArch64_LDRSHXroX = 2317, + AArch64_LDRSHXui = 2318, + AArch64_LDRSWl = 2319, + AArch64_LDRSWpost = 2320, + AArch64_LDRSWpre = 2321, + AArch64_LDRSWroW = 2322, + AArch64_LDRSWroX = 2323, + AArch64_LDRSWui = 2324, + AArch64_LDRSl = 2325, + AArch64_LDRSpost = 2326, + AArch64_LDRSpre = 2327, + AArch64_LDRSroW = 2328, + AArch64_LDRSroX = 2329, + AArch64_LDRSui = 2330, + AArch64_LDRWl = 2331, + AArch64_LDRWpost = 2332, + AArch64_LDRWpre = 2333, + AArch64_LDRWroW = 2334, + AArch64_LDRWroX = 2335, + AArch64_LDRWui = 2336, + AArch64_LDRXl = 2337, + AArch64_LDRXpost = 2338, + AArch64_LDRXpre = 2339, + AArch64_LDRXroW = 2340, + AArch64_LDRXroX = 2341, + AArch64_LDRXui = 2342, + AArch64_LDR_PXI = 2343, + AArch64_LDR_ZXI = 2344, + AArch64_LDSETAB = 2345, + AArch64_LDSETAH = 2346, + AArch64_LDSETALB = 2347, + AArch64_LDSETALH = 2348, + AArch64_LDSETALW = 2349, + AArch64_LDSETALX = 2350, + AArch64_LDSETAW = 2351, + AArch64_LDSETAX = 2352, + AArch64_LDSETB = 2353, + AArch64_LDSETH = 2354, + AArch64_LDSETLB = 2355, + AArch64_LDSETLH = 2356, + AArch64_LDSETLW = 2357, + AArch64_LDSETLX = 2358, + AArch64_LDSETW = 2359, + AArch64_LDSETX = 2360, + AArch64_LDSMAXAB = 2361, + AArch64_LDSMAXAH = 2362, + AArch64_LDSMAXALB = 2363, + AArch64_LDSMAXALH = 2364, + AArch64_LDSMAXALW = 2365, + AArch64_LDSMAXALX = 2366, + AArch64_LDSMAXAW = 2367, + AArch64_LDSMAXAX = 2368, + AArch64_LDSMAXB = 2369, + AArch64_LDSMAXH = 2370, + AArch64_LDSMAXLB = 2371, + AArch64_LDSMAXLH = 2372, + AArch64_LDSMAXLW = 2373, + AArch64_LDSMAXLX = 2374, + AArch64_LDSMAXW = 2375, + AArch64_LDSMAXX = 2376, + AArch64_LDSMINAB = 2377, + AArch64_LDSMINAH = 2378, + AArch64_LDSMINALB = 2379, + AArch64_LDSMINALH = 2380, + AArch64_LDSMINALW = 2381, + AArch64_LDSMINALX = 2382, + AArch64_LDSMINAW = 2383, + AArch64_LDSMINAX = 2384, + AArch64_LDSMINB = 2385, + AArch64_LDSMINH = 2386, + AArch64_LDSMINLB = 2387, + AArch64_LDSMINLH = 2388, + AArch64_LDSMINLW = 2389, + AArch64_LDSMINLX = 2390, + AArch64_LDSMINW = 2391, + AArch64_LDSMINX = 2392, + AArch64_LDTRBi = 2393, + AArch64_LDTRHi = 2394, + AArch64_LDTRSBWi = 2395, + AArch64_LDTRSBXi = 2396, + AArch64_LDTRSHWi = 2397, + AArch64_LDTRSHXi = 2398, + AArch64_LDTRSWi = 2399, + AArch64_LDTRWi = 2400, + AArch64_LDTRXi = 2401, + AArch64_LDUMAXAB = 2402, + AArch64_LDUMAXAH = 2403, + AArch64_LDUMAXALB = 2404, + AArch64_LDUMAXALH = 2405, + AArch64_LDUMAXALW = 2406, + AArch64_LDUMAXALX = 2407, + AArch64_LDUMAXAW = 2408, + AArch64_LDUMAXAX = 2409, + AArch64_LDUMAXB = 2410, + AArch64_LDUMAXH = 2411, + AArch64_LDUMAXLB = 2412, + AArch64_LDUMAXLH = 2413, + AArch64_LDUMAXLW = 2414, + AArch64_LDUMAXLX = 2415, + AArch64_LDUMAXW = 2416, + AArch64_LDUMAXX = 2417, + AArch64_LDUMINAB = 2418, + AArch64_LDUMINAH = 2419, + AArch64_LDUMINALB = 2420, + AArch64_LDUMINALH = 2421, + AArch64_LDUMINALW = 2422, + AArch64_LDUMINALX = 2423, + AArch64_LDUMINAW = 2424, + AArch64_LDUMINAX = 2425, + AArch64_LDUMINB = 2426, + AArch64_LDUMINH = 2427, + AArch64_LDUMINLB = 2428, + AArch64_LDUMINLH = 2429, + AArch64_LDUMINLW = 2430, + AArch64_LDUMINLX = 2431, + AArch64_LDUMINW = 2432, + AArch64_LDUMINX = 2433, + AArch64_LDURBBi = 2434, + AArch64_LDURBi = 2435, + AArch64_LDURDi = 2436, + AArch64_LDURHHi = 2437, + AArch64_LDURHi = 2438, + AArch64_LDURQi = 2439, + AArch64_LDURSBWi = 2440, + AArch64_LDURSBXi = 2441, + AArch64_LDURSHWi = 2442, + AArch64_LDURSHXi = 2443, + AArch64_LDURSWi = 2444, + AArch64_LDURSi = 2445, + AArch64_LDURWi = 2446, + AArch64_LDURXi = 2447, + AArch64_LDXPW = 2448, + AArch64_LDXPX = 2449, + AArch64_LDXRB = 2450, + AArch64_LDXRH = 2451, + AArch64_LDXRW = 2452, + AArch64_LDXRX = 2453, + AArch64_LOADgot = 2454, + AArch64_LSLR_ZPmZ_B = 2455, + AArch64_LSLR_ZPmZ_D = 2456, + AArch64_LSLR_ZPmZ_H = 2457, + AArch64_LSLR_ZPmZ_S = 2458, + AArch64_LSLVWr = 2459, + AArch64_LSLVXr = 2460, + AArch64_LSL_WIDE_ZPmZ_B = 2461, + AArch64_LSL_WIDE_ZPmZ_H = 2462, + AArch64_LSL_WIDE_ZPmZ_S = 2463, + AArch64_LSL_WIDE_ZZZ_B = 2464, + AArch64_LSL_WIDE_ZZZ_H = 2465, + AArch64_LSL_WIDE_ZZZ_S = 2466, + AArch64_LSL_ZPmI_B = 2467, + AArch64_LSL_ZPmI_D = 2468, + AArch64_LSL_ZPmI_H = 2469, + AArch64_LSL_ZPmI_S = 2470, + AArch64_LSL_ZPmZ_B = 2471, + AArch64_LSL_ZPmZ_D = 2472, + AArch64_LSL_ZPmZ_H = 2473, + AArch64_LSL_ZPmZ_S = 2474, + AArch64_LSL_ZZI_B = 2475, + AArch64_LSL_ZZI_D = 2476, + AArch64_LSL_ZZI_H = 2477, + AArch64_LSL_ZZI_S = 2478, + AArch64_LSRR_ZPmZ_B = 2479, + AArch64_LSRR_ZPmZ_D = 2480, + AArch64_LSRR_ZPmZ_H = 2481, + AArch64_LSRR_ZPmZ_S = 2482, + AArch64_LSRVWr = 2483, + AArch64_LSRVXr = 2484, + AArch64_LSR_WIDE_ZPmZ_B = 2485, + AArch64_LSR_WIDE_ZPmZ_H = 2486, + AArch64_LSR_WIDE_ZPmZ_S = 2487, + AArch64_LSR_WIDE_ZZZ_B = 2488, + AArch64_LSR_WIDE_ZZZ_H = 2489, + AArch64_LSR_WIDE_ZZZ_S = 2490, + AArch64_LSR_ZPmI_B = 2491, + AArch64_LSR_ZPmI_D = 2492, + AArch64_LSR_ZPmI_H = 2493, + AArch64_LSR_ZPmI_S = 2494, + AArch64_LSR_ZPmZ_B = 2495, + AArch64_LSR_ZPmZ_D = 2496, + AArch64_LSR_ZPmZ_H = 2497, + AArch64_LSR_ZPmZ_S = 2498, + AArch64_LSR_ZZI_B = 2499, + AArch64_LSR_ZZI_D = 2500, + AArch64_LSR_ZZI_H = 2501, + AArch64_LSR_ZZI_S = 2502, + AArch64_MADDWrrr = 2503, + AArch64_MADDXrrr = 2504, + AArch64_MAD_ZPmZZ_B = 2505, + AArch64_MAD_ZPmZZ_D = 2506, + AArch64_MAD_ZPmZZ_H = 2507, + AArch64_MAD_ZPmZZ_S = 2508, + AArch64_MLA_ZPmZZ_B = 2509, + AArch64_MLA_ZPmZZ_D = 2510, + AArch64_MLA_ZPmZZ_H = 2511, + AArch64_MLA_ZPmZZ_S = 2512, + AArch64_MLAv16i8 = 2513, + AArch64_MLAv2i32 = 2514, + AArch64_MLAv2i32_indexed = 2515, + AArch64_MLAv4i16 = 2516, + AArch64_MLAv4i16_indexed = 2517, + AArch64_MLAv4i32 = 2518, + AArch64_MLAv4i32_indexed = 2519, + AArch64_MLAv8i16 = 2520, + AArch64_MLAv8i16_indexed = 2521, + AArch64_MLAv8i8 = 2522, + AArch64_MLS_ZPmZZ_B = 2523, + AArch64_MLS_ZPmZZ_D = 2524, + AArch64_MLS_ZPmZZ_H = 2525, + AArch64_MLS_ZPmZZ_S = 2526, + AArch64_MLSv16i8 = 2527, + AArch64_MLSv2i32 = 2528, + AArch64_MLSv2i32_indexed = 2529, + AArch64_MLSv4i16 = 2530, + AArch64_MLSv4i16_indexed = 2531, + AArch64_MLSv4i32 = 2532, + AArch64_MLSv4i32_indexed = 2533, + AArch64_MLSv8i16 = 2534, + AArch64_MLSv8i16_indexed = 2535, + AArch64_MLSv8i8 = 2536, + AArch64_MOVID = 2537, + AArch64_MOVIv16b_ns = 2538, + AArch64_MOVIv2d_ns = 2539, + AArch64_MOVIv2i32 = 2540, + AArch64_MOVIv2s_msl = 2541, + AArch64_MOVIv4i16 = 2542, + AArch64_MOVIv4i32 = 2543, + AArch64_MOVIv4s_msl = 2544, + AArch64_MOVIv8b_ns = 2545, + AArch64_MOVIv8i16 = 2546, + AArch64_MOVKWi = 2547, + AArch64_MOVKXi = 2548, + AArch64_MOVNWi = 2549, + AArch64_MOVNXi = 2550, + AArch64_MOVPRFX_ZPmZ_B = 2551, + AArch64_MOVPRFX_ZPmZ_D = 2552, + AArch64_MOVPRFX_ZPmZ_H = 2553, + AArch64_MOVPRFX_ZPmZ_S = 2554, + AArch64_MOVPRFX_ZPzZ_B = 2555, + AArch64_MOVPRFX_ZPzZ_D = 2556, + AArch64_MOVPRFX_ZPzZ_H = 2557, + AArch64_MOVPRFX_ZPzZ_S = 2558, + AArch64_MOVPRFX_ZZ = 2559, + AArch64_MOVZWi = 2560, + AArch64_MOVZXi = 2561, + AArch64_MOVaddr = 2562, + AArch64_MOVaddrBA = 2563, + AArch64_MOVaddrCP = 2564, + AArch64_MOVaddrEXT = 2565, + AArch64_MOVaddrJT = 2566, + AArch64_MOVaddrTLS = 2567, + AArch64_MOVbaseTLS = 2568, + AArch64_MOVi32imm = 2569, + AArch64_MOVi64imm = 2570, + AArch64_MRS = 2571, + AArch64_MSB_ZPmZZ_B = 2572, + AArch64_MSB_ZPmZZ_D = 2573, + AArch64_MSB_ZPmZZ_H = 2574, + AArch64_MSB_ZPmZZ_S = 2575, + AArch64_MSR = 2576, + AArch64_MSRpstateImm1 = 2577, + AArch64_MSRpstateImm4 = 2578, + AArch64_MSUBWrrr = 2579, + AArch64_MSUBXrrr = 2580, + AArch64_MUL_ZI_B = 2581, + AArch64_MUL_ZI_D = 2582, + AArch64_MUL_ZI_H = 2583, + AArch64_MUL_ZI_S = 2584, + AArch64_MUL_ZPmZ_B = 2585, + AArch64_MUL_ZPmZ_D = 2586, + AArch64_MUL_ZPmZ_H = 2587, + AArch64_MUL_ZPmZ_S = 2588, + AArch64_MULv16i8 = 2589, + AArch64_MULv2i32 = 2590, + AArch64_MULv2i32_indexed = 2591, + AArch64_MULv4i16 = 2592, + AArch64_MULv4i16_indexed = 2593, + AArch64_MULv4i32 = 2594, + AArch64_MULv4i32_indexed = 2595, + AArch64_MULv8i16 = 2596, + AArch64_MULv8i16_indexed = 2597, + AArch64_MULv8i8 = 2598, + AArch64_MVNIv2i32 = 2599, + AArch64_MVNIv2s_msl = 2600, + AArch64_MVNIv4i16 = 2601, + AArch64_MVNIv4i32 = 2602, + AArch64_MVNIv4s_msl = 2603, + AArch64_MVNIv8i16 = 2604, + AArch64_NANDS_PPzPP = 2605, + AArch64_NAND_PPzPP = 2606, + AArch64_NEG_ZPmZ_B = 2607, + AArch64_NEG_ZPmZ_D = 2608, + AArch64_NEG_ZPmZ_H = 2609, + AArch64_NEG_ZPmZ_S = 2610, + AArch64_NEGv16i8 = 2611, + AArch64_NEGv1i64 = 2612, + AArch64_NEGv2i32 = 2613, + AArch64_NEGv2i64 = 2614, + AArch64_NEGv4i16 = 2615, + AArch64_NEGv4i32 = 2616, + AArch64_NEGv8i16 = 2617, + AArch64_NEGv8i8 = 2618, + AArch64_NORS_PPzPP = 2619, + AArch64_NOR_PPzPP = 2620, + AArch64_NOT_ZPmZ_B = 2621, + AArch64_NOT_ZPmZ_D = 2622, + AArch64_NOT_ZPmZ_H = 2623, + AArch64_NOT_ZPmZ_S = 2624, + AArch64_NOTv16i8 = 2625, + AArch64_NOTv8i8 = 2626, + AArch64_ORNS_PPzPP = 2627, + AArch64_ORNWrr = 2628, + AArch64_ORNWrs = 2629, + AArch64_ORNXrr = 2630, + AArch64_ORNXrs = 2631, + AArch64_ORN_PPzPP = 2632, + AArch64_ORNv16i8 = 2633, + AArch64_ORNv8i8 = 2634, + AArch64_ORRS_PPzPP = 2635, + AArch64_ORRWri = 2636, + AArch64_ORRWrr = 2637, + AArch64_ORRWrs = 2638, + AArch64_ORRXri = 2639, + AArch64_ORRXrr = 2640, + AArch64_ORRXrs = 2641, + AArch64_ORR_PPzPP = 2642, + AArch64_ORR_ZI = 2643, + AArch64_ORR_ZPmZ_B = 2644, + AArch64_ORR_ZPmZ_D = 2645, + AArch64_ORR_ZPmZ_H = 2646, + AArch64_ORR_ZPmZ_S = 2647, + AArch64_ORR_ZZZ = 2648, + AArch64_ORRv16i8 = 2649, + AArch64_ORRv2i32 = 2650, + AArch64_ORRv4i16 = 2651, + AArch64_ORRv4i32 = 2652, + AArch64_ORRv8i16 = 2653, + AArch64_ORRv8i8 = 2654, + AArch64_ORV_VPZ_B = 2655, + AArch64_ORV_VPZ_D = 2656, + AArch64_ORV_VPZ_H = 2657, + AArch64_ORV_VPZ_S = 2658, + AArch64_PACDA = 2659, + AArch64_PACDB = 2660, + AArch64_PACDZA = 2661, + AArch64_PACDZB = 2662, + AArch64_PACGA = 2663, + AArch64_PACIA = 2664, + AArch64_PACIA1716 = 2665, + AArch64_PACIASP = 2666, + AArch64_PACIAZ = 2667, + AArch64_PACIB = 2668, + AArch64_PACIB1716 = 2669, + AArch64_PACIBSP = 2670, + AArch64_PACIBZ = 2671, + AArch64_PACIZA = 2672, + AArch64_PACIZB = 2673, + AArch64_PFALSE = 2674, + AArch64_PMULLv16i8 = 2675, + AArch64_PMULLv1i64 = 2676, + AArch64_PMULLv2i64 = 2677, + AArch64_PMULLv8i8 = 2678, + AArch64_PMULv16i8 = 2679, + AArch64_PMULv8i8 = 2680, + AArch64_PNEXT_B = 2681, + AArch64_PNEXT_D = 2682, + AArch64_PNEXT_H = 2683, + AArch64_PNEXT_S = 2684, + AArch64_PRFB_D_PZI = 2685, + AArch64_PRFB_D_SCALED = 2686, + AArch64_PRFB_D_SXTW_SCALED = 2687, + AArch64_PRFB_D_UXTW_SCALED = 2688, + AArch64_PRFB_PRI = 2689, + AArch64_PRFB_PRR = 2690, + AArch64_PRFB_S_PZI = 2691, + AArch64_PRFB_S_SXTW_SCALED = 2692, + AArch64_PRFB_S_UXTW_SCALED = 2693, + AArch64_PRFD_D_PZI = 2694, + AArch64_PRFD_D_SCALED = 2695, + AArch64_PRFD_D_SXTW_SCALED = 2696, + AArch64_PRFD_D_UXTW_SCALED = 2697, + AArch64_PRFD_PRI = 2698, + AArch64_PRFD_PRR = 2699, + AArch64_PRFD_S_PZI = 2700, + AArch64_PRFD_S_SXTW_SCALED = 2701, + AArch64_PRFD_S_UXTW_SCALED = 2702, + AArch64_PRFH_D_PZI = 2703, + AArch64_PRFH_D_SCALED = 2704, + AArch64_PRFH_D_SXTW_SCALED = 2705, + AArch64_PRFH_D_UXTW_SCALED = 2706, + AArch64_PRFH_PRI = 2707, + AArch64_PRFH_PRR = 2708, + AArch64_PRFH_S_PZI = 2709, + AArch64_PRFH_S_SXTW_SCALED = 2710, + AArch64_PRFH_S_UXTW_SCALED = 2711, + AArch64_PRFMl = 2712, + AArch64_PRFMroW = 2713, + AArch64_PRFMroX = 2714, + AArch64_PRFMui = 2715, + AArch64_PRFS_PRR = 2716, + AArch64_PRFUMi = 2717, + AArch64_PRFW_D_PZI = 2718, + AArch64_PRFW_D_SCALED = 2719, + AArch64_PRFW_D_SXTW_SCALED = 2720, + AArch64_PRFW_D_UXTW_SCALED = 2721, + AArch64_PRFW_PRI = 2722, + AArch64_PRFW_S_PZI = 2723, + AArch64_PRFW_S_SXTW_SCALED = 2724, + AArch64_PRFW_S_UXTW_SCALED = 2725, + AArch64_PTEST_PP = 2726, + AArch64_PTRUES_B = 2727, + AArch64_PTRUES_D = 2728, + AArch64_PTRUES_H = 2729, + AArch64_PTRUES_S = 2730, + AArch64_PTRUE_B = 2731, + AArch64_PTRUE_D = 2732, + AArch64_PTRUE_H = 2733, + AArch64_PTRUE_S = 2734, + AArch64_PUNPKHI_PP = 2735, + AArch64_PUNPKLO_PP = 2736, + AArch64_RADDHNv2i64_v2i32 = 2737, + AArch64_RADDHNv2i64_v4i32 = 2738, + AArch64_RADDHNv4i32_v4i16 = 2739, + AArch64_RADDHNv4i32_v8i16 = 2740, + AArch64_RADDHNv8i16_v16i8 = 2741, + AArch64_RADDHNv8i16_v8i8 = 2742, + AArch64_RAX1 = 2743, + AArch64_RBITWr = 2744, + AArch64_RBITXr = 2745, + AArch64_RBIT_ZPmZ_B = 2746, + AArch64_RBIT_ZPmZ_D = 2747, + AArch64_RBIT_ZPmZ_H = 2748, + AArch64_RBIT_ZPmZ_S = 2749, + AArch64_RBITv16i8 = 2750, + AArch64_RBITv8i8 = 2751, + AArch64_RDFFRS_PPz = 2752, + AArch64_RDFFR_P = 2753, + AArch64_RDFFR_PPz = 2754, + AArch64_RDVLI_XI = 2755, + AArch64_RET = 2756, + AArch64_RETAA = 2757, + AArch64_RETAB = 2758, + AArch64_RET_ReallyLR = 2759, + AArch64_REV16Wr = 2760, + AArch64_REV16Xr = 2761, + AArch64_REV16v16i8 = 2762, + AArch64_REV16v8i8 = 2763, + AArch64_REV32Xr = 2764, + AArch64_REV32v16i8 = 2765, + AArch64_REV32v4i16 = 2766, + AArch64_REV32v8i16 = 2767, + AArch64_REV32v8i8 = 2768, + AArch64_REV64v16i8 = 2769, + AArch64_REV64v2i32 = 2770, + AArch64_REV64v4i16 = 2771, + AArch64_REV64v4i32 = 2772, + AArch64_REV64v8i16 = 2773, + AArch64_REV64v8i8 = 2774, + AArch64_REVB_ZPmZ_D = 2775, + AArch64_REVB_ZPmZ_H = 2776, + AArch64_REVB_ZPmZ_S = 2777, + AArch64_REVH_ZPmZ_D = 2778, + AArch64_REVH_ZPmZ_S = 2779, + AArch64_REVW_ZPmZ_D = 2780, + AArch64_REVWr = 2781, + AArch64_REVXr = 2782, + AArch64_REV_PP_B = 2783, + AArch64_REV_PP_D = 2784, + AArch64_REV_PP_H = 2785, + AArch64_REV_PP_S = 2786, + AArch64_REV_ZZ_B = 2787, + AArch64_REV_ZZ_D = 2788, + AArch64_REV_ZZ_H = 2789, + AArch64_REV_ZZ_S = 2790, + AArch64_RMIF = 2791, + AArch64_RORVWr = 2792, + AArch64_RORVXr = 2793, + AArch64_RSHRNv16i8_shift = 2794, + AArch64_RSHRNv2i32_shift = 2795, + AArch64_RSHRNv4i16_shift = 2796, + AArch64_RSHRNv4i32_shift = 2797, + AArch64_RSHRNv8i16_shift = 2798, + AArch64_RSHRNv8i8_shift = 2799, + AArch64_RSUBHNv2i64_v2i32 = 2800, + AArch64_RSUBHNv2i64_v4i32 = 2801, + AArch64_RSUBHNv4i32_v4i16 = 2802, + AArch64_RSUBHNv4i32_v8i16 = 2803, + AArch64_RSUBHNv8i16_v16i8 = 2804, + AArch64_RSUBHNv8i16_v8i8 = 2805, + AArch64_SABALv16i8_v8i16 = 2806, + AArch64_SABALv2i32_v2i64 = 2807, + AArch64_SABALv4i16_v4i32 = 2808, + AArch64_SABALv4i32_v2i64 = 2809, + AArch64_SABALv8i16_v4i32 = 2810, + AArch64_SABALv8i8_v8i16 = 2811, + AArch64_SABAv16i8 = 2812, + AArch64_SABAv2i32 = 2813, + AArch64_SABAv4i16 = 2814, + AArch64_SABAv4i32 = 2815, + AArch64_SABAv8i16 = 2816, + AArch64_SABAv8i8 = 2817, + AArch64_SABDLv16i8_v8i16 = 2818, + AArch64_SABDLv2i32_v2i64 = 2819, + AArch64_SABDLv4i16_v4i32 = 2820, + AArch64_SABDLv4i32_v2i64 = 2821, + AArch64_SABDLv8i16_v4i32 = 2822, + AArch64_SABDLv8i8_v8i16 = 2823, + AArch64_SABD_ZPmZ_B = 2824, + AArch64_SABD_ZPmZ_D = 2825, + AArch64_SABD_ZPmZ_H = 2826, + AArch64_SABD_ZPmZ_S = 2827, + AArch64_SABDv16i8 = 2828, + AArch64_SABDv2i32 = 2829, + AArch64_SABDv4i16 = 2830, + AArch64_SABDv4i32 = 2831, + AArch64_SABDv8i16 = 2832, + AArch64_SABDv8i8 = 2833, + AArch64_SADALPv16i8_v8i16 = 2834, + AArch64_SADALPv2i32_v1i64 = 2835, + AArch64_SADALPv4i16_v2i32 = 2836, + AArch64_SADALPv4i32_v2i64 = 2837, + AArch64_SADALPv8i16_v4i32 = 2838, + AArch64_SADALPv8i8_v4i16 = 2839, + AArch64_SADDLPv16i8_v8i16 = 2840, + AArch64_SADDLPv2i32_v1i64 = 2841, + AArch64_SADDLPv4i16_v2i32 = 2842, + AArch64_SADDLPv4i32_v2i64 = 2843, + AArch64_SADDLPv8i16_v4i32 = 2844, + AArch64_SADDLPv8i8_v4i16 = 2845, + AArch64_SADDLVv16i8v = 2846, + AArch64_SADDLVv4i16v = 2847, + AArch64_SADDLVv4i32v = 2848, + AArch64_SADDLVv8i16v = 2849, + AArch64_SADDLVv8i8v = 2850, + AArch64_SADDLv16i8_v8i16 = 2851, + AArch64_SADDLv2i32_v2i64 = 2852, + AArch64_SADDLv4i16_v4i32 = 2853, + AArch64_SADDLv4i32_v2i64 = 2854, + AArch64_SADDLv8i16_v4i32 = 2855, + AArch64_SADDLv8i8_v8i16 = 2856, + AArch64_SADDV_VPZ_B = 2857, + AArch64_SADDV_VPZ_H = 2858, + AArch64_SADDV_VPZ_S = 2859, + AArch64_SADDWv16i8_v8i16 = 2860, + AArch64_SADDWv2i32_v2i64 = 2861, + AArch64_SADDWv4i16_v4i32 = 2862, + AArch64_SADDWv4i32_v2i64 = 2863, + AArch64_SADDWv8i16_v4i32 = 2864, + AArch64_SADDWv8i8_v8i16 = 2865, + AArch64_SBCSWr = 2866, + AArch64_SBCSXr = 2867, + AArch64_SBCWr = 2868, + AArch64_SBCXr = 2869, + AArch64_SBFMWri = 2870, + AArch64_SBFMXri = 2871, + AArch64_SCVTFSWDri = 2872, + AArch64_SCVTFSWHri = 2873, + AArch64_SCVTFSWSri = 2874, + AArch64_SCVTFSXDri = 2875, + AArch64_SCVTFSXHri = 2876, + AArch64_SCVTFSXSri = 2877, + AArch64_SCVTFUWDri = 2878, + AArch64_SCVTFUWHri = 2879, + AArch64_SCVTFUWSri = 2880, + AArch64_SCVTFUXDri = 2881, + AArch64_SCVTFUXHri = 2882, + AArch64_SCVTFUXSri = 2883, + AArch64_SCVTF_ZPmZ_DtoD = 2884, + AArch64_SCVTF_ZPmZ_DtoH = 2885, + AArch64_SCVTF_ZPmZ_DtoS = 2886, + AArch64_SCVTF_ZPmZ_HtoH = 2887, + AArch64_SCVTF_ZPmZ_StoD = 2888, + AArch64_SCVTF_ZPmZ_StoH = 2889, + AArch64_SCVTF_ZPmZ_StoS = 2890, + AArch64_SCVTFd = 2891, + AArch64_SCVTFh = 2892, + AArch64_SCVTFs = 2893, + AArch64_SCVTFv1i16 = 2894, + AArch64_SCVTFv1i32 = 2895, + AArch64_SCVTFv1i64 = 2896, + AArch64_SCVTFv2f32 = 2897, + AArch64_SCVTFv2f64 = 2898, + AArch64_SCVTFv2i32_shift = 2899, + AArch64_SCVTFv2i64_shift = 2900, + AArch64_SCVTFv4f16 = 2901, + AArch64_SCVTFv4f32 = 2902, + AArch64_SCVTFv4i16_shift = 2903, + AArch64_SCVTFv4i32_shift = 2904, + AArch64_SCVTFv8f16 = 2905, + AArch64_SCVTFv8i16_shift = 2906, + AArch64_SDIVR_ZPmZ_D = 2907, + AArch64_SDIVR_ZPmZ_S = 2908, + AArch64_SDIVWr = 2909, + AArch64_SDIVXr = 2910, + AArch64_SDIV_ZPmZ_D = 2911, + AArch64_SDIV_ZPmZ_S = 2912, + AArch64_SDOT_ZZZI_D = 2913, + AArch64_SDOT_ZZZI_S = 2914, + AArch64_SDOT_ZZZ_D = 2915, + AArch64_SDOT_ZZZ_S = 2916, + AArch64_SDOTlanev16i8 = 2917, + AArch64_SDOTlanev8i8 = 2918, + AArch64_SDOTv16i8 = 2919, + AArch64_SDOTv8i8 = 2920, + AArch64_SEL_PPPP = 2921, + AArch64_SEL_ZPZZ_B = 2922, + AArch64_SEL_ZPZZ_D = 2923, + AArch64_SEL_ZPZZ_H = 2924, + AArch64_SEL_ZPZZ_S = 2925, + AArch64_SETF16 = 2926, + AArch64_SETF8 = 2927, + AArch64_SETFFR = 2928, + AArch64_SHA1Crrr = 2929, + AArch64_SHA1Hrr = 2930, + AArch64_SHA1Mrrr = 2931, + AArch64_SHA1Prrr = 2932, + AArch64_SHA1SU0rrr = 2933, + AArch64_SHA1SU1rr = 2934, + AArch64_SHA256H2rrr = 2935, + AArch64_SHA256Hrrr = 2936, + AArch64_SHA256SU0rr = 2937, + AArch64_SHA256SU1rrr = 2938, + AArch64_SHA512H = 2939, + AArch64_SHA512H2 = 2940, + AArch64_SHA512SU0 = 2941, + AArch64_SHA512SU1 = 2942, + AArch64_SHADDv16i8 = 2943, + AArch64_SHADDv2i32 = 2944, + AArch64_SHADDv4i16 = 2945, + AArch64_SHADDv4i32 = 2946, + AArch64_SHADDv8i16 = 2947, + AArch64_SHADDv8i8 = 2948, + AArch64_SHLLv16i8 = 2949, + AArch64_SHLLv2i32 = 2950, + AArch64_SHLLv4i16 = 2951, + AArch64_SHLLv4i32 = 2952, + AArch64_SHLLv8i16 = 2953, + AArch64_SHLLv8i8 = 2954, + AArch64_SHLd = 2955, + AArch64_SHLv16i8_shift = 2956, + AArch64_SHLv2i32_shift = 2957, + AArch64_SHLv2i64_shift = 2958, + AArch64_SHLv4i16_shift = 2959, + AArch64_SHLv4i32_shift = 2960, + AArch64_SHLv8i16_shift = 2961, + AArch64_SHLv8i8_shift = 2962, + AArch64_SHRNv16i8_shift = 2963, + AArch64_SHRNv2i32_shift = 2964, + AArch64_SHRNv4i16_shift = 2965, + AArch64_SHRNv4i32_shift = 2966, + AArch64_SHRNv8i16_shift = 2967, + AArch64_SHRNv8i8_shift = 2968, + AArch64_SHSUBv16i8 = 2969, + AArch64_SHSUBv2i32 = 2970, + AArch64_SHSUBv4i16 = 2971, + AArch64_SHSUBv4i32 = 2972, + AArch64_SHSUBv8i16 = 2973, + AArch64_SHSUBv8i8 = 2974, + AArch64_SLId = 2975, + AArch64_SLIv16i8_shift = 2976, + AArch64_SLIv2i32_shift = 2977, + AArch64_SLIv2i64_shift = 2978, + AArch64_SLIv4i16_shift = 2979, + AArch64_SLIv4i32_shift = 2980, + AArch64_SLIv8i16_shift = 2981, + AArch64_SLIv8i8_shift = 2982, + AArch64_SM3PARTW1 = 2983, + AArch64_SM3PARTW2 = 2984, + AArch64_SM3SS1 = 2985, + AArch64_SM3TT1A = 2986, + AArch64_SM3TT1B = 2987, + AArch64_SM3TT2A = 2988, + AArch64_SM3TT2B = 2989, + AArch64_SM4E = 2990, + AArch64_SM4ENCKEY = 2991, + AArch64_SMADDLrrr = 2992, + AArch64_SMAXPv16i8 = 2993, + AArch64_SMAXPv2i32 = 2994, + AArch64_SMAXPv4i16 = 2995, + AArch64_SMAXPv4i32 = 2996, + AArch64_SMAXPv8i16 = 2997, + AArch64_SMAXPv8i8 = 2998, + AArch64_SMAXV_VPZ_B = 2999, + AArch64_SMAXV_VPZ_D = 3000, + AArch64_SMAXV_VPZ_H = 3001, + AArch64_SMAXV_VPZ_S = 3002, + AArch64_SMAXVv16i8v = 3003, + AArch64_SMAXVv4i16v = 3004, + AArch64_SMAXVv4i32v = 3005, + AArch64_SMAXVv8i16v = 3006, + AArch64_SMAXVv8i8v = 3007, + AArch64_SMAX_ZI_B = 3008, + AArch64_SMAX_ZI_D = 3009, + AArch64_SMAX_ZI_H = 3010, + AArch64_SMAX_ZI_S = 3011, + AArch64_SMAX_ZPmZ_B = 3012, + AArch64_SMAX_ZPmZ_D = 3013, + AArch64_SMAX_ZPmZ_H = 3014, + AArch64_SMAX_ZPmZ_S = 3015, + AArch64_SMAXv16i8 = 3016, + AArch64_SMAXv2i32 = 3017, + AArch64_SMAXv4i16 = 3018, + AArch64_SMAXv4i32 = 3019, + AArch64_SMAXv8i16 = 3020, + AArch64_SMAXv8i8 = 3021, + AArch64_SMC = 3022, + AArch64_SMINPv16i8 = 3023, + AArch64_SMINPv2i32 = 3024, + AArch64_SMINPv4i16 = 3025, + AArch64_SMINPv4i32 = 3026, + AArch64_SMINPv8i16 = 3027, + AArch64_SMINPv8i8 = 3028, + AArch64_SMINV_VPZ_B = 3029, + AArch64_SMINV_VPZ_D = 3030, + AArch64_SMINV_VPZ_H = 3031, + AArch64_SMINV_VPZ_S = 3032, + AArch64_SMINVv16i8v = 3033, + AArch64_SMINVv4i16v = 3034, + AArch64_SMINVv4i32v = 3035, + AArch64_SMINVv8i16v = 3036, + AArch64_SMINVv8i8v = 3037, + AArch64_SMIN_ZI_B = 3038, + AArch64_SMIN_ZI_D = 3039, + AArch64_SMIN_ZI_H = 3040, + AArch64_SMIN_ZI_S = 3041, + AArch64_SMIN_ZPmZ_B = 3042, + AArch64_SMIN_ZPmZ_D = 3043, + AArch64_SMIN_ZPmZ_H = 3044, + AArch64_SMIN_ZPmZ_S = 3045, + AArch64_SMINv16i8 = 3046, + AArch64_SMINv2i32 = 3047, + AArch64_SMINv4i16 = 3048, + AArch64_SMINv4i32 = 3049, + AArch64_SMINv8i16 = 3050, + AArch64_SMINv8i8 = 3051, + AArch64_SMLALv16i8_v8i16 = 3052, + AArch64_SMLALv2i32_indexed = 3053, + AArch64_SMLALv2i32_v2i64 = 3054, + AArch64_SMLALv4i16_indexed = 3055, + AArch64_SMLALv4i16_v4i32 = 3056, + AArch64_SMLALv4i32_indexed = 3057, + AArch64_SMLALv4i32_v2i64 = 3058, + AArch64_SMLALv8i16_indexed = 3059, + AArch64_SMLALv8i16_v4i32 = 3060, + AArch64_SMLALv8i8_v8i16 = 3061, + AArch64_SMLSLv16i8_v8i16 = 3062, + AArch64_SMLSLv2i32_indexed = 3063, + AArch64_SMLSLv2i32_v2i64 = 3064, + AArch64_SMLSLv4i16_indexed = 3065, + AArch64_SMLSLv4i16_v4i32 = 3066, + AArch64_SMLSLv4i32_indexed = 3067, + AArch64_SMLSLv4i32_v2i64 = 3068, + AArch64_SMLSLv8i16_indexed = 3069, + AArch64_SMLSLv8i16_v4i32 = 3070, + AArch64_SMLSLv8i8_v8i16 = 3071, + AArch64_SMOVvi16to32 = 3072, + AArch64_SMOVvi16to64 = 3073, + AArch64_SMOVvi32to64 = 3074, + AArch64_SMOVvi8to32 = 3075, + AArch64_SMOVvi8to64 = 3076, + AArch64_SMSUBLrrr = 3077, + AArch64_SMULH_ZPmZ_B = 3078, + AArch64_SMULH_ZPmZ_D = 3079, + AArch64_SMULH_ZPmZ_H = 3080, + AArch64_SMULH_ZPmZ_S = 3081, + AArch64_SMULHrr = 3082, + AArch64_SMULLv16i8_v8i16 = 3083, + AArch64_SMULLv2i32_indexed = 3084, + AArch64_SMULLv2i32_v2i64 = 3085, + AArch64_SMULLv4i16_indexed = 3086, + AArch64_SMULLv4i16_v4i32 = 3087, + AArch64_SMULLv4i32_indexed = 3088, + AArch64_SMULLv4i32_v2i64 = 3089, + AArch64_SMULLv8i16_indexed = 3090, + AArch64_SMULLv8i16_v4i32 = 3091, + AArch64_SMULLv8i8_v8i16 = 3092, + AArch64_SPLICE_ZPZ_B = 3093, + AArch64_SPLICE_ZPZ_D = 3094, + AArch64_SPLICE_ZPZ_H = 3095, + AArch64_SPLICE_ZPZ_S = 3096, + AArch64_SQABSv16i8 = 3097, + AArch64_SQABSv1i16 = 3098, + AArch64_SQABSv1i32 = 3099, + AArch64_SQABSv1i64 = 3100, + AArch64_SQABSv1i8 = 3101, + AArch64_SQABSv2i32 = 3102, + AArch64_SQABSv2i64 = 3103, + AArch64_SQABSv4i16 = 3104, + AArch64_SQABSv4i32 = 3105, + AArch64_SQABSv8i16 = 3106, + AArch64_SQABSv8i8 = 3107, + AArch64_SQADD_ZI_B = 3108, + AArch64_SQADD_ZI_D = 3109, + AArch64_SQADD_ZI_H = 3110, + AArch64_SQADD_ZI_S = 3111, + AArch64_SQADD_ZZZ_B = 3112, + AArch64_SQADD_ZZZ_D = 3113, + AArch64_SQADD_ZZZ_H = 3114, + AArch64_SQADD_ZZZ_S = 3115, + AArch64_SQADDv16i8 = 3116, + AArch64_SQADDv1i16 = 3117, + AArch64_SQADDv1i32 = 3118, + AArch64_SQADDv1i64 = 3119, + AArch64_SQADDv1i8 = 3120, + AArch64_SQADDv2i32 = 3121, + AArch64_SQADDv2i64 = 3122, + AArch64_SQADDv4i16 = 3123, + AArch64_SQADDv4i32 = 3124, + AArch64_SQADDv8i16 = 3125, + AArch64_SQADDv8i8 = 3126, + AArch64_SQDECB_XPiI = 3127, + AArch64_SQDECB_XPiWdI = 3128, + AArch64_SQDECD_XPiI = 3129, + AArch64_SQDECD_XPiWdI = 3130, + AArch64_SQDECD_ZPiI = 3131, + AArch64_SQDECH_XPiI = 3132, + AArch64_SQDECH_XPiWdI = 3133, + AArch64_SQDECH_ZPiI = 3134, + AArch64_SQDECP_XPWd_B = 3135, + AArch64_SQDECP_XPWd_D = 3136, + AArch64_SQDECP_XPWd_H = 3137, + AArch64_SQDECP_XPWd_S = 3138, + AArch64_SQDECP_XP_B = 3139, + AArch64_SQDECP_XP_D = 3140, + AArch64_SQDECP_XP_H = 3141, + AArch64_SQDECP_XP_S = 3142, + AArch64_SQDECP_ZP_D = 3143, + AArch64_SQDECP_ZP_H = 3144, + AArch64_SQDECP_ZP_S = 3145, + AArch64_SQDECW_XPiI = 3146, + AArch64_SQDECW_XPiWdI = 3147, + AArch64_SQDECW_ZPiI = 3148, + AArch64_SQDMLALi16 = 3149, + AArch64_SQDMLALi32 = 3150, + AArch64_SQDMLALv1i32_indexed = 3151, + AArch64_SQDMLALv1i64_indexed = 3152, + AArch64_SQDMLALv2i32_indexed = 3153, + AArch64_SQDMLALv2i32_v2i64 = 3154, + AArch64_SQDMLALv4i16_indexed = 3155, + AArch64_SQDMLALv4i16_v4i32 = 3156, + AArch64_SQDMLALv4i32_indexed = 3157, + AArch64_SQDMLALv4i32_v2i64 = 3158, + AArch64_SQDMLALv8i16_indexed = 3159, + AArch64_SQDMLALv8i16_v4i32 = 3160, + AArch64_SQDMLSLi16 = 3161, + AArch64_SQDMLSLi32 = 3162, + AArch64_SQDMLSLv1i32_indexed = 3163, + AArch64_SQDMLSLv1i64_indexed = 3164, + AArch64_SQDMLSLv2i32_indexed = 3165, + AArch64_SQDMLSLv2i32_v2i64 = 3166, + AArch64_SQDMLSLv4i16_indexed = 3167, + AArch64_SQDMLSLv4i16_v4i32 = 3168, + AArch64_SQDMLSLv4i32_indexed = 3169, + AArch64_SQDMLSLv4i32_v2i64 = 3170, + AArch64_SQDMLSLv8i16_indexed = 3171, + AArch64_SQDMLSLv8i16_v4i32 = 3172, + AArch64_SQDMULHv1i16 = 3173, + AArch64_SQDMULHv1i16_indexed = 3174, + AArch64_SQDMULHv1i32 = 3175, + AArch64_SQDMULHv1i32_indexed = 3176, + AArch64_SQDMULHv2i32 = 3177, + AArch64_SQDMULHv2i32_indexed = 3178, + AArch64_SQDMULHv4i16 = 3179, + AArch64_SQDMULHv4i16_indexed = 3180, + AArch64_SQDMULHv4i32 = 3181, + AArch64_SQDMULHv4i32_indexed = 3182, + AArch64_SQDMULHv8i16 = 3183, + AArch64_SQDMULHv8i16_indexed = 3184, + AArch64_SQDMULLi16 = 3185, + AArch64_SQDMULLi32 = 3186, + AArch64_SQDMULLv1i32_indexed = 3187, + AArch64_SQDMULLv1i64_indexed = 3188, + AArch64_SQDMULLv2i32_indexed = 3189, + AArch64_SQDMULLv2i32_v2i64 = 3190, + AArch64_SQDMULLv4i16_indexed = 3191, + AArch64_SQDMULLv4i16_v4i32 = 3192, + AArch64_SQDMULLv4i32_indexed = 3193, + AArch64_SQDMULLv4i32_v2i64 = 3194, + AArch64_SQDMULLv8i16_indexed = 3195, + AArch64_SQDMULLv8i16_v4i32 = 3196, + AArch64_SQINCB_XPiI = 3197, + AArch64_SQINCB_XPiWdI = 3198, + AArch64_SQINCD_XPiI = 3199, + AArch64_SQINCD_XPiWdI = 3200, + AArch64_SQINCD_ZPiI = 3201, + AArch64_SQINCH_XPiI = 3202, + AArch64_SQINCH_XPiWdI = 3203, + AArch64_SQINCH_ZPiI = 3204, + AArch64_SQINCP_XPWd_B = 3205, + AArch64_SQINCP_XPWd_D = 3206, + AArch64_SQINCP_XPWd_H = 3207, + AArch64_SQINCP_XPWd_S = 3208, + AArch64_SQINCP_XP_B = 3209, + AArch64_SQINCP_XP_D = 3210, + AArch64_SQINCP_XP_H = 3211, + AArch64_SQINCP_XP_S = 3212, + AArch64_SQINCP_ZP_D = 3213, + AArch64_SQINCP_ZP_H = 3214, + AArch64_SQINCP_ZP_S = 3215, + AArch64_SQINCW_XPiI = 3216, + AArch64_SQINCW_XPiWdI = 3217, + AArch64_SQINCW_ZPiI = 3218, + AArch64_SQNEGv16i8 = 3219, + AArch64_SQNEGv1i16 = 3220, + AArch64_SQNEGv1i32 = 3221, + AArch64_SQNEGv1i64 = 3222, + AArch64_SQNEGv1i8 = 3223, + AArch64_SQNEGv2i32 = 3224, + AArch64_SQNEGv2i64 = 3225, + AArch64_SQNEGv4i16 = 3226, + AArch64_SQNEGv4i32 = 3227, + AArch64_SQNEGv8i16 = 3228, + AArch64_SQNEGv8i8 = 3229, + AArch64_SQRDMLAHi16_indexed = 3230, + AArch64_SQRDMLAHi32_indexed = 3231, + AArch64_SQRDMLAHv1i16 = 3232, + AArch64_SQRDMLAHv1i32 = 3233, + AArch64_SQRDMLAHv2i32 = 3234, + AArch64_SQRDMLAHv2i32_indexed = 3235, + AArch64_SQRDMLAHv4i16 = 3236, + AArch64_SQRDMLAHv4i16_indexed = 3237, + AArch64_SQRDMLAHv4i32 = 3238, + AArch64_SQRDMLAHv4i32_indexed = 3239, + AArch64_SQRDMLAHv8i16 = 3240, + AArch64_SQRDMLAHv8i16_indexed = 3241, + AArch64_SQRDMLSHi16_indexed = 3242, + AArch64_SQRDMLSHi32_indexed = 3243, + AArch64_SQRDMLSHv1i16 = 3244, + AArch64_SQRDMLSHv1i32 = 3245, + AArch64_SQRDMLSHv2i32 = 3246, + AArch64_SQRDMLSHv2i32_indexed = 3247, + AArch64_SQRDMLSHv4i16 = 3248, + AArch64_SQRDMLSHv4i16_indexed = 3249, + AArch64_SQRDMLSHv4i32 = 3250, + AArch64_SQRDMLSHv4i32_indexed = 3251, + AArch64_SQRDMLSHv8i16 = 3252, + AArch64_SQRDMLSHv8i16_indexed = 3253, + AArch64_SQRDMULHv1i16 = 3254, + AArch64_SQRDMULHv1i16_indexed = 3255, + AArch64_SQRDMULHv1i32 = 3256, + AArch64_SQRDMULHv1i32_indexed = 3257, + AArch64_SQRDMULHv2i32 = 3258, + AArch64_SQRDMULHv2i32_indexed = 3259, + AArch64_SQRDMULHv4i16 = 3260, + AArch64_SQRDMULHv4i16_indexed = 3261, + AArch64_SQRDMULHv4i32 = 3262, + AArch64_SQRDMULHv4i32_indexed = 3263, + AArch64_SQRDMULHv8i16 = 3264, + AArch64_SQRDMULHv8i16_indexed = 3265, + AArch64_SQRSHLv16i8 = 3266, + AArch64_SQRSHLv1i16 = 3267, + AArch64_SQRSHLv1i32 = 3268, + AArch64_SQRSHLv1i64 = 3269, + AArch64_SQRSHLv1i8 = 3270, + AArch64_SQRSHLv2i32 = 3271, + AArch64_SQRSHLv2i64 = 3272, + AArch64_SQRSHLv4i16 = 3273, + AArch64_SQRSHLv4i32 = 3274, + AArch64_SQRSHLv8i16 = 3275, + AArch64_SQRSHLv8i8 = 3276, + AArch64_SQRSHRNb = 3277, + AArch64_SQRSHRNh = 3278, + AArch64_SQRSHRNs = 3279, + AArch64_SQRSHRNv16i8_shift = 3280, + AArch64_SQRSHRNv2i32_shift = 3281, + AArch64_SQRSHRNv4i16_shift = 3282, + AArch64_SQRSHRNv4i32_shift = 3283, + AArch64_SQRSHRNv8i16_shift = 3284, + AArch64_SQRSHRNv8i8_shift = 3285, + AArch64_SQRSHRUNb = 3286, + AArch64_SQRSHRUNh = 3287, + AArch64_SQRSHRUNs = 3288, + AArch64_SQRSHRUNv16i8_shift = 3289, + AArch64_SQRSHRUNv2i32_shift = 3290, + AArch64_SQRSHRUNv4i16_shift = 3291, + AArch64_SQRSHRUNv4i32_shift = 3292, + AArch64_SQRSHRUNv8i16_shift = 3293, + AArch64_SQRSHRUNv8i8_shift = 3294, + AArch64_SQSHLUb = 3295, + AArch64_SQSHLUd = 3296, + AArch64_SQSHLUh = 3297, + AArch64_SQSHLUs = 3298, + AArch64_SQSHLUv16i8_shift = 3299, + AArch64_SQSHLUv2i32_shift = 3300, + AArch64_SQSHLUv2i64_shift = 3301, + AArch64_SQSHLUv4i16_shift = 3302, + AArch64_SQSHLUv4i32_shift = 3303, + AArch64_SQSHLUv8i16_shift = 3304, + AArch64_SQSHLUv8i8_shift = 3305, + AArch64_SQSHLb = 3306, + AArch64_SQSHLd = 3307, + AArch64_SQSHLh = 3308, + AArch64_SQSHLs = 3309, + AArch64_SQSHLv16i8 = 3310, + AArch64_SQSHLv16i8_shift = 3311, + AArch64_SQSHLv1i16 = 3312, + AArch64_SQSHLv1i32 = 3313, + AArch64_SQSHLv1i64 = 3314, + AArch64_SQSHLv1i8 = 3315, + AArch64_SQSHLv2i32 = 3316, + AArch64_SQSHLv2i32_shift = 3317, + AArch64_SQSHLv2i64 = 3318, + AArch64_SQSHLv2i64_shift = 3319, + AArch64_SQSHLv4i16 = 3320, + AArch64_SQSHLv4i16_shift = 3321, + AArch64_SQSHLv4i32 = 3322, + AArch64_SQSHLv4i32_shift = 3323, + AArch64_SQSHLv8i16 = 3324, + AArch64_SQSHLv8i16_shift = 3325, + AArch64_SQSHLv8i8 = 3326, + AArch64_SQSHLv8i8_shift = 3327, + AArch64_SQSHRNb = 3328, + AArch64_SQSHRNh = 3329, + AArch64_SQSHRNs = 3330, + AArch64_SQSHRNv16i8_shift = 3331, + AArch64_SQSHRNv2i32_shift = 3332, + AArch64_SQSHRNv4i16_shift = 3333, + AArch64_SQSHRNv4i32_shift = 3334, + AArch64_SQSHRNv8i16_shift = 3335, + AArch64_SQSHRNv8i8_shift = 3336, + AArch64_SQSHRUNb = 3337, + AArch64_SQSHRUNh = 3338, + AArch64_SQSHRUNs = 3339, + AArch64_SQSHRUNv16i8_shift = 3340, + AArch64_SQSHRUNv2i32_shift = 3341, + AArch64_SQSHRUNv4i16_shift = 3342, + AArch64_SQSHRUNv4i32_shift = 3343, + AArch64_SQSHRUNv8i16_shift = 3344, + AArch64_SQSHRUNv8i8_shift = 3345, + AArch64_SQSUB_ZI_B = 3346, + AArch64_SQSUB_ZI_D = 3347, + AArch64_SQSUB_ZI_H = 3348, + AArch64_SQSUB_ZI_S = 3349, + AArch64_SQSUB_ZZZ_B = 3350, + AArch64_SQSUB_ZZZ_D = 3351, + AArch64_SQSUB_ZZZ_H = 3352, + AArch64_SQSUB_ZZZ_S = 3353, + AArch64_SQSUBv16i8 = 3354, + AArch64_SQSUBv1i16 = 3355, + AArch64_SQSUBv1i32 = 3356, + AArch64_SQSUBv1i64 = 3357, + AArch64_SQSUBv1i8 = 3358, + AArch64_SQSUBv2i32 = 3359, + AArch64_SQSUBv2i64 = 3360, + AArch64_SQSUBv4i16 = 3361, + AArch64_SQSUBv4i32 = 3362, + AArch64_SQSUBv8i16 = 3363, + AArch64_SQSUBv8i8 = 3364, + AArch64_SQXTNv16i8 = 3365, + AArch64_SQXTNv1i16 = 3366, + AArch64_SQXTNv1i32 = 3367, + AArch64_SQXTNv1i8 = 3368, + AArch64_SQXTNv2i32 = 3369, + AArch64_SQXTNv4i16 = 3370, + AArch64_SQXTNv4i32 = 3371, + AArch64_SQXTNv8i16 = 3372, + AArch64_SQXTNv8i8 = 3373, + AArch64_SQXTUNv16i8 = 3374, + AArch64_SQXTUNv1i16 = 3375, + AArch64_SQXTUNv1i32 = 3376, + AArch64_SQXTUNv1i8 = 3377, + AArch64_SQXTUNv2i32 = 3378, + AArch64_SQXTUNv4i16 = 3379, + AArch64_SQXTUNv4i32 = 3380, + AArch64_SQXTUNv8i16 = 3381, + AArch64_SQXTUNv8i8 = 3382, + AArch64_SRHADDv16i8 = 3383, + AArch64_SRHADDv2i32 = 3384, + AArch64_SRHADDv4i16 = 3385, + AArch64_SRHADDv4i32 = 3386, + AArch64_SRHADDv8i16 = 3387, + AArch64_SRHADDv8i8 = 3388, + AArch64_SRId = 3389, + AArch64_SRIv16i8_shift = 3390, + AArch64_SRIv2i32_shift = 3391, + AArch64_SRIv2i64_shift = 3392, + AArch64_SRIv4i16_shift = 3393, + AArch64_SRIv4i32_shift = 3394, + AArch64_SRIv8i16_shift = 3395, + AArch64_SRIv8i8_shift = 3396, + AArch64_SRSHLv16i8 = 3397, + AArch64_SRSHLv1i64 = 3398, + AArch64_SRSHLv2i32 = 3399, + AArch64_SRSHLv2i64 = 3400, + AArch64_SRSHLv4i16 = 3401, + AArch64_SRSHLv4i32 = 3402, + AArch64_SRSHLv8i16 = 3403, + AArch64_SRSHLv8i8 = 3404, + AArch64_SRSHRd = 3405, + AArch64_SRSHRv16i8_shift = 3406, + AArch64_SRSHRv2i32_shift = 3407, + AArch64_SRSHRv2i64_shift = 3408, + AArch64_SRSHRv4i16_shift = 3409, + AArch64_SRSHRv4i32_shift = 3410, + AArch64_SRSHRv8i16_shift = 3411, + AArch64_SRSHRv8i8_shift = 3412, + AArch64_SRSRAd = 3413, + AArch64_SRSRAv16i8_shift = 3414, + AArch64_SRSRAv2i32_shift = 3415, + AArch64_SRSRAv2i64_shift = 3416, + AArch64_SRSRAv4i16_shift = 3417, + AArch64_SRSRAv4i32_shift = 3418, + AArch64_SRSRAv8i16_shift = 3419, + AArch64_SRSRAv8i8_shift = 3420, + AArch64_SSHLLv16i8_shift = 3421, + AArch64_SSHLLv2i32_shift = 3422, + AArch64_SSHLLv4i16_shift = 3423, + AArch64_SSHLLv4i32_shift = 3424, + AArch64_SSHLLv8i16_shift = 3425, + AArch64_SSHLLv8i8_shift = 3426, + AArch64_SSHLv16i8 = 3427, + AArch64_SSHLv1i64 = 3428, + AArch64_SSHLv2i32 = 3429, + AArch64_SSHLv2i64 = 3430, + AArch64_SSHLv4i16 = 3431, + AArch64_SSHLv4i32 = 3432, + AArch64_SSHLv8i16 = 3433, + AArch64_SSHLv8i8 = 3434, + AArch64_SSHRd = 3435, + AArch64_SSHRv16i8_shift = 3436, + AArch64_SSHRv2i32_shift = 3437, + AArch64_SSHRv2i64_shift = 3438, + AArch64_SSHRv4i16_shift = 3439, + AArch64_SSHRv4i32_shift = 3440, + AArch64_SSHRv8i16_shift = 3441, + AArch64_SSHRv8i8_shift = 3442, + AArch64_SSRAd = 3443, + AArch64_SSRAv16i8_shift = 3444, + AArch64_SSRAv2i32_shift = 3445, + AArch64_SSRAv2i64_shift = 3446, + AArch64_SSRAv4i16_shift = 3447, + AArch64_SSRAv4i32_shift = 3448, + AArch64_SSRAv8i16_shift = 3449, + AArch64_SSRAv8i8_shift = 3450, + AArch64_SST1B_D = 3451, + AArch64_SST1B_D_IMM = 3452, + AArch64_SST1B_D_SXTW = 3453, + AArch64_SST1B_D_UXTW = 3454, + AArch64_SST1B_S_IMM = 3455, + AArch64_SST1B_S_SXTW = 3456, + AArch64_SST1B_S_UXTW = 3457, + AArch64_SST1D = 3458, + AArch64_SST1D_IMM = 3459, + AArch64_SST1D_SCALED = 3460, + AArch64_SST1D_SXTW = 3461, + AArch64_SST1D_SXTW_SCALED = 3462, + AArch64_SST1D_UXTW = 3463, + AArch64_SST1D_UXTW_SCALED = 3464, + AArch64_SST1H_D = 3465, + AArch64_SST1H_D_IMM = 3466, + AArch64_SST1H_D_SCALED = 3467, + AArch64_SST1H_D_SXTW = 3468, + AArch64_SST1H_D_SXTW_SCALED = 3469, + AArch64_SST1H_D_UXTW = 3470, + AArch64_SST1H_D_UXTW_SCALED = 3471, + AArch64_SST1H_S_IMM = 3472, + AArch64_SST1H_S_SXTW = 3473, + AArch64_SST1H_S_SXTW_SCALED = 3474, + AArch64_SST1H_S_UXTW = 3475, + AArch64_SST1H_S_UXTW_SCALED = 3476, + AArch64_SST1W_D = 3477, + AArch64_SST1W_D_IMM = 3478, + AArch64_SST1W_D_SCALED = 3479, + AArch64_SST1W_D_SXTW = 3480, + AArch64_SST1W_D_SXTW_SCALED = 3481, + AArch64_SST1W_D_UXTW = 3482, + AArch64_SST1W_D_UXTW_SCALED = 3483, + AArch64_SST1W_IMM = 3484, + AArch64_SST1W_SXTW = 3485, + AArch64_SST1W_SXTW_SCALED = 3486, + AArch64_SST1W_UXTW = 3487, + AArch64_SST1W_UXTW_SCALED = 3488, + AArch64_SSUBLv16i8_v8i16 = 3489, + AArch64_SSUBLv2i32_v2i64 = 3490, + AArch64_SSUBLv4i16_v4i32 = 3491, + AArch64_SSUBLv4i32_v2i64 = 3492, + AArch64_SSUBLv8i16_v4i32 = 3493, + AArch64_SSUBLv8i8_v8i16 = 3494, + AArch64_SSUBWv16i8_v8i16 = 3495, + AArch64_SSUBWv2i32_v2i64 = 3496, + AArch64_SSUBWv4i16_v4i32 = 3497, + AArch64_SSUBWv4i32_v2i64 = 3498, + AArch64_SSUBWv8i16_v4i32 = 3499, + AArch64_SSUBWv8i8_v8i16 = 3500, + AArch64_ST1B = 3501, + AArch64_ST1B_D = 3502, + AArch64_ST1B_D_IMM = 3503, + AArch64_ST1B_H = 3504, + AArch64_ST1B_H_IMM = 3505, + AArch64_ST1B_IMM = 3506, + AArch64_ST1B_S = 3507, + AArch64_ST1B_S_IMM = 3508, + AArch64_ST1D = 3509, + AArch64_ST1D_IMM = 3510, + AArch64_ST1Fourv16b = 3511, + AArch64_ST1Fourv16b_POST = 3512, + AArch64_ST1Fourv1d = 3513, + AArch64_ST1Fourv1d_POST = 3514, + AArch64_ST1Fourv2d = 3515, + AArch64_ST1Fourv2d_POST = 3516, + AArch64_ST1Fourv2s = 3517, + AArch64_ST1Fourv2s_POST = 3518, + AArch64_ST1Fourv4h = 3519, + AArch64_ST1Fourv4h_POST = 3520, + AArch64_ST1Fourv4s = 3521, + AArch64_ST1Fourv4s_POST = 3522, + AArch64_ST1Fourv8b = 3523, + AArch64_ST1Fourv8b_POST = 3524, + AArch64_ST1Fourv8h = 3525, + AArch64_ST1Fourv8h_POST = 3526, + AArch64_ST1H = 3527, + AArch64_ST1H_D = 3528, + AArch64_ST1H_D_IMM = 3529, + AArch64_ST1H_IMM = 3530, + AArch64_ST1H_S = 3531, + AArch64_ST1H_S_IMM = 3532, + AArch64_ST1Onev16b = 3533, + AArch64_ST1Onev16b_POST = 3534, + AArch64_ST1Onev1d = 3535, + AArch64_ST1Onev1d_POST = 3536, + AArch64_ST1Onev2d = 3537, + AArch64_ST1Onev2d_POST = 3538, + AArch64_ST1Onev2s = 3539, + AArch64_ST1Onev2s_POST = 3540, + AArch64_ST1Onev4h = 3541, + AArch64_ST1Onev4h_POST = 3542, + AArch64_ST1Onev4s = 3543, + AArch64_ST1Onev4s_POST = 3544, + AArch64_ST1Onev8b = 3545, + AArch64_ST1Onev8b_POST = 3546, + AArch64_ST1Onev8h = 3547, + AArch64_ST1Onev8h_POST = 3548, + AArch64_ST1Threev16b = 3549, + AArch64_ST1Threev16b_POST = 3550, + AArch64_ST1Threev1d = 3551, + AArch64_ST1Threev1d_POST = 3552, + AArch64_ST1Threev2d = 3553, + AArch64_ST1Threev2d_POST = 3554, + AArch64_ST1Threev2s = 3555, + AArch64_ST1Threev2s_POST = 3556, + AArch64_ST1Threev4h = 3557, + AArch64_ST1Threev4h_POST = 3558, + AArch64_ST1Threev4s = 3559, + AArch64_ST1Threev4s_POST = 3560, + AArch64_ST1Threev8b = 3561, + AArch64_ST1Threev8b_POST = 3562, + AArch64_ST1Threev8h = 3563, + AArch64_ST1Threev8h_POST = 3564, + AArch64_ST1Twov16b = 3565, + AArch64_ST1Twov16b_POST = 3566, + AArch64_ST1Twov1d = 3567, + AArch64_ST1Twov1d_POST = 3568, + AArch64_ST1Twov2d = 3569, + AArch64_ST1Twov2d_POST = 3570, + AArch64_ST1Twov2s = 3571, + AArch64_ST1Twov2s_POST = 3572, + AArch64_ST1Twov4h = 3573, + AArch64_ST1Twov4h_POST = 3574, + AArch64_ST1Twov4s = 3575, + AArch64_ST1Twov4s_POST = 3576, + AArch64_ST1Twov8b = 3577, + AArch64_ST1Twov8b_POST = 3578, + AArch64_ST1Twov8h = 3579, + AArch64_ST1Twov8h_POST = 3580, + AArch64_ST1W = 3581, + AArch64_ST1W_D = 3582, + AArch64_ST1W_D_IMM = 3583, + AArch64_ST1W_IMM = 3584, + AArch64_ST1i16 = 3585, + AArch64_ST1i16_POST = 3586, + AArch64_ST1i32 = 3587, + AArch64_ST1i32_POST = 3588, + AArch64_ST1i64 = 3589, + AArch64_ST1i64_POST = 3590, + AArch64_ST1i8 = 3591, + AArch64_ST1i8_POST = 3592, + AArch64_ST2B = 3593, + AArch64_ST2B_IMM = 3594, + AArch64_ST2D = 3595, + AArch64_ST2D_IMM = 3596, + AArch64_ST2H = 3597, + AArch64_ST2H_IMM = 3598, + AArch64_ST2Twov16b = 3599, + AArch64_ST2Twov16b_POST = 3600, + AArch64_ST2Twov2d = 3601, + AArch64_ST2Twov2d_POST = 3602, + AArch64_ST2Twov2s = 3603, + AArch64_ST2Twov2s_POST = 3604, + AArch64_ST2Twov4h = 3605, + AArch64_ST2Twov4h_POST = 3606, + AArch64_ST2Twov4s = 3607, + AArch64_ST2Twov4s_POST = 3608, + AArch64_ST2Twov8b = 3609, + AArch64_ST2Twov8b_POST = 3610, + AArch64_ST2Twov8h = 3611, + AArch64_ST2Twov8h_POST = 3612, + AArch64_ST2W = 3613, + AArch64_ST2W_IMM = 3614, + AArch64_ST2i16 = 3615, + AArch64_ST2i16_POST = 3616, + AArch64_ST2i32 = 3617, + AArch64_ST2i32_POST = 3618, + AArch64_ST2i64 = 3619, + AArch64_ST2i64_POST = 3620, + AArch64_ST2i8 = 3621, + AArch64_ST2i8_POST = 3622, + AArch64_ST3B = 3623, + AArch64_ST3B_IMM = 3624, + AArch64_ST3D = 3625, + AArch64_ST3D_IMM = 3626, + AArch64_ST3H = 3627, + AArch64_ST3H_IMM = 3628, + AArch64_ST3Threev16b = 3629, + AArch64_ST3Threev16b_POST = 3630, + AArch64_ST3Threev2d = 3631, + AArch64_ST3Threev2d_POST = 3632, + AArch64_ST3Threev2s = 3633, + AArch64_ST3Threev2s_POST = 3634, + AArch64_ST3Threev4h = 3635, + AArch64_ST3Threev4h_POST = 3636, + AArch64_ST3Threev4s = 3637, + AArch64_ST3Threev4s_POST = 3638, + AArch64_ST3Threev8b = 3639, + AArch64_ST3Threev8b_POST = 3640, + AArch64_ST3Threev8h = 3641, + AArch64_ST3Threev8h_POST = 3642, + AArch64_ST3W = 3643, + AArch64_ST3W_IMM = 3644, + AArch64_ST3i16 = 3645, + AArch64_ST3i16_POST = 3646, + AArch64_ST3i32 = 3647, + AArch64_ST3i32_POST = 3648, + AArch64_ST3i64 = 3649, + AArch64_ST3i64_POST = 3650, + AArch64_ST3i8 = 3651, + AArch64_ST3i8_POST = 3652, + AArch64_ST4B = 3653, + AArch64_ST4B_IMM = 3654, + AArch64_ST4D = 3655, + AArch64_ST4D_IMM = 3656, + AArch64_ST4Fourv16b = 3657, + AArch64_ST4Fourv16b_POST = 3658, + AArch64_ST4Fourv2d = 3659, + AArch64_ST4Fourv2d_POST = 3660, + AArch64_ST4Fourv2s = 3661, + AArch64_ST4Fourv2s_POST = 3662, + AArch64_ST4Fourv4h = 3663, + AArch64_ST4Fourv4h_POST = 3664, + AArch64_ST4Fourv4s = 3665, + AArch64_ST4Fourv4s_POST = 3666, + AArch64_ST4Fourv8b = 3667, + AArch64_ST4Fourv8b_POST = 3668, + AArch64_ST4Fourv8h = 3669, + AArch64_ST4Fourv8h_POST = 3670, + AArch64_ST4H = 3671, + AArch64_ST4H_IMM = 3672, + AArch64_ST4W = 3673, + AArch64_ST4W_IMM = 3674, + AArch64_ST4i16 = 3675, + AArch64_ST4i16_POST = 3676, + AArch64_ST4i32 = 3677, + AArch64_ST4i32_POST = 3678, + AArch64_ST4i64 = 3679, + AArch64_ST4i64_POST = 3680, + AArch64_ST4i8 = 3681, + AArch64_ST4i8_POST = 3682, + AArch64_STLLRB = 3683, + AArch64_STLLRH = 3684, + AArch64_STLLRW = 3685, + AArch64_STLLRX = 3686, + AArch64_STLRB = 3687, + AArch64_STLRH = 3688, + AArch64_STLRW = 3689, + AArch64_STLRX = 3690, + AArch64_STLURBi = 3691, + AArch64_STLURHi = 3692, + AArch64_STLURWi = 3693, + AArch64_STLURXi = 3694, + AArch64_STLXPW = 3695, + AArch64_STLXPX = 3696, + AArch64_STLXRB = 3697, + AArch64_STLXRH = 3698, + AArch64_STLXRW = 3699, + AArch64_STLXRX = 3700, + AArch64_STNPDi = 3701, + AArch64_STNPQi = 3702, + AArch64_STNPSi = 3703, + AArch64_STNPWi = 3704, + AArch64_STNPXi = 3705, + AArch64_STNT1B_ZRI = 3706, + AArch64_STNT1B_ZRR = 3707, + AArch64_STNT1D_ZRI = 3708, + AArch64_STNT1D_ZRR = 3709, + AArch64_STNT1H_ZRI = 3710, + AArch64_STNT1H_ZRR = 3711, + AArch64_STNT1W_ZRI = 3712, + AArch64_STNT1W_ZRR = 3713, + AArch64_STPDi = 3714, + AArch64_STPDpost = 3715, + AArch64_STPDpre = 3716, + AArch64_STPQi = 3717, + AArch64_STPQpost = 3718, + AArch64_STPQpre = 3719, + AArch64_STPSi = 3720, + AArch64_STPSpost = 3721, + AArch64_STPSpre = 3722, + AArch64_STPWi = 3723, + AArch64_STPWpost = 3724, + AArch64_STPWpre = 3725, + AArch64_STPXi = 3726, + AArch64_STPXpost = 3727, + AArch64_STPXpre = 3728, + AArch64_STRBBpost = 3729, + AArch64_STRBBpre = 3730, + AArch64_STRBBroW = 3731, + AArch64_STRBBroX = 3732, + AArch64_STRBBui = 3733, + AArch64_STRBpost = 3734, + AArch64_STRBpre = 3735, + AArch64_STRBroW = 3736, + AArch64_STRBroX = 3737, + AArch64_STRBui = 3738, + AArch64_STRDpost = 3739, + AArch64_STRDpre = 3740, + AArch64_STRDroW = 3741, + AArch64_STRDroX = 3742, + AArch64_STRDui = 3743, + AArch64_STRHHpost = 3744, + AArch64_STRHHpre = 3745, + AArch64_STRHHroW = 3746, + AArch64_STRHHroX = 3747, + AArch64_STRHHui = 3748, + AArch64_STRHpost = 3749, + AArch64_STRHpre = 3750, + AArch64_STRHroW = 3751, + AArch64_STRHroX = 3752, + AArch64_STRHui = 3753, + AArch64_STRQpost = 3754, + AArch64_STRQpre = 3755, + AArch64_STRQroW = 3756, + AArch64_STRQroX = 3757, + AArch64_STRQui = 3758, + AArch64_STRSpost = 3759, + AArch64_STRSpre = 3760, + AArch64_STRSroW = 3761, + AArch64_STRSroX = 3762, + AArch64_STRSui = 3763, + AArch64_STRWpost = 3764, + AArch64_STRWpre = 3765, + AArch64_STRWroW = 3766, + AArch64_STRWroX = 3767, + AArch64_STRWui = 3768, + AArch64_STRXpost = 3769, + AArch64_STRXpre = 3770, + AArch64_STRXroW = 3771, + AArch64_STRXroX = 3772, + AArch64_STRXui = 3773, + AArch64_STR_PXI = 3774, + AArch64_STR_ZXI = 3775, + AArch64_STTRBi = 3776, + AArch64_STTRHi = 3777, + AArch64_STTRWi = 3778, + AArch64_STTRXi = 3779, + AArch64_STURBBi = 3780, + AArch64_STURBi = 3781, + AArch64_STURDi = 3782, + AArch64_STURHHi = 3783, + AArch64_STURHi = 3784, + AArch64_STURQi = 3785, + AArch64_STURSi = 3786, + AArch64_STURWi = 3787, + AArch64_STURXi = 3788, + AArch64_STXPW = 3789, + AArch64_STXPX = 3790, + AArch64_STXRB = 3791, + AArch64_STXRH = 3792, + AArch64_STXRW = 3793, + AArch64_STXRX = 3794, + AArch64_SUBHNv2i64_v2i32 = 3795, + AArch64_SUBHNv2i64_v4i32 = 3796, + AArch64_SUBHNv4i32_v4i16 = 3797, + AArch64_SUBHNv4i32_v8i16 = 3798, + AArch64_SUBHNv8i16_v16i8 = 3799, + AArch64_SUBHNv8i16_v8i8 = 3800, + AArch64_SUBR_ZI_B = 3801, + AArch64_SUBR_ZI_D = 3802, + AArch64_SUBR_ZI_H = 3803, + AArch64_SUBR_ZI_S = 3804, + AArch64_SUBR_ZPmZ_B = 3805, + AArch64_SUBR_ZPmZ_D = 3806, + AArch64_SUBR_ZPmZ_H = 3807, + AArch64_SUBR_ZPmZ_S = 3808, + AArch64_SUBSWri = 3809, + AArch64_SUBSWrr = 3810, + AArch64_SUBSWrs = 3811, + AArch64_SUBSWrx = 3812, + AArch64_SUBSXri = 3813, + AArch64_SUBSXrr = 3814, + AArch64_SUBSXrs = 3815, + AArch64_SUBSXrx = 3816, + AArch64_SUBSXrx64 = 3817, + AArch64_SUBWri = 3818, + AArch64_SUBWrr = 3819, + AArch64_SUBWrs = 3820, + AArch64_SUBWrx = 3821, + AArch64_SUBXri = 3822, + AArch64_SUBXrr = 3823, + AArch64_SUBXrs = 3824, + AArch64_SUBXrx = 3825, + AArch64_SUBXrx64 = 3826, + AArch64_SUB_ZI_B = 3827, + AArch64_SUB_ZI_D = 3828, + AArch64_SUB_ZI_H = 3829, + AArch64_SUB_ZI_S = 3830, + AArch64_SUB_ZPmZ_B = 3831, + AArch64_SUB_ZPmZ_D = 3832, + AArch64_SUB_ZPmZ_H = 3833, + AArch64_SUB_ZPmZ_S = 3834, + AArch64_SUB_ZZZ_B = 3835, + AArch64_SUB_ZZZ_D = 3836, + AArch64_SUB_ZZZ_H = 3837, + AArch64_SUB_ZZZ_S = 3838, + AArch64_SUBv16i8 = 3839, + AArch64_SUBv1i64 = 3840, + AArch64_SUBv2i32 = 3841, + AArch64_SUBv2i64 = 3842, + AArch64_SUBv4i16 = 3843, + AArch64_SUBv4i32 = 3844, + AArch64_SUBv8i16 = 3845, + AArch64_SUBv8i8 = 3846, + AArch64_SUNPKHI_ZZ_D = 3847, + AArch64_SUNPKHI_ZZ_H = 3848, + AArch64_SUNPKHI_ZZ_S = 3849, + AArch64_SUNPKLO_ZZ_D = 3850, + AArch64_SUNPKLO_ZZ_H = 3851, + AArch64_SUNPKLO_ZZ_S = 3852, + AArch64_SUQADDv16i8 = 3853, + AArch64_SUQADDv1i16 = 3854, + AArch64_SUQADDv1i32 = 3855, + AArch64_SUQADDv1i64 = 3856, + AArch64_SUQADDv1i8 = 3857, + AArch64_SUQADDv2i32 = 3858, + AArch64_SUQADDv2i64 = 3859, + AArch64_SUQADDv4i16 = 3860, + AArch64_SUQADDv4i32 = 3861, + AArch64_SUQADDv8i16 = 3862, + AArch64_SUQADDv8i8 = 3863, + AArch64_SVC = 3864, + AArch64_SWPAB = 3865, + AArch64_SWPAH = 3866, + AArch64_SWPALB = 3867, + AArch64_SWPALH = 3868, + AArch64_SWPALW = 3869, + AArch64_SWPALX = 3870, + AArch64_SWPAW = 3871, + AArch64_SWPAX = 3872, + AArch64_SWPB = 3873, + AArch64_SWPH = 3874, + AArch64_SWPLB = 3875, + AArch64_SWPLH = 3876, + AArch64_SWPLW = 3877, + AArch64_SWPLX = 3878, + AArch64_SWPW = 3879, + AArch64_SWPX = 3880, + AArch64_SXTB_ZPmZ_D = 3881, + AArch64_SXTB_ZPmZ_H = 3882, + AArch64_SXTB_ZPmZ_S = 3883, + AArch64_SXTH_ZPmZ_D = 3884, + AArch64_SXTH_ZPmZ_S = 3885, + AArch64_SXTW_ZPmZ_D = 3886, + AArch64_SYSLxt = 3887, + AArch64_SYSxt = 3888, + AArch64_TBL_ZZZ_B = 3889, + AArch64_TBL_ZZZ_D = 3890, + AArch64_TBL_ZZZ_H = 3891, + AArch64_TBL_ZZZ_S = 3892, + AArch64_TBLv16i8Four = 3893, + AArch64_TBLv16i8One = 3894, + AArch64_TBLv16i8Three = 3895, + AArch64_TBLv16i8Two = 3896, + AArch64_TBLv8i8Four = 3897, + AArch64_TBLv8i8One = 3898, + AArch64_TBLv8i8Three = 3899, + AArch64_TBLv8i8Two = 3900, + AArch64_TBNZW = 3901, + AArch64_TBNZX = 3902, + AArch64_TBXv16i8Four = 3903, + AArch64_TBXv16i8One = 3904, + AArch64_TBXv16i8Three = 3905, + AArch64_TBXv16i8Two = 3906, + AArch64_TBXv8i8Four = 3907, + AArch64_TBXv8i8One = 3908, + AArch64_TBXv8i8Three = 3909, + AArch64_TBXv8i8Two = 3910, + AArch64_TBZW = 3911, + AArch64_TBZX = 3912, + AArch64_TCRETURNdi = 3913, + AArch64_TCRETURNri = 3914, + AArch64_TLSDESCCALL = 3915, + AArch64_TLSDESC_CALLSEQ = 3916, + AArch64_TRN1_PPP_B = 3917, + AArch64_TRN1_PPP_D = 3918, + AArch64_TRN1_PPP_H = 3919, + AArch64_TRN1_PPP_S = 3920, + AArch64_TRN1_ZZZ_B = 3921, + AArch64_TRN1_ZZZ_D = 3922, + AArch64_TRN1_ZZZ_H = 3923, + AArch64_TRN1_ZZZ_S = 3924, + AArch64_TRN1v16i8 = 3925, + AArch64_TRN1v2i32 = 3926, + AArch64_TRN1v2i64 = 3927, + AArch64_TRN1v4i16 = 3928, + AArch64_TRN1v4i32 = 3929, + AArch64_TRN1v8i16 = 3930, + AArch64_TRN1v8i8 = 3931, + AArch64_TRN2_PPP_B = 3932, + AArch64_TRN2_PPP_D = 3933, + AArch64_TRN2_PPP_H = 3934, + AArch64_TRN2_PPP_S = 3935, + AArch64_TRN2_ZZZ_B = 3936, + AArch64_TRN2_ZZZ_D = 3937, + AArch64_TRN2_ZZZ_H = 3938, + AArch64_TRN2_ZZZ_S = 3939, + AArch64_TRN2v16i8 = 3940, + AArch64_TRN2v2i32 = 3941, + AArch64_TRN2v2i64 = 3942, + AArch64_TRN2v4i16 = 3943, + AArch64_TRN2v4i32 = 3944, + AArch64_TRN2v8i16 = 3945, + AArch64_TRN2v8i8 = 3946, + AArch64_TSB = 3947, + AArch64_UABALv16i8_v8i16 = 3948, + AArch64_UABALv2i32_v2i64 = 3949, + AArch64_UABALv4i16_v4i32 = 3950, + AArch64_UABALv4i32_v2i64 = 3951, + AArch64_UABALv8i16_v4i32 = 3952, + AArch64_UABALv8i8_v8i16 = 3953, + AArch64_UABAv16i8 = 3954, + AArch64_UABAv2i32 = 3955, + AArch64_UABAv4i16 = 3956, + AArch64_UABAv4i32 = 3957, + AArch64_UABAv8i16 = 3958, + AArch64_UABAv8i8 = 3959, + AArch64_UABDLv16i8_v8i16 = 3960, + AArch64_UABDLv2i32_v2i64 = 3961, + AArch64_UABDLv4i16_v4i32 = 3962, + AArch64_UABDLv4i32_v2i64 = 3963, + AArch64_UABDLv8i16_v4i32 = 3964, + AArch64_UABDLv8i8_v8i16 = 3965, + AArch64_UABD_ZPmZ_B = 3966, + AArch64_UABD_ZPmZ_D = 3967, + AArch64_UABD_ZPmZ_H = 3968, + AArch64_UABD_ZPmZ_S = 3969, + AArch64_UABDv16i8 = 3970, + AArch64_UABDv2i32 = 3971, + AArch64_UABDv4i16 = 3972, + AArch64_UABDv4i32 = 3973, + AArch64_UABDv8i16 = 3974, + AArch64_UABDv8i8 = 3975, + AArch64_UADALPv16i8_v8i16 = 3976, + AArch64_UADALPv2i32_v1i64 = 3977, + AArch64_UADALPv4i16_v2i32 = 3978, + AArch64_UADALPv4i32_v2i64 = 3979, + AArch64_UADALPv8i16_v4i32 = 3980, + AArch64_UADALPv8i8_v4i16 = 3981, + AArch64_UADDLPv16i8_v8i16 = 3982, + AArch64_UADDLPv2i32_v1i64 = 3983, + AArch64_UADDLPv4i16_v2i32 = 3984, + AArch64_UADDLPv4i32_v2i64 = 3985, + AArch64_UADDLPv8i16_v4i32 = 3986, + AArch64_UADDLPv8i8_v4i16 = 3987, + AArch64_UADDLVv16i8v = 3988, + AArch64_UADDLVv4i16v = 3989, + AArch64_UADDLVv4i32v = 3990, + AArch64_UADDLVv8i16v = 3991, + AArch64_UADDLVv8i8v = 3992, + AArch64_UADDLv16i8_v8i16 = 3993, + AArch64_UADDLv2i32_v2i64 = 3994, + AArch64_UADDLv4i16_v4i32 = 3995, + AArch64_UADDLv4i32_v2i64 = 3996, + AArch64_UADDLv8i16_v4i32 = 3997, + AArch64_UADDLv8i8_v8i16 = 3998, + AArch64_UADDV_VPZ_B = 3999, + AArch64_UADDV_VPZ_D = 4000, + AArch64_UADDV_VPZ_H = 4001, + AArch64_UADDV_VPZ_S = 4002, + AArch64_UADDWv16i8_v8i16 = 4003, + AArch64_UADDWv2i32_v2i64 = 4004, + AArch64_UADDWv4i16_v4i32 = 4005, + AArch64_UADDWv4i32_v2i64 = 4006, + AArch64_UADDWv8i16_v4i32 = 4007, + AArch64_UADDWv8i8_v8i16 = 4008, + AArch64_UBFMWri = 4009, + AArch64_UBFMXri = 4010, + AArch64_UCVTFSWDri = 4011, + AArch64_UCVTFSWHri = 4012, + AArch64_UCVTFSWSri = 4013, + AArch64_UCVTFSXDri = 4014, + AArch64_UCVTFSXHri = 4015, + AArch64_UCVTFSXSri = 4016, + AArch64_UCVTFUWDri = 4017, + AArch64_UCVTFUWHri = 4018, + AArch64_UCVTFUWSri = 4019, + AArch64_UCVTFUXDri = 4020, + AArch64_UCVTFUXHri = 4021, + AArch64_UCVTFUXSri = 4022, + AArch64_UCVTF_ZPmZ_DtoD = 4023, + AArch64_UCVTF_ZPmZ_DtoH = 4024, + AArch64_UCVTF_ZPmZ_DtoS = 4025, + AArch64_UCVTF_ZPmZ_HtoH = 4026, + AArch64_UCVTF_ZPmZ_StoD = 4027, + AArch64_UCVTF_ZPmZ_StoH = 4028, + AArch64_UCVTF_ZPmZ_StoS = 4029, + AArch64_UCVTFd = 4030, + AArch64_UCVTFh = 4031, + AArch64_UCVTFs = 4032, + AArch64_UCVTFv1i16 = 4033, + AArch64_UCVTFv1i32 = 4034, + AArch64_UCVTFv1i64 = 4035, + AArch64_UCVTFv2f32 = 4036, + AArch64_UCVTFv2f64 = 4037, + AArch64_UCVTFv2i32_shift = 4038, + AArch64_UCVTFv2i64_shift = 4039, + AArch64_UCVTFv4f16 = 4040, + AArch64_UCVTFv4f32 = 4041, + AArch64_UCVTFv4i16_shift = 4042, + AArch64_UCVTFv4i32_shift = 4043, + AArch64_UCVTFv8f16 = 4044, + AArch64_UCVTFv8i16_shift = 4045, + AArch64_UDIVR_ZPmZ_D = 4046, + AArch64_UDIVR_ZPmZ_S = 4047, + AArch64_UDIVWr = 4048, + AArch64_UDIVXr = 4049, + AArch64_UDIV_ZPmZ_D = 4050, + AArch64_UDIV_ZPmZ_S = 4051, + AArch64_UDOT_ZZZI_D = 4052, + AArch64_UDOT_ZZZI_S = 4053, + AArch64_UDOT_ZZZ_D = 4054, + AArch64_UDOT_ZZZ_S = 4055, + AArch64_UDOTlanev16i8 = 4056, + AArch64_UDOTlanev8i8 = 4057, + AArch64_UDOTv16i8 = 4058, + AArch64_UDOTv8i8 = 4059, + AArch64_UHADDv16i8 = 4060, + AArch64_UHADDv2i32 = 4061, + AArch64_UHADDv4i16 = 4062, + AArch64_UHADDv4i32 = 4063, + AArch64_UHADDv8i16 = 4064, + AArch64_UHADDv8i8 = 4065, + AArch64_UHSUBv16i8 = 4066, + AArch64_UHSUBv2i32 = 4067, + AArch64_UHSUBv4i16 = 4068, + AArch64_UHSUBv4i32 = 4069, + AArch64_UHSUBv8i16 = 4070, + AArch64_UHSUBv8i8 = 4071, + AArch64_UMADDLrrr = 4072, + AArch64_UMAXPv16i8 = 4073, + AArch64_UMAXPv2i32 = 4074, + AArch64_UMAXPv4i16 = 4075, + AArch64_UMAXPv4i32 = 4076, + AArch64_UMAXPv8i16 = 4077, + AArch64_UMAXPv8i8 = 4078, + AArch64_UMAXV_VPZ_B = 4079, + AArch64_UMAXV_VPZ_D = 4080, + AArch64_UMAXV_VPZ_H = 4081, + AArch64_UMAXV_VPZ_S = 4082, + AArch64_UMAXVv16i8v = 4083, + AArch64_UMAXVv4i16v = 4084, + AArch64_UMAXVv4i32v = 4085, + AArch64_UMAXVv8i16v = 4086, + AArch64_UMAXVv8i8v = 4087, + AArch64_UMAX_ZI_B = 4088, + AArch64_UMAX_ZI_D = 4089, + AArch64_UMAX_ZI_H = 4090, + AArch64_UMAX_ZI_S = 4091, + AArch64_UMAX_ZPmZ_B = 4092, + AArch64_UMAX_ZPmZ_D = 4093, + AArch64_UMAX_ZPmZ_H = 4094, + AArch64_UMAX_ZPmZ_S = 4095, + AArch64_UMAXv16i8 = 4096, + AArch64_UMAXv2i32 = 4097, + AArch64_UMAXv4i16 = 4098, + AArch64_UMAXv4i32 = 4099, + AArch64_UMAXv8i16 = 4100, + AArch64_UMAXv8i8 = 4101, + AArch64_UMINPv16i8 = 4102, + AArch64_UMINPv2i32 = 4103, + AArch64_UMINPv4i16 = 4104, + AArch64_UMINPv4i32 = 4105, + AArch64_UMINPv8i16 = 4106, + AArch64_UMINPv8i8 = 4107, + AArch64_UMINV_VPZ_B = 4108, + AArch64_UMINV_VPZ_D = 4109, + AArch64_UMINV_VPZ_H = 4110, + AArch64_UMINV_VPZ_S = 4111, + AArch64_UMINVv16i8v = 4112, + AArch64_UMINVv4i16v = 4113, + AArch64_UMINVv4i32v = 4114, + AArch64_UMINVv8i16v = 4115, + AArch64_UMINVv8i8v = 4116, + AArch64_UMIN_ZI_B = 4117, + AArch64_UMIN_ZI_D = 4118, + AArch64_UMIN_ZI_H = 4119, + AArch64_UMIN_ZI_S = 4120, + AArch64_UMIN_ZPmZ_B = 4121, + AArch64_UMIN_ZPmZ_D = 4122, + AArch64_UMIN_ZPmZ_H = 4123, + AArch64_UMIN_ZPmZ_S = 4124, + AArch64_UMINv16i8 = 4125, + AArch64_UMINv2i32 = 4126, + AArch64_UMINv4i16 = 4127, + AArch64_UMINv4i32 = 4128, + AArch64_UMINv8i16 = 4129, + AArch64_UMINv8i8 = 4130, + AArch64_UMLALv16i8_v8i16 = 4131, + AArch64_UMLALv2i32_indexed = 4132, + AArch64_UMLALv2i32_v2i64 = 4133, + AArch64_UMLALv4i16_indexed = 4134, + AArch64_UMLALv4i16_v4i32 = 4135, + AArch64_UMLALv4i32_indexed = 4136, + AArch64_UMLALv4i32_v2i64 = 4137, + AArch64_UMLALv8i16_indexed = 4138, + AArch64_UMLALv8i16_v4i32 = 4139, + AArch64_UMLALv8i8_v8i16 = 4140, + AArch64_UMLSLv16i8_v8i16 = 4141, + AArch64_UMLSLv2i32_indexed = 4142, + AArch64_UMLSLv2i32_v2i64 = 4143, + AArch64_UMLSLv4i16_indexed = 4144, + AArch64_UMLSLv4i16_v4i32 = 4145, + AArch64_UMLSLv4i32_indexed = 4146, + AArch64_UMLSLv4i32_v2i64 = 4147, + AArch64_UMLSLv8i16_indexed = 4148, + AArch64_UMLSLv8i16_v4i32 = 4149, + AArch64_UMLSLv8i8_v8i16 = 4150, + AArch64_UMOVvi16 = 4151, + AArch64_UMOVvi32 = 4152, + AArch64_UMOVvi64 = 4153, + AArch64_UMOVvi8 = 4154, + AArch64_UMSUBLrrr = 4155, + AArch64_UMULH_ZPmZ_B = 4156, + AArch64_UMULH_ZPmZ_D = 4157, + AArch64_UMULH_ZPmZ_H = 4158, + AArch64_UMULH_ZPmZ_S = 4159, + AArch64_UMULHrr = 4160, + AArch64_UMULLv16i8_v8i16 = 4161, + AArch64_UMULLv2i32_indexed = 4162, + AArch64_UMULLv2i32_v2i64 = 4163, + AArch64_UMULLv4i16_indexed = 4164, + AArch64_UMULLv4i16_v4i32 = 4165, + AArch64_UMULLv4i32_indexed = 4166, + AArch64_UMULLv4i32_v2i64 = 4167, + AArch64_UMULLv8i16_indexed = 4168, + AArch64_UMULLv8i16_v4i32 = 4169, + AArch64_UMULLv8i8_v8i16 = 4170, + AArch64_UQADD_ZI_B = 4171, + AArch64_UQADD_ZI_D = 4172, + AArch64_UQADD_ZI_H = 4173, + AArch64_UQADD_ZI_S = 4174, + AArch64_UQADD_ZZZ_B = 4175, + AArch64_UQADD_ZZZ_D = 4176, + AArch64_UQADD_ZZZ_H = 4177, + AArch64_UQADD_ZZZ_S = 4178, + AArch64_UQADDv16i8 = 4179, + AArch64_UQADDv1i16 = 4180, + AArch64_UQADDv1i32 = 4181, + AArch64_UQADDv1i64 = 4182, + AArch64_UQADDv1i8 = 4183, + AArch64_UQADDv2i32 = 4184, + AArch64_UQADDv2i64 = 4185, + AArch64_UQADDv4i16 = 4186, + AArch64_UQADDv4i32 = 4187, + AArch64_UQADDv8i16 = 4188, + AArch64_UQADDv8i8 = 4189, + AArch64_UQDECB_WPiI = 4190, + AArch64_UQDECB_XPiI = 4191, + AArch64_UQDECD_WPiI = 4192, + AArch64_UQDECD_XPiI = 4193, + AArch64_UQDECD_ZPiI = 4194, + AArch64_UQDECH_WPiI = 4195, + AArch64_UQDECH_XPiI = 4196, + AArch64_UQDECH_ZPiI = 4197, + AArch64_UQDECP_WP_B = 4198, + AArch64_UQDECP_WP_D = 4199, + AArch64_UQDECP_WP_H = 4200, + AArch64_UQDECP_WP_S = 4201, + AArch64_UQDECP_XP_B = 4202, + AArch64_UQDECP_XP_D = 4203, + AArch64_UQDECP_XP_H = 4204, + AArch64_UQDECP_XP_S = 4205, + AArch64_UQDECP_ZP_D = 4206, + AArch64_UQDECP_ZP_H = 4207, + AArch64_UQDECP_ZP_S = 4208, + AArch64_UQDECW_WPiI = 4209, + AArch64_UQDECW_XPiI = 4210, + AArch64_UQDECW_ZPiI = 4211, + AArch64_UQINCB_WPiI = 4212, + AArch64_UQINCB_XPiI = 4213, + AArch64_UQINCD_WPiI = 4214, + AArch64_UQINCD_XPiI = 4215, + AArch64_UQINCD_ZPiI = 4216, + AArch64_UQINCH_WPiI = 4217, + AArch64_UQINCH_XPiI = 4218, + AArch64_UQINCH_ZPiI = 4219, + AArch64_UQINCP_WP_B = 4220, + AArch64_UQINCP_WP_D = 4221, + AArch64_UQINCP_WP_H = 4222, + AArch64_UQINCP_WP_S = 4223, + AArch64_UQINCP_XP_B = 4224, + AArch64_UQINCP_XP_D = 4225, + AArch64_UQINCP_XP_H = 4226, + AArch64_UQINCP_XP_S = 4227, + AArch64_UQINCP_ZP_D = 4228, + AArch64_UQINCP_ZP_H = 4229, + AArch64_UQINCP_ZP_S = 4230, + AArch64_UQINCW_WPiI = 4231, + AArch64_UQINCW_XPiI = 4232, + AArch64_UQINCW_ZPiI = 4233, + AArch64_UQRSHLv16i8 = 4234, + AArch64_UQRSHLv1i16 = 4235, + AArch64_UQRSHLv1i32 = 4236, + AArch64_UQRSHLv1i64 = 4237, + AArch64_UQRSHLv1i8 = 4238, + AArch64_UQRSHLv2i32 = 4239, + AArch64_UQRSHLv2i64 = 4240, + AArch64_UQRSHLv4i16 = 4241, + AArch64_UQRSHLv4i32 = 4242, + AArch64_UQRSHLv8i16 = 4243, + AArch64_UQRSHLv8i8 = 4244, + AArch64_UQRSHRNb = 4245, + AArch64_UQRSHRNh = 4246, + AArch64_UQRSHRNs = 4247, + AArch64_UQRSHRNv16i8_shift = 4248, + AArch64_UQRSHRNv2i32_shift = 4249, + AArch64_UQRSHRNv4i16_shift = 4250, + AArch64_UQRSHRNv4i32_shift = 4251, + AArch64_UQRSHRNv8i16_shift = 4252, + AArch64_UQRSHRNv8i8_shift = 4253, + AArch64_UQSHLb = 4254, + AArch64_UQSHLd = 4255, + AArch64_UQSHLh = 4256, + AArch64_UQSHLs = 4257, + AArch64_UQSHLv16i8 = 4258, + AArch64_UQSHLv16i8_shift = 4259, + AArch64_UQSHLv1i16 = 4260, + AArch64_UQSHLv1i32 = 4261, + AArch64_UQSHLv1i64 = 4262, + AArch64_UQSHLv1i8 = 4263, + AArch64_UQSHLv2i32 = 4264, + AArch64_UQSHLv2i32_shift = 4265, + AArch64_UQSHLv2i64 = 4266, + AArch64_UQSHLv2i64_shift = 4267, + AArch64_UQSHLv4i16 = 4268, + AArch64_UQSHLv4i16_shift = 4269, + AArch64_UQSHLv4i32 = 4270, + AArch64_UQSHLv4i32_shift = 4271, + AArch64_UQSHLv8i16 = 4272, + AArch64_UQSHLv8i16_shift = 4273, + AArch64_UQSHLv8i8 = 4274, + AArch64_UQSHLv8i8_shift = 4275, + AArch64_UQSHRNb = 4276, + AArch64_UQSHRNh = 4277, + AArch64_UQSHRNs = 4278, + AArch64_UQSHRNv16i8_shift = 4279, + AArch64_UQSHRNv2i32_shift = 4280, + AArch64_UQSHRNv4i16_shift = 4281, + AArch64_UQSHRNv4i32_shift = 4282, + AArch64_UQSHRNv8i16_shift = 4283, + AArch64_UQSHRNv8i8_shift = 4284, + AArch64_UQSUB_ZI_B = 4285, + AArch64_UQSUB_ZI_D = 4286, + AArch64_UQSUB_ZI_H = 4287, + AArch64_UQSUB_ZI_S = 4288, + AArch64_UQSUB_ZZZ_B = 4289, + AArch64_UQSUB_ZZZ_D = 4290, + AArch64_UQSUB_ZZZ_H = 4291, + AArch64_UQSUB_ZZZ_S = 4292, + AArch64_UQSUBv16i8 = 4293, + AArch64_UQSUBv1i16 = 4294, + AArch64_UQSUBv1i32 = 4295, + AArch64_UQSUBv1i64 = 4296, + AArch64_UQSUBv1i8 = 4297, + AArch64_UQSUBv2i32 = 4298, + AArch64_UQSUBv2i64 = 4299, + AArch64_UQSUBv4i16 = 4300, + AArch64_UQSUBv4i32 = 4301, + AArch64_UQSUBv8i16 = 4302, + AArch64_UQSUBv8i8 = 4303, + AArch64_UQXTNv16i8 = 4304, + AArch64_UQXTNv1i16 = 4305, + AArch64_UQXTNv1i32 = 4306, + AArch64_UQXTNv1i8 = 4307, + AArch64_UQXTNv2i32 = 4308, + AArch64_UQXTNv4i16 = 4309, + AArch64_UQXTNv4i32 = 4310, + AArch64_UQXTNv8i16 = 4311, + AArch64_UQXTNv8i8 = 4312, + AArch64_URECPEv2i32 = 4313, + AArch64_URECPEv4i32 = 4314, + AArch64_URHADDv16i8 = 4315, + AArch64_URHADDv2i32 = 4316, + AArch64_URHADDv4i16 = 4317, + AArch64_URHADDv4i32 = 4318, + AArch64_URHADDv8i16 = 4319, + AArch64_URHADDv8i8 = 4320, + AArch64_URSHLv16i8 = 4321, + AArch64_URSHLv1i64 = 4322, + AArch64_URSHLv2i32 = 4323, + AArch64_URSHLv2i64 = 4324, + AArch64_URSHLv4i16 = 4325, + AArch64_URSHLv4i32 = 4326, + AArch64_URSHLv8i16 = 4327, + AArch64_URSHLv8i8 = 4328, + AArch64_URSHRd = 4329, + AArch64_URSHRv16i8_shift = 4330, + AArch64_URSHRv2i32_shift = 4331, + AArch64_URSHRv2i64_shift = 4332, + AArch64_URSHRv4i16_shift = 4333, + AArch64_URSHRv4i32_shift = 4334, + AArch64_URSHRv8i16_shift = 4335, + AArch64_URSHRv8i8_shift = 4336, + AArch64_URSQRTEv2i32 = 4337, + AArch64_URSQRTEv4i32 = 4338, + AArch64_URSRAd = 4339, + AArch64_URSRAv16i8_shift = 4340, + AArch64_URSRAv2i32_shift = 4341, + AArch64_URSRAv2i64_shift = 4342, + AArch64_URSRAv4i16_shift = 4343, + AArch64_URSRAv4i32_shift = 4344, + AArch64_URSRAv8i16_shift = 4345, + AArch64_URSRAv8i8_shift = 4346, + AArch64_USHLLv16i8_shift = 4347, + AArch64_USHLLv2i32_shift = 4348, + AArch64_USHLLv4i16_shift = 4349, + AArch64_USHLLv4i32_shift = 4350, + AArch64_USHLLv8i16_shift = 4351, + AArch64_USHLLv8i8_shift = 4352, + AArch64_USHLv16i8 = 4353, + AArch64_USHLv1i64 = 4354, + AArch64_USHLv2i32 = 4355, + AArch64_USHLv2i64 = 4356, + AArch64_USHLv4i16 = 4357, + AArch64_USHLv4i32 = 4358, + AArch64_USHLv8i16 = 4359, + AArch64_USHLv8i8 = 4360, + AArch64_USHRd = 4361, + AArch64_USHRv16i8_shift = 4362, + AArch64_USHRv2i32_shift = 4363, + AArch64_USHRv2i64_shift = 4364, + AArch64_USHRv4i16_shift = 4365, + AArch64_USHRv4i32_shift = 4366, + AArch64_USHRv8i16_shift = 4367, + AArch64_USHRv8i8_shift = 4368, + AArch64_USQADDv16i8 = 4369, + AArch64_USQADDv1i16 = 4370, + AArch64_USQADDv1i32 = 4371, + AArch64_USQADDv1i64 = 4372, + AArch64_USQADDv1i8 = 4373, + AArch64_USQADDv2i32 = 4374, + AArch64_USQADDv2i64 = 4375, + AArch64_USQADDv4i16 = 4376, + AArch64_USQADDv4i32 = 4377, + AArch64_USQADDv8i16 = 4378, + AArch64_USQADDv8i8 = 4379, + AArch64_USRAd = 4380, + AArch64_USRAv16i8_shift = 4381, + AArch64_USRAv2i32_shift = 4382, + AArch64_USRAv2i64_shift = 4383, + AArch64_USRAv4i16_shift = 4384, + AArch64_USRAv4i32_shift = 4385, + AArch64_USRAv8i16_shift = 4386, + AArch64_USRAv8i8_shift = 4387, + AArch64_USUBLv16i8_v8i16 = 4388, + AArch64_USUBLv2i32_v2i64 = 4389, + AArch64_USUBLv4i16_v4i32 = 4390, + AArch64_USUBLv4i32_v2i64 = 4391, + AArch64_USUBLv8i16_v4i32 = 4392, + AArch64_USUBLv8i8_v8i16 = 4393, + AArch64_USUBWv16i8_v8i16 = 4394, + AArch64_USUBWv2i32_v2i64 = 4395, + AArch64_USUBWv4i16_v4i32 = 4396, + AArch64_USUBWv4i32_v2i64 = 4397, + AArch64_USUBWv8i16_v4i32 = 4398, + AArch64_USUBWv8i8_v8i16 = 4399, + AArch64_UUNPKHI_ZZ_D = 4400, + AArch64_UUNPKHI_ZZ_H = 4401, + AArch64_UUNPKHI_ZZ_S = 4402, + AArch64_UUNPKLO_ZZ_D = 4403, + AArch64_UUNPKLO_ZZ_H = 4404, + AArch64_UUNPKLO_ZZ_S = 4405, + AArch64_UXTB_ZPmZ_D = 4406, + AArch64_UXTB_ZPmZ_H = 4407, + AArch64_UXTB_ZPmZ_S = 4408, + AArch64_UXTH_ZPmZ_D = 4409, + AArch64_UXTH_ZPmZ_S = 4410, + AArch64_UXTW_ZPmZ_D = 4411, + AArch64_UZP1_PPP_B = 4412, + AArch64_UZP1_PPP_D = 4413, + AArch64_UZP1_PPP_H = 4414, + AArch64_UZP1_PPP_S = 4415, + AArch64_UZP1_ZZZ_B = 4416, + AArch64_UZP1_ZZZ_D = 4417, + AArch64_UZP1_ZZZ_H = 4418, + AArch64_UZP1_ZZZ_S = 4419, + AArch64_UZP1v16i8 = 4420, + AArch64_UZP1v2i32 = 4421, + AArch64_UZP1v2i64 = 4422, + AArch64_UZP1v4i16 = 4423, + AArch64_UZP1v4i32 = 4424, + AArch64_UZP1v8i16 = 4425, + AArch64_UZP1v8i8 = 4426, + AArch64_UZP2_PPP_B = 4427, + AArch64_UZP2_PPP_D = 4428, + AArch64_UZP2_PPP_H = 4429, + AArch64_UZP2_PPP_S = 4430, + AArch64_UZP2_ZZZ_B = 4431, + AArch64_UZP2_ZZZ_D = 4432, + AArch64_UZP2_ZZZ_H = 4433, + AArch64_UZP2_ZZZ_S = 4434, + AArch64_UZP2v16i8 = 4435, + AArch64_UZP2v2i32 = 4436, + AArch64_UZP2v2i64 = 4437, + AArch64_UZP2v4i16 = 4438, + AArch64_UZP2v4i32 = 4439, + AArch64_UZP2v8i16 = 4440, + AArch64_UZP2v8i8 = 4441, + AArch64_WHILELE_PWW_B = 4442, + AArch64_WHILELE_PWW_D = 4443, + AArch64_WHILELE_PWW_H = 4444, + AArch64_WHILELE_PWW_S = 4445, + AArch64_WHILELE_PXX_B = 4446, + AArch64_WHILELE_PXX_D = 4447, + AArch64_WHILELE_PXX_H = 4448, + AArch64_WHILELE_PXX_S = 4449, + AArch64_WHILELO_PWW_B = 4450, + AArch64_WHILELO_PWW_D = 4451, + AArch64_WHILELO_PWW_H = 4452, + AArch64_WHILELO_PWW_S = 4453, + AArch64_WHILELO_PXX_B = 4454, + AArch64_WHILELO_PXX_D = 4455, + AArch64_WHILELO_PXX_H = 4456, + AArch64_WHILELO_PXX_S = 4457, + AArch64_WHILELS_PWW_B = 4458, + AArch64_WHILELS_PWW_D = 4459, + AArch64_WHILELS_PWW_H = 4460, + AArch64_WHILELS_PWW_S = 4461, + AArch64_WHILELS_PXX_B = 4462, + AArch64_WHILELS_PXX_D = 4463, + AArch64_WHILELS_PXX_H = 4464, + AArch64_WHILELS_PXX_S = 4465, + AArch64_WHILELT_PWW_B = 4466, + AArch64_WHILELT_PWW_D = 4467, + AArch64_WHILELT_PWW_H = 4468, + AArch64_WHILELT_PWW_S = 4469, + AArch64_WHILELT_PXX_B = 4470, + AArch64_WHILELT_PXX_D = 4471, + AArch64_WHILELT_PXX_H = 4472, + AArch64_WHILELT_PXX_S = 4473, + AArch64_WRFFR = 4474, + AArch64_XAR = 4475, + AArch64_XPACD = 4476, + AArch64_XPACI = 4477, + AArch64_XPACLRI = 4478, + AArch64_XTNv16i8 = 4479, + AArch64_XTNv2i32 = 4480, + AArch64_XTNv4i16 = 4481, + AArch64_XTNv4i32 = 4482, + AArch64_XTNv8i16 = 4483, + AArch64_XTNv8i8 = 4484, + AArch64_ZIP1_PPP_B = 4485, + AArch64_ZIP1_PPP_D = 4486, + AArch64_ZIP1_PPP_H = 4487, + AArch64_ZIP1_PPP_S = 4488, + AArch64_ZIP1_ZZZ_B = 4489, + AArch64_ZIP1_ZZZ_D = 4490, + AArch64_ZIP1_ZZZ_H = 4491, + AArch64_ZIP1_ZZZ_S = 4492, + AArch64_ZIP1v16i8 = 4493, + AArch64_ZIP1v2i32 = 4494, + AArch64_ZIP1v2i64 = 4495, + AArch64_ZIP1v4i16 = 4496, + AArch64_ZIP1v4i32 = 4497, + AArch64_ZIP1v8i16 = 4498, + AArch64_ZIP1v8i8 = 4499, + AArch64_ZIP2_PPP_B = 4500, + AArch64_ZIP2_PPP_D = 4501, + AArch64_ZIP2_PPP_H = 4502, + AArch64_ZIP2_PPP_S = 4503, + AArch64_ZIP2_ZZZ_B = 4504, + AArch64_ZIP2_ZZZ_D = 4505, + AArch64_ZIP2_ZZZ_H = 4506, + AArch64_ZIP2_ZZZ_S = 4507, + AArch64_ZIP2v16i8 = 4508, + AArch64_ZIP2v2i32 = 4509, + AArch64_ZIP2v2i64 = 4510, + AArch64_ZIP2v4i16 = 4511, + AArch64_ZIP2v4i32 = 4512, + AArch64_ZIP2v8i16 = 4513, + AArch64_ZIP2v8i8 = 4514, + AArch64_anonymous_1349 = 4515, + AArch64_INSTRUCTION_LIST_END = 4516 }; #endif // GET_INSTRINFO_ENUM +#ifdef GET_INSTRINFO_MC_DESC +#undef GET_INSTRINFO_MC_DESC + +#define nullptr 0 + +static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<, 2013-2019 */ +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ +|* *| +|* Target Register Enum Values *| +|* *| +|* Automatically generated file, do not edit! *| +|* *| +\*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM enum { AArch64_NoRegister, - AArch64_FP = 1, - AArch64_LR = 2, - AArch64_NZCV = 3, - AArch64_SP = 4, - AArch64_WSP = 5, - AArch64_WZR = 6, - AArch64_XZR = 7, - AArch64_B0 = 8, - AArch64_B1 = 9, - AArch64_B2 = 10, - AArch64_B3 = 11, - AArch64_B4 = 12, - AArch64_B5 = 13, - AArch64_B6 = 14, - AArch64_B7 = 15, - AArch64_B8 = 16, - AArch64_B9 = 17, - AArch64_B10 = 18, - AArch64_B11 = 19, - AArch64_B12 = 20, - AArch64_B13 = 21, - AArch64_B14 = 22, - AArch64_B15 = 23, - AArch64_B16 = 24, - AArch64_B17 = 25, - AArch64_B18 = 26, - AArch64_B19 = 27, - AArch64_B20 = 28, - AArch64_B21 = 29, - AArch64_B22 = 30, - AArch64_B23 = 31, - AArch64_B24 = 32, - AArch64_B25 = 33, - AArch64_B26 = 34, - AArch64_B27 = 35, - AArch64_B28 = 36, - AArch64_B29 = 37, - AArch64_B30 = 38, - AArch64_B31 = 39, - AArch64_D0 = 40, - AArch64_D1 = 41, - AArch64_D2 = 42, - AArch64_D3 = 43, - AArch64_D4 = 44, - AArch64_D5 = 45, - AArch64_D6 = 46, - AArch64_D7 = 47, - AArch64_D8 = 48, - AArch64_D9 = 49, - AArch64_D10 = 50, - AArch64_D11 = 51, - AArch64_D12 = 52, - AArch64_D13 = 53, - AArch64_D14 = 54, - AArch64_D15 = 55, - AArch64_D16 = 56, - AArch64_D17 = 57, - AArch64_D18 = 58, - AArch64_D19 = 59, - AArch64_D20 = 60, - AArch64_D21 = 61, - AArch64_D22 = 62, - AArch64_D23 = 63, - AArch64_D24 = 64, - AArch64_D25 = 65, - AArch64_D26 = 66, - AArch64_D27 = 67, - AArch64_D28 = 68, - AArch64_D29 = 69, - AArch64_D30 = 70, - AArch64_D31 = 71, - AArch64_H0 = 72, - AArch64_H1 = 73, - AArch64_H2 = 74, - AArch64_H3 = 75, - AArch64_H4 = 76, - AArch64_H5 = 77, - AArch64_H6 = 78, - AArch64_H7 = 79, - AArch64_H8 = 80, - AArch64_H9 = 81, - AArch64_H10 = 82, - AArch64_H11 = 83, - AArch64_H12 = 84, - AArch64_H13 = 85, - AArch64_H14 = 86, - AArch64_H15 = 87, - AArch64_H16 = 88, - AArch64_H17 = 89, - AArch64_H18 = 90, - AArch64_H19 = 91, - AArch64_H20 = 92, - AArch64_H21 = 93, - AArch64_H22 = 94, - AArch64_H23 = 95, - AArch64_H24 = 96, - AArch64_H25 = 97, - AArch64_H26 = 98, - AArch64_H27 = 99, - AArch64_H28 = 100, - AArch64_H29 = 101, - AArch64_H30 = 102, - AArch64_H31 = 103, - AArch64_Q0 = 104, - AArch64_Q1 = 105, - AArch64_Q2 = 106, - AArch64_Q3 = 107, - AArch64_Q4 = 108, - AArch64_Q5 = 109, - AArch64_Q6 = 110, - AArch64_Q7 = 111, - AArch64_Q8 = 112, - AArch64_Q9 = 113, - AArch64_Q10 = 114, - AArch64_Q11 = 115, - AArch64_Q12 = 116, - AArch64_Q13 = 117, - AArch64_Q14 = 118, - AArch64_Q15 = 119, - AArch64_Q16 = 120, - AArch64_Q17 = 121, - AArch64_Q18 = 122, - AArch64_Q19 = 123, - AArch64_Q20 = 124, - AArch64_Q21 = 125, - AArch64_Q22 = 126, - AArch64_Q23 = 127, - AArch64_Q24 = 128, - AArch64_Q25 = 129, - AArch64_Q26 = 130, - AArch64_Q27 = 131, - AArch64_Q28 = 132, - AArch64_Q29 = 133, - AArch64_Q30 = 134, - AArch64_Q31 = 135, - AArch64_S0 = 136, - AArch64_S1 = 137, - AArch64_S2 = 138, - AArch64_S3 = 139, - AArch64_S4 = 140, - AArch64_S5 = 141, - AArch64_S6 = 142, - AArch64_S7 = 143, - AArch64_S8 = 144, - AArch64_S9 = 145, - AArch64_S10 = 146, - AArch64_S11 = 147, - AArch64_S12 = 148, - AArch64_S13 = 149, - AArch64_S14 = 150, - AArch64_S15 = 151, - AArch64_S16 = 152, - AArch64_S17 = 153, - AArch64_S18 = 154, - AArch64_S19 = 155, - AArch64_S20 = 156, - AArch64_S21 = 157, - AArch64_S22 = 158, - AArch64_S23 = 159, - AArch64_S24 = 160, - AArch64_S25 = 161, - AArch64_S26 = 162, - AArch64_S27 = 163, - AArch64_S28 = 164, - AArch64_S29 = 165, - AArch64_S30 = 166, - AArch64_S31 = 167, - AArch64_W0 = 168, - AArch64_W1 = 169, - AArch64_W2 = 170, - AArch64_W3 = 171, - AArch64_W4 = 172, - AArch64_W5 = 173, - AArch64_W6 = 174, - AArch64_W7 = 175, - AArch64_W8 = 176, - AArch64_W9 = 177, - AArch64_W10 = 178, - AArch64_W11 = 179, - AArch64_W12 = 180, - AArch64_W13 = 181, - AArch64_W14 = 182, - AArch64_W15 = 183, - AArch64_W16 = 184, - AArch64_W17 = 185, - AArch64_W18 = 186, - AArch64_W19 = 187, - AArch64_W20 = 188, - AArch64_W21 = 189, - AArch64_W22 = 190, - AArch64_W23 = 191, - AArch64_W24 = 192, - AArch64_W25 = 193, - AArch64_W26 = 194, - AArch64_W27 = 195, - AArch64_W28 = 196, - AArch64_W29 = 197, - AArch64_W30 = 198, - AArch64_X0 = 199, - AArch64_X1 = 200, - AArch64_X2 = 201, - AArch64_X3 = 202, - AArch64_X4 = 203, - AArch64_X5 = 204, - AArch64_X6 = 205, - AArch64_X7 = 206, - AArch64_X8 = 207, - AArch64_X9 = 208, - AArch64_X10 = 209, - AArch64_X11 = 210, - AArch64_X12 = 211, - AArch64_X13 = 212, - AArch64_X14 = 213, - AArch64_X15 = 214, - AArch64_X16 = 215, - AArch64_X17 = 216, - AArch64_X18 = 217, - AArch64_X19 = 218, - AArch64_X20 = 219, - AArch64_X21 = 220, - AArch64_X22 = 221, - AArch64_X23 = 222, - AArch64_X24 = 223, - AArch64_X25 = 224, - AArch64_X26 = 225, - AArch64_X27 = 226, - AArch64_X28 = 227, - AArch64_D0_D1 = 228, - AArch64_D1_D2 = 229, - AArch64_D2_D3 = 230, - AArch64_D3_D4 = 231, - AArch64_D4_D5 = 232, - AArch64_D5_D6 = 233, - AArch64_D6_D7 = 234, - AArch64_D7_D8 = 235, - AArch64_D8_D9 = 236, - AArch64_D9_D10 = 237, - AArch64_D10_D11 = 238, - AArch64_D11_D12 = 239, - AArch64_D12_D13 = 240, - AArch64_D13_D14 = 241, - AArch64_D14_D15 = 242, - AArch64_D15_D16 = 243, - AArch64_D16_D17 = 244, - AArch64_D17_D18 = 245, - AArch64_D18_D19 = 246, - AArch64_D19_D20 = 247, - AArch64_D20_D21 = 248, - AArch64_D21_D22 = 249, - AArch64_D22_D23 = 250, - AArch64_D23_D24 = 251, - AArch64_D24_D25 = 252, - AArch64_D25_D26 = 253, - AArch64_D26_D27 = 254, - AArch64_D27_D28 = 255, - AArch64_D28_D29 = 256, - AArch64_D29_D30 = 257, - AArch64_D30_D31 = 258, - AArch64_D31_D0 = 259, - AArch64_D0_D1_D2_D3 = 260, - AArch64_D1_D2_D3_D4 = 261, - AArch64_D2_D3_D4_D5 = 262, - AArch64_D3_D4_D5_D6 = 263, - AArch64_D4_D5_D6_D7 = 264, - AArch64_D5_D6_D7_D8 = 265, - AArch64_D6_D7_D8_D9 = 266, - AArch64_D7_D8_D9_D10 = 267, - AArch64_D8_D9_D10_D11 = 268, - AArch64_D9_D10_D11_D12 = 269, - AArch64_D10_D11_D12_D13 = 270, - AArch64_D11_D12_D13_D14 = 271, - AArch64_D12_D13_D14_D15 = 272, - AArch64_D13_D14_D15_D16 = 273, - AArch64_D14_D15_D16_D17 = 274, - AArch64_D15_D16_D17_D18 = 275, - AArch64_D16_D17_D18_D19 = 276, - AArch64_D17_D18_D19_D20 = 277, - AArch64_D18_D19_D20_D21 = 278, - AArch64_D19_D20_D21_D22 = 279, - AArch64_D20_D21_D22_D23 = 280, - AArch64_D21_D22_D23_D24 = 281, - AArch64_D22_D23_D24_D25 = 282, - AArch64_D23_D24_D25_D26 = 283, - AArch64_D24_D25_D26_D27 = 284, - AArch64_D25_D26_D27_D28 = 285, - AArch64_D26_D27_D28_D29 = 286, - AArch64_D27_D28_D29_D30 = 287, - AArch64_D28_D29_D30_D31 = 288, - AArch64_D29_D30_D31_D0 = 289, - AArch64_D30_D31_D0_D1 = 290, - AArch64_D31_D0_D1_D2 = 291, - AArch64_D0_D1_D2 = 292, - AArch64_D1_D2_D3 = 293, - AArch64_D2_D3_D4 = 294, - AArch64_D3_D4_D5 = 295, - AArch64_D4_D5_D6 = 296, - AArch64_D5_D6_D7 = 297, - AArch64_D6_D7_D8 = 298, - AArch64_D7_D8_D9 = 299, - AArch64_D8_D9_D10 = 300, - AArch64_D9_D10_D11 = 301, - AArch64_D10_D11_D12 = 302, - AArch64_D11_D12_D13 = 303, - AArch64_D12_D13_D14 = 304, - AArch64_D13_D14_D15 = 305, - AArch64_D14_D15_D16 = 306, - AArch64_D15_D16_D17 = 307, - AArch64_D16_D17_D18 = 308, - AArch64_D17_D18_D19 = 309, - AArch64_D18_D19_D20 = 310, - AArch64_D19_D20_D21 = 311, - AArch64_D20_D21_D22 = 312, - AArch64_D21_D22_D23 = 313, - AArch64_D22_D23_D24 = 314, - AArch64_D23_D24_D25 = 315, - AArch64_D24_D25_D26 = 316, - AArch64_D25_D26_D27 = 317, - AArch64_D26_D27_D28 = 318, - AArch64_D27_D28_D29 = 319, - AArch64_D28_D29_D30 = 320, - AArch64_D29_D30_D31 = 321, - AArch64_D30_D31_D0 = 322, - AArch64_D31_D0_D1 = 323, - AArch64_Q0_Q1 = 324, - AArch64_Q1_Q2 = 325, - AArch64_Q2_Q3 = 326, - AArch64_Q3_Q4 = 327, - AArch64_Q4_Q5 = 328, - AArch64_Q5_Q6 = 329, - AArch64_Q6_Q7 = 330, - AArch64_Q7_Q8 = 331, - AArch64_Q8_Q9 = 332, - AArch64_Q9_Q10 = 333, - AArch64_Q10_Q11 = 334, - AArch64_Q11_Q12 = 335, - AArch64_Q12_Q13 = 336, - AArch64_Q13_Q14 = 337, - AArch64_Q14_Q15 = 338, - AArch64_Q15_Q16 = 339, - AArch64_Q16_Q17 = 340, - AArch64_Q17_Q18 = 341, - AArch64_Q18_Q19 = 342, - AArch64_Q19_Q20 = 343, - AArch64_Q20_Q21 = 344, - AArch64_Q21_Q22 = 345, - AArch64_Q22_Q23 = 346, - AArch64_Q23_Q24 = 347, - AArch64_Q24_Q25 = 348, - AArch64_Q25_Q26 = 349, - AArch64_Q26_Q27 = 350, - AArch64_Q27_Q28 = 351, - AArch64_Q28_Q29 = 352, - AArch64_Q29_Q30 = 353, - AArch64_Q30_Q31 = 354, - AArch64_Q31_Q0 = 355, - AArch64_Q0_Q1_Q2_Q3 = 356, - AArch64_Q1_Q2_Q3_Q4 = 357, - AArch64_Q2_Q3_Q4_Q5 = 358, - AArch64_Q3_Q4_Q5_Q6 = 359, - AArch64_Q4_Q5_Q6_Q7 = 360, - AArch64_Q5_Q6_Q7_Q8 = 361, - AArch64_Q6_Q7_Q8_Q9 = 362, - AArch64_Q7_Q8_Q9_Q10 = 363, - AArch64_Q8_Q9_Q10_Q11 = 364, - AArch64_Q9_Q10_Q11_Q12 = 365, - AArch64_Q10_Q11_Q12_Q13 = 366, - AArch64_Q11_Q12_Q13_Q14 = 367, - AArch64_Q12_Q13_Q14_Q15 = 368, - AArch64_Q13_Q14_Q15_Q16 = 369, - AArch64_Q14_Q15_Q16_Q17 = 370, - AArch64_Q15_Q16_Q17_Q18 = 371, - AArch64_Q16_Q17_Q18_Q19 = 372, - AArch64_Q17_Q18_Q19_Q20 = 373, - AArch64_Q18_Q19_Q20_Q21 = 374, - AArch64_Q19_Q20_Q21_Q22 = 375, - AArch64_Q20_Q21_Q22_Q23 = 376, - AArch64_Q21_Q22_Q23_Q24 = 377, - AArch64_Q22_Q23_Q24_Q25 = 378, - AArch64_Q23_Q24_Q25_Q26 = 379, - AArch64_Q24_Q25_Q26_Q27 = 380, - AArch64_Q25_Q26_Q27_Q28 = 381, - AArch64_Q26_Q27_Q28_Q29 = 382, - AArch64_Q27_Q28_Q29_Q30 = 383, - AArch64_Q28_Q29_Q30_Q31 = 384, - AArch64_Q29_Q30_Q31_Q0 = 385, - AArch64_Q30_Q31_Q0_Q1 = 386, - AArch64_Q31_Q0_Q1_Q2 = 387, - AArch64_Q0_Q1_Q2 = 388, - AArch64_Q1_Q2_Q3 = 389, - AArch64_Q2_Q3_Q4 = 390, - AArch64_Q3_Q4_Q5 = 391, - AArch64_Q4_Q5_Q6 = 392, - AArch64_Q5_Q6_Q7 = 393, - AArch64_Q6_Q7_Q8 = 394, - AArch64_Q7_Q8_Q9 = 395, - AArch64_Q8_Q9_Q10 = 396, - AArch64_Q9_Q10_Q11 = 397, - AArch64_Q10_Q11_Q12 = 398, - AArch64_Q11_Q12_Q13 = 399, - AArch64_Q12_Q13_Q14 = 400, - AArch64_Q13_Q14_Q15 = 401, - AArch64_Q14_Q15_Q16 = 402, - AArch64_Q15_Q16_Q17 = 403, - AArch64_Q16_Q17_Q18 = 404, - AArch64_Q17_Q18_Q19 = 405, - AArch64_Q18_Q19_Q20 = 406, - AArch64_Q19_Q20_Q21 = 407, - AArch64_Q20_Q21_Q22 = 408, - AArch64_Q21_Q22_Q23 = 409, - AArch64_Q22_Q23_Q24 = 410, - AArch64_Q23_Q24_Q25 = 411, - AArch64_Q24_Q25_Q26 = 412, - AArch64_Q25_Q26_Q27 = 413, - AArch64_Q26_Q27_Q28 = 414, - AArch64_Q27_Q28_Q29 = 415, - AArch64_Q28_Q29_Q30 = 416, - AArch64_Q29_Q30_Q31 = 417, - AArch64_Q30_Q31_Q0 = 418, - AArch64_Q31_Q0_Q1 = 419, - AArch64_NUM_TARGET_REGS // 420 + AArch64_FFR = 1, + AArch64_FP = 2, + AArch64_LR = 3, + AArch64_NZCV = 4, + AArch64_SP = 5, + AArch64_WSP = 6, + AArch64_WZR = 7, + AArch64_XZR = 8, + AArch64_B0 = 9, + AArch64_B1 = 10, + AArch64_B2 = 11, + AArch64_B3 = 12, + AArch64_B4 = 13, + AArch64_B5 = 14, + AArch64_B6 = 15, + AArch64_B7 = 16, + AArch64_B8 = 17, + AArch64_B9 = 18, + AArch64_B10 = 19, + AArch64_B11 = 20, + AArch64_B12 = 21, + AArch64_B13 = 22, + AArch64_B14 = 23, + AArch64_B15 = 24, + AArch64_B16 = 25, + AArch64_B17 = 26, + AArch64_B18 = 27, + AArch64_B19 = 28, + AArch64_B20 = 29, + AArch64_B21 = 30, + AArch64_B22 = 31, + AArch64_B23 = 32, + AArch64_B24 = 33, + AArch64_B25 = 34, + AArch64_B26 = 35, + AArch64_B27 = 36, + AArch64_B28 = 37, + AArch64_B29 = 38, + AArch64_B30 = 39, + AArch64_B31 = 40, + AArch64_D0 = 41, + AArch64_D1 = 42, + AArch64_D2 = 43, + AArch64_D3 = 44, + AArch64_D4 = 45, + AArch64_D5 = 46, + AArch64_D6 = 47, + AArch64_D7 = 48, + AArch64_D8 = 49, + AArch64_D9 = 50, + AArch64_D10 = 51, + AArch64_D11 = 52, + AArch64_D12 = 53, + AArch64_D13 = 54, + AArch64_D14 = 55, + AArch64_D15 = 56, + AArch64_D16 = 57, + AArch64_D17 = 58, + AArch64_D18 = 59, + AArch64_D19 = 60, + AArch64_D20 = 61, + AArch64_D21 = 62, + AArch64_D22 = 63, + AArch64_D23 = 64, + AArch64_D24 = 65, + AArch64_D25 = 66, + AArch64_D26 = 67, + AArch64_D27 = 68, + AArch64_D28 = 69, + AArch64_D29 = 70, + AArch64_D30 = 71, + AArch64_D31 = 72, + AArch64_H0 = 73, + AArch64_H1 = 74, + AArch64_H2 = 75, + AArch64_H3 = 76, + AArch64_H4 = 77, + AArch64_H5 = 78, + AArch64_H6 = 79, + AArch64_H7 = 80, + AArch64_H8 = 81, + AArch64_H9 = 82, + AArch64_H10 = 83, + AArch64_H11 = 84, + AArch64_H12 = 85, + AArch64_H13 = 86, + AArch64_H14 = 87, + AArch64_H15 = 88, + AArch64_H16 = 89, + AArch64_H17 = 90, + AArch64_H18 = 91, + AArch64_H19 = 92, + AArch64_H20 = 93, + AArch64_H21 = 94, + AArch64_H22 = 95, + AArch64_H23 = 96, + AArch64_H24 = 97, + AArch64_H25 = 98, + AArch64_H26 = 99, + AArch64_H27 = 100, + AArch64_H28 = 101, + AArch64_H29 = 102, + AArch64_H30 = 103, + AArch64_H31 = 104, + AArch64_P0 = 105, + AArch64_P1 = 106, + AArch64_P2 = 107, + AArch64_P3 = 108, + AArch64_P4 = 109, + AArch64_P5 = 110, + AArch64_P6 = 111, + AArch64_P7 = 112, + AArch64_P8 = 113, + AArch64_P9 = 114, + AArch64_P10 = 115, + AArch64_P11 = 116, + AArch64_P12 = 117, + AArch64_P13 = 118, + AArch64_P14 = 119, + AArch64_P15 = 120, + AArch64_Q0 = 121, + AArch64_Q1 = 122, + AArch64_Q2 = 123, + AArch64_Q3 = 124, + AArch64_Q4 = 125, + AArch64_Q5 = 126, + AArch64_Q6 = 127, + AArch64_Q7 = 128, + AArch64_Q8 = 129, + AArch64_Q9 = 130, + AArch64_Q10 = 131, + AArch64_Q11 = 132, + AArch64_Q12 = 133, + AArch64_Q13 = 134, + AArch64_Q14 = 135, + AArch64_Q15 = 136, + AArch64_Q16 = 137, + AArch64_Q17 = 138, + AArch64_Q18 = 139, + AArch64_Q19 = 140, + AArch64_Q20 = 141, + AArch64_Q21 = 142, + AArch64_Q22 = 143, + AArch64_Q23 = 144, + AArch64_Q24 = 145, + AArch64_Q25 = 146, + AArch64_Q26 = 147, + AArch64_Q27 = 148, + AArch64_Q28 = 149, + AArch64_Q29 = 150, + AArch64_Q30 = 151, + AArch64_Q31 = 152, + AArch64_S0 = 153, + AArch64_S1 = 154, + AArch64_S2 = 155, + AArch64_S3 = 156, + AArch64_S4 = 157, + AArch64_S5 = 158, + AArch64_S6 = 159, + AArch64_S7 = 160, + AArch64_S8 = 161, + AArch64_S9 = 162, + AArch64_S10 = 163, + AArch64_S11 = 164, + AArch64_S12 = 165, + AArch64_S13 = 166, + AArch64_S14 = 167, + AArch64_S15 = 168, + AArch64_S16 = 169, + AArch64_S17 = 170, + AArch64_S18 = 171, + AArch64_S19 = 172, + AArch64_S20 = 173, + AArch64_S21 = 174, + AArch64_S22 = 175, + AArch64_S23 = 176, + AArch64_S24 = 177, + AArch64_S25 = 178, + AArch64_S26 = 179, + AArch64_S27 = 180, + AArch64_S28 = 181, + AArch64_S29 = 182, + AArch64_S30 = 183, + AArch64_S31 = 184, + AArch64_W0 = 185, + AArch64_W1 = 186, + AArch64_W2 = 187, + AArch64_W3 = 188, + AArch64_W4 = 189, + AArch64_W5 = 190, + AArch64_W6 = 191, + AArch64_W7 = 192, + AArch64_W8 = 193, + AArch64_W9 = 194, + AArch64_W10 = 195, + AArch64_W11 = 196, + AArch64_W12 = 197, + AArch64_W13 = 198, + AArch64_W14 = 199, + AArch64_W15 = 200, + AArch64_W16 = 201, + AArch64_W17 = 202, + AArch64_W18 = 203, + AArch64_W19 = 204, + AArch64_W20 = 205, + AArch64_W21 = 206, + AArch64_W22 = 207, + AArch64_W23 = 208, + AArch64_W24 = 209, + AArch64_W25 = 210, + AArch64_W26 = 211, + AArch64_W27 = 212, + AArch64_W28 = 213, + AArch64_W29 = 214, + AArch64_W30 = 215, + AArch64_X0 = 216, + AArch64_X1 = 217, + AArch64_X2 = 218, + AArch64_X3 = 219, + AArch64_X4 = 220, + AArch64_X5 = 221, + AArch64_X6 = 222, + AArch64_X7 = 223, + AArch64_X8 = 224, + AArch64_X9 = 225, + AArch64_X10 = 226, + AArch64_X11 = 227, + AArch64_X12 = 228, + AArch64_X13 = 229, + AArch64_X14 = 230, + AArch64_X15 = 231, + AArch64_X16 = 232, + AArch64_X17 = 233, + AArch64_X18 = 234, + AArch64_X19 = 235, + AArch64_X20 = 236, + AArch64_X21 = 237, + AArch64_X22 = 238, + AArch64_X23 = 239, + AArch64_X24 = 240, + AArch64_X25 = 241, + AArch64_X26 = 242, + AArch64_X27 = 243, + AArch64_X28 = 244, + AArch64_Z0 = 245, + AArch64_Z1 = 246, + AArch64_Z2 = 247, + AArch64_Z3 = 248, + AArch64_Z4 = 249, + AArch64_Z5 = 250, + AArch64_Z6 = 251, + AArch64_Z7 = 252, + AArch64_Z8 = 253, + AArch64_Z9 = 254, + AArch64_Z10 = 255, + AArch64_Z11 = 256, + AArch64_Z12 = 257, + AArch64_Z13 = 258, + AArch64_Z14 = 259, + AArch64_Z15 = 260, + AArch64_Z16 = 261, + AArch64_Z17 = 262, + AArch64_Z18 = 263, + AArch64_Z19 = 264, + AArch64_Z20 = 265, + AArch64_Z21 = 266, + AArch64_Z22 = 267, + AArch64_Z23 = 268, + AArch64_Z24 = 269, + AArch64_Z25 = 270, + AArch64_Z26 = 271, + AArch64_Z27 = 272, + AArch64_Z28 = 273, + AArch64_Z29 = 274, + AArch64_Z30 = 275, + AArch64_Z31 = 276, + AArch64_Z0_HI = 277, + AArch64_Z1_HI = 278, + AArch64_Z2_HI = 279, + AArch64_Z3_HI = 280, + AArch64_Z4_HI = 281, + AArch64_Z5_HI = 282, + AArch64_Z6_HI = 283, + AArch64_Z7_HI = 284, + AArch64_Z8_HI = 285, + AArch64_Z9_HI = 286, + AArch64_Z10_HI = 287, + AArch64_Z11_HI = 288, + AArch64_Z12_HI = 289, + AArch64_Z13_HI = 290, + AArch64_Z14_HI = 291, + AArch64_Z15_HI = 292, + AArch64_Z16_HI = 293, + AArch64_Z17_HI = 294, + AArch64_Z18_HI = 295, + AArch64_Z19_HI = 296, + AArch64_Z20_HI = 297, + AArch64_Z21_HI = 298, + AArch64_Z22_HI = 299, + AArch64_Z23_HI = 300, + AArch64_Z24_HI = 301, + AArch64_Z25_HI = 302, + AArch64_Z26_HI = 303, + AArch64_Z27_HI = 304, + AArch64_Z28_HI = 305, + AArch64_Z29_HI = 306, + AArch64_Z30_HI = 307, + AArch64_Z31_HI = 308, + AArch64_D0_D1 = 309, + AArch64_D1_D2 = 310, + AArch64_D2_D3 = 311, + AArch64_D3_D4 = 312, + AArch64_D4_D5 = 313, + AArch64_D5_D6 = 314, + AArch64_D6_D7 = 315, + AArch64_D7_D8 = 316, + AArch64_D8_D9 = 317, + AArch64_D9_D10 = 318, + AArch64_D10_D11 = 319, + AArch64_D11_D12 = 320, + AArch64_D12_D13 = 321, + AArch64_D13_D14 = 322, + AArch64_D14_D15 = 323, + AArch64_D15_D16 = 324, + AArch64_D16_D17 = 325, + AArch64_D17_D18 = 326, + AArch64_D18_D19 = 327, + AArch64_D19_D20 = 328, + AArch64_D20_D21 = 329, + AArch64_D21_D22 = 330, + AArch64_D22_D23 = 331, + AArch64_D23_D24 = 332, + AArch64_D24_D25 = 333, + AArch64_D25_D26 = 334, + AArch64_D26_D27 = 335, + AArch64_D27_D28 = 336, + AArch64_D28_D29 = 337, + AArch64_D29_D30 = 338, + AArch64_D30_D31 = 339, + AArch64_D31_D0 = 340, + AArch64_D0_D1_D2_D3 = 341, + AArch64_D1_D2_D3_D4 = 342, + AArch64_D2_D3_D4_D5 = 343, + AArch64_D3_D4_D5_D6 = 344, + AArch64_D4_D5_D6_D7 = 345, + AArch64_D5_D6_D7_D8 = 346, + AArch64_D6_D7_D8_D9 = 347, + AArch64_D7_D8_D9_D10 = 348, + AArch64_D8_D9_D10_D11 = 349, + AArch64_D9_D10_D11_D12 = 350, + AArch64_D10_D11_D12_D13 = 351, + AArch64_D11_D12_D13_D14 = 352, + AArch64_D12_D13_D14_D15 = 353, + AArch64_D13_D14_D15_D16 = 354, + AArch64_D14_D15_D16_D17 = 355, + AArch64_D15_D16_D17_D18 = 356, + AArch64_D16_D17_D18_D19 = 357, + AArch64_D17_D18_D19_D20 = 358, + AArch64_D18_D19_D20_D21 = 359, + AArch64_D19_D20_D21_D22 = 360, + AArch64_D20_D21_D22_D23 = 361, + AArch64_D21_D22_D23_D24 = 362, + AArch64_D22_D23_D24_D25 = 363, + AArch64_D23_D24_D25_D26 = 364, + AArch64_D24_D25_D26_D27 = 365, + AArch64_D25_D26_D27_D28 = 366, + AArch64_D26_D27_D28_D29 = 367, + AArch64_D27_D28_D29_D30 = 368, + AArch64_D28_D29_D30_D31 = 369, + AArch64_D29_D30_D31_D0 = 370, + AArch64_D30_D31_D0_D1 = 371, + AArch64_D31_D0_D1_D2 = 372, + AArch64_D0_D1_D2 = 373, + AArch64_D1_D2_D3 = 374, + AArch64_D2_D3_D4 = 375, + AArch64_D3_D4_D5 = 376, + AArch64_D4_D5_D6 = 377, + AArch64_D5_D6_D7 = 378, + AArch64_D6_D7_D8 = 379, + AArch64_D7_D8_D9 = 380, + AArch64_D8_D9_D10 = 381, + AArch64_D9_D10_D11 = 382, + AArch64_D10_D11_D12 = 383, + AArch64_D11_D12_D13 = 384, + AArch64_D12_D13_D14 = 385, + AArch64_D13_D14_D15 = 386, + AArch64_D14_D15_D16 = 387, + AArch64_D15_D16_D17 = 388, + AArch64_D16_D17_D18 = 389, + AArch64_D17_D18_D19 = 390, + AArch64_D18_D19_D20 = 391, + AArch64_D19_D20_D21 = 392, + AArch64_D20_D21_D22 = 393, + AArch64_D21_D22_D23 = 394, + AArch64_D22_D23_D24 = 395, + AArch64_D23_D24_D25 = 396, + AArch64_D24_D25_D26 = 397, + AArch64_D25_D26_D27 = 398, + AArch64_D26_D27_D28 = 399, + AArch64_D27_D28_D29 = 400, + AArch64_D28_D29_D30 = 401, + AArch64_D29_D30_D31 = 402, + AArch64_D30_D31_D0 = 403, + AArch64_D31_D0_D1 = 404, + AArch64_Q0_Q1 = 405, + AArch64_Q1_Q2 = 406, + AArch64_Q2_Q3 = 407, + AArch64_Q3_Q4 = 408, + AArch64_Q4_Q5 = 409, + AArch64_Q5_Q6 = 410, + AArch64_Q6_Q7 = 411, + AArch64_Q7_Q8 = 412, + AArch64_Q8_Q9 = 413, + AArch64_Q9_Q10 = 414, + AArch64_Q10_Q11 = 415, + AArch64_Q11_Q12 = 416, + AArch64_Q12_Q13 = 417, + AArch64_Q13_Q14 = 418, + AArch64_Q14_Q15 = 419, + AArch64_Q15_Q16 = 420, + AArch64_Q16_Q17 = 421, + AArch64_Q17_Q18 = 422, + AArch64_Q18_Q19 = 423, + AArch64_Q19_Q20 = 424, + AArch64_Q20_Q21 = 425, + AArch64_Q21_Q22 = 426, + AArch64_Q22_Q23 = 427, + AArch64_Q23_Q24 = 428, + AArch64_Q24_Q25 = 429, + AArch64_Q25_Q26 = 430, + AArch64_Q26_Q27 = 431, + AArch64_Q27_Q28 = 432, + AArch64_Q28_Q29 = 433, + AArch64_Q29_Q30 = 434, + AArch64_Q30_Q31 = 435, + AArch64_Q31_Q0 = 436, + AArch64_Q0_Q1_Q2_Q3 = 437, + AArch64_Q1_Q2_Q3_Q4 = 438, + AArch64_Q2_Q3_Q4_Q5 = 439, + AArch64_Q3_Q4_Q5_Q6 = 440, + AArch64_Q4_Q5_Q6_Q7 = 441, + AArch64_Q5_Q6_Q7_Q8 = 442, + AArch64_Q6_Q7_Q8_Q9 = 443, + AArch64_Q7_Q8_Q9_Q10 = 444, + AArch64_Q8_Q9_Q10_Q11 = 445, + AArch64_Q9_Q10_Q11_Q12 = 446, + AArch64_Q10_Q11_Q12_Q13 = 447, + AArch64_Q11_Q12_Q13_Q14 = 448, + AArch64_Q12_Q13_Q14_Q15 = 449, + AArch64_Q13_Q14_Q15_Q16 = 450, + AArch64_Q14_Q15_Q16_Q17 = 451, + AArch64_Q15_Q16_Q17_Q18 = 452, + AArch64_Q16_Q17_Q18_Q19 = 453, + AArch64_Q17_Q18_Q19_Q20 = 454, + AArch64_Q18_Q19_Q20_Q21 = 455, + AArch64_Q19_Q20_Q21_Q22 = 456, + AArch64_Q20_Q21_Q22_Q23 = 457, + AArch64_Q21_Q22_Q23_Q24 = 458, + AArch64_Q22_Q23_Q24_Q25 = 459, + AArch64_Q23_Q24_Q25_Q26 = 460, + AArch64_Q24_Q25_Q26_Q27 = 461, + AArch64_Q25_Q26_Q27_Q28 = 462, + AArch64_Q26_Q27_Q28_Q29 = 463, + AArch64_Q27_Q28_Q29_Q30 = 464, + AArch64_Q28_Q29_Q30_Q31 = 465, + AArch64_Q29_Q30_Q31_Q0 = 466, + AArch64_Q30_Q31_Q0_Q1 = 467, + AArch64_Q31_Q0_Q1_Q2 = 468, + AArch64_Q0_Q1_Q2 = 469, + AArch64_Q1_Q2_Q3 = 470, + AArch64_Q2_Q3_Q4 = 471, + AArch64_Q3_Q4_Q5 = 472, + AArch64_Q4_Q5_Q6 = 473, + AArch64_Q5_Q6_Q7 = 474, + AArch64_Q6_Q7_Q8 = 475, + AArch64_Q7_Q8_Q9 = 476, + AArch64_Q8_Q9_Q10 = 477, + AArch64_Q9_Q10_Q11 = 478, + AArch64_Q10_Q11_Q12 = 479, + AArch64_Q11_Q12_Q13 = 480, + AArch64_Q12_Q13_Q14 = 481, + AArch64_Q13_Q14_Q15 = 482, + AArch64_Q14_Q15_Q16 = 483, + AArch64_Q15_Q16_Q17 = 484, + AArch64_Q16_Q17_Q18 = 485, + AArch64_Q17_Q18_Q19 = 486, + AArch64_Q18_Q19_Q20 = 487, + AArch64_Q19_Q20_Q21 = 488, + AArch64_Q20_Q21_Q22 = 489, + AArch64_Q21_Q22_Q23 = 490, + AArch64_Q22_Q23_Q24 = 491, + AArch64_Q23_Q24_Q25 = 492, + AArch64_Q24_Q25_Q26 = 493, + AArch64_Q25_Q26_Q27 = 494, + AArch64_Q26_Q27_Q28 = 495, + AArch64_Q27_Q28_Q29 = 496, + AArch64_Q28_Q29_Q30 = 497, + AArch64_Q29_Q30_Q31 = 498, + AArch64_Q30_Q31_Q0 = 499, + AArch64_Q31_Q0_Q1 = 500, + AArch64_WZR_W0 = 501, + AArch64_W30_WZR = 502, + AArch64_W0_W1 = 503, + AArch64_W1_W2 = 504, + AArch64_W2_W3 = 505, + AArch64_W3_W4 = 506, + AArch64_W4_W5 = 507, + AArch64_W5_W6 = 508, + AArch64_W6_W7 = 509, + AArch64_W7_W8 = 510, + AArch64_W8_W9 = 511, + AArch64_W9_W10 = 512, + AArch64_W10_W11 = 513, + AArch64_W11_W12 = 514, + AArch64_W12_W13 = 515, + AArch64_W13_W14 = 516, + AArch64_W14_W15 = 517, + AArch64_W15_W16 = 518, + AArch64_W16_W17 = 519, + AArch64_W17_W18 = 520, + AArch64_W18_W19 = 521, + AArch64_W19_W20 = 522, + AArch64_W20_W21 = 523, + AArch64_W21_W22 = 524, + AArch64_W22_W23 = 525, + AArch64_W23_W24 = 526, + AArch64_W24_W25 = 527, + AArch64_W25_W26 = 528, + AArch64_W26_W27 = 529, + AArch64_W27_W28 = 530, + AArch64_W28_W29 = 531, + AArch64_W29_W30 = 532, + AArch64_FP_LR = 533, + AArch64_LR_XZR = 534, + AArch64_XZR_X0 = 535, + AArch64_X28_FP = 536, + AArch64_X0_X1 = 537, + AArch64_X1_X2 = 538, + AArch64_X2_X3 = 539, + AArch64_X3_X4 = 540, + AArch64_X4_X5 = 541, + AArch64_X5_X6 = 542, + AArch64_X6_X7 = 543, + AArch64_X7_X8 = 544, + AArch64_X8_X9 = 545, + AArch64_X9_X10 = 546, + AArch64_X10_X11 = 547, + AArch64_X11_X12 = 548, + AArch64_X12_X13 = 549, + AArch64_X13_X14 = 550, + AArch64_X14_X15 = 551, + AArch64_X15_X16 = 552, + AArch64_X16_X17 = 553, + AArch64_X17_X18 = 554, + AArch64_X18_X19 = 555, + AArch64_X19_X20 = 556, + AArch64_X20_X21 = 557, + AArch64_X21_X22 = 558, + AArch64_X22_X23 = 559, + AArch64_X23_X24 = 560, + AArch64_X24_X25 = 561, + AArch64_X25_X26 = 562, + AArch64_X26_X27 = 563, + AArch64_X27_X28 = 564, + AArch64_Z0_Z1 = 565, + AArch64_Z1_Z2 = 566, + AArch64_Z2_Z3 = 567, + AArch64_Z3_Z4 = 568, + AArch64_Z4_Z5 = 569, + AArch64_Z5_Z6 = 570, + AArch64_Z6_Z7 = 571, + AArch64_Z7_Z8 = 572, + AArch64_Z8_Z9 = 573, + AArch64_Z9_Z10 = 574, + AArch64_Z10_Z11 = 575, + AArch64_Z11_Z12 = 576, + AArch64_Z12_Z13 = 577, + AArch64_Z13_Z14 = 578, + AArch64_Z14_Z15 = 579, + AArch64_Z15_Z16 = 580, + AArch64_Z16_Z17 = 581, + AArch64_Z17_Z18 = 582, + AArch64_Z18_Z19 = 583, + AArch64_Z19_Z20 = 584, + AArch64_Z20_Z21 = 585, + AArch64_Z21_Z22 = 586, + AArch64_Z22_Z23 = 587, + AArch64_Z23_Z24 = 588, + AArch64_Z24_Z25 = 589, + AArch64_Z25_Z26 = 590, + AArch64_Z26_Z27 = 591, + AArch64_Z27_Z28 = 592, + AArch64_Z28_Z29 = 593, + AArch64_Z29_Z30 = 594, + AArch64_Z30_Z31 = 595, + AArch64_Z31_Z0 = 596, + AArch64_Z0_Z1_Z2_Z3 = 597, + AArch64_Z1_Z2_Z3_Z4 = 598, + AArch64_Z2_Z3_Z4_Z5 = 599, + AArch64_Z3_Z4_Z5_Z6 = 600, + AArch64_Z4_Z5_Z6_Z7 = 601, + AArch64_Z5_Z6_Z7_Z8 = 602, + AArch64_Z6_Z7_Z8_Z9 = 603, + AArch64_Z7_Z8_Z9_Z10 = 604, + AArch64_Z8_Z9_Z10_Z11 = 605, + AArch64_Z9_Z10_Z11_Z12 = 606, + AArch64_Z10_Z11_Z12_Z13 = 607, + AArch64_Z11_Z12_Z13_Z14 = 608, + AArch64_Z12_Z13_Z14_Z15 = 609, + AArch64_Z13_Z14_Z15_Z16 = 610, + AArch64_Z14_Z15_Z16_Z17 = 611, + AArch64_Z15_Z16_Z17_Z18 = 612, + AArch64_Z16_Z17_Z18_Z19 = 613, + AArch64_Z17_Z18_Z19_Z20 = 614, + AArch64_Z18_Z19_Z20_Z21 = 615, + AArch64_Z19_Z20_Z21_Z22 = 616, + AArch64_Z20_Z21_Z22_Z23 = 617, + AArch64_Z21_Z22_Z23_Z24 = 618, + AArch64_Z22_Z23_Z24_Z25 = 619, + AArch64_Z23_Z24_Z25_Z26 = 620, + AArch64_Z24_Z25_Z26_Z27 = 621, + AArch64_Z25_Z26_Z27_Z28 = 622, + AArch64_Z26_Z27_Z28_Z29 = 623, + AArch64_Z27_Z28_Z29_Z30 = 624, + AArch64_Z28_Z29_Z30_Z31 = 625, + AArch64_Z29_Z30_Z31_Z0 = 626, + AArch64_Z30_Z31_Z0_Z1 = 627, + AArch64_Z31_Z0_Z1_Z2 = 628, + AArch64_Z0_Z1_Z2 = 629, + AArch64_Z1_Z2_Z3 = 630, + AArch64_Z2_Z3_Z4 = 631, + AArch64_Z3_Z4_Z5 = 632, + AArch64_Z4_Z5_Z6 = 633, + AArch64_Z5_Z6_Z7 = 634, + AArch64_Z6_Z7_Z8 = 635, + AArch64_Z7_Z8_Z9 = 636, + AArch64_Z8_Z9_Z10 = 637, + AArch64_Z9_Z10_Z11 = 638, + AArch64_Z10_Z11_Z12 = 639, + AArch64_Z11_Z12_Z13 = 640, + AArch64_Z12_Z13_Z14 = 641, + AArch64_Z13_Z14_Z15 = 642, + AArch64_Z14_Z15_Z16 = 643, + AArch64_Z15_Z16_Z17 = 644, + AArch64_Z16_Z17_Z18 = 645, + AArch64_Z17_Z18_Z19 = 646, + AArch64_Z18_Z19_Z20 = 647, + AArch64_Z19_Z20_Z21 = 648, + AArch64_Z20_Z21_Z22 = 649, + AArch64_Z21_Z22_Z23 = 650, + AArch64_Z22_Z23_Z24 = 651, + AArch64_Z23_Z24_Z25 = 652, + AArch64_Z24_Z25_Z26 = 653, + AArch64_Z25_Z26_Z27 = 654, + AArch64_Z26_Z27_Z28 = 655, + AArch64_Z27_Z28_Z29 = 656, + AArch64_Z28_Z29_Z30 = 657, + AArch64_Z29_Z30_Z31 = 658, + AArch64_Z30_Z31_Z0 = 659, + AArch64_Z31_Z0_Z1 = 660, + AArch64_NUM_TARGET_REGS // 661 }; // Register classes enum { AArch64_FPR8RegClassID = 0, AArch64_FPR16RegClassID = 1, - AArch64_GPR32allRegClassID = 2, - AArch64_FPR32RegClassID = 3, - AArch64_GPR32RegClassID = 4, - AArch64_GPR32spRegClassID = 5, - AArch64_GPR32commonRegClassID = 6, - AArch64_CCRRegClassID = 7, - AArch64_GPR32sponlyRegClassID = 8, - AArch64_GPR64allRegClassID = 9, - AArch64_FPR64RegClassID = 10, - AArch64_GPR64RegClassID = 11, - AArch64_GPR64spRegClassID = 12, - AArch64_GPR64commonRegClassID = 13, - AArch64_tcGPR64RegClassID = 14, - AArch64_GPR64sponlyRegClassID = 15, - AArch64_DDRegClassID = 16, - AArch64_FPR128RegClassID = 17, - AArch64_FPR128_loRegClassID = 18, - AArch64_DDDRegClassID = 19, - AArch64_DDDDRegClassID = 20, - AArch64_QQRegClassID = 21, - AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 22, - AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 23, - AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 24, - AArch64_QQQRegClassID = 25, - AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 26, - AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 27, - AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 28, - AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 29, - AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 30, - AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 31, - AArch64_QQQQRegClassID = 32, - AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 33, - AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 34, - AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 35, - AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 36, - AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 37, - AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 38, - AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 39, - AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 40, - AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 41, - AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 42, + AArch64_PPRRegClassID = 2, + AArch64_PPR_3bRegClassID = 3, + AArch64_GPR32allRegClassID = 4, + AArch64_FPR32RegClassID = 5, + AArch64_GPR32RegClassID = 6, + AArch64_GPR32spRegClassID = 7, + AArch64_GPR32commonRegClassID = 8, + AArch64_CCRRegClassID = 9, + AArch64_GPR32sponlyRegClassID = 10, + AArch64_WSeqPairsClassRegClassID = 11, + AArch64_WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 12, + AArch64_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 13, + AArch64_WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 14, + AArch64_GPR64allRegClassID = 15, + AArch64_FPR64RegClassID = 16, + AArch64_GPR64RegClassID = 17, + AArch64_GPR64spRegClassID = 18, + AArch64_GPR64commonRegClassID = 19, + AArch64_tcGPR64RegClassID = 20, + AArch64_GPR64sponlyRegClassID = 21, + AArch64_DDRegClassID = 22, + AArch64_XSeqPairsClassRegClassID = 23, + AArch64_XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 24, + AArch64_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 25, + AArch64_XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 26, + AArch64_XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 27, + AArch64_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 28, + AArch64_XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 29, + AArch64_FPR128RegClassID = 30, + AArch64_ZPRRegClassID = 31, + AArch64_FPR128_loRegClassID = 32, + AArch64_ZPR_4bRegClassID = 33, + AArch64_ZPR_3bRegClassID = 34, + AArch64_DDDRegClassID = 35, + AArch64_DDDDRegClassID = 36, + AArch64_QQRegClassID = 37, + AArch64_ZPR2RegClassID = 38, + AArch64_QQ_with_qsub0_in_FPR128_loRegClassID = 39, + AArch64_QQ_with_qsub1_in_FPR128_loRegClassID = 40, + AArch64_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 41, + AArch64_ZPR2_with_zsub_in_FPR128_loRegClassID = 42, + AArch64_QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 43, + AArch64_ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 44, + AArch64_ZPR2_with_zsub0_in_ZPR_3bRegClassID = 45, + AArch64_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 46, + AArch64_ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 47, + AArch64_QQQRegClassID = 48, + AArch64_ZPR3RegClassID = 49, + AArch64_QQQ_with_qsub0_in_FPR128_loRegClassID = 50, + AArch64_QQQ_with_qsub1_in_FPR128_loRegClassID = 51, + AArch64_QQQ_with_qsub2_in_FPR128_loRegClassID = 52, + AArch64_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 53, + AArch64_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 54, + AArch64_ZPR3_with_zsub_in_FPR128_loRegClassID = 55, + AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 56, + AArch64_QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 57, + AArch64_ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 58, + AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 59, + AArch64_QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 60, + AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 61, + AArch64_ZPR3_with_zsub0_in_ZPR_3bRegClassID = 62, + AArch64_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 63, + AArch64_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 64, + AArch64_ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 65, + AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 66, + AArch64_ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 67, + AArch64_QQQQRegClassID = 68, + AArch64_ZPR4RegClassID = 69, + AArch64_QQQQ_with_qsub0_in_FPR128_loRegClassID = 70, + AArch64_QQQQ_with_qsub1_in_FPR128_loRegClassID = 71, + AArch64_QQQQ_with_qsub2_in_FPR128_loRegClassID = 72, + AArch64_QQQQ_with_qsub3_in_FPR128_loRegClassID = 73, + AArch64_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 74, + AArch64_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 75, + AArch64_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 76, + AArch64_ZPR4_with_zsub_in_FPR128_loRegClassID = 77, + AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 78, + AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 79, + AArch64_QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 80, + AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 81, + AArch64_ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 82, + AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 83, + AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 84, + AArch64_QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 85, + AArch64_ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 86, + AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 87, + AArch64_QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 88, + AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 89, + AArch64_ZPR4_with_zsub0_in_ZPR_3bRegClassID = 90, + AArch64_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 91, + AArch64_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 92, + AArch64_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 93, + AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 94, + AArch64_ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 95, + AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 96, + AArch64_ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 97, + AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 98, + AArch64_ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 99, }; // Register alternate name indices enum { - AArch64_NoRegAltName, // 0 - AArch64_vlist1, // 1 - AArch64_vreg, // 2 - AArch64_NUM_TARGET_REG_ALT_NAMES = 3 + AArch64_NoRegAltName, // 0 + AArch64_vlist1, // 1 + AArch64_vreg, // 2 + AArch64_NUM_TARGET_REG_ALT_NAMES = 3 }; // Subregister indices @@ -510,43 +808,90 @@ enum { AArch64_qsub3, // 13 AArch64_ssub, // 14 AArch64_sub_32, // 15 - AArch64_dsub1_then_bsub, // 16 - AArch64_dsub1_then_hsub, // 17 - AArch64_dsub1_then_ssub, // 18 - AArch64_dsub3_then_bsub, // 19 - AArch64_dsub3_then_hsub, // 20 - AArch64_dsub3_then_ssub, // 21 - AArch64_dsub2_then_bsub, // 22 - AArch64_dsub2_then_hsub, // 23 - AArch64_dsub2_then_ssub, // 24 - AArch64_qsub1_then_bsub, // 25 - AArch64_qsub1_then_dsub, // 26 - AArch64_qsub1_then_hsub, // 27 - AArch64_qsub1_then_ssub, // 28 - AArch64_qsub3_then_bsub, // 29 - AArch64_qsub3_then_dsub, // 30 - AArch64_qsub3_then_hsub, // 31 - AArch64_qsub3_then_ssub, // 32 - AArch64_qsub2_then_bsub, // 33 - AArch64_qsub2_then_dsub, // 34 - AArch64_qsub2_then_hsub, // 35 - AArch64_qsub2_then_ssub, // 36 - AArch64_dsub0_dsub1, // 37 - AArch64_dsub0_dsub1_dsub2, // 38 - AArch64_dsub1_dsub2, // 39 - AArch64_dsub1_dsub2_dsub3, // 40 - AArch64_dsub2_dsub3, // 41 - AArch64_dsub_qsub1_then_dsub, // 42 - AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 43 - AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 44 - AArch64_qsub0_qsub1, // 45 - AArch64_qsub0_qsub1_qsub2, // 46 - AArch64_qsub1_qsub2, // 47 - AArch64_qsub1_qsub2_qsub3, // 48 - AArch64_qsub2_qsub3, // 49 - AArch64_qsub1_then_dsub_qsub2_then_dsub, // 50 - AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 51 - AArch64_qsub2_then_dsub_qsub3_then_dsub, // 52 + AArch64_sube32, // 16 + AArch64_sube64, // 17 + AArch64_subo32, // 18 + AArch64_subo64, // 19 + AArch64_zsub, // 20 + AArch64_zsub0, // 21 + AArch64_zsub1, // 22 + AArch64_zsub2, // 23 + AArch64_zsub3, // 24 + AArch64_zsub_hi, // 25 + AArch64_dsub1_then_bsub, // 26 + AArch64_dsub1_then_hsub, // 27 + AArch64_dsub1_then_ssub, // 28 + AArch64_dsub3_then_bsub, // 29 + AArch64_dsub3_then_hsub, // 30 + AArch64_dsub3_then_ssub, // 31 + AArch64_dsub2_then_bsub, // 32 + AArch64_dsub2_then_hsub, // 33 + AArch64_dsub2_then_ssub, // 34 + AArch64_qsub1_then_bsub, // 35 + AArch64_qsub1_then_dsub, // 36 + AArch64_qsub1_then_hsub, // 37 + AArch64_qsub1_then_ssub, // 38 + AArch64_qsub3_then_bsub, // 39 + AArch64_qsub3_then_dsub, // 40 + AArch64_qsub3_then_hsub, // 41 + AArch64_qsub3_then_ssub, // 42 + AArch64_qsub2_then_bsub, // 43 + AArch64_qsub2_then_dsub, // 44 + AArch64_qsub2_then_hsub, // 45 + AArch64_qsub2_then_ssub, // 46 + AArch64_subo64_then_sub_32, // 47 + AArch64_zsub1_then_bsub, // 48 + AArch64_zsub1_then_dsub, // 49 + AArch64_zsub1_then_hsub, // 50 + AArch64_zsub1_then_ssub, // 51 + AArch64_zsub1_then_zsub, // 52 + AArch64_zsub1_then_zsub_hi, // 53 + AArch64_zsub3_then_bsub, // 54 + AArch64_zsub3_then_dsub, // 55 + AArch64_zsub3_then_hsub, // 56 + AArch64_zsub3_then_ssub, // 57 + AArch64_zsub3_then_zsub, // 58 + AArch64_zsub3_then_zsub_hi, // 59 + AArch64_zsub2_then_bsub, // 60 + AArch64_zsub2_then_dsub, // 61 + AArch64_zsub2_then_hsub, // 62 + AArch64_zsub2_then_ssub, // 63 + AArch64_zsub2_then_zsub, // 64 + AArch64_zsub2_then_zsub_hi, // 65 + AArch64_dsub0_dsub1, // 66 + AArch64_dsub0_dsub1_dsub2, // 67 + AArch64_dsub1_dsub2, // 68 + AArch64_dsub1_dsub2_dsub3, // 69 + AArch64_dsub2_dsub3, // 70 + AArch64_dsub_qsub1_then_dsub, // 71 + AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 72 + AArch64_dsub_qsub1_then_dsub_qsub2_then_dsub, // 73 + AArch64_qsub0_qsub1, // 74 + AArch64_qsub0_qsub1_qsub2, // 75 + AArch64_qsub1_qsub2, // 76 + AArch64_qsub1_qsub2_qsub3, // 77 + AArch64_qsub2_qsub3, // 78 + AArch64_qsub1_then_dsub_qsub2_then_dsub, // 79 + AArch64_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 80 + AArch64_qsub2_then_dsub_qsub3_then_dsub, // 81 + AArch64_sub_32_subo64_then_sub_32, // 82 + AArch64_dsub_zsub1_then_dsub, // 83 + AArch64_zsub_zsub1_then_zsub, // 84 + AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 85 + AArch64_dsub_zsub1_then_dsub_zsub2_then_dsub, // 86 + AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 87 + AArch64_zsub_zsub1_then_zsub_zsub2_then_zsub, // 88 + AArch64_zsub0_zsub1, // 89 + AArch64_zsub0_zsub1_zsub2, // 90 + AArch64_zsub1_zsub2, // 91 + AArch64_zsub1_zsub2_zsub3, // 92 + AArch64_zsub2_zsub3, // 93 + AArch64_zsub1_then_dsub_zsub2_then_dsub, // 94 + AArch64_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 95 + AArch64_zsub1_then_zsub_zsub2_then_zsub, // 96 + AArch64_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 97 + AArch64_zsub2_then_dsub_zsub3_then_dsub, // 98 + AArch64_zsub2_then_zsub_zsub3_then_zsub, // 99 AArch64_NUM_TARGET_SUBREGS }; @@ -555,933 +900,1609 @@ enum { #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC + static const MCPhysReg AArch64RegDiffLists[] = { - /* 0 */ 65185, 1, 1, 1, 0, - /* 5 */ 65281, 1, 1, 1, 0, - /* 10 */ 5, 29, 1, 1, 0, - /* 15 */ 65153, 1, 1, 0, - /* 19 */ 65249, 1, 1, 0, - /* 23 */ 5, 1, 29, 1, 0, - /* 28 */ 5, 30, 1, 0, - /* 32 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 218, 1, 0, - /* 47 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 250, 1, 0, - /* 62 */ 65217, 1, 0, - /* 65 */ 65313, 1, 0, - /* 68 */ 64, 64, 65440, 64, 123, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, - /* 91 */ 219, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, - /* 101 */ 64, 64, 65440, 64, 124, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, - /* 124 */ 220, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, - /* 134 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0, - /* 146 */ 64, 64, 65440, 64, 123, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, - /* 169 */ 219, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, - /* 179 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0, - /* 191 */ 65503, 1, 128, 65503, 1, 0, - /* 197 */ 3, 0, - /* 199 */ 4, 0, - /* 201 */ 5, 1, 1, 29, 0, - /* 206 */ 64, 64, 65440, 64, 123, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, - /* 229 */ 219, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, - /* 239 */ 5, 1, 30, 0, - /* 243 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0, - /* 255 */ 5, 31, 0, - /* 258 */ 65504, 31, 97, 65504, 31, 0, - /* 264 */ 96, 0, - /* 266 */ 196, 0, - /* 268 */ 65316, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 219, 0, - /* 280 */ 65316, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 251, 0, - /* 292 */ 65339, 0, - /* 294 */ 65340, 0, - /* 296 */ 65374, 0, - /* 298 */ 65405, 0, - /* 300 */ 65437, 0, - /* 302 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 218, 64, 32, 1, 65440, 0, - /* 323 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 250, 64, 32, 1, 65440, 0, - /* 344 */ 65252, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 250, 64, 32, 65505, 65440, 0, - /* 365 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0, - /* 397 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65473, 64, 65441, 0, - /* 419 */ 65469, 0, - /* 421 */ 65348, 96, 65472, 65472, 1, 96, 65472, 65472, 0, - /* 430 */ 65348, 96, 65472, 65472, 33, 96, 65472, 65472, 0, - /* 439 */ 65472, 96, 65472, 65472, 0, - /* 444 */ 65284, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0, - /* 476 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 217, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, - /* 508 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, - /* 540 */ 65316, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65441, 64, 65473, 0, - /* 562 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 217, 64, 65473, 64, 65473, 0, - /* 584 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 249, 64, 65473, 64, 65473, 0, - /* 606 */ 65501, 0, - /* 608 */ 65284, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 250, 65505, 0, - /* 623 */ 65533, 0, - /* 625 */ 65535, 0, + /* 0 */ 64945, 1, 1, 1, 74, 1, 1, 1, 0, + /* 9 */ 65105, 1, 1, 1, 0, + /* 14 */ 65201, 1, 1, 1, 0, + /* 19 */ 6, 29, 1, 1, 0, + /* 24 */ 6, 29, 1, 1, 46, 29, 1, 1, 0, + /* 33 */ 65324, 499, 30, 1, 1, 0, + /* 39 */ 64913, 1, 1, 75, 1, 1, 0, + /* 46 */ 65073, 1, 1, 0, + /* 50 */ 65169, 1, 1, 0, + /* 54 */ 6, 1, 29, 1, 0, + /* 59 */ 6, 1, 29, 1, 46, 1, 29, 1, 0, + /* 68 */ 6, 30, 1, 0, + /* 72 */ 6, 30, 1, 46, 30, 1, 0, + /* 79 */ 1, 493, 1, 32, 1, 0, + /* 85 */ 31, 286, 1, 33, 1, 0, + /* 91 */ 64977, 1, 76, 1, 0, + /* 96 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0, + /* 111 */ 320, 1, 0, + /* 114 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0, + /* 129 */ 526, 1, 0, + /* 132 */ 530, 1, 0, + /* 135 */ 65053, 1, 0, + /* 138 */ 65087, 1, 0, + /* 141 */ 65137, 1, 0, + /* 144 */ 65218, 1, 0, + /* 147 */ 65233, 1, 0, + /* 150 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, + /* 183 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 127, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, + /* 203 */ 65504, 319, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, + /* 214 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, + /* 247 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 97, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, + /* 267 */ 65504, 320, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, + /* 278 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 128, 63, 65503, 34, 65503, 1, 0, + /* 296 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, + /* 329 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 97, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, + /* 349 */ 65504, 319, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, + /* 360 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 97, 64, 65504, 63, 65503, 1, 0, + /* 378 */ 65503, 1, 128, 65503, 1, 192, 65503, 1, 0, + /* 387 */ 31, 285, 2, 32, 2, 0, + /* 393 */ 319, 2, 0, + /* 396 */ 65324, 529, 1, 1, 3, 0, + /* 402 */ 2, 3, 0, + /* 405 */ 531, 3, 0, + /* 408 */ 65004, 3, 0, + /* 411 */ 4, 0, + /* 413 */ 5, 0, + /* 415 */ 31, 286, 1, 5, 28, 0, + /* 421 */ 292, 28, 0, + /* 424 */ 6, 1, 1, 29, 0, + /* 429 */ 6, 1, 1, 29, 46, 1, 1, 29, 0, + /* 438 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, + /* 471 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 98, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, + /* 491 */ 65504, 319, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, + /* 502 */ 6, 1, 30, 0, + /* 506 */ 6, 1, 30, 46, 1, 30, 0, + /* 513 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 98, 63, 1, 65503, 1, 30, 0, + /* 531 */ 6, 31, 0, + /* 534 */ 6, 31, 46, 31, 0, + /* 539 */ 65504, 31, 97, 65504, 31, 161, 65504, 31, 0, + /* 548 */ 32, 0, + /* 550 */ 34, 0, + /* 552 */ 5, 49, 0, + /* 555 */ 63936, 49, 0, + /* 558 */ 65297, 77, 0, + /* 561 */ 1, 81, 0, + /* 564 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0, + /* 581 */ 65216, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0, + /* 598 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 96, 1, 65280, 96, 0, + /* 628 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 1, 65280, 96, 0, + /* 658 */ 65152, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 96, 65505, 65280, 96, 0, + /* 688 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65441, 65311, 64, 32, 64, 65345, 96, 0, + /* 734 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65441, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0, + /* 780 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0, + /* 826 */ 65184, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 96, 64, 65473, 64, 65473, 65279, 64, 32, 64, 65377, 96, 0, + /* 872 */ 96, 160, 0, + /* 875 */ 65042, 178, 0, + /* 878 */ 212, 0, + /* 880 */ 65412, 65456, 112, 65456, 65472, 268, 0, + /* 887 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0, + /* 899 */ 65009, 65535, 209, 65505, 316, 0, + /* 905 */ 65005, 212, 65325, 212, 317, 0, + /* 911 */ 65244, 65505, 65325, 212, 317, 0, + /* 917 */ 65215, 65505, 32, 65505, 317, 0, + /* 923 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0, + /* 935 */ 65005, 212, 65329, 65535, 495, 0, + /* 941 */ 65323, 0, + /* 943 */ 65249, 65328, 0, + /* 946 */ 65342, 0, + /* 948 */ 65374, 0, + /* 950 */ 65389, 0, + /* 952 */ 65405, 0, + /* 954 */ 65421, 0, + /* 956 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0, + /* 977 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0, + /* 998 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0, + /* 1019 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0, + /* 1051 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0, + /* 1073 */ 65469, 0, + /* 1075 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0, + /* 1084 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0, + /* 1093 */ 65456, 112, 65456, 65472, 0, + /* 1098 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0, + /* 1130 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, + /* 1162 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, + /* 1194 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0, + /* 1216 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0, + /* 1238 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0, + /* 1260 */ 65501, 0, + /* 1262 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0, + /* 1277 */ 65533, 0, + /* 1279 */ 65535, 0, }; static const uint16_t AArch64SubRegIdxLists[] = { /* 0 */ 2, 14, 7, 1, 0, /* 5 */ 15, 0, - /* 7 */ 3, 14, 7, 1, 4, 18, 17, 16, 0, - /* 16 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 37, 39, 0, - /* 31 */ 3, 14, 7, 1, 4, 18, 17, 16, 5, 24, 23, 22, 6, 21, 20, 19, 37, 38, 39, 40, 41, 0, - /* 53 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 42, 0, - /* 65 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 42, 44, 45, 47, 50, 0, - /* 86 */ 10, 2, 14, 7, 1, 11, 26, 28, 27, 25, 12, 34, 36, 35, 33, 13, 30, 32, 31, 29, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0, + /* 7 */ 16, 18, 0, + /* 10 */ 20, 2, 14, 7, 1, 25, 0, + /* 17 */ 3, 14, 7, 1, 4, 28, 27, 26, 0, + /* 26 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 66, 68, 0, + /* 41 */ 3, 14, 7, 1, 4, 28, 27, 26, 5, 34, 33, 32, 6, 31, 30, 29, 66, 67, 68, 69, 70, 0, + /* 63 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 71, 0, + /* 75 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 71, 73, 74, 76, 79, 0, + /* 96 */ 10, 2, 14, 7, 1, 11, 36, 38, 37, 35, 12, 44, 46, 45, 43, 13, 40, 42, 41, 39, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 0, + /* 128 */ 17, 15, 19, 47, 82, 0, + /* 134 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 83, 84, 0, + /* 151 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 83, 84, 86, 88, 89, 91, 94, 96, 0, + /* 181 */ 21, 20, 2, 14, 7, 1, 25, 22, 52, 49, 51, 50, 48, 53, 23, 64, 61, 63, 62, 60, 65, 24, 58, 55, 57, 56, 54, 59, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 0, }; -static MCRegisterDesc AArch64RegDesc[] = { // Descriptors +static MCRegisterDesc AArch64RegDesc[] = { { 3, 0, 0, 0, 0, 0 }, - { 1518, 266, 4, 5, 10001, 26 }, - { 1525, 266, 4, 5, 10001, 26 }, - { 1536, 4, 4, 4, 10001, 0 }, - { 1522, 3, 4, 5, 3152, 26 }, - { 1521, 4, 625, 4, 3152, 0 }, - { 1528, 4, 3, 4, 3184, 0 }, - { 1532, 625, 4, 5, 3184, 26 }, - { 146, 4, 101, 4, 9969, 0 }, - { 335, 4, 146, 4, 9969, 0 }, - { 480, 4, 206, 4, 9969, 0 }, - { 625, 4, 68, 4, 9969, 0 }, - { 768, 4, 68, 4, 9969, 0 }, - { 911, 4, 68, 4, 9969, 0 }, - { 1054, 4, 68, 4, 9969, 0 }, - { 1197, 4, 68, 4, 9969, 0 }, - { 1340, 4, 68, 4, 9969, 0 }, - { 1479, 4, 68, 4, 9969, 0 }, - { 0, 4, 68, 4, 9969, 0 }, - { 191, 4, 68, 4, 9969, 0 }, - { 378, 4, 68, 4, 9969, 0 }, - { 521, 4, 68, 4, 9969, 0 }, - { 664, 4, 68, 4, 9969, 0 }, - { 807, 4, 68, 4, 9969, 0 }, - { 950, 4, 68, 4, 9969, 0 }, - { 1093, 4, 68, 4, 9969, 0 }, - { 1236, 4, 68, 4, 9969, 0 }, - { 1379, 4, 68, 4, 9969, 0 }, - { 46, 4, 68, 4, 9969, 0 }, - { 239, 4, 68, 4, 9969, 0 }, - { 428, 4, 68, 4, 9969, 0 }, - { 573, 4, 68, 4, 9969, 0 }, - { 716, 4, 68, 4, 9969, 0 }, - { 859, 4, 68, 4, 9969, 0 }, - { 1002, 4, 68, 4, 9969, 0 }, - { 1145, 4, 68, 4, 9969, 0 }, - { 1288, 4, 68, 4, 9969, 0 }, - { 1431, 4, 68, 4, 9969, 0 }, - { 98, 4, 68, 4, 9969, 0 }, - { 291, 4, 68, 4, 9969, 0 }, - { 161, 426, 104, 1, 9697, 3 }, - { 349, 426, 149, 1, 9697, 3 }, - { 493, 426, 209, 1, 9697, 3 }, - { 637, 426, 71, 1, 9697, 3 }, - { 780, 426, 71, 1, 9697, 3 }, - { 923, 426, 71, 1, 9697, 3 }, - { 1066, 426, 71, 1, 9697, 3 }, - { 1209, 426, 71, 1, 9697, 3 }, - { 1352, 426, 71, 1, 9697, 3 }, - { 1491, 426, 71, 1, 9697, 3 }, - { 13, 426, 71, 1, 9697, 3 }, - { 205, 426, 71, 1, 9697, 3 }, - { 393, 426, 71, 1, 9697, 3 }, - { 537, 426, 71, 1, 9697, 3 }, - { 680, 426, 71, 1, 9697, 3 }, - { 823, 426, 71, 1, 9697, 3 }, - { 966, 426, 71, 1, 9697, 3 }, - { 1109, 426, 71, 1, 9697, 3 }, - { 1252, 426, 71, 1, 9697, 3 }, - { 1395, 426, 71, 1, 9697, 3 }, - { 62, 426, 71, 1, 9697, 3 }, - { 255, 426, 71, 1, 9697, 3 }, - { 444, 426, 71, 1, 9697, 3 }, - { 589, 426, 71, 1, 9697, 3 }, - { 732, 426, 71, 1, 9697, 3 }, - { 875, 426, 71, 1, 9697, 3 }, - { 1018, 426, 71, 1, 9697, 3 }, - { 1161, 426, 71, 1, 9697, 3 }, - { 1304, 426, 71, 1, 9697, 3 }, - { 1447, 426, 71, 1, 9697, 3 }, - { 114, 426, 71, 1, 9697, 3 }, - { 307, 426, 71, 1, 9697, 3 }, - { 164, 428, 102, 3, 6705, 3 }, - { 352, 428, 147, 3, 6705, 3 }, - { 496, 428, 207, 3, 6705, 3 }, - { 640, 428, 69, 3, 6705, 3 }, - { 783, 428, 69, 3, 6705, 3 }, - { 926, 428, 69, 3, 6705, 3 }, - { 1069, 428, 69, 3, 6705, 3 }, - { 1212, 428, 69, 3, 6705, 3 }, - { 1355, 428, 69, 3, 6705, 3 }, - { 1494, 428, 69, 3, 6705, 3 }, - { 17, 428, 69, 3, 6705, 3 }, - { 209, 428, 69, 3, 6705, 3 }, - { 397, 428, 69, 3, 6705, 3 }, - { 541, 428, 69, 3, 6705, 3 }, - { 684, 428, 69, 3, 6705, 3 }, - { 827, 428, 69, 3, 6705, 3 }, - { 970, 428, 69, 3, 6705, 3 }, - { 1113, 428, 69, 3, 6705, 3 }, - { 1256, 428, 69, 3, 6705, 3 }, - { 1399, 428, 69, 3, 6705, 3 }, - { 66, 428, 69, 3, 6705, 3 }, - { 259, 428, 69, 3, 6705, 3 }, - { 448, 428, 69, 3, 6705, 3 }, - { 593, 428, 69, 3, 6705, 3 }, - { 736, 428, 69, 3, 6705, 3 }, - { 879, 428, 69, 3, 6705, 3 }, - { 1022, 428, 69, 3, 6705, 3 }, - { 1165, 428, 69, 3, 6705, 3 }, - { 1308, 428, 69, 3, 6705, 3 }, - { 1451, 428, 69, 3, 6705, 3 }, - { 118, 428, 69, 3, 6705, 3 }, - { 311, 428, 69, 3, 6705, 3 }, - { 179, 439, 124, 0, 4801, 3 }, - { 366, 439, 169, 0, 4801, 3 }, - { 509, 439, 229, 0, 4801, 3 }, - { 652, 439, 91, 0, 4801, 3 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}, + { 1842, 564, 290, 134, 1457, 100 }, + { 2054, 564, 290, 134, 1457, 100 }, + { 2258, 564, 290, 134, 1457, 100 }, + { 62, 564, 290, 134, 1457, 100 }, + { 350, 564, 290, 134, 1457, 100 }, + { 629, 564, 290, 134, 1457, 100 }, + { 848, 564, 290, 134, 1457, 100 }, + { 1064, 564, 290, 134, 1457, 100 }, + { 1280, 564, 290, 134, 1457, 100 }, + { 1492, 564, 290, 134, 1457, 100 }, + { 1704, 564, 290, 134, 1457, 100 }, + { 1916, 564, 290, 134, 1457, 100 }, + { 2128, 564, 290, 134, 1457, 100 }, + { 137, 564, 290, 134, 1457, 100 }, + { 426, 564, 290, 134, 1457, 100 }, + { 705, 564, 290, 134, 1457, 100 }, + { 924, 564, 290, 134, 1457, 100 }, + { 1140, 564, 290, 134, 1457, 100 }, + { 1356, 564, 290, 134, 1457, 100 }, + { 1568, 564, 290, 134, 1457, 100 }, + { 1780, 564, 290, 134, 1457, 100 }, + { 1992, 564, 290, 134, 1457, 100 }, + { 2196, 564, 290, 134, 1457, 100 }, + { 205, 564, 290, 134, 1457, 100 }, + { 486, 564, 290, 134, 1457, 100 }, + { 277, 581, 290, 134, 8544, 38 }, + { 980, 780, 8, 181, 1, 121 }, + { 1196, 780, 8, 181, 1, 121 }, + { 1412, 780, 8, 181, 1, 121 }, + { 1624, 780, 8, 181, 1, 121 }, + { 1836, 780, 8, 181, 1, 121 }, + { 2048, 780, 8, 181, 1, 121 }, + { 2252, 780, 8, 181, 1, 121 }, + { 56, 780, 8, 181, 1, 121 }, + { 344, 780, 8, 181, 1, 121 }, + { 622, 780, 8, 181, 1, 121 }, + { 840, 780, 8, 181, 1, 121 }, + { 1056, 780, 8, 181, 1, 121 }, + { 1272, 780, 8, 181, 1, 121 }, + { 1484, 780, 8, 181, 1, 121 }, + { 1696, 780, 8, 181, 1, 121 }, + { 1908, 780, 8, 181, 1, 121 }, + { 2120, 780, 8, 181, 1, 121 }, + { 129, 780, 8, 181, 1, 121 }, + { 418, 780, 8, 181, 1, 121 }, + { 697, 780, 8, 181, 1, 121 }, + { 916, 780, 8, 181, 1, 121 }, + { 1132, 780, 8, 181, 1, 121 }, + { 1348, 780, 8, 181, 1, 121 }, + { 1560, 780, 8, 181, 1, 121 }, + { 1772, 780, 8, 181, 1, 121 }, + { 1984, 780, 8, 181, 1, 121 }, + { 2188, 780, 8, 181, 1, 121 }, + { 197, 780, 8, 181, 1, 121 }, + { 478, 780, 8, 181, 1, 121 }, + { 269, 826, 8, 181, 384, 130 }, + { 546, 688, 8, 181, 944, 105 }, + { 763, 734, 8, 181, 6864, 43 }, + { 767, 598, 545, 151, 625, 139 }, + { 983, 598, 180, 151, 625, 139 }, + { 1199, 598, 180, 151, 625, 139 }, + { 1415, 598, 180, 151, 625, 139 }, + { 1627, 598, 180, 151, 625, 139 }, + { 1839, 598, 180, 151, 625, 139 }, + { 2051, 598, 180, 151, 625, 139 }, + { 2255, 598, 180, 151, 625, 139 }, + { 59, 598, 180, 151, 625, 139 }, + { 347, 598, 180, 151, 625, 139 }, + { 625, 598, 180, 151, 625, 139 }, + { 844, 598, 180, 151, 625, 139 }, + { 1060, 598, 180, 151, 625, 139 }, + { 1276, 598, 180, 151, 625, 139 }, + { 1488, 598, 180, 151, 625, 139 }, + { 1700, 598, 180, 151, 625, 139 }, + { 1912, 598, 180, 151, 625, 139 }, + { 2124, 598, 180, 151, 625, 139 }, + { 133, 598, 180, 151, 625, 139 }, + { 422, 598, 180, 151, 625, 139 }, + { 701, 598, 180, 151, 625, 139 }, + { 920, 598, 180, 151, 625, 139 }, + { 1136, 598, 180, 151, 625, 139 }, + { 1352, 598, 180, 151, 625, 139 }, + { 1564, 598, 180, 151, 625, 139 }, + { 1776, 598, 180, 151, 625, 139 }, + { 1988, 598, 180, 151, 625, 139 }, + { 2192, 598, 180, 151, 625, 139 }, + { 201, 598, 180, 151, 625, 139 }, + { 482, 598, 180, 151, 625, 139 }, + { 273, 628, 180, 151, 1152, 114 }, + { 550, 658, 180, 151, 8096, 52 }, }; // FPR8 Register Class... static const MCPhysReg FPR8[] = { AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4, AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9, AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14, AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19, AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24, AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29, AArch64_B30, AArch64_B31, }; - // FPR8 Bit set. static const uint8_t FPR8Bits[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; - // FPR16 Register Class... static const MCPhysReg FPR16[] = { AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4, AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9, AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14, AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19, AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24, AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29, AArch64_H30, AArch64_H31, }; - // FPR16 Bit set. static const uint8_t FPR16Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + // PPR Register Class... + static const MCPhysReg PPR[] = { + AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, AArch64_P8, AArch64_P9, AArch64_P10, AArch64_P11, AArch64_P12, AArch64_P13, AArch64_P14, AArch64_P15, + }; + // PPR Bit set. + static const uint8_t PPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, + }; + // PPR_3b Register Class... + static const MCPhysReg PPR_3b[] = { + AArch64_P0, AArch64_P1, AArch64_P2, AArch64_P3, AArch64_P4, AArch64_P5, AArch64_P6, AArch64_P7, + }; + // PPR_3b Bit set. + static const uint8_t PPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, }; - // GPR32all Register Class... static const MCPhysReg GPR32all[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, AArch64_WSP, }; - // GPR32all Bit set. static const uint8_t GPR32allBits[] = { - 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; - // FPR32 Register Class... static const MCPhysReg FPR32[] = { AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4, AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9, AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14, AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19, AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24, AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29, AArch64_S30, AArch64_S31, }; - // FPR32 Bit set. static const uint8_t FPR32Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; - // GPR32 Register Class... static const MCPhysReg GPR32[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WZR, }; - // GPR32 Bit set. static const uint8_t GPR32Bits[] = { - 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; - // GPR32sp Register Class... static const MCPhysReg GPR32sp[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, AArch64_WSP, }; - // GPR32sp Bit set. static const uint8_t GPR32spBits[] = { - 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; - // GPR32common Register Class... static const MCPhysReg GPR32common[] = { AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4, AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9, AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14, AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19, AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24, AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29, AArch64_W30, }; - // GPR32common Bit set. static const uint8_t GPR32commonBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, }; - // CCR Register Class... static const MCPhysReg CCR[] = { AArch64_NZCV, }; - // CCR Bit set. static const uint8_t CCRBits[] = { - 0x08, + 0x10, }; - // GPR32sponly Register Class... static const MCPhysReg GPR32sponly[] = { AArch64_WSP, }; - // GPR32sponly Bit set. static const uint8_t GPR32sponlyBits[] = { - 0x20, + 0x40, + }; + // WSeqPairsClass Register Class... + static const MCPhysReg WSeqPairsClass[] = { + AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_W30_WZR, AArch64_WZR_W0, + }; + // WSeqPairsClass Bit set. + static const uint8_t WSeqPairsClassBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // WSeqPairsClass_with_sube32_in_GPR32common Register Class... + static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = { + AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_W30_WZR, + }; + // WSeqPairsClass_with_sube32_in_GPR32common Bit set. + static const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, + }; + // WSeqPairsClass_with_subo32_in_GPR32common Register Class... + static const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = { + AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, AArch64_WZR_W0, + }; + // WSeqPairsClass_with_subo32_in_GPR32common Bit set. + static const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, + }; + // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class... + static const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = { + AArch64_W0_W1, AArch64_W1_W2, AArch64_W2_W3, AArch64_W3_W4, AArch64_W4_W5, AArch64_W5_W6, AArch64_W6_W7, AArch64_W7_W8, AArch64_W8_W9, AArch64_W9_W10, AArch64_W10_W11, AArch64_W11_W12, AArch64_W12_W13, AArch64_W13_W14, AArch64_W14_W15, AArch64_W15_W16, AArch64_W16_W17, AArch64_W17_W18, AArch64_W18_W19, AArch64_W19_W20, AArch64_W20_W21, AArch64_W21_W22, AArch64_W22_W23, AArch64_W23_W24, AArch64_W24_W25, AArch64_W25_W26, AArch64_W26_W27, AArch64_W27_W28, AArch64_W28_W29, AArch64_W29_W30, + }; + // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set. + static const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f, }; - // GPR64all Register Class... static const MCPhysReg GPR64all[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, AArch64_SP, }; - // GPR64all Bit set. static const uint8_t GPR64allBits[] = { - 0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + 0x2c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; - // FPR64 Register Class... static const MCPhysReg FPR64[] = { AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4, AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9, AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14, AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19, AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24, AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29, AArch64_D30, AArch64_D31, }; - // FPR64 Bit set. static const uint8_t FPR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; - // GPR64 Register Class... static const MCPhysReg GPR64[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_XZR, }; - // GPR64 Bit set. static const uint8_t GPR64Bits[] = { - 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + 0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; - // GPR64sp Register Class... static const MCPhysReg GPR64sp[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, AArch64_SP, }; - // GPR64sp Bit set. static const uint8_t GPR64spBits[] = { - 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; - // GPR64common Register Class... static const MCPhysReg GPR64common[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19, AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24, AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP, AArch64_LR, }; - // GPR64common Bit set. static const uint8_t GPR64commonBits[] = { - 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, + 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x1f, }; - // tcGPR64 Register Class... static const MCPhysReg tcGPR64[] = { AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4, AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9, AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14, AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, }; - // tcGPR64 Bit set. static const uint8_t tcGPR64Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, }; - // GPR64sponly Register Class... static const MCPhysReg GPR64sponly[] = { AArch64_SP, }; - // GPR64sponly Bit set. static const uint8_t GPR64sponlyBits[] = { - 0x10, + 0x20, }; - // DD Register Class... static const MCPhysReg DD[] = { AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4, AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8, AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12, AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16, AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20, AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24, AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28, AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0, }; - // DD Bit set. static const uint8_t DDBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // XSeqPairsClass Register Class... + static const MCPhysReg XSeqPairsClass[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_LR_XZR, AArch64_XZR_X0, + }; + // XSeqPairsClass Bit set. + static const uint8_t XSeqPairsClassBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // XSeqPairsClass_with_sub_32_in_GPR32common Register Class... + static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_LR_XZR, + }; + // XSeqPairsClass_with_sub_32_in_GPR32common Bit set. + static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0xff, 0xff, 0xff, 0x1f, + }; + // XSeqPairsClass_with_subo64_in_GPR64common Register Class... + static const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, AArch64_XZR_X0, + }; + // XSeqPairsClass_with_subo64_in_GPR64common Bit set. + static const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xff, 0xff, 0xff, 0x1f, + }; + // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class... + static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, AArch64_X19_X20, AArch64_X20_X21, AArch64_X21_X22, AArch64_X22_X23, AArch64_X23_X24, AArch64_X24_X25, AArch64_X25_X26, AArch64_X26_X27, AArch64_X27_X28, AArch64_X28_FP, AArch64_FP_LR, + }; + // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set. + static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0xff, 0xff, 0xff, 0x1f, + }; + // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class... + static const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_X18_X19, + }; + // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set. + static const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, + }; + // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class... + static const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, AArch64_XZR_X0, + }; + // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set. + static const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xfe, 0xff, 0x07, + }; + // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class... + static const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = { + AArch64_X0_X1, AArch64_X1_X2, AArch64_X2_X3, AArch64_X3_X4, AArch64_X4_X5, AArch64_X5_X6, AArch64_X6_X7, AArch64_X7_X8, AArch64_X8_X9, AArch64_X9_X10, AArch64_X10_X11, AArch64_X11_X12, AArch64_X12_X13, AArch64_X13_X14, AArch64_X14_X15, AArch64_X15_X16, AArch64_X16_X17, AArch64_X17_X18, + }; + // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set. + static const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x07, }; - // FPR128 Register Class... static const MCPhysReg FPR128[] = { AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19, AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24, AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29, AArch64_Q30, AArch64_Q31, }; - // FPR128 Bit set. static const uint8_t FPR128Bits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, + }; + // ZPR Register Class... + static const MCPhysReg ZPR[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, AArch64_Z16, AArch64_Z17, AArch64_Z18, AArch64_Z19, AArch64_Z20, AArch64_Z21, AArch64_Z22, AArch64_Z23, AArch64_Z24, AArch64_Z25, AArch64_Z26, AArch64_Z27, AArch64_Z28, AArch64_Z29, AArch64_Z30, AArch64_Z31, + }; + // ZPR Bit set. + static const uint8_t ZPRBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; - // FPR128_lo Register Class... static const MCPhysReg FPR128_lo[] = { AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4, AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9, AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14, AArch64_Q15, }; - // FPR128_lo Bit set. static const uint8_t FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, + }; + // ZPR_4b Register Class... + static const MCPhysReg ZPR_4b[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, AArch64_Z8, AArch64_Z9, AArch64_Z10, AArch64_Z11, AArch64_Z12, AArch64_Z13, AArch64_Z14, AArch64_Z15, + }; + // ZPR_4b Bit set. + static const uint8_t ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, + }; + // ZPR_3b Register Class... + static const MCPhysReg ZPR_3b[] = { + AArch64_Z0, AArch64_Z1, AArch64_Z2, AArch64_Z3, AArch64_Z4, AArch64_Z5, AArch64_Z6, AArch64_Z7, + }; + // ZPR_3b Bit set. + static const uint8_t ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, }; - // DDD Register Class... static const MCPhysReg DDD[] = { AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4, AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7, AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10, AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13, AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16, AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19, AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22, AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25, AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28, AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31, AArch64_D30_D31_D0, AArch64_D31_D0_D1, }; - // DDD Bit set. static const uint8_t DDDBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; - // DDDD Register Class... static const MCPhysReg DDDD[] = { AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5, AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8, AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11, AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14, AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17, AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20, AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23, AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26, AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29, AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0, AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2, }; - // DDDD Bit set. static const uint8_t DDDDBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; - // QQ Register Class... static const MCPhysReg QQ[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20, AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24, AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28, AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0, }; - // QQ Bit set. static const uint8_t QQBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // ZPR2 Register Class... + static const MCPhysReg ZPR2[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, AArch64_Z16_Z17, AArch64_Z17_Z18, AArch64_Z18_Z19, AArch64_Z19_Z20, AArch64_Z20_Z21, AArch64_Z21_Z22, AArch64_Z22_Z23, AArch64_Z23_Z24, AArch64_Z24_Z25, AArch64_Z25_Z26, AArch64_Z26_Z27, AArch64_Z27_Z28, AArch64_Z28_Z29, AArch64_Z29_Z30, AArch64_Z30_Z31, AArch64_Z31_Z0, + }; + // ZPR2 Bit set. + static const uint8_t ZPR2Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; - // QQ_with_qsub0_in_FPR128_lo Register Class... static const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16, }; - // QQ_with_qsub0_in_FPR128_lo Bit set. static const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; - // QQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q31_Q0, }; - // QQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, + }; + // ZPR2_with_zsub1_in_ZPR_4b Register Class... + static const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z31_Z0, + }; + // ZPR2_with_zsub1_in_ZPR_4b Bit set. + static const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, + }; + // ZPR2_with_zsub_in_FPR128_lo Register Class... + static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, AArch64_Z15_Z16, + }; + // ZPR2_with_zsub_in_FPR128_lo Bit set. + static const uint8_t ZPR2_with_zsub_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; - // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4, AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8, AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12, AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, }; - // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, + }; + // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class... + static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, AArch64_Z8_Z9, AArch64_Z9_Z10, AArch64_Z10_Z11, AArch64_Z11_Z12, AArch64_Z12_Z13, AArch64_Z13_Z14, AArch64_Z14_Z15, + }; + // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set. + static const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, + }; + // ZPR2_with_zsub0_in_ZPR_3b Register Class... + static const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z7_Z8, + }; + // ZPR2_with_zsub0_in_ZPR_3b Bit set. + static const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // ZPR2_with_zsub1_in_ZPR_3b Register Class... + static const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, AArch64_Z31_Z0, + }; + // ZPR2_with_zsub1_in_ZPR_3b Bit set. + static const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, + }; + // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class... + static const MCPhysReg ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1, AArch64_Z1_Z2, AArch64_Z2_Z3, AArch64_Z3_Z4, AArch64_Z4_Z5, AArch64_Z5_Z6, AArch64_Z6_Z7, + }; + // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set. + static const uint8_t ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, }; - // QQQ Register Class... static const MCPhysReg QQQ[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19, AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22, AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25, AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28, AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, }; - // QQQ Bit set. static const uint8_t QQQBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // ZPR3 Register Class... + static const MCPhysReg ZPR3[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17, AArch64_Z16_Z17_Z18, AArch64_Z17_Z18_Z19, AArch64_Z18_Z19_Z20, AArch64_Z19_Z20_Z21, AArch64_Z20_Z21_Z22, AArch64_Z21_Z22_Z23, AArch64_Z22_Z23_Z24, AArch64_Z23_Z24_Z25, AArch64_Z24_Z25_Z26, AArch64_Z25_Z26_Z27, AArch64_Z26_Z27_Z28, AArch64_Z27_Z28_Z29, AArch64_Z28_Z29_Z30, AArch64_Z29_Z30_Z31, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, + }; + // ZPR3 Bit set. + static const uint8_t ZPR3Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; - // QQQ_with_qsub0_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q15_Q16_Q17, }; - // QQQ_with_qsub0_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; - // QQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, AArch64_Q31_Q0_Q1, }; - // QQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; - // QQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1, }; - // QQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, + }; + // ZPR3_with_zsub1_in_ZPR_4b Register Class... + static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z31_Z0_Z1, + }; + // ZPR3_with_zsub1_in_ZPR_4b Bit set. + static const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, + }; + // ZPR3_with_zsub2_in_ZPR_4b Register Class... + static const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, + }; + // ZPR3_with_zsub2_in_ZPR_4b Bit set. + static const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, + }; + // ZPR3_with_zsub_in_FPR128_lo Register Class... + static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, AArch64_Z15_Z16_Z17, + }; + // ZPR3_with_zsub_in_FPR128_lo Bit set. + static const uint8_t ZPR3_with_zsub_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; - // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16, }; - // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; - // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q31_Q0_Q1, }; - // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, + }; + // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... + static const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z31_Z0_Z1, + }; + // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. + static const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class... + static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, AArch64_Z14_Z15_Z16, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set. + static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; - // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4, AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7, AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10, AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13, AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, }; - // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... + static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, AArch64_Z8_Z9_Z10, AArch64_Z9_Z10_Z11, AArch64_Z10_Z11_Z12, AArch64_Z11_Z12_Z13, AArch64_Z12_Z13_Z14, AArch64_Z13_Z14_Z15, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. + static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, + }; + // ZPR3_with_zsub0_in_ZPR_3b Register Class... + static const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z7_Z8_Z9, + }; + // ZPR3_with_zsub0_in_ZPR_3b Bit set. + static const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // ZPR3_with_zsub1_in_ZPR_3b Register Class... + static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, AArch64_Z31_Z0_Z1, + }; + // ZPR3_with_zsub1_in_ZPR_3b Bit set. + static const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, + }; + // ZPR3_with_zsub2_in_ZPR_3b Register Class... + static const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z30_Z31_Z0, AArch64_Z31_Z0_Z1, + }; + // ZPR3_with_zsub2_in_ZPR_3b Bit set. + static const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, + }; + // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... + static const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z31_Z0_Z1, + }; + // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. + static const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class... + static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, AArch64_Z6_Z7_Z8, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set. + static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... + static const MCPhysReg ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2, AArch64_Z1_Z2_Z3, AArch64_Z2_Z3_Z4, AArch64_Z3_Z4_Z5, AArch64_Z4_Z5_Z6, AArch64_Z5_Z6_Z7, + }; + // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. + static const uint8_t ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, }; - // QQQQ Register Class... static const MCPhysReg QQQQ[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20, AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23, AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26, AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29, AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ Bit set. static const uint8_t QQQQBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, + }; + // ZPR4 Register Class... + static const MCPhysReg ZPR4[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18, AArch64_Z16_Z17_Z18_Z19, AArch64_Z17_Z18_Z19_Z20, AArch64_Z18_Z19_Z20_Z21, AArch64_Z19_Z20_Z21_Z22, AArch64_Z20_Z21_Z22_Z23, AArch64_Z21_Z22_Z23_Z24, AArch64_Z22_Z23_Z24_Z25, AArch64_Z23_Z24_Z25_Z26, AArch64_Z24_Z25_Z26_Z27, AArch64_Z25_Z26_Z27_Z28, AArch64_Z26_Z27_Z28_Z29, AArch64_Z27_Z28_Z29_Z30, AArch64_Z28_Z29_Z30_Z31, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4 Bit set. + static const uint8_t ZPR4Bits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, }; - // QQQQ_with_qsub0_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q15_Q16_Q17_Q18, }; - // QQQQ_with_qsub0_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; - // QQQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, }; - // QQQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, }; - // QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q29_Q30_Q31_Q0, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, + }; + // ZPR4_with_zsub1_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub1_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 0x00, 0x10, + }; + // ZPR4_with_zsub2_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub2_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x18, + }; + // ZPR4_with_zsub3_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub3_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x1c, + }; + // ZPR4_with_zsub_in_FPR128_lo Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, AArch64_Z15_Z16_Z17_Z18, + }; + // ZPR4_with_zsub_in_FPR128_lo Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_loBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f, }; - // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17, }; - // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; - // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, }; - // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, + }; + // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 0x00, 0x10, + }; + // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x18, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, AArch64_Z14_Z15_Z16_Z17, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, }; - // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, }; - // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, }; - // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, AArch64_Q31_Q0_Q1_Q2, }; - // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, + }; + // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, 0x00, 0x10, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, AArch64_Z13_Z14_Z15_Z16, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, }; - // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... static const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5, AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8, AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11, AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14, AArch64_Q12_Q13_Q14_Q15, }; - // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. static const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, AArch64_Z8_Z9_Z10_Z11, AArch64_Z9_Z10_Z11_Z12, AArch64_Z10_Z11_Z12_Z13, AArch64_Z11_Z12_Z13_Z14, AArch64_Z12_Z13_Z14_Z15, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x03, + }; + // ZPR4_with_zsub0_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z7_Z8_Z9_Z10, + }; + // ZPR4_with_zsub0_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f, + }; + // ZPR4_with_zsub1_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub1_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, 0x00, 0x00, 0x10, + }; + // ZPR4_with_zsub2_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub2_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x18, + }; + // ZPR4_with_zsub3_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z29_Z30_Z31_Z0, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub3_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x1c, + }; + // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, 0x00, 0x00, 0x10, + }; + // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z30_Z31_Z0_Z1, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x18, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, AArch64_Z6_Z7_Z8_Z9, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x0f, + }; + // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z31_Z0_Z1_Z2, + }; + // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x10, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, AArch64_Z5_Z6_Z7_Z8, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... + static const MCPhysReg ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = { + AArch64_Z0_Z1_Z2_Z3, AArch64_Z1_Z2_Z3_Z4, AArch64_Z2_Z3_Z4_Z5, AArch64_Z3_Z4_Z5_Z6, AArch64_Z4_Z5_Z6_Z7, + }; + // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. + static const uint8_t ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, + }; + static MCRegisterClass AArch64MCRegisterClasses[] = { { FPR8, FPR8Bits, sizeof(FPR8Bits) }, { FPR16, FPR16Bits, sizeof(FPR16Bits) }, + { PPR, PPRBits, sizeof(PPRBits) }, + { PPR_3b, PPR_3bBits, sizeof(PPR_3bBits) }, { GPR32all, GPR32allBits, sizeof(GPR32allBits) }, { FPR32, FPR32Bits, sizeof(FPR32Bits) }, { GPR32, GPR32Bits, sizeof(GPR32Bits) }, @@ -1489,6 +2510,10 @@ static MCRegisterClass AArch64MCRegisterClasses[] = { { GPR32common, GPR32commonBits, sizeof(GPR32commonBits) }, { CCR, CCRBits, sizeof(CCRBits) }, { GPR32sponly, GPR32sponlyBits, sizeof(GPR32sponlyBits) }, + { WSeqPairsClass, WSeqPairsClassBits, sizeof(WSeqPairsClassBits) }, + { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits) }, + { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits) }, + { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits) }, { GPR64all, GPR64allBits, sizeof(GPR64allBits) }, { FPR64, FPR64Bits, sizeof(FPR64Bits) }, { GPR64, GPR64Bits, sizeof(GPR64Bits) }, @@ -1497,32 +2522,83 @@ static MCRegisterClass AArch64MCRegisterClasses[] = { { tcGPR64, tcGPR64Bits, sizeof(tcGPR64Bits) }, { GPR64sponly, GPR64sponlyBits, sizeof(GPR64sponlyBits) }, { DD, DDBits, sizeof(DDBits) }, + { XSeqPairsClass, XSeqPairsClassBits, sizeof(XSeqPairsClassBits) }, + { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits) }, + { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits) }, + { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits) }, + { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits) }, + { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits) }, + { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits) }, { FPR128, FPR128Bits, sizeof(FPR128Bits) }, + { ZPR, ZPRBits, sizeof(ZPRBits) }, { FPR128_lo, FPR128_loBits, sizeof(FPR128_loBits) }, + { ZPR_4b, ZPR_4bBits, sizeof(ZPR_4bBits) }, + { ZPR_3b, ZPR_3bBits, sizeof(ZPR_3bBits) }, { DDD, DDDBits, sizeof(DDDBits) }, { DDDD, DDDDBits, sizeof(DDDDBits) }, { QQ, QQBits, sizeof(QQBits) }, + { ZPR2, ZPR2Bits, sizeof(ZPR2Bits) }, { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, sizeof(QQ_with_qsub0_in_FPR128_loBits) }, { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, sizeof(QQ_with_qsub1_in_FPR128_loBits) }, + { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits) }, + { ZPR2_with_zsub_in_FPR128_lo, ZPR2_with_zsub_in_FPR128_loBits, sizeof(ZPR2_with_zsub_in_FPR128_loBits) }, { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits) }, + { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits) }, + { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits) }, + { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits) }, + { ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, sizeof(ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits) }, { QQQ, QQQBits, sizeof(QQQBits) }, + { ZPR3, ZPR3Bits, sizeof(ZPR3Bits) }, { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_loBits) }, { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQ_with_qsub1_in_FPR128_loBits) }, { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub2_in_FPR128_loBits) }, + { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits) }, + { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits) }, + { ZPR3_with_zsub_in_FPR128_lo, ZPR3_with_zsub_in_FPR128_loBits, sizeof(ZPR3_with_zsub_in_FPR128_loBits) }, { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits) }, { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits) }, + { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits) }, + { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits) }, { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits) }, + { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits) }, + { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits) }, + { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits) }, + { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits) }, + { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits) }, + { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits) }, + { ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, sizeof(ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits) }, { QQQQ, QQQQBits, sizeof(QQQQBits) }, + { ZPR4, ZPR4Bits, sizeof(ZPR4Bits) }, { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_loBits) }, { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_loBits) }, { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub2_in_FPR128_loBits) }, { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub3_in_FPR128_loBits) }, + { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits) }, + { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits) }, + { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits) }, + { ZPR4_with_zsub_in_FPR128_lo, ZPR4_with_zsub_in_FPR128_loBits, sizeof(ZPR4_with_zsub_in_FPR128_loBits) }, { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits) }, { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits) }, { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) }, + { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits) }, + { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits) }, + { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits) }, { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits) }, { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) }, + { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits) }, + { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits) }, { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits) }, + { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits) }, + { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits) }, + { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits) }, + { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits) }, + { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits) }, + { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits) }, + { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits) }, + { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits) }, + { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits) }, + { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits) }, + { ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, sizeof(ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits) }, }; #endif // GET_REGINFO_MC_DESC diff --git a/arch/AArch64/AArch64GenRegisterName.inc b/arch/AArch64/AArch64GenRegisterName.inc new file mode 100644 index 000000000..56bc35efa --- /dev/null +++ b/arch/AArch64/AArch64GenRegisterName.inc @@ -0,0 +1,686 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/// getRegisterName - This method is automatically generated by tblgen +/// from the register set description. This returns the assembler name +/// for the specified register. +static const char *getRegisterName(unsigned RegNo, unsigned AltIdx) +{ + +#ifndef CAPSTONE_DIET + static const char AsmStrsNoRegAltName[] = { + /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, + /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, + /* 26 */ 'W', '9', '_', 'W', '1', '0', 0, + /* 33 */ 'X', '9', '_', 'X', '1', '0', 0, + /* 40 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0, + /* 53 */ 'b', '1', '0', 0, + /* 57 */ 'd', '1', '0', 0, + /* 61 */ 'h', '1', '0', 0, + /* 65 */ 'p', '1', '0', 0, + /* 69 */ 'q', '1', '0', 0, + /* 73 */ 's', '1', '0', 0, + /* 77 */ 'w', '1', '0', 0, + /* 81 */ 'x', '1', '0', 0, + /* 85 */ 'z', '1', '0', 0, + /* 89 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, + /* 105 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, + /* 121 */ 'W', '1', '9', '_', 'W', '2', '0', 0, + /* 129 */ 'X', '1', '9', '_', 'X', '2', '0', 0, + /* 137 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0, + /* 153 */ 'b', '2', '0', 0, + /* 157 */ 'd', '2', '0', 0, + /* 161 */ 'h', '2', '0', 0, + /* 165 */ 'q', '2', '0', 0, + /* 169 */ 's', '2', '0', 0, + /* 173 */ 'w', '2', '0', 0, + /* 177 */ 'x', '2', '0', 0, + /* 181 */ 'z', '2', '0', 0, + /* 185 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, + /* 201 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, + /* 217 */ 'W', '2', '9', '_', 'W', '3', '0', 0, + /* 225 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0, + /* 241 */ 'b', '3', '0', 0, + /* 245 */ 'd', '3', '0', 0, + /* 249 */ 'h', '3', '0', 0, + /* 253 */ 'q', '3', '0', 0, + /* 257 */ 's', '3', '0', 0, + /* 261 */ 'w', '3', '0', 0, + /* 265 */ 'x', '3', '0', 0, + /* 269 */ 'z', '3', '0', 0, + /* 273 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, + /* 288 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, + /* 303 */ 'W', 'Z', 'R', '_', 'W', '0', 0, + /* 310 */ 'X', 'Z', 'R', '_', 'X', '0', 0, + /* 317 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0, + /* 332 */ 'b', '0', 0, + /* 335 */ 'd', '0', 0, + /* 338 */ 'h', '0', 0, + /* 341 */ 'p', '0', 0, + /* 344 */ 'q', '0', 0, + /* 347 */ 's', '0', 0, + /* 350 */ 'w', '0', 0, + /* 353 */ 'x', '0', 0, + /* 356 */ 'z', '0', 0, + /* 359 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, + /* 373 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, + /* 387 */ 'W', '1', '0', '_', 'W', '1', '1', 0, + /* 395 */ 'X', '1', '0', '_', 'X', '1', '1', 0, + /* 403 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0, + /* 417 */ 'b', '1', '1', 0, + /* 421 */ 'd', '1', '1', 0, + /* 425 */ 'h', '1', '1', 0, + /* 429 */ 'p', '1', '1', 0, + /* 433 */ 'q', '1', '1', 0, + /* 437 */ 's', '1', '1', 0, + /* 441 */ 'w', '1', '1', 0, + /* 445 */ 'x', '1', '1', 0, + /* 449 */ 'z', '1', '1', 0, + /* 453 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, + /* 469 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, + /* 485 */ 'W', '2', '0', '_', 'W', '2', '1', 0, + /* 493 */ 'X', '2', '0', '_', 'X', '2', '1', 0, + /* 501 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0, + /* 517 */ 'b', '2', '1', 0, + /* 521 */ 'd', '2', '1', 0, + /* 525 */ 'h', '2', '1', 0, + /* 529 */ 'q', '2', '1', 0, + /* 533 */ 's', '2', '1', 0, + /* 537 */ 'w', '2', '1', 0, + /* 541 */ 'x', '2', '1', 0, + /* 545 */ 'z', '2', '1', 0, + /* 549 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, + /* 565 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, + /* 581 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0, + /* 597 */ 'b', '3', '1', 0, + /* 601 */ 'd', '3', '1', 0, + /* 605 */ 'h', '3', '1', 0, + /* 609 */ 'q', '3', '1', 0, + /* 613 */ 's', '3', '1', 0, + /* 617 */ 'z', '3', '1', 0, + /* 621 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, + /* 635 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, + /* 649 */ 'W', '0', '_', 'W', '1', 0, + /* 655 */ 'X', '0', '_', 'X', '1', 0, + /* 661 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0, + /* 675 */ 'b', '1', 0, + /* 678 */ 'd', '1', 0, + /* 681 */ 'h', '1', 0, + /* 684 */ 'p', '1', 0, + /* 687 */ 'q', '1', 0, + /* 690 */ 's', '1', 0, + /* 693 */ 'w', '1', 0, + /* 696 */ 'x', '1', 0, + /* 699 */ 'z', '1', 0, + /* 702 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, + /* 717 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, + /* 732 */ 'W', '1', '1', '_', 'W', '1', '2', 0, + /* 740 */ 'X', '1', '1', '_', 'X', '1', '2', 0, + /* 748 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0, + /* 763 */ 'b', '1', '2', 0, + /* 767 */ 'd', '1', '2', 0, + /* 771 */ 'h', '1', '2', 0, + /* 775 */ 'p', '1', '2', 0, + /* 779 */ 'q', '1', '2', 0, + /* 783 */ 's', '1', '2', 0, + /* 787 */ 'w', '1', '2', 0, + /* 791 */ 'x', '1', '2', 0, + /* 795 */ 'z', '1', '2', 0, + /* 799 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, + /* 815 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, + /* 831 */ 'W', '2', '1', '_', 'W', '2', '2', 0, + /* 839 */ 'X', '2', '1', '_', 'X', '2', '2', 0, + /* 847 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0, + /* 863 */ 'b', '2', '2', 0, + /* 867 */ 'd', '2', '2', 0, + /* 871 */ 'h', '2', '2', 0, + /* 875 */ 'q', '2', '2', 0, + /* 879 */ 's', '2', '2', 0, + /* 883 */ 'w', '2', '2', 0, + /* 887 */ 'x', '2', '2', 0, + /* 891 */ 'z', '2', '2', 0, + /* 895 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, + /* 908 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, + /* 921 */ 'W', '1', '_', 'W', '2', 0, + /* 927 */ 'X', '1', '_', 'X', '2', 0, + /* 933 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0, + /* 946 */ 'b', '2', 0, + /* 949 */ 'd', '2', 0, + /* 952 */ 'h', '2', 0, + /* 955 */ 'p', '2', 0, + /* 958 */ 'q', '2', 0, + /* 961 */ 's', '2', 0, + /* 964 */ 'w', '2', 0, + /* 967 */ 'x', '2', 0, + /* 970 */ 'z', '2', 0, + /* 973 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, + /* 989 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, + /* 1005 */ 'W', '1', '2', '_', 'W', '1', '3', 0, + /* 1013 */ 'X', '1', '2', '_', 'X', '1', '3', 0, + /* 1021 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0, + /* 1037 */ 'b', '1', '3', 0, + /* 1041 */ 'd', '1', '3', 0, + /* 1045 */ 'h', '1', '3', 0, + /* 1049 */ 'p', '1', '3', 0, + /* 1053 */ 'q', '1', '3', 0, + /* 1057 */ 's', '1', '3', 0, + /* 1061 */ 'w', '1', '3', 0, + /* 1065 */ 'x', '1', '3', 0, + /* 1069 */ 'z', '1', '3', 0, + /* 1073 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, + /* 1089 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, + /* 1105 */ 'W', '2', '2', '_', 'W', '2', '3', 0, + /* 1113 */ 'X', '2', '2', '_', 'X', '2', '3', 0, + /* 1121 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0, + /* 1137 */ 'b', '2', '3', 0, + /* 1141 */ 'd', '2', '3', 0, + /* 1145 */ 'h', '2', '3', 0, + /* 1149 */ 'q', '2', '3', 0, + /* 1153 */ 's', '2', '3', 0, + /* 1157 */ 'w', '2', '3', 0, + /* 1161 */ 'x', '2', '3', 0, + /* 1165 */ 'z', '2', '3', 0, + /* 1169 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, + /* 1181 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, + /* 1193 */ 'W', '2', '_', 'W', '3', 0, + /* 1199 */ 'X', '2', '_', 'X', '3', 0, + /* 1205 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0, + /* 1217 */ 'b', '3', 0, + /* 1220 */ 'd', '3', 0, + /* 1223 */ 'h', '3', 0, + /* 1226 */ 'p', '3', 0, + /* 1229 */ 'q', '3', 0, + /* 1232 */ 's', '3', 0, + /* 1235 */ 'w', '3', 0, + /* 1238 */ 'x', '3', 0, + /* 1241 */ 'z', '3', 0, + /* 1244 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, + /* 1260 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, + /* 1276 */ 'W', '1', '3', '_', 'W', '1', '4', 0, + /* 1284 */ 'X', '1', '3', '_', 'X', '1', '4', 0, + /* 1292 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0, + /* 1308 */ 'b', '1', '4', 0, + /* 1312 */ 'd', '1', '4', 0, + /* 1316 */ 'h', '1', '4', 0, + /* 1320 */ 'p', '1', '4', 0, + /* 1324 */ 'q', '1', '4', 0, + /* 1328 */ 's', '1', '4', 0, + /* 1332 */ 'w', '1', '4', 0, + /* 1336 */ 'x', '1', '4', 0, + /* 1340 */ 'z', '1', '4', 0, + /* 1344 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, + /* 1360 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, + /* 1376 */ 'W', '2', '3', '_', 'W', '2', '4', 0, + /* 1384 */ 'X', '2', '3', '_', 'X', '2', '4', 0, + /* 1392 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0, + /* 1408 */ 'b', '2', '4', 0, + /* 1412 */ 'd', '2', '4', 0, + /* 1416 */ 'h', '2', '4', 0, + /* 1420 */ 'q', '2', '4', 0, + /* 1424 */ 's', '2', '4', 0, + /* 1428 */ 'w', '2', '4', 0, + /* 1432 */ 'x', '2', '4', 0, + /* 1436 */ 'z', '2', '4', 0, + /* 1440 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, + /* 1452 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, + /* 1464 */ 'W', '3', '_', 'W', '4', 0, + /* 1470 */ 'X', '3', '_', 'X', '4', 0, + /* 1476 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0, + /* 1488 */ 'b', '4', 0, + /* 1491 */ 'd', '4', 0, + /* 1494 */ 'h', '4', 0, + /* 1497 */ 'p', '4', 0, + /* 1500 */ 'q', '4', 0, + /* 1503 */ 's', '4', 0, + /* 1506 */ 'w', '4', 0, + /* 1509 */ 'x', '4', 0, + /* 1512 */ 'z', '4', 0, + /* 1515 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, + /* 1531 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, + /* 1547 */ 'W', '1', '4', '_', 'W', '1', '5', 0, + /* 1555 */ 'X', '1', '4', '_', 'X', '1', '5', 0, + /* 1563 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0, + /* 1579 */ 'b', '1', '5', 0, + /* 1583 */ 'd', '1', '5', 0, + /* 1587 */ 'h', '1', '5', 0, + /* 1591 */ 'p', '1', '5', 0, + /* 1595 */ 'q', '1', '5', 0, + /* 1599 */ 's', '1', '5', 0, + /* 1603 */ 'w', '1', '5', 0, + /* 1607 */ 'x', '1', '5', 0, + /* 1611 */ 'z', '1', '5', 0, + /* 1615 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, + /* 1631 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, + /* 1647 */ 'W', '2', '4', '_', 'W', '2', '5', 0, + /* 1655 */ 'X', '2', '4', '_', 'X', '2', '5', 0, + /* 1663 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0, + /* 1679 */ 'b', '2', '5', 0, + /* 1683 */ 'd', '2', '5', 0, + /* 1687 */ 'h', '2', '5', 0, + /* 1691 */ 'q', '2', '5', 0, + /* 1695 */ 's', '2', '5', 0, + /* 1699 */ 'w', '2', '5', 0, + /* 1703 */ 'x', '2', '5', 0, + /* 1707 */ 'z', '2', '5', 0, + /* 1711 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, + /* 1723 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, + /* 1735 */ 'W', '4', '_', 'W', '5', 0, + /* 1741 */ 'X', '4', '_', 'X', '5', 0, + /* 1747 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0, + /* 1759 */ 'b', '5', 0, + /* 1762 */ 'd', '5', 0, + /* 1765 */ 'h', '5', 0, + /* 1768 */ 'p', '5', 0, + /* 1771 */ 'q', '5', 0, + /* 1774 */ 's', '5', 0, + /* 1777 */ 'w', '5', 0, + /* 1780 */ 'x', '5', 0, + /* 1783 */ 'z', '5', 0, + /* 1786 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, + /* 1802 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, + /* 1818 */ 'W', '1', '5', '_', 'W', '1', '6', 0, + /* 1826 */ 'X', '1', '5', '_', 'X', '1', '6', 0, + /* 1834 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0, + /* 1850 */ 'b', '1', '6', 0, + /* 1854 */ 'd', '1', '6', 0, + /* 1858 */ 'h', '1', '6', 0, + /* 1862 */ 'q', '1', '6', 0, + /* 1866 */ 's', '1', '6', 0, + /* 1870 */ 'w', '1', '6', 0, + /* 1874 */ 'x', '1', '6', 0, + /* 1878 */ 'z', '1', '6', 0, + /* 1882 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, + /* 1898 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, + /* 1914 */ 'W', '2', '5', '_', 'W', '2', '6', 0, + /* 1922 */ 'X', '2', '5', '_', 'X', '2', '6', 0, + /* 1930 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0, + /* 1946 */ 'b', '2', '6', 0, + /* 1950 */ 'd', '2', '6', 0, + /* 1954 */ 'h', '2', '6', 0, + /* 1958 */ 'q', '2', '6', 0, + /* 1962 */ 's', '2', '6', 0, + /* 1966 */ 'w', '2', '6', 0, + /* 1970 */ 'x', '2', '6', 0, + /* 1974 */ 'z', '2', '6', 0, + /* 1978 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, + /* 1990 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, + /* 2002 */ 'W', '5', '_', 'W', '6', 0, + /* 2008 */ 'X', '5', '_', 'X', '6', 0, + /* 2014 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0, + /* 2026 */ 'b', '6', 0, + /* 2029 */ 'd', '6', 0, + /* 2032 */ 'h', '6', 0, + /* 2035 */ 'p', '6', 0, + /* 2038 */ 'q', '6', 0, + /* 2041 */ 's', '6', 0, + /* 2044 */ 'w', '6', 0, + /* 2047 */ 'x', '6', 0, + /* 2050 */ 'z', '6', 0, + /* 2053 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, + /* 2069 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, + /* 2085 */ 'W', '1', '6', '_', 'W', '1', '7', 0, + /* 2093 */ 'X', '1', '6', '_', 'X', '1', '7', 0, + /* 2101 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0, + /* 2117 */ 'b', '1', '7', 0, + /* 2121 */ 'd', '1', '7', 0, + /* 2125 */ 'h', '1', '7', 0, + /* 2129 */ 'q', '1', '7', 0, + /* 2133 */ 's', '1', '7', 0, + /* 2137 */ 'w', '1', '7', 0, + /* 2141 */ 'x', '1', '7', 0, + /* 2145 */ 'z', '1', '7', 0, + /* 2149 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, + /* 2165 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, + /* 2181 */ 'W', '2', '6', '_', 'W', '2', '7', 0, + /* 2189 */ 'X', '2', '6', '_', 'X', '2', '7', 0, + /* 2197 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0, + /* 2213 */ 'b', '2', '7', 0, + /* 2217 */ 'd', '2', '7', 0, + /* 2221 */ 'h', '2', '7', 0, + /* 2225 */ 'q', '2', '7', 0, + /* 2229 */ 's', '2', '7', 0, + /* 2233 */ 'w', '2', '7', 0, + /* 2237 */ 'x', '2', '7', 0, + /* 2241 */ 'z', '2', '7', 0, + /* 2245 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, + /* 2257 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, + /* 2269 */ 'W', '6', '_', 'W', '7', 0, + /* 2275 */ 'X', '6', '_', 'X', '7', 0, + /* 2281 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0, + /* 2293 */ 'b', '7', 0, + /* 2296 */ 'd', '7', 0, + /* 2299 */ 'h', '7', 0, + /* 2302 */ 'p', '7', 0, + /* 2305 */ 'q', '7', 0, + /* 2308 */ 's', '7', 0, + /* 2311 */ 'w', '7', 0, + /* 2314 */ 'x', '7', 0, + /* 2317 */ 'z', '7', 0, + /* 2320 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, + /* 2336 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, + /* 2352 */ 'W', '1', '7', '_', 'W', '1', '8', 0, + /* 2360 */ 'X', '1', '7', '_', 'X', '1', '8', 0, + /* 2368 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0, + /* 2384 */ 'b', '1', '8', 0, + /* 2388 */ 'd', '1', '8', 0, + /* 2392 */ 'h', '1', '8', 0, + /* 2396 */ 'q', '1', '8', 0, + /* 2400 */ 's', '1', '8', 0, + /* 2404 */ 'w', '1', '8', 0, + /* 2408 */ 'x', '1', '8', 0, + /* 2412 */ 'z', '1', '8', 0, + /* 2416 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, + /* 2432 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, + /* 2448 */ 'W', '2', '7', '_', 'W', '2', '8', 0, + /* 2456 */ 'X', '2', '7', '_', 'X', '2', '8', 0, + /* 2464 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0, + /* 2480 */ 'b', '2', '8', 0, + /* 2484 */ 'd', '2', '8', 0, + /* 2488 */ 'h', '2', '8', 0, + /* 2492 */ 'q', '2', '8', 0, + /* 2496 */ 's', '2', '8', 0, + /* 2500 */ 'w', '2', '8', 0, + /* 2504 */ 'x', '2', '8', 0, + /* 2508 */ 'z', '2', '8', 0, + /* 2512 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, + /* 2524 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, + /* 2536 */ 'W', '7', '_', 'W', '8', 0, + /* 2542 */ 'X', '7', '_', 'X', '8', 0, + /* 2548 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0, + /* 2560 */ 'b', '8', 0, + /* 2563 */ 'd', '8', 0, + /* 2566 */ 'h', '8', 0, + /* 2569 */ 'p', '8', 0, + /* 2572 */ 'q', '8', 0, + /* 2575 */ 's', '8', 0, + /* 2578 */ 'w', '8', 0, + /* 2581 */ 'x', '8', 0, + /* 2584 */ 'z', '8', 0, + /* 2587 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, + /* 2603 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, + /* 2619 */ 'W', '1', '8', '_', 'W', '1', '9', 0, + /* 2627 */ 'X', '1', '8', '_', 'X', '1', '9', 0, + /* 2635 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0, + /* 2651 */ 'b', '1', '9', 0, + /* 2655 */ 'd', '1', '9', 0, + /* 2659 */ 'h', '1', '9', 0, + /* 2663 */ 'q', '1', '9', 0, + /* 2667 */ 's', '1', '9', 0, + /* 2671 */ 'w', '1', '9', 0, + /* 2675 */ 'x', '1', '9', 0, + /* 2679 */ 'z', '1', '9', 0, + /* 2683 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, + /* 2699 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, + /* 2715 */ 'W', '2', '8', '_', 'W', '2', '9', 0, + /* 2723 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0, + /* 2739 */ 'b', '2', '9', 0, + /* 2743 */ 'd', '2', '9', 0, + /* 2747 */ 'h', '2', '9', 0, + /* 2751 */ 'q', '2', '9', 0, + /* 2755 */ 's', '2', '9', 0, + /* 2759 */ 'w', '2', '9', 0, + /* 2763 */ 'x', '2', '9', 0, + /* 2767 */ 'z', '2', '9', 0, + /* 2771 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, + /* 2783 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, + /* 2795 */ 'W', '8', '_', 'W', '9', 0, + /* 2801 */ 'X', '8', '_', 'X', '9', 0, + /* 2807 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0, + /* 2819 */ 'b', '9', 0, + /* 2822 */ 'd', '9', 0, + /* 2825 */ 'h', '9', 0, + /* 2828 */ 'p', '9', 0, + /* 2831 */ 'q', '9', 0, + /* 2834 */ 's', '9', 0, + /* 2837 */ 'w', '9', 0, + /* 2840 */ 'x', '9', 0, + /* 2843 */ 'z', '9', 0, + /* 2846 */ 'X', '2', '8', '_', 'F', 'P', 0, + /* 2853 */ 'F', 'P', '_', 'L', 'R', 0, + /* 2859 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0, + /* 2867 */ 'L', 'R', '_', 'X', 'Z', 'R', 0, + /* 2874 */ 'z', '1', '0', '_', 'h', 'i', 0, + /* 2881 */ 'z', '2', '0', '_', 'h', 'i', 0, + /* 2888 */ 'z', '3', '0', '_', 'h', 'i', 0, + /* 2895 */ 'z', '0', '_', 'h', 'i', 0, + /* 2901 */ 'z', '1', '1', '_', 'h', 'i', 0, + /* 2908 */ 'z', '2', '1', '_', 'h', 'i', 0, + /* 2915 */ 'z', '3', '1', '_', 'h', 'i', 0, + /* 2922 */ 'z', '1', '_', 'h', 'i', 0, + /* 2928 */ 'z', '1', '2', '_', 'h', 'i', 0, + /* 2935 */ 'z', '2', '2', '_', 'h', 'i', 0, + /* 2942 */ 'z', '2', '_', 'h', 'i', 0, + /* 2948 */ 'z', '1', '3', '_', 'h', 'i', 0, + /* 2955 */ 'z', '2', '3', '_', 'h', 'i', 0, + /* 2962 */ 'z', '3', '_', 'h', 'i', 0, + /* 2968 */ 'z', '1', '4', '_', 'h', 'i', 0, + /* 2975 */ 'z', '2', '4', '_', 'h', 'i', 0, + /* 2982 */ 'z', '4', '_', 'h', 'i', 0, + /* 2988 */ 'z', '1', '5', '_', 'h', 'i', 0, + /* 2995 */ 'z', '2', '5', '_', 'h', 'i', 0, + /* 3002 */ 'z', '5', '_', 'h', 'i', 0, + /* 3008 */ 'z', '1', '6', '_', 'h', 'i', 0, + /* 3015 */ 'z', '2', '6', '_', 'h', 'i', 0, + /* 3022 */ 'z', '6', '_', 'h', 'i', 0, + /* 3028 */ 'z', '1', '7', '_', 'h', 'i', 0, + /* 3035 */ 'z', '2', '7', '_', 'h', 'i', 0, + /* 3042 */ 'z', '7', '_', 'h', 'i', 0, + /* 3048 */ 'z', '1', '8', '_', 'h', 'i', 0, + /* 3055 */ 'z', '2', '8', '_', 'h', 'i', 0, + /* 3062 */ 'z', '8', '_', 'h', 'i', 0, + /* 3068 */ 'z', '1', '9', '_', 'h', 'i', 0, + /* 3075 */ 'z', '2', '9', '_', 'h', 'i', 0, + /* 3082 */ 'z', '9', '_', 'h', 'i', 0, + /* 3088 */ 'w', 's', 'p', 0, + /* 3092 */ 'f', 'f', 'r', 0, + /* 3096 */ 'w', 'z', 'r', 0, + /* 3100 */ 'x', 'z', 'r', 0, + /* 3104 */ 'n', 'z', 'c', 'v', 0, + }; + + static const uint16_t RegAsmOffsetNoRegAltName[] = { + 3092, 2763, 265, 3104, 3089, 3088, 3096, 3100, 332, 675, 946, 1217, 1488, 1759, + 2026, 2293, 2560, 2819, 53, 417, 763, 1037, 1308, 1579, 1850, 2117, 2384, 2651, + 153, 517, 863, 1137, 1408, 1679, 1946, 2213, 2480, 2739, 241, 597, 335, 678, + 949, 1220, 1491, 1762, 2029, 2296, 2563, 2822, 57, 421, 767, 1041, 1312, 1583, + 1854, 2121, 2388, 2655, 157, 521, 867, 1141, 1412, 1683, 1950, 2217, 2484, 2743, + 245, 601, 338, 681, 952, 1223, 1494, 1765, 2032, 2299, 2566, 2825, 61, 425, + 771, 1045, 1316, 1587, 1858, 2125, 2392, 2659, 161, 525, 871, 1145, 1416, 1687, + 1954, 2221, 2488, 2747, 249, 605, 341, 684, 955, 1226, 1497, 1768, 2035, 2302, + 2569, 2828, 65, 429, 775, 1049, 1320, 1591, 344, 687, 958, 1229, 1500, 1771, + 2038, 2305, 2572, 2831, 69, 433, 779, 1053, 1324, 1595, 1862, 2129, 2396, 2663, + 165, 529, 875, 1149, 1420, 1691, 1958, 2225, 2492, 2751, 253, 609, 347, 690, + 961, 1232, 1503, 1774, 2041, 2308, 2575, 2834, 73, 437, 783, 1057, 1328, 1599, + 1866, 2133, 2400, 2667, 169, 533, 879, 1153, 1424, 1695, 1962, 2229, 2496, 2755, + 257, 613, 350, 693, 964, 1235, 1506, 1777, 2044, 2311, 2578, 2837, 77, 441, + 787, 1061, 1332, 1603, 1870, 2137, 2404, 2671, 173, 537, 883, 1157, 1428, 1699, + 1966, 2233, 2500, 2759, 261, 353, 696, 967, 1238, 1509, 1780, 2047, 2314, 2581, + 2840, 81, 445, 791, 1065, 1336, 1607, 1874, 2141, 2408, 2675, 177, 541, 887, + 1161, 1432, 1703, 1970, 2237, 2504, 356, 699, 970, 1241, 1512, 1783, 2050, 2317, + 2584, 2843, 85, 449, 795, 1069, 1340, 1611, 1878, 2145, 2412, 2679, 181, 545, + 891, 1165, 1436, 1707, 1974, 2241, 2508, 2767, 269, 617, 2895, 2922, 2942, 2962, + 2982, 3002, 3022, 3042, 3062, 3082, 2874, 2901, 2928, 2948, 2968, 2988, 3008, 3028, + 3048, 3068, 2881, 2908, 2935, 2955, 2975, 2995, 3015, 3035, 3055, 3075, 2888, 2915, + 629, 902, 1175, 1446, 1717, 1984, 2251, 2518, 2777, 6, 365, 709, 981, 1252, + 1523, 1794, 2061, 2328, 2595, 97, 461, 807, 1081, 1352, 1623, 1890, 2157, 2424, + 2691, 193, 557, 281, 1169, 1440, 1711, 1978, 2245, 2512, 2771, 0, 359, 702, + 973, 1244, 1515, 1786, 2053, 2320, 2587, 89, 453, 799, 1073, 1344, 1615, 1882, + 2149, 2416, 2683, 185, 549, 273, 621, 895, 899, 1172, 1443, 1714, 1981, 2248, + 2515, 2774, 3, 362, 705, 977, 1248, 1519, 1790, 2057, 2324, 2591, 93, 457, + 803, 1077, 1348, 1619, 1886, 2153, 2420, 2687, 189, 553, 277, 625, 643, 915, + 1187, 1458, 1729, 1996, 2263, 2530, 2789, 19, 379, 724, 997, 1268, 1539, 1810, + 2077, 2344, 2611, 113, 477, 823, 1097, 1368, 1639, 1906, 2173, 2440, 2707, 209, + 573, 296, 1181, 1452, 1723, 1990, 2257, 2524, 2783, 13, 373, 717, 989, 1260, + 1531, 1802, 2069, 2336, 2603, 105, 469, 815, 1089, 1360, 1631, 1898, 2165, 2432, + 2699, 201, 565, 288, 635, 908, 912, 1184, 1455, 1726, 1993, 2260, 2527, 2786, + 16, 376, 720, 993, 1264, 1535, 1806, 2073, 2340, 2607, 109, 473, 819, 1093, + 1364, 1635, 1902, 2169, 2436, 2703, 205, 569, 292, 639, 303, 2859, 649, 921, + 1193, 1464, 1735, 2002, 2269, 2536, 2795, 26, 387, 732, 1005, 1276, 1547, 1818, + 2085, 2352, 2619, 121, 485, 831, 1105, 1376, 1647, 1914, 2181, 2448, 2715, 217, + 2853, 2867, 310, 2846, 655, 927, 1199, 1470, 1741, 2008, 2275, 2542, 2801, 33, + 395, 740, 1013, 1284, 1555, 1826, 2093, 2360, 2627, 129, 493, 839, 1113, 1384, + 1655, 1922, 2189, 2456, 669, 940, 1211, 1482, 1753, 2020, 2287, 2554, 2813, 46, + 409, 755, 1029, 1300, 1571, 1842, 2109, 2376, 2643, 145, 509, 855, 1129, 1400, + 1671, 1938, 2205, 2472, 2731, 233, 589, 325, 1205, 1476, 1747, 2014, 2281, 2548, + 2807, 40, 403, 748, 1021, 1292, 1563, 1834, 2101, 2368, 2635, 137, 501, 847, + 1121, 1392, 1663, 1930, 2197, 2464, 2723, 225, 581, 317, 661, 933, 937, 1208, + 1479, 1750, 2017, 2284, 2551, 2810, 43, 406, 751, 1025, 1296, 1567, 1838, 2105, + 2372, 2639, 141, 505, 851, 1125, 1396, 1667, 1934, 2201, 2468, 2727, 229, 585, + 321, 665, + }; + + static const char AsmStrsvlist1[] = { + /* 0 */ 0, + }; + + static const uint8_t RegAsmOffsetvlist1[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, + }; + + static const char AsmStrsvreg[] = { + /* 0 */ 'v', '1', '0', 0, + /* 4 */ 'v', '2', '0', 0, + /* 8 */ 'v', '3', '0', 0, + /* 12 */ 'v', '0', 0, + /* 15 */ 'v', '1', '1', 0, + /* 19 */ 'v', '2', '1', 0, + /* 23 */ 'v', '3', '1', 0, + /* 27 */ 'v', '1', 0, + /* 30 */ 'v', '1', '2', 0, + /* 34 */ 'v', '2', '2', 0, + /* 38 */ 'v', '2', 0, + /* 41 */ 'v', '1', '3', 0, + /* 45 */ 'v', '2', '3', 0, + /* 49 */ 'v', '3', 0, + /* 52 */ 'v', '1', '4', 0, + /* 56 */ 'v', '2', '4', 0, + /* 60 */ 'v', '4', 0, + /* 63 */ 'v', '1', '5', 0, + /* 67 */ 'v', '2', '5', 0, + /* 71 */ 'v', '5', 0, + /* 74 */ 'v', '1', '6', 0, + /* 78 */ 'v', '2', '6', 0, + /* 82 */ 'v', '6', 0, + /* 85 */ 'v', '1', '7', 0, + /* 89 */ 'v', '2', '7', 0, + /* 93 */ 'v', '7', 0, + /* 96 */ 'v', '1', '8', 0, + /* 100 */ 'v', '2', '8', 0, + /* 104 */ 'v', '8', 0, + /* 107 */ 'v', '1', '9', 0, + /* 111 */ 'v', '2', '9', 0, + /* 115 */ 'v', '9', 0, + }; + + static const uint8_t RegAsmOffsetvreg[] = { + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, + 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, + 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, + 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, + 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, + 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, + 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, + 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, + 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, + 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, + 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, + 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, + 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, + 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, + 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, + 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, + 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, + 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, + 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, + }; + + switch(AltIdx) { + default: + return (const char *)(sizeof(RegAsmOffsetvreg)/sizeof(RegAsmOffsetvreg[0])); + case AArch64_NoRegAltName: + return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; + case AArch64_vlist1: + return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; + case AArch64_vreg: + return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; + } +#else + return NULL; +#endif +} diff --git a/arch/AArch64/AArch64GenRegisterV.inc b/arch/AArch64/AArch64GenRegisterV.inc new file mode 100644 index 000000000..628ad5bf9 --- /dev/null +++ b/arch/AArch64/AArch64GenRegisterV.inc @@ -0,0 +1,660 @@ +// size = 660 +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +ARM64_REG_V0, +ARM64_REG_V1, +ARM64_REG_V2, +ARM64_REG_V3, +ARM64_REG_V4, +ARM64_REG_V5, +ARM64_REG_V6, +ARM64_REG_V7, +ARM64_REG_V8, +ARM64_REG_V9, +ARM64_REG_V10, +ARM64_REG_V11, +ARM64_REG_V12, +ARM64_REG_V13, +ARM64_REG_V14, +ARM64_REG_V15, +ARM64_REG_V16, +ARM64_REG_V17, +ARM64_REG_V18, +ARM64_REG_V19, +ARM64_REG_V20, +ARM64_REG_V21, +ARM64_REG_V22, +ARM64_REG_V23, +ARM64_REG_V24, +ARM64_REG_V25, +ARM64_REG_V26, +ARM64_REG_V27, +ARM64_REG_V28, +ARM64_REG_V29, +ARM64_REG_V30, +ARM64_REG_V31, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, +0, diff --git a/arch/AArch64/AArch64GenSubtargetInfo.inc b/arch/AArch64/AArch64GenSubtargetInfo.inc index d4fd4af42..f7e6a7bd1 100644 --- a/arch/AArch64/AArch64GenSubtargetInfo.inc +++ b/arch/AArch64/AArch64GenSubtargetInfo.inc @@ -1,29 +1,82 @@ -/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ -|* *| -|*Subtarget Enumeration Source Fragment *| + +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *| +|* Subtarget Enumeration Source Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ -/* Capstone Disassembly Engine, http://www.capstone-engine.org */ -/* By Nguyen Anh Quynh , 2013-2015 */ - - -#ifdef GET_SUBTARGETINFO_ENUM -#undef GET_SUBTARGETINFO_ENUM enum { - AArch64_FeatureCRC = 1ULL << 0, - AArch64_FeatureCrypto = 1ULL << 1, - AArch64_FeatureFPARMv8 = 1ULL << 2, - AArch64_FeatureNEON = 1ULL << 3, - AArch64_FeatureZCRegMove = 1ULL << 4, - AArch64_FeatureZCZeroing = 1ULL << 5, - AArch64_ProcA53 = 1ULL << 6, - AArch64_ProcA57 = 1ULL << 7, - AArch64_ProcCyclone = 1ULL << 8 + AArch64_FeatureAES = 0, + AArch64_FeatureAggressiveFMA = 1, + AArch64_FeatureAlternateSExtLoadCVTF32Pattern = 2, + AArch64_FeatureArithmeticBccFusion = 3, + AArch64_FeatureArithmeticCbzFusion = 4, + AArch64_FeatureBalanceFPOps = 5, + AArch64_FeatureCRC = 6, + AArch64_FeatureCrypto = 7, + AArch64_FeatureCustomCheapAsMoveHandling = 8, + AArch64_FeatureDisableLatencySchedHeuristic = 9, + AArch64_FeatureDotProd = 10, + AArch64_FeatureExynosCheapAsMoveHandling = 11, + AArch64_FeatureFPARMv8 = 12, + AArch64_FeatureFullFP16 = 13, + AArch64_FeatureFuseAES = 14, + AArch64_FeatureFuseAddress = 15, + AArch64_FeatureFuseCCSelect = 16, + AArch64_FeatureFuseLiterals = 17, + AArch64_FeatureLSE = 18, + AArch64_FeatureLSLFast = 19, + AArch64_FeatureNEON = 20, + AArch64_FeatureNoNegativeImmediates = 21, + AArch64_FeaturePerfMon = 22, + AArch64_FeaturePostRAScheduler = 23, + AArch64_FeaturePredictableSelectIsExpensive = 24, + AArch64_FeatureRAS = 25, + AArch64_FeatureRCPC = 26, + AArch64_FeatureRDM = 27, + AArch64_FeatureReserveX18 = 28, + AArch64_FeatureReserveX20 = 29, + AArch64_FeatureSHA2 = 30, + AArch64_FeatureSHA3 = 31, + AArch64_FeatureSM4 = 32, + AArch64_FeatureSPE = 33, + AArch64_FeatureSVE = 34, + AArch64_FeatureSlowMisaligned128Store = 35, + AArch64_FeatureSlowPaired128 = 36, + AArch64_FeatureSlowSTRQro = 37, + AArch64_FeatureStrictAlign = 38, + AArch64_FeatureUseAA = 39, + AArch64_FeatureUseRSqrt = 40, + AArch64_FeatureZCRegMove = 41, + AArch64_FeatureZCZeroing = 42, + AArch64_FeatureZCZeroingFPWorkaround = 43, + AArch64_HasV8_1aOps = 44, + AArch64_HasV8_2aOps = 45, + AArch64_HasV8_3aOps = 46, + AArch64_HasV8_4aOps = 47, + AArch64_ProcA35 = 48, + AArch64_ProcA53 = 49, + AArch64_ProcA55 = 50, + AArch64_ProcA57 = 51, + AArch64_ProcA72 = 52, + AArch64_ProcA73 = 53, + AArch64_ProcA75 = 54, + AArch64_ProcCyclone = 55, + AArch64_ProcExynosM1 = 56, + AArch64_ProcExynosM2 = 57, + AArch64_ProcExynosM3 = 58, + AArch64_ProcFalkor = 59, + AArch64_ProcKryo = 60, + AArch64_ProcSaphira = 61, + AArch64_ProcThunderX = 62, + AArch64_ProcThunderX2T99 = 63, + AArch64_ProcThunderXT81 = 64, + AArch64_ProcThunderXT83 = 65, + AArch64_ProcThunderXT88 = 66, }; -#endif // GET_SUBTARGETINFO_ENUM - diff --git a/arch/AArch64/AArch64GenSystemOperands.inc b/arch/AArch64/AArch64GenSystemOperands.inc new file mode 100644 index 000000000..d1dc10590 --- /dev/null +++ b/arch/AArch64/AArch64GenSystemOperands.inc @@ -0,0 +1,2049 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +static const AT ATsList[] = { + { "s1e1r", 0x3C0 }, // 0 + { "s1e2r", 0x23C0 }, // 1 + { "s1e3r", 0x33C0 }, // 2 + { "s1e1w", 0x3C1 }, // 3 + { "s1e2w", 0x23C1 }, // 4 + { "s1e3w", 0x33C1 }, // 5 + { "s1e0r", 0x3C2 }, // 6 + { "s1e0w", 0x3C3 }, // 7 + { "s12e1r", 0x23C4 }, // 8 + { "s12e1w", 0x23C5 }, // 9 + { "s12e0r", 0x23C6 }, // 10 + { "s12e0w", 0x23C7 }, // 11 + { "s1e1rp", 0x3C8 }, // 12 + { "s1e1wp", 0x3C9 }, // 13 +}; + +const AT *lookupATByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x3C0, 0 }, + { 0x3C1, 3 }, + { 0x3C2, 6 }, + { 0x3C3, 7 }, + { 0x3C8, 12 }, + { 0x3C9, 13 }, + { 0x23C0, 1 }, + { 0x23C1, 4 }, + { 0x23C4, 8 }, + { 0x23C5, 9 }, + { 0x23C6, 10 }, + { 0x23C7, 11 }, + { 0x33C0, 2 }, + { 0x33C1, 5 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &ATsList[Index[i].index]; +} + +static const DB DBsList[] = { + { "oshld", 0x1 }, // 0 + { "oshst", 0x2 }, // 1 + { "osh", 0x3 }, // 2 + { "nshld", 0x5 }, // 3 + { "nshst", 0x6 }, // 4 + { "nsh", 0x7 }, // 5 + { "ishld", 0x9 }, // 6 + { "ishst", 0xA }, // 7 + { "ish", 0xB }, // 8 + { "ld", 0xD }, // 9 + { "st", 0xE }, // 10 + { "sy", 0xF }, // 11 +}; + +const DB *lookupDBByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x1, 0 }, + { 0x2, 1 }, + { 0x3, 2 }, + { 0x5, 3 }, + { 0x6, 4 }, + { 0x7, 5 }, + { 0x9, 6 }, + { 0xA, 7 }, + { 0xB, 8 }, + { 0xD, 9 }, + { 0xE, 10 }, + { 0xF, 11 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &DBsList[Index[i].index]; +} + +static const DC DCsList[] = { + { "zva", 0x1BA1 }, // 0 + { "ivac", 0x3B1 }, // 1 + { "isw", 0x3B2 }, // 2 + { "cvac", 0x1BD1 }, // 3 + { "csw", 0x3D2 }, // 4 + { "cvau", 0x1BD9 }, // 5 + { "civac", 0x1BF1 }, // 6 + { "cisw", 0x3F2 }, // 7 + { "cvap", 0x1BE1 }, // 8 +}; + +const DC *lookupDCByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x3B1, 1 }, + { 0x3B2, 2 }, + { 0x3D2, 4 }, + { 0x3F2, 7 }, + { 0x1BA1, 0 }, + { 0x1BD1, 3 }, + { 0x1BD9, 5 }, + { 0x1BE1, 8 }, + { 0x1BF1, 6 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &DCsList[Index[i].index]; +} + +static const IC ICsList[] = { + { "ialluis", 0x388, false }, // 0 + { "iallu", 0x3a8, false }, // 1 + { "ivau", 0x1ba9, true }, // 2 +}; + +const IC *lookupICByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x388, 0 }, + { 0x3A8, 1 }, + { 0x1BA9, 2 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &ICsList[Index[i].index]; +} + +static const TLBI TLBIsList[] = { + { "ipas2e1is", 0x2401, true }, // 0 + { "ipas2le1is", 0x2405, true }, // 1 + { "vmalle1is", 0x418, false }, // 2 + { "alle2is", 0x2418, false }, // 3 + { "alle3is", 0x3418, false }, // 4 + { "vae1is", 0x419, true }, // 5 + { "vae2is", 0x2419, true }, // 6 + { "vae3is", 0x3419, true }, // 7 + { "aside1is", 0x41A, true }, // 8 + { "vaae1is", 0x41B, true }, // 9 + { "alle1is", 0x241C, false }, // 10 + { "vale1is", 0x41D, true }, // 11 + { "vale2is", 0x241D, true }, // 12 + { "vale3is", 0x341D, true }, // 13 + { "vmalls12e1is", 0x241E, false }, // 14 + { "vaale1is", 0x41F, true }, // 15 + { "ipas2e1", 0x2421, true }, // 16 + { "ipas2le1", 0x2425, true }, // 17 + { "vmalle1", 0x438, false }, // 18 + { "alle2", 0x2438, false }, // 19 + { "alle3", 0x3438, false }, // 20 + { "vae1", 0x439, true }, // 21 + { "vae2", 0x2439, true }, // 22 + { "vae3", 0x3439, true }, // 23 + { "aside1", 0x43A, true }, // 24 + { "vaae1", 0x43B, true }, // 25 + { "alle1", 0x243C, false }, // 26 + { "vale1", 0x43D, true }, // 27 + { "vale2", 0x243D, true }, // 28 + { "vale3", 0x343D, true }, // 29 + { "vmalls12e1", 0x243E, false }, // 30 + { "vaale1", 0x43F, true }, // 31 + { "vmalle1os", 0x408, false }, // 32 + { "vae1os", 0x409, true }, // 33 + { "aside1os", 0x40A, true }, // 34 + { "vaae1os", 0x40B, true }, // 35 + { "vale1os", 0x40D, true }, // 36 + { "vaale1os", 0x40F, true }, // 37 + { "ipas2e1os", 0x2420, true }, // 38 + { "ipas2le1os", 0x2424, true }, // 39 + { "vae2os", 0x2409, true }, // 40 + { "vale2os", 0x240D, true }, // 41 + { "vmalls12e1os", 0x240E, false }, // 42 + { "vae3os", 0x3409, true }, // 43 + { "vale3os", 0x340D, true }, // 44 + { "alle2os", 0x2408, false }, // 45 + { "alle1os", 0x240C, false }, // 46 + { "alle3os", 0x3408, false }, // 47 + { "rvae1", 0x431, true }, // 48 + { "rvaae1", 0x433, true }, // 49 + { "rvale1", 0x435, true }, // 50 + { "rvaale1", 0x437, true }, // 51 + { "rvae1is", 0x411, true }, // 52 + { "rvaae1is", 0x413, true }, // 53 + { "rvale1is", 0x415, true }, // 54 + { "rvaale1is", 0x417, true }, // 55 + { "rvae1os", 0x429, true }, // 56 + { "rvaae1os", 0x42B, true }, // 57 + { "rvale1os", 0x42D, true }, // 58 + { "rvaale1os", 0x42F, true }, // 59 + { "ripas2e1is", 0x2402, true }, // 60 + { "ripas2le1is", 0x2406, true }, // 61 + { "ripas2e1", 0x2422, true }, // 62 + { "ripas2le1", 0x2426, true }, // 63 + { "ripas2e1os", 0x2423, true }, // 64 + { "ripas2le1os", 0x2427, true }, // 65 + { "rvae2", 0x2431, true }, // 66 + { "rvale2", 0x2435, true }, // 67 + { "rvae2is", 0x2411, true }, // 68 + { "rvale2is", 0x2415, true }, // 69 + { "rvae2os", 0x2429, true }, // 70 + { "rvale2os", 0x242D, true }, // 71 + { "rvae3", 0x3431, true }, // 72 + { "rvale3", 0x3435, true }, // 73 + { "rvae3is", 0x3411, true }, // 74 + { "rvale3is", 0x3415, true }, // 75 + { "rvae3os", 0x3429, true }, // 76 + { "rvale3os", 0x342D, true }, // 77 +}; + +const TLBI *lookupTLBIByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x408, 32 }, + { 0x409, 33 }, + { 0x40A, 34 }, + { 0x40B, 35 }, + { 0x40D, 36 }, + { 0x40F, 37 }, + { 0x411, 52 }, + { 0x413, 53 }, + { 0x415, 54 }, + { 0x417, 55 }, + { 0x418, 2 }, + { 0x419, 5 }, + { 0x41A, 8 }, + { 0x41B, 9 }, + { 0x41D, 11 }, + { 0x41F, 15 }, + { 0x429, 56 }, + { 0x42B, 57 }, + { 0x42D, 58 }, + { 0x42F, 59 }, + { 0x431, 48 }, + { 0x433, 49 }, + { 0x435, 50 }, + { 0x437, 51 }, + { 0x438, 18 }, + { 0x439, 21 }, + { 0x43A, 24 }, + { 0x43B, 25 }, + { 0x43D, 27 }, + { 0x43F, 31 }, + { 0x2401, 0 }, + { 0x2402, 60 }, + { 0x2405, 1 }, + { 0x2406, 61 }, + { 0x2408, 45 }, + { 0x2409, 40 }, + { 0x240C, 46 }, + { 0x240D, 41 }, + { 0x240E, 42 }, + { 0x2411, 68 }, + { 0x2415, 69 }, + { 0x2418, 3 }, + { 0x2419, 6 }, + { 0x241C, 10 }, + { 0x241D, 12 }, + { 0x241E, 14 }, + { 0x2420, 38 }, + { 0x2421, 16 }, + { 0x2422, 62 }, + { 0x2423, 64 }, + { 0x2424, 39 }, + { 0x2425, 17 }, + { 0x2426, 63 }, + { 0x2427, 65 }, + { 0x2429, 70 }, + { 0x242D, 71 }, + { 0x2431, 66 }, + { 0x2435, 67 }, + { 0x2438, 19 }, + { 0x2439, 22 }, + { 0x243C, 26 }, + { 0x243D, 28 }, + { 0x243E, 30 }, + { 0x3408, 47 }, + { 0x3409, 43 }, + { 0x340D, 44 }, + { 0x3411, 74 }, + { 0x3415, 75 }, + { 0x3418, 4 }, + { 0x3419, 7 }, + { 0x341D, 13 }, + { 0x3429, 76 }, + { 0x342D, 77 }, + { 0x3431, 72 }, + { 0x3435, 73 }, + { 0x3438, 20 }, + { 0x3439, 23 }, + { 0x343D, 29 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &TLBIsList[Index[i].index]; +} + +static const SVEPRFM SVEPRFMsList[] = { + { "pldl1keep", 0x0 }, // 0 + { "pldl1strm", 0x1 }, // 1 + { "pldl2keep", 0x2 }, // 2 + { "pldl2strm", 0x3 }, // 3 + { "pldl3keep", 0x4 }, // 4 + { "pldl3strm", 0x5 }, // 5 + { "pstl1keep", 0x8 }, // 6 + { "pstl1strm", 0x9 }, // 7 + { "pstl2keep", 0xA }, // 8 + { "pstl2strm", 0xB }, // 9 + { "pstl3keep", 0xC }, // 10 + { "pstl3strm", 0xD }, // 11 +}; + +const SVEPRFM *lookupSVEPRFMByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x0, 0 }, + { 0x1, 1 }, + { 0x2, 2 }, + { 0x3, 3 }, + { 0x4, 4 }, + { 0x5, 5 }, + { 0x8, 6 }, + { 0x9, 7 }, + { 0xA, 8 }, + { 0xB, 9 }, + { 0xC, 10 }, + { 0xD, 11 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &SVEPRFMsList[Index[i].index]; +} + +static const PRFM PRFMsList[] = { + { "pldl1keep", 0x0 }, // 0 + { "pldl1strm", 0x1 }, // 1 + { "pldl2keep", 0x2 }, // 2 + { "pldl2strm", 0x3 }, // 3 + { "pldl3keep", 0x4 }, // 4 + { "pldl3strm", 0x5 }, // 5 + { "plil1keep", 0x8 }, // 6 + { "plil1strm", 0x9 }, // 7 + { "plil2keep", 0xa }, // 8 + { "plil2strm", 0xb }, // 9 + { "plil3keep", 0xc }, // 10 + { "plil3strm", 0xd }, // 11 + { "pstl1keep", 0x10 }, // 12 + { "pstl1strm", 0x11 }, // 13 + { "pstl2keep", 0x12 }, // 14 + { "pstl2strm", 0x13 }, // 15 + { "pstl3keep", 0x14 }, // 16 + { "pstl3strm", 0x15 }, // 17 +}; + +const PRFM *lookupPRFMByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x0, 0 }, + { 0x1, 1 }, + { 0x2, 2 }, + { 0x3, 3 }, + { 0x4, 4 }, + { 0x5, 5 }, + { 0x8, 6 }, + { 0x9, 7 }, + { 0xA, 8 }, + { 0xB, 9 }, + { 0xC, 10 }, + { 0xD, 11 }, + { 0x10, 12 }, + { 0x11, 13 }, + { 0x12, 14 }, + { 0x13, 15 }, + { 0x14, 16 }, + { 0x15, 17 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &PRFMsList[Index[i].index]; +} + +static const PSB PSBsList[] = { + { "csync", 0x11 }, // 0 +}; + +const PSB *AArch64PSBHint_lookupPSBByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x11, 0 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &PSBsList[Index[i].index]; +} + +static const ISB ISBsList[] = { + { "sy", 0xf }, // 0 +}; + +const ISB *lookupISBByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0xF, 0 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &ISBsList[Index[i].index]; +} + +static const TSB TSBsList[] = { + { "csync", 0x0 }, // 0 +}; + +const TSB *lookupTSBByEncoding(uint16_t Encoding) +{ + static const struct IndexType Index[] = { + { 0x0, 0 }, + }; + + if (Encoding >= ARR_SIZE(TSBsList)) + return NULL; + else + return &TSBsList[Index[Encoding].index]; +} + +static const SysReg SysRegsList[] = { + { "mdccsr_el0", 0x9808, true, false }, // 0 + { "dbgdtrrx_el0", 0x9828, true, false }, // 1 + { "mdrar_el1", 0x8080, true, false }, // 2 + { "oslsr_el1", 0x808C, true, false }, // 3 + { "dbgauthstatus_el1", 0x83F6, true, false }, // 4 + { "pmceid0_el0", 0xDCE6, true, false }, // 5 + { "pmceid1_el0", 0xDCE7, true, false }, // 6 + { "midr_el1", 0xC000, true, false }, // 7 + { "ccsidr_el1", 0xC800, true, false }, // 8 + { "ccsidr2_el1", 0xC802, true, false }, // 9 + { "clidr_el1", 0xC801, true, false }, // 10 + { "ctr_el0", 0xD801, true, false }, // 11 + { "mpidr_el1", 0xC005, true, false }, // 12 + { "revidr_el1", 0xC006, true, false }, // 13 + { "aidr_el1", 0xC807, true, false }, // 14 + { "dczid_el0", 0xD807, true, false }, // 15 + { "id_pfr0_el1", 0xC008, true, false }, // 16 + { "id_pfr1_el1", 0xC009, true, false }, // 17 + { "id_dfr0_el1", 0xC00A, true, false }, // 18 + { "id_afr0_el1", 0xC00B, true, false }, // 19 + { "id_mmfr0_el1", 0xC00C, true, false }, // 20 + { "id_mmfr1_el1", 0xC00D, true, false }, // 21 + { "id_mmfr2_el1", 0xC00E, true, false }, // 22 + { "id_mmfr3_el1", 0xC00F, true, false }, // 23 + { "id_isar0_el1", 0xC010, true, false }, // 24 + { "id_isar1_el1", 0xC011, true, false }, // 25 + { "id_isar2_el1", 0xC012, true, false }, // 26 + { "id_isar3_el1", 0xC013, true, false }, // 27 + { "id_isar4_el1", 0xC014, true, false }, // 28 + { "id_isar5_el1", 0xC015, true, false }, // 29 + { "id_isar6_el1", 0xC017, true, false }, // 30 + { "id_aa64pfr0_el1", 0xC020, true, false }, // 31 + { "id_aa64pfr1_el1", 0xC021, true, false }, // 32 + { "id_aa64dfr0_el1", 0xC028, true, false }, // 33 + { "id_aa64dfr1_el1", 0xC029, true, false }, // 34 + { "id_aa64afr0_el1", 0xC02C, true, false }, // 35 + { "id_aa64afr1_el1", 0xC02D, true, false }, // 36 + { "id_aa64isar0_el1", 0xC030, true, false }, // 37 + { "id_aa64isar1_el1", 0xC031, true, false }, // 38 + { "id_aa64mmfr0_el1", 0xC038, true, false }, // 39 + { "id_aa64mmfr1_el1", 0xC039, true, false }, // 40 + { "id_aa64mmfr2_el1", 0xC03A, true, false }, // 41 + { "mvfr0_el1", 0xC018, true, false }, // 42 + { "mvfr1_el1", 0xC019, true, false }, // 43 + { "mvfr2_el1", 0xC01A, true, false }, // 44 + { "rvbar_el1", 0xC601, true, false }, // 45 + { "rvbar_el2", 0xE601, true, false }, // 46 + { "rvbar_el3", 0xF601, true, false }, // 47 + { "isr_el1", 0xC608, true, false }, // 48 + { "cntpct_el0", 0xDF01, true, false }, // 49 + { "cntvct_el0", 0xDF02, true, false }, // 50 + { "id_mmfr4_el1", 0xC016, true, false }, // 51 + { "trcstatr", 0x8818, true, false }, // 52 + { "trcidr8", 0x8806, true, false }, // 53 + { "trcidr9", 0x880E, true, false }, // 54 + { "trcidr10", 0x8816, true, false }, // 55 + { "trcidr11", 0x881E, true, false }, // 56 + { "trcidr12", 0x8826, true, false }, // 57 + { "trcidr13", 0x882E, true, false }, // 58 + { "trcidr0", 0x8847, true, false }, // 59 + { "trcidr1", 0x884F, true, false }, // 60 + { "trcidr2", 0x8857, true, false }, // 61 + { "trcidr3", 0x885F, true, false }, // 62 + { "trcidr4", 0x8867, true, false }, // 63 + { "trcidr5", 0x886F, true, false }, // 64 + { "trcidr6", 0x8877, true, false }, // 65 + { "trcidr7", 0x887F, true, false }, // 66 + { "trcoslsr", 0x888C, true, false }, // 67 + { "trcpdsr", 0x88AC, true, false }, // 68 + { "trcdevaff0", 0x8BD6, true, false }, // 69 + { "trcdevaff1", 0x8BDE, true, false }, // 70 + { "trclsr", 0x8BEE, true, false }, // 71 + { "trcauthstatus", 0x8BF6, true, false }, // 72 + { "trcdevarch", 0x8BFE, true, false }, // 73 + { "trcdevid", 0x8B97, true, false }, // 74 + { "trcdevtype", 0x8B9F, true, false }, // 75 + { "trcpidr4", 0x8BA7, true, false }, // 76 + { "trcpidr5", 0x8BAF, true, false }, // 77 + { "trcpidr6", 0x8BB7, true, false }, // 78 + { "trcpidr7", 0x8BBF, true, false }, // 79 + { "trcpidr0", 0x8BC7, true, false }, // 80 + { "trcpidr1", 0x8BCF, true, false }, // 81 + { "trcpidr2", 0x8BD7, true, false }, // 82 + { "trcpidr3", 0x8BDF, true, false }, // 83 + { "trccidr0", 0x8BE7, true, false }, // 84 + { "trccidr1", 0x8BEF, true, false }, // 85 + { "trccidr2", 0x8BF7, true, false }, // 86 + { "trccidr3", 0x8BFF, true, false }, // 87 + { "icc_iar1_el1", 0xC660, true, false }, // 88 + { "icc_iar0_el1", 0xC640, true, false }, // 89 + { "icc_hppir1_el1", 0xC662, true, false }, // 90 + { "icc_hppir0_el1", 0xC642, true, false }, // 91 + { "icc_rpr_el1", 0xC65B, true, false }, // 92 + { "ich_vtr_el2", 0xE659, true, false }, // 93 + { "ich_eisr_el2", 0xE65B, true, false }, // 94 + { "ich_elrsr_el2", 0xE65D, true, false }, // 95 + { "id_aa64zfr0_el1", 0xC024, true, false }, // 96 + { "lorid_el1", 0xC527, true, false }, // 97 + { "erridr_el1", 0xC298, true, false }, // 98 + { "erxfr_el1", 0xC2A0, true, false }, // 99 + { "dbgdtrtx_el0", 0x9828, false, true }, // 100 + { "oslar_el1", 0x8084, false, true }, // 101 + { "pmswinc_el0", 0xDCE4, false, true }, // 102 + { "trcoslar", 0x8884, false, true }, // 103 + { "trclar", 0x8BE6, false, true }, // 104 + { "icc_eoir1_el1", 0xC661, false, true }, // 105 + { "icc_eoir0_el1", 0xC641, false, true }, // 106 + { "icc_dir_el1", 0xC659, false, true }, // 107 + { "icc_sgi1r_el1", 0xC65D, false, true }, // 108 + { "icc_asgi1r_el1", 0xC65E, false, true }, // 109 + { "icc_sgi0r_el1", 0xC65F, false, true }, // 110 + { "osdtrrx_el1", 0x8002, true, true }, // 111 + { "osdtrtx_el1", 0x801A, true, true }, // 112 + { "teecr32_el1", 0x9000, true, true }, // 113 + { "mdccint_el1", 0x8010, true, true }, // 114 + { "mdscr_el1", 0x8012, true, true }, // 115 + { "dbgdtr_el0", 0x9820, true, true }, // 116 + { "oseccr_el1", 0x8032, true, true }, // 117 + { "dbgvcr32_el2", 0xA038, true, true }, // 118 + { "dbgbvr0_el1", 0x8004, true, true }, // 119 + { "dbgbvr1_el1", 0x800C, true, true }, // 120 + { "dbgbvr2_el1", 0x8014, true, true }, // 121 + { "dbgbvr3_el1", 0x801C, true, true }, // 122 + { "dbgbvr4_el1", 0x8024, true, true }, // 123 + { "dbgbvr5_el1", 0x802C, true, true }, // 124 + { "dbgbvr6_el1", 0x8034, true, true }, // 125 + { "dbgbvr7_el1", 0x803C, true, true }, // 126 + { "dbgbvr8_el1", 0x8044, true, true }, // 127 + { "dbgbvr9_el1", 0x804C, true, true }, // 128 + { "dbgbvr10_el1", 0x8054, true, true }, // 129 + { "dbgbvr11_el1", 0x805C, true, true }, // 130 + { "dbgbvr12_el1", 0x8064, true, true }, // 131 + { "dbgbvr13_el1", 0x806C, true, true }, // 132 + { "dbgbvr14_el1", 0x8074, true, true }, // 133 + { "dbgbvr15_el1", 0x807C, true, true }, // 134 + { "dbgbcr0_el1", 0x8005, true, true }, // 135 + { "dbgbcr1_el1", 0x800D, true, true }, // 136 + { "dbgbcr2_el1", 0x8015, true, true }, // 137 + { "dbgbcr3_el1", 0x801D, true, true }, // 138 + { "dbgbcr4_el1", 0x8025, true, true }, // 139 + { "dbgbcr5_el1", 0x802D, true, true }, // 140 + { "dbgbcr6_el1", 0x8035, true, true }, // 141 + { "dbgbcr7_el1", 0x803D, true, true }, // 142 + { "dbgbcr8_el1", 0x8045, true, true }, // 143 + { "dbgbcr9_el1", 0x804D, true, true }, // 144 + { "dbgbcr10_el1", 0x8055, true, true }, // 145 + { "dbgbcr11_el1", 0x805D, true, true }, // 146 + { "dbgbcr12_el1", 0x8065, true, true }, // 147 + { "dbgbcr13_el1", 0x806D, true, true }, // 148 + { "dbgbcr14_el1", 0x8075, true, true }, // 149 + { "dbgbcr15_el1", 0x807D, true, true }, // 150 + { "dbgwvr0_el1", 0x8006, true, true }, // 151 + { "dbgwvr1_el1", 0x800E, true, true }, // 152 + { "dbgwvr2_el1", 0x8016, true, true }, // 153 + { "dbgwvr3_el1", 0x801E, true, true }, // 154 + { "dbgwvr4_el1", 0x8026, true, true }, // 155 + { "dbgwvr5_el1", 0x802E, true, true }, // 156 + { "dbgwvr6_el1", 0x8036, true, true }, // 157 + { "dbgwvr7_el1", 0x803E, true, true }, // 158 + { "dbgwvr8_el1", 0x8046, true, true }, // 159 + { "dbgwvr9_el1", 0x804E, true, true }, // 160 + { "dbgwvr10_el1", 0x8056, true, true }, // 161 + { "dbgwvr11_el1", 0x805E, true, true }, // 162 + { "dbgwvr12_el1", 0x8066, true, true }, // 163 + { "dbgwvr13_el1", 0x806E, true, true }, // 164 + { "dbgwvr14_el1", 0x8076, true, true }, // 165 + { "dbgwvr15_el1", 0x807E, true, true }, // 166 + { "dbgwcr0_el1", 0x8007, true, true }, // 167 + { "dbgwcr1_el1", 0x800F, true, true }, // 168 + { "dbgwcr2_el1", 0x8017, true, true }, // 169 + { "dbgwcr3_el1", 0x801F, true, true }, // 170 + { "dbgwcr4_el1", 0x8027, true, true }, // 171 + { "dbgwcr5_el1", 0x802F, true, true }, // 172 + { "dbgwcr6_el1", 0x8037, true, true }, // 173 + { "dbgwcr7_el1", 0x803F, true, true }, // 174 + { "dbgwcr8_el1", 0x8047, true, true }, // 175 + { "dbgwcr9_el1", 0x804F, true, true }, // 176 + { "dbgwcr10_el1", 0x8057, true, true }, // 177 + { "dbgwcr11_el1", 0x805F, true, true }, // 178 + { "dbgwcr12_el1", 0x8067, true, true }, // 179 + { "dbgwcr13_el1", 0x806F, true, true }, // 180 + { "dbgwcr14_el1", 0x8077, true, true }, // 181 + { "dbgwcr15_el1", 0x807F, true, true }, // 182 + { "teehbr32_el1", 0x9080, true, true }, // 183 + { "osdlr_el1", 0x809C, true, true }, // 184 + { "dbgprcr_el1", 0x80A4, true, true }, // 185 + { "dbgclaimset_el1", 0x83C6, true, true }, // 186 + { "dbgclaimclr_el1", 0x83CE, true, true }, // 187 + { "csselr_el1", 0xD000, true, true }, // 188 + { "vpidr_el2", 0xE000, true, true }, // 189 + { "vmpidr_el2", 0xE005, true, true }, // 190 + { "cpacr_el1", 0xC082, true, true }, // 191 + { "sctlr_el1", 0xC080, true, true }, // 192 + { "sctlr_el2", 0xE080, true, true }, // 193 + { "sctlr_el3", 0xF080, true, true }, // 194 + { "actlr_el1", 0xC081, true, true }, // 195 + { "actlr_el2", 0xE081, true, true }, // 196 + { "actlr_el3", 0xF081, true, true }, // 197 + { "hcr_el2", 0xE088, true, true }, // 198 + { "scr_el3", 0xF088, true, true }, // 199 + { "mdcr_el2", 0xE089, true, true }, // 200 + { "sder32_el3", 0xF089, true, true }, // 201 + { "cptr_el2", 0xE08A, true, true }, // 202 + { "cptr_el3", 0xF08A, true, true }, // 203 + { "hstr_el2", 0xE08B, true, true }, // 204 + { "hacr_el2", 0xE08F, true, true }, // 205 + { "mdcr_el3", 0xF099, true, true }, // 206 + { "ttbr0_el1", 0xC100, true, true }, // 207 + { "ttbr0_el2", 0xE100, true, true }, // 208 + { "ttbr0_el3", 0xF100, true, true }, // 209 + { "ttbr1_el1", 0xC101, true, true }, // 210 + { "tcr_el1", 0xC102, true, true }, // 211 + { "tcr_el2", 0xE102, true, true }, // 212 + { "tcr_el3", 0xF102, true, true }, // 213 + { "vttbr_el2", 0xE108, true, true }, // 214 + { "vtcr_el2", 0xE10A, true, true }, // 215 + { "dacr32_el2", 0xE180, true, true }, // 216 + { "spsr_el1", 0xC200, true, true }, // 217 + { "spsr_el2", 0xE200, true, true }, // 218 + { "spsr_el3", 0xF200, true, true }, // 219 + { "elr_el1", 0xC201, true, true }, // 220 + { "elr_el2", 0xE201, true, true }, // 221 + { "elr_el3", 0xF201, true, true }, // 222 + { "sp_el0", 0xC208, true, true }, // 223 + { "sp_el1", 0xE208, true, true }, // 224 + { "sp_el2", 0xF208, true, true }, // 225 + { "spsel", 0xC210, true, true }, // 226 + { "nzcv", 0xDA10, true, true }, // 227 + { "daif", 0xDA11, true, true }, // 228 + { "currentel", 0xC212, true, true }, // 229 + { "spsr_irq", 0xE218, true, true }, // 230 + { "spsr_abt", 0xE219, true, true }, // 231 + { "spsr_und", 0xE21A, true, true }, // 232 + { "spsr_fiq", 0xE21B, true, true }, // 233 + { "fpcr", 0xDA20, true, true }, // 234 + { "fpsr", 0xDA21, true, true }, // 235 + { "dspsr_el0", 0xDA28, true, true }, // 236 + { "dlr_el0", 0xDA29, true, true }, // 237 + { "ifsr32_el2", 0xE281, true, true }, // 238 + { "afsr0_el1", 0xC288, true, true }, // 239 + { "afsr0_el2", 0xE288, true, true }, // 240 + { "afsr0_el3", 0xF288, true, true }, // 241 + { "afsr1_el1", 0xC289, true, true }, // 242 + { "afsr1_el2", 0xE289, true, true }, // 243 + { "afsr1_el3", 0xF289, true, true }, // 244 + { "esr_el1", 0xC290, true, true }, // 245 + { "esr_el2", 0xE290, true, true }, // 246 + { "esr_el3", 0xF290, true, true }, // 247 + { "fpexc32_el2", 0xE298, true, true }, // 248 + { "far_el1", 0xC300, true, true }, // 249 + { "far_el2", 0xE300, true, true }, // 250 + { "far_el3", 0xF300, true, true }, // 251 + { "hpfar_el2", 0xE304, true, true }, // 252 + { "par_el1", 0xC3A0, true, true }, // 253 + { "pmcr_el0", 0xDCE0, true, true }, // 254 + { "pmcntenset_el0", 0xDCE1, true, true }, // 255 + { "pmcntenclr_el0", 0xDCE2, true, true }, // 256 + { "pmovsclr_el0", 0xDCE3, true, true }, // 257 + { "pmselr_el0", 0xDCE5, true, true }, // 258 + { "pmccntr_el0", 0xDCE8, true, true }, // 259 + { "pmxevtyper_el0", 0xDCE9, true, true }, // 260 + { "pmxevcntr_el0", 0xDCEA, true, true }, // 261 + { "pmuserenr_el0", 0xDCF0, true, true }, // 262 + { "pmintenset_el1", 0xC4F1, true, true }, // 263 + { "pmintenclr_el1", 0xC4F2, true, true }, // 264 + { "pmovsset_el0", 0xDCF3, true, true }, // 265 + { "mair_el1", 0xC510, true, true }, // 266 + { "mair_el2", 0xE510, true, true }, // 267 + { "mair_el3", 0xF510, true, true }, // 268 + { "amair_el1", 0xC518, true, true }, // 269 + { "amair_el2", 0xE518, true, true }, // 270 + { "amair_el3", 0xF518, true, true }, // 271 + { "vbar_el1", 0xC600, true, true }, // 272 + { "vbar_el2", 0xE600, true, true }, // 273 + { "vbar_el3", 0xF600, true, true }, // 274 + { "rmr_el1", 0xC602, true, true }, // 275 + { "rmr_el2", 0xE602, true, true }, // 276 + { "rmr_el3", 0xF602, true, true }, // 277 + { "contextidr_el1", 0xC681, true, true }, // 278 + { "tpidr_el0", 0xDE82, true, true }, // 279 + { "tpidr_el2", 0xE682, true, true }, // 280 + { "tpidr_el3", 0xF682, true, true }, // 281 + { "tpidrro_el0", 0xDE83, true, true }, // 282 + { "tpidr_el1", 0xC684, true, true }, // 283 + { "cntfrq_el0", 0xDF00, true, true }, // 284 + { "cntvoff_el2", 0xE703, true, true }, // 285 + { "cntkctl_el1", 0xC708, true, true }, // 286 + { "cnthctl_el2", 0xE708, true, true }, // 287 + { "cntp_tval_el0", 0xDF10, true, true }, // 288 + { "cnthp_tval_el2", 0xE710, true, true }, // 289 + { "cntps_tval_el1", 0xFF10, true, true }, // 290 + { "cntp_ctl_el0", 0xDF11, true, true }, // 291 + { "cnthp_ctl_el2", 0xE711, true, true }, // 292 + { "cntps_ctl_el1", 0xFF11, true, true }, // 293 + { "cntp_cval_el0", 0xDF12, true, true }, // 294 + { "cnthp_cval_el2", 0xE712, true, true }, // 295 + { "cntps_cval_el1", 0xFF12, true, true }, // 296 + { "cntv_tval_el0", 0xDF18, true, true }, // 297 + { "cntv_ctl_el0", 0xDF19, true, true }, // 298 + { "cntv_cval_el0", 0xDF1A, true, true }, // 299 + { "pmevcntr0_el0", 0xDF40, true, true }, // 300 + { "pmevcntr1_el0", 0xDF41, true, true }, // 301 + { "pmevcntr2_el0", 0xDF42, true, true }, // 302 + { "pmevcntr3_el0", 0xDF43, true, true }, // 303 + { "pmevcntr4_el0", 0xDF44, true, true }, // 304 + { "pmevcntr5_el0", 0xDF45, true, true }, // 305 + { "pmevcntr6_el0", 0xDF46, true, true }, // 306 + { "pmevcntr7_el0", 0xDF47, true, true }, // 307 + { "pmevcntr8_el0", 0xDF48, true, true }, // 308 + { "pmevcntr9_el0", 0xDF49, true, true }, // 309 + { "pmevcntr10_el0", 0xDF4A, true, true }, // 310 + { "pmevcntr11_el0", 0xDF4B, true, true }, // 311 + { "pmevcntr12_el0", 0xDF4C, true, true }, // 312 + { "pmevcntr13_el0", 0xDF4D, true, true }, // 313 + { "pmevcntr14_el0", 0xDF4E, true, true }, // 314 + { "pmevcntr15_el0", 0xDF4F, true, true }, // 315 + { "pmevcntr16_el0", 0xDF50, true, true }, // 316 + { "pmevcntr17_el0", 0xDF51, true, true }, // 317 + { "pmevcntr18_el0", 0xDF52, true, true }, // 318 + { "pmevcntr19_el0", 0xDF53, true, true }, // 319 + { "pmevcntr20_el0", 0xDF54, true, true }, // 320 + { "pmevcntr21_el0", 0xDF55, true, true }, // 321 + { "pmevcntr22_el0", 0xDF56, true, true }, // 322 + { "pmevcntr23_el0", 0xDF57, true, true }, // 323 + { "pmevcntr24_el0", 0xDF58, true, true }, // 324 + { "pmevcntr25_el0", 0xDF59, true, true }, // 325 + { "pmevcntr26_el0", 0xDF5A, true, true }, // 326 + { "pmevcntr27_el0", 0xDF5B, true, true }, // 327 + { "pmevcntr28_el0", 0xDF5C, true, true }, // 328 + { "pmevcntr29_el0", 0xDF5D, true, true }, // 329 + { "pmevcntr30_el0", 0xDF5E, true, true }, // 330 + { "pmccfiltr_el0", 0xDF7F, true, true }, // 331 + { "pmevtyper0_el0", 0xDF60, true, true }, // 332 + { "pmevtyper1_el0", 0xDF61, true, true }, // 333 + { "pmevtyper2_el0", 0xDF62, true, true }, // 334 + { "pmevtyper3_el0", 0xDF63, true, true }, // 335 + { "pmevtyper4_el0", 0xDF64, true, true }, // 336 + { "pmevtyper5_el0", 0xDF65, true, true }, // 337 + { "pmevtyper6_el0", 0xDF66, true, true }, // 338 + { "pmevtyper7_el0", 0xDF67, true, true }, // 339 + { "pmevtyper8_el0", 0xDF68, true, true }, // 340 + { "pmevtyper9_el0", 0xDF69, true, true }, // 341 + { "pmevtyper10_el0", 0xDF6A, true, true }, // 342 + { "pmevtyper11_el0", 0xDF6B, true, true }, // 343 + { "pmevtyper12_el0", 0xDF6C, true, true }, // 344 + { "pmevtyper13_el0", 0xDF6D, true, true }, // 345 + { "pmevtyper14_el0", 0xDF6E, true, true }, // 346 + { "pmevtyper15_el0", 0xDF6F, true, true }, // 347 + { "pmevtyper16_el0", 0xDF70, true, true }, // 348 + { "pmevtyper17_el0", 0xDF71, true, true }, // 349 + { "pmevtyper18_el0", 0xDF72, true, true }, // 350 + { "pmevtyper19_el0", 0xDF73, true, true }, // 351 + { "pmevtyper20_el0", 0xDF74, true, true }, // 352 + { "pmevtyper21_el0", 0xDF75, true, true }, // 353 + { "pmevtyper22_el0", 0xDF76, true, true }, // 354 + { "pmevtyper23_el0", 0xDF77, true, true }, // 355 + { "pmevtyper24_el0", 0xDF78, true, true }, // 356 + { "pmevtyper25_el0", 0xDF79, true, true }, // 357 + { "pmevtyper26_el0", 0xDF7A, true, true }, // 358 + { "pmevtyper27_el0", 0xDF7B, true, true }, // 359 + { "pmevtyper28_el0", 0xDF7C, true, true }, // 360 + { "pmevtyper29_el0", 0xDF7D, true, true }, // 361 + { "pmevtyper30_el0", 0xDF7E, true, true }, // 362 + { "trcprgctlr", 0x8808, true, true }, // 363 + { "trcprocselr", 0x8810, true, true }, // 364 + { "trcconfigr", 0x8820, true, true }, // 365 + { "trcauxctlr", 0x8830, true, true }, // 366 + { "trceventctl0r", 0x8840, true, true }, // 367 + { "trceventctl1r", 0x8848, true, true }, // 368 + { "trcstallctlr", 0x8858, true, true }, // 369 + { "trctsctlr", 0x8860, true, true }, // 370 + { "trcsyncpr", 0x8868, true, true }, // 371 + { "trcccctlr", 0x8870, true, true }, // 372 + { "trcbbctlr", 0x8878, true, true }, // 373 + { "trctraceidr", 0x8801, true, true }, // 374 + { "trcqctlr", 0x8809, true, true }, // 375 + { "trcvictlr", 0x8802, true, true }, // 376 + { "trcviiectlr", 0x880A, true, true }, // 377 + { "trcvissctlr", 0x8812, true, true }, // 378 + { "trcvipcssctlr", 0x881A, true, true }, // 379 + { "trcvdctlr", 0x8842, true, true }, // 380 + { "trcvdsacctlr", 0x884A, true, true }, // 381 + { "trcvdarcctlr", 0x8852, true, true }, // 382 + { "trcseqevr0", 0x8804, true, true }, // 383 + { "trcseqevr1", 0x880C, true, true }, // 384 + { "trcseqevr2", 0x8814, true, true }, // 385 + { "trcseqrstevr", 0x8834, true, true }, // 386 + { "trcseqstr", 0x883C, true, true }, // 387 + { "trcextinselr", 0x8844, true, true }, // 388 + { "trccntrldvr0", 0x8805, true, true }, // 389 + { "trccntrldvr1", 0x880D, true, true }, // 390 + { "trccntrldvr2", 0x8815, true, true }, // 391 + { "trccntrldvr3", 0x881D, true, true }, // 392 + { "trccntctlr0", 0x8825, true, true }, // 393 + { "trccntctlr1", 0x882D, true, true }, // 394 + { "trccntctlr2", 0x8835, true, true }, // 395 + { "trccntctlr3", 0x883D, true, true }, // 396 + { "trccntvr0", 0x8845, true, true }, // 397 + { "trccntvr1", 0x884D, true, true }, // 398 + { "trccntvr2", 0x8855, true, true }, // 399 + { "trccntvr3", 0x885D, true, true }, // 400 + { "trcimspec0", 0x8807, true, true }, // 401 + { "trcimspec1", 0x880F, true, true }, // 402 + { "trcimspec2", 0x8817, true, true }, // 403 + { "trcimspec3", 0x881F, true, true }, // 404 + { "trcimspec4", 0x8827, true, true }, // 405 + { "trcimspec5", 0x882F, true, true }, // 406 + { "trcimspec6", 0x8837, true, true }, // 407 + { "trcimspec7", 0x883F, true, true }, // 408 + { "trcrsctlr2", 0x8890, true, true }, // 409 + { "trcrsctlr3", 0x8898, true, true }, // 410 + { "trcrsctlr4", 0x88A0, true, true }, // 411 + { "trcrsctlr5", 0x88A8, true, true }, // 412 + { "trcrsctlr6", 0x88B0, true, true }, // 413 + { "trcrsctlr7", 0x88B8, true, true }, // 414 + { "trcrsctlr8", 0x88C0, true, true }, // 415 + { "trcrsctlr9", 0x88C8, true, true }, // 416 + { "trcrsctlr10", 0x88D0, true, true }, // 417 + { "trcrsctlr11", 0x88D8, true, true }, // 418 + { "trcrsctlr12", 0x88E0, true, true }, // 419 + { "trcrsctlr13", 0x88E8, true, true }, // 420 + { "trcrsctlr14", 0x88F0, true, true }, // 421 + { "trcrsctlr15", 0x88F8, true, true }, // 422 + { "trcrsctlr16", 0x8881, true, true }, // 423 + { "trcrsctlr17", 0x8889, true, true }, // 424 + { "trcrsctlr18", 0x8891, true, true }, // 425 + { "trcrsctlr19", 0x8899, true, true }, // 426 + { "trcrsctlr20", 0x88A1, true, true }, // 427 + { "trcrsctlr21", 0x88A9, true, true }, // 428 + { "trcrsctlr22", 0x88B1, true, true }, // 429 + { "trcrsctlr23", 0x88B9, true, true }, // 430 + { "trcrsctlr24", 0x88C1, true, true }, // 431 + { "trcrsctlr25", 0x88C9, true, true }, // 432 + { "trcrsctlr26", 0x88D1, true, true }, // 433 + { "trcrsctlr27", 0x88D9, true, true }, // 434 + { "trcrsctlr28", 0x88E1, true, true }, // 435 + { "trcrsctlr29", 0x88E9, true, true }, // 436 + { "trcrsctlr30", 0x88F1, true, true }, // 437 + { "trcrsctlr31", 0x88F9, true, true }, // 438 + { "trcssccr0", 0x8882, true, true }, // 439 + { "trcssccr1", 0x888A, true, true }, // 440 + { "trcssccr2", 0x8892, true, true }, // 441 + { "trcssccr3", 0x889A, true, true }, // 442 + { "trcssccr4", 0x88A2, true, true }, // 443 + { "trcssccr5", 0x88AA, true, true }, // 444 + { "trcssccr6", 0x88B2, true, true }, // 445 + { "trcssccr7", 0x88BA, true, true }, // 446 + { "trcsscsr0", 0x88C2, true, true }, // 447 + { "trcsscsr1", 0x88CA, true, true }, // 448 + { "trcsscsr2", 0x88D2, true, true }, // 449 + { "trcsscsr3", 0x88DA, true, true }, // 450 + { "trcsscsr4", 0x88E2, true, true }, // 451 + { "trcsscsr5", 0x88EA, true, true }, // 452 + { "trcsscsr6", 0x88F2, true, true }, // 453 + { "trcsscsr7", 0x88FA, true, true }, // 454 + { "trcsspcicr0", 0x8883, true, true }, // 455 + { "trcsspcicr1", 0x888B, true, true }, // 456 + { "trcsspcicr2", 0x8893, true, true }, // 457 + { "trcsspcicr3", 0x889B, true, true }, // 458 + { "trcsspcicr4", 0x88A3, true, true }, // 459 + { "trcsspcicr5", 0x88AB, true, true }, // 460 + { "trcsspcicr6", 0x88B3, true, true }, // 461 + { "trcsspcicr7", 0x88BB, true, true }, // 462 + { "trcpdcr", 0x88A4, true, true }, // 463 + { "trcacvr0", 0x8900, true, true }, // 464 + { "trcacvr1", 0x8910, true, true }, // 465 + { "trcacvr2", 0x8920, true, true }, // 466 + { "trcacvr3", 0x8930, true, true }, // 467 + { "trcacvr4", 0x8940, true, true }, // 468 + { "trcacvr5", 0x8950, true, true }, // 469 + { "trcacvr6", 0x8960, true, true }, // 470 + { "trcacvr7", 0x8970, true, true }, // 471 + { "trcacvr8", 0x8901, true, true }, // 472 + { "trcacvr9", 0x8911, true, true }, // 473 + { "trcacvr10", 0x8921, true, true }, // 474 + { "trcacvr11", 0x8931, true, true }, // 475 + { "trcacvr12", 0x8941, true, true }, // 476 + { "trcacvr13", 0x8951, true, true }, // 477 + { "trcacvr14", 0x8961, true, true }, // 478 + { "trcacvr15", 0x8971, true, true }, // 479 + { "trcacatr0", 0x8902, true, true }, // 480 + { "trcacatr1", 0x8912, true, true }, // 481 + { "trcacatr2", 0x8922, true, true }, // 482 + { "trcacatr3", 0x8932, true, true }, // 483 + { "trcacatr4", 0x8942, true, true }, // 484 + { "trcacatr5", 0x8952, true, true }, // 485 + { "trcacatr6", 0x8962, true, true }, // 486 + { "trcacatr7", 0x8972, true, true }, // 487 + { "trcacatr8", 0x8903, true, true }, // 488 + { "trcacatr9", 0x8913, true, true }, // 489 + { "trcacatr10", 0x8923, true, true }, // 490 + { "trcacatr11", 0x8933, true, true }, // 491 + { "trcacatr12", 0x8943, true, true }, // 492 + { "trcacatr13", 0x8953, true, true }, // 493 + { "trcacatr14", 0x8963, true, true }, // 494 + { "trcacatr15", 0x8973, true, true }, // 495 + { "trcdvcvr0", 0x8904, true, true }, // 496 + { "trcdvcvr1", 0x8924, true, true }, // 497 + { "trcdvcvr2", 0x8944, true, true }, // 498 + { "trcdvcvr3", 0x8964, true, true }, // 499 + { "trcdvcvr4", 0x8905, true, true }, // 500 + { "trcdvcvr5", 0x8925, true, true }, // 501 + { "trcdvcvr6", 0x8945, true, true }, // 502 + { "trcdvcvr7", 0x8965, true, true }, // 503 + { "trcdvcmr0", 0x8906, true, true }, // 504 + { "trcdvcmr1", 0x8926, true, true }, // 505 + { "trcdvcmr2", 0x8946, true, true }, // 506 + { "trcdvcmr3", 0x8966, true, true }, // 507 + { "trcdvcmr4", 0x8907, true, true }, // 508 + { "trcdvcmr5", 0x8927, true, true }, // 509 + { "trcdvcmr6", 0x8947, true, true }, // 510 + { "trcdvcmr7", 0x8967, true, true }, // 511 + { "trccidcvr0", 0x8980, true, true }, // 512 + { "trccidcvr1", 0x8990, true, true }, // 513 + { "trccidcvr2", 0x89A0, true, true }, // 514 + { "trccidcvr3", 0x89B0, true, true }, // 515 + { "trccidcvr4", 0x89C0, true, true }, // 516 + { "trccidcvr5", 0x89D0, true, true }, // 517 + { "trccidcvr6", 0x89E0, true, true }, // 518 + { "trccidcvr7", 0x89F0, true, true }, // 519 + { "trcvmidcvr0", 0x8981, true, true }, // 520 + { "trcvmidcvr1", 0x8991, true, true }, // 521 + { "trcvmidcvr2", 0x89A1, true, true }, // 522 + { "trcvmidcvr3", 0x89B1, true, true }, // 523 + { "trcvmidcvr4", 0x89C1, true, true }, // 524 + { "trcvmidcvr5", 0x89D1, true, true }, // 525 + { "trcvmidcvr6", 0x89E1, true, true }, // 526 + { "trcvmidcvr7", 0x89F1, true, true }, // 527 + { "trccidcctlr0", 0x8982, true, true }, // 528 + { "trccidcctlr1", 0x898A, true, true }, // 529 + { "trcvmidcctlr0", 0x8992, true, true }, // 530 + { "trcvmidcctlr1", 0x899A, true, true }, // 531 + { "trcitctrl", 0x8B84, true, true }, // 532 + { "trcclaimset", 0x8BC6, true, true }, // 533 + { "trcclaimclr", 0x8BCE, true, true }, // 534 + { "icc_bpr1_el1", 0xC663, true, true }, // 535 + { "icc_bpr0_el1", 0xC643, true, true }, // 536 + { "icc_pmr_el1", 0xC230, true, true }, // 537 + { "icc_ctlr_el1", 0xC664, true, true }, // 538 + { "icc_ctlr_el3", 0xF664, true, true }, // 539 + { "icc_sre_el1", 0xC665, true, true }, // 540 + { "icc_sre_el2", 0xE64D, true, true }, // 541 + { "icc_sre_el3", 0xF665, true, true }, // 542 + { "icc_igrpen0_el1", 0xC666, true, true }, // 543 + { "icc_igrpen1_el1", 0xC667, true, true }, // 544 + { "icc_igrpen1_el3", 0xF667, true, true }, // 545 + { "icc_seien_el1", 0xC668, true, true }, // 546 + { "icc_ap0r0_el1", 0xC644, true, true }, // 547 + { "icc_ap0r1_el1", 0xC645, true, true }, // 548 + { "icc_ap0r2_el1", 0xC646, true, true }, // 549 + { "icc_ap0r3_el1", 0xC647, true, true }, // 550 + { "icc_ap1r0_el1", 0xC648, true, true }, // 551 + { "icc_ap1r1_el1", 0xC649, true, true }, // 552 + { "icc_ap1r2_el1", 0xC64A, true, true }, // 553 + { "icc_ap1r3_el1", 0xC64B, true, true }, // 554 + { "ich_ap0r0_el2", 0xE640, true, true }, // 555 + { "ich_ap0r1_el2", 0xE641, true, true }, // 556 + { "ich_ap0r2_el2", 0xE642, true, true }, // 557 + { "ich_ap0r3_el2", 0xE643, true, true }, // 558 + { "ich_ap1r0_el2", 0xE648, true, true }, // 559 + { "ich_ap1r1_el2", 0xE649, true, true }, // 560 + { "ich_ap1r2_el2", 0xE64A, true, true }, // 561 + { "ich_ap1r3_el2", 0xE64B, true, true }, // 562 + { "ich_hcr_el2", 0xE658, true, true }, // 563 + { "ich_misr_el2", 0xE65A, true, true }, // 564 + { "ich_vmcr_el2", 0xE65F, true, true }, // 565 + { "ich_vseir_el2", 0xE64C, true, true }, // 566 + { "ich_lr0_el2", 0xE660, true, true }, // 567 + { "ich_lr1_el2", 0xE661, true, true }, // 568 + { "ich_lr2_el2", 0xE662, true, true }, // 569 + { "ich_lr3_el2", 0xE663, true, true }, // 570 + { "ich_lr4_el2", 0xE664, true, true }, // 571 + { "ich_lr5_el2", 0xE665, true, true }, // 572 + { "ich_lr6_el2", 0xE666, true, true }, // 573 + { "ich_lr7_el2", 0xE667, true, true }, // 574 + { "ich_lr8_el2", 0xE668, true, true }, // 575 + { "ich_lr9_el2", 0xE669, true, true }, // 576 + { "ich_lr10_el2", 0xE66A, true, true }, // 577 + { "ich_lr11_el2", 0xE66B, true, true }, // 578 + { "ich_lr12_el2", 0xE66C, true, true }, // 579 + { "ich_lr13_el2", 0xE66D, true, true }, // 580 + { "ich_lr14_el2", 0xE66E, true, true }, // 581 + { "ich_lr15_el2", 0xE66F, true, true }, // 582 + { "pan", 0xC213, true, true }, // 583 + { "lorsa_el1", 0xC520, true, true }, // 584 + { "lorea_el1", 0xC521, true, true }, // 585 + { "lorn_el1", 0xC522, true, true }, // 586 + { "lorc_el1", 0xC523, true, true }, // 587 + { "ttbr1_el2", 0xE101, true, true }, // 588 + { "contextidr_el2", 0xE681, true, true }, // 589 + { "cnthv_tval_el2", 0xE718, true, true }, // 590 + { "cnthv_cval_el2", 0xE71A, true, true }, // 591 + { "cnthv_ctl_el2", 0xE719, true, true }, // 592 + { "sctlr_el12", 0xE880, true, true }, // 593 + { "cpacr_el12", 0xE882, true, true }, // 594 + { "ttbr0_el12", 0xE900, true, true }, // 595 + { "ttbr1_el12", 0xE901, true, true }, // 596 + { "tcr_el12", 0xE902, true, true }, // 597 + { "afsr0_el12", 0xEA88, true, true }, // 598 + { "afsr1_el12", 0xEA89, true, true }, // 599 + { "esr_el12", 0xEA90, true, true }, // 600 + { "far_el12", 0xEB00, true, true }, // 601 + { "mair_el12", 0xED10, true, true }, // 602 + { "amair_el12", 0xED18, true, true }, // 603 + { "vbar_el12", 0xEE00, true, true }, // 604 + { "contextidr_el12", 0xEE81, true, true }, // 605 + { "cntkctl_el12", 0xEF08, true, true }, // 606 + { "cntp_tval_el02", 0xEF10, true, true }, // 607 + { "cntp_ctl_el02", 0xEF11, true, true }, // 608 + { "cntp_cval_el02", 0xEF12, true, true }, // 609 + { "cntv_tval_el02", 0xEF18, true, true }, // 610 + { "cntv_ctl_el02", 0xEF19, true, true }, // 611 + { "cntv_cval_el02", 0xEF1A, true, true }, // 612 + { "spsr_el12", 0xEA00, true, true }, // 613 + { "elr_el12", 0xEA01, true, true }, // 614 + { "uao", 0xC214, true, true }, // 615 + { "pmblimitr_el1", 0xC4D0, true, true }, // 616 + { "pmbptr_el1", 0xC4D1, true, true }, // 617 + { "pmbsr_el1", 0xC4D3, true, true }, // 618 + { "pmbidr_el1", 0xC4D7, true, true }, // 619 + { "pmscr_el2", 0xE4C8, true, true }, // 620 + { "pmscr_el12", 0xECC8, true, true }, // 621 + { "pmscr_el1", 0xC4C8, true, true }, // 622 + { "pmsicr_el1", 0xC4CA, true, true }, // 623 + { "pmsirr_el1", 0xC4CB, true, true }, // 624 + { "pmsfcr_el1", 0xC4CC, true, true }, // 625 + { "pmsevfr_el1", 0xC4CD, true, true }, // 626 + { "pmslatfr_el1", 0xC4CE, true, true }, // 627 + { "pmsidr_el1", 0xC4CF, true, true }, // 628 + { "errselr_el1", 0xC299, true, true }, // 629 + { "erxctlr_el1", 0xC2A1, true, true }, // 630 + { "erxstatus_el1", 0xC2A2, true, true }, // 631 + { "erxaddr_el1", 0xC2A3, true, true }, // 632 + { "erxmisc0_el1", 0xC2A8, true, true }, // 633 + { "erxmisc1_el1", 0xC2A9, true, true }, // 634 + { "disr_el1", 0xC609, true, true }, // 635 + { "vdisr_el2", 0xE609, true, true }, // 636 + { "vsesr_el2", 0xE293, true, true }, // 637 + { "apiakeylo_el1", 0xC108, true, true }, // 638 + { "apiakeyhi_el1", 0xC109, true, true }, // 639 + { "apibkeylo_el1", 0xC10A, true, true }, // 640 + { "apibkeyhi_el1", 0xC10B, true, true }, // 641 + { "apdakeylo_el1", 0xC110, true, true }, // 642 + { "apdakeyhi_el1", 0xC111, true, true }, // 643 + { "apdbkeylo_el1", 0xC112, true, true }, // 644 + { "apdbkeyhi_el1", 0xC113, true, true }, // 645 + { "apgakeylo_el1", 0xC118, true, true }, // 646 + { "apgakeyhi_el1", 0xC119, true, true }, // 647 + { "vstcr_el2", 0xE132, true, true }, // 648 + { "vsttbr_el2", 0xE130, true, true }, // 649 + { "cnthvs_tval_el2", 0xE720, true, true }, // 650 + { "cnthvs_cval_el2", 0xE722, true, true }, // 651 + { "cnthvs_ctl_el2", 0xE721, true, true }, // 652 + { "cnthps_tval_el2", 0xE728, true, true }, // 653 + { "cnthps_cval_el2", 0xE72A, true, true }, // 654 + { "cnthps_ctl_el2", 0xE729, true, true }, // 655 + { "sder32_el2", 0xE099, true, true }, // 656 + { "erxpfgctl_el1", 0xC2A5, true, true }, // 657 + { "erxpfgcdn_el1", 0xC2A6, true, true }, // 658 + { "erxts_el1", 0xC2AF, true, true }, // 659 + { "erxmisc2_el1", 0xC2AA, true, true }, // 660 + { "erxmisc3_el1", 0xC2AB, true, true }, // 661 + { "erxpfgf_el1", 0xC2A4, true, false }, // 662 + { "mpam0_el1", 0xC529, true, true }, // 663 + { "mpam1_el1", 0xC528, true, true }, // 664 + { "mpam2_el2", 0xE528, true, true }, // 665 + { "mpam3_el3", 0xF528, true, true }, // 666 + { "mpam1_el12", 0xED28, true, true }, // 667 + { "mpamhcr_el2", 0xE520, true, true }, // 668 + { "mpamvpmv_el2", 0xE521, true, true }, // 669 + { "mpamvpm0_el2", 0xE530, true, true }, // 670 + { "mpamvpm1_el2", 0xE531, true, true }, // 671 + { "mpamvpm2_el2", 0xE532, true, true }, // 672 + { "mpamvpm3_el2", 0xE533, true, true }, // 673 + { "mpamvpm4_el2", 0xE534, true, true }, // 674 + { "mpamvpm5_el2", 0xE535, true, true }, // 675 + { "mpamvpm6_el2", 0xE536, true, true }, // 676 + { "mpamvpm7_el2", 0xE537, true, true }, // 677 + { "mpamidr_el1", 0xC524, true, false }, // 678 + { "amcr_el0", 0xDE90, true, true }, // 679 + { "amcfgr_el0", 0xDE91, true, false }, // 680 + { "amcgcr_el0", 0xDE92, true, false }, // 681 + { "amuserenr_el0", 0xDE93, true, true }, // 682 + { "amcntenclr0_el0", 0xDE94, true, true }, // 683 + { "amcntenset0_el0", 0xDE95, true, true }, // 684 + { "amevcntr00_el0", 0xDEA0, true, true }, // 685 + { "amevcntr01_el0", 0xDEA1, true, true }, // 686 + { "amevcntr02_el0", 0xDEA2, true, true }, // 687 + { "amevcntr03_el0", 0xDEA3, true, true }, // 688 + { "amevtyper00_el0", 0xDEB0, true, false }, // 689 + { "amevtyper01_el0", 0xDEB1, true, false }, // 690 + { "amevtyper02_el0", 0xDEB2, true, false }, // 691 + { "amevtyper03_el0", 0xDEB3, true, false }, // 692 + { "amcntenclr1_el0", 0xDE98, true, true }, // 693 + { "amcntenset1_el0", 0xDE99, true, true }, // 694 + { "amevcntr10_el0", 0xDEE0, true, true }, // 695 + { "amevcntr11_el0", 0xDEE1, true, true }, // 696 + { "amevcntr12_el0", 0xDEE2, true, true }, // 697 + { "amevcntr13_el0", 0xDEE3, true, true }, // 698 + { "amevcntr14_el0", 0xDEE4, true, true }, // 699 + { "amevcntr15_el0", 0xDEE5, true, true }, // 700 + { "amevcntr16_el0", 0xDEE6, true, true }, // 701 + { "amevcntr17_el0", 0xDEE7, true, true }, // 702 + { "amevcntr18_el0", 0xDEE8, true, true }, // 703 + { "amevcntr19_el0", 0xDEE9, true, true }, // 704 + { "amevcntr110_el0", 0xDEEA, true, true }, // 705 + { "amevcntr111_el0", 0xDEEB, true, true }, // 706 + { "amevcntr112_el0", 0xDEEC, true, true }, // 707 + { "amevcntr113_el0", 0xDEED, true, true }, // 708 + { "amevcntr114_el0", 0xDEEE, true, true }, // 709 + { "amevcntr115_el0", 0xDEEF, true, true }, // 710 + { "amevtyper10_el0", 0xDEF0, true, true }, // 711 + { "amevtyper11_el0", 0xDEF1, true, true }, // 712 + { "amevtyper12_el0", 0xDEF2, true, true }, // 713 + { "amevtyper13_el0", 0xDEF3, true, true }, // 714 + { "amevtyper14_el0", 0xDEF4, true, true }, // 715 + { "amevtyper15_el0", 0xDEF5, true, true }, // 716 + { "amevtyper16_el0", 0xDEF6, true, true }, // 717 + { "amevtyper17_el0", 0xDEF7, true, true }, // 718 + { "amevtyper18_el0", 0xDEF8, true, true }, // 719 + { "amevtyper19_el0", 0xDEF9, true, true }, // 720 + { "amevtyper110_el0", 0xDEFA, true, true }, // 721 + { "amevtyper111_el0", 0xDEFB, true, true }, // 722 + { "amevtyper112_el0", 0xDEFC, true, true }, // 723 + { "amevtyper113_el0", 0xDEFD, true, true }, // 724 + { "amevtyper114_el0", 0xDEFE, true, true }, // 725 + { "amevtyper115_el0", 0xDEFF, true, true }, // 726 + { "trfcr_el1", 0xC091, true, true }, // 727 + { "trfcr_el2", 0xE091, true, true }, // 728 + { "trfcr_el12", 0xE891, true, true }, // 729 + { "dit", 0xDA15, true, true }, // 730 + { "vncr_el2", 0xE110, true, true }, // 731 + { "zcr_el1", 0xC090, true, true }, // 732 + { "zcr_el2", 0xE090, true, true }, // 733 + { "zcr_el3", 0xF090, true, true }, // 734 + { "zcr_el12", 0xE890, true, true }, // 735 + { "cpm_ioacc_ctl_el3", 0xFF90, true, true }, // 736 +}; + +const SysReg *lookupSysRegByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x8002, 111 }, + { 0x8004, 119 }, + { 0x8005, 135 }, + { 0x8006, 151 }, + { 0x8007, 167 }, + { 0x800C, 120 }, + { 0x800D, 136 }, + { 0x800E, 152 }, + { 0x800F, 168 }, + { 0x8010, 114 }, + { 0x8012, 115 }, + { 0x8014, 121 }, + { 0x8015, 137 }, + { 0x8016, 153 }, + { 0x8017, 169 }, + { 0x801A, 112 }, + { 0x801C, 122 }, + { 0x801D, 138 }, + { 0x801E, 154 }, + { 0x801F, 170 }, + { 0x8024, 123 }, + { 0x8025, 139 }, + { 0x8026, 155 }, + { 0x8027, 171 }, + { 0x802C, 124 }, + { 0x802D, 140 }, + { 0x802E, 156 }, + { 0x802F, 172 }, + { 0x8032, 117 }, + { 0x8034, 125 }, + { 0x8035, 141 }, + { 0x8036, 157 }, + { 0x8037, 173 }, + { 0x803C, 126 }, + { 0x803D, 142 }, + { 0x803E, 158 }, + { 0x803F, 174 }, + { 0x8044, 127 }, + { 0x8045, 143 }, + { 0x8046, 159 }, + { 0x8047, 175 }, + { 0x804C, 128 }, + { 0x804D, 144 }, + { 0x804E, 160 }, + { 0x804F, 176 }, + { 0x8054, 129 }, + { 0x8055, 145 }, + { 0x8056, 161 }, + { 0x8057, 177 }, + { 0x805C, 130 }, + { 0x805D, 146 }, + { 0x805E, 162 }, + { 0x805F, 178 }, + { 0x8064, 131 }, + { 0x8065, 147 }, + { 0x8066, 163 }, + { 0x8067, 179 }, + { 0x806C, 132 }, + { 0x806D, 148 }, + { 0x806E, 164 }, + { 0x806F, 180 }, + { 0x8074, 133 }, + { 0x8075, 149 }, + { 0x8076, 165 }, + { 0x8077, 181 }, + { 0x807C, 134 }, + { 0x807D, 150 }, + { 0x807E, 166 }, + { 0x807F, 182 }, + { 0x8080, 2 }, + { 0x8084, 101 }, + { 0x808C, 3 }, + { 0x809C, 184 }, + { 0x80A4, 185 }, + { 0x83C6, 186 }, + { 0x83CE, 187 }, + { 0x83F6, 4 }, + { 0x8801, 374 }, + { 0x8802, 376 }, + { 0x8804, 383 }, + { 0x8805, 389 }, + { 0x8806, 53 }, + { 0x8807, 401 }, + { 0x8808, 363 }, + { 0x8809, 375 }, + { 0x880A, 377 }, + { 0x880C, 384 }, + { 0x880D, 390 }, + { 0x880E, 54 }, + { 0x880F, 402 }, + { 0x8810, 364 }, + { 0x8812, 378 }, + { 0x8814, 385 }, + { 0x8815, 391 }, + { 0x8816, 55 }, + { 0x8817, 403 }, + { 0x8818, 52 }, + { 0x881A, 379 }, + { 0x881D, 392 }, + { 0x881E, 56 }, + { 0x881F, 404 }, + { 0x8820, 365 }, + { 0x8825, 393 }, + { 0x8826, 57 }, + { 0x8827, 405 }, + { 0x882D, 394 }, + { 0x882E, 58 }, + { 0x882F, 406 }, + { 0x8830, 366 }, + { 0x8834, 386 }, + { 0x8835, 395 }, + { 0x8837, 407 }, + { 0x883C, 387 }, + { 0x883D, 396 }, + { 0x883F, 408 }, + { 0x8840, 367 }, + { 0x8842, 380 }, + { 0x8844, 388 }, + { 0x8845, 397 }, + { 0x8847, 59 }, + { 0x8848, 368 }, + { 0x884A, 381 }, + { 0x884D, 398 }, + { 0x884F, 60 }, + { 0x8852, 382 }, + { 0x8855, 399 }, + { 0x8857, 61 }, + { 0x8858, 369 }, + { 0x885D, 400 }, + { 0x885F, 62 }, + { 0x8860, 370 }, + { 0x8867, 63 }, + { 0x8868, 371 }, + { 0x886F, 64 }, + { 0x8870, 372 }, + { 0x8877, 65 }, + { 0x8878, 373 }, + { 0x887F, 66 }, + { 0x8881, 423 }, + { 0x8882, 439 }, + { 0x8883, 455 }, + { 0x8884, 103 }, + { 0x8889, 424 }, + { 0x888A, 440 }, + { 0x888B, 456 }, + { 0x888C, 67 }, + { 0x8890, 409 }, + { 0x8891, 425 }, + { 0x8892, 441 }, + { 0x8893, 457 }, + { 0x8898, 410 }, + { 0x8899, 426 }, + { 0x889A, 442 }, + { 0x889B, 458 }, + { 0x88A0, 411 }, + { 0x88A1, 427 }, + { 0x88A2, 443 }, + { 0x88A3, 459 }, + { 0x88A4, 463 }, + { 0x88A8, 412 }, + { 0x88A9, 428 }, + { 0x88AA, 444 }, + { 0x88AB, 460 }, + { 0x88AC, 68 }, + { 0x88B0, 413 }, + { 0x88B1, 429 }, + { 0x88B2, 445 }, + { 0x88B3, 461 }, + { 0x88B8, 414 }, + { 0x88B9, 430 }, + { 0x88BA, 446 }, + { 0x88BB, 462 }, + { 0x88C0, 415 }, + { 0x88C1, 431 }, + { 0x88C2, 447 }, + { 0x88C8, 416 }, + { 0x88C9, 432 }, + { 0x88CA, 448 }, + { 0x88D0, 417 }, + { 0x88D1, 433 }, + { 0x88D2, 449 }, + { 0x88D8, 418 }, + { 0x88D9, 434 }, + { 0x88DA, 450 }, + { 0x88E0, 419 }, + { 0x88E1, 435 }, + { 0x88E2, 451 }, + { 0x88E8, 420 }, + { 0x88E9, 436 }, + { 0x88EA, 452 }, + { 0x88F0, 421 }, + { 0x88F1, 437 }, + { 0x88F2, 453 }, + { 0x88F8, 422 }, + { 0x88F9, 438 }, + { 0x88FA, 454 }, + { 0x8900, 464 }, + { 0x8901, 472 }, + { 0x8902, 480 }, + { 0x8903, 488 }, + { 0x8904, 496 }, + { 0x8905, 500 }, + { 0x8906, 504 }, + { 0x8907, 508 }, + { 0x8910, 465 }, + { 0x8911, 473 }, + { 0x8912, 481 }, + { 0x8913, 489 }, + { 0x8920, 466 }, + { 0x8921, 474 }, + { 0x8922, 482 }, + { 0x8923, 490 }, + { 0x8924, 497 }, + { 0x8925, 501 }, + { 0x8926, 505 }, + { 0x8927, 509 }, + { 0x8930, 467 }, + { 0x8931, 475 }, + { 0x8932, 483 }, + { 0x8933, 491 }, + { 0x8940, 468 }, + { 0x8941, 476 }, + { 0x8942, 484 }, + { 0x8943, 492 }, + { 0x8944, 498 }, + { 0x8945, 502 }, + { 0x8946, 506 }, + { 0x8947, 510 }, + { 0x8950, 469 }, + { 0x8951, 477 }, + { 0x8952, 485 }, + { 0x8953, 493 }, + { 0x8960, 470 }, + { 0x8961, 478 }, + { 0x8962, 486 }, + { 0x8963, 494 }, + { 0x8964, 499 }, + { 0x8965, 503 }, + { 0x8966, 507 }, + { 0x8967, 511 }, + { 0x8970, 471 }, + { 0x8971, 479 }, + { 0x8972, 487 }, + { 0x8973, 495 }, + { 0x8980, 512 }, + { 0x8981, 520 }, + { 0x8982, 528 }, + { 0x898A, 529 }, + { 0x8990, 513 }, + { 0x8991, 521 }, + { 0x8992, 530 }, + { 0x899A, 531 }, + { 0x89A0, 514 }, + { 0x89A1, 522 }, + { 0x89B0, 515 }, + { 0x89B1, 523 }, + { 0x89C0, 516 }, + { 0x89C1, 524 }, + { 0x89D0, 517 }, + { 0x89D1, 525 }, + { 0x89E0, 518 }, + { 0x89E1, 526 }, + { 0x89F0, 519 }, + { 0x89F1, 527 }, + { 0x8B84, 532 }, + { 0x8B97, 74 }, + { 0x8B9F, 75 }, + { 0x8BA7, 76 }, + { 0x8BAF, 77 }, + { 0x8BB7, 78 }, + { 0x8BBF, 79 }, + { 0x8BC6, 533 }, + { 0x8BC7, 80 }, + { 0x8BCE, 534 }, + { 0x8BCF, 81 }, + { 0x8BD6, 69 }, + { 0x8BD7, 82 }, + { 0x8BDE, 70 }, + { 0x8BDF, 83 }, + { 0x8BE6, 104 }, + { 0x8BE7, 84 }, + { 0x8BEE, 71 }, + { 0x8BEF, 85 }, + { 0x8BF6, 72 }, + { 0x8BF7, 86 }, + { 0x8BFE, 73 }, + { 0x8BFF, 87 }, + { 0x9000, 113 }, + { 0x9080, 183 }, + { 0x9808, 0 }, + { 0x9820, 116 }, + { 0x9828, 1 }, + { 0x9828, 100 }, + { 0xA038, 118 }, + { 0xC000, 7 }, + { 0xC005, 12 }, + { 0xC006, 13 }, + { 0xC008, 16 }, + { 0xC009, 17 }, + { 0xC00A, 18 }, + { 0xC00B, 19 }, + { 0xC00C, 20 }, + { 0xC00D, 21 }, + { 0xC00E, 22 }, + { 0xC00F, 23 }, + { 0xC010, 24 }, + { 0xC011, 25 }, + { 0xC012, 26 }, + { 0xC013, 27 }, + { 0xC014, 28 }, + { 0xC015, 29 }, + { 0xC016, 51 }, + { 0xC017, 30 }, + { 0xC018, 42 }, + { 0xC019, 43 }, + { 0xC01A, 44 }, + { 0xC020, 31 }, + { 0xC021, 32 }, + { 0xC024, 96 }, + { 0xC028, 33 }, + { 0xC029, 34 }, + { 0xC02C, 35 }, + { 0xC02D, 36 }, + { 0xC030, 37 }, + { 0xC031, 38 }, + { 0xC038, 39 }, + { 0xC039, 40 }, + { 0xC03A, 41 }, + { 0xC080, 192 }, + { 0xC081, 195 }, + { 0xC082, 191 }, + { 0xC090, 732 }, + { 0xC091, 727 }, + { 0xC100, 207 }, + { 0xC101, 210 }, + { 0xC102, 211 }, + { 0xC108, 638 }, + { 0xC109, 639 }, + { 0xC10A, 640 }, + { 0xC10B, 641 }, + { 0xC110, 642 }, + { 0xC111, 643 }, + { 0xC112, 644 }, + { 0xC113, 645 }, + { 0xC118, 646 }, + { 0xC119, 647 }, + { 0xC200, 217 }, + { 0xC201, 220 }, + { 0xC208, 223 }, + { 0xC210, 226 }, + { 0xC212, 229 }, + { 0xC213, 583 }, + { 0xC214, 615 }, + { 0xC230, 537 }, + { 0xC288, 239 }, + { 0xC289, 242 }, + { 0xC290, 245 }, + { 0xC298, 98 }, + { 0xC299, 629 }, + { 0xC2A0, 99 }, + { 0xC2A1, 630 }, + { 0xC2A2, 631 }, + { 0xC2A3, 632 }, + { 0xC2A4, 662 }, + { 0xC2A5, 657 }, + { 0xC2A6, 658 }, + { 0xC2A8, 633 }, + { 0xC2A9, 634 }, + { 0xC2AA, 660 }, + { 0xC2AB, 661 }, + { 0xC2AF, 659 }, + { 0xC300, 249 }, + { 0xC3A0, 253 }, + { 0xC4C8, 622 }, + { 0xC4CA, 623 }, + { 0xC4CB, 624 }, + { 0xC4CC, 625 }, + { 0xC4CD, 626 }, + { 0xC4CE, 627 }, + { 0xC4CF, 628 }, + { 0xC4D0, 616 }, + { 0xC4D1, 617 }, + { 0xC4D3, 618 }, + { 0xC4D7, 619 }, + { 0xC4F1, 263 }, + { 0xC4F2, 264 }, + { 0xC510, 266 }, + { 0xC518, 269 }, + { 0xC520, 584 }, + { 0xC521, 585 }, + { 0xC522, 586 }, + { 0xC523, 587 }, + { 0xC524, 678 }, + { 0xC527, 97 }, + { 0xC528, 664 }, + { 0xC529, 663 }, + { 0xC600, 272 }, + { 0xC601, 45 }, + { 0xC602, 275 }, + { 0xC608, 48 }, + { 0xC609, 635 }, + { 0xC640, 89 }, + { 0xC641, 106 }, + { 0xC642, 91 }, + { 0xC643, 536 }, + { 0xC644, 547 }, + { 0xC645, 548 }, + { 0xC646, 549 }, + { 0xC647, 550 }, + { 0xC648, 551 }, + { 0xC649, 552 }, + { 0xC64A, 553 }, + { 0xC64B, 554 }, + { 0xC659, 107 }, + { 0xC65B, 92 }, + { 0xC65D, 108 }, + { 0xC65E, 109 }, + { 0xC65F, 110 }, + { 0xC660, 88 }, + { 0xC661, 105 }, + { 0xC662, 90 }, + { 0xC663, 535 }, + { 0xC664, 538 }, + { 0xC665, 540 }, + { 0xC666, 543 }, + { 0xC667, 544 }, + { 0xC668, 546 }, + { 0xC681, 278 }, + { 0xC684, 283 }, + { 0xC708, 286 }, + { 0xC800, 8 }, + { 0xC801, 10 }, + { 0xC802, 9 }, + { 0xC807, 14 }, + { 0xD000, 188 }, + { 0xD801, 11 }, + { 0xD807, 15 }, + { 0xDA10, 227 }, + { 0xDA11, 228 }, + { 0xDA15, 730 }, + { 0xDA20, 234 }, + { 0xDA21, 235 }, + { 0xDA28, 236 }, + { 0xDA29, 237 }, + { 0xDCE0, 254 }, + { 0xDCE1, 255 }, + { 0xDCE2, 256 }, + { 0xDCE3, 257 }, + { 0xDCE4, 102 }, + { 0xDCE5, 258 }, + { 0xDCE6, 5 }, + { 0xDCE7, 6 }, + { 0xDCE8, 259 }, + { 0xDCE9, 260 }, + { 0xDCEA, 261 }, + { 0xDCF0, 262 }, + { 0xDCF3, 265 }, + { 0xDE82, 279 }, + { 0xDE83, 282 }, + { 0xDE90, 679 }, + { 0xDE91, 680 }, + { 0xDE92, 681 }, + { 0xDE93, 682 }, + { 0xDE94, 683 }, + { 0xDE95, 684 }, + { 0xDE98, 693 }, + { 0xDE99, 694 }, + { 0xDEA0, 685 }, + { 0xDEA1, 686 }, + { 0xDEA2, 687 }, + { 0xDEA3, 688 }, + { 0xDEB0, 689 }, + { 0xDEB1, 690 }, + { 0xDEB2, 691 }, + { 0xDEB3, 692 }, + { 0xDEE0, 695 }, + { 0xDEE1, 696 }, + { 0xDEE2, 697 }, + { 0xDEE3, 698 }, + { 0xDEE4, 699 }, + { 0xDEE5, 700 }, + { 0xDEE6, 701 }, + { 0xDEE7, 702 }, + { 0xDEE8, 703 }, + { 0xDEE9, 704 }, + { 0xDEEA, 705 }, + { 0xDEEB, 706 }, + { 0xDEEC, 707 }, + { 0xDEED, 708 }, + { 0xDEEE, 709 }, + { 0xDEEF, 710 }, + { 0xDEF0, 711 }, + { 0xDEF1, 712 }, + { 0xDEF2, 713 }, + { 0xDEF3, 714 }, + { 0xDEF4, 715 }, + { 0xDEF5, 716 }, + { 0xDEF6, 717 }, + { 0xDEF7, 718 }, + { 0xDEF8, 719 }, + { 0xDEF9, 720 }, + { 0xDEFA, 721 }, + { 0xDEFB, 722 }, + { 0xDEFC, 723 }, + { 0xDEFD, 724 }, + { 0xDEFE, 725 }, + { 0xDEFF, 726 }, + { 0xDF00, 284 }, + { 0xDF01, 49 }, + { 0xDF02, 50 }, + { 0xDF10, 288 }, + { 0xDF11, 291 }, + { 0xDF12, 294 }, + { 0xDF18, 297 }, + { 0xDF19, 298 }, + { 0xDF1A, 299 }, + { 0xDF40, 300 }, + { 0xDF41, 301 }, + { 0xDF42, 302 }, + { 0xDF43, 303 }, + { 0xDF44, 304 }, + { 0xDF45, 305 }, + { 0xDF46, 306 }, + { 0xDF47, 307 }, + { 0xDF48, 308 }, + { 0xDF49, 309 }, + { 0xDF4A, 310 }, + { 0xDF4B, 311 }, + { 0xDF4C, 312 }, + { 0xDF4D, 313 }, + { 0xDF4E, 314 }, + { 0xDF4F, 315 }, + { 0xDF50, 316 }, + { 0xDF51, 317 }, + { 0xDF52, 318 }, + { 0xDF53, 319 }, + { 0xDF54, 320 }, + { 0xDF55, 321 }, + { 0xDF56, 322 }, + { 0xDF57, 323 }, + { 0xDF58, 324 }, + { 0xDF59, 325 }, + { 0xDF5A, 326 }, + { 0xDF5B, 327 }, + { 0xDF5C, 328 }, + { 0xDF5D, 329 }, + { 0xDF5E, 330 }, + { 0xDF60, 332 }, + { 0xDF61, 333 }, + { 0xDF62, 334 }, + { 0xDF63, 335 }, + { 0xDF64, 336 }, + { 0xDF65, 337 }, + { 0xDF66, 338 }, + { 0xDF67, 339 }, + { 0xDF68, 340 }, + { 0xDF69, 341 }, + { 0xDF6A, 342 }, + { 0xDF6B, 343 }, + { 0xDF6C, 344 }, + { 0xDF6D, 345 }, + { 0xDF6E, 346 }, + { 0xDF6F, 347 }, + { 0xDF70, 348 }, + { 0xDF71, 349 }, + { 0xDF72, 350 }, + { 0xDF73, 351 }, + { 0xDF74, 352 }, + { 0xDF75, 353 }, + { 0xDF76, 354 }, + { 0xDF77, 355 }, + { 0xDF78, 356 }, + { 0xDF79, 357 }, + { 0xDF7A, 358 }, + { 0xDF7B, 359 }, + { 0xDF7C, 360 }, + { 0xDF7D, 361 }, + { 0xDF7E, 362 }, + { 0xDF7F, 331 }, + { 0xE000, 189 }, + { 0xE005, 190 }, + { 0xE080, 193 }, + { 0xE081, 196 }, + { 0xE088, 198 }, + { 0xE089, 200 }, + { 0xE08A, 202 }, + { 0xE08B, 204 }, + { 0xE08F, 205 }, + { 0xE090, 733 }, + { 0xE091, 728 }, + { 0xE099, 656 }, + { 0xE100, 208 }, + { 0xE101, 588 }, + { 0xE102, 212 }, + { 0xE108, 214 }, + { 0xE10A, 215 }, + { 0xE110, 731 }, + { 0xE130, 649 }, + { 0xE132, 648 }, + { 0xE180, 216 }, + { 0xE200, 218 }, + { 0xE201, 221 }, + { 0xE208, 224 }, + { 0xE218, 230 }, + { 0xE219, 231 }, + { 0xE21A, 232 }, + { 0xE21B, 233 }, + { 0xE281, 238 }, + { 0xE288, 240 }, + { 0xE289, 243 }, + { 0xE290, 246 }, + { 0xE293, 637 }, + { 0xE298, 248 }, + { 0xE300, 250 }, + { 0xE304, 252 }, + { 0xE4C8, 620 }, + { 0xE510, 267 }, + { 0xE518, 270 }, + { 0xE520, 668 }, + { 0xE521, 669 }, + { 0xE528, 665 }, + { 0xE530, 670 }, + { 0xE531, 671 }, + { 0xE532, 672 }, + { 0xE533, 673 }, + { 0xE534, 674 }, + { 0xE535, 675 }, + { 0xE536, 676 }, + { 0xE537, 677 }, + { 0xE600, 273 }, + { 0xE601, 46 }, + { 0xE602, 276 }, + { 0xE609, 636 }, + { 0xE640, 555 }, + { 0xE641, 556 }, + { 0xE642, 557 }, + { 0xE643, 558 }, + { 0xE648, 559 }, + { 0xE649, 560 }, + { 0xE64A, 561 }, + { 0xE64B, 562 }, + { 0xE64C, 566 }, + { 0xE64D, 541 }, + { 0xE658, 563 }, + { 0xE659, 93 }, + { 0xE65A, 564 }, + { 0xE65B, 94 }, + { 0xE65D, 95 }, + { 0xE65F, 565 }, + { 0xE660, 567 }, + { 0xE661, 568 }, + { 0xE662, 569 }, + { 0xE663, 570 }, + { 0xE664, 571 }, + { 0xE665, 572 }, + { 0xE666, 573 }, + { 0xE667, 574 }, + { 0xE668, 575 }, + { 0xE669, 576 }, + { 0xE66A, 577 }, + { 0xE66B, 578 }, + { 0xE66C, 579 }, + { 0xE66D, 580 }, + { 0xE66E, 581 }, + { 0xE66F, 582 }, + { 0xE681, 589 }, + { 0xE682, 280 }, + { 0xE703, 285 }, + { 0xE708, 287 }, + { 0xE710, 289 }, + { 0xE711, 292 }, + { 0xE712, 295 }, + { 0xE718, 590 }, + { 0xE719, 592 }, + { 0xE71A, 591 }, + { 0xE720, 650 }, + { 0xE721, 652 }, + { 0xE722, 651 }, + { 0xE728, 653 }, + { 0xE729, 655 }, + { 0xE72A, 654 }, + { 0xE880, 593 }, + { 0xE882, 594 }, + { 0xE890, 735 }, + { 0xE891, 729 }, + { 0xE900, 595 }, + { 0xE901, 596 }, + { 0xE902, 597 }, + { 0xEA00, 613 }, + { 0xEA01, 614 }, + { 0xEA88, 598 }, + { 0xEA89, 599 }, + { 0xEA90, 600 }, + { 0xEB00, 601 }, + { 0xECC8, 621 }, + { 0xED10, 602 }, + { 0xED18, 603 }, + { 0xED28, 667 }, + { 0xEE00, 604 }, + { 0xEE81, 605 }, + { 0xEF08, 606 }, + { 0xEF10, 607 }, + { 0xEF11, 608 }, + { 0xEF12, 609 }, + { 0xEF18, 610 }, + { 0xEF19, 611 }, + { 0xEF1A, 612 }, + { 0xF080, 194 }, + { 0xF081, 197 }, + { 0xF088, 199 }, + { 0xF089, 201 }, + { 0xF08A, 203 }, + { 0xF090, 734 }, + { 0xF099, 206 }, + { 0xF100, 209 }, + { 0xF102, 213 }, + { 0xF200, 219 }, + { 0xF201, 222 }, + { 0xF208, 225 }, + { 0xF288, 241 }, + { 0xF289, 244 }, + { 0xF290, 247 }, + { 0xF300, 251 }, + { 0xF510, 268 }, + { 0xF518, 271 }, + { 0xF528, 666 }, + { 0xF600, 274 }, + { 0xF601, 47 }, + { 0xF602, 277 }, + { 0xF664, 539 }, + { 0xF665, 542 }, + { 0xF667, 545 }, + { 0xF682, 281 }, + { 0xFF10, 290 }, + { 0xFF11, 293 }, + { 0xFF12, 296 }, + { 0xFF90, 736 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &SysRegsList[Index[i].index]; +} + +static const PState PStatesList[] = { + { "spsel", 0x5 }, // 0 + { "daifset", 0x1E }, // 1 + { "daifclr", 0x1F }, // 2 + { "pan", 0x4 }, // 3 + { "uao", 0x3 }, // 4 + { "dit", 0x1A }, // 5 +}; + +const PState *lookupPStateByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x3, 4 }, + { 0x4, 3 }, + { 0x5, 0 }, + { 0x1A, 5 }, + { 0x1E, 1 }, + { 0x1F, 2 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &PStatesList[Index[i].index]; +} + +static const SVEPREDPAT SVEPREDPATsList[] = { + { "pow2", 0x0 }, // 0 + { "vl1", 0x1 }, // 1 + { "vl2", 0x2 }, // 2 + { "vl3", 0x3 }, // 3 + { "vl4", 0x4 }, // 4 + { "vl5", 0x5 }, // 5 + { "vl6", 0x6 }, // 6 + { "vl7", 0x7 }, // 7 + { "vl8", 0x8 }, // 8 + { "vl16", 0x9 }, // 9 + { "vl32", 0xa }, // 10 + { "vl64", 0xb }, // 11 + { "vl128", 0xc }, // 12 + { "vl256", 0xd }, // 13 + { "mul4", 0x1d }, // 14 + { "mul3", 0x1e }, // 15 + { "all", 0x1f }, // 16 +}; + +const SVEPREDPAT *lookupSVEPREDPATByEncoding(uint16_t Encoding) +{ + unsigned int i; + static const struct IndexType Index[] = { + { 0x0, 0 }, + { 0x1, 1 }, + { 0x2, 2 }, + { 0x3, 3 }, + { 0x4, 4 }, + { 0x5, 5 }, + { 0x6, 6 }, + { 0x7, 7 }, + { 0x8, 8 }, + { 0x9, 9 }, + { 0xA, 10 }, + { 0xB, 11 }, + { 0xC, 12 }, + { 0xD, 13 }, + { 0x1D, 14 }, + { 0x1E, 15 }, + { 0x1F, 16 }, + }; + + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); + if (i == -1) + return NULL; + else + return &SVEPREDPATsList[Index[i].index]; +} + +static const ExactFPImm ExactFPImmsList[] = { + { "zero", 0x0, "0.0" }, // 0 + { "half", 0x1, "0.5" }, // 1 + { "one", 0x2, "1.0" }, // 2 + { "two", 0x3, "2.0" }, // 3 +}; + +const ExactFPImm *lookupExactFPImmByEnum(uint16_t Encoding) +{ + static const struct IndexType Index[] = { + { 0x0, 0 }, + { 0x1, 1 }, + { 0x2, 2 }, + { 0x3, 3 }, + }; + + if (Encoding >= ARR_SIZE(TSBsList)) + return NULL; + else + return &ExactFPImmsList[Index[Encoding].index]; +} + diff --git a/arch/AArch64/AArch64GenSystemOperands_enum.inc b/arch/AArch64/AArch64GenSystemOperands_enum.inc new file mode 100644 index 000000000..400022637 --- /dev/null +++ b/arch/AArch64/AArch64GenSystemOperands_enum.inc @@ -0,0 +1,19 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* By Nguyen Anh Quynh , 2013-2019 */ + +enum PStateValues { + AArch64PState_SPSel = 5, + AArch64PState_DAIFSet = 30, + AArch64PState_DAIFClr = 31, + AArch64PState_PAN = 4, + AArch64PState_UAO = 3, + AArch64PState_DIT = 26, +}; + +enum ExactFPImmValues { + AArch64ExactFPImm_zero = 0, + AArch64ExactFPImm_half = 1, + AArch64ExactFPImm_one = 2, + AArch64ExactFPImm_two = 3, +}; + diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 0fd915206..1b9955ca4 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -21,6 +21,7 @@ #include #include "AArch64InstPrinter.h" +#include "AArch64Disassembler.h" #include "AArch64BaseInfo.h" #include "../../utils.h" #include "../../MCInst.h" @@ -37,13 +38,18 @@ #define GET_INSTRINFO_ENUM #include "AArch64GenInstrInfo.inc" +#include "AArch64GenSubtargetInfo.inc" -static const char *getRegisterName(unsigned RegNo, int AltIdx); + +static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); static void printOperand(MCInst *MI, unsigned OpNum, SStream *O); static bool printSysAlias(MCInst *MI, SStream *O); -static char *printAliasInstr(MCInst *MI, SStream *OS, void *info); -static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI); +static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI); +static void printInstruction(MCInst *MI, SStream *O); static void printShifter(MCInst *MI, unsigned OpNum, SStream *O); +static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, SStream *OS); + static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int index) { @@ -59,6 +65,15 @@ static cs_ac_type get_op_access(cs_struct *h, unsigned int id, unsigned int inde #endif } +static void op_addImm(MCInst *MI, int v) +{ + if (MI->csh->detail) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = v; + MI->flat_insn->detail->arm64.op_count++; + } +} + static void set_mem_access(MCInst *MI, bool status) { MI->csh->doing_mem = status; @@ -83,18 +98,11 @@ static void set_mem_access(MCInst *MI, bool status) } } -void AArch64_printRegName(SStream *O, unsigned RegNo) -{ - // This is for .cfi directives. - SStream_concat0(O, getRegisterName(RegNo, AArch64_NoRegAltName)); -} - void AArch64_printInst(MCInst *MI, SStream *O, void *Info) { // Check for special encodings and print the canonical alias instead. unsigned Opcode = MCInst_getOpcode(MI); - int LSB; - int Width; + int LSB, Width; char *mnem; if (Opcode == AArch64_SYSxt && printSysAlias(MI, O)) @@ -103,32 +111,35 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) // SBFM/UBFM should print to a nicer aliased form if possible. if (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri || Opcode == AArch64_UBFMXri || Opcode == AArch64_UBFMWri) { + bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); + bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); + MCOperand *Op0 = MCInst_getOperand(MI, 0); MCOperand *Op1 = MCInst_getOperand(MI, 1); MCOperand *Op2 = MCInst_getOperand(MI, 2); MCOperand *Op3 = MCInst_getOperand(MI, 3); - bool IsSigned = (Opcode == AArch64_SBFMXri || Opcode == AArch64_SBFMWri); - bool Is64Bit = (Opcode == AArch64_SBFMXri || Opcode == AArch64_UBFMXri); - if (MCOperand_isImm(Op2) && MCOperand_getImm(Op2) == 0 && MCOperand_isImm(Op3)) { const char *AsmMnemonic = NULL; switch (MCOperand_getImm(Op3)) { default: break; + case 7: if (IsSigned) AsmMnemonic = "sxtb"; else if (!Is64Bit) AsmMnemonic = "uxtb"; break; + case 15: if (IsSigned) AsmMnemonic = "sxth"; else if (!Is64Bit) AsmMnemonic = "uxth"; break; + case 31: // *xtw is only valid for signed 64-bit operations. if (Is64Bit && IsSigned) @@ -243,8 +254,11 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfiz" : "ubfiz"), getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + printInt32Bang(O, (int)((Is64Bit ? 64 : 32) - MCOperand_getImm(Op2))); + SStream_concat0(O, ", "); + printInt32Bang(O, (int)MCOperand_getImm(Op3) + 1); MCInst_setOpcodePub(MI, AArch64_map_insn(IsSigned ? "sbfiz" : "ubfiz")); @@ -292,6 +306,7 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) SStream_concat(O, "%s\t%s, %s, ", (IsSigned ? "sbfx" : "ubfx"), getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op1), AArch64_NoRegAltName)); + printInt32Bang(O, (int)MCOperand_getImm(Op2)); SStream_concat0(O, ", "); printInt32Bang(O, (int)MCOperand_getImm(Op3) - (int)MCOperand_getImm(Op2) + 1); @@ -343,8 +358,53 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) int ImmR = (int)MCOperand_getImm(MCInst_getOperand(MI, 3)); int ImmS = (int)MCOperand_getImm(MCInst_getOperand(MI, 4)); - // BFI alias - if (ImmS < ImmR) { + if ((MCOperand_getReg(Op2) == AArch64_WZR || MCOperand_getReg(Op2) == AArch64_XZR) && + (ImmR == 0 || ImmS < ImmR)) { + // BFC takes precedence over its entire range, sligtly differently to BFI. + int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; + int LSB = (BitWidth - ImmR) % BitWidth; + int Width = ImmS + 1; + + SStream_concat(O, "bfc\t%s, ", + getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName)); + + printInt32Bang(O, LSB); + SStream_concat0(O, ", "); + printInt32Bang(O, Width); + MCInst_setOpcodePub(MI, AArch64_map_insn("bfc")); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(Op0); + MI->flat_insn->detail->arm64.op_count++; + +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = LSB; + MI->flat_insn->detail->arm64.op_count++; +#ifndef CAPSTONE_DIET + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Width; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } else if (ImmS < ImmR) { + // BFI alias int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; LSB = (BitWidth - ImmR) % BitWidth; Width = ImmS + 1; @@ -352,9 +412,11 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) SStream_concat(O, "bfi\t%s, %s, ", getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); + printInt32Bang(O, LSB); SStream_concat0(O, ", "); printInt32Bang(O, Width); + MCInst_setOpcodePub(MI, AArch64_map_insn("bfi")); if (MI->csh->detail) { @@ -402,9 +464,11 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) SStream_concat(O, "bfxil\t%s, %s, ", getRegisterName(MCOperand_getReg(Op0), AArch64_NoRegAltName), getRegisterName(MCOperand_getReg(Op2), AArch64_NoRegAltName)); + printInt32Bang(O, LSB); SStream_concat0(O, ", "); printInt32Bang(O, Width); + MCInst_setOpcodePub(MI, AArch64_map_insn("bfxil")); if (MI->csh->detail) { @@ -446,12 +510,142 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info) return; } - mnem = printAliasInstr(MI, O, Info); + // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their + // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 > + // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction + // that can represent the move is the MOV alias, and the rest get printed + // normally. + if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { + int RegWidth = Opcode == AArch64_MOVZXi ? 64 : 32; + int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); + uint64_t Value = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift; + + if (isMOVZMovAlias(Value, Shift, + Opcode == AArch64_MOVZXi ? 64 : 32)) { + SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); + + printInt64Bang(O, SignExtend64(Value, RegWidth)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = RegWidth; + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + + return; + } + } + + if ((Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) && + MCOperand_isImm(MCInst_getOperand(MI, 1)) && MCOperand_isImm(MCInst_getOperand(MI, 2))) { + int RegWidth = Opcode == AArch64_MOVNXi ? 64 : 32; + int Shift = MCOperand_getImm(MCInst_getOperand(MI, 2)); + uint64_t Value = ~((uint64_t)MCOperand_getImm(MCInst_getOperand(MI, 1)) << Shift); + + if (RegWidth == 32) + Value = Value & 0xffffffff; + + if (AArch64_AM_isMOVNMovAlias(Value, Shift, RegWidth)) { + SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); + + printInt64Bang(O, SignExtend64(Value, RegWidth)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = RegWidth; + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + + return; + } + } + + if ((Opcode == AArch64_ORRXri || Opcode == AArch64_ORRWri) && + (MCOperand_getReg(MCInst_getOperand(MI, 0)) == AArch64_XZR || + MCOperand_getReg(MCInst_getOperand(MI, 1)) == AArch64_WZR) && + MCOperand_isImm(MCInst_getOperand(MI, 2))) { + int RegWidth = Opcode == AArch64_ORRXri ? 64 : 32; + uint64_t Value = AArch64_AM_decodeLogicalImmediate( + MCOperand_getImm(MCInst_getOperand(MI, 2)), RegWidth); + if (!AArch64_AM_isAnyMOVWMovAlias(Value, RegWidth)) { + SStream_concat(O, "mov\t%s, ", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 0)), AArch64_NoRegAltName)); + + printInt64Bang(O, SignExtend64(Value, RegWidth)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0)); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = RegWidth; + MI->flat_insn->detail->arm64.op_count++; + } + + MCInst_setOpcodePub(MI, AArch64_map_insn("mov")); + + return; + } + } + + // Instruction TSB is specified as a one operand instruction, but 'csync' is + // not encoded, so for printing it is treated as a special case here: + if (Opcode == AArch64_TSB) { + SStream_concat0(O, "tsb\tcsync"); + MCInst_setOpcodePub(MI, AArch64_map_insn("tsb")); + return; + } + + mnem = printAliasInstr(MI, O, (MCRegisterInfo *)Info); if (mnem) { MCInst_setOpcodePub(MI, AArch64_map_insn(mnem)); cs_mem_free(mnem); + + // printf("opcode = %u\n", MCInst_getOpcode(MI)); + switch(MCInst_getOpcode(MI)) { + default: break; + case AArch64_UMOVvi64: + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1D); + break; + case AArch64_UMOVvi32: + arm64_op_addVectorArrSpecifier(MI, ARM64_VAS_1S); + break; + } + } else { - printInstruction(MI, O, Info); + MI->MRI = Info; + printInstruction(MI, O); } } @@ -460,7 +654,10 @@ static bool printSysAlias(MCInst *MI, SStream *O) // unsigned Opcode = MCInst_getOpcode(MI); //assert(Opcode == AArch64_SYSxt && "Invalid opcode for SYS alias!"); - const char *Asm = NULL; + const char *Ins; + uint16_t Encoding; + bool NeedsReg; + char Name[64]; MCOperand *Op1 = MCInst_getOperand(MI, 0); MCOperand *Cn = MCInst_getOperand(MI, 1); MCOperand *Cm = MCInst_getOperand(MI, 2); @@ -470,267 +667,95 @@ static bool printSysAlias(MCInst *MI, SStream *O) unsigned CnVal = (unsigned)MCOperand_getImm(Cn); unsigned CmVal = (unsigned)MCOperand_getImm(Cm); unsigned Op2Val = (unsigned)MCOperand_getImm(Op2); - unsigned insn_id = ARM64_INS_INVALID; - unsigned op_ic = 0, op_dc = 0, op_at = 0, op_tlbi = 0; + + Encoding = Op2Val; + Encoding |= CmVal << 3; + Encoding |= CnVal << 7; + Encoding |= Op1Val << 11; if (CnVal == 7) { switch (CmVal) { default: - break; + return false; - // IC aliases - case 1: - if (Op1Val == 0 && Op2Val == 0) { - Asm = "ic\tialluis"; - insn_id = ARM64_INS_IC; - op_ic = ARM64_IC_IALLUIS; - } - break; - case 5: - if (Op1Val == 0 && Op2Val == 0) { - Asm = "ic\tiallu"; - insn_id = ARM64_INS_IC; - op_ic = ARM64_IC_IALLU; - } else if (Op1Val == 3 && Op2Val == 1) { - Asm = "ic\tivau"; - insn_id = ARM64_INS_IC; - op_ic = ARM64_IC_IVAU; - } - break; + // IC aliases + case 1: case 5: { + const IC *IC = lookupICByEncoding(Encoding); + // if (!IC || !IC->haveFeatures(STI.getFeatureBits())) + if (!IC) + return false; - // DC aliases - case 4: - if (Op1Val == 3 && Op2Val == 1) { - Asm = "dc\tzva"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_ZVA; - } - break; - case 6: - if (Op1Val == 0 && Op2Val == 1) { - Asm = "dc\tivac"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_IVAC; - } - if (Op1Val == 0 && Op2Val == 2) { - Asm = "dc\tisw"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_ISW; - } - break; - case 10: - if (Op1Val == 3 && Op2Val == 1) { - Asm = "dc\tcvac"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_CVAC; - } else if (Op1Val == 0 && Op2Val == 2) { - Asm = "dc\tcsw"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_CSW; - } - break; - case 11: - if (Op1Val == 3 && Op2Val == 1) { - Asm = "dc\tcvau"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_CVAU; - } - break; - case 14: - if (Op1Val == 3 && Op2Val == 1) { - Asm = "dc\tcivac"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_CIVAC; - } else if (Op1Val == 0 && Op2Val == 2) { - Asm = "dc\tcisw"; - insn_id = ARM64_INS_DC; - op_dc = ARM64_DC_CISW; - } - break; + NeedsReg = IC->NeedsReg; + Ins = "ic"; + strncpy(Name, IC->Name, sizeof(Name) - 1); + } + break; - // AT aliases - case 8: - switch (Op1Val) { - default: - break; - case 0: - switch (Op2Val) { - default: - break; - case 0: Asm = "at\ts1e1r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1R; break; - case 1: Asm = "at\ts1e1w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1W; break; - case 2: Asm = "at\ts1e0r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0R; break; - case 3: Asm = "at\ts1e0w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0W; break; - } - break; - case 4: - switch (Op2Val) { - default: - break; - case 0: Asm = "at\ts1e2r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E2R; break; - case 1: Asm = "at\ts1e2w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E2W; break; - case 4: Asm = "at\ts12e1r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1R; break; - case 5: Asm = "at\ts12e1w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E1W; break; - case 6: Asm = "at\ts12e0r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0R; break; - case 7: Asm = "at\ts12e0w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E0W; break; - } - break; - case 6: - switch (Op2Val) { - default: - break; - case 0: Asm = "at\ts1e3r"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E3R; break; - case 1: Asm = "at\ts1e3w"; insn_id = ARM64_INS_AT; op_at = ARM64_AT_S1E3W; break; - } - break; - } - break; + // DC aliases + case 4: case 6: case 10: case 11: case 12: case 14: { + const DC *DC = lookupDCByEncoding(Encoding); + // if (!DC || !DC->haveFeatures(STI.getFeatureBits())) + if (!DC) + return false; + + NeedsReg = true; + Ins = "dc"; + strncpy(Name, DC->Name, sizeof(Name) - 1); + } + break; + + // AT aliases + case 8: case 9: { + const AT *AT = lookupATByEncoding(Encoding); + // if (!AT || !AT->haveFeatures(STI.getFeatureBits())) + if (!AT) + return false; + + NeedsReg = true; + Ins = "at"; + strncpy(Name, AT->Name, sizeof(Name) - 1); + } + break; } } else if (CnVal == 8) { // TLBI aliases - switch (CmVal) { - default: - break; - case 3: - switch (Op1Val) { - default: - break; - case 0: - switch (Op2Val) { - default: - break; - case 0: Asm = "tlbi\tvmalle1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLE1IS; break; - case 1: Asm = "tlbi\tvae1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE1IS; break; - case 2: Asm = "tlbi\taside1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ASIDE1IS; break; - case 3: Asm = "tlbi\tvaae1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAAE1IS; break; - case 5: Asm = "tlbi\tvale1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE1IS; break; - case 7: Asm = "tlbi\tvaale1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAALE1IS; break; - } - break; - case 4: - switch (Op2Val) { - default: - break; - case 0: Asm = "tlbi\talle2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE2IS; break; - case 1: Asm = "tlbi\tvae2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE2IS; break; - case 4: Asm = "tlbi\talle1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE1IS; break; - case 5: Asm = "tlbi\tvale2is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE2IS; break; - case 6: Asm = "tlbi\tvmalls12e1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLS12E1IS; break; - } - break; - case 6: - switch (Op2Val) { - default: - break; - case 0: Asm = "tlbi\talle3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE3IS; break; - case 1: Asm = "tlbi\tvae3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE3IS; break; - case 5: Asm = "tlbi\tvale3is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE3IS; break; - } - break; - } - break; - case 0: - switch (Op1Val) { - default: - break; - case 4: - switch (Op2Val) { - default: - break; - case 1: Asm = "tlbi\tipas2e1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2E1IS; break; - case 5: Asm = "tlbi\tipas2le1is"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2LE1IS; break; - } - break; - } - break; - case 4: - switch (Op1Val) { - default: - break; - case 4: - switch (Op2Val) { - default: - break; - case 1: Asm = "tlbi\tipas2e1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2E1; break; - case 5: Asm = "tlbi\tipas2le1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_IPAS2LE1; break; - } - break; - } - break; - case 7: - switch (Op1Val) { - default: - break; - case 0: - switch (Op2Val) { - default: - break; - case 0: Asm = "tlbi\tvmalle1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLE1; break; - case 1: Asm = "tlbi\tvae1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE1; break; - case 2: Asm = "tlbi\taside1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ASIDE1; break; - case 3: Asm = "tlbi\tvaae1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAAE1; break; - case 5: Asm = "tlbi\tvale1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE1; break; - case 7: Asm = "tlbi\tvaale1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAALE1; break; - } - break; - case 4: - switch (Op2Val) { - default: - break; - case 0: Asm = "tlbi\talle2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE2; break; - case 1: Asm = "tlbi\tvae2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE2; break; - case 4: Asm = "tlbi\talle1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE1; break; - case 5: Asm = "tlbi\tvale2"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE2; break; - case 6: Asm = "tlbi\tvmalls12e1"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VMALLS12E1; break; - } - break; - case 6: - switch (Op2Val) { - default: - break; - case 0: Asm = "tlbi\talle3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_ALLE3; break; - case 1: Asm = "tlbi\tvae3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VAE3; break; - case 5: Asm = "tlbi\tvale3"; insn_id = ARM64_INS_TLBI; op_tlbi = ARM64_TLBI_VALE3; break; - } - break; - } - break; - } + const TLBI *TLBI = lookupTLBIByEncoding(Encoding); + // if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits())) + if (!TLBI) + return false; + + NeedsReg = TLBI->NeedsReg; + Ins = "tlbi"; + strncpy(Name, TLBI->Name, sizeof(Name) - 1); + } else + return false; + + SStream_concat(O, "%s\t%s", Ins, Name); + + if (NeedsReg) { + SStream_concat(O, ", %s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, 4)), AArch64_NoRegAltName)); } - if (Asm) { - MCInst_setOpcodePub(MI, insn_id); - SStream_concat0(O, Asm); - if (MI->csh->detail) { + MCInst_setOpcodePub(MI, AArch64_map_insn(Ins)); + + if (MI->csh->detail) { +#if 0 #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = op_ic + op_dc + op_at + op_tlbi; +#endif + + if (NeedsReg) { + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); MI->flat_insn->detail->arm64.op_count++; } - - if (!strstr(Asm, "all")) { - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, 4)); - SStream_concat(O, ", %s", getRegisterName(Reg, AArch64_NoRegAltName)); - if (MI->csh->detail) { -#ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Reg; - MI->flat_insn->detail->arm64.op_count++; - } - } } - return Asm != NULL; + return true; } static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) @@ -739,7 +764,9 @@ static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) if (MCOperand_isReg(Op)) { unsigned Reg = MCOperand_getReg(Op); + SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { if (MI->csh->doing_mem) { if (MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.base == ARM64_REG_INVALID) { @@ -751,6 +778,7 @@ static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) } else { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -783,6 +811,7 @@ static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) } else { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -795,9 +824,11 @@ static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) } } -static void printImm(MCInst *MI, unsigned OpNum, SStream *O) { +static void printImm(MCInst *MI, unsigned OpNum, SStream *O) +{ MCOperand *Op = MCInst_getOperand(MI, OpNum); - SStream_concat0(O, "#", MCOperand_getImm(Op)); + printUInt64Bang(O, MCOperand_getImm(Op)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; @@ -814,7 +845,8 @@ static void printImm(MCInst *MI, unsigned OpNum, SStream *O) { static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); - SStream_concat(O, "#%#llx", MCOperand_getImm(Op)); + printUInt64Bang(O, MCOperand_getImm(Op)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; @@ -828,8 +860,8 @@ static void printImmHex(MCInst *MI, unsigned OpNum, SStream *O) } } -static void printPostIncOperand(MCInst *MI, unsigned OpNum, - unsigned Imm, SStream *O) +static void printPostIncOperand(MCInst *MI, unsigned OpNum, SStream *O, + unsigned Imm) { MCOperand *Op = MCInst_getOperand(MI, OpNum); @@ -837,9 +869,11 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNum, unsigned Reg = MCOperand_getReg(Op); if (Reg == AArch64_XZR) { printInt32Bang(O, Imm); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -850,9 +884,11 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNum, } } else { SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -866,17 +902,14 @@ static void printPostIncOperand(MCInst *MI, unsigned OpNum, //llvm_unreachable("unknown operand kind in printPostIncOperand64"); } -static void printPostIncOperand2(MCInst *MI, unsigned OpNum, SStream *O, int Amount) -{ - printPostIncOperand(MI, OpNum, Amount, O); -} - static void printVRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); //assert(Op.isReg() && "Non-register vreg operand!"); unsigned Reg = MCOperand_getReg(Op); + SStream_concat0(O, getRegisterName(Reg, AArch64_vreg)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; @@ -895,9 +928,11 @@ static void printSysCROperand(MCInst *MI, unsigned OpNum, SStream *O) MCOperand *Op = MCInst_getOperand(MI, OpNum); //assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); SStream_concat(O, "c%u", MCOperand_getImm(Op)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -921,6 +956,7 @@ static void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O) if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -945,6 +981,7 @@ static void printLogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -964,6 +1001,7 @@ static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) default: printInt64Bang(O, Val); break; + case ARM64_INS_ORR: case ARM64_INS_AND: case ARM64_INS_EOR: @@ -979,6 +1017,7 @@ static void printLogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1000,22 +1039,28 @@ static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) SStream_concat(O, ", %s ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val))); printInt32BangDec(O, AArch64_AM_getShiftValue(Val)); + if (MI->csh->detail) { arm64_shifter shifter = ARM64_SFT_INVALID; + switch(AArch64_AM_getShiftType(Val)) { default: // never reach case AArch64_AM_LSL: shifter = ARM64_SFT_LSL; break; + case AArch64_AM_LSR: shifter = ARM64_SFT_LSR; break; + case AArch64_AM_ASR: shifter = ARM64_SFT_ASR; break; + case AArch64_AM_ROR: shifter = ARM64_SFT_ROR; break; + case AArch64_AM_MSL: shifter = ARM64_SFT_MSL; break; @@ -1029,6 +1074,7 @@ static void printShifter(MCInst *MI, unsigned OpNum, SStream *O) static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) { SStream_concat0(O, getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; @@ -1040,6 +1086,7 @@ static void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O) MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); MI->flat_insn->detail->arm64.op_count++; } + printShifter(MI, OpNum + 1, O); } @@ -1055,13 +1102,15 @@ static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { unsigned Dest = MCOperand_getReg(MCInst_getOperand(MI, 0)); unsigned Src1 = MCOperand_getReg(MCInst_getOperand(MI, 1)); - if ( ((Dest == AArch64_SP || Src1 == AArch64_SP) && + + if (((Dest == AArch64_SP || Src1 == AArch64_SP) && ExtType == AArch64_AM_UXTX) || ((Dest == AArch64_WSP || Src1 == AArch64_WSP) && - ExtType == AArch64_AM_UXTW) ) { + ExtType == AArch64_AM_UXTW)) { if (ShiftVal != 0) { SStream_concat0(O, ", lsl "); printInt32Bang(O, ShiftVal); + if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; @@ -1073,31 +1122,40 @@ static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) } SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); + if (MI->csh->detail) { arm64_extender ext = ARM64_EXT_INVALID; switch(ExtType) { default: // never reach + case AArch64_AM_UXTB: ext = ARM64_EXT_UXTB; break; + case AArch64_AM_UXTH: ext = ARM64_EXT_UXTH; break; + case AArch64_AM_UXTW: ext = ARM64_EXT_UXTW; break; + case AArch64_AM_UXTX: ext = ARM64_EXT_UXTX; break; + case AArch64_AM_SXTB: ext = ARM64_EXT_SXTB; break; + case AArch64_AM_SXTH: ext = ARM64_EXT_SXTH; break; + case AArch64_AM_SXTW: ext = ARM64_EXT_SXTW; break; + case AArch64_AM_SXTX: ext = ARM64_EXT_SXTX; break; @@ -1109,6 +1167,7 @@ static void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O) if (ShiftVal != 0) { SStream_concat0(O, " "); printInt32Bang(O, ShiftVal); + if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.type = ARM64_SFT_LSL; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].shift.value = ShiftVal; @@ -1121,6 +1180,7 @@ static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; @@ -1136,18 +1196,20 @@ static void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O) printArithExtend(MI, OpNum + 1, O); } -static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, +static void printMemExtendImpl(MCInst *MI, bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, SStream *O) { - // sxtw, sxtx, uxtw or lsl (== uxtx) + // sxtw, sxtx, uxtw or lsl (== uxtx) bool IsLSL = !SignExtend && SrcRegKind == 'x'; if (IsLSL) { SStream_concat0(O, "lsl"); + if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; } } else { SStream_concat(O, "%cxt%c", (SignExtend ? 's' : 'u'), SrcRegKind); + if (MI->csh->detail) { if (!SignExtend) { switch(SrcRegKind) { @@ -1184,6 +1246,7 @@ static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, if (DoShift || IsLSL) { SStream_concat(O, " #%u", Log2_32(Width / 8)); + if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.type = ARM64_SFT_LSL; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].shift.value = Log2_32(Width / 8); @@ -1195,29 +1258,31 @@ static void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKi { unsigned SignExtend = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned DoShift = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); - printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O) + + printMemExtendImpl(MI, SignExtend, DoShift, Width, SrcRegKind, O); } static void printRegWithShiftExtend(MCInst *MI, unsigned OpNum, SStream *O, bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix) { - printOperand(MI, OpNum, O); - if (Suffix == 's' || Suffix == 'd') - SStream_concat0(O, ".", Suffix); -// else -// assert(Suffix == 0 && "Unsupported suffix size"); + bool DoShift; - bool DoShift = ExtWidth != 8; + printOperand(MI, OpNum, O); + + if (Suffix == 's' || Suffix == 'd') + SStream_concat(O, ".%c", Suffix); + + DoShift = ExtWidth != 8; if (SignExtend || DoShift || SrcRegKind == 'w') { SStream_concat0(O, ", "); - printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O); + printMemExtendImpl(MI, SignExtend, DoShift, ExtWidth, SrcRegKind, O); } } static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) { - A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getCondCodeName(CC)); if (MI->csh->detail) @@ -1226,7 +1291,7 @@ static void printCondCode(MCInst *MI, unsigned OpNum, SStream *O) static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) { - A64CC_CondCode CC = (A64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + AArch64CC_CondCode CC = (AArch64CC_CondCode)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getCondCodeName(getInvertedCondCode(CC))); if (MI->csh->detail) { @@ -1234,11 +1299,6 @@ static void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O) } } -static void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O) -{ - SStream_concat0(O, "[", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName), "]"); -} - static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) { int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); @@ -1251,6 +1311,7 @@ static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) } else { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1262,19 +1323,21 @@ static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale) } } -static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O) +static void printUImm12Offset(MCInst *MI, unsigned OpNum, SStream *O, unsigned Scale) { MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { int64_t val = Scale * MCOperand_getImm(MO); printInt64Bang(O, val); + if (MI->csh->detail) { if (MI->csh->doing_mem) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val; } else { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1287,15 +1350,13 @@ static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStrea } } -static void printUImm12Offset2(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale) -{ - printUImm12Offset(MI, OpNum, Scale, O); -} - +#if 0 static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned int Scale) { MCOperand *MO = MCInst_getOperand(MI, OpNum + 1); - SStream_concat0(O, "[", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); + + SStream_concat(O, "[%s", getRegisterName(MCOperand_getReg(MCInst_getOperand(MI, OpNum)), AArch64_NoRegAltName)); + if (MCOperand_isImm(MO)) { int64_t val = Scale * MCOperand_getImm(MCInst_getOperand(MI, OpNum)); printInt64Bang(O, val); @@ -1304,36 +1365,40 @@ static void printAMIndexedWB(MCInst *MI, unsigned OpNum, SStream *O, unsigned in // SStream_concat0(O, ", "); // MO1.getExpr()->print(O, &MAI); } + SStream_concat0(O, "]"); } +#endif -static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O) +// IsSVEPrefetch = false +static void printPrefetchOp(MCInst *MI, unsigned OpNum, SStream *O, bool IsSVEPrefetch) { unsigned prfop = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - bool Valid; - const char *Name = A64NamedImmMapper_toString(&A64PRFM_PRFMMapper, prfop, &Valid); - if (Valid) { - SStream_concat0(O, Name); - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_PREFETCH; - // we have to plus 1 to prfop because 0 is a valid value of prfop - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].prefetch = prfop + 1; - MI->flat_insn->detail->arm64.op_count++; - } + if (IsSVEPrefetch) { + const SVEPRFM *PRFM = lookupSVEPRFMByEncoding(prfop); + if (PRFM) + SStream_concat0(O, PRFM->Name); } else { - printInt32Bang(O, prfop); - if (MI->csh->detail) { + const PRFM *PRFM = lookupPRFMByEncoding(prfop); + if (PRFM) + SStream_concat0(O, PRFM->Name); + } + + // FIXME: set OpcodePub? + + printInt32Bang(O, prfop); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; - MI->flat_insn->detail->arm64.op_count++; - } + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = prfop; + MI->flat_insn->detail->arm64.op_count++; } } @@ -1341,17 +1406,18 @@ static void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *Op = MCInst_getOperand(MI, OpNum); unsigned int psbhintop = MCOperand_getImm(Op); - // auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop); - // if (PSB) - // O << PSB->Name; - // else - printInt32Bang(O, psbhintop); + + const PSB *PSB = AArch64PSBHint_lookupPSBByEncoding(psbhintop); + if (PSB) + SStream_concat0(O, PSB->Name); + else + printUInt32Bang(O, psbhintop); } static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, OpNum); - double FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); + float FPImm = MCOperand_isFPImm(MO) ? MCOperand_getFPImm(MO) : AArch64_AM_getFPImmFloat((int)MCOperand_getImm(MO)); // 8 decimal places are enough to perfectly represent permitted floats. #if defined(_KERNEL_MODE) @@ -1360,9 +1426,11 @@ static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) #else SStream_concat(O, "#%.8f", FPImm); #endif + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1377,43 +1445,14 @@ static void printFPImmOperand(MCInst *MI, unsigned OpNum, SStream *O) static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride) { while (Stride--) { - switch (Reg) { - default: - // llvm_unreachable("Vector register expected!"); - case AArch64_Q0: Reg = AArch64_Q1; break; - case AArch64_Q1: Reg = AArch64_Q2; break; - case AArch64_Q2: Reg = AArch64_Q3; break; - case AArch64_Q3: Reg = AArch64_Q4; break; - case AArch64_Q4: Reg = AArch64_Q5; break; - case AArch64_Q5: Reg = AArch64_Q6; break; - case AArch64_Q6: Reg = AArch64_Q7; break; - case AArch64_Q7: Reg = AArch64_Q8; break; - case AArch64_Q8: Reg = AArch64_Q9; break; - case AArch64_Q9: Reg = AArch64_Q10; break; - case AArch64_Q10: Reg = AArch64_Q11; break; - case AArch64_Q11: Reg = AArch64_Q12; break; - case AArch64_Q12: Reg = AArch64_Q13; break; - case AArch64_Q13: Reg = AArch64_Q14; break; - case AArch64_Q14: Reg = AArch64_Q15; break; - case AArch64_Q15: Reg = AArch64_Q16; break; - case AArch64_Q16: Reg = AArch64_Q17; break; - case AArch64_Q17: Reg = AArch64_Q18; break; - case AArch64_Q18: Reg = AArch64_Q19; break; - case AArch64_Q19: Reg = AArch64_Q20; break; - case AArch64_Q20: Reg = AArch64_Q21; break; - case AArch64_Q21: Reg = AArch64_Q22; break; - case AArch64_Q22: Reg = AArch64_Q23; break; - case AArch64_Q23: Reg = AArch64_Q24; break; - case AArch64_Q24: Reg = AArch64_Q25; break; - case AArch64_Q25: Reg = AArch64_Q26; break; - case AArch64_Q26: Reg = AArch64_Q27; break; - case AArch64_Q27: Reg = AArch64_Q28; break; - case AArch64_Q28: Reg = AArch64_Q29; break; - case AArch64_Q29: Reg = AArch64_Q30; break; - case AArch64_Q30: Reg = AArch64_Q31; break; - // Vector lists can wrap around. - case AArch64_Q31: Reg = AArch64_Q0; break; - } + if (Reg >= AArch64_Q0 && Reg <= AArch64_Q30) // AArch64_Q0 .. AArch64_Q30 + Reg += 1; + else if (Reg == AArch64_Q31) // Vector lists can wrap around. + Reg = AArch64_Q0; + else if (Reg >= AArch64_Z0 && Reg <= AArch64_Z30) // AArch64_Z0 .. AArch64_Z30 + Reg += 1; + else if (Reg == AArch64_Z31) // Vector lists can wrap around. + Reg = AArch64_Z0; } return Reg; @@ -1423,18 +1462,38 @@ static void printGPRSeqPairsClassOperand(MCInst *MI, unsigned OpNum, SStream *O, { // static_assert(size == 64 || size == 32, // "Template parameter must be either 32 or 64"); - unsigned Reg = MI->getOperand(OpNum).getReg(); + unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned Sube = (size == 32) ? AArch64_sube32 : AArch64_sube64; unsigned Subo = (size == 32) ? AArch64_subo32 : AArch64_subo64; - unsigned Even = MCRegisterInfo_getSubReg(MRI, Reg, Sube); - unsigned Odd = MCRegisterInfo_getSubReg(MRI, Reg, Subo); - SStream_concat0(O, getRegisterName(Even, AArch64_NoRegAltName), ", ", getRegisterName(Odd, AArch64_NoRegAltName); + unsigned Even = MCRegisterInfo_getSubReg(MI->MRI, Reg, Sube); + unsigned Odd = MCRegisterInfo_getSubReg(MI->MRI, Reg, Subo); + + SStream_concat(O, "%s, %s", getRegisterName(Even, AArch64_NoRegAltName), + getRegisterName(Odd, AArch64_NoRegAltName)); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Even); + MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Odd); + MI->flat_insn->detail->arm64.op_count++; + } } -static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas, arm64_vess vess) +static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, + char *LayoutSuffix, MCRegisterInfo *MRI, arm64_vas vas) { #define GETREGCLASS_CONTAIN0(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), _reg) - unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); unsigned NumRegs = 1, FirstReg, i; @@ -1443,12 +1502,15 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *Layout // Work out how many registers there are in the list (if there is an actual // list). if (GETREGCLASS_CONTAIN0(AArch64_DDRegClassID , Reg) || + GETREGCLASS_CONTAIN0(AArch64_ZPR2RegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_QQRegClassID, Reg)) NumRegs = 2; else if (GETREGCLASS_CONTAIN0(AArch64_DDDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_ZPR3RegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_QQQRegClassID, Reg)) NumRegs = 3; else if (GETREGCLASS_CONTAIN0(AArch64_DDDDRegClassID, Reg) || + GETREGCLASS_CONTAIN0(AArch64_ZPR4RegClassID, Reg) || GETREGCLASS_CONTAIN0(AArch64_QQQQRegClassID, Reg)) NumRegs = 4; @@ -1457,6 +1519,8 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *Layout Reg = FirstReg; else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_qsub0))) Reg = FirstReg; + else if ((FirstReg = MCRegisterInfo_getSubReg(MRI, Reg, AArch64_zsub0))) + Reg = FirstReg; // If it's a D-reg, we need to promote it to the equivalent Q-reg before // printing (otherwise getRegisterName fails). @@ -1466,45 +1530,52 @@ static void printVectorList(MCInst *MI, unsigned OpNum, SStream *O, char *Layout } for (i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg, 1)) { - SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); - if (i + 1 != NumRegs) - SStream_concat0(O, ", "); + if (GETREGCLASS_CONTAIN0(AArch64_ZPRRegClassID, Reg)) + SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_NoRegAltName), LayoutSuffix); + else + SStream_concat(O, "%s%s", getRegisterName(Reg, AArch64_vreg), LayoutSuffix); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; #endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG; MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = AArch64_map_vregister(Reg); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vas = vas; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].vess = vess; MI->flat_insn->detail->arm64.op_count++; } + + if (i + 1 != NumRegs) + SStream_concat0(O, ", "); } SStream_concat0(O, "}"); } -static void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O) -{ - printVectorList(MI, OpNum, O, ""); -} - -static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind, MCRegisterInfo *MRI) +static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigned NumLanes, char LaneKind) { char Suffix[32]; arm64_vas vas = 0; - arm64_vess vess = 0; if (NumLanes) { cs_snprintf(Suffix, sizeof(Suffix), ".%u%c", NumLanes, LaneKind); + switch(LaneKind) { default: break; case 'b': switch(NumLanes) { default: break; + case 1: + vas = ARM64_VAS_1B; + break; + case 4: + vas = ARM64_VAS_4B; + break; case 8: vas = ARM64_VAS_8B; break; @@ -1516,6 +1587,12 @@ static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigne case 'h': switch(NumLanes) { default: break; + case 1: + vas = ARM64_VAS_1H; + break; + case 2: + vas = ARM64_VAS_2H; + break; case 4: vas = ARM64_VAS_4H; break; @@ -1527,6 +1604,9 @@ static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigne case 's': switch(NumLanes) { default: break; + case 1: + vas = ARM64_VAS_1S; + break; case 2: vas = ARM64_VAS_2S; break; @@ -1557,24 +1637,28 @@ static void printTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O, unsigne } } else { cs_snprintf(Suffix, sizeof(Suffix), ".%c", LaneKind); + switch(LaneKind) { default: break; case 'b': - vess = ARM64_VESS_B; + vas = ARM64_VAS_1B; break; case 'h': - vess = ARM64_VESS_H; + vas = ARM64_VAS_1H; break; case 's': - vess = ARM64_VESS_S; + vas = ARM64_VAS_1S; break; case 'd': - vess = ARM64_VESS_D; + vas = ARM64_VAS_1D; + break; + case 'q': + vas = ARM64_VAS_1Q; break; } } - printVectorList(MI, OpNum, O, Suffix, MRI, vas, vess); + printVectorList(MI, OpNum, O, Suffix, MI->MRI, vas); } static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) @@ -1582,6 +1666,7 @@ static void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) SStream_concat0(O, "["); printInt32(O, (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum))); SStream_concat0(O, "]"); + if (MI->csh->detail) { MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vector_index = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); } @@ -1596,9 +1681,11 @@ static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) if (MCOperand_isImm(Op)) { uint64_t imm = (MCOperand_getImm(Op) * 4) + MI->address; printUInt64Bang(O, imm); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1607,7 +1694,6 @@ static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O) MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; MI->flat_insn->detail->arm64.op_count++; } - return; } } @@ -1624,6 +1710,7 @@ static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1632,7 +1719,6 @@ static void printAdrpLabel(MCInst *MI, unsigned OpNum, SStream *O) MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm; MI->flat_insn->detail->arm64.op_count++; } - return; } } @@ -1640,19 +1726,26 @@ static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Opcode = MCInst_getOpcode(MI); - bool Valid; - const char *Name; + const char *Name = NULL; - if (Opcode == AArch64_ISB) - Name = A64NamedImmMapper_toString(&A64ISB_ISBMapper, Val, &Valid); - else - Name = A64NamedImmMapper_toString(&A64DB_DBarrierMapper, Val, &Valid); + if (Opcode == AArch64_ISB) { + const ISB *ISB = lookupISBByEncoding(Val); + Name = ISB ? ISB->Name : NULL; + } else if (Opcode == AArch64_TSB) { + const TSB *TSB = lookupTSBByEncoding(Val); + Name = TSB ? TSB->Name : NULL; + } else { + const DB *DB = lookupDBByEncoding(Val); + Name = DB ? DB->Name : NULL; + } - if (Valid) { + if (Name) { SStream_concat0(O, Name); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1663,9 +1756,11 @@ static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) } } else { printUInt32Bang(O, Val); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1680,54 +1775,142 @@ static void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O) static void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - char Name[128]; + const SysReg *Reg = lookupSysRegByEncoding(Val); - A64SysRegMapper_toString(&AArch64_MRSMapper, Val, Name); + // Horrible hack for the one register that has identical encodings but + // different names in MSR and MRS. Because of this, one of MRS and MSR is + // going to get the wrong entry + if (Val == ARM64_SYSREG_DBGDTRRX_EL0) { + SStream_concat0(O, "dbgdtrrx_el0"); - SStream_concat0(O, Name); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; - MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + // if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits())) + if (Reg && Reg->Readable) { + SStream_concat0(O, Reg->Name); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + char result[128]; + + AArch64SysReg_genericRegisterString(Val, result); + SStream_concat0(O, result); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; + MI->flat_insn->detail->arm64.op_count++; + } } } static void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - char Name[128]; + const SysReg *Reg = lookupSysRegByEncoding(Val); - A64SysRegMapper_toString(&AArch64_MSRMapper, Val, Name); + // Horrible hack for the one register that has identical encodings but + // different names in MSR and MRS. Because of this, one of MRS and MSR is + // going to get the wrong entry + if (Val == ARM64_SYSREG_DBGDTRTX_EL0) { + SStream_concat0(O, "dbgdtrtx_el0"); - SStream_concat0(O, Name); - if (MI->csh->detail) { + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - uint8_t access; - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; #endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MSR; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; - MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Val; + MI->flat_insn->detail->arm64.op_count++; + } + + return; + } + + // if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits())) + if (Reg && Reg->Writeable) { + SStream_concat0(O, Reg->Name); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_SYS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].sys = Reg->Encoding; + MI->flat_insn->detail->arm64.op_count++; + } + } else { + char result[128]; + + AArch64SysReg_genericRegisterString(Val, result); + SStream_concat0(O, result); + + if (MI->csh->detail) { +#ifndef CAPSTONE_DIET + uint8_t access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; +#endif + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_REG_MRS; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].reg = Val; + MI->flat_insn->detail->arm64.op_count++; + } } } static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = (unsigned)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - bool Valid; - const char *Name; - Name = A64NamedImmMapper_toString(&A64PState_PStateMapper, Val, &Valid); - if (Valid) { - SStream_concat0(O, Name); + const PState *PState = lookupPStateByEncoding(Val); + + if (PState) { + SStream_concat0(O, PState->Name); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET uint8_t access; @@ -1740,18 +1923,21 @@ static void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O) MI->flat_insn->detail->arm64.op_count++; } } else { + printUInt32Bang(O, Val); + + if (MI->csh->detail) { #ifndef CAPSTONE_DIET - unsigned char access; + unsigned char access; + + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; + MI->ac_idx++; #endif - printInt32Bang(O, Val); -#ifndef CAPSTONE_DIET - access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; - MI->ac_idx++; -#endif - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; - MI->flat_insn->detail->arm64.op_count++; + + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM; + MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = Val; + MI->flat_insn->detail->arm64.op_count++; + } } } @@ -1759,10 +1945,13 @@ static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O) { uint8_t RawVal = (uint8_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum)); uint64_t Val = AArch64_AM_decodeAdvSIMDModImmType10(RawVal); + SStream_concat(O, "#%#016llx", Val); + if (MI->csh->detail) { #ifndef CAPSTONE_DIET unsigned char access; + access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; MI->ac_idx++; @@ -1776,21 +1965,27 @@ static void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O) static void printComplexRotationOp(MCInst *MI, unsigned OpNum, SStream *O, int64_t Angle, int64_t Remainder) { unsigned int Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - printInt64Bang((Val * Angle) + Remainder); + printInt64Bang(O, (Val * Angle) + Remainder); + op_addImm(MI, (Val * Angle) + Remainder); } static void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O) { unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // TODO: Fix this - // if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val)) - // O << Pat->Name; - // else - SStream_concat0(O, "#", Val); + + const SVEPREDPAT *Pat = lookupSVEPREDPATByEncoding(Val); + if (Pat) + SStream_concat0(O, Pat->Name); + else + printUInt32Bang(O, Val); } +// default suffix = 0 static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix) { + unsigned int Reg; + +#if 0 switch (suffix) { case 0: case 'b': @@ -1802,101 +1997,137 @@ static void printSVERegOp(MCInst *MI, unsigned OpNum, SStream *O, char suffix) default: // llvm_unreachable("Invalid kind specifier."); } +#endif + + Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); - unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); SStream_concat0(O, getRegisterName(Reg, AArch64_NoRegAltName)); - if (suffix != 0) - SStream_concat0(O, ".", suffix); + + if (suffix != '\0') + SStream_concat(O, ".%c", suffix); } -// TODO: should I make a few more versions of this func to handle the other templates? -static void printImmSVE(uint64_t Val, SStream *O) +static void printImmSVE16(int16_t Val, SStream *O) { - // do not print number in negative form - if (Val >= 0 && Val <= HEX_THRESHOLD) - SStream_concat(O, "#%u", (int)Val); - else - SStream_concat(O, "#0x%"PRIx64, Val); - // Do the opposite to that used for instruction operands. - // TODO: Add CommentStream support - // if (CommentStream) { - // // do not print number in negative form - // if (Val >= 0 && Val <= HEX_THRESHOLD) - // SStream_concat(CommentStream, "=#%u\n", (int)Val); - // else - // SStream_concat(CommentStream, "=#0x%llx\n", Val); - // } + printUInt32Bang(O, Val); } -static void printImm8OptLsl(MCInst *MI, unsigned OpNum, SStream *O, bool is_signed) +static void printImmSVE32(int32_t Val, SStream *O) +{ + printUInt32Bang(O, Val); +} + +static void printImmSVE64(int64_t Val, SStream *O) +{ + printUInt64Bang(O, Val); +} + +static void printImm8OptLsl32(MCInst *MI, unsigned OpNum, SStream *O) { unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint32_t Val; + // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && // "Unexepected shift type!"); // #0 lsl #8 is never pretty printed if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { - SStream_concat0(O, "#", UnscaledVal); + printUInt32Bang(O, UnscaledVal); printShifter(MI, OpNum + 1, O); return; } - if (is_signed) - int8_t Val = (int8_t)UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); - else - uint8_t Val = (uint8_t)UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); - - printImmSVE(Val, O); + Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); + printImmSVE32(Val, O); } -static void printSVELogicalImm(MCInst *MI, unsigned OpNum, SStream *O, bool Signed) +static void printImm8OptLsl64(MCInst *MI, unsigned OpNum, SStream *O) +{ + unsigned UnscaledVal = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + unsigned Shift = MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1)); + uint64_t Val; + + // assert(AArch64_AM::getShiftType(Shift) == AArch64_AM::LSL && + // "Unexepected shift type!"); + + // #0 lsl #8 is never pretty printed + if ((UnscaledVal == 0) && (AArch64_AM_getShiftValue(Shift) != 0)) { + printUInt32Bang(O, UnscaledVal); + printShifter(MI, OpNum + 1, O); + return; + } + + Val = UnscaledVal * (1 << AArch64_AM_getShiftValue(Shift)); + printImmSVE64(Val, O); +} + +static void printSVELogicalImm16(MCInst *MI, unsigned OpNum, SStream *O) { - // typedef typename std::make_signed::type SignedT; - // typedef typename std::make_unsigned::type UnsignedT; uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); // Prefer the default format for 16bit values, hex otherwise. - if (Signed) - printImmSVE((int16_t)PrintVal, O); + printImmSVE16(PrintVal, O); +} + +static void printSVELogicalImm32(MCInst *MI, unsigned OpNum, SStream *O) +{ + uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); + + // Prefer the default format for 16bit values, hex otherwise. + if ((uint16_t)PrintVal == (uint32_t)PrintVal) + printImmSVE16(PrintVal, O); else - printUInt64Bang(O, PrintVal) + printUInt64Bang(O, PrintVal); +} + +static void printSVELogicalImm64(MCInst *MI, unsigned OpNum, SStream *O) +{ + uint64_t Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + uint64_t PrintVal = AArch64_AM_decodeLogicalImmediate(Val, 64); + + printImmSVE64(PrintVal, O); } static void printZPRasFPR(MCInst *MI, unsigned OpNum, SStream *O, int Width) { - unsigned int Base; + unsigned int Base, Reg; + switch (Width) { - case 8: Base = AArch64_B0; break; - case 16: Base = AArch64_H0; break; - case 32: Base = AArch64_S0; break; - case 64: Base = AArch64_D0; break; - case 128: Base = AArch64_Q0; break; - default: - // llvm_unreachable("Unsupported width"); + default: // llvm_unreachable("Unsupported width"); + case 8: Base = AArch64_B0; break; + case 16: Base = AArch64_H0; break; + case 32: Base = AArch64_S0; break; + case 64: Base = AArch64_D0; break; + case 128: Base = AArch64_Q0; break; } - unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + + Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, getRegisterName(Reg - AArch64_Z0 + Base, AArch64_NoRegAltName)); } static void printExactFPImm(MCInst *MI, unsigned OpNum, SStream *O, unsigned ImmIs0, unsigned ImmIs1) { - // TODO: fix this !!!! - // auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0); - // auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1); - // unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - // O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr); + const ExactFPImm *Imm0Desc = lookupExactFPImmByEnum(ImmIs0); + const ExactFPImm *Imm1Desc = lookupExactFPImmByEnum(ImmIs1); + unsigned Val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); + + SStream_concat0(O, Val ? Imm1Desc->Repr : Imm0Desc->Repr); } static void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O) { - unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)) + unsigned int Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum)); + SStream_concat0(O, getRegisterName(getWRegFromXReg(Reg), AArch64_NoRegAltName)); } #define PRINT_ALIAS_INSTR #include "AArch64GenAsmWriter.inc" +#include "AArch64GenRegisterName.inc" void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst *mci) { @@ -1905,6 +2136,7 @@ void AArch64_post_printer(csh handle, cs_insn *flat_insn, char *insn_asm, MCInst if (mci->csh->detail) { unsigned opcode = MCInst_getOpcode(mci); + switch (opcode) { default: break; diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 7fbfbf446..603e48d62 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -14,269 +14,327 @@ #include "AArch64GenInstrInfo.inc" #ifndef CAPSTONE_DIET -static const name_map reg_name_maps[] = { - { ARM64_REG_INVALID, NULL }, +// NOTE: this reg_name_maps[] reflects the order of registers in arm64_reg +static const char *reg_name_maps[] = { + NULL, /* ARM64_REG_INVALID */ - { ARM64_REG_X29, "x29"}, - { ARM64_REG_X30, "x30"}, - { ARM64_REG_NZCV, "nzcv"}, - { ARM64_REG_SP, "sp"}, - { ARM64_REG_WSP, "wsp"}, - { ARM64_REG_WZR, "wzr"}, - { ARM64_REG_XZR, "xzr"}, - { ARM64_REG_B0, "b0"}, - { ARM64_REG_B1, "b1"}, - { ARM64_REG_B2, "b2"}, - { ARM64_REG_B3, "b3"}, - { ARM64_REG_B4, "b4"}, - { ARM64_REG_B5, "b5"}, - { ARM64_REG_B6, "b6"}, - { ARM64_REG_B7, "b7"}, - { ARM64_REG_B8, "b8"}, - { ARM64_REG_B9, "b9"}, - { ARM64_REG_B10, "b10"}, - { ARM64_REG_B11, "b11"}, - { ARM64_REG_B12, "b12"}, - { ARM64_REG_B13, "b13"}, - { ARM64_REG_B14, "b14"}, - { ARM64_REG_B15, "b15"}, - { ARM64_REG_B16, "b16"}, - { ARM64_REG_B17, "b17"}, - { ARM64_REG_B18, "b18"}, - { ARM64_REG_B19, "b19"}, - { ARM64_REG_B20, "b20"}, - { ARM64_REG_B21, "b21"}, - { ARM64_REG_B22, "b22"}, - { ARM64_REG_B23, "b23"}, - { ARM64_REG_B24, "b24"}, - { ARM64_REG_B25, "b25"}, - { ARM64_REG_B26, "b26"}, - { ARM64_REG_B27, "b27"}, - { ARM64_REG_B28, "b28"}, - { ARM64_REG_B29, "b29"}, - { ARM64_REG_B30, "b30"}, - { ARM64_REG_B31, "b31"}, - { ARM64_REG_D0, "d0"}, - { ARM64_REG_D1, "d1"}, - { ARM64_REG_D2, "d2"}, - { ARM64_REG_D3, "d3"}, - { ARM64_REG_D4, "d4"}, - { ARM64_REG_D5, "d5"}, - { ARM64_REG_D6, "d6"}, - { ARM64_REG_D7, "d7"}, - { ARM64_REG_D8, "d8"}, - { ARM64_REG_D9, "d9"}, - { ARM64_REG_D10, "d10"}, - { ARM64_REG_D11, "d11"}, - { ARM64_REG_D12, "d12"}, - { ARM64_REG_D13, "d13"}, - { ARM64_REG_D14, "d14"}, - { ARM64_REG_D15, "d15"}, - { ARM64_REG_D16, "d16"}, - { ARM64_REG_D17, "d17"}, - { ARM64_REG_D18, "d18"}, - { ARM64_REG_D19, "d19"}, - { ARM64_REG_D20, "d20"}, - { ARM64_REG_D21, "d21"}, - { ARM64_REG_D22, "d22"}, - { ARM64_REG_D23, "d23"}, - { ARM64_REG_D24, "d24"}, - { ARM64_REG_D25, "d25"}, - { ARM64_REG_D26, "d26"}, - { ARM64_REG_D27, "d27"}, - { ARM64_REG_D28, "d28"}, - { ARM64_REG_D29, "d29"}, - { ARM64_REG_D30, "d30"}, - { ARM64_REG_D31, "d31"}, - { ARM64_REG_H0, "h0"}, - { ARM64_REG_H1, "h1"}, - { ARM64_REG_H2, "h2"}, - { ARM64_REG_H3, "h3"}, - { ARM64_REG_H4, "h4"}, - { ARM64_REG_H5, "h5"}, - { ARM64_REG_H6, "h6"}, - { ARM64_REG_H7, "h7"}, - { ARM64_REG_H8, "h8"}, - { ARM64_REG_H9, "h9"}, - { ARM64_REG_H10, "h10"}, - { ARM64_REG_H11, "h11"}, - { ARM64_REG_H12, "h12"}, - { ARM64_REG_H13, "h13"}, - { ARM64_REG_H14, "h14"}, - { ARM64_REG_H15, "h15"}, - { ARM64_REG_H16, "h16"}, - { ARM64_REG_H17, "h17"}, - { ARM64_REG_H18, "h18"}, - { ARM64_REG_H19, "h19"}, - { ARM64_REG_H20, "h20"}, - { ARM64_REG_H21, "h21"}, - { ARM64_REG_H22, "h22"}, - { ARM64_REG_H23, "h23"}, - { ARM64_REG_H24, "h24"}, - { ARM64_REG_H25, "h25"}, - { ARM64_REG_H26, "h26"}, - { ARM64_REG_H27, "h27"}, - { ARM64_REG_H28, "h28"}, - { ARM64_REG_H29, "h29"}, - { ARM64_REG_H30, "h30"}, - { ARM64_REG_H31, "h31"}, - { ARM64_REG_Q0, "q0"}, - { ARM64_REG_Q1, "q1"}, - { ARM64_REG_Q2, "q2"}, - { ARM64_REG_Q3, "q3"}, - { ARM64_REG_Q4, "q4"}, - { ARM64_REG_Q5, "q5"}, - { ARM64_REG_Q6, "q6"}, - { ARM64_REG_Q7, "q7"}, - { ARM64_REG_Q8, "q8"}, - { ARM64_REG_Q9, "q9"}, - { ARM64_REG_Q10, "q10"}, - { ARM64_REG_Q11, "q11"}, - { ARM64_REG_Q12, "q12"}, - { ARM64_REG_Q13, "q13"}, - { ARM64_REG_Q14, "q14"}, - { ARM64_REG_Q15, "q15"}, - { ARM64_REG_Q16, "q16"}, - { ARM64_REG_Q17, "q17"}, - { ARM64_REG_Q18, "q18"}, - { ARM64_REG_Q19, "q19"}, - { ARM64_REG_Q20, "q20"}, - { ARM64_REG_Q21, "q21"}, - { ARM64_REG_Q22, "q22"}, - { ARM64_REG_Q23, "q23"}, - { ARM64_REG_Q24, "q24"}, - { ARM64_REG_Q25, "q25"}, - { ARM64_REG_Q26, "q26"}, - { ARM64_REG_Q27, "q27"}, - { ARM64_REG_Q28, "q28"}, - { ARM64_REG_Q29, "q29"}, - { ARM64_REG_Q30, "q30"}, - { ARM64_REG_Q31, "q31"}, - { ARM64_REG_S0, "s0"}, - { ARM64_REG_S1, "s1"}, - { ARM64_REG_S2, "s2"}, - { ARM64_REG_S3, "s3"}, - { ARM64_REG_S4, "s4"}, - { ARM64_REG_S5, "s5"}, - { ARM64_REG_S6, "s6"}, - { ARM64_REG_S7, "s7"}, - { ARM64_REG_S8, "s8"}, - { ARM64_REG_S9, "s9"}, - { ARM64_REG_S10, "s10"}, - { ARM64_REG_S11, "s11"}, - { ARM64_REG_S12, "s12"}, - { ARM64_REG_S13, "s13"}, - { ARM64_REG_S14, "s14"}, - { ARM64_REG_S15, "s15"}, - { ARM64_REG_S16, "s16"}, - { ARM64_REG_S17, "s17"}, - { ARM64_REG_S18, "s18"}, - { ARM64_REG_S19, "s19"}, - { ARM64_REG_S20, "s20"}, - { ARM64_REG_S21, "s21"}, - { ARM64_REG_S22, "s22"}, - { ARM64_REG_S23, "s23"}, - { ARM64_REG_S24, "s24"}, - { ARM64_REG_S25, "s25"}, - { ARM64_REG_S26, "s26"}, - { ARM64_REG_S27, "s27"}, - { ARM64_REG_S28, "s28"}, - { ARM64_REG_S29, "s29"}, - { ARM64_REG_S30, "s30"}, - { ARM64_REG_S31, "s31"}, - { ARM64_REG_W0, "w0"}, - { ARM64_REG_W1, "w1"}, - { ARM64_REG_W2, "w2"}, - { ARM64_REG_W3, "w3"}, - { ARM64_REG_W4, "w4"}, - { ARM64_REG_W5, "w5"}, - { ARM64_REG_W6, "w6"}, - { ARM64_REG_W7, "w7"}, - { ARM64_REG_W8, "w8"}, - { ARM64_REG_W9, "w9"}, - { ARM64_REG_W10, "w10"}, - { ARM64_REG_W11, "w11"}, - { ARM64_REG_W12, "w12"}, - { ARM64_REG_W13, "w13"}, - { ARM64_REG_W14, "w14"}, - { ARM64_REG_W15, "w15"}, - { ARM64_REG_W16, "w16"}, - { ARM64_REG_W17, "w17"}, - { ARM64_REG_W18, "w18"}, - { ARM64_REG_W19, "w19"}, - { ARM64_REG_W20, "w20"}, - { ARM64_REG_W21, "w21"}, - { ARM64_REG_W22, "w22"}, - { ARM64_REG_W23, "w23"}, - { ARM64_REG_W24, "w24"}, - { ARM64_REG_W25, "w25"}, - { ARM64_REG_W26, "w26"}, - { ARM64_REG_W27, "w27"}, - { ARM64_REG_W28, "w28"}, - { ARM64_REG_W29, "w29"}, - { ARM64_REG_W30, "w30"}, - { ARM64_REG_X0, "x0"}, - { ARM64_REG_X1, "x1"}, - { ARM64_REG_X2, "x2"}, - { ARM64_REG_X3, "x3"}, - { ARM64_REG_X4, "x4"}, - { ARM64_REG_X5, "x5"}, - { ARM64_REG_X6, "x6"}, - { ARM64_REG_X7, "x7"}, - { ARM64_REG_X8, "x8"}, - { ARM64_REG_X9, "x9"}, - { ARM64_REG_X10, "x10"}, - { ARM64_REG_X11, "x11"}, - { ARM64_REG_X12, "x12"}, - { ARM64_REG_X13, "x13"}, - { ARM64_REG_X14, "x14"}, - { ARM64_REG_X15, "x15"}, - { ARM64_REG_X16, "x16"}, - { ARM64_REG_X17, "x17"}, - { ARM64_REG_X18, "x18"}, - { ARM64_REG_X19, "x19"}, - { ARM64_REG_X20, "x20"}, - { ARM64_REG_X21, "x21"}, - { ARM64_REG_X22, "x22"}, - { ARM64_REG_X23, "x23"}, - { ARM64_REG_X24, "x24"}, - { ARM64_REG_X25, "x25"}, - { ARM64_REG_X26, "x26"}, - { ARM64_REG_X27, "x27"}, - { ARM64_REG_X28, "x28"}, + "ffr", + "fp", + "lr", + "nzcv", + "sp", + "wsp", + "wzr", + "xzr", - { ARM64_REG_V0, "v0"}, - { ARM64_REG_V1, "v1"}, - { ARM64_REG_V2, "v2"}, - { ARM64_REG_V3, "v3"}, - { ARM64_REG_V4, "v4"}, - { ARM64_REG_V5, "v5"}, - { ARM64_REG_V6, "v6"}, - { ARM64_REG_V7, "v7"}, - { ARM64_REG_V8, "v8"}, - { ARM64_REG_V9, "v9"}, - { ARM64_REG_V10, "v10"}, - { ARM64_REG_V11, "v11"}, - { ARM64_REG_V12, "v12"}, - { ARM64_REG_V13, "v13"}, - { ARM64_REG_V14, "v14"}, - { ARM64_REG_V15, "v15"}, - { ARM64_REG_V16, "v16"}, - { ARM64_REG_V17, "v17"}, - { ARM64_REG_V18, "v18"}, - { ARM64_REG_V19, "v19"}, - { ARM64_REG_V20, "v20"}, - { ARM64_REG_V21, "v21"}, - { ARM64_REG_V22, "v22"}, - { ARM64_REG_V23, "v23"}, - { ARM64_REG_V24, "v24"}, - { ARM64_REG_V25, "v25"}, - { ARM64_REG_V26, "v26"}, - { ARM64_REG_V27, "v27"}, - { ARM64_REG_V28, "v28"}, - { ARM64_REG_V29, "v29"}, - { ARM64_REG_V30, "v30"}, - { ARM64_REG_V31, "v31"}, + "b0", + "b1", + "b2", + "b3", + "b4", + "b5", + "b6", + "b7", + "b8", + "b9", + "b10", + "b11", + "b12", + "b13", + "b14", + "b15", + "b16", + "b17", + "b18", + "b19", + "b20", + "b21", + "b22", + "b23", + "b24", + "b25", + "b26", + "b27", + "b28", + "b29", + "b30", + "b31", + + "d0", + "d1", + "d2", + "d3", + "d4", + "d5", + "d6", + "d7", + "d8", + "d9", + "d10", + "d11", + "d12", + "d13", + "d14", + "d15", + "d16", + "d17", + "d18", + "d19", + "d20", + "d21", + "d22", + "d23", + "d24", + "d25", + "d26", + "d27", + "d28", + "d29", + "d30", + "d31", + + "h0", + "h1", + "h2", + "h3", + "h4", + "h5", + "h6", + "h7", + "h8", + "h9", + "h10", + "h11", + "h12", + "h13", + "h14", + "h15", + "h16", + "h17", + "h18", + "h19", + "h20", + "h21", + "h22", + "h23", + "h24", + "h25", + "h26", + "h27", + "h28", + "h29", + "h30", + "h31", + + "p0", + "p1", + "p2", + "p3", + "p4", + "p5", + "p6", + "p7", + "p8", + "p9", + "p10", + "p11", + "p12", + "p13", + "p14", + "p15", + + "q0", + "q1", + "q2", + "q3", + "q4", + "q5", + "q6", + "q7", + "q8", + "q9", + "q10", + "q11", + "q12", + "q13", + "q14", + "q15", + "q16", + "q17", + "q18", + "q19", + "q20", + "q21", + "q22", + "q23", + "q24", + "q25", + "q26", + "q27", + "q28", + "q29", + "q30", + "q31", + "s0", + "s1", + "s2", + "s3", + "s4", + "s5", + "s6", + "s7", + "s8", + "s9", + "s10", + "s11", + "s12", + "s13", + "s14", + "s15", + "s16", + "s17", + "s18", + "s19", + "s20", + "s21", + "s22", + "s23", + "s24", + "s25", + "s26", + "s27", + "s28", + "s29", + "s30", + "s31", + + "w0", + "w1", + "w2", + "w3", + "w4", + "w5", + "w6", + "w7", + "w8", + "w9", + "w10", + "w11", + "w12", + "w13", + "w14", + "w15", + "w16", + "w17", + "w18", + "w19", + "w20", + "w21", + "w22", + "w23", + "w24", + "w25", + "w26", + "w27", + "w28", + "w29", + "w30", + + "x0", + "x1", + "x2", + "x3", + "x4", + "x5", + "x6", + "x7", + "x8", + "x9", + "x10", + "x11", + "x12", + "x13", + "x14", + "x15", + "x16", + "x17", + "x18", + "x19", + "x20", + "x21", + "x22", + "x23", + "x24", + "x25", + "x26", + "x27", + "x28", + + "z0", + "z1", + "z2", + "z3", + "z4", + "z5", + "z6", + "z7", + "z8", + "z9", + "z10", + "z11", + "z12", + "z13", + "z14", + "z15", + "z16", + "z17", + "z18", + "z19", + "z20", + "z21", + "z22", + "z23", + "z24", + "z25", + "z26", + "z27", + "z28", + "z29", + "z30", + "z31", + + "v0", + "v1", + "v2", + "v3", + "v4", + "v5", + "v6", + "v7", + "v8", + "v9", + "v10", + "v11", + "v12", + "v13", + "v14", + "v15", + "v16", + "v17", + "v18", + "v19", + "v20", + "v21", + "v22", + "v23", + "v24", + "v25", + "v26", + "v27", + "v28", + "v29", + "v30", + "v31", }; #endif @@ -286,7 +344,7 @@ const char *AArch64_reg_name(csh handle, unsigned int reg) if (reg >= ARR_SIZE(reg_name_maps)) return NULL; - return reg_name_maps[reg].name; + return reg_name_maps[reg]; #else return NULL; #endif @@ -331,82 +389,20 @@ void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) } } -#ifndef CAPSTONE_DIET -static const name_map insn_name_maps[] = { - { ARM64_INS_INVALID, NULL }, - -#include "AArch64GenInsnNameMaps.inc" +static const char *insn_name_maps[] = { + NULL, // ARM64_INS_INVALID +#include "AArch64MappingInsnName.inc" }; -// map *S & alias instructions back to original id -static const name_map alias_insn_name_maps[] = { - { ARM64_INS_ADC, "adcs" }, - { ARM64_INS_AND, "ands" }, - { ARM64_INS_ADD, "adds" }, - { ARM64_INS_BIC, "bics" }, - { ARM64_INS_SBC, "sbcs" }, - { ARM64_INS_SUB, "subs" }, - - // alias insn - { ARM64_INS_MNEG, "mneg" }, - { ARM64_INS_UMNEGL, "umnegl" }, - { ARM64_INS_SMNEGL, "smnegl" }, - { ARM64_INS_NOP, "nop" }, - { ARM64_INS_YIELD, "yield" }, - { ARM64_INS_WFE, "wfe" }, - { ARM64_INS_WFI, "wfi" }, - { ARM64_INS_SEV, "sev" }, - { ARM64_INS_SEVL, "sevl" }, - { ARM64_INS_NGC, "ngc" }, - { ARM64_INS_NGCS, "ngcs" }, - { ARM64_INS_NEGS, "negs" }, - - { ARM64_INS_SBFIZ, "sbfiz" }, - { ARM64_INS_UBFIZ, "ubfiz" }, - { ARM64_INS_SBFX, "sbfx" }, - { ARM64_INS_UBFX, "ubfx" }, - { ARM64_INS_BFI, "bfi" }, - { ARM64_INS_BFXIL, "bfxil" }, - { ARM64_INS_CMN, "cmn" }, - { ARM64_INS_MVN, "mvn" }, - { ARM64_INS_TST, "tst" }, - { ARM64_INS_CSET, "cset" }, - { ARM64_INS_CINC, "cinc" }, - { ARM64_INS_CSETM, "csetm" }, - { ARM64_INS_CINV, "cinv" }, - { ARM64_INS_CNEG, "cneg" }, - { ARM64_INS_SXTB, "sxtb" }, - { ARM64_INS_SXTH, "sxth" }, - { ARM64_INS_SXTW, "sxtw" }, - { ARM64_INS_CMP, "cmp" }, - { ARM64_INS_UXTB, "uxtb" }, - { ARM64_INS_UXTH, "uxth" }, - { ARM64_INS_UXTW, "uxtw" }, - - { ARM64_INS_IC, "ic" }, - { ARM64_INS_DC, "dc" }, - { ARM64_INS_AT, "at" }, - { ARM64_INS_TLBI, "tlbi" }, -}; -#endif - const char *AArch64_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET - unsigned int i; - if (id >= ARM64_INS_ENDING) return NULL; if (id < ARR_SIZE(insn_name_maps)) return insn_name_maps[id]; - // then find alias insn - for (i = 0; i < ARR_SIZE(alias_insn_name_maps); i++) { - if (alias_insn_name_maps[i].id == id) - return alias_insn_name_maps[i].name; - } - // not found return NULL; #else @@ -431,23 +427,19 @@ static const name_map group_name_maps[] = { { ARM64_GRP_NEON, "neon" }, { ARM64_GRP_CRC, "crc" }, - // new - { ARM64_GRP_HASAES, "hasaes" }, - { ARM64_GRP_HASCRC, "hascrc" }, - { ARM64_GRP_HASDOTPROD, "hasdotprod" }, - { ARM64_GRP_HASFPARMV8, "hasfparmv8" }, - { ARM64_GRP_HASFULLFP16, "hasfullfp16" }, - { ARM64_GRP_HASLSE, "haslse" }, - { ARM64_GRP_HASNEON, "hasneon" }, - { ARM64_GRP_HASRCPC, "hasrcpc" }, - { ARM64_GRP_HASRDM, "hasrdm" }, - { ARM64_GRP_HASSHA2, "hassha2" }, - { ARM64_GRP_HASSHA3, "hassha3" }, - { ARM64_GRP_HASSM4, "hassm4" }, - { ARM64_GRP_HASSVE, "hassve" }, - { ARM64_GRP_HASV8_1A, "hasv8_1a" }, - { ARM64_GRP_HASV8_3A, "hasv8_3a" }, - { ARM64_GRP_HASV8_4A, "hasv8_4a" }, + { ARM64_GRP_AES, "aes" }, + { ARM64_GRP_DOTPROD, "dotprod" }, + { ARM64_GRP_FULLFP16, "fullfp16" }, + { ARM64_GRP_LSE, "lse" }, + { ARM64_GRP_RCPC, "rcpc" }, + { ARM64_GRP_RDM, "rdm" }, + { ARM64_GRP_SHA2, "sha2" }, + { ARM64_GRP_SHA3, "sha3" }, + { ARM64_GRP_SM4, "sm4" }, + { ARM64_GRP_SVE, "sve" }, + { ARM64_GRP_V8_1A, "v8_1a" }, + { ARM64_GRP_V8_3A, "v8_3a" }, + { ARM64_GRP_V8_4A, "v8_4a" }, }; #endif @@ -461,108 +453,28 @@ const char *AArch64_group_name(csh handle, unsigned int id) } // map instruction name to public instruction ID -arm64_reg AArch64_map_insn(const char *name) +arm64_insn AArch64_map_insn(const char *name) { - // NOTE: skip first NULL name in insn_name_maps - int i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name); + unsigned int i; - if (i == -1) - // try again with 'special' insn that is not available in insn_name_maps - i = name2id(alias_insn_name_maps, ARR_SIZE(alias_insn_name_maps), name); + for(i = 1; i < ARR_SIZE(insn_name_maps); i++) { + if (!strcmp(name, insn_name_maps[i])) + return i; + } - return (i != -1)? i : ARM64_REG_INVALID; + // not found + return ARM64_INS_INVALID; } // map internal raw vregister to 'public' register arm64_reg AArch64_map_vregister(unsigned int r) { - // for some reasons different Arm64 can map different register number to - // the same register. this function handles the issue for exposing Mips - // operands by mapping internal registers to 'public' register. - static const unsigned int map[] = { 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, ARM64_REG_V0, - ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, - ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, - ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, - ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, - ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, - ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, - ARM64_REG_V31, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, ARM64_REG_V0, ARM64_REG_V1, - ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, - ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, - ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, - ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, - ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, - ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, - 0, 0, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, - ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, - ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, - ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, - ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, - ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, - ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, - ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, - ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, - ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, - ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, - ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, - ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, - ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, - ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, - ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, - ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, - ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, - ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, - ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, - ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, - ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, - ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, - ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, - ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, - ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, - ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, ARM64_REG_V3, ARM64_REG_V4, - ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, ARM64_REG_V8, ARM64_REG_V9, - ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, ARM64_REG_V13, ARM64_REG_V14, - ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, ARM64_REG_V18, ARM64_REG_V19, - ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, ARM64_REG_V23, ARM64_REG_V24, - ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, ARM64_REG_V28, ARM64_REG_V29, - ARM64_REG_V30, ARM64_REG_V31, ARM64_REG_V0, ARM64_REG_V1, ARM64_REG_V2, - ARM64_REG_V3, ARM64_REG_V4, ARM64_REG_V5, ARM64_REG_V6, ARM64_REG_V7, - ARM64_REG_V8, ARM64_REG_V9, ARM64_REG_V10, ARM64_REG_V11, ARM64_REG_V12, - ARM64_REG_V13, ARM64_REG_V14, ARM64_REG_V15, ARM64_REG_V16, ARM64_REG_V17, - ARM64_REG_V18, ARM64_REG_V19, ARM64_REG_V20, ARM64_REG_V21, ARM64_REG_V22, - ARM64_REG_V23, ARM64_REG_V24, ARM64_REG_V25, ARM64_REG_V26, ARM64_REG_V27, - ARM64_REG_V28, ARM64_REG_V29, ARM64_REG_V30, ARM64_REG_V31, }; + static const unsigned short RegAsmOffsetvreg[] = { +#include "AArch64GenRegisterV.inc" + }; - if (r < ARR_SIZE(map)) - return map[r]; + if (r < ARR_SIZE(RegAsmOffsetvreg)) + return RegAsmOffsetvreg[r - 1]; // cannot find this register return 0; @@ -575,13 +487,6 @@ void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp) } } -void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp) -{ - if (MI->csh->detail) { - MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count - 1].vess = sp; - } -} - void arm64_op_addFP(MCInst *MI, float fp) { if (MI->csh->detail) { @@ -681,4 +586,4 @@ void AArch64_reg_access(const cs_insn *insn, } #endif -#endif \ No newline at end of file +#endif diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index d77654a85..2e414daf8 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -6,6 +6,8 @@ #include "capstone/capstone.h" +#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) + // return name of regiser in friendly string const char *AArch64_reg_name(csh handle, unsigned int reg); @@ -17,7 +19,7 @@ const char *AArch64_insn_name(csh handle, unsigned int id); const char *AArch64_group_name(csh handle, unsigned int id); // map instruction name to public instruction ID -arm64_reg AArch64_map_insn(const char *name); +arm64_insn AArch64_map_insn(const char *name); // map internal vregister to public register arm64_reg AArch64_map_vregister(unsigned int r); @@ -26,8 +28,6 @@ void arm64_op_addReg(MCInst *MI, int reg); void arm64_op_addVectorArrSpecifier(MCInst * MI, int sp); -void arm64_op_addVectorElementSizeSpecifier(MCInst * MI, int sp); - void arm64_op_addFP(MCInst *MI, float fp); void arm64_op_addImm(MCInst *MI, int64_t imm); diff --git a/arch/AArch64/AArch64MappingInsn.inc b/arch/AArch64/AArch64MappingInsn.inc index 02d07e71c..e9d2edd5d 100644 --- a/arch/AArch64/AArch64MappingInsn.inc +++ b/arch/AArch64/AArch64MappingInsn.inc @@ -1,5 +1,35 @@ -// This is auto-gen data for Capstone engine (www.capstone-engine.org) -// By Nguyen Anh Quynh +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + +{ + AArch64_ABS_ZPmZ_B, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ABS_ZPmZ_D, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ABS_ZPmZ_H, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ABS_ZPmZ_S, ARM64_INS_ABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, { AArch64_ABSv16i8, ARM64_INS_ABS, @@ -7,13959 +37,30320 @@ { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv1i64, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv2i32, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv2i64, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv4i16, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv4i32, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv8i16, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ABSv8i8, ARM64_INS_ABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_ADCSWr, ARM64_INS_ADC, + AArch64_ADCSWr, ARM64_INS_ADCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADCSXr, ARM64_INS_ADC, + AArch64_ADCSXr, ARM64_INS_ADCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADCWr, ARM64_INS_ADC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADCXr, ARM64_INS_ADC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ADDPL_XXI, ARM64_INS_ADDPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ADDPv16i8, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv2i32, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv2i64, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv2i64p, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv4i16, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv4i32, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv8i16, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDPv8i8, ARM64_INS_ADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_ADDSWri, ARM64_INS_ADD, + AArch64_ADDSWri, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADDSWrs, ARM64_INS_ADD, + AArch64_ADDSWrs, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADDSWrx, ARM64_INS_ADD, + AArch64_ADDSWrx, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADDSXri, ARM64_INS_ADD, + AArch64_ADDSXri, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADDSXrs, ARM64_INS_ADD, + AArch64_ADDSXrs, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADDSXrx, ARM64_INS_ADD, + AArch64_ADDSXrx, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ADDSXrx64, ARM64_INS_ADD, + AArch64_ADDSXrx64, ARM64_INS_ADDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_ADDVL_XXI, ARM64_INS_ADDVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ADDVv16i8v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDVv4i16v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDVv4i32v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDVv8i16v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDVv8i8v, ARM64_INS_ADDV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDWri, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDWrs, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDWrx, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDXri, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDXrs, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDXrx, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADDXrx64, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_ADD_ZI_B, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZI_D, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZI_H, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZI_S, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZPmZ_B, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZPmZ_D, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZPmZ_H, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZPmZ_S, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZZZ_B, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZZZ_D, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZZZ_H, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADD_ZZZ_S, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ADDv16i8, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv1i64, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv2i32, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv2i64, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv4i16, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv4i32, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv8i16, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADDv8i8, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ADR, ARM64_INS_ADR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ADRP, ARM64_INS_ADRP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_ADR_LSL_ZZZ_D_0, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_D_1, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_D_2, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_D_3, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_S_0, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_S_1, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_S_2, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_LSL_ZZZ_S_3, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_SXTW_ZZZ_D_0, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_SXTW_ZZZ_D_1, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_SXTW_ZZZ_D_2, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_SXTW_ZZZ_D_3, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_UXTW_ZZZ_D_0, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_UXTW_ZZZ_D_1, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_UXTW_ZZZ_D_2, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ADR_UXTW_ZZZ_D_3, ARM64_INS_ADR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_AESDrr, ARM64_INS_AESD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_AESErr, ARM64_INS_AESE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_AESIMCrr, ARM64_INS_AESIMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_AESMCrr, ARM64_INS_AESMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { - AArch64_ANDSWri, ARM64_INS_AND, + AArch64_ANDSWri, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ANDSWrs, ARM64_INS_AND, + AArch64_ANDSWrs, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ANDSXri, ARM64_INS_AND, + AArch64_ANDSXri, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ANDSXrs, ARM64_INS_AND, + AArch64_ANDSXrs, ARM64_INS_ANDS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_ANDS_PPzPP, ARM64_INS_ANDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ANDV_VPZ_B, ARM64_INS_ANDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ANDV_VPZ_D, ARM64_INS_ANDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ANDV_VPZ_H, ARM64_INS_ANDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ANDV_VPZ_S, ARM64_INS_ANDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ANDWri, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ANDWrs, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ANDXri, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ANDXrs, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_AND_PPzPP, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AND_ZI, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AND_ZPmZ_B, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AND_ZPmZ_D, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AND_ZPmZ_H, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AND_ZPmZ_S, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AND_ZZZ, ARM64_INS_AND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ANDv16i8, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ANDv8i8, ARM64_INS_AND, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ASRD_ZPmI_B, ARM64_INS_ASRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRD_ZPmI_D, ARM64_INS_ASRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRD_ZPmI_H, ARM64_INS_ASRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRD_ZPmI_S, ARM64_INS_ASRD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRR_ZPmZ_B, ARM64_INS_ASRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRR_ZPmZ_D, ARM64_INS_ASRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRR_ZPmZ_H, ARM64_INS_ASRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASRR_ZPmZ_S, ARM64_INS_ASRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ASRVWr, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_ASRVXr, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_ASR_WIDE_ZPmZ_B, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_WIDE_ZPmZ_H, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_WIDE_ZPmZ_S, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_WIDE_ZZZ_B, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_WIDE_ZZZ_H, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_WIDE_ZZZ_S, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmI_B, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmI_D, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmI_H, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmI_S, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmZ_B, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmZ_D, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmZ_H, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZPmZ_S, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZZI_B, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZZI_D, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZZI_H, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ASR_ZZI_S, ARM64_INS_ASR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTDA, ARM64_INS_AUTDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTDB, ARM64_INS_AUTDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTDZA, ARM64_INS_AUTDZA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTDZB, ARM64_INS_AUTDZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIA, ARM64_INS_AUTIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIA1716, ARM64_INS_AUTIA1716, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIASP, ARM64_INS_AUTIASP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIAZ, ARM64_INS_AUTIAZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIB, ARM64_INS_AUTIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIB1716, ARM64_INS_AUTIB1716, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIBSP, ARM64_INS_AUTIBSP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIBZ, ARM64_INS_AUTIBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIZA, ARM64_INS_AUTIZA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_AUTIZB, ARM64_INS_AUTIZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_B, ARM64_INS_B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + +{ + AArch64_BCAX, ARM64_INS_BCAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_BFMWri, ARM64_INS_BFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_BFMXri, ARM64_INS_BFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_BICSWrs, ARM64_INS_BIC, + AArch64_BICSWrs, ARM64_INS_BICS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_BICSXrs, ARM64_INS_BIC, + AArch64_BICSXrs, ARM64_INS_BICS, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_BICS_PPzPP, ARM64_INS_BICS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_BICWrs, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_BICXrs, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_BIC_PPzPP, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BIC_ZPmZ_B, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BIC_ZPmZ_D, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BIC_ZPmZ_H, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BIC_ZPmZ_S, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BIC_ZZZ, ARM64_INS_BIC, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_BICv16i8, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BICv2i32, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BICv4i16, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BICv4i32, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BICv8i16, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BICv8i8, ARM64_INS_BIC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BIFv16i8, ARM64_INS_BIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BIFv8i8, ARM64_INS_BIF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BITv16i8, ARM64_INS_BIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BITv8i8, ARM64_INS_BIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BL, ARM64_INS_BL, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_BLR, ARM64_INS_BLR, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1 #endif }, + +{ + AArch64_BLRAA, ARM64_INS_BLRAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BLRAAZ, ARM64_INS_BLRAAZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BLRAB, ARM64_INS_BLRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BLRABZ, ARM64_INS_BLRABZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_BR, ARM64_INS_BR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 1 #endif }, + +{ + AArch64_BRAA, ARM64_INS_BRAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRAAZ, ARM64_INS_BRAAZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRAB, ARM64_INS_BRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRABZ, ARM64_INS_BRABZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_BRK, ARM64_INS_BRK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_BRKAS_PPzP, ARM64_INS_BRKAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKA_PPmP, ARM64_INS_BRKA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKA_PPzP, ARM64_INS_BRKA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKBS_PPzP, ARM64_INS_BRKBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKB_PPmP, ARM64_INS_BRKB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKB_PPzP, ARM64_INS_BRKB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKNS_PPzP, ARM64_INS_BRKNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKN_PPzP, ARM64_INS_BRKN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKPAS_PPzPP, ARM64_INS_BRKPAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKPA_PPzPP, ARM64_INS_BRKPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKPBS_PPzPP, ARM64_INS_BRKPBS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_BRKPB_PPzPP, ARM64_INS_BRKPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_BSLv16i8, ARM64_INS_BSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_BSLv8i8, ARM64_INS_BSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_Bcc, ARM64_INS_B, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + +{ + AArch64_CASAB, ARM64_INS_CASAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASAH, ARM64_INS_CASAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASALB, ARM64_INS_CASALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASALH, ARM64_INS_CASALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASALW, ARM64_INS_CASAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASALX, ARM64_INS_CASAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASAW, ARM64_INS_CASA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASAX, ARM64_INS_CASA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASB, ARM64_INS_CASB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASH, ARM64_INS_CASH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASLB, ARM64_INS_CASLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASLH, ARM64_INS_CASLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASLW, ARM64_INS_CASL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASLX, ARM64_INS_CASL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPALW, ARM64_INS_CASPAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPALX, ARM64_INS_CASPAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPAW, ARM64_INS_CASPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPAX, ARM64_INS_CASPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPLW, ARM64_INS_CASPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPLX, ARM64_INS_CASPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPW, ARM64_INS_CASP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASPX, ARM64_INS_CASP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASW, ARM64_INS_CAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CASX, ARM64_INS_CAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_CBNZW, ARM64_INS_CBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_CBNZX, ARM64_INS_CBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_CBZW, ARM64_INS_CBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_CBZX, ARM64_INS_CBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_CCMNWi, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMNWr, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMNXi, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMNXr, ARM64_INS_CCMN, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMPWi, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMPWr, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMPXi, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CCMPXr, ARM64_INS_CCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_CFINV, ARM64_INS_CFINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_RPZ_B, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_RPZ_D, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_RPZ_H, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_RPZ_S, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_VPZ_B, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_VPZ_D, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_VPZ_H, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_VPZ_S, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_ZPZ_B, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_ZPZ_D, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_ZPZ_H, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTA_ZPZ_S, ARM64_INS_CLASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_RPZ_B, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_RPZ_D, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_RPZ_H, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_RPZ_S, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_VPZ_B, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_VPZ_D, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_VPZ_H, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_VPZ_S, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_ZPZ_B, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_ZPZ_D, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_ZPZ_H, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLASTB_ZPZ_S, ARM64_INS_CLASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_CLREX, ARM64_INS_CLREX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CLSWr, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CLSXr, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_CLS_ZPmZ_B, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLS_ZPmZ_D, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLS_ZPmZ_H, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLS_ZPmZ_S, ARM64_INS_CLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_CLSv16i8, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLSv2i32, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLSv4i16, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLSv4i32, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLSv8i16, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLSv8i8, ARM64_INS_CLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLZWr, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CLZXr, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_CLZ_ZPmZ_B, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLZ_ZPmZ_D, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLZ_ZPmZ_H, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CLZ_ZPmZ_S, ARM64_INS_CLZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_CLZv16i8, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLZv2i32, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLZv4i16, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLZv4i32, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLZv8i16, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CLZv8i8, ARM64_INS_CLZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv16i8, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv16i8rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv1i64, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv1i64rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv2i32, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv2i32rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv2i64, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv2i64rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv4i16, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv4i16rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv4i32, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv4i32rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv8i16, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv8i16rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv8i8, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMEQv8i8rz, ARM64_INS_CMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv16i8, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv16i8rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv1i64, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv1i64rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv2i32, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv2i32rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv2i64, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv2i64rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv4i16, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv4i16rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv4i32, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv4i32rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv8i16, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv8i16rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv8i8, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGEv8i8rz, ARM64_INS_CMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv16i8, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv16i8rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv1i64, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv1i64rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv2i32, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv2i32rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv2i64, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv2i64rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv4i16, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv4i16rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv4i32, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv4i32rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv8i16, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv8i16rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv8i8, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMGTv8i8rz, ARM64_INS_CMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv16i8, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv1i64, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv2i32, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv2i64, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv4i16, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv4i32, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv8i16, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHIv8i8, ARM64_INS_CMHI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv16i8, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv1i64, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv2i32, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv2i64, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv4i16, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv4i32, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv8i16, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMHSv8i8, ARM64_INS_CMHS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv16i8rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv1i64rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv2i32rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv2i64rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv4i16rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv4i32rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv8i16rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLEv8i8rz, ARM64_INS_CMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv16i8rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv1i64rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv2i32rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv2i64rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv4i16rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv4i32rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv8i16rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMLTv8i8rz, ARM64_INS_CMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_CMPEQ_PPzZI_B, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZI_D, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZI_H, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZI_S, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZZ_B, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZZ_D, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZZ_H, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_PPzZZ_S, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_WIDE_PPzZZ_B, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_WIDE_PPzZZ_H, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPEQ_WIDE_PPzZZ_S, ARM64_INS_CMPEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZI_B, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZI_D, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZI_H, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZI_S, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZZ_B, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZZ_D, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZZ_H, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_PPzZZ_S, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_WIDE_PPzZZ_B, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_WIDE_PPzZZ_H, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGE_WIDE_PPzZZ_S, ARM64_INS_CMPGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZI_B, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZI_D, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZI_H, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZI_S, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZZ_B, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZZ_D, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZZ_H, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_PPzZZ_S, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_WIDE_PPzZZ_B, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_WIDE_PPzZZ_H, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPGT_WIDE_PPzZZ_S, ARM64_INS_CMPGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZI_B, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZI_D, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZI_H, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZI_S, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZZ_B, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZZ_D, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZZ_H, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_PPzZZ_S, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_WIDE_PPzZZ_B, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_WIDE_PPzZZ_H, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHI_WIDE_PPzZZ_S, ARM64_INS_CMPHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZI_B, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZI_D, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZI_H, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZI_S, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZZ_B, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZZ_D, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZZ_H, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_PPzZZ_S, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_WIDE_PPzZZ_B, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_WIDE_PPzZZ_H, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPHS_WIDE_PPzZZ_S, ARM64_INS_CMPHS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_PPzZI_B, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_PPzZI_D, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_PPzZI_H, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_PPzZI_S, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_WIDE_PPzZZ_B, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_WIDE_PPzZZ_H, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLE_WIDE_PPzZZ_S, ARM64_INS_CMPLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_PPzZI_B, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_PPzZI_D, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_PPzZI_H, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_PPzZI_S, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_WIDE_PPzZZ_B, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_WIDE_PPzZZ_H, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLO_WIDE_PPzZZ_S, ARM64_INS_CMPLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_PPzZI_B, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_PPzZI_D, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_PPzZI_H, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_PPzZI_S, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_WIDE_PPzZZ_B, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_WIDE_PPzZZ_H, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLS_WIDE_PPzZZ_S, ARM64_INS_CMPLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_PPzZI_B, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_PPzZI_D, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_PPzZI_H, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_PPzZI_S, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_WIDE_PPzZZ_B, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_WIDE_PPzZZ_H, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPLT_WIDE_PPzZZ_S, ARM64_INS_CMPLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZI_B, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZI_D, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZI_H, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZI_S, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZZ_B, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZZ_D, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZZ_H, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_PPzZZ_S, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_WIDE_PPzZZ_B, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_WIDE_PPzZZ_H, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CMPNE_WIDE_PPzZZ_S, ARM64_INS_CMPNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_CMTSTv16i8, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv1i64, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv2i32, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv2i64, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv4i16, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv4i32, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv8i16, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CMTSTv8i8, ARM64_INS_CMTST, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_CNOT_ZPmZ_B, ARM64_INS_CNOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNOT_ZPmZ_D, ARM64_INS_CNOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNOT_ZPmZ_H, ARM64_INS_CNOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNOT_ZPmZ_S, ARM64_INS_CNOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTB_XPiI, ARM64_INS_CNTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTD_XPiI, ARM64_INS_CNTD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTH_XPiI, ARM64_INS_CNTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTP_XPP_B, ARM64_INS_CNTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTP_XPP_D, ARM64_INS_CNTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTP_XPP_H, ARM64_INS_CNTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTP_XPP_S, ARM64_INS_CNTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNTW_XPiI, ARM64_INS_CNTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNT_ZPmZ_B, ARM64_INS_CNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNT_ZPmZ_D, ARM64_INS_CNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNT_ZPmZ_H, ARM64_INS_CNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CNT_ZPmZ_S, ARM64_INS_CNT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_CNTv16i8, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CNTv8i8, ARM64_INS_CNT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_CPYi16, ARM64_INS_MOV, + AArch64_COMPACT_ZPZ_D, ARM64_INS_COMPACT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_COMPACT_ZPZ_S, ARM64_INS_COMPACT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmI_B, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmI_D, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmI_H, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmI_S, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmR_B, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmR_D, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmR_H, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmR_S, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmV_B, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmV_D, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmV_H, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPmV_S, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPzI_B, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPzI_D, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPzI_H, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPY_ZPzI_S, ARM64_INS_CPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CPYi16, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_CPYi32, ARM64_INS_MOV, + AArch64_CPYi32, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_CPYi64, ARM64_INS_MOV, + AArch64_CPYi64, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_CPYi8, ARM64_INS_MOV, + AArch64_CPYi8, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_CRC32Brr, ARM64_INS_CRC32B, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32CBrr, ARM64_INS_CRC32CB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32CHrr, ARM64_INS_CRC32CH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32CWrr, ARM64_INS_CRC32CW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32CXrr, ARM64_INS_CRC32CX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32Hrr, ARM64_INS_CRC32H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32Wrr, ARM64_INS_CRC32W, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CRC32Xrr, ARM64_INS_CRC32X, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRC, 0 }, 0, 0 #endif }, + { AArch64_CSELWr, ARM64_INS_CSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_CSELXr, ARM64_INS_CSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_CSINCWr, ARM64_INS_CSINC, + AArch64_CSINCWr, ARM64_INS_CINC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_CSINCXr, ARM64_INS_CSINC, + AArch64_CSINCXr, ARM64_INS_CINC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_CSINVWr, ARM64_INS_CSINV, + AArch64_CSINVWr, ARM64_INS_CINV, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_CSINVXr, ARM64_INS_CSINV, + AArch64_CSINVXr, ARM64_INS_CINV, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_CSNEGWr, ARM64_INS_CSNEG, + AArch64_CSNEGWr, ARM64_INS_CNEG, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_CSNEGXr, ARM64_INS_CSNEG, + AArch64_CSNEGXr, ARM64_INS_CNEG, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_CTERMEQ_WW, ARM64_INS_CTERMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CTERMEQ_XX, ARM64_INS_CTERMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CTERMNE_WW, ARM64_INS_CTERMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_CTERMNE_XX, ARM64_INS_CTERMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_DCPS1, ARM64_INS_DCPS1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_DCPS2, ARM64_INS_DCPS2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_DCPS3, ARM64_INS_DCPS3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_DECB_XPiI, ARM64_INS_DECB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECD_XPiI, ARM64_INS_DECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECD_ZPiI, ARM64_INS_DECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECH_XPiI, ARM64_INS_DECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECH_ZPiI, ARM64_INS_DECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_XP_B, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_XP_D, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_XP_H, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_XP_S, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_ZP_D, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_ZP_H, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECP_ZP_S, ARM64_INS_DECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECW_XPiI, ARM64_INS_DECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DECW_ZPiI, ARM64_INS_DECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_DMB, ARM64_INS_DMB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_DRPS, ARM64_INS_DRPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_DSB, ARM64_INS_DSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_DUPM_ZI, ARM64_INS_DUPM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZI_B, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZI_D, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZI_H, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZI_S, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZR_B, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZR_D, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZR_H, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZR_S, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZZI_B, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZZI_D, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZZI_H, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZZI_Q, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_DUP_ZZI_S, ARM64_INS_DUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_DUPv16i8gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv16i8lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv2i32gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv2i32lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv2i64gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv2i64lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv4i16gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv4i16lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv4i32gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv4i32lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv8i16gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv8i16lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv8i8gpr, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_DUPv8i8lane, ARM64_INS_DUP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_EONWrs, ARM64_INS_EON, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_EONXrs, ARM64_INS_EON, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_EORWri, ARM64_INS_EOR, + AArch64_EOR3, ARM64_INS_EOR3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_EORS_PPzPP, ARM64_INS_EORS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EORV_VPZ_B, ARM64_INS_EORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EORV_VPZ_D, ARM64_INS_EORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EORV_VPZ_H, ARM64_INS_EORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EORV_VPZ_S, ARM64_INS_EORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EORWri, ARM64_INS_EON, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_EORWrs, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_EORXri, ARM64_INS_EOR, + AArch64_EORXri, ARM64_INS_EON, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_EORXrs, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_EOR_PPzPP, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EOR_ZI, ARM64_INS_EON, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EOR_ZPmZ_B, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EOR_ZPmZ_D, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EOR_ZPmZ_H, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EOR_ZPmZ_S, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_EOR_ZZZ, ARM64_INS_EOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_EORv16i8, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_EORv8i8, ARM64_INS_EOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ERET, ARM64_INS_ERET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_ERETAA, ARM64_INS_ERETAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ERETAB, ARM64_INS_ERETAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_EXTRWrri, ARM64_INS_EXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_EXTRXrri, ARM64_INS_EXTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_EXT_ZZI, ARM64_INS_EXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_EXTv16i8, ARM64_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_EXTv8i8, ARM64_INS_EXT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FABD16, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABD32, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FABD64, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FABD_ZPmZ_D, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FABD_ZPmZ_H, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FABD_ZPmZ_S, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABDv2f32, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FABDv2f64, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FABDv4f16, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABDv4f32, ARM64_INS_FABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FABDv8f16, ARM64_INS_FABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABSDr, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FABSHr, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABSSr, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FABS_ZPmZ_D, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FABS_ZPmZ_H, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FABS_ZPmZ_S, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABSv2f32, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FABSv2f64, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FABSv4f16, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FABSv4f32, ARM64_INS_FABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FABSv8f16, ARM64_INS_FABS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FACGE16, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FACGE32, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FACGE64, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FACGE_PPzZZ_D, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FACGE_PPzZZ_H, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FACGE_PPzZZ_S, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FACGEv2f32, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FACGEv2f64, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FACGEv4f16, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FACGEv4f32, ARM64_INS_FACGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FACGEv8f16, ARM64_INS_FACGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FACGT16, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FACGT32, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FACGT64, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FACGT_PPzZZ_D, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FACGT_PPzZZ_H, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FACGT_PPzZZ_S, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FACGTv2f32, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FACGTv2f64, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FACGTv4f16, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FACGTv4f32, ARM64_INS_FACGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FACGTv8f16, ARM64_INS_FACGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADDA_VPZ_D, ARM64_INS_FADDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADDA_VPZ_H, ARM64_INS_FADDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADDA_VPZ_S, ARM64_INS_FADDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDDrr, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDHrr, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDPv2f32, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FADDPv2f64, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDPv2i16p, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDPv2i32p, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FADDPv2i64p, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDPv4f16, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDPv4f32, ARM64_INS_FADDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDPv8f16, ARM64_INS_FADDP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDSrr, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDV_VPZ_D, ARM64_INS_FADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADDV_VPZ_H, ARM64_INS_FADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADDV_VPZ_S, ARM64_INS_FADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZPmI_D, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZPmI_H, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZPmI_S, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZPmZ_D, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZPmZ_H, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZPmZ_S, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZZZ_D, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZZZ_H, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FADD_ZZZ_S, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDv2f32, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FADDv2f64, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDv4f16, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FADDv4f32, ARM64_INS_FADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FADDv8f16, ARM64_INS_FADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADD_ZPmZ_D, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADD_ZPmZ_H, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADD_ZPmZ_S, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADDv2f32, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADDv2f64, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADDv4f16, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADDv4f32, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCADDv8f16, ARM64_INS_FCADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCCMPDrr, ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCCMPEDrr, ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCCMPEHrr, ARM64_INS_FCCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCCMPESrr, ARM64_INS_FCCMPE, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCCMPHrr, ARM64_INS_FCCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCCMPSrr, ARM64_INS_FCCMP, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMEQ16, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMEQ32, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMEQ64, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMEQ_PPzZ0_D, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQ_PPzZ0_H, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQ_PPzZ0_S, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQ_PPzZZ_D, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQ_PPzZZ_H, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQ_PPzZZ_S, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQv1i16rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMEQv2f32, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMEQv2f64, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMEQv4f16, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMEQv4f32, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMEQv4i16rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMEQv8f16, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMEQv8i16rz, ARM64_INS_FCMEQ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGE16, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGE32, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGE64, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGE_PPzZ0_D, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGE_PPzZ0_H, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGE_PPzZ0_S, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGE_PPzZZ_D, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGE_PPzZZ_H, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGE_PPzZZ_S, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGEv1i16rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGEv2f32, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGEv2f64, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGEv4f16, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGEv4f32, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGEv4i16rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGEv8f16, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGEv8i16rz, ARM64_INS_FCMGE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGT16, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGT32, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGT64, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGT_PPzZ0_D, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGT_PPzZ0_H, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGT_PPzZ0_S, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGT_PPzZZ_D, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGT_PPzZZ_H, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGT_PPzZZ_S, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGTv1i16rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGTv2f32, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGTv2f64, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGTv4f16, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGTv4f32, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGTv4i16rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMGTv8f16, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMGTv8i16rz, ARM64_INS_FCMGT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLA_ZPmZZ_D, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLA_ZPmZZ_H, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLA_ZPmZZ_S, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLA_ZZZI_H, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLA_ZZZI_S, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv2f32, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv2f64, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv4f16, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv4f16_indexed, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv4f32, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv4f32_indexed, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv8f16, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLAv8f16_indexed, ARM64_INS_FCMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLE_PPzZ0_D, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLE_PPzZ0_H, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLE_PPzZ0_S, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLEv1i16rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMLEv4i16rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMLEv8i16rz, ARM64_INS_FCMLE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLT_PPzZ0_D, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLT_PPzZ0_H, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLT_PPzZ0_S, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMLTv1i16rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMLTv4i16rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMLTv8i16rz, ARM64_INS_FCMLT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMNE_PPzZ0_D, ARM64_INS_FCMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMNE_PPzZ0_H, ARM64_INS_FCMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMNE_PPzZ0_S, ARM64_INS_FCMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMNE_PPzZZ_D, ARM64_INS_FCMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMNE_PPzZZ_H, ARM64_INS_FCMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMNE_PPzZZ_S, ARM64_INS_FCMNE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMPDri, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCMPDrr, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCMPEDri, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCMPEDrr, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMPEHri, ARM64_INS_FCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMPEHrr, ARM64_INS_FCMPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMPESri, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCMPESrr, ARM64_INS_FCMPE, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMPHri, ARM64_INS_FCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMPHrr, ARM64_INS_FCMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCMPSri, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCMPSrr, ARM64_INS_FCMP, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCMUO_PPzZZ_D, ARM64_INS_FCMUO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMUO_PPzZZ_H, ARM64_INS_FCMUO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCMUO_PPzZZ_S, ARM64_INS_FCMUO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCPY_ZPmI_D, ARM64_INS_FCPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCPY_ZPmI_H, ARM64_INS_FCPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCPY_ZPmI_S, ARM64_INS_FCPY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCSELDrrr, ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCSELHrrr, ARM64_INS_FCSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCSELSrrr, ARM64_INS_FCSEL, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTASUWDr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTASUWHr, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTASUWSr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTASUXDr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTASUXHr, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTASUXSr, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTASv1f16, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTASv1i32, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTASv1i64, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTASv2f32, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTASv2f64, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTASv4f16, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTASv4f32, ARM64_INS_FCVTAS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTASv8f16, ARM64_INS_FCVTAS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTAUUWHr, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTAUUXHr, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTAUv1f16, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTAUv4f16, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTAUv8f16, ARM64_INS_FCVTAU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTDHr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTDSr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTHDr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTHSr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTLv2i32, ARM64_INS_FCVTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTLv4i16, ARM64_INS_FCVTL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTLv4i32, ARM64_INS_FCVTL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTLv8i16, ARM64_INS_FCVTL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMSUWHr, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMSUXHr, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMSv1f16, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMSv4f16, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMSv8f16, ARM64_INS_FCVTMS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMUUWHr, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMUUXHr, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMUv1f16, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMUv4f16, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTMUv8f16, ARM64_INS_FCVTMU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNSUWHr, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNSUXHr, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNSv1f16, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNSv4f16, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNSv8f16, ARM64_INS_FCVTNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNUUWHr, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNUUXHr, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNUv1f16, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNUv4f16, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTNUv8f16, ARM64_INS_FCVTNU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTNv2i32, ARM64_INS_FCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNv4i16, ARM64_INS_FCVTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNv4i32, ARM64_INS_FCVTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTNv8i16, ARM64_INS_FCVTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPSUWHr, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPSUXHr, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPSv1f16, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPSv4f16, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPSv8f16, ARM64_INS_FCVTPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPUUWHr, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPUUXHr, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPUv1f16, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPUv4f16, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTPUv8f16, ARM64_INS_FCVTPU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTSDr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTSHr, ARM64_INS_FCVT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSSWHri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSSXHri, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSUWHr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSUXHr, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_DtoD, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_DtoS, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_HtoD, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_HtoH, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_HtoS, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_StoD, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS, + AArch64_FCVTZS_ZPmZ_StoS, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_FCVTZSd, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSh, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSs, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSv1f16, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSv4f16, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSv4i16_shift, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZSv8f16, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVTZSv8i16_shift, ARM64_INS_FCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUSWHri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUSXHri, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUUWHr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUUXHr, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_DtoD, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_DtoS, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_HtoD, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_HtoH, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_HtoS, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_StoD, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU, + AArch64_FCVTZU_ZPmZ_StoS, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 -#endif -}, -{ - AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 + { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_FCVTZUd, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUh, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUs, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUv1f16, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUv4f16, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUv4i16_shift, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FCVTZUv8f16, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVTZUv8i16_shift, ARM64_INS_FCVTZU, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVT_ZPmZ_DtoH, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVT_ZPmZ_DtoS, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVT_ZPmZ_HtoD, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVT_ZPmZ_HtoS, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVT_ZPmZ_StoD, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FCVT_ZPmZ_StoH, ARM64_INS_FCVT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FDIVDrr, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FDIVHrr, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDIVR_ZPmZ_D, ARM64_INS_FDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDIVR_ZPmZ_H, ARM64_INS_FDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDIVR_ZPmZ_S, ARM64_INS_FDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FDIVSrr, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FDIV_ZPmZ_D, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDIV_ZPmZ_H, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDIV_ZPmZ_S, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FDIVv2f32, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FDIVv2f64, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FDIVv4f16, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FDIVv4f32, ARM64_INS_FDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FDIVv8f16, ARM64_INS_FDIV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDUP_ZI_D, ARM64_INS_FDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDUP_ZI_H, ARM64_INS_FDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FDUP_ZI_S, ARM64_INS_FDUP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FEXPA_ZZ_D, ARM64_INS_FEXPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FEXPA_ZZ_H, ARM64_INS_FEXPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FEXPA_ZZ_S, ARM64_INS_FEXPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FJCVTZS, ARM64_INS_FJCVTZS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMADDDrrr, ARM64_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMADDHrrr, ARM64_INS_FMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMADDSrrr, ARM64_INS_FMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAD_ZPmZZ_D, ARM64_INS_FMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAD_ZPmZZ_H, ARM64_INS_FMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAD_ZPmZZ_S, ARM64_INS_FMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXDrr, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXHrr, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMDrr, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMHrr, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMPv2i16p, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMPv4f16, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMPv8f16, ARM64_INS_FMAXNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMSrr, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMV_VPZ_D, ARM64_INS_FMAXNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNMV_VPZ_H, ARM64_INS_FMAXNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNMV_VPZ_S, ARM64_INS_FMAXNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNMVv4i16v, ARM64_INS_FMAXNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMVv8i16v, ARM64_INS_FMAXNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNM_ZPmI_D, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNM_ZPmI_H, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNM_ZPmI_S, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNM_ZPmZ_D, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNM_ZPmZ_H, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXNM_ZPmZ_S, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMv4f16, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXNMv8f16, ARM64_INS_FMAXNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXPv2f32, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMAXPv2f64, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXPv2i16p, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXPv2i32p, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMAXPv2i64p, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXPv4f16, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXPv4f32, ARM64_INS_FMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXPv8f16, ARM64_INS_FMAXP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXSrr, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXV_VPZ_D, ARM64_INS_FMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXV_VPZ_H, ARM64_INS_FMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXV_VPZ_S, ARM64_INS_FMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAXVv4i16v, ARM64_INS_FMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXVv4i32v, ARM64_INS_FMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXVv8i16v, ARM64_INS_FMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAX_ZPmI_D, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAX_ZPmI_H, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAX_ZPmI_S, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAX_ZPmZ_D, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAX_ZPmZ_H, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMAX_ZPmZ_S, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXv2f32, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMAXv2f64, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXv4f16, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMAXv4f32, ARM64_INS_FMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMAXv8f16, ARM64_INS_FMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINDrr, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINHrr, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMDrr, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMHrr, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMPv2i16p, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMPv4f16, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMPv8f16, ARM64_INS_FMINNMP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMSrr, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMV_VPZ_D, ARM64_INS_FMINNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNMV_VPZ_H, ARM64_INS_FMINNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNMV_VPZ_S, ARM64_INS_FMINNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNMVv4i16v, ARM64_INS_FMINNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMVv8i16v, ARM64_INS_FMINNMV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNM_ZPmI_D, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNM_ZPmI_H, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNM_ZPmI_S, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNM_ZPmZ_D, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNM_ZPmZ_H, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINNM_ZPmZ_S, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMv2f32, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMINNMv2f64, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMv4f16, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINNMv4f32, ARM64_INS_FMINNM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINNMv8f16, ARM64_INS_FMINNM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINPv2f32, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMINPv2f64, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINPv2i16p, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINPv2i32p, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMINPv2i64p, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINPv4f16, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINPv4f32, ARM64_INS_FMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINPv8f16, ARM64_INS_FMINP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINSrr, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINV_VPZ_D, ARM64_INS_FMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINV_VPZ_H, ARM64_INS_FMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINV_VPZ_S, ARM64_INS_FMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMINVv4i16v, ARM64_INS_FMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINVv4i32v, ARM64_INS_FMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINVv8i16v, ARM64_INS_FMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMIN_ZPmI_D, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMIN_ZPmI_H, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMIN_ZPmI_S, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMIN_ZPmZ_D, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMIN_ZPmZ_H, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMIN_ZPmZ_S, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINv2f32, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMINv2f64, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINv4f16, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMINv4f32, ARM64_INS_FMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMINv8f16, ARM64_INS_FMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLA_ZPmZZ_D, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLA_ZPmZZ_H, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLA_ZPmZZ_S, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLA_ZZZI_D, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLA_ZZZI_H, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLA_ZZZI_S, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLAv1i16_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLAv2f32, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLAv2f64, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMLAv4f16, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMLAv4f32, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMLAv4i16_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMLAv8f16, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLAv8i16_indexed, ARM64_INS_FMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLS_ZPmZZ_D, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLS_ZPmZZ_H, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLS_ZPmZZ_S, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLS_ZZZI_D, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLS_ZZZI_H, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLS_ZZZI_S, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLSv1i16_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLSv2f32, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLSv2f64, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMLSv4f16, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMLSv4f32, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMLSv4i16_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMLSv8f16, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMLSv8i16_indexed, ARM64_INS_FMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMOVDXHighr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVDXr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVDi, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVDr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMOVHWr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMOVHXr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMOVHi, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMOVHr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMOVSWr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVSi, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVSr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMOVWHr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMOVWSr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVXDHighr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMOVXDr, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMOVXHr, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMOVv2f32_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMOVv2f64_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMOVv4f16_ns, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMOVv4f32_ns, ARM64_INS_FMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMOVv8f16_ns, ARM64_INS_FMOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMSB_ZPmZZ_D, ARM64_INS_FMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMSB_ZPmZZ_H, ARM64_INS_FMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMSB_ZPmZZ_S, ARM64_INS_FMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMSUBDrrr, ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMSUBHrrr, ARM64_INS_FMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMSUBSrrr, ARM64_INS_FMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FMULDrr, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULHrr, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULSrr, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULX16, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULX32, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULX64, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULX_ZPmZ_D, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMULX_ZPmZ_H, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMULX_ZPmZ_S, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMULXv1i16_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULXv2f32, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULXv2f64, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULXv4f16, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULXv4f32, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULXv4i16_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULXv8f16, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMULXv8i16_indexed, ARM64_INS_FMULX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZPmI_D, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZPmI_H, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZPmI_S, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZPmZ_D, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZPmZ_H, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZPmZ_S, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZZZI_D, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZZZI_H, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZZZI_S, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZZZ_D, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZZZ_H, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMUL_ZZZ_S, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMULv1i16_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULv1i32_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULv1i64_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULv2f32, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULv2f64, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULv2i32_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FMULv2i64_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULv4f16, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULv4f32, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULv4i16_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FMULv4i32_indexed, ARM64_INS_FMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FMULv8f16, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FMULv8i16_indexed, ARM64_INS_FMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNEGDr, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FNEGHr, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNEGSr, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FNEG_ZPmZ_D, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNEG_ZPmZ_H, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNEG_ZPmZ_S, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNEGv2f32, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FNEGv2f64, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FNEGv4f16, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNEGv4f32, ARM64_INS_FNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FNEGv8f16, ARM64_INS_FNEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNMADDDrrr, ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FNMADDHrrr, ARM64_INS_FNMADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNMADDSrrr, ARM64_INS_FNMADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FNMAD_ZPmZZ_D, ARM64_INS_FNMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMAD_ZPmZZ_H, ARM64_INS_FNMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMAD_ZPmZZ_S, ARM64_INS_FNMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMLA_ZPmZZ_D, ARM64_INS_FNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMLA_ZPmZZ_H, ARM64_INS_FNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMLA_ZPmZZ_S, ARM64_INS_FNMLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMLS_ZPmZZ_D, ARM64_INS_FNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMLS_ZPmZZ_H, ARM64_INS_FNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMLS_ZPmZZ_S, ARM64_INS_FNMLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMSB_ZPmZZ_D, ARM64_INS_FNMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMSB_ZPmZZ_H, ARM64_INS_FNMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FNMSB_ZPmZZ_S, ARM64_INS_FNMSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FNMSUBHrrr, ARM64_INS_FNMSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_FNMULDrr, ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FNMULHrr, ARM64_INS_FNMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FNMULSrr, ARM64_INS_FNMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRECPE_ZZ_D, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPE_ZZ_H, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPE_ZZ_S, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPEv1f16, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRECPEv1i32, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRECPEv1i64, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRECPEv2f32, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRECPEv2f64, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRECPEv4f16, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRECPEv4f32, ARM64_INS_FRECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRECPEv8f16, ARM64_INS_FRECPE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPS16, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRECPS32, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRECPS64, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRECPS_ZZZ_D, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPS_ZZZ_H, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPS_ZZZ_S, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRECPSv2f32, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRECPSv2f64, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRECPSv4f16, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRECPSv4f32, ARM64_INS_FRECPS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRECPSv8f16, ARM64_INS_FRECPS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPX_ZPmZ_D, ARM64_INS_FRECPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPX_ZPmZ_H, ARM64_INS_FRECPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPX_ZPmZ_S, ARM64_INS_FRECPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRECPXv1f16, ARM64_INS_FRECPX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRECPXv1i32, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRECPXv1i64, ARM64_INS_FRECPX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTADr, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTAHr, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTASr, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTA_ZPmZ_D, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTA_ZPmZ_H, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTA_ZPmZ_S, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTAv2f32, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTAv2f64, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTAv4f16, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTAv4f32, ARM64_INS_FRINTA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTAv8f16, ARM64_INS_FRINTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTIDr, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTIHr, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTISr, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTI_ZPmZ_D, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTI_ZPmZ_H, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTI_ZPmZ_S, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTIv2f32, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTIv2f64, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTIv4f16, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTIv4f32, ARM64_INS_FRINTI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTIv8f16, ARM64_INS_FRINTI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTMDr, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTMHr, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTMSr, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTM_ZPmZ_D, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTM_ZPmZ_H, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTM_ZPmZ_S, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTMv2f32, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTMv2f64, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTMv4f16, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTMv4f32, ARM64_INS_FRINTM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTMv8f16, ARM64_INS_FRINTM, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTNDr, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTNHr, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTNSr, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTN_ZPmZ_D, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTN_ZPmZ_H, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTN_ZPmZ_S, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTNv2f32, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTNv2f64, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTNv4f16, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTNv4f32, ARM64_INS_FRINTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTNv8f16, ARM64_INS_FRINTN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTPDr, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTPHr, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTPSr, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTP_ZPmZ_D, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTP_ZPmZ_H, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTP_ZPmZ_S, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTPv2f32, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTPv2f64, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTPv4f16, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTPv4f32, ARM64_INS_FRINTP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTPv8f16, ARM64_INS_FRINTP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTXDr, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTXHr, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTXSr, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTX_ZPmZ_D, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTX_ZPmZ_H, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTX_ZPmZ_S, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTXv2f32, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTXv2f64, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTXv4f16, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTXv4f32, ARM64_INS_FRINTX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTXv8f16, ARM64_INS_FRINTX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTZDr, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTZHr, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTZSr, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTZ_ZPmZ_D, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTZ_ZPmZ_H, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRINTZ_ZPmZ_S, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTZv2f32, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRINTZv2f64, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTZv4f16, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRINTZv4f32, ARM64_INS_FRINTZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRINTZv8f16, ARM64_INS_FRINTZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTE_ZZ_D, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTE_ZZ_H, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTE_ZZ_S, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTEv1f16, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRSQRTEv4f16, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRSQRTEv8f16, ARM64_INS_FRSQRTE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTS16, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRSQRTS32, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRSQRTS64, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRSQRTS_ZZZ_D, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTS_ZZZ_H, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FRSQRTS_ZZZ_S, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRSQRTSv4f16, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FRSQRTSv8f16, ARM64_INS_FRSQRTS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSCALE_ZPmZ_D, ARM64_INS_FSCALE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSCALE_ZPmZ_H, ARM64_INS_FSCALE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSCALE_ZPmZ_S, ARM64_INS_FSCALE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSQRTDr, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FSQRTHr, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSQRTSr, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FSQRT_ZPmZ_D, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSQRT_ZPmZ_H, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSQRT_ZPmZ_S, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSQRTv2f32, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FSQRTv2f64, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FSQRTv4f16, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSQRTv4f32, ARM64_INS_FSQRT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FSQRTv8f16, ARM64_INS_FSQRT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSUBDrr, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FSUBHrr, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUBR_ZPmI_D, ARM64_INS_FSUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUBR_ZPmI_H, ARM64_INS_FSUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUBR_ZPmI_S, ARM64_INS_FSUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUBR_ZPmZ_D, ARM64_INS_FSUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUBR_ZPmZ_H, ARM64_INS_FSUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUBR_ZPmZ_S, ARM64_INS_FSUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSUBSrr, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_FSUB_ZPmI_D, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZPmI_H, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZPmI_S, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZPmZ_D, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZPmZ_H, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZPmZ_S, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZZZ_D, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZZZ_H, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FSUB_ZZZ_S, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSUBv2f32, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_FSUBv2f64, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_FSUBv4f16, ARM64_INS_FSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_FSUBv4f32, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_HINT, ARM64_INS_HINT, + AArch64_FSUBv8f16, ARM64_INS_FSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_FTMAD_ZZI_D, ARM64_INS_FTMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTMAD_ZZI_H, ARM64_INS_FTMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTMAD_ZZI_S, ARM64_INS_FTMAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTSMUL_ZZZ_D, ARM64_INS_FTSMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTSMUL_ZZZ_H, ARM64_INS_FTSMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTSMUL_ZZZ_S, ARM64_INS_FTSMUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTSSEL_ZZZ_D, ARM64_INS_FTSSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTSSEL_ZZZ_H, ARM64_INS_FTSSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_FTSSEL_ZZZ_S, ARM64_INS_FTSSEL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_D_IMM_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_D_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_D_SXTW_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_D_UXTW_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_S_IMM_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_S_SXTW_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1B_S_UXTW_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_IMM_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_SCALED_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_SXTW_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_SXTW_SCALED_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_UXTW_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1D_UXTW_SCALED_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_IMM_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_SCALED_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_SXTW_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_SXTW_SCALED_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_UXTW_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_D_UXTW_SCALED_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_S_IMM_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_S_SXTW_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_S_SXTW_SCALED_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_S_UXTW_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1H_S_UXTW_SCALED_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_D_IMM_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_D_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_D_SXTW_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_D_UXTW_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_S_IMM_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_S_SXTW_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SB_S_UXTW_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_IMM_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_SCALED_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_SXTW_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_SXTW_SCALED_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_UXTW_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_D_UXTW_SCALED_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_S_IMM_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_S_SXTW_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_S_SXTW_SCALED_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_S_UXTW_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SH_S_UXTW_SCALED_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_IMM_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_SCALED_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_SXTW_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_SXTW_SCALED_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_UXTW_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1SW_D_UXTW_SCALED_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_IMM_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_SCALED_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_SXTW_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_SXTW_SCALED_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_UXTW_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_D_UXTW_SCALED_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_IMM_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_SXTW_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_SXTW_SCALED_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_UXTW_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLD1W_UXTW_SCALED_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_D_IMM_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_D_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_D_SXTW_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_D_UXTW_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_S_IMM_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_S_SXTW_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1B_S_UXTW_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_IMM_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_SCALED_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_SXTW_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_SXTW_SCALED_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_UXTW_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1D_UXTW_SCALED_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_IMM_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_SCALED_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_SXTW_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_UXTW_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_S_IMM_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_S_SXTW_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_S_SXTW_SCALED_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_S_UXTW_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1H_S_UXTW_SCALED_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_D_IMM_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_D_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_D_SXTW_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_D_UXTW_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_S_IMM_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_S_SXTW_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SB_S_UXTW_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_IMM_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_SCALED_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_SXTW_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_UXTW_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_S_IMM_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_S_SXTW_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_S_UXTW_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_IMM_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_SCALED_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_SXTW_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_UXTW_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_IMM_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_SCALED_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_SXTW_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_SXTW_SCALED_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_UXTW_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_D_UXTW_SCALED_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_IMM_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_SXTW_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_SXTW_SCALED_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_UXTW_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_GLDFF1W_UXTW_SCALED_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_HINT, ARM64_INS_CSDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_HLT, ARM64_INS_HLT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_HVC, ARM64_INS_HVC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_INCB_XPiI, ARM64_INS_INCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCD_XPiI, ARM64_INS_INCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCD_ZPiI, ARM64_INS_INCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCH_XPiI, ARM64_INS_INCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCH_ZPiI, ARM64_INS_INCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_XP_B, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_XP_D, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_XP_H, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_XP_S, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_ZP_D, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_ZP_H, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCP_ZP_S, ARM64_INS_INCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCW_XPiI, ARM64_INS_INCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INCW_ZPiI, ARM64_INS_INCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_II_B, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_II_D, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_II_H, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_II_S, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_IR_B, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_IR_D, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_IR_H, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_IR_S, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RI_B, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RI_D, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RI_H, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RI_S, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RR_B, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RR_D, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RR_H, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INDEX_RR_S, ARM64_INS_INDEX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZR_B, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZR_D, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZR_H, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZR_S, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZV_B, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZV_D, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZV_H, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_INSR_ZV_S, ARM64_INS_INSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_INSvi16gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi16lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi32gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi32lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi64gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi64lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi8gpr, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_INSvi8lane, ARM64_INS_INS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ISB, ARM64_INS_ISB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LASTA_RPZ_B, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_RPZ_D, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_RPZ_H, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_RPZ_S, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_VPZ_B, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_VPZ_D, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_VPZ_H, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTA_VPZ_S, ARM64_INS_LASTA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_RPZ_B, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_RPZ_D, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_RPZ_H, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_RPZ_S, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_VPZ_B, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_VPZ_D, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_VPZ_H, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LASTB_VPZ_S, ARM64_INS_LASTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_D, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_D_IMM_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_H, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_H_IMM_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_IMM_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_S, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1B_S_IMM_REAL, ARM64_INS_LD1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1D, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1D_IMM_REAL, ARM64_INS_LD1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD1Fourv16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Fourv8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD1H, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1H_D, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1H_D_IMM_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1H_IMM_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1H_S, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1H_S_IMM_REAL, ARM64_INS_LD1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD1Onev16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Onev8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD1RB_D_IMM, ARM64_INS_LD1RB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RB_H_IMM, ARM64_INS_LD1RB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RB_IMM, ARM64_INS_LD1RB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RB_S_IMM, ARM64_INS_LD1RB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RD_IMM, ARM64_INS_LD1RD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RH_D_IMM, ARM64_INS_LD1RH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RH_IMM, ARM64_INS_LD1RH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RH_S_IMM, ARM64_INS_LD1RH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_B, ARM64_INS_LD1RQB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_B_IMM, ARM64_INS_LD1RQB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_D, ARM64_INS_LD1RQD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_D_IMM, ARM64_INS_LD1RQD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_H, ARM64_INS_LD1RQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_H_IMM, ARM64_INS_LD1RQH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_W, ARM64_INS_LD1RQW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RQ_W_IMM, ARM64_INS_LD1RQW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RSB_D_IMM, ARM64_INS_LD1RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RSB_H_IMM, ARM64_INS_LD1RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RSB_S_IMM, ARM64_INS_LD1RSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RSH_D_IMM, ARM64_INS_LD1RSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RSH_S_IMM, ARM64_INS_LD1RSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RSW_IMM, ARM64_INS_LD1RSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RW_D_IMM, ARM64_INS_LD1RW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1RW_IMM, ARM64_INS_LD1RW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD1Rv16b, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv16b_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv1d, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv1d_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv2d, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv2d_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv2s, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv2s_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv4h, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv4h_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv4s, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv4s_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv8b, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv8b_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv8h, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Rv8h_POST, ARM64_INS_LD1R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD1SB_D, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SB_D_IMM_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SB_H, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SB_H_IMM_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SB_S, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SB_S_IMM_REAL, ARM64_INS_LD1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SH_D, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SH_D_IMM_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SH_S, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SH_S_IMM_REAL, ARM64_INS_LD1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SW_D, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1SW_D_IMM_REAL, ARM64_INS_LD1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD1Threev16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Threev8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov16b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov16b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov1d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov1d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov2d, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov2d_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov2s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov2s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov4h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov4h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov4s, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov4s_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov8b, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov8b_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov8h, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1Twov8h_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD1W, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1W_D, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1W_D_IMM_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD1W_IMM_REAL, ARM64_INS_LD1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD1i16, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i16_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i32, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i32_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i64, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i64_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i8, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD1i8_POST, ARM64_INS_LD1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD2B, ARM64_INS_LD2B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD2B_IMM, ARM64_INS_LD2B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD2D, ARM64_INS_LD2D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD2D_IMM, ARM64_INS_LD2D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD2H, ARM64_INS_LD2H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD2H_IMM, ARM64_INS_LD2H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD2Rv16b, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv16b_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv1d, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv1d_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv2d, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv2d_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv2s, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv2s_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv4h, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv4h_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv4s, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv4s_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv8b, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv8b_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv8h, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Rv8h_POST, ARM64_INS_LD2R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov16b, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov16b_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov2d, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov2d_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov2s, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov2s_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov4h, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov4h_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov4s, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov4s_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov8b, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov8b_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov8h, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2Twov8h_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD2W, ARM64_INS_LD2W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD2W_IMM, ARM64_INS_LD2W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD2i16, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i16_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i32, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i32_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i64, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i64_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i8, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD2i8_POST, ARM64_INS_LD2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD3B, ARM64_INS_LD3B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD3B_IMM, ARM64_INS_LD3B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD3D, ARM64_INS_LD3D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD3D_IMM, ARM64_INS_LD3D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD3H, ARM64_INS_LD3H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD3H_IMM, ARM64_INS_LD3H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD3Rv16b, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv16b_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv1d, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv1d_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv2d, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv2d_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv2s, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv2s_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv4h, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv4h_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv4s, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv4s_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv8b, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv8b_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv8h, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Rv8h_POST, ARM64_INS_LD3R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev16b, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev16b_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev2d, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev2d_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev2s, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev2s_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev4h, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev4h_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev4s, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev4s_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev8b, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev8b_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev8h, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3Threev8h_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD3W, ARM64_INS_LD3W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD3W_IMM, ARM64_INS_LD3W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD3i16, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i16_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i32, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i32_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i64, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i64_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i8, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD3i8_POST, ARM64_INS_LD3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD4B, ARM64_INS_LD4B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD4B_IMM, ARM64_INS_LD4B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD4D, ARM64_INS_LD4D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD4D_IMM, ARM64_INS_LD4D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD4Fourv16b, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv16b_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv2d, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv2d_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv2s, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv2s_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv4h, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv4h_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv4s, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv4s_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv8b, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv8b_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv8h, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Fourv8h_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD4H, ARM64_INS_LD4H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD4H_IMM, ARM64_INS_LD4H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD4Rv16b, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv16b_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv1d, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv1d_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv2d, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv2d_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv2s, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv2s_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv4h, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv4h_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv4s, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv4s_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv8b, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv8b_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv8h, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4Rv8h_POST, ARM64_INS_LD4R, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LD4W, ARM64_INS_LD4W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LD4W_IMM, ARM64_INS_LD4W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LD4i16, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i16_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i32, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i32_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i64, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i64_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i8, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_LD4i8_POST, ARM64_INS_LD4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_LDADDAB, ARM64_INS_LDADDAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDAH, ARM64_INS_LDADDAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDALB, ARM64_INS_LDADDALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDALH, ARM64_INS_LDADDALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDALW, ARM64_INS_LDADDAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDALX, ARM64_INS_LDADDAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDAW, ARM64_INS_LDADDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDAX, ARM64_INS_LDADDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDB, ARM64_INS_LDADDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDH, ARM64_INS_LDADDH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDLB, ARM64_INS_LDADDLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDLH, ARM64_INS_LDADDLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDLW, ARM64_INS_LDADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDLX, ARM64_INS_LDADDL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDW, ARM64_INS_LDADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDADDX, ARM64_INS_LDADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPRB, ARM64_INS_LDAPRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPRH, ARM64_INS_LDAPRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPRW, ARM64_INS_LDAPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPRX, ARM64_INS_LDAPR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURBi, ARM64_INS_LDAPURB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURHi, ARM64_INS_LDAPURH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURSBWi, ARM64_INS_LDAPURSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURSBXi, ARM64_INS_LDAPURSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURSHWi, ARM64_INS_LDAPURSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURSHXi, ARM64_INS_LDAPURSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURSWi, ARM64_INS_LDAPURSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURXi, ARM64_INS_LDAPUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDAPURi, ARM64_INS_LDAPUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LDARB, ARM64_INS_LDARB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDARH, ARM64_INS_LDARH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDARW, ARM64_INS_LDAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDARX, ARM64_INS_LDAR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDAXPW, ARM64_INS_LDAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDAXPX, ARM64_INS_LDAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDAXRB, ARM64_INS_LDAXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDAXRH, ARM64_INS_LDAXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDAXRW, ARM64_INS_LDAXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDAXRX, ARM64_INS_LDAXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LDCLRAB, ARM64_INS_LDCLRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRAH, ARM64_INS_LDCLRAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRALB, ARM64_INS_LDCLRALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRALH, ARM64_INS_LDCLRALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRALW, ARM64_INS_LDCLRAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRALX, ARM64_INS_LDCLRAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRAW, ARM64_INS_LDCLRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRAX, ARM64_INS_LDCLRA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRB, ARM64_INS_LDCLRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRH, ARM64_INS_LDCLRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRLB, ARM64_INS_LDCLRLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRLH, ARM64_INS_LDCLRLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRLW, ARM64_INS_LDCLRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRLX, ARM64_INS_LDCLRL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRW, ARM64_INS_LDCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDCLRX, ARM64_INS_LDCLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORAB, ARM64_INS_LDEORAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORAH, ARM64_INS_LDEORAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORALB, ARM64_INS_LDEORALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORALH, ARM64_INS_LDEORALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORALW, ARM64_INS_LDEORAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORALX, ARM64_INS_LDEORAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORAW, ARM64_INS_LDEORA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORAX, ARM64_INS_LDEORA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORB, ARM64_INS_LDEORB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORH, ARM64_INS_LDEORH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORLB, ARM64_INS_LDEORLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORLH, ARM64_INS_LDEORLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORLW, ARM64_INS_LDEORL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORLX, ARM64_INS_LDEORL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORW, ARM64_INS_LDEOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDEORX, ARM64_INS_LDEOR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1B_D_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1B_H_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1B_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1B_S_REAL, ARM64_INS_LDFF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1D_REAL, ARM64_INS_LDFF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1H_D_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1H_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1H_S_REAL, ARM64_INS_LDFF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1SB_D_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1SB_H_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1SB_S_REAL, ARM64_INS_LDFF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1SH_D_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1SH_S_REAL, ARM64_INS_LDFF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1SW_D_REAL, ARM64_INS_LDFF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1W_D_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDFF1W_REAL, ARM64_INS_LDFF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDLARB, ARM64_INS_LDLARB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDLARH, ARM64_INS_LDLARH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDLARW, ARM64_INS_LDLAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDLARX, ARM64_INS_LDLAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1B_D_IMM_REAL, ARM64_INS_LDNF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1B_H_IMM_REAL, ARM64_INS_LDNF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1B_IMM_REAL, ARM64_INS_LDNF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1B_S_IMM_REAL, ARM64_INS_LDNF1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1D_IMM_REAL, ARM64_INS_LDNF1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1H_D_IMM_REAL, ARM64_INS_LDNF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1H_IMM_REAL, ARM64_INS_LDNF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1H_S_IMM_REAL, ARM64_INS_LDNF1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1SB_D_IMM_REAL, ARM64_INS_LDNF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1SB_H_IMM_REAL, ARM64_INS_LDNF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1SB_S_IMM_REAL, ARM64_INS_LDNF1SB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1SH_D_IMM_REAL, ARM64_INS_LDNF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1SH_S_IMM_REAL, ARM64_INS_LDNF1SH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1SW_D_IMM_REAL, ARM64_INS_LDNF1SW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1W_D_IMM_REAL, ARM64_INS_LDNF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNF1W_IMM_REAL, ARM64_INS_LDNF1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LDNPDi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDNPQi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDNPSi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDNPWi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDNPXi, ARM64_INS_LDNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LDNT1B_ZRI, ARM64_INS_LDNT1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1B_ZRR, ARM64_INS_LDNT1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1D_ZRI, ARM64_INS_LDNT1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1D_ZRR, ARM64_INS_LDNT1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1H_ZRI, ARM64_INS_LDNT1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1H_ZRR, ARM64_INS_LDNT1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1W_ZRI, ARM64_INS_LDNT1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDNT1W_ZRR, ARM64_INS_LDNT1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LDPDi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPDpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPDpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPQi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPQpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPQpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPSWi, ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPSWpost, ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPSWpre, ARM64_INS_LDPSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPSi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPSpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPSpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPWi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPWpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPWpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPXi, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPXpost, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDPXpre, ARM64_INS_LDP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LDRAAindexed, ARM64_INS_LDRAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDRAAwriteback, ARM64_INS_LDRAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDRABindexed, ARM64_INS_LDRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDRABwriteback, ARM64_INS_LDRAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LDRBBpost, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBBpre, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBBroW, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBBroX, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBBui, ARM64_INS_LDRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRBui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRDl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRDpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRDpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRDroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRDroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRDui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHHpost, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHHpre, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHHroW, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHHroX, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHHui, ARM64_INS_LDRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRHui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRQl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRQpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRQpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRQroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRQroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRQui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBWpost, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBWpre, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBWroW, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBWroX, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBWui, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBXpost, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBXpre, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBXroW, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBXroX, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSBXui, ARM64_INS_LDRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHWpost, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHWpre, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHWroW, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHWroX, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHWui, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHXpost, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHXpre, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHXroW, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHXroX, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSHXui, ARM64_INS_LDRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSWl, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSWpost, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSWpre, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSWroW, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSWroX, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSWui, ARM64_INS_LDRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRSui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRWl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRWpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRWpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRWroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRWroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRWui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRXl, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRXpost, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRXpre, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRXroW, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRXroX, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDRXui, ARM64_INS_LDR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LDR_PXI, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDR_ZXI, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETAB, ARM64_INS_LDSETAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETAH, ARM64_INS_LDSETAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETALB, ARM64_INS_LDSETALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETALH, ARM64_INS_LDSETALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETALW, ARM64_INS_LDSETAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETALX, ARM64_INS_LDSETAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETAW, ARM64_INS_LDSETA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETAX, ARM64_INS_LDSETA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETB, ARM64_INS_LDSETB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETH, ARM64_INS_LDSETH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETLB, ARM64_INS_LDSETLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETLH, ARM64_INS_LDSETLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETLW, ARM64_INS_LDSETL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETLX, ARM64_INS_LDSETL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETW, ARM64_INS_LDSET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSETX, ARM64_INS_LDSET, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXAB, ARM64_INS_LDSMAXAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXAH, ARM64_INS_LDSMAXAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXALB, ARM64_INS_LDSMAXALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXALH, ARM64_INS_LDSMAXALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXALW, ARM64_INS_LDSMAXAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXALX, ARM64_INS_LDSMAXAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXAW, ARM64_INS_LDSMAXA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXAX, ARM64_INS_LDSMAXA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXB, ARM64_INS_LDSMAXB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXH, ARM64_INS_LDSMAXH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXLB, ARM64_INS_LDSMAXLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXLH, ARM64_INS_LDSMAXLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXLW, ARM64_INS_LDSMAXL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXLX, ARM64_INS_LDSMAXL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXW, ARM64_INS_LDSMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMAXX, ARM64_INS_LDSMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINAB, ARM64_INS_LDSMINAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINAH, ARM64_INS_LDSMINAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINALB, ARM64_INS_LDSMINALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINALH, ARM64_INS_LDSMINALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINALW, ARM64_INS_LDSMINAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINALX, ARM64_INS_LDSMINAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINAW, ARM64_INS_LDSMINA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINAX, ARM64_INS_LDSMINA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINB, ARM64_INS_LDSMINB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINH, ARM64_INS_LDSMINH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINLB, ARM64_INS_LDSMINLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINLH, ARM64_INS_LDSMINLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINLW, ARM64_INS_LDSMINL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINLX, ARM64_INS_LDSMINL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINW, ARM64_INS_LDSMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDSMINX, ARM64_INS_LDSMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LDTRBi, ARM64_INS_LDTRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRHi, ARM64_INS_LDTRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRSBWi, ARM64_INS_LDTRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRSBXi, ARM64_INS_LDTRSB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRSHWi, ARM64_INS_LDTRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRSHXi, ARM64_INS_LDTRSH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRSWi, ARM64_INS_LDTRSW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRWi, ARM64_INS_LDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDTRXi, ARM64_INS_LDTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURBBi, ARM64_INS_LDURB, + AArch64_LDUMAXAB, ARM64_INS_LDUMAXAB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURBi, ARM64_INS_LDUR, + AArch64_LDUMAXAH, ARM64_INS_LDUMAXAH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURDi, ARM64_INS_LDUR, + AArch64_LDUMAXALB, ARM64_INS_LDUMAXALB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURHHi, ARM64_INS_LDURH, + AArch64_LDUMAXALH, ARM64_INS_LDUMAXALH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURHi, ARM64_INS_LDUR, + AArch64_LDUMAXALW, ARM64_INS_LDUMAXAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURQi, ARM64_INS_LDUR, + AArch64_LDUMAXALX, ARM64_INS_LDUMAXAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURSBWi, ARM64_INS_LDURSB, + AArch64_LDUMAXAW, ARM64_INS_LDUMAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURSBXi, ARM64_INS_LDURSB, + AArch64_LDUMAXAX, ARM64_INS_LDUMAXA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURSHWi, ARM64_INS_LDURSH, + AArch64_LDUMAXB, ARM64_INS_LDUMAXB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURSHXi, ARM64_INS_LDURSH, + AArch64_LDUMAXH, ARM64_INS_LDUMAXH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURSWi, ARM64_INS_LDURSW, + AArch64_LDUMAXLB, ARM64_INS_LDUMAXLB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURSi, ARM64_INS_LDUR, + AArch64_LDUMAXLH, ARM64_INS_LDUMAXLH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURWi, ARM64_INS_LDUR, + AArch64_LDUMAXLW, ARM64_INS_LDUMAXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_LDURXi, ARM64_INS_LDUR, + AArch64_LDUMAXLX, ARM64_INS_LDUMAXL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LDUMAXW, ARM64_INS_LDUMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMAXX, ARM64_INS_LDUMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINAB, ARM64_INS_LDUMINAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINAH, ARM64_INS_LDUMINAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINALB, ARM64_INS_LDUMINALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINALH, ARM64_INS_LDUMINALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINALW, ARM64_INS_LDUMINAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINALX, ARM64_INS_LDUMINAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINAW, ARM64_INS_LDUMINA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINAX, ARM64_INS_LDUMINA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINB, ARM64_INS_LDUMINB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINH, ARM64_INS_LDUMINH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINLB, ARM64_INS_LDUMINLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINLH, ARM64_INS_LDUMINLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINLW, ARM64_INS_LDUMINL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINLX, ARM64_INS_LDUMINL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINW, ARM64_INS_LDUMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDUMINX, ARM64_INS_LDUMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURBBi, ARM64_INS_LDRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURBi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURDi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURHHi, ARM64_INS_LDRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURHi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURQi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURSBWi, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURSBXi, ARM64_INS_LDRSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURSHWi, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURSHXi, ARM64_INS_LDRSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURSWi, ARM64_INS_LDRSW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURSi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURWi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LDURXi, ARM64_INS_LDR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LDXPW, ARM64_INS_LDXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDXPX, ARM64_INS_LDXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDXRB, ARM64_INS_LDXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDXRH, ARM64_INS_LDXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDXRW, ARM64_INS_LDXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LDXRX, ARM64_INS_LDXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LSLR_ZPmZ_B, ARM64_INS_LSLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSLR_ZPmZ_D, ARM64_INS_LSLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSLR_ZPmZ_H, ARM64_INS_LSLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSLR_ZPmZ_S, ARM64_INS_LSLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LSLVWr, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LSLVXr, ARM64_INS_LSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LSL_WIDE_ZPmZ_B, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_WIDE_ZPmZ_H, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_WIDE_ZPmZ_S, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_WIDE_ZZZ_B, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_WIDE_ZZZ_H, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_WIDE_ZZZ_S, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmI_B, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmI_D, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmI_H, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmI_S, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmZ_B, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmZ_D, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmZ_H, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZPmZ_S, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZZI_B, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZZI_D, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZZI_H, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSL_ZZI_S, ARM64_INS_LSL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSRR_ZPmZ_B, ARM64_INS_LSRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSRR_ZPmZ_D, ARM64_INS_LSRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSRR_ZPmZ_H, ARM64_INS_LSRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSRR_ZPmZ_S, ARM64_INS_LSRR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_LSRVWr, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_LSRVXr, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_LSR_WIDE_ZPmZ_B, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_WIDE_ZPmZ_H, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_WIDE_ZPmZ_S, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_WIDE_ZZZ_B, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_WIDE_ZZZ_H, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_WIDE_ZZZ_S, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmI_B, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmI_D, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmI_H, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmI_S, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmZ_B, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmZ_D, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmZ_H, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZPmZ_S, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZZI_B, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZZI_D, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZZI_H, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_LSR_ZZI_S, ARM64_INS_LSR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_MADDWrrr, ARM64_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_MADDXrrr, ARM64_INS_MADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_MAD_ZPmZZ_B, ARM64_INS_MAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MAD_ZPmZZ_D, ARM64_INS_MAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MAD_ZPmZZ_H, ARM64_INS_MAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MAD_ZPmZZ_S, ARM64_INS_MAD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLA_ZPmZZ_B, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLA_ZPmZZ_D, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLA_ZPmZZ_H, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLA_ZPmZZ_S, ARM64_INS_MLA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_MLAv16i8, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv2i32, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv2i32_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv4i16, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv4i16_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv4i32, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv4i32_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv8i16, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv8i16_indexed, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLAv8i8, ARM64_INS_MLA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_MLS_ZPmZZ_B, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLS_ZPmZZ_D, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLS_ZPmZZ_H, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MLS_ZPmZZ_S, ARM64_INS_MLS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_MLSv16i8, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv2i32, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv2i32_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv4i16, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv4i16_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv4i32, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv4i32_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv8i16, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv8i16_indexed, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MLSv8i8, ARM64_INS_MLS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVID, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv16b_ns, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv2d_ns, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv2i32, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv2s_msl, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv4i16, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv4i32, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv4s_msl, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv8b_ns, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVIv8i16, ARM64_INS_MOVI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MOVKWi, ARM64_INS_MOVK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_MOVKXi, ARM64_INS_MOVK, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_MOVNWi, ARM64_INS_MOVN, + AArch64_MOVNWi, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_MOVNXi, ARM64_INS_MOVN, + AArch64_MOVNXi, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_MOVZWi, ARM64_INS_MOVZ, + AArch64_MOVPRFX_ZPmZ_B, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_MOVZXi, ARM64_INS_MOVZ, + AArch64_MOVPRFX_ZPmZ_D, ARM64_INS_MOVPRFX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_MOVPRFX_ZPmZ_H, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVPRFX_ZPmZ_S, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVPRFX_ZPzZ_B, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVPRFX_ZPzZ_D, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVPRFX_ZPzZ_H, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVPRFX_ZPzZ_S, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVPRFX_ZZ, ARM64_INS_MOVPRFX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVZWi, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MOVZXi, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_MRS, ARM64_INS_MRS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, + +{ + AArch64_MSB_ZPmZZ_B, ARM64_INS_MSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MSB_ZPmZZ_D, ARM64_INS_MSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MSB_ZPmZZ_H, ARM64_INS_MSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MSB_ZPmZZ_S, ARM64_INS_MSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_MSR, ARM64_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, + { - AArch64_MSRpstate, ARM64_INS_MSR, + AArch64_MSRpstateImm1, ARM64_INS_MSR, #ifndef CAPSTONE_DIET { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 #endif }, + { - AArch64_MSUBWrrr, ARM64_INS_MSUB, + AArch64_MSRpstateImm4, ARM64_INS_MSR, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { ARM64_GRP_PRIVILEGE, 0 }, 0, 0 +#endif +}, + +{ + AArch64_MSUBWrrr, ARM64_INS_MNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_MSUBXrrr, ARM64_INS_MSUB, + AArch64_MSUBXrrr, ARM64_INS_MNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_MUL_ZI_B, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZI_D, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZI_H, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZI_S, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZPmZ_B, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZPmZ_D, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZPmZ_H, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_MUL_ZPmZ_S, ARM64_INS_MUL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_MULv16i8, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv2i32, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv2i32_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv4i16, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv4i16_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv4i32, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv4i32_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv8i16, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv8i16_indexed, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MULv8i8, ARM64_INS_MUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MVNIv2i32, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MVNIv2s_msl, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MVNIv4i16, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MVNIv4i32, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MVNIv4s_msl, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_MVNIv8i16, ARM64_INS_MVNI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_NANDS_PPzPP, ARM64_INS_NANDS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NAND_PPzPP, ARM64_INS_NAND, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NEG_ZPmZ_B, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NEG_ZPmZ_D, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NEG_ZPmZ_H, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NEG_ZPmZ_S, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_NEGv16i8, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv1i64, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv2i32, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv2i64, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv4i16, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv4i32, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv8i16, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_NEGv8i8, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_NOTv16i8, ARM64_INS_NOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 -#endif -}, -{ - AArch64_NOTv8i8, ARM64_INS_NOT, -#ifndef CAPSTONE_DIET - { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 -#endif -}, -{ - AArch64_ORNWrs, ARM64_INS_ORN, + AArch64_NORS_PPzPP, ARM64_INS_NORS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ORNXrs, ARM64_INS_ORN, + AArch64_NOR_PPzPP, ARM64_INS_NOR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_NOT_ZPmZ_B, ARM64_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NOT_ZPmZ_D, ARM64_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NOT_ZPmZ_H, ARM64_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NOT_ZPmZ_S, ARM64_INS_NOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_NOTv16i8, ARM64_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + AArch64_NOTv8i8, ARM64_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORNS_PPzPP, ARM64_INS_ORNS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORNWrs, ARM64_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORNXrs, ARM64_INS_MVN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORN_PPzPP, ARM64_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ORNv16i8, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ORNv8i8, ARM64_INS_ORN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_ORRWri, ARM64_INS_ORR, + AArch64_ORRS_PPzPP, ARM64_INS_MOVS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ORRWrs, ARM64_INS_ORR, + AArch64_ORRWri, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ORRXri, ARM64_INS_ORR, + AArch64_ORRWrs, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ORRXrs, ARM64_INS_ORR, + AArch64_ORRXri, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_ORRv16i8, ARM64_INS_ORR, + AArch64_ORRXrs, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_PPzPP, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_ZI, ARM64_INS_ORN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_ZPmZ_B, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_ZPmZ_D, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_ZPmZ_H, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_ZPmZ_S, ARM64_INS_ORR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORR_ZZZ, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORRv16i8, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ORRv2i32, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ORRv4i16, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ORRv4i32, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ORRv8i16, ARM64_INS_ORR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_ORRv8i8, ARM64_INS_ORR, + AArch64_ORRv8i8, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ORV_VPZ_B, ARM64_INS_ORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORV_VPZ_D, ARM64_INS_ORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORV_VPZ_H, ARM64_INS_ORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ORV_VPZ_S, ARM64_INS_ORV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACDA, ARM64_INS_PACDA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACDB, ARM64_INS_PACDB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACDZA, ARM64_INS_PACDZA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACDZB, ARM64_INS_PACDZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACGA, ARM64_INS_PACGA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIA, ARM64_INS_PACIA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIA1716, ARM64_INS_PACIA1716, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIASP, ARM64_INS_PACIASP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIAZ, ARM64_INS_PACIAZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIB, ARM64_INS_PACIB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIB1716, ARM64_INS_PACIB1716, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIBSP, ARM64_INS_PACIBSP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIBZ, ARM64_INS_PACIBZ, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIZA, ARM64_INS_PACIZA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PACIZB, ARM64_INS_PACIZB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PFALSE, ARM64_INS_PFALSE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_PMULLv16i8, ARM64_INS_PMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_PMULLv1i64, ARM64_INS_PMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_PMULLv2i64, ARM64_INS_PMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_PMULLv8i8, ARM64_INS_PMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_PMULv16i8, ARM64_INS_PMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_PMULv8i8, ARM64_INS_PMUL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_PNEXT_B, ARM64_INS_PNEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PNEXT_D, ARM64_INS_PNEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PNEXT_H, ARM64_INS_PNEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PNEXT_S, ARM64_INS_PNEXT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_D_PZI, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_D_SCALED, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_D_SXTW_SCALED, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_D_UXTW_SCALED, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_PRI, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_PRR, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_S_PZI, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_S_SXTW_SCALED, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFB_S_UXTW_SCALED, ARM64_INS_PRFB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_D_PZI, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_D_SCALED, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_D_SXTW_SCALED, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_D_UXTW_SCALED, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_PRI, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_PRR, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_S_PZI, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_S_SXTW_SCALED, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFD_S_UXTW_SCALED, ARM64_INS_PRFD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_D_PZI, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_D_SCALED, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_D_SXTW_SCALED, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_D_UXTW_SCALED, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_PRI, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_PRR, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_S_PZI, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_S_SXTW_SCALED, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFH_S_UXTW_SCALED, ARM64_INS_PRFH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_PRFMl, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_PRFMroW, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_PRFMroX, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_PRFMui, ARM64_INS_PRFM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_PRFS_PRR, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_PRFUMi, ARM64_INS_PRFUM, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_PRFW_D_PZI, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_D_SCALED, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_D_SXTW_SCALED, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_D_UXTW_SCALED, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_PRI, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_S_PZI, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_S_SXTW_SCALED, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PRFW_S_UXTW_SCALED, ARM64_INS_PRFW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTEST_PP, ARM64_INS_PTEST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUES_B, ARM64_INS_PTRUES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUES_D, ARM64_INS_PTRUES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUES_H, ARM64_INS_PTRUES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUES_S, ARM64_INS_PTRUES, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUE_B, ARM64_INS_PTRUE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUE_D, ARM64_INS_PTRUE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUE_H, ARM64_INS_PTRUE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PTRUE_S, ARM64_INS_PTRUE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PUNPKHI_PP, ARM64_INS_PUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_PUNPKLO_PP, ARM64_INS_PUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_RAX1, ARM64_INS_RAX1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_RBITWr, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_RBITXr, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_RBIT_ZPmZ_B, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RBIT_ZPmZ_D, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RBIT_ZPmZ_H, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RBIT_ZPmZ_S, ARM64_INS_RBIT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_RBITv16i8, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RBITv8i8, ARM64_INS_RBIT, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_RDFFRS_PPz, ARM64_INS_RDFFRS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RDFFR_P, ARM64_INS_RDFFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RDFFR_PPz, ARM64_INS_RDFFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RDVLI_XI, ARM64_INS_RDVL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_RET, ARM64_INS_RET, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_RET, 0 }, 0, 0 #endif }, + +{ + AArch64_RETAA, ARM64_INS_RETAA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RETAB, ARM64_INS_RETAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_REV16Wr, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_REV16Xr, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_REV16v16i8, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV16v8i8, ARM64_INS_REV16, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV32Xr, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_REV32v16i8, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV32v4i16, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV32v8i16, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV32v8i8, ARM64_INS_REV32, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV64v16i8, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV64v2i32, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV64v4i16, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV64v4i32, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV64v8i16, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_REV64v8i8, ARM64_INS_REV64, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_REVB_ZPmZ_D, ARM64_INS_REVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REVB_ZPmZ_H, ARM64_INS_REVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REVB_ZPmZ_S, ARM64_INS_REVB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REVH_ZPmZ_D, ARM64_INS_REVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REVH_ZPmZ_S, ARM64_INS_REVH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REVW_ZPmZ_D, ARM64_INS_REVW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_REVWr, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_REVXr, ARM64_INS_REV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_REV_PP_B, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_PP_D, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_PP_H, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_PP_S, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_ZZ_B, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_ZZ_D, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_ZZ_H, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_REV_ZZ_S, ARM64_INS_REV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_RMIF, ARM64_INS_RMIF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_RORVWr, ARM64_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_RORVXr, ARM64_INS_ROR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABAv16i8, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABAv2i32, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABAv4i16, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABAv4i32, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABAv8i16, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABAv8i8, ARM64_INS_SABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SABD_ZPmZ_B, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SABD_ZPmZ_D, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SABD_ZPmZ_H, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SABD_ZPmZ_S, ARM64_INS_SABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SABDv16i8, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDv2i32, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDv4i16, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDv4i32, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDv8i16, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SABDv8i8, ARM64_INS_SABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLVv16i8v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLVv4i16v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLVv4i32v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLVv8i16v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLVv8i8v, ARM64_INS_SADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SADDV_VPZ_B, ARM64_INS_SADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SADDV_VPZ_H, ARM64_INS_SADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SADDV_VPZ_S, ARM64_INS_SADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_SBCSWr, ARM64_INS_SBC, + AArch64_SBCSWr, ARM64_INS_NGCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SBCSXr, ARM64_INS_SBC, + AArch64_SBCSXr, ARM64_INS_NGCS, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SBCWr, ARM64_INS_SBC, + AArch64_SBCWr, ARM64_INS_NGC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SBCXr, ARM64_INS_SBC, + AArch64_SBCXr, ARM64_INS_NGC, #ifndef CAPSTONE_DIET { ARM64_REG_NZCV, 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SBFMWri, ARM64_INS_SBFM, + AArch64_SBFMWri, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SBFMXri, ARM64_INS_SBFM, + AArch64_SBFMXri, ARM64_INS_ASR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SCVTFSWDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFSWHri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFSWSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_SCVTFSXDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFSXHri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFSXSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_SCVTFUWDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFUWHri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFUWSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_SCVTFUXDri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFUXHri, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFUXSri, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTF_ZPmZ_DtoD, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTF_ZPmZ_DtoH, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTF_ZPmZ_DtoS, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTF_ZPmZ_HtoH, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTF_ZPmZ_StoD, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTF_ZPmZ_StoH, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTF_ZPmZ_StoS, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFd, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFh, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFs, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFv1i16, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFv1i32, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SCVTFv1i64, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SCVTFv2f32, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SCVTFv2f64, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFv4f16, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFv4f32, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFv4i16_shift, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SCVTFv8f16, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SCVTFv8i16_shift, ARM64_INS_SCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDIVR_ZPmZ_D, ARM64_INS_SDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDIVR_ZPmZ_S, ARM64_INS_SDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SDIVWr, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SDIVXr, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SDIV_IntWr, ARM64_INS_SDIV, + AArch64_SDIV_ZPmZ_D, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SDIV_IntXr, ARM64_INS_SDIV, + AArch64_SDIV_ZPmZ_S, ARM64_INS_SDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_SDOT_ZZZI_D, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOT_ZZZI_S, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOT_ZZZ_D, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOT_ZZZ_S, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOTlanev16i8, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOTlanev8i8, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOTv16i8, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SDOTv8i8, ARM64_INS_SDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SEL_PPPP, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SEL_ZPZZ_B, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SEL_ZPZZ_D, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SEL_ZPZZ_H, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SEL_ZPZZ_S, ARM64_INS_MOV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SETF16, ARM64_INS_SETF16, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SETF8, ARM64_INS_SETF8, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SETFFR, ARM64_INS_SETFFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SHA1Crrr, ARM64_INS_SHA1C, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA1Hrr, ARM64_INS_SHA1H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA1Mrrr, ARM64_INS_SHA1M, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA1Prrr, ARM64_INS_SHA1P, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA256H2rrr, ARM64_INS_SHA256H2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA256Hrrr, ARM64_INS_SHA256H, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + { AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_CRYPTO, 0 }, 0, 0 #endif }, + +{ + AArch64_SHA512H, ARM64_INS_SHA512H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SHA512H2, ARM64_INS_SHA512H2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SHA512SU0, ARM64_INS_SHA512SU0, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SHA512SU1, ARM64_INS_SHA512SU1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SHADDv16i8, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHADDv2i32, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHADDv4i16, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHADDv4i32, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHADDv8i16, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHADDv8i8, ARM64_INS_SHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLLv16i8, ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLLv2i32, ARM64_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLLv4i16, ARM64_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLLv4i32, ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLLv8i16, ARM64_INS_SHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLLv8i8, ARM64_INS_SHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLd, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv16i8_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv2i32_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv2i64_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv4i16_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv4i32_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv8i16_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHLv8i8_shift, ARM64_INS_SHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHRNv2i32_shift, ARM64_INS_SHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHRNv4i16_shift, ARM64_INS_SHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHRNv8i8_shift, ARM64_INS_SHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHSUBv16i8, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHSUBv2i32, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHSUBv4i16, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHSUBv4i32, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHSUBv8i16, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SHSUBv8i8, ARM64_INS_SHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLId, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv16i8_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv2i32_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv2i64_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv4i16_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv4i32_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv8i16_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SLIv8i8_shift, ARM64_INS_SLI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SM3PARTW1, ARM64_INS_SM3PARTW1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM3PARTW2, ARM64_INS_SM3PARTW2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM3SS1, ARM64_INS_SM3SS1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM3TT1A, ARM64_INS_SM3TT1A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM3TT1B, ARM64_INS_SM3TT1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM3TT2A, ARM64_INS_SM3TT2A, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM3TT2B, ARM64_INS_SM3TT2B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM4E, ARM64_INS_SM4E, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SM4ENCKEY, ARM64_INS_SM4EKEY, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SMADDLrrr, ARM64_INS_SMADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SMAXPv16i8, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXPv2i32, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXPv4i16, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXPv4i32, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXPv8i16, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXPv8i8, ARM64_INS_SMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SMAXV_VPZ_B, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAXV_VPZ_D, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAXV_VPZ_H, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAXV_VPZ_S, ARM64_INS_SMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SMAXVv16i8v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXVv4i16v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXVv4i32v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXVv8i16v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXVv8i8v, ARM64_INS_SMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SMAX_ZI_B, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZI_D, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZI_H, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZI_S, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZPmZ_B, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZPmZ_D, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZPmZ_H, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMAX_ZPmZ_S, ARM64_INS_SMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SMAXv16i8, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXv2i32, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXv4i16, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXv4i32, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXv8i16, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMAXv8i8, ARM64_INS_SMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMC, ARM64_INS_SMC, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SMINPv16i8, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINPv2i32, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINPv4i16, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINPv4i32, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINPv8i16, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINPv8i8, ARM64_INS_SMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SMINV_VPZ_B, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMINV_VPZ_D, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMINV_VPZ_H, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMINV_VPZ_S, ARM64_INS_SMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SMINVv16i8v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINVv4i16v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINVv4i32v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINVv8i16v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINVv8i8v, ARM64_INS_SMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SMIN_ZI_B, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZI_D, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZI_H, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZI_S, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZPmZ_B, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZPmZ_D, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZPmZ_H, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMIN_ZPmZ_S, ARM64_INS_SMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SMINv16i8, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINv2i32, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINv4i16, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINv4i32, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINv8i16, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMINv8i8, ARM64_INS_SMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMOVvi16to32, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMOVvi16to64, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMOVvi32to64, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMOVvi8to32, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMOVvi8to64, ARM64_INS_SMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_SMSUBLrrr, ARM64_INS_SMSUBL, + AArch64_SMSUBLrrr, ARM64_INS_SMNEGL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_SMULH_ZPmZ_B, ARM64_INS_SMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMULH_ZPmZ_D, ARM64_INS_SMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMULH_ZPmZ_H, ARM64_INS_SMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SMULH_ZPmZ_S, ARM64_INS_SMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SMULHrr, ARM64_INS_SMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SPLICE_ZPZ_B, ARM64_INS_SPLICE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SPLICE_ZPZ_D, ARM64_INS_SPLICE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SPLICE_ZPZ_H, ARM64_INS_SPLICE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SPLICE_ZPZ_S, ARM64_INS_SPLICE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SQABSv16i8, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv1i16, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv1i32, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv1i64, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv1i8, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv2i32, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv2i64, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv4i16, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv4i32, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv8i16, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQABSv8i8, ARM64_INS_SQABS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SQADD_ZI_B, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZI_D, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZI_H, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZI_S, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZZZ_B, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZZZ_D, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZZZ_H, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQADD_ZZZ_S, ARM64_INS_SQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SQADDv16i8, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv1i16, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv1i32, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv1i64, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv1i8, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv2i32, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv2i64, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv4i16, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv4i32, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv8i16, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQADDv8i8, ARM64_INS_SQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SQDECB_XPiI, ARM64_INS_SQDECB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECB_XPiWdI, ARM64_INS_SQDECB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECD_XPiI, ARM64_INS_SQDECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECD_XPiWdI, ARM64_INS_SQDECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECD_ZPiI, ARM64_INS_SQDECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECH_XPiI, ARM64_INS_SQDECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECH_XPiWdI, ARM64_INS_SQDECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECH_ZPiI, ARM64_INS_SQDECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XPWd_B, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XPWd_D, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XPWd_H, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XPWd_S, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XP_B, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XP_D, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XP_H, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_XP_S, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_ZP_D, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_ZP_H, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECP_ZP_S, ARM64_INS_SQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECW_XPiI, ARM64_INS_SQDECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECW_XPiWdI, ARM64_INS_SQDECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQDECW_ZPiI, ARM64_INS_SQDECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SQDMLALi16, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALi32, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLi16, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLi32, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SQINCB_XPiI, ARM64_INS_SQINCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCB_XPiWdI, ARM64_INS_SQINCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCD_XPiI, ARM64_INS_SQINCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCD_XPiWdI, ARM64_INS_SQINCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCD_ZPiI, ARM64_INS_SQINCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCH_XPiI, ARM64_INS_SQINCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCH_XPiWdI, ARM64_INS_SQINCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCH_ZPiI, ARM64_INS_SQINCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XPWd_B, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XPWd_D, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XPWd_H, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XPWd_S, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XP_B, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XP_D, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XP_H, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_XP_S, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_ZP_D, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_ZP_H, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCP_ZP_S, ARM64_INS_SQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCW_XPiI, ARM64_INS_SQINCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCW_XPiWdI, ARM64_INS_SQINCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQINCW_ZPiI, ARM64_INS_SQINCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SQNEGv16i8, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv1i16, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv1i32, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv1i64, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv1i8, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv2i32, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv2i64, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv4i16, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv4i32, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv8i16, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQNEGv8i8, ARM64_INS_SQNEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SQRDMLAHi16_indexed, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHi32_indexed, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv1i16, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv1i32, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv2i32, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv2i32_indexed, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv4i16, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv4i16_indexed, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv4i32, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv4i32_indexed, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv8i16, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLAHv8i16_indexed, ARM64_INS_SQRDMLAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHi16_indexed, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHi32_indexed, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv1i16, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv1i32, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv2i32, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv2i32_indexed, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv4i16, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv4i16_indexed, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv4i32, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv4i32_indexed, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv8i16, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQRDMLSHv8i16_indexed, ARM64_INS_SQRDMLSH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNb, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNh, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNs, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUb, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUd, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUh, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUs, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLb, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLd, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLh, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLs, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv16i8, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv1i16, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv1i32, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv1i64, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv1i8, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv2i32, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv2i64, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv4i16, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv4i32, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv8i16, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv8i8, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNb, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNh, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNs, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNb, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNh, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNs, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SQSUB_ZI_B, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZI_D, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZI_H, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZI_S, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZZZ_B, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZZZ_D, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZZZ_H, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SQSUB_ZZZ_S, ARM64_INS_SQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SQSUBv16i8, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv1i16, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv1i32, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv1i64, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv1i8, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv2i32, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv2i64, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv4i16, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv4i32, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv8i16, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQSUBv8i8, ARM64_INS_SQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv16i8, ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv1i16, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv1i32, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv1i8, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv2i32, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv4i16, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv4i32, ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv8i16, ARM64_INS_SQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTNv8i8, ARM64_INS_SQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRHADDv16i8, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRHADDv2i32, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRHADDv4i16, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRHADDv4i32, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRHADDv8i16, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRHADDv8i8, ARM64_INS_SRHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRId, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv16i8_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv2i32_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv2i64_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv4i16_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv4i32_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv8i16_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRIv8i8_shift, ARM64_INS_SRI, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv16i8, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv1i64, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv2i32, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv2i64, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv4i16, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv4i32, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv8i16, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHLv8i8, ARM64_INS_SRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRd, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAd, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv16i8, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv1i64, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv2i32, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv2i64, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv4i16, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv4i32, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv8i16, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHLv8i8, ARM64_INS_SSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRd, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv16i8_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv2i32_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv2i64_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv4i16_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv4i32_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv8i16_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSHRv8i8_shift, ARM64_INS_SSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAd, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv16i8_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv2i32_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv2i64_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv4i16_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv4i32_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv8i16_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSRAv8i8_shift, ARM64_INS_SSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SST1B_D, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1B_D_IMM, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1B_D_SXTW, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1B_D_UXTW, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1B_S_IMM, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1B_S_SXTW, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1B_S_UXTW, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D_IMM, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D_SCALED, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D_SXTW, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D_SXTW_SCALED, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D_UXTW, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1D_UXTW_SCALED, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D_IMM, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D_SCALED, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D_SXTW, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D_SXTW_SCALED, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D_UXTW, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_D_UXTW_SCALED, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_S_IMM, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_S_SXTW, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_S_SXTW_SCALED, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_S_UXTW, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1H_S_UXTW_SCALED, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D_IMM, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D_SCALED, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D_SXTW, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D_SXTW_SCALED, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D_UXTW, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_D_UXTW_SCALED, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_IMM, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_SXTW, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_SXTW_SCALED, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_UXTW, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SST1W_UXTW_SCALED, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST1B, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_D, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_D_IMM, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_H, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_H_IMM, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_IMM, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_S, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1B_S_IMM, ARM64_INS_ST1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1D, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1D_IMM, ARM64_INS_ST1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST1Fourv16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Fourv8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST1H, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1H_D, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1H_D_IMM, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1H_IMM, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1H_S, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1H_S_IMM, ARM64_INS_ST1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST1Onev16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Onev8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Threev8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov16b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov16b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov1d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov1d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov2d, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov2d_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov2s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov2s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov4h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov4h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov4s, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov4s_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov8b, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov8b_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov8h, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1Twov8h_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST1W, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1W_D, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1W_D_IMM, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST1W_IMM, ARM64_INS_ST1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST1i16, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i16_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i32, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i32_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i64, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i64_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i8, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST1i8_POST, ARM64_INS_ST1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST2B, ARM64_INS_ST2B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST2B_IMM, ARM64_INS_ST2B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST2D, ARM64_INS_ST2D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST2D_IMM, ARM64_INS_ST2D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST2H, ARM64_INS_ST2H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST2H_IMM, ARM64_INS_ST2H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST2Twov16b, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov16b_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov2d, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov2d_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov2s, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov2s_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov4h, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov4h_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov4s, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov4s_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov8b, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov8b_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov8h, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2Twov8h_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST2W, ARM64_INS_ST2W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST2W_IMM, ARM64_INS_ST2W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST2i16, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i16_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i32, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i32_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i64, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i64_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i8, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST2i8_POST, ARM64_INS_ST2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST3B, ARM64_INS_ST3B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST3B_IMM, ARM64_INS_ST3B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST3D, ARM64_INS_ST3D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST3D_IMM, ARM64_INS_ST3D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST3H, ARM64_INS_ST3H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST3H_IMM, ARM64_INS_ST3H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST3Threev16b, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev16b_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev2d, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev2d_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev2s, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev2s_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev4h, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev4h_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev4s, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev4s_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev8b, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev8b_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev8h, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3Threev8h_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST3W, ARM64_INS_ST3W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST3W_IMM, ARM64_INS_ST3W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST3i16, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i16_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i32, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i32_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i64, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i64_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i8, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST3i8_POST, ARM64_INS_ST3, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST4B, ARM64_INS_ST4B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST4B_IMM, ARM64_INS_ST4B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST4D, ARM64_INS_ST4D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST4D_IMM, ARM64_INS_ST4D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST4Fourv16b, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv16b_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv2d, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv2d_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv2s, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv2s_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv4h, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv4h_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv4s, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv4s_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv8b, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv8b_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv8h, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4Fourv8h_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ST4H, ARM64_INS_ST4H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST4H_IMM, ARM64_INS_ST4H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST4W, ARM64_INS_ST4W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ST4W_IMM, ARM64_INS_ST4W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ST4i16, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i16_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i32, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i32_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i64, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i64_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i8, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ST4i8_POST, ARM64_INS_ST4, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_STLLRB, ARM64_INS_STLLRB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STLLRH, ARM64_INS_STLLRH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STLLRW, ARM64_INS_STLLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STLLRX, ARM64_INS_STLLR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_STLRB, ARM64_INS_STLRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLRH, ARM64_INS_STLRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLRW, ARM64_INS_STLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLRX, ARM64_INS_STLR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_STLURBi, ARM64_INS_STLURB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STLURHi, ARM64_INS_STLURH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STLURWi, ARM64_INS_STLUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STLURXi, ARM64_INS_STLUR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_STLXPW, ARM64_INS_STLXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLXPX, ARM64_INS_STLXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLXRB, ARM64_INS_STLXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLXRH, ARM64_INS_STLXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLXRW, ARM64_INS_STLXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STLXRX, ARM64_INS_STLXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STNPDi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STNPQi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STNPSi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STNPWi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STNPXi, ARM64_INS_STNP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_STNT1B_ZRI, ARM64_INS_STNT1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1B_ZRR, ARM64_INS_STNT1B, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1D_ZRI, ARM64_INS_STNT1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1D_ZRR, ARM64_INS_STNT1D, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1H_ZRI, ARM64_INS_STNT1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1H_ZRR, ARM64_INS_STNT1H, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1W_ZRI, ARM64_INS_STNT1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STNT1W_ZRR, ARM64_INS_STNT1W, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_STPDi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPDpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPDpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPQi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPQpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPQpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPSi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPSpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPSpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPWi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPWpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPWpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPXi, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPXpost, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STPXpre, ARM64_INS_STP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBBpost, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBBpre, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBBroW, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBBroX, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBBui, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRBui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRDpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRDpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRDroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRDroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRDui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHHpost, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHHpre, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHHroW, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHHroX, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHHui, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRHui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRQpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRQpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRQroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRQroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRQui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRSpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRSpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRSroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRSroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRSui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRWpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRWpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRWroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRWroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRWui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRXpost, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRXpre, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRXroW, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRXroX, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STRXui, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_STR_PXI, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_STR_ZXI, ARM64_INS_STR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_STTRBi, ARM64_INS_STTRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STTRHi, ARM64_INS_STTRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STTRWi, ARM64_INS_STTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STTRXi, ARM64_INS_STTR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURBBi, ARM64_INS_STURB, + AArch64_STURBBi, ARM64_INS_STRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURBi, ARM64_INS_STUR, + AArch64_STURBi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURDi, ARM64_INS_STUR, + AArch64_STURDi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURHHi, ARM64_INS_STURH, + AArch64_STURHHi, ARM64_INS_STRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURHi, ARM64_INS_STUR, + AArch64_STURHi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURQi, ARM64_INS_STUR, + AArch64_STURQi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURSi, ARM64_INS_STUR, + AArch64_STURSi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURWi, ARM64_INS_STUR, + AArch64_STURWi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_STURXi, ARM64_INS_STUR, + AArch64_STURXi, ARM64_INS_STR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STXPW, ARM64_INS_STXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STXPX, ARM64_INS_STXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STXRB, ARM64_INS_STXRB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STXRH, ARM64_INS_STXRH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STXRW, ARM64_INS_STXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_STXRX, ARM64_INS_STXR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_SUBSWri, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBSWrs, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBSWrx, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBSXri, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBSXrs, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBSXrx, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBSXrx64, ARM64_INS_SUB, -#ifndef CAPSTONE_DIET - { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 -#endif -}, -{ - AArch64_SUBWri, ARM64_INS_SUB, + AArch64_SUBR_ZI_B, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SUBWrs, ARM64_INS_SUB, + AArch64_SUBR_ZI_D, ARM64_INS_SUBR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_SUBR_ZI_H, ARM64_INS_SUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBR_ZI_S, ARM64_INS_SUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBR_ZPmZ_B, ARM64_INS_SUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBR_ZPmZ_D, ARM64_INS_SUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBR_ZPmZ_H, ARM64_INS_SUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBR_ZPmZ_S, ARM64_INS_SUBR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSWri, ARM64_INS_ADDS, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSWrs, ARM64_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSWrx, ARM64_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSXri, ARM64_INS_ADDS, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSXrs, ARM64_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSXrx, ARM64_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBSXrx64, ARM64_INS_CMP, +#ifndef CAPSTONE_DIET + { 0 }, { ARM64_REG_NZCV, 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBWri, ARM64_INS_ADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUBWrs, ARM64_INS_NEG, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SUBWrx, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SUBXri, ARM64_INS_SUB, + AArch64_SUBXri, ARM64_INS_ADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_SUBXrs, ARM64_INS_SUB, + AArch64_SUBXrs, ARM64_INS_NEG, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SUBXrx, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SUBXrx64, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_SUB_ZI_B, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZI_D, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZI_H, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZI_S, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZPmZ_B, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZPmZ_D, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZPmZ_H, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZPmZ_S, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZZZ_B, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZZZ_D, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZZZ_H, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUB_ZZZ_S, ARM64_INS_SUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SUBv16i8, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv1i64, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv2i32, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv2i64, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv4i16, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv4i32, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv8i16, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUBv8i8, ARM64_INS_SUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_SUNPKHI_ZZ_D, ARM64_INS_SUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUNPKHI_ZZ_H, ARM64_INS_SUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUNPKHI_ZZ_S, ARM64_INS_SUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUNPKLO_ZZ_D, ARM64_INS_SUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUNPKLO_ZZ_H, ARM64_INS_SUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SUNPKLO_ZZ_S, ARM64_INS_SUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SUQADDv16i8, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv1i16, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv1i32, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv1i64, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv1i8, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv2i32, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv2i64, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv4i16, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv4i32, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv8i16, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SUQADDv8i8, ARM64_INS_SUQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_SVC, ARM64_INS_SVC, #ifndef CAPSTONE_DIET { 0, 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_INT, 0 }, 0, 0 #endif }, + +{ + AArch64_SWPAB, ARM64_INS_SWPAB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPAH, ARM64_INS_SWPAH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPALB, ARM64_INS_SWPALB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPALH, ARM64_INS_SWPALH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPALW, ARM64_INS_SWPAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPALX, ARM64_INS_SWPAL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPAW, ARM64_INS_SWPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPAX, ARM64_INS_SWPA, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPB, ARM64_INS_SWPB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPH, ARM64_INS_SWPH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPLB, ARM64_INS_SWPLB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPLH, ARM64_INS_SWPLH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPLW, ARM64_INS_SWPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPLX, ARM64_INS_SWPL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPW, ARM64_INS_SWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SWPX, ARM64_INS_SWP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SXTB_ZPmZ_D, ARM64_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SXTB_ZPmZ_H, ARM64_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SXTB_ZPmZ_S, ARM64_INS_SXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SXTH_ZPmZ_D, ARM64_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SXTH_ZPmZ_S, ARM64_INS_SXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_SXTW_ZPmZ_D, ARM64_INS_SXTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_SYSLxt, ARM64_INS_SYSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_SYSxt, ARM64_INS_SYS, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_TBL_ZZZ_B, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TBL_ZZZ_D, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TBL_ZZZ_H, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TBL_ZZZ_S, ARM64_INS_TBL, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_TBLv16i8Four, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv16i8One, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv16i8Three, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv16i8Two, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv8i8Four, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv8i8One, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv8i8Three, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBLv8i8Two, ARM64_INS_TBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBNZW, ARM64_INS_TBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_TBNZX, ARM64_INS_TBNZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_TBXv16i8Four, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv16i8One, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv16i8Three, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv16i8Two, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv8i8Four, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv8i8One, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv8i8Three, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBXv8i8Two, ARM64_INS_TBX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TBZW, ARM64_INS_TBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + { AArch64_TBZX, ARM64_INS_TBZ, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0 #endif }, + +{ + AArch64_TRN1_PPP_B, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_PPP_D, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_PPP_H, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_PPP_S, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_ZZZ_B, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_ZZZ_D, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_ZZZ_H, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN1_ZZZ_S, ARM64_INS_TRN1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_TRN1v16i8, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN1v2i32, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN1v2i64, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN1v4i16, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN1v4i32, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN1v8i16, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN1v8i8, ARM64_INS_TRN1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_TRN2_PPP_B, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_PPP_D, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_PPP_H, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_PPP_S, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_ZZZ_B, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_ZZZ_D, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_ZZZ_H, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_TRN2_ZZZ_S, ARM64_INS_TRN2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_TRN2v16i8, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN2v2i32, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN2v2i64, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN2v4i16, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN2v4i32, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN2v8i16, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_TRN2v8i8, ARM64_INS_TRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_TSB, ARM64_INS_TSB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABAv16i8, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABAv2i32, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABAv4i16, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABAv4i32, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABAv8i16, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABAv8i8, ARM64_INS_UABA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UABD_ZPmZ_B, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UABD_ZPmZ_D, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UABD_ZPmZ_H, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UABD_ZPmZ_S, ARM64_INS_UABD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UABDv16i8, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDv2i32, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDv4i16, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDv4i32, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDv8i16, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UABDv8i8, ARM64_INS_UABD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLVv16i8v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLVv4i16v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLVv4i32v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLVv8i16v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLVv8i8v, ARM64_INS_UADDLV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UADDV_VPZ_B, ARM64_INS_UADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UADDV_VPZ_D, ARM64_INS_UADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UADDV_VPZ_H, ARM64_INS_UADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UADDV_VPZ_S, ARM64_INS_UADDV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_UBFMWri, ARM64_INS_UBFM, + AArch64_UBFMWri, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_UBFMXri, ARM64_INS_UBFM, + AArch64_UBFMXri, ARM64_INS_LSR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_UCVTFSWDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFSWHri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFSWSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_UCVTFSXDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFSXHri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFSXSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_UCVTFUWDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFUWHri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFUWSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + { AArch64_UCVTFUXDri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFUXHri, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFUXSri, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_FPARMV8, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTF_ZPmZ_DtoD, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTF_ZPmZ_DtoH, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTF_ZPmZ_DtoS, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTF_ZPmZ_HtoH, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTF_ZPmZ_StoD, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTF_ZPmZ_StoH, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTF_ZPmZ_StoS, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFd, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFh, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFs, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFv1i16, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFv1i32, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UCVTFv1i64, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UCVTFv2f32, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UCVTFv2f64, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFv4f16, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFv4f32, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFv4i16_shift, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UCVTFv8f16, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UCVTFv8i16_shift, ARM64_INS_UCVTF, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDIVR_ZPmZ_D, ARM64_INS_UDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDIVR_ZPmZ_S, ARM64_INS_UDIVR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UDIVWr, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_UDIVXr, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_UDIV_IntWr, ARM64_INS_UDIV, + AArch64_UDIV_ZPmZ_D, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { - AArch64_UDIV_IntXr, ARM64_INS_UDIV, + AArch64_UDIV_ZPmZ_S, ARM64_INS_UDIV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_UDOT_ZZZI_D, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOT_ZZZI_S, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOT_ZZZ_D, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOT_ZZZ_S, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOTlanev16i8, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOTlanev8i8, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOTv16i8, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UDOTv8i8, ARM64_INS_UDOT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UHADDv16i8, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHADDv2i32, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHADDv4i16, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHADDv4i32, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHADDv8i16, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHADDv8i8, ARM64_INS_UHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHSUBv16i8, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHSUBv2i32, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHSUBv4i16, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHSUBv4i32, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHSUBv8i16, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UHSUBv8i8, ARM64_INS_UHSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMADDLrrr, ARM64_INS_UMADDL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_UMAXPv16i8, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXPv2i32, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXPv4i16, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXPv4i32, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXPv8i16, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXPv8i8, ARM64_INS_UMAXP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UMAXV_VPZ_B, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAXV_VPZ_D, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAXV_VPZ_H, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAXV_VPZ_S, ARM64_INS_UMAXV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UMAXVv16i8v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXVv4i16v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXVv4i32v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXVv8i16v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXVv8i8v, ARM64_INS_UMAXV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UMAX_ZI_B, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZI_D, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZI_H, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZI_S, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZPmZ_B, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZPmZ_D, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZPmZ_H, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMAX_ZPmZ_S, ARM64_INS_UMAX, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UMAXv16i8, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXv2i32, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXv4i16, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXv4i32, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXv8i16, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMAXv8i8, ARM64_INS_UMAX, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINPv16i8, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINPv2i32, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINPv4i16, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINPv4i32, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINPv8i16, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINPv8i8, ARM64_INS_UMINP, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UMINV_VPZ_B, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMINV_VPZ_D, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMINV_VPZ_H, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMINV_VPZ_S, ARM64_INS_UMINV, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UMINVv16i8v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINVv4i16v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINVv4i32v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINVv8i16v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINVv8i8v, ARM64_INS_UMINV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UMIN_ZI_B, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZI_D, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZI_H, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZI_S, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZPmZ_B, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZPmZ_D, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZPmZ_H, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMIN_ZPmZ_S, ARM64_INS_UMIN, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UMINv16i8, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINv2i32, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINv4i16, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINv4i32, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINv8i16, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMINv8i8, ARM64_INS_UMIN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMOVvi16, ARM64_INS_UMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_UMOVvi32, ARM64_INS_UMOV, + AArch64_UMOVvi32, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_UMOVvi64, ARM64_INS_UMOV, + AArch64_UMOVvi64, ARM64_INS_MOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMOVvi8, ARM64_INS_UMOV, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { - AArch64_UMSUBLrrr, ARM64_INS_UMSUBL, + AArch64_UMSUBLrrr, ARM64_INS_UMNEGL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + +{ + AArch64_UMULH_ZPmZ_B, ARM64_INS_UMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMULH_ZPmZ_D, ARM64_INS_UMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMULH_ZPmZ_H, ARM64_INS_UMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UMULH_ZPmZ_S, ARM64_INS_UMULH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UMULHrr, ARM64_INS_UMULH, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { 0 }, 0, 0 #endif }, + { AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UQADD_ZI_B, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZI_D, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZI_H, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZI_S, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZZZ_B, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZZZ_D, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZZZ_H, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQADD_ZZZ_S, ARM64_INS_UQADD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UQADDv16i8, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv1i16, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv1i32, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv1i64, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv1i8, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv2i32, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv2i64, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv4i16, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv4i32, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv8i16, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQADDv8i8, ARM64_INS_UQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UQDECB_WPiI, ARM64_INS_UQDECB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECB_XPiI, ARM64_INS_UQDECB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECD_WPiI, ARM64_INS_UQDECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECD_XPiI, ARM64_INS_UQDECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECD_ZPiI, ARM64_INS_UQDECD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECH_WPiI, ARM64_INS_UQDECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECH_XPiI, ARM64_INS_UQDECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECH_ZPiI, ARM64_INS_UQDECH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_WP_B, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_WP_D, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_WP_H, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_WP_S, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_XP_B, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_XP_D, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_XP_H, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_XP_S, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_ZP_D, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_ZP_H, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECP_ZP_S, ARM64_INS_UQDECP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECW_WPiI, ARM64_INS_UQDECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECW_XPiI, ARM64_INS_UQDECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQDECW_ZPiI, ARM64_INS_UQDECW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCB_WPiI, ARM64_INS_UQINCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCB_XPiI, ARM64_INS_UQINCB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCD_WPiI, ARM64_INS_UQINCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCD_XPiI, ARM64_INS_UQINCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCD_ZPiI, ARM64_INS_UQINCD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCH_WPiI, ARM64_INS_UQINCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCH_XPiI, ARM64_INS_UQINCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCH_ZPiI, ARM64_INS_UQINCH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_WP_B, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_WP_D, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_WP_H, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_WP_S, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_XP_B, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_XP_D, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_XP_H, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_XP_S, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_ZP_D, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_ZP_H, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCP_ZP_S, ARM64_INS_UQINCP, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCW_WPiI, ARM64_INS_UQINCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCW_XPiI, ARM64_INS_UQINCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQINCW_ZPiI, ARM64_INS_UQINCW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNb, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNh, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNs, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLb, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLd, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLh, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLs, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv16i8, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv1i16, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv1i32, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv1i64, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv1i8, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv2i32, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv2i64, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv4i16, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv4i32, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv8i16, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv8i8, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNb, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNh, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNs, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UQSUB_ZI_B, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZI_D, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZI_H, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZI_S, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZZZ_B, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZZZ_D, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZZZ_H, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UQSUB_ZZZ_S, ARM64_INS_UQSUB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UQSUBv16i8, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv1i16, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv1i32, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv1i64, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv1i8, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv2i32, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv2i64, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv4i16, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv4i32, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv8i16, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQSUBv8i8, ARM64_INS_UQSUB, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv16i8, ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv1i16, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv1i32, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv1i8, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv2i32, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv4i16, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv4i32, ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv8i16, ARM64_INS_UQXTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UQXTNv8i8, ARM64_INS_UQXTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URECPEv2i32, ARM64_INS_URECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URECPEv4i32, ARM64_INS_URECPE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URHADDv16i8, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URHADDv2i32, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URHADDv4i16, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URHADDv4i32, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URHADDv8i16, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URHADDv8i8, ARM64_INS_URHADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv16i8, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv1i64, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv2i32, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv2i64, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv4i16, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv4i32, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv8i16, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHLv8i8, ARM64_INS_URSHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRd, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv16i8_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv2i32_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv2i64_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv4i16_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv4i32_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv8i16_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSHRv8i8_shift, ARM64_INS_URSHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAd, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv16i8_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv2i32_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv2i64_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv4i16_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv4i32_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv8i16_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_URSRAv8i8_shift, ARM64_INS_URSRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLLv2i32_shift, ARM64_INS_USHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLLv4i16_shift, ARM64_INS_USHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLLv8i8_shift, ARM64_INS_USHLL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv16i8, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv1i64, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv2i32, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv2i64, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv4i16, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv4i32, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv8i16, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHLv8i8, ARM64_INS_USHL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRd, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv16i8_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv2i32_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv2i64_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv4i16_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv4i32_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv8i16_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USHRv8i8_shift, ARM64_INS_USHR, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv16i8, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv1i16, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv1i32, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv1i64, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv1i8, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv2i32, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv2i64, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv4i16, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv4i32, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv8i16, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USQADDv8i8, ARM64_INS_USQADD, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAd, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv16i8_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv2i32_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv2i64_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv4i16_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv4i32_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv8i16_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USRAv8i8_shift, ARM64_INS_USRA, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UUNPKHI_ZZ_D, ARM64_INS_UUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UUNPKHI_ZZ_H, ARM64_INS_UUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UUNPKHI_ZZ_S, ARM64_INS_UUNPKHI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UUNPKLO_ZZ_D, ARM64_INS_UUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UUNPKLO_ZZ_H, ARM64_INS_UUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UUNPKLO_ZZ_S, ARM64_INS_UUNPKLO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UXTB_ZPmZ_D, ARM64_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UXTB_ZPmZ_H, ARM64_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UXTB_ZPmZ_S, ARM64_INS_UXTB, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UXTH_ZPmZ_D, ARM64_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UXTH_ZPmZ_S, ARM64_INS_UXTH, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UXTW_ZPmZ_D, ARM64_INS_UXTW, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_PPP_B, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_PPP_D, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_PPP_H, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_PPP_S, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_ZZZ_B, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_ZZZ_D, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_ZZZ_H, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP1_ZZZ_S, ARM64_INS_UZP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UZP1v16i8, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP1v2i32, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP1v2i64, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP1v4i16, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP1v4i32, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP1v8i16, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP1v8i8, ARM64_INS_UZP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_UZP2_PPP_B, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_PPP_D, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_PPP_H, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_PPP_S, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_ZZZ_B, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_ZZZ_D, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_ZZZ_H, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_UZP2_ZZZ_S, ARM64_INS_UZP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_UZP2v16i8, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP2v2i32, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP2v2i64, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP2v4i16, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP2v4i32, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP2v8i16, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_UZP2v8i8, ARM64_INS_UZP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_WHILELE_PWW_B, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PWW_D, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PWW_H, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PWW_S, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PXX_B, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PXX_D, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PXX_H, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELE_PXX_S, ARM64_INS_WHILELE, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PWW_B, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PWW_D, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PWW_H, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PWW_S, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PXX_B, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PXX_D, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PXX_H, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELO_PXX_S, ARM64_INS_WHILELO, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PWW_B, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PWW_D, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PWW_H, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PWW_S, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PXX_B, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PXX_D, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PXX_H, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELS_PXX_S, ARM64_INS_WHILELS, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PWW_B, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PWW_D, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PWW_H, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PWW_S, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PXX_B, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PXX_D, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PXX_H, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WHILELT_PXX_S, ARM64_INS_WHILELT, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_WRFFR, ARM64_INS_WRFFR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_XAR, ARM64_INS_XAR, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_XPACD, ARM64_INS_XPACD, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_XPACI, ARM64_INS_XPACI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_XPACLRI, ARM64_INS_XPACLRI, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_XTNv16i8, ARM64_INS_XTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_XTNv2i32, ARM64_INS_XTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_XTNv4i16, ARM64_INS_XTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_XTNv4i32, ARM64_INS_XTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_XTNv8i16, ARM64_INS_XTN2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_XTNv8i8, ARM64_INS_XTN, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ZIP1_PPP_B, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_PPP_D, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_PPP_H, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_PPP_S, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_ZZZ_B, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_ZZZ_D, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_ZZZ_H, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP1_ZZZ_S, ARM64_INS_ZIP1, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ZIP1v16i8, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP1v2i32, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP1v2i64, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP1v4i16, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP1v4i32, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP1v8i16, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP1v8i8, ARM64_INS_ZIP1, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_ZIP2_PPP_B, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_PPP_D, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_PPP_H, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_PPP_S, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_ZZZ_B, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_ZZZ_D, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_ZZZ_H, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + +{ + AArch64_ZIP2_ZZZ_S, ARM64_INS_ZIP2, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, + { AArch64_ZIP2v16i8, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP2v2i32, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP2v2i64, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP2v4i16, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP2v4i32, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP2v8i16, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + { AArch64_ZIP2v8i8, ARM64_INS_ZIP2, #ifndef CAPSTONE_DIET { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 #endif }, + +{ + AArch64_anonymous_1349, ARM64_INS_PFIRST, +#ifndef CAPSTONE_DIET + { 0 }, { 0 }, { 0 }, 0, 0 +#endif +}, diff --git a/arch/AArch64/AArch64MappingInsnName.inc b/arch/AArch64/AArch64MappingInsnName.inc new file mode 100644 index 000000000..e57765b36 --- /dev/null +++ b/arch/AArch64/AArch64MappingInsnName.inc @@ -0,0 +1,943 @@ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + "abs", // ARM64_INS_ABS, + "adc", // ARM64_INS_ADC, + "adcs", // ARM64_INS_ADCS, + "add", // ARM64_INS_ADD, + "addhn", // ARM64_INS_ADDHN, + "addhn2", // ARM64_INS_ADDHN2, + "addp", // ARM64_INS_ADDP, + "addpl", // ARM64_INS_ADDPL, + "adds", // ARM64_INS_ADDS, + "addv", // ARM64_INS_ADDV, + "addvl", // ARM64_INS_ADDVL, + "adr", // ARM64_INS_ADR, + "adrp", // ARM64_INS_ADRP, + "aesd", // ARM64_INS_AESD, + "aese", // ARM64_INS_AESE, + "aesimc", // ARM64_INS_AESIMC, + "aesmc", // ARM64_INS_AESMC, + "and", // ARM64_INS_AND, + "ands", // ARM64_INS_ANDS, + "andv", // ARM64_INS_ANDV, + "asr", // ARM64_INS_ASR, + "asrd", // ARM64_INS_ASRD, + "asrr", // ARM64_INS_ASRR, + "asrv", // ARM64_INS_ASRV, + "autda", // ARM64_INS_AUTDA, + "autdb", // ARM64_INS_AUTDB, + "autdza", // ARM64_INS_AUTDZA, + "autdzb", // ARM64_INS_AUTDZB, + "autia", // ARM64_INS_AUTIA, + "autia1716", // ARM64_INS_AUTIA1716, + "autiasp", // ARM64_INS_AUTIASP, + "autiaz", // ARM64_INS_AUTIAZ, + "autib", // ARM64_INS_AUTIB, + "autib1716", // ARM64_INS_AUTIB1716, + "autibsp", // ARM64_INS_AUTIBSP, + "autibz", // ARM64_INS_AUTIBZ, + "autiza", // ARM64_INS_AUTIZA, + "autizb", // ARM64_INS_AUTIZB, + "b", // ARM64_INS_B, + "bcax", // ARM64_INS_BCAX, + "bfm", // ARM64_INS_BFM, + "bic", // ARM64_INS_BIC, + "bics", // ARM64_INS_BICS, + "bif", // ARM64_INS_BIF, + "bit", // ARM64_INS_BIT, + "bl", // ARM64_INS_BL, + "blr", // ARM64_INS_BLR, + "blraa", // ARM64_INS_BLRAA, + "blraaz", // ARM64_INS_BLRAAZ, + "blrab", // ARM64_INS_BLRAB, + "blrabz", // ARM64_INS_BLRABZ, + "br", // ARM64_INS_BR, + "braa", // ARM64_INS_BRAA, + "braaz", // ARM64_INS_BRAAZ, + "brab", // ARM64_INS_BRAB, + "brabz", // ARM64_INS_BRABZ, + "brk", // ARM64_INS_BRK, + "brka", // ARM64_INS_BRKA, + "brkas", // ARM64_INS_BRKAS, + "brkb", // ARM64_INS_BRKB, + "brkbs", // ARM64_INS_BRKBS, + "brkn", // ARM64_INS_BRKN, + "brkns", // ARM64_INS_BRKNS, + "brkpa", // ARM64_INS_BRKPA, + "brkpas", // ARM64_INS_BRKPAS, + "brkpb", // ARM64_INS_BRKPB, + "brkpbs", // ARM64_INS_BRKPBS, + "bsl", // ARM64_INS_BSL, + "cas", // ARM64_INS_CAS, + "casa", // ARM64_INS_CASA, + "casab", // ARM64_INS_CASAB, + "casah", // ARM64_INS_CASAH, + "casal", // ARM64_INS_CASAL, + "casalb", // ARM64_INS_CASALB, + "casalh", // ARM64_INS_CASALH, + "casb", // ARM64_INS_CASB, + "cash", // ARM64_INS_CASH, + "casl", // ARM64_INS_CASL, + "caslb", // ARM64_INS_CASLB, + "caslh", // ARM64_INS_CASLH, + "casp", // ARM64_INS_CASP, + "caspa", // ARM64_INS_CASPA, + "caspal", // ARM64_INS_CASPAL, + "caspl", // ARM64_INS_CASPL, + "cbnz", // ARM64_INS_CBNZ, + "cbz", // ARM64_INS_CBZ, + "ccmn", // ARM64_INS_CCMN, + "ccmp", // ARM64_INS_CCMP, + "cfinv", // ARM64_INS_CFINV, + "cinc", // ARM64_INS_CINC, + "cinv", // ARM64_INS_CINV, + "clasta", // ARM64_INS_CLASTA, + "clastb", // ARM64_INS_CLASTB, + "clrex", // ARM64_INS_CLREX, + "cls", // ARM64_INS_CLS, + "clz", // ARM64_INS_CLZ, + "cmeq", // ARM64_INS_CMEQ, + "cmge", // ARM64_INS_CMGE, + "cmgt", // ARM64_INS_CMGT, + "cmhi", // ARM64_INS_CMHI, + "cmhs", // ARM64_INS_CMHS, + "cmle", // ARM64_INS_CMLE, + "cmlo", // ARM64_INS_CMLO, + "cmls", // ARM64_INS_CMLS, + "cmlt", // ARM64_INS_CMLT, + "cmn", // ARM64_INS_CMN, + "cmp", // ARM64_INS_CMP, + "cmpeq", // ARM64_INS_CMPEQ, + "cmpge", // ARM64_INS_CMPGE, + "cmpgt", // ARM64_INS_CMPGT, + "cmphi", // ARM64_INS_CMPHI, + "cmphs", // ARM64_INS_CMPHS, + "cmple", // ARM64_INS_CMPLE, + "cmplo", // ARM64_INS_CMPLO, + "cmpls", // ARM64_INS_CMPLS, + "cmplt", // ARM64_INS_CMPLT, + "cmpne", // ARM64_INS_CMPNE, + "cmtst", // ARM64_INS_CMTST, + "cneg", // ARM64_INS_CNEG, + "cnot", // ARM64_INS_CNOT, + "cnt", // ARM64_INS_CNT, + "cntb", // ARM64_INS_CNTB, + "cntd", // ARM64_INS_CNTD, + "cnth", // ARM64_INS_CNTH, + "cntp", // ARM64_INS_CNTP, + "cntw", // ARM64_INS_CNTW, + "compact", // ARM64_INS_COMPACT, + "cpy", // ARM64_INS_CPY, + "crc32b", // ARM64_INS_CRC32B, + "crc32cb", // ARM64_INS_CRC32CB, + "crc32ch", // ARM64_INS_CRC32CH, + "crc32cw", // ARM64_INS_CRC32CW, + "crc32cx", // ARM64_INS_CRC32CX, + "crc32h", // ARM64_INS_CRC32H, + "crc32w", // ARM64_INS_CRC32W, + "crc32x", // ARM64_INS_CRC32X, + "csdb", // ARM64_INS_CSDB, + "csel", // ARM64_INS_CSEL, + "cset", // ARM64_INS_CSET, + "csetm", // ARM64_INS_CSETM, + "csinc", // ARM64_INS_CSINC, + "csinv", // ARM64_INS_CSINV, + "csneg", // ARM64_INS_CSNEG, + "ctermeq", // ARM64_INS_CTERMEQ, + "ctermne", // ARM64_INS_CTERMNE, + "dcps1", // ARM64_INS_DCPS1, + "dcps2", // ARM64_INS_DCPS2, + "dcps3", // ARM64_INS_DCPS3, + "decb", // ARM64_INS_DECB, + "decd", // ARM64_INS_DECD, + "dech", // ARM64_INS_DECH, + "decp", // ARM64_INS_DECP, + "decw", // ARM64_INS_DECW, + "dmb", // ARM64_INS_DMB, + "drps", // ARM64_INS_DRPS, + "dsb", // ARM64_INS_DSB, + "dup", // ARM64_INS_DUP, + "dupm", // ARM64_INS_DUPM, + "eon", // ARM64_INS_EON, + "eor", // ARM64_INS_EOR, + "eor3", // ARM64_INS_EOR3, + "eors", // ARM64_INS_EORS, + "eorv", // ARM64_INS_EORV, + "eret", // ARM64_INS_ERET, + "eretaa", // ARM64_INS_ERETAA, + "eretab", // ARM64_INS_ERETAB, + "esb", // ARM64_INS_ESB, + "ext", // ARM64_INS_EXT, + "extr", // ARM64_INS_EXTR, + "fabd", // ARM64_INS_FABD, + "fabs", // ARM64_INS_FABS, + "facge", // ARM64_INS_FACGE, + "facgt", // ARM64_INS_FACGT, + "facle", // ARM64_INS_FACLE, + "faclt", // ARM64_INS_FACLT, + "fadd", // ARM64_INS_FADD, + "fadda", // ARM64_INS_FADDA, + "faddp", // ARM64_INS_FADDP, + "faddv", // ARM64_INS_FADDV, + "fcadd", // ARM64_INS_FCADD, + "fccmp", // ARM64_INS_FCCMP, + "fccmpe", // ARM64_INS_FCCMPE, + "fcmeq", // ARM64_INS_FCMEQ, + "fcmge", // ARM64_INS_FCMGE, + "fcmgt", // ARM64_INS_FCMGT, + "fcmla", // ARM64_INS_FCMLA, + "fcmle", // ARM64_INS_FCMLE, + "fcmlt", // ARM64_INS_FCMLT, + "fcmne", // ARM64_INS_FCMNE, + "fcmp", // ARM64_INS_FCMP, + "fcmpe", // ARM64_INS_FCMPE, + "fcmuo", // ARM64_INS_FCMUO, + "fcpy", // ARM64_INS_FCPY, + "fcsel", // ARM64_INS_FCSEL, + "fcvt", // ARM64_INS_FCVT, + "fcvtas", // ARM64_INS_FCVTAS, + "fcvtau", // ARM64_INS_FCVTAU, + "fcvtl", // ARM64_INS_FCVTL, + "fcvtl2", // ARM64_INS_FCVTL2, + "fcvtms", // ARM64_INS_FCVTMS, + "fcvtmu", // ARM64_INS_FCVTMU, + "fcvtn", // ARM64_INS_FCVTN, + "fcvtn2", // ARM64_INS_FCVTN2, + "fcvtns", // ARM64_INS_FCVTNS, + "fcvtnu", // ARM64_INS_FCVTNU, + "fcvtps", // ARM64_INS_FCVTPS, + "fcvtpu", // ARM64_INS_FCVTPU, + "fcvtxn", // ARM64_INS_FCVTXN, + "fcvtxn2", // ARM64_INS_FCVTXN2, + "fcvtzs", // ARM64_INS_FCVTZS, + "fcvtzu", // ARM64_INS_FCVTZU, + "fdiv", // ARM64_INS_FDIV, + "fdivr", // ARM64_INS_FDIVR, + "fdup", // ARM64_INS_FDUP, + "fexpa", // ARM64_INS_FEXPA, + "fjcvtzs", // ARM64_INS_FJCVTZS, + "fmad", // ARM64_INS_FMAD, + "fmadd", // ARM64_INS_FMADD, + "fmax", // ARM64_INS_FMAX, + "fmaxnm", // ARM64_INS_FMAXNM, + "fmaxnmp", // ARM64_INS_FMAXNMP, + "fmaxnmv", // ARM64_INS_FMAXNMV, + "fmaxp", // ARM64_INS_FMAXP, + "fmaxv", // ARM64_INS_FMAXV, + "fmin", // ARM64_INS_FMIN, + "fminnm", // ARM64_INS_FMINNM, + "fminnmp", // ARM64_INS_FMINNMP, + "fminnmv", // ARM64_INS_FMINNMV, + "fminp", // ARM64_INS_FMINP, + "fminv", // ARM64_INS_FMINV, + "fmla", // ARM64_INS_FMLA, + "fmls", // ARM64_INS_FMLS, + "fmov", // ARM64_INS_FMOV, + "fmsb", // ARM64_INS_FMSB, + "fmsub", // ARM64_INS_FMSUB, + "fmul", // ARM64_INS_FMUL, + "fmulx", // ARM64_INS_FMULX, + "fneg", // ARM64_INS_FNEG, + "fnmad", // ARM64_INS_FNMAD, + "fnmadd", // ARM64_INS_FNMADD, + "fnmla", // ARM64_INS_FNMLA, + "fnmls", // ARM64_INS_FNMLS, + "fnmsb", // ARM64_INS_FNMSB, + "fnmsub", // ARM64_INS_FNMSUB, + "fnmul", // ARM64_INS_FNMUL, + "frecpe", // ARM64_INS_FRECPE, + "frecps", // ARM64_INS_FRECPS, + "frecpx", // ARM64_INS_FRECPX, + "frinta", // ARM64_INS_FRINTA, + "frinti", // ARM64_INS_FRINTI, + "frintm", // ARM64_INS_FRINTM, + "frintn", // ARM64_INS_FRINTN, + "frintp", // ARM64_INS_FRINTP, + "frintx", // ARM64_INS_FRINTX, + "frintz", // ARM64_INS_FRINTZ, + "frsqrte", // ARM64_INS_FRSQRTE, + "frsqrts", // ARM64_INS_FRSQRTS, + "fscale", // ARM64_INS_FSCALE, + "fsqrt", // ARM64_INS_FSQRT, + "fsub", // ARM64_INS_FSUB, + "fsubr", // ARM64_INS_FSUBR, + "ftmad", // ARM64_INS_FTMAD, + "ftsmul", // ARM64_INS_FTSMUL, + "ftssel", // ARM64_INS_FTSSEL, + "hint", // ARM64_INS_HINT, + "hlt", // ARM64_INS_HLT, + "hvc", // ARM64_INS_HVC, + "incb", // ARM64_INS_INCB, + "incd", // ARM64_INS_INCD, + "inch", // ARM64_INS_INCH, + "incp", // ARM64_INS_INCP, + "incw", // ARM64_INS_INCW, + "index", // ARM64_INS_INDEX, + "ins", // ARM64_INS_INS, + "insr", // ARM64_INS_INSR, + "isb", // ARM64_INS_ISB, + "lasta", // ARM64_INS_LASTA, + "lastb", // ARM64_INS_LASTB, + "ld1", // ARM64_INS_LD1, + "ld1b", // ARM64_INS_LD1B, + "ld1d", // ARM64_INS_LD1D, + "ld1h", // ARM64_INS_LD1H, + "ld1r", // ARM64_INS_LD1R, + "ld1rb", // ARM64_INS_LD1RB, + "ld1rd", // ARM64_INS_LD1RD, + "ld1rh", // ARM64_INS_LD1RH, + "ld1rqb", // ARM64_INS_LD1RQB, + "ld1rqd", // ARM64_INS_LD1RQD, + "ld1rqh", // ARM64_INS_LD1RQH, + "ld1rqw", // ARM64_INS_LD1RQW, + "ld1rsb", // ARM64_INS_LD1RSB, + "ld1rsh", // ARM64_INS_LD1RSH, + "ld1rsw", // ARM64_INS_LD1RSW, + "ld1rw", // ARM64_INS_LD1RW, + "ld1sb", // ARM64_INS_LD1SB, + "ld1sh", // ARM64_INS_LD1SH, + "ld1sw", // ARM64_INS_LD1SW, + "ld1w", // ARM64_INS_LD1W, + "ld2", // ARM64_INS_LD2, + "ld2b", // ARM64_INS_LD2B, + "ld2d", // ARM64_INS_LD2D, + "ld2h", // ARM64_INS_LD2H, + "ld2r", // ARM64_INS_LD2R, + "ld2w", // ARM64_INS_LD2W, + "ld3", // ARM64_INS_LD3, + "ld3b", // ARM64_INS_LD3B, + "ld3d", // ARM64_INS_LD3D, + "ld3h", // ARM64_INS_LD3H, + "ld3r", // ARM64_INS_LD3R, + "ld3w", // ARM64_INS_LD3W, + "ld4", // ARM64_INS_LD4, + "ld4b", // ARM64_INS_LD4B, + "ld4d", // ARM64_INS_LD4D, + "ld4h", // ARM64_INS_LD4H, + "ld4r", // ARM64_INS_LD4R, + "ld4w", // ARM64_INS_LD4W, + "ldadd", // ARM64_INS_LDADD, + "ldadda", // ARM64_INS_LDADDA, + "ldaddab", // ARM64_INS_LDADDAB, + "ldaddah", // ARM64_INS_LDADDAH, + "ldaddal", // ARM64_INS_LDADDAL, + "ldaddalb", // ARM64_INS_LDADDALB, + "ldaddalh", // ARM64_INS_LDADDALH, + "ldaddb", // ARM64_INS_LDADDB, + "ldaddh", // ARM64_INS_LDADDH, + "ldaddl", // ARM64_INS_LDADDL, + "ldaddlb", // ARM64_INS_LDADDLB, + "ldaddlh", // ARM64_INS_LDADDLH, + "ldapr", // ARM64_INS_LDAPR, + "ldaprb", // ARM64_INS_LDAPRB, + "ldaprh", // ARM64_INS_LDAPRH, + "ldapur", // ARM64_INS_LDAPUR, + "ldapurb", // ARM64_INS_LDAPURB, + "ldapurh", // ARM64_INS_LDAPURH, + "ldapursb", // ARM64_INS_LDAPURSB, + "ldapursh", // ARM64_INS_LDAPURSH, + "ldapursw", // ARM64_INS_LDAPURSW, + "ldar", // ARM64_INS_LDAR, + "ldarb", // ARM64_INS_LDARB, + "ldarh", // ARM64_INS_LDARH, + "ldaxp", // ARM64_INS_LDAXP, + "ldaxr", // ARM64_INS_LDAXR, + "ldaxrb", // ARM64_INS_LDAXRB, + "ldaxrh", // ARM64_INS_LDAXRH, + "ldclr", // ARM64_INS_LDCLR, + "ldclra", // ARM64_INS_LDCLRA, + "ldclrab", // ARM64_INS_LDCLRAB, + "ldclrah", // ARM64_INS_LDCLRAH, + "ldclral", // ARM64_INS_LDCLRAL, + "ldclralb", // ARM64_INS_LDCLRALB, + "ldclralh", // ARM64_INS_LDCLRALH, + "ldclrb", // ARM64_INS_LDCLRB, + "ldclrh", // ARM64_INS_LDCLRH, + "ldclrl", // ARM64_INS_LDCLRL, + "ldclrlb", // ARM64_INS_LDCLRLB, + "ldclrlh", // ARM64_INS_LDCLRLH, + "ldeor", // ARM64_INS_LDEOR, + "ldeora", // ARM64_INS_LDEORA, + "ldeorab", // ARM64_INS_LDEORAB, + "ldeorah", // ARM64_INS_LDEORAH, + "ldeoral", // ARM64_INS_LDEORAL, + "ldeoralb", // ARM64_INS_LDEORALB, + "ldeoralh", // ARM64_INS_LDEORALH, + "ldeorb", // ARM64_INS_LDEORB, + "ldeorh", // ARM64_INS_LDEORH, + "ldeorl", // ARM64_INS_LDEORL, + "ldeorlb", // ARM64_INS_LDEORLB, + "ldeorlh", // ARM64_INS_LDEORLH, + "ldff1b", // ARM64_INS_LDFF1B, + "ldff1d", // ARM64_INS_LDFF1D, + "ldff1h", // ARM64_INS_LDFF1H, + "ldff1sb", // ARM64_INS_LDFF1SB, + "ldff1sh", // ARM64_INS_LDFF1SH, + "ldff1sw", // ARM64_INS_LDFF1SW, + "ldff1w", // ARM64_INS_LDFF1W, + "ldlar", // ARM64_INS_LDLAR, + "ldlarb", // ARM64_INS_LDLARB, + "ldlarh", // ARM64_INS_LDLARH, + "ldnf1b", // ARM64_INS_LDNF1B, + "ldnf1d", // ARM64_INS_LDNF1D, + "ldnf1h", // ARM64_INS_LDNF1H, + "ldnf1sb", // ARM64_INS_LDNF1SB, + "ldnf1sh", // ARM64_INS_LDNF1SH, + "ldnf1sw", // ARM64_INS_LDNF1SW, + "ldnf1w", // ARM64_INS_LDNF1W, + "ldnp", // ARM64_INS_LDNP, + "ldnt1b", // ARM64_INS_LDNT1B, + "ldnt1d", // ARM64_INS_LDNT1D, + "ldnt1h", // ARM64_INS_LDNT1H, + "ldnt1w", // ARM64_INS_LDNT1W, + "ldp", // ARM64_INS_LDP, + "ldpsw", // ARM64_INS_LDPSW, + "ldr", // ARM64_INS_LDR, + "ldraa", // ARM64_INS_LDRAA, + "ldrab", // ARM64_INS_LDRAB, + "ldrb", // ARM64_INS_LDRB, + "ldrh", // ARM64_INS_LDRH, + "ldrsb", // ARM64_INS_LDRSB, + "ldrsh", // ARM64_INS_LDRSH, + "ldrsw", // ARM64_INS_LDRSW, + "ldset", // ARM64_INS_LDSET, + "ldseta", // ARM64_INS_LDSETA, + "ldsetab", // ARM64_INS_LDSETAB, + "ldsetah", // ARM64_INS_LDSETAH, + "ldsetal", // ARM64_INS_LDSETAL, + "ldsetalb", // ARM64_INS_LDSETALB, + "ldsetalh", // ARM64_INS_LDSETALH, + "ldsetb", // ARM64_INS_LDSETB, + "ldseth", // ARM64_INS_LDSETH, + "ldsetl", // ARM64_INS_LDSETL, + "ldsetlb", // ARM64_INS_LDSETLB, + "ldsetlh", // ARM64_INS_LDSETLH, + "ldsmax", // ARM64_INS_LDSMAX, + "ldsmaxa", // ARM64_INS_LDSMAXA, + "ldsmaxab", // ARM64_INS_LDSMAXAB, + "ldsmaxah", // ARM64_INS_LDSMAXAH, + "ldsmaxal", // ARM64_INS_LDSMAXAL, + "ldsmaxalb", // ARM64_INS_LDSMAXALB, + "ldsmaxalh", // ARM64_INS_LDSMAXALH, + "ldsmaxb", // ARM64_INS_LDSMAXB, + "ldsmaxh", // ARM64_INS_LDSMAXH, + "ldsmaxl", // ARM64_INS_LDSMAXL, + "ldsmaxlb", // ARM64_INS_LDSMAXLB, + "ldsmaxlh", // ARM64_INS_LDSMAXLH, + "ldsmin", // ARM64_INS_LDSMIN, + "ldsmina", // ARM64_INS_LDSMINA, + "ldsminab", // ARM64_INS_LDSMINAB, + "ldsminah", // ARM64_INS_LDSMINAH, + "ldsminal", // ARM64_INS_LDSMINAL, + "ldsminalb", // ARM64_INS_LDSMINALB, + "ldsminalh", // ARM64_INS_LDSMINALH, + "ldsminb", // ARM64_INS_LDSMINB, + "ldsminh", // ARM64_INS_LDSMINH, + "ldsminl", // ARM64_INS_LDSMINL, + "ldsminlb", // ARM64_INS_LDSMINLB, + "ldsminlh", // ARM64_INS_LDSMINLH, + "ldtr", // ARM64_INS_LDTR, + "ldtrb", // ARM64_INS_LDTRB, + "ldtrh", // ARM64_INS_LDTRH, + "ldtrsb", // ARM64_INS_LDTRSB, + "ldtrsh", // ARM64_INS_LDTRSH, + "ldtrsw", // ARM64_INS_LDTRSW, + "ldumax", // ARM64_INS_LDUMAX, + "ldumaxa", // ARM64_INS_LDUMAXA, + "ldumaxab", // ARM64_INS_LDUMAXAB, + "ldumaxah", // ARM64_INS_LDUMAXAH, + "ldumaxal", // ARM64_INS_LDUMAXAL, + "ldumaxalb", // ARM64_INS_LDUMAXALB, + "ldumaxalh", // ARM64_INS_LDUMAXALH, + "ldumaxb", // ARM64_INS_LDUMAXB, + "ldumaxh", // ARM64_INS_LDUMAXH, + "ldumaxl", // ARM64_INS_LDUMAXL, + "ldumaxlb", // ARM64_INS_LDUMAXLB, + "ldumaxlh", // ARM64_INS_LDUMAXLH, + "ldumin", // ARM64_INS_LDUMIN, + "ldumina", // ARM64_INS_LDUMINA, + "lduminab", // ARM64_INS_LDUMINAB, + "lduminah", // ARM64_INS_LDUMINAH, + "lduminal", // ARM64_INS_LDUMINAL, + "lduminalb", // ARM64_INS_LDUMINALB, + "lduminalh", // ARM64_INS_LDUMINALH, + "lduminb", // ARM64_INS_LDUMINB, + "lduminh", // ARM64_INS_LDUMINH, + "lduminl", // ARM64_INS_LDUMINL, + "lduminlb", // ARM64_INS_LDUMINLB, + "lduminlh", // ARM64_INS_LDUMINLH, + "ldur", // ARM64_INS_LDUR, + "ldurb", // ARM64_INS_LDURB, + "ldurh", // ARM64_INS_LDURH, + "ldursb", // ARM64_INS_LDURSB, + "ldursh", // ARM64_INS_LDURSH, + "ldursw", // ARM64_INS_LDURSW, + "ldxp", // ARM64_INS_LDXP, + "ldxr", // ARM64_INS_LDXR, + "ldxrb", // ARM64_INS_LDXRB, + "ldxrh", // ARM64_INS_LDXRH, + "lsl", // ARM64_INS_LSL, + "lslr", // ARM64_INS_LSLR, + "lslv", // ARM64_INS_LSLV, + "lsr", // ARM64_INS_LSR, + "lsrr", // ARM64_INS_LSRR, + "lsrv", // ARM64_INS_LSRV, + "mad", // ARM64_INS_MAD, + "madd", // ARM64_INS_MADD, + "mla", // ARM64_INS_MLA, + "mls", // ARM64_INS_MLS, + "mneg", // ARM64_INS_MNEG, + "mov", // ARM64_INS_MOV, + "movi", // ARM64_INS_MOVI, + "movk", // ARM64_INS_MOVK, + "movn", // ARM64_INS_MOVN, + "movprfx", // ARM64_INS_MOVPRFX, + "movs", // ARM64_INS_MOVS, + "movz", // ARM64_INS_MOVZ, + "mrs", // ARM64_INS_MRS, + "msb", // ARM64_INS_MSB, + "msr", // ARM64_INS_MSR, + "msub", // ARM64_INS_MSUB, + "mul", // ARM64_INS_MUL, + "mvn", // ARM64_INS_MVN, + "mvni", // ARM64_INS_MVNI, + "nand", // ARM64_INS_NAND, + "nands", // ARM64_INS_NANDS, + "neg", // ARM64_INS_NEG, + "negs", // ARM64_INS_NEGS, + "ngc", // ARM64_INS_NGC, + "ngcs", // ARM64_INS_NGCS, + "nop", // ARM64_INS_NOP, + "nor", // ARM64_INS_NOR, + "nors", // ARM64_INS_NORS, + "not", // ARM64_INS_NOT, + "nots", // ARM64_INS_NOTS, + "orn", // ARM64_INS_ORN, + "orns", // ARM64_INS_ORNS, + "orr", // ARM64_INS_ORR, + "orrs", // ARM64_INS_ORRS, + "orv", // ARM64_INS_ORV, + "pacda", // ARM64_INS_PACDA, + "pacdb", // ARM64_INS_PACDB, + "pacdza", // ARM64_INS_PACDZA, + "pacdzb", // ARM64_INS_PACDZB, + "pacga", // ARM64_INS_PACGA, + "pacia", // ARM64_INS_PACIA, + "pacia1716", // ARM64_INS_PACIA1716, + "paciasp", // ARM64_INS_PACIASP, + "paciaz", // ARM64_INS_PACIAZ, + "pacib", // ARM64_INS_PACIB, + "pacib1716", // ARM64_INS_PACIB1716, + "pacibsp", // ARM64_INS_PACIBSP, + "pacibz", // ARM64_INS_PACIBZ, + "paciza", // ARM64_INS_PACIZA, + "pacizb", // ARM64_INS_PACIZB, + "pfalse", // ARM64_INS_PFALSE, + "pfirst", // ARM64_INS_PFIRST, + "pmul", // ARM64_INS_PMUL, + "pmull", // ARM64_INS_PMULL, + "pmull2", // ARM64_INS_PMULL2, + "pnext", // ARM64_INS_PNEXT, + "prfb", // ARM64_INS_PRFB, + "prfd", // ARM64_INS_PRFD, + "prfh", // ARM64_INS_PRFH, + "prfm", // ARM64_INS_PRFM, + "prfum", // ARM64_INS_PRFUM, + "prfw", // ARM64_INS_PRFW, + "psb", // ARM64_INS_PSB, + "ptest", // ARM64_INS_PTEST, + "ptrue", // ARM64_INS_PTRUE, + "ptrues", // ARM64_INS_PTRUES, + "punpkhi", // ARM64_INS_PUNPKHI, + "punpklo", // ARM64_INS_PUNPKLO, + "raddhn", // ARM64_INS_RADDHN, + "raddhn2", // ARM64_INS_RADDHN2, + "rax1", // ARM64_INS_RAX1, + "rbit", // ARM64_INS_RBIT, + "rdffr", // ARM64_INS_RDFFR, + "rdffrs", // ARM64_INS_RDFFRS, + "rdvl", // ARM64_INS_RDVL, + "ret", // ARM64_INS_RET, + "retaa", // ARM64_INS_RETAA, + "retab", // ARM64_INS_RETAB, + "rev", // ARM64_INS_REV, + "rev16", // ARM64_INS_REV16, + "rev32", // ARM64_INS_REV32, + "rev64", // ARM64_INS_REV64, + "revb", // ARM64_INS_REVB, + "revh", // ARM64_INS_REVH, + "revw", // ARM64_INS_REVW, + "rmif", // ARM64_INS_RMIF, + "ror", // ARM64_INS_ROR, + "rorv", // ARM64_INS_RORV, + "rshrn", // ARM64_INS_RSHRN, + "rshrn2", // ARM64_INS_RSHRN2, + "rsubhn", // ARM64_INS_RSUBHN, + "rsubhn2", // ARM64_INS_RSUBHN2, + "saba", // ARM64_INS_SABA, + "sabal", // ARM64_INS_SABAL, + "sabal2", // ARM64_INS_SABAL2, + "sabd", // ARM64_INS_SABD, + "sabdl", // ARM64_INS_SABDL, + "sabdl2", // ARM64_INS_SABDL2, + "sadalp", // ARM64_INS_SADALP, + "saddl", // ARM64_INS_SADDL, + "saddl2", // ARM64_INS_SADDL2, + "saddlp", // ARM64_INS_SADDLP, + "saddlv", // ARM64_INS_SADDLV, + "saddv", // ARM64_INS_SADDV, + "saddw", // ARM64_INS_SADDW, + "saddw2", // ARM64_INS_SADDW2, + "sbc", // ARM64_INS_SBC, + "sbcs", // ARM64_INS_SBCS, + "sbfm", // ARM64_INS_SBFM, + "scvtf", // ARM64_INS_SCVTF, + "sdiv", // ARM64_INS_SDIV, + "sdivr", // ARM64_INS_SDIVR, + "sdot", // ARM64_INS_SDOT, + "sel", // ARM64_INS_SEL, + "setf16", // ARM64_INS_SETF16, + "setf8", // ARM64_INS_SETF8, + "setffr", // ARM64_INS_SETFFR, + "sev", // ARM64_INS_SEV, + "sevl", // ARM64_INS_SEVL, + "sha1c", // ARM64_INS_SHA1C, + "sha1h", // ARM64_INS_SHA1H, + "sha1m", // ARM64_INS_SHA1M, + "sha1p", // ARM64_INS_SHA1P, + "sha1su0", // ARM64_INS_SHA1SU0, + "sha1su1", // ARM64_INS_SHA1SU1, + "sha256h", // ARM64_INS_SHA256H, + "sha256h2", // ARM64_INS_SHA256H2, + "sha256su0", // ARM64_INS_SHA256SU0, + "sha256su1", // ARM64_INS_SHA256SU1, + "sha512h", // ARM64_INS_SHA512H, + "sha512h2", // ARM64_INS_SHA512H2, + "sha512su0", // ARM64_INS_SHA512SU0, + "sha512su1", // ARM64_INS_SHA512SU1, + "shadd", // ARM64_INS_SHADD, + "shl", // ARM64_INS_SHL, + "shll", // ARM64_INS_SHLL, + "shll2", // ARM64_INS_SHLL2, + "shrn", // ARM64_INS_SHRN, + "shrn2", // ARM64_INS_SHRN2, + "shsub", // ARM64_INS_SHSUB, + "sli", // ARM64_INS_SLI, + "sm3partw1", // ARM64_INS_SM3PARTW1, + "sm3partw2", // ARM64_INS_SM3PARTW2, + "sm3ss1", // ARM64_INS_SM3SS1, + "sm3tt1a", // ARM64_INS_SM3TT1A, + "sm3tt1b", // ARM64_INS_SM3TT1B, + "sm3tt2a", // ARM64_INS_SM3TT2A, + "sm3tt2b", // ARM64_INS_SM3TT2B, + "sm4e", // ARM64_INS_SM4E, + "sm4ekey", // ARM64_INS_SM4EKEY, + "smaddl", // ARM64_INS_SMADDL, + "smax", // ARM64_INS_SMAX, + "smaxp", // ARM64_INS_SMAXP, + "smaxv", // ARM64_INS_SMAXV, + "smc", // ARM64_INS_SMC, + "smin", // ARM64_INS_SMIN, + "sminp", // ARM64_INS_SMINP, + "sminv", // ARM64_INS_SMINV, + "smlal", // ARM64_INS_SMLAL, + "smlal2", // ARM64_INS_SMLAL2, + "smlsl", // ARM64_INS_SMLSL, + "smlsl2", // ARM64_INS_SMLSL2, + "smnegl", // ARM64_INS_SMNEGL, + "smov", // ARM64_INS_SMOV, + "smsubl", // ARM64_INS_SMSUBL, + "smulh", // ARM64_INS_SMULH, + "smull", // ARM64_INS_SMULL, + "smull2", // ARM64_INS_SMULL2, + "splice", // ARM64_INS_SPLICE, + "sqabs", // ARM64_INS_SQABS, + "sqadd", // ARM64_INS_SQADD, + "sqdecb", // ARM64_INS_SQDECB, + "sqdecd", // ARM64_INS_SQDECD, + "sqdech", // ARM64_INS_SQDECH, + "sqdecp", // ARM64_INS_SQDECP, + "sqdecw", // ARM64_INS_SQDECW, + "sqdmlal", // ARM64_INS_SQDMLAL, + "sqdmlal2", // ARM64_INS_SQDMLAL2, + "sqdmlsl", // ARM64_INS_SQDMLSL, + "sqdmlsl2", // ARM64_INS_SQDMLSL2, + "sqdmulh", // ARM64_INS_SQDMULH, + "sqdmull", // ARM64_INS_SQDMULL, + "sqdmull2", // ARM64_INS_SQDMULL2, + "sqincb", // ARM64_INS_SQINCB, + "sqincd", // ARM64_INS_SQINCD, + "sqinch", // ARM64_INS_SQINCH, + "sqincp", // ARM64_INS_SQINCP, + "sqincw", // ARM64_INS_SQINCW, + "sqneg", // ARM64_INS_SQNEG, + "sqrdmlah", // ARM64_INS_SQRDMLAH, + "sqrdmlsh", // ARM64_INS_SQRDMLSH, + "sqrdmulh", // ARM64_INS_SQRDMULH, + "sqrshl", // ARM64_INS_SQRSHL, + "sqrshrn", // ARM64_INS_SQRSHRN, + "sqrshrn2", // ARM64_INS_SQRSHRN2, + "sqrshrun", // ARM64_INS_SQRSHRUN, + "sqrshrun2", // ARM64_INS_SQRSHRUN2, + "sqshl", // ARM64_INS_SQSHL, + "sqshlu", // ARM64_INS_SQSHLU, + "sqshrn", // ARM64_INS_SQSHRN, + "sqshrn2", // ARM64_INS_SQSHRN2, + "sqshrun", // ARM64_INS_SQSHRUN, + "sqshrun2", // ARM64_INS_SQSHRUN2, + "sqsub", // ARM64_INS_SQSUB, + "sqxtn", // ARM64_INS_SQXTN, + "sqxtn2", // ARM64_INS_SQXTN2, + "sqxtun", // ARM64_INS_SQXTUN, + "sqxtun2", // ARM64_INS_SQXTUN2, + "srhadd", // ARM64_INS_SRHADD, + "sri", // ARM64_INS_SRI, + "srshl", // ARM64_INS_SRSHL, + "srshr", // ARM64_INS_SRSHR, + "srsra", // ARM64_INS_SRSRA, + "sshl", // ARM64_INS_SSHL, + "sshll", // ARM64_INS_SSHLL, + "sshll2", // ARM64_INS_SSHLL2, + "sshr", // ARM64_INS_SSHR, + "ssra", // ARM64_INS_SSRA, + "ssubl", // ARM64_INS_SSUBL, + "ssubl2", // ARM64_INS_SSUBL2, + "ssubw", // ARM64_INS_SSUBW, + "ssubw2", // ARM64_INS_SSUBW2, + "st1", // ARM64_INS_ST1, + "st1b", // ARM64_INS_ST1B, + "st1d", // ARM64_INS_ST1D, + "st1h", // ARM64_INS_ST1H, + "st1w", // ARM64_INS_ST1W, + "st2", // ARM64_INS_ST2, + "st2b", // ARM64_INS_ST2B, + "st2d", // ARM64_INS_ST2D, + "st2h", // ARM64_INS_ST2H, + "st2w", // ARM64_INS_ST2W, + "st3", // ARM64_INS_ST3, + "st3b", // ARM64_INS_ST3B, + "st3d", // ARM64_INS_ST3D, + "st3h", // ARM64_INS_ST3H, + "st3w", // ARM64_INS_ST3W, + "st4", // ARM64_INS_ST4, + "st4b", // ARM64_INS_ST4B, + "st4d", // ARM64_INS_ST4D, + "st4h", // ARM64_INS_ST4H, + "st4w", // ARM64_INS_ST4W, + "stadd", // ARM64_INS_STADD, + "staddb", // ARM64_INS_STADDB, + "staddh", // ARM64_INS_STADDH, + "staddl", // ARM64_INS_STADDL, + "staddlb", // ARM64_INS_STADDLB, + "staddlh", // ARM64_INS_STADDLH, + "stclr", // ARM64_INS_STCLR, + "stclrb", // ARM64_INS_STCLRB, + "stclrh", // ARM64_INS_STCLRH, + "stclrl", // ARM64_INS_STCLRL, + "stclrlb", // ARM64_INS_STCLRLB, + "stclrlh", // ARM64_INS_STCLRLH, + "steor", // ARM64_INS_STEOR, + "steorb", // ARM64_INS_STEORB, + "steorh", // ARM64_INS_STEORH, + "steorl", // ARM64_INS_STEORL, + "steorlb", // ARM64_INS_STEORLB, + "steorlh", // ARM64_INS_STEORLH, + "stllr", // ARM64_INS_STLLR, + "stllrb", // ARM64_INS_STLLRB, + "stllrh", // ARM64_INS_STLLRH, + "stlr", // ARM64_INS_STLR, + "stlrb", // ARM64_INS_STLRB, + "stlrh", // ARM64_INS_STLRH, + "stlur", // ARM64_INS_STLUR, + "stlurb", // ARM64_INS_STLURB, + "stlurh", // ARM64_INS_STLURH, + "stlxp", // ARM64_INS_STLXP, + "stlxr", // ARM64_INS_STLXR, + "stlxrb", // ARM64_INS_STLXRB, + "stlxrh", // ARM64_INS_STLXRH, + "stnp", // ARM64_INS_STNP, + "stnt1b", // ARM64_INS_STNT1B, + "stnt1d", // ARM64_INS_STNT1D, + "stnt1h", // ARM64_INS_STNT1H, + "stnt1w", // ARM64_INS_STNT1W, + "stp", // ARM64_INS_STP, + "str", // ARM64_INS_STR, + "strb", // ARM64_INS_STRB, + "strh", // ARM64_INS_STRH, + "stset", // ARM64_INS_STSET, + "stsetb", // ARM64_INS_STSETB, + "stseth", // ARM64_INS_STSETH, + "stsetl", // ARM64_INS_STSETL, + "stsetlb", // ARM64_INS_STSETLB, + "stsetlh", // ARM64_INS_STSETLH, + "stsmax", // ARM64_INS_STSMAX, + "stsmaxb", // ARM64_INS_STSMAXB, + "stsmaxh", // ARM64_INS_STSMAXH, + "stsmaxl", // ARM64_INS_STSMAXL, + "stsmaxlb", // ARM64_INS_STSMAXLB, + "stsmaxlh", // ARM64_INS_STSMAXLH, + "stsmin", // ARM64_INS_STSMIN, + "stsminb", // ARM64_INS_STSMINB, + "stsminh", // ARM64_INS_STSMINH, + "stsminl", // ARM64_INS_STSMINL, + "stsminlb", // ARM64_INS_STSMINLB, + "stsminlh", // ARM64_INS_STSMINLH, + "sttr", // ARM64_INS_STTR, + "sttrb", // ARM64_INS_STTRB, + "sttrh", // ARM64_INS_STTRH, + "stumax", // ARM64_INS_STUMAX, + "stumaxb", // ARM64_INS_STUMAXB, + "stumaxh", // ARM64_INS_STUMAXH, + "stumaxl", // ARM64_INS_STUMAXL, + "stumaxlb", // ARM64_INS_STUMAXLB, + "stumaxlh", // ARM64_INS_STUMAXLH, + "stumin", // ARM64_INS_STUMIN, + "stuminb", // ARM64_INS_STUMINB, + "stuminh", // ARM64_INS_STUMINH, + "stuminl", // ARM64_INS_STUMINL, + "stuminlb", // ARM64_INS_STUMINLB, + "stuminlh", // ARM64_INS_STUMINLH, + "stur", // ARM64_INS_STUR, + "sturb", // ARM64_INS_STURB, + "sturh", // ARM64_INS_STURH, + "stxp", // ARM64_INS_STXP, + "stxr", // ARM64_INS_STXR, + "stxrb", // ARM64_INS_STXRB, + "stxrh", // ARM64_INS_STXRH, + "sub", // ARM64_INS_SUB, + "subhn", // ARM64_INS_SUBHN, + "subhn2", // ARM64_INS_SUBHN2, + "subr", // ARM64_INS_SUBR, + "subs", // ARM64_INS_SUBS, + "sunpkhi", // ARM64_INS_SUNPKHI, + "sunpklo", // ARM64_INS_SUNPKLO, + "suqadd", // ARM64_INS_SUQADD, + "svc", // ARM64_INS_SVC, + "swp", // ARM64_INS_SWP, + "swpa", // ARM64_INS_SWPA, + "swpab", // ARM64_INS_SWPAB, + "swpah", // ARM64_INS_SWPAH, + "swpal", // ARM64_INS_SWPAL, + "swpalb", // ARM64_INS_SWPALB, + "swpalh", // ARM64_INS_SWPALH, + "swpb", // ARM64_INS_SWPB, + "swph", // ARM64_INS_SWPH, + "swpl", // ARM64_INS_SWPL, + "swplb", // ARM64_INS_SWPLB, + "swplh", // ARM64_INS_SWPLH, + "sxtb", // ARM64_INS_SXTB, + "sxth", // ARM64_INS_SXTH, + "sxtl", // ARM64_INS_SXTL, + "sxtl2", // ARM64_INS_SXTL2, + "sxtw", // ARM64_INS_SXTW, + "sys", // ARM64_INS_SYS, + "sysl", // ARM64_INS_SYSL, + "tbl", // ARM64_INS_TBL, + "tbnz", // ARM64_INS_TBNZ, + "tbx", // ARM64_INS_TBX, + "tbz", // ARM64_INS_TBZ, + "trn1", // ARM64_INS_TRN1, + "trn2", // ARM64_INS_TRN2, + "tsb", // ARM64_INS_TSB, + "tst", // ARM64_INS_TST, + "uaba", // ARM64_INS_UABA, + "uabal", // ARM64_INS_UABAL, + "uabal2", // ARM64_INS_UABAL2, + "uabd", // ARM64_INS_UABD, + "uabdl", // ARM64_INS_UABDL, + "uabdl2", // ARM64_INS_UABDL2, + "uadalp", // ARM64_INS_UADALP, + "uaddl", // ARM64_INS_UADDL, + "uaddl2", // ARM64_INS_UADDL2, + "uaddlp", // ARM64_INS_UADDLP, + "uaddlv", // ARM64_INS_UADDLV, + "uaddv", // ARM64_INS_UADDV, + "uaddw", // ARM64_INS_UADDW, + "uaddw2", // ARM64_INS_UADDW2, + "ubfm", // ARM64_INS_UBFM, + "ucvtf", // ARM64_INS_UCVTF, + "udiv", // ARM64_INS_UDIV, + "udivr", // ARM64_INS_UDIVR, + "udot", // ARM64_INS_UDOT, + "uhadd", // ARM64_INS_UHADD, + "uhsub", // ARM64_INS_UHSUB, + "umaddl", // ARM64_INS_UMADDL, + "umax", // ARM64_INS_UMAX, + "umaxp", // ARM64_INS_UMAXP, + "umaxv", // ARM64_INS_UMAXV, + "umin", // ARM64_INS_UMIN, + "uminp", // ARM64_INS_UMINP, + "uminv", // ARM64_INS_UMINV, + "umlal", // ARM64_INS_UMLAL, + "umlal2", // ARM64_INS_UMLAL2, + "umlsl", // ARM64_INS_UMLSL, + "umlsl2", // ARM64_INS_UMLSL2, + "umnegl", // ARM64_INS_UMNEGL, + "umov", // ARM64_INS_UMOV, + "umsubl", // ARM64_INS_UMSUBL, + "umulh", // ARM64_INS_UMULH, + "umull", // ARM64_INS_UMULL, + "umull2", // ARM64_INS_UMULL2, + "uqadd", // ARM64_INS_UQADD, + "uqdecb", // ARM64_INS_UQDECB, + "uqdecd", // ARM64_INS_UQDECD, + "uqdech", // ARM64_INS_UQDECH, + "uqdecp", // ARM64_INS_UQDECP, + "uqdecw", // ARM64_INS_UQDECW, + "uqincb", // ARM64_INS_UQINCB, + "uqincd", // ARM64_INS_UQINCD, + "uqinch", // ARM64_INS_UQINCH, + "uqincp", // ARM64_INS_UQINCP, + "uqincw", // ARM64_INS_UQINCW, + "uqrshl", // ARM64_INS_UQRSHL, + "uqrshrn", // ARM64_INS_UQRSHRN, + "uqrshrn2", // ARM64_INS_UQRSHRN2, + "uqshl", // ARM64_INS_UQSHL, + "uqshrn", // ARM64_INS_UQSHRN, + "uqshrn2", // ARM64_INS_UQSHRN2, + "uqsub", // ARM64_INS_UQSUB, + "uqxtn", // ARM64_INS_UQXTN, + "uqxtn2", // ARM64_INS_UQXTN2, + "urecpe", // ARM64_INS_URECPE, + "urhadd", // ARM64_INS_URHADD, + "urshl", // ARM64_INS_URSHL, + "urshr", // ARM64_INS_URSHR, + "ursqrte", // ARM64_INS_URSQRTE, + "ursra", // ARM64_INS_URSRA, + "ushl", // ARM64_INS_USHL, + "ushll", // ARM64_INS_USHLL, + "ushll2", // ARM64_INS_USHLL2, + "ushr", // ARM64_INS_USHR, + "usqadd", // ARM64_INS_USQADD, + "usra", // ARM64_INS_USRA, + "usubl", // ARM64_INS_USUBL, + "usubl2", // ARM64_INS_USUBL2, + "usubw", // ARM64_INS_USUBW, + "usubw2", // ARM64_INS_USUBW2, + "uunpkhi", // ARM64_INS_UUNPKHI, + "uunpklo", // ARM64_INS_UUNPKLO, + "uxtb", // ARM64_INS_UXTB, + "uxth", // ARM64_INS_UXTH, + "uxtl", // ARM64_INS_UXTL, + "uxtl2", // ARM64_INS_UXTL2, + "uxtw", // ARM64_INS_UXTW, + "uzp1", // ARM64_INS_UZP1, + "uzp2", // ARM64_INS_UZP2, + "wfe", // ARM64_INS_WFE, + "wfi", // ARM64_INS_WFI, + "whilele", // ARM64_INS_WHILELE, + "whilelo", // ARM64_INS_WHILELO, + "whilels", // ARM64_INS_WHILELS, + "whilelt", // ARM64_INS_WHILELT, + "wrffr", // ARM64_INS_WRFFR, + "xar", // ARM64_INS_XAR, + "xpacd", // ARM64_INS_XPACD, + "xpaci", // ARM64_INS_XPACI, + "xpaclri", // ARM64_INS_XPACLRI, + "xtn", // ARM64_INS_XTN, + "xtn2", // ARM64_INS_XTN2, + "yield", // ARM64_INS_YIELD, + "zip1", // ARM64_INS_ZIP1, + "zip2", // ARM64_INS_ZIP2, diff --git a/arch/AArch64/AArch64MappingInsnOp.inc b/arch/AArch64/AArch64MappingInsnOp.inc index 15d554152..49449a406 100644 --- a/arch/AArch64/AArch64MappingInsnOp.inc +++ b/arch/AArch64/AArch64MappingInsnOp.inc @@ -1,9308 +1,21684 @@ -{ /* AArch64_ABSv16i8, ARM64_INS_ABS: abs.16b $rd, $rn */ +/* Capstone Disassembly Engine, http://www.capstone-engine.org */ +/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */ +/* By Nguyen Anh Quynh , 2013-2019 */ + + +{ /* AArch64_ABS_ZPmZ_B, AArch64_INS_ABS: abs */ + 0, + { 0 } +}, + +{ /* AArch64_ABS_ZPmZ_D, AArch64_INS_ABS: abs */ + 0, + { 0 } +}, + +{ /* AArch64_ABS_ZPmZ_H, AArch64_INS_ABS: abs */ + 0, + { 0 } +}, + +{ /* AArch64_ABS_ZPmZ_S, AArch64_INS_ABS: abs */ + 0, + { 0 } +}, + +{ /* AArch64_ABSv16i8, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv1i64, ARM64_INS_ABS: abs $rd, $rn */ + +{ /* AArch64_ABSv1i64, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv2i32, ARM64_INS_ABS: abs.2s $rd, $rn */ + +{ /* AArch64_ABSv2i32, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv2i64, ARM64_INS_ABS: abs.2d $rd, $rn */ + +{ /* AArch64_ABSv2i64, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv4i16, ARM64_INS_ABS: abs.4h $rd, $rn */ + +{ /* AArch64_ABSv4i16, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv4i32, ARM64_INS_ABS: abs.4s $rd, $rn */ + +{ /* AArch64_ABSv4i32, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv8i16, ARM64_INS_ABS: abs.8h $rd, $rn */ + +{ /* AArch64_ABSv8i16, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ABSv8i8, ARM64_INS_ABS: abs.8b $rd, $rn */ + +{ /* AArch64_ABSv8i8, AArch64_INS_ABS: abs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADCSWr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */ + +{ /* AArch64_ADCSWr, AArch64_INS_ADCS: adcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADCSXr, ARM64_INS_ADCS: adcs $rd, $rn, $rm */ + +{ /* AArch64_ADCSXr, AArch64_INS_ADCS: adcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADCWr, ARM64_INS_ADC: adc $rd, $rn, $rm */ + +{ /* AArch64_ADCWr, AArch64_INS_ADC: adc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADCXr, ARM64_INS_ADC: adc $rd, $rn, $rm */ + +{ /* AArch64_ADCXr, AArch64_INS_ADC: adc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDHNv2i64_v2i32, ARM64_INS_ADDHN: addhn.2s $rd, $rn, $rm */ + +{ /* AArch64_ADDHNv2i64_v2i32, AArch64_INS_ADDHN: addhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDHNv2i64_v4i32, ARM64_INS_ADDHN2: addhn2.4s $rd, $rn, $rm */ + +{ /* AArch64_ADDHNv2i64_v4i32, AArch64_INS_ADDHN2: addhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDHNv4i32_v4i16, ARM64_INS_ADDHN: addhn.4h $rd, $rn, $rm */ + +{ /* AArch64_ADDHNv4i32_v4i16, AArch64_INS_ADDHN: addhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDHNv4i32_v8i16, ARM64_INS_ADDHN2: addhn2.8h $rd, $rn, $rm */ + +{ /* AArch64_ADDHNv4i32_v8i16, AArch64_INS_ADDHN2: addhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDHNv8i16_v16i8, ARM64_INS_ADDHN2: addhn2.16b $rd, $rn, $rm */ + +{ /* AArch64_ADDHNv8i16_v16i8, AArch64_INS_ADDHN2: addhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDHNv8i16_v8i8, ARM64_INS_ADDHN: addhn.8b $rd, $rn, $rm */ + +{ /* AArch64_ADDHNv8i16_v8i8, AArch64_INS_ADDHN: addhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv16i8, ARM64_INS_ADDP: addp.16b $rd, $rn, $rm| */ + +{ /* AArch64_ADDPL_XXI, AArch64_INS_ADDPL: addpl */ + 0, + { 0 } +}, + +{ /* AArch64_ADDPv16i8, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv2i32, ARM64_INS_ADDP: addp.2s $rd, $rn, $rm| */ + +{ /* AArch64_ADDPv2i32, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv2i64, ARM64_INS_ADDP: addp.2d $rd, $rn, $rm| */ + +{ /* AArch64_ADDPv2i64, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv2i64p, ARM64_INS_ADDP: addp.2d $rd, $rn */ + +{ /* AArch64_ADDPv2i64p, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv4i16, ARM64_INS_ADDP: addp.4h $rd, $rn, $rm| */ + +{ /* AArch64_ADDPv4i16, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv4i32, ARM64_INS_ADDP: addp.4s $rd, $rn, $rm| */ + +{ /* AArch64_ADDPv4i32, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv8i16, ARM64_INS_ADDP: addp.8h $rd, $rn, $rm| */ + +{ /* AArch64_ADDPv8i16, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDPv8i8, ARM64_INS_ADDP: addp.8b $rd, $rn, $rm| */ + +{ /* AArch64_ADDPv8i8, AArch64_INS_ADDP: addp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDSWri, ARM64_INS_ADDS: adds $rd, $rn, $imm */ + +{ /* AArch64_ADDSWri, AArch64_INS_ADDS: adds */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ,0 } }, -{ /* AArch64_ADDSWrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */ + +{ /* AArch64_ADDSWrs, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDSWrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */ + +{ /* AArch64_ADDSWrx, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDSXri, ARM64_INS_ADDS: adds $rd, $rn, $imm */ + +{ /* AArch64_ADDSXri, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDSXrs, ARM64_INS_ADDS: adds $rd, $rn, $rm */ + +{ /* AArch64_ADDSXrs, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDSXrx, ARM64_INS_ADDS: adds $r1, $r2, $r3 */ + +{ /* AArch64_ADDSXrx, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDSXrx64, ARM64_INS_ADDS: adds $rd, $rn, $rm$ext */ + +{ /* AArch64_ADDSXrx64, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDVv16i8v, ARM64_INS_ADDV: addv.16b $rd, $rn */ + +{ /* AArch64_ADDVL_XXI, AArch64_INS_ADDVL: addvl */ + 0, + { 0 } +}, + +{ /* AArch64_ADDVv16i8v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADDVv4i16v, ARM64_INS_ADDV: addv.4h $rd, $rn */ + +{ /* AArch64_ADDVv4i16v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADDVv4i32v, ARM64_INS_ADDV: addv.4s $rd, $rn */ + +{ /* AArch64_ADDVv4i32v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADDVv8i16v, ARM64_INS_ADDV: addv.8h $rd, $rn */ + +{ /* AArch64_ADDVv8i16v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADDVv8i8v, ARM64_INS_ADDV: addv.8b $rd, $rn */ + +{ /* AArch64_ADDVv8i8v, AArch64_INS_ADDV: addv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADDWri, ARM64_INS_ADD: add $rd, $rn, $imm */ + +{ /* AArch64_ADDWri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDWrs, ARM64_INS_ADD: add $rd, $rn, $rm */ + +{ /* AArch64_ADDWrs, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDWrx, ARM64_INS_ADD: add $r1, $r2, $r3 */ + +{ /* AArch64_ADDWrx, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDXri, ARM64_INS_ADD: add $rd, $rn, $imm */ + +{ /* AArch64_ADDXri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDXrs, ARM64_INS_ADD: add $rd, $rn, $rm */ + +{ /* AArch64_ADDXrs, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDXrx, ARM64_INS_ADD: add $r1, $r2, $r3 */ + +{ /* AArch64_ADDXrx, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDXrx64, ARM64_INS_ADD: add $rd, $rn, $rm$ext */ + +{ /* AArch64_ADDXrx64, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv16i8, ARM64_INS_ADD: add.16b $rd, $rn, $rm| */ + +{ /* AArch64_ADD_ZI_B, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZI_D, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZI_H, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZI_S, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZPmZ_B, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZPmZ_D, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZPmZ_H, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZPmZ_S, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZZZ_B, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZZZ_D, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZZZ_H, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADD_ZZZ_S, AArch64_INS_ADD: add */ + 0, + { 0 } +}, + +{ /* AArch64_ADDv16i8, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv1i64, ARM64_INS_ADD: add $rd, $rn, $rm */ + +{ /* AArch64_ADDv1i64, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv2i32, ARM64_INS_ADD: add.2s $rd, $rn, $rm| */ + +{ /* AArch64_ADDv2i32, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv2i64, ARM64_INS_ADD: add.2d $rd, $rn, $rm| */ + +{ /* AArch64_ADDv2i64, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv4i16, ARM64_INS_ADD: add.4h $rd, $rn, $rm| */ + +{ /* AArch64_ADDv4i16, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv4i32, ARM64_INS_ADD: add.4s $rd, $rn, $rm| */ + +{ /* AArch64_ADDv4i32, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv8i16, ARM64_INS_ADD: add.8h $rd, $rn, $rm| */ + +{ /* AArch64_ADDv8i16, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADDv8i8, ARM64_INS_ADD: add.8b $rd, $rn, $rm| */ + +{ /* AArch64_ADDv8i8, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ADR, ARM64_INS_ADR: adr $xd, $label */ + +{ /* AArch64_ADR, AArch64_INS_ADR: adr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ADRP, ARM64_INS_ADRP: adrp $xd, $label */ + +{ /* AArch64_ADRP, AArch64_INS_ADRP: adrp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_AESDrr, ARM64_INS_AESD: aesd.16b $rd, $rn */ + +{ /* AArch64_ADR_LSL_ZZZ_D_0, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_D_1, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_D_2, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_D_3, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_S_0, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_S_1, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_S_2, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_LSL_ZZZ_S_3, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_SXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_SXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_SXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_SXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_UXTW_ZZZ_D_0, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_UXTW_ZZZ_D_1, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_UXTW_ZZZ_D_2, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_ADR_UXTW_ZZZ_D_3, AArch64_INS_ADR: adr */ + 0, + { 0 } +}, + +{ /* AArch64_AESDrr, AArch64_INS_AESD: aesd */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_AESErr, ARM64_INS_AESE: aese.16b $rd, $rn */ + +{ /* AArch64_AESErr, AArch64_INS_AESE: aese */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_AESIMCrr, ARM64_INS_AESIMC: aesimc.16b $rd, $rn */ + +{ /* AArch64_AESIMCrr, AArch64_INS_AESIMC: aesimc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_AESMCrr, ARM64_INS_AESMC: aesmc.16b $rd, $rn */ + +{ /* AArch64_AESMCrr, AArch64_INS_AESMC: aesmc */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ANDSWri, ARM64_INS_ANDS: ands $rd, $rn, $imm */ + +{ /* AArch64_ANDSWri, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDSWrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */ + +{ /* AArch64_ANDSWrs, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDSXri, ARM64_INS_ANDS: ands $rd, $rn, $imm */ + +{ /* AArch64_ANDSXri, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDSXrs, ARM64_INS_ANDS: ands $rd, $rn, $rm */ + +{ /* AArch64_ANDSXrs, AArch64_INS_ANDS: ands */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDWri, ARM64_INS_AND: and $rd, $rn, $imm */ + +{ /* AArch64_ANDS_PPzPP, AArch64_INS_ANDS: ands */ + 0, + { 0 } +}, + +{ /* AArch64_ANDV_VPZ_B, AArch64_INS_ANDV: andv */ + 0, + { 0 } +}, + +{ /* AArch64_ANDV_VPZ_D, AArch64_INS_ANDV: andv */ + 0, + { 0 } +}, + +{ /* AArch64_ANDV_VPZ_H, AArch64_INS_ANDV: andv */ + 0, + { 0 } +}, + +{ /* AArch64_ANDV_VPZ_S, AArch64_INS_ANDV: andv */ + 0, + { 0 } +}, + +{ /* AArch64_ANDWri, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDWrs, ARM64_INS_AND: and $rd, $rn, $rm */ + +{ /* AArch64_ANDWrs, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDXri, ARM64_INS_AND: and $rd, $rn, $imm */ + +{ /* AArch64_ANDXri, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDXrs, ARM64_INS_AND: and $rd, $rn, $rm */ + +{ /* AArch64_ANDXrs, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDv16i8, ARM64_INS_AND: and.16b $rd, $rn, $rm| */ + +{ /* AArch64_AND_PPzPP, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_AND_ZI, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_AND_ZPmZ_B, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_AND_ZPmZ_D, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_AND_ZPmZ_H, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_AND_ZPmZ_S, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_AND_ZZZ, AArch64_INS_AND: and */ + 0, + { 0 } +}, + +{ /* AArch64_ANDv16i8, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ANDv8i8, ARM64_INS_AND: and.8b $rd, $rn, $rm| */ + +{ /* AArch64_ANDv8i8, AArch64_INS_AND: and */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ASRVWr, ARM64_INS_ASR: asr $rd, $rn, $rm */ + +{ /* AArch64_ASRD_ZPmI_B, AArch64_INS_ASRD: asrd */ + 0, + { 0 } +}, + +{ /* AArch64_ASRD_ZPmI_D, AArch64_INS_ASRD: asrd */ + 0, + { 0 } +}, + +{ /* AArch64_ASRD_ZPmI_H, AArch64_INS_ASRD: asrd */ + 0, + { 0 } +}, + +{ /* AArch64_ASRD_ZPmI_S, AArch64_INS_ASRD: asrd */ + 0, + { 0 } +}, + +{ /* AArch64_ASRR_ZPmZ_B, AArch64_INS_ASRR: asrr */ + 0, + { 0 } +}, + +{ /* AArch64_ASRR_ZPmZ_D, AArch64_INS_ASRR: asrr */ + 0, + { 0 } +}, + +{ /* AArch64_ASRR_ZPmZ_H, AArch64_INS_ASRR: asrr */ + 0, + { 0 } +}, + +{ /* AArch64_ASRR_ZPmZ_S, AArch64_INS_ASRR: asrr */ + 0, + { 0 } +}, + +{ /* AArch64_ASRVWr, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ASRVXr, ARM64_INS_ASR: asr $rd, $rn, $rm */ + +{ /* AArch64_ASRVXr, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_B, ARM64_INS_B: b $addr */ + +{ /* AArch64_ASR_WIDE_ZPmZ_B, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_WIDE_ZPmZ_H, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_WIDE_ZPmZ_S, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_WIDE_ZZZ_B, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_WIDE_ZZZ_H, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_WIDE_ZZZ_S, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmI_B, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmI_D, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmI_H, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmI_S, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmZ_B, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmZ_D, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmZ_H, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZPmZ_S, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZZI_B, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZZI_D, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZZI_H, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_ASR_ZZI_S, AArch64_INS_ASR: asr */ + 0, + { 0 } +}, + +{ /* AArch64_AUTDA, AArch64_INS_AUTDA: autda */ + 0, + { 0 } +}, + +{ /* AArch64_AUTDB, AArch64_INS_AUTDB: autdb */ + 0, + { 0 } +}, + +{ /* AArch64_AUTDZA, AArch64_INS_AUTDZA: autdza */ + 0, + { 0 } +}, + +{ /* AArch64_AUTDZB, AArch64_INS_AUTDZB: autdzb */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIA, AArch64_INS_AUTIA: autia */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIA1716, AArch64_INS_AUTIA1716: autia1716 */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIASP, AArch64_INS_AUTIASP: autiasp */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIAZ, AArch64_INS_AUTIAZ: autiaz */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIB, AArch64_INS_AUTIB: autib */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIB1716, AArch64_INS_AUTIB1716: autib1716 */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIBSP, AArch64_INS_AUTIBSP: autibsp */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIBZ, AArch64_INS_AUTIBZ: autibz */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIZA, AArch64_INS_AUTIZA: autiza */ + 0, + { 0 } +}, + +{ /* AArch64_AUTIZB, AArch64_INS_AUTIZB: autizb */ + 0, + { 0 } +}, + +{ /* AArch64_B, AArch64_INS_B: b */ 0, { CS_AC_READ, 0 } }, -{ /* AArch64_BFMWri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */ + +{ /* AArch64_BCAX, AArch64_INS_BCAX: bcax */ + 0, + { 0 } +}, + +{ /* AArch64_BFMWri, AArch64_INS_BFM: bfm */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_BFMXri, ARM64_INS_BFM: bfm $rd, $rn, $immr, $imms */ + +{ /* AArch64_BFMXri, AArch64_INS_BFM: bfm */ 0, { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_BICSWrs, ARM64_INS_BICS: bics $rd, $rn, $rm */ + +{ /* AArch64_BICSWrs, AArch64_INS_BICS: bics */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_BICSXrs, ARM64_INS_BICS: bics $rd, $rn, $rm */ + +{ /* AArch64_BICSXrs, AArch64_INS_BICS: bics */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_BICWrs, ARM64_INS_BIC: bic $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BICXrs, ARM64_INS_BIC: bic $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BICv16i8, ARM64_INS_BIC: bic.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BICv2i32, ARM64_INS_BIC: bic.2s $rd, $imm8$shift */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_BICv4i16, ARM64_INS_BIC: bic.4h $rd, $imm8$shift */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_BICv4i32, ARM64_INS_BIC: bic.4s $rd, $imm8$shift */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_BICv8i16, ARM64_INS_BIC: bic.8h $rd, $imm8$shift */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_BICv8i8, ARM64_INS_BIC: bic.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_BIFv16i8, ARM64_INS_BIF: bif.16b $rd, $rn, $rm| */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BIFv8i8, ARM64_INS_BIF: bif.8b $rd, $rn, $rm| */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BITv16i8, ARM64_INS_BIT: bit.16b $rd, $rn, $rm */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BITv8i8, ARM64_INS_BIT: bit.8b $rd, $rn, $rm */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BL, ARM64_INS_BL: bl $addr */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_BLR, ARM64_INS_BLR: blr $rn */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_BR, ARM64_INS_BR: br $rn */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_BRK, ARM64_INS_BRK: brk $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_BSLv16i8, ARM64_INS_BSL: bsl.16b $rd, $rn, $rm */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_BSLv8i8, ARM64_INS_BSL: bsl.8b $rd, $rn, $rm */ - 0, - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_Bcc, ARM64_INS_B: b.$cond $target */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_CBNZW, ARM64_INS_CBNZ: cbnz $rt, $target */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CBNZX, ARM64_INS_CBNZ: cbnz $rt, $target */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CBZW, ARM64_INS_CBZ: cbz $rt, $target */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CBZX, ARM64_INS_CBZ: cbz $rt, $target */ - 0, - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CCMNWi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMNWr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMNXi, ARM64_INS_CCMN: ccmn $rn, $imm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMNXr, ARM64_INS_CCMN: ccmn $rn, $rm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMPWi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMPWr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMPXi, ARM64_INS_CCMP: ccmp $rn, $imm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CCMPXr, ARM64_INS_CCMP: ccmp $rn, $rm, $nzcv, $cond */ - 0, - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CLREX, ARM64_INS_CLREX: clrex $crm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_CLSWr, ARM64_INS_CLS: cls $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSXr, ARM64_INS_CLS: cls $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSv16i8, ARM64_INS_CLS: cls.16b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSv2i32, ARM64_INS_CLS: cls.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSv4i16, ARM64_INS_CLS: cls.4h $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSv4i32, ARM64_INS_CLS: cls.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSv8i16, ARM64_INS_CLS: cls.8h $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLSv8i8, ARM64_INS_CLS: cls.8b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZWr, ARM64_INS_CLZ: clz $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZXr, ARM64_INS_CLZ: clz $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZv16i8, ARM64_INS_CLZ: clz.16b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZv2i32, ARM64_INS_CLZ: clz.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZv4i16, ARM64_INS_CLZ: clz.4h $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZv4i32, ARM64_INS_CLZ: clz.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZv8i16, ARM64_INS_CLZ: clz.8h $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CLZv8i8, ARM64_INS_CLZ: clz.8b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv16i8, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv16i8rz, ARM64_INS_CMEQ: cmeq.16b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv1i64, ARM64_INS_CMEQ: cmeq $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv1i64rz, ARM64_INS_CMEQ: cmeq $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv2i32, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv2i32rz, ARM64_INS_CMEQ: cmeq.2s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv2i64, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv2i64rz, ARM64_INS_CMEQ: cmeq.2d $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv4i16, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv4i16rz, ARM64_INS_CMEQ: cmeq.4h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv4i32, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv4i32rz, ARM64_INS_CMEQ: cmeq.4s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv8i16, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv8i16rz, ARM64_INS_CMEQ: cmeq.8h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv8i8, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMEQv8i8rz, ARM64_INS_CMEQ: cmeq.8b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv16i8, ARM64_INS_CMGE: cmge.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv16i8rz, ARM64_INS_CMGE: cmge.16b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv1i64, ARM64_INS_CMGE: cmge $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv1i64rz, ARM64_INS_CMGE: cmge $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv2i32, ARM64_INS_CMGE: cmge.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv2i32rz, ARM64_INS_CMGE: cmge.2s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv2i64, ARM64_INS_CMGE: cmge.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv2i64rz, ARM64_INS_CMGE: cmge.2d $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv4i16, ARM64_INS_CMGE: cmge.4h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv4i16rz, ARM64_INS_CMGE: cmge.4h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv4i32, ARM64_INS_CMGE: cmge.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv4i32rz, ARM64_INS_CMGE: cmge.4s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv8i16, ARM64_INS_CMGE: cmge.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv8i16rz, ARM64_INS_CMGE: cmge.8h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv8i8, ARM64_INS_CMGE: cmge.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGEv8i8rz, ARM64_INS_CMGE: cmge.8b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv16i8, ARM64_INS_CMGT: cmgt.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv16i8rz, ARM64_INS_CMGT: cmgt.16b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv1i64, ARM64_INS_CMGT: cmgt $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv1i64rz, ARM64_INS_CMGT: cmgt $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv2i32, ARM64_INS_CMGT: cmgt.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv2i32rz, ARM64_INS_CMGT: cmgt.2s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv2i64, ARM64_INS_CMGT: cmgt.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv2i64rz, ARM64_INS_CMGT: cmgt.2d $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv4i16, ARM64_INS_CMGT: cmgt.4h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv4i16rz, ARM64_INS_CMGT: cmgt.4h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv4i32, ARM64_INS_CMGT: cmgt.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv4i32rz, ARM64_INS_CMGT: cmgt.4s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv8i16, ARM64_INS_CMGT: cmgt.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv8i16rz, ARM64_INS_CMGT: cmgt.8h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv8i8, ARM64_INS_CMGT: cmgt.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMGTv8i8rz, ARM64_INS_CMGT: cmgt.8b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv16i8, ARM64_INS_CMHI: cmhi.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv1i64, ARM64_INS_CMHI: cmhi $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv2i32, ARM64_INS_CMHI: cmhi.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv2i64, ARM64_INS_CMHI: cmhi.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv4i16, ARM64_INS_CMHI: cmhi.4h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv4i32, ARM64_INS_CMHI: cmhi.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv8i16, ARM64_INS_CMHI: cmhi.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHIv8i8, ARM64_INS_CMHI: cmhi.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv16i8, ARM64_INS_CMHS: cmhs.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv1i64, ARM64_INS_CMHS: cmhs $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv2i32, ARM64_INS_CMHS: cmhs.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv2i64, ARM64_INS_CMHS: cmhs.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv4i16, ARM64_INS_CMHS: cmhs.4h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv4i32, ARM64_INS_CMHS: cmhs.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv8i16, ARM64_INS_CMHS: cmhs.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMHSv8i8, ARM64_INS_CMHS: cmhs.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv16i8rz, ARM64_INS_CMLE: cmle.16b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv1i64rz, ARM64_INS_CMLE: cmle $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv2i32rz, ARM64_INS_CMLE: cmle.2s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv2i64rz, ARM64_INS_CMLE: cmle.2d $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv4i16rz, ARM64_INS_CMLE: cmle.4h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv4i32rz, ARM64_INS_CMLE: cmle.4s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv8i16rz, ARM64_INS_CMLE: cmle.8h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLEv8i8rz, ARM64_INS_CMLE: cmle.8b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv16i8rz, ARM64_INS_CMLT: cmlt.16b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv1i64rz, ARM64_INS_CMLT: cmlt $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv2i32rz, ARM64_INS_CMLT: cmlt.2s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv2i64rz, ARM64_INS_CMLT: cmlt.2d $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv4i16rz, ARM64_INS_CMLT: cmlt.4h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv4i32rz, ARM64_INS_CMLT: cmlt.4s $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv8i16rz, ARM64_INS_CMLT: cmlt.8h $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMLTv8i8rz, ARM64_INS_CMLT: cmlt.8b $rd, $rn, #0 */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv16i8, ARM64_INS_CMTST: cmtst.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv1i64, ARM64_INS_CMTST: cmtst $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv2i32, ARM64_INS_CMTST: cmtst.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv2i64, ARM64_INS_CMTST: cmtst.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv4i16, ARM64_INS_CMTST: cmtst.4h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv4i32, ARM64_INS_CMTST: cmtst.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv8i16, ARM64_INS_CMTST: cmtst.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CMTSTv8i8, ARM64_INS_CMTST: cmtst.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CNTv16i8, ARM64_INS_CNT: cnt.16b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CNTv8i8, ARM64_INS_CNT: cnt.8b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_CPYi16, ARM64_INS_MOV: mov $dst, $src$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CPYi32, ARM64_INS_MOV: mov $dst, $src$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CPYi64, ARM64_INS_MOV: mov $dst, $src$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CPYi8, ARM64_INS_MOV: mov $dst, $src$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32Brr, ARM64_INS_CRC32B: crc32b $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32CBrr, ARM64_INS_CRC32CB: crc32cb $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32CHrr, ARM64_INS_CRC32CH: crc32ch $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32CWrr, ARM64_INS_CRC32CW: crc32cw $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32CXrr, ARM64_INS_CRC32CX: crc32cx $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32Hrr, ARM64_INS_CRC32H: crc32h $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32Wrr, ARM64_INS_CRC32W: crc32w $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CRC32Xrr, ARM64_INS_CRC32X: crc32x $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_CSELWr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSELXr, ARM64_INS_CSEL: csel $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSINCWr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSINCXr, ARM64_INS_CSINC: csinc $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSINVWr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSINVXr, ARM64_INS_CSINV: csinv $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSNEGWr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_CSNEGXr, ARM64_INS_CSNEG: csneg $rd, $rn, $rm, $cond */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_DCPS1, ARM64_INS_DCPS1: dcps1 $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_DCPS2, ARM64_INS_DCPS2: dcps2 $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_DCPS3, ARM64_INS_DCPS3: dcps3 $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_DMB, ARM64_INS_DMB: dmb $crm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_DRPS, ARM64_INS_DRPS: drps */ + +{ /* AArch64_BICS_PPzPP, AArch64_INS_BICS: bics */ 0, { 0 } }, -{ /* AArch64_DSB, ARM64_INS_DSB: dsb $crm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv16i8gpr, ARM64_INS_DUP: dup.16b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv16i8lane, ARM64_INS_DUP: dup.16b $rd, $rn$idx */ + +{ /* AArch64_BICWrs, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_DUPv2i32gpr, ARM64_INS_DUP: dup.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv2i32lane, ARM64_INS_DUP: dup.2s $rd, $rn$idx */ + +{ /* AArch64_BICXrs, AArch64_INS_BIC: bic */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_DUPv2i64gpr, ARM64_INS_DUP: dup.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv2i64lane, ARM64_INS_DUP: dup.2d $rd, $rn$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv4i16gpr, ARM64_INS_DUP: dup.4h $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv4i16lane, ARM64_INS_DUP: dup.4h $rd, $rn$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv4i32gpr, ARM64_INS_DUP: dup.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv4i32lane, ARM64_INS_DUP: dup.4s $rd, $rn$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv8i16gpr, ARM64_INS_DUP: dup.8h $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv8i16lane, ARM64_INS_DUP: dup.8h $rd, $rn$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv8i8gpr, ARM64_INS_DUP: dup.8b $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_DUPv8i8lane, ARM64_INS_DUP: dup.8b $rd, $rn$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EONWrs, ARM64_INS_EON: eon $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EONXrs, ARM64_INS_EON: eon $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EORWri, ARM64_INS_EOR: eor $rd, $rn, $imm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EORWrs, ARM64_INS_EOR: eor $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EORXri, ARM64_INS_EOR: eor $rd, $rn, $imm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EORXrs, ARM64_INS_EOR: eor $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EORv16i8, ARM64_INS_EOR: eor.16b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_EORv8i8, ARM64_INS_EOR: eor.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_ERET, ARM64_INS_ERET: eret */ + +{ /* AArch64_BIC_PPzPP, AArch64_INS_BIC: bic */ 0, { 0 } }, -{ /* AArch64_EXTRWrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */ + +{ /* AArch64_BIC_ZPmZ_B, AArch64_INS_BIC: bic */ + 0, + { 0 } +}, + +{ /* AArch64_BIC_ZPmZ_D, AArch64_INS_BIC: bic */ + 0, + { 0 } +}, + +{ /* AArch64_BIC_ZPmZ_H, AArch64_INS_BIC: bic */ + 0, + { 0 } +}, + +{ /* AArch64_BIC_ZPmZ_S, AArch64_INS_BIC: bic */ + 0, + { 0 } +}, + +{ /* AArch64_BIC_ZZZ, AArch64_INS_BIC: bic */ + 0, + { 0 } +}, + +{ /* AArch64_BICv16i8, AArch64_INS_BIC: bic */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_BICv2i32, AArch64_INS_BIC: bic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_BICv4i16, AArch64_INS_BIC: bic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_BICv4i32, AArch64_INS_BIC: bic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_BICv8i16, AArch64_INS_BIC: bic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_BICv8i8, AArch64_INS_BIC: bic */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_BIFv16i8, AArch64_INS_BIF: bif */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_BIFv8i8, AArch64_INS_BIF: bif */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_BITv16i8, AArch64_INS_BIT: bit */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_BITv8i8, AArch64_INS_BIT: bit */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_BL, AArch64_INS_BL: bl */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_BLR, AArch64_INS_BLR: blr */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_BLRAA, AArch64_INS_BLRAA: blraa */ + 0, + { 0 } +}, + +{ /* AArch64_BLRAAZ, AArch64_INS_BLRAAZ: blraaz */ + 0, + { 0 } +}, + +{ /* AArch64_BLRAB, AArch64_INS_BLRAB: blrab */ + 0, + { 0 } +}, + +{ /* AArch64_BLRABZ, AArch64_INS_BLRABZ: blrabz */ + 0, + { 0 } +}, + +{ /* AArch64_BR, AArch64_INS_BR: br */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_BRAA, AArch64_INS_BRAA: braa */ + 0, + { 0 } +}, + +{ /* AArch64_BRAAZ, AArch64_INS_BRAAZ: braaz */ + 0, + { 0 } +}, + +{ /* AArch64_BRAB, AArch64_INS_BRAB: brab */ + 0, + { 0 } +}, + +{ /* AArch64_BRABZ, AArch64_INS_BRABZ: brabz */ + 0, + { 0 } +}, + +{ /* AArch64_BRK, AArch64_INS_BRK: brk */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_BRKAS_PPzP, AArch64_INS_BRKAS: brkas */ + 0, + { 0 } +}, + +{ /* AArch64_BRKA_PPmP, AArch64_INS_BRKA: brka */ + 0, + { 0 } +}, + +{ /* AArch64_BRKA_PPzP, AArch64_INS_BRKA: brka */ + 0, + { 0 } +}, + +{ /* AArch64_BRKBS_PPzP, AArch64_INS_BRKBS: brkbs */ + 0, + { 0 } +}, + +{ /* AArch64_BRKB_PPmP, AArch64_INS_BRKB: brkb */ + 0, + { 0 } +}, + +{ /* AArch64_BRKB_PPzP, AArch64_INS_BRKB: brkb */ + 0, + { 0 } +}, + +{ /* AArch64_BRKNS_PPzP, AArch64_INS_BRKNS: brkns */ + 0, + { 0 } +}, + +{ /* AArch64_BRKN_PPzP, AArch64_INS_BRKN: brkn */ + 0, + { 0 } +}, + +{ /* AArch64_BRKPAS_PPzPP, AArch64_INS_BRKPAS: brkpas */ + 0, + { 0 } +}, + +{ /* AArch64_BRKPA_PPzPP, AArch64_INS_BRKPA: brkpa */ + 0, + { 0 } +}, + +{ /* AArch64_BRKPBS_PPzPP, AArch64_INS_BRKPBS: brkpbs */ + 0, + { 0 } +}, + +{ /* AArch64_BRKPB_PPzPP, AArch64_INS_BRKPB: brkpb */ + 0, + { 0 } +}, + +{ /* AArch64_BSLv16i8, AArch64_INS_BSL: bsl */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_BSLv8i8, AArch64_INS_BSL: bsl */ + 0, + { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_Bcc, AArch64_INS_B: b */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_CASAB, AArch64_INS_CASAB: casab */ + 0, + { 0 } +}, + +{ /* AArch64_CASAH, AArch64_INS_CASAH: casah */ + 0, + { 0 } +}, + +{ /* AArch64_CASALB, AArch64_INS_CASALB: casalb */ + 0, + { 0 } +}, + +{ /* AArch64_CASALH, AArch64_INS_CASALH: casalh */ + 0, + { 0 } +}, + +{ /* AArch64_CASALW, AArch64_INS_CASAL: casal */ + 0, + { 0 } +}, + +{ /* AArch64_CASALX, AArch64_INS_CASAL: casal */ + 0, + { 0 } +}, + +{ /* AArch64_CASAW, AArch64_INS_CASA: casa */ + 0, + { 0 } +}, + +{ /* AArch64_CASAX, AArch64_INS_CASA: casa */ + 0, + { 0 } +}, + +{ /* AArch64_CASB, AArch64_INS_CASB: casb */ + 0, + { 0 } +}, + +{ /* AArch64_CASH, AArch64_INS_CASH: cash */ + 0, + { 0 } +}, + +{ /* AArch64_CASLB, AArch64_INS_CASLB: caslb */ + 0, + { 0 } +}, + +{ /* AArch64_CASLH, AArch64_INS_CASLH: caslh */ + 0, + { 0 } +}, + +{ /* AArch64_CASLW, AArch64_INS_CASL: casl */ + 0, + { 0 } +}, + +{ /* AArch64_CASLX, AArch64_INS_CASL: casl */ + 0, + { 0 } +}, + +{ /* AArch64_CASPALW, AArch64_INS_CASPAL: caspal */ + 0, + { 0 } +}, + +{ /* AArch64_CASPALX, AArch64_INS_CASPAL: caspal */ + 0, + { 0 } +}, + +{ /* AArch64_CASPAW, AArch64_INS_CASPA: caspa */ + 0, + { 0 } +}, + +{ /* AArch64_CASPAX, AArch64_INS_CASPA: caspa */ + 0, + { 0 } +}, + +{ /* AArch64_CASPLW, AArch64_INS_CASPL: caspl */ + 0, + { 0 } +}, + +{ /* AArch64_CASPLX, AArch64_INS_CASPL: caspl */ + 0, + { 0 } +}, + +{ /* AArch64_CASPW, AArch64_INS_CASP: casp */ + 0, + { 0 } +}, + +{ /* AArch64_CASPX, AArch64_INS_CASP: casp */ + 0, + { 0 } +}, + +{ /* AArch64_CASW, AArch64_INS_CAS: cas */ + 0, + { 0 } +}, + +{ /* AArch64_CASX, AArch64_INS_CAS: cas */ + 0, + { 0 } +}, + +{ /* AArch64_CBNZW, AArch64_INS_CBNZ: cbnz */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CBNZX, AArch64_INS_CBNZ: cbnz */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CBZW, AArch64_INS_CBZ: cbz */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CBZX, AArch64_INS_CBZ: cbz */ + 0, + { CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CCMNWi, AArch64_INS_CCMN: ccmn */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMNWr, AArch64_INS_CCMN: ccmn */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMNXi, AArch64_INS_CCMN: ccmn */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMNXr, AArch64_INS_CCMN: ccmn */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMPWi, AArch64_INS_CCMP: ccmp */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMPWr, AArch64_INS_CCMP: ccmp */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMPXi, AArch64_INS_CCMP: ccmp */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CCMPXr, AArch64_INS_CCMP: ccmp */ + 0, + { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_CFINV, AArch64_INS_CFINV: cfinv */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_RPZ_B, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_RPZ_D, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_RPZ_H, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_RPZ_S, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_VPZ_B, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_VPZ_D, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_VPZ_H, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_VPZ_S, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_ZPZ_B, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_ZPZ_D, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_ZPZ_H, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTA_ZPZ_S, AArch64_INS_CLASTA: clasta */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_RPZ_B, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_RPZ_D, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_RPZ_H, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_RPZ_S, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_VPZ_B, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_VPZ_D, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_VPZ_H, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_VPZ_S, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_ZPZ_B, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_ZPZ_D, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_ZPZ_H, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLASTB_ZPZ_S, AArch64_INS_CLASTB: clastb */ + 0, + { 0 } +}, + +{ /* AArch64_CLREX, AArch64_INS_CLREX: clrex */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSWr, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSXr, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLS_ZPmZ_B, AArch64_INS_CLS: cls */ + 0, + { 0 } +}, + +{ /* AArch64_CLS_ZPmZ_D, AArch64_INS_CLS: cls */ + 0, + { 0 } +}, + +{ /* AArch64_CLS_ZPmZ_H, AArch64_INS_CLS: cls */ + 0, + { 0 } +}, + +{ /* AArch64_CLS_ZPmZ_S, AArch64_INS_CLS: cls */ + 0, + { 0 } +}, + +{ /* AArch64_CLSv16i8, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSv2i32, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSv4i16, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSv4i32, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSv8i16, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLSv8i8, AArch64_INS_CLS: cls */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZWr, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZXr, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZ_ZPmZ_B, AArch64_INS_CLZ: clz */ + 0, + { 0 } +}, + +{ /* AArch64_CLZ_ZPmZ_D, AArch64_INS_CLZ: clz */ + 0, + { 0 } +}, + +{ /* AArch64_CLZ_ZPmZ_H, AArch64_INS_CLZ: clz */ + 0, + { 0 } +}, + +{ /* AArch64_CLZ_ZPmZ_S, AArch64_INS_CLZ: clz */ + 0, + { 0 } +}, + +{ /* AArch64_CLZv16i8, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZv2i32, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZv4i16, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZv4i32, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZv8i16, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CLZv8i8, AArch64_INS_CLZ: clz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv16i8, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv16i8rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv1i64, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv1i64rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv2i32, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv2i32rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv2i64, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv2i64rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv4i16, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv4i16rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv4i32, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv4i32rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv8i16, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv8i16rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv8i8, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMEQv8i8rz, AArch64_INS_CMEQ: cmeq */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv16i8, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv16i8rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv1i64, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv1i64rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv2i32, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv2i32rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv2i64, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv2i64rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv4i16, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv4i16rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv4i32, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv4i32rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv8i16, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv8i16rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv8i8, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGEv8i8rz, AArch64_INS_CMGE: cmge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv16i8, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv16i8rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv1i64, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv1i64rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv2i32, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv2i32rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv2i64, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv2i64rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv4i16, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv4i16rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv4i32, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv4i32rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv8i16, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv8i16rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv8i8, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMGTv8i8rz, AArch64_INS_CMGT: cmgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv16i8, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv1i64, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv2i32, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv2i64, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv4i16, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv4i32, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv8i16, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHIv8i8, AArch64_INS_CMHI: cmhi */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv16i8, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv1i64, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv2i32, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv2i64, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv4i16, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv4i32, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv8i16, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMHSv8i8, AArch64_INS_CMHS: cmhs */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv16i8rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv1i64rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv2i32rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv2i64rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv4i16rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv4i32rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv8i16rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLEv8i8rz, AArch64_INS_CMLE: cmle */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv16i8rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv1i64rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv2i32rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv2i64rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv4i16rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv4i32rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv8i16rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMLTv8i8rz, AArch64_INS_CMLT: cmlt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMPEQ_PPzZI_B, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZI_D, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZI_H, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZI_S, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZZ_D, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_WIDE_PPzZZ_B, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_WIDE_PPzZZ_H, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPEQ_WIDE_PPzZZ_S, AArch64_INS_CMPEQ: cmpeq */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZI_B, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZI_D, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZI_H, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZI_S, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZZ_D, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_WIDE_PPzZZ_B, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_WIDE_PPzZZ_H, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGE_WIDE_PPzZZ_S, AArch64_INS_CMPGE: cmpge */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZI_B, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZI_D, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZI_H, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZI_S, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZZ_D, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_WIDE_PPzZZ_B, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_WIDE_PPzZZ_H, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPGT_WIDE_PPzZZ_S, AArch64_INS_CMPGT: cmpgt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZI_B, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZI_D, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZI_H, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZI_S, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZZ_D, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_WIDE_PPzZZ_B, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_WIDE_PPzZZ_H, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHI_WIDE_PPzZZ_S, AArch64_INS_CMPHI: cmphi */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZI_B, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZI_D, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZI_H, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZI_S, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZZ_D, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_WIDE_PPzZZ_B, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_WIDE_PPzZZ_H, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPHS_WIDE_PPzZZ_S, AArch64_INS_CMPHS: cmphs */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_PPzZI_B, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_PPzZI_D, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_PPzZI_H, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_PPzZI_S, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_WIDE_PPzZZ_B, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_WIDE_PPzZZ_H, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLE_WIDE_PPzZZ_S, AArch64_INS_CMPLE: cmple */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_PPzZI_B, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_PPzZI_D, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_PPzZI_H, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_PPzZI_S, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_WIDE_PPzZZ_B, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_WIDE_PPzZZ_H, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLO_WIDE_PPzZZ_S, AArch64_INS_CMPLO: cmplo */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_PPzZI_B, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_PPzZI_D, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_PPzZI_H, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_PPzZI_S, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_WIDE_PPzZZ_B, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_WIDE_PPzZZ_H, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLS_WIDE_PPzZZ_S, AArch64_INS_CMPLS: cmpls */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_PPzZI_B, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_PPzZI_D, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_PPzZI_H, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_PPzZI_S, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_WIDE_PPzZZ_B, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_WIDE_PPzZZ_H, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPLT_WIDE_PPzZZ_S, AArch64_INS_CMPLT: cmplt */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZI_B, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZI_D, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZI_H, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZI_S, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZZ_D, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_WIDE_PPzZZ_B, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_WIDE_PPzZZ_H, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMPNE_WIDE_PPzZZ_S, AArch64_INS_CMPNE: cmpne */ + 0, + { 0 } +}, + +{ /* AArch64_CMTSTv16i8, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv1i64, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv2i32, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv2i64, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv4i16, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv4i32, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv8i16, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CMTSTv8i8, AArch64_INS_CMTST: cmtst */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CNOT_ZPmZ_B, AArch64_INS_CNOT: cnot */ + 0, + { 0 } +}, + +{ /* AArch64_CNOT_ZPmZ_D, AArch64_INS_CNOT: cnot */ + 0, + { 0 } +}, + +{ /* AArch64_CNOT_ZPmZ_H, AArch64_INS_CNOT: cnot */ + 0, + { 0 } +}, + +{ /* AArch64_CNOT_ZPmZ_S, AArch64_INS_CNOT: cnot */ + 0, + { 0 } +}, + +{ /* AArch64_CNTB_XPiI, AArch64_INS_CNTB: cntb */ + 0, + { 0 } +}, + +{ /* AArch64_CNTD_XPiI, AArch64_INS_CNTD: cntd */ + 0, + { 0 } +}, + +{ /* AArch64_CNTH_XPiI, AArch64_INS_CNTH: cnth */ + 0, + { 0 } +}, + +{ /* AArch64_CNTP_XPP_B, AArch64_INS_CNTP: cntp */ + 0, + { 0 } +}, + +{ /* AArch64_CNTP_XPP_D, AArch64_INS_CNTP: cntp */ + 0, + { 0 } +}, + +{ /* AArch64_CNTP_XPP_H, AArch64_INS_CNTP: cntp */ + 0, + { 0 } +}, + +{ /* AArch64_CNTP_XPP_S, AArch64_INS_CNTP: cntp */ + 0, + { 0 } +}, + +{ /* AArch64_CNTW_XPiI, AArch64_INS_CNTW: cntw */ + 0, + { 0 } +}, + +{ /* AArch64_CNT_ZPmZ_B, AArch64_INS_CNT: cnt */ + 0, + { 0 } +}, + +{ /* AArch64_CNT_ZPmZ_D, AArch64_INS_CNT: cnt */ + 0, + { 0 } +}, + +{ /* AArch64_CNT_ZPmZ_H, AArch64_INS_CNT: cnt */ + 0, + { 0 } +}, + +{ /* AArch64_CNT_ZPmZ_S, AArch64_INS_CNT: cnt */ + 0, + { 0 } +}, + +{ /* AArch64_CNTv16i8, AArch64_INS_CNT: cnt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_CNTv8i8, AArch64_INS_CNT: cnt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_COMPACT_ZPZ_D, AArch64_INS_COMPACT: compact */ + 0, + { 0 } +}, + +{ /* AArch64_COMPACT_ZPZ_S, AArch64_INS_COMPACT: compact */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmI_B, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmI_D, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmI_H, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmI_S, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmR_B, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmR_D, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmR_H, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmR_S, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmV_B, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmV_D, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmV_H, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPmV_S, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPzI_B, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPzI_D, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPzI_H, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPY_ZPzI_S, AArch64_INS_CPY: cpy */ + 0, + { 0 } +}, + +{ /* AArch64_CPYi16, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CPYi32, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CPYi64, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CPYi8, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32Brr, AArch64_INS_CRC32B: crc32b */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32CBrr, AArch64_INS_CRC32CB: crc32cb */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32CHrr, AArch64_INS_CRC32CH: crc32ch */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32CWrr, AArch64_INS_CRC32CW: crc32cw */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32CXrr, AArch64_INS_CRC32CX: crc32cx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32Hrr, AArch64_INS_CRC32H: crc32h */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32Wrr, AArch64_INS_CRC32W: crc32w */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CRC32Xrr, AArch64_INS_CRC32X: crc32x */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_CSELWr, AArch64_INS_CSEL: csel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_EXTRXrri, ARM64_INS_EXTR: extr $rd, $rn, $rm, $imm */ + +{ /* AArch64_CSELXr, AArch64_INS_CSEL: csel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_EXTv16i8, ARM64_INS_EXT: ext.16b $rd, $rn, $rm, $imm */ + +{ /* AArch64_CSINCWr, AArch64_INS_CINC: cinc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_EXTv8i8, ARM64_INS_EXT: ext.8b $rd, $rn, $rm, $imm */ + +{ /* AArch64_CSINCXr, AArch64_INS_CINC: cinc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FABD32, ARM64_INS_FABD: fabd $rd, $rn, $rm */ + +{ /* AArch64_CSINVWr, AArch64_INS_CINV: cinv */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FABD64, ARM64_INS_FABD: fabd $rd, $rn, $rm */ + +{ /* AArch64_CSINVXr, AArch64_INS_CINV: cinv */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FABDv2f32, ARM64_INS_FABD: fabd.2s $rd, $rn, $rm| */ + +{ /* AArch64_CSNEGWr, AArch64_INS_CNEG: cneg */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FABDv2f64, ARM64_INS_FABD: fabd.2d $rd, $rn, $rm| */ + +{ /* AArch64_CSNEGXr, AArch64_INS_CNEG: cneg */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FABDv4f32, ARM64_INS_FABD: fabd.4s $rd, $rn, $rm| */ + +{ /* AArch64_CTERMEQ_WW, AArch64_INS_CTERMEQ: ctermeq */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FABSDr, ARM64_INS_FABS: fabs $rd, $rn */ + +{ /* AArch64_CTERMEQ_XX, AArch64_INS_CTERMEQ: ctermeq */ + 0, + { 0 } +}, + +{ /* AArch64_CTERMNE_WW, AArch64_INS_CTERMNE: ctermne */ + 0, + { 0 } +}, + +{ /* AArch64_CTERMNE_XX, AArch64_INS_CTERMNE: ctermne */ + 0, + { 0 } +}, + +{ /* AArch64_DCPS1, AArch64_INS_DCPS1: dcps1 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_DCPS2, AArch64_INS_DCPS2: dcps2 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_DCPS3, AArch64_INS_DCPS3: dcps3 */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_DECB_XPiI, AArch64_INS_DECB: decb */ + 0, + { 0 } +}, + +{ /* AArch64_DECD_XPiI, AArch64_INS_DECD: decd */ + 0, + { 0 } +}, + +{ /* AArch64_DECD_ZPiI, AArch64_INS_DECD: decd */ + 0, + { 0 } +}, + +{ /* AArch64_DECH_XPiI, AArch64_INS_DECH: dech */ + 0, + { 0 } +}, + +{ /* AArch64_DECH_ZPiI, AArch64_INS_DECH: dech */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_XP_B, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_XP_D, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_XP_H, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_XP_S, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_ZP_D, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_ZP_H, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECP_ZP_S, AArch64_INS_DECP: decp */ + 0, + { 0 } +}, + +{ /* AArch64_DECW_XPiI, AArch64_INS_DECW: decw */ + 0, + { 0 } +}, + +{ /* AArch64_DECW_ZPiI, AArch64_INS_DECW: decw */ + 0, + { 0 } +}, + +{ /* AArch64_DMB, AArch64_INS_DMB: dmb */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_DRPS, AArch64_INS_DRPS: drps */ + 0, + { 0 } +}, + +{ /* AArch64_DSB, AArch64_INS_DSB: dsb */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_DUPM_ZI, AArch64_INS_DUPM: dupm */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZI_B, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZI_D, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZI_H, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZI_S, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZR_B, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZR_D, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZR_H, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZR_S, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZZI_B, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZZI_D, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZZI_H, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZZI_Q, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUP_ZZI_S, AArch64_INS_DUP: dup */ + 0, + { 0 } +}, + +{ /* AArch64_DUPv16i8gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FABSSr, ARM64_INS_FABS: fabs $rd, $rn */ + +{ /* AArch64_DUPv16i8lane, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_DUPv2i32gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FABSv2f32, ARM64_INS_FABS: fabs.2s $rd, $rn */ + +{ /* AArch64_DUPv2i32lane, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_DUPv2i64gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FABSv2f64, ARM64_INS_FABS: fabs.2d $rd, $rn */ + +{ /* AArch64_DUPv2i64lane, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_DUPv4i16gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FABSv4f32, ARM64_INS_FABS: fabs.4s $rd, $rn */ + +{ /* AArch64_DUPv4i16lane, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_DUPv4i32gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FACGE32, ARM64_INS_FACGE: facge $rd, $rn, $rm */ + +{ /* AArch64_DUPv4i32lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FACGE64, ARM64_INS_FACGE: facge $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGEv2f32, ARM64_INS_FACGE: facge.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGEv2f64, ARM64_INS_FACGE: facge.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGEv4f32, ARM64_INS_FACGE: facge.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGT32, ARM64_INS_FACGT: facgt $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGT64, ARM64_INS_FACGT: facgt $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGTv2f32, ARM64_INS_FACGT: facgt.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGTv2f64, ARM64_INS_FACGT: facgt.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FACGTv4f32, ARM64_INS_FACGT: facgt.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FADDDrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FADDPv2f32, ARM64_INS_FADDP: faddp.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FADDPv2f64, ARM64_INS_FADDP: faddp.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FADDPv2i32p, ARM64_INS_FADDP: faddp.2s $rd, $rn */ + +{ /* AArch64_DUPv8i16gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FADDPv2i64p, ARM64_INS_FADDP: faddp.2d $rd, $rn */ + +{ /* AArch64_DUPv8i16lane, AArch64_INS_DUP: dup */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_DUPv8i8gpr, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FADDPv4f32, ARM64_INS_FADDP: faddp.4s $rd, $rn, $rm| */ + +{ /* AArch64_DUPv8i8lane, AArch64_INS_DUP: dup */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FADDSrr, ARM64_INS_FADD: fadd $rd, $rn, $rm */ + +{ /* AArch64_EONWrs, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FADDv2f32, ARM64_INS_FADD: fadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_EONXrs, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FADDv2f64, ARM64_INS_FADD: fadd.2d $rd, $rn, $rm| */ + +{ /* AArch64_EOR3, AArch64_INS_EOR3: eor3 */ + 0, + { 0 } +}, + +{ /* AArch64_EORS_PPzPP, AArch64_INS_EORS: eors */ + 0, + { 0 } +}, + +{ /* AArch64_EORV_VPZ_B, AArch64_INS_EORV: eorv */ + 0, + { 0 } +}, + +{ /* AArch64_EORV_VPZ_D, AArch64_INS_EORV: eorv */ + 0, + { 0 } +}, + +{ /* AArch64_EORV_VPZ_H, AArch64_INS_EORV: eorv */ + 0, + { 0 } +}, + +{ /* AArch64_EORV_VPZ_S, AArch64_INS_EORV: eorv */ + 0, + { 0 } +}, + +{ /* AArch64_EORWri, AArch64_INS_EON: eon */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FADDv4f32, ARM64_INS_FADD: fadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_EORWrs, AArch64_INS_EOR: eor */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCCMPDrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */ + +{ /* AArch64_EORXri, AArch64_INS_EON: eon */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_EORXrs, AArch64_INS_EOR: eor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_EOR_PPzPP, AArch64_INS_EOR: eor */ + 0, + { 0 } +}, + +{ /* AArch64_EOR_ZI, AArch64_INS_EON: eon */ + 0, + { 0 } +}, + +{ /* AArch64_EOR_ZPmZ_B, AArch64_INS_EOR: eor */ + 0, + { 0 } +}, + +{ /* AArch64_EOR_ZPmZ_D, AArch64_INS_EOR: eor */ + 0, + { 0 } +}, + +{ /* AArch64_EOR_ZPmZ_H, AArch64_INS_EOR: eor */ + 0, + { 0 } +}, + +{ /* AArch64_EOR_ZPmZ_S, AArch64_INS_EOR: eor */ + 0, + { 0 } +}, + +{ /* AArch64_EOR_ZZZ, AArch64_INS_EOR: eor */ + 0, + { 0 } +}, + +{ /* AArch64_EORv16i8, AArch64_INS_EOR: eor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_EORv8i8, AArch64_INS_EOR: eor */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_ERET, AArch64_INS_ERET: eret */ + 0, + { 0 } +}, + +{ /* AArch64_ERETAA, AArch64_INS_ERETAA: eretaa */ + 0, + { 0 } +}, + +{ /* AArch64_ERETAB, AArch64_INS_ERETAB: eretab */ + 0, + { 0 } +}, + +{ /* AArch64_EXTRWrri, AArch64_INS_EXTR: extr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_EXTRXrri, AArch64_INS_EXTR: extr */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_EXT_ZZI, AArch64_INS_EXT: ext */ + 0, + { 0 } +}, + +{ /* AArch64_EXTv16i8, AArch64_INS_EXT: ext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_EXTv8i8, AArch64_INS_EXT: ext */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FABD16, AArch64_INS_FABD: fabd */ + 0, + { 0 } +}, + +{ /* AArch64_FABD32, AArch64_INS_FABD: fabd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABD64, AArch64_INS_FABD: fabd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABD_ZPmZ_D, AArch64_INS_FABD: fabd */ + 0, + { 0 } +}, + +{ /* AArch64_FABD_ZPmZ_H, AArch64_INS_FABD: fabd */ + 0, + { 0 } +}, + +{ /* AArch64_FABD_ZPmZ_S, AArch64_INS_FABD: fabd */ + 0, + { 0 } +}, + +{ /* AArch64_FABDv2f32, AArch64_INS_FABD: fabd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABDv2f64, AArch64_INS_FABD: fabd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABDv4f16, AArch64_INS_FABD: fabd */ + 0, + { 0 } +}, + +{ /* AArch64_FABDv4f32, AArch64_INS_FABD: fabd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABDv8f16, AArch64_INS_FABD: fabd */ + 0, + { 0 } +}, + +{ /* AArch64_FABSDr, AArch64_INS_FABS: fabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABSHr, AArch64_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* AArch64_FABSSr, AArch64_INS_FABS: fabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABS_ZPmZ_D, AArch64_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* AArch64_FABS_ZPmZ_H, AArch64_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* AArch64_FABS_ZPmZ_S, AArch64_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* AArch64_FABSv2f32, AArch64_INS_FABS: fabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABSv2f64, AArch64_INS_FABS: fabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABSv4f16, AArch64_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* AArch64_FABSv4f32, AArch64_INS_FABS: fabs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FABSv8f16, AArch64_INS_FABS: fabs */ + 0, + { 0 } +}, + +{ /* AArch64_FACGE16, AArch64_INS_FACGE: facge */ + 0, + { 0 } +}, + +{ /* AArch64_FACGE32, AArch64_INS_FACGE: facge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGE64, AArch64_INS_FACGE: facge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGE_PPzZZ_D, AArch64_INS_FACGE: facge */ + 0, + { 0 } +}, + +{ /* AArch64_FACGE_PPzZZ_H, AArch64_INS_FACGE: facge */ + 0, + { 0 } +}, + +{ /* AArch64_FACGE_PPzZZ_S, AArch64_INS_FACGE: facge */ + 0, + { 0 } +}, + +{ /* AArch64_FACGEv2f32, AArch64_INS_FACGE: facge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGEv2f64, AArch64_INS_FACGE: facge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGEv4f16, AArch64_INS_FACGE: facge */ + 0, + { 0 } +}, + +{ /* AArch64_FACGEv4f32, AArch64_INS_FACGE: facge */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGEv8f16, AArch64_INS_FACGE: facge */ + 0, + { 0 } +}, + +{ /* AArch64_FACGT16, AArch64_INS_FACGT: facgt */ + 0, + { 0 } +}, + +{ /* AArch64_FACGT32, AArch64_INS_FACGT: facgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGT64, AArch64_INS_FACGT: facgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGT_PPzZZ_D, AArch64_INS_FACGT: facgt */ + 0, + { 0 } +}, + +{ /* AArch64_FACGT_PPzZZ_H, AArch64_INS_FACGT: facgt */ + 0, + { 0 } +}, + +{ /* AArch64_FACGT_PPzZZ_S, AArch64_INS_FACGT: facgt */ + 0, + { 0 } +}, + +{ /* AArch64_FACGTv2f32, AArch64_INS_FACGT: facgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGTv2f64, AArch64_INS_FACGT: facgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGTv4f16, AArch64_INS_FACGT: facgt */ + 0, + { 0 } +}, + +{ /* AArch64_FACGTv4f32, AArch64_INS_FACGT: facgt */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FACGTv8f16, AArch64_INS_FACGT: facgt */ + 0, + { 0 } +}, + +{ /* AArch64_FADDA_VPZ_D, AArch64_INS_FADDA: fadda */ + 0, + { 0 } +}, + +{ /* AArch64_FADDA_VPZ_H, AArch64_INS_FADDA: fadda */ + 0, + { 0 } +}, + +{ /* AArch64_FADDA_VPZ_S, AArch64_INS_FADDA: fadda */ + 0, + { 0 } +}, + +{ /* AArch64_FADDDrr, AArch64_INS_FADD: fadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDHrr, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADDPv2f32, AArch64_INS_FADDP: faddp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDPv2f64, AArch64_INS_FADDP: faddp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDPv2i16p, AArch64_INS_FADDP: faddp */ + 0, + { 0 } +}, + +{ /* AArch64_FADDPv2i32p, AArch64_INS_FADDP: faddp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDPv2i64p, AArch64_INS_FADDP: faddp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDPv4f16, AArch64_INS_FADDP: faddp */ + 0, + { 0 } +}, + +{ /* AArch64_FADDPv4f32, AArch64_INS_FADDP: faddp */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDPv8f16, AArch64_INS_FADDP: faddp */ + 0, + { 0 } +}, + +{ /* AArch64_FADDSrr, AArch64_INS_FADD: fadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDV_VPZ_D, AArch64_INS_FADDV: faddv */ + 0, + { 0 } +}, + +{ /* AArch64_FADDV_VPZ_H, AArch64_INS_FADDV: faddv */ + 0, + { 0 } +}, + +{ /* AArch64_FADDV_VPZ_S, AArch64_INS_FADDV: faddv */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZPmI_D, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZPmI_H, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZPmI_S, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZPmZ_D, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZPmZ_H, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZPmZ_S, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZZZ_D, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZZZ_H, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADD_ZZZ_S, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADDv2f32, AArch64_INS_FADD: fadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDv2f64, AArch64_INS_FADD: fadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDv4f16, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FADDv4f32, AArch64_INS_FADD: fadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FADDv8f16, AArch64_INS_FADD: fadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADD_ZPmZ_D, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADD_ZPmZ_H, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADD_ZPmZ_S, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADDv2f32, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADDv2f64, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADDv4f16, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADDv4f32, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCADDv8f16, AArch64_INS_FCADD: fcadd */ + 0, + { 0 } +}, + +{ /* AArch64_FCCMPDrr, AArch64_INS_FCCMP: fccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, -{ /* AArch64_FCCMPEDrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */ + +{ /* AArch64_FCCMPEDrr, AArch64_INS_FCCMPE: fccmpe */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, -{ /* AArch64_FCCMPESrr, ARM64_INS_FCCMPE: fccmpe $rn, $rm, $nzcv, $cond */ + +{ /* AArch64_FCCMPEHrr, AArch64_INS_FCCMPE: fccmpe */ + 0, + { 0 } +}, + +{ /* AArch64_FCCMPESrr, AArch64_INS_FCCMPE: fccmpe */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, -{ /* AArch64_FCCMPSrr, ARM64_INS_FCCMP: fccmp $rn, $rm, $nzcv, $cond */ + +{ /* AArch64_FCCMPHrr, AArch64_INS_FCCMP: fccmp */ + 0, + { 0 } +}, + +{ /* AArch64_FCCMPSrr, AArch64_INS_FCCMP: fccmp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE, CS_AC_READ } }, -{ /* AArch64_FCMEQ32, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */ + +{ /* AArch64_FCMEQ16, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQ32, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQ64, ARM64_INS_FCMEQ: fcmeq $rd, $rn, $rm */ + +{ /* AArch64_FCMEQ64, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv1i32rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */ + +{ /* AArch64_FCMEQ_PPzZ0_D, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQ_PPzZ0_H, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQ_PPzZ0_S, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQ_PPzZZ_D, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQ_PPzZZ_H, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQ_PPzZZ_S, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQv1i16rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQv1i32rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv1i64rz, ARM64_INS_FCMEQ: fcmeq $rd, $rn, #0.0 */ + +{ /* AArch64_FCMEQv1i64rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv2f32, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, $rm| */ + +{ /* AArch64_FCMEQv2f32, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv2f64, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, $rm| */ + +{ /* AArch64_FCMEQv2f64, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv2i32rz, ARM64_INS_FCMEQ: fcmeq.2s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMEQv2i32rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv2i64rz, ARM64_INS_FCMEQ: fcmeq.2d $rd, $rn, #0.0 */ + +{ /* AArch64_FCMEQv2i64rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv4f32, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, $rm| */ + +{ /* AArch64_FCMEQv4f16, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQv4f32, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMEQv4i32rz, ARM64_INS_FCMEQ: fcmeq.4s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMEQv4i16rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQv4i32rz, AArch64_INS_FCMEQ: fcmeq */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGE32, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */ + +{ /* AArch64_FCMEQv8f16, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMEQv8i16rz, AArch64_INS_FCMEQ: fcmeq */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE16, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE32, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGE64, ARM64_INS_FCMGE: fcmge $rd, $rn, $rm */ + +{ /* AArch64_FCMGE64, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv1i32rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGE_PPzZ0_D, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE_PPzZ0_H, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE_PPzZ0_S, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE_PPzZZ_D, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE_PPzZZ_H, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGE_PPzZZ_S, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGEv1i16rz, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGEv1i32rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv1i64rz, ARM64_INS_FCMGE: fcmge $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGEv1i64rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv2f32, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, $rm| */ + +{ /* AArch64_FCMGEv2f32, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv2f64, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, $rm| */ + +{ /* AArch64_FCMGEv2f64, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv2i32rz, ARM64_INS_FCMGE: fcmge.2s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGEv2i32rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv2i64rz, ARM64_INS_FCMGE: fcmge.2d $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGEv2i64rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv4f32, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, $rm| */ + +{ /* AArch64_FCMGEv4f16, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGEv4f32, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGEv4i32rz, ARM64_INS_FCMGE: fcmge.4s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGEv4i16rz, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGEv4i32rz, AArch64_INS_FCMGE: fcmge */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGT32, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */ + +{ /* AArch64_FCMGEv8f16, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGEv8i16rz, AArch64_INS_FCMGE: fcmge */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT16, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT32, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGT64, ARM64_INS_FCMGT: fcmgt $rd, $rn, $rm */ + +{ /* AArch64_FCMGT64, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv1i32rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGT_PPzZ0_D, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT_PPzZ0_H, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT_PPzZ0_S, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT_PPzZZ_D, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT_PPzZZ_H, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGT_PPzZZ_S, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGTv1i16rz, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGTv1i32rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv1i64rz, ARM64_INS_FCMGT: fcmgt $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGTv1i64rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv2f32, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, $rm| */ + +{ /* AArch64_FCMGTv2f32, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv2f64, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, $rm| */ + +{ /* AArch64_FCMGTv2f64, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv2i32rz, ARM64_INS_FCMGT: fcmgt.2s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGTv2i32rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv2i64rz, ARM64_INS_FCMGT: fcmgt.2d $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGTv2i64rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv4f32, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, $rm| */ + +{ /* AArch64_FCMGTv4f16, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGTv4f32, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMGTv4i32rz, ARM64_INS_FCMGT: fcmgt.4s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGTv4i16rz, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGTv4i32rz, AArch64_INS_FCMGT: fcmgt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLEv1i32rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */ + +{ /* AArch64_FCMGTv8f16, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMGTv8i16rz, AArch64_INS_FCMGT: fcmgt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLA_ZPmZZ_D, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLA_ZPmZZ_H, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLA_ZPmZZ_S, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLA_ZZZI_H, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLA_ZZZI_S, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv2f32, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv2f64, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv4f16, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv4f16_indexed, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv4f32, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv4f32_indexed, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv8f16, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLAv8f16_indexed, AArch64_INS_FCMLA: fcmla */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLE_PPzZ0_D, AArch64_INS_FCMLE: fcmle */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLE_PPzZ0_H, AArch64_INS_FCMLE: fcmle */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLE_PPzZ0_S, AArch64_INS_FCMLE: fcmle */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLEv1i16rz, AArch64_INS_FCMLE: fcmle */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLEv1i32rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLEv1i64rz, ARM64_INS_FCMLE: fcmle $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLEv1i64rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLEv2i32rz, ARM64_INS_FCMLE: fcmle.2s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLEv2i32rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLEv2i64rz, ARM64_INS_FCMLE: fcmle.2d $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLEv2i64rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLEv4i32rz, ARM64_INS_FCMLE: fcmle.4s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLEv4i16rz, AArch64_INS_FCMLE: fcmle */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLEv4i32rz, AArch64_INS_FCMLE: fcmle */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLTv1i32rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLEv8i16rz, AArch64_INS_FCMLE: fcmle */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLT_PPzZ0_D, AArch64_INS_FCMLT: fcmlt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLT_PPzZ0_H, AArch64_INS_FCMLT: fcmlt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLT_PPzZ0_S, AArch64_INS_FCMLT: fcmlt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLTv1i16rz, AArch64_INS_FCMLT: fcmlt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLTv1i32rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLTv1i64rz, ARM64_INS_FCMLT: fcmlt $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLTv1i64rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLTv2i32rz, ARM64_INS_FCMLT: fcmlt.2s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLTv2i32rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLTv2i64rz, ARM64_INS_FCMLT: fcmlt.2d $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLTv2i64rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMLTv4i32rz, ARM64_INS_FCMLT: fcmlt.4s $rd, $rn, #0.0 */ + +{ /* AArch64_FCMLTv4i16rz, AArch64_INS_FCMLT: fcmlt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMLTv4i32rz, AArch64_INS_FCMLT: fcmlt */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPDri, ARM64_INS_FCMP: fcmp $rn, #0.0 */ + +{ /* AArch64_FCMLTv8i16rz, AArch64_INS_FCMLT: fcmlt */ + 0, + { 0 } +}, + +{ /* AArch64_FCMNE_PPzZ0_D, AArch64_INS_FCMNE: fcmne */ + 0, + { 0 } +}, + +{ /* AArch64_FCMNE_PPzZ0_H, AArch64_INS_FCMNE: fcmne */ + 0, + { 0 } +}, + +{ /* AArch64_FCMNE_PPzZ0_S, AArch64_INS_FCMNE: fcmne */ + 0, + { 0 } +}, + +{ /* AArch64_FCMNE_PPzZZ_D, AArch64_INS_FCMNE: fcmne */ + 0, + { 0 } +}, + +{ /* AArch64_FCMNE_PPzZZ_H, AArch64_INS_FCMNE: fcmne */ + 0, + { 0 } +}, + +{ /* AArch64_FCMNE_PPzZZ_S, AArch64_INS_FCMNE: fcmne */ + 0, + { 0 } +}, + +{ /* AArch64_FCMPDri, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPDrr, ARM64_INS_FCMP: fcmp $rn, $rm */ + +{ /* AArch64_FCMPDrr, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPEDri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */ + +{ /* AArch64_FCMPEDri, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPEDrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */ + +{ /* AArch64_FCMPEDrr, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPESri, ARM64_INS_FCMPE: fcmpe $rn, #0.0 */ + +{ /* AArch64_FCMPEHri, AArch64_INS_FCMPE: fcmpe */ + 0, + { 0 } +}, + +{ /* AArch64_FCMPEHrr, AArch64_INS_FCMPE: fcmpe */ + 0, + { 0 } +}, + +{ /* AArch64_FCMPESri, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPESrr, ARM64_INS_FCMPE: fcmpe $rn, $rm */ + +{ /* AArch64_FCMPESrr, AArch64_INS_FCMPE: fcmpe */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPSri, ARM64_INS_FCMP: fcmp $rn, #0.0 */ + +{ /* AArch64_FCMPHri, AArch64_INS_FCMP: fcmp */ + 0, + { 0 } +}, + +{ /* AArch64_FCMPHrr, AArch64_INS_FCMP: fcmp */ + 0, + { 0 } +}, + +{ /* AArch64_FCMPSri, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCMPSrr, ARM64_INS_FCMP: fcmp $rn, $rm */ + +{ /* AArch64_FCMPSrr, AArch64_INS_FCMP: fcmp */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCSELDrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */ + +{ /* AArch64_FCMUO_PPzZZ_D, AArch64_INS_FCMUO: fcmuo */ + 0, + { 0 } +}, + +{ /* AArch64_FCMUO_PPzZZ_H, AArch64_INS_FCMUO: fcmuo */ + 0, + { 0 } +}, + +{ /* AArch64_FCMUO_PPzZZ_S, AArch64_INS_FCMUO: fcmuo */ + 0, + { 0 } +}, + +{ /* AArch64_FCPY_ZPmI_D, AArch64_INS_FCPY: fcpy */ + 0, + { 0 } +}, + +{ /* AArch64_FCPY_ZPmI_H, AArch64_INS_FCPY: fcpy */ + 0, + { 0 } +}, + +{ /* AArch64_FCPY_ZPmI_S, AArch64_INS_FCPY: fcpy */ + 0, + { 0 } +}, + +{ /* AArch64_FCSELDrrr, AArch64_INS_FCSEL: fcsel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FCSELSrrr, ARM64_INS_FCSEL: fcsel $rd, $rn, $rm, $cond */ + +{ /* AArch64_FCSELHrrr, AArch64_INS_FCSEL: fcsel */ + 0, + { 0 } +}, + +{ /* AArch64_FCSELSrrr, AArch64_INS_FCSEL: fcsel */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FCVTASUWDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + +{ /* AArch64_FCVTASUWDr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASUWSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + +{ /* AArch64_FCVTASUWHr, AArch64_INS_FCVTAS: fcvtas */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTASUWSr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASUXDr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + +{ /* AArch64_FCVTASUXDr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASUXSr, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + +{ /* AArch64_FCVTASUXHr, AArch64_INS_FCVTAS: fcvtas */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTASUXSr, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASv1i32, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + +{ /* AArch64_FCVTASv1f16, AArch64_INS_FCVTAS: fcvtas */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTASv1i32, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASv1i64, ARM64_INS_FCVTAS: fcvtas $rd, $rn */ + +{ /* AArch64_FCVTASv1i64, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASv2f32, ARM64_INS_FCVTAS: fcvtas.2s $rd, $rn */ + +{ /* AArch64_FCVTASv2f32, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASv2f64, ARM64_INS_FCVTAS: fcvtas.2d $rd, $rn */ + +{ /* AArch64_FCVTASv2f64, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTASv4f32, ARM64_INS_FCVTAS: fcvtas.4s $rd, $rn */ + +{ /* AArch64_FCVTASv4f16, AArch64_INS_FCVTAS: fcvtas */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTASv4f32, AArch64_INS_FCVTAS: fcvtas */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUUWDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + +{ /* AArch64_FCVTASv8f16, AArch64_INS_FCVTAS: fcvtas */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTAUUWDr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUUWSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + +{ /* AArch64_FCVTAUUWHr, AArch64_INS_FCVTAU: fcvtau */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTAUUWSr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUUXDr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + +{ /* AArch64_FCVTAUUXDr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUUXSr, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + +{ /* AArch64_FCVTAUUXHr, AArch64_INS_FCVTAU: fcvtau */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTAUUXSr, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUv1i32, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + +{ /* AArch64_FCVTAUv1f16, AArch64_INS_FCVTAU: fcvtau */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTAUv1i32, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUv1i64, ARM64_INS_FCVTAU: fcvtau $rd, $rn */ + +{ /* AArch64_FCVTAUv1i64, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUv2f32, ARM64_INS_FCVTAU: fcvtau.2s $rd, $rn */ + +{ /* AArch64_FCVTAUv2f32, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUv2f64, ARM64_INS_FCVTAU: fcvtau.2d $rd, $rn */ + +{ /* AArch64_FCVTAUv2f64, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTAUv4f32, ARM64_INS_FCVTAU: fcvtau.4s $rd, $rn */ + +{ /* AArch64_FCVTAUv4f16, AArch64_INS_FCVTAU: fcvtau */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTAUv4f32, AArch64_INS_FCVTAU: fcvtau */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTDHr, ARM64_INS_FCVT: fcvt $rd, $rn */ + +{ /* AArch64_FCVTAUv8f16, AArch64_INS_FCVTAU: fcvtau */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTDHr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTDSr, ARM64_INS_FCVT: fcvt $rd, $rn */ + +{ /* AArch64_FCVTDSr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTHDr, ARM64_INS_FCVT: fcvt $rd, $rn */ + +{ /* AArch64_FCVTHDr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTHSr, ARM64_INS_FCVT: fcvt $rd, $rn */ + +{ /* AArch64_FCVTHSr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTLv2i32, ARM64_INS_FCVTL: fcvtl $rd.2d, $rn.2s */ + +{ /* AArch64_FCVTLv2i32, AArch64_INS_FCVTL: fcvtl */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTLv4i16, ARM64_INS_FCVTL: fcvtl $rd.4s, $rn.4h */ + +{ /* AArch64_FCVTLv4i16, AArch64_INS_FCVTL: fcvtl */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTLv4i32, ARM64_INS_FCVTL2: fcvtl2 $rd.2d, $rn.4s */ + +{ /* AArch64_FCVTLv4i32, AArch64_INS_FCVTL2: fcvtl2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTLv8i16, ARM64_INS_FCVTL2: fcvtl2 $rd.4s, $rn.8h */ + +{ /* AArch64_FCVTLv8i16, AArch64_INS_FCVTL2: fcvtl2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSUWDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + +{ /* AArch64_FCVTMSUWDr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSUWSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + +{ /* AArch64_FCVTMSUWHr, AArch64_INS_FCVTMS: fcvtms */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMSUWSr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSUXDr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + +{ /* AArch64_FCVTMSUXDr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSUXSr, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + +{ /* AArch64_FCVTMSUXHr, AArch64_INS_FCVTMS: fcvtms */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMSUXSr, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSv1i32, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + +{ /* AArch64_FCVTMSv1f16, AArch64_INS_FCVTMS: fcvtms */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMSv1i32, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSv1i64, ARM64_INS_FCVTMS: fcvtms $rd, $rn */ + +{ /* AArch64_FCVTMSv1i64, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSv2f32, ARM64_INS_FCVTMS: fcvtms.2s $rd, $rn */ + +{ /* AArch64_FCVTMSv2f32, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSv2f64, ARM64_INS_FCVTMS: fcvtms.2d $rd, $rn */ + +{ /* AArch64_FCVTMSv2f64, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMSv4f32, ARM64_INS_FCVTMS: fcvtms.4s $rd, $rn */ + +{ /* AArch64_FCVTMSv4f16, AArch64_INS_FCVTMS: fcvtms */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMSv4f32, AArch64_INS_FCVTMS: fcvtms */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUUWDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + +{ /* AArch64_FCVTMSv8f16, AArch64_INS_FCVTMS: fcvtms */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMUUWDr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUUWSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + +{ /* AArch64_FCVTMUUWHr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMUUWSr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUUXDr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + +{ /* AArch64_FCVTMUUXDr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUUXSr, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + +{ /* AArch64_FCVTMUUXHr, AArch64_INS_FCVTMU: fcvtmu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMUUXSr, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUv1i32, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + +{ /* AArch64_FCVTMUv1f16, AArch64_INS_FCVTMU: fcvtmu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMUv1i32, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUv1i64, ARM64_INS_FCVTMU: fcvtmu $rd, $rn */ + +{ /* AArch64_FCVTMUv1i64, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUv2f32, ARM64_INS_FCVTMU: fcvtmu.2s $rd, $rn */ + +{ /* AArch64_FCVTMUv2f32, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUv2f64, ARM64_INS_FCVTMU: fcvtmu.2d $rd, $rn */ + +{ /* AArch64_FCVTMUv2f64, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTMUv4f32, ARM64_INS_FCVTMU: fcvtmu.4s $rd, $rn */ + +{ /* AArch64_FCVTMUv4f16, AArch64_INS_FCVTMU: fcvtmu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTMUv4f32, AArch64_INS_FCVTMU: fcvtmu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSUWDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + +{ /* AArch64_FCVTMUv8f16, AArch64_INS_FCVTMU: fcvtmu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNSUWDr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSUWSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + +{ /* AArch64_FCVTNSUWHr, AArch64_INS_FCVTNS: fcvtns */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNSUWSr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSUXDr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + +{ /* AArch64_FCVTNSUXDr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSUXSr, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + +{ /* AArch64_FCVTNSUXHr, AArch64_INS_FCVTNS: fcvtns */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNSUXSr, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSv1i32, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + +{ /* AArch64_FCVTNSv1f16, AArch64_INS_FCVTNS: fcvtns */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNSv1i32, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSv1i64, ARM64_INS_FCVTNS: fcvtns $rd, $rn */ + +{ /* AArch64_FCVTNSv1i64, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSv2f32, ARM64_INS_FCVTNS: fcvtns.2s $rd, $rn */ + +{ /* AArch64_FCVTNSv2f32, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSv2f64, ARM64_INS_FCVTNS: fcvtns.2d $rd, $rn */ + +{ /* AArch64_FCVTNSv2f64, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNSv4f32, ARM64_INS_FCVTNS: fcvtns.4s $rd, $rn */ + +{ /* AArch64_FCVTNSv4f16, AArch64_INS_FCVTNS: fcvtns */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNSv4f32, AArch64_INS_FCVTNS: fcvtns */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUUWDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + +{ /* AArch64_FCVTNSv8f16, AArch64_INS_FCVTNS: fcvtns */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNUUWDr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUUWSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + +{ /* AArch64_FCVTNUUWHr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNUUWSr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUUXDr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + +{ /* AArch64_FCVTNUUXDr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUUXSr, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + +{ /* AArch64_FCVTNUUXHr, AArch64_INS_FCVTNU: fcvtnu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNUUXSr, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUv1i32, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + +{ /* AArch64_FCVTNUv1f16, AArch64_INS_FCVTNU: fcvtnu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNUv1i32, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUv1i64, ARM64_INS_FCVTNU: fcvtnu $rd, $rn */ + +{ /* AArch64_FCVTNUv1i64, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUv2f32, ARM64_INS_FCVTNU: fcvtnu.2s $rd, $rn */ + +{ /* AArch64_FCVTNUv2f32, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUv2f64, ARM64_INS_FCVTNU: fcvtnu.2d $rd, $rn */ + +{ /* AArch64_FCVTNUv2f64, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNUv4f32, ARM64_INS_FCVTNU: fcvtnu.4s $rd, $rn */ + +{ /* AArch64_FCVTNUv4f16, AArch64_INS_FCVTNU: fcvtnu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNUv4f32, AArch64_INS_FCVTNU: fcvtnu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNv2i32, ARM64_INS_FCVTN: fcvtn $rd.2s, $rn.2d */ + +{ /* AArch64_FCVTNUv8f16, AArch64_INS_FCVTNU: fcvtnu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTNv2i32, AArch64_INS_FCVTN: fcvtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNv4i16, ARM64_INS_FCVTN: fcvtn $rd.4h, $rn.4s */ + +{ /* AArch64_FCVTNv4i16, AArch64_INS_FCVTN: fcvtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNv4i32, ARM64_INS_FCVTN2: fcvtn2 $rd.4s, $rn.2d */ + +{ /* AArch64_FCVTNv4i32, AArch64_INS_FCVTN2: fcvtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTNv8i16, ARM64_INS_FCVTN2: fcvtn2 $rd.8h, $rn.4s */ + +{ /* AArch64_FCVTNv8i16, AArch64_INS_FCVTN2: fcvtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSUWDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + +{ /* AArch64_FCVTPSUWDr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSUWSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + +{ /* AArch64_FCVTPSUWHr, AArch64_INS_FCVTPS: fcvtps */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPSUWSr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSUXDr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + +{ /* AArch64_FCVTPSUXDr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSUXSr, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + +{ /* AArch64_FCVTPSUXHr, AArch64_INS_FCVTPS: fcvtps */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPSUXSr, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSv1i32, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + +{ /* AArch64_FCVTPSv1f16, AArch64_INS_FCVTPS: fcvtps */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPSv1i32, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSv1i64, ARM64_INS_FCVTPS: fcvtps $rd, $rn */ + +{ /* AArch64_FCVTPSv1i64, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSv2f32, ARM64_INS_FCVTPS: fcvtps.2s $rd, $rn */ + +{ /* AArch64_FCVTPSv2f32, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSv2f64, ARM64_INS_FCVTPS: fcvtps.2d $rd, $rn */ + +{ /* AArch64_FCVTPSv2f64, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPSv4f32, ARM64_INS_FCVTPS: fcvtps.4s $rd, $rn */ + +{ /* AArch64_FCVTPSv4f16, AArch64_INS_FCVTPS: fcvtps */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPSv4f32, AArch64_INS_FCVTPS: fcvtps */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUUWDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + +{ /* AArch64_FCVTPSv8f16, AArch64_INS_FCVTPS: fcvtps */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPUUWDr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUUWSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + +{ /* AArch64_FCVTPUUWHr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPUUWSr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUUXDr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + +{ /* AArch64_FCVTPUUXDr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUUXSr, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + +{ /* AArch64_FCVTPUUXHr, AArch64_INS_FCVTPU: fcvtpu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPUUXSr, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUv1i32, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + +{ /* AArch64_FCVTPUv1f16, AArch64_INS_FCVTPU: fcvtpu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPUv1i32, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUv1i64, ARM64_INS_FCVTPU: fcvtpu $rd, $rn */ + +{ /* AArch64_FCVTPUv1i64, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUv2f32, ARM64_INS_FCVTPU: fcvtpu.2s $rd, $rn */ + +{ /* AArch64_FCVTPUv2f32, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUv2f64, ARM64_INS_FCVTPU: fcvtpu.2d $rd, $rn */ + +{ /* AArch64_FCVTPUv2f64, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTPUv4f32, ARM64_INS_FCVTPU: fcvtpu.4s $rd, $rn */ + +{ /* AArch64_FCVTPUv4f16, AArch64_INS_FCVTPU: fcvtpu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTPUv4f32, AArch64_INS_FCVTPU: fcvtpu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTSDr, ARM64_INS_FCVT: fcvt $rd, $rn */ + +{ /* AArch64_FCVTPUv8f16, AArch64_INS_FCVTPU: fcvtpu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTSDr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTSHr, ARM64_INS_FCVT: fcvt $rd, $rn */ + +{ /* AArch64_FCVTSHr, AArch64_INS_FCVT: fcvt */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTXNv1i64, ARM64_INS_FCVTXN: fcvtxn $rd, $rn */ + +{ /* AArch64_FCVTXNv1i64, AArch64_INS_FCVTXN: fcvtxn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTXNv2f32, ARM64_INS_FCVTXN: fcvtxn $rd.2s, $rn.2d */ + +{ /* AArch64_FCVTXNv2f32, AArch64_INS_FCVTXN: fcvtxn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTXNv4f32, ARM64_INS_FCVTXN2: fcvtxn2 $rd.4s, $rn.2d */ + +{ /* AArch64_FCVTXNv4f32, AArch64_INS_FCVTXN2: fcvtxn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSSWDri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSSWHri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSSWSri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSSXDri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSSXHri, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSSXSri, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZSUWDr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZSUWHr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSUWSr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZSUXDr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZSUXHr, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSUXSr, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZS_IntSWDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZS_ZPmZ_DtoD, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZS_ZPmZ_DtoS, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZS_ZPmZ_HtoD, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZS_ZPmZ_HtoH, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZS_ZPmZ_HtoS, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZS_ZPmZ_StoD, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZS_ZPmZ_StoS, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSd, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZS_IntSWSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSh, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSs, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZS_IntSXDri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSv1f16, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSv1i32, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZSv1i64, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZSv2f32, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZSv2f64, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZSv2i32_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZS_IntSXSri, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $scale */ + +{ /* AArch64_FCVTZSv2i64_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZS_IntUWDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZSv4f16, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSv4f32, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZS_IntUWSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZSv4i16_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, - { CS_AC_WRITE, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZS_IntUXDr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZS_IntUXSr, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZS_Intv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZS_Intv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZS_Intv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZSd, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */ + +{ /* AArch64_FCVTZSv4i32_shift, AArch64_INS_FCVTZS: fcvtzs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSs, ARM64_INS_FCVTZS: fcvtzs $rd, $rn, $imm */ + +{ /* AArch64_FCVTZSv8f16, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZSv8i16_shift, AArch64_INS_FCVTZS: fcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUSWDri, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv1i32, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZUSWHri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUSWSri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZUSXDri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZUSXHri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUSXSri, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FCVTZUUWDr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv1i64, ARM64_INS_FCVTZS: fcvtzs $rd, $rn */ + +{ /* AArch64_FCVTZUUWHr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUUWSr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv2f32, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn */ + +{ /* AArch64_FCVTZUUXDr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv2f64, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn */ + +{ /* AArch64_FCVTZUUXHr, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUUXSr, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv2i32_shift, ARM64_INS_FCVTZS: fcvtzs.2s $rd, $rn, $imm */ + +{ /* AArch64_FCVTZU_ZPmZ_DtoD, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZU_ZPmZ_DtoS, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZU_ZPmZ_HtoD, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZU_ZPmZ_HtoH, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZU_ZPmZ_HtoS, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZU_ZPmZ_StoD, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZU_ZPmZ_StoS, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUd, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv2i64_shift, ARM64_INS_FCVTZS: fcvtzs.2d $rd, $rn, $imm */ + +{ /* AArch64_FCVTZUh, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUs, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv4f32, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn */ + +{ /* AArch64_FCVTZUv1f16, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUv1i32, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZSv4i32_shift, ARM64_INS_FCVTZS: fcvtzs.4s $rd, $rn, $imm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FCVTZUv1i64, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FCVTZUv2f32, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FCVTZUv2f64, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZU_IntSWDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + +{ /* AArch64_FCVTZUv2i32_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZU_IntSWSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + +{ /* AArch64_FCVTZUv2i64_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZU_IntSXDri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ + +{ /* AArch64_FCVTZUv4f16, AArch64_INS_FCVTZU: fcvtzu */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZU_IntSXSri, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $scale */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZU_IntUWDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FCVTZUv4f32, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZU_IntUWSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FCVTZUv4i16_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, - { CS_AC_WRITE, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZU_IntUXDr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZU_IntUXSr, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZU_Intv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZU_Intv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZU_Intv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUd, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */ + +{ /* AArch64_FCVTZUv4i32_shift, AArch64_INS_FCVTZU: fcvtzu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUs, ARM64_INS_FCVTZU: fcvtzu $rd, $rn, $imm */ + +{ /* AArch64_FCVTZUv8f16, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVTZUv8i16_shift, AArch64_INS_FCVTZU: fcvtzu */ + 0, + { 0 } +}, + +{ /* AArch64_FCVT_ZPmZ_DtoH, AArch64_INS_FCVT: fcvt */ + 0, + { 0 } +}, + +{ /* AArch64_FCVT_ZPmZ_DtoS, AArch64_INS_FCVT: fcvt */ + 0, + { 0 } +}, + +{ /* AArch64_FCVT_ZPmZ_HtoD, AArch64_INS_FCVT: fcvt */ + 0, + { 0 } +}, + +{ /* AArch64_FCVT_ZPmZ_HtoS, AArch64_INS_FCVT: fcvt */ + 0, + { 0 } +}, + +{ /* AArch64_FCVT_ZPmZ_StoD, AArch64_INS_FCVT: fcvt */ + 0, + { 0 } +}, + +{ /* AArch64_FCVT_ZPmZ_StoH, AArch64_INS_FCVT: fcvt */ + 0, + { 0 } +}, + +{ /* AArch64_FDIVDrr, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUv1i32, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FDIVHrr, AArch64_INS_FDIV: fdiv */ 0, - { CS_AC_WRITE, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZUv1i64, ARM64_INS_FCVTZU: fcvtzu $rd, $rn */ + +{ /* AArch64_FDIVR_ZPmZ_D, AArch64_INS_FDIVR: fdivr */ 0, - { CS_AC_WRITE, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZUv2f32, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn */ + +{ /* AArch64_FDIVR_ZPmZ_H, AArch64_INS_FDIVR: fdivr */ 0, - { CS_AC_WRITE, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZUv2f64, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn */ + +{ /* AArch64_FDIVR_ZPmZ_S, AArch64_INS_FDIVR: fdivr */ 0, - { CS_AC_WRITE, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FCVTZUv2i32_shift, ARM64_INS_FCVTZU: fcvtzu.2s $rd, $rn, $imm */ + +{ /* AArch64_FDIVSrr, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUv2i64_shift, ARM64_INS_FCVTZU: fcvtzu.2d $rd, $rn, $imm */ + +{ /* AArch64_FDIV_ZPmZ_D, AArch64_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* AArch64_FDIV_ZPmZ_H, AArch64_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* AArch64_FDIV_ZPmZ_S, AArch64_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* AArch64_FDIVv2f32, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FCVTZUv4f32, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FCVTZUv4i32_shift, ARM64_INS_FCVTZU: fcvtzu.4s $rd, $rn, $imm */ + +{ /* AArch64_FDIVv2f64, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FDIVDrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */ + +{ /* AArch64_FDIVv4f16, AArch64_INS_FDIV: fdiv */ + 0, + { 0 } +}, + +{ /* AArch64_FDIVv4f32, AArch64_INS_FDIV: fdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FDIVSrr, ARM64_INS_FDIV: fdiv $rd, $rn, $rm */ + +{ /* AArch64_FDIVv8f16, AArch64_INS_FDIV: fdiv */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FDIVv2f32, ARM64_INS_FDIV: fdiv.2s $rd, $rn, $rm| */ + +{ /* AArch64_FDUP_ZI_D, AArch64_INS_FDUP: fdup */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FDIVv2f64, ARM64_INS_FDIV: fdiv.2d $rd, $rn, $rm| */ + +{ /* AArch64_FDUP_ZI_H, AArch64_INS_FDUP: fdup */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FDIVv4f32, ARM64_INS_FDIV: fdiv.4s $rd, $rn, $rm| */ + +{ /* AArch64_FDUP_ZI_S, AArch64_INS_FDUP: fdup */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } + { 0 } }, -{ /* AArch64_FMADDDrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */ + +{ /* AArch64_FEXPA_ZZ_D, AArch64_INS_FEXPA: fexpa */ + 0, + { 0 } +}, + +{ /* AArch64_FEXPA_ZZ_H, AArch64_INS_FEXPA: fexpa */ + 0, + { 0 } +}, + +{ /* AArch64_FEXPA_ZZ_S, AArch64_INS_FEXPA: fexpa */ + 0, + { 0 } +}, + +{ /* AArch64_FJCVTZS, AArch64_INS_FJCVTZS: fjcvtzs */ + 0, + { 0 } +}, + +{ /* AArch64_FMADDDrrr, AArch64_INS_FMADD: fmadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMADDSrrr, ARM64_INS_FMADD: fmadd $rd, $rn, $rm, $ra */ + +{ /* AArch64_FMADDHrrr, AArch64_INS_FMADD: fmadd */ + 0, + { 0 } +}, + +{ /* AArch64_FMADDSrrr, AArch64_INS_FMADD: fmadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMAXDrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */ + +{ /* AArch64_FMAD_ZPmZZ_D, AArch64_INS_FMAD: fmad */ + 0, + { 0 } +}, + +{ /* AArch64_FMAD_ZPmZZ_H, AArch64_INS_FMAD: fmad */ + 0, + { 0 } +}, + +{ /* AArch64_FMAD_ZPmZZ_S, AArch64_INS_FMAD: fmad */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXDrr, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMDrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */ + +{ /* AArch64_FMAXHrr, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMDrr, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMPv2f32, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMHrr, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMPv2f32, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMPv2f64, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMPv2f64, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMPv2i32p, ARM64_INS_FMAXNMP: fmaxnmp.2s $rd, $rn */ + +{ /* AArch64_FMAXNMPv2i16p, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMPv2i32p, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMPv2i64p, ARM64_INS_FMAXNMP: fmaxnmp.2d $rd, $rn */ + +{ /* AArch64_FMAXNMPv2i64p, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMPv4f32, ARM64_INS_FMAXNMP: fmaxnmp.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMPv4f16, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMPv4f32, AArch64_INS_FMAXNMP: fmaxnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMSrr, ARM64_INS_FMAXNM: fmaxnm $rd, $rn, $rm */ + +{ /* AArch64_FMAXNMPv8f16, AArch64_INS_FMAXNMP: fmaxnmp */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMSrr, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMVv4i32v, ARM64_INS_FMAXNMV: fmaxnmv.4s $rd, $rn */ + +{ /* AArch64_FMAXNMV_VPZ_D, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMV_VPZ_H, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMV_VPZ_S, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMVv4i16v, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMVv4i32v, AArch64_INS_FMAXNMV: fmaxnmv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMv2f32, ARM64_INS_FMAXNM: fmaxnm.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMVv8i16v, AArch64_INS_FMAXNMV: fmaxnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNM_ZPmI_D, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNM_ZPmI_H, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNM_ZPmI_S, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNM_ZPmZ_D, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNM_ZPmZ_H, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNM_ZPmZ_S, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMv2f32, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMv2f64, ARM64_INS_FMAXNM: fmaxnm.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMv2f64, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXNMv4f32, ARM64_INS_FMAXNM: fmaxnm.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMv4f16, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXNMv4f32, AArch64_INS_FMAXNM: fmaxnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXPv2f32, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXNMv8f16, AArch64_INS_FMAXNM: fmaxnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXPv2f32, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXPv2f64, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMAXPv2f64, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXPv2i32p, ARM64_INS_FMAXP: fmaxp.2s $rd, $rn */ + +{ /* AArch64_FMAXPv2i16p, AArch64_INS_FMAXP: fmaxp */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXPv2i32p, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXPv2i64p, ARM64_INS_FMAXP: fmaxp.2d $rd, $rn */ + +{ /* AArch64_FMAXPv2i64p, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXPv4f32, ARM64_INS_FMAXP: fmaxp.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXPv4f16, AArch64_INS_FMAXP: fmaxp */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXPv4f32, AArch64_INS_FMAXP: fmaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXSrr, ARM64_INS_FMAX: fmax $rd, $rn, $rm */ + +{ /* AArch64_FMAXPv8f16, AArch64_INS_FMAXP: fmaxp */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXSrr, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXVv4i32v, ARM64_INS_FMAXV: fmaxv.4s $rd, $rn */ + +{ /* AArch64_FMAXV_VPZ_D, AArch64_INS_FMAXV: fmaxv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXV_VPZ_H, AArch64_INS_FMAXV: fmaxv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXV_VPZ_S, AArch64_INS_FMAXV: fmaxv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXVv4i16v, AArch64_INS_FMAXV: fmaxv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXVv4i32v, AArch64_INS_FMAXV: fmaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXv2f32, ARM64_INS_FMAX: fmax.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXVv8i16v, AArch64_INS_FMAXV: fmaxv */ + 0, + { 0 } +}, + +{ /* AArch64_FMAX_ZPmI_D, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAX_ZPmI_H, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAX_ZPmI_S, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAX_ZPmZ_D, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAX_ZPmZ_H, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAX_ZPmZ_S, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXv2f32, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXv2f64, ARM64_INS_FMAX: fmax.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMAXv2f64, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMAXv4f32, ARM64_INS_FMAX: fmax.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMAXv4f16, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMAXv4f32, AArch64_INS_FMAX: fmax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINDrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */ + +{ /* AArch64_FMAXv8f16, AArch64_INS_FMAX: fmax */ + 0, + { 0 } +}, + +{ /* AArch64_FMINDrr, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMDrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */ + +{ /* AArch64_FMINHrr, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMDrr, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMPv2f32, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMHrr, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMPv2f32, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMPv2f64, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMPv2f64, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMPv2i32p, ARM64_INS_FMINNMP: fminnmp.2s $rd, $rn */ + +{ /* AArch64_FMINNMPv2i16p, AArch64_INS_FMINNMP: fminnmp */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMPv2i32p, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMPv2i64p, ARM64_INS_FMINNMP: fminnmp.2d $rd, $rn */ + +{ /* AArch64_FMINNMPv2i64p, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMPv4f32, ARM64_INS_FMINNMP: fminnmp.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMPv4f16, AArch64_INS_FMINNMP: fminnmp */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMPv4f32, AArch64_INS_FMINNMP: fminnmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMSrr, ARM64_INS_FMINNM: fminnm $rd, $rn, $rm */ + +{ /* AArch64_FMINNMPv8f16, AArch64_INS_FMINNMP: fminnmp */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMSrr, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMVv4i32v, ARM64_INS_FMINNMV: fminnmv.4s $rd, $rn */ + +{ /* AArch64_FMINNMV_VPZ_D, AArch64_INS_FMINNMV: fminnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMV_VPZ_H, AArch64_INS_FMINNMV: fminnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMV_VPZ_S, AArch64_INS_FMINNMV: fminnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMVv4i16v, AArch64_INS_FMINNMV: fminnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMVv4i32v, AArch64_INS_FMINNMV: fminnmv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMv2f32, ARM64_INS_FMINNM: fminnm.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMVv8i16v, AArch64_INS_FMINNMV: fminnmv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNM_ZPmI_D, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNM_ZPmI_H, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNM_ZPmI_S, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNM_ZPmZ_D, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNM_ZPmZ_H, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNM_ZPmZ_S, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMv2f32, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMv2f64, ARM64_INS_FMINNM: fminnm.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMv2f64, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINNMv4f32, ARM64_INS_FMINNM: fminnm.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMv4f16, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINNMv4f32, AArch64_INS_FMINNM: fminnm */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINPv2f32, ARM64_INS_FMINP: fminp.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMINNMv8f16, AArch64_INS_FMINNM: fminnm */ + 0, + { 0 } +}, + +{ /* AArch64_FMINPv2f32, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINPv2f64, ARM64_INS_FMINP: fminp.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMINPv2f64, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINPv2i32p, ARM64_INS_FMINP: fminp.2s $rd, $rn */ + +{ /* AArch64_FMINPv2i16p, AArch64_INS_FMINP: fminp */ + 0, + { 0 } +}, + +{ /* AArch64_FMINPv2i32p, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMINPv2i64p, ARM64_INS_FMINP: fminp.2d $rd, $rn */ + +{ /* AArch64_FMINPv2i64p, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMINPv4f32, ARM64_INS_FMINP: fminp.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMINPv4f16, AArch64_INS_FMINP: fminp */ + 0, + { 0 } +}, + +{ /* AArch64_FMINPv4f32, AArch64_INS_FMINP: fminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINSrr, ARM64_INS_FMIN: fmin $rd, $rn, $rm */ + +{ /* AArch64_FMINPv8f16, AArch64_INS_FMINP: fminp */ + 0, + { 0 } +}, + +{ /* AArch64_FMINSrr, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINVv4i32v, ARM64_INS_FMINV: fminv.4s $rd, $rn */ + +{ /* AArch64_FMINV_VPZ_D, AArch64_INS_FMINV: fminv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINV_VPZ_H, AArch64_INS_FMINV: fminv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINV_VPZ_S, AArch64_INS_FMINV: fminv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINVv4i16v, AArch64_INS_FMINV: fminv */ + 0, + { 0 } +}, + +{ /* AArch64_FMINVv4i32v, AArch64_INS_FMINV: fminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMINv2f32, ARM64_INS_FMIN: fmin.2s $rd, $rn, $rm| */ + +{ /* AArch64_FMINVv8i16v, AArch64_INS_FMINV: fminv */ + 0, + { 0 } +}, + +{ /* AArch64_FMIN_ZPmI_D, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMIN_ZPmI_H, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMIN_ZPmI_S, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMIN_ZPmZ_D, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMIN_ZPmZ_H, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMIN_ZPmZ_S, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMINv2f32, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINv2f64, ARM64_INS_FMIN: fmin.2d $rd, $rn, $rm| */ + +{ /* AArch64_FMINv2f64, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMINv4f32, ARM64_INS_FMIN: fmin.4s $rd, $rn, $rm| */ + +{ /* AArch64_FMINv4f16, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMINv4f32, AArch64_INS_FMIN: fmin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLAv1i32_indexed, ARM64_INS_FMLA: fmla.s $rd, $rn, $rm$idx */ + +{ /* AArch64_FMINv8f16, AArch64_INS_FMIN: fmin */ + 0, + { 0 } +}, + +{ /* AArch64_FMLA_ZPmZZ_D, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLA_ZPmZZ_H, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLA_ZPmZZ_S, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLA_ZZZI_D, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLA_ZZZI_H, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLA_ZZZI_S, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLAv1i16_indexed, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLAv1i32_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLAv1i64_indexed, ARM64_INS_FMLA: fmla.d $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLAv1i64_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLAv2f32, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm */ + +{ /* AArch64_FMLAv2f32, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLAv2f64, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm */ + +{ /* AArch64_FMLAv2f64, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLAv2i32_indexed, ARM64_INS_FMLA: fmla.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLAv2i32_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLAv2i64_indexed, ARM64_INS_FMLA: fmla.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLAv2i64_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLAv4f32, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm */ + +{ /* AArch64_FMLAv4f16, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLAv4f32, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLAv4i32_indexed, ARM64_INS_FMLA: fmla.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLAv4i16_indexed, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLAv4i32_indexed, AArch64_INS_FMLA: fmla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLSv1i32_indexed, ARM64_INS_FMLS: fmls.s $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLAv8f16, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLAv8i16_indexed, AArch64_INS_FMLA: fmla */ + 0, + { 0 } +}, + +{ /* AArch64_FMLS_ZPmZZ_D, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLS_ZPmZZ_H, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLS_ZPmZZ_S, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLS_ZZZI_D, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLS_ZZZI_H, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLS_ZZZI_S, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLSv1i16_indexed, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLSv1i32_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLSv1i64_indexed, ARM64_INS_FMLS: fmls.d $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLSv1i64_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLSv2f32, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm */ + +{ /* AArch64_FMLSv2f32, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLSv2f64, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm */ + +{ /* AArch64_FMLSv2f64, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLSv2i32_indexed, ARM64_INS_FMLS: fmls.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLSv2i32_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLSv2i64_indexed, ARM64_INS_FMLS: fmls.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLSv2i64_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMLSv4f32, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm */ + +{ /* AArch64_FMLSv4f16, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLSv4f32, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMLSv4i32_indexed, ARM64_INS_FMLS: fmls.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_FMLSv4i16_indexed, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLSv4i32_indexed, AArch64_INS_FMLS: fmls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_FMOVDXHighr, ARM64_INS_FMOV: fmov.d $rd, $rn$idx */ + +{ /* AArch64_FMLSv8f16, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMLSv8i16_indexed, AArch64_INS_FMLS: fmls */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVDXHighr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMOVDXr, ARM64_INS_FMOV: fmov $rd, $rn */ + +{ /* AArch64_FMOVDXr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMOVDi, ARM64_INS_FMOV: fmov $rd, $imm */ + +{ /* AArch64_FMOVDi, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_FMOVDr, ARM64_INS_FMOV: fmov $rd, $rn */ + +{ /* AArch64_FMOVDr, AArch64_INS_FMOV: fmov */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_FMOVSWr, ARM64_INS_FMOV: fmov $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FMOVSi, ARM64_INS_FMOV: fmov $rd, $imm */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMOVSr, ARM64_INS_FMOV: fmov $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FMOVWSr, ARM64_INS_FMOV: fmov $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FMOVXDHighr, ARM64_INS_FMOV: fmov.d $rd$idx, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FMOVXDr, ARM64_INS_FMOV: fmov $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FMOVv2f32_ns, ARM64_INS_FMOV: fmov.2s $rd, $imm8 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } -}, -{ /* AArch64_FMOVv2f64_ns, ARM64_INS_FMOV: fmov.2d $rd, $imm8 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } -}, -{ /* AArch64_FMOVv4f32_ns, ARM64_INS_FMOV: fmov.4s $rd, $imm8 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } -}, -{ /* AArch64_FMSUBDrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMSUBSrrr, ARM64_INS_FMSUB: fmsub $rd, $rn, $rm, $ra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULDrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULSrr, ARM64_INS_FMUL: fmul $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULX32, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULX64, ARM64_INS_FMULX: fmulx $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULXv1i32_indexed, ARM64_INS_FMULX: fmulx.s $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULXv1i64_indexed, ARM64_INS_FMULX: fmulx.d $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULXv2f32, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULXv2f64, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULXv2i32_indexed, ARM64_INS_FMULX: fmulx.2s $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULXv2i64_indexed, ARM64_INS_FMULX: fmulx.2d $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULXv4f32, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULXv4i32_indexed, ARM64_INS_FMULX: fmulx.4s $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULv1i32_indexed, ARM64_INS_FMUL: fmul.s $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULv1i64_indexed, ARM64_INS_FMUL: fmul.d $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULv2f32, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULv2f64, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULv2i32_indexed, ARM64_INS_FMUL: fmul.2s $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULv2i64_indexed, ARM64_INS_FMUL: fmul.2d $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FMULv4f32, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FMULv4i32_indexed, ARM64_INS_FMUL: fmul.4s $rd, $rn, $rm$idx */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FNEGDr, ARM64_INS_FNEG: fneg $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FNEGSr, ARM64_INS_FNEG: fneg $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FNEGv2f32, ARM64_INS_FNEG: fneg.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FNEGv2f64, ARM64_INS_FNEG: fneg.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FNEGv4f32, ARM64_INS_FNEG: fneg.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FNMADDDrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FNMADDSrrr, ARM64_INS_FNMADD: fnmadd $rd, $rn, $rm, $ra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FNMSUBDrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FNMSUBSrrr, ARM64_INS_FNMSUB: fnmsub $rd, $rn, $rm, $ra */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_FNMULDrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FNMULSrr, ARM64_INS_FNMUL: fnmul $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPEv1i32, ARM64_INS_FRECPE: frecpe $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPEv1i64, ARM64_INS_FRECPE: frecpe $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPEv2f32, ARM64_INS_FRECPE: frecpe.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPEv2f64, ARM64_INS_FRECPE: frecpe.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPEv4f32, ARM64_INS_FRECPE: frecpe.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPS32, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPS64, ARM64_INS_FRECPS: frecps $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPSv2f32, ARM64_INS_FRECPS: frecps.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPSv2f64, ARM64_INS_FRECPS: frecps.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPSv4f32, ARM64_INS_FRECPS: frecps.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPXv1i32, ARM64_INS_FRECPX: frecpx $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRECPXv1i64, ARM64_INS_FRECPX: frecpx $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTADr, ARM64_INS_FRINTA: frinta $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTASr, ARM64_INS_FRINTA: frinta $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTAv2f32, ARM64_INS_FRINTA: frinta.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTAv2f64, ARM64_INS_FRINTA: frinta.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTAv4f32, ARM64_INS_FRINTA: frinta.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTIDr, ARM64_INS_FRINTI: frinti $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTISr, ARM64_INS_FRINTI: frinti $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTIv2f32, ARM64_INS_FRINTI: frinti.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTIv2f64, ARM64_INS_FRINTI: frinti.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTIv4f32, ARM64_INS_FRINTI: frinti.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTMDr, ARM64_INS_FRINTM: frintm $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTMSr, ARM64_INS_FRINTM: frintm $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTMv2f32, ARM64_INS_FRINTM: frintm.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTMv2f64, ARM64_INS_FRINTM: frintm.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTMv4f32, ARM64_INS_FRINTM: frintm.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTNDr, ARM64_INS_FRINTN: frintn $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTNSr, ARM64_INS_FRINTN: frintn $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTNv2f32, ARM64_INS_FRINTN: frintn.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTNv2f64, ARM64_INS_FRINTN: frintn.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTNv4f32, ARM64_INS_FRINTN: frintn.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTPDr, ARM64_INS_FRINTP: frintp $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTPSr, ARM64_INS_FRINTP: frintp $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTPv2f32, ARM64_INS_FRINTP: frintp.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTPv2f64, ARM64_INS_FRINTP: frintp.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTPv4f32, ARM64_INS_FRINTP: frintp.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTXDr, ARM64_INS_FRINTX: frintx $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTXSr, ARM64_INS_FRINTX: frintx $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTXv2f32, ARM64_INS_FRINTX: frintx.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTXv2f64, ARM64_INS_FRINTX: frintx.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTXv4f32, ARM64_INS_FRINTX: frintx.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTZDr, ARM64_INS_FRINTZ: frintz $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTZSr, ARM64_INS_FRINTZ: frintz $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTZv2f32, ARM64_INS_FRINTZ: frintz.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTZv2f64, ARM64_INS_FRINTZ: frintz.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRINTZv4f32, ARM64_INS_FRINTZ: frintz.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTEv1i32, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTEv1i64, ARM64_INS_FRSQRTE: frsqrte $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTEv2f32, ARM64_INS_FRSQRTE: frsqrte.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTEv2f64, ARM64_INS_FRSQRTE: frsqrte.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTEv4f32, ARM64_INS_FRSQRTE: frsqrte.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTS32, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTS64, ARM64_INS_FRSQRTS: frsqrts $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTSv2f32, ARM64_INS_FRSQRTS: frsqrts.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTSv2f64, ARM64_INS_FRSQRTS: frsqrts.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FRSQRTSv4f32, ARM64_INS_FRSQRTS: frsqrts.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FSQRTDr, ARM64_INS_FSQRT: fsqrt $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FSQRTSr, ARM64_INS_FSQRT: fsqrt $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FSQRTv2f32, ARM64_INS_FSQRT: fsqrt.2s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FSQRTv2f64, ARM64_INS_FSQRT: fsqrt.2d $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FSQRTv4f32, ARM64_INS_FSQRT: fsqrt.4s $rd, $rn */ - 0, - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* AArch64_FSUBDrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FSUBSrr, ARM64_INS_FSUB: fsub $rd, $rn, $rm */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FSUBv2f32, ARM64_INS_FSUB: fsub.2s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FSUBv2f64, ARM64_INS_FSUB: fsub.2d $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_FSUBv4f32, ARM64_INS_FSUB: fsub.4s $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_HINT, ARM64_INS_HINT: hint $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_HLT, ARM64_INS_HLT: hlt $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_HVC, ARM64_INS_HVC: hvc $imm */ - 0, - { CS_AC_READ, 0 } -}, -{ /* AArch64_INSvi16gpr, ARM64_INS_INS: ins.h $rd$idx, $rn */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_INSvi16lane, ARM64_INS_INS: ins.h $rd$idx, $rn$idx2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_INSvi32gpr, ARM64_INS_INS: ins.s $rd$idx, $rn */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_INSvi32lane, ARM64_INS_INS: ins.s $rd$idx, $rn$idx2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_INSvi64gpr, ARM64_INS_INS: ins.d $rd$idx, $rn */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_INSvi64lane, ARM64_INS_INS: ins.d $rd$idx, $rn$idx2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_INSvi8gpr, ARM64_INS_INS: ins.b $rd$idx, $rn */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_INSvi8lane, ARM64_INS_INS: ins.b $rd$idx, $rn$idx2 */ - 0, - { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } -}, -{ /* AArch64_ISB, ARM64_INS_ISB: isb $crm */ + +{ /* AArch64_FMOVHWr, AArch64_INS_FMOV: fmov */ 0, { 0 } }, -{ /* AArch64_LD1Fourv16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_FMOVHXr, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVHi, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVHr, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVSWr, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMOVSi, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMOVSr, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMOVWHr, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVWSr, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMOVXDHighr, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMOVXDr, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMOVXHr, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVv2f32_ns, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } +}, + +{ /* AArch64_FMOVv2f64_ns, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } +}, + +{ /* AArch64_FMOVv4f16_ns, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMOVv4f32_ns, AArch64_INS_FMOV: fmov */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ,0 } +}, + +{ /* AArch64_FMOVv8f16_ns, AArch64_INS_FMOV: fmov */ + 0, + { 0 } +}, + +{ /* AArch64_FMSB_ZPmZZ_D, AArch64_INS_FMSB: fmsb */ + 0, + { 0 } +}, + +{ /* AArch64_FMSB_ZPmZZ_H, AArch64_INS_FMSB: fmsb */ + 0, + { 0 } +}, + +{ /* AArch64_FMSB_ZPmZZ_S, AArch64_INS_FMSB: fmsb */ + 0, + { 0 } +}, + +{ /* AArch64_FMSUBDrrr, AArch64_INS_FMSUB: fmsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMSUBHrrr, AArch64_INS_FMSUB: fmsub */ + 0, + { 0 } +}, + +{ /* AArch64_FMSUBSrrr, AArch64_INS_FMSUB: fmsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULDrr, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULHrr, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMULSrr, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULX16, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULX32, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULX64, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULX_ZPmZ_D, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULX_ZPmZ_H, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULX_ZPmZ_S, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULXv1i16_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULXv1i32_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULXv1i64_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULXv2f32, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULXv2f64, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULXv2i32_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULXv2i64_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULXv4f16, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULXv4f32, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULXv4i16_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULXv4i32_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULXv8f16, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMULXv8i16_indexed, AArch64_INS_FMULX: fmulx */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZPmI_D, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZPmI_H, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZPmI_S, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZPmZ_D, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZPmZ_H, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZPmZ_S, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZZZI_D, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZZZI_H, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZZZI_S, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZZZ_D, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZZZ_H, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMUL_ZZZ_S, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMULv1i16_indexed, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMULv1i32_indexed, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULv1i64_indexed, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULv2f32, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULv2f64, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULv2i32_indexed, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULv2i64_indexed, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULv4f16, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMULv4f32, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FMULv4i16_indexed, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMULv4i32_indexed, AArch64_INS_FMUL: fmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FMULv8f16, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FMULv8i16_indexed, AArch64_INS_FMUL: fmul */ + 0, + { 0 } +}, + +{ /* AArch64_FNEGDr, AArch64_INS_FNEG: fneg */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FNEGHr, AArch64_INS_FNEG: fneg */ + 0, + { 0 } +}, + +{ /* AArch64_FNEGSr, AArch64_INS_FNEG: fneg */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FNEG_ZPmZ_D, AArch64_INS_FNEG: fneg */ + 0, + { 0 } +}, + +{ /* AArch64_FNEG_ZPmZ_H, AArch64_INS_FNEG: fneg */ + 0, + { 0 } +}, + +{ /* AArch64_FNEG_ZPmZ_S, AArch64_INS_FNEG: fneg */ + 0, + { 0 } +}, + +{ /* AArch64_FNEGv2f32, AArch64_INS_FNEG: fneg */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FNEGv2f64, AArch64_INS_FNEG: fneg */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FNEGv4f16, AArch64_INS_FNEG: fneg */ + 0, + { 0 } +}, + +{ /* AArch64_FNEGv4f32, AArch64_INS_FNEG: fneg */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FNEGv8f16, AArch64_INS_FNEG: fneg */ + 0, + { 0 } +}, + +{ /* AArch64_FNMADDDrrr, AArch64_INS_FNMADD: fnmadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FNMADDHrrr, AArch64_INS_FNMADD: fnmadd */ + 0, + { 0 } +}, + +{ /* AArch64_FNMADDSrrr, AArch64_INS_FNMADD: fnmadd */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FNMAD_ZPmZZ_D, AArch64_INS_FNMAD: fnmad */ + 0, + { 0 } +}, + +{ /* AArch64_FNMAD_ZPmZZ_H, AArch64_INS_FNMAD: fnmad */ + 0, + { 0 } +}, + +{ /* AArch64_FNMAD_ZPmZZ_S, AArch64_INS_FNMAD: fnmad */ + 0, + { 0 } +}, + +{ /* AArch64_FNMLA_ZPmZZ_D, AArch64_INS_FNMLA: fnmla */ + 0, + { 0 } +}, + +{ /* AArch64_FNMLA_ZPmZZ_H, AArch64_INS_FNMLA: fnmla */ + 0, + { 0 } +}, + +{ /* AArch64_FNMLA_ZPmZZ_S, AArch64_INS_FNMLA: fnmla */ + 0, + { 0 } +}, + +{ /* AArch64_FNMLS_ZPmZZ_D, AArch64_INS_FNMLS: fnmls */ + 0, + { 0 } +}, + +{ /* AArch64_FNMLS_ZPmZZ_H, AArch64_INS_FNMLS: fnmls */ + 0, + { 0 } +}, + +{ /* AArch64_FNMLS_ZPmZZ_S, AArch64_INS_FNMLS: fnmls */ + 0, + { 0 } +}, + +{ /* AArch64_FNMSB_ZPmZZ_D, AArch64_INS_FNMSB: fnmsb */ + 0, + { 0 } +}, + +{ /* AArch64_FNMSB_ZPmZZ_H, AArch64_INS_FNMSB: fnmsb */ + 0, + { 0 } +}, + +{ /* AArch64_FNMSB_ZPmZZ_S, AArch64_INS_FNMSB: fnmsb */ + 0, + { 0 } +}, + +{ /* AArch64_FNMSUBDrrr, AArch64_INS_FNMSUB: fnmsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FNMSUBHrrr, AArch64_INS_FNMSUB: fnmsub */ + 0, + { 0 } +}, + +{ /* AArch64_FNMSUBSrrr, AArch64_INS_FNMSUB: fnmsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_FNMULDrr, AArch64_INS_FNMUL: fnmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FNMULHrr, AArch64_INS_FNMUL: fnmul */ + 0, + { 0 } +}, + +{ /* AArch64_FNMULSrr, AArch64_INS_FNMUL: fnmul */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPE_ZZ_D, AArch64_INS_FRECPE: frecpe */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPE_ZZ_H, AArch64_INS_FRECPE: frecpe */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPE_ZZ_S, AArch64_INS_FRECPE: frecpe */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPEv1f16, AArch64_INS_FRECPE: frecpe */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPEv1i32, AArch64_INS_FRECPE: frecpe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPEv1i64, AArch64_INS_FRECPE: frecpe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPEv2f32, AArch64_INS_FRECPE: frecpe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPEv2f64, AArch64_INS_FRECPE: frecpe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPEv4f16, AArch64_INS_FRECPE: frecpe */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPEv4f32, AArch64_INS_FRECPE: frecpe */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPEv8f16, AArch64_INS_FRECPE: frecpe */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPS16, AArch64_INS_FRECPS: frecps */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPS32, AArch64_INS_FRECPS: frecps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPS64, AArch64_INS_FRECPS: frecps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPS_ZZZ_D, AArch64_INS_FRECPS: frecps */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPS_ZZZ_H, AArch64_INS_FRECPS: frecps */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPS_ZZZ_S, AArch64_INS_FRECPS: frecps */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPSv2f32, AArch64_INS_FRECPS: frecps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPSv2f64, AArch64_INS_FRECPS: frecps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPSv4f16, AArch64_INS_FRECPS: frecps */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPSv4f32, AArch64_INS_FRECPS: frecps */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPSv8f16, AArch64_INS_FRECPS: frecps */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPX_ZPmZ_D, AArch64_INS_FRECPX: frecpx */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPX_ZPmZ_H, AArch64_INS_FRECPX: frecpx */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPX_ZPmZ_S, AArch64_INS_FRECPX: frecpx */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPXv1f16, AArch64_INS_FRECPX: frecpx */ + 0, + { 0 } +}, + +{ /* AArch64_FRECPXv1i32, AArch64_INS_FRECPX: frecpx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRECPXv1i64, AArch64_INS_FRECPX: frecpx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTADr, AArch64_INS_FRINTA: frinta */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTAHr, AArch64_INS_FRINTA: frinta */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTASr, AArch64_INS_FRINTA: frinta */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTA_ZPmZ_D, AArch64_INS_FRINTA: frinta */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTA_ZPmZ_H, AArch64_INS_FRINTA: frinta */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTA_ZPmZ_S, AArch64_INS_FRINTA: frinta */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTAv2f32, AArch64_INS_FRINTA: frinta */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTAv2f64, AArch64_INS_FRINTA: frinta */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTAv4f16, AArch64_INS_FRINTA: frinta */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTAv4f32, AArch64_INS_FRINTA: frinta */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTAv8f16, AArch64_INS_FRINTA: frinta */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTIDr, AArch64_INS_FRINTI: frinti */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTIHr, AArch64_INS_FRINTI: frinti */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTISr, AArch64_INS_FRINTI: frinti */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTI_ZPmZ_D, AArch64_INS_FRINTI: frinti */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTI_ZPmZ_H, AArch64_INS_FRINTI: frinti */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTI_ZPmZ_S, AArch64_INS_FRINTI: frinti */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTIv2f32, AArch64_INS_FRINTI: frinti */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTIv2f64, AArch64_INS_FRINTI: frinti */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTIv4f16, AArch64_INS_FRINTI: frinti */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTIv4f32, AArch64_INS_FRINTI: frinti */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTIv8f16, AArch64_INS_FRINTI: frinti */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTMDr, AArch64_INS_FRINTM: frintm */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTMHr, AArch64_INS_FRINTM: frintm */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTMSr, AArch64_INS_FRINTM: frintm */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTM_ZPmZ_D, AArch64_INS_FRINTM: frintm */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTM_ZPmZ_H, AArch64_INS_FRINTM: frintm */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTM_ZPmZ_S, AArch64_INS_FRINTM: frintm */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTMv2f32, AArch64_INS_FRINTM: frintm */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTMv2f64, AArch64_INS_FRINTM: frintm */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTMv4f16, AArch64_INS_FRINTM: frintm */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTMv4f32, AArch64_INS_FRINTM: frintm */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTMv8f16, AArch64_INS_FRINTM: frintm */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTNDr, AArch64_INS_FRINTN: frintn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTNHr, AArch64_INS_FRINTN: frintn */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTNSr, AArch64_INS_FRINTN: frintn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTN_ZPmZ_D, AArch64_INS_FRINTN: frintn */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTN_ZPmZ_H, AArch64_INS_FRINTN: frintn */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTN_ZPmZ_S, AArch64_INS_FRINTN: frintn */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTNv2f32, AArch64_INS_FRINTN: frintn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTNv2f64, AArch64_INS_FRINTN: frintn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTNv4f16, AArch64_INS_FRINTN: frintn */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTNv4f32, AArch64_INS_FRINTN: frintn */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTNv8f16, AArch64_INS_FRINTN: frintn */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTPDr, AArch64_INS_FRINTP: frintp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTPHr, AArch64_INS_FRINTP: frintp */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTPSr, AArch64_INS_FRINTP: frintp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTP_ZPmZ_D, AArch64_INS_FRINTP: frintp */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTP_ZPmZ_H, AArch64_INS_FRINTP: frintp */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTP_ZPmZ_S, AArch64_INS_FRINTP: frintp */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTPv2f32, AArch64_INS_FRINTP: frintp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTPv2f64, AArch64_INS_FRINTP: frintp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTPv4f16, AArch64_INS_FRINTP: frintp */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTPv4f32, AArch64_INS_FRINTP: frintp */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTPv8f16, AArch64_INS_FRINTP: frintp */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTXDr, AArch64_INS_FRINTX: frintx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTXHr, AArch64_INS_FRINTX: frintx */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTXSr, AArch64_INS_FRINTX: frintx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTX_ZPmZ_D, AArch64_INS_FRINTX: frintx */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTX_ZPmZ_H, AArch64_INS_FRINTX: frintx */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTX_ZPmZ_S, AArch64_INS_FRINTX: frintx */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTXv2f32, AArch64_INS_FRINTX: frintx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTXv2f64, AArch64_INS_FRINTX: frintx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTXv4f16, AArch64_INS_FRINTX: frintx */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTXv4f32, AArch64_INS_FRINTX: frintx */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTXv8f16, AArch64_INS_FRINTX: frintx */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTZDr, AArch64_INS_FRINTZ: frintz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTZHr, AArch64_INS_FRINTZ: frintz */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTZSr, AArch64_INS_FRINTZ: frintz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTZ_ZPmZ_D, AArch64_INS_FRINTZ: frintz */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTZ_ZPmZ_H, AArch64_INS_FRINTZ: frintz */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTZ_ZPmZ_S, AArch64_INS_FRINTZ: frintz */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTZv2f32, AArch64_INS_FRINTZ: frintz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTZv2f64, AArch64_INS_FRINTZ: frintz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTZv4f16, AArch64_INS_FRINTZ: frintz */ + 0, + { 0 } +}, + +{ /* AArch64_FRINTZv4f32, AArch64_INS_FRINTZ: frintz */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRINTZv8f16, AArch64_INS_FRINTZ: frintz */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTE_ZZ_D, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTE_ZZ_H, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTE_ZZ_S, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTEv1f16, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTEv1i32, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTEv1i64, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTEv2f32, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTEv2f64, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTEv4f16, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTEv4f32, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTEv8f16, AArch64_INS_FRSQRTE: frsqrte */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTS16, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTS32, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTS64, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTS_ZZZ_D, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTS_ZZZ_H, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTS_ZZZ_S, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTSv2f32, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTSv2f64, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTSv4f16, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { 0 } +}, + +{ /* AArch64_FRSQRTSv4f32, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FRSQRTSv8f16, AArch64_INS_FRSQRTS: frsqrts */ + 0, + { 0 } +}, + +{ /* AArch64_FSCALE_ZPmZ_D, AArch64_INS_FSCALE: fscale */ + 0, + { 0 } +}, + +{ /* AArch64_FSCALE_ZPmZ_H, AArch64_INS_FSCALE: fscale */ + 0, + { 0 } +}, + +{ /* AArch64_FSCALE_ZPmZ_S, AArch64_INS_FSCALE: fscale */ + 0, + { 0 } +}, + +{ /* AArch64_FSQRTDr, AArch64_INS_FSQRT: fsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSQRTHr, AArch64_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* AArch64_FSQRTSr, AArch64_INS_FSQRT: fsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSQRT_ZPmZ_D, AArch64_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* AArch64_FSQRT_ZPmZ_H, AArch64_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* AArch64_FSQRT_ZPmZ_S, AArch64_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* AArch64_FSQRTv2f32, AArch64_INS_FSQRT: fsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSQRTv2f64, AArch64_INS_FSQRT: fsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSQRTv4f16, AArch64_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* AArch64_FSQRTv4f32, AArch64_INS_FSQRT: fsqrt */ + 0, + { CS_AC_WRITE, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSQRTv8f16, AArch64_INS_FSQRT: fsqrt */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBDrr, AArch64_INS_FSUB: fsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSUBHrr, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBR_ZPmI_D, AArch64_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBR_ZPmI_H, AArch64_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBR_ZPmI_S, AArch64_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBR_ZPmZ_D, AArch64_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBR_ZPmZ_H, AArch64_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBR_ZPmZ_S, AArch64_INS_FSUBR: fsubr */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBSrr, AArch64_INS_FSUB: fsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSUB_ZPmI_D, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZPmI_H, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZPmI_S, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZPmZ_D, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZPmZ_H, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZPmZ_S, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZZZ_D, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZZZ_H, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUB_ZZZ_S, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBv2f32, AArch64_INS_FSUB: fsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSUBv2f64, AArch64_INS_FSUB: fsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSUBv4f16, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FSUBv4f32, AArch64_INS_FSUB: fsub */ + 0, + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_FSUBv8f16, AArch64_INS_FSUB: fsub */ + 0, + { 0 } +}, + +{ /* AArch64_FTMAD_ZZI_D, AArch64_INS_FTMAD: ftmad */ + 0, + { 0 } +}, + +{ /* AArch64_FTMAD_ZZI_H, AArch64_INS_FTMAD: ftmad */ + 0, + { 0 } +}, + +{ /* AArch64_FTMAD_ZZI_S, AArch64_INS_FTMAD: ftmad */ + 0, + { 0 } +}, + +{ /* AArch64_FTSMUL_ZZZ_D, AArch64_INS_FTSMUL: ftsmul */ + 0, + { 0 } +}, + +{ /* AArch64_FTSMUL_ZZZ_H, AArch64_INS_FTSMUL: ftsmul */ + 0, + { 0 } +}, + +{ /* AArch64_FTSMUL_ZZZ_S, AArch64_INS_FTSMUL: ftsmul */ + 0, + { 0 } +}, + +{ /* AArch64_FTSSEL_ZZZ_D, AArch64_INS_FTSSEL: ftssel */ + 0, + { 0 } +}, + +{ /* AArch64_FTSSEL_ZZZ_H, AArch64_INS_FTSSEL: ftssel */ + 0, + { 0 } +}, + +{ /* AArch64_FTSSEL_ZZZ_S, AArch64_INS_FTSSEL: ftssel */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_D_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_D_SXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_D_UXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_S_SXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1B_S_UXTW_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_SCALED_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_SXTW_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_SXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_UXTW_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1D_UXTW_SCALED_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_SXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_UXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_D_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_S_SXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_S_SXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_S_UXTW_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1H_S_UXTW_SCALED_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_D_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_D_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_D_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_S_SXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SB_S_UXTW_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_D_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_S_SXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_S_SXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_S_UXTW_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SH_S_UXTW_SCALED_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_SXTW_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_SXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_UXTW_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1SW_D_UXTW_SCALED_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_SXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_UXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_D_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_SXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_SXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_UXTW_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLD1W_UXTW_SCALED_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_D_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_D_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_D_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_S_IMM_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_S_SXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1B_S_UXTW_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_IMM_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_SXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_SXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_UXTW_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1D_UXTW_SCALED_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_S_IMM_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_S_SXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_S_UXTW_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1H_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_D_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_D_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_D_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_S_IMM_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_S_SXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SB_S_UXTW_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_S_IMM_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_S_SXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_S_SXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_S_UXTW_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SH_S_UXTW_SCALED_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_IMM_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_SXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_UXTW_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1SW_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_D_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_IMM_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_SXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_SXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_UXTW_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_GLDFF1W_UXTW_SCALED_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_HINT, AArch64_INS_CSDB: csdb */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_HLT, AArch64_INS_HLT: hlt */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_HVC, AArch64_INS_HVC: hvc */ + 0, + { CS_AC_READ, 0 } +}, + +{ /* AArch64_INCB_XPiI, AArch64_INS_INCB: incb */ + 0, + { 0 } +}, + +{ /* AArch64_INCD_XPiI, AArch64_INS_INCD: incd */ + 0, + { 0 } +}, + +{ /* AArch64_INCD_ZPiI, AArch64_INS_INCD: incd */ + 0, + { 0 } +}, + +{ /* AArch64_INCH_XPiI, AArch64_INS_INCH: inch */ + 0, + { 0 } +}, + +{ /* AArch64_INCH_ZPiI, AArch64_INS_INCH: inch */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_XP_B, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_XP_D, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_XP_H, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_XP_S, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_ZP_D, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_ZP_H, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCP_ZP_S, AArch64_INS_INCP: incp */ + 0, + { 0 } +}, + +{ /* AArch64_INCW_XPiI, AArch64_INS_INCW: incw */ + 0, + { 0 } +}, + +{ /* AArch64_INCW_ZPiI, AArch64_INS_INCW: incw */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_II_B, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_II_D, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_II_H, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_II_S, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_IR_B, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_IR_D, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_IR_H, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_IR_S, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RI_B, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RI_D, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RI_H, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RI_S, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RR_B, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RR_D, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RR_H, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INDEX_RR_S, AArch64_INS_INDEX: index */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZR_B, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZR_D, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZR_H, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZR_S, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZV_B, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZV_D, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZV_H, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSR_ZV_S, AArch64_INS_INSR: insr */ + 0, + { 0 } +}, + +{ /* AArch64_INSvi16gpr, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_INSvi16lane, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_INSvi32gpr, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_INSvi32lane, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_INSvi64gpr, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_INSvi64lane, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_INSvi8gpr, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_INSvi8lane, AArch64_INS_INS: ins */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } +}, + +{ /* AArch64_ISB, AArch64_INS_ISB: isb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_RPZ_B, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_RPZ_D, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_RPZ_H, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_RPZ_S, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_VPZ_B, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_VPZ_D, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_VPZ_H, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTA_VPZ_S, AArch64_INS_LASTA: lasta */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_RPZ_B, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_RPZ_D, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_RPZ_H, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_RPZ_S, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_VPZ_B, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_VPZ_D, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_VPZ_H, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LASTB_VPZ_S, AArch64_INS_LASTB: lastb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_D, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_D_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_H, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_H_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_S, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1B_S_IMM_REAL, AArch64_INS_LD1B: ld1b */ + 0, + { 0 } +}, + +{ /* AArch64_LD1D, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_LD1D_IMM_REAL, AArch64_INS_LD1D: ld1d */ + 0, + { 0 } +}, + +{ /* AArch64_LD1Fourv16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Fourv8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Fourv8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Fourv8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1H, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_LD1H_D, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_LD1H_D_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_LD1H_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_LD1H_S, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_LD1H_S_IMM_REAL, AArch64_INS_LD1H: ld1h */ + 0, + { 0 } +}, + +{ /* AArch64_LD1Onev16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD1Onev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Onev8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Onev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Onev8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv16b, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1RB_D_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RB_H_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RB_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RB_S_IMM, AArch64_INS_LD1RB: ld1rb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RD_IMM, AArch64_INS_LD1RD: ld1rd */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RH_D_IMM, AArch64_INS_LD1RH: ld1rh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RH_IMM, AArch64_INS_LD1RH: ld1rh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RH_S_IMM, AArch64_INS_LD1RH: ld1rh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_B, AArch64_INS_LD1RQB: ld1rqb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_B_IMM, AArch64_INS_LD1RQB: ld1rqb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_D, AArch64_INS_LD1RQD: ld1rqd */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_D_IMM, AArch64_INS_LD1RQD: ld1rqd */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_H, AArch64_INS_LD1RQH: ld1rqh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_H_IMM, AArch64_INS_LD1RQH: ld1rqh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_W, AArch64_INS_LD1RQW: ld1rqw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RQ_W_IMM, AArch64_INS_LD1RQW: ld1rqw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RSB_D_IMM, AArch64_INS_LD1RSB: ld1rsb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RSB_H_IMM, AArch64_INS_LD1RSB: ld1rsb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RSB_S_IMM, AArch64_INS_LD1RSB: ld1rsb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RSH_D_IMM, AArch64_INS_LD1RSH: ld1rsh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RSH_S_IMM, AArch64_INS_LD1RSH: ld1rsh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RSW_IMM, AArch64_INS_LD1RSW: ld1rsw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RW_D_IMM, AArch64_INS_LD1RW: ld1rw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1RW_IMM, AArch64_INS_LD1RW: ld1rw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1Rv16b, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv16b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv16b_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv1d, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv1d, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv1d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv1d_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv2d, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv2d, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv2d_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv2d_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv2s, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv2s, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv2s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv2s_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv4h, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv4h, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv4h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv4h_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv4s, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv4s, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv4s_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv4s_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv8b, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv8b, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv8b_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv8b_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv8h, ARM64_INS_LD1R: ld1r $vt, [$rn] */ + +{ /* AArch64_LD1Rv8h, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Rv8h_POST, ARM64_INS_LD1R: ld1r $vt, [$rn], $xm */ + +{ /* AArch64_LD1Rv8h_POST, AArch64_INS_LD1R: ld1r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1SB_D, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SB_D_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SB_H, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SB_H_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SB_S, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SB_S_IMM_REAL, AArch64_INS_LD1SB: ld1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SH_D, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SH_D_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SH_S, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SH_S_IMM_REAL, AArch64_INS_LD1SH: ld1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SW_D, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1SW_D_IMM_REAL, AArch64_INS_LD1SW: ld1sw */ + 0, + { 0 } +}, + +{ /* AArch64_LD1Threev16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Threev8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Threev8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Threev8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov16b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov16b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov16b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov16b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov1d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov1d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov1d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov1d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov2d, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov2d, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov2d_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov2d_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov2s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov2s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov2s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov2s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov4h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov4h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov4h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov4h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov4s, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov4s, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov4s_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov4s_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov8b, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov8b, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov8b_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov8b_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov8h, ARM64_INS_LD1: ld1 $vt, [$rn] */ + +{ /* AArch64_LD1Twov8h, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1Twov8h_POST, ARM64_INS_LD1: ld1 $vt, [$rn], $xm */ + +{ /* AArch64_LD1Twov8h_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1i16, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + +{ /* AArch64_LD1W, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_LD1W_D, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_LD1W_D_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_LD1W_IMM_REAL, AArch64_INS_LD1W: ld1w */ + 0, + { 0 } +}, + +{ /* AArch64_LD1i16, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1i16_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD1i16_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1i32, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + +{ /* AArch64_LD1i32, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1i32_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD1i32_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1i64, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + +{ /* AArch64_LD1i64, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1i64_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD1i64_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD1i8, ARM64_INS_LD1: ld1 $vt$idx, [$rn] */ + +{ /* AArch64_LD1i8, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD1i8_POST, ARM64_INS_LD1: ld1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD1i8_POST, AArch64_INS_LD1: ld1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv16b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2B, AArch64_INS_LD2B: ld2b */ + 0, + { 0 } +}, + +{ /* AArch64_LD2B_IMM, AArch64_INS_LD2B: ld2b */ + 0, + { 0 } +}, + +{ /* AArch64_LD2D, AArch64_INS_LD2D: ld2d */ + 0, + { 0 } +}, + +{ /* AArch64_LD2D_IMM, AArch64_INS_LD2D: ld2d */ + 0, + { 0 } +}, + +{ /* AArch64_LD2H, AArch64_INS_LD2H: ld2h */ + 0, + { 0 } +}, + +{ /* AArch64_LD2H_IMM, AArch64_INS_LD2H: ld2h */ + 0, + { 0 } +}, + +{ /* AArch64_LD2Rv16b, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv16b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv16b_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv1d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv1d, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv1d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv1d_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv2d, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv2d, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv2d_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv2d_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv2s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv2s, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv2s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv2s_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv4h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv4h, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv4h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv4h_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv4s, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv4s, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv4s_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv4s_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv8b, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv8b, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv8b_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv8b_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv8h, ARM64_INS_LD2R: ld2r $vt, [$rn] */ + +{ /* AArch64_LD2Rv8h, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD2Rv8h_POST, ARM64_INS_LD2R: ld2r $vt, [$rn], $xm */ + +{ /* AArch64_LD2Rv8h_POST, AArch64_INS_LD2R: ld2r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD2Twov16b, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov16b, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov16b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov16b_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov2d, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov2d, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov2d_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov2d_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov2s, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov2s, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov2s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov2s_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov4h, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov4h, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov4h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov4h_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov4s, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov4s, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov4s_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov4s_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov8b, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov8b, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov8b_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov8b_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov8h, ARM64_INS_LD2: ld2 $vt, [$rn] */ + +{ /* AArch64_LD2Twov8h, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2Twov8h_POST, ARM64_INS_LD2: ld2 $vt, [$rn], $xm */ + +{ /* AArch64_LD2Twov8h_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2i16, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + +{ /* AArch64_LD2W, AArch64_INS_LD2W: ld2w */ + 0, + { 0 } +}, + +{ /* AArch64_LD2W_IMM, AArch64_INS_LD2W: ld2w */ + 0, + { 0 } +}, + +{ /* AArch64_LD2i16, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2i16_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD2i16_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2i32, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + +{ /* AArch64_LD2i32, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2i32_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD2i32_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2i64, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + +{ /* AArch64_LD2i64, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2i64_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD2i64_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD2i8, ARM64_INS_LD2: ld2 $vt$idx, [$rn] */ + +{ /* AArch64_LD2i8, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0} }, -{ /* AArch64_LD2i8_POST, ARM64_INS_LD2: ld2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD2i8_POST, AArch64_INS_LD2: ld2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LD3Rv16b, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3B, AArch64_INS_LD3B: ld3b */ + 0, + { 0 } +}, + +{ /* AArch64_LD3B_IMM, AArch64_INS_LD3B: ld3b */ + 0, + { 0 } +}, + +{ /* AArch64_LD3D, AArch64_INS_LD3D: ld3d */ + 0, + { 0 } +}, + +{ /* AArch64_LD3D_IMM, AArch64_INS_LD3D: ld3d */ + 0, + { 0 } +}, + +{ /* AArch64_LD3H, AArch64_INS_LD3H: ld3h */ + 0, + { 0 } +}, + +{ /* AArch64_LD3H_IMM, AArch64_INS_LD3H: ld3h */ + 0, + { 0 } +}, + +{ /* AArch64_LD3Rv16b, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv16b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv16b_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv1d, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv1d, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv1d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv1d_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv2d, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv2d, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv2d_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv2d_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv2s, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv2s, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv2s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv2s_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv4h, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv4h, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv4h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv4h_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv4s, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv4s, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv4s_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv4s_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv8b, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv8b, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv8b_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv8b_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv8h, ARM64_INS_LD3R: ld3r $vt, [$rn] */ + +{ /* AArch64_LD3Rv8h, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Rv8h_POST, ARM64_INS_LD3R: ld3r $vt, [$rn], $xm */ + +{ /* AArch64_LD3Rv8h_POST, AArch64_INS_LD3R: ld3r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev16b, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev16b, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev16b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev16b_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev2d, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev2d, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev2d_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev2d_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev2s, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev2s, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev2s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev2s_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev4h, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev4h, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev4h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev4h_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev4s, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev4s, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev4s_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev4s_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev8b, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev8b, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev8b_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev8b_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev8h, ARM64_INS_LD3: ld3 $vt, [$rn] */ + +{ /* AArch64_LD3Threev8h, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3Threev8h_POST, ARM64_INS_LD3: ld3 $vt, [$rn], $xm */ + +{ /* AArch64_LD3Threev8h_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD3i16, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + +{ /* AArch64_LD3W, AArch64_INS_LD3W: ld3w */ + 0, + { 0 } +}, + +{ /* AArch64_LD3W_IMM, AArch64_INS_LD3W: ld3w */ + 0, + { 0 } +}, + +{ /* AArch64_LD3i16, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3i16_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD3i16_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD3i32, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + +{ /* AArch64_LD3i32, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3i32_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD3i32_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD3i64, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + +{ /* AArch64_LD3i64, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3i64_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD3i64_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD3i8, ARM64_INS_LD3: ld3 $vt$idx, [$rn] */ + +{ /* AArch64_LD3i8, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD3i8_POST, ARM64_INS_LD3: ld3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD3i8_POST, AArch64_INS_LD3: ld3 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD4Fourv16b, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4B, AArch64_INS_LD4B: ld4b */ + 0, + { 0 } +}, + +{ /* AArch64_LD4B_IMM, AArch64_INS_LD4B: ld4b */ + 0, + { 0 } +}, + +{ /* AArch64_LD4D, AArch64_INS_LD4D: ld4d */ + 0, + { 0 } +}, + +{ /* AArch64_LD4D_IMM, AArch64_INS_LD4D: ld4d */ + 0, + { 0 } +}, + +{ /* AArch64_LD4Fourv16b, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv16b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv16b_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv2d, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4Fourv2d, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv2d_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv2d_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv2s, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4Fourv2s, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv2s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv2s_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv4h, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4Fourv4h, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv4h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv4h_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv4s, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4Fourv4s, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv4s_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv4s_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv8b, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4Fourv8b, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv8b_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv8b_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv8h, ARM64_INS_LD4: ld4 $vt, [$rn] */ + +{ /* AArch64_LD4Fourv8h, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Fourv8h_POST, ARM64_INS_LD4: ld4 $vt, [$rn], $xm */ + +{ /* AArch64_LD4Fourv8h_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv16b, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4H, AArch64_INS_LD4H: ld4h */ + 0, + { 0 } +}, + +{ /* AArch64_LD4H_IMM, AArch64_INS_LD4H: ld4h */ + 0, + { 0 } +}, + +{ /* AArch64_LD4Rv16b, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv16b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv16b_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv1d, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv1d, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv1d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv1d_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv2d, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv2d, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv2d_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv2d_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv2s, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv2s, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv2s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv2s_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv4h, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv4h, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv4h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv4h_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv4s, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv4s, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv4s_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv4s_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv8b, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv8b, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv8b_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv8b_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv8h, ARM64_INS_LD4R: ld4r $vt, [$rn] */ + +{ /* AArch64_LD4Rv8h, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4Rv8h_POST, ARM64_INS_LD4R: ld4r $vt, [$rn], $xm */ + +{ /* AArch64_LD4Rv8h_POST, AArch64_INS_LD4R: ld4r */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LD4i16, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + +{ /* AArch64_LD4W, AArch64_INS_LD4W: ld4w */ + 0, + { 0 } +}, + +{ /* AArch64_LD4W_IMM, AArch64_INS_LD4W: ld4w */ + 0, + { 0 } +}, + +{ /* AArch64_LD4i16, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4i16_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD4i16_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD4i32, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + +{ /* AArch64_LD4i32, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4i32_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD4i32_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD4i64, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + +{ /* AArch64_LD4i64, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4i64_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD4i64_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LD4i8, ARM64_INS_LD4: ld4 $vt$idx, [$rn] */ + +{ /* AArch64_LD4i8, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_LD4i8_POST, ARM64_INS_LD4: ld4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_LD4i8_POST, AArch64_INS_LD4: ld4 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDARB, ARM64_INS_LDARB: ldarb $rt, [$rn] */ + +{ /* AArch64_LDADDAB, AArch64_INS_LDADDAB: ldaddab */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDAH, AArch64_INS_LDADDAH: ldaddah */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDALB, AArch64_INS_LDADDALB: ldaddalb */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDALH, AArch64_INS_LDADDALH: ldaddalh */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDALW, AArch64_INS_LDADDAL: ldaddal */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDALX, AArch64_INS_LDADDAL: ldaddal */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDAW, AArch64_INS_LDADDA: ldadda */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDAX, AArch64_INS_LDADDA: ldadda */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDB, AArch64_INS_LDADDB: ldaddb */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDH, AArch64_INS_LDADDH: ldaddh */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDLB, AArch64_INS_LDADDLB: ldaddlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDLH, AArch64_INS_LDADDLH: ldaddlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDLW, AArch64_INS_LDADDL: ldaddl */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDLX, AArch64_INS_LDADDL: ldaddl */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDW, AArch64_INS_LDADD: ldadd */ + 0, + { 0 } +}, + +{ /* AArch64_LDADDX, AArch64_INS_LDADD: ldadd */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPRB, AArch64_INS_LDAPRB: ldaprb */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPRH, AArch64_INS_LDAPRH: ldaprh */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPRW, AArch64_INS_LDAPR: ldapr */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPRX, AArch64_INS_LDAPR: ldapr */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURBi, AArch64_INS_LDAPURB: ldapurb */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURHi, AArch64_INS_LDAPURH: ldapurh */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURSBWi, AArch64_INS_LDAPURSB: ldapursb */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURSBXi, AArch64_INS_LDAPURSB: ldapursb */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURSHWi, AArch64_INS_LDAPURSH: ldapursh */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURSHXi, AArch64_INS_LDAPURSH: ldapursh */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURSWi, AArch64_INS_LDAPURSW: ldapursw */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURXi, AArch64_INS_LDAPUR: ldapur */ + 0, + { 0 } +}, + +{ /* AArch64_LDAPURi, AArch64_INS_LDAPUR: ldapur */ + 0, + { 0 } +}, + +{ /* AArch64_LDARB, AArch64_INS_LDARB: ldarb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDARH, ARM64_INS_LDARH: ldarh $rt, [$rn] */ + +{ /* AArch64_LDARH, AArch64_INS_LDARH: ldarh */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDARW, ARM64_INS_LDAR: ldar $rt, [$rn] */ + +{ /* AArch64_LDARW, AArch64_INS_LDAR: ldar */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDARX, ARM64_INS_LDAR: ldar $rt, [$rn] */ + +{ /* AArch64_LDARX, AArch64_INS_LDAR: ldar */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDAXPW, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */ + +{ /* AArch64_LDAXPW, AArch64_INS_LDAXP: ldaxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDAXPX, ARM64_INS_LDAXP: ldaxp $rt, $rt2, [$rn] */ + +{ /* AArch64_LDAXPX, AArch64_INS_LDAXP: ldaxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDAXRB, ARM64_INS_LDAXRB: ldaxrb $rt, [$rn] */ + +{ /* AArch64_LDAXRB, AArch64_INS_LDAXRB: ldaxrb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDAXRH, ARM64_INS_LDAXRH: ldaxrh $rt, [$rn] */ + +{ /* AArch64_LDAXRH, AArch64_INS_LDAXRH: ldaxrh */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDAXRW, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */ + +{ /* AArch64_LDAXRW, AArch64_INS_LDAXR: ldaxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDAXRX, ARM64_INS_LDAXR: ldaxr $rt, [$rn] */ + +{ /* AArch64_LDAXRX, AArch64_INS_LDAXR: ldaxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDNPDi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDCLRAB, AArch64_INS_LDCLRAB: ldclrab */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRAH, AArch64_INS_LDCLRAH: ldclrah */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRALB, AArch64_INS_LDCLRALB: ldclralb */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRALH, AArch64_INS_LDCLRALH: ldclralh */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRALW, AArch64_INS_LDCLRAL: ldclral */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRALX, AArch64_INS_LDCLRAL: ldclral */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRAW, AArch64_INS_LDCLRA: ldclra */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRAX, AArch64_INS_LDCLRA: ldclra */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRB, AArch64_INS_LDCLRB: ldclrb */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRH, AArch64_INS_LDCLRH: ldclrh */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRLB, AArch64_INS_LDCLRLB: ldclrlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRLH, AArch64_INS_LDCLRLH: ldclrlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRLW, AArch64_INS_LDCLRL: ldclrl */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRLX, AArch64_INS_LDCLRL: ldclrl */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRW, AArch64_INS_LDCLR: ldclr */ + 0, + { 0 } +}, + +{ /* AArch64_LDCLRX, AArch64_INS_LDCLR: ldclr */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORAB, AArch64_INS_LDEORAB: ldeorab */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORAH, AArch64_INS_LDEORAH: ldeorah */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORALB, AArch64_INS_LDEORALB: ldeoralb */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORALH, AArch64_INS_LDEORALH: ldeoralh */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORALW, AArch64_INS_LDEORAL: ldeoral */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORALX, AArch64_INS_LDEORAL: ldeoral */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORAW, AArch64_INS_LDEORA: ldeora */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORAX, AArch64_INS_LDEORA: ldeora */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORB, AArch64_INS_LDEORB: ldeorb */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORH, AArch64_INS_LDEORH: ldeorh */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORLB, AArch64_INS_LDEORLB: ldeorlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORLH, AArch64_INS_LDEORLH: ldeorlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORLW, AArch64_INS_LDEORL: ldeorl */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORLX, AArch64_INS_LDEORL: ldeorl */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORW, AArch64_INS_LDEOR: ldeor */ + 0, + { 0 } +}, + +{ /* AArch64_LDEORX, AArch64_INS_LDEOR: ldeor */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1B_D_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1B_H_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1B_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1B_S_REAL, AArch64_INS_LDFF1B: ldff1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1D_REAL, AArch64_INS_LDFF1D: ldff1d */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1H_D_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1H_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1H_S_REAL, AArch64_INS_LDFF1H: ldff1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1SB_D_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1SB_H_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1SB_S_REAL, AArch64_INS_LDFF1SB: ldff1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1SH_D_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1SH_S_REAL, AArch64_INS_LDFF1SH: ldff1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1SW_D_REAL, AArch64_INS_LDFF1SW: ldff1sw */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1W_D_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_LDFF1W_REAL, AArch64_INS_LDFF1W: ldff1w */ + 0, + { 0 } +}, + +{ /* AArch64_LDLARB, AArch64_INS_LDLARB: ldlarb */ + 0, + { 0 } +}, + +{ /* AArch64_LDLARH, AArch64_INS_LDLARH: ldlarh */ + 0, + { 0 } +}, + +{ /* AArch64_LDLARW, AArch64_INS_LDLAR: ldlar */ + 0, + { 0 } +}, + +{ /* AArch64_LDLARX, AArch64_INS_LDLAR: ldlar */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1B_D_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1B_H_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1B_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1B_S_IMM_REAL, AArch64_INS_LDNF1B: ldnf1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1D_IMM_REAL, AArch64_INS_LDNF1D: ldnf1d */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1H_D_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1H_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1H_S_IMM_REAL, AArch64_INS_LDNF1H: ldnf1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1SB_D_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1SB_H_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1SB_S_IMM_REAL, AArch64_INS_LDNF1SB: ldnf1sb */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1SH_D_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1SH_S_IMM_REAL, AArch64_INS_LDNF1SH: ldnf1sh */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1SW_D_IMM_REAL, AArch64_INS_LDNF1SW: ldnf1sw */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1W_D_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ + 0, + { 0 } +}, + +{ /* AArch64_LDNF1W_IMM_REAL, AArch64_INS_LDNF1W: ldnf1w */ + 0, + { 0 } +}, + +{ /* AArch64_LDNPDi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDNPQi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDNPQi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDNPSi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDNPSi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDNPWi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDNPWi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDNPXi, ARM64_INS_LDNP: ldnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDNPXi, AArch64_INS_LDNP: ldnp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPDi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDNT1B_ZRI, AArch64_INS_LDNT1B: ldnt1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1B_ZRR, AArch64_INS_LDNT1B: ldnt1b */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1D_ZRI, AArch64_INS_LDNT1D: ldnt1d */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1D_ZRR, AArch64_INS_LDNT1D: ldnt1d */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1H_ZRI, AArch64_INS_LDNT1H: ldnt1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1H_ZRR, AArch64_INS_LDNT1H: ldnt1h */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1W_ZRI, AArch64_INS_LDNT1W: ldnt1w */ + 0, + { 0 } +}, + +{ /* AArch64_LDNT1W_ZRR, AArch64_INS_LDNT1W: ldnt1w */ + 0, + { 0 } +}, + +{ /* AArch64_LDPDi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPDpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_LDPDpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPDpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_LDPDpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPQi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDPQi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPQpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_LDPQpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPQpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_LDPQpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPSWi, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDPSWi, AArch64_INS_LDPSW: ldpsw */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPSWpost, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_LDPSWpost, AArch64_INS_LDPSW: ldpsw */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPSWpre, ARM64_INS_LDPSW: ldpsw $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_LDPSWpre, AArch64_INS_LDPSW: ldpsw */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPSi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDPSi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPSpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_LDPSpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPSpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_LDPSpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPWi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDPWi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPWpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_LDPWpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPWpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_LDPWpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPXi, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_LDPXi, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPXpost, ARM64_INS_LDP: ldp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_LDPXpost, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDPXpre, ARM64_INS_LDP: ldp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_LDPXpre, AArch64_INS_LDP: ldp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRBBpost, ARM64_INS_LDRB: ldrb $rt, [$rn], $offset */ + +{ /* AArch64_LDRAAindexed, AArch64_INS_LDRAA: ldraa */ + 0, + { 0 } +}, + +{ /* AArch64_LDRAAwriteback, AArch64_INS_LDRAA: ldraa */ + 0, + { 0 } +}, + +{ /* AArch64_LDRABindexed, AArch64_INS_LDRAB: ldrab */ + 0, + { 0 } +}, + +{ /* AArch64_LDRABwriteback, AArch64_INS_LDRAB: ldrab */ + 0, + { 0 } +}, + +{ /* AArch64_LDRBBpost, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRBBpre, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRBBpre, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRBBroW, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRBBroW, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRBBroX, ARM64_INS_LDRB: ldrb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRBBroX, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRBBui, ARM64_INS_LDRB: ldrb $rt, [$rn, $offset] */ + +{ /* AArch64_LDRBBui, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRBpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRBpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRBpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRBpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRBroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRBroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRBroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRBroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRBui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRBui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRDl, ARM64_INS_LDR: ldr $rt, $label */ + +{ /* AArch64_LDRDl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDRDpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRDpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRDpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRDpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRDroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRDroW, AArch64_INS_LDR: ldr */ 00, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRDroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRDroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRDui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRDui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHHpost, ARM64_INS_LDRH: ldrh $rt, [$rn], $offset */ + +{ /* AArch64_LDRHHpost, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHHpre, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRHHpre, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHHroW, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRHHroW, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHHroX, ARM64_INS_LDRH: ldrh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRHHroX, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHHui, ARM64_INS_LDRH: ldrh $rt, [$rn, $offset] */ + +{ /* AArch64_LDRHHui, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRHpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRHpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRHroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRHroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRHroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRHroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRHui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRHui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRQl, ARM64_INS_LDR: ldr $rt, $label */ + +{ /* AArch64_LDRQl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDRQpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRQpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRQpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRQpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRQroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRQroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRQroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRQroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRQui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRQui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSBWpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */ + +{ /* AArch64_LDRSBWpost, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSBWpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRSBWpre, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSBWroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSBWroW, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSBWroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSBWroX, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSBWui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */ + +{ /* AArch64_LDRSBWui, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSBXpost, ARM64_INS_LDRSB: ldrsb $rt, [$rn], $offset */ + +{ /* AArch64_LDRSBXpost, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSBXpre, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRSBXpre, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSBXroW, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSBXroW, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSBXroX, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSBXroX, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSBXui, ARM64_INS_LDRSB: ldrsb $rt, [$rn, $offset] */ + +{ /* AArch64_LDRSBXui, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSHWpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */ + +{ /* AArch64_LDRSHWpost, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSHWpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRSHWpre, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSHWroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSHWroW, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSHWroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSHWroX, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSHWui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */ + +{ /* AArch64_LDRSHWui, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSHXpost, ARM64_INS_LDRSH: ldrsh $rt, [$rn], $offset */ + +{ /* AArch64_LDRSHXpost, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSHXpre, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRSHXpre, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSHXroW, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSHXroW, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSHXroX, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSHXroX, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSHXui, ARM64_INS_LDRSH: ldrsh $rt, [$rn, $offset] */ + +{ /* AArch64_LDRSHXui, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSWl, ARM64_INS_LDRSW: ldrsw $rt, $label */ + +{ /* AArch64_LDRSWl, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSWpost, ARM64_INS_LDRSW: ldrsw $rt, [$rn], $offset */ + +{ /* AArch64_LDRSWpost, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSWpre, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRSWpre, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSWroW, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSWroW, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSWroX, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSWroX, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSWui, ARM64_INS_LDRSW: ldrsw $rt, [$rn, $offset] */ + +{ /* AArch64_LDRSWui, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSl, ARM64_INS_LDR: ldr $rt, $label */ + +{ /* AArch64_LDRSl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRSpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRSpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRSroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRSroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRSui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRSui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRWl, ARM64_INS_LDR: ldr $rt, $label */ + +{ /* AArch64_LDRWl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDRWpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRWpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRWpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRWpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRWroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRWroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRWroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRWroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRWui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRWui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRXl, ARM64_INS_LDR: ldr $rt, $label */ + +{ /* AArch64_LDRXl, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDRXpost, ARM64_INS_LDR: ldr $rt, [$rn], $offset */ + +{ /* AArch64_LDRXpost, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRXpre, ARM64_INS_LDR: ldr $rt, [$rn, $offset]! */ + +{ /* AArch64_LDRXpre, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDRXroW, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRXroW, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRXroX, ARM64_INS_LDR: ldr $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_LDRXroX, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_LDRXui, ARM64_INS_LDR: ldr $rt, [$rn, $offset] */ + +{ /* AArch64_LDRXui, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LDTRBi, ARM64_INS_LDTRB: ldtrb $rt, [$rn, $offset] */ + +{ /* AArch64_LDR_PXI, AArch64_INS_LDR: ldr */ + 0, + { 0 } +}, + +{ /* AArch64_LDR_ZXI, AArch64_INS_LDR: ldr */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETAB, AArch64_INS_LDSETAB: ldsetab */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETAH, AArch64_INS_LDSETAH: ldsetah */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETALB, AArch64_INS_LDSETALB: ldsetalb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETALH, AArch64_INS_LDSETALH: ldsetalh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETALW, AArch64_INS_LDSETAL: ldsetal */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETALX, AArch64_INS_LDSETAL: ldsetal */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETAW, AArch64_INS_LDSETA: ldseta */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETAX, AArch64_INS_LDSETA: ldseta */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETB, AArch64_INS_LDSETB: ldsetb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETH, AArch64_INS_LDSETH: ldseth */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETLB, AArch64_INS_LDSETLB: ldsetlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETLH, AArch64_INS_LDSETLH: ldsetlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETLW, AArch64_INS_LDSETL: ldsetl */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETLX, AArch64_INS_LDSETL: ldsetl */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETW, AArch64_INS_LDSET: ldset */ + 0, + { 0 } +}, + +{ /* AArch64_LDSETX, AArch64_INS_LDSET: ldset */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXAB, AArch64_INS_LDSMAXAB: ldsmaxab */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXAH, AArch64_INS_LDSMAXAH: ldsmaxah */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXALB, AArch64_INS_LDSMAXALB: ldsmaxalb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXALH, AArch64_INS_LDSMAXALH: ldsmaxalh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXALW, AArch64_INS_LDSMAXAL: ldsmaxal */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXALX, AArch64_INS_LDSMAXAL: ldsmaxal */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXAW, AArch64_INS_LDSMAXA: ldsmaxa */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXAX, AArch64_INS_LDSMAXA: ldsmaxa */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXB, AArch64_INS_LDSMAXB: ldsmaxb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXH, AArch64_INS_LDSMAXH: ldsmaxh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXLB, AArch64_INS_LDSMAXLB: ldsmaxlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXLH, AArch64_INS_LDSMAXLH: ldsmaxlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXLW, AArch64_INS_LDSMAXL: ldsmaxl */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXLX, AArch64_INS_LDSMAXL: ldsmaxl */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXW, AArch64_INS_LDSMAX: ldsmax */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMAXX, AArch64_INS_LDSMAX: ldsmax */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINAB, AArch64_INS_LDSMINAB: ldsminab */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINAH, AArch64_INS_LDSMINAH: ldsminah */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINALB, AArch64_INS_LDSMINALB: ldsminalb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINALH, AArch64_INS_LDSMINALH: ldsminalh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINALW, AArch64_INS_LDSMINAL: ldsminal */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINALX, AArch64_INS_LDSMINAL: ldsminal */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINAW, AArch64_INS_LDSMINA: ldsmina */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINAX, AArch64_INS_LDSMINA: ldsmina */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINB, AArch64_INS_LDSMINB: ldsminb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINH, AArch64_INS_LDSMINH: ldsminh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINLB, AArch64_INS_LDSMINLB: ldsminlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINLH, AArch64_INS_LDSMINLH: ldsminlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINLW, AArch64_INS_LDSMINL: ldsminl */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINLX, AArch64_INS_LDSMINL: ldsminl */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINW, AArch64_INS_LDSMIN: ldsmin */ + 0, + { 0 } +}, + +{ /* AArch64_LDSMINX, AArch64_INS_LDSMIN: ldsmin */ + 0, + { 0 } +}, + +{ /* AArch64_LDTRBi, AArch64_INS_LDTRB: ldtrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRHi, ARM64_INS_LDTRH: ldtrh $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRHi, AArch64_INS_LDTRH: ldtrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRSBWi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRSBWi, AArch64_INS_LDTRSB: ldtrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRSBXi, ARM64_INS_LDTRSB: ldtrsb $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRSBXi, AArch64_INS_LDTRSB: ldtrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRSHWi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRSHWi, AArch64_INS_LDTRSH: ldtrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRSHXi, ARM64_INS_LDTRSH: ldtrsh $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRSHXi, AArch64_INS_LDTRSH: ldtrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRSWi, ARM64_INS_LDTRSW: ldtrsw $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRSWi, AArch64_INS_LDTRSW: ldtrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRWi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRWi, AArch64_INS_LDTR: ldtr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDTRXi, ARM64_INS_LDTR: ldtr $rt, [$rn, $offset] */ + +{ /* AArch64_LDTRXi, AArch64_INS_LDTR: ldtr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURBBi, ARM64_INS_LDURB: ldurb $rt, [$rn, $offset] */ + +{ /* AArch64_LDUMAXAB, AArch64_INS_LDUMAXAB: ldumaxab */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXAH, AArch64_INS_LDUMAXAH: ldumaxah */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXALB, AArch64_INS_LDUMAXALB: ldumaxalb */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXALH, AArch64_INS_LDUMAXALH: ldumaxalh */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXALW, AArch64_INS_LDUMAXAL: ldumaxal */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXALX, AArch64_INS_LDUMAXAL: ldumaxal */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXAW, AArch64_INS_LDUMAXA: ldumaxa */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXAX, AArch64_INS_LDUMAXA: ldumaxa */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXB, AArch64_INS_LDUMAXB: ldumaxb */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXH, AArch64_INS_LDUMAXH: ldumaxh */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXLB, AArch64_INS_LDUMAXLB: ldumaxlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXLH, AArch64_INS_LDUMAXLH: ldumaxlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXLW, AArch64_INS_LDUMAXL: ldumaxl */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXLX, AArch64_INS_LDUMAXL: ldumaxl */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXW, AArch64_INS_LDUMAX: ldumax */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMAXX, AArch64_INS_LDUMAX: ldumax */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINAB, AArch64_INS_LDUMINAB: lduminab */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINAH, AArch64_INS_LDUMINAH: lduminah */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINALB, AArch64_INS_LDUMINALB: lduminalb */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINALH, AArch64_INS_LDUMINALH: lduminalh */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINALW, AArch64_INS_LDUMINAL: lduminal */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINALX, AArch64_INS_LDUMINAL: lduminal */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINAW, AArch64_INS_LDUMINA: ldumina */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINAX, AArch64_INS_LDUMINA: ldumina */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINB, AArch64_INS_LDUMINB: lduminb */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINH, AArch64_INS_LDUMINH: lduminh */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINLB, AArch64_INS_LDUMINLB: lduminlb */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINLH, AArch64_INS_LDUMINLH: lduminlh */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINLW, AArch64_INS_LDUMINL: lduminl */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINLX, AArch64_INS_LDUMINL: lduminl */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINW, AArch64_INS_LDUMIN: ldumin */ + 0, + { 0 } +}, + +{ /* AArch64_LDUMINX, AArch64_INS_LDUMIN: ldumin */ + 0, + { 0 } +}, + +{ /* AArch64_LDURBBi, AArch64_INS_LDRB: ldrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURBi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURBi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURDi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURDi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURHHi, ARM64_INS_LDURH: ldurh $rt, [$rn, $offset] */ + +{ /* AArch64_LDURHHi, AArch64_INS_LDRH: ldrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURHi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURHi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURQi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURQi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURSBWi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */ + +{ /* AArch64_LDURSBWi, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURSBXi, ARM64_INS_LDURSB: ldursb $rt, [$rn, $offset] */ + +{ /* AArch64_LDURSBXi, AArch64_INS_LDRSB: ldrsb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURSHWi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */ + +{ /* AArch64_LDURSHWi, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURSHXi, ARM64_INS_LDURSH: ldursh $rt, [$rn, $offset] */ + +{ /* AArch64_LDURSHXi, AArch64_INS_LDRSH: ldrsh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURSWi, ARM64_INS_LDURSW: ldursw $rt, [$rn, $offset] */ + +{ /* AArch64_LDURSWi, AArch64_INS_LDRSW: ldrsw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURSi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURSi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURWi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURWi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDURXi, ARM64_INS_LDUR: ldur $rt, [$rn, $offset] */ + +{ /* AArch64_LDURXi, AArch64_INS_LDR: ldr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_LDXPW, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */ + +{ /* AArch64_LDXPW, AArch64_INS_LDXP: ldxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDXPX, ARM64_INS_LDXP: ldxp $rt, $rt2, [$rn] */ + +{ /* AArch64_LDXPX, AArch64_INS_LDXP: ldxp */ 0, { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDXRB, ARM64_INS_LDXRB: ldxrb $rt, [$rn] */ + +{ /* AArch64_LDXRB, AArch64_INS_LDXRB: ldxrb */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDXRH, ARM64_INS_LDXRH: ldxrh $rt, [$rn] */ + +{ /* AArch64_LDXRH, AArch64_INS_LDXRH: ldxrh */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDXRW, ARM64_INS_LDXR: ldxr $rt, [$rn] */ + +{ /* AArch64_LDXRW, AArch64_INS_LDXR: ldxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LDXRX, ARM64_INS_LDXR: ldxr $rt, [$rn] */ + +{ /* AArch64_LDXRX, AArch64_INS_LDXR: ldxr */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_LSLVWr, ARM64_INS_LSL: lsl $rd, $rn, $rm */ + +{ /* AArch64_LSLR_ZPmZ_B, AArch64_INS_LSLR: lslr */ + 0, + { 0 } +}, + +{ /* AArch64_LSLR_ZPmZ_D, AArch64_INS_LSLR: lslr */ + 0, + { 0 } +}, + +{ /* AArch64_LSLR_ZPmZ_H, AArch64_INS_LSLR: lslr */ + 0, + { 0 } +}, + +{ /* AArch64_LSLR_ZPmZ_S, AArch64_INS_LSLR: lslr */ + 0, + { 0 } +}, + +{ /* AArch64_LSLVWr, AArch64_INS_LSL: lsl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LSLVXr, ARM64_INS_LSL: lsl $rd, $rn, $rm */ + +{ /* AArch64_LSLVXr, AArch64_INS_LSL: lsl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LSRVWr, ARM64_INS_LSR: lsr $rd, $rn, $rm */ + +{ /* AArch64_LSL_WIDE_ZPmZ_B, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_WIDE_ZPmZ_H, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_WIDE_ZPmZ_S, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_WIDE_ZZZ_B, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_WIDE_ZZZ_H, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_WIDE_ZZZ_S, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmI_B, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmI_D, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmI_H, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmI_S, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmZ_B, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmZ_D, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmZ_H, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZPmZ_S, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZZI_B, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZZI_D, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZZI_H, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSL_ZZI_S, AArch64_INS_LSL: lsl */ + 0, + { 0 } +}, + +{ /* AArch64_LSRR_ZPmZ_B, AArch64_INS_LSRR: lsrr */ + 0, + { 0 } +}, + +{ /* AArch64_LSRR_ZPmZ_D, AArch64_INS_LSRR: lsrr */ + 0, + { 0 } +}, + +{ /* AArch64_LSRR_ZPmZ_H, AArch64_INS_LSRR: lsrr */ + 0, + { 0 } +}, + +{ /* AArch64_LSRR_ZPmZ_S, AArch64_INS_LSRR: lsrr */ + 0, + { 0 } +}, + +{ /* AArch64_LSRVWr, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_LSRVXr, ARM64_INS_LSR: lsr $rd, $rn, $rm */ + +{ /* AArch64_LSRVXr, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MADDWrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */ + +{ /* AArch64_LSR_WIDE_ZPmZ_B, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_WIDE_ZPmZ_H, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_WIDE_ZPmZ_S, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_WIDE_ZZZ_B, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_WIDE_ZZZ_H, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_WIDE_ZZZ_S, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmI_B, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmI_D, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmI_H, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmI_S, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmZ_B, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmZ_D, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmZ_H, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZPmZ_S, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZZI_B, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZZI_D, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZZI_H, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_LSR_ZZI_S, AArch64_INS_LSR: lsr */ + 0, + { 0 } +}, + +{ /* AArch64_MADDWrrr, AArch64_INS_MADD: madd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MADDXrrr, ARM64_INS_MADD: madd $rd, $rn, $rm, $ra */ + +{ /* AArch64_MADDXrrr, AArch64_INS_MADD: madd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLAv16i8, ARM64_INS_MLA: mla.16b $rd, $rn, $rm */ + +{ /* AArch64_MAD_ZPmZZ_B, AArch64_INS_MAD: mad */ + 0, + { 0 } +}, + +{ /* AArch64_MAD_ZPmZZ_D, AArch64_INS_MAD: mad */ + 0, + { 0 } +}, + +{ /* AArch64_MAD_ZPmZZ_H, AArch64_INS_MAD: mad */ + 0, + { 0 } +}, + +{ /* AArch64_MAD_ZPmZZ_S, AArch64_INS_MAD: mad */ + 0, + { 0 } +}, + +{ /* AArch64_MLA_ZPmZZ_B, AArch64_INS_MLA: mla */ + 0, + { 0 } +}, + +{ /* AArch64_MLA_ZPmZZ_D, AArch64_INS_MLA: mla */ + 0, + { 0 } +}, + +{ /* AArch64_MLA_ZPmZZ_H, AArch64_INS_MLA: mla */ + 0, + { 0 } +}, + +{ /* AArch64_MLA_ZPmZZ_S, AArch64_INS_MLA: mla */ + 0, + { 0 } +}, + +{ /* AArch64_MLAv16i8, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLAv2i32, ARM64_INS_MLA: mla.2s $rd, $rn, $rm */ + +{ /* AArch64_MLAv2i32, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLAv2i32_indexed, ARM64_INS_MLA: mla.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_MLAv2i32_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLAv4i16, ARM64_INS_MLA: mla.4h $rd, $rn, $rm */ + +{ /* AArch64_MLAv4i16, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLAv4i16_indexed, ARM64_INS_MLA: mla.4h $rd, $rn, $rm$idx */ + +{ /* AArch64_MLAv4i16_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLAv4i32, ARM64_INS_MLA: mla.4s $rd, $rn, $rm */ + +{ /* AArch64_MLAv4i32, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLAv4i32_indexed, ARM64_INS_MLA: mla.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_MLAv4i32_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLAv8i16, ARM64_INS_MLA: mla.8h $rd, $rn, $rm */ + +{ /* AArch64_MLAv8i16, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLAv8i16_indexed, ARM64_INS_MLA: mla.8h $rd, $rn, $rm$idx */ + +{ /* AArch64_MLAv8i16_indexed, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLAv8i8, ARM64_INS_MLA: mla.8b $rd, $rn, $rm */ + +{ /* AArch64_MLAv8i8, AArch64_INS_MLA: mla */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLSv16i8, ARM64_INS_MLS: mls.16b $rd, $rn, $rm */ + +{ /* AArch64_MLS_ZPmZZ_B, AArch64_INS_MLS: mls */ + 0, + { 0 } +}, + +{ /* AArch64_MLS_ZPmZZ_D, AArch64_INS_MLS: mls */ + 0, + { 0 } +}, + +{ /* AArch64_MLS_ZPmZZ_H, AArch64_INS_MLS: mls */ + 0, + { 0 } +}, + +{ /* AArch64_MLS_ZPmZZ_S, AArch64_INS_MLS: mls */ + 0, + { 0 } +}, + +{ /* AArch64_MLSv16i8, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLSv2i32, ARM64_INS_MLS: mls.2s $rd, $rn, $rm */ + +{ /* AArch64_MLSv2i32, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLSv2i32_indexed, ARM64_INS_MLS: mls.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_MLSv2i32_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLSv4i16, ARM64_INS_MLS: mls.4h $rd, $rn, $rm */ + +{ /* AArch64_MLSv4i16, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLSv4i16_indexed, ARM64_INS_MLS: mls.4h $rd, $rn, $rm$idx */ + +{ /* AArch64_MLSv4i16_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLSv4i32, ARM64_INS_MLS: mls.4s $rd, $rn, $rm */ + +{ /* AArch64_MLSv4i32, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLSv4i32_indexed, ARM64_INS_MLS: mls.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_MLSv4i32_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLSv8i16, ARM64_INS_MLS: mls.8h $rd, $rn, $rm */ + +{ /* AArch64_MLSv8i16, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MLSv8i16_indexed, ARM64_INS_MLS: mls.8h $rd, $rn, $rm$idx */ + +{ /* AArch64_MLSv8i16_indexed, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MLSv8i8, ARM64_INS_MLS: mls.8b $rd, $rn, $rm */ + +{ /* AArch64_MLSv8i8, AArch64_INS_MLS: mls */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVID, ARM64_INS_MOVI: movi $rd, $imm8 */ + +{ /* AArch64_MOVID, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv16b_ns, ARM64_INS_MOVI: movi.16b $rd, $imm8 */ + +{ /* AArch64_MOVIv16b_ns, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv2d_ns, ARM64_INS_MOVI: movi.2d $rd, $imm8 */ + +{ /* AArch64_MOVIv2d_ns, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv2i32, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */ + +{ /* AArch64_MOVIv2i32, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv2s_msl, ARM64_INS_MOVI: movi.2s $rd, $imm8$shift */ + +{ /* AArch64_MOVIv2s_msl, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv4i16, ARM64_INS_MOVI: movi.4h $rd, $imm8$shift */ + +{ /* AArch64_MOVIv4i16, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv4i32, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */ + +{ /* AArch64_MOVIv4i32, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv4s_msl, ARM64_INS_MOVI: movi.4s $rd, $imm8$shift */ + +{ /* AArch64_MOVIv4s_msl, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv8b_ns, ARM64_INS_MOVI: movi.8b $rd, $imm8 */ + +{ /* AArch64_MOVIv8b_ns, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVIv8i16, ARM64_INS_MOVI: movi.8h $rd, $imm8$shift */ + +{ /* AArch64_MOVIv8i16, AArch64_INS_MOVI: movi */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVKWi, ARM64_INS_MOVK: movk $rd, $imm$shift */ + +{ /* AArch64_MOVKWi, AArch64_INS_MOVK: movk */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVKXi, ARM64_INS_MOVK: movk $rd, $imm$shift */ + +{ /* AArch64_MOVKXi, AArch64_INS_MOVK: movk */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVNWi, ARM64_INS_MOVN: movn $rd, $imm$shift */ + +{ /* AArch64_MOVNWi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVNXi, ARM64_INS_MOVN: movn $rd, $imm$shift */ + +{ /* AArch64_MOVNXi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVZWi, ARM64_INS_MOVZ: movz $rd, $imm$shift */ + +{ /* AArch64_MOVPRFX_ZPmZ_B, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPmZ_D, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPmZ_H, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPmZ_S, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPzZ_B, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPzZ_D, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPzZ_H, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZPzZ_S, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVPRFX_ZZ, AArch64_INS_MOVPRFX: movprfx */ + 0, + { 0 } +}, + +{ /* AArch64_MOVZWi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MOVZXi, ARM64_INS_MOVZ: movz $rd, $imm$shift */ + +{ /* AArch64_MOVZXi, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MRS, ARM64_INS_MRS: mrs $rt, $systemreg */ + +{ /* AArch64_MRS, AArch64_INS_MRS: mrs */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_MSR, ARM64_INS_MSR: msr $systemreg, $rt */ + +{ /* AArch64_MSB_ZPmZZ_B, AArch64_INS_MSB: msb */ + 0, + { 0 } +}, + +{ /* AArch64_MSB_ZPmZZ_D, AArch64_INS_MSB: msb */ + 0, + { 0 } +}, + +{ /* AArch64_MSB_ZPmZZ_H, AArch64_INS_MSB: msb */ + 0, + { 0 } +}, + +{ /* AArch64_MSB_ZPmZZ_S, AArch64_INS_MSB: msb */ + 0, + { 0 } +}, + +{ /* AArch64_MSR, AArch64_INS_MSR: msr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_MSRpstate, ARM64_INS_MSR: msr $pstate_field, $imm */ + +{ /* AArch64_MSRpstateImm1, AArch64_INS_MSR: msr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MSUBWrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */ + +{ /* AArch64_MSRpstateImm4, AArch64_INS_MSR: msr */ + 0, + { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } +}, + +{ /* AArch64_MSUBWrrr, AArch64_INS_MNEG: mneg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MSUBXrrr, ARM64_INS_MSUB: msub $rd, $rn, $rm, $ra */ + +{ /* AArch64_MSUBXrrr, AArch64_INS_MNEG: mneg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MULv16i8, ARM64_INS_MUL: mul.16b $rd, $rn, $rm| */ + +{ /* AArch64_MUL_ZI_B, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZI_D, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZI_H, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZI_S, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZPmZ_B, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZPmZ_D, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZPmZ_H, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MUL_ZPmZ_S, AArch64_INS_MUL: mul */ + 0, + { 0 } +}, + +{ /* AArch64_MULv16i8, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv2i32, ARM64_INS_MUL: mul.2s $rd, $rn, $rm| */ + +{ /* AArch64_MULv2i32, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv2i32_indexed, ARM64_INS_MUL: mul.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_MULv2i32_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MULv4i16, ARM64_INS_MUL: mul.4h $rd, $rn, $rm| */ + +{ /* AArch64_MULv4i16, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv4i16_indexed, ARM64_INS_MUL: mul.4h $rd, $rn, $rm$idx */ + +{ /* AArch64_MULv4i16_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_MULv4i32, ARM64_INS_MUL: mul.4s $rd, $rn, $rm| */ + +{ /* AArch64_MULv4i32, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv4i32_indexed, ARM64_INS_MUL: mul.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_MULv4i32_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv8i16, ARM64_INS_MUL: mul.8h $rd, $rn, $rm| */ + +{ /* AArch64_MULv8i16, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv8i16_indexed, ARM64_INS_MUL: mul.8h $rd, $rn, $rm$idx */ + +{ /* AArch64_MULv8i16_indexed, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MULv8i8, ARM64_INS_MUL: mul.8b $rd, $rn, $rm| */ + +{ /* AArch64_MULv8i8, AArch64_INS_MUL: mul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MVNIv2i32, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */ + +{ /* AArch64_MVNIv2i32, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MVNIv2s_msl, ARM64_INS_MVNI: mvni.2s $rd, $imm8$shift */ + +{ /* AArch64_MVNIv2s_msl, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MVNIv4i16, ARM64_INS_MVNI: mvni.4h $rd, $imm8$shift */ + +{ /* AArch64_MVNIv4i16, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MVNIv4i32, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */ + +{ /* AArch64_MVNIv4i32, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MVNIv4s_msl, ARM64_INS_MVNI: mvni.4s $rd, $imm8$shift */ + +{ /* AArch64_MVNIv4s_msl, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_MVNIv8i16, ARM64_INS_MVNI: mvni.8h $rd, $imm8$shift */ + +{ /* AArch64_MVNIv8i16, AArch64_INS_MVNI: mvni */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv16i8, ARM64_INS_NEG: neg.16b $rd, $rn */ + +{ /* AArch64_NANDS_PPzPP, AArch64_INS_NANDS: nands */ + 0, + { 0 } +}, + +{ /* AArch64_NAND_PPzPP, AArch64_INS_NAND: nand */ + 0, + { 0 } +}, + +{ /* AArch64_NEG_ZPmZ_B, AArch64_INS_NEG: neg */ + 0, + { 0 } +}, + +{ /* AArch64_NEG_ZPmZ_D, AArch64_INS_NEG: neg */ + 0, + { 0 } +}, + +{ /* AArch64_NEG_ZPmZ_H, AArch64_INS_NEG: neg */ + 0, + { 0 } +}, + +{ /* AArch64_NEG_ZPmZ_S, AArch64_INS_NEG: neg */ + 0, + { 0 } +}, + +{ /* AArch64_NEGv16i8, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv1i64, ARM64_INS_NEG: neg $rd, $rn */ + +{ /* AArch64_NEGv1i64, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv2i32, ARM64_INS_NEG: neg.2s $rd, $rn */ + +{ /* AArch64_NEGv2i32, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv2i64, ARM64_INS_NEG: neg.2d $rd, $rn */ + +{ /* AArch64_NEGv2i64, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv4i16, ARM64_INS_NEG: neg.4h $rd, $rn */ + +{ /* AArch64_NEGv4i16, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv4i32, ARM64_INS_NEG: neg.4s $rd, $rn */ + +{ /* AArch64_NEGv4i32, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv8i16, ARM64_INS_NEG: neg.8h $rd, $rn */ + +{ /* AArch64_NEGv8i16, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NEGv8i8, ARM64_INS_NEG: neg.8b $rd, $rn */ + +{ /* AArch64_NEGv8i8, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NOTv16i8, ARM64_INS_NOT: not.16b $rd, $rn */ + +{ /* AArch64_NORS_PPzPP, AArch64_INS_NORS: nors */ + 0, + { 0 } +}, + +{ /* AArch64_NOR_PPzPP, AArch64_INS_NOR: nor */ + 0, + { 0 } +}, + +{ /* AArch64_NOT_ZPmZ_B, AArch64_INS_NOT: not */ + 0, + { 0 } +}, + +{ /* AArch64_NOT_ZPmZ_D, AArch64_INS_NOT: not */ + 0, + { 0 } +}, + +{ /* AArch64_NOT_ZPmZ_H, AArch64_INS_NOT: not */ + 0, + { 0 } +}, + +{ /* AArch64_NOT_ZPmZ_S, AArch64_INS_NOT: not */ + 0, + { 0 } +}, + +{ /* AArch64_NOTv16i8, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_NOTv8i8, ARM64_INS_NOT: not.8b $rd, $rn */ + +{ /* AArch64_NOTv8i8, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ORNWrs, ARM64_INS_ORN: orn $rd, $rn, $rm */ + +{ /* AArch64_ORNS_PPzPP, AArch64_INS_ORNS: orns */ + 0, + { 0 } +}, + +{ /* AArch64_ORNWrs, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORNXrs, ARM64_INS_ORN: orn $rd, $rn, $rm */ + +{ /* AArch64_ORNXrs, AArch64_INS_MVN: mvn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORNv16i8, ARM64_INS_ORN: orn.16b $rd, $rn, $rm| */ + +{ /* AArch64_ORN_PPzPP, AArch64_INS_ORN: orn */ + 0, + { 0 } +}, + +{ /* AArch64_ORNv16i8, AArch64_INS_ORN: orn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORNv8i8, ARM64_INS_ORN: orn.8b $rd, $rn, $rm| */ + +{ /* AArch64_ORNv8i8, AArch64_INS_ORN: orn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRWri, ARM64_INS_ORR: orr $rd, $rn, $imm */ + +{ /* AArch64_ORRS_PPzPP, AArch64_INS_MOVS: movs */ + 0, + { 0 } +}, + +{ /* AArch64_ORRWri, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRWrs, ARM64_INS_ORR: orr $rd, $rn, $rm */ + +{ /* AArch64_ORRWrs, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRXri, ARM64_INS_ORR: orr $rd, $rn, $imm */ + +{ /* AArch64_ORRXri, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRXrs, ARM64_INS_ORR: orr $rd, $rn, $rm */ + +{ /* AArch64_ORRXrs, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRv16i8, ARM64_INS_ORR: orr.16b $rd, $rn, $rm| */ + +{ /* AArch64_ORR_PPzPP, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_ORR_ZI, AArch64_INS_ORN: orn */ + 0, + { 0 } +}, + +{ /* AArch64_ORR_ZPmZ_B, AArch64_INS_ORR: orr */ + 0, + { 0 } +}, + +{ /* AArch64_ORR_ZPmZ_D, AArch64_INS_ORR: orr */ + 0, + { 0 } +}, + +{ /* AArch64_ORR_ZPmZ_H, AArch64_INS_ORR: orr */ + 0, + { 0 } +}, + +{ /* AArch64_ORR_ZPmZ_S, AArch64_INS_ORR: orr */ + 0, + { 0 } +}, + +{ /* AArch64_ORR_ZZZ, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_ORRv16i8, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRv2i32, ARM64_INS_ORR: orr.2s $rd, $imm8$shift */ + +{ /* AArch64_ORRv2i32, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRv4i16, ARM64_INS_ORR: orr.4h $rd, $imm8$shift */ + +{ /* AArch64_ORRv4i16, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRv4i32, ARM64_INS_ORR: orr.4s $rd, $imm8$shift */ + +{ /* AArch64_ORRv4i32, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRv8i16, ARM64_INS_ORR: orr.8h $rd, $imm8$shift */ + +{ /* AArch64_ORRv8i16, AArch64_INS_ORR: orr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ORRv8i8, ARM64_INS_ORR: orr.8b $rd, $rn, $rm| */ + +{ /* AArch64_ORRv8i8, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_PMULLv16i8, ARM64_INS_PMULL2: pmull2.8h $rd, $rn, $rm */ + +{ /* AArch64_ORV_VPZ_B, AArch64_INS_ORV: orv */ + 0, + { 0 } +}, + +{ /* AArch64_ORV_VPZ_D, AArch64_INS_ORV: orv */ + 0, + { 0 } +}, + +{ /* AArch64_ORV_VPZ_H, AArch64_INS_ORV: orv */ + 0, + { 0 } +}, + +{ /* AArch64_ORV_VPZ_S, AArch64_INS_ORV: orv */ + 0, + { 0 } +}, + +{ /* AArch64_PACDA, AArch64_INS_PACDA: pacda */ + 0, + { 0 } +}, + +{ /* AArch64_PACDB, AArch64_INS_PACDB: pacdb */ + 0, + { 0 } +}, + +{ /* AArch64_PACDZA, AArch64_INS_PACDZA: pacdza */ + 0, + { 0 } +}, + +{ /* AArch64_PACDZB, AArch64_INS_PACDZB: pacdzb */ + 0, + { 0 } +}, + +{ /* AArch64_PACGA, AArch64_INS_PACGA: pacga */ + 0, + { 0 } +}, + +{ /* AArch64_PACIA, AArch64_INS_PACIA: pacia */ + 0, + { 0 } +}, + +{ /* AArch64_PACIA1716, AArch64_INS_PACIA1716: pacia1716 */ + 0, + { 0 } +}, + +{ /* AArch64_PACIASP, AArch64_INS_PACIASP: paciasp */ + 0, + { 0 } +}, + +{ /* AArch64_PACIAZ, AArch64_INS_PACIAZ: paciaz */ + 0, + { 0 } +}, + +{ /* AArch64_PACIB, AArch64_INS_PACIB: pacib */ + 0, + { 0 } +}, + +{ /* AArch64_PACIB1716, AArch64_INS_PACIB1716: pacib1716 */ + 0, + { 0 } +}, + +{ /* AArch64_PACIBSP, AArch64_INS_PACIBSP: pacibsp */ + 0, + { 0 } +}, + +{ /* AArch64_PACIBZ, AArch64_INS_PACIBZ: pacibz */ + 0, + { 0 } +}, + +{ /* AArch64_PACIZA, AArch64_INS_PACIZA: paciza */ + 0, + { 0 } +}, + +{ /* AArch64_PACIZB, AArch64_INS_PACIZB: pacizb */ + 0, + { 0 } +}, + +{ /* AArch64_PFALSE, AArch64_INS_PFALSE: pfalse */ + 0, + { 0 } +}, + +{ /* AArch64_PMULLv16i8, AArch64_INS_PMULL2: pmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_PMULLv1i64, ARM64_INS_PMULL: pmull.1q $rd, $rn, $rm */ + +{ /* AArch64_PMULLv1i64, AArch64_INS_PMULL: pmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_PMULLv2i64, ARM64_INS_PMULL2: pmull2.1q $rd, $rn, $rm */ + +{ /* AArch64_PMULLv2i64, AArch64_INS_PMULL2: pmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_PMULLv8i8, ARM64_INS_PMULL: pmull.8h $rd, $rn, $rm */ + +{ /* AArch64_PMULLv8i8, AArch64_INS_PMULL: pmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_PMULv16i8, ARM64_INS_PMUL: pmul.16b $rd, $rn, $rm| */ + +{ /* AArch64_PMULv16i8, AArch64_INS_PMUL: pmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_PMULv8i8, ARM64_INS_PMUL: pmul.8b $rd, $rn, $rm| */ + +{ /* AArch64_PMULv8i8, AArch64_INS_PMUL: pmul */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_PRFMl, ARM64_INS_PRFM: prfm $rt, $label */ + +{ /* AArch64_PNEXT_B, AArch64_INS_PNEXT: pnext */ + 0, + { 0 } +}, + +{ /* AArch64_PNEXT_D, AArch64_INS_PNEXT: pnext */ + 0, + { 0 } +}, + +{ /* AArch64_PNEXT_H, AArch64_INS_PNEXT: pnext */ + 0, + { 0 } +}, + +{ /* AArch64_PNEXT_S, AArch64_INS_PNEXT: pnext */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_D_PZI, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_D_SCALED, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_D_SXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_D_UXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_PRI, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_PRR, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_S_PZI, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_S_SXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFB_S_UXTW_SCALED, AArch64_INS_PRFB: prfb */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_D_PZI, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_D_SCALED, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_D_SXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_D_UXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_PRI, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_PRR, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_S_PZI, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_S_SXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFD_S_UXTW_SCALED, AArch64_INS_PRFD: prfd */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_D_PZI, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_D_SCALED, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_D_SXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_D_UXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_PRI, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_PRR, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_S_PZI, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_S_SXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFH_S_UXTW_SCALED, AArch64_INS_PRFH: prfh */ + 0, + { 0 } +}, + +{ /* AArch64_PRFMl, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_PRFMroW, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_PRFMroW, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_PRFMroX, ARM64_INS_PRFM: prfm $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_PRFMroX, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_PRFMui, ARM64_INS_PRFM: prfm $rt, [$rn, $offset] */ + +{ /* AArch64_PRFMui, AArch64_INS_PRFM: prfm */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_PRFUMi, ARM64_INS_PRFUM: prfum $rt, [$rn, $offset] */ + +{ /* AArch64_PRFS_PRR, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFUMi, AArch64_INS_PRFUM: prfum */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_RADDHNv2i64_v2i32, ARM64_INS_RADDHN: raddhn.2s $rd, $rn, $rm */ + +{ /* AArch64_PRFW_D_PZI, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_D_SCALED, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_D_SXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_D_UXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_PRI, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_S_PZI, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_S_SXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PRFW_S_UXTW_SCALED, AArch64_INS_PRFW: prfw */ + 0, + { 0 } +}, + +{ /* AArch64_PTEST_PP, AArch64_INS_PTEST: ptest */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUES_B, AArch64_INS_PTRUES: ptrues */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUES_D, AArch64_INS_PTRUES: ptrues */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUES_H, AArch64_INS_PTRUES: ptrues */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUES_S, AArch64_INS_PTRUES: ptrues */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUE_B, AArch64_INS_PTRUE: ptrue */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUE_D, AArch64_INS_PTRUE: ptrue */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUE_H, AArch64_INS_PTRUE: ptrue */ + 0, + { 0 } +}, + +{ /* AArch64_PTRUE_S, AArch64_INS_PTRUE: ptrue */ + 0, + { 0 } +}, + +{ /* AArch64_PUNPKHI_PP, AArch64_INS_PUNPKHI: punpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_PUNPKLO_PP, AArch64_INS_PUNPKLO: punpklo */ + 0, + { 0 } +}, + +{ /* AArch64_RADDHNv2i64_v2i32, AArch64_INS_RADDHN: raddhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RADDHNv2i64_v4i32, ARM64_INS_RADDHN2: raddhn2.4s $rd, $rn, $rm */ + +{ /* AArch64_RADDHNv2i64_v4i32, AArch64_INS_RADDHN2: raddhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RADDHNv4i32_v4i16, ARM64_INS_RADDHN: raddhn.4h $rd, $rn, $rm */ + +{ /* AArch64_RADDHNv4i32_v4i16, AArch64_INS_RADDHN: raddhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RADDHNv4i32_v8i16, ARM64_INS_RADDHN2: raddhn2.8h $rd, $rn, $rm */ + +{ /* AArch64_RADDHNv4i32_v8i16, AArch64_INS_RADDHN2: raddhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RADDHNv8i16_v16i8, ARM64_INS_RADDHN2: raddhn2.16b $rd, $rn, $rm */ + +{ /* AArch64_RADDHNv8i16_v16i8, AArch64_INS_RADDHN2: raddhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RADDHNv8i16_v8i8, ARM64_INS_RADDHN: raddhn.8b $rd, $rn, $rm */ + +{ /* AArch64_RADDHNv8i16_v8i8, AArch64_INS_RADDHN: raddhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RBITWr, ARM64_INS_RBIT: rbit $rd, $rn */ + +{ /* AArch64_RAX1, AArch64_INS_RAX1: rax1 */ + 0, + { 0 } +}, + +{ /* AArch64_RBITWr, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_RBITXr, ARM64_INS_RBIT: rbit $rd, $rn */ + +{ /* AArch64_RBITXr, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_RBITv16i8, ARM64_INS_RBIT: rbit.16b $rd, $rn */ + +{ /* AArch64_RBIT_ZPmZ_B, AArch64_INS_RBIT: rbit */ + 0, + { 0 } +}, + +{ /* AArch64_RBIT_ZPmZ_D, AArch64_INS_RBIT: rbit */ + 0, + { 0 } +}, + +{ /* AArch64_RBIT_ZPmZ_H, AArch64_INS_RBIT: rbit */ + 0, + { 0 } +}, + +{ /* AArch64_RBIT_ZPmZ_S, AArch64_INS_RBIT: rbit */ + 0, + { 0 } +}, + +{ /* AArch64_RBITv16i8, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_RBITv8i8, ARM64_INS_RBIT: rbit.8b $rd, $rn */ + +{ /* AArch64_RBITv8i8, AArch64_INS_RBIT: rbit */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_RET, ARM64_INS_RET: ret $rn */ + +{ /* AArch64_RDFFRS_PPz, AArch64_INS_RDFFRS: rdffrs */ + 0, + { 0 } +}, + +{ /* AArch64_RDFFR_P, AArch64_INS_RDFFR: rdffr */ + 0, + { 0 } +}, + +{ /* AArch64_RDFFR_PPz, AArch64_INS_RDFFR: rdffr */ + 0, + { 0 } +}, + +{ /* AArch64_RDVLI_XI, AArch64_INS_RDVL: rdvl */ + 0, + { 0 } +}, + +{ /* AArch64_RET, AArch64_INS_RET: ret */ 0, { CS_AC_READ, 0 } }, -{ /* AArch64_REV16Wr, ARM64_INS_REV16: rev16 $rd, $rn */ + +{ /* AArch64_RETAA, AArch64_INS_RETAA: retaa */ + 0, + { 0 } +}, + +{ /* AArch64_RETAB, AArch64_INS_RETAB: retab */ + 0, + { 0 } +}, + +{ /* AArch64_REV16Wr, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV16Xr, ARM64_INS_REV16: rev16 $rd, $rn */ + +{ /* AArch64_REV16Xr, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV16v16i8, ARM64_INS_REV16: rev16.16b $rd, $rn */ + +{ /* AArch64_REV16v16i8, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV16v8i8, ARM64_INS_REV16: rev16.8b $rd, $rn */ + +{ /* AArch64_REV16v8i8, AArch64_INS_REV16: rev16 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV32Xr, ARM64_INS_REV32: rev32 $rd, $rn */ + +{ /* AArch64_REV32Xr, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV32v16i8, ARM64_INS_REV32: rev32.16b $rd, $rn */ + +{ /* AArch64_REV32v16i8, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV32v4i16, ARM64_INS_REV32: rev32.4h $rd, $rn */ + +{ /* AArch64_REV32v4i16, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV32v8i16, ARM64_INS_REV32: rev32.8h $rd, $rn */ + +{ /* AArch64_REV32v8i16, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV32v8i8, ARM64_INS_REV32: rev32.8b $rd, $rn */ + +{ /* AArch64_REV32v8i8, AArch64_INS_REV32: rev32 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV64v16i8, ARM64_INS_REV64: rev64.16b $rd, $rn */ + +{ /* AArch64_REV64v16i8, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV64v2i32, ARM64_INS_REV64: rev64.2s $rd, $rn */ + +{ /* AArch64_REV64v2i32, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV64v4i16, ARM64_INS_REV64: rev64.4h $rd, $rn */ + +{ /* AArch64_REV64v4i16, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV64v4i32, ARM64_INS_REV64: rev64.4s $rd, $rn */ + +{ /* AArch64_REV64v4i32, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV64v8i16, ARM64_INS_REV64: rev64.8h $rd, $rn */ + +{ /* AArch64_REV64v8i16, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REV64v8i8, ARM64_INS_REV64: rev64.8b $rd, $rn */ + +{ /* AArch64_REV64v8i8, AArch64_INS_REV64: rev64 */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REVWr, ARM64_INS_REV: rev $rd, $rn */ + +{ /* AArch64_REVB_ZPmZ_D, AArch64_INS_REVB: revb */ + 0, + { 0 } +}, + +{ /* AArch64_REVB_ZPmZ_H, AArch64_INS_REVB: revb */ + 0, + { 0 } +}, + +{ /* AArch64_REVB_ZPmZ_S, AArch64_INS_REVB: revb */ + 0, + { 0 } +}, + +{ /* AArch64_REVH_ZPmZ_D, AArch64_INS_REVH: revh */ + 0, + { 0 } +}, + +{ /* AArch64_REVH_ZPmZ_S, AArch64_INS_REVH: revh */ + 0, + { 0 } +}, + +{ /* AArch64_REVW_ZPmZ_D, AArch64_INS_REVW: revw */ + 0, + { 0 } +}, + +{ /* AArch64_REVWr, AArch64_INS_REV: rev */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_REVXr, ARM64_INS_REV: rev $rd, $rn */ + +{ /* AArch64_REVXr, AArch64_INS_REV: rev */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_RORVWr, ARM64_INS_ROR: ror $rd, $rn, $rm */ + +{ /* AArch64_REV_PP_B, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_PP_D, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_PP_H, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_PP_S, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_ZZ_B, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_ZZ_D, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_ZZ_H, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_REV_ZZ_S, AArch64_INS_REV: rev */ + 0, + { 0 } +}, + +{ /* AArch64_RMIF, AArch64_INS_RMIF: rmif */ + 0, + { 0 } +}, + +{ /* AArch64_RORVWr, AArch64_INS_ROR: ror */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RORVXr, ARM64_INS_ROR: ror $rd, $rn, $rm */ + +{ /* AArch64_RORVXr, AArch64_INS_ROR: ror */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSHRNv16i8_shift, ARM64_INS_RSHRN2: rshrn2.16b $rd, $rn, $imm */ + +{ /* AArch64_RSHRNv16i8_shift, AArch64_INS_RSHRN2: rshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSHRNv2i32_shift, ARM64_INS_RSHRN: rshrn.2s $rd, $rn, $imm */ + +{ /* AArch64_RSHRNv2i32_shift, AArch64_INS_RSHRN: rshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSHRNv4i16_shift, ARM64_INS_RSHRN: rshrn.4h $rd, $rn, $imm */ + +{ /* AArch64_RSHRNv4i16_shift, AArch64_INS_RSHRN: rshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSHRNv4i32_shift, ARM64_INS_RSHRN2: rshrn2.4s $rd, $rn, $imm */ + +{ /* AArch64_RSHRNv4i32_shift, AArch64_INS_RSHRN2: rshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSHRNv8i16_shift, ARM64_INS_RSHRN2: rshrn2.8h $rd, $rn, $imm */ + +{ /* AArch64_RSHRNv8i16_shift, AArch64_INS_RSHRN2: rshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSHRNv8i8_shift, ARM64_INS_RSHRN: rshrn.8b $rd, $rn, $imm */ + +{ /* AArch64_RSHRNv8i8_shift, AArch64_INS_RSHRN: rshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSUBHNv2i64_v2i32, ARM64_INS_RSUBHN: rsubhn.2s $rd, $rn, $rm */ + +{ /* AArch64_RSUBHNv2i64_v2i32, AArch64_INS_RSUBHN: rsubhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSUBHNv2i64_v4i32, ARM64_INS_RSUBHN2: rsubhn2.4s $rd, $rn, $rm */ + +{ /* AArch64_RSUBHNv2i64_v4i32, AArch64_INS_RSUBHN2: rsubhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSUBHNv4i32_v4i16, ARM64_INS_RSUBHN: rsubhn.4h $rd, $rn, $rm */ + +{ /* AArch64_RSUBHNv4i32_v4i16, AArch64_INS_RSUBHN: rsubhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSUBHNv4i32_v8i16, ARM64_INS_RSUBHN2: rsubhn2.8h $rd, $rn, $rm */ + +{ /* AArch64_RSUBHNv4i32_v8i16, AArch64_INS_RSUBHN2: rsubhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSUBHNv8i16_v16i8, ARM64_INS_RSUBHN2: rsubhn2.16b $rd, $rn, $rm */ + +{ /* AArch64_RSUBHNv8i16_v16i8, AArch64_INS_RSUBHN2: rsubhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_RSUBHNv8i16_v8i8, ARM64_INS_RSUBHN: rsubhn.8b $rd, $rn, $rm */ + +{ /* AArch64_RSUBHNv8i16_v8i8, AArch64_INS_RSUBHN: rsubhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABALv16i8_v8i16, ARM64_INS_SABAL2: sabal2.8h $rd, $rn, $rm */ + +{ /* AArch64_SABALv16i8_v8i16, AArch64_INS_SABAL2: sabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABALv2i32_v2i64, ARM64_INS_SABAL: sabal.2d $rd, $rn, $rm */ + +{ /* AArch64_SABALv2i32_v2i64, AArch64_INS_SABAL: sabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABALv4i16_v4i32, ARM64_INS_SABAL: sabal.4s $rd, $rn, $rm */ + +{ /* AArch64_SABALv4i16_v4i32, AArch64_INS_SABAL: sabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABALv4i32_v2i64, ARM64_INS_SABAL2: sabal2.2d $rd, $rn, $rm */ + +{ /* AArch64_SABALv4i32_v2i64, AArch64_INS_SABAL2: sabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABALv8i16_v4i32, ARM64_INS_SABAL2: sabal2.4s $rd, $rn, $rm */ + +{ /* AArch64_SABALv8i16_v4i32, AArch64_INS_SABAL2: sabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABALv8i8_v8i16, ARM64_INS_SABAL: sabal.8h $rd, $rn, $rm */ + +{ /* AArch64_SABALv8i8_v8i16, AArch64_INS_SABAL: sabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABAv16i8, ARM64_INS_SABA: saba.16b $rd, $rn, $rm */ + +{ /* AArch64_SABAv16i8, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABAv2i32, ARM64_INS_SABA: saba.2s $rd, $rn, $rm */ + +{ /* AArch64_SABAv2i32, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABAv4i16, ARM64_INS_SABA: saba.4h $rd, $rn, $rm */ + +{ /* AArch64_SABAv4i16, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABAv4i32, ARM64_INS_SABA: saba.4s $rd, $rn, $rm */ + +{ /* AArch64_SABAv4i32, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABAv8i16, ARM64_INS_SABA: saba.8h $rd, $rn, $rm */ + +{ /* AArch64_SABAv8i16, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABAv8i8, ARM64_INS_SABA: saba.8b $rd, $rn, $rm */ + +{ /* AArch64_SABAv8i8, AArch64_INS_SABA: saba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDLv16i8_v8i16, ARM64_INS_SABDL2: sabdl2.8h $rd, $rn, $rm */ + +{ /* AArch64_SABDLv16i8_v8i16, AArch64_INS_SABDL2: sabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDLv2i32_v2i64, ARM64_INS_SABDL: sabdl.2d $rd, $rn, $rm */ + +{ /* AArch64_SABDLv2i32_v2i64, AArch64_INS_SABDL: sabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDLv4i16_v4i32, ARM64_INS_SABDL: sabdl.4s $rd, $rn, $rm */ + +{ /* AArch64_SABDLv4i16_v4i32, AArch64_INS_SABDL: sabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDLv4i32_v2i64, ARM64_INS_SABDL2: sabdl2.2d $rd, $rn, $rm */ + +{ /* AArch64_SABDLv4i32_v2i64, AArch64_INS_SABDL2: sabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDLv8i16_v4i32, ARM64_INS_SABDL2: sabdl2.4s $rd, $rn, $rm */ + +{ /* AArch64_SABDLv8i16_v4i32, AArch64_INS_SABDL2: sabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDLv8i8_v8i16, ARM64_INS_SABDL: sabdl.8h $rd, $rn, $rm */ + +{ /* AArch64_SABDLv8i8_v8i16, AArch64_INS_SABDL: sabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDv16i8, ARM64_INS_SABD: sabd.16b $rd, $rn, $rm| */ + +{ /* AArch64_SABD_ZPmZ_B, AArch64_INS_SABD: sabd */ + 0, + { 0 } +}, + +{ /* AArch64_SABD_ZPmZ_D, AArch64_INS_SABD: sabd */ + 0, + { 0 } +}, + +{ /* AArch64_SABD_ZPmZ_H, AArch64_INS_SABD: sabd */ + 0, + { 0 } +}, + +{ /* AArch64_SABD_ZPmZ_S, AArch64_INS_SABD: sabd */ + 0, + { 0 } +}, + +{ /* AArch64_SABDv16i8, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDv2i32, ARM64_INS_SABD: sabd.2s $rd, $rn, $rm| */ + +{ /* AArch64_SABDv2i32, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDv4i16, ARM64_INS_SABD: sabd.4h $rd, $rn, $rm| */ + +{ /* AArch64_SABDv4i16, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDv4i32, ARM64_INS_SABD: sabd.4s $rd, $rn, $rm| */ + +{ /* AArch64_SABDv4i32, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDv8i16, ARM64_INS_SABD: sabd.8h $rd, $rn, $rm| */ + +{ /* AArch64_SABDv8i16, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SABDv8i8, ARM64_INS_SABD: sabd.8b $rd, $rn, $rm| */ + +{ /* AArch64_SABDv8i8, AArch64_INS_SABD: sabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADALPv16i8_v8i16, ARM64_INS_SADALP: sadalp.8h $rd, $rn */ + +{ /* AArch64_SADALPv16i8_v8i16, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADALPv2i32_v1i64, ARM64_INS_SADALP: sadalp.1d $rd, $rn */ + +{ /* AArch64_SADALPv2i32_v1i64, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADALPv4i16_v2i32, ARM64_INS_SADALP: sadalp.2s $rd, $rn */ + +{ /* AArch64_SADALPv4i16_v2i32, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADALPv4i32_v2i64, ARM64_INS_SADALP: sadalp.2d $rd, $rn */ + +{ /* AArch64_SADALPv4i32_v2i64, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADALPv8i16_v4i32, ARM64_INS_SADALP: sadalp.4s $rd, $rn */ + +{ /* AArch64_SADALPv8i16_v4i32, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADALPv8i8_v4i16, ARM64_INS_SADALP: sadalp.4h $rd, $rn */ + +{ /* AArch64_SADALPv8i8_v4i16, AArch64_INS_SADALP: sadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLPv16i8_v8i16, ARM64_INS_SADDLP: saddlp.8h $rd, $rn */ + +{ /* AArch64_SADDLPv16i8_v8i16, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLPv2i32_v1i64, ARM64_INS_SADDLP: saddlp.1d $rd, $rn */ + +{ /* AArch64_SADDLPv2i32_v1i64, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLPv4i16_v2i32, ARM64_INS_SADDLP: saddlp.2s $rd, $rn */ + +{ /* AArch64_SADDLPv4i16_v2i32, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLPv4i32_v2i64, ARM64_INS_SADDLP: saddlp.2d $rd, $rn */ + +{ /* AArch64_SADDLPv4i32_v2i64, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLPv8i16_v4i32, ARM64_INS_SADDLP: saddlp.4s $rd, $rn */ + +{ /* AArch64_SADDLPv8i16_v4i32, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLPv8i8_v4i16, ARM64_INS_SADDLP: saddlp.4h $rd, $rn */ + +{ /* AArch64_SADDLPv8i8_v4i16, AArch64_INS_SADDLP: saddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLVv16i8v, ARM64_INS_SADDLV: saddlv.16b $rd, $rn */ + +{ /* AArch64_SADDLVv16i8v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SADDLVv4i16v, ARM64_INS_SADDLV: saddlv.4h $rd, $rn */ + +{ /* AArch64_SADDLVv4i16v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SADDLVv4i32v, ARM64_INS_SADDLV: saddlv.4s $rd, $rn */ + +{ /* AArch64_SADDLVv4i32v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SADDLVv8i16v, ARM64_INS_SADDLV: saddlv.8h $rd, $rn */ + +{ /* AArch64_SADDLVv8i16v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SADDLVv8i8v, ARM64_INS_SADDLV: saddlv.8b $rd, $rn */ + +{ /* AArch64_SADDLVv8i8v, AArch64_INS_SADDLV: saddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SADDLv16i8_v8i16, ARM64_INS_SADDL2: saddl2.8h $rd, $rn, $rm */ + +{ /* AArch64_SADDLv16i8_v8i16, AArch64_INS_SADDL2: saddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLv2i32_v2i64, ARM64_INS_SADDL: saddl.2d $rd, $rn, $rm */ + +{ /* AArch64_SADDLv2i32_v2i64, AArch64_INS_SADDL: saddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLv4i16_v4i32, ARM64_INS_SADDL: saddl.4s $rd, $rn, $rm */ + +{ /* AArch64_SADDLv4i16_v4i32, AArch64_INS_SADDL: saddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLv4i32_v2i64, ARM64_INS_SADDL2: saddl2.2d $rd, $rn, $rm */ + +{ /* AArch64_SADDLv4i32_v2i64, AArch64_INS_SADDL2: saddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLv8i16_v4i32, ARM64_INS_SADDL2: saddl2.4s $rd, $rn, $rm */ + +{ /* AArch64_SADDLv8i16_v4i32, AArch64_INS_SADDL2: saddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDLv8i8_v8i16, ARM64_INS_SADDL: saddl.8h $rd, $rn, $rm */ + +{ /* AArch64_SADDLv8i8_v8i16, AArch64_INS_SADDL: saddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDWv16i8_v8i16, ARM64_INS_SADDW2: saddw2.8h $rd, $rn, $rm */ + +{ /* AArch64_SADDV_VPZ_B, AArch64_INS_SADDV: saddv */ + 0, + { 0 } +}, + +{ /* AArch64_SADDV_VPZ_H, AArch64_INS_SADDV: saddv */ + 0, + { 0 } +}, + +{ /* AArch64_SADDV_VPZ_S, AArch64_INS_SADDV: saddv */ + 0, + { 0 } +}, + +{ /* AArch64_SADDWv16i8_v8i16, AArch64_INS_SADDW2: saddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDWv2i32_v2i64, ARM64_INS_SADDW: saddw.2d $rd, $rn, $rm */ + +{ /* AArch64_SADDWv2i32_v2i64, AArch64_INS_SADDW: saddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDWv4i16_v4i32, ARM64_INS_SADDW: saddw.4s $rd, $rn, $rm */ + +{ /* AArch64_SADDWv4i16_v4i32, AArch64_INS_SADDW: saddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDWv4i32_v2i64, ARM64_INS_SADDW2: saddw2.2d $rd, $rn, $rm */ + +{ /* AArch64_SADDWv4i32_v2i64, AArch64_INS_SADDW2: saddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDWv8i16_v4i32, ARM64_INS_SADDW2: saddw2.4s $rd, $rn, $rm */ + +{ /* AArch64_SADDWv8i16_v4i32, AArch64_INS_SADDW2: saddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SADDWv8i8_v8i16, ARM64_INS_SADDW: saddw.8h $rd, $rn, $rm */ + +{ /* AArch64_SADDWv8i8_v8i16, AArch64_INS_SADDW: saddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SBCSWr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */ + +{ /* AArch64_SBCSWr, AArch64_INS_NGCS: ngcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SBCSXr, ARM64_INS_SBCS: sbcs $rd, $rn, $rm */ + +{ /* AArch64_SBCSXr, AArch64_INS_NGCS: ngcs */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SBCWr, ARM64_INS_SBC: sbc $rd, $rn, $rm */ + +{ /* AArch64_SBCWr, AArch64_INS_NGC: ngc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SBCXr, ARM64_INS_SBC: sbc $rd, $rn, $rm */ + +{ /* AArch64_SBCXr, AArch64_INS_NGC: ngc */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SBFMWri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */ + +{ /* AArch64_SBFMWri, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SBFMXri, ARM64_INS_SBFM: sbfm $rd, $rn, $immr, $imms */ + +{ /* AArch64_SBFMXri, AArch64_INS_ASR: asr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SCVTFSWDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + +{ /* AArch64_SCVTFSWDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFSWSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + +{ /* AArch64_SCVTFSWHri, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFSWSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFSXDri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + +{ /* AArch64_SCVTFSXDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFSXSri, ARM64_INS_SCVTF: scvtf $rd, $rn, $scale */ + +{ /* AArch64_SCVTFSXHri, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFSXSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFUWDri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + +{ /* AArch64_SCVTFUWDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFUWSri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + +{ /* AArch64_SCVTFUWHri, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFUWSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFUXDri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + +{ /* AArch64_SCVTFUXDri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFUXSri, ARM64_INS_SCVTF: scvtf $rd, $rn */ + +{ /* AArch64_SCVTFUXHri, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFUXSri, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFd, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */ + +{ /* AArch64_SCVTF_ZPmZ_DtoD, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTF_ZPmZ_DtoH, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTF_ZPmZ_DtoS, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTF_ZPmZ_HtoH, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTF_ZPmZ_StoD, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTF_ZPmZ_StoH, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTF_ZPmZ_StoS, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFd, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFs, ARM64_INS_SCVTF: scvtf $rd, $rn, $imm */ + +{ /* AArch64_SCVTFh, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFs, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv1i32, ARM64_INS_SCVTF: scvtf $rd, $rn */ + +{ /* AArch64_SCVTFv1i16, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFv1i32, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv1i64, ARM64_INS_SCVTF: scvtf $rd, $rn */ + +{ /* AArch64_SCVTFv1i64, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv2f32, ARM64_INS_SCVTF: scvtf.2s $rd, $rn */ + +{ /* AArch64_SCVTFv2f32, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv2f64, ARM64_INS_SCVTF: scvtf.2d $rd, $rn */ + +{ /* AArch64_SCVTFv2f64, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv2i32_shift, ARM64_INS_SCVTF: scvtf.2s $rd, $rn, $imm */ + +{ /* AArch64_SCVTFv2i32_shift, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv2i64_shift, ARM64_INS_SCVTF: scvtf.2d $rd, $rn, $imm */ + +{ /* AArch64_SCVTFv2i64_shift, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv4f32, ARM64_INS_SCVTF: scvtf.4s $rd, $rn */ + +{ /* AArch64_SCVTFv4f16, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFv4f32, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0} }, -{ /* AArch64_SCVTFv4i32_shift, ARM64_INS_SCVTF: scvtf.4s $rd, $rn, $imm */ + +{ /* AArch64_SCVTFv4i16_shift, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFv4i32_shift, AArch64_INS_SCVTF: scvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SDIVWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + +{ /* AArch64_SCVTFv8f16, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SCVTFv8i16_shift, AArch64_INS_SCVTF: scvtf */ + 0, + { 0 } +}, + +{ /* AArch64_SDIVR_ZPmZ_D, AArch64_INS_SDIVR: sdivr */ + 0, + { 0 } +}, + +{ /* AArch64_SDIVR_ZPmZ_S, AArch64_INS_SDIVR: sdivr */ + 0, + { 0 } +}, + +{ /* AArch64_SDIVWr, AArch64_INS_SDIV: sdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SDIVXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + +{ /* AArch64_SDIVXr, AArch64_INS_SDIV: sdiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SDIV_IntWr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + +{ /* AArch64_SDIV_ZPmZ_D, AArch64_INS_SDIV: sdiv */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} + { 0 } }, -{ /* AArch64_SDIV_IntXr, ARM64_INS_SDIV: sdiv $rd, $rn, $rm */ + +{ /* AArch64_SDIV_ZPmZ_S, AArch64_INS_SDIV: sdiv */ 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} + { 0 } }, -{ /* AArch64_SHA1Crrr, ARM64_INS_SHA1C: sha1c.4s $rd, $rn, $rm */ + +{ /* AArch64_SDOT_ZZZI_D, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOT_ZZZI_S, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOT_ZZZ_D, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOT_ZZZ_S, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOTlanev16i8, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOTlanev8i8, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOTv16i8, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SDOTv8i8, AArch64_INS_SDOT: sdot */ + 0, + { 0 } +}, + +{ /* AArch64_SEL_PPPP, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_SEL_ZPZZ_B, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_SEL_ZPZZ_D, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_SEL_ZPZZ_H, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_SEL_ZPZZ_S, AArch64_INS_MOV: mov */ + 0, + { 0 } +}, + +{ /* AArch64_SETF16, AArch64_INS_SETF16: setf16 */ + 0, + { 0 } +}, + +{ /* AArch64_SETF8, AArch64_INS_SETF8: setf8 */ + 0, + { 0 } +}, + +{ /* AArch64_SETFFR, AArch64_INS_SETFFR: setffr */ + 0, + { 0 } +}, + +{ /* AArch64_SHA1Crrr, AArch64_INS_SHA1C: sha1c */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA1Hrr, ARM64_INS_SHA1H: sha1h $rd, $rn */ + +{ /* AArch64_SHA1Hrr, AArch64_INS_SHA1H: sha1h */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SHA1Mrrr, ARM64_INS_SHA1M: sha1m.4s $rd, $rn, $rm */ + +{ /* AArch64_SHA1Mrrr, AArch64_INS_SHA1M: sha1m */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA1Prrr, ARM64_INS_SHA1P: sha1p.4s $rd, $rn, $rm */ + +{ /* AArch64_SHA1Prrr, AArch64_INS_SHA1P: sha1p */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA1SU0rrr, ARM64_INS_SHA1SU0: sha1su0.4s $rd, $rn, $rm */ + +{ /* AArch64_SHA1SU0rrr, AArch64_INS_SHA1SU0: sha1su0 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA1SU1rr, ARM64_INS_SHA1SU1: sha1su1.4s $rd, $rn */ + +{ /* AArch64_SHA1SU1rr, AArch64_INS_SHA1SU1: sha1su1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA256H2rrr, ARM64_INS_SHA256H2: sha256h2.4s $rd, $rn, $rm */ + +{ /* AArch64_SHA256H2rrr, AArch64_INS_SHA256H2: sha256h2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA256Hrrr, ARM64_INS_SHA256H: sha256h.4s $rd, $rn, $rm */ + +{ /* AArch64_SHA256Hrrr, AArch64_INS_SHA256H: sha256h */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA256SU0rr, ARM64_INS_SHA256SU0: sha256su0.4s $rd, $rn */ + +{ /* AArch64_SHA256SU0rr, AArch64_INS_SHA256SU0: sha256su0 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHA256SU1rrr, ARM64_INS_SHA256SU1: sha256su1.4s $rd, $rn, $rm */ + +{ /* AArch64_SHA256SU1rrr, AArch64_INS_SHA256SU1: sha256su1 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SHADDv16i8, ARM64_INS_SHADD: shadd.16b $rd, $rn, $rm| */ + +{ /* AArch64_SHA512H, AArch64_INS_SHA512H: sha512h */ + 0, + { 0 } +}, + +{ /* AArch64_SHA512H2, AArch64_INS_SHA512H2: sha512h2 */ + 0, + { 0 } +}, + +{ /* AArch64_SHA512SU0, AArch64_INS_SHA512SU0: sha512su0 */ + 0, + { 0 } +}, + +{ /* AArch64_SHA512SU1, AArch64_INS_SHA512SU1: sha512su1 */ + 0, + { 0 } +}, + +{ /* AArch64_SHADDv16i8, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHADDv2i32, ARM64_INS_SHADD: shadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_SHADDv2i32, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHADDv4i16, ARM64_INS_SHADD: shadd.4h $rd, $rn, $rm| */ + +{ /* AArch64_SHADDv4i16, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHADDv4i32, ARM64_INS_SHADD: shadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_SHADDv4i32, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHADDv8i16, ARM64_INS_SHADD: shadd.8h $rd, $rn, $rm| */ + +{ /* AArch64_SHADDv8i16, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHADDv8i8, ARM64_INS_SHADD: shadd.8b $rd, $rn, $rm| */ + +{ /* AArch64_SHADDv8i8, AArch64_INS_SHADD: shadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLLv16i8, ARM64_INS_SHLL2: shll2.8h $rd, $rn, #8 */ + +{ /* AArch64_SHLLv16i8, AArch64_INS_SHLL2: shll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLLv2i32, ARM64_INS_SHLL: shll.2d $rd, $rn, #32 */ + +{ /* AArch64_SHLLv2i32, AArch64_INS_SHLL: shll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLLv4i16, ARM64_INS_SHLL: shll.4s $rd, $rn, #16 */ + +{ /* AArch64_SHLLv4i16, AArch64_INS_SHLL: shll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLLv4i32, ARM64_INS_SHLL2: shll2.2d $rd, $rn, #32 */ + +{ /* AArch64_SHLLv4i32, AArch64_INS_SHLL2: shll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLLv8i16, ARM64_INS_SHLL2: shll2.4s $rd, $rn, #16 */ + +{ /* AArch64_SHLLv8i16, AArch64_INS_SHLL2: shll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLLv8i8, ARM64_INS_SHLL: shll.8h $rd, $rn, #8 */ + +{ /* AArch64_SHLLv8i8, AArch64_INS_SHLL: shll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLd, ARM64_INS_SHL: shl $rd, $rn, $imm */ + +{ /* AArch64_SHLd, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv16i8_shift, ARM64_INS_SHL: shl.16b $rd, $rn, $imm */ + +{ /* AArch64_SHLv16i8_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv2i32_shift, ARM64_INS_SHL: shl.2s $rd, $rn, $imm */ + +{ /* AArch64_SHLv2i32_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv2i64_shift, ARM64_INS_SHL: shl.2d $rd, $rn, $imm */ + +{ /* AArch64_SHLv2i64_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv4i16_shift, ARM64_INS_SHL: shl.4h $rd, $rn, $imm */ + +{ /* AArch64_SHLv4i16_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv4i32_shift, ARM64_INS_SHL: shl.4s $rd, $rn, $imm */ + +{ /* AArch64_SHLv4i32_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv8i16_shift, ARM64_INS_SHL: shl.8h $rd, $rn, $imm */ + +{ /* AArch64_SHLv8i16_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHLv8i8_shift, ARM64_INS_SHL: shl.8b $rd, $rn, $imm */ + +{ /* AArch64_SHLv8i8_shift, AArch64_INS_SHL: shl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHRNv16i8_shift, ARM64_INS_SHRN2: shrn2.16b $rd, $rn, $imm */ + +{ /* AArch64_SHRNv16i8_shift, AArch64_INS_SHRN2: shrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHRNv2i32_shift, ARM64_INS_SHRN: shrn.2s $rd, $rn, $imm */ + +{ /* AArch64_SHRNv2i32_shift, AArch64_INS_SHRN: shrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHRNv4i16_shift, ARM64_INS_SHRN: shrn.4h $rd, $rn, $imm */ + +{ /* AArch64_SHRNv4i16_shift, AArch64_INS_SHRN: shrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHRNv4i32_shift, ARM64_INS_SHRN2: shrn2.4s $rd, $rn, $imm */ + +{ /* AArch64_SHRNv4i32_shift, AArch64_INS_SHRN2: shrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHRNv8i16_shift, ARM64_INS_SHRN2: shrn2.8h $rd, $rn, $imm */ + +{ /* AArch64_SHRNv8i16_shift, AArch64_INS_SHRN2: shrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHRNv8i8_shift, ARM64_INS_SHRN: shrn.8b $rd, $rn, $imm */ + +{ /* AArch64_SHRNv8i8_shift, AArch64_INS_SHRN: shrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHSUBv16i8, ARM64_INS_SHSUB: shsub.16b $rd, $rn, $rm| */ + +{ /* AArch64_SHSUBv16i8, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHSUBv2i32, ARM64_INS_SHSUB: shsub.2s $rd, $rn, $rm| */ + +{ /* AArch64_SHSUBv2i32, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHSUBv4i16, ARM64_INS_SHSUB: shsub.4h $rd, $rn, $rm| */ + +{ /* AArch64_SHSUBv4i16, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHSUBv4i32, ARM64_INS_SHSUB: shsub.4s $rd, $rn, $rm| */ + +{ /* AArch64_SHSUBv4i32, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHSUBv8i16, ARM64_INS_SHSUB: shsub.8h $rd, $rn, $rm| */ + +{ /* AArch64_SHSUBv8i16, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SHSUBv8i8, ARM64_INS_SHSUB: shsub.8b $rd, $rn, $rm| */ + +{ /* AArch64_SHSUBv8i8, AArch64_INS_SHSUB: shsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLId, ARM64_INS_SLI: sli $rd, $rn, $imm */ + +{ /* AArch64_SLId, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv16i8_shift, ARM64_INS_SLI: sli.16b $rd, $rn, $imm */ + +{ /* AArch64_SLIv16i8_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv2i32_shift, ARM64_INS_SLI: sli.2s $rd, $rn, $imm */ + +{ /* AArch64_SLIv2i32_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv2i64_shift, ARM64_INS_SLI: sli.2d $rd, $rn, $imm */ + +{ /* AArch64_SLIv2i64_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv4i16_shift, ARM64_INS_SLI: sli.4h $rd, $rn, $imm */ + +{ /* AArch64_SLIv4i16_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv4i32_shift, ARM64_INS_SLI: sli.4s $rd, $rn, $imm */ + +{ /* AArch64_SLIv4i32_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv8i16_shift, ARM64_INS_SLI: sli.8h $rd, $rn, $imm */ + +{ /* AArch64_SLIv8i16_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SLIv8i8_shift, ARM64_INS_SLI: sli.8b $rd, $rn, $imm */ + +{ /* AArch64_SLIv8i8_shift, AArch64_INS_SLI: sli */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0} }, -{ /* AArch64_SMADDLrrr, ARM64_INS_SMADDL: smaddl $rd, $rn, $rm, $ra */ + +{ /* AArch64_SM3PARTW1, AArch64_INS_SM3PARTW1: sm3partw1 */ + 0, + { 0 } +}, + +{ /* AArch64_SM3PARTW2, AArch64_INS_SM3PARTW2: sm3partw2 */ + 0, + { 0 } +}, + +{ /* AArch64_SM3SS1, AArch64_INS_SM3SS1: sm3ss1 */ + 0, + { 0 } +}, + +{ /* AArch64_SM3TT1A, AArch64_INS_SM3TT1A: sm3tt1a */ + 0, + { 0 } +}, + +{ /* AArch64_SM3TT1B, AArch64_INS_SM3TT1B: sm3tt1b */ + 0, + { 0 } +}, + +{ /* AArch64_SM3TT2A, AArch64_INS_SM3TT2A: sm3tt2a */ + 0, + { 0 } +}, + +{ /* AArch64_SM3TT2B, AArch64_INS_SM3TT2B: sm3tt2b */ + 0, + { 0 } +}, + +{ /* AArch64_SM4E, AArch64_INS_SM4E: sm4e */ + 0, + { 0 } +}, + +{ /* AArch64_SM4ENCKEY, AArch64_INS_SM4EKEY: sm4ekey */ + 0, + { 0 } +}, + +{ /* AArch64_SMADDLrrr, AArch64_INS_SMADDL: smaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXPv16i8, ARM64_INS_SMAXP: smaxp.16b $rd, $rn, $rm| */ + +{ /* AArch64_SMAXPv16i8, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXPv2i32, ARM64_INS_SMAXP: smaxp.2s $rd, $rn, $rm| */ + +{ /* AArch64_SMAXPv2i32, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXPv4i16, ARM64_INS_SMAXP: smaxp.4h $rd, $rn, $rm| */ + +{ /* AArch64_SMAXPv4i16, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXPv4i32, ARM64_INS_SMAXP: smaxp.4s $rd, $rn, $rm| */ + +{ /* AArch64_SMAXPv4i32, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXPv8i16, ARM64_INS_SMAXP: smaxp.8h $rd, $rn, $rm| */ + +{ /* AArch64_SMAXPv8i16, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXPv8i8, ARM64_INS_SMAXP: smaxp.8b $rd, $rn, $rm| */ + +{ /* AArch64_SMAXPv8i8, AArch64_INS_SMAXP: smaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXVv16i8v, ARM64_INS_SMAXV: smaxv.16b $rd, $rn */ + +{ /* AArch64_SMAXV_VPZ_B, AArch64_INS_SMAXV: smaxv */ + 0, + { 0 } +}, + +{ /* AArch64_SMAXV_VPZ_D, AArch64_INS_SMAXV: smaxv */ + 0, + { 0 } +}, + +{ /* AArch64_SMAXV_VPZ_H, AArch64_INS_SMAXV: smaxv */ + 0, + { 0 } +}, + +{ /* AArch64_SMAXV_VPZ_S, AArch64_INS_SMAXV: smaxv */ + 0, + { 0 } +}, + +{ /* AArch64_SMAXVv16i8v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXVv4i16v, ARM64_INS_SMAXV: smaxv.4h $rd, $rn */ + +{ /* AArch64_SMAXVv4i16v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXVv4i32v, ARM64_INS_SMAXV: smaxv.4s $rd, $rn */ + +{ /* AArch64_SMAXVv4i32v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXVv8i16v, ARM64_INS_SMAXV: smaxv.8h $rd, $rn */ + +{ /* AArch64_SMAXVv8i16v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXVv8i8v, ARM64_INS_SMAXV: smaxv.8b $rd, $rn */ + +{ /* AArch64_SMAXVv8i8v, AArch64_INS_SMAXV: smaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXv16i8, ARM64_INS_SMAX: smax.16b $rd, $rn, $rm| */ + +{ /* AArch64_SMAX_ZI_B, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZI_D, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZI_H, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZI_S, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZPmZ_B, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZPmZ_D, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZPmZ_H, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAX_ZPmZ_S, AArch64_INS_SMAX: smax */ + 0, + { 0 } +}, + +{ /* AArch64_SMAXv16i8, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXv2i32, ARM64_INS_SMAX: smax.2s $rd, $rn, $rm| */ + +{ /* AArch64_SMAXv2i32, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXv4i16, ARM64_INS_SMAX: smax.4h $rd, $rn, $rm| */ + +{ /* AArch64_SMAXv4i16, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXv4i32, ARM64_INS_SMAX: smax.4s $rd, $rn, $rm| */ + +{ /* AArch64_SMAXv4i32, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXv8i16, ARM64_INS_SMAX: smax.8h $rd, $rn, $rm| */ + +{ /* AArch64_SMAXv8i16, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMAXv8i8, ARM64_INS_SMAX: smax.8b $rd, $rn, $rm| */ + +{ /* AArch64_SMAXv8i8, AArch64_INS_SMAX: smax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMC, ARM64_INS_SMC: smc $imm */ + +{ /* AArch64_SMC, AArch64_INS_SMC: smc */ 0, { CS_AC_READ, 0 } }, -{ /* AArch64_SMINPv16i8, ARM64_INS_SMINP: sminp.16b $rd, $rn, $rm| */ + +{ /* AArch64_SMINPv16i8, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINPv2i32, ARM64_INS_SMINP: sminp.2s $rd, $rn, $rm| */ + +{ /* AArch64_SMINPv2i32, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINPv4i16, ARM64_INS_SMINP: sminp.4h $rd, $rn, $rm| */ + +{ /* AArch64_SMINPv4i16, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINPv4i32, ARM64_INS_SMINP: sminp.4s $rd, $rn, $rm| */ + +{ /* AArch64_SMINPv4i32, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINPv8i16, ARM64_INS_SMINP: sminp.8h $rd, $rn, $rm| */ + +{ /* AArch64_SMINPv8i16, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINPv8i8, ARM64_INS_SMINP: sminp.8b $rd, $rn, $rm| */ + +{ /* AArch64_SMINPv8i8, AArch64_INS_SMINP: sminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINVv16i8v, ARM64_INS_SMINV: sminv.16b $rd, $rn */ + +{ /* AArch64_SMINV_VPZ_B, AArch64_INS_SMINV: sminv */ + 0, + { 0 } +}, + +{ /* AArch64_SMINV_VPZ_D, AArch64_INS_SMINV: sminv */ + 0, + { 0 } +}, + +{ /* AArch64_SMINV_VPZ_H, AArch64_INS_SMINV: sminv */ + 0, + { 0 } +}, + +{ /* AArch64_SMINV_VPZ_S, AArch64_INS_SMINV: sminv */ + 0, + { 0 } +}, + +{ /* AArch64_SMINVv16i8v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMINVv4i16v, ARM64_INS_SMINV: sminv.4h $rd, $rn */ + +{ /* AArch64_SMINVv4i16v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMINVv4i32v, ARM64_INS_SMINV: sminv.4s $rd, $rn */ + +{ /* AArch64_SMINVv4i32v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMINVv8i16v, ARM64_INS_SMINV: sminv.8h $rd, $rn */ + +{ /* AArch64_SMINVv8i16v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMINVv8i8v, ARM64_INS_SMINV: sminv.8b $rd, $rn */ + +{ /* AArch64_SMINVv8i8v, AArch64_INS_SMINV: sminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SMINv16i8, ARM64_INS_SMIN: smin.16b $rd, $rn, $rm| */ + +{ /* AArch64_SMIN_ZI_B, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZI_D, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZI_H, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZI_S, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZPmZ_B, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZPmZ_D, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZPmZ_H, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMIN_ZPmZ_S, AArch64_INS_SMIN: smin */ + 0, + { 0 } +}, + +{ /* AArch64_SMINv16i8, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINv2i32, ARM64_INS_SMIN: smin.2s $rd, $rn, $rm| */ + +{ /* AArch64_SMINv2i32, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINv4i16, ARM64_INS_SMIN: smin.4h $rd, $rn, $rm| */ + +{ /* AArch64_SMINv4i16, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINv4i32, ARM64_INS_SMIN: smin.4s $rd, $rn, $rm| */ + +{ /* AArch64_SMINv4i32, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINv8i16, ARM64_INS_SMIN: smin.8h $rd, $rn, $rm| */ + +{ /* AArch64_SMINv8i16, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMINv8i8, ARM64_INS_SMIN: smin.8b $rd, $rn, $rm| */ + +{ /* AArch64_SMINv8i8, AArch64_INS_SMIN: smin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLALv16i8_v8i16, ARM64_INS_SMLAL2: smlal2.8h $rd, $rn, $rm */ + +{ /* AArch64_SMLALv16i8_v8i16, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLALv2i32_indexed, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLALv2i32_indexed, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLALv2i32_v2i64, ARM64_INS_SMLAL: smlal.2d $rd, $rn, $rm */ + +{ /* AArch64_SMLALv2i32_v2i64, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLALv4i16_indexed, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLALv4i16_indexed, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLALv4i16_v4i32, ARM64_INS_SMLAL: smlal.4s $rd, $rn, $rm */ + +{ /* AArch64_SMLALv4i16_v4i32, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLALv4i32_indexed, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLALv4i32_indexed, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLALv4i32_v2i64, ARM64_INS_SMLAL2: smlal2.2d $rd, $rn, $rm */ + +{ /* AArch64_SMLALv4i32_v2i64, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLALv8i16_indexed, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLALv8i16_indexed, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLALv8i16_v4i32, ARM64_INS_SMLAL2: smlal2.4s $rd, $rn, $rm */ + +{ /* AArch64_SMLALv8i16_v4i32, AArch64_INS_SMLAL2: smlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLALv8i8_v8i16, ARM64_INS_SMLAL: smlal.8h $rd, $rn, $rm */ + +{ /* AArch64_SMLALv8i8_v8i16, AArch64_INS_SMLAL: smlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLSLv16i8_v8i16, ARM64_INS_SMLSL2: smlsl2.8h $rd, $rn, $rm */ + +{ /* AArch64_SMLSLv16i8_v8i16, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLSLv2i32_indexed, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLSLv2i32_indexed, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLSLv2i32_v2i64, ARM64_INS_SMLSL: smlsl.2d $rd, $rn, $rm */ + +{ /* AArch64_SMLSLv2i32_v2i64, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLSLv4i16_indexed, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLSLv4i16_indexed, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLSLv4i16_v4i32, ARM64_INS_SMLSL: smlsl.4s $rd, $rn, $rm */ + +{ /* AArch64_SMLSLv4i16_v4i32, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLSLv4i32_indexed, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLSLv4i32_indexed, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLSLv4i32_v2i64, ARM64_INS_SMLSL2: smlsl2.2d $rd, $rn, $rm */ + +{ /* AArch64_SMLSLv4i32_v2i64, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLSLv8i16_indexed, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SMLSLv8i16_indexed, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SMLSLv8i16_v4i32, ARM64_INS_SMLSL2: smlsl2.4s $rd, $rn, $rm */ + +{ /* AArch64_SMLSLv8i16_v4i32, AArch64_INS_SMLSL2: smlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMLSLv8i8_v8i16, ARM64_INS_SMLSL: smlsl.8h $rd, $rn, $rm */ + +{ /* AArch64_SMLSLv8i8_v8i16, AArch64_INS_SMLSL: smlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMOVvi16to32, ARM64_INS_SMOV: smov.h $rd, $rn$idx */ + +{ /* AArch64_SMOVvi16to32, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMOVvi16to64, ARM64_INS_SMOV: smov.h $rd, $rn$idx */ + +{ /* AArch64_SMOVvi16to64, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMOVvi32to64, ARM64_INS_SMOV: smov.s $rd, $rn$idx */ + +{ /* AArch64_SMOVvi32to64, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMOVvi8to32, ARM64_INS_SMOV: smov.b $rd, $rn$idx */ + +{ /* AArch64_SMOVvi8to32, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMOVvi8to64, ARM64_INS_SMOV: smov.b $rd, $rn$idx */ + +{ /* AArch64_SMOVvi8to64, AArch64_INS_SMOV: smov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMSUBLrrr, ARM64_INS_SMSUBL: smsubl $rd, $rn, $rm, $ra */ + +{ /* AArch64_SMSUBLrrr, AArch64_INS_SMNEGL: smnegl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULHrr, ARM64_INS_SMULH: smulh $rd, $rn, $rm */ + +{ /* AArch64_SMULH_ZPmZ_B, AArch64_INS_SMULH: smulh */ + 0, + { 0 } +}, + +{ /* AArch64_SMULH_ZPmZ_D, AArch64_INS_SMULH: smulh */ + 0, + { 0 } +}, + +{ /* AArch64_SMULH_ZPmZ_H, AArch64_INS_SMULH: smulh */ + 0, + { 0 } +}, + +{ /* AArch64_SMULH_ZPmZ_S, AArch64_INS_SMULH: smulh */ + 0, + { 0 } +}, + +{ /* AArch64_SMULHrr, AArch64_INS_SMULH: smulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv16i8_v8i16, ARM64_INS_SMULL2: smull2.8h $rd, $rn, $rm */ + +{ /* AArch64_SMULLv16i8_v8i16, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv2i32_indexed, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SMULLv2i32_indexed, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv2i32_v2i64, ARM64_INS_SMULL: smull.2d $rd, $rn, $rm */ + +{ /* AArch64_SMULLv2i32_v2i64, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv4i16_indexed, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SMULLv4i16_indexed, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv4i16_v4i32, ARM64_INS_SMULL: smull.4s $rd, $rn, $rm */ + +{ /* AArch64_SMULLv4i16_v4i32, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv4i32_indexed, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SMULLv4i32_indexed, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv4i32_v2i64, ARM64_INS_SMULL2: smull2.2d $rd, $rn, $rm */ + +{ /* AArch64_SMULLv4i32_v2i64, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv8i16_indexed, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SMULLv8i16_indexed, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv8i16_v4i32, ARM64_INS_SMULL2: smull2.4s $rd, $rn, $rm */ + +{ /* AArch64_SMULLv8i16_v4i32, AArch64_INS_SMULL2: smull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SMULLv8i8_v8i16, ARM64_INS_SMULL: smull.8h $rd, $rn, $rm */ + +{ /* AArch64_SMULLv8i8_v8i16, AArch64_INS_SMULL: smull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv16i8, ARM64_INS_SQABS: sqabs.16b $rd, $rn */ + +{ /* AArch64_SPLICE_ZPZ_B, AArch64_INS_SPLICE: splice */ + 0, + { 0 } +}, + +{ /* AArch64_SPLICE_ZPZ_D, AArch64_INS_SPLICE: splice */ + 0, + { 0 } +}, + +{ /* AArch64_SPLICE_ZPZ_H, AArch64_INS_SPLICE: splice */ + 0, + { 0 } +}, + +{ /* AArch64_SPLICE_ZPZ_S, AArch64_INS_SPLICE: splice */ + 0, + { 0 } +}, + +{ /* AArch64_SQABSv16i8, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv1i16, ARM64_INS_SQABS: sqabs $rd, $rn */ + +{ /* AArch64_SQABSv1i16, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv1i32, ARM64_INS_SQABS: sqabs $rd, $rn */ + +{ /* AArch64_SQABSv1i32, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv1i64, ARM64_INS_SQABS: sqabs $rd, $rn */ + +{ /* AArch64_SQABSv1i64, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv1i8, ARM64_INS_SQABS: sqabs $rd, $rn */ + +{ /* AArch64_SQABSv1i8, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv2i32, ARM64_INS_SQABS: sqabs.2s $rd, $rn */ + +{ /* AArch64_SQABSv2i32, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv2i64, ARM64_INS_SQABS: sqabs.2d $rd, $rn */ + +{ /* AArch64_SQABSv2i64, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv4i16, ARM64_INS_SQABS: sqabs.4h $rd, $rn */ + +{ /* AArch64_SQABSv4i16, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv4i32, ARM64_INS_SQABS: sqabs.4s $rd, $rn */ + +{ /* AArch64_SQABSv4i32, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv8i16, ARM64_INS_SQABS: sqabs.8h $rd, $rn */ + +{ /* AArch64_SQABSv8i16, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQABSv8i8, ARM64_INS_SQABS: sqabs.8b $rd, $rn */ + +{ /* AArch64_SQABSv8i8, AArch64_INS_SQABS: sqabs */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv16i8, ARM64_INS_SQADD: sqadd.16b $rd, $rn, $rm| */ + +{ /* AArch64_SQADD_ZI_B, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZI_D, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZI_H, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZI_S, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZZZ_B, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZZZ_D, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZZZ_H, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADD_ZZZ_S, AArch64_INS_SQADD: sqadd */ + 0, + { 0 } +}, + +{ /* AArch64_SQADDv16i8, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv1i16, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + +{ /* AArch64_SQADDv1i16, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv1i32, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + +{ /* AArch64_SQADDv1i32, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv1i64, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + +{ /* AArch64_SQADDv1i64, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv1i8, ARM64_INS_SQADD: sqadd $rd, $rn, $rm */ + +{ /* AArch64_SQADDv1i8, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv2i32, ARM64_INS_SQADD: sqadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_SQADDv2i32, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv2i64, ARM64_INS_SQADD: sqadd.2d $rd, $rn, $rm| */ + +{ /* AArch64_SQADDv2i64, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv4i16, ARM64_INS_SQADD: sqadd.4h $rd, $rn, $rm| */ + +{ /* AArch64_SQADDv4i16, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv4i32, ARM64_INS_SQADD: sqadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_SQADDv4i32, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv8i16, ARM64_INS_SQADD: sqadd.8h $rd, $rn, $rm| */ + +{ /* AArch64_SQADDv8i16, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQADDv8i8, ARM64_INS_SQADD: sqadd.8b $rd, $rn, $rm| */ + +{ /* AArch64_SQADDv8i8, AArch64_INS_SQADD: sqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLALi16, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */ + +{ /* AArch64_SQDECB_XPiI, AArch64_INS_SQDECB: sqdecb */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECB_XPiWdI, AArch64_INS_SQDECB: sqdecb */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECD_XPiI, AArch64_INS_SQDECD: sqdecd */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECD_XPiWdI, AArch64_INS_SQDECD: sqdecd */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECD_ZPiI, AArch64_INS_SQDECD: sqdecd */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECH_XPiI, AArch64_INS_SQDECH: sqdech */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECH_XPiWdI, AArch64_INS_SQDECH: sqdech */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECH_ZPiI, AArch64_INS_SQDECH: sqdech */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XPWd_B, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XPWd_D, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XPWd_H, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XPWd_S, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XP_B, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XP_D, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XP_H, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_XP_S, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_ZP_D, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_ZP_H, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECP_ZP_S, AArch64_INS_SQDECP: sqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECW_XPiI, AArch64_INS_SQDECW: sqdecw */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECW_XPiWdI, AArch64_INS_SQDECW: sqdecw */ + 0, + { 0 } +}, + +{ /* AArch64_SQDECW_ZPiI, AArch64_INS_SQDECW: sqdecw */ + 0, + { 0 } +}, + +{ /* AArch64_SQDMLALi16, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLALi32, ARM64_INS_SQDMLAL: sqdmlal $rd, $rn, $rm */ + +{ /* AArch64_SQDMLALi32, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLALv1i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLALv1i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLALv1i64_indexed, ARM64_INS_SQDMLAL: sqdmlal.s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLALv1i64_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLALv2i32_indexed, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLALv2i32_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLALv2i32_v2i64, ARM64_INS_SQDMLAL: sqdmlal.2d $rd, $rn, $rm */ + +{ /* AArch64_SQDMLALv2i32_v2i64, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLALv4i16_indexed, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLALv4i16_indexed, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLALv4i16_v4i32, ARM64_INS_SQDMLAL: sqdmlal.4s $rd, $rn, $rm */ + +{ /* AArch64_SQDMLALv4i16_v4i32, AArch64_INS_SQDMLAL: sqdmlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLALv4i32_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLALv4i32_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLALv4i32_v2i64, ARM64_INS_SQDMLAL2: sqdmlal2.2d $rd, $rn, $rm */ + +{ /* AArch64_SQDMLALv4i32_v2i64, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLALv8i16_indexed, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLALv8i16_indexed, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLALv8i16_v4i32, ARM64_INS_SQDMLAL2: sqdmlal2.4s $rd, $rn, $rm */ + +{ /* AArch64_SQDMLALv8i16_v4i32, AArch64_INS_SQDMLAL2: sqdmlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLSLi16, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */ + +{ /* AArch64_SQDMLSLi16, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLSLi32, ARM64_INS_SQDMLSL: sqdmlsl $rd, $rn, $rm */ + +{ /* AArch64_SQDMLSLi32, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLSLv1i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLSLv1i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLSLv1i64_indexed, ARM64_INS_SQDMLSL: sqdmlsl.s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLSLv1i64_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLSLv2i32_indexed, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLSLv2i32_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLSLv2i32_v2i64, ARM64_INS_SQDMLSL: sqdmlsl.2d $rd, $rn, $rm */ + +{ /* AArch64_SQDMLSLv2i32_v2i64, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLSLv4i16_indexed, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLSLv4i16_indexed, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLSLv4i16_v4i32, ARM64_INS_SQDMLSL: sqdmlsl.4s $rd, $rn, $rm */ + +{ /* AArch64_SQDMLSLv4i16_v4i32, AArch64_INS_SQDMLSL: sqdmlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLSLv4i32_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLSLv4i32_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLSLv4i32_v2i64, ARM64_INS_SQDMLSL2: sqdmlsl2.2d $rd, $rn, $rm */ + +{ /* AArch64_SQDMLSLv4i32_v2i64, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMLSLv8i16_indexed, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMLSLv8i16_indexed, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQDMLSLv8i16_v4i32, ARM64_INS_SQDMLSL2: sqdmlsl2.4s $rd, $rn, $rm */ + +{ /* AArch64_SQDMLSLv8i16_v4i32, AArch64_INS_SQDMLSL2: sqdmlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv1i16, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */ + +{ /* AArch64_SQDMULHv1i16, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv1i16_indexed, ARM64_INS_SQDMULH: sqdmulh.h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULHv1i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv1i32, ARM64_INS_SQDMULH: sqdmulh $rd, $rn, $rm */ + +{ /* AArch64_SQDMULHv1i32, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv1i32_indexed, ARM64_INS_SQDMULH: sqdmulh.s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULHv1i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv2i32, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm| */ + +{ /* AArch64_SQDMULHv2i32, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv2i32_indexed, ARM64_INS_SQDMULH: sqdmulh.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULHv2i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv4i16, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm| */ + +{ /* AArch64_SQDMULHv4i16, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv4i16_indexed, ARM64_INS_SQDMULH: sqdmulh.4h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULHv4i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv4i32, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm| */ + +{ /* AArch64_SQDMULHv4i32, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv4i32_indexed, ARM64_INS_SQDMULH: sqdmulh.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULHv4i32_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv8i16, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm| */ + +{ /* AArch64_SQDMULHv8i16, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULHv8i16_indexed, ARM64_INS_SQDMULH: sqdmulh.8h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULHv8i16_indexed, AArch64_INS_SQDMULH: sqdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLi16, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */ + +{ /* AArch64_SQDMULLi16, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLi32, ARM64_INS_SQDMULL: sqdmull $rd, $rn, $rm */ + +{ /* AArch64_SQDMULLi32, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv1i32_indexed, ARM64_INS_SQDMULL: sqdmull.h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULLv1i32_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv1i64_indexed, ARM64_INS_SQDMULL: sqdmull.s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULLv1i64_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv2i32_indexed, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULLv2i32_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv2i32_v2i64, ARM64_INS_SQDMULL: sqdmull.2d $rd, $rn, $rm */ + +{ /* AArch64_SQDMULLv2i32_v2i64, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv4i16_indexed, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULLv4i16_indexed, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv4i16_v4i32, ARM64_INS_SQDMULL: sqdmull.4s $rd, $rn, $rm */ + +{ /* AArch64_SQDMULLv4i16_v4i32, AArch64_INS_SQDMULL: sqdmull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv4i32_indexed, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULLv4i32_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv4i32_v2i64, ARM64_INS_SQDMULL2: sqdmull2.2d $rd, $rn, $rm */ + +{ /* AArch64_SQDMULLv4i32_v2i64, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv8i16_indexed, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQDMULLv8i16_indexed, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQDMULLv8i16_v4i32, ARM64_INS_SQDMULL2: sqdmull2.4s $rd, $rn, $rm */ + +{ /* AArch64_SQDMULLv8i16_v4i32, AArch64_INS_SQDMULL2: sqdmull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv16i8, ARM64_INS_SQNEG: sqneg.16b $rd, $rn */ + +{ /* AArch64_SQINCB_XPiI, AArch64_INS_SQINCB: sqincb */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCB_XPiWdI, AArch64_INS_SQINCB: sqincb */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCD_XPiI, AArch64_INS_SQINCD: sqincd */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCD_XPiWdI, AArch64_INS_SQINCD: sqincd */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCD_ZPiI, AArch64_INS_SQINCD: sqincd */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCH_XPiI, AArch64_INS_SQINCH: sqinch */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCH_XPiWdI, AArch64_INS_SQINCH: sqinch */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCH_ZPiI, AArch64_INS_SQINCH: sqinch */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XPWd_B, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XPWd_D, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XPWd_H, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XPWd_S, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XP_B, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XP_D, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XP_H, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_XP_S, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_ZP_D, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_ZP_H, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCP_ZP_S, AArch64_INS_SQINCP: sqincp */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCW_XPiI, AArch64_INS_SQINCW: sqincw */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCW_XPiWdI, AArch64_INS_SQINCW: sqincw */ + 0, + { 0 } +}, + +{ /* AArch64_SQINCW_ZPiI, AArch64_INS_SQINCW: sqincw */ + 0, + { 0 } +}, + +{ /* AArch64_SQNEGv16i8, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv1i16, ARM64_INS_SQNEG: sqneg $rd, $rn */ + +{ /* AArch64_SQNEGv1i16, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv1i32, ARM64_INS_SQNEG: sqneg $rd, $rn */ + +{ /* AArch64_SQNEGv1i32, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv1i64, ARM64_INS_SQNEG: sqneg $rd, $rn */ + +{ /* AArch64_SQNEGv1i64, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv1i8, ARM64_INS_SQNEG: sqneg $rd, $rn */ + +{ /* AArch64_SQNEGv1i8, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv2i32, ARM64_INS_SQNEG: sqneg.2s $rd, $rn */ + +{ /* AArch64_SQNEGv2i32, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv2i64, ARM64_INS_SQNEG: sqneg.2d $rd, $rn */ + +{ /* AArch64_SQNEGv2i64, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv4i16, ARM64_INS_SQNEG: sqneg.4h $rd, $rn */ + +{ /* AArch64_SQNEGv4i16, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv4i32, ARM64_INS_SQNEG: sqneg.4s $rd, $rn */ + +{ /* AArch64_SQNEGv4i32, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv8i16, ARM64_INS_SQNEG: sqneg.8h $rd, $rn */ + +{ /* AArch64_SQNEGv8i16, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQNEGv8i8, ARM64_INS_SQNEG: sqneg.8b $rd, $rn */ + +{ /* AArch64_SQNEGv8i8, AArch64_INS_SQNEG: sqneg */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv1i16, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */ + +{ /* AArch64_SQRDMLAHi16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHi32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv1i16, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv1i32, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv2i32, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv2i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv4i16, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv4i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv4i32, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv4i32_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv8i16, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLAHv8i16_indexed, AArch64_INS_SQRDMLAH: sqrdmlah */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHi16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHi32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv1i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv1i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv2i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv2i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv4i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv4i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv4i32, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv4i32_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv8i16, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMLSHv8i16_indexed, AArch64_INS_SQRDMLSH: sqrdmlsh */ + 0, + { 0 } +}, + +{ /* AArch64_SQRDMULHv1i16, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv1i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQRDMULHv1i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQRDMULHv1i32, ARM64_INS_SQRDMULH: sqrdmulh $rd, $rn, $rm */ + +{ /* AArch64_SQRDMULHv1i32, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv1i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQRDMULHv1i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQRDMULHv2i32, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm| */ + +{ /* AArch64_SQRDMULHv2i32, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv2i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.2s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQRDMULHv2i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQRDMULHv4i16, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm| */ + +{ /* AArch64_SQRDMULHv4i16, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv4i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQRDMULHv4i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQRDMULHv4i32, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm| */ + +{ /* AArch64_SQRDMULHv4i32, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv4i32_indexed, ARM64_INS_SQRDMULH: sqrdmulh.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_SQRDMULHv4i32_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQRDMULHv8i16, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm| */ + +{ /* AArch64_SQRDMULHv8i16, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRDMULHv8i16_indexed, ARM64_INS_SQRDMULH: sqrdmulh.8h $rd, $rn, $rm$idx */ + +{ /* AArch64_SQRDMULHv8i16_indexed, AArch64_INS_SQRDMULH: sqrdmulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SQRSHLv16i8, ARM64_INS_SQRSHL: sqrshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv16i8, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv1i16, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + +{ /* AArch64_SQRSHLv1i16, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv1i32, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + +{ /* AArch64_SQRSHLv1i32, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv1i64, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + +{ /* AArch64_SQRSHLv1i64, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv1i8, ARM64_INS_SQRSHL: sqrshl $rd, $rn, $rm */ + +{ /* AArch64_SQRSHLv1i8, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv2i32, ARM64_INS_SQRSHL: sqrshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv2i32, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv2i64, ARM64_INS_SQRSHL: sqrshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv2i64, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv4i16, ARM64_INS_SQRSHL: sqrshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv4i16, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv4i32, ARM64_INS_SQRSHL: sqrshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv4i32, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv8i16, ARM64_INS_SQRSHL: sqrshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv8i16, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHLv8i8, ARM64_INS_SQRSHL: sqrshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_SQRSHLv8i8, AArch64_INS_SQRSHL: sqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNb, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNb, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNh, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNh, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNs, ARM64_INS_SQRSHRN: sqrshrn $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNs, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNv16i8_shift, ARM64_INS_SQRSHRN2: sqrshrn2.16b $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNv16i8_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNv2i32_shift, ARM64_INS_SQRSHRN: sqrshrn.2s $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNv2i32_shift, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNv4i16_shift, ARM64_INS_SQRSHRN: sqrshrn.4h $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNv4i16_shift, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNv4i32_shift, ARM64_INS_SQRSHRN2: sqrshrn2.4s $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNv4i32_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNv8i16_shift, ARM64_INS_SQRSHRN2: sqrshrn2.8h $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNv8i16_shift, AArch64_INS_SQRSHRN2: sqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRNv8i8_shift, ARM64_INS_SQRSHRN: sqrshrn.8b $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRNv8i8_shift, AArch64_INS_SQRSHRN: sqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNb, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNb, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNh, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNh, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNs, ARM64_INS_SQRSHRUN: sqrshrun $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNs, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNv16i8_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.16b $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNv16i8_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNv2i32_shift, ARM64_INS_SQRSHRUN: sqrshrun.2s $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNv2i32_shift, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNv4i16_shift, ARM64_INS_SQRSHRUN: sqrshrun.4h $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNv4i16_shift, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNv4i32_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.4s $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNv4i32_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNv8i16_shift, ARM64_INS_SQRSHRUN2: sqrshrun2.8h $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNv8i16_shift, AArch64_INS_SQRSHRUN2: sqrshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQRSHRUNv8i8_shift, ARM64_INS_SQRSHRUN: sqrshrun.8b $rd, $rn, $imm */ + +{ /* AArch64_SQRSHRUNv8i8_shift, AArch64_INS_SQRSHRUN: sqrshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUb, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUb, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUd, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUd, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUh, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUh, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUs, ARM64_INS_SQSHLU: sqshlu $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUs, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv16i8_shift, ARM64_INS_SQSHLU: sqshlu.16b $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv16i8_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv2i32_shift, ARM64_INS_SQSHLU: sqshlu.2s $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv2i32_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv2i64_shift, ARM64_INS_SQSHLU: sqshlu.2d $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv2i64_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv4i16_shift, ARM64_INS_SQSHLU: sqshlu.4h $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv4i16_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv4i32_shift, ARM64_INS_SQSHLU: sqshlu.4s $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv4i32_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv8i16_shift, ARM64_INS_SQSHLU: sqshlu.8h $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv8i16_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLUv8i8_shift, ARM64_INS_SQSHLU: sqshlu.8b $rd, $rn, $imm */ + +{ /* AArch64_SQSHLUv8i8_shift, AArch64_INS_SQSHLU: sqshlu */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLb, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + +{ /* AArch64_SQSHLb, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLd, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + +{ /* AArch64_SQSHLd, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLh, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + +{ /* AArch64_SQSHLh, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLs, ARM64_INS_SQSHL: sqshl $rd, $rn, $imm */ + +{ /* AArch64_SQSHLs, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv16i8, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv16i8, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv16i8_shift, ARM64_INS_SQSHL: sqshl.16b $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv16i8_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv1i16, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + +{ /* AArch64_SQSHLv1i16, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv1i32, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + +{ /* AArch64_SQSHLv1i32, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv1i64, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + +{ /* AArch64_SQSHLv1i64, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv1i8, ARM64_INS_SQSHL: sqshl $rd, $rn, $rm */ + +{ /* AArch64_SQSHLv1i8, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv2i32, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv2i32, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv2i32_shift, ARM64_INS_SQSHL: sqshl.2s $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv2i32_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv2i64, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv2i64, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv2i64_shift, ARM64_INS_SQSHL: sqshl.2d $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv2i64_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv4i16, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv4i16, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv4i16_shift, ARM64_INS_SQSHL: sqshl.4h $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv4i16_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv4i32, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv4i32, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv4i32_shift, ARM64_INS_SQSHL: sqshl.4s $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv4i32_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv8i16, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv8i16, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv8i16_shift, ARM64_INS_SQSHL: sqshl.8h $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv8i16_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv8i8, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_SQSHLv8i8, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHLv8i8_shift, ARM64_INS_SQSHL: sqshl.8b $rd, $rn, $imm */ + +{ /* AArch64_SQSHLv8i8_shift, AArch64_INS_SQSHL: sqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNb, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNb, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNh, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNh, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNs, ARM64_INS_SQSHRN: sqshrn $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNs, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNv16i8_shift, ARM64_INS_SQSHRN2: sqshrn2.16b $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNv16i8_shift, AArch64_INS_SQSHRN2: sqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNv2i32_shift, ARM64_INS_SQSHRN: sqshrn.2s $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNv2i32_shift, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNv4i16_shift, ARM64_INS_SQSHRN: sqshrn.4h $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNv4i16_shift, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNv4i32_shift, ARM64_INS_SQSHRN2: sqshrn2.4s $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNv4i32_shift, AArch64_INS_SQSHRN2: sqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNv8i16_shift, ARM64_INS_SQSHRN2: sqshrn2.8h $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNv8i16_shift, AArch64_INS_SQSHRN2: sqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRNv8i8_shift, ARM64_INS_SQSHRN: sqshrn.8b $rd, $rn, $imm */ + +{ /* AArch64_SQSHRNv8i8_shift, AArch64_INS_SQSHRN: sqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNb, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNb, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNh, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNh, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNs, ARM64_INS_SQSHRUN: sqshrun $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNs, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNv16i8_shift, ARM64_INS_SQSHRUN2: sqshrun2.16b $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNv16i8_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNv2i32_shift, ARM64_INS_SQSHRUN: sqshrun.2s $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNv2i32_shift, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNv4i16_shift, ARM64_INS_SQSHRUN: sqshrun.4h $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNv4i16_shift, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNv4i32_shift, ARM64_INS_SQSHRUN2: sqshrun2.4s $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNv4i32_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNv8i16_shift, ARM64_INS_SQSHRUN2: sqshrun2.8h $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNv8i16_shift, AArch64_INS_SQSHRUN2: sqshrun2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSHRUNv8i8_shift, ARM64_INS_SQSHRUN: sqshrun.8b $rd, $rn, $imm */ + +{ /* AArch64_SQSHRUNv8i8_shift, AArch64_INS_SQSHRUN: sqshrun */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv16i8, ARM64_INS_SQSUB: sqsub.16b $rd, $rn, $rm| */ + +{ /* AArch64_SQSUB_ZI_B, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZI_D, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZI_H, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZI_S, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZZZ_B, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZZZ_D, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZZZ_H, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUB_ZZZ_S, AArch64_INS_SQSUB: sqsub */ + 0, + { 0 } +}, + +{ /* AArch64_SQSUBv16i8, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv1i16, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + +{ /* AArch64_SQSUBv1i16, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv1i32, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + +{ /* AArch64_SQSUBv1i32, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv1i64, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + +{ /* AArch64_SQSUBv1i64, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv1i8, ARM64_INS_SQSUB: sqsub $rd, $rn, $rm */ + +{ /* AArch64_SQSUBv1i8, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv2i32, ARM64_INS_SQSUB: sqsub.2s $rd, $rn, $rm| */ + +{ /* AArch64_SQSUBv2i32, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv2i64, ARM64_INS_SQSUB: sqsub.2d $rd, $rn, $rm| */ + +{ /* AArch64_SQSUBv2i64, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv4i16, ARM64_INS_SQSUB: sqsub.4h $rd, $rn, $rm| */ + +{ /* AArch64_SQSUBv4i16, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv4i32, ARM64_INS_SQSUB: sqsub.4s $rd, $rn, $rm| */ + +{ /* AArch64_SQSUBv4i32, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv8i16, ARM64_INS_SQSUB: sqsub.8h $rd, $rn, $rm| */ + +{ /* AArch64_SQSUBv8i16, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQSUBv8i8, ARM64_INS_SQSUB: sqsub.8b $rd, $rn, $rm| */ + +{ /* AArch64_SQSUBv8i8, AArch64_INS_SQSUB: sqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv16i8, ARM64_INS_SQXTN2: sqxtn2.16b $rd, $rn */ + +{ /* AArch64_SQXTNv16i8, AArch64_INS_SQXTN2: sqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv1i16, ARM64_INS_SQXTN: sqxtn $rd, $rn */ + +{ /* AArch64_SQXTNv1i16, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv1i32, ARM64_INS_SQXTN: sqxtn $rd, $rn */ + +{ /* AArch64_SQXTNv1i32, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv1i8, ARM64_INS_SQXTN: sqxtn $rd, $rn */ + +{ /* AArch64_SQXTNv1i8, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv2i32, ARM64_INS_SQXTN: sqxtn.2s $rd, $rn */ + +{ /* AArch64_SQXTNv2i32, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv4i16, ARM64_INS_SQXTN: sqxtn.4h $rd, $rn */ + +{ /* AArch64_SQXTNv4i16, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv4i32, ARM64_INS_SQXTN2: sqxtn2.4s $rd, $rn */ + +{ /* AArch64_SQXTNv4i32, AArch64_INS_SQXTN2: sqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv8i16, ARM64_INS_SQXTN2: sqxtn2.8h $rd, $rn */ + +{ /* AArch64_SQXTNv8i16, AArch64_INS_SQXTN2: sqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTNv8i8, ARM64_INS_SQXTN: sqxtn.8b $rd, $rn */ + +{ /* AArch64_SQXTNv8i8, AArch64_INS_SQXTN: sqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv16i8, ARM64_INS_SQXTUN2: sqxtun2.16b $rd, $rn */ + +{ /* AArch64_SQXTUNv16i8, AArch64_INS_SQXTUN2: sqxtun2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv1i16, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ + +{ /* AArch64_SQXTUNv1i16, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv1i32, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ + +{ /* AArch64_SQXTUNv1i32, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv1i8, ARM64_INS_SQXTUN: sqxtun $rd, $rn */ + +{ /* AArch64_SQXTUNv1i8, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv2i32, ARM64_INS_SQXTUN: sqxtun.2s $rd, $rn */ + +{ /* AArch64_SQXTUNv2i32, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv4i16, ARM64_INS_SQXTUN: sqxtun.4h $rd, $rn */ + +{ /* AArch64_SQXTUNv4i16, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv4i32, ARM64_INS_SQXTUN2: sqxtun2.4s $rd, $rn */ + +{ /* AArch64_SQXTUNv4i32, AArch64_INS_SQXTUN2: sqxtun2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv8i16, ARM64_INS_SQXTUN2: sqxtun2.8h $rd, $rn */ + +{ /* AArch64_SQXTUNv8i16, AArch64_INS_SQXTUN2: sqxtun2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SQXTUNv8i8, ARM64_INS_SQXTUN: sqxtun.8b $rd, $rn */ + +{ /* AArch64_SQXTUNv8i8, AArch64_INS_SQXTUN: sqxtun */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_SRHADDv16i8, ARM64_INS_SRHADD: srhadd.16b $rd, $rn, $rm| */ + +{ /* AArch64_SRHADDv16i8, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRHADDv2i32, ARM64_INS_SRHADD: srhadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_SRHADDv2i32, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRHADDv4i16, ARM64_INS_SRHADD: srhadd.4h $rd, $rn, $rm| */ + +{ /* AArch64_SRHADDv4i16, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRHADDv4i32, ARM64_INS_SRHADD: srhadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_SRHADDv4i32, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRHADDv8i16, ARM64_INS_SRHADD: srhadd.8h $rd, $rn, $rm| */ + +{ /* AArch64_SRHADDv8i16, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRHADDv8i8, ARM64_INS_SRHADD: srhadd.8b $rd, $rn, $rm| */ + +{ /* AArch64_SRHADDv8i8, AArch64_INS_SRHADD: srhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRId, ARM64_INS_SRI: sri $rd, $rn, $imm */ + +{ /* AArch64_SRId, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv16i8_shift, ARM64_INS_SRI: sri.16b $rd, $rn, $imm */ + +{ /* AArch64_SRIv16i8_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv2i32_shift, ARM64_INS_SRI: sri.2s $rd, $rn, $imm */ + +{ /* AArch64_SRIv2i32_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv2i64_shift, ARM64_INS_SRI: sri.2d $rd, $rn, $imm */ + +{ /* AArch64_SRIv2i64_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv4i16_shift, ARM64_INS_SRI: sri.4h $rd, $rn, $imm */ + +{ /* AArch64_SRIv4i16_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv4i32_shift, ARM64_INS_SRI: sri.4s $rd, $rn, $imm */ + +{ /* AArch64_SRIv4i32_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv8i16_shift, ARM64_INS_SRI: sri.8h $rd, $rn, $imm */ + +{ /* AArch64_SRIv8i16_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRIv8i8_shift, ARM64_INS_SRI: sri.8b $rd, $rn, $imm */ + +{ /* AArch64_SRIv8i8_shift, AArch64_INS_SRI: sri */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv16i8, ARM64_INS_SRSHL: srshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv16i8, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv1i64, ARM64_INS_SRSHL: srshl $rd, $rn, $rm */ + +{ /* AArch64_SRSHLv1i64, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv2i32, ARM64_INS_SRSHL: srshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv2i32, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv2i64, ARM64_INS_SRSHL: srshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv2i64, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv4i16, ARM64_INS_SRSHL: srshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv4i16, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv4i32, ARM64_INS_SRSHL: srshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv4i32, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv8i16, ARM64_INS_SRSHL: srshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv8i16, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHLv8i8, ARM64_INS_SRSHL: srshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_SRSHLv8i8, AArch64_INS_SRSHL: srshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRd, ARM64_INS_SRSHR: srshr $rd, $rn, $imm */ + +{ /* AArch64_SRSHRd, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv16i8_shift, ARM64_INS_SRSHR: srshr.16b $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv16i8_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv2i32_shift, ARM64_INS_SRSHR: srshr.2s $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv2i32_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv2i64_shift, ARM64_INS_SRSHR: srshr.2d $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv2i64_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv4i16_shift, ARM64_INS_SRSHR: srshr.4h $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv4i16_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv4i32_shift, ARM64_INS_SRSHR: srshr.4s $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv4i32_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv8i16_shift, ARM64_INS_SRSHR: srshr.8h $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv8i16_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSHRv8i8_shift, ARM64_INS_SRSHR: srshr.8b $rd, $rn, $imm */ + +{ /* AArch64_SRSHRv8i8_shift, AArch64_INS_SRSHR: srshr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAd, ARM64_INS_SRSRA: srsra $rd, $rn, $imm */ + +{ /* AArch64_SRSRAd, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv16i8_shift, ARM64_INS_SRSRA: srsra.16b $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv16i8_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv2i32_shift, ARM64_INS_SRSRA: srsra.2s $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv2i32_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv2i64_shift, ARM64_INS_SRSRA: srsra.2d $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv2i64_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv4i16_shift, ARM64_INS_SRSRA: srsra.4h $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv4i16_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv4i32_shift, ARM64_INS_SRSRA: srsra.4s $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv4i32_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv8i16_shift, ARM64_INS_SRSRA: srsra.8h $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv8i16_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SRSRAv8i8_shift, ARM64_INS_SRSRA: srsra.8b $rd, $rn, $imm */ + +{ /* AArch64_SRSRAv8i8_shift, AArch64_INS_SRSRA: srsra */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLLv16i8_shift, ARM64_INS_SSHLL2: sshll2.8h $rd, $rn, $imm */ + +{ /* AArch64_SSHLLv16i8_shift, AArch64_INS_SSHLL2: sshll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLLv2i32_shift, ARM64_INS_SSHLL: sshll.2d $rd, $rn, $imm */ + +{ /* AArch64_SSHLLv2i32_shift, AArch64_INS_SSHLL: sshll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLLv4i16_shift, ARM64_INS_SSHLL: sshll.4s $rd, $rn, $imm */ + +{ /* AArch64_SSHLLv4i16_shift, AArch64_INS_SSHLL: sshll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLLv4i32_shift, ARM64_INS_SSHLL2: sshll2.2d $rd, $rn, $imm */ + +{ /* AArch64_SSHLLv4i32_shift, AArch64_INS_SSHLL2: sshll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLLv8i16_shift, ARM64_INS_SSHLL2: sshll2.4s $rd, $rn, $imm */ + +{ /* AArch64_SSHLLv8i16_shift, AArch64_INS_SSHLL2: sshll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLLv8i8_shift, ARM64_INS_SSHLL: sshll.8h $rd, $rn, $imm */ + +{ /* AArch64_SSHLLv8i8_shift, AArch64_INS_SSHLL: sshll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv16i8, ARM64_INS_SSHL: sshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv16i8, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv1i64, ARM64_INS_SSHL: sshl $rd, $rn, $rm */ + +{ /* AArch64_SSHLv1i64, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv2i32, ARM64_INS_SSHL: sshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv2i32, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv2i64, ARM64_INS_SSHL: sshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv2i64, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv4i16, ARM64_INS_SSHL: sshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv4i16, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv4i32, ARM64_INS_SSHL: sshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv4i32, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv8i16, ARM64_INS_SSHL: sshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv8i16, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHLv8i8, ARM64_INS_SSHL: sshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_SSHLv8i8, AArch64_INS_SSHL: sshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRd, ARM64_INS_SSHR: sshr $rd, $rn, $imm */ + +{ /* AArch64_SSHRd, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv16i8_shift, ARM64_INS_SSHR: sshr.16b $rd, $rn, $imm */ + +{ /* AArch64_SSHRv16i8_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv2i32_shift, ARM64_INS_SSHR: sshr.2s $rd, $rn, $imm */ + +{ /* AArch64_SSHRv2i32_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv2i64_shift, ARM64_INS_SSHR: sshr.2d $rd, $rn, $imm */ + +{ /* AArch64_SSHRv2i64_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv4i16_shift, ARM64_INS_SSHR: sshr.4h $rd, $rn, $imm */ + +{ /* AArch64_SSHRv4i16_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv4i32_shift, ARM64_INS_SSHR: sshr.4s $rd, $rn, $imm */ + +{ /* AArch64_SSHRv4i32_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv8i16_shift, ARM64_INS_SSHR: sshr.8h $rd, $rn, $imm */ + +{ /* AArch64_SSHRv8i16_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSHRv8i8_shift, ARM64_INS_SSHR: sshr.8b $rd, $rn, $imm */ + +{ /* AArch64_SSHRv8i8_shift, AArch64_INS_SSHR: sshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAd, ARM64_INS_SSRA: ssra $rd, $rn, $imm */ + +{ /* AArch64_SSRAd, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv16i8_shift, ARM64_INS_SSRA: ssra.16b $rd, $rn, $imm */ + +{ /* AArch64_SSRAv16i8_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv2i32_shift, ARM64_INS_SSRA: ssra.2s $rd, $rn, $imm */ + +{ /* AArch64_SSRAv2i32_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv2i64_shift, ARM64_INS_SSRA: ssra.2d $rd, $rn, $imm */ + +{ /* AArch64_SSRAv2i64_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv4i16_shift, ARM64_INS_SSRA: ssra.4h $rd, $rn, $imm */ + +{ /* AArch64_SSRAv4i16_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv4i32_shift, ARM64_INS_SSRA: ssra.4s $rd, $rn, $imm */ + +{ /* AArch64_SSRAv4i32_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv8i16_shift, ARM64_INS_SSRA: ssra.8h $rd, $rn, $imm */ + +{ /* AArch64_SSRAv8i16_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSRAv8i8_shift, ARM64_INS_SSRA: ssra.8b $rd, $rn, $imm */ + +{ /* AArch64_SSRAv8i8_shift, AArch64_INS_SSRA: ssra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBLv16i8_v8i16, ARM64_INS_SSUBL2: ssubl2.8h $rd, $rn, $rm */ + +{ /* AArch64_SST1B_D, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1B_D_IMM, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1B_D_SXTW, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1B_D_UXTW, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1B_S_IMM, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1B_S_SXTW, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1B_S_UXTW, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D_IMM, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D_SCALED, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D_SXTW, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D_SXTW_SCALED, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D_UXTW, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1D_UXTW_SCALED, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D_IMM, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D_SCALED, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D_SXTW, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D_SXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D_UXTW, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_D_UXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_S_IMM, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_S_SXTW, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_S_SXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_S_UXTW, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1H_S_UXTW_SCALED, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D_IMM, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D_SCALED, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D_SXTW, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D_SXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D_UXTW, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_D_UXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_IMM, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_SXTW, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_SXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_UXTW, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SST1W_UXTW_SCALED, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_SSUBLv16i8_v8i16, AArch64_INS_SSUBL2: ssubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBLv2i32_v2i64, ARM64_INS_SSUBL: ssubl.2d $rd, $rn, $rm */ + +{ /* AArch64_SSUBLv2i32_v2i64, AArch64_INS_SSUBL: ssubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBLv4i16_v4i32, ARM64_INS_SSUBL: ssubl.4s $rd, $rn, $rm */ + +{ /* AArch64_SSUBLv4i16_v4i32, AArch64_INS_SSUBL: ssubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBLv4i32_v2i64, ARM64_INS_SSUBL2: ssubl2.2d $rd, $rn, $rm */ + +{ /* AArch64_SSUBLv4i32_v2i64, AArch64_INS_SSUBL2: ssubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBLv8i16_v4i32, ARM64_INS_SSUBL2: ssubl2.4s $rd, $rn, $rm */ + +{ /* AArch64_SSUBLv8i16_v4i32, AArch64_INS_SSUBL2: ssubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBLv8i8_v8i16, ARM64_INS_SSUBL: ssubl.8h $rd, $rn, $rm */ + +{ /* AArch64_SSUBLv8i8_v8i16, AArch64_INS_SSUBL: ssubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBWv16i8_v8i16, ARM64_INS_SSUBW2: ssubw2.8h $rd, $rn, $rm */ + +{ /* AArch64_SSUBWv16i8_v8i16, AArch64_INS_SSUBW2: ssubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBWv2i32_v2i64, ARM64_INS_SSUBW: ssubw.2d $rd, $rn, $rm */ + +{ /* AArch64_SSUBWv2i32_v2i64, AArch64_INS_SSUBW: ssubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBWv4i16_v4i32, ARM64_INS_SSUBW: ssubw.4s $rd, $rn, $rm */ + +{ /* AArch64_SSUBWv4i16_v4i32, AArch64_INS_SSUBW: ssubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBWv4i32_v2i64, ARM64_INS_SSUBW2: ssubw2.2d $rd, $rn, $rm */ + +{ /* AArch64_SSUBWv4i32_v2i64, AArch64_INS_SSUBW2: ssubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBWv8i16_v4i32, ARM64_INS_SSUBW2: ssubw2.4s $rd, $rn, $rm */ + +{ /* AArch64_SSUBWv8i16_v4i32, AArch64_INS_SSUBW2: ssubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SSUBWv8i8_v8i16, ARM64_INS_SSUBW: ssubw.8h $rd, $rn, $rm */ + +{ /* AArch64_SSUBWv8i8_v8i16, AArch64_INS_SSUBW: ssubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1B, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_D, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_D_IMM, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_H, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_H_IMM, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_IMM, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_S, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1B_S_IMM, AArch64_INS_ST1B: st1b */ + 0, + { 0 } +}, + +{ /* AArch64_ST1D, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_ST1D_IMM, AArch64_INS_ST1D: st1d */ + 0, + { 0 } +}, + +{ /* AArch64_ST1Fourv16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Fourv8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Fourv8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Fourv8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1H, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_ST1H_D, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_ST1H_D_IMM, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_ST1H_IMM, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_ST1H_S, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_ST1H_S_IMM, AArch64_INS_ST1H: st1h */ + 0, + { 0 } +}, + +{ /* AArch64_ST1Onev16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Onev8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Onev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Onev8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Threev8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Threev8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Threev8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov16b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov16b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov16b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov16b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov1d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov1d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov1d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov1d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov2d, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov2d, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov2d_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov2d_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov2s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov2s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov2s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov2s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov4h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov4h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov4h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov4h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov4s, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov4s, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov4s_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov4s_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov8b, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov8b, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov8b_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov8b_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov8h, ARM64_INS_ST1: st1 $vt, [$rn] */ + +{ /* AArch64_ST1Twov8h, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1Twov8h_POST, ARM64_INS_ST1: st1 $vt, [$rn], $xm */ + +{ /* AArch64_ST1Twov8h_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1i16, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + +{ /* AArch64_ST1W, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_ST1W_D, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_ST1W_D_IMM, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_ST1W_IMM, AArch64_INS_ST1W: st1w */ + 0, + { 0 } +}, + +{ /* AArch64_ST1i16, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1i16_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST1i16_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1i32, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + +{ /* AArch64_ST1i32, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1i32_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST1i32_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1i64, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + +{ /* AArch64_ST1i64, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1i64_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST1i64_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST1i8, ARM64_INS_ST1: st1 $vt$idx, [$rn] */ + +{ /* AArch64_ST1i8, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST1i8_POST, ARM64_INS_ST1: st1 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST1i8_POST, AArch64_INS_ST1: st1 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov16b, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2B, AArch64_INS_ST2B: st2b */ + 0, + { 0 } +}, + +{ /* AArch64_ST2B_IMM, AArch64_INS_ST2B: st2b */ + 0, + { 0 } +}, + +{ /* AArch64_ST2D, AArch64_INS_ST2D: st2d */ + 0, + { 0 } +}, + +{ /* AArch64_ST2D_IMM, AArch64_INS_ST2D: st2d */ + 0, + { 0 } +}, + +{ /* AArch64_ST2H, AArch64_INS_ST2H: st2h */ + 0, + { 0 } +}, + +{ /* AArch64_ST2H_IMM, AArch64_INS_ST2H: st2h */ + 0, + { 0 } +}, + +{ /* AArch64_ST2Twov16b, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov16b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov16b_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov2d, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2Twov2d, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov2d_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov2d_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov2s, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2Twov2s, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov2s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov2s_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov4h, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2Twov4h, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov4h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov4h_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov4s, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2Twov4s, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov4s_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov4s_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov8b, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2Twov8b, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov8b_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov8b_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov8h, ARM64_INS_ST2: st2 $vt, [$rn] */ + +{ /* AArch64_ST2Twov8h, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2Twov8h_POST, ARM64_INS_ST2: st2 $vt, [$rn], $xm */ + +{ /* AArch64_ST2Twov8h_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2i16, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + +{ /* AArch64_ST2W, AArch64_INS_ST2W: st2w */ + 0, + { 0 } +}, + +{ /* AArch64_ST2W_IMM, AArch64_INS_ST2W: st2w */ + 0, + { 0 } +}, + +{ /* AArch64_ST2i16, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2i16_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST2i16_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2i32, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + +{ /* AArch64_ST2i32, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2i32_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST2i32_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2i64, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + +{ /* AArch64_ST2i64, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2i64_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST2i64_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST2i8, ARM64_INS_ST2: st2 $vt$idx, [$rn] */ + +{ /* AArch64_ST2i8, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST2i8_POST, ARM64_INS_ST2: st2 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST2i8_POST, AArch64_INS_ST2: st2 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev16b, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3B, AArch64_INS_ST3B: st3b */ + 0, + { 0 } +}, + +{ /* AArch64_ST3B_IMM, AArch64_INS_ST3B: st3b */ + 0, + { 0 } +}, + +{ /* AArch64_ST3D, AArch64_INS_ST3D: st3d */ + 0, + { 0 } +}, + +{ /* AArch64_ST3D_IMM, AArch64_INS_ST3D: st3d */ + 0, + { 0 } +}, + +{ /* AArch64_ST3H, AArch64_INS_ST3H: st3h */ + 0, + { 0 } +}, + +{ /* AArch64_ST3H_IMM, AArch64_INS_ST3H: st3h */ + 0, + { 0 } +}, + +{ /* AArch64_ST3Threev16b, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev16b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev16b_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev2d, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3Threev2d, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev2d_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev2d_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev2s, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3Threev2s, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev2s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev2s_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev4h, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3Threev4h, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev4h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev4h_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev4s, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3Threev4s, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev4s_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev4s_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev8b, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3Threev8b, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev8b_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev8b_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev8h, ARM64_INS_ST3: st3 $vt, [$rn] */ + +{ /* AArch64_ST3Threev8h, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3Threev8h_POST, ARM64_INS_ST3: st3 $vt, [$rn], $xm */ + +{ /* AArch64_ST3Threev8h_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3i16, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + +{ /* AArch64_ST3W, AArch64_INS_ST3W: st3w */ + 0, + { 0 } +}, + +{ /* AArch64_ST3W_IMM, AArch64_INS_ST3W: st3w */ + 0, + { 0 } +}, + +{ /* AArch64_ST3i16, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3i16_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST3i16_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3i32, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + +{ /* AArch64_ST3i32, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3i32_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST3i32_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3i64, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + +{ /* AArch64_ST3i64, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3i64_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST3i64_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST3i8, ARM64_INS_ST3: st3 $vt$idx, [$rn] */ + +{ /* AArch64_ST3i8, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST3i8_POST, ARM64_INS_ST3: st3 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST3i8_POST, AArch64_INS_ST3: st3 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv16b, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4B, AArch64_INS_ST4B: st4b */ + 0, + { 0 } +}, + +{ /* AArch64_ST4B_IMM, AArch64_INS_ST4B: st4b */ + 0, + { 0 } +}, + +{ /* AArch64_ST4D, AArch64_INS_ST4D: st4d */ + 0, + { 0 } +}, + +{ /* AArch64_ST4D_IMM, AArch64_INS_ST4D: st4d */ + 0, + { 0 } +}, + +{ /* AArch64_ST4Fourv16b, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv16b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv16b_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv2d, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4Fourv2d, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv2d_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv2d_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv2s, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4Fourv2s, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv2s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv2s_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv4h, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4Fourv4h, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv4h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv4h_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv4s, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4Fourv4s, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv4s_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv4s_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv8b, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4Fourv8b, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv8b_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv8b_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv8h, ARM64_INS_ST4: st4 $vt, [$rn] */ + +{ /* AArch64_ST4Fourv8h, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4Fourv8h_POST, ARM64_INS_ST4: st4 $vt, [$rn], $xm */ + +{ /* AArch64_ST4Fourv8h_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4i16, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + +{ /* AArch64_ST4H, AArch64_INS_ST4H: st4h */ + 0, + { 0 } +}, + +{ /* AArch64_ST4H_IMM, AArch64_INS_ST4H: st4h */ + 0, + { 0 } +}, + +{ /* AArch64_ST4W, AArch64_INS_ST4W: st4w */ + 0, + { 0 } +}, + +{ /* AArch64_ST4W_IMM, AArch64_INS_ST4W: st4w */ + 0, + { 0 } +}, + +{ /* AArch64_ST4i16, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4i16_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST4i16_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4i32, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + +{ /* AArch64_ST4i32, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4i32_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST4i32_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4i64, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + +{ /* AArch64_ST4i64, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4i64_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST4i64_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ST4i8, ARM64_INS_ST4: st4 $vt$idx, [$rn] */ + +{ /* AArch64_ST4i8, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, 0 } }, -{ /* AArch64_ST4i8_POST, ARM64_INS_ST4: st4 $vt$idx, [$rn], $xm */ + +{ /* AArch64_ST4i8_POST, AArch64_INS_ST4: st4 */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLRB, ARM64_INS_STLRB: stlrb $rt, [$rn] */ + +{ /* AArch64_STLLRB, AArch64_INS_STLLRB: stllrb */ + 0, + { 0 } +}, + +{ /* AArch64_STLLRH, AArch64_INS_STLLRH: stllrh */ + 0, + { 0 } +}, + +{ /* AArch64_STLLRW, AArch64_INS_STLLR: stllr */ + 0, + { 0 } +}, + +{ /* AArch64_STLLRX, AArch64_INS_STLLR: stllr */ + 0, + { 0 } +}, + +{ /* AArch64_STLRB, AArch64_INS_STLRB: stlrb */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLRH, ARM64_INS_STLRH: stlrh $rt, [$rn] */ + +{ /* AArch64_STLRH, AArch64_INS_STLRH: stlrh */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLRW, ARM64_INS_STLR: stlr $rt, [$rn] */ + +{ /* AArch64_STLRW, AArch64_INS_STLR: stlr */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLRX, ARM64_INS_STLR: stlr $rt, [$rn] */ + +{ /* AArch64_STLRX, AArch64_INS_STLR: stlr */ 0, { CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLXPW, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */ + +{ /* AArch64_STLURBi, AArch64_INS_STLURB: stlurb */ + 0, + { 0 } +}, + +{ /* AArch64_STLURHi, AArch64_INS_STLURH: stlurh */ + 0, + { 0 } +}, + +{ /* AArch64_STLURWi, AArch64_INS_STLUR: stlur */ + 0, + { 0 } +}, + +{ /* AArch64_STLURXi, AArch64_INS_STLUR: stlur */ + 0, + { 0 } +}, + +{ /* AArch64_STLXPW, AArch64_INS_STLXP: stlxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLXPX, ARM64_INS_STLXP: stlxp $ws, $rt, $rt2, [$rn] */ + +{ /* AArch64_STLXPX, AArch64_INS_STLXP: stlxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLXRB, ARM64_INS_STLXRB: stlxrb $ws, $rt, [$rn] */ + +{ /* AArch64_STLXRB, AArch64_INS_STLXRB: stlxrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLXRH, ARM64_INS_STLXRH: stlxrh $ws, $rt, [$rn] */ + +{ /* AArch64_STLXRH, AArch64_INS_STLXRH: stlxrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLXRW, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */ + +{ /* AArch64_STLXRW, AArch64_INS_STLXR: stlxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STLXRX, ARM64_INS_STLXR: stlxr $ws, $rt, [$rn] */ + +{ /* AArch64_STLXRX, AArch64_INS_STLXR: stlxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STNPDi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STNPDi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STNPQi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STNPQi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STNPSi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STNPSi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STNPWi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STNPWi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STNPXi, ARM64_INS_STNP: stnp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STNPXi, AArch64_INS_STNP: stnp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPDi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STNT1B_ZRI, AArch64_INS_STNT1B: stnt1b */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1B_ZRR, AArch64_INS_STNT1B: stnt1b */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1D_ZRI, AArch64_INS_STNT1D: stnt1d */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1D_ZRR, AArch64_INS_STNT1D: stnt1d */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1H_ZRI, AArch64_INS_STNT1H: stnt1h */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1H_ZRR, AArch64_INS_STNT1H: stnt1h */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1W_ZRI, AArch64_INS_STNT1W: stnt1w */ + 0, + { 0 } +}, + +{ /* AArch64_STNT1W_ZRR, AArch64_INS_STNT1W: stnt1w */ + 0, + { 0 } +}, + +{ /* AArch64_STPDi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPDpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_STPDpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPDpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_STPDpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPQi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STPQi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPQpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_STPQpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPQpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_STPQpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPSi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STPSi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPSpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_STPSpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPSpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_STPSpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPWi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STPWi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPWpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_STPWpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPWpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_STPWpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPXi, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset] */ + +{ /* AArch64_STPXi, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPXpost, ARM64_INS_STP: stp $rt, $rt2, [$rn], $offset */ + +{ /* AArch64_STPXpost, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STPXpre, ARM64_INS_STP: stp $rt, $rt2, [$rn, $offset]! */ + +{ /* AArch64_STPXpre, AArch64_INS_STP: stp */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRBBpost, ARM64_INS_STRB: strb $rt, [$rn], $offset */ + +{ /* AArch64_STRBBpost, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRBBpre, ARM64_INS_STRB: strb $rt, [$rn, $offset]! */ + +{ /* AArch64_STRBBpre, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRBBroW, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRBBroW, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRBBroX, ARM64_INS_STRB: strb $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRBBroX, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRBBui, ARM64_INS_STRB: strb $rt, [$rn, $offset] */ + +{ /* AArch64_STRBBui, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRBpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRBpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRBpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRBpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRBroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRBroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRBroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRBroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRBui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRBui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRDpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRDpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRDpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRDpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRDroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRDroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRDroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRDroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRDui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRDui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRHHpost, ARM64_INS_STRH: strh $rt, [$rn], $offset */ + +{ /* AArch64_STRHHpost, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRHHpre, ARM64_INS_STRH: strh $rt, [$rn, $offset]! */ + +{ /* AArch64_STRHHpre, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRHHroW, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRHHroW, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRHHroX, ARM64_INS_STRH: strh $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRHHroX, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRHHui, ARM64_INS_STRH: strh $rt, [$rn, $offset] */ + +{ /* AArch64_STRHHui, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRHpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRHpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRHpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRHpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRHroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRHroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRHroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRHroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRHui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRHui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRQpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRQpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRQpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRQpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRQroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRQroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRQroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRQroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRQui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRQui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRSpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRSpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRSpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRSpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRSroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRSroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRSroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRSroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRSui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRSui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRWpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRWpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRWpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRWpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRWroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRWroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRWroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRWroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRWui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRWui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRXpost, ARM64_INS_STR: str $rt, [$rn], $offset */ + +{ /* AArch64_STRXpost, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRXpre, ARM64_INS_STR: str $rt, [$rn, $offset]! */ + +{ /* AArch64_STRXpre, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STRXroW, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRXroW, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRXroX, ARM64_INS_STR: str $rt, [$rn, $rm, $extend] */ + +{ /* AArch64_STRXroX, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STRXui, ARM64_INS_STR: str $rt, [$rn, $offset] */ + +{ /* AArch64_STRXui, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STTRBi, ARM64_INS_STTRB: sttrb $rt, [$rn, $offset] */ + +{ /* AArch64_STR_PXI, AArch64_INS_STR: str */ + 0, + { 0 } +}, + +{ /* AArch64_STR_ZXI, AArch64_INS_STR: str */ + 0, + { 0 } +}, + +{ /* AArch64_STTRBi, AArch64_INS_STTRB: sttrb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STTRHi, ARM64_INS_STTRH: sttrh $rt, [$rn, $offset] */ + +{ /* AArch64_STTRHi, AArch64_INS_STTRH: sttrh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STTRWi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */ + +{ /* AArch64_STTRWi, AArch64_INS_STTR: sttr */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STTRXi, ARM64_INS_STTR: sttr $rt, [$rn, $offset] */ + +{ /* AArch64_STTRXi, AArch64_INS_STTR: sttr */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURBBi, ARM64_INS_STURB: sturb $rt, [$rn, $offset] */ + +{ /* AArch64_STURBBi, AArch64_INS_STRB: strb */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURBi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURBi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURDi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURDi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURHHi, ARM64_INS_STURH: sturh $rt, [$rn, $offset] */ + +{ /* AArch64_STURHHi, AArch64_INS_STRH: strh */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURHi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURHi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURQi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURQi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURSi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURSi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURWi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURWi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STURXi, ARM64_INS_STUR: stur $rt, [$rn, $offset] */ + +{ /* AArch64_STURXi, AArch64_INS_STR: str */ 0, { CS_AC_READ, CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STXPW, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */ + +{ /* AArch64_STXPW, AArch64_INS_STXP: stxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STXPX, ARM64_INS_STXP: stxp $ws, $rt, $rt2, [$rn] */ + +{ /* AArch64_STXPX, AArch64_INS_STXP: stxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_STXRB, ARM64_INS_STXRB: stxrb $ws, $rt, [$rn] */ + +{ /* AArch64_STXRB, AArch64_INS_STXRB: stxrb */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STXRH, ARM64_INS_STXRH: stxrh $ws, $rt, [$rn] */ + +{ /* AArch64_STXRH, AArch64_INS_STXRH: stxrh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STXRW, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */ + +{ /* AArch64_STXRW, AArch64_INS_STXR: stxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_STXRX, ARM64_INS_STXR: stxr $ws, $rt, [$rn] */ + +{ /* AArch64_STXRX, AArch64_INS_STXR: stxr */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBHNv2i64_v2i32, ARM64_INS_SUBHN: subhn.2s $rd, $rn, $rm */ + +{ /* AArch64_SUBHNv2i64_v2i32, AArch64_INS_SUBHN: subhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBHNv2i64_v4i32, ARM64_INS_SUBHN2: subhn2.4s $rd, $rn, $rm */ + +{ /* AArch64_SUBHNv2i64_v4i32, AArch64_INS_SUBHN2: subhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBHNv4i32_v4i16, ARM64_INS_SUBHN: subhn.4h $rd, $rn, $rm */ + +{ /* AArch64_SUBHNv4i32_v4i16, AArch64_INS_SUBHN: subhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBHNv4i32_v8i16, ARM64_INS_SUBHN2: subhn2.8h $rd, $rn, $rm */ + +{ /* AArch64_SUBHNv4i32_v8i16, AArch64_INS_SUBHN2: subhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBHNv8i16_v16i8, ARM64_INS_SUBHN2: subhn2.16b $rd, $rn, $rm */ + +{ /* AArch64_SUBHNv8i16_v16i8, AArch64_INS_SUBHN2: subhn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBHNv8i16_v8i8, ARM64_INS_SUBHN: subhn.8b $rd, $rn, $rm */ + +{ /* AArch64_SUBHNv8i16_v8i8, AArch64_INS_SUBHN: subhn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSWri, ARM64_INS_SUBS: subs $rd, $rn, $imm */ + +{ /* AArch64_SUBR_ZI_B, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZI_D, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZI_H, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZI_S, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZPmZ_B, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZPmZ_D, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZPmZ_H, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBR_ZPmZ_S, AArch64_INS_SUBR: subr */ + 0, + { 0 } +}, + +{ /* AArch64_SUBSWri, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSWrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */ + +{ /* AArch64_SUBSWrs, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSWrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */ + +{ /* AArch64_SUBSWrx, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSXri, ARM64_INS_SUBS: subs $rd, $rn, $imm */ + +{ /* AArch64_SUBSXri, AArch64_INS_ADDS: adds */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSXrs, ARM64_INS_SUBS: subs $rd, $rn, $rm */ + +{ /* AArch64_SUBSXrs, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSXrx, ARM64_INS_SUBS: subs $r1, $r2, $r3 */ + +{ /* AArch64_SUBSXrx, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBSXrx64, ARM64_INS_SUBS: subs $rd, $rn, $rm$ext */ + +{ /* AArch64_SUBSXrx64, AArch64_INS_CMP: cmp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SUBWri, ARM64_INS_SUB: sub $rd, $rn, $imm */ + +{ /* AArch64_SUBWri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBWrs, ARM64_INS_SUB: sub $rd, $rn, $rm */ + +{ /* AArch64_SUBWrs, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBWrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */ + +{ /* AArch64_SUBWrx, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBXri, ARM64_INS_SUB: sub $rd, $rn, $imm */ + +{ /* AArch64_SUBXri, AArch64_INS_ADD: add */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBXrs, ARM64_INS_SUB: sub $rd, $rn, $rm */ + +{ /* AArch64_SUBXrs, AArch64_INS_NEG: neg */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBXrx, ARM64_INS_SUB: sub $r1, $r2, $r3 */ + +{ /* AArch64_SUBXrx, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBXrx64, ARM64_INS_SUB: sub $rd, $rn, $rm$ext */ + +{ /* AArch64_SUBXrx64, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SUBv16i8, ARM64_INS_SUB: sub.16b $rd, $rn, $rm| */ + +{ /* AArch64_SUB_ZI_B, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZI_D, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZI_H, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZI_S, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZPmZ_B, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZPmZ_D, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZPmZ_H, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZPmZ_S, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZZZ_B, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZZZ_D, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZZZ_H, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUB_ZZZ_S, AArch64_INS_SUB: sub */ + 0, + { 0 } +}, + +{ /* AArch64_SUBv16i8, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv1i64, ARM64_INS_SUB: sub $rd, $rn, $rm */ + +{ /* AArch64_SUBv1i64, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv2i32, ARM64_INS_SUB: sub.2s $rd, $rn, $rm| */ + +{ /* AArch64_SUBv2i32, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv2i64, ARM64_INS_SUB: sub.2d $rd, $rn, $rm| */ + +{ /* AArch64_SUBv2i64, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv4i16, ARM64_INS_SUB: sub.4h $rd, $rn, $rm| */ + +{ /* AArch64_SUBv4i16, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv4i32, ARM64_INS_SUB: sub.4s $rd, $rn, $rm| */ + +{ /* AArch64_SUBv4i32, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv8i16, ARM64_INS_SUB: sub.8h $rd, $rn, $rm| */ + +{ /* AArch64_SUBv8i16, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUBv8i8, ARM64_INS_SUB: sub.8b $rd, $rn, $rm| */ + +{ /* AArch64_SUBv8i8, AArch64_INS_SUB: sub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv16i8, ARM64_INS_SUQADD: suqadd.16b $rd, $rn */ + +{ /* AArch64_SUNPKHI_ZZ_D, AArch64_INS_SUNPKHI: sunpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_SUNPKHI_ZZ_H, AArch64_INS_SUNPKHI: sunpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_SUNPKHI_ZZ_S, AArch64_INS_SUNPKHI: sunpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_SUNPKLO_ZZ_D, AArch64_INS_SUNPKLO: sunpklo */ + 0, + { 0 } +}, + +{ /* AArch64_SUNPKLO_ZZ_H, AArch64_INS_SUNPKLO: sunpklo */ + 0, + { 0 } +}, + +{ /* AArch64_SUNPKLO_ZZ_S, AArch64_INS_SUNPKLO: sunpklo */ + 0, + { 0 } +}, + +{ /* AArch64_SUQADDv16i8, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv1i16, ARM64_INS_SUQADD: suqadd $rd, $rn */ + +{ /* AArch64_SUQADDv1i16, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv1i32, ARM64_INS_SUQADD: suqadd $rd, $rn */ + +{ /* AArch64_SUQADDv1i32, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv1i64, ARM64_INS_SUQADD: suqadd $rd, $rn */ + +{ /* AArch64_SUQADDv1i64, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv1i8, ARM64_INS_SUQADD: suqadd $rd, $rn */ + +{ /* AArch64_SUQADDv1i8, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv2i32, ARM64_INS_SUQADD: suqadd.2s $rd, $rn */ + +{ /* AArch64_SUQADDv2i32, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv2i64, ARM64_INS_SUQADD: suqadd.2d $rd, $rn */ + +{ /* AArch64_SUQADDv2i64, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv4i16, ARM64_INS_SUQADD: suqadd.4h $rd, $rn */ + +{ /* AArch64_SUQADDv4i16, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv4i32, ARM64_INS_SUQADD: suqadd.4s $rd, $rn */ + +{ /* AArch64_SUQADDv4i32, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv8i16, ARM64_INS_SUQADD: suqadd.8h $rd, $rn */ + +{ /* AArch64_SUQADDv8i16, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SUQADDv8i8, ARM64_INS_SUQADD: suqadd.8b $rd, $rn */ + +{ /* AArch64_SUQADDv8i8, AArch64_INS_SUQADD: suqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_SVC, ARM64_INS_SVC: svc $imm */ + +{ /* AArch64_SVC, AArch64_INS_SVC: svc */ 0, { CS_AC_READ, 0 } }, -{ /* AArch64_SYSLxt, ARM64_INS_SYSL: sysl $rt, $op1, $cn, $cm, $op2 */ + +{ /* AArch64_SWPAB, AArch64_INS_SWPAB: swpab */ + 0, + { 0 } +}, + +{ /* AArch64_SWPAH, AArch64_INS_SWPAH: swpah */ + 0, + { 0 } +}, + +{ /* AArch64_SWPALB, AArch64_INS_SWPALB: swpalb */ + 0, + { 0 } +}, + +{ /* AArch64_SWPALH, AArch64_INS_SWPALH: swpalh */ + 0, + { 0 } +}, + +{ /* AArch64_SWPALW, AArch64_INS_SWPAL: swpal */ + 0, + { 0 } +}, + +{ /* AArch64_SWPALX, AArch64_INS_SWPAL: swpal */ + 0, + { 0 } +}, + +{ /* AArch64_SWPAW, AArch64_INS_SWPA: swpa */ + 0, + { 0 } +}, + +{ /* AArch64_SWPAX, AArch64_INS_SWPA: swpa */ + 0, + { 0 } +}, + +{ /* AArch64_SWPB, AArch64_INS_SWPB: swpb */ + 0, + { 0 } +}, + +{ /* AArch64_SWPH, AArch64_INS_SWPH: swph */ + 0, + { 0 } +}, + +{ /* AArch64_SWPLB, AArch64_INS_SWPLB: swplb */ + 0, + { 0 } +}, + +{ /* AArch64_SWPLH, AArch64_INS_SWPLH: swplh */ + 0, + { 0 } +}, + +{ /* AArch64_SWPLW, AArch64_INS_SWPL: swpl */ + 0, + { 0 } +}, + +{ /* AArch64_SWPLX, AArch64_INS_SWPL: swpl */ + 0, + { 0 } +}, + +{ /* AArch64_SWPW, AArch64_INS_SWP: swp */ + 0, + { 0 } +}, + +{ /* AArch64_SWPX, AArch64_INS_SWP: swp */ + 0, + { 0 } +}, + +{ /* AArch64_SXTB_ZPmZ_D, AArch64_INS_SXTB: sxtb */ + 0, + { 0 } +}, + +{ /* AArch64_SXTB_ZPmZ_H, AArch64_INS_SXTB: sxtb */ + 0, + { 0 } +}, + +{ /* AArch64_SXTB_ZPmZ_S, AArch64_INS_SXTB: sxtb */ + 0, + { 0 } +}, + +{ /* AArch64_SXTH_ZPmZ_D, AArch64_INS_SXTH: sxth */ + 0, + { 0 } +}, + +{ /* AArch64_SXTH_ZPmZ_S, AArch64_INS_SXTH: sxth */ + 0, + { 0 } +}, + +{ /* AArch64_SXTW_ZPmZ_D, AArch64_INS_SXTW: sxtw */ + 0, + { 0 } +}, + +{ /* AArch64_SYSLxt, AArch64_INS_SYSL: sysl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ } }, -{ /* AArch64_SYSxt, ARM64_INS_SYS: sys $op1, $cn, $cm, $op2, $rt */ + +{ /* AArch64_SYSxt, AArch64_INS_SYS: sys */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_WRITE | CS_AC_READ } }, -{ /* AArch64_TBLv16i8Four, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBL_ZZZ_B, AArch64_INS_TBL: tbl */ + 0, + { 0 } +}, + +{ /* AArch64_TBL_ZZZ_D, AArch64_INS_TBL: tbl */ + 0, + { 0 } +}, + +{ /* AArch64_TBL_ZZZ_H, AArch64_INS_TBL: tbl */ + 0, + { 0 } +}, + +{ /* AArch64_TBL_ZZZ_S, AArch64_INS_TBL: tbl */ + 0, + { 0 } +}, + +{ /* AArch64_TBLv16i8Four, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv16i8One, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBLv16i8One, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv16i8Three, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBLv16i8Three, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv16i8Two, ARM64_INS_TBL: tbl $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBLv16i8Two, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv8i8Four, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBLv8i8Four, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv8i8One, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBLv8i8One, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv8i8Three, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBLv8i8Three, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBLv8i8Two, ARM64_INS_TBL: tbl $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBLv8i8Two, AArch64_INS_TBL: tbl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBNZW, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */ + +{ /* AArch64_TBNZW, AArch64_INS_TBNZ: tbnz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBNZX, ARM64_INS_TBNZ: tbnz $rt, $bit_off, $target */ + +{ /* AArch64_TBNZX, AArch64_INS_TBNZ: tbnz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv16i8Four, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBXv16i8Four, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv16i8One, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBXv16i8One, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv16i8Three, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBXv16i8Three, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv16i8Two, ARM64_INS_TBX: tbx $vd.16b, $vn, $vm.16b */ + +{ /* AArch64_TBXv16i8Two, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv8i8Four, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBXv8i8Four, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv8i8One, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBXv8i8One, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv8i8Three, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBXv8i8Three, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBXv8i8Two, ARM64_INS_TBX: tbx $vd.8b, $vn, $vm.8b */ + +{ /* AArch64_TBXv8i8Two, AArch64_INS_TBX: tbx */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBZW, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */ + +{ /* AArch64_TBZW, AArch64_INS_TBZ: tbz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TBZX, ARM64_INS_TBZ: tbz $rt, $bit_off, $target */ + +{ /* AArch64_TBZX, AArch64_INS_TBZ: tbz */ 0, { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v16i8, ARM64_INS_TRN1: trn1.16b $rd, $rn, $rm */ + +{ /* AArch64_TRN1_PPP_B, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_PPP_D, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_PPP_H, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_PPP_S, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_ZZZ_B, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_ZZZ_D, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_ZZZ_H, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1_ZZZ_S, AArch64_INS_TRN1: trn1 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN1v16i8, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v2i32, ARM64_INS_TRN1: trn1.2s $rd, $rn, $rm */ + +{ /* AArch64_TRN1v2i32, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v2i64, ARM64_INS_TRN1: trn1.2d $rd, $rn, $rm */ + +{ /* AArch64_TRN1v2i64, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v4i16, ARM64_INS_TRN1: trn1.4h $rd, $rn, $rm */ + +{ /* AArch64_TRN1v4i16, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v4i32, ARM64_INS_TRN1: trn1.4s $rd, $rn, $rm */ + +{ /* AArch64_TRN1v4i32, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v8i16, ARM64_INS_TRN1: trn1.8h $rd, $rn, $rm */ + +{ /* AArch64_TRN1v8i16, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN1v8i8, ARM64_INS_TRN1: trn1.8b $rd, $rn, $rm */ + +{ /* AArch64_TRN1v8i8, AArch64_INS_TRN1: trn1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v16i8, ARM64_INS_TRN2: trn2.16b $rd, $rn, $rm */ + +{ /* AArch64_TRN2_PPP_B, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_PPP_D, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_PPP_H, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_PPP_S, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_ZZZ_B, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_ZZZ_D, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_ZZZ_H, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2_ZZZ_S, AArch64_INS_TRN2: trn2 */ + 0, + { 0 } +}, + +{ /* AArch64_TRN2v16i8, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v2i32, ARM64_INS_TRN2: trn2.2s $rd, $rn, $rm */ + +{ /* AArch64_TRN2v2i32, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v2i64, ARM64_INS_TRN2: trn2.2d $rd, $rn, $rm */ + +{ /* AArch64_TRN2v2i64, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v4i16, ARM64_INS_TRN2: trn2.4h $rd, $rn, $rm */ + +{ /* AArch64_TRN2v4i16, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v4i32, ARM64_INS_TRN2: trn2.4s $rd, $rn, $rm */ + +{ /* AArch64_TRN2v4i32, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v8i16, ARM64_INS_TRN2: trn2.8h $rd, $rn, $rm */ + +{ /* AArch64_TRN2v8i16, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_TRN2v8i8, ARM64_INS_TRN2: trn2.8b $rd, $rn, $rm */ + +{ /* AArch64_TRN2v8i8, AArch64_INS_TRN2: trn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABALv16i8_v8i16, ARM64_INS_UABAL2: uabal2.8h $rd, $rn, $rm */ + +{ /* AArch64_TSB, AArch64_INS_TSB: tsb */ + 0, + { 0 } +}, + +{ /* AArch64_UABALv16i8_v8i16, AArch64_INS_UABAL2: uabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABALv2i32_v2i64, ARM64_INS_UABAL: uabal.2d $rd, $rn, $rm */ + +{ /* AArch64_UABALv2i32_v2i64, AArch64_INS_UABAL: uabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABALv4i16_v4i32, ARM64_INS_UABAL: uabal.4s $rd, $rn, $rm */ + +{ /* AArch64_UABALv4i16_v4i32, AArch64_INS_UABAL: uabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABALv4i32_v2i64, ARM64_INS_UABAL2: uabal2.2d $rd, $rn, $rm */ + +{ /* AArch64_UABALv4i32_v2i64, AArch64_INS_UABAL2: uabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABALv8i16_v4i32, ARM64_INS_UABAL2: uabal2.4s $rd, $rn, $rm */ + +{ /* AArch64_UABALv8i16_v4i32, AArch64_INS_UABAL2: uabal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABALv8i8_v8i16, ARM64_INS_UABAL: uabal.8h $rd, $rn, $rm */ + +{ /* AArch64_UABALv8i8_v8i16, AArch64_INS_UABAL: uabal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABAv16i8, ARM64_INS_UABA: uaba.16b $rd, $rn, $rm */ + +{ /* AArch64_UABAv16i8, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABAv2i32, ARM64_INS_UABA: uaba.2s $rd, $rn, $rm */ + +{ /* AArch64_UABAv2i32, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABAv4i16, ARM64_INS_UABA: uaba.4h $rd, $rn, $rm */ + +{ /* AArch64_UABAv4i16, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABAv4i32, ARM64_INS_UABA: uaba.4s $rd, $rn, $rm */ + +{ /* AArch64_UABAv4i32, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABAv8i16, ARM64_INS_UABA: uaba.8h $rd, $rn, $rm */ + +{ /* AArch64_UABAv8i16, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABAv8i8, ARM64_INS_UABA: uaba.8b $rd, $rn, $rm */ + +{ /* AArch64_UABAv8i8, AArch64_INS_UABA: uaba */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDLv16i8_v8i16, ARM64_INS_UABDL2: uabdl2.8h $rd, $rn, $rm */ + +{ /* AArch64_UABDLv16i8_v8i16, AArch64_INS_UABDL2: uabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDLv2i32_v2i64, ARM64_INS_UABDL: uabdl.2d $rd, $rn, $rm */ + +{ /* AArch64_UABDLv2i32_v2i64, AArch64_INS_UABDL: uabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDLv4i16_v4i32, ARM64_INS_UABDL: uabdl.4s $rd, $rn, $rm */ + +{ /* AArch64_UABDLv4i16_v4i32, AArch64_INS_UABDL: uabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDLv4i32_v2i64, ARM64_INS_UABDL2: uabdl2.2d $rd, $rn, $rm */ + +{ /* AArch64_UABDLv4i32_v2i64, AArch64_INS_UABDL2: uabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDLv8i16_v4i32, ARM64_INS_UABDL2: uabdl2.4s $rd, $rn, $rm */ + +{ /* AArch64_UABDLv8i16_v4i32, AArch64_INS_UABDL2: uabdl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDLv8i8_v8i16, ARM64_INS_UABDL: uabdl.8h $rd, $rn, $rm */ + +{ /* AArch64_UABDLv8i8_v8i16, AArch64_INS_UABDL: uabdl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDv16i8, ARM64_INS_UABD: uabd.16b $rd, $rn, $rm| */ + +{ /* AArch64_UABD_ZPmZ_B, AArch64_INS_UABD: uabd */ + 0, + { 0 } +}, + +{ /* AArch64_UABD_ZPmZ_D, AArch64_INS_UABD: uabd */ + 0, + { 0 } +}, + +{ /* AArch64_UABD_ZPmZ_H, AArch64_INS_UABD: uabd */ + 0, + { 0 } +}, + +{ /* AArch64_UABD_ZPmZ_S, AArch64_INS_UABD: uabd */ + 0, + { 0 } +}, + +{ /* AArch64_UABDv16i8, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDv2i32, ARM64_INS_UABD: uabd.2s $rd, $rn, $rm| */ + +{ /* AArch64_UABDv2i32, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDv4i16, ARM64_INS_UABD: uabd.4h $rd, $rn, $rm| */ + +{ /* AArch64_UABDv4i16, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDv4i32, ARM64_INS_UABD: uabd.4s $rd, $rn, $rm| */ + +{ /* AArch64_UABDv4i32, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDv8i16, ARM64_INS_UABD: uabd.8h $rd, $rn, $rm| */ + +{ /* AArch64_UABDv8i16, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UABDv8i8, ARM64_INS_UABD: uabd.8b $rd, $rn, $rm| */ + +{ /* AArch64_UABDv8i8, AArch64_INS_UABD: uabd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADALPv16i8_v8i16, ARM64_INS_UADALP: uadalp.8h $rd, $rn */ + +{ /* AArch64_UADALPv16i8_v8i16, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADALPv2i32_v1i64, ARM64_INS_UADALP: uadalp.1d $rd, $rn */ + +{ /* AArch64_UADALPv2i32_v1i64, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADALPv4i16_v2i32, ARM64_INS_UADALP: uadalp.2s $rd, $rn */ + +{ /* AArch64_UADALPv4i16_v2i32, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADALPv4i32_v2i64, ARM64_INS_UADALP: uadalp.2d $rd, $rn */ + +{ /* AArch64_UADALPv4i32_v2i64, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADALPv8i16_v4i32, ARM64_INS_UADALP: uadalp.4s $rd, $rn */ + +{ /* AArch64_UADALPv8i16_v4i32, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADALPv8i8_v4i16, ARM64_INS_UADALP: uadalp.4h $rd, $rn */ + +{ /* AArch64_UADALPv8i8_v4i16, AArch64_INS_UADALP: uadalp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLPv16i8_v8i16, ARM64_INS_UADDLP: uaddlp.8h $rd, $rn */ + +{ /* AArch64_UADDLPv16i8_v8i16, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLPv2i32_v1i64, ARM64_INS_UADDLP: uaddlp.1d $rd, $rn */ + +{ /* AArch64_UADDLPv2i32_v1i64, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLPv4i16_v2i32, ARM64_INS_UADDLP: uaddlp.2s $rd, $rn */ + +{ /* AArch64_UADDLPv4i16_v2i32, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLPv4i32_v2i64, ARM64_INS_UADDLP: uaddlp.2d $rd, $rn */ + +{ /* AArch64_UADDLPv4i32_v2i64, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLPv8i16_v4i32, ARM64_INS_UADDLP: uaddlp.4s $rd, $rn */ + +{ /* AArch64_UADDLPv8i16_v4i32, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLPv8i8_v4i16, ARM64_INS_UADDLP: uaddlp.4h $rd, $rn */ + +{ /* AArch64_UADDLPv8i8_v4i16, AArch64_INS_UADDLP: uaddlp */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLVv16i8v, ARM64_INS_UADDLV: uaddlv.16b $rd, $rn */ + +{ /* AArch64_UADDLVv16i8v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLVv4i16v, ARM64_INS_UADDLV: uaddlv.4h $rd, $rn */ + +{ /* AArch64_UADDLVv4i16v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLVv4i32v, ARM64_INS_UADDLV: uaddlv.4s $rd, $rn */ + +{ /* AArch64_UADDLVv4i32v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLVv8i16v, ARM64_INS_UADDLV: uaddlv.8h $rd, $rn */ + +{ /* AArch64_UADDLVv8i16v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLVv8i8v, ARM64_INS_UADDLV: uaddlv.8b $rd, $rn */ + +{ /* AArch64_UADDLVv8i8v, AArch64_INS_UADDLV: uaddlv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLv16i8_v8i16, ARM64_INS_UADDL2: uaddl2.8h $rd, $rn, $rm */ + +{ /* AArch64_UADDLv16i8_v8i16, AArch64_INS_UADDL2: uaddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLv2i32_v2i64, ARM64_INS_UADDL: uaddl.2d $rd, $rn, $rm */ + +{ /* AArch64_UADDLv2i32_v2i64, AArch64_INS_UADDL: uaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLv4i16_v4i32, ARM64_INS_UADDL: uaddl.4s $rd, $rn, $rm */ + +{ /* AArch64_UADDLv4i16_v4i32, AArch64_INS_UADDL: uaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLv4i32_v2i64, ARM64_INS_UADDL2: uaddl2.2d $rd, $rn, $rm */ + +{ /* AArch64_UADDLv4i32_v2i64, AArch64_INS_UADDL2: uaddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLv8i16_v4i32, ARM64_INS_UADDL2: uaddl2.4s $rd, $rn, $rm */ + +{ /* AArch64_UADDLv8i16_v4i32, AArch64_INS_UADDL2: uaddl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDLv8i8_v8i16, ARM64_INS_UADDL: uaddl.8h $rd, $rn, $rm */ + +{ /* AArch64_UADDLv8i8_v8i16, AArch64_INS_UADDL: uaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDWv16i8_v8i16, ARM64_INS_UADDW2: uaddw2.8h $rd, $rn, $rm */ + +{ /* AArch64_UADDV_VPZ_B, AArch64_INS_UADDV: uaddv */ + 0, + { 0 } +}, + +{ /* AArch64_UADDV_VPZ_D, AArch64_INS_UADDV: uaddv */ + 0, + { 0 } +}, + +{ /* AArch64_UADDV_VPZ_H, AArch64_INS_UADDV: uaddv */ + 0, + { 0 } +}, + +{ /* AArch64_UADDV_VPZ_S, AArch64_INS_UADDV: uaddv */ + 0, + { 0 } +}, + +{ /* AArch64_UADDWv16i8_v8i16, AArch64_INS_UADDW2: uaddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDWv2i32_v2i64, ARM64_INS_UADDW: uaddw.2d $rd, $rn, $rm */ + +{ /* AArch64_UADDWv2i32_v2i64, AArch64_INS_UADDW: uaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDWv4i16_v4i32, ARM64_INS_UADDW: uaddw.4s $rd, $rn, $rm */ + +{ /* AArch64_UADDWv4i16_v4i32, AArch64_INS_UADDW: uaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDWv4i32_v2i64, ARM64_INS_UADDW2: uaddw2.2d $rd, $rn, $rm */ + +{ /* AArch64_UADDWv4i32_v2i64, AArch64_INS_UADDW2: uaddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDWv8i16_v4i32, ARM64_INS_UADDW2: uaddw2.4s $rd, $rn, $rm */ + +{ /* AArch64_UADDWv8i16_v4i32, AArch64_INS_UADDW2: uaddw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UADDWv8i8_v8i16, ARM64_INS_UADDW: uaddw.8h $rd, $rn, $rm */ + +{ /* AArch64_UADDWv8i8_v8i16, AArch64_INS_UADDW: uaddw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UBFMWri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */ + +{ /* AArch64_UBFMWri, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UBFMXri, ARM64_INS_UBFM: ubfm $rd, $rn, $immr, $imms */ + +{ /* AArch64_UBFMXri, AArch64_INS_LSR: lsr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFSWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + +{ /* AArch64_UCVTFSWDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFSWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + +{ /* AArch64_UCVTFSWHri, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFSWSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFSXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + +{ /* AArch64_UCVTFSXDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFSXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn, $scale */ + +{ /* AArch64_UCVTFSXHri, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFSXSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFUWDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + +{ /* AArch64_UCVTFUWDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFUWSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + +{ /* AArch64_UCVTFUWHri, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFUWSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFUXDri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + +{ /* AArch64_UCVTFUXDri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFUXSri, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + +{ /* AArch64_UCVTFUXHri, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFUXSri, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFd, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */ + +{ /* AArch64_UCVTF_ZPmZ_DtoD, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTF_ZPmZ_DtoH, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTF_ZPmZ_DtoS, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTF_ZPmZ_HtoH, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTF_ZPmZ_StoD, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTF_ZPmZ_StoH, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTF_ZPmZ_StoS, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFd, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFs, ARM64_INS_UCVTF: ucvtf $rd, $rn, $imm */ + +{ /* AArch64_UCVTFh, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFs, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv1i32, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + +{ /* AArch64_UCVTFv1i16, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFv1i32, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv1i64, ARM64_INS_UCVTF: ucvtf $rd, $rn */ + +{ /* AArch64_UCVTFv1i64, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv2f32, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn */ + +{ /* AArch64_UCVTFv2f32, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv2f64, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn */ + +{ /* AArch64_UCVTFv2f64, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv2i32_shift, ARM64_INS_UCVTF: ucvtf.2s $rd, $rn, $imm */ + +{ /* AArch64_UCVTFv2i32_shift, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv2i64_shift, ARM64_INS_UCVTF: ucvtf.2d $rd, $rn, $imm */ + +{ /* AArch64_UCVTFv2i64_shift, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv4f32, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn */ + +{ /* AArch64_UCVTFv4f16, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFv4f32, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UCVTFv4i32_shift, ARM64_INS_UCVTF: ucvtf.4s $rd, $rn, $imm */ + +{ /* AArch64_UCVTFv4i16_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFv4i32_shift, AArch64_INS_UCVTF: ucvtf */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UDIVWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + +{ /* AArch64_UCVTFv8f16, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UCVTFv8i16_shift, AArch64_INS_UCVTF: ucvtf */ + 0, + { 0 } +}, + +{ /* AArch64_UDIVR_ZPmZ_D, AArch64_INS_UDIVR: udivr */ + 0, + { 0 } +}, + +{ /* AArch64_UDIVR_ZPmZ_S, AArch64_INS_UDIVR: udivr */ + 0, + { 0 } +}, + +{ /* AArch64_UDIVWr, AArch64_INS_UDIV: udiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UDIVXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + +{ /* AArch64_UDIVXr, AArch64_INS_UDIV: udiv */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UDIV_IntWr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + +{ /* AArch64_UDIV_ZPmZ_D, AArch64_INS_UDIV: udiv */ + 0, + { 0 } +}, + +{ /* AArch64_UDIV_ZPmZ_S, AArch64_INS_UDIV: udiv */ + 0, + { 0 } +}, + +{ /* AArch64_UDOT_ZZZI_D, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOT_ZZZI_S, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOT_ZZZ_D, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOT_ZZZ_S, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOTlanev16i8, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOTlanev8i8, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOTv16i8, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UDOTv8i8, AArch64_INS_UDOT: udot */ + 0, + { 0 } +}, + +{ /* AArch64_UHADDv16i8, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UDIV_IntXr, ARM64_INS_UDIV: udiv $rd, $rn, $rm */ + +{ /* AArch64_UHADDv2i32, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHADDv16i8, ARM64_INS_UHADD: uhadd.16b $rd, $rn, $rm| */ + +{ /* AArch64_UHADDv4i16, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHADDv2i32, ARM64_INS_UHADD: uhadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_UHADDv4i32, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHADDv4i16, ARM64_INS_UHADD: uhadd.4h $rd, $rn, $rm| */ + +{ /* AArch64_UHADDv8i16, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHADDv4i32, ARM64_INS_UHADD: uhadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_UHADDv8i8, AArch64_INS_UHADD: uhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHADDv8i16, ARM64_INS_UHADD: uhadd.8h $rd, $rn, $rm| */ + +{ /* AArch64_UHSUBv16i8, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHADDv8i8, ARM64_INS_UHADD: uhadd.8b $rd, $rn, $rm| */ + +{ /* AArch64_UHSUBv2i32, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHSUBv16i8, ARM64_INS_UHSUB: uhsub.16b $rd, $rn, $rm| */ + +{ /* AArch64_UHSUBv4i16, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHSUBv2i32, ARM64_INS_UHSUB: uhsub.2s $rd, $rn, $rm| */ + +{ /* AArch64_UHSUBv4i32, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHSUBv4i16, ARM64_INS_UHSUB: uhsub.4h $rd, $rn, $rm| */ + +{ /* AArch64_UHSUBv8i16, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHSUBv4i32, ARM64_INS_UHSUB: uhsub.4s $rd, $rn, $rm| */ + +{ /* AArch64_UHSUBv8i8, AArch64_INS_UHSUB: uhsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UHSUBv8i16, ARM64_INS_UHSUB: uhsub.8h $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_UHSUBv8i8, ARM64_INS_UHSUB: uhsub.8b $rd, $rn, $rm| */ - 0, - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* AArch64_UMADDLrrr, ARM64_INS_UMADDL: umaddl $rd, $rn, $rm, $ra */ + +{ /* AArch64_UMADDLrrr, AArch64_INS_UMADDL: umaddl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXPv16i8, ARM64_INS_UMAXP: umaxp.16b $rd, $rn, $rm| */ + +{ /* AArch64_UMAXPv16i8, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXPv2i32, ARM64_INS_UMAXP: umaxp.2s $rd, $rn, $rm| */ + +{ /* AArch64_UMAXPv2i32, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXPv4i16, ARM64_INS_UMAXP: umaxp.4h $rd, $rn, $rm| */ + +{ /* AArch64_UMAXPv4i16, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXPv4i32, ARM64_INS_UMAXP: umaxp.4s $rd, $rn, $rm| */ + +{ /* AArch64_UMAXPv4i32, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXPv8i16, ARM64_INS_UMAXP: umaxp.8h $rd, $rn, $rm| */ + +{ /* AArch64_UMAXPv8i16, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXPv8i8, ARM64_INS_UMAXP: umaxp.8b $rd, $rn, $rm| */ + +{ /* AArch64_UMAXPv8i8, AArch64_INS_UMAXP: umaxp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXVv16i8v, ARM64_INS_UMAXV: umaxv.16b $rd, $rn */ + +{ /* AArch64_UMAXV_VPZ_B, AArch64_INS_UMAXV: umaxv */ + 0, + { 0 } +}, + +{ /* AArch64_UMAXV_VPZ_D, AArch64_INS_UMAXV: umaxv */ + 0, + { 0 } +}, + +{ /* AArch64_UMAXV_VPZ_H, AArch64_INS_UMAXV: umaxv */ + 0, + { 0 } +}, + +{ /* AArch64_UMAXV_VPZ_S, AArch64_INS_UMAXV: umaxv */ + 0, + { 0 } +}, + +{ /* AArch64_UMAXVv16i8v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXVv4i16v, ARM64_INS_UMAXV: umaxv.4h $rd, $rn */ + +{ /* AArch64_UMAXVv4i16v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXVv4i32v, ARM64_INS_UMAXV: umaxv.4s $rd, $rn */ + +{ /* AArch64_UMAXVv4i32v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXVv8i16v, ARM64_INS_UMAXV: umaxv.8h $rd, $rn */ + +{ /* AArch64_UMAXVv8i16v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXVv8i8v, ARM64_INS_UMAXV: umaxv.8b $rd, $rn */ + +{ /* AArch64_UMAXVv8i8v, AArch64_INS_UMAXV: umaxv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXv16i8, ARM64_INS_UMAX: umax.16b $rd, $rn, $rm| */ + +{ /* AArch64_UMAX_ZI_B, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZI_D, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZI_H, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZI_S, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZPmZ_B, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZPmZ_D, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZPmZ_H, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAX_ZPmZ_S, AArch64_INS_UMAX: umax */ + 0, + { 0 } +}, + +{ /* AArch64_UMAXv16i8, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXv2i32, ARM64_INS_UMAX: umax.2s $rd, $rn, $rm| */ + +{ /* AArch64_UMAXv2i32, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXv4i16, ARM64_INS_UMAX: umax.4h $rd, $rn, $rm| */ + +{ /* AArch64_UMAXv4i16, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXv4i32, ARM64_INS_UMAX: umax.4s $rd, $rn, $rm| */ + +{ /* AArch64_UMAXv4i32, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXv8i16, ARM64_INS_UMAX: umax.8h $rd, $rn, $rm| */ + +{ /* AArch64_UMAXv8i16, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMAXv8i8, ARM64_INS_UMAX: umax.8b $rd, $rn, $rm| */ + +{ /* AArch64_UMAXv8i8, AArch64_INS_UMAX: umax */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINPv16i8, ARM64_INS_UMINP: uminp.16b $rd, $rn, $rm| */ + +{ /* AArch64_UMINPv16i8, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINPv2i32, ARM64_INS_UMINP: uminp.2s $rd, $rn, $rm| */ + +{ /* AArch64_UMINPv2i32, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINPv4i16, ARM64_INS_UMINP: uminp.4h $rd, $rn, $rm| */ + +{ /* AArch64_UMINPv4i16, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINPv4i32, ARM64_INS_UMINP: uminp.4s $rd, $rn, $rm| */ + +{ /* AArch64_UMINPv4i32, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINPv8i16, ARM64_INS_UMINP: uminp.8h $rd, $rn, $rm| */ + +{ /* AArch64_UMINPv8i16, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINPv8i8, ARM64_INS_UMINP: uminp.8b $rd, $rn, $rm| */ + +{ /* AArch64_UMINPv8i8, AArch64_INS_UMINP: uminp */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINVv16i8v, ARM64_INS_UMINV: uminv.16b $rd, $rn */ + +{ /* AArch64_UMINV_VPZ_B, AArch64_INS_UMINV: uminv */ + 0, + { 0 } +}, + +{ /* AArch64_UMINV_VPZ_D, AArch64_INS_UMINV: uminv */ + 0, + { 0 } +}, + +{ /* AArch64_UMINV_VPZ_H, AArch64_INS_UMINV: uminv */ + 0, + { 0 } +}, + +{ /* AArch64_UMINV_VPZ_S, AArch64_INS_UMINV: uminv */ + 0, + { 0 } +}, + +{ /* AArch64_UMINVv16i8v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMINVv4i16v, ARM64_INS_UMINV: uminv.4h $rd, $rn */ + +{ /* AArch64_UMINVv4i16v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMINVv4i32v, ARM64_INS_UMINV: uminv.4s $rd, $rn */ + +{ /* AArch64_UMINVv4i32v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMINVv8i16v, ARM64_INS_UMINV: uminv.8h $rd, $rn */ + +{ /* AArch64_UMINVv8i16v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMINVv8i8v, ARM64_INS_UMINV: uminv.8b $rd, $rn */ + +{ /* AArch64_UMINVv8i8v, AArch64_INS_UMINV: uminv */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UMINv16i8, ARM64_INS_UMIN: umin.16b $rd, $rn, $rm| */ + +{ /* AArch64_UMIN_ZI_B, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZI_D, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZI_H, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZI_S, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZPmZ_B, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZPmZ_D, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZPmZ_H, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMIN_ZPmZ_S, AArch64_INS_UMIN: umin */ + 0, + { 0 } +}, + +{ /* AArch64_UMINv16i8, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINv2i32, ARM64_INS_UMIN: umin.2s $rd, $rn, $rm| */ + +{ /* AArch64_UMINv2i32, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINv4i16, ARM64_INS_UMIN: umin.4h $rd, $rn, $rm| */ + +{ /* AArch64_UMINv4i16, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINv4i32, ARM64_INS_UMIN: umin.4s $rd, $rn, $rm| */ + +{ /* AArch64_UMINv4i32, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINv8i16, ARM64_INS_UMIN: umin.8h $rd, $rn, $rm| */ + +{ /* AArch64_UMINv8i16, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMINv8i8, ARM64_INS_UMIN: umin.8b $rd, $rn, $rm| */ + +{ /* AArch64_UMINv8i8, AArch64_INS_UMIN: umin */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv16i8_v8i16, ARM64_INS_UMLAL2: umlal2.8h $rd, $rn, $rm */ + +{ /* AArch64_UMLALv16i8_v8i16, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv2i32_indexed, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLALv2i32_indexed, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv2i32_v2i64, ARM64_INS_UMLAL: umlal.2d $rd, $rn, $rm */ + +{ /* AArch64_UMLALv2i32_v2i64, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv4i16_indexed, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLALv4i16_indexed, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv4i16_v4i32, ARM64_INS_UMLAL: umlal.4s $rd, $rn, $rm */ + +{ /* AArch64_UMLALv4i16_v4i32, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv4i32_indexed, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLALv4i32_indexed, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv4i32_v2i64, ARM64_INS_UMLAL2: umlal2.2d $rd, $rn, $rm */ + +{ /* AArch64_UMLALv4i32_v2i64, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv8i16_indexed, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLALv8i16_indexed, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv8i16_v4i32, ARM64_INS_UMLAL2: umlal2.4s $rd, $rn, $rm */ + +{ /* AArch64_UMLALv8i16_v4i32, AArch64_INS_UMLAL2: umlal2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLALv8i8_v8i16, ARM64_INS_UMLAL: umlal.8h $rd, $rn, $rm */ + +{ /* AArch64_UMLALv8i8_v8i16, AArch64_INS_UMLAL: umlal */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv16i8_v8i16, ARM64_INS_UMLSL2: umlsl2.8h $rd, $rn, $rm */ + +{ /* AArch64_UMLSLv16i8_v8i16, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv2i32_indexed, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLSLv2i32_indexed, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv2i32_v2i64, ARM64_INS_UMLSL: umlsl.2d $rd, $rn, $rm */ + +{ /* AArch64_UMLSLv2i32_v2i64, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv4i16_indexed, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLSLv4i16_indexed, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv4i16_v4i32, ARM64_INS_UMLSL: umlsl.4s $rd, $rn, $rm */ + +{ /* AArch64_UMLSLv4i16_v4i32, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv4i32_indexed, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLSLv4i32_indexed, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv4i32_v2i64, ARM64_INS_UMLSL2: umlsl2.2d $rd, $rn, $rm */ + +{ /* AArch64_UMLSLv4i32_v2i64, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv8i16_indexed, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_UMLSLv8i16_indexed, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv8i16_v4i32, ARM64_INS_UMLSL2: umlsl2.4s $rd, $rn, $rm */ + +{ /* AArch64_UMLSLv8i16_v4i32, AArch64_INS_UMLSL2: umlsl2 */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMLSLv8i8_v8i16, ARM64_INS_UMLSL: umlsl.8h $rd, $rn, $rm */ + +{ /* AArch64_UMLSLv8i8_v8i16, AArch64_INS_UMLSL: umlsl */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMOVvi16, ARM64_INS_UMOV: umov.h $rd, $rn$idx */ + +{ /* AArch64_UMOVvi16, AArch64_INS_UMOV: umov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMOVvi32, ARM64_INS_UMOV: umov.s $rd, $rn$idx */ + +{ /* AArch64_UMOVvi32, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMOVvi64, ARM64_INS_UMOV: umov.d $rd, $rn$idx */ + +{ /* AArch64_UMOVvi64, AArch64_INS_MOV: mov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMOVvi8, ARM64_INS_UMOV: umov.b $rd, $rn$idx */ + +{ /* AArch64_UMOVvi8, AArch64_INS_UMOV: umov */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMSUBLrrr, ARM64_INS_UMSUBL: umsubl $rd, $rn, $rm, $ra */ + +{ /* AArch64_UMSUBLrrr, AArch64_INS_UMNEGL: umnegl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULHrr, ARM64_INS_UMULH: umulh $rd, $rn, $rm */ + +{ /* AArch64_UMULH_ZPmZ_B, AArch64_INS_UMULH: umulh */ + 0, + { 0 } +}, + +{ /* AArch64_UMULH_ZPmZ_D, AArch64_INS_UMULH: umulh */ + 0, + { 0 } +}, + +{ /* AArch64_UMULH_ZPmZ_H, AArch64_INS_UMULH: umulh */ + 0, + { 0 } +}, + +{ /* AArch64_UMULH_ZPmZ_S, AArch64_INS_UMULH: umulh */ + 0, + { 0 } +}, + +{ /* AArch64_UMULHrr, AArch64_INS_UMULH: umulh */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv16i8_v8i16, ARM64_INS_UMULL2: umull2.8h $rd, $rn, $rm */ + +{ /* AArch64_UMULLv16i8_v8i16, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv2i32_indexed, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_UMULLv2i32_indexed, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv2i32_v2i64, ARM64_INS_UMULL: umull.2d $rd, $rn, $rm */ + +{ /* AArch64_UMULLv2i32_v2i64, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv4i16_indexed, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_UMULLv4i16_indexed, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv4i16_v4i32, ARM64_INS_UMULL: umull.4s $rd, $rn, $rm */ + +{ /* AArch64_UMULLv4i16_v4i32, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv4i32_indexed, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm$idx */ + +{ /* AArch64_UMULLv4i32_indexed, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv4i32_v2i64, ARM64_INS_UMULL2: umull2.2d $rd, $rn, $rm */ + +{ /* AArch64_UMULLv4i32_v2i64, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv8i16_indexed, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm$idx */ + +{ /* AArch64_UMULLv8i16_indexed, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv8i16_v4i32, ARM64_INS_UMULL2: umull2.4s $rd, $rn, $rm */ + +{ /* AArch64_UMULLv8i16_v4i32, AArch64_INS_UMULL2: umull2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UMULLv8i8_v8i16, ARM64_INS_UMULL: umull.8h $rd, $rn, $rm */ + +{ /* AArch64_UMULLv8i8_v8i16, AArch64_INS_UMULL: umull */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv16i8, ARM64_INS_UQADD: uqadd.16b $rd, $rn, $rm| */ + +{ /* AArch64_UQADD_ZI_B, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZI_D, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZI_H, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZI_S, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZZZ_B, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZZZ_D, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZZZ_H, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADD_ZZZ_S, AArch64_INS_UQADD: uqadd */ + 0, + { 0 } +}, + +{ /* AArch64_UQADDv16i8, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv1i16, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + +{ /* AArch64_UQADDv1i16, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv1i32, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + +{ /* AArch64_UQADDv1i32, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv1i64, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + +{ /* AArch64_UQADDv1i64, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv1i8, ARM64_INS_UQADD: uqadd $rd, $rn, $rm */ + +{ /* AArch64_UQADDv1i8, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv2i32, ARM64_INS_UQADD: uqadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_UQADDv2i32, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv2i64, ARM64_INS_UQADD: uqadd.2d $rd, $rn, $rm| */ + +{ /* AArch64_UQADDv2i64, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv4i16, ARM64_INS_UQADD: uqadd.4h $rd, $rn, $rm| */ + +{ /* AArch64_UQADDv4i16, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv4i32, ARM64_INS_UQADD: uqadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_UQADDv4i32, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv8i16, ARM64_INS_UQADD: uqadd.8h $rd, $rn, $rm| */ + +{ /* AArch64_UQADDv8i16, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQADDv8i8, ARM64_INS_UQADD: uqadd.8b $rd, $rn, $rm| */ + +{ /* AArch64_UQADDv8i8, AArch64_INS_UQADD: uqadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv16i8, ARM64_INS_UQRSHL: uqrshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_UQDECB_WPiI, AArch64_INS_UQDECB: uqdecb */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECB_XPiI, AArch64_INS_UQDECB: uqdecb */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECD_WPiI, AArch64_INS_UQDECD: uqdecd */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECD_XPiI, AArch64_INS_UQDECD: uqdecd */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECD_ZPiI, AArch64_INS_UQDECD: uqdecd */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECH_WPiI, AArch64_INS_UQDECH: uqdech */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECH_XPiI, AArch64_INS_UQDECH: uqdech */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECH_ZPiI, AArch64_INS_UQDECH: uqdech */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_WP_B, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_WP_D, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_WP_H, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_WP_S, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_XP_B, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_XP_D, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_XP_H, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_XP_S, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_ZP_D, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_ZP_H, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECP_ZP_S, AArch64_INS_UQDECP: uqdecp */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECW_WPiI, AArch64_INS_UQDECW: uqdecw */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECW_XPiI, AArch64_INS_UQDECW: uqdecw */ + 0, + { 0 } +}, + +{ /* AArch64_UQDECW_ZPiI, AArch64_INS_UQDECW: uqdecw */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCB_WPiI, AArch64_INS_UQINCB: uqincb */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCB_XPiI, AArch64_INS_UQINCB: uqincb */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCD_WPiI, AArch64_INS_UQINCD: uqincd */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCD_XPiI, AArch64_INS_UQINCD: uqincd */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCD_ZPiI, AArch64_INS_UQINCD: uqincd */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCH_WPiI, AArch64_INS_UQINCH: uqinch */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCH_XPiI, AArch64_INS_UQINCH: uqinch */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCH_ZPiI, AArch64_INS_UQINCH: uqinch */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_WP_B, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_WP_D, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_WP_H, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_WP_S, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_XP_B, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_XP_D, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_XP_H, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_XP_S, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_ZP_D, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_ZP_H, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCP_ZP_S, AArch64_INS_UQINCP: uqincp */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCW_WPiI, AArch64_INS_UQINCW: uqincw */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCW_XPiI, AArch64_INS_UQINCW: uqincw */ + 0, + { 0 } +}, + +{ /* AArch64_UQINCW_ZPiI, AArch64_INS_UQINCW: uqincw */ + 0, + { 0 } +}, + +{ /* AArch64_UQRSHLv16i8, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv1i16, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + +{ /* AArch64_UQRSHLv1i16, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv1i32, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + +{ /* AArch64_UQRSHLv1i32, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv1i64, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + +{ /* AArch64_UQRSHLv1i64, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv1i8, ARM64_INS_UQRSHL: uqrshl $rd, $rn, $rm */ + +{ /* AArch64_UQRSHLv1i8, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv2i32, ARM64_INS_UQRSHL: uqrshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_UQRSHLv2i32, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv2i64, ARM64_INS_UQRSHL: uqrshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_UQRSHLv2i64, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv4i16, ARM64_INS_UQRSHL: uqrshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_UQRSHLv4i16, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv4i32, ARM64_INS_UQRSHL: uqrshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_UQRSHLv4i32, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv8i16, ARM64_INS_UQRSHL: uqrshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_UQRSHLv8i16, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHLv8i8, ARM64_INS_UQRSHL: uqrshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_UQRSHLv8i8, AArch64_INS_UQRSHL: uqrshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNb, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNb, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNh, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNh, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNs, ARM64_INS_UQRSHRN: uqrshrn $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNs, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNv16i8_shift, ARM64_INS_UQRSHRN2: uqrshrn2.16b $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNv16i8_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNv2i32_shift, ARM64_INS_UQRSHRN: uqrshrn.2s $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNv2i32_shift, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNv4i16_shift, ARM64_INS_UQRSHRN: uqrshrn.4h $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNv4i16_shift, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNv4i32_shift, ARM64_INS_UQRSHRN2: uqrshrn2.4s $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNv4i32_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNv8i16_shift, ARM64_INS_UQRSHRN2: uqrshrn2.8h $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNv8i16_shift, AArch64_INS_UQRSHRN2: uqrshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQRSHRNv8i8_shift, ARM64_INS_UQRSHRN: uqrshrn.8b $rd, $rn, $imm */ + +{ /* AArch64_UQRSHRNv8i8_shift, AArch64_INS_UQRSHRN: uqrshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLb, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + +{ /* AArch64_UQSHLb, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLd, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + +{ /* AArch64_UQSHLd, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLh, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + +{ /* AArch64_UQSHLh, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLs, ARM64_INS_UQSHL: uqshl $rd, $rn, $imm */ + +{ /* AArch64_UQSHLs, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv16i8, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv16i8, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv16i8_shift, ARM64_INS_UQSHL: uqshl.16b $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv16i8_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv1i16, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + +{ /* AArch64_UQSHLv1i16, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv1i32, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + +{ /* AArch64_UQSHLv1i32, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv1i64, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + +{ /* AArch64_UQSHLv1i64, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv1i8, ARM64_INS_UQSHL: uqshl $rd, $rn, $rm */ + +{ /* AArch64_UQSHLv1i8, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv2i32, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv2i32, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv2i32_shift, ARM64_INS_UQSHL: uqshl.2s $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv2i32_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv2i64, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv2i64, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv2i64_shift, ARM64_INS_UQSHL: uqshl.2d $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv2i64_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv4i16, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv4i16, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv4i16_shift, ARM64_INS_UQSHL: uqshl.4h $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv4i16_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv4i32, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv4i32, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv4i32_shift, ARM64_INS_UQSHL: uqshl.4s $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv4i32_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv8i16, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv8i16, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv8i16_shift, ARM64_INS_UQSHL: uqshl.8h $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv8i16_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv8i8, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_UQSHLv8i8, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHLv8i8_shift, ARM64_INS_UQSHL: uqshl.8b $rd, $rn, $imm */ + +{ /* AArch64_UQSHLv8i8_shift, AArch64_INS_UQSHL: uqshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNb, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNb, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNh, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNh, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNs, ARM64_INS_UQSHRN: uqshrn $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNs, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNv16i8_shift, ARM64_INS_UQSHRN2: uqshrn2.16b $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNv16i8_shift, AArch64_INS_UQSHRN2: uqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNv2i32_shift, ARM64_INS_UQSHRN: uqshrn.2s $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNv2i32_shift, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNv4i16_shift, ARM64_INS_UQSHRN: uqshrn.4h $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNv4i16_shift, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNv4i32_shift, ARM64_INS_UQSHRN2: uqshrn2.4s $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNv4i32_shift, AArch64_INS_UQSHRN2: uqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNv8i16_shift, ARM64_INS_UQSHRN2: uqshrn2.8h $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNv8i16_shift, AArch64_INS_UQSHRN2: uqshrn2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSHRNv8i8_shift, ARM64_INS_UQSHRN: uqshrn.8b $rd, $rn, $imm */ + +{ /* AArch64_UQSHRNv8i8_shift, AArch64_INS_UQSHRN: uqshrn */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv16i8, ARM64_INS_UQSUB: uqsub.16b $rd, $rn, $rm| */ + +{ /* AArch64_UQSUB_ZI_B, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZI_D, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZI_H, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZI_S, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZZZ_B, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZZZ_D, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZZZ_H, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUB_ZZZ_S, AArch64_INS_UQSUB: uqsub */ + 0, + { 0 } +}, + +{ /* AArch64_UQSUBv16i8, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv1i16, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + +{ /* AArch64_UQSUBv1i16, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv1i32, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + +{ /* AArch64_UQSUBv1i32, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv1i64, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + +{ /* AArch64_UQSUBv1i64, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv1i8, ARM64_INS_UQSUB: uqsub $rd, $rn, $rm */ + +{ /* AArch64_UQSUBv1i8, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv2i32, ARM64_INS_UQSUB: uqsub.2s $rd, $rn, $rm| */ + +{ /* AArch64_UQSUBv2i32, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv2i64, ARM64_INS_UQSUB: uqsub.2d $rd, $rn, $rm| */ + +{ /* AArch64_UQSUBv2i64, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv4i16, ARM64_INS_UQSUB: uqsub.4h $rd, $rn, $rm| */ + +{ /* AArch64_UQSUBv4i16, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv4i32, ARM64_INS_UQSUB: uqsub.4s $rd, $rn, $rm| */ + +{ /* AArch64_UQSUBv4i32, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv8i16, ARM64_INS_UQSUB: uqsub.8h $rd, $rn, $rm| */ + +{ /* AArch64_UQSUBv8i16, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQSUBv8i8, ARM64_INS_UQSUB: uqsub.8b $rd, $rn, $rm| */ + +{ /* AArch64_UQSUBv8i8, AArch64_INS_UQSUB: uqsub */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv16i8, ARM64_INS_UQXTN2: uqxtn2.16b $rd, $rn */ + +{ /* AArch64_UQXTNv16i8, AArch64_INS_UQXTN2: uqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv1i16, ARM64_INS_UQXTN: uqxtn $rd, $rn */ + +{ /* AArch64_UQXTNv1i16, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv1i32, ARM64_INS_UQXTN: uqxtn $rd, $rn */ + +{ /* AArch64_UQXTNv1i32, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv1i8, ARM64_INS_UQXTN: uqxtn $rd, $rn */ + +{ /* AArch64_UQXTNv1i8, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv2i32, ARM64_INS_UQXTN: uqxtn.2s $rd, $rn */ + +{ /* AArch64_UQXTNv2i32, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv4i16, ARM64_INS_UQXTN: uqxtn.4h $rd, $rn */ + +{ /* AArch64_UQXTNv4i16, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv4i32, ARM64_INS_UQXTN2: uqxtn2.4s $rd, $rn */ + +{ /* AArch64_UQXTNv4i32, AArch64_INS_UQXTN2: uqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv8i16, ARM64_INS_UQXTN2: uqxtn2.8h $rd, $rn */ + +{ /* AArch64_UQXTNv8i16, AArch64_INS_UQXTN2: uqxtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_UQXTNv8i8, ARM64_INS_UQXTN: uqxtn.8b $rd, $rn */ + +{ /* AArch64_UQXTNv8i8, AArch64_INS_UQXTN: uqxtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_URECPEv2i32, ARM64_INS_URECPE: urecpe.2s $rd, $rn */ + +{ /* AArch64_URECPEv2i32, AArch64_INS_URECPE: urecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_URECPEv4i32, ARM64_INS_URECPE: urecpe.4s $rd, $rn */ + +{ /* AArch64_URECPEv4i32, AArch64_INS_URECPE: urecpe */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_URHADDv16i8, ARM64_INS_URHADD: urhadd.16b $rd, $rn, $rm| */ + +{ /* AArch64_URHADDv16i8, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URHADDv2i32, ARM64_INS_URHADD: urhadd.2s $rd, $rn, $rm| */ + +{ /* AArch64_URHADDv2i32, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URHADDv4i16, ARM64_INS_URHADD: urhadd.4h $rd, $rn, $rm| */ + +{ /* AArch64_URHADDv4i16, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URHADDv4i32, ARM64_INS_URHADD: urhadd.4s $rd, $rn, $rm| */ + +{ /* AArch64_URHADDv4i32, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URHADDv8i16, ARM64_INS_URHADD: urhadd.8h $rd, $rn, $rm| */ + +{ /* AArch64_URHADDv8i16, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URHADDv8i8, ARM64_INS_URHADD: urhadd.8b $rd, $rn, $rm| */ + +{ /* AArch64_URHADDv8i8, AArch64_INS_URHADD: urhadd */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv16i8, ARM64_INS_URSHL: urshl.16b $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv16i8, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv1i64, ARM64_INS_URSHL: urshl $rd, $rn, $rm */ + +{ /* AArch64_URSHLv1i64, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv2i32, ARM64_INS_URSHL: urshl.2s $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv2i32, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv2i64, ARM64_INS_URSHL: urshl.2d $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv2i64, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv4i16, ARM64_INS_URSHL: urshl.4h $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv4i16, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv4i32, ARM64_INS_URSHL: urshl.4s $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv4i32, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv8i16, ARM64_INS_URSHL: urshl.8h $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv8i16, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHLv8i8, ARM64_INS_URSHL: urshl.8b $rd, $rn, $rm| */ + +{ /* AArch64_URSHLv8i8, AArch64_INS_URSHL: urshl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRd, ARM64_INS_URSHR: urshr $rd, $rn, $imm */ + +{ /* AArch64_URSHRd, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv16i8_shift, ARM64_INS_URSHR: urshr.16b $rd, $rn, $imm */ + +{ /* AArch64_URSHRv16i8_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv2i32_shift, ARM64_INS_URSHR: urshr.2s $rd, $rn, $imm */ + +{ /* AArch64_URSHRv2i32_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv2i64_shift, ARM64_INS_URSHR: urshr.2d $rd, $rn, $imm */ + +{ /* AArch64_URSHRv2i64_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv4i16_shift, ARM64_INS_URSHR: urshr.4h $rd, $rn, $imm */ + +{ /* AArch64_URSHRv4i16_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv4i32_shift, ARM64_INS_URSHR: urshr.4s $rd, $rn, $imm */ + +{ /* AArch64_URSHRv4i32_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv8i16_shift, ARM64_INS_URSHR: urshr.8h $rd, $rn, $imm */ + +{ /* AArch64_URSHRv8i16_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSHRv8i8_shift, ARM64_INS_URSHR: urshr.8b $rd, $rn, $imm */ + +{ /* AArch64_URSHRv8i8_shift, AArch64_INS_URSHR: urshr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSQRTEv2i32, ARM64_INS_URSQRTE: ursqrte.2s $rd, $rn */ + +{ /* AArch64_URSQRTEv2i32, AArch64_INS_URSQRTE: ursqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_URSQRTEv4i32, ARM64_INS_URSQRTE: ursqrte.4s $rd, $rn */ + +{ /* AArch64_URSQRTEv4i32, AArch64_INS_URSQRTE: ursqrte */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAd, ARM64_INS_URSRA: ursra $rd, $rn, $imm */ + +{ /* AArch64_URSRAd, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv16i8_shift, ARM64_INS_URSRA: ursra.16b $rd, $rn, $imm */ + +{ /* AArch64_URSRAv16i8_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv2i32_shift, ARM64_INS_URSRA: ursra.2s $rd, $rn, $imm */ + +{ /* AArch64_URSRAv2i32_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv2i64_shift, ARM64_INS_URSRA: ursra.2d $rd, $rn, $imm */ + +{ /* AArch64_URSRAv2i64_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv4i16_shift, ARM64_INS_URSRA: ursra.4h $rd, $rn, $imm */ + +{ /* AArch64_URSRAv4i16_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv4i32_shift, ARM64_INS_URSRA: ursra.4s $rd, $rn, $imm */ + +{ /* AArch64_URSRAv4i32_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv8i16_shift, ARM64_INS_URSRA: ursra.8h $rd, $rn, $imm */ + +{ /* AArch64_URSRAv8i16_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_URSRAv8i8_shift, ARM64_INS_URSRA: ursra.8b $rd, $rn, $imm */ + +{ /* AArch64_URSRAv8i8_shift, AArch64_INS_URSRA: ursra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLLv16i8_shift, ARM64_INS_USHLL2: ushll2.8h $rd, $rn, $imm */ + +{ /* AArch64_USHLLv16i8_shift, AArch64_INS_USHLL2: ushll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLLv2i32_shift, ARM64_INS_USHLL: ushll.2d $rd, $rn, $imm */ + +{ /* AArch64_USHLLv2i32_shift, AArch64_INS_USHLL: ushll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLLv4i16_shift, ARM64_INS_USHLL: ushll.4s $rd, $rn, $imm */ + +{ /* AArch64_USHLLv4i16_shift, AArch64_INS_USHLL: ushll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLLv4i32_shift, ARM64_INS_USHLL2: ushll2.2d $rd, $rn, $imm */ + +{ /* AArch64_USHLLv4i32_shift, AArch64_INS_USHLL2: ushll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLLv8i16_shift, ARM64_INS_USHLL2: ushll2.4s $rd, $rn, $imm */ + +{ /* AArch64_USHLLv8i16_shift, AArch64_INS_USHLL2: ushll2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLLv8i8_shift, ARM64_INS_USHLL: ushll.8h $rd, $rn, $imm */ + +{ /* AArch64_USHLLv8i8_shift, AArch64_INS_USHLL: ushll */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv16i8, ARM64_INS_USHL: ushl.16b $rd, $rn, $rm| */ + +{ /* AArch64_USHLv16i8, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv1i64, ARM64_INS_USHL: ushl $rd, $rn, $rm */ + +{ /* AArch64_USHLv1i64, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv2i32, ARM64_INS_USHL: ushl.2s $rd, $rn, $rm| */ + +{ /* AArch64_USHLv2i32, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv2i64, ARM64_INS_USHL: ushl.2d $rd, $rn, $rm| */ + +{ /* AArch64_USHLv2i64, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv4i16, ARM64_INS_USHL: ushl.4h $rd, $rn, $rm| */ + +{ /* AArch64_USHLv4i16, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv4i32, ARM64_INS_USHL: ushl.4s $rd, $rn, $rm| */ + +{ /* AArch64_USHLv4i32, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv8i16, ARM64_INS_USHL: ushl.8h $rd, $rn, $rm| */ + +{ /* AArch64_USHLv8i16, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHLv8i8, ARM64_INS_USHL: ushl.8b $rd, $rn, $rm| */ + +{ /* AArch64_USHLv8i8, AArch64_INS_USHL: ushl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRd, ARM64_INS_USHR: ushr $rd, $rn, $imm */ + +{ /* AArch64_USHRd, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv16i8_shift, ARM64_INS_USHR: ushr.16b $rd, $rn, $imm */ + +{ /* AArch64_USHRv16i8_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv2i32_shift, ARM64_INS_USHR: ushr.2s $rd, $rn, $imm */ + +{ /* AArch64_USHRv2i32_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv2i64_shift, ARM64_INS_USHR: ushr.2d $rd, $rn, $imm */ + +{ /* AArch64_USHRv2i64_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv4i16_shift, ARM64_INS_USHR: ushr.4h $rd, $rn, $imm */ + +{ /* AArch64_USHRv4i16_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv4i32_shift, ARM64_INS_USHR: ushr.4s $rd, $rn, $imm */ + +{ /* AArch64_USHRv4i32_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv8i16_shift, ARM64_INS_USHR: ushr.8h $rd, $rn, $imm */ + +{ /* AArch64_USHRv8i16_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USHRv8i8_shift, ARM64_INS_USHR: ushr.8b $rd, $rn, $imm */ + +{ /* AArch64_USHRv8i8_shift, AArch64_INS_USHR: ushr */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv16i8, ARM64_INS_USQADD: usqadd.16b $rd, $rn */ + +{ /* AArch64_USQADDv16i8, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv1i16, ARM64_INS_USQADD: usqadd $rd, $rn */ + +{ /* AArch64_USQADDv1i16, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv1i32, ARM64_INS_USQADD: usqadd $rd, $rn */ + +{ /* AArch64_USQADDv1i32, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv1i64, ARM64_INS_USQADD: usqadd $rd, $rn */ + +{ /* AArch64_USQADDv1i64, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv1i8, ARM64_INS_USQADD: usqadd $rd, $rn */ + +{ /* AArch64_USQADDv1i8, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv2i32, ARM64_INS_USQADD: usqadd.2s $rd, $rn */ + +{ /* AArch64_USQADDv2i32, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv2i64, ARM64_INS_USQADD: usqadd.2d $rd, $rn */ + +{ /* AArch64_USQADDv2i64, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv4i16, ARM64_INS_USQADD: usqadd.4h $rd, $rn */ + +{ /* AArch64_USQADDv4i16, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv4i32, ARM64_INS_USQADD: usqadd.4s $rd, $rn */ + +{ /* AArch64_USQADDv4i32, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv8i16, ARM64_INS_USQADD: usqadd.8h $rd, $rn */ + +{ /* AArch64_USQADDv8i16, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USQADDv8i8, ARM64_INS_USQADD: usqadd.8b $rd, $rn */ + +{ /* AArch64_USQADDv8i8, AArch64_INS_USQADD: usqadd */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAd, ARM64_INS_USRA: usra $rd, $rn, $imm */ + +{ /* AArch64_USRAd, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv16i8_shift, ARM64_INS_USRA: usra.16b $rd, $rn, $imm */ + +{ /* AArch64_USRAv16i8_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv2i32_shift, ARM64_INS_USRA: usra.2s $rd, $rn, $imm */ + +{ /* AArch64_USRAv2i32_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv2i64_shift, ARM64_INS_USRA: usra.2d $rd, $rn, $imm */ + +{ /* AArch64_USRAv2i64_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv4i16_shift, ARM64_INS_USRA: usra.4h $rd, $rn, $imm */ + +{ /* AArch64_USRAv4i16_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv4i32_shift, ARM64_INS_USRA: usra.4s $rd, $rn, $imm */ + +{ /* AArch64_USRAv4i32_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv8i16_shift, ARM64_INS_USRA: usra.8h $rd, $rn, $imm */ + +{ /* AArch64_USRAv8i16_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USRAv8i8_shift, ARM64_INS_USRA: usra.8b $rd, $rn, $imm */ + +{ /* AArch64_USRAv8i8_shift, AArch64_INS_USRA: usra */ 0, { CS_AC_WRITE | CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBLv16i8_v8i16, ARM64_INS_USUBL2: usubl2.8h $rd, $rn, $rm */ + +{ /* AArch64_USUBLv16i8_v8i16, AArch64_INS_USUBL2: usubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBLv2i32_v2i64, ARM64_INS_USUBL: usubl.2d $rd, $rn, $rm */ + +{ /* AArch64_USUBLv2i32_v2i64, AArch64_INS_USUBL: usubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBLv4i16_v4i32, ARM64_INS_USUBL: usubl.4s $rd, $rn, $rm */ + +{ /* AArch64_USUBLv4i16_v4i32, AArch64_INS_USUBL: usubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBLv4i32_v2i64, ARM64_INS_USUBL2: usubl2.2d $rd, $rn, $rm */ + +{ /* AArch64_USUBLv4i32_v2i64, AArch64_INS_USUBL2: usubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBLv8i16_v4i32, ARM64_INS_USUBL2: usubl2.4s $rd, $rn, $rm */ + +{ /* AArch64_USUBLv8i16_v4i32, AArch64_INS_USUBL2: usubl2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBLv8i8_v8i16, ARM64_INS_USUBL: usubl.8h $rd, $rn, $rm */ + +{ /* AArch64_USUBLv8i8_v8i16, AArch64_INS_USUBL: usubl */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBWv16i8_v8i16, ARM64_INS_USUBW2: usubw2.8h $rd, $rn, $rm */ + +{ /* AArch64_USUBWv16i8_v8i16, AArch64_INS_USUBW2: usubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBWv2i32_v2i64, ARM64_INS_USUBW: usubw.2d $rd, $rn, $rm */ + +{ /* AArch64_USUBWv2i32_v2i64, AArch64_INS_USUBW: usubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBWv4i16_v4i32, ARM64_INS_USUBW: usubw.4s $rd, $rn, $rm */ + +{ /* AArch64_USUBWv4i16_v4i32, AArch64_INS_USUBW: usubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBWv4i32_v2i64, ARM64_INS_USUBW2: usubw2.2d $rd, $rn, $rm */ + +{ /* AArch64_USUBWv4i32_v2i64, AArch64_INS_USUBW2: usubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBWv8i16_v4i32, ARM64_INS_USUBW2: usubw2.4s $rd, $rn, $rm */ + +{ /* AArch64_USUBWv8i16_v4i32, AArch64_INS_USUBW2: usubw2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_USUBWv8i8_v8i16, ARM64_INS_USUBW: usubw.8h $rd, $rn, $rm */ + +{ /* AArch64_USUBWv8i8_v8i16, AArch64_INS_USUBW: usubw */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v16i8, ARM64_INS_UZP1: uzp1.16b $rd, $rn, $rm */ + +{ /* AArch64_UUNPKHI_ZZ_D, AArch64_INS_UUNPKHI: uunpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_UUNPKHI_ZZ_H, AArch64_INS_UUNPKHI: uunpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_UUNPKHI_ZZ_S, AArch64_INS_UUNPKHI: uunpkhi */ + 0, + { 0 } +}, + +{ /* AArch64_UUNPKLO_ZZ_D, AArch64_INS_UUNPKLO: uunpklo */ + 0, + { 0 } +}, + +{ /* AArch64_UUNPKLO_ZZ_H, AArch64_INS_UUNPKLO: uunpklo */ + 0, + { 0 } +}, + +{ /* AArch64_UUNPKLO_ZZ_S, AArch64_INS_UUNPKLO: uunpklo */ + 0, + { 0 } +}, + +{ /* AArch64_UXTB_ZPmZ_D, AArch64_INS_UXTB: uxtb */ + 0, + { 0 } +}, + +{ /* AArch64_UXTB_ZPmZ_H, AArch64_INS_UXTB: uxtb */ + 0, + { 0 } +}, + +{ /* AArch64_UXTB_ZPmZ_S, AArch64_INS_UXTB: uxtb */ + 0, + { 0 } +}, + +{ /* AArch64_UXTH_ZPmZ_D, AArch64_INS_UXTH: uxth */ + 0, + { 0 } +}, + +{ /* AArch64_UXTH_ZPmZ_S, AArch64_INS_UXTH: uxth */ + 0, + { 0 } +}, + +{ /* AArch64_UXTW_ZPmZ_D, AArch64_INS_UXTW: uxtw */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_PPP_B, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_PPP_D, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_PPP_H, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_PPP_S, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_ZZZ_B, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_ZZZ_D, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_ZZZ_H, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1_ZZZ_S, AArch64_INS_UZP1: uzp1 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP1v16i8, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v2i32, ARM64_INS_UZP1: uzp1.2s $rd, $rn, $rm */ + +{ /* AArch64_UZP1v2i32, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v2i64, ARM64_INS_UZP1: uzp1.2d $rd, $rn, $rm */ + +{ /* AArch64_UZP1v2i64, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v4i16, ARM64_INS_UZP1: uzp1.4h $rd, $rn, $rm */ + +{ /* AArch64_UZP1v4i16, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v4i32, ARM64_INS_UZP1: uzp1.4s $rd, $rn, $rm */ + +{ /* AArch64_UZP1v4i32, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v8i16, ARM64_INS_UZP1: uzp1.8h $rd, $rn, $rm */ + +{ /* AArch64_UZP1v8i16, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP1v8i8, ARM64_INS_UZP1: uzp1.8b $rd, $rn, $rm */ + +{ /* AArch64_UZP1v8i8, AArch64_INS_UZP1: uzp1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v16i8, ARM64_INS_UZP2: uzp2.16b $rd, $rn, $rm */ + +{ /* AArch64_UZP2_PPP_B, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_PPP_D, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_PPP_H, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_PPP_S, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_ZZZ_B, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_ZZZ_D, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_ZZZ_H, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2_ZZZ_S, AArch64_INS_UZP2: uzp2 */ + 0, + { 0 } +}, + +{ /* AArch64_UZP2v16i8, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v2i32, ARM64_INS_UZP2: uzp2.2s $rd, $rn, $rm */ + +{ /* AArch64_UZP2v2i32, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v2i64, ARM64_INS_UZP2: uzp2.2d $rd, $rn, $rm */ + +{ /* AArch64_UZP2v2i64, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v4i16, ARM64_INS_UZP2: uzp2.4h $rd, $rn, $rm */ + +{ /* AArch64_UZP2v4i16, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v4i32, ARM64_INS_UZP2: uzp2.4s $rd, $rn, $rm */ + +{ /* AArch64_UZP2v4i32, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v8i16, ARM64_INS_UZP2: uzp2.8h $rd, $rn, $rm */ + +{ /* AArch64_UZP2v8i16, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_UZP2v8i8, ARM64_INS_UZP2: uzp2.8b $rd, $rn, $rm */ + +{ /* AArch64_UZP2v8i8, AArch64_INS_UZP2: uzp2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_XTNv16i8, ARM64_INS_XTN2: xtn2.16b $rd, $rn */ + +{ /* AArch64_WHILELE_PWW_B, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PWW_D, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PWW_H, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PWW_S, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PXX_B, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PXX_D, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PXX_H, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELE_PXX_S, AArch64_INS_WHILELE: whilele */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PWW_B, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PWW_D, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PWW_H, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PWW_S, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PXX_B, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PXX_D, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PXX_H, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELO_PXX_S, AArch64_INS_WHILELO: whilelo */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PWW_B, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PWW_D, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PWW_H, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PWW_S, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PXX_B, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PXX_D, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PXX_H, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELS_PXX_S, AArch64_INS_WHILELS: whilels */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PWW_B, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PWW_D, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PWW_H, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PWW_S, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PXX_B, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PXX_D, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PXX_H, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WHILELT_PXX_S, AArch64_INS_WHILELT: whilelt */ + 0, + { 0 } +}, + +{ /* AArch64_WRFFR, AArch64_INS_WRFFR: wrffr */ + 0, + { 0 } +}, + +{ /* AArch64_XAR, AArch64_INS_XAR: xar */ + 0, + { 0 } +}, + +{ /* AArch64_XPACD, AArch64_INS_XPACD: xpacd */ + 0, + { 0 } +}, + +{ /* AArch64_XPACI, AArch64_INS_XPACI: xpaci */ + 0, + { 0 } +}, + +{ /* AArch64_XPACLRI, AArch64_INS_XPACLRI: xpaclri */ + 0, + { 0 } +}, + +{ /* AArch64_XTNv16i8, AArch64_INS_XTN2: xtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_XTNv2i32, ARM64_INS_XTN: xtn.2s $rd, $rn */ + +{ /* AArch64_XTNv2i32, AArch64_INS_XTN: xtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_XTNv4i16, ARM64_INS_XTN: xtn.4h $rd, $rn */ + +{ /* AArch64_XTNv4i16, AArch64_INS_XTN: xtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_XTNv4i32, ARM64_INS_XTN2: xtn2.4s $rd, $rn */ + +{ /* AArch64_XTNv4i32, AArch64_INS_XTN2: xtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_XTNv8i16, ARM64_INS_XTN2: xtn2.8h $rd, $rn */ + +{ /* AArch64_XTNv8i16, AArch64_INS_XTN2: xtn2 */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_XTNv8i8, ARM64_INS_XTN: xtn.8b $rd, $rn */ + +{ /* AArch64_XTNv8i8, AArch64_INS_XTN: xtn */ 0, { CS_AC_WRITE, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v16i8, ARM64_INS_ZIP1: zip1.16b $rd, $rn, $rm */ + +{ /* AArch64_ZIP1_PPP_B, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_PPP_D, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_PPP_H, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_PPP_S, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_ZZZ_B, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_ZZZ_D, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_ZZZ_H, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1_ZZZ_S, AArch64_INS_ZIP1: zip1 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP1v16i8, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v2i32, ARM64_INS_ZIP1: zip1.2s $rd, $rn, $rm */ + +{ /* AArch64_ZIP1v2i32, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v2i64, ARM64_INS_ZIP1: zip1.2d $rd, $rn, $rm */ + +{ /* AArch64_ZIP1v2i64, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v4i16, ARM64_INS_ZIP1: zip1.4h $rd, $rn, $rm */ + +{ /* AArch64_ZIP1v4i16, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v4i32, ARM64_INS_ZIP1: zip1.4s $rd, $rn, $rm */ + +{ /* AArch64_ZIP1v4i32, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v8i16, ARM64_INS_ZIP1: zip1.8h $rd, $rn, $rm */ + +{ /* AArch64_ZIP1v8i16, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP1v8i8, ARM64_INS_ZIP1: zip1.8b $rd, $rn, $rm */ + +{ /* AArch64_ZIP1v8i8, AArch64_INS_ZIP1: zip1 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v16i8, ARM64_INS_ZIP2: zip2.16b $rd, $rn, $rm */ + +{ /* AArch64_ZIP2_PPP_B, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_PPP_D, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_PPP_H, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_PPP_S, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_ZZZ_B, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_ZZZ_D, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_ZZZ_H, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2_ZZZ_S, AArch64_INS_ZIP2: zip2 */ + 0, + { 0 } +}, + +{ /* AArch64_ZIP2v16i8, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v2i32, ARM64_INS_ZIP2: zip2.2s $rd, $rn, $rm */ + +{ /* AArch64_ZIP2v2i32, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v2i64, ARM64_INS_ZIP2: zip2.2d $rd, $rn, $rm */ + +{ /* AArch64_ZIP2v2i64, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v4i16, ARM64_INS_ZIP2: zip2.4h $rd, $rn, $rm */ + +{ /* AArch64_ZIP2v4i16, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v4i32, ARM64_INS_ZIP2: zip2.4s $rd, $rn, $rm */ + +{ /* AArch64_ZIP2v4i32, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v8i16, ARM64_INS_ZIP2: zip2.8h $rd, $rn, $rm */ + +{ /* AArch64_ZIP2v8i16, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, -{ /* AArch64_ZIP2v8i8, ARM64_INS_ZIP2: zip2.8b $rd, $rn, $rm */ + +{ /* AArch64_ZIP2v8i8, AArch64_INS_ZIP2: zip2 */ 0, { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -} +}, + +{ /* AArch64_anonymous_1349, AArch64_INS_PFIRST: pfirst */ + 0, + { 0 } +}, diff --git a/arch/AArch64/ARMMappingInsnOp.inc b/arch/AArch64/ARMMappingInsnOp.inc deleted file mode 100644 index dee436f29..000000000 --- a/arch/AArch64/ARMMappingInsnOp.inc +++ /dev/null @@ -1,6657 +0,0 @@ -// This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) -// By Nguyen Anh Quynh - -{ /* ARM_ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ADCrr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ADCrsi, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ADCrsr, ARM_INS_ADC: adc${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ADDri, ARM_INS_ADD: add${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ADDrsi, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ADDrsr, ARM_INS_ADD: add${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ADR, ARM_INS_ADR: adr${p} $rd, $label */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_AESD, ARM_INS_AESD: aesd.8 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_AESE, ARM_INS_AESE: aese.8 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_AESIMC, ARM_INS_AESIMC: aesimc.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_AESMC, ARM_INS_AESMC: aesmc.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ANDrr, ARM_INS_AND: and${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ANDrsi, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ANDrsr, ARM_INS_AND: and${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_BICrr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_BICrsi, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_BICrsr, ARM_INS_BIC: bic${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_BKPT, ARM_INS_BKPT: bkpt $val */ - { 0 } -}, -{ /* ARM_BL, ARM_INS_BL: bl $func */ - { 0 } -}, -{ /* ARM_BLX, ARM_INS_BLX: blx $func */ - { CS_AC_READ, 0 } -}, -{ /* ARM_BLX_pred, ARM_INS_BLX: blx${p} $func */ - { CS_AC_READ, 0 } -}, -{ /* ARM_BLXi, ARM_INS_BLX: blx $target */ - { 0 } -}, -{ /* ARM_BL_pred, ARM_INS_BL: bl${p} $func */ - { 0 } -}, -{ /* ARM_BX, ARM_INS_BX: bx $dst */ - { CS_AC_READ, 0 } -}, -{ /* ARM_BXJ, ARM_INS_BXJ: bxj${p} $func */ - { CS_AC_READ, 0 } -}, -{ /* ARM_BX_RET, ARM_INS_BX: bx${p} lr */ - { 0 } -}, -{ /* ARM_BX_pred, ARM_INS_BX: bx${p} $dst */ - { CS_AC_READ, 0 } -}, -{ /* ARM_Bcc, ARM_INS_B: b${p} $target */ - { 0 } -}, -{ /* ARM_CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_CDP2, ARM_INS_CDP2: cdp2 $cop, $opc1, $crd, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_CLREX, ARM_INS_CLREX: clrex */ - { 0 } -}, -{ /* ARM_CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_CMNri, ARM_INS_CMN: cmn${p} $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_CMNzrr, ARM_INS_CMN: cmn${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CMNzrsi, ARM_INS_CMN: cmn${p} $rn, $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_CMNzrsr, ARM_INS_CMN: cmn${p} $rn, $shift */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CMPri, ARM_INS_CMP: cmp${p} $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_CMPrr, ARM_INS_CMP: cmp${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CMPrsi, ARM_INS_CMP: cmp${p} $rn, $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_CMPrsr, ARM_INS_CMP: cmp${p} $rn, $shift */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CPS1p, ARM_INS_CPS: cps $mode */ - { 0 } -}, -{ /* ARM_CPS2p, ARM_INS_CPS: cps$imod $iflags */ - { 0 } -}, -{ /* ARM_CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ - { 0 } -}, -{ /* ARM_CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_DBG, ARM_INS_DBG: dbg${p} $opt */ - { 0 } -}, -{ /* ARM_DMB, ARM_INS_DMB: dmb $opt */ - { 0 } -}, -{ /* ARM_DSB, ARM_INS_DSB: dsb $opt */ - { 0 } -}, -{ /* ARM_EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_EORrr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_EORrsi, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_EORrsr, ARM_INS_EOR: eor${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ERET, ARM_INS_ERET: eret${p} */ - { 0 } -}, -{ /* ARM_FCONSTD, ARM_INS_VMOV: vmov${p}.f64 $dd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_FCONSTS, ARM_INS_VMOV: vmov${p}.f32 $sd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_FLDMXDB_UPD, ARM_INS_FLDMDBX: fldmdbx${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_FLDMXIA, ARM_INS_FLDMIAX: fldmiax${p} $rn, $regs */ - { CS_AC_READ, 0 } -}, -{ /* ARM_FLDMXIA_UPD, ARM_INS_FLDMIAX: fldmiax${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_FMSTAT, ARM_INS_VMRS: vmrs${p} apsr_nzcv, fpscr */ - { 0 } -}, -{ /* ARM_FSTMXDB_UPD, ARM_INS_FSTMDBX: fstmdbx${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_FSTMXIA, ARM_INS_FSTMIAX: fstmiax${p} $rn, $regs */ - { CS_AC_READ, 0 } -}, -{ /* ARM_FSTMXIA_UPD, ARM_INS_FSTMIAX: fstmiax${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_HINT, ARM_INS_HINT: hint${p} $imm */ - { 0 } -}, -{ /* ARM_HLT, ARM_INS_HLT: hlt $val */ - { 0 } -}, -{ /* ARM_HVC, ARM_INS_HVC: hvc $imm */ - { 0 } -}, -{ /* ARM_ISB, ARM_INS_ISB: isb $opt */ - { 0 } -}, -{ /* ARM_LDA, ARM_INS_LDA: lda${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2L_OPTION, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2L_POST, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2L_PRE, ARM_INS_LDC2L: ldc2l $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2_OFFSET, ARM_INS_LDC2: ldc2 $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2_OPTION, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2_POST, ARM_INS_LDC2: ldc2 $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC2_PRE, ARM_INS_LDC2: ldc2 $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRBT_POST_IMM, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRBT_POST_REG, ARM_INS_LDRBT: ldrbt${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRB_POST_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRB_POST_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRB_PRE_IMM, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRB_PRE_REG, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRBi12, ARM_INS_LDRB: ldrb${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRBrs, ARM_INS_LDRB: ldrb${p} $rt, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRD, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr, $offset */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRH, ARM_INS_LDRH: ldrh${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRHTi, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRHTr, ARM_INS_LDRHT: ldrht${p} $rt, $addr, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRSBTi, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRSBTr, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRSHTi, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRSHTr, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_LDRT_POST_IMM, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRT_POST_REG, ARM_INS_LDRT: ldrt${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDR_POST_IMM, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDR_POST_REG, ARM_INS_LDR: ldr${p} $rt, $addr, $offset */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDR_PRE_IMM, ARM_INS_LDR: ldr${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDR_PRE_REG, ARM_INS_LDR: ldr${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRcp, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRi12, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_LDRrs, ARM_INS_LDR: ldr${p} $rt, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_MCR2, ARM_INS_MCR2: mcr2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MCRR2, ARM_INS_MCRR2: mcrr2 $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MLA, ARM_INS_MLA: mla${s}${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MOVPCLR, ARM_INS_MOV: mov${p} pc, lr */ - { 0 } -}, -{ /* ARM_MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_MOVi, ARM_INS_MOV: mov${s}${p} $rd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MOVr, ARM_INS_MOV: mov${s}${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_MOVr_TC, ARM_INS_MOV: mov${s}${p} $rd, $rm */ - { 0 } -}, -{ /* ARM_MOVsi, ARM_INS_MOV: mov${s}${p} $rd, $src */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MOVsr, ARM_INS_MOV: mov${s}${p} $rd, $src */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_MRC2, ARM_INS_MRC2: mrc2 $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MRRC2, ARM_INS_MRRC2: mrrc2 $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MRS, ARM_INS_MRS: mrs${p} $rd, apsr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MRSsys, ARM_INS_MRS: mrs${p} $rd, spsr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MSR, ARM_INS_MSR: msr${p} $mask, $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_MSRi, ARM_INS_MSR: msr${p} $mask, $imm */ - { 0 } -}, -{ /* ARM_MUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MVNr, ARM_INS_MVN: mvn${s}${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_MVNsi, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_MVNsr, ARM_INS_MVN: mvn${s}${p} $rd, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ORRrr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_ORRrsi, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_ORRrsr, ARM_INS_ORR: orr${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_PLDWi12, ARM_INS_PLDW: pldw $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_PLDWrs, ARM_INS_PLDW: pldw $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_PLDi12, ARM_INS_PLD: pld $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_PLDrs, ARM_INS_PLD: pld $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_PLIi12, ARM_INS_PLI: pli $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_PLIrs, ARM_INS_PLI: pli $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_REV, ARM_INS_REV: rev${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_REV16, ARM_INS_REV16: rev16${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_REVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_RFEDA, ARM_INS_RFEDA: rfeda $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEDA_UPD, ARM_INS_RFEDA: rfeda $rn! */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEDB, ARM_INS_RFEDB: rfedb $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEDB_UPD, ARM_INS_RFEDB: rfedb $rn! */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEIA, ARM_INS_RFEIA: rfeia $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEIA_UPD, ARM_INS_RFEIA: rfeia $rn! */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEIB, ARM_INS_RFEIB: rfeib $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RFEIB_UPD, ARM_INS_RFEIB: rfeib $rn! */ - { CS_AC_READ, 0 } -}, -{ /* ARM_RSBri, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_RSBrsi, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_RSBrsr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_RSCri, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_RSCrr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_RSCrsi, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_RSCrsr, ARM_INS_RSC: rsc${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SBCrr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SBCrsi, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SBCrsr, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $width */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SETEND, ARM_INS_SETEND: setend $end */ - { 0 } -}, -{ /* ARM_SHA1C, ARM_INS_SHA1C: sha1c.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHA1H, ARM_INS_SHA1H: sha1h.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SHA1M, ARM_INS_SHA1M: sha1m.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHA1P, ARM_INS_SHA1P: sha1p.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHA1SU0, ARM_INS_SHA1SU0: sha1su0.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHA1SU1, ARM_INS_SHA1SU1: sha1su1.32 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SHA256H, ARM_INS_SHA256H: sha256h.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHA256H2, ARM_INS_SHA256H2: sha256h2.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHA256SU0, ARM_INS_SHA256SU0: sha256su0.32 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SHA256SU1, ARM_INS_SHA256SU1: sha256su1.32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMC, ARM_INS_SMC: smc${p} $opt */ - { 0 } -}, -{ /* ARM_SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLAL, ARM_INS_SMLAL: smlal${s}${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLALD, ARM_INS_SMLALD: smlald${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLSLD, ARM_INS_SMLSLD: smlsld${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULL, ARM_INS_SMULL: smull${s}${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SRSDA, ARM_INS_SRSDA: srsda sp, $mode */ - { 0 } -}, -{ /* ARM_SRSDA_UPD, ARM_INS_SRSDA: srsda sp!, $mode */ - { 0 } -}, -{ /* ARM_SRSDB, ARM_INS_SRSDB: srsdb sp, $mode */ - { 0 } -}, -{ /* ARM_SRSDB_UPD, ARM_INS_SRSDB: srsdb sp!, $mode */ - { 0 } -}, -{ /* ARM_SRSIA, ARM_INS_SRSIA: srsia sp, $mode */ - { 0 } -}, -{ /* ARM_SRSIA_UPD, ARM_INS_SRSIA: srsia sp!, $mode */ - { 0 } -}, -{ /* ARM_SRSIB, ARM_INS_SRSIB: srsib sp, $mode */ - { 0 } -}, -{ /* ARM_SRSIB_UPD, ARM_INS_SRSIB: srsib sp!, $mode */ - { 0 } -}, -{ /* ARM_SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2L_OFFSET, ARM_INS_STC2L: stc2l $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2L_OPTION, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2L_POST, ARM_INS_STC2L: stc2l $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2L_PRE, ARM_INS_STC2L: stc2l $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2_OFFSET, ARM_INS_STC2: stc2 $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2_OPTION, ARM_INS_STC2: stc2 $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2_POST, ARM_INS_STC2: stc2 $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC2_PRE, ARM_INS_STC2: stc2 $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STL, ARM_INS_STL: stl${p} $rt, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STMDA, ARM_INS_STMDA: stmda${p} $rn, $regs */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_STMIA, ARM_INS_STM: stm${p} $rn, $regs */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_STMIB, ARM_INS_STMIB: stmib${p} $rn, $regs */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_STRBT_POST_IMM, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRBT_POST_REG, ARM_INS_STRBT: strbt${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRB_POST_IMM, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRB_POST_REG, ARM_INS_STRB: strb${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRB_PRE_IMM, ARM_INS_STRB: strb${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRB_PRE_REG, ARM_INS_STRB: strb${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRBi12, ARM_INS_STRB: strb${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRBrs, ARM_INS_STRB: strb${p} $rt, $shift */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRD, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRH, ARM_INS_STRH: strh${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRHTi, ARM_INS_STRHT: strht${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRHTr, ARM_INS_STRHT: strht${p} $rt, $addr, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRH_POST, ARM_INS_STRH: strh${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRT_POST_IMM, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRT_POST_REG, ARM_INS_STRT: strt${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STR_POST_IMM, ARM_INS_STR: str${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STR_POST_REG, ARM_INS_STR: str${p} $rt, $addr, $offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STR_PRE_IMM, ARM_INS_STR: str${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STR_PRE_REG, ARM_INS_STR: str${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRi12, ARM_INS_STR: str${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_STRrs, ARM_INS_STR: str${p} $rt, $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_SUBri, ARM_INS_SUB: sub${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SUBrsi, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SUBrsr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $shift */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SVC, ARM_INS_SVC: svc${p} $svc */ - { 0 } -}, -{ /* ARM_SWP, ARM_INS_SWP: swp${p} $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SWPB, ARM_INS_SWPB: swpb${p} $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_SXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_SXTH, ARM_INS_SXTH: sxth${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_TEQri, ARM_INS_TEQ: teq${p} $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_TEQrr, ARM_INS_TEQ: teq${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_TEQrsi, ARM_INS_TEQ: teq${p} $rn, $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_TEQrsr, ARM_INS_TEQ: teq${p} $rn, $shift */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_TRAP, ARM_INS_TRAP: trap */ - { 0 } -}, -{ /* ARM_TRAPNaCl, ARM_INS_TRAP: trap */ - { 0 } -}, -{ /* ARM_TSTri, ARM_INS_TST: tst${p} $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_TSTrr, ARM_INS_TST: tst${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_TSTrsi, ARM_INS_TST: tst${p} $rn, $shift */ - { CS_AC_READ, 0 } -}, -{ /* ARM_TSTrsr, ARM_INS_TST: tst${p} $rn, $shift */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $width */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_UDF, ARM_INS_UDF: udf $imm16 */ - { 0 } -}, -{ /* ARM_UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UMLAL, ARM_INS_UMLAL: umlal${s}${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UMULL, ARM_INS_UMULL: umull${s}${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_UXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_UXTH, ARM_INS_UXTH: uxth${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VABALsv2i64, ARM_INS_VABAL: vabal${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABALsv4i32, ARM_INS_VABAL: vabal${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABALsv8i16, ARM_INS_VABAL: vabal${p}.s8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABALuv2i64, ARM_INS_VABAL: vabal${p}.u32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABALuv4i32, ARM_INS_VABAL: vabal${p}.u16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABALuv8i16, ARM_INS_VABAL: vabal${p}.u8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAsv16i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAsv2i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAsv4i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAsv4i32, ARM_INS_VABA: vaba${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAsv8i16, ARM_INS_VABA: vaba${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAsv8i8, ARM_INS_VABA: vaba${p}.s8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAuv16i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAuv2i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAuv4i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAuv4i32, ARM_INS_VABA: vaba${p}.u32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAuv8i16, ARM_INS_VABA: vaba${p}.u16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABAuv8i8, ARM_INS_VABA: vaba${p}.u8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDLsv2i64, ARM_INS_VABDL: vabdl${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDLsv4i32, ARM_INS_VABDL: vabdl${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDLsv8i16, ARM_INS_VABDL: vabdl${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDLuv2i64, ARM_INS_VABDL: vabdl${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDLuv4i32, ARM_INS_VABDL: vabdl${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDLuv8i16, ARM_INS_VABDL: vabdl${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDfd, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDfq, ARM_INS_VABD: vabd${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDsv16i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDsv2i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDsv4i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDsv4i32, ARM_INS_VABD: vabd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDsv8i16, ARM_INS_VABD: vabd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDsv8i8, ARM_INS_VABD: vabd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDuv16i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDuv2i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDuv4i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDuv4i32, ARM_INS_VABD: vabd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDuv8i16, ARM_INS_VABD: vabd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABDuv8i8, ARM_INS_VABD: vabd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VABSD, ARM_INS_VABS: vabs${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSS, ARM_INS_VABS: vabs${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSfd, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSfq, ARM_INS_VABS: vabs${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSv16i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSv2i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSv4i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSv4i32, ARM_INS_VABS: vabs${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSv8i16, ARM_INS_VABS: vabs${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VABSv8i8, ARM_INS_VABS: vabs${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VACGEd, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VACGEq, ARM_INS_VACGE: vacge${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VACGTd, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VACGTq, ARM_INS_VACGT: vacgt${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDD, ARM_INS_VADD: vadd${p}.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDHNv2i32, ARM_INS_VADDHN: vaddhn${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDHNv4i16, ARM_INS_VADDHN: vaddhn${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDHNv8i8, ARM_INS_VADDHN: vaddhn${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDLsv2i64, ARM_INS_VADDL: vaddl${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDLsv4i32, ARM_INS_VADDL: vaddl${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDLsv8i16, ARM_INS_VADDL: vaddl${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDLuv2i64, ARM_INS_VADDL: vaddl${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDLuv4i32, ARM_INS_VADDL: vaddl${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDLuv8i16, ARM_INS_VADDL: vaddl${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDS, ARM_INS_VADD: vadd${p}.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDWsv2i64, ARM_INS_VADDW: vaddw${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDWsv4i32, ARM_INS_VADDW: vaddw${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDWsv8i16, ARM_INS_VADDW: vaddw${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDWuv2i64, ARM_INS_VADDW: vaddw${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDWuv4i32, ARM_INS_VADDW: vaddw${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDWuv8i16, ARM_INS_VADDW: vaddw${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDfd, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDfq, ARM_INS_VADD: vadd${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv16i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv1i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv2i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv2i64, ARM_INS_VADD: vadd${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv4i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv4i32, ARM_INS_VADD: vadd${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv8i16, ARM_INS_VADD: vadd${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VADDv8i8, ARM_INS_VADD: vadd${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VANDd, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VANDq, ARM_INS_VAND: vand${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBICd, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBICiv2i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VBICiv4i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VBICiv4i32, ARM_INS_VBIC: vbic${p}.i32 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VBICiv8i16, ARM_INS_VBIC: vbic${p}.i16 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VBICq, ARM_INS_VBIC: vbic${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBIFd, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBIFq, ARM_INS_VBIF: vbif${p} $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBITd, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBITq, ARM_INS_VBIT: vbit${p} $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBSLd, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VBSLq, ARM_INS_VBSL: vbsl${p} $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQfd, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQfq, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv16i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv2f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv2i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv4f32, ARM_INS_VCEQ: vceq${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv4i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv4i32, ARM_INS_VCEQ: vceq${p}.i32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv8i16, ARM_INS_VCEQ: vceq${p}.i16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCEQzv8i8, ARM_INS_VCEQ: vceq${p}.i8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEfd, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEfq, ARM_INS_VCGE: vcge${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEsv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEsv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEsv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEsv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEsv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEsv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEuv16i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEuv2i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEuv4i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEuv4i32, ARM_INS_VCGE: vcge${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEuv8i16, ARM_INS_VCGE: vcge${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEuv8i8, ARM_INS_VCGE: vcge${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv16i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv2f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv2i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv4f32, ARM_INS_VCGE: vcge${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv4i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv4i32, ARM_INS_VCGE: vcge${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv8i16, ARM_INS_VCGE: vcge${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGEzv8i8, ARM_INS_VCGE: vcge${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTfd, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTfq, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTsv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTsv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTsv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTsv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTsv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTsv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTuv16i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTuv2i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTuv4i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTuv4i32, ARM_INS_VCGT: vcgt${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTuv8i16, ARM_INS_VCGT: vcgt${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTuv8i8, ARM_INS_VCGT: vcgt${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv16i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv2f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv2i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv4f32, ARM_INS_VCGT: vcgt${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv4i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv4i32, ARM_INS_VCGT: vcgt${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv8i16, ARM_INS_VCGT: vcgt${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCGTzv8i8, ARM_INS_VCGT: vcgt${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv16i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv2f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv2i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv4f32, ARM_INS_VCLE: vcle${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv4i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv4i32, ARM_INS_VCLE: vcle${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv8i16, ARM_INS_VCLE: vcle${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLEzv8i8, ARM_INS_VCLE: vcle${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLSv16i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLSv2i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLSv4i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLSv4i32, ARM_INS_VCLS: vcls${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLSv8i16, ARM_INS_VCLS: vcls${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLSv8i8, ARM_INS_VCLS: vcls${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv16i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv2f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv2i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv4f32, ARM_INS_VCLT: vclt${p}.f32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv4i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv4i32, ARM_INS_VCLT: vclt${p}.s32 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv8i16, ARM_INS_VCLT: vclt${p}.s16 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLTzv8i8, ARM_INS_VCLT: vclt${p}.s8 $vd, $vm, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLZv16i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLZv2i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLZv4i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLZv4i32, ARM_INS_VCLZ: vclz${p}.i32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLZv8i16, ARM_INS_VCLZ: vclz${p}.i16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCLZv8i8, ARM_INS_VCLZ: vclz${p}.i8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCMPD, ARM_INS_VCMP: vcmp${p}.f64 $dd, $dm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCMPED, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, $dm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCMPES, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, $sm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCMPEZD, ARM_INS_VCMPE: vcmpe${p}.f64 $dd, #0 */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VCMPEZS, ARM_INS_VCMPE: vcmpe${p}.f32 $sd, #0 */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VCMPS, ARM_INS_VCMP: vcmp${p}.f32 $sd, $sm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VCMPZD, ARM_INS_VCMP: vcmp${p}.f64 $dd, #0 */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VCMPZS, ARM_INS_VCMP: vcmp${p}.f32 $sd, #0 */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VCNTd, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCNTq, ARM_INS_VCNT: vcnt${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTANSD, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTANSQ, ARM_INS_VCVTA: vcvta.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTANUD, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTANUQ, ARM_INS_VCVTA: vcvta.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTASD, ARM_INS_VCVTA: vcvta.s32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTASS, ARM_INS_VCVTA: vcvta.s32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTAUD, ARM_INS_VCVTA: vcvta.u32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTAUS, ARM_INS_VCVTA: vcvta.u32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTBDH, ARM_INS_VCVTB: vcvtb${p}.f16.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTBHD, ARM_INS_VCVTB: vcvtb${p}.f64.f16 $dd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTBHS, ARM_INS_VCVTB: vcvtb${p}.f32.f16 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTBSH, ARM_INS_VCVTB: vcvtb${p}.f16.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTDS, ARM_INS_VCVT: vcvt${p}.f64.f32 $dd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMNSD, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMNSQ, ARM_INS_VCVTM: vcvtm.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMNUD, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMNUQ, ARM_INS_VCVTM: vcvtm.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMSD, ARM_INS_VCVTM: vcvtm.s32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMSS, ARM_INS_VCVTM: vcvtm.s32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMUD, ARM_INS_VCVTM: vcvtm.u32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTMUS, ARM_INS_VCVTM: vcvtm.u32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNNSD, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNNSQ, ARM_INS_VCVTN: vcvtn.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNNUD, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNNUQ, ARM_INS_VCVTN: vcvtn.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNSD, ARM_INS_VCVTN: vcvtn.s32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNSS, ARM_INS_VCVTN: vcvtn.s32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNUD, ARM_INS_VCVTN: vcvtn.u32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTNUS, ARM_INS_VCVTN: vcvtn.u32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPNSD, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPNSQ, ARM_INS_VCVTP: vcvtp.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPNUD, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPNUQ, ARM_INS_VCVTP: vcvtp.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPSD, ARM_INS_VCVTP: vcvtp.s32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPSS, ARM_INS_VCVTP: vcvtp.s32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPUD, ARM_INS_VCVTP: vcvtp.u32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTPUS, ARM_INS_VCVTP: vcvtp.u32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTSD, ARM_INS_VCVT: vcvt${p}.f32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTTDH, ARM_INS_VCVTT: vcvtt${p}.f16.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTTHD, ARM_INS_VCVTT: vcvtt${p}.f64.f16 $dd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTTHS, ARM_INS_VCVTT: vcvtt${p}.f32.f16 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTTSH, ARM_INS_VCVTT: vcvtt${p}.f16.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2h, ARM_INS_VCVT: vcvt${p}.f16.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2sd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2sq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2ud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2uq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2xsd, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2xsq, ARM_INS_VCVT: vcvt${p}.s32.f32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2xud, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTf2xuq, ARM_INS_VCVT: vcvt${p}.u32.f32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTh2f, ARM_INS_VCVT: vcvt${p}.f32.f16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTxs2fd, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTxs2fq, ARM_INS_VCVT: vcvt${p}.f32.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTxu2fd, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VCVTxu2fq, ARM_INS_VCVT: vcvt${p}.f32.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDIVD, ARM_INS_VDIV: vdiv${p}.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VDIVS, ARM_INS_VDIV: vdiv${p}.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VDUP16d, ARM_INS_VDUP: vdup${p}.16 $v, $r */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUP16q, ARM_INS_VDUP: vdup${p}.16 $v, $r */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUP32d, ARM_INS_VDUP: vdup${p}.32 $v, $r */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUP32q, ARM_INS_VDUP: vdup${p}.32 $v, $r */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUP8d, ARM_INS_VDUP: vdup${p}.8 $v, $r */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUP8q, ARM_INS_VDUP: vdup${p}.8 $v, $r */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUPLN16d, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUPLN16q, ARM_INS_VDUP: vdup${p}.16 $vd, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUPLN32d, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUPLN32q, ARM_INS_VDUP: vdup${p}.32 $vd, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUPLN8d, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VDUPLN8q, ARM_INS_VDUP: vdup${p}.8 $vd, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VEORd, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEORq, ARM_INS_VEOR: veor${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTd16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTd32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTd8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTq16, ARM_INS_VEXT: vext${p}.16 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTq32, ARM_INS_VEXT: vext${p}.32 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTq64, ARM_INS_VEXT: vext${p}.64 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VEXTq8, ARM_INS_VEXT: vext${p}.8 $vd, $vn, $vm, $index */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMAD, ARM_INS_VFMA: vfma${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMAS, ARM_INS_VFMA: vfma${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMAfd, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMAfq, ARM_INS_VFMA: vfma${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMSD, ARM_INS_VFMS: vfms${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMSS, ARM_INS_VFMS: vfms${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMSfd, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFMSfq, ARM_INS_VFMS: vfms${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFNMAD, ARM_INS_VFNMA: vfnma${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFNMAS, ARM_INS_VFNMA: vfnma${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFNMSD, ARM_INS_VFNMS: vfnms${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VFNMSS, ARM_INS_VFNMS: vfnms${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VGETLNi32, ARM_INS_VMOV: vmov${p}.32 $r, $v$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VGETLNs16, ARM_INS_VMOV: vmov${p}.s16 $r, $v$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VGETLNs8, ARM_INS_VMOV: vmov${p}.s8 $r, $v$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VGETLNu16, ARM_INS_VMOV: vmov${p}.u16 $r, $v$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VGETLNu8, ARM_INS_VMOV: vmov${p}.u8 $r, $v$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDsv16i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDsv2i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDsv4i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDsv4i32, ARM_INS_VHADD: vhadd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDsv8i16, ARM_INS_VHADD: vhadd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDsv8i8, ARM_INS_VHADD: vhadd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDuv16i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDuv2i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDuv4i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDuv4i32, ARM_INS_VHADD: vhadd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDuv8i16, ARM_INS_VHADD: vhadd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHADDuv8i8, ARM_INS_VHADD: vhadd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBsv16i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBsv2i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBsv4i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBsv4i32, ARM_INS_VHSUB: vhsub${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBsv8i16, ARM_INS_VHSUB: vhsub${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBsv8i8, ARM_INS_VHSUB: vhsub${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBuv16i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBuv2i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBuv4i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBuv4i32, ARM_INS_VHSUB: vhsub${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBuv8i16, ARM_INS_VHSUB: vhsub${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VHSUBuv8i8, ARM_INS_VHSUB: vhsub${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPd8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1DUPq8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1LNd16, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1LNd16_UPD, ARM_INS_VLD1: vld1${p}.16 \{$vd[$lane]\}, $rn$rm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD1LNd32, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD1LNd32_UPD, ARM_INS_VLD1: vld1${p}.32 \{$vd[$lane]\}, $rn$rm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD1LNd8, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1LNd8_UPD, ARM_INS_VLD1: vld1${p}.8 \{$vd[$lane]\}, $rn$rm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD1d16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16Q, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16Qwb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16Qwb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16T, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16Twb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16Twb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32Q, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32Qwb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32Qwb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32T, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32Twb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32Twb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64Q, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64Qwb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64Qwb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64T, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64Twb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64Twb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8Q, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8Qwb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8Qwb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8T, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8Twb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8Twb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1d8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q16, ARM_INS_VLD1: vld1${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q16wb_fixed, ARM_INS_VLD1: vld1${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q16wb_register, ARM_INS_VLD1: vld1${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q32, ARM_INS_VLD1: vld1${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q32wb_fixed, ARM_INS_VLD1: vld1${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q32wb_register, ARM_INS_VLD1: vld1${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q64, ARM_INS_VLD1: vld1${p}.64 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q64wb_fixed, ARM_INS_VLD1: vld1${p}.64 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q64wb_register, ARM_INS_VLD1: vld1${p}.64 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q8, ARM_INS_VLD1: vld1${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q8wb_fixed, ARM_INS_VLD1: vld1${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD1q8wb_register, ARM_INS_VLD1: vld1${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd16x2, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd16x2wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd16x2wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd32x2, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd32x2wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd32x2wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd8x2, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd8x2wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2DUPd8x2wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2LNd16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2LNd16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD2LNd32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2LNd32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD2LNd8, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2LNd8_UPD, ARM_INS_VLD2: vld2${p}.8 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD2LNq16, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2LNq16_UPD, ARM_INS_VLD2: vld2${p}.16 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD2LNq32, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2LNq32_UPD, ARM_INS_VLD2: vld2${p}.32 \{$vd[$lane], $dst2[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD2b16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2b8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2d8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q16, ARM_INS_VLD2: vld2${p}.16 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q16wb_fixed, ARM_INS_VLD2: vld2${p}.16 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q16wb_register, ARM_INS_VLD2: vld2${p}.16 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q32, ARM_INS_VLD2: vld2${p}.32 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q32wb_fixed, ARM_INS_VLD2: vld2${p}.32 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q32wb_register, ARM_INS_VLD2: vld2${p}.32 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q8, ARM_INS_VLD2: vld2${p}.8 $vd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q8wb_fixed, ARM_INS_VLD2: vld2${p}.8 $vd, $rn! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD2q8wb_register, ARM_INS_VLD2: vld2${p}.8 $vd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPq8, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3DUPq8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[], $dst2[], $dst3[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3LNd16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3LNd16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3LNd32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3LNd32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3LNd8, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3LNd8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3LNq16, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3LNq16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3LNq32, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3LNq32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3d16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3d16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3d32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3d32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3d8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3d8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3q16, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3q16_UPD, ARM_INS_VLD3: vld3${p}.16 \{$vd, $dst2, $dst3\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3q32, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3q32_UPD, ARM_INS_VLD3: vld3${p}.32 \{$vd, $dst2, $dst3\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD3q8, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD3q8_UPD, ARM_INS_VLD3: vld3${p}.8 \{$vd, $dst2, $dst3\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4DUPd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPq8, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4DUPq8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[], $dst2[], $dst3[], $dst4[]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4LNd16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4LNd16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4LNd32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4LNd32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4LNd8, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4LNd8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4LNq16, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4LNq16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4LNq32, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4LNq32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4d16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4d16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4d32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4d32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4d8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4d8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4q16, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4q16_UPD, ARM_INS_VLD4: vld4${p}.16 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4q32, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4q32_UPD, ARM_INS_VLD4: vld4${p}.32 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLD4q8, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VLD4q8_UPD, ARM_INS_VLD4: vld4${p}.8 \{$vd, $dst2, $dst3, $dst4\}, $rn$rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VLDMDDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VLDMDIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VLDMDIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VLDMSDB_UPD, ARM_INS_VLDMDB: vldmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VLDMSIA, ARM_INS_VLDMIA: vldmia${p} $rn, $regs */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VLDMSIA_UPD, ARM_INS_VLDMIA: vldmia${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VLDRD, ARM_INS_VLDR: vldr${p} $dd, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VLDRS, ARM_INS_VLDR: vldr${p} $sd, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMAXNMD, ARM_INS_VMAXNM: vmaxnm.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXNMND, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXNMNQ, ARM_INS_VMAXNM: vmaxnm.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXNMS, ARM_INS_VMAXNM: vmaxnm.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXfd, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXfq, ARM_INS_VMAX: vmax${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXsv16i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXsv2i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXsv4i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXsv4i32, ARM_INS_VMAX: vmax${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXsv8i16, ARM_INS_VMAX: vmax${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXsv8i8, ARM_INS_VMAX: vmax${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXuv16i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXuv2i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXuv4i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXuv4i32, ARM_INS_VMAX: vmax${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXuv8i16, ARM_INS_VMAX: vmax${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMAXuv8i8, ARM_INS_VMAX: vmax${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINNMD, ARM_INS_VMINNM: vminnm.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINNMND, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINNMNQ, ARM_INS_VMINNM: vminnm.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINNMS, ARM_INS_VMINNM: vminnm.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINfd, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINfq, ARM_INS_VMIN: vmin${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINsv16i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINsv2i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINsv4i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINsv4i32, ARM_INS_VMIN: vmin${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINsv8i16, ARM_INS_VMIN: vmin${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINsv8i8, ARM_INS_VMIN: vmin${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINuv16i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINuv2i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINuv4i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINuv4i32, ARM_INS_VMIN: vmin${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINuv8i16, ARM_INS_VMIN: vmin${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMINuv8i8, ARM_INS_VMIN: vmin${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAD, ARM_INS_VMLA: vmla${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALslsv2i32, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALslsv4i16, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALsluv2i32, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALsluv4i16, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALsv2i64, ARM_INS_VMLAL: vmlal${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALsv4i32, ARM_INS_VMLAL: vmlal${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALsv8i16, ARM_INS_VMLAL: vmlal${p}.s8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALuv2i64, ARM_INS_VMLAL: vmlal${p}.u32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALuv4i32, ARM_INS_VMLAL: vmlal${p}.u16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLALuv8i16, ARM_INS_VMLAL: vmlal${p}.u8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAS, ARM_INS_VMLA: vmla${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAslfd, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAslfq, ARM_INS_VMLA: vmla${p}.f32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAslv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAslv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAslv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAslv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAv16i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAv2i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAv4i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAv4i32, ARM_INS_VMLA: vmla${p}.i32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAv8i16, ARM_INS_VMLA: vmla${p}.i16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLAv8i8, ARM_INS_VMLA: vmla${p}.i8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSD, ARM_INS_VMLS: vmls${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLslsv2i32, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLslsv4i16, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLsluv2i32, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLsluv4i16, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLsv2i64, ARM_INS_VMLSL: vmlsl${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLsv4i32, ARM_INS_VMLSL: vmlsl${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLsv8i16, ARM_INS_VMLSL: vmlsl${p}.s8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLuv2i64, ARM_INS_VMLSL: vmlsl${p}.u32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLuv4i32, ARM_INS_VMLSL: vmlsl${p}.u16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSLuv8i16, ARM_INS_VMLSL: vmlsl${p}.u8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSS, ARM_INS_VMLS: vmls${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSslfd, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSslfq, ARM_INS_VMLS: vmls${p}.f32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSslv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSslv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSslv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSslv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSv16i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSv2i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSv4i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSv4i32, ARM_INS_VMLS: vmls${p}.i32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSv8i16, ARM_INS_VMLS: vmls${p}.i16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMLSv8i8, ARM_INS_VMLS: vmls${p}.i8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVD, ARM_INS_VMOV: vmov${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVDRR, ARM_INS_VMOV: vmov${p} $dm, $rt, $rt2 */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVLsv2i64, ARM_INS_VMOVL: vmovl${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVLsv4i32, ARM_INS_VMOVL: vmovl${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVLsv8i16, ARM_INS_VMOVL: vmovl${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVLuv2i64, ARM_INS_VMOVL: vmovl${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVLuv4i32, ARM_INS_VMOVL: vmovl${p}.u16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVLuv8i16, ARM_INS_VMOVL: vmovl${p}.u8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVNv2i32, ARM_INS_VMOVN: vmovn${p}.i64 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVNv4i16, ARM_INS_VMOVN: vmovn${p}.i32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVNv8i8, ARM_INS_VMOVN: vmovn${p}.i16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVRRD, ARM_INS_VMOV: vmov${p} $rt, $rt2, $dm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVRRS, ARM_INS_VMOV: vmov${p} $rt, $rt2, $src1, $src2 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVRS, ARM_INS_VMOV: vmov${p} $rt, $sn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVS, ARM_INS_VMOV: vmov${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVSR, ARM_INS_VMOV: vmov${p} $sn, $rt */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVSRR, ARM_INS_VMOV: vmov${p} $dst1, $dst2, $src1, $src2 */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMOVv16i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv1i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv2f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv2i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv2i64, ARM_INS_VMOV: vmov${p}.i64 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv4f32, ARM_INS_VMOV: vmov${p}.f32 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv4i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv4i32, ARM_INS_VMOV: vmov${p}.i32 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv8i16, ARM_INS_VMOV: vmov${p}.i16 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMOVv8i8, ARM_INS_VMOV: vmov${p}.i8 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS, ARM_INS_VMRS: vmrs${p} $rt, fpscr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_FPEXC, ARM_INS_VMRS: vmrs${p} $rt, fpexc */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_FPINST, ARM_INS_VMRS: vmrs${p} $rt, fpinst */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_FPINST2, ARM_INS_VMRS: vmrs${p} $rt, fpinst2 */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_FPSID, ARM_INS_VMRS: vmrs${p} $rt, fpsid */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_MVFR0, ARM_INS_VMRS: vmrs${p} $rt, mvfr0 */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_MVFR1, ARM_INS_VMRS: vmrs${p} $rt, mvfr1 */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMRS_MVFR2, ARM_INS_VMRS: vmrs${p} $rt, mvfr2 */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMSR, ARM_INS_VMSR: vmsr${p} fpscr, $src */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_VMSR_FPEXC, ARM_INS_VMSR: vmsr${p} fpexc, $src */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_VMSR_FPINST, ARM_INS_VMSR: vmsr${p} fpinst, $src */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_VMSR_FPINST2, ARM_INS_VMSR: vmsr${p} fpinst2, $src */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_VMSR_FPSID, ARM_INS_VMSR: vmsr${p} fpsid, $src */ - { CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULD, ARM_INS_VMUL: vmul${p}.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLp64, ARM_INS_VMULL: vmull.p64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLp8, ARM_INS_VMULL: vmull${p}.p8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLslsv2i32, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLslsv4i16, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLsluv2i32, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLsluv4i16, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLsv2i64, ARM_INS_VMULL: vmull${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLsv4i32, ARM_INS_VMULL: vmull${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLsv8i16, ARM_INS_VMULL: vmull${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLuv2i64, ARM_INS_VMULL: vmull${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLuv4i32, ARM_INS_VMULL: vmull${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULLuv8i16, ARM_INS_VMULL: vmull${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULS, ARM_INS_VMUL: vmul${p}.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULpd, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULpq, ARM_INS_VMUL: vmul${p}.p8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULslfd, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULslfq, ARM_INS_VMUL: vmul${p}.f32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULslv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULslv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULslv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULslv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMULv16i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULv2i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULv4i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULv4i32, ARM_INS_VMUL: vmul${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULv8i16, ARM_INS_VMUL: vmul${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMULv8i8, ARM_INS_VMUL: vmul${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VMVNd, ARM_INS_VMVN: vmvn${p} $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMVNq, ARM_INS_VMVN: vmvn${p} $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VMVNv2i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMVNv4i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMVNv4i32, ARM_INS_VMVN: vmvn${p}.i32 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VMVNv8i16, ARM_INS_VMVN: vmvn${p}.i16 $vd, $simm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_VNEGD, ARM_INS_VNEG: vneg${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGS, ARM_INS_VNEG: vneg${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGf32q, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGfd, ARM_INS_VNEG: vneg${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGs16d, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGs16q, ARM_INS_VNEG: vneg${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGs32d, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGs32q, ARM_INS_VNEG: vneg${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGs8d, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNEGs8q, ARM_INS_VNEG: vneg${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VNMLAD, ARM_INS_VNMLA: vnmla${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VNMLAS, ARM_INS_VNMLA: vnmla${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VNMLSD, ARM_INS_VNMLS: vnmls${p}.f64 $dd, $dn, $dm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VNMLSS, ARM_INS_VNMLS: vnmls${p}.f32 $sd, $sn, $sm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VNMULD, ARM_INS_VNMUL: vnmul${p}.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VNMULS, ARM_INS_VNMUL: vnmul${p}.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VORNd, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VORNq, ARM_INS_VORN: vorn${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VORRd, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VORRiv2i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VORRiv4i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VORRiv4i32, ARM_INS_VORR: vorr${p}.i32 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VORRiv8i16, ARM_INS_VORR: vorr${p}.i16 $vd, $simm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VORRq, ARM_INS_VORR: vorr${p} $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALsv16i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALsv2i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALsv4i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALsv4i32, ARM_INS_VPADAL: vpadal${p}.s32 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALsv8i16, ARM_INS_VPADAL: vpadal${p}.s16 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALsv8i8, ARM_INS_VPADAL: vpadal${p}.s8 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALuv16i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALuv2i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALuv4i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALuv4i32, ARM_INS_VPADAL: vpadal${p}.u32 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALuv8i16, ARM_INS_VPADAL: vpadal${p}.u16 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADALuv8i8, ARM_INS_VPADAL: vpadal${p}.u8 $vd, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLsv16i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLsv2i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLsv4i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLsv4i32, ARM_INS_VPADDL: vpaddl${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLsv8i16, ARM_INS_VPADDL: vpaddl${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLsv8i8, ARM_INS_VPADDL: vpaddl${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLuv16i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLuv2i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLuv4i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLuv4i32, ARM_INS_VPADDL: vpaddl${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLuv8i16, ARM_INS_VPADDL: vpaddl${p}.u16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDLuv8i8, ARM_INS_VPADDL: vpaddl${p}.u8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDf, ARM_INS_VPADD: vpadd${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDi16, ARM_INS_VPADD: vpadd${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDi32, ARM_INS_VPADD: vpadd${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPADDi8, ARM_INS_VPADD: vpadd${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXf, ARM_INS_VPMAX: vpmax${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXs16, ARM_INS_VPMAX: vpmax${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXs32, ARM_INS_VPMAX: vpmax${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXs8, ARM_INS_VPMAX: vpmax${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXu16, ARM_INS_VPMAX: vpmax${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXu32, ARM_INS_VPMAX: vpmax${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMAXu8, ARM_INS_VPMAX: vpmax${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINf, ARM_INS_VPMIN: vpmin${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINs16, ARM_INS_VPMIN: vpmin${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINs32, ARM_INS_VPMIN: vpmin${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINs8, ARM_INS_VPMIN: vpmin${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINu16, ARM_INS_VPMIN: vpmin${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINu32, ARM_INS_VPMIN: vpmin${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VPMINu8, ARM_INS_VPMIN: vpmin${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQABSv16i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQABSv2i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQABSv4i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQABSv4i32, ARM_INS_VQABS: vqabs${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQABSv8i16, ARM_INS_VQABS: vqabs${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQABSv8i8, ARM_INS_VQABS: vqabs${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv16i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv1i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv2i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv2i64, ARM_INS_VQADD: vqadd${p}.s64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv4i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv4i32, ARM_INS_VQADD: vqadd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv8i16, ARM_INS_VQADD: vqadd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDsv8i8, ARM_INS_VQADD: vqadd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv16i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv1i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv2i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv2i64, ARM_INS_VQADD: vqadd${p}.u64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv4i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv4i32, ARM_INS_VQADD: vqadd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv8i16, ARM_INS_VQADD: vqadd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQADDuv8i8, ARM_INS_VQADD: vqadd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLALslv2i32, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLALslv4i16, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLALv2i64, ARM_INS_VQDMLAL: vqdmlal${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLALv4i32, ARM_INS_VQDMLAL: vqdmlal${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLSLslv2i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLSLslv4i16, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLSLv2i64, ARM_INS_VQDMLSL: vqdmlsl${p}.s32 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMLSLv4i32, ARM_INS_VQDMLSL: vqdmlsl${p}.s16 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHslv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHslv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHslv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHslv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHv2i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHv4i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHv4i32, ARM_INS_VQDMULH: vqdmulh${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULHv8i16, ARM_INS_VQDMULH: vqdmulh${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULLslv2i32, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULLslv4i16, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULLv2i64, ARM_INS_VQDMULL: vqdmull${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQDMULLv4i32, ARM_INS_VQDMULL: vqdmull${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNsuv2i32, ARM_INS_VQMOVUN: vqmovun${p}.s64 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNsuv4i16, ARM_INS_VQMOVUN: vqmovun${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNsuv8i8, ARM_INS_VQMOVUN: vqmovun${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNsv2i32, ARM_INS_VQMOVN: vqmovn${p}.s64 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNsv4i16, ARM_INS_VQMOVN: vqmovn${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNsv8i8, ARM_INS_VQMOVN: vqmovn${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNuv2i32, ARM_INS_VQMOVN: vqmovn${p}.u64 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNuv4i16, ARM_INS_VQMOVN: vqmovn${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQMOVNuv8i8, ARM_INS_VQMOVN: vqmovn${p}.u16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQNEGv16i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQNEGv2i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQNEGv4i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQNEGv4i32, ARM_INS_VQNEG: vqneg${p}.s32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQNEGv8i16, ARM_INS_VQNEG: vqneg${p}.s16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQNEGv8i8, ARM_INS_VQNEG: vqneg${p}.s8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHslv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHslv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHslv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHslv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm$lane */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHv2i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHv4i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHv4i32, ARM_INS_VQRDMULH: vqrdmulh${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRDMULHv8i16, ARM_INS_VQRDMULH: vqrdmulh${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv16i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv1i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv2i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv2i64, ARM_INS_VQRSHL: vqrshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv4i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv4i32, ARM_INS_VQRSHL: vqrshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv8i16, ARM_INS_VQRSHL: vqrshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLsv8i8, ARM_INS_VQRSHL: vqrshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv16i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv1i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv2i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv2i64, ARM_INS_VQRSHL: vqrshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv4i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv4i32, ARM_INS_VQRSHL: vqrshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv8i16, ARM_INS_VQRSHL: vqrshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHLuv8i8, ARM_INS_VQRSHL: vqrshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRNsv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRNsv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRNsv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRNuv2i32, ARM_INS_VQRSHRN: vqrshrn${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRNuv4i16, ARM_INS_VQRSHRN: vqrshrn${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRNuv8i8, ARM_INS_VQRSHRN: vqrshrn${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRUNv2i32, ARM_INS_VQRSHRUN: vqrshrun${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRUNv4i16, ARM_INS_VQRSHRUN: vqrshrun${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQRSHRUNv8i8, ARM_INS_VQRSHRUN: vqrshrun${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsiv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv16i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv1i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv2i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv2i64, ARM_INS_VQSHLU: vqshlu${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv4i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv4i32, ARM_INS_VQSHLU: vqshlu${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv8i16, ARM_INS_VQSHLU: vqshlu${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsuv8i8, ARM_INS_VQSHLU: vqshlu${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv16i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv1i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv2i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv2i64, ARM_INS_VQSHL: vqshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv4i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv4i32, ARM_INS_VQSHL: vqshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv8i16, ARM_INS_VQSHL: vqshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLsv8i8, ARM_INS_VQSHL: vqshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuiv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv16i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv1i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv2i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv2i64, ARM_INS_VQSHL: vqshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv4i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv4i32, ARM_INS_VQSHL: vqshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv8i16, ARM_INS_VQSHL: vqshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHLuv8i8, ARM_INS_VQSHL: vqshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRNsv2i32, ARM_INS_VQSHRN: vqshrn${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRNsv4i16, ARM_INS_VQSHRN: vqshrn${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRNsv8i8, ARM_INS_VQSHRN: vqshrn${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRNuv2i32, ARM_INS_VQSHRN: vqshrn${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRNuv4i16, ARM_INS_VQSHRN: vqshrn${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRNuv8i8, ARM_INS_VQSHRN: vqshrn${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRUNv2i32, ARM_INS_VQSHRUN: vqshrun${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRUNv4i16, ARM_INS_VQSHRUN: vqshrun${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSHRUNv8i8, ARM_INS_VQSHRUN: vqshrun${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv16i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv1i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv2i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv2i64, ARM_INS_VQSUB: vqsub${p}.s64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv4i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv4i32, ARM_INS_VQSUB: vqsub${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv8i16, ARM_INS_VQSUB: vqsub${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBsv8i8, ARM_INS_VQSUB: vqsub${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv16i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv1i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv2i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv2i64, ARM_INS_VQSUB: vqsub${p}.u64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv4i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv4i32, ARM_INS_VQSUB: vqsub${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv8i16, ARM_INS_VQSUB: vqsub${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VQSUBuv8i8, ARM_INS_VQSUB: vqsub${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRECPEd, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRECPEfd, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRECPEfq, ARM_INS_VRECPE: vrecpe${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRECPEq, ARM_INS_VRECPE: vrecpe${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRECPSfd, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRECPSfq, ARM_INS_VRECPS: vrecps${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VREV16d8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV16q8, ARM_INS_VREV16: vrev16${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV32d16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV32d8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV32q16, ARM_INS_VREV32: vrev32${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV32q8, ARM_INS_VREV32: vrev32${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV64d16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV64d32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV64d8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV64q16, ARM_INS_VREV64: vrev64${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV64q32, ARM_INS_VREV64: vrev64${p}.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VREV64q8, ARM_INS_VREV64: vrev64${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDsv16i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDsv2i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDsv4i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDsv4i32, ARM_INS_VRHADD: vrhadd${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDsv8i16, ARM_INS_VRHADD: vrhadd${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDsv8i8, ARM_INS_VRHADD: vrhadd${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDuv16i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDuv2i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDuv4i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDuv4i32, ARM_INS_VRHADD: vrhadd${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDuv8i16, ARM_INS_VRHADD: vrhadd${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRHADDuv8i8, ARM_INS_VRHADD: vrhadd${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTAD, ARM_INS_VRINTA: vrinta.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTAND, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTANQ, ARM_INS_VRINTA: vrinta.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTAS, ARM_INS_VRINTA: vrinta.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTMD, ARM_INS_VRINTM: vrintm.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTMND, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTMNQ, ARM_INS_VRINTM: vrintm.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTMS, ARM_INS_VRINTM: vrintm.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTND, ARM_INS_VRINTN: vrintn.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTNND, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTNNQ, ARM_INS_VRINTN: vrintn.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTNS, ARM_INS_VRINTN: vrintn.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTPD, ARM_INS_VRINTP: vrintp.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTPND, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTPNQ, ARM_INS_VRINTP: vrintp.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTPS, ARM_INS_VRINTP: vrintp.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTRD, ARM_INS_VRINTR: vrintr${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTRS, ARM_INS_VRINTR: vrintr${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTXD, ARM_INS_VRINTX: vrintx${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTXND, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTXNQ, ARM_INS_VRINTX: vrintx.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTXS, ARM_INS_VRINTX: vrintx${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTZD, ARM_INS_VRINTZ: vrintz${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTZND, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTZNQ, ARM_INS_VRINTZ: vrintz.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRINTZS, ARM_INS_VRINTZ: vrintz${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv2i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv2i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv4i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv4i32, ARM_INS_VRSHL: vrshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv8i16, ARM_INS_VRSHL: vrshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHLuv8i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRNv2i32, ARM_INS_VRSHRN: vrshrn${p}.i64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRNv4i16, ARM_INS_VRSHRN: vrshrn${p}.i32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRNv8i8, ARM_INS_VRSHRN: vrshrn${p}.i16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv16i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv1i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv2i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv2i64, ARM_INS_VRSHR: vrshr${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv4i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv4i32, ARM_INS_VRSHR: vrshr${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv8i16, ARM_INS_VRSHR: vrshr${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRsv8i8, ARM_INS_VRSHR: vrshr${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv16i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv1i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv2i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv2i64, ARM_INS_VRSHR: vrshr${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv4i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv4i32, ARM_INS_VRSHR: vrshr${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv8i16, ARM_INS_VRSHR: vrshr${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSHRuv8i8, ARM_INS_VRSHR: vrshr${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSQRTEd, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSQRTEfd, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSQRTEfq, ARM_INS_VRSQRTE: vrsqrte${p}.f32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSQRTEq, ARM_INS_VRSQRTE: vrsqrte${p}.u32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSQRTSfd, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSQRTSfq, ARM_INS_VRSQRTS: vrsqrts${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv16i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv1i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv2i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv2i64, ARM_INS_VRSRA: vrsra${p}.s64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv4i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv4i32, ARM_INS_VRSRA: vrsra${p}.s32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv8i16, ARM_INS_VRSRA: vrsra${p}.s16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAsv8i8, ARM_INS_VRSRA: vrsra${p}.s8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv16i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv1i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv2i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv2i64, ARM_INS_VRSRA: vrsra${p}.u64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv4i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv4i32, ARM_INS_VRSRA: vrsra${p}.u32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv8i16, ARM_INS_VRSRA: vrsra${p}.u16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSRAuv8i8, ARM_INS_VRSRA: vrsra${p}.u8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VRSUBHNv2i32, ARM_INS_VRSUBHN: vrsubhn${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSUBHNv4i16, ARM_INS_VRSUBHN: vrsubhn${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VRSUBHNv8i8, ARM_INS_VRSUBHN: vrsubhn${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELEQD, ARM_INS_VSELEQ: vseleq.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELEQS, ARM_INS_VSELEQ: vseleq.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELGED, ARM_INS_VSELGE: vselge.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELGES, ARM_INS_VSELGE: vselge.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELGTD, ARM_INS_VSELGT: vselgt.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELGTS, ARM_INS_VSELGT: vselgt.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELVSD, ARM_INS_VSELVS: vselvs.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSELVSS, ARM_INS_VSELVS: vselvs.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSETLNi16, ARM_INS_VMOV: vmov${p}.16 $v$lane, $r */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSETLNi32, ARM_INS_VMOV: vmov${p}.32 $v$lane, $r */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSETLNi8, ARM_INS_VMOV: vmov${p}.8 $v$lane, $r */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLi16, ARM_INS_VSHLL: vshll${p}.i16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLi32, ARM_INS_VSHLL: vshll${p}.i32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLi8, ARM_INS_VSHLL: vshll${p}.i8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLsv2i64, ARM_INS_VSHLL: vshll${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLsv4i32, ARM_INS_VSHLL: vshll${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLsv8i16, ARM_INS_VSHLL: vshll${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLuv2i64, ARM_INS_VSHLL: vshll${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLuv4i32, ARM_INS_VSHLL: vshll${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLLuv8i16, ARM_INS_VSHLL: vshll${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv16i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv1i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv2i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv2i64, ARM_INS_VSHL: vshl${p}.i64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv4i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv4i32, ARM_INS_VSHL: vshl${p}.i32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv8i16, ARM_INS_VSHL: vshl${p}.i16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLiv8i8, ARM_INS_VSHL: vshl${p}.i8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv16i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv1i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv2i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv2i64, ARM_INS_VSHL: vshl${p}.s64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv4i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv4i32, ARM_INS_VSHL: vshl${p}.s32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv8i16, ARM_INS_VSHL: vshl${p}.s16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLsv8i8, ARM_INS_VSHL: vshl${p}.s8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv16i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv1i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv2i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv2i64, ARM_INS_VSHL: vshl${p}.u64 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv4i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv4i32, ARM_INS_VSHL: vshl${p}.u32 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv8i16, ARM_INS_VSHL: vshl${p}.u16 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHLuv8i8, ARM_INS_VSHL: vshl${p}.u8 $vd, $vm, $vn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRNv2i32, ARM_INS_VSHRN: vshrn${p}.i64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRNv4i16, ARM_INS_VSHRN: vshrn${p}.i32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRNv8i8, ARM_INS_VSHRN: vshrn${p}.i16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv16i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv1i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv2i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv2i64, ARM_INS_VSHR: vshr${p}.s64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv4i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv4i32, ARM_INS_VSHR: vshr${p}.s32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv8i16, ARM_INS_VSHR: vshr${p}.s16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRsv8i8, ARM_INS_VSHR: vshr${p}.s8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv16i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv1i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv2i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv2i64, ARM_INS_VSHR: vshr${p}.u64 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv4i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv4i32, ARM_INS_VSHR: vshr${p}.u32 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv8i16, ARM_INS_VSHR: vshr${p}.u16 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHRuv8i8, ARM_INS_VSHR: vshr${p}.u8 $vd, $vm, $simm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSHTOD, ARM_INS_VCVT: vcvt${p}.f64.s16 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSHTOS, ARM_INS_VCVT: vcvt${p}.f32.s16 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSITOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSITOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv16i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv1i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv2i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv2i64, ARM_INS_VSLI: vsli${p}.64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv4i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv4i32, ARM_INS_VSLI: vsli${p}.32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv8i16, ARM_INS_VSLI: vsli${p}.16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLIv8i8, ARM_INS_VSLI: vsli${p}.8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSLTOD, ARM_INS_VCVT: vcvt${p}.f64.s32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSLTOS, ARM_INS_VCVT: vcvt${p}.f32.s32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSQRTD, ARM_INS_VSQRT: vsqrt${p}.f64 $dd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSQRTS, ARM_INS_VSQRT: vsqrt${p}.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv16i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv1i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv2i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv2i64, ARM_INS_VSRA: vsra${p}.s64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv4i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv4i32, ARM_INS_VSRA: vsra${p}.s32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv8i16, ARM_INS_VSRA: vsra${p}.s16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAsv8i8, ARM_INS_VSRA: vsra${p}.s8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv16i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv1i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv2i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv2i64, ARM_INS_VSRA: vsra${p}.u64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv4i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv4i32, ARM_INS_VSRA: vsra${p}.u32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv8i16, ARM_INS_VSRA: vsra${p}.u16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRAuv8i8, ARM_INS_VSRA: vsra${p}.u8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv16i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv1i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv2i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv2i64, ARM_INS_VSRI: vsri${p}.64 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv4i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv4i32, ARM_INS_VSRI: vsri${p}.32 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv8i16, ARM_INS_VSRI: vsri${p}.16 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VSRIv8i8, ARM_INS_VSRI: vsri${p}.8 $vd, $vm, $simm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VST1LNd16, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1LNd16_UPD, ARM_INS_VST1: vst1${p}.16 \{$vd[$lane]\}, $rn$rm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VST1LNd32, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VST1LNd32_UPD, ARM_INS_VST1: vst1${p}.32 \{$vd[$lane]\}, $rn$rm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VST1LNd8, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1LNd8_UPD, ARM_INS_VST1: vst1${p}.8 \{$vd[$lane]\}, $rn$rm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16Q, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16Qwb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16Qwb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16T, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16Twb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16Twb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32Q, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32Qwb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32Qwb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32T, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32Twb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32Twb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64Q, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64Qwb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64Qwb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64T, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64Twb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64Twb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8Q, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8Qwb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8Qwb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8T, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8Twb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8Twb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1d8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q16, ARM_INS_VST1: vst1${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q16wb_fixed, ARM_INS_VST1: vst1${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q16wb_register, ARM_INS_VST1: vst1${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q32, ARM_INS_VST1: vst1${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q32wb_fixed, ARM_INS_VST1: vst1${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q32wb_register, ARM_INS_VST1: vst1${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q64, ARM_INS_VST1: vst1${p}.64 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q64wb_fixed, ARM_INS_VST1: vst1${p}.64 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q64wb_register, ARM_INS_VST1: vst1${p}.64 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q8, ARM_INS_VST1: vst1${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q8wb_fixed, ARM_INS_VST1: vst1${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST1q8wb_register, ARM_INS_VST1: vst1${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNd16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNd16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNd32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNd32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNd8, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNd8_UPD, ARM_INS_VST2: vst2${p}.8 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNq16, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNq16_UPD, ARM_INS_VST2: vst2${p}.16 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNq32, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2LNq32_UPD, ARM_INS_VST2: vst2${p}.32 \{$vd[$lane], $src2[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2b8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2d8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q16, ARM_INS_VST2: vst2${p}.16 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q16wb_fixed, ARM_INS_VST2: vst2${p}.16 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q16wb_register, ARM_INS_VST2: vst2${p}.16 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q32, ARM_INS_VST2: vst2${p}.32 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q32wb_fixed, ARM_INS_VST2: vst2${p}.32 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q32wb_register, ARM_INS_VST2: vst2${p}.32 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q8, ARM_INS_VST2: vst2${p}.8 $vd, $rn */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q8wb_fixed, ARM_INS_VST2: vst2${p}.8 $vd, $rn! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST2q8wb_register, ARM_INS_VST2: vst2${p}.8 $vd, $rn, $rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNd16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNd16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNd32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNd32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNd8, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNd8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNq16, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNq16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNq32, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3LNq32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3d16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3d16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3d32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3d32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3d8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3d8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3q16, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3q16_UPD, ARM_INS_VST3: vst3${p}.16 \{$vd, $src2, $src3\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3q32, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3q32_UPD, ARM_INS_VST3: vst3${p}.32 \{$vd, $src2, $src3\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3q8, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST3q8_UPD, ARM_INS_VST3: vst3${p}.8 \{$vd, $src2, $src3\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNd16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNd16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNd32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNd32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNd8, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNd8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNq16, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNq16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNq32, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4LNq32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4d16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4d16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4d32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4d32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4d8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4d8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4q16, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4q16_UPD, ARM_INS_VST4: vst4${p}.16 \{$vd, $src2, $src3, $src4\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4q32, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4q32_UPD, ARM_INS_VST4: vst4${p}.32 \{$vd, $src2, $src3, $src4\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4q8, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VST4q8_UPD, ARM_INS_VST4: vst4${p}.8 \{$vd, $src2, $src3, $src4\}, $rn$rm */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSTMDDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSTMDIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VSTMDIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSTMSDB_UPD, ARM_INS_VSTMDB: vstmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSTMSIA, ARM_INS_VSTMIA: vstmia${p} $rn, $regs */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VSTMSIA_UPD, ARM_INS_VSTMIA: vstmia${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VSTRD, ARM_INS_VSTR: vstr${p} $dd, $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VSTRS, ARM_INS_VSTR: vstr${p} $sd, $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_VSUBD, ARM_INS_VSUB: vsub${p}.f64 $dd, $dn, $dm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBHNv2i32, ARM_INS_VSUBHN: vsubhn${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBHNv4i16, ARM_INS_VSUBHN: vsubhn${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBHNv8i8, ARM_INS_VSUBHN: vsubhn${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBLsv2i64, ARM_INS_VSUBL: vsubl${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBLsv4i32, ARM_INS_VSUBL: vsubl${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBLsv8i16, ARM_INS_VSUBL: vsubl${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBLuv2i64, ARM_INS_VSUBL: vsubl${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBLuv4i32, ARM_INS_VSUBL: vsubl${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBLuv8i16, ARM_INS_VSUBL: vsubl${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBS, ARM_INS_VSUB: vsub${p}.f32 $sd, $sn, $sm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBWsv2i64, ARM_INS_VSUBW: vsubw${p}.s32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBWsv4i32, ARM_INS_VSUBW: vsubw${p}.s16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBWsv8i16, ARM_INS_VSUBW: vsubw${p}.s8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBWuv2i64, ARM_INS_VSUBW: vsubw${p}.u32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBWuv4i32, ARM_INS_VSUBW: vsubw${p}.u16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBWuv8i16, ARM_INS_VSUBW: vsubw${p}.u8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBfd, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBfq, ARM_INS_VSUB: vsub${p}.f32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv16i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv1i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv2i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv2i64, ARM_INS_VSUB: vsub${p}.i64 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv4i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv4i32, ARM_INS_VSUB: vsub${p}.i32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv8i16, ARM_INS_VSUB: vsub${p}.i16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSUBv8i8, ARM_INS_VSUB: vsub${p}.i8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VSWPd, ARM_INS_VSWP: vswp${p} $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VSWPq, ARM_INS_VSWP: vswp${p} $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTBL1, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBL2, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBL3, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBL4, ARM_INS_VTBL: vtbl${p}.8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBX1, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBX2, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBX3, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTBX4, ARM_INS_VTBX: vtbx${p}.8 $vd, $vn, $vm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTOSHD, ARM_INS_VCVT: vcvt${p}.s16.f64 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOSHS, ARM_INS_VCVT: vcvt${p}.s16.f32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOSIRD, ARM_INS_VCVTR: vcvtr${p}.s32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOSIRS, ARM_INS_VCVTR: vcvtr${p}.s32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOSIZD, ARM_INS_VCVT: vcvt${p}.s32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOSIZS, ARM_INS_VCVT: vcvt${p}.s32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOSLD, ARM_INS_VCVT: vcvt${p}.s32.f64 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOSLS, ARM_INS_VCVT: vcvt${p}.s32.f32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOUHD, ARM_INS_VCVT: vcvt${p}.u16.f64 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOUHS, ARM_INS_VCVT: vcvt${p}.u16.f32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOUIRD, ARM_INS_VCVTR: vcvtr${p}.u32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOUIRS, ARM_INS_VCVTR: vcvtr${p}.u32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOUIZD, ARM_INS_VCVT: vcvt${p}.u32.f64 $sd, $dm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOUIZS, ARM_INS_VCVT: vcvt${p}.u32.f32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VTOULD, ARM_INS_VCVT: vcvt${p}.u32.f64 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTOULS, ARM_INS_VCVT: vcvt${p}.u32.f32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VTRNd16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTRNd32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTRNd8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTRNq16, ARM_INS_VTRN: vtrn${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTRNq32, ARM_INS_VTRN: vtrn${p}.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTRNq8, ARM_INS_VTRN: vtrn${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VTSTv16i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTSTv2i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTSTv4i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTSTv4i32, ARM_INS_VTST: vtst${p}.32 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTSTv8i16, ARM_INS_VTST: vtst${p}.16 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VTSTv8i8, ARM_INS_VTST: vtst${p}.8 $vd, $vn, $vm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_VUHTOD, ARM_INS_VCVT: vcvt${p}.f64.u16 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VUHTOS, ARM_INS_VCVT: vcvt${p}.f32.u16 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VUITOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VUITOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $sd, $sm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_VULTOD, ARM_INS_VCVT: vcvt${p}.f64.u32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VULTOS, ARM_INS_VCVT: vcvt${p}.f32.u32 $dst, $a, $fbits */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_VUZPd16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VUZPd8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VUZPq16, ARM_INS_VUZP: vuzp${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VUZPq32, ARM_INS_VUZP: vuzp${p}.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VUZPq8, ARM_INS_VUZP: vuzp${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VZIPd16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VZIPd8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VZIPq16, ARM_INS_VZIP: vzip${p}.16 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VZIPq32, ARM_INS_VZIP: vzip${p}.32 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_VZIPq8, ARM_INS_VZIP: vzip${p}.8 $vd, $vm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMDA, ARM_INS_LDMDA: ldmda${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMDA_UPD, ARM_INS_LDMDA: ldmda${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMIA_UPD, ARM_INS_LDM: ldm${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMIB, ARM_INS_LDMIB: ldmib${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysLDMIB_UPD, ARM_INS_LDMIB: ldmib${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_sysSTMDA, ARM_INS_STMDA: stmda${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMDA_UPD, ARM_INS_STMDA: stmda${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMIA, ARM_INS_STM: stm${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMIB, ARM_INS_STMIB: stmib${p} $rn, $regs ^ */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_sysSTMIB_UPD, ARM_INS_STMIB: stmib${p} $rn!, $regs ^ */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADCri, ARM_INS_ADC: adc${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADCrr, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADCrs, ARM_INS_ADC: adc${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADDri, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADDri12, ARM_INS_ADDW: addw${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADDrr, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADDrs, ARM_INS_ADD: add${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ADR, ARM_INS_ADR: adr{$p}.w $rd, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2ANDri, ARM_INS_AND: and${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ANDrr, ARM_INS_AND: and${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2ANDrs, ARM_INS_AND: and${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ASRri, ARM_INS_ASR: asr${s}${p}.w $rd, $rm, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ASRrr, ARM_INS_ASR: asr${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2B, ARM_INS_B: b${p}.w $target */ - { 0 } -}, -{ /* ARM_t2BFC, ARM_INS_BFC: bfc${p} $rd, $imm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_t2BFI, ARM_INS_BFI: bfi${p} $rd, $rn, $imm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2BICri, ARM_INS_BIC: bic${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2BICrr, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2BICrs, ARM_INS_BIC: bic${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2BXJ, ARM_INS_BXJ: bxj${p} $func */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2Bcc, ARM_INS_B: b${p}.w $target */ - { 0 } -}, -{ /* ARM_t2CDP, ARM_INS_CDP: cdp${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_t2CDP2, ARM_INS_CDP2: cdp2${p} $cop, $opc1, $crd, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_t2CLREX, ARM_INS_CLREX: clrex${p} */ - { 0 } -}, -{ /* ARM_t2CLZ, ARM_INS_CLZ: clz${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2CMNri, ARM_INS_CMN: cmn${p}.w $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2CMNzrr, ARM_INS_CMN: cmn${p}.w $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CMNzrs, ARM_INS_CMN: cmn${p}.w $rn, $shiftedrm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2CMPri, ARM_INS_CMP: cmp${p}.w $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2CMPrr, ARM_INS_CMP: cmp${p}.w $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CMPrs, ARM_INS_CMP: cmp${p}.w $rn, $shiftedrm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2CPS1p, ARM_INS_CPS: cps $mode */ - { 0 } -}, -{ /* ARM_t2CPS2p, ARM_INS_CPS: cps$imod.w $iflags */ - { 0 } -}, -{ /* ARM_t2CPS3p, ARM_INS_CPS: cps$imod $iflags, $mode */ - { 0 } -}, -{ /* ARM_t2CRC32B, ARM_INS_CRC32B: crc32b $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CRC32CB, ARM_INS_CRC32CB: crc32cb $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CRC32CH, ARM_INS_CRC32CH: crc32ch $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CRC32CW, ARM_INS_CRC32CW: crc32cw $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CRC32H, ARM_INS_CRC32H: crc32h $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2CRC32W, ARM_INS_CRC32W: crc32w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2DBG, ARM_INS_DBG: dbg${p} $opt */ - { 0 } -}, -{ /* ARM_t2DCPS1, ARM_INS_DCPS1: dcps1${p} */ - { 0 } -}, -{ /* ARM_t2DCPS2, ARM_INS_DCPS2: dcps2${p} */ - { 0 } -}, -{ /* ARM_t2DCPS3, ARM_INS_DCPS3: dcps3${p} */ - { 0 } -}, -{ /* ARM_t2DMB, ARM_INS_DMB: dmb${p} $opt */ - { 0 } -}, -{ /* ARM_t2DSB, ARM_INS_DSB: dsb${p} $opt */ - { 0 } -}, -{ /* ARM_t2EORri, ARM_INS_EOR: eor${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2EORrr, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2EORrs, ARM_INS_EOR: eor${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2HINT, ARM_INS_HINT: hint${p}.w $imm */ - { 0 } -}, -{ /* ARM_t2HVC, ARM_INS_HVC: hvc.w $imm16 */ - { 0 } -}, -{ /* ARM_t2ISB, ARM_INS_ISB: isb${p} $opt */ - { 0 } -}, -{ /* ARM_t2IT, ARM_INS_IT: it$mask $cc */ - { 0 } -}, -{ /* ARM_t2LDA, ARM_INS_LDA: lda${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDAB, ARM_INS_LDAB: ldab${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDAEX, ARM_INS_LDAEX: ldaex${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDAEXB, ARM_INS_LDAEXB: ldaexb${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDAEXD, ARM_INS_LDAEXD: ldaexd${p} $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDAEXH, ARM_INS_LDAEXH: ldaexh${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDAH, ARM_INS_LDAH: ldah${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2L_OPTION, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2L_POST, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2L_PRE, ARM_INS_LDC2L: ldc2l${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2_OFFSET, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2_OPTION, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2_POST, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC2_PRE, ARM_INS_LDC2: ldc2${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDCL_OFFSET, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDCL_OPTION, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDCL_POST, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDCL_PRE, ARM_INS_LDCL: ldcl${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC_OFFSET, ARM_INS_LDC: ldc${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC_OPTION, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC_POST, ARM_INS_LDC: ldc${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDC_PRE, ARM_INS_LDC: ldc${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDMDB, ARM_INS_LDMDB: ldmdb${p} $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDMDB_UPD, ARM_INS_LDMDB: ldmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDMIA, ARM_INS_LDM: ldm${p}.w $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDMIA_UPD, ARM_INS_LDM: ldm${p}.w $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRBT, ARM_INS_LDRBT: ldrbt${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRB_POST, ARM_INS_LDRB: ldrb${p} $rt, $rn$offset */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRB_PRE, ARM_INS_LDRB: ldrb${p} $rt, $addr! */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRBi12, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRBi8, ARM_INS_LDRB: ldrb${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRBpci, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRBs, ARM_INS_LDRB: ldrb${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRD_POST, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr$imm */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRD_PRE, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr! */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRDi8, ARM_INS_LDRD: ldrd${p} $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDREX, ARM_INS_LDREX: ldrex${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDREXB, ARM_INS_LDREXB: ldrexb${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDREXD, ARM_INS_LDREXD: ldrexd${p} $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDREXH, ARM_INS_LDREXH: ldrexh${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRHT, ARM_INS_LDRHT: ldrht${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRH_POST, ARM_INS_LDRH: ldrh${p} $rt, $rn$offset */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRH_PRE, ARM_INS_LDRH: ldrh${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRHi12, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRHi8, ARM_INS_LDRH: ldrh${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRHpci, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRHs, ARM_INS_LDRH: ldrh${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSBT, ARM_INS_LDRSBT: ldrsbt${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSB_POST, ARM_INS_LDRSB: ldrsb${p} $rt, $rn$offset */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRSB_PRE, ARM_INS_LDRSB: ldrsb${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSBi12, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSBi8, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSBpci, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSBs, ARM_INS_LDRSB: ldrsb${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSHT, ARM_INS_LDRSHT: ldrsht${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSH_POST, ARM_INS_LDRSH: ldrsh${p} $rt, $rn$offset */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRSH_PRE, ARM_INS_LDRSH: ldrsh${p} $rt, $addr! */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSHi12, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSHi8, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSHpci, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRSHs, ARM_INS_LDRSH: ldrsh${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LDRT, ARM_INS_LDRT: ldrt${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDR_POST, ARM_INS_LDR: ldr${p} $rt, $rn$offset */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDR_PRE, ARM_INS_LDR: ldr${p} $rt, $addr! */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRi12, ARM_INS_LDR: ldr${p}.w $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRi8, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRpci, ARM_INS_LDR: ldr${p}.w $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2LDRs, ARM_INS_LDR: ldr${p}.w $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LSLri, ARM_INS_LSL: lsl${s}${p}.w $rd, $rm, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LSLrr, ARM_INS_LSL: lsl${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2LSRri, ARM_INS_LSR: lsr${s}${p}.w $rd, $rm, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2LSRrr, ARM_INS_LSR: lsr${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MCR, ARM_INS_MCR: mcr${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_t2MCR2, ARM_INS_MCR2: mcr2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_t2MCRR, ARM_INS_MCRR: mcrr${p} $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MCRR2, ARM_INS_MCRR2: mcrr2${p} $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MLA, ARM_INS_MLA: mla${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MLS, ARM_INS_MLS: mls${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MOVTi16, ARM_INS_MOVT: movt${p} $rd, $imm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MOVi, ARM_INS_MOV: mov${s}${p}.w $rd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MOVi16, ARM_INS_MOVW: movw${p} $rd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MOVr, ARM_INS_MOV: mov${s}${p}.w $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2MOVsra_flag, ARM_INS_ASR: asrs${p}.w $rd, $rm, #1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2MOVsrl_flag, ARM_INS_LSR: lsrs${p}.w $rd, $rm, #1 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2MRC, ARM_INS_MRC: mrc${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_t2MRC2, ARM_INS_MRC2: mrc2${p} $cop, $opc1, $rt, $crn, $crm, $opc2 */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_IGNORE, 0 } -}, -{ /* ARM_t2MRRC, ARM_INS_MRRC: mrrc${p} $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MRRC2, ARM_INS_MRRC2: mrrc2${p} $cop, $opc1, $rt, $rt2, $crm */ - { CS_AC_READ, CS_AC_IGNORE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MRS_AR, ARM_INS_MRS: mrs${p} $rd, apsr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MRS_M, ARM_INS_MRS: mrs${p} $rd, $sysm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MRSbanked, ARM_INS_MRS: mrs${p} $rd, $banked */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MRSsys_AR, ARM_INS_MRS: mrs${p} $rd, spsr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MSR_AR, ARM_INS_MSR: msr${p} $mask, $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2MSR_M, ARM_INS_MSR: msr${p} $sysm, $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2MSRbanked, ARM_INS_MSR: msr${p} $banked, $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2MUL, ARM_INS_MUL: mul${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2MVNi, ARM_INS_MVN: mvn${s}${p} $rd, $imm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2MVNr, ARM_INS_MVN: mvn${s}${p}.w $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2MVNs, ARM_INS_MVN: mvn${s}${p}.w $rd, $shiftedrm */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2ORNri, ARM_INS_ORN: orn${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ORNrr, ARM_INS_ORN: orn${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2ORNrs, ARM_INS_ORN: orn${s}${p} $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ORRri, ARM_INS_ORR: orr${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2ORRrr, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2ORRrs, ARM_INS_ORR: orr${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2PKHBT, ARM_INS_PKHBT: pkhbt${p} $rd, $rn, $rm$sh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2PKHTB, ARM_INS_PKHTB: pkhtb${p} $rd, $rn, $rm$sh */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDWi12, ARM_INS_PLDW: pldw${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDWi8, ARM_INS_PLDW: pldw${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDWs, ARM_INS_PLDW: pldw${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDi12, ARM_INS_PLD: pld${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDi8, ARM_INS_PLD: pld${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDpci, ARM_INS_PLD: pld${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLDs, ARM_INS_PLD: pld${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLIi12, ARM_INS_PLI: pli${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLIi8, ARM_INS_PLI: pli${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLIpci, ARM_INS_PLI: pli${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2PLIs, ARM_INS_PLI: pli${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2QADD, ARM_INS_QADD: qadd${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QADD16, ARM_INS_QADD16: qadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QADD8, ARM_INS_QADD8: qadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QASX, ARM_INS_QASX: qasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QDADD, ARM_INS_QDADD: qdadd${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QDSUB, ARM_INS_QDSUB: qdsub${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QSAX, ARM_INS_QSAX: qsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QSUB, ARM_INS_QSUB: qsub${p} $rd, $rm, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QSUB16, ARM_INS_QSUB16: qsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2RBIT, ARM_INS_RBIT: rbit${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2REV, ARM_INS_REV: rev${p}.w $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2REV16, ARM_INS_REV16: rev16${p}.w $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2REVSH, ARM_INS_REVSH: revsh${p}.w $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2RFEDB, ARM_INS_RFEDB: rfedb${p} $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2RFEDBW, ARM_INS_RFEDB: rfedb${p} $rn! */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2RFEIA, ARM_INS_RFEIA: rfeia${p} $rn */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2RFEIAW, ARM_INS_RFEIA: rfeia${p} $rn! */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2RORri, ARM_INS_ROR: ror${s}${p}.w $rd, $rm, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2RORrr, ARM_INS_ROR: ror${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2RRX, ARM_INS_RRX: rrx${s}${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2RSBri, ARM_INS_RSB: rsb${s}${p}.w $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2RSBrr, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2RSBrs, ARM_INS_RSB: rsb${s}${p} $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SADD16, ARM_INS_SADD16: sadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SADD8, ARM_INS_SADD8: sadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SASX, ARM_INS_SASX: sasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SBCri, ARM_INS_SBC: sbc${s}${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SBCrr, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SBCrs, ARM_INS_SBC: sbc${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SBFX, ARM_INS_SBFX: sbfx${p} $rd, $rn, $lsb, $msb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SDIV, ARM_INS_SDIV: sdiv${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SEL, ARM_INS_SEL: sel${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SHADD16, ARM_INS_SHADD16: shadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SHADD8, ARM_INS_SHADD8: shadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SHASX, ARM_INS_SHASX: shasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SHSAX, ARM_INS_SHSAX: shsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SHSUB16, ARM_INS_SHSUB16: shsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SHSUB8, ARM_INS_SHSUB8: shsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMC, ARM_INS_SMC: smc${p} $opt */ - { 0 } -}, -{ /* ARM_t2SMLABB, ARM_INS_SMLABB: smlabb${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLABT, ARM_INS_SMLABT: smlabt${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLAD, ARM_INS_SMLAD: smlad${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLADX, ARM_INS_SMLADX: smladx${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLAL, ARM_INS_SMLAL: smlal${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLALBB, ARM_INS_SMLALBB: smlalbb${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLALBT, ARM_INS_SMLALBT: smlalbt${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLALD, ARM_INS_SMLALD: smlald${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLALDX, ARM_INS_SMLALDX: smlaldx${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLALTB, ARM_INS_SMLALTB: smlaltb${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLALTT, ARM_INS_SMLALTT: smlaltt${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLATB, ARM_INS_SMLATB: smlatb${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLATT, ARM_INS_SMLATT: smlatt${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLAWB, ARM_INS_SMLAWB: smlawb${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLAWT, ARM_INS_SMLAWT: smlawt${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLSD, ARM_INS_SMLSD: smlsd${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLSDX, ARM_INS_SMLSDX: smlsdx${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLSLD, ARM_INS_SMLSLD: smlsld${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMLSLDX, ARM_INS_SMLSLDX: smlsldx${p} $ra, $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMMLA, ARM_INS_SMMLA: smmla${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMMLAR, ARM_INS_SMMLAR: smmlar${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMMLS, ARM_INS_SMMLS: smmls${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMMLSR, ARM_INS_SMMLSR: smmlsr${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMMUL, ARM_INS_SMMUL: smmul${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMMULR, ARM_INS_SMMULR: smmulr${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMUADX, ARM_INS_SMUADX: smuadx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULBB, ARM_INS_SMULBB: smulbb${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULBT, ARM_INS_SMULBT: smulbt${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULL, ARM_INS_SMULL: smull${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULTB, ARM_INS_SMULTB: smultb${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULTT, ARM_INS_SMULTT: smultt${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULWB, ARM_INS_SMULWB: smulwb${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMULWT, ARM_INS_SMULWT: smulwt${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMUSD, ARM_INS_SMUSD: smusd${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SMUSDX, ARM_INS_SMUSDX: smusdx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SRSDB, ARM_INS_SRSDB: srsdb${p} sp, $mode */ - { 0 } -}, -{ /* ARM_t2SRSDB_UPD, ARM_INS_SRSDB: srsdb${p} sp!, $mode */ - { 0 } -}, -{ /* ARM_t2SRSIA, ARM_INS_SRSIA: srsia${p} sp, $mode */ - { 0 } -}, -{ /* ARM_t2SRSIA_UPD, ARM_INS_SRSIA: srsia${p} sp!, $mode */ - { 0 } -}, -{ /* ARM_t2SSAT, ARM_INS_SSAT: ssat${p} $rd, $sat_imm, $rn$sh */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2SSAT16, ARM_INS_SSAT16: ssat16${p} $rd, $sat_imm, $rn */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SSAX, ARM_INS_SSAX: ssax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SSUB16, ARM_INS_SSUB16: ssub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SSUB8, ARM_INS_SSUB8: ssub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2L_OFFSET, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2L_OPTION, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2L_POST, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2L_PRE, ARM_INS_STC2L: stc2l${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2_OFFSET, ARM_INS_STC2: stc2${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2_OPTION, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2_POST, ARM_INS_STC2: stc2${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC2_PRE, ARM_INS_STC2: stc2${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STCL_OFFSET, ARM_INS_STCL: stcl${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STCL_OPTION, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STCL_POST, ARM_INS_STCL: stcl${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STCL_PRE, ARM_INS_STCL: stcl${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC_OFFSET, ARM_INS_STC: stc${p} $cop, $crd, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC_OPTION, ARM_INS_STC: stc${p} $cop, $crd, $addr, $option */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC_POST, ARM_INS_STC: stc${p} $cop, $crd, $addr, $offset */ - { CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STC_PRE, ARM_INS_STC: stc${p} $cop, $crd, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STL, ARM_INS_STL: stl${p} $rt, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STLB, ARM_INS_STLB: stlb${p} $rt, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STLEX, ARM_INS_STLEX: stlex${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STLEXB, ARM_INS_STLEXB: stlexb${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STLEXD, ARM_INS_STLEXD: stlexd${p} $rd, $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STLEXH, ARM_INS_STLEXH: stlexh${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STLH, ARM_INS_STLH: stlh${p} $rt, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STMDB, ARM_INS_STMDB: stmdb${p} $rn, $regs */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STMDB_UPD, ARM_INS_STMDB: stmdb${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2STMIA, ARM_INS_STM: stm${p}.w $rn, $regs */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STMIA_UPD, ARM_INS_STM: stm${p}.w $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2STRBT, ARM_INS_STRBT: strbt${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRB_POST, ARM_INS_STRB: strb${p} $rt, $rn$offset */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2STRB_PRE, ARM_INS_STRB: strb${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRBi12, ARM_INS_STRB: strb${p}.w $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRBi8, ARM_INS_STRB: strb${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRBs, ARM_INS_STRB: strb${p}.w $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRD_POST, ARM_INS_STRD: strd${p} $rt, $rt2, $addr$imm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STRD_PRE, ARM_INS_STRD: strd${p} $rt, $rt2, $addr! */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STRDi8, ARM_INS_STRD: strd${p} $rt, $rt2, $addr */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STREX, ARM_INS_STREX: strex${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2STREXB, ARM_INS_STREXB: strexb${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STREXD, ARM_INS_STREXD: strexd${p} $rd, $rt, $rt2, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STREXH, ARM_INS_STREXH: strexh${p} $rd, $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2STRHT, ARM_INS_STRHT: strht${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRH_POST, ARM_INS_STRH: strh${p} $rt, $rn$offset */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRH_PRE, ARM_INS_STRH: strh${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRHi12, ARM_INS_STRH: strh${p}.w $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRHi8, ARM_INS_STRH: strh${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRHs, ARM_INS_STRH: strh${p}.w $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRT, ARM_INS_STRT: strt${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STR_POST, ARM_INS_STR: str${p} $rt, $rn$offset */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2STR_PRE, ARM_INS_STR: str${p} $rt, $addr! */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRi12, ARM_INS_STR: str${p}.w $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRi8, ARM_INS_STR: str${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2STRs, ARM_INS_STR: str${p}.w $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_t2SUBS_PC_LR, ARM_INS_SUB: subs${p} pc, lr, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SUBri, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SUBri12, ARM_INS_SUBW: subw${p} $rd, $rn, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SUBrr, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2SUBrs, ARM_INS_SUB: sub${s}${p}.w $rd, $rn, $shiftedrm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SXTAB, ARM_INS_SXTAB: sxtab${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SXTAB16, ARM_INS_SXTAB16: sxtab16${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SXTAH, ARM_INS_SXTAH: sxtah${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SXTB, ARM_INS_SXTB: sxtb${p}.w $rd, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SXTB16, ARM_INS_SXTB16: sxtb16${p} $rd, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2SXTH, ARM_INS_SXTH: sxth${p}.w $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2TBB, ARM_INS_TBB: tbb${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2TBH, ARM_INS_TBH: tbh${p} $addr */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2TEQri, ARM_INS_TEQ: teq${p}.w $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2TEQrr, ARM_INS_TEQ: teq${p}.w $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2TEQrs, ARM_INS_TEQ: teq${p}.w $rn, $shiftedrm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2TSTri, ARM_INS_TST: tst${p}.w $rn, $imm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2TSTrr, ARM_INS_TST: tst${p}.w $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2TSTrs, ARM_INS_TST: tst${p}.w $rn, $shiftedrm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_t2UADD16, ARM_INS_UADD16: uadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UADD8, ARM_INS_UADD8: uadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UASX, ARM_INS_UASX: uasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UBFX, ARM_INS_UBFX: ubfx${p} $rd, $rn, $lsb, $msb */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2UDF, ARM_INS_UDF: udf.w $imm16 */ - { 0 } -}, -{ /* ARM_t2UDIV, ARM_INS_UDIV: udiv${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UHADD16, ARM_INS_UHADD16: uhadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UHADD8, ARM_INS_UHADD8: uhadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UHASX, ARM_INS_UHASX: uhasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UHSAX, ARM_INS_UHSAX: uhsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UHSUB16, ARM_INS_UHSUB16: uhsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UHSUB8, ARM_INS_UHSUB8: uhsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UMAAL, ARM_INS_UMAAL: umaal${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UMLAL, ARM_INS_UMLAL: umlal${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UMULL, ARM_INS_UMULL: umull${p} $rdlo, $rdhi, $rn, $rm */ - { CS_AC_WRITE, CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UQADD16, ARM_INS_UQADD16: uqadd16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UQADD8, ARM_INS_UQADD8: uqadd8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UQASX, ARM_INS_UQASX: uqasx${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UQSAX, ARM_INS_UQSAX: uqsax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UQSUB16, ARM_INS_UQSUB16: uqsub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UQSUB8, ARM_INS_UQSUB8: uqsub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2USAD8, ARM_INS_USAD8: usad8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2USADA8, ARM_INS_USADA8: usada8${p} $rd, $rn, $rm, $ra */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2USAT, ARM_INS_USAT: usat${p} $rd, $sat_imm, $rn$sh */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2USAT16, ARM_INS_USAT16: usat16${p} $rd, $sat_imm, $rn */ - { CS_AC_WRITE, CS_AC_IGNORE, CS_AC_READ, 0 } -}, -{ /* ARM_t2USAX, ARM_INS_USAX: usax${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2USUB16, ARM_INS_USUB16: usub16${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2USUB8, ARM_INS_USUB8: usub8${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_t2UXTAB, ARM_INS_UXTAB: uxtab${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2UXTAB16, ARM_INS_UXTAB16: uxtab16${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2UXTAH, ARM_INS_UXTAH: uxtah${p} $rd, $rn, $rm$rot */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_t2UXTB, ARM_INS_UXTB: uxtb${p}.w $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2UXTB16, ARM_INS_UXTB16: uxtb16${p} $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_t2UXTH, ARM_INS_UXTH: uxth${p}.w $rd, $rm$rot */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tADC, ARM_INS_ADC: adc${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tADDhirr, ARM_INS_ADD: add${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tADDi3, ARM_INS_ADD: add${s}${p} $rd, $rm, $imm3 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tADDi8, ARM_INS_ADD: add${s}${p} $rdn, $imm8 */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_tADDrSP, ARM_INS_ADD: add${p} $rdn, $sp, $rn */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tADDrSPi, ARM_INS_ADD: add${p} $dst, $sp, $imm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tADDrr, ARM_INS_ADD: add${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tADDspi, ARM_INS_ADD: add${p} $rdn, $imm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_tADDspr, ARM_INS_ADD: add${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tADR, ARM_INS_ADR: adr{$p} $rd, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tAND, ARM_INS_AND: and${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tASRri, ARM_INS_ASR: asr${s}${p} $rd, $rm, $imm5 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tASRrr, ARM_INS_ASR: asr${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tB, ARM_INS_B: b${p} $target */ - { 0 } -}, -{ /* ARM_tBIC, ARM_INS_BIC: bic${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tBKPT, ARM_INS_BKPT: bkpt $val */ - { 0 } -}, -{ /* ARM_tBL, ARM_INS_BL: bl${p} $func */ - { 0 } -}, -{ /* ARM_tBLXi, ARM_INS_BLX: blx${p} $func */ - { 0 } -}, -{ /* ARM_tBLXr, ARM_INS_BLX: blx${p} $func */ - { CS_AC_READ, 0 } -}, -{ /* ARM_tBX, ARM_INS_BX: bx${p} $rm */ - { CS_AC_READ, 0 } -}, -{ /* ARM_tBcc, ARM_INS_B: b${p} $target */ - { 0 } -}, -{ /* ARM_tCBNZ, ARM_INS_CBNZ: cbnz $rn, $target */ - { CS_AC_READ, 0 } -}, -{ /* ARM_tCBZ, ARM_INS_CBZ: cbz $rn, $target */ - { CS_AC_READ, 0 } -}, -{ /* ARM_tCMNz, ARM_INS_CMN: cmn${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tCMPhir, ARM_INS_CMP: cmp${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tCMPi8, ARM_INS_CMP: cmp${p} $rn, $imm8 */ - { CS_AC_READ, 0 } -}, -{ /* ARM_tCMPr, ARM_INS_CMP: cmp${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tCPS, ARM_INS_CPS: cps$imod $iflags */ - { 0 } -}, -{ /* ARM_tEOR, ARM_INS_EOR: eor${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tHINT, ARM_INS_HINT: hint${p} $imm */ - { 0 } -}, -{ /* ARM_tHLT, ARM_INS_HLT: hlt $val */ - { 0 } -}, -{ /* ARM_tLDMIA, ARM_INS_LDM: ldm${p} $rn, $regs */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRBi, ARM_INS_LDRB: ldrb${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRBr, ARM_INS_LDRB: ldrb${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRHi, ARM_INS_LDRH: ldrh${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRHr, ARM_INS_LDRH: ldrh${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRSB, ARM_INS_LDRSB: ldrsb${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRSH, ARM_INS_LDRSH: ldrsh${p} $rt, $addr */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tLDRi, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLDRpci, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLDRr, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLDRspi, ARM_INS_LDR: ldr${p} $rt, $addr */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLSLri, ARM_INS_LSL: lsl${s}${p} $rd, $rm, $imm5 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLSLrr, ARM_INS_LSL: lsl${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLSRri, ARM_INS_LSR: lsr${s}${p} $rd, $rm, $imm5 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tLSRrr, ARM_INS_LSR: lsr${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tMOVSr, ARM_INS_MOV: movs $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tMOVi8, ARM_INS_MOV: mov${s}${p} $rd, $imm8 */ - { CS_AC_WRITE, 0 } -}, -{ /* ARM_tMOVr, ARM_INS_MOV: mov${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tMUL, ARM_INS_MUL: mul${s}${p} $rd, $rn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_tMVN, ARM_INS_MVN: mvn${s}${p} $rd, $rn */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tORR, ARM_INS_ORR: orr${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tPOP, ARM_INS_POP: pop${p} $regs */ - { 0 } -}, -{ /* ARM_tPUSH, ARM_INS_PUSH: push${p} $regs */ - { 0 } -}, -{ /* ARM_tREV, ARM_INS_REV: rev${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tREV16, ARM_INS_REV16: rev16${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tREVSH, ARM_INS_REVSH: revsh${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tROR, ARM_INS_ROR: ror${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tRSB, ARM_INS_RSB: rsb${s}${p} $rd, $rn, #0 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tSBC, ARM_INS_SBC: sbc${s}${p} $rdn, $rm */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tSETEND, ARM_INS_SETEND: setend $end */ - { 0 } -}, -{ /* ARM_tSTMIA_UPD, ARM_INS_STM: stm${p} $rn!, $regs */ - { CS_AC_READ | CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tSTRBi, ARM_INS_STRB: strb${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSTRBr, ARM_INS_STRB: strb${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSTRHi, ARM_INS_STRH: strh${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSTRHr, ARM_INS_STRH: strh${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSTRi, ARM_INS_STR: str${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSTRr, ARM_INS_STR: str${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSTRspi, ARM_INS_STR: str${p} $rt, $addr */ - { CS_AC_READ, CS_AC_WRITE, 0 } -}, -{ /* ARM_tSUBi3, ARM_INS_SUB: sub${s}${p} $rd, $rm, $imm3 */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tSUBi8, ARM_INS_SUB: sub${s}${p} $rdn, $imm8 */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_tSUBrr, ARM_INS_SUB: sub${s}${p} $rd, $rn, $rm */ - { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tSUBspi, ARM_INS_SUB: sub${p} $rdn, $imm */ - { CS_AC_READ | CS_AC_WRITE, 0 } -}, -{ /* ARM_tSVC, ARM_INS_SVC: svc${p} $imm */ - { 0 } -}, -{ /* ARM_tSXTB, ARM_INS_SXTB: sxtb${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tSXTH, ARM_INS_SXTH: sxth${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tTRAP, ARM_INS_TRAP: trap */ - { 0 } -}, -{ /* ARM_tTST, ARM_INS_TST: tst${p} $rn, $rm */ - { CS_AC_READ, CS_AC_READ, 0 } -}, -{ /* ARM_tUDF, ARM_INS_UDF: udf $imm8 */ - { 0 } -}, -{ /* ARM_tUXTB, ARM_INS_UXTB: uxtb${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, -{ /* ARM_tUXTH, ARM_INS_UXTH: uxth${p} $rd, $rm */ - { CS_AC_WRITE, CS_AC_READ, 0 } -}, diff --git a/arch/ARM/ARMGenSystemRegister.inc b/arch/ARM/ARMGenSystemRegister.inc index 9cc6e812e..55199ac3e 100644 --- a/arch/ARM/ARMGenSystemRegister.inc +++ b/arch/ARM/ARMGenSystemRegister.inc @@ -165,7 +165,7 @@ MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding) { 0x303, 7 }, }; - i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding); + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else @@ -215,7 +215,7 @@ MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding) { 0x1803, 15 }, }; - i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding); + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else @@ -261,7 +261,7 @@ BankedReg *lookupBankedRegByEncoding(uint8_t encoding) { 0x3E, 32 }, }; - i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding); + i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), encoding); if (i == -1) return NULL; else diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index d99a3462c..02a77fa19 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -515,35 +515,4 @@ void ARM_reg_access(const cs_insn *insn, } #endif -// binary search for encoding in IndexType array -// return -1 if not found, or index if found -unsigned int binsearch_IndexType(const struct IndexType *index, size_t size, uint16_t encoding) -{ - // binary searching since the index is sorted in encoding order - size_t left, right, m; - - right = size - 1; - - if (encoding < index[0].encoding || encoding > index[right].encoding) - // not found - return -1; - - left = 0; - - while(left <= right) { - m = (left + right) / 2; - if (encoding == index[m].encoding) { - return m; - } - - if (encoding < index[m].encoding) - right = m - 1; - else - left = m + 1; - } - - // not found - return -1; -} - #endif diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index 633df873f..3e039c55c 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -29,15 +29,6 @@ void ARM_reg_access(const cs_insn *insn, cs_regs regs_read, uint8_t *regs_read_count, cs_regs regs_write, uint8_t *regs_write_count); -struct IndexType { - uint16_t encoding; - unsigned index; -}; - -// binary search for encoding in IndexType array -// return -1 if not found, or index if found -unsigned int binsearch_IndexType(const struct IndexType *index, size_t size, uint16_t encoding); - typedef struct BankedReg { const char *Name; arm_sysreg sysreg; diff --git a/bindings/java/TestArm64.java b/bindings/java/TestArm64.java index 828442f6f..ce78f5ef5 100644 --- a/bindings/java/TestArm64.java +++ b/bindings/java/TestArm64.java @@ -75,8 +75,6 @@ public class TestArm64 { System.out.printf("\t\t\tExt: %d\n", i.ext); if (i.vas != ARM64_VAS_INVALID) System.out.printf("\t\t\tVector Arrangement Specifier: 0x%x\n", i.vas); - if (i.vess != ARM64_VESS_INVALID) - System.out.printf("\t\t\tVector Element Size Specifier: %d\n", i.vess); if (i.vector_index != -1) System.out.printf("\t\t\tVector Index: %d\n", i.vector_index); diff --git a/bindings/java/capstone/Arm64.java b/bindings/java/capstone/Arm64.java index 258e1b54a..fdc1f2bc5 100644 --- a/bindings/java/capstone/Arm64.java +++ b/bindings/java/capstone/Arm64.java @@ -53,7 +53,6 @@ public class Arm64 { public static class Operand extends Structure { public int vector_index; public int vas; - public int vess; public OpShift shift; public int ext; public int type; @@ -72,14 +71,13 @@ public class Arm64 { readField("value"); readField("ext"); readField("shift"); - readField("vess"); readField("vas"); readField("vector_index"); } @Override public List getFieldOrder() { - return Arrays.asList("vector_index", "vas", "vess", "shift", "ext", "type", "value"); + return Arrays.asList("vector_index", "vas", "shift", "ext", "type", "value"); } } diff --git a/bindings/java/capstone/Arm64_const.java b/bindings/java/capstone/Arm64_const.java index 54c688467..3048c4398 100644 --- a/bindings/java/capstone/Arm64_const.java +++ b/bindings/java/capstone/Arm64_const.java @@ -42,95 +42,740 @@ public class Arm64_const { public static final int ARM64_SYSREG_MDCCSR_EL0 = 0x9808; public static final int ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828; public static final int ARM64_SYSREG_MDRAR_EL1 = 0x8080; - public static final int ARM64_SYSREG_OSLSR_EL1 = 0x808c; - public static final int ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6; - public static final int ARM64_SYSREG_PMCEID0_EL0 = 0xdce6; - public static final int ARM64_SYSREG_PMCEID1_EL0 = 0xdce7; - public static final int ARM64_SYSREG_MIDR_EL1 = 0xc000; - public static final int ARM64_SYSREG_CCSIDR_EL1 = 0xc800; - public static final int ARM64_SYSREG_CLIDR_EL1 = 0xc801; - public static final int ARM64_SYSREG_CTR_EL0 = 0xd801; - public static final int ARM64_SYSREG_MPIDR_EL1 = 0xc005; - public static final int ARM64_SYSREG_REVIDR_EL1 = 0xc006; - public static final int ARM64_SYSREG_AIDR_EL1 = 0xc807; - public static final int ARM64_SYSREG_DCZID_EL0 = 0xd807; - public static final int ARM64_SYSREG_ID_PFR0_EL1 = 0xc008; - public static final int ARM64_SYSREG_ID_PFR1_EL1 = 0xc009; - public static final int ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a; - public static final int ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b; - public static final int ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c; - public static final int ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d; - public static final int ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e; - public static final int ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f; - public static final int ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010; - public static final int ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011; - public static final int ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012; - public static final int ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013; - public static final int ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014; - public static final int ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015; - public static final int ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020; - public static final int ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021; - public static final int ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028; - public static final int ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029; - public static final int ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c; - public static final int ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d; - public static final int ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030; - public static final int ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031; - public static final int ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038; - public static final int ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039; - public static final int ARM64_SYSREG_MVFR0_EL1 = 0xc018; - public static final int ARM64_SYSREG_MVFR1_EL1 = 0xc019; - public static final int ARM64_SYSREG_MVFR2_EL1 = 0xc01a; - public static final int ARM64_SYSREG_RVBAR_EL1 = 0xc601; - public static final int ARM64_SYSREG_RVBAR_EL2 = 0xe601; - public static final int ARM64_SYSREG_RVBAR_EL3 = 0xf601; - public static final int ARM64_SYSREG_ISR_EL1 = 0xc608; - public static final int ARM64_SYSREG_CNTPCT_EL0 = 0xdf01; - public static final int ARM64_SYSREG_CNTVCT_EL0 = 0xdf02; + public static final int ARM64_SYSREG_OSLSR_EL1 = 0x808C; + public static final int ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6; + public static final int ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6; + public static final int ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7; + public static final int ARM64_SYSREG_MIDR_EL1 = 0xC000; + public static final int ARM64_SYSREG_CCSIDR_EL1 = 0xC800; + public static final int ARM64_SYSREG_CCSIDR2_EL1 = 0xC802; + public static final int ARM64_SYSREG_CLIDR_EL1 = 0xC801; + public static final int ARM64_SYSREG_CTR_EL0 = 0xD801; + public static final int ARM64_SYSREG_MPIDR_EL1 = 0xC005; + public static final int ARM64_SYSREG_REVIDR_EL1 = 0xC006; + public static final int ARM64_SYSREG_AIDR_EL1 = 0xC807; + public static final int ARM64_SYSREG_DCZID_EL0 = 0xD807; + public static final int ARM64_SYSREG_ID_PFR0_EL1 = 0xC008; + public static final int ARM64_SYSREG_ID_PFR1_EL1 = 0xC009; + public static final int ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A; + public static final int ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B; + public static final int ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C; + public static final int ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D; + public static final int ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E; + public static final int ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F; + public static final int ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010; + public static final int ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011; + public static final int ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012; + public static final int ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013; + public static final int ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014; + public static final int ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015; + public static final int ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017; + public static final int ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020; + public static final int ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021; + public static final int ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028; + public static final int ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029; + public static final int ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C; + public static final int ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D; + public static final int ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030; + public static final int ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031; + public static final int ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038; + public static final int ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039; + public static final int ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A; + public static final int ARM64_SYSREG_MVFR0_EL1 = 0xC018; + public static final int ARM64_SYSREG_MVFR1_EL1 = 0xC019; + public static final int ARM64_SYSREG_MVFR2_EL1 = 0xC01A; + public static final int ARM64_SYSREG_RVBAR_EL1 = 0xC601; + public static final int ARM64_SYSREG_RVBAR_EL2 = 0xE601; + public static final int ARM64_SYSREG_RVBAR_EL3 = 0xF601; + public static final int ARM64_SYSREG_ISR_EL1 = 0xC608; + public static final int ARM64_SYSREG_CNTPCT_EL0 = 0xDF01; + public static final int ARM64_SYSREG_CNTVCT_EL0 = 0xDF02; + public static final int ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016; public static final int ARM64_SYSREG_TRCSTATR = 0x8818; public static final int ARM64_SYSREG_TRCIDR8 = 0x8806; - public static final int ARM64_SYSREG_TRCIDR9 = 0x880e; + public static final int ARM64_SYSREG_TRCIDR9 = 0x880E; public static final int ARM64_SYSREG_TRCIDR10 = 0x8816; - public static final int ARM64_SYSREG_TRCIDR11 = 0x881e; + public static final int ARM64_SYSREG_TRCIDR11 = 0x881E; public static final int ARM64_SYSREG_TRCIDR12 = 0x8826; - public static final int ARM64_SYSREG_TRCIDR13 = 0x882e; + public static final int ARM64_SYSREG_TRCIDR13 = 0x882E; public static final int ARM64_SYSREG_TRCIDR0 = 0x8847; - public static final int ARM64_SYSREG_TRCIDR1 = 0x884f; + public static final int ARM64_SYSREG_TRCIDR1 = 0x884F; public static final int ARM64_SYSREG_TRCIDR2 = 0x8857; - public static final int ARM64_SYSREG_TRCIDR3 = 0x885f; + public static final int ARM64_SYSREG_TRCIDR3 = 0x885F; public static final int ARM64_SYSREG_TRCIDR4 = 0x8867; - public static final int ARM64_SYSREG_TRCIDR5 = 0x886f; + public static final int ARM64_SYSREG_TRCIDR5 = 0x886F; public static final int ARM64_SYSREG_TRCIDR6 = 0x8877; - public static final int ARM64_SYSREG_TRCIDR7 = 0x887f; - public static final int ARM64_SYSREG_TRCOSLSR = 0x888c; - public static final int ARM64_SYSREG_TRCPDSR = 0x88ac; - public static final int ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6; - public static final int ARM64_SYSREG_TRCDEVAFF1 = 0x8bde; - public static final int ARM64_SYSREG_TRCLSR = 0x8bee; - public static final int ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6; - public static final int ARM64_SYSREG_TRCDEVARCH = 0x8bfe; - public static final int ARM64_SYSREG_TRCDEVID = 0x8b97; - public static final int ARM64_SYSREG_TRCDEVTYPE = 0x8b9f; - public static final int ARM64_SYSREG_TRCPIDR4 = 0x8ba7; - public static final int ARM64_SYSREG_TRCPIDR5 = 0x8baf; - public static final int ARM64_SYSREG_TRCPIDR6 = 0x8bb7; - public static final int ARM64_SYSREG_TRCPIDR7 = 0x8bbf; - public static final int ARM64_SYSREG_TRCPIDR0 = 0x8bc7; - public static final int ARM64_SYSREG_TRCPIDR1 = 0x8bcf; - public static final int ARM64_SYSREG_TRCPIDR2 = 0x8bd7; - public static final int ARM64_SYSREG_TRCPIDR3 = 0x8bdf; - public static final int ARM64_SYSREG_TRCCIDR0 = 0x8be7; - public static final int ARM64_SYSREG_TRCCIDR1 = 0x8bef; - public static final int ARM64_SYSREG_TRCCIDR2 = 0x8bf7; - public static final int ARM64_SYSREG_TRCCIDR3 = 0x8bff; - public static final int ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660; - public static final int ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640; - public static final int ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662; - public static final int ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642; - public static final int ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b; - public static final int ARM64_SYSREG_ICH_VTR_EL2 = 0xe659; - public static final int ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b; - public static final int ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d; + public static final int ARM64_SYSREG_TRCIDR7 = 0x887F; + public static final int ARM64_SYSREG_TRCOSLSR = 0x888C; + public static final int ARM64_SYSREG_TRCPDSR = 0x88AC; + public static final int ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6; + public static final int ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE; + public static final int ARM64_SYSREG_TRCLSR = 0x8BEE; + public static final int ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6; + public static final int ARM64_SYSREG_TRCDEVARCH = 0x8BFE; + public static final int ARM64_SYSREG_TRCDEVID = 0x8B97; + public static final int ARM64_SYSREG_TRCDEVTYPE = 0x8B9F; + public static final int ARM64_SYSREG_TRCPIDR4 = 0x8BA7; + public static final int ARM64_SYSREG_TRCPIDR5 = 0x8BAF; + public static final int ARM64_SYSREG_TRCPIDR6 = 0x8BB7; + public static final int ARM64_SYSREG_TRCPIDR7 = 0x8BBF; + public static final int ARM64_SYSREG_TRCPIDR0 = 0x8BC7; + public static final int ARM64_SYSREG_TRCPIDR1 = 0x8BCF; + public static final int ARM64_SYSREG_TRCPIDR2 = 0x8BD7; + public static final int ARM64_SYSREG_TRCPIDR3 = 0x8BDF; + public static final int ARM64_SYSREG_TRCCIDR0 = 0x8BE7; + public static final int ARM64_SYSREG_TRCCIDR1 = 0x8BEF; + public static final int ARM64_SYSREG_TRCCIDR2 = 0x8BF7; + public static final int ARM64_SYSREG_TRCCIDR3 = 0x8BFF; + public static final int ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660; + public static final int ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640; + public static final int ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662; + public static final int ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642; + public static final int ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B; + public static final int ARM64_SYSREG_ICH_VTR_EL2 = 0xE659; + public static final int ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B; + public static final int ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D; + public static final int ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024; + public static final int ARM64_SYSREG_LORID_EL1 = 0xC527; + public static final int ARM64_SYSREG_ERRIDR_EL1 = 0xC298; + public static final int ARM64_SYSREG_ERXFR_EL1 = 0xC2A0; + public static final int ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828; + public static final int ARM64_SYSREG_OSLAR_EL1 = 0x8084; + public static final int ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4; + public static final int ARM64_SYSREG_TRCOSLAR = 0x8884; + public static final int ARM64_SYSREG_TRCLAR = 0x8BE6; + public static final int ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661; + public static final int ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641; + public static final int ARM64_SYSREG_ICC_DIR_EL1 = 0xC659; + public static final int ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D; + public static final int ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E; + public static final int ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F; + public static final int ARM64_SYSREG_OSDTRRX_EL1 = 0x8002; + public static final int ARM64_SYSREG_OSDTRTX_EL1 = 0x801A; + public static final int ARM64_SYSREG_TEECR32_EL1 = 0x9000; + public static final int ARM64_SYSREG_MDCCINT_EL1 = 0x8010; + public static final int ARM64_SYSREG_MDSCR_EL1 = 0x8012; + public static final int ARM64_SYSREG_DBGDTR_EL0 = 0x9820; + public static final int ARM64_SYSREG_OSECCR_EL1 = 0x8032; + public static final int ARM64_SYSREG_DBGVCR32_EL2 = 0xA038; + public static final int ARM64_SYSREG_DBGBVR0_EL1 = 0x8004; + public static final int ARM64_SYSREG_DBGBVR1_EL1 = 0x800C; + public static final int ARM64_SYSREG_DBGBVR2_EL1 = 0x8014; + public static final int ARM64_SYSREG_DBGBVR3_EL1 = 0x801C; + public static final int ARM64_SYSREG_DBGBVR4_EL1 = 0x8024; + public static final int ARM64_SYSREG_DBGBVR5_EL1 = 0x802C; + public static final int ARM64_SYSREG_DBGBVR6_EL1 = 0x8034; + public static final int ARM64_SYSREG_DBGBVR7_EL1 = 0x803C; + public static final int ARM64_SYSREG_DBGBVR8_EL1 = 0x8044; + public static final int ARM64_SYSREG_DBGBVR9_EL1 = 0x804C; + public static final int ARM64_SYSREG_DBGBVR10_EL1 = 0x8054; + public static final int ARM64_SYSREG_DBGBVR11_EL1 = 0x805C; + public static final int ARM64_SYSREG_DBGBVR12_EL1 = 0x8064; + public static final int ARM64_SYSREG_DBGBVR13_EL1 = 0x806C; + public static final int ARM64_SYSREG_DBGBVR14_EL1 = 0x8074; + public static final int ARM64_SYSREG_DBGBVR15_EL1 = 0x807C; + public static final int ARM64_SYSREG_DBGBCR0_EL1 = 0x8005; + public static final int ARM64_SYSREG_DBGBCR1_EL1 = 0x800D; + public static final int ARM64_SYSREG_DBGBCR2_EL1 = 0x8015; + public static final int ARM64_SYSREG_DBGBCR3_EL1 = 0x801D; + public static final int ARM64_SYSREG_DBGBCR4_EL1 = 0x8025; + public static final int ARM64_SYSREG_DBGBCR5_EL1 = 0x802D; + public static final int ARM64_SYSREG_DBGBCR6_EL1 = 0x8035; + public static final int ARM64_SYSREG_DBGBCR7_EL1 = 0x803D; + public static final int ARM64_SYSREG_DBGBCR8_EL1 = 0x8045; + public static final int ARM64_SYSREG_DBGBCR9_EL1 = 0x804D; + public static final int ARM64_SYSREG_DBGBCR10_EL1 = 0x8055; + public static final int ARM64_SYSREG_DBGBCR11_EL1 = 0x805D; + public static final int ARM64_SYSREG_DBGBCR12_EL1 = 0x8065; + public static final int ARM64_SYSREG_DBGBCR13_EL1 = 0x806D; + public static final int ARM64_SYSREG_DBGBCR14_EL1 = 0x8075; + public static final int ARM64_SYSREG_DBGBCR15_EL1 = 0x807D; + public static final int ARM64_SYSREG_DBGWVR0_EL1 = 0x8006; + public static final int ARM64_SYSREG_DBGWVR1_EL1 = 0x800E; + public static final int ARM64_SYSREG_DBGWVR2_EL1 = 0x8016; + public static final int ARM64_SYSREG_DBGWVR3_EL1 = 0x801E; + public static final int ARM64_SYSREG_DBGWVR4_EL1 = 0x8026; + public static final int ARM64_SYSREG_DBGWVR5_EL1 = 0x802E; + public static final int ARM64_SYSREG_DBGWVR6_EL1 = 0x8036; + public static final int ARM64_SYSREG_DBGWVR7_EL1 = 0x803E; + public static final int ARM64_SYSREG_DBGWVR8_EL1 = 0x8046; + public static final int ARM64_SYSREG_DBGWVR9_EL1 = 0x804E; + public static final int ARM64_SYSREG_DBGWVR10_EL1 = 0x8056; + public static final int ARM64_SYSREG_DBGWVR11_EL1 = 0x805E; + public static final int ARM64_SYSREG_DBGWVR12_EL1 = 0x8066; + public static final int ARM64_SYSREG_DBGWVR13_EL1 = 0x806E; + public static final int ARM64_SYSREG_DBGWVR14_EL1 = 0x8076; + public static final int ARM64_SYSREG_DBGWVR15_EL1 = 0x807E; + public static final int ARM64_SYSREG_DBGWCR0_EL1 = 0x8007; + public static final int ARM64_SYSREG_DBGWCR1_EL1 = 0x800F; + public static final int ARM64_SYSREG_DBGWCR2_EL1 = 0x8017; + public static final int ARM64_SYSREG_DBGWCR3_EL1 = 0x801F; + public static final int ARM64_SYSREG_DBGWCR4_EL1 = 0x8027; + public static final int ARM64_SYSREG_DBGWCR5_EL1 = 0x802F; + public static final int ARM64_SYSREG_DBGWCR6_EL1 = 0x8037; + public static final int ARM64_SYSREG_DBGWCR7_EL1 = 0x803F; + public static final int ARM64_SYSREG_DBGWCR8_EL1 = 0x8047; + public static final int ARM64_SYSREG_DBGWCR9_EL1 = 0x804F; + public static final int ARM64_SYSREG_DBGWCR10_EL1 = 0x8057; + public static final int ARM64_SYSREG_DBGWCR11_EL1 = 0x805F; + public static final int ARM64_SYSREG_DBGWCR12_EL1 = 0x8067; + public static final int ARM64_SYSREG_DBGWCR13_EL1 = 0x806F; + public static final int ARM64_SYSREG_DBGWCR14_EL1 = 0x8077; + public static final int ARM64_SYSREG_DBGWCR15_EL1 = 0x807F; + public static final int ARM64_SYSREG_TEEHBR32_EL1 = 0x9080; + public static final int ARM64_SYSREG_OSDLR_EL1 = 0x809C; + public static final int ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4; + public static final int ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6; + public static final int ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE; + public static final int ARM64_SYSREG_CSSELR_EL1 = 0xD000; + public static final int ARM64_SYSREG_VPIDR_EL2 = 0xE000; + public static final int ARM64_SYSREG_VMPIDR_EL2 = 0xE005; + public static final int ARM64_SYSREG_CPACR_EL1 = 0xC082; + public static final int ARM64_SYSREG_SCTLR_EL1 = 0xC080; + public static final int ARM64_SYSREG_SCTLR_EL2 = 0xE080; + public static final int ARM64_SYSREG_SCTLR_EL3 = 0xF080; + public static final int ARM64_SYSREG_ACTLR_EL1 = 0xC081; + public static final int ARM64_SYSREG_ACTLR_EL2 = 0xE081; + public static final int ARM64_SYSREG_ACTLR_EL3 = 0xF081; + public static final int ARM64_SYSREG_HCR_EL2 = 0xE088; + public static final int ARM64_SYSREG_SCR_EL3 = 0xF088; + public static final int ARM64_SYSREG_MDCR_EL2 = 0xE089; + public static final int ARM64_SYSREG_SDER32_EL3 = 0xF089; + public static final int ARM64_SYSREG_CPTR_EL2 = 0xE08A; + public static final int ARM64_SYSREG_CPTR_EL3 = 0xF08A; + public static final int ARM64_SYSREG_HSTR_EL2 = 0xE08B; + public static final int ARM64_SYSREG_HACR_EL2 = 0xE08F; + public static final int ARM64_SYSREG_MDCR_EL3 = 0xF099; + public static final int ARM64_SYSREG_TTBR0_EL1 = 0xC100; + public static final int ARM64_SYSREG_TTBR0_EL2 = 0xE100; + public static final int ARM64_SYSREG_TTBR0_EL3 = 0xF100; + public static final int ARM64_SYSREG_TTBR1_EL1 = 0xC101; + public static final int ARM64_SYSREG_TCR_EL1 = 0xC102; + public static final int ARM64_SYSREG_TCR_EL2 = 0xE102; + public static final int ARM64_SYSREG_TCR_EL3 = 0xF102; + public static final int ARM64_SYSREG_VTTBR_EL2 = 0xE108; + public static final int ARM64_SYSREG_VTCR_EL2 = 0xE10A; + public static final int ARM64_SYSREG_DACR32_EL2 = 0xE180; + public static final int ARM64_SYSREG_SPSR_EL1 = 0xC200; + public static final int ARM64_SYSREG_SPSR_EL2 = 0xE200; + public static final int ARM64_SYSREG_SPSR_EL3 = 0xF200; + public static final int ARM64_SYSREG_ELR_EL1 = 0xC201; + public static final int ARM64_SYSREG_ELR_EL2 = 0xE201; + public static final int ARM64_SYSREG_ELR_EL3 = 0xF201; + public static final int ARM64_SYSREG_SP_EL0 = 0xC208; + public static final int ARM64_SYSREG_SP_EL1 = 0xE208; + public static final int ARM64_SYSREG_SP_EL2 = 0xF208; + public static final int ARM64_SYSREG_SPSEL = 0xC210; + public static final int ARM64_SYSREG_NZCV = 0xDA10; + public static final int ARM64_SYSREG_DAIF = 0xDA11; + public static final int ARM64_SYSREG_CURRENTEL = 0xC212; + public static final int ARM64_SYSREG_SPSR_IRQ = 0xE218; + public static final int ARM64_SYSREG_SPSR_ABT = 0xE219; + public static final int ARM64_SYSREG_SPSR_UND = 0xE21A; + public static final int ARM64_SYSREG_SPSR_FIQ = 0xE21B; + public static final int ARM64_SYSREG_FPCR = 0xDA20; + public static final int ARM64_SYSREG_FPSR = 0xDA21; + public static final int ARM64_SYSREG_DSPSR_EL0 = 0xDA28; + public static final int ARM64_SYSREG_DLR_EL0 = 0xDA29; + public static final int ARM64_SYSREG_IFSR32_EL2 = 0xE281; + public static final int ARM64_SYSREG_AFSR0_EL1 = 0xC288; + public static final int ARM64_SYSREG_AFSR0_EL2 = 0xE288; + public static final int ARM64_SYSREG_AFSR0_EL3 = 0xF288; + public static final int ARM64_SYSREG_AFSR1_EL1 = 0xC289; + public static final int ARM64_SYSREG_AFSR1_EL2 = 0xE289; + public static final int ARM64_SYSREG_AFSR1_EL3 = 0xF289; + public static final int ARM64_SYSREG_ESR_EL1 = 0xC290; + public static final int ARM64_SYSREG_ESR_EL2 = 0xE290; + public static final int ARM64_SYSREG_ESR_EL3 = 0xF290; + public static final int ARM64_SYSREG_FPEXC32_EL2 = 0xE298; + public static final int ARM64_SYSREG_FAR_EL1 = 0xC300; + public static final int ARM64_SYSREG_FAR_EL2 = 0xE300; + public static final int ARM64_SYSREG_FAR_EL3 = 0xF300; + public static final int ARM64_SYSREG_HPFAR_EL2 = 0xE304; + public static final int ARM64_SYSREG_PAR_EL1 = 0xC3A0; + public static final int ARM64_SYSREG_PMCR_EL0 = 0xDCE0; + public static final int ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1; + public static final int ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2; + public static final int ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3; + public static final int ARM64_SYSREG_PMSELR_EL0 = 0xDCE5; + public static final int ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8; + public static final int ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9; + public static final int ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA; + public static final int ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0; + public static final int ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1; + public static final int ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2; + public static final int ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3; + public static final int ARM64_SYSREG_MAIR_EL1 = 0xC510; + public static final int ARM64_SYSREG_MAIR_EL2 = 0xE510; + public static final int ARM64_SYSREG_MAIR_EL3 = 0xF510; + public static final int ARM64_SYSREG_AMAIR_EL1 = 0xC518; + public static final int ARM64_SYSREG_AMAIR_EL2 = 0xE518; + public static final int ARM64_SYSREG_AMAIR_EL3 = 0xF518; + public static final int ARM64_SYSREG_VBAR_EL1 = 0xC600; + public static final int ARM64_SYSREG_VBAR_EL2 = 0xE600; + public static final int ARM64_SYSREG_VBAR_EL3 = 0xF600; + public static final int ARM64_SYSREG_RMR_EL1 = 0xC602; + public static final int ARM64_SYSREG_RMR_EL2 = 0xE602; + public static final int ARM64_SYSREG_RMR_EL3 = 0xF602; + public static final int ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681; + public static final int ARM64_SYSREG_TPIDR_EL0 = 0xDE82; + public static final int ARM64_SYSREG_TPIDR_EL2 = 0xE682; + public static final int ARM64_SYSREG_TPIDR_EL3 = 0xF682; + public static final int ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83; + public static final int ARM64_SYSREG_TPIDR_EL1 = 0xC684; + public static final int ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00; + public static final int ARM64_SYSREG_CNTVOFF_EL2 = 0xE703; + public static final int ARM64_SYSREG_CNTKCTL_EL1 = 0xC708; + public static final int ARM64_SYSREG_CNTHCTL_EL2 = 0xE708; + public static final int ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10; + public static final int ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710; + public static final int ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10; + public static final int ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11; + public static final int ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711; + public static final int ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11; + public static final int ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12; + public static final int ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712; + public static final int ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12; + public static final int ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18; + public static final int ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19; + public static final int ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A; + public static final int ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40; + public static final int ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41; + public static final int ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42; + public static final int ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43; + public static final int ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44; + public static final int ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45; + public static final int ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46; + public static final int ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47; + public static final int ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48; + public static final int ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49; + public static final int ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A; + public static final int ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B; + public static final int ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C; + public static final int ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D; + public static final int ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E; + public static final int ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F; + public static final int ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50; + public static final int ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51; + public static final int ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52; + public static final int ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53; + public static final int ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54; + public static final int ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55; + public static final int ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56; + public static final int ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57; + public static final int ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58; + public static final int ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59; + public static final int ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A; + public static final int ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B; + public static final int ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C; + public static final int ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D; + public static final int ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E; + public static final int ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F; + public static final int ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60; + public static final int ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61; + public static final int ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62; + public static final int ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63; + public static final int ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64; + public static final int ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65; + public static final int ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66; + public static final int ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67; + public static final int ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68; + public static final int ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69; + public static final int ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A; + public static final int ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B; + public static final int ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C; + public static final int ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D; + public static final int ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E; + public static final int ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F; + public static final int ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70; + public static final int ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71; + public static final int ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72; + public static final int ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73; + public static final int ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74; + public static final int ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75; + public static final int ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76; + public static final int ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77; + public static final int ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78; + public static final int ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79; + public static final int ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A; + public static final int ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B; + public static final int ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C; + public static final int ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D; + public static final int ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E; + public static final int ARM64_SYSREG_TRCPRGCTLR = 0x8808; + public static final int ARM64_SYSREG_TRCPROCSELR = 0x8810; + public static final int ARM64_SYSREG_TRCCONFIGR = 0x8820; + public static final int ARM64_SYSREG_TRCAUXCTLR = 0x8830; + public static final int ARM64_SYSREG_TRCEVENTCTL0R = 0x8840; + public static final int ARM64_SYSREG_TRCEVENTCTL1R = 0x8848; + public static final int ARM64_SYSREG_TRCSTALLCTLR = 0x8858; + public static final int ARM64_SYSREG_TRCTSCTLR = 0x8860; + public static final int ARM64_SYSREG_TRCSYNCPR = 0x8868; + public static final int ARM64_SYSREG_TRCCCCTLR = 0x8870; + public static final int ARM64_SYSREG_TRCBBCTLR = 0x8878; + public static final int ARM64_SYSREG_TRCTRACEIDR = 0x8801; + public static final int ARM64_SYSREG_TRCQCTLR = 0x8809; + public static final int ARM64_SYSREG_TRCVICTLR = 0x8802; + public static final int ARM64_SYSREG_TRCVIIECTLR = 0x880A; + public static final int ARM64_SYSREG_TRCVISSCTLR = 0x8812; + public static final int ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A; + public static final int ARM64_SYSREG_TRCVDCTLR = 0x8842; + public static final int ARM64_SYSREG_TRCVDSACCTLR = 0x884A; + public static final int ARM64_SYSREG_TRCVDARCCTLR = 0x8852; + public static final int ARM64_SYSREG_TRCSEQEVR0 = 0x8804; + public static final int ARM64_SYSREG_TRCSEQEVR1 = 0x880C; + public static final int ARM64_SYSREG_TRCSEQEVR2 = 0x8814; + public static final int ARM64_SYSREG_TRCSEQRSTEVR = 0x8834; + public static final int ARM64_SYSREG_TRCSEQSTR = 0x883C; + public static final int ARM64_SYSREG_TRCEXTINSELR = 0x8844; + public static final int ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805; + public static final int ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D; + public static final int ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815; + public static final int ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D; + public static final int ARM64_SYSREG_TRCCNTCTLR0 = 0x8825; + public static final int ARM64_SYSREG_TRCCNTCTLR1 = 0x882D; + public static final int ARM64_SYSREG_TRCCNTCTLR2 = 0x8835; + public static final int ARM64_SYSREG_TRCCNTCTLR3 = 0x883D; + public static final int ARM64_SYSREG_TRCCNTVR0 = 0x8845; + public static final int ARM64_SYSREG_TRCCNTVR1 = 0x884D; + public static final int ARM64_SYSREG_TRCCNTVR2 = 0x8855; + public static final int ARM64_SYSREG_TRCCNTVR3 = 0x885D; + public static final int ARM64_SYSREG_TRCIMSPEC0 = 0x8807; + public static final int ARM64_SYSREG_TRCIMSPEC1 = 0x880F; + public static final int ARM64_SYSREG_TRCIMSPEC2 = 0x8817; + public static final int ARM64_SYSREG_TRCIMSPEC3 = 0x881F; + public static final int ARM64_SYSREG_TRCIMSPEC4 = 0x8827; + public static final int ARM64_SYSREG_TRCIMSPEC5 = 0x882F; + public static final int ARM64_SYSREG_TRCIMSPEC6 = 0x8837; + public static final int ARM64_SYSREG_TRCIMSPEC7 = 0x883F; + public static final int ARM64_SYSREG_TRCRSCTLR2 = 0x8890; + public static final int ARM64_SYSREG_TRCRSCTLR3 = 0x8898; + public static final int ARM64_SYSREG_TRCRSCTLR4 = 0x88A0; + public static final int ARM64_SYSREG_TRCRSCTLR5 = 0x88A8; + public static final int ARM64_SYSREG_TRCRSCTLR6 = 0x88B0; + public static final int ARM64_SYSREG_TRCRSCTLR7 = 0x88B8; + public static final int ARM64_SYSREG_TRCRSCTLR8 = 0x88C0; + public static final int ARM64_SYSREG_TRCRSCTLR9 = 0x88C8; + public static final int ARM64_SYSREG_TRCRSCTLR10 = 0x88D0; + public static final int ARM64_SYSREG_TRCRSCTLR11 = 0x88D8; + public static final int ARM64_SYSREG_TRCRSCTLR12 = 0x88E0; + public static final int ARM64_SYSREG_TRCRSCTLR13 = 0x88E8; + public static final int ARM64_SYSREG_TRCRSCTLR14 = 0x88F0; + public static final int ARM64_SYSREG_TRCRSCTLR15 = 0x88F8; + public static final int ARM64_SYSREG_TRCRSCTLR16 = 0x8881; + public static final int ARM64_SYSREG_TRCRSCTLR17 = 0x8889; + public static final int ARM64_SYSREG_TRCRSCTLR18 = 0x8891; + public static final int ARM64_SYSREG_TRCRSCTLR19 = 0x8899; + public static final int ARM64_SYSREG_TRCRSCTLR20 = 0x88A1; + public static final int ARM64_SYSREG_TRCRSCTLR21 = 0x88A9; + public static final int ARM64_SYSREG_TRCRSCTLR22 = 0x88B1; + public static final int ARM64_SYSREG_TRCRSCTLR23 = 0x88B9; + public static final int ARM64_SYSREG_TRCRSCTLR24 = 0x88C1; + public static final int ARM64_SYSREG_TRCRSCTLR25 = 0x88C9; + public static final int ARM64_SYSREG_TRCRSCTLR26 = 0x88D1; + public static final int ARM64_SYSREG_TRCRSCTLR27 = 0x88D9; + public static final int ARM64_SYSREG_TRCRSCTLR28 = 0x88E1; + public static final int ARM64_SYSREG_TRCRSCTLR29 = 0x88E9; + public static final int ARM64_SYSREG_TRCRSCTLR30 = 0x88F1; + public static final int ARM64_SYSREG_TRCRSCTLR31 = 0x88F9; + public static final int ARM64_SYSREG_TRCSSCCR0 = 0x8882; + public static final int ARM64_SYSREG_TRCSSCCR1 = 0x888A; + public static final int ARM64_SYSREG_TRCSSCCR2 = 0x8892; + public static final int ARM64_SYSREG_TRCSSCCR3 = 0x889A; + public static final int ARM64_SYSREG_TRCSSCCR4 = 0x88A2; + public static final int ARM64_SYSREG_TRCSSCCR5 = 0x88AA; + public static final int ARM64_SYSREG_TRCSSCCR6 = 0x88B2; + public static final int ARM64_SYSREG_TRCSSCCR7 = 0x88BA; + public static final int ARM64_SYSREG_TRCSSCSR0 = 0x88C2; + public static final int ARM64_SYSREG_TRCSSCSR1 = 0x88CA; + public static final int ARM64_SYSREG_TRCSSCSR2 = 0x88D2; + public static final int ARM64_SYSREG_TRCSSCSR3 = 0x88DA; + public static final int ARM64_SYSREG_TRCSSCSR4 = 0x88E2; + public static final int ARM64_SYSREG_TRCSSCSR5 = 0x88EA; + public static final int ARM64_SYSREG_TRCSSCSR6 = 0x88F2; + public static final int ARM64_SYSREG_TRCSSCSR7 = 0x88FA; + public static final int ARM64_SYSREG_TRCSSPCICR0 = 0x8883; + public static final int ARM64_SYSREG_TRCSSPCICR1 = 0x888B; + public static final int ARM64_SYSREG_TRCSSPCICR2 = 0x8893; + public static final int ARM64_SYSREG_TRCSSPCICR3 = 0x889B; + public static final int ARM64_SYSREG_TRCSSPCICR4 = 0x88A3; + public static final int ARM64_SYSREG_TRCSSPCICR5 = 0x88AB; + public static final int ARM64_SYSREG_TRCSSPCICR6 = 0x88B3; + public static final int ARM64_SYSREG_TRCSSPCICR7 = 0x88BB; + public static final int ARM64_SYSREG_TRCPDCR = 0x88A4; + public static final int ARM64_SYSREG_TRCACVR0 = 0x8900; + public static final int ARM64_SYSREG_TRCACVR1 = 0x8910; + public static final int ARM64_SYSREG_TRCACVR2 = 0x8920; + public static final int ARM64_SYSREG_TRCACVR3 = 0x8930; + public static final int ARM64_SYSREG_TRCACVR4 = 0x8940; + public static final int ARM64_SYSREG_TRCACVR5 = 0x8950; + public static final int ARM64_SYSREG_TRCACVR6 = 0x8960; + public static final int ARM64_SYSREG_TRCACVR7 = 0x8970; + public static final int ARM64_SYSREG_TRCACVR8 = 0x8901; + public static final int ARM64_SYSREG_TRCACVR9 = 0x8911; + public static final int ARM64_SYSREG_TRCACVR10 = 0x8921; + public static final int ARM64_SYSREG_TRCACVR11 = 0x8931; + public static final int ARM64_SYSREG_TRCACVR12 = 0x8941; + public static final int ARM64_SYSREG_TRCACVR13 = 0x8951; + public static final int ARM64_SYSREG_TRCACVR14 = 0x8961; + public static final int ARM64_SYSREG_TRCACVR15 = 0x8971; + public static final int ARM64_SYSREG_TRCACATR0 = 0x8902; + public static final int ARM64_SYSREG_TRCACATR1 = 0x8912; + public static final int ARM64_SYSREG_TRCACATR2 = 0x8922; + public static final int ARM64_SYSREG_TRCACATR3 = 0x8932; + public static final int ARM64_SYSREG_TRCACATR4 = 0x8942; + public static final int ARM64_SYSREG_TRCACATR5 = 0x8952; + public static final int ARM64_SYSREG_TRCACATR6 = 0x8962; + public static final int ARM64_SYSREG_TRCACATR7 = 0x8972; + public static final int ARM64_SYSREG_TRCACATR8 = 0x8903; + public static final int ARM64_SYSREG_TRCACATR9 = 0x8913; + public static final int ARM64_SYSREG_TRCACATR10 = 0x8923; + public static final int ARM64_SYSREG_TRCACATR11 = 0x8933; + public static final int ARM64_SYSREG_TRCACATR12 = 0x8943; + public static final int ARM64_SYSREG_TRCACATR13 = 0x8953; + public static final int ARM64_SYSREG_TRCACATR14 = 0x8963; + public static final int ARM64_SYSREG_TRCACATR15 = 0x8973; + public static final int ARM64_SYSREG_TRCDVCVR0 = 0x8904; + public static final int ARM64_SYSREG_TRCDVCVR1 = 0x8924; + public static final int ARM64_SYSREG_TRCDVCVR2 = 0x8944; + public static final int ARM64_SYSREG_TRCDVCVR3 = 0x8964; + public static final int ARM64_SYSREG_TRCDVCVR4 = 0x8905; + public static final int ARM64_SYSREG_TRCDVCVR5 = 0x8925; + public static final int ARM64_SYSREG_TRCDVCVR6 = 0x8945; + public static final int ARM64_SYSREG_TRCDVCVR7 = 0x8965; + public static final int ARM64_SYSREG_TRCDVCMR0 = 0x8906; + public static final int ARM64_SYSREG_TRCDVCMR1 = 0x8926; + public static final int ARM64_SYSREG_TRCDVCMR2 = 0x8946; + public static final int ARM64_SYSREG_TRCDVCMR3 = 0x8966; + public static final int ARM64_SYSREG_TRCDVCMR4 = 0x8907; + public static final int ARM64_SYSREG_TRCDVCMR5 = 0x8927; + public static final int ARM64_SYSREG_TRCDVCMR6 = 0x8947; + public static final int ARM64_SYSREG_TRCDVCMR7 = 0x8967; + public static final int ARM64_SYSREG_TRCCIDCVR0 = 0x8980; + public static final int ARM64_SYSREG_TRCCIDCVR1 = 0x8990; + public static final int ARM64_SYSREG_TRCCIDCVR2 = 0x89A0; + public static final int ARM64_SYSREG_TRCCIDCVR3 = 0x89B0; + public static final int ARM64_SYSREG_TRCCIDCVR4 = 0x89C0; + public static final int ARM64_SYSREG_TRCCIDCVR5 = 0x89D0; + public static final int ARM64_SYSREG_TRCCIDCVR6 = 0x89E0; + public static final int ARM64_SYSREG_TRCCIDCVR7 = 0x89F0; + public static final int ARM64_SYSREG_TRCVMIDCVR0 = 0x8981; + public static final int ARM64_SYSREG_TRCVMIDCVR1 = 0x8991; + public static final int ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1; + public static final int ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1; + public static final int ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1; + public static final int ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1; + public static final int ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1; + public static final int ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1; + public static final int ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982; + public static final int ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A; + public static final int ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992; + public static final int ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A; + public static final int ARM64_SYSREG_TRCITCTRL = 0x8B84; + public static final int ARM64_SYSREG_TRCCLAIMSET = 0x8BC6; + public static final int ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE; + public static final int ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663; + public static final int ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643; + public static final int ARM64_SYSREG_ICC_PMR_EL1 = 0xC230; + public static final int ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664; + public static final int ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664; + public static final int ARM64_SYSREG_ICC_SRE_EL1 = 0xC665; + public static final int ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D; + public static final int ARM64_SYSREG_ICC_SRE_EL3 = 0xF665; + public static final int ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666; + public static final int ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667; + public static final int ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667; + public static final int ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668; + public static final int ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644; + public static final int ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645; + public static final int ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646; + public static final int ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647; + public static final int ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648; + public static final int ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649; + public static final int ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A; + public static final int ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B; + public static final int ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640; + public static final int ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641; + public static final int ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642; + public static final int ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643; + public static final int ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648; + public static final int ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649; + public static final int ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A; + public static final int ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B; + public static final int ARM64_SYSREG_ICH_HCR_EL2 = 0xE658; + public static final int ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A; + public static final int ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F; + public static final int ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C; + public static final int ARM64_SYSREG_ICH_LR0_EL2 = 0xE660; + public static final int ARM64_SYSREG_ICH_LR1_EL2 = 0xE661; + public static final int ARM64_SYSREG_ICH_LR2_EL2 = 0xE662; + public static final int ARM64_SYSREG_ICH_LR3_EL2 = 0xE663; + public static final int ARM64_SYSREG_ICH_LR4_EL2 = 0xE664; + public static final int ARM64_SYSREG_ICH_LR5_EL2 = 0xE665; + public static final int ARM64_SYSREG_ICH_LR6_EL2 = 0xE666; + public static final int ARM64_SYSREG_ICH_LR7_EL2 = 0xE667; + public static final int ARM64_SYSREG_ICH_LR8_EL2 = 0xE668; + public static final int ARM64_SYSREG_ICH_LR9_EL2 = 0xE669; + public static final int ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A; + public static final int ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B; + public static final int ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C; + public static final int ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D; + public static final int ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E; + public static final int ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F; + public static final int ARM64_SYSREG_PAN = 0xC213; + public static final int ARM64_SYSREG_LORSA_EL1 = 0xC520; + public static final int ARM64_SYSREG_LOREA_EL1 = 0xC521; + public static final int ARM64_SYSREG_LORN_EL1 = 0xC522; + public static final int ARM64_SYSREG_LORC_EL1 = 0xC523; + public static final int ARM64_SYSREG_TTBR1_EL2 = 0xE101; + public static final int ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681; + public static final int ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718; + public static final int ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A; + public static final int ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719; + public static final int ARM64_SYSREG_SCTLR_EL12 = 0xE880; + public static final int ARM64_SYSREG_CPACR_EL12 = 0xE882; + public static final int ARM64_SYSREG_TTBR0_EL12 = 0xE900; + public static final int ARM64_SYSREG_TTBR1_EL12 = 0xE901; + public static final int ARM64_SYSREG_TCR_EL12 = 0xE902; + public static final int ARM64_SYSREG_AFSR0_EL12 = 0xEA88; + public static final int ARM64_SYSREG_AFSR1_EL12 = 0xEA89; + public static final int ARM64_SYSREG_ESR_EL12 = 0xEA90; + public static final int ARM64_SYSREG_FAR_EL12 = 0xEB00; + public static final int ARM64_SYSREG_MAIR_EL12 = 0xED10; + public static final int ARM64_SYSREG_AMAIR_EL12 = 0xED18; + public static final int ARM64_SYSREG_VBAR_EL12 = 0xEE00; + public static final int ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81; + public static final int ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08; + public static final int ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10; + public static final int ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11; + public static final int ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12; + public static final int ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18; + public static final int ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19; + public static final int ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A; + public static final int ARM64_SYSREG_SPSR_EL12 = 0xEA00; + public static final int ARM64_SYSREG_ELR_EL12 = 0xEA01; + public static final int ARM64_SYSREG_UAO = 0xC214; + public static final int ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0; + public static final int ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1; + public static final int ARM64_SYSREG_PMBSR_EL1 = 0xC4D3; + public static final int ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7; + public static final int ARM64_SYSREG_PMSCR_EL2 = 0xE4C8; + public static final int ARM64_SYSREG_PMSCR_EL12 = 0xECC8; + public static final int ARM64_SYSREG_PMSCR_EL1 = 0xC4C8; + public static final int ARM64_SYSREG_PMSICR_EL1 = 0xC4CA; + public static final int ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB; + public static final int ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC; + public static final int ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD; + public static final int ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE; + public static final int ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF; + public static final int ARM64_SYSREG_ERRSELR_EL1 = 0xC299; + public static final int ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1; + public static final int ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2; + public static final int ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3; + public static final int ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8; + public static final int ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9; + public static final int ARM64_SYSREG_DISR_EL1 = 0xC609; + public static final int ARM64_SYSREG_VDISR_EL2 = 0xE609; + public static final int ARM64_SYSREG_VSESR_EL2 = 0xE293; + public static final int ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108; + public static final int ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109; + public static final int ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A; + public static final int ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B; + public static final int ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110; + public static final int ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111; + public static final int ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112; + public static final int ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113; + public static final int ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118; + public static final int ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119; + public static final int ARM64_SYSREG_VSTCR_EL2 = 0xE132; + public static final int ARM64_SYSREG_VSTTBR_EL2 = 0xE130; + public static final int ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720; + public static final int ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722; + public static final int ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721; + public static final int ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728; + public static final int ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A; + public static final int ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729; + public static final int ARM64_SYSREG_SDER32_EL2 = 0xE099; + public static final int ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5; + public static final int ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6; + public static final int ARM64_SYSREG_ERXTS_EL1 = 0xC2AF; + public static final int ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA; + public static final int ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB; + public static final int ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4; + public static final int ARM64_SYSREG_MPAM0_EL1 = 0xC529; + public static final int ARM64_SYSREG_MPAM1_EL1 = 0xC528; + public static final int ARM64_SYSREG_MPAM2_EL2 = 0xE528; + public static final int ARM64_SYSREG_MPAM3_EL3 = 0xF528; + public static final int ARM64_SYSREG_MPAM1_EL12 = 0xED28; + public static final int ARM64_SYSREG_MPAMHCR_EL2 = 0xE520; + public static final int ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521; + public static final int ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530; + public static final int ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531; + public static final int ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532; + public static final int ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533; + public static final int ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534; + public static final int ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535; + public static final int ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536; + public static final int ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537; + public static final int ARM64_SYSREG_MPAMIDR_EL1 = 0xC524; + public static final int ARM64_SYSREG_AMCR_EL0 = 0xDE90; + public static final int ARM64_SYSREG_AMCFGR_EL0 = 0xDE91; + public static final int ARM64_SYSREG_AMCGCR_EL0 = 0xDE92; + public static final int ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93; + public static final int ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94; + public static final int ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95; + public static final int ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0; + public static final int ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1; + public static final int ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2; + public static final int ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3; + public static final int ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0; + public static final int ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1; + public static final int ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2; + public static final int ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3; + public static final int ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98; + public static final int ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99; + public static final int ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0; + public static final int ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1; + public static final int ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2; + public static final int ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3; + public static final int ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4; + public static final int ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5; + public static final int ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6; + public static final int ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7; + public static final int ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8; + public static final int ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9; + public static final int ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA; + public static final int ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB; + public static final int ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC; + public static final int ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED; + public static final int ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE; + public static final int ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF; + public static final int ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0; + public static final int ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1; + public static final int ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2; + public static final int ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3; + public static final int ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4; + public static final int ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5; + public static final int ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6; + public static final int ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7; + public static final int ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8; + public static final int ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9; + public static final int ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA; + public static final int ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB; + public static final int ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC; + public static final int ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD; + public static final int ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE; + public static final int ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF; + public static final int ARM64_SYSREG_TRFCR_EL1 = 0xC091; + public static final int ARM64_SYSREG_TRFCR_EL2 = 0xE091; + public static final int ARM64_SYSREG_TRFCR_EL12 = 0xE891; + public static final int ARM64_SYSREG_DIT = 0xDA15; + public static final int ARM64_SYSREG_VNCR_EL2 = 0xE110; + public static final int ARM64_SYSREG_ZCR_EL1 = 0xC090; + public static final int ARM64_SYSREG_ZCR_EL2 = 0xE090; + public static final int ARM64_SYSREG_ZCR_EL3 = 0xF090; + public static final int ARM64_SYSREG_ZCR_EL12 = 0xE890; + public static final int ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90; public static final int ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828; public static final int ARM64_SYSREG_OSLAR_EL1 = 0x8084; public static final int ARM64_SYSREG_PMSWINC_EL0 = 0xdce4; @@ -147,23 +792,25 @@ public class Arm64_const { public static final int ARM64_PSTATE_SPSEL = 0x05; public static final int ARM64_PSTATE_DAIFSET = 0x1e; public static final int ARM64_PSTATE_DAIFCLR = 0x1f; + public static final int ARM64_PSTATE_PAN = 0x4; + public static final int ARM64_PSTATE_UAO = 0x3; + public static final int ARM64_PSTATE_DIT = 0x1a; public static final int ARM64_VAS_INVALID = 0; - public static final int ARM64_VAS_8B = 1; - public static final int ARM64_VAS_16B = 2; - public static final int ARM64_VAS_4H = 3; - public static final int ARM64_VAS_8H = 4; - public static final int ARM64_VAS_2S = 5; - public static final int ARM64_VAS_4S = 6; - public static final int ARM64_VAS_1D = 7; - public static final int ARM64_VAS_2D = 8; - public static final int ARM64_VAS_1Q = 9; - - public static final int ARM64_VESS_INVALID = 0; - public static final int ARM64_VESS_B = 1; - public static final int ARM64_VESS_H = 2; - public static final int ARM64_VESS_S = 3; - public static final int ARM64_VESS_D = 4; + public static final int ARM64_VAS_16B = 1; + public static final int ARM64_VAS_8B = 2; + public static final int ARM64_VAS_4B = 3; + public static final int ARM64_VAS_1B = 4; + public static final int ARM64_VAS_8H = 5; + public static final int ARM64_VAS_4H = 6; + public static final int ARM64_VAS_2H = 7; + public static final int ARM64_VAS_1H = 8; + public static final int ARM64_VAS_4S = 9; + public static final int ARM64_VAS_2S = 10; + public static final int ARM64_VAS_1S = 11; + public static final int ARM64_VAS_2D = 12; + public static final int ARM64_VAS_1D = 13; + public static final int ARM64_VAS_1Q = 14; public static final int ARM64_BARRIER_INVALID = 0; public static final int ARM64_BARRIER_OSHLD = 0x1; @@ -193,50 +840,98 @@ public class Arm64_const { public static final int ARM64_OP_BARRIER = 70; public static final int ARM64_TLBI_INVALID = 0; - public static final int ARM64_TLBI_VMALLE1IS = 1; - public static final int ARM64_TLBI_VAE1IS = 2; - public static final int ARM64_TLBI_ASIDE1IS = 3; - public static final int ARM64_TLBI_VAAE1IS = 4; - public static final int ARM64_TLBI_VALE1IS = 5; - public static final int ARM64_TLBI_VAALE1IS = 6; - public static final int ARM64_TLBI_ALLE2IS = 7; - public static final int ARM64_TLBI_VAE2IS = 8; - public static final int ARM64_TLBI_ALLE1IS = 9; - public static final int ARM64_TLBI_VALE2IS = 10; - public static final int ARM64_TLBI_VMALLS12E1IS = 11; - public static final int ARM64_TLBI_ALLE3IS = 12; - public static final int ARM64_TLBI_VAE3IS = 13; + public static final int ARM64_TLBI_IPAS2E1IS = 1; + public static final int ARM64_TLBI_IPAS2LE1IS = 2; + public static final int ARM64_TLBI_VMALLE1IS = 3; + public static final int ARM64_TLBI_ALLE2IS = 4; + public static final int ARM64_TLBI_ALLE3IS = 5; + public static final int ARM64_TLBI_VAE1IS = 6; + public static final int ARM64_TLBI_VAE2IS = 7; + public static final int ARM64_TLBI_VAE3IS = 8; + public static final int ARM64_TLBI_ASIDE1IS = 9; + public static final int ARM64_TLBI_VAAE1IS = 10; + public static final int ARM64_TLBI_ALLE1IS = 11; + public static final int ARM64_TLBI_VALE1IS = 12; + public static final int ARM64_TLBI_VALE2IS = 13; public static final int ARM64_TLBI_VALE3IS = 14; - public static final int ARM64_TLBI_IPAS2E1IS = 15; - public static final int ARM64_TLBI_IPAS2LE1IS = 16; + public static final int ARM64_TLBI_VMALLS12E1IS = 15; + public static final int ARM64_TLBI_VAALE1IS = 16; public static final int ARM64_TLBI_IPAS2E1 = 17; public static final int ARM64_TLBI_IPAS2LE1 = 18; public static final int ARM64_TLBI_VMALLE1 = 19; - public static final int ARM64_TLBI_VAE1 = 20; - public static final int ARM64_TLBI_ASIDE1 = 21; - public static final int ARM64_TLBI_VAAE1 = 22; - public static final int ARM64_TLBI_VALE1 = 23; - public static final int ARM64_TLBI_VAALE1 = 24; - public static final int ARM64_TLBI_ALLE2 = 25; - public static final int ARM64_TLBI_VAE2 = 26; + public static final int ARM64_TLBI_ALLE2 = 20; + public static final int ARM64_TLBI_ALLE3 = 21; + public static final int ARM64_TLBI_VAE1 = 22; + public static final int ARM64_TLBI_VAE2 = 23; + public static final int ARM64_TLBI_VAE3 = 24; + public static final int ARM64_TLBI_ASIDE1 = 25; + public static final int ARM64_TLBI_VAAE1 = 26; public static final int ARM64_TLBI_ALLE1 = 27; - public static final int ARM64_TLBI_VALE2 = 28; - public static final int ARM64_TLBI_VMALLS12E1 = 29; - public static final int ARM64_TLBI_ALLE3 = 30; - public static final int ARM64_TLBI_VAE3 = 31; - public static final int ARM64_TLBI_VALE3 = 32; - public static final int ARM64_AT_S1E1R = 33; - public static final int ARM64_AT_S1E1W = 34; - public static final int ARM64_AT_S1E0R = 35; - public static final int ARM64_AT_S1E0W = 36; - public static final int ARM64_AT_S1E2R = 37; - public static final int ARM64_AT_S1E2W = 38; - public static final int ARM64_AT_S12E1R = 39; - public static final int ARM64_AT_S12E1W = 40; - public static final int ARM64_AT_S12E0R = 41; - public static final int ARM64_AT_S12E0W = 42; - public static final int ARM64_AT_S1E3R = 43; - public static final int ARM64_AT_S1E3W = 44; + public static final int ARM64_TLBI_VALE1 = 28; + public static final int ARM64_TLBI_VALE2 = 29; + public static final int ARM64_TLBI_VALE3 = 30; + public static final int ARM64_TLBI_VMALLS12E1 = 31; + public static final int ARM64_TLBI_VAALE1 = 32; + public static final int ARM64_TLBI_VMALLE1OS = 33; + public static final int ARM64_TLBI_VAE1OS = 34; + public static final int ARM64_TLBI_ASIDE1OS = 35; + public static final int ARM64_TLBI_VAAE1OS = 36; + public static final int ARM64_TLBI_VALE1OS = 37; + public static final int ARM64_TLBI_VAALE1OS = 38; + public static final int ARM64_TLBI_IPAS2E1OS = 39; + public static final int ARM64_TLBI_IPAS2LE1OS = 40; + public static final int ARM64_TLBI_VAE2OS = 41; + public static final int ARM64_TLBI_VALE2OS = 42; + public static final int ARM64_TLBI_VMALLS12E1OS = 43; + public static final int ARM64_TLBI_VAE3OS = 44; + public static final int ARM64_TLBI_VALE3OS = 45; + public static final int ARM64_TLBI_ALLE2OS = 46; + public static final int ARM64_TLBI_ALLE1OS = 47; + public static final int ARM64_TLBI_ALLE3OS = 48; + public static final int ARM64_TLBI_RVAE1 = 49; + public static final int ARM64_TLBI_RVAAE1 = 50; + public static final int ARM64_TLBI_RVALE1 = 51; + public static final int ARM64_TLBI_RVAALE1 = 52; + public static final int ARM64_TLBI_RVAE1IS = 53; + public static final int ARM64_TLBI_RVAAE1IS = 54; + public static final int ARM64_TLBI_RVALE1IS = 55; + public static final int ARM64_TLBI_RVAALE1IS = 56; + public static final int ARM64_TLBI_RVAE1OS = 57; + public static final int ARM64_TLBI_RVAAE1OS = 58; + public static final int ARM64_TLBI_RVALE1OS = 59; + public static final int ARM64_TLBI_RVAALE1OS = 60; + public static final int ARM64_TLBI_RIPAS2E1IS = 61; + public static final int ARM64_TLBI_RIPAS2LE1IS = 62; + public static final int ARM64_TLBI_RIPAS2E1 = 63; + public static final int ARM64_TLBI_RIPAS2LE1 = 64; + public static final int ARM64_TLBI_RIPAS2E1OS = 65; + public static final int ARM64_TLBI_RIPAS2LE1OS = 66; + public static final int ARM64_TLBI_RVAE2 = 67; + public static final int ARM64_TLBI_RVALE2 = 68; + public static final int ARM64_TLBI_RVAE2IS = 69; + public static final int ARM64_TLBI_RVALE2IS = 70; + public static final int ARM64_TLBI_RVAE2OS = 71; + public static final int ARM64_TLBI_RVALE2OS = 72; + public static final int ARM64_TLBI_RVAE3 = 73; + public static final int ARM64_TLBI_RVALE3 = 74; + public static final int ARM64_TLBI_RVAE3IS = 75; + public static final int ARM64_TLBI_RVALE3IS = 76; + public static final int ARM64_TLBI_RVAE3OS = 77; + public static final int ARM64_TLBI_RVALE3OS = 78; + public static final int ARM64_AT_S1E1R = 79; + public static final int ARM64_AT_S1E2R = 80; + public static final int ARM64_AT_S1E3R = 81; + public static final int ARM64_AT_S1E1W = 82; + public static final int ARM64_AT_S1E2W = 83; + public static final int ARM64_AT_S1E3W = 84; + public static final int ARM64_AT_S1E0R = 85; + public static final int ARM64_AT_S1E0W = 86; + public static final int ARM64_AT_S12E1R = 87; + public static final int ARM64_AT_S12E1W = 88; + public static final int ARM64_AT_S12E0R = 89; + public static final int ARM64_AT_S12E0W = 90; + public static final int ARM64_AT_S1E1RP = 91; + public static final int ARM64_AT_S1E1WP = 92; public static final int ARM64_DC_INVALID = 0; public static final int ARM64_DC_ZVA = 1; @@ -247,6 +942,7 @@ public class Arm64_const { public static final int ARM64_DC_CVAU = 6; public static final int ARM64_DC_CIVAC = 7; public static final int ARM64_DC_CISW = 8; + public static final int ARM64_DC_CVAP = 9; public static final int ARM64_IC_INVALID = 0; public static final int ARM64_IC_IALLUIS = 1; @@ -274,726 +970,1271 @@ public class Arm64_const { public static final int ARM64_PRFM_PSTL3STRM = 0x15+1; public static final int ARM64_REG_INVALID = 0; - public static final int ARM64_REG_X29 = 1; - public static final int ARM64_REG_X30 = 2; - public static final int ARM64_REG_NZCV = 3; - public static final int ARM64_REG_SP = 4; - public static final int ARM64_REG_WSP = 5; - public static final int ARM64_REG_WZR = 6; - public static final int ARM64_REG_XZR = 7; - public static final int ARM64_REG_B0 = 8; - public static final int ARM64_REG_B1 = 9; - public static final int ARM64_REG_B2 = 10; - public static final int ARM64_REG_B3 = 11; - public static final int ARM64_REG_B4 = 12; - public static final int ARM64_REG_B5 = 13; - public static final int ARM64_REG_B6 = 14; - public static final int ARM64_REG_B7 = 15; - public static final int ARM64_REG_B8 = 16; - public static final int ARM64_REG_B9 = 17; - public static final int ARM64_REG_B10 = 18; - public static final int ARM64_REG_B11 = 19; - public static final int ARM64_REG_B12 = 20; - public static final int ARM64_REG_B13 = 21; - public static final int ARM64_REG_B14 = 22; - public static final int ARM64_REG_B15 = 23; - public static final int ARM64_REG_B16 = 24; - public static final int ARM64_REG_B17 = 25; - public static final int ARM64_REG_B18 = 26; - public static final int ARM64_REG_B19 = 27; - public static final int ARM64_REG_B20 = 28; - public static final int ARM64_REG_B21 = 29; - public static final int ARM64_REG_B22 = 30; - public static final int ARM64_REG_B23 = 31; - public static final int ARM64_REG_B24 = 32; - public static final int ARM64_REG_B25 = 33; - public static final int ARM64_REG_B26 = 34; - public static final int ARM64_REG_B27 = 35; - public static final int ARM64_REG_B28 = 36; - public static final int ARM64_REG_B29 = 37; - public static final int ARM64_REG_B30 = 38; - public static final int ARM64_REG_B31 = 39; - public static final int ARM64_REG_D0 = 40; - public static final int ARM64_REG_D1 = 41; - public static final int ARM64_REG_D2 = 42; - public static final int ARM64_REG_D3 = 43; - public static final int ARM64_REG_D4 = 44; - public static final int ARM64_REG_D5 = 45; - public static final int ARM64_REG_D6 = 46; - public static final int ARM64_REG_D7 = 47; - public static final int ARM64_REG_D8 = 48; - public static final int ARM64_REG_D9 = 49; - public static final int ARM64_REG_D10 = 50; - public static final int ARM64_REG_D11 = 51; - public static final int ARM64_REG_D12 = 52; - public static final int ARM64_REG_D13 = 53; - public static final int ARM64_REG_D14 = 54; - public static final int ARM64_REG_D15 = 55; - public static final int ARM64_REG_D16 = 56; - public static final int ARM64_REG_D17 = 57; - public static final int ARM64_REG_D18 = 58; - public static final int ARM64_REG_D19 = 59; - public static final int ARM64_REG_D20 = 60; - public static final int ARM64_REG_D21 = 61; - public static final int ARM64_REG_D22 = 62; - public static final int ARM64_REG_D23 = 63; - public static final int ARM64_REG_D24 = 64; - public static final int ARM64_REG_D25 = 65; - public static final int ARM64_REG_D26 = 66; - public static final int ARM64_REG_D27 = 67; - public static final int ARM64_REG_D28 = 68; - public static final int ARM64_REG_D29 = 69; - public static final int ARM64_REG_D30 = 70; - public static final int ARM64_REG_D31 = 71; - public static final int ARM64_REG_H0 = 72; - public static final int ARM64_REG_H1 = 73; - public static final int ARM64_REG_H2 = 74; - public static final int ARM64_REG_H3 = 75; - public static final int ARM64_REG_H4 = 76; - public static final int ARM64_REG_H5 = 77; - public static final int ARM64_REG_H6 = 78; - public static final int ARM64_REG_H7 = 79; - public static final int ARM64_REG_H8 = 80; - public static final int ARM64_REG_H9 = 81; - public static final int ARM64_REG_H10 = 82; - public static final int ARM64_REG_H11 = 83; - public static final int ARM64_REG_H12 = 84; - public static final int ARM64_REG_H13 = 85; - public static final int ARM64_REG_H14 = 86; - public static final int ARM64_REG_H15 = 87; - public static final int ARM64_REG_H16 = 88; - public static final int ARM64_REG_H17 = 89; - public static final int ARM64_REG_H18 = 90; - public static final int ARM64_REG_H19 = 91; - public static final int ARM64_REG_H20 = 92; - public static final int ARM64_REG_H21 = 93; - public static final int ARM64_REG_H22 = 94; - public static final int ARM64_REG_H23 = 95; - public static final int ARM64_REG_H24 = 96; - public static final int ARM64_REG_H25 = 97; - public static final int ARM64_REG_H26 = 98; - public static final int ARM64_REG_H27 = 99; - public static final int ARM64_REG_H28 = 100; - public static final int ARM64_REG_H29 = 101; - public static final int ARM64_REG_H30 = 102; - public static final int ARM64_REG_H31 = 103; - public static final int ARM64_REG_Q0 = 104; - public static final int ARM64_REG_Q1 = 105; - public static final int ARM64_REG_Q2 = 106; - public static final int ARM64_REG_Q3 = 107; - public static final int ARM64_REG_Q4 = 108; - public static final int ARM64_REG_Q5 = 109; - public static final int ARM64_REG_Q6 = 110; - public static final int ARM64_REG_Q7 = 111; - public static final int ARM64_REG_Q8 = 112; - public static final int ARM64_REG_Q9 = 113; - public static final int ARM64_REG_Q10 = 114; - public static final int ARM64_REG_Q11 = 115; - public static final int ARM64_REG_Q12 = 116; - public static final int ARM64_REG_Q13 = 117; - public static final int ARM64_REG_Q14 = 118; - public static final int ARM64_REG_Q15 = 119; - public static final int ARM64_REG_Q16 = 120; - public static final int ARM64_REG_Q17 = 121; - public static final int ARM64_REG_Q18 = 122; - public static final int ARM64_REG_Q19 = 123; - public static final int ARM64_REG_Q20 = 124; - public static final int ARM64_REG_Q21 = 125; - public static final int ARM64_REG_Q22 = 126; - public static final int ARM64_REG_Q23 = 127; - public static final int ARM64_REG_Q24 = 128; - public static final int ARM64_REG_Q25 = 129; - public static final int ARM64_REG_Q26 = 130; - public static final int ARM64_REG_Q27 = 131; - public static final int ARM64_REG_Q28 = 132; - public static final int ARM64_REG_Q29 = 133; - public static final int ARM64_REG_Q30 = 134; - public static final int ARM64_REG_Q31 = 135; - public static final int ARM64_REG_S0 = 136; - public static final int ARM64_REG_S1 = 137; - public static final int ARM64_REG_S2 = 138; - public static final int ARM64_REG_S3 = 139; - public static final int ARM64_REG_S4 = 140; - public static final int ARM64_REG_S5 = 141; - public static final int ARM64_REG_S6 = 142; - public static final int ARM64_REG_S7 = 143; - public static final int ARM64_REG_S8 = 144; - public static final int ARM64_REG_S9 = 145; - public static final int ARM64_REG_S10 = 146; - public static final int ARM64_REG_S11 = 147; - public static final int ARM64_REG_S12 = 148; - public static final int ARM64_REG_S13 = 149; - public static final int ARM64_REG_S14 = 150; - public static final int ARM64_REG_S15 = 151; - public static final int ARM64_REG_S16 = 152; - public static final int ARM64_REG_S17 = 153; - public static final int ARM64_REG_S18 = 154; - public static final int ARM64_REG_S19 = 155; - public static final int ARM64_REG_S20 = 156; - public static final int ARM64_REG_S21 = 157; - public static final int ARM64_REG_S22 = 158; - public static final int ARM64_REG_S23 = 159; - public static final int ARM64_REG_S24 = 160; - public static final int ARM64_REG_S25 = 161; - public static final int ARM64_REG_S26 = 162; - public static final int ARM64_REG_S27 = 163; - public static final int ARM64_REG_S28 = 164; - public static final int ARM64_REG_S29 = 165; - public static final int ARM64_REG_S30 = 166; - public static final int ARM64_REG_S31 = 167; - public static final int ARM64_REG_W0 = 168; - public static final int ARM64_REG_W1 = 169; - public static final int ARM64_REG_W2 = 170; - public static final int ARM64_REG_W3 = 171; - public static final int ARM64_REG_W4 = 172; - public static final int ARM64_REG_W5 = 173; - public static final int ARM64_REG_W6 = 174; - public static final int ARM64_REG_W7 = 175; - public static final int ARM64_REG_W8 = 176; - public static final int ARM64_REG_W9 = 177; - public static final int ARM64_REG_W10 = 178; - public static final int ARM64_REG_W11 = 179; - public static final int ARM64_REG_W12 = 180; - public static final int ARM64_REG_W13 = 181; - public static final int ARM64_REG_W14 = 182; - public static final int ARM64_REG_W15 = 183; - public static final int ARM64_REG_W16 = 184; - public static final int ARM64_REG_W17 = 185; - public static final int ARM64_REG_W18 = 186; - public static final int ARM64_REG_W19 = 187; - public static final int ARM64_REG_W20 = 188; - public static final int ARM64_REG_W21 = 189; - public static final int ARM64_REG_W22 = 190; - public static final int ARM64_REG_W23 = 191; - public static final int ARM64_REG_W24 = 192; - public static final int ARM64_REG_W25 = 193; - public static final int ARM64_REG_W26 = 194; - public static final int ARM64_REG_W27 = 195; - public static final int ARM64_REG_W28 = 196; - public static final int ARM64_REG_W29 = 197; - public static final int ARM64_REG_W30 = 198; - public static final int ARM64_REG_X0 = 199; - public static final int ARM64_REG_X1 = 200; - public static final int ARM64_REG_X2 = 201; - public static final int ARM64_REG_X3 = 202; - public static final int ARM64_REG_X4 = 203; - public static final int ARM64_REG_X5 = 204; - public static final int ARM64_REG_X6 = 205; - public static final int ARM64_REG_X7 = 206; - public static final int ARM64_REG_X8 = 207; - public static final int ARM64_REG_X9 = 208; - public static final int ARM64_REG_X10 = 209; - public static final int ARM64_REG_X11 = 210; - public static final int ARM64_REG_X12 = 211; - public static final int ARM64_REG_X13 = 212; - public static final int ARM64_REG_X14 = 213; - public static final int ARM64_REG_X15 = 214; - public static final int ARM64_REG_X16 = 215; - public static final int ARM64_REG_X17 = 216; - public static final int ARM64_REG_X18 = 217; - public static final int ARM64_REG_X19 = 218; - public static final int ARM64_REG_X20 = 219; - public static final int ARM64_REG_X21 = 220; - public static final int ARM64_REG_X22 = 221; - public static final int ARM64_REG_X23 = 222; - public static final int ARM64_REG_X24 = 223; - public static final int ARM64_REG_X25 = 224; - public static final int ARM64_REG_X26 = 225; - public static final int ARM64_REG_X27 = 226; - public static final int ARM64_REG_X28 = 227; - public static final int ARM64_REG_V0 = 228; - public static final int ARM64_REG_V1 = 229; - public static final int ARM64_REG_V2 = 230; - public static final int ARM64_REG_V3 = 231; - public static final int ARM64_REG_V4 = 232; - public static final int ARM64_REG_V5 = 233; - public static final int ARM64_REG_V6 = 234; - public static final int ARM64_REG_V7 = 235; - public static final int ARM64_REG_V8 = 236; - public static final int ARM64_REG_V9 = 237; - public static final int ARM64_REG_V10 = 238; - public static final int ARM64_REG_V11 = 239; - public static final int ARM64_REG_V12 = 240; - public static final int ARM64_REG_V13 = 241; - public static final int ARM64_REG_V14 = 242; - public static final int ARM64_REG_V15 = 243; - public static final int ARM64_REG_V16 = 244; - public static final int ARM64_REG_V17 = 245; - public static final int ARM64_REG_V18 = 246; - public static final int ARM64_REG_V19 = 247; - public static final int ARM64_REG_V20 = 248; - public static final int ARM64_REG_V21 = 249; - public static final int ARM64_REG_V22 = 250; - public static final int ARM64_REG_V23 = 251; - public static final int ARM64_REG_V24 = 252; - public static final int ARM64_REG_V25 = 253; - public static final int ARM64_REG_V26 = 254; - public static final int ARM64_REG_V27 = 255; - public static final int ARM64_REG_V28 = 256; - public static final int ARM64_REG_V29 = 257; - public static final int ARM64_REG_V30 = 258; - public static final int ARM64_REG_V31 = 259; - public static final int ARM64_REG_ENDING = 260; + public static final int ARM64_REG_FFR = 1; + public static final int ARM64_REG_FP = 2; + public static final int ARM64_REG_LR = 3; + public static final int ARM64_REG_NZCV = 4; + public static final int ARM64_REG_SP = 5; + public static final int ARM64_REG_WSP = 6; + public static final int ARM64_REG_WZR = 7; + public static final int ARM64_REG_XZR = 8; + public static final int ARM64_REG_B0 = 9; + public static final int ARM64_REG_B1 = 10; + public static final int ARM64_REG_B2 = 11; + public static final int ARM64_REG_B3 = 12; + public static final int ARM64_REG_B4 = 13; + public static final int ARM64_REG_B5 = 14; + public static final int ARM64_REG_B6 = 15; + public static final int ARM64_REG_B7 = 16; + public static final int ARM64_REG_B8 = 17; + public static final int ARM64_REG_B9 = 18; + public static final int ARM64_REG_B10 = 19; + public static final int ARM64_REG_B11 = 20; + public static final int ARM64_REG_B12 = 21; + public static final int ARM64_REG_B13 = 22; + public static final int ARM64_REG_B14 = 23; + public static final int ARM64_REG_B15 = 24; + public static final int ARM64_REG_B16 = 25; + public static final int ARM64_REG_B17 = 26; + public static final int ARM64_REG_B18 = 27; + public static final int ARM64_REG_B19 = 28; + public static final int ARM64_REG_B20 = 29; + public static final int ARM64_REG_B21 = 30; + public static final int ARM64_REG_B22 = 31; + public static final int ARM64_REG_B23 = 32; + public static final int ARM64_REG_B24 = 33; + public static final int ARM64_REG_B25 = 34; + public static final int ARM64_REG_B26 = 35; + public static final int ARM64_REG_B27 = 36; + public static final int ARM64_REG_B28 = 37; + public static final int ARM64_REG_B29 = 38; + public static final int ARM64_REG_B30 = 39; + public static final int ARM64_REG_B31 = 40; + public static final int ARM64_REG_D0 = 41; + public static final int ARM64_REG_D1 = 42; + public static final int ARM64_REG_D2 = 43; + public static final int ARM64_REG_D3 = 44; + public static final int ARM64_REG_D4 = 45; + public static final int ARM64_REG_D5 = 46; + public static final int ARM64_REG_D6 = 47; + public static final int ARM64_REG_D7 = 48; + public static final int ARM64_REG_D8 = 49; + public static final int ARM64_REG_D9 = 50; + public static final int ARM64_REG_D10 = 51; + public static final int ARM64_REG_D11 = 52; + public static final int ARM64_REG_D12 = 53; + public static final int ARM64_REG_D13 = 54; + public static final int ARM64_REG_D14 = 55; + public static final int ARM64_REG_D15 = 56; + public static final int ARM64_REG_D16 = 57; + public static final int ARM64_REG_D17 = 58; + public static final int ARM64_REG_D18 = 59; + public static final int ARM64_REG_D19 = 60; + public static final int ARM64_REG_D20 = 61; + public static final int ARM64_REG_D21 = 62; + public static final int ARM64_REG_D22 = 63; + public static final int ARM64_REG_D23 = 64; + public static final int ARM64_REG_D24 = 65; + public static final int ARM64_REG_D25 = 66; + public static final int ARM64_REG_D26 = 67; + public static final int ARM64_REG_D27 = 68; + public static final int ARM64_REG_D28 = 69; + public static final int ARM64_REG_D29 = 70; + public static final int ARM64_REG_D30 = 71; + public static final int ARM64_REG_D31 = 72; + public static final int ARM64_REG_H0 = 73; + public static final int ARM64_REG_H1 = 74; + public static final int ARM64_REG_H2 = 75; + public static final int ARM64_REG_H3 = 76; + public static final int ARM64_REG_H4 = 77; + public static final int ARM64_REG_H5 = 78; + public static final int ARM64_REG_H6 = 79; + public static final int ARM64_REG_H7 = 80; + public static final int ARM64_REG_H8 = 81; + public static final int ARM64_REG_H9 = 82; + public static final int ARM64_REG_H10 = 83; + public static final int ARM64_REG_H11 = 84; + public static final int ARM64_REG_H12 = 85; + public static final int ARM64_REG_H13 = 86; + public static final int ARM64_REG_H14 = 87; + public static final int ARM64_REG_H15 = 88; + public static final int ARM64_REG_H16 = 89; + public static final int ARM64_REG_H17 = 90; + public static final int ARM64_REG_H18 = 91; + public static final int ARM64_REG_H19 = 92; + public static final int ARM64_REG_H20 = 93; + public static final int ARM64_REG_H21 = 94; + public static final int ARM64_REG_H22 = 95; + public static final int ARM64_REG_H23 = 96; + public static final int ARM64_REG_H24 = 97; + public static final int ARM64_REG_H25 = 98; + public static final int ARM64_REG_H26 = 99; + public static final int ARM64_REG_H27 = 100; + public static final int ARM64_REG_H28 = 101; + public static final int ARM64_REG_H29 = 102; + public static final int ARM64_REG_H30 = 103; + public static final int ARM64_REG_H31 = 104; + public static final int ARM64_REG_P0 = 105; + public static final int ARM64_REG_P1 = 106; + public static final int ARM64_REG_P2 = 107; + public static final int ARM64_REG_P3 = 108; + public static final int ARM64_REG_P4 = 109; + public static final int ARM64_REG_P5 = 110; + public static final int ARM64_REG_P6 = 111; + public static final int ARM64_REG_P7 = 112; + public static final int ARM64_REG_P8 = 113; + public static final int ARM64_REG_P9 = 114; + public static final int ARM64_REG_P10 = 115; + public static final int ARM64_REG_P11 = 116; + public static final int ARM64_REG_P12 = 117; + public static final int ARM64_REG_P13 = 118; + public static final int ARM64_REG_P14 = 119; + public static final int ARM64_REG_P15 = 120; + public static final int ARM64_REG_Q0 = 121; + public static final int ARM64_REG_Q1 = 122; + public static final int ARM64_REG_Q2 = 123; + public static final int ARM64_REG_Q3 = 124; + public static final int ARM64_REG_Q4 = 125; + public static final int ARM64_REG_Q5 = 126; + public static final int ARM64_REG_Q6 = 127; + public static final int ARM64_REG_Q7 = 128; + public static final int ARM64_REG_Q8 = 129; + public static final int ARM64_REG_Q9 = 130; + public static final int ARM64_REG_Q10 = 131; + public static final int ARM64_REG_Q11 = 132; + public static final int ARM64_REG_Q12 = 133; + public static final int ARM64_REG_Q13 = 134; + public static final int ARM64_REG_Q14 = 135; + public static final int ARM64_REG_Q15 = 136; + public static final int ARM64_REG_Q16 = 137; + public static final int ARM64_REG_Q17 = 138; + public static final int ARM64_REG_Q18 = 139; + public static final int ARM64_REG_Q19 = 140; + public static final int ARM64_REG_Q20 = 141; + public static final int ARM64_REG_Q21 = 142; + public static final int ARM64_REG_Q22 = 143; + public static final int ARM64_REG_Q23 = 144; + public static final int ARM64_REG_Q24 = 145; + public static final int ARM64_REG_Q25 = 146; + public static final int ARM64_REG_Q26 = 147; + public static final int ARM64_REG_Q27 = 148; + public static final int ARM64_REG_Q28 = 149; + public static final int ARM64_REG_Q29 = 150; + public static final int ARM64_REG_Q30 = 151; + public static final int ARM64_REG_Q31 = 152; + public static final int ARM64_REG_S0 = 153; + public static final int ARM64_REG_S1 = 154; + public static final int ARM64_REG_S2 = 155; + public static final int ARM64_REG_S3 = 156; + public static final int ARM64_REG_S4 = 157; + public static final int ARM64_REG_S5 = 158; + public static final int ARM64_REG_S6 = 159; + public static final int ARM64_REG_S7 = 160; + public static final int ARM64_REG_S8 = 161; + public static final int ARM64_REG_S9 = 162; + public static final int ARM64_REG_S10 = 163; + public static final int ARM64_REG_S11 = 164; + public static final int ARM64_REG_S12 = 165; + public static final int ARM64_REG_S13 = 166; + public static final int ARM64_REG_S14 = 167; + public static final int ARM64_REG_S15 = 168; + public static final int ARM64_REG_S16 = 169; + public static final int ARM64_REG_S17 = 170; + public static final int ARM64_REG_S18 = 171; + public static final int ARM64_REG_S19 = 172; + public static final int ARM64_REG_S20 = 173; + public static final int ARM64_REG_S21 = 174; + public static final int ARM64_REG_S22 = 175; + public static final int ARM64_REG_S23 = 176; + public static final int ARM64_REG_S24 = 177; + public static final int ARM64_REG_S25 = 178; + public static final int ARM64_REG_S26 = 179; + public static final int ARM64_REG_S27 = 180; + public static final int ARM64_REG_S28 = 181; + public static final int ARM64_REG_S29 = 182; + public static final int ARM64_REG_S30 = 183; + public static final int ARM64_REG_S31 = 184; + public static final int ARM64_REG_W0 = 185; + public static final int ARM64_REG_W1 = 186; + public static final int ARM64_REG_W2 = 187; + public static final int ARM64_REG_W3 = 188; + public static final int ARM64_REG_W4 = 189; + public static final int ARM64_REG_W5 = 190; + public static final int ARM64_REG_W6 = 191; + public static final int ARM64_REG_W7 = 192; + public static final int ARM64_REG_W8 = 193; + public static final int ARM64_REG_W9 = 194; + public static final int ARM64_REG_W10 = 195; + public static final int ARM64_REG_W11 = 196; + public static final int ARM64_REG_W12 = 197; + public static final int ARM64_REG_W13 = 198; + public static final int ARM64_REG_W14 = 199; + public static final int ARM64_REG_W15 = 200; + public static final int ARM64_REG_W16 = 201; + public static final int ARM64_REG_W17 = 202; + public static final int ARM64_REG_W18 = 203; + public static final int ARM64_REG_W19 = 204; + public static final int ARM64_REG_W20 = 205; + public static final int ARM64_REG_W21 = 206; + public static final int ARM64_REG_W22 = 207; + public static final int ARM64_REG_W23 = 208; + public static final int ARM64_REG_W24 = 209; + public static final int ARM64_REG_W25 = 210; + public static final int ARM64_REG_W26 = 211; + public static final int ARM64_REG_W27 = 212; + public static final int ARM64_REG_W28 = 213; + public static final int ARM64_REG_W29 = 214; + public static final int ARM64_REG_W30 = 215; + public static final int ARM64_REG_X0 = 216; + public static final int ARM64_REG_X1 = 217; + public static final int ARM64_REG_X2 = 218; + public static final int ARM64_REG_X3 = 219; + public static final int ARM64_REG_X4 = 220; + public static final int ARM64_REG_X5 = 221; + public static final int ARM64_REG_X6 = 222; + public static final int ARM64_REG_X7 = 223; + public static final int ARM64_REG_X8 = 224; + public static final int ARM64_REG_X9 = 225; + public static final int ARM64_REG_X10 = 226; + public static final int ARM64_REG_X11 = 227; + public static final int ARM64_REG_X12 = 228; + public static final int ARM64_REG_X13 = 229; + public static final int ARM64_REG_X14 = 230; + public static final int ARM64_REG_X15 = 231; + public static final int ARM64_REG_X16 = 232; + public static final int ARM64_REG_X17 = 233; + public static final int ARM64_REG_X18 = 234; + public static final int ARM64_REG_X19 = 235; + public static final int ARM64_REG_X20 = 236; + public static final int ARM64_REG_X21 = 237; + public static final int ARM64_REG_X22 = 238; + public static final int ARM64_REG_X23 = 239; + public static final int ARM64_REG_X24 = 240; + public static final int ARM64_REG_X25 = 241; + public static final int ARM64_REG_X26 = 242; + public static final int ARM64_REG_X27 = 243; + public static final int ARM64_REG_X28 = 244; + public static final int ARM64_REG_Z0 = 245; + public static final int ARM64_REG_Z1 = 246; + public static final int ARM64_REG_Z2 = 247; + public static final int ARM64_REG_Z3 = 248; + public static final int ARM64_REG_Z4 = 249; + public static final int ARM64_REG_Z5 = 250; + public static final int ARM64_REG_Z6 = 251; + public static final int ARM64_REG_Z7 = 252; + public static final int ARM64_REG_Z8 = 253; + public static final int ARM64_REG_Z9 = 254; + public static final int ARM64_REG_Z10 = 255; + public static final int ARM64_REG_Z11 = 256; + public static final int ARM64_REG_Z12 = 257; + public static final int ARM64_REG_Z13 = 258; + public static final int ARM64_REG_Z14 = 259; + public static final int ARM64_REG_Z15 = 260; + public static final int ARM64_REG_Z16 = 261; + public static final int ARM64_REG_Z17 = 262; + public static final int ARM64_REG_Z18 = 263; + public static final int ARM64_REG_Z19 = 264; + public static final int ARM64_REG_Z20 = 265; + public static final int ARM64_REG_Z21 = 266; + public static final int ARM64_REG_Z22 = 267; + public static final int ARM64_REG_Z23 = 268; + public static final int ARM64_REG_Z24 = 269; + public static final int ARM64_REG_Z25 = 270; + public static final int ARM64_REG_Z26 = 271; + public static final int ARM64_REG_Z27 = 272; + public static final int ARM64_REG_Z28 = 273; + public static final int ARM64_REG_Z29 = 274; + public static final int ARM64_REG_Z30 = 275; + public static final int ARM64_REG_Z31 = 276; + public static final int ARM64_REG_V0 = 277; + public static final int ARM64_REG_V1 = 278; + public static final int ARM64_REG_V2 = 279; + public static final int ARM64_REG_V3 = 280; + public static final int ARM64_REG_V4 = 281; + public static final int ARM64_REG_V5 = 282; + public static final int ARM64_REG_V6 = 283; + public static final int ARM64_REG_V7 = 284; + public static final int ARM64_REG_V8 = 285; + public static final int ARM64_REG_V9 = 286; + public static final int ARM64_REG_V10 = 287; + public static final int ARM64_REG_V11 = 288; + public static final int ARM64_REG_V12 = 289; + public static final int ARM64_REG_V13 = 290; + public static final int ARM64_REG_V14 = 291; + public static final int ARM64_REG_V15 = 292; + public static final int ARM64_REG_V16 = 293; + public static final int ARM64_REG_V17 = 294; + public static final int ARM64_REG_V18 = 295; + public static final int ARM64_REG_V19 = 296; + public static final int ARM64_REG_V20 = 297; + public static final int ARM64_REG_V21 = 298; + public static final int ARM64_REG_V22 = 299; + public static final int ARM64_REG_V23 = 300; + public static final int ARM64_REG_V24 = 301; + public static final int ARM64_REG_V25 = 302; + public static final int ARM64_REG_V26 = 303; + public static final int ARM64_REG_V27 = 304; + public static final int ARM64_REG_V28 = 305; + public static final int ARM64_REG_V29 = 306; + public static final int ARM64_REG_V30 = 307; + public static final int ARM64_REG_V31 = 308; + public static final int ARM64_REG_ENDING = 309; public static final int ARM64_REG_IP0 = ARM64_REG_X16; public static final int ARM64_REG_IP1 = ARM64_REG_X17; - public static final int ARM64_REG_FP = ARM64_REG_X29; - public static final int ARM64_REG_LR = ARM64_REG_X30; + public static final int ARM64_REG_X29 = ARM64_REG_FP; + public static final int ARM64_REG_X30 = ARM64_REG_LR; public static final int ARM64_INS_INVALID = 0; public static final int ARM64_INS_ABS = 1; public static final int ARM64_INS_ADC = 2; - public static final int ARM64_INS_ADDHN = 3; - public static final int ARM64_INS_ADDHN2 = 4; - public static final int ARM64_INS_ADDP = 5; - public static final int ARM64_INS_ADD = 6; - public static final int ARM64_INS_ADDV = 7; - public static final int ARM64_INS_ADR = 8; - public static final int ARM64_INS_ADRP = 9; - public static final int ARM64_INS_AESD = 10; - public static final int ARM64_INS_AESE = 11; - public static final int ARM64_INS_AESIMC = 12; - public static final int ARM64_INS_AESMC = 13; - public static final int ARM64_INS_AND = 14; - public static final int ARM64_INS_ASR = 15; - public static final int ARM64_INS_B = 16; - public static final int ARM64_INS_BFM = 17; - public static final int ARM64_INS_BIC = 18; - public static final int ARM64_INS_BIF = 19; - public static final int ARM64_INS_BIT = 20; - public static final int ARM64_INS_BL = 21; - public static final int ARM64_INS_BLR = 22; - public static final int ARM64_INS_BR = 23; - public static final int ARM64_INS_BRK = 24; - public static final int ARM64_INS_BSL = 25; - public static final int ARM64_INS_CBNZ = 26; - public static final int ARM64_INS_CBZ = 27; - public static final int ARM64_INS_CCMN = 28; - public static final int ARM64_INS_CCMP = 29; - public static final int ARM64_INS_CLREX = 30; - public static final int ARM64_INS_CLS = 31; - public static final int ARM64_INS_CLZ = 32; - public static final int ARM64_INS_CMEQ = 33; - public static final int ARM64_INS_CMGE = 34; - public static final int ARM64_INS_CMGT = 35; - public static final int ARM64_INS_CMHI = 36; - public static final int ARM64_INS_CMHS = 37; - public static final int ARM64_INS_CMLE = 38; - public static final int ARM64_INS_CMLT = 39; - public static final int ARM64_INS_CMTST = 40; - public static final int ARM64_INS_CNT = 41; - public static final int ARM64_INS_MOV = 42; - public static final int ARM64_INS_CRC32B = 43; - public static final int ARM64_INS_CRC32CB = 44; - public static final int ARM64_INS_CRC32CH = 45; - public static final int ARM64_INS_CRC32CW = 46; - public static final int ARM64_INS_CRC32CX = 47; - public static final int ARM64_INS_CRC32H = 48; - public static final int ARM64_INS_CRC32W = 49; - public static final int ARM64_INS_CRC32X = 50; - public static final int ARM64_INS_CSEL = 51; - public static final int ARM64_INS_CSINC = 52; - public static final int ARM64_INS_CSINV = 53; - public static final int ARM64_INS_CSNEG = 54; - public static final int ARM64_INS_DCPS1 = 55; - public static final int ARM64_INS_DCPS2 = 56; - public static final int ARM64_INS_DCPS3 = 57; - public static final int ARM64_INS_DMB = 58; - public static final int ARM64_INS_DRPS = 59; - public static final int ARM64_INS_DSB = 60; - public static final int ARM64_INS_DUP = 61; - public static final int ARM64_INS_EON = 62; - public static final int ARM64_INS_EOR = 63; - public static final int ARM64_INS_ERET = 64; - public static final int ARM64_INS_EXTR = 65; - public static final int ARM64_INS_EXT = 66; - public static final int ARM64_INS_FABD = 67; - public static final int ARM64_INS_FABS = 68; - public static final int ARM64_INS_FACGE = 69; - public static final int ARM64_INS_FACGT = 70; - public static final int ARM64_INS_FADD = 71; - public static final int ARM64_INS_FADDP = 72; - public static final int ARM64_INS_FCCMP = 73; - public static final int ARM64_INS_FCCMPE = 74; - public static final int ARM64_INS_FCMEQ = 75; - public static final int ARM64_INS_FCMGE = 76; - public static final int ARM64_INS_FCMGT = 77; - public static final int ARM64_INS_FCMLE = 78; - public static final int ARM64_INS_FCMLT = 79; - public static final int ARM64_INS_FCMP = 80; - public static final int ARM64_INS_FCMPE = 81; - public static final int ARM64_INS_FCSEL = 82; - public static final int ARM64_INS_FCVTAS = 83; - public static final int ARM64_INS_FCVTAU = 84; - public static final int ARM64_INS_FCVT = 85; - public static final int ARM64_INS_FCVTL = 86; - public static final int ARM64_INS_FCVTL2 = 87; - public static final int ARM64_INS_FCVTMS = 88; - public static final int ARM64_INS_FCVTMU = 89; - public static final int ARM64_INS_FCVTNS = 90; - public static final int ARM64_INS_FCVTNU = 91; - public static final int ARM64_INS_FCVTN = 92; - public static final int ARM64_INS_FCVTN2 = 93; - public static final int ARM64_INS_FCVTPS = 94; - public static final int ARM64_INS_FCVTPU = 95; - public static final int ARM64_INS_FCVTXN = 96; - public static final int ARM64_INS_FCVTXN2 = 97; - public static final int ARM64_INS_FCVTZS = 98; - public static final int ARM64_INS_FCVTZU = 99; - public static final int ARM64_INS_FDIV = 100; - public static final int ARM64_INS_FMADD = 101; - public static final int ARM64_INS_FMAX = 102; - public static final int ARM64_INS_FMAXNM = 103; - public static final int ARM64_INS_FMAXNMP = 104; - public static final int ARM64_INS_FMAXNMV = 105; - public static final int ARM64_INS_FMAXP = 106; - public static final int ARM64_INS_FMAXV = 107; - public static final int ARM64_INS_FMIN = 108; - public static final int ARM64_INS_FMINNM = 109; - public static final int ARM64_INS_FMINNMP = 110; - public static final int ARM64_INS_FMINNMV = 111; - public static final int ARM64_INS_FMINP = 112; - public static final int ARM64_INS_FMINV = 113; - public static final int ARM64_INS_FMLA = 114; - public static final int ARM64_INS_FMLS = 115; - public static final int ARM64_INS_FMOV = 116; - public static final int ARM64_INS_FMSUB = 117; - public static final int ARM64_INS_FMUL = 118; - public static final int ARM64_INS_FMULX = 119; - public static final int ARM64_INS_FNEG = 120; - public static final int ARM64_INS_FNMADD = 121; - public static final int ARM64_INS_FNMSUB = 122; - public static final int ARM64_INS_FNMUL = 123; - public static final int ARM64_INS_FRECPE = 124; - public static final int ARM64_INS_FRECPS = 125; - public static final int ARM64_INS_FRECPX = 126; - public static final int ARM64_INS_FRINTA = 127; - public static final int ARM64_INS_FRINTI = 128; - public static final int ARM64_INS_FRINTM = 129; - public static final int ARM64_INS_FRINTN = 130; - public static final int ARM64_INS_FRINTP = 131; - public static final int ARM64_INS_FRINTX = 132; - public static final int ARM64_INS_FRINTZ = 133; - public static final int ARM64_INS_FRSQRTE = 134; - public static final int ARM64_INS_FRSQRTS = 135; - public static final int ARM64_INS_FSQRT = 136; - public static final int ARM64_INS_FSUB = 137; - public static final int ARM64_INS_HINT = 138; - public static final int ARM64_INS_HLT = 139; - public static final int ARM64_INS_HVC = 140; - public static final int ARM64_INS_INS = 141; - public static final int ARM64_INS_ISB = 142; - public static final int ARM64_INS_LD1 = 143; - public static final int ARM64_INS_LD1R = 144; - public static final int ARM64_INS_LD2R = 145; - public static final int ARM64_INS_LD2 = 146; - public static final int ARM64_INS_LD3R = 147; - public static final int ARM64_INS_LD3 = 148; - public static final int ARM64_INS_LD4 = 149; - public static final int ARM64_INS_LD4R = 150; - public static final int ARM64_INS_LDARB = 151; - public static final int ARM64_INS_LDARH = 152; - public static final int ARM64_INS_LDAR = 153; - public static final int ARM64_INS_LDAXP = 154; - public static final int ARM64_INS_LDAXRB = 155; - public static final int ARM64_INS_LDAXRH = 156; - public static final int ARM64_INS_LDAXR = 157; - public static final int ARM64_INS_LDNP = 158; - public static final int ARM64_INS_LDP = 159; - public static final int ARM64_INS_LDPSW = 160; - public static final int ARM64_INS_LDRB = 161; - public static final int ARM64_INS_LDR = 162; - public static final int ARM64_INS_LDRH = 163; - public static final int ARM64_INS_LDRSB = 164; - public static final int ARM64_INS_LDRSH = 165; - public static final int ARM64_INS_LDRSW = 166; - public static final int ARM64_INS_LDTRB = 167; - public static final int ARM64_INS_LDTRH = 168; - public static final int ARM64_INS_LDTRSB = 169; - public static final int ARM64_INS_LDTRSH = 170; - public static final int ARM64_INS_LDTRSW = 171; - public static final int ARM64_INS_LDTR = 172; - public static final int ARM64_INS_LDURB = 173; - public static final int ARM64_INS_LDUR = 174; - public static final int ARM64_INS_LDURH = 175; - public static final int ARM64_INS_LDURSB = 176; - public static final int ARM64_INS_LDURSH = 177; - public static final int ARM64_INS_LDURSW = 178; - public static final int ARM64_INS_LDXP = 179; - public static final int ARM64_INS_LDXRB = 180; - public static final int ARM64_INS_LDXRH = 181; - public static final int ARM64_INS_LDXR = 182; - public static final int ARM64_INS_LSL = 183; - public static final int ARM64_INS_LSR = 184; - public static final int ARM64_INS_MADD = 185; - public static final int ARM64_INS_MLA = 186; - public static final int ARM64_INS_MLS = 187; - public static final int ARM64_INS_MOVI = 188; - public static final int ARM64_INS_MOVK = 189; - public static final int ARM64_INS_MOVN = 190; - public static final int ARM64_INS_MOVZ = 191; - public static final int ARM64_INS_MRS = 192; - public static final int ARM64_INS_MSR = 193; - public static final int ARM64_INS_MSUB = 194; - public static final int ARM64_INS_MUL = 195; - public static final int ARM64_INS_MVNI = 196; - public static final int ARM64_INS_NEG = 197; - public static final int ARM64_INS_NOT = 198; - public static final int ARM64_INS_ORN = 199; - public static final int ARM64_INS_ORR = 200; - public static final int ARM64_INS_PMULL2 = 201; - public static final int ARM64_INS_PMULL = 202; - public static final int ARM64_INS_PMUL = 203; - public static final int ARM64_INS_PRFM = 204; - public static final int ARM64_INS_PRFUM = 205; - public static final int ARM64_INS_RADDHN = 206; - public static final int ARM64_INS_RADDHN2 = 207; - public static final int ARM64_INS_RBIT = 208; - public static final int ARM64_INS_RET = 209; - public static final int ARM64_INS_REV16 = 210; - public static final int ARM64_INS_REV32 = 211; - public static final int ARM64_INS_REV64 = 212; - public static final int ARM64_INS_REV = 213; - public static final int ARM64_INS_ROR = 214; - public static final int ARM64_INS_RSHRN2 = 215; - public static final int ARM64_INS_RSHRN = 216; - public static final int ARM64_INS_RSUBHN = 217; - public static final int ARM64_INS_RSUBHN2 = 218; - public static final int ARM64_INS_SABAL2 = 219; - public static final int ARM64_INS_SABAL = 220; - public static final int ARM64_INS_SABA = 221; - public static final int ARM64_INS_SABDL2 = 222; - public static final int ARM64_INS_SABDL = 223; - public static final int ARM64_INS_SABD = 224; - public static final int ARM64_INS_SADALP = 225; - public static final int ARM64_INS_SADDLP = 226; - public static final int ARM64_INS_SADDLV = 227; - public static final int ARM64_INS_SADDL2 = 228; - public static final int ARM64_INS_SADDL = 229; - public static final int ARM64_INS_SADDW2 = 230; - public static final int ARM64_INS_SADDW = 231; - public static final int ARM64_INS_SBC = 232; - public static final int ARM64_INS_SBFM = 233; - public static final int ARM64_INS_SCVTF = 234; - public static final int ARM64_INS_SDIV = 235; - public static final int ARM64_INS_SHA1C = 236; - public static final int ARM64_INS_SHA1H = 237; - public static final int ARM64_INS_SHA1M = 238; - public static final int ARM64_INS_SHA1P = 239; - public static final int ARM64_INS_SHA1SU0 = 240; - public static final int ARM64_INS_SHA1SU1 = 241; - public static final int ARM64_INS_SHA256H2 = 242; - public static final int ARM64_INS_SHA256H = 243; - public static final int ARM64_INS_SHA256SU0 = 244; - public static final int ARM64_INS_SHA256SU1 = 245; - public static final int ARM64_INS_SHADD = 246; - public static final int ARM64_INS_SHLL2 = 247; - public static final int ARM64_INS_SHLL = 248; - public static final int ARM64_INS_SHL = 249; - public static final int ARM64_INS_SHRN2 = 250; - public static final int ARM64_INS_SHRN = 251; - public static final int ARM64_INS_SHSUB = 252; - public static final int ARM64_INS_SLI = 253; - public static final int ARM64_INS_SMADDL = 254; - public static final int ARM64_INS_SMAXP = 255; - public static final int ARM64_INS_SMAXV = 256; - public static final int ARM64_INS_SMAX = 257; - public static final int ARM64_INS_SMC = 258; - public static final int ARM64_INS_SMINP = 259; - public static final int ARM64_INS_SMINV = 260; - public static final int ARM64_INS_SMIN = 261; - public static final int ARM64_INS_SMLAL2 = 262; - public static final int ARM64_INS_SMLAL = 263; - public static final int ARM64_INS_SMLSL2 = 264; - public static final int ARM64_INS_SMLSL = 265; - public static final int ARM64_INS_SMOV = 266; - public static final int ARM64_INS_SMSUBL = 267; - public static final int ARM64_INS_SMULH = 268; - public static final int ARM64_INS_SMULL2 = 269; - public static final int ARM64_INS_SMULL = 270; - public static final int ARM64_INS_SQABS = 271; - public static final int ARM64_INS_SQADD = 272; - public static final int ARM64_INS_SQDMLAL = 273; - public static final int ARM64_INS_SQDMLAL2 = 274; - public static final int ARM64_INS_SQDMLSL = 275; - public static final int ARM64_INS_SQDMLSL2 = 276; - public static final int ARM64_INS_SQDMULH = 277; - public static final int ARM64_INS_SQDMULL = 278; - public static final int ARM64_INS_SQDMULL2 = 279; - public static final int ARM64_INS_SQNEG = 280; - public static final int ARM64_INS_SQRDMULH = 281; - public static final int ARM64_INS_SQRSHL = 282; - public static final int ARM64_INS_SQRSHRN = 283; - public static final int ARM64_INS_SQRSHRN2 = 284; - public static final int ARM64_INS_SQRSHRUN = 285; - public static final int ARM64_INS_SQRSHRUN2 = 286; - public static final int ARM64_INS_SQSHLU = 287; - public static final int ARM64_INS_SQSHL = 288; - public static final int ARM64_INS_SQSHRN = 289; - public static final int ARM64_INS_SQSHRN2 = 290; - public static final int ARM64_INS_SQSHRUN = 291; - public static final int ARM64_INS_SQSHRUN2 = 292; - public static final int ARM64_INS_SQSUB = 293; - public static final int ARM64_INS_SQXTN2 = 294; - public static final int ARM64_INS_SQXTN = 295; - public static final int ARM64_INS_SQXTUN2 = 296; - public static final int ARM64_INS_SQXTUN = 297; - public static final int ARM64_INS_SRHADD = 298; - public static final int ARM64_INS_SRI = 299; - public static final int ARM64_INS_SRSHL = 300; - public static final int ARM64_INS_SRSHR = 301; - public static final int ARM64_INS_SRSRA = 302; - public static final int ARM64_INS_SSHLL2 = 303; - public static final int ARM64_INS_SSHLL = 304; - public static final int ARM64_INS_SSHL = 305; - public static final int ARM64_INS_SSHR = 306; - public static final int ARM64_INS_SSRA = 307; - public static final int ARM64_INS_SSUBL2 = 308; - public static final int ARM64_INS_SSUBL = 309; - public static final int ARM64_INS_SSUBW2 = 310; - public static final int ARM64_INS_SSUBW = 311; - public static final int ARM64_INS_ST1 = 312; - public static final int ARM64_INS_ST2 = 313; - public static final int ARM64_INS_ST3 = 314; - public static final int ARM64_INS_ST4 = 315; - public static final int ARM64_INS_STLRB = 316; - public static final int ARM64_INS_STLRH = 317; - public static final int ARM64_INS_STLR = 318; - public static final int ARM64_INS_STLXP = 319; - public static final int ARM64_INS_STLXRB = 320; - public static final int ARM64_INS_STLXRH = 321; - public static final int ARM64_INS_STLXR = 322; - public static final int ARM64_INS_STNP = 323; - public static final int ARM64_INS_STP = 324; - public static final int ARM64_INS_STRB = 325; - public static final int ARM64_INS_STR = 326; - public static final int ARM64_INS_STRH = 327; - public static final int ARM64_INS_STTRB = 328; - public static final int ARM64_INS_STTRH = 329; - public static final int ARM64_INS_STTR = 330; - public static final int ARM64_INS_STURB = 331; - public static final int ARM64_INS_STUR = 332; - public static final int ARM64_INS_STURH = 333; - public static final int ARM64_INS_STXP = 334; - public static final int ARM64_INS_STXRB = 335; - public static final int ARM64_INS_STXRH = 336; - public static final int ARM64_INS_STXR = 337; - public static final int ARM64_INS_SUBHN = 338; - public static final int ARM64_INS_SUBHN2 = 339; - public static final int ARM64_INS_SUB = 340; - public static final int ARM64_INS_SUQADD = 341; - public static final int ARM64_INS_SVC = 342; - public static final int ARM64_INS_SYSL = 343; - public static final int ARM64_INS_SYS = 344; - public static final int ARM64_INS_TBL = 345; - public static final int ARM64_INS_TBNZ = 346; - public static final int ARM64_INS_TBX = 347; - public static final int ARM64_INS_TBZ = 348; - public static final int ARM64_INS_TRN1 = 349; - public static final int ARM64_INS_TRN2 = 350; - public static final int ARM64_INS_UABAL2 = 351; - public static final int ARM64_INS_UABAL = 352; - public static final int ARM64_INS_UABA = 353; - public static final int ARM64_INS_UABDL2 = 354; - public static final int ARM64_INS_UABDL = 355; - public static final int ARM64_INS_UABD = 356; - public static final int ARM64_INS_UADALP = 357; - public static final int ARM64_INS_UADDLP = 358; - public static final int ARM64_INS_UADDLV = 359; - public static final int ARM64_INS_UADDL2 = 360; - public static final int ARM64_INS_UADDL = 361; - public static final int ARM64_INS_UADDW2 = 362; - public static final int ARM64_INS_UADDW = 363; - public static final int ARM64_INS_UBFM = 364; - public static final int ARM64_INS_UCVTF = 365; - public static final int ARM64_INS_UDIV = 366; - public static final int ARM64_INS_UHADD = 367; - public static final int ARM64_INS_UHSUB = 368; - public static final int ARM64_INS_UMADDL = 369; - public static final int ARM64_INS_UMAXP = 370; - public static final int ARM64_INS_UMAXV = 371; - public static final int ARM64_INS_UMAX = 372; - public static final int ARM64_INS_UMINP = 373; - public static final int ARM64_INS_UMINV = 374; - public static final int ARM64_INS_UMIN = 375; - public static final int ARM64_INS_UMLAL2 = 376; - public static final int ARM64_INS_UMLAL = 377; - public static final int ARM64_INS_UMLSL2 = 378; - public static final int ARM64_INS_UMLSL = 379; - public static final int ARM64_INS_UMOV = 380; - public static final int ARM64_INS_UMSUBL = 381; - public static final int ARM64_INS_UMULH = 382; - public static final int ARM64_INS_UMULL2 = 383; - public static final int ARM64_INS_UMULL = 384; - public static final int ARM64_INS_UQADD = 385; - public static final int ARM64_INS_UQRSHL = 386; - public static final int ARM64_INS_UQRSHRN = 387; - public static final int ARM64_INS_UQRSHRN2 = 388; - public static final int ARM64_INS_UQSHL = 389; - public static final int ARM64_INS_UQSHRN = 390; - public static final int ARM64_INS_UQSHRN2 = 391; - public static final int ARM64_INS_UQSUB = 392; - public static final int ARM64_INS_UQXTN2 = 393; - public static final int ARM64_INS_UQXTN = 394; - public static final int ARM64_INS_URECPE = 395; - public static final int ARM64_INS_URHADD = 396; - public static final int ARM64_INS_URSHL = 397; - public static final int ARM64_INS_URSHR = 398; - public static final int ARM64_INS_URSQRTE = 399; - public static final int ARM64_INS_URSRA = 400; - public static final int ARM64_INS_USHLL2 = 401; - public static final int ARM64_INS_USHLL = 402; - public static final int ARM64_INS_USHL = 403; - public static final int ARM64_INS_USHR = 404; - public static final int ARM64_INS_USQADD = 405; - public static final int ARM64_INS_USRA = 406; - public static final int ARM64_INS_USUBL2 = 407; - public static final int ARM64_INS_USUBL = 408; - public static final int ARM64_INS_USUBW2 = 409; - public static final int ARM64_INS_USUBW = 410; - public static final int ARM64_INS_UZP1 = 411; - public static final int ARM64_INS_UZP2 = 412; - public static final int ARM64_INS_XTN2 = 413; - public static final int ARM64_INS_XTN = 414; - public static final int ARM64_INS_ZIP1 = 415; - public static final int ARM64_INS_ZIP2 = 416; - public static final int ARM64_INS_MNEG = 417; - public static final int ARM64_INS_UMNEGL = 418; - public static final int ARM64_INS_SMNEGL = 419; - public static final int ARM64_INS_NOP = 420; - public static final int ARM64_INS_YIELD = 421; - public static final int ARM64_INS_WFE = 422; - public static final int ARM64_INS_WFI = 423; - public static final int ARM64_INS_SEV = 424; - public static final int ARM64_INS_SEVL = 425; - public static final int ARM64_INS_NGC = 426; - public static final int ARM64_INS_SBFIZ = 427; - public static final int ARM64_INS_UBFIZ = 428; - public static final int ARM64_INS_SBFX = 429; - public static final int ARM64_INS_UBFX = 430; - public static final int ARM64_INS_BFI = 431; - public static final int ARM64_INS_BFXIL = 432; - public static final int ARM64_INS_CMN = 433; - public static final int ARM64_INS_MVN = 434; - public static final int ARM64_INS_TST = 435; - public static final int ARM64_INS_CSET = 436; - public static final int ARM64_INS_CINC = 437; - public static final int ARM64_INS_CSETM = 438; - public static final int ARM64_INS_CINV = 439; - public static final int ARM64_INS_CNEG = 440; - public static final int ARM64_INS_SXTB = 441; - public static final int ARM64_INS_SXTH = 442; - public static final int ARM64_INS_SXTW = 443; - public static final int ARM64_INS_CMP = 444; - public static final int ARM64_INS_UXTB = 445; - public static final int ARM64_INS_UXTH = 446; - public static final int ARM64_INS_UXTW = 447; - public static final int ARM64_INS_IC = 448; - public static final int ARM64_INS_DC = 449; - public static final int ARM64_INS_AT = 450; - public static final int ARM64_INS_TLBI = 451; - public static final int ARM64_INS_NEGS = 452; - public static final int ARM64_INS_NGCS = 453; - public static final int ARM64_INS_ENDING = 454; + public static final int ARM64_INS_ADCS = 3; + public static final int ARM64_INS_ADD = 4; + public static final int ARM64_INS_ADDHN = 5; + public static final int ARM64_INS_ADDHN2 = 6; + public static final int ARM64_INS_ADDP = 7; + public static final int ARM64_INS_ADDPL = 8; + public static final int ARM64_INS_ADDS = 9; + public static final int ARM64_INS_ADDV = 10; + public static final int ARM64_INS_ADDVL = 11; + public static final int ARM64_INS_ADR = 12; + public static final int ARM64_INS_ADRP = 13; + public static final int ARM64_INS_AESD = 14; + public static final int ARM64_INS_AESE = 15; + public static final int ARM64_INS_AESIMC = 16; + public static final int ARM64_INS_AESMC = 17; + public static final int ARM64_INS_AND = 18; + public static final int ARM64_INS_ANDS = 19; + public static final int ARM64_INS_ANDV = 20; + public static final int ARM64_INS_ASR = 21; + public static final int ARM64_INS_ASRD = 22; + public static final int ARM64_INS_ASRR = 23; + public static final int ARM64_INS_ASRV = 24; + public static final int ARM64_INS_AUTDA = 25; + public static final int ARM64_INS_AUTDB = 26; + public static final int ARM64_INS_AUTDZA = 27; + public static final int ARM64_INS_AUTDZB = 28; + public static final int ARM64_INS_AUTIA = 29; + public static final int ARM64_INS_AUTIA1716 = 30; + public static final int ARM64_INS_AUTIASP = 31; + public static final int ARM64_INS_AUTIAZ = 32; + public static final int ARM64_INS_AUTIB = 33; + public static final int ARM64_INS_AUTIB1716 = 34; + public static final int ARM64_INS_AUTIBSP = 35; + public static final int ARM64_INS_AUTIBZ = 36; + public static final int ARM64_INS_AUTIZA = 37; + public static final int ARM64_INS_AUTIZB = 38; + public static final int ARM64_INS_B = 39; + public static final int ARM64_INS_BCAX = 40; + public static final int ARM64_INS_BFM = 41; + public static final int ARM64_INS_BIC = 42; + public static final int ARM64_INS_BICS = 43; + public static final int ARM64_INS_BIF = 44; + public static final int ARM64_INS_BIT = 45; + public static final int ARM64_INS_BL = 46; + public static final int ARM64_INS_BLR = 47; + public static final int ARM64_INS_BLRAA = 48; + public static final int ARM64_INS_BLRAAZ = 49; + public static final int ARM64_INS_BLRAB = 50; + public static final int ARM64_INS_BLRABZ = 51; + public static final int ARM64_INS_BR = 52; + public static final int ARM64_INS_BRAA = 53; + public static final int ARM64_INS_BRAAZ = 54; + public static final int ARM64_INS_BRAB = 55; + public static final int ARM64_INS_BRABZ = 56; + public static final int ARM64_INS_BRK = 57; + public static final int ARM64_INS_BRKA = 58; + public static final int ARM64_INS_BRKAS = 59; + public static final int ARM64_INS_BRKB = 60; + public static final int ARM64_INS_BRKBS = 61; + public static final int ARM64_INS_BRKN = 62; + public static final int ARM64_INS_BRKNS = 63; + public static final int ARM64_INS_BRKPA = 64; + public static final int ARM64_INS_BRKPAS = 65; + public static final int ARM64_INS_BRKPB = 66; + public static final int ARM64_INS_BRKPBS = 67; + public static final int ARM64_INS_BSL = 68; + public static final int ARM64_INS_CAS = 69; + public static final int ARM64_INS_CASA = 70; + public static final int ARM64_INS_CASAB = 71; + public static final int ARM64_INS_CASAH = 72; + public static final int ARM64_INS_CASAL = 73; + public static final int ARM64_INS_CASALB = 74; + public static final int ARM64_INS_CASALH = 75; + public static final int ARM64_INS_CASB = 76; + public static final int ARM64_INS_CASH = 77; + public static final int ARM64_INS_CASL = 78; + public static final int ARM64_INS_CASLB = 79; + public static final int ARM64_INS_CASLH = 80; + public static final int ARM64_INS_CASP = 81; + public static final int ARM64_INS_CASPA = 82; + public static final int ARM64_INS_CASPAL = 83; + public static final int ARM64_INS_CASPL = 84; + public static final int ARM64_INS_CBNZ = 85; + public static final int ARM64_INS_CBZ = 86; + public static final int ARM64_INS_CCMN = 87; + public static final int ARM64_INS_CCMP = 88; + public static final int ARM64_INS_CFINV = 89; + public static final int ARM64_INS_CINC = 90; + public static final int ARM64_INS_CINV = 91; + public static final int ARM64_INS_CLASTA = 92; + public static final int ARM64_INS_CLASTB = 93; + public static final int ARM64_INS_CLREX = 94; + public static final int ARM64_INS_CLS = 95; + public static final int ARM64_INS_CLZ = 96; + public static final int ARM64_INS_CMEQ = 97; + public static final int ARM64_INS_CMGE = 98; + public static final int ARM64_INS_CMGT = 99; + public static final int ARM64_INS_CMHI = 100; + public static final int ARM64_INS_CMHS = 101; + public static final int ARM64_INS_CMLE = 102; + public static final int ARM64_INS_CMLO = 103; + public static final int ARM64_INS_CMLS = 104; + public static final int ARM64_INS_CMLT = 105; + public static final int ARM64_INS_CMN = 106; + public static final int ARM64_INS_CMP = 107; + public static final int ARM64_INS_CMPEQ = 108; + public static final int ARM64_INS_CMPGE = 109; + public static final int ARM64_INS_CMPGT = 110; + public static final int ARM64_INS_CMPHI = 111; + public static final int ARM64_INS_CMPHS = 112; + public static final int ARM64_INS_CMPLE = 113; + public static final int ARM64_INS_CMPLO = 114; + public static final int ARM64_INS_CMPLS = 115; + public static final int ARM64_INS_CMPLT = 116; + public static final int ARM64_INS_CMPNE = 117; + public static final int ARM64_INS_CMTST = 118; + public static final int ARM64_INS_CNEG = 119; + public static final int ARM64_INS_CNOT = 120; + public static final int ARM64_INS_CNT = 121; + public static final int ARM64_INS_CNTB = 122; + public static final int ARM64_INS_CNTD = 123; + public static final int ARM64_INS_CNTH = 124; + public static final int ARM64_INS_CNTP = 125; + public static final int ARM64_INS_CNTW = 126; + public static final int ARM64_INS_COMPACT = 127; + public static final int ARM64_INS_CPY = 128; + public static final int ARM64_INS_CRC32B = 129; + public static final int ARM64_INS_CRC32CB = 130; + public static final int ARM64_INS_CRC32CH = 131; + public static final int ARM64_INS_CRC32CW = 132; + public static final int ARM64_INS_CRC32CX = 133; + public static final int ARM64_INS_CRC32H = 134; + public static final int ARM64_INS_CRC32W = 135; + public static final int ARM64_INS_CRC32X = 136; + public static final int ARM64_INS_CSDB = 137; + public static final int ARM64_INS_CSEL = 138; + public static final int ARM64_INS_CSET = 139; + public static final int ARM64_INS_CSETM = 140; + public static final int ARM64_INS_CSINC = 141; + public static final int ARM64_INS_CSINV = 142; + public static final int ARM64_INS_CSNEG = 143; + public static final int ARM64_INS_CTERMEQ = 144; + public static final int ARM64_INS_CTERMNE = 145; + public static final int ARM64_INS_DCPS1 = 146; + public static final int ARM64_INS_DCPS2 = 147; + public static final int ARM64_INS_DCPS3 = 148; + public static final int ARM64_INS_DECB = 149; + public static final int ARM64_INS_DECD = 150; + public static final int ARM64_INS_DECH = 151; + public static final int ARM64_INS_DECP = 152; + public static final int ARM64_INS_DECW = 153; + public static final int ARM64_INS_DMB = 154; + public static final int ARM64_INS_DRPS = 155; + public static final int ARM64_INS_DSB = 156; + public static final int ARM64_INS_DUP = 157; + public static final int ARM64_INS_DUPM = 158; + public static final int ARM64_INS_EON = 159; + public static final int ARM64_INS_EOR = 160; + public static final int ARM64_INS_EOR3 = 161; + public static final int ARM64_INS_EORS = 162; + public static final int ARM64_INS_EORV = 163; + public static final int ARM64_INS_ERET = 164; + public static final int ARM64_INS_ERETAA = 165; + public static final int ARM64_INS_ERETAB = 166; + public static final int ARM64_INS_ESB = 167; + public static final int ARM64_INS_EXT = 168; + public static final int ARM64_INS_EXTR = 169; + public static final int ARM64_INS_FABD = 170; + public static final int ARM64_INS_FABS = 171; + public static final int ARM64_INS_FACGE = 172; + public static final int ARM64_INS_FACGT = 173; + public static final int ARM64_INS_FACLE = 174; + public static final int ARM64_INS_FACLT = 175; + public static final int ARM64_INS_FADD = 176; + public static final int ARM64_INS_FADDA = 177; + public static final int ARM64_INS_FADDP = 178; + public static final int ARM64_INS_FADDV = 179; + public static final int ARM64_INS_FCADD = 180; + public static final int ARM64_INS_FCCMP = 181; + public static final int ARM64_INS_FCCMPE = 182; + public static final int ARM64_INS_FCMEQ = 183; + public static final int ARM64_INS_FCMGE = 184; + public static final int ARM64_INS_FCMGT = 185; + public static final int ARM64_INS_FCMLA = 186; + public static final int ARM64_INS_FCMLE = 187; + public static final int ARM64_INS_FCMLT = 188; + public static final int ARM64_INS_FCMNE = 189; + public static final int ARM64_INS_FCMP = 190; + public static final int ARM64_INS_FCMPE = 191; + public static final int ARM64_INS_FCMUO = 192; + public static final int ARM64_INS_FCPY = 193; + public static final int ARM64_INS_FCSEL = 194; + public static final int ARM64_INS_FCVT = 195; + public static final int ARM64_INS_FCVTAS = 196; + public static final int ARM64_INS_FCVTAU = 197; + public static final int ARM64_INS_FCVTL = 198; + public static final int ARM64_INS_FCVTL2 = 199; + public static final int ARM64_INS_FCVTMS = 200; + public static final int ARM64_INS_FCVTMU = 201; + public static final int ARM64_INS_FCVTN = 202; + public static final int ARM64_INS_FCVTN2 = 203; + public static final int ARM64_INS_FCVTNS = 204; + public static final int ARM64_INS_FCVTNU = 205; + public static final int ARM64_INS_FCVTPS = 206; + public static final int ARM64_INS_FCVTPU = 207; + public static final int ARM64_INS_FCVTXN = 208; + public static final int ARM64_INS_FCVTXN2 = 209; + public static final int ARM64_INS_FCVTZS = 210; + public static final int ARM64_INS_FCVTZU = 211; + public static final int ARM64_INS_FDIV = 212; + public static final int ARM64_INS_FDIVR = 213; + public static final int ARM64_INS_FDUP = 214; + public static final int ARM64_INS_FEXPA = 215; + public static final int ARM64_INS_FJCVTZS = 216; + public static final int ARM64_INS_FMAD = 217; + public static final int ARM64_INS_FMADD = 218; + public static final int ARM64_INS_FMAX = 219; + public static final int ARM64_INS_FMAXNM = 220; + public static final int ARM64_INS_FMAXNMP = 221; + public static final int ARM64_INS_FMAXNMV = 222; + public static final int ARM64_INS_FMAXP = 223; + public static final int ARM64_INS_FMAXV = 224; + public static final int ARM64_INS_FMIN = 225; + public static final int ARM64_INS_FMINNM = 226; + public static final int ARM64_INS_FMINNMP = 227; + public static final int ARM64_INS_FMINNMV = 228; + public static final int ARM64_INS_FMINP = 229; + public static final int ARM64_INS_FMINV = 230; + public static final int ARM64_INS_FMLA = 231; + public static final int ARM64_INS_FMLS = 232; + public static final int ARM64_INS_FMOV = 233; + public static final int ARM64_INS_FMSB = 234; + public static final int ARM64_INS_FMSUB = 235; + public static final int ARM64_INS_FMUL = 236; + public static final int ARM64_INS_FMULX = 237; + public static final int ARM64_INS_FNEG = 238; + public static final int ARM64_INS_FNMAD = 239; + public static final int ARM64_INS_FNMADD = 240; + public static final int ARM64_INS_FNMLA = 241; + public static final int ARM64_INS_FNMLS = 242; + public static final int ARM64_INS_FNMSB = 243; + public static final int ARM64_INS_FNMSUB = 244; + public static final int ARM64_INS_FNMUL = 245; + public static final int ARM64_INS_FRECPE = 246; + public static final int ARM64_INS_FRECPS = 247; + public static final int ARM64_INS_FRECPX = 248; + public static final int ARM64_INS_FRINTA = 249; + public static final int ARM64_INS_FRINTI = 250; + public static final int ARM64_INS_FRINTM = 251; + public static final int ARM64_INS_FRINTN = 252; + public static final int ARM64_INS_FRINTP = 253; + public static final int ARM64_INS_FRINTX = 254; + public static final int ARM64_INS_FRINTZ = 255; + public static final int ARM64_INS_FRSQRTE = 256; + public static final int ARM64_INS_FRSQRTS = 257; + public static final int ARM64_INS_FSCALE = 258; + public static final int ARM64_INS_FSQRT = 259; + public static final int ARM64_INS_FSUB = 260; + public static final int ARM64_INS_FSUBR = 261; + public static final int ARM64_INS_FTMAD = 262; + public static final int ARM64_INS_FTSMUL = 263; + public static final int ARM64_INS_FTSSEL = 264; + public static final int ARM64_INS_HINT = 265; + public static final int ARM64_INS_HLT = 266; + public static final int ARM64_INS_HVC = 267; + public static final int ARM64_INS_INCB = 268; + public static final int ARM64_INS_INCD = 269; + public static final int ARM64_INS_INCH = 270; + public static final int ARM64_INS_INCP = 271; + public static final int ARM64_INS_INCW = 272; + public static final int ARM64_INS_INDEX = 273; + public static final int ARM64_INS_INS = 274; + public static final int ARM64_INS_INSR = 275; + public static final int ARM64_INS_ISB = 276; + public static final int ARM64_INS_LASTA = 277; + public static final int ARM64_INS_LASTB = 278; + public static final int ARM64_INS_LD1 = 279; + public static final int ARM64_INS_LD1B = 280; + public static final int ARM64_INS_LD1D = 281; + public static final int ARM64_INS_LD1H = 282; + public static final int ARM64_INS_LD1R = 283; + public static final int ARM64_INS_LD1RB = 284; + public static final int ARM64_INS_LD1RD = 285; + public static final int ARM64_INS_LD1RH = 286; + public static final int ARM64_INS_LD1RQB = 287; + public static final int ARM64_INS_LD1RQD = 288; + public static final int ARM64_INS_LD1RQH = 289; + public static final int ARM64_INS_LD1RQW = 290; + public static final int ARM64_INS_LD1RSB = 291; + public static final int ARM64_INS_LD1RSH = 292; + public static final int ARM64_INS_LD1RSW = 293; + public static final int ARM64_INS_LD1RW = 294; + public static final int ARM64_INS_LD1SB = 295; + public static final int ARM64_INS_LD1SH = 296; + public static final int ARM64_INS_LD1SW = 297; + public static final int ARM64_INS_LD1W = 298; + public static final int ARM64_INS_LD2 = 299; + public static final int ARM64_INS_LD2B = 300; + public static final int ARM64_INS_LD2D = 301; + public static final int ARM64_INS_LD2H = 302; + public static final int ARM64_INS_LD2R = 303; + public static final int ARM64_INS_LD2W = 304; + public static final int ARM64_INS_LD3 = 305; + public static final int ARM64_INS_LD3B = 306; + public static final int ARM64_INS_LD3D = 307; + public static final int ARM64_INS_LD3H = 308; + public static final int ARM64_INS_LD3R = 309; + public static final int ARM64_INS_LD3W = 310; + public static final int ARM64_INS_LD4 = 311; + public static final int ARM64_INS_LD4B = 312; + public static final int ARM64_INS_LD4D = 313; + public static final int ARM64_INS_LD4H = 314; + public static final int ARM64_INS_LD4R = 315; + public static final int ARM64_INS_LD4W = 316; + public static final int ARM64_INS_LDADD = 317; + public static final int ARM64_INS_LDADDA = 318; + public static final int ARM64_INS_LDADDAB = 319; + public static final int ARM64_INS_LDADDAH = 320; + public static final int ARM64_INS_LDADDAL = 321; + public static final int ARM64_INS_LDADDALB = 322; + public static final int ARM64_INS_LDADDALH = 323; + public static final int ARM64_INS_LDADDB = 324; + public static final int ARM64_INS_LDADDH = 325; + public static final int ARM64_INS_LDADDL = 326; + public static final int ARM64_INS_LDADDLB = 327; + public static final int ARM64_INS_LDADDLH = 328; + public static final int ARM64_INS_LDAPR = 329; + public static final int ARM64_INS_LDAPRB = 330; + public static final int ARM64_INS_LDAPRH = 331; + public static final int ARM64_INS_LDAPUR = 332; + public static final int ARM64_INS_LDAPURB = 333; + public static final int ARM64_INS_LDAPURH = 334; + public static final int ARM64_INS_LDAPURSB = 335; + public static final int ARM64_INS_LDAPURSH = 336; + public static final int ARM64_INS_LDAPURSW = 337; + public static final int ARM64_INS_LDAR = 338; + public static final int ARM64_INS_LDARB = 339; + public static final int ARM64_INS_LDARH = 340; + public static final int ARM64_INS_LDAXP = 341; + public static final int ARM64_INS_LDAXR = 342; + public static final int ARM64_INS_LDAXRB = 343; + public static final int ARM64_INS_LDAXRH = 344; + public static final int ARM64_INS_LDCLR = 345; + public static final int ARM64_INS_LDCLRA = 346; + public static final int ARM64_INS_LDCLRAB = 347; + public static final int ARM64_INS_LDCLRAH = 348; + public static final int ARM64_INS_LDCLRAL = 349; + public static final int ARM64_INS_LDCLRALB = 350; + public static final int ARM64_INS_LDCLRALH = 351; + public static final int ARM64_INS_LDCLRB = 352; + public static final int ARM64_INS_LDCLRH = 353; + public static final int ARM64_INS_LDCLRL = 354; + public static final int ARM64_INS_LDCLRLB = 355; + public static final int ARM64_INS_LDCLRLH = 356; + public static final int ARM64_INS_LDEOR = 357; + public static final int ARM64_INS_LDEORA = 358; + public static final int ARM64_INS_LDEORAB = 359; + public static final int ARM64_INS_LDEORAH = 360; + public static final int ARM64_INS_LDEORAL = 361; + public static final int ARM64_INS_LDEORALB = 362; + public static final int ARM64_INS_LDEORALH = 363; + public static final int ARM64_INS_LDEORB = 364; + public static final int ARM64_INS_LDEORH = 365; + public static final int ARM64_INS_LDEORL = 366; + public static final int ARM64_INS_LDEORLB = 367; + public static final int ARM64_INS_LDEORLH = 368; + public static final int ARM64_INS_LDFF1B = 369; + public static final int ARM64_INS_LDFF1D = 370; + public static final int ARM64_INS_LDFF1H = 371; + public static final int ARM64_INS_LDFF1SB = 372; + public static final int ARM64_INS_LDFF1SH = 373; + public static final int ARM64_INS_LDFF1SW = 374; + public static final int ARM64_INS_LDFF1W = 375; + public static final int ARM64_INS_LDLAR = 376; + public static final int ARM64_INS_LDLARB = 377; + public static final int ARM64_INS_LDLARH = 378; + public static final int ARM64_INS_LDNF1B = 379; + public static final int ARM64_INS_LDNF1D = 380; + public static final int ARM64_INS_LDNF1H = 381; + public static final int ARM64_INS_LDNF1SB = 382; + public static final int ARM64_INS_LDNF1SH = 383; + public static final int ARM64_INS_LDNF1SW = 384; + public static final int ARM64_INS_LDNF1W = 385; + public static final int ARM64_INS_LDNP = 386; + public static final int ARM64_INS_LDNT1B = 387; + public static final int ARM64_INS_LDNT1D = 388; + public static final int ARM64_INS_LDNT1H = 389; + public static final int ARM64_INS_LDNT1W = 390; + public static final int ARM64_INS_LDP = 391; + public static final int ARM64_INS_LDPSW = 392; + public static final int ARM64_INS_LDR = 393; + public static final int ARM64_INS_LDRAA = 394; + public static final int ARM64_INS_LDRAB = 395; + public static final int ARM64_INS_LDRB = 396; + public static final int ARM64_INS_LDRH = 397; + public static final int ARM64_INS_LDRSB = 398; + public static final int ARM64_INS_LDRSH = 399; + public static final int ARM64_INS_LDRSW = 400; + public static final int ARM64_INS_LDSET = 401; + public static final int ARM64_INS_LDSETA = 402; + public static final int ARM64_INS_LDSETAB = 403; + public static final int ARM64_INS_LDSETAH = 404; + public static final int ARM64_INS_LDSETAL = 405; + public static final int ARM64_INS_LDSETALB = 406; + public static final int ARM64_INS_LDSETALH = 407; + public static final int ARM64_INS_LDSETB = 408; + public static final int ARM64_INS_LDSETH = 409; + public static final int ARM64_INS_LDSETL = 410; + public static final int ARM64_INS_LDSETLB = 411; + public static final int ARM64_INS_LDSETLH = 412; + public static final int ARM64_INS_LDSMAX = 413; + public static final int ARM64_INS_LDSMAXA = 414; + public static final int ARM64_INS_LDSMAXAB = 415; + public static final int ARM64_INS_LDSMAXAH = 416; + public static final int ARM64_INS_LDSMAXAL = 417; + public static final int ARM64_INS_LDSMAXALB = 418; + public static final int ARM64_INS_LDSMAXALH = 419; + public static final int ARM64_INS_LDSMAXB = 420; + public static final int ARM64_INS_LDSMAXH = 421; + public static final int ARM64_INS_LDSMAXL = 422; + public static final int ARM64_INS_LDSMAXLB = 423; + public static final int ARM64_INS_LDSMAXLH = 424; + public static final int ARM64_INS_LDSMIN = 425; + public static final int ARM64_INS_LDSMINA = 426; + public static final int ARM64_INS_LDSMINAB = 427; + public static final int ARM64_INS_LDSMINAH = 428; + public static final int ARM64_INS_LDSMINAL = 429; + public static final int ARM64_INS_LDSMINALB = 430; + public static final int ARM64_INS_LDSMINALH = 431; + public static final int ARM64_INS_LDSMINB = 432; + public static final int ARM64_INS_LDSMINH = 433; + public static final int ARM64_INS_LDSMINL = 434; + public static final int ARM64_INS_LDSMINLB = 435; + public static final int ARM64_INS_LDSMINLH = 436; + public static final int ARM64_INS_LDTR = 437; + public static final int ARM64_INS_LDTRB = 438; + public static final int ARM64_INS_LDTRH = 439; + public static final int ARM64_INS_LDTRSB = 440; + public static final int ARM64_INS_LDTRSH = 441; + public static final int ARM64_INS_LDTRSW = 442; + public static final int ARM64_INS_LDUMAX = 443; + public static final int ARM64_INS_LDUMAXA = 444; + public static final int ARM64_INS_LDUMAXAB = 445; + public static final int ARM64_INS_LDUMAXAH = 446; + public static final int ARM64_INS_LDUMAXAL = 447; + public static final int ARM64_INS_LDUMAXALB = 448; + public static final int ARM64_INS_LDUMAXALH = 449; + public static final int ARM64_INS_LDUMAXB = 450; + public static final int ARM64_INS_LDUMAXH = 451; + public static final int ARM64_INS_LDUMAXL = 452; + public static final int ARM64_INS_LDUMAXLB = 453; + public static final int ARM64_INS_LDUMAXLH = 454; + public static final int ARM64_INS_LDUMIN = 455; + public static final int ARM64_INS_LDUMINA = 456; + public static final int ARM64_INS_LDUMINAB = 457; + public static final int ARM64_INS_LDUMINAH = 458; + public static final int ARM64_INS_LDUMINAL = 459; + public static final int ARM64_INS_LDUMINALB = 460; + public static final int ARM64_INS_LDUMINALH = 461; + public static final int ARM64_INS_LDUMINB = 462; + public static final int ARM64_INS_LDUMINH = 463; + public static final int ARM64_INS_LDUMINL = 464; + public static final int ARM64_INS_LDUMINLB = 465; + public static final int ARM64_INS_LDUMINLH = 466; + public static final int ARM64_INS_LDUR = 467; + public static final int ARM64_INS_LDURB = 468; + public static final int ARM64_INS_LDURH = 469; + public static final int ARM64_INS_LDURSB = 470; + public static final int ARM64_INS_LDURSH = 471; + public static final int ARM64_INS_LDURSW = 472; + public static final int ARM64_INS_LDXP = 473; + public static final int ARM64_INS_LDXR = 474; + public static final int ARM64_INS_LDXRB = 475; + public static final int ARM64_INS_LDXRH = 476; + public static final int ARM64_INS_LSL = 477; + public static final int ARM64_INS_LSLR = 478; + public static final int ARM64_INS_LSLV = 479; + public static final int ARM64_INS_LSR = 480; + public static final int ARM64_INS_LSRR = 481; + public static final int ARM64_INS_LSRV = 482; + public static final int ARM64_INS_MAD = 483; + public static final int ARM64_INS_MADD = 484; + public static final int ARM64_INS_MLA = 485; + public static final int ARM64_INS_MLS = 486; + public static final int ARM64_INS_MNEG = 487; + public static final int ARM64_INS_MOV = 488; + public static final int ARM64_INS_MOVI = 489; + public static final int ARM64_INS_MOVK = 490; + public static final int ARM64_INS_MOVN = 491; + public static final int ARM64_INS_MOVPRFX = 492; + public static final int ARM64_INS_MOVS = 493; + public static final int ARM64_INS_MOVZ = 494; + public static final int ARM64_INS_MRS = 495; + public static final int ARM64_INS_MSB = 496; + public static final int ARM64_INS_MSR = 497; + public static final int ARM64_INS_MSUB = 498; + public static final int ARM64_INS_MUL = 499; + public static final int ARM64_INS_MVN = 500; + public static final int ARM64_INS_MVNI = 501; + public static final int ARM64_INS_NAND = 502; + public static final int ARM64_INS_NANDS = 503; + public static final int ARM64_INS_NEG = 504; + public static final int ARM64_INS_NEGS = 505; + public static final int ARM64_INS_NGC = 506; + public static final int ARM64_INS_NGCS = 507; + public static final int ARM64_INS_NOP = 508; + public static final int ARM64_INS_NOR = 509; + public static final int ARM64_INS_NORS = 510; + public static final int ARM64_INS_NOT = 511; + public static final int ARM64_INS_NOTS = 512; + public static final int ARM64_INS_ORN = 513; + public static final int ARM64_INS_ORNS = 514; + public static final int ARM64_INS_ORR = 515; + public static final int ARM64_INS_ORRS = 516; + public static final int ARM64_INS_ORV = 517; + public static final int ARM64_INS_PACDA = 518; + public static final int ARM64_INS_PACDB = 519; + public static final int ARM64_INS_PACDZA = 520; + public static final int ARM64_INS_PACDZB = 521; + public static final int ARM64_INS_PACGA = 522; + public static final int ARM64_INS_PACIA = 523; + public static final int ARM64_INS_PACIA1716 = 524; + public static final int ARM64_INS_PACIASP = 525; + public static final int ARM64_INS_PACIAZ = 526; + public static final int ARM64_INS_PACIB = 527; + public static final int ARM64_INS_PACIB1716 = 528; + public static final int ARM64_INS_PACIBSP = 529; + public static final int ARM64_INS_PACIBZ = 530; + public static final int ARM64_INS_PACIZA = 531; + public static final int ARM64_INS_PACIZB = 532; + public static final int ARM64_INS_PFALSE = 533; + public static final int ARM64_INS_PFIRST = 534; + public static final int ARM64_INS_PMUL = 535; + public static final int ARM64_INS_PMULL = 536; + public static final int ARM64_INS_PMULL2 = 537; + public static final int ARM64_INS_PNEXT = 538; + public static final int ARM64_INS_PRFB = 539; + public static final int ARM64_INS_PRFD = 540; + public static final int ARM64_INS_PRFH = 541; + public static final int ARM64_INS_PRFM = 542; + public static final int ARM64_INS_PRFUM = 543; + public static final int ARM64_INS_PRFW = 544; + public static final int ARM64_INS_PSB = 545; + public static final int ARM64_INS_PTEST = 546; + public static final int ARM64_INS_PTRUE = 547; + public static final int ARM64_INS_PTRUES = 548; + public static final int ARM64_INS_PUNPKHI = 549; + public static final int ARM64_INS_PUNPKLO = 550; + public static final int ARM64_INS_RADDHN = 551; + public static final int ARM64_INS_RADDHN2 = 552; + public static final int ARM64_INS_RAX1 = 553; + public static final int ARM64_INS_RBIT = 554; + public static final int ARM64_INS_RDFFR = 555; + public static final int ARM64_INS_RDFFRS = 556; + public static final int ARM64_INS_RDVL = 557; + public static final int ARM64_INS_RET = 558; + public static final int ARM64_INS_RETAA = 559; + public static final int ARM64_INS_RETAB = 560; + public static final int ARM64_INS_REV = 561; + public static final int ARM64_INS_REV16 = 562; + public static final int ARM64_INS_REV32 = 563; + public static final int ARM64_INS_REV64 = 564; + public static final int ARM64_INS_REVB = 565; + public static final int ARM64_INS_REVH = 566; + public static final int ARM64_INS_REVW = 567; + public static final int ARM64_INS_RMIF = 568; + public static final int ARM64_INS_ROR = 569; + public static final int ARM64_INS_RORV = 570; + public static final int ARM64_INS_RSHRN = 571; + public static final int ARM64_INS_RSHRN2 = 572; + public static final int ARM64_INS_RSUBHN = 573; + public static final int ARM64_INS_RSUBHN2 = 574; + public static final int ARM64_INS_SABA = 575; + public static final int ARM64_INS_SABAL = 576; + public static final int ARM64_INS_SABAL2 = 577; + public static final int ARM64_INS_SABD = 578; + public static final int ARM64_INS_SABDL = 579; + public static final int ARM64_INS_SABDL2 = 580; + public static final int ARM64_INS_SADALP = 581; + public static final int ARM64_INS_SADDL = 582; + public static final int ARM64_INS_SADDL2 = 583; + public static final int ARM64_INS_SADDLP = 584; + public static final int ARM64_INS_SADDLV = 585; + public static final int ARM64_INS_SADDV = 586; + public static final int ARM64_INS_SADDW = 587; + public static final int ARM64_INS_SADDW2 = 588; + public static final int ARM64_INS_SBC = 589; + public static final int ARM64_INS_SBCS = 590; + public static final int ARM64_INS_SBFM = 591; + public static final int ARM64_INS_SCVTF = 592; + public static final int ARM64_INS_SDIV = 593; + public static final int ARM64_INS_SDIVR = 594; + public static final int ARM64_INS_SDOT = 595; + public static final int ARM64_INS_SEL = 596; + public static final int ARM64_INS_SETF16 = 597; + public static final int ARM64_INS_SETF8 = 598; + public static final int ARM64_INS_SETFFR = 599; + public static final int ARM64_INS_SEV = 600; + public static final int ARM64_INS_SEVL = 601; + public static final int ARM64_INS_SHA1C = 602; + public static final int ARM64_INS_SHA1H = 603; + public static final int ARM64_INS_SHA1M = 604; + public static final int ARM64_INS_SHA1P = 605; + public static final int ARM64_INS_SHA1SU0 = 606; + public static final int ARM64_INS_SHA1SU1 = 607; + public static final int ARM64_INS_SHA256H = 608; + public static final int ARM64_INS_SHA256H2 = 609; + public static final int ARM64_INS_SHA256SU0 = 610; + public static final int ARM64_INS_SHA256SU1 = 611; + public static final int ARM64_INS_SHA512H = 612; + public static final int ARM64_INS_SHA512H2 = 613; + public static final int ARM64_INS_SHA512SU0 = 614; + public static final int ARM64_INS_SHA512SU1 = 615; + public static final int ARM64_INS_SHADD = 616; + public static final int ARM64_INS_SHL = 617; + public static final int ARM64_INS_SHLL = 618; + public static final int ARM64_INS_SHLL2 = 619; + public static final int ARM64_INS_SHRN = 620; + public static final int ARM64_INS_SHRN2 = 621; + public static final int ARM64_INS_SHSUB = 622; + public static final int ARM64_INS_SLI = 623; + public static final int ARM64_INS_SM3PARTW1 = 624; + public static final int ARM64_INS_SM3PARTW2 = 625; + public static final int ARM64_INS_SM3SS1 = 626; + public static final int ARM64_INS_SM3TT1A = 627; + public static final int ARM64_INS_SM3TT1B = 628; + public static final int ARM64_INS_SM3TT2A = 629; + public static final int ARM64_INS_SM3TT2B = 630; + public static final int ARM64_INS_SM4E = 631; + public static final int ARM64_INS_SM4EKEY = 632; + public static final int ARM64_INS_SMADDL = 633; + public static final int ARM64_INS_SMAX = 634; + public static final int ARM64_INS_SMAXP = 635; + public static final int ARM64_INS_SMAXV = 636; + public static final int ARM64_INS_SMC = 637; + public static final int ARM64_INS_SMIN = 638; + public static final int ARM64_INS_SMINP = 639; + public static final int ARM64_INS_SMINV = 640; + public static final int ARM64_INS_SMLAL = 641; + public static final int ARM64_INS_SMLAL2 = 642; + public static final int ARM64_INS_SMLSL = 643; + public static final int ARM64_INS_SMLSL2 = 644; + public static final int ARM64_INS_SMNEGL = 645; + public static final int ARM64_INS_SMOV = 646; + public static final int ARM64_INS_SMSUBL = 647; + public static final int ARM64_INS_SMULH = 648; + public static final int ARM64_INS_SMULL = 649; + public static final int ARM64_INS_SMULL2 = 650; + public static final int ARM64_INS_SPLICE = 651; + public static final int ARM64_INS_SQABS = 652; + public static final int ARM64_INS_SQADD = 653; + public static final int ARM64_INS_SQDECB = 654; + public static final int ARM64_INS_SQDECD = 655; + public static final int ARM64_INS_SQDECH = 656; + public static final int ARM64_INS_SQDECP = 657; + public static final int ARM64_INS_SQDECW = 658; + public static final int ARM64_INS_SQDMLAL = 659; + public static final int ARM64_INS_SQDMLAL2 = 660; + public static final int ARM64_INS_SQDMLSL = 661; + public static final int ARM64_INS_SQDMLSL2 = 662; + public static final int ARM64_INS_SQDMULH = 663; + public static final int ARM64_INS_SQDMULL = 664; + public static final int ARM64_INS_SQDMULL2 = 665; + public static final int ARM64_INS_SQINCB = 666; + public static final int ARM64_INS_SQINCD = 667; + public static final int ARM64_INS_SQINCH = 668; + public static final int ARM64_INS_SQINCP = 669; + public static final int ARM64_INS_SQINCW = 670; + public static final int ARM64_INS_SQNEG = 671; + public static final int ARM64_INS_SQRDMLAH = 672; + public static final int ARM64_INS_SQRDMLSH = 673; + public static final int ARM64_INS_SQRDMULH = 674; + public static final int ARM64_INS_SQRSHL = 675; + public static final int ARM64_INS_SQRSHRN = 676; + public static final int ARM64_INS_SQRSHRN2 = 677; + public static final int ARM64_INS_SQRSHRUN = 678; + public static final int ARM64_INS_SQRSHRUN2 = 679; + public static final int ARM64_INS_SQSHL = 680; + public static final int ARM64_INS_SQSHLU = 681; + public static final int ARM64_INS_SQSHRN = 682; + public static final int ARM64_INS_SQSHRN2 = 683; + public static final int ARM64_INS_SQSHRUN = 684; + public static final int ARM64_INS_SQSHRUN2 = 685; + public static final int ARM64_INS_SQSUB = 686; + public static final int ARM64_INS_SQXTN = 687; + public static final int ARM64_INS_SQXTN2 = 688; + public static final int ARM64_INS_SQXTUN = 689; + public static final int ARM64_INS_SQXTUN2 = 690; + public static final int ARM64_INS_SRHADD = 691; + public static final int ARM64_INS_SRI = 692; + public static final int ARM64_INS_SRSHL = 693; + public static final int ARM64_INS_SRSHR = 694; + public static final int ARM64_INS_SRSRA = 695; + public static final int ARM64_INS_SSHL = 696; + public static final int ARM64_INS_SSHLL = 697; + public static final int ARM64_INS_SSHLL2 = 698; + public static final int ARM64_INS_SSHR = 699; + public static final int ARM64_INS_SSRA = 700; + public static final int ARM64_INS_SSUBL = 701; + public static final int ARM64_INS_SSUBL2 = 702; + public static final int ARM64_INS_SSUBW = 703; + public static final int ARM64_INS_SSUBW2 = 704; + public static final int ARM64_INS_ST1 = 705; + public static final int ARM64_INS_ST1B = 706; + public static final int ARM64_INS_ST1D = 707; + public static final int ARM64_INS_ST1H = 708; + public static final int ARM64_INS_ST1W = 709; + public static final int ARM64_INS_ST2 = 710; + public static final int ARM64_INS_ST2B = 711; + public static final int ARM64_INS_ST2D = 712; + public static final int ARM64_INS_ST2H = 713; + public static final int ARM64_INS_ST2W = 714; + public static final int ARM64_INS_ST3 = 715; + public static final int ARM64_INS_ST3B = 716; + public static final int ARM64_INS_ST3D = 717; + public static final int ARM64_INS_ST3H = 718; + public static final int ARM64_INS_ST3W = 719; + public static final int ARM64_INS_ST4 = 720; + public static final int ARM64_INS_ST4B = 721; + public static final int ARM64_INS_ST4D = 722; + public static final int ARM64_INS_ST4H = 723; + public static final int ARM64_INS_ST4W = 724; + public static final int ARM64_INS_STADD = 725; + public static final int ARM64_INS_STADDB = 726; + public static final int ARM64_INS_STADDH = 727; + public static final int ARM64_INS_STADDL = 728; + public static final int ARM64_INS_STADDLB = 729; + public static final int ARM64_INS_STADDLH = 730; + public static final int ARM64_INS_STCLR = 731; + public static final int ARM64_INS_STCLRB = 732; + public static final int ARM64_INS_STCLRH = 733; + public static final int ARM64_INS_STCLRL = 734; + public static final int ARM64_INS_STCLRLB = 735; + public static final int ARM64_INS_STCLRLH = 736; + public static final int ARM64_INS_STEOR = 737; + public static final int ARM64_INS_STEORB = 738; + public static final int ARM64_INS_STEORH = 739; + public static final int ARM64_INS_STEORL = 740; + public static final int ARM64_INS_STEORLB = 741; + public static final int ARM64_INS_STEORLH = 742; + public static final int ARM64_INS_STLLR = 743; + public static final int ARM64_INS_STLLRB = 744; + public static final int ARM64_INS_STLLRH = 745; + public static final int ARM64_INS_STLR = 746; + public static final int ARM64_INS_STLRB = 747; + public static final int ARM64_INS_STLRH = 748; + public static final int ARM64_INS_STLUR = 749; + public static final int ARM64_INS_STLURB = 750; + public static final int ARM64_INS_STLURH = 751; + public static final int ARM64_INS_STLXP = 752; + public static final int ARM64_INS_STLXR = 753; + public static final int ARM64_INS_STLXRB = 754; + public static final int ARM64_INS_STLXRH = 755; + public static final int ARM64_INS_STNP = 756; + public static final int ARM64_INS_STNT1B = 757; + public static final int ARM64_INS_STNT1D = 758; + public static final int ARM64_INS_STNT1H = 759; + public static final int ARM64_INS_STNT1W = 760; + public static final int ARM64_INS_STP = 761; + public static final int ARM64_INS_STR = 762; + public static final int ARM64_INS_STRB = 763; + public static final int ARM64_INS_STRH = 764; + public static final int ARM64_INS_STSET = 765; + public static final int ARM64_INS_STSETB = 766; + public static final int ARM64_INS_STSETH = 767; + public static final int ARM64_INS_STSETL = 768; + public static final int ARM64_INS_STSETLB = 769; + public static final int ARM64_INS_STSETLH = 770; + public static final int ARM64_INS_STSMAX = 771; + public static final int ARM64_INS_STSMAXB = 772; + public static final int ARM64_INS_STSMAXH = 773; + public static final int ARM64_INS_STSMAXL = 774; + public static final int ARM64_INS_STSMAXLB = 775; + public static final int ARM64_INS_STSMAXLH = 776; + public static final int ARM64_INS_STSMIN = 777; + public static final int ARM64_INS_STSMINB = 778; + public static final int ARM64_INS_STSMINH = 779; + public static final int ARM64_INS_STSMINL = 780; + public static final int ARM64_INS_STSMINLB = 781; + public static final int ARM64_INS_STSMINLH = 782; + public static final int ARM64_INS_STTR = 783; + public static final int ARM64_INS_STTRB = 784; + public static final int ARM64_INS_STTRH = 785; + public static final int ARM64_INS_STUMAX = 786; + public static final int ARM64_INS_STUMAXB = 787; + public static final int ARM64_INS_STUMAXH = 788; + public static final int ARM64_INS_STUMAXL = 789; + public static final int ARM64_INS_STUMAXLB = 790; + public static final int ARM64_INS_STUMAXLH = 791; + public static final int ARM64_INS_STUMIN = 792; + public static final int ARM64_INS_STUMINB = 793; + public static final int ARM64_INS_STUMINH = 794; + public static final int ARM64_INS_STUMINL = 795; + public static final int ARM64_INS_STUMINLB = 796; + public static final int ARM64_INS_STUMINLH = 797; + public static final int ARM64_INS_STUR = 798; + public static final int ARM64_INS_STURB = 799; + public static final int ARM64_INS_STURH = 800; + public static final int ARM64_INS_STXP = 801; + public static final int ARM64_INS_STXR = 802; + public static final int ARM64_INS_STXRB = 803; + public static final int ARM64_INS_STXRH = 804; + public static final int ARM64_INS_SUB = 805; + public static final int ARM64_INS_SUBHN = 806; + public static final int ARM64_INS_SUBHN2 = 807; + public static final int ARM64_INS_SUBR = 808; + public static final int ARM64_INS_SUBS = 809; + public static final int ARM64_INS_SUNPKHI = 810; + public static final int ARM64_INS_SUNPKLO = 811; + public static final int ARM64_INS_SUQADD = 812; + public static final int ARM64_INS_SVC = 813; + public static final int ARM64_INS_SWP = 814; + public static final int ARM64_INS_SWPA = 815; + public static final int ARM64_INS_SWPAB = 816; + public static final int ARM64_INS_SWPAH = 817; + public static final int ARM64_INS_SWPAL = 818; + public static final int ARM64_INS_SWPALB = 819; + public static final int ARM64_INS_SWPALH = 820; + public static final int ARM64_INS_SWPB = 821; + public static final int ARM64_INS_SWPH = 822; + public static final int ARM64_INS_SWPL = 823; + public static final int ARM64_INS_SWPLB = 824; + public static final int ARM64_INS_SWPLH = 825; + public static final int ARM64_INS_SXTB = 826; + public static final int ARM64_INS_SXTH = 827; + public static final int ARM64_INS_SXTL = 828; + public static final int ARM64_INS_SXTL2 = 829; + public static final int ARM64_INS_SXTW = 830; + public static final int ARM64_INS_SYS = 831; + public static final int ARM64_INS_SYSL = 832; + public static final int ARM64_INS_TBL = 833; + public static final int ARM64_INS_TBNZ = 834; + public static final int ARM64_INS_TBX = 835; + public static final int ARM64_INS_TBZ = 836; + public static final int ARM64_INS_TRN1 = 837; + public static final int ARM64_INS_TRN2 = 838; + public static final int ARM64_INS_TSB = 839; + public static final int ARM64_INS_TST = 840; + public static final int ARM64_INS_UABA = 841; + public static final int ARM64_INS_UABAL = 842; + public static final int ARM64_INS_UABAL2 = 843; + public static final int ARM64_INS_UABD = 844; + public static final int ARM64_INS_UABDL = 845; + public static final int ARM64_INS_UABDL2 = 846; + public static final int ARM64_INS_UADALP = 847; + public static final int ARM64_INS_UADDL = 848; + public static final int ARM64_INS_UADDL2 = 849; + public static final int ARM64_INS_UADDLP = 850; + public static final int ARM64_INS_UADDLV = 851; + public static final int ARM64_INS_UADDV = 852; + public static final int ARM64_INS_UADDW = 853; + public static final int ARM64_INS_UADDW2 = 854; + public static final int ARM64_INS_UBFM = 855; + public static final int ARM64_INS_UCVTF = 856; + public static final int ARM64_INS_UDIV = 857; + public static final int ARM64_INS_UDIVR = 858; + public static final int ARM64_INS_UDOT = 859; + public static final int ARM64_INS_UHADD = 860; + public static final int ARM64_INS_UHSUB = 861; + public static final int ARM64_INS_UMADDL = 862; + public static final int ARM64_INS_UMAX = 863; + public static final int ARM64_INS_UMAXP = 864; + public static final int ARM64_INS_UMAXV = 865; + public static final int ARM64_INS_UMIN = 866; + public static final int ARM64_INS_UMINP = 867; + public static final int ARM64_INS_UMINV = 868; + public static final int ARM64_INS_UMLAL = 869; + public static final int ARM64_INS_UMLAL2 = 870; + public static final int ARM64_INS_UMLSL = 871; + public static final int ARM64_INS_UMLSL2 = 872; + public static final int ARM64_INS_UMNEGL = 873; + public static final int ARM64_INS_UMOV = 874; + public static final int ARM64_INS_UMSUBL = 875; + public static final int ARM64_INS_UMULH = 876; + public static final int ARM64_INS_UMULL = 877; + public static final int ARM64_INS_UMULL2 = 878; + public static final int ARM64_INS_UQADD = 879; + public static final int ARM64_INS_UQDECB = 880; + public static final int ARM64_INS_UQDECD = 881; + public static final int ARM64_INS_UQDECH = 882; + public static final int ARM64_INS_UQDECP = 883; + public static final int ARM64_INS_UQDECW = 884; + public static final int ARM64_INS_UQINCB = 885; + public static final int ARM64_INS_UQINCD = 886; + public static final int ARM64_INS_UQINCH = 887; + public static final int ARM64_INS_UQINCP = 888; + public static final int ARM64_INS_UQINCW = 889; + public static final int ARM64_INS_UQRSHL = 890; + public static final int ARM64_INS_UQRSHRN = 891; + public static final int ARM64_INS_UQRSHRN2 = 892; + public static final int ARM64_INS_UQSHL = 893; + public static final int ARM64_INS_UQSHRN = 894; + public static final int ARM64_INS_UQSHRN2 = 895; + public static final int ARM64_INS_UQSUB = 896; + public static final int ARM64_INS_UQXTN = 897; + public static final int ARM64_INS_UQXTN2 = 898; + public static final int ARM64_INS_URECPE = 899; + public static final int ARM64_INS_URHADD = 900; + public static final int ARM64_INS_URSHL = 901; + public static final int ARM64_INS_URSHR = 902; + public static final int ARM64_INS_URSQRTE = 903; + public static final int ARM64_INS_URSRA = 904; + public static final int ARM64_INS_USHL = 905; + public static final int ARM64_INS_USHLL = 906; + public static final int ARM64_INS_USHLL2 = 907; + public static final int ARM64_INS_USHR = 908; + public static final int ARM64_INS_USQADD = 909; + public static final int ARM64_INS_USRA = 910; + public static final int ARM64_INS_USUBL = 911; + public static final int ARM64_INS_USUBL2 = 912; + public static final int ARM64_INS_USUBW = 913; + public static final int ARM64_INS_USUBW2 = 914; + public static final int ARM64_INS_UUNPKHI = 915; + public static final int ARM64_INS_UUNPKLO = 916; + public static final int ARM64_INS_UXTB = 917; + public static final int ARM64_INS_UXTH = 918; + public static final int ARM64_INS_UXTL = 919; + public static final int ARM64_INS_UXTL2 = 920; + public static final int ARM64_INS_UXTW = 921; + public static final int ARM64_INS_UZP1 = 922; + public static final int ARM64_INS_UZP2 = 923; + public static final int ARM64_INS_WFE = 924; + public static final int ARM64_INS_WFI = 925; + public static final int ARM64_INS_WHILELE = 926; + public static final int ARM64_INS_WHILELO = 927; + public static final int ARM64_INS_WHILELS = 928; + public static final int ARM64_INS_WHILELT = 929; + public static final int ARM64_INS_WRFFR = 930; + public static final int ARM64_INS_XAR = 931; + public static final int ARM64_INS_XPACD = 932; + public static final int ARM64_INS_XPACI = 933; + public static final int ARM64_INS_XPACLRI = 934; + public static final int ARM64_INS_XTN = 935; + public static final int ARM64_INS_XTN2 = 936; + public static final int ARM64_INS_YIELD = 937; + public static final int ARM64_INS_ZIP1 = 938; + public static final int ARM64_INS_ZIP2 = 939; + public static final int ARM64_INS_SBFIZ = 940; + public static final int ARM64_INS_UBFIZ = 941; + public static final int ARM64_INS_SBFX = 942; + public static final int ARM64_INS_UBFX = 943; + public static final int ARM64_INS_BFI = 944; + public static final int ARM64_INS_BFXIL = 945; + public static final int ARM64_INS_IC = 946; + public static final int ARM64_INS_DC = 947; + public static final int ARM64_INS_AT = 948; + public static final int ARM64_INS_TLBI = 949; + public static final int ARM64_INS_ENDING = 950; public static final int ARM64_GRP_INVALID = 0; public static final int ARM64_GRP_JUMP = 1; @@ -1006,5 +2247,18 @@ public class Arm64_const { public static final int ARM64_GRP_FPARMV8 = 129; public static final int ARM64_GRP_NEON = 130; public static final int ARM64_GRP_CRC = 131; - public static final int ARM64_GRP_ENDING = 132; + public static final int ARM64_GRP_AES = 132; + public static final int ARM64_GRP_DOTPROD = 133; + public static final int ARM64_GRP_FULLFP16 = 134; + public static final int ARM64_GRP_LSE = 135; + public static final int ARM64_GRP_RCPC = 136; + public static final int ARM64_GRP_RDM = 137; + public static final int ARM64_GRP_SHA2 = 138; + public static final int ARM64_GRP_SHA3 = 139; + public static final int ARM64_GRP_SM4 = 140; + public static final int ARM64_GRP_SVE = 141; + public static final int ARM64_GRP_V8_1A = 142; + public static final int ARM64_GRP_V8_3A = 143; + public static final int ARM64_GRP_V8_4A = 144; + public static final int ARM64_GRP_ENDING = 145; } \ No newline at end of file diff --git a/bindings/ocaml/arm64.ml b/bindings/ocaml/arm64.ml index 1a5d98115..20d7030c8 100644 --- a/bindings/ocaml/arm64.ml +++ b/bindings/ocaml/arm64.ml @@ -32,7 +32,6 @@ type arm64_op_value = type arm64_op = { vector_index: int; vas: int; - vess: int; shift: arm64_op_shift; ext: int; value: arm64_op_value; diff --git a/bindings/ocaml/arm64_const.ml b/bindings/ocaml/arm64_const.ml index aeae5543f..388b8e82f 100644 --- a/bindings/ocaml/arm64_const.ml +++ b/bindings/ocaml/arm64_const.ml @@ -39,95 +39,740 @@ let _ARM64_SYSREG_INVALID = 0;; let _ARM64_SYSREG_MDCCSR_EL0 = 0x9808;; let _ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828;; let _ARM64_SYSREG_MDRAR_EL1 = 0x8080;; -let _ARM64_SYSREG_OSLSR_EL1 = 0x808c;; -let _ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6;; -let _ARM64_SYSREG_PMCEID0_EL0 = 0xdce6;; -let _ARM64_SYSREG_PMCEID1_EL0 = 0xdce7;; -let _ARM64_SYSREG_MIDR_EL1 = 0xc000;; -let _ARM64_SYSREG_CCSIDR_EL1 = 0xc800;; -let _ARM64_SYSREG_CLIDR_EL1 = 0xc801;; -let _ARM64_SYSREG_CTR_EL0 = 0xd801;; -let _ARM64_SYSREG_MPIDR_EL1 = 0xc005;; -let _ARM64_SYSREG_REVIDR_EL1 = 0xc006;; -let _ARM64_SYSREG_AIDR_EL1 = 0xc807;; -let _ARM64_SYSREG_DCZID_EL0 = 0xd807;; -let _ARM64_SYSREG_ID_PFR0_EL1 = 0xc008;; -let _ARM64_SYSREG_ID_PFR1_EL1 = 0xc009;; -let _ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a;; -let _ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b;; -let _ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c;; -let _ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d;; -let _ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e;; -let _ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f;; -let _ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010;; -let _ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011;; -let _ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012;; -let _ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013;; -let _ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014;; -let _ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015;; -let _ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020;; -let _ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021;; -let _ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028;; -let _ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029;; -let _ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c;; -let _ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d;; -let _ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030;; -let _ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031;; -let _ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038;; -let _ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039;; -let _ARM64_SYSREG_MVFR0_EL1 = 0xc018;; -let _ARM64_SYSREG_MVFR1_EL1 = 0xc019;; -let _ARM64_SYSREG_MVFR2_EL1 = 0xc01a;; -let _ARM64_SYSREG_RVBAR_EL1 = 0xc601;; -let _ARM64_SYSREG_RVBAR_EL2 = 0xe601;; -let _ARM64_SYSREG_RVBAR_EL3 = 0xf601;; -let _ARM64_SYSREG_ISR_EL1 = 0xc608;; -let _ARM64_SYSREG_CNTPCT_EL0 = 0xdf01;; -let _ARM64_SYSREG_CNTVCT_EL0 = 0xdf02;; +let _ARM64_SYSREG_OSLSR_EL1 = 0x808C;; +let _ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6;; +let _ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6;; +let _ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7;; +let _ARM64_SYSREG_MIDR_EL1 = 0xC000;; +let _ARM64_SYSREG_CCSIDR_EL1 = 0xC800;; +let _ARM64_SYSREG_CCSIDR2_EL1 = 0xC802;; +let _ARM64_SYSREG_CLIDR_EL1 = 0xC801;; +let _ARM64_SYSREG_CTR_EL0 = 0xD801;; +let _ARM64_SYSREG_MPIDR_EL1 = 0xC005;; +let _ARM64_SYSREG_REVIDR_EL1 = 0xC006;; +let _ARM64_SYSREG_AIDR_EL1 = 0xC807;; +let _ARM64_SYSREG_DCZID_EL0 = 0xD807;; +let _ARM64_SYSREG_ID_PFR0_EL1 = 0xC008;; +let _ARM64_SYSREG_ID_PFR1_EL1 = 0xC009;; +let _ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A;; +let _ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B;; +let _ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C;; +let _ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D;; +let _ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E;; +let _ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F;; +let _ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010;; +let _ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011;; +let _ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012;; +let _ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013;; +let _ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014;; +let _ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015;; +let _ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017;; +let _ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020;; +let _ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021;; +let _ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028;; +let _ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029;; +let _ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C;; +let _ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D;; +let _ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030;; +let _ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031;; +let _ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038;; +let _ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039;; +let _ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A;; +let _ARM64_SYSREG_MVFR0_EL1 = 0xC018;; +let _ARM64_SYSREG_MVFR1_EL1 = 0xC019;; +let _ARM64_SYSREG_MVFR2_EL1 = 0xC01A;; +let _ARM64_SYSREG_RVBAR_EL1 = 0xC601;; +let _ARM64_SYSREG_RVBAR_EL2 = 0xE601;; +let _ARM64_SYSREG_RVBAR_EL3 = 0xF601;; +let _ARM64_SYSREG_ISR_EL1 = 0xC608;; +let _ARM64_SYSREG_CNTPCT_EL0 = 0xDF01;; +let _ARM64_SYSREG_CNTVCT_EL0 = 0xDF02;; +let _ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016;; let _ARM64_SYSREG_TRCSTATR = 0x8818;; let _ARM64_SYSREG_TRCIDR8 = 0x8806;; -let _ARM64_SYSREG_TRCIDR9 = 0x880e;; +let _ARM64_SYSREG_TRCIDR9 = 0x880E;; let _ARM64_SYSREG_TRCIDR10 = 0x8816;; -let _ARM64_SYSREG_TRCIDR11 = 0x881e;; +let _ARM64_SYSREG_TRCIDR11 = 0x881E;; let _ARM64_SYSREG_TRCIDR12 = 0x8826;; -let _ARM64_SYSREG_TRCIDR13 = 0x882e;; +let _ARM64_SYSREG_TRCIDR13 = 0x882E;; let _ARM64_SYSREG_TRCIDR0 = 0x8847;; -let _ARM64_SYSREG_TRCIDR1 = 0x884f;; +let _ARM64_SYSREG_TRCIDR1 = 0x884F;; let _ARM64_SYSREG_TRCIDR2 = 0x8857;; -let _ARM64_SYSREG_TRCIDR3 = 0x885f;; +let _ARM64_SYSREG_TRCIDR3 = 0x885F;; let _ARM64_SYSREG_TRCIDR4 = 0x8867;; -let _ARM64_SYSREG_TRCIDR5 = 0x886f;; +let _ARM64_SYSREG_TRCIDR5 = 0x886F;; let _ARM64_SYSREG_TRCIDR6 = 0x8877;; -let _ARM64_SYSREG_TRCIDR7 = 0x887f;; -let _ARM64_SYSREG_TRCOSLSR = 0x888c;; -let _ARM64_SYSREG_TRCPDSR = 0x88ac;; -let _ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6;; -let _ARM64_SYSREG_TRCDEVAFF1 = 0x8bde;; -let _ARM64_SYSREG_TRCLSR = 0x8bee;; -let _ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6;; -let _ARM64_SYSREG_TRCDEVARCH = 0x8bfe;; -let _ARM64_SYSREG_TRCDEVID = 0x8b97;; -let _ARM64_SYSREG_TRCDEVTYPE = 0x8b9f;; -let _ARM64_SYSREG_TRCPIDR4 = 0x8ba7;; -let _ARM64_SYSREG_TRCPIDR5 = 0x8baf;; -let _ARM64_SYSREG_TRCPIDR6 = 0x8bb7;; -let _ARM64_SYSREG_TRCPIDR7 = 0x8bbf;; -let _ARM64_SYSREG_TRCPIDR0 = 0x8bc7;; -let _ARM64_SYSREG_TRCPIDR1 = 0x8bcf;; -let _ARM64_SYSREG_TRCPIDR2 = 0x8bd7;; -let _ARM64_SYSREG_TRCPIDR3 = 0x8bdf;; -let _ARM64_SYSREG_TRCCIDR0 = 0x8be7;; -let _ARM64_SYSREG_TRCCIDR1 = 0x8bef;; -let _ARM64_SYSREG_TRCCIDR2 = 0x8bf7;; -let _ARM64_SYSREG_TRCCIDR3 = 0x8bff;; -let _ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660;; -let _ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640;; -let _ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662;; -let _ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642;; -let _ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b;; -let _ARM64_SYSREG_ICH_VTR_EL2 = 0xe659;; -let _ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b;; -let _ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d;; +let _ARM64_SYSREG_TRCIDR7 = 0x887F;; +let _ARM64_SYSREG_TRCOSLSR = 0x888C;; +let _ARM64_SYSREG_TRCPDSR = 0x88AC;; +let _ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6;; +let _ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE;; +let _ARM64_SYSREG_TRCLSR = 0x8BEE;; +let _ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6;; +let _ARM64_SYSREG_TRCDEVARCH = 0x8BFE;; +let _ARM64_SYSREG_TRCDEVID = 0x8B97;; +let _ARM64_SYSREG_TRCDEVTYPE = 0x8B9F;; +let _ARM64_SYSREG_TRCPIDR4 = 0x8BA7;; +let _ARM64_SYSREG_TRCPIDR5 = 0x8BAF;; +let _ARM64_SYSREG_TRCPIDR6 = 0x8BB7;; +let _ARM64_SYSREG_TRCPIDR7 = 0x8BBF;; +let _ARM64_SYSREG_TRCPIDR0 = 0x8BC7;; +let _ARM64_SYSREG_TRCPIDR1 = 0x8BCF;; +let _ARM64_SYSREG_TRCPIDR2 = 0x8BD7;; +let _ARM64_SYSREG_TRCPIDR3 = 0x8BDF;; +let _ARM64_SYSREG_TRCCIDR0 = 0x8BE7;; +let _ARM64_SYSREG_TRCCIDR1 = 0x8BEF;; +let _ARM64_SYSREG_TRCCIDR2 = 0x8BF7;; +let _ARM64_SYSREG_TRCCIDR3 = 0x8BFF;; +let _ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660;; +let _ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640;; +let _ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662;; +let _ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642;; +let _ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B;; +let _ARM64_SYSREG_ICH_VTR_EL2 = 0xE659;; +let _ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B;; +let _ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D;; +let _ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024;; +let _ARM64_SYSREG_LORID_EL1 = 0xC527;; +let _ARM64_SYSREG_ERRIDR_EL1 = 0xC298;; +let _ARM64_SYSREG_ERXFR_EL1 = 0xC2A0;; +let _ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;; +let _ARM64_SYSREG_OSLAR_EL1 = 0x8084;; +let _ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4;; +let _ARM64_SYSREG_TRCOSLAR = 0x8884;; +let _ARM64_SYSREG_TRCLAR = 0x8BE6;; +let _ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661;; +let _ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641;; +let _ARM64_SYSREG_ICC_DIR_EL1 = 0xC659;; +let _ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D;; +let _ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E;; +let _ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F;; +let _ARM64_SYSREG_OSDTRRX_EL1 = 0x8002;; +let _ARM64_SYSREG_OSDTRTX_EL1 = 0x801A;; +let _ARM64_SYSREG_TEECR32_EL1 = 0x9000;; +let _ARM64_SYSREG_MDCCINT_EL1 = 0x8010;; +let _ARM64_SYSREG_MDSCR_EL1 = 0x8012;; +let _ARM64_SYSREG_DBGDTR_EL0 = 0x9820;; +let _ARM64_SYSREG_OSECCR_EL1 = 0x8032;; +let _ARM64_SYSREG_DBGVCR32_EL2 = 0xA038;; +let _ARM64_SYSREG_DBGBVR0_EL1 = 0x8004;; +let _ARM64_SYSREG_DBGBVR1_EL1 = 0x800C;; +let _ARM64_SYSREG_DBGBVR2_EL1 = 0x8014;; +let _ARM64_SYSREG_DBGBVR3_EL1 = 0x801C;; +let _ARM64_SYSREG_DBGBVR4_EL1 = 0x8024;; +let _ARM64_SYSREG_DBGBVR5_EL1 = 0x802C;; +let _ARM64_SYSREG_DBGBVR6_EL1 = 0x8034;; +let _ARM64_SYSREG_DBGBVR7_EL1 = 0x803C;; +let _ARM64_SYSREG_DBGBVR8_EL1 = 0x8044;; +let _ARM64_SYSREG_DBGBVR9_EL1 = 0x804C;; +let _ARM64_SYSREG_DBGBVR10_EL1 = 0x8054;; +let _ARM64_SYSREG_DBGBVR11_EL1 = 0x805C;; +let _ARM64_SYSREG_DBGBVR12_EL1 = 0x8064;; +let _ARM64_SYSREG_DBGBVR13_EL1 = 0x806C;; +let _ARM64_SYSREG_DBGBVR14_EL1 = 0x8074;; +let _ARM64_SYSREG_DBGBVR15_EL1 = 0x807C;; +let _ARM64_SYSREG_DBGBCR0_EL1 = 0x8005;; +let _ARM64_SYSREG_DBGBCR1_EL1 = 0x800D;; +let _ARM64_SYSREG_DBGBCR2_EL1 = 0x8015;; +let _ARM64_SYSREG_DBGBCR3_EL1 = 0x801D;; +let _ARM64_SYSREG_DBGBCR4_EL1 = 0x8025;; +let _ARM64_SYSREG_DBGBCR5_EL1 = 0x802D;; +let _ARM64_SYSREG_DBGBCR6_EL1 = 0x8035;; +let _ARM64_SYSREG_DBGBCR7_EL1 = 0x803D;; +let _ARM64_SYSREG_DBGBCR8_EL1 = 0x8045;; +let _ARM64_SYSREG_DBGBCR9_EL1 = 0x804D;; +let _ARM64_SYSREG_DBGBCR10_EL1 = 0x8055;; +let _ARM64_SYSREG_DBGBCR11_EL1 = 0x805D;; +let _ARM64_SYSREG_DBGBCR12_EL1 = 0x8065;; +let _ARM64_SYSREG_DBGBCR13_EL1 = 0x806D;; +let _ARM64_SYSREG_DBGBCR14_EL1 = 0x8075;; +let _ARM64_SYSREG_DBGBCR15_EL1 = 0x807D;; +let _ARM64_SYSREG_DBGWVR0_EL1 = 0x8006;; +let _ARM64_SYSREG_DBGWVR1_EL1 = 0x800E;; +let _ARM64_SYSREG_DBGWVR2_EL1 = 0x8016;; +let _ARM64_SYSREG_DBGWVR3_EL1 = 0x801E;; +let _ARM64_SYSREG_DBGWVR4_EL1 = 0x8026;; +let _ARM64_SYSREG_DBGWVR5_EL1 = 0x802E;; +let _ARM64_SYSREG_DBGWVR6_EL1 = 0x8036;; +let _ARM64_SYSREG_DBGWVR7_EL1 = 0x803E;; +let _ARM64_SYSREG_DBGWVR8_EL1 = 0x8046;; +let _ARM64_SYSREG_DBGWVR9_EL1 = 0x804E;; +let _ARM64_SYSREG_DBGWVR10_EL1 = 0x8056;; +let _ARM64_SYSREG_DBGWVR11_EL1 = 0x805E;; +let _ARM64_SYSREG_DBGWVR12_EL1 = 0x8066;; +let _ARM64_SYSREG_DBGWVR13_EL1 = 0x806E;; +let _ARM64_SYSREG_DBGWVR14_EL1 = 0x8076;; +let _ARM64_SYSREG_DBGWVR15_EL1 = 0x807E;; +let _ARM64_SYSREG_DBGWCR0_EL1 = 0x8007;; +let _ARM64_SYSREG_DBGWCR1_EL1 = 0x800F;; +let _ARM64_SYSREG_DBGWCR2_EL1 = 0x8017;; +let _ARM64_SYSREG_DBGWCR3_EL1 = 0x801F;; +let _ARM64_SYSREG_DBGWCR4_EL1 = 0x8027;; +let _ARM64_SYSREG_DBGWCR5_EL1 = 0x802F;; +let _ARM64_SYSREG_DBGWCR6_EL1 = 0x8037;; +let _ARM64_SYSREG_DBGWCR7_EL1 = 0x803F;; +let _ARM64_SYSREG_DBGWCR8_EL1 = 0x8047;; +let _ARM64_SYSREG_DBGWCR9_EL1 = 0x804F;; +let _ARM64_SYSREG_DBGWCR10_EL1 = 0x8057;; +let _ARM64_SYSREG_DBGWCR11_EL1 = 0x805F;; +let _ARM64_SYSREG_DBGWCR12_EL1 = 0x8067;; +let _ARM64_SYSREG_DBGWCR13_EL1 = 0x806F;; +let _ARM64_SYSREG_DBGWCR14_EL1 = 0x8077;; +let _ARM64_SYSREG_DBGWCR15_EL1 = 0x807F;; +let _ARM64_SYSREG_TEEHBR32_EL1 = 0x9080;; +let _ARM64_SYSREG_OSDLR_EL1 = 0x809C;; +let _ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4;; +let _ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6;; +let _ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE;; +let _ARM64_SYSREG_CSSELR_EL1 = 0xD000;; +let _ARM64_SYSREG_VPIDR_EL2 = 0xE000;; +let _ARM64_SYSREG_VMPIDR_EL2 = 0xE005;; +let _ARM64_SYSREG_CPACR_EL1 = 0xC082;; +let _ARM64_SYSREG_SCTLR_EL1 = 0xC080;; +let _ARM64_SYSREG_SCTLR_EL2 = 0xE080;; +let _ARM64_SYSREG_SCTLR_EL3 = 0xF080;; +let _ARM64_SYSREG_ACTLR_EL1 = 0xC081;; +let _ARM64_SYSREG_ACTLR_EL2 = 0xE081;; +let _ARM64_SYSREG_ACTLR_EL3 = 0xF081;; +let _ARM64_SYSREG_HCR_EL2 = 0xE088;; +let _ARM64_SYSREG_SCR_EL3 = 0xF088;; +let _ARM64_SYSREG_MDCR_EL2 = 0xE089;; +let _ARM64_SYSREG_SDER32_EL3 = 0xF089;; +let _ARM64_SYSREG_CPTR_EL2 = 0xE08A;; +let _ARM64_SYSREG_CPTR_EL3 = 0xF08A;; +let _ARM64_SYSREG_HSTR_EL2 = 0xE08B;; +let _ARM64_SYSREG_HACR_EL2 = 0xE08F;; +let _ARM64_SYSREG_MDCR_EL3 = 0xF099;; +let _ARM64_SYSREG_TTBR0_EL1 = 0xC100;; +let _ARM64_SYSREG_TTBR0_EL2 = 0xE100;; +let _ARM64_SYSREG_TTBR0_EL3 = 0xF100;; +let _ARM64_SYSREG_TTBR1_EL1 = 0xC101;; +let _ARM64_SYSREG_TCR_EL1 = 0xC102;; +let _ARM64_SYSREG_TCR_EL2 = 0xE102;; +let _ARM64_SYSREG_TCR_EL3 = 0xF102;; +let _ARM64_SYSREG_VTTBR_EL2 = 0xE108;; +let _ARM64_SYSREG_VTCR_EL2 = 0xE10A;; +let _ARM64_SYSREG_DACR32_EL2 = 0xE180;; +let _ARM64_SYSREG_SPSR_EL1 = 0xC200;; +let _ARM64_SYSREG_SPSR_EL2 = 0xE200;; +let _ARM64_SYSREG_SPSR_EL3 = 0xF200;; +let _ARM64_SYSREG_ELR_EL1 = 0xC201;; +let _ARM64_SYSREG_ELR_EL2 = 0xE201;; +let _ARM64_SYSREG_ELR_EL3 = 0xF201;; +let _ARM64_SYSREG_SP_EL0 = 0xC208;; +let _ARM64_SYSREG_SP_EL1 = 0xE208;; +let _ARM64_SYSREG_SP_EL2 = 0xF208;; +let _ARM64_SYSREG_SPSEL = 0xC210;; +let _ARM64_SYSREG_NZCV = 0xDA10;; +let _ARM64_SYSREG_DAIF = 0xDA11;; +let _ARM64_SYSREG_CURRENTEL = 0xC212;; +let _ARM64_SYSREG_SPSR_IRQ = 0xE218;; +let _ARM64_SYSREG_SPSR_ABT = 0xE219;; +let _ARM64_SYSREG_SPSR_UND = 0xE21A;; +let _ARM64_SYSREG_SPSR_FIQ = 0xE21B;; +let _ARM64_SYSREG_FPCR = 0xDA20;; +let _ARM64_SYSREG_FPSR = 0xDA21;; +let _ARM64_SYSREG_DSPSR_EL0 = 0xDA28;; +let _ARM64_SYSREG_DLR_EL0 = 0xDA29;; +let _ARM64_SYSREG_IFSR32_EL2 = 0xE281;; +let _ARM64_SYSREG_AFSR0_EL1 = 0xC288;; +let _ARM64_SYSREG_AFSR0_EL2 = 0xE288;; +let _ARM64_SYSREG_AFSR0_EL3 = 0xF288;; +let _ARM64_SYSREG_AFSR1_EL1 = 0xC289;; +let _ARM64_SYSREG_AFSR1_EL2 = 0xE289;; +let _ARM64_SYSREG_AFSR1_EL3 = 0xF289;; +let _ARM64_SYSREG_ESR_EL1 = 0xC290;; +let _ARM64_SYSREG_ESR_EL2 = 0xE290;; +let _ARM64_SYSREG_ESR_EL3 = 0xF290;; +let _ARM64_SYSREG_FPEXC32_EL2 = 0xE298;; +let _ARM64_SYSREG_FAR_EL1 = 0xC300;; +let _ARM64_SYSREG_FAR_EL2 = 0xE300;; +let _ARM64_SYSREG_FAR_EL3 = 0xF300;; +let _ARM64_SYSREG_HPFAR_EL2 = 0xE304;; +let _ARM64_SYSREG_PAR_EL1 = 0xC3A0;; +let _ARM64_SYSREG_PMCR_EL0 = 0xDCE0;; +let _ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1;; +let _ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2;; +let _ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3;; +let _ARM64_SYSREG_PMSELR_EL0 = 0xDCE5;; +let _ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8;; +let _ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9;; +let _ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA;; +let _ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0;; +let _ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1;; +let _ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2;; +let _ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3;; +let _ARM64_SYSREG_MAIR_EL1 = 0xC510;; +let _ARM64_SYSREG_MAIR_EL2 = 0xE510;; +let _ARM64_SYSREG_MAIR_EL3 = 0xF510;; +let _ARM64_SYSREG_AMAIR_EL1 = 0xC518;; +let _ARM64_SYSREG_AMAIR_EL2 = 0xE518;; +let _ARM64_SYSREG_AMAIR_EL3 = 0xF518;; +let _ARM64_SYSREG_VBAR_EL1 = 0xC600;; +let _ARM64_SYSREG_VBAR_EL2 = 0xE600;; +let _ARM64_SYSREG_VBAR_EL3 = 0xF600;; +let _ARM64_SYSREG_RMR_EL1 = 0xC602;; +let _ARM64_SYSREG_RMR_EL2 = 0xE602;; +let _ARM64_SYSREG_RMR_EL3 = 0xF602;; +let _ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681;; +let _ARM64_SYSREG_TPIDR_EL0 = 0xDE82;; +let _ARM64_SYSREG_TPIDR_EL2 = 0xE682;; +let _ARM64_SYSREG_TPIDR_EL3 = 0xF682;; +let _ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83;; +let _ARM64_SYSREG_TPIDR_EL1 = 0xC684;; +let _ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00;; +let _ARM64_SYSREG_CNTVOFF_EL2 = 0xE703;; +let _ARM64_SYSREG_CNTKCTL_EL1 = 0xC708;; +let _ARM64_SYSREG_CNTHCTL_EL2 = 0xE708;; +let _ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10;; +let _ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710;; +let _ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10;; +let _ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11;; +let _ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711;; +let _ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11;; +let _ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12;; +let _ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712;; +let _ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12;; +let _ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18;; +let _ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19;; +let _ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A;; +let _ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40;; +let _ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41;; +let _ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42;; +let _ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43;; +let _ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44;; +let _ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45;; +let _ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46;; +let _ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47;; +let _ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48;; +let _ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49;; +let _ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A;; +let _ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B;; +let _ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C;; +let _ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D;; +let _ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E;; +let _ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F;; +let _ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50;; +let _ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51;; +let _ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52;; +let _ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53;; +let _ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54;; +let _ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55;; +let _ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56;; +let _ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57;; +let _ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58;; +let _ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59;; +let _ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A;; +let _ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B;; +let _ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C;; +let _ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D;; +let _ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E;; +let _ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F;; +let _ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60;; +let _ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61;; +let _ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62;; +let _ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63;; +let _ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64;; +let _ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65;; +let _ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66;; +let _ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67;; +let _ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68;; +let _ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69;; +let _ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A;; +let _ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B;; +let _ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C;; +let _ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D;; +let _ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E;; +let _ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F;; +let _ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70;; +let _ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71;; +let _ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72;; +let _ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73;; +let _ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74;; +let _ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75;; +let _ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76;; +let _ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77;; +let _ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78;; +let _ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79;; +let _ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A;; +let _ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B;; +let _ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C;; +let _ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D;; +let _ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E;; +let _ARM64_SYSREG_TRCPRGCTLR = 0x8808;; +let _ARM64_SYSREG_TRCPROCSELR = 0x8810;; +let _ARM64_SYSREG_TRCCONFIGR = 0x8820;; +let _ARM64_SYSREG_TRCAUXCTLR = 0x8830;; +let _ARM64_SYSREG_TRCEVENTCTL0R = 0x8840;; +let _ARM64_SYSREG_TRCEVENTCTL1R = 0x8848;; +let _ARM64_SYSREG_TRCSTALLCTLR = 0x8858;; +let _ARM64_SYSREG_TRCTSCTLR = 0x8860;; +let _ARM64_SYSREG_TRCSYNCPR = 0x8868;; +let _ARM64_SYSREG_TRCCCCTLR = 0x8870;; +let _ARM64_SYSREG_TRCBBCTLR = 0x8878;; +let _ARM64_SYSREG_TRCTRACEIDR = 0x8801;; +let _ARM64_SYSREG_TRCQCTLR = 0x8809;; +let _ARM64_SYSREG_TRCVICTLR = 0x8802;; +let _ARM64_SYSREG_TRCVIIECTLR = 0x880A;; +let _ARM64_SYSREG_TRCVISSCTLR = 0x8812;; +let _ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A;; +let _ARM64_SYSREG_TRCVDCTLR = 0x8842;; +let _ARM64_SYSREG_TRCVDSACCTLR = 0x884A;; +let _ARM64_SYSREG_TRCVDARCCTLR = 0x8852;; +let _ARM64_SYSREG_TRCSEQEVR0 = 0x8804;; +let _ARM64_SYSREG_TRCSEQEVR1 = 0x880C;; +let _ARM64_SYSREG_TRCSEQEVR2 = 0x8814;; +let _ARM64_SYSREG_TRCSEQRSTEVR = 0x8834;; +let _ARM64_SYSREG_TRCSEQSTR = 0x883C;; +let _ARM64_SYSREG_TRCEXTINSELR = 0x8844;; +let _ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805;; +let _ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D;; +let _ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815;; +let _ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D;; +let _ARM64_SYSREG_TRCCNTCTLR0 = 0x8825;; +let _ARM64_SYSREG_TRCCNTCTLR1 = 0x882D;; +let _ARM64_SYSREG_TRCCNTCTLR2 = 0x8835;; +let _ARM64_SYSREG_TRCCNTCTLR3 = 0x883D;; +let _ARM64_SYSREG_TRCCNTVR0 = 0x8845;; +let _ARM64_SYSREG_TRCCNTVR1 = 0x884D;; +let _ARM64_SYSREG_TRCCNTVR2 = 0x8855;; +let _ARM64_SYSREG_TRCCNTVR3 = 0x885D;; +let _ARM64_SYSREG_TRCIMSPEC0 = 0x8807;; +let _ARM64_SYSREG_TRCIMSPEC1 = 0x880F;; +let _ARM64_SYSREG_TRCIMSPEC2 = 0x8817;; +let _ARM64_SYSREG_TRCIMSPEC3 = 0x881F;; +let _ARM64_SYSREG_TRCIMSPEC4 = 0x8827;; +let _ARM64_SYSREG_TRCIMSPEC5 = 0x882F;; +let _ARM64_SYSREG_TRCIMSPEC6 = 0x8837;; +let _ARM64_SYSREG_TRCIMSPEC7 = 0x883F;; +let _ARM64_SYSREG_TRCRSCTLR2 = 0x8890;; +let _ARM64_SYSREG_TRCRSCTLR3 = 0x8898;; +let _ARM64_SYSREG_TRCRSCTLR4 = 0x88A0;; +let _ARM64_SYSREG_TRCRSCTLR5 = 0x88A8;; +let _ARM64_SYSREG_TRCRSCTLR6 = 0x88B0;; +let _ARM64_SYSREG_TRCRSCTLR7 = 0x88B8;; +let _ARM64_SYSREG_TRCRSCTLR8 = 0x88C0;; +let _ARM64_SYSREG_TRCRSCTLR9 = 0x88C8;; +let _ARM64_SYSREG_TRCRSCTLR10 = 0x88D0;; +let _ARM64_SYSREG_TRCRSCTLR11 = 0x88D8;; +let _ARM64_SYSREG_TRCRSCTLR12 = 0x88E0;; +let _ARM64_SYSREG_TRCRSCTLR13 = 0x88E8;; +let _ARM64_SYSREG_TRCRSCTLR14 = 0x88F0;; +let _ARM64_SYSREG_TRCRSCTLR15 = 0x88F8;; +let _ARM64_SYSREG_TRCRSCTLR16 = 0x8881;; +let _ARM64_SYSREG_TRCRSCTLR17 = 0x8889;; +let _ARM64_SYSREG_TRCRSCTLR18 = 0x8891;; +let _ARM64_SYSREG_TRCRSCTLR19 = 0x8899;; +let _ARM64_SYSREG_TRCRSCTLR20 = 0x88A1;; +let _ARM64_SYSREG_TRCRSCTLR21 = 0x88A9;; +let _ARM64_SYSREG_TRCRSCTLR22 = 0x88B1;; +let _ARM64_SYSREG_TRCRSCTLR23 = 0x88B9;; +let _ARM64_SYSREG_TRCRSCTLR24 = 0x88C1;; +let _ARM64_SYSREG_TRCRSCTLR25 = 0x88C9;; +let _ARM64_SYSREG_TRCRSCTLR26 = 0x88D1;; +let _ARM64_SYSREG_TRCRSCTLR27 = 0x88D9;; +let _ARM64_SYSREG_TRCRSCTLR28 = 0x88E1;; +let _ARM64_SYSREG_TRCRSCTLR29 = 0x88E9;; +let _ARM64_SYSREG_TRCRSCTLR30 = 0x88F1;; +let _ARM64_SYSREG_TRCRSCTLR31 = 0x88F9;; +let _ARM64_SYSREG_TRCSSCCR0 = 0x8882;; +let _ARM64_SYSREG_TRCSSCCR1 = 0x888A;; +let _ARM64_SYSREG_TRCSSCCR2 = 0x8892;; +let _ARM64_SYSREG_TRCSSCCR3 = 0x889A;; +let _ARM64_SYSREG_TRCSSCCR4 = 0x88A2;; +let _ARM64_SYSREG_TRCSSCCR5 = 0x88AA;; +let _ARM64_SYSREG_TRCSSCCR6 = 0x88B2;; +let _ARM64_SYSREG_TRCSSCCR7 = 0x88BA;; +let _ARM64_SYSREG_TRCSSCSR0 = 0x88C2;; +let _ARM64_SYSREG_TRCSSCSR1 = 0x88CA;; +let _ARM64_SYSREG_TRCSSCSR2 = 0x88D2;; +let _ARM64_SYSREG_TRCSSCSR3 = 0x88DA;; +let _ARM64_SYSREG_TRCSSCSR4 = 0x88E2;; +let _ARM64_SYSREG_TRCSSCSR5 = 0x88EA;; +let _ARM64_SYSREG_TRCSSCSR6 = 0x88F2;; +let _ARM64_SYSREG_TRCSSCSR7 = 0x88FA;; +let _ARM64_SYSREG_TRCSSPCICR0 = 0x8883;; +let _ARM64_SYSREG_TRCSSPCICR1 = 0x888B;; +let _ARM64_SYSREG_TRCSSPCICR2 = 0x8893;; +let _ARM64_SYSREG_TRCSSPCICR3 = 0x889B;; +let _ARM64_SYSREG_TRCSSPCICR4 = 0x88A3;; +let _ARM64_SYSREG_TRCSSPCICR5 = 0x88AB;; +let _ARM64_SYSREG_TRCSSPCICR6 = 0x88B3;; +let _ARM64_SYSREG_TRCSSPCICR7 = 0x88BB;; +let _ARM64_SYSREG_TRCPDCR = 0x88A4;; +let _ARM64_SYSREG_TRCACVR0 = 0x8900;; +let _ARM64_SYSREG_TRCACVR1 = 0x8910;; +let _ARM64_SYSREG_TRCACVR2 = 0x8920;; +let _ARM64_SYSREG_TRCACVR3 = 0x8930;; +let _ARM64_SYSREG_TRCACVR4 = 0x8940;; +let _ARM64_SYSREG_TRCACVR5 = 0x8950;; +let _ARM64_SYSREG_TRCACVR6 = 0x8960;; +let _ARM64_SYSREG_TRCACVR7 = 0x8970;; +let _ARM64_SYSREG_TRCACVR8 = 0x8901;; +let _ARM64_SYSREG_TRCACVR9 = 0x8911;; +let _ARM64_SYSREG_TRCACVR10 = 0x8921;; +let _ARM64_SYSREG_TRCACVR11 = 0x8931;; +let _ARM64_SYSREG_TRCACVR12 = 0x8941;; +let _ARM64_SYSREG_TRCACVR13 = 0x8951;; +let _ARM64_SYSREG_TRCACVR14 = 0x8961;; +let _ARM64_SYSREG_TRCACVR15 = 0x8971;; +let _ARM64_SYSREG_TRCACATR0 = 0x8902;; +let _ARM64_SYSREG_TRCACATR1 = 0x8912;; +let _ARM64_SYSREG_TRCACATR2 = 0x8922;; +let _ARM64_SYSREG_TRCACATR3 = 0x8932;; +let _ARM64_SYSREG_TRCACATR4 = 0x8942;; +let _ARM64_SYSREG_TRCACATR5 = 0x8952;; +let _ARM64_SYSREG_TRCACATR6 = 0x8962;; +let _ARM64_SYSREG_TRCACATR7 = 0x8972;; +let _ARM64_SYSREG_TRCACATR8 = 0x8903;; +let _ARM64_SYSREG_TRCACATR9 = 0x8913;; +let _ARM64_SYSREG_TRCACATR10 = 0x8923;; +let _ARM64_SYSREG_TRCACATR11 = 0x8933;; +let _ARM64_SYSREG_TRCACATR12 = 0x8943;; +let _ARM64_SYSREG_TRCACATR13 = 0x8953;; +let _ARM64_SYSREG_TRCACATR14 = 0x8963;; +let _ARM64_SYSREG_TRCACATR15 = 0x8973;; +let _ARM64_SYSREG_TRCDVCVR0 = 0x8904;; +let _ARM64_SYSREG_TRCDVCVR1 = 0x8924;; +let _ARM64_SYSREG_TRCDVCVR2 = 0x8944;; +let _ARM64_SYSREG_TRCDVCVR3 = 0x8964;; +let _ARM64_SYSREG_TRCDVCVR4 = 0x8905;; +let _ARM64_SYSREG_TRCDVCVR5 = 0x8925;; +let _ARM64_SYSREG_TRCDVCVR6 = 0x8945;; +let _ARM64_SYSREG_TRCDVCVR7 = 0x8965;; +let _ARM64_SYSREG_TRCDVCMR0 = 0x8906;; +let _ARM64_SYSREG_TRCDVCMR1 = 0x8926;; +let _ARM64_SYSREG_TRCDVCMR2 = 0x8946;; +let _ARM64_SYSREG_TRCDVCMR3 = 0x8966;; +let _ARM64_SYSREG_TRCDVCMR4 = 0x8907;; +let _ARM64_SYSREG_TRCDVCMR5 = 0x8927;; +let _ARM64_SYSREG_TRCDVCMR6 = 0x8947;; +let _ARM64_SYSREG_TRCDVCMR7 = 0x8967;; +let _ARM64_SYSREG_TRCCIDCVR0 = 0x8980;; +let _ARM64_SYSREG_TRCCIDCVR1 = 0x8990;; +let _ARM64_SYSREG_TRCCIDCVR2 = 0x89A0;; +let _ARM64_SYSREG_TRCCIDCVR3 = 0x89B0;; +let _ARM64_SYSREG_TRCCIDCVR4 = 0x89C0;; +let _ARM64_SYSREG_TRCCIDCVR5 = 0x89D0;; +let _ARM64_SYSREG_TRCCIDCVR6 = 0x89E0;; +let _ARM64_SYSREG_TRCCIDCVR7 = 0x89F0;; +let _ARM64_SYSREG_TRCVMIDCVR0 = 0x8981;; +let _ARM64_SYSREG_TRCVMIDCVR1 = 0x8991;; +let _ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1;; +let _ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1;; +let _ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1;; +let _ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1;; +let _ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1;; +let _ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1;; +let _ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982;; +let _ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A;; +let _ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992;; +let _ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A;; +let _ARM64_SYSREG_TRCITCTRL = 0x8B84;; +let _ARM64_SYSREG_TRCCLAIMSET = 0x8BC6;; +let _ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE;; +let _ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663;; +let _ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643;; +let _ARM64_SYSREG_ICC_PMR_EL1 = 0xC230;; +let _ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664;; +let _ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664;; +let _ARM64_SYSREG_ICC_SRE_EL1 = 0xC665;; +let _ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D;; +let _ARM64_SYSREG_ICC_SRE_EL3 = 0xF665;; +let _ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666;; +let _ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667;; +let _ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667;; +let _ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668;; +let _ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644;; +let _ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645;; +let _ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646;; +let _ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647;; +let _ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648;; +let _ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649;; +let _ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A;; +let _ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B;; +let _ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640;; +let _ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641;; +let _ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642;; +let _ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643;; +let _ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648;; +let _ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649;; +let _ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A;; +let _ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B;; +let _ARM64_SYSREG_ICH_HCR_EL2 = 0xE658;; +let _ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A;; +let _ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F;; +let _ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C;; +let _ARM64_SYSREG_ICH_LR0_EL2 = 0xE660;; +let _ARM64_SYSREG_ICH_LR1_EL2 = 0xE661;; +let _ARM64_SYSREG_ICH_LR2_EL2 = 0xE662;; +let _ARM64_SYSREG_ICH_LR3_EL2 = 0xE663;; +let _ARM64_SYSREG_ICH_LR4_EL2 = 0xE664;; +let _ARM64_SYSREG_ICH_LR5_EL2 = 0xE665;; +let _ARM64_SYSREG_ICH_LR6_EL2 = 0xE666;; +let _ARM64_SYSREG_ICH_LR7_EL2 = 0xE667;; +let _ARM64_SYSREG_ICH_LR8_EL2 = 0xE668;; +let _ARM64_SYSREG_ICH_LR9_EL2 = 0xE669;; +let _ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A;; +let _ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B;; +let _ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C;; +let _ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D;; +let _ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E;; +let _ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F;; +let _ARM64_SYSREG_PAN = 0xC213;; +let _ARM64_SYSREG_LORSA_EL1 = 0xC520;; +let _ARM64_SYSREG_LOREA_EL1 = 0xC521;; +let _ARM64_SYSREG_LORN_EL1 = 0xC522;; +let _ARM64_SYSREG_LORC_EL1 = 0xC523;; +let _ARM64_SYSREG_TTBR1_EL2 = 0xE101;; +let _ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681;; +let _ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718;; +let _ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A;; +let _ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719;; +let _ARM64_SYSREG_SCTLR_EL12 = 0xE880;; +let _ARM64_SYSREG_CPACR_EL12 = 0xE882;; +let _ARM64_SYSREG_TTBR0_EL12 = 0xE900;; +let _ARM64_SYSREG_TTBR1_EL12 = 0xE901;; +let _ARM64_SYSREG_TCR_EL12 = 0xE902;; +let _ARM64_SYSREG_AFSR0_EL12 = 0xEA88;; +let _ARM64_SYSREG_AFSR1_EL12 = 0xEA89;; +let _ARM64_SYSREG_ESR_EL12 = 0xEA90;; +let _ARM64_SYSREG_FAR_EL12 = 0xEB00;; +let _ARM64_SYSREG_MAIR_EL12 = 0xED10;; +let _ARM64_SYSREG_AMAIR_EL12 = 0xED18;; +let _ARM64_SYSREG_VBAR_EL12 = 0xEE00;; +let _ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81;; +let _ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08;; +let _ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10;; +let _ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11;; +let _ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12;; +let _ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18;; +let _ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19;; +let _ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A;; +let _ARM64_SYSREG_SPSR_EL12 = 0xEA00;; +let _ARM64_SYSREG_ELR_EL12 = 0xEA01;; +let _ARM64_SYSREG_UAO = 0xC214;; +let _ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0;; +let _ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1;; +let _ARM64_SYSREG_PMBSR_EL1 = 0xC4D3;; +let _ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7;; +let _ARM64_SYSREG_PMSCR_EL2 = 0xE4C8;; +let _ARM64_SYSREG_PMSCR_EL12 = 0xECC8;; +let _ARM64_SYSREG_PMSCR_EL1 = 0xC4C8;; +let _ARM64_SYSREG_PMSICR_EL1 = 0xC4CA;; +let _ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB;; +let _ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC;; +let _ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD;; +let _ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE;; +let _ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF;; +let _ARM64_SYSREG_ERRSELR_EL1 = 0xC299;; +let _ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1;; +let _ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2;; +let _ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3;; +let _ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8;; +let _ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9;; +let _ARM64_SYSREG_DISR_EL1 = 0xC609;; +let _ARM64_SYSREG_VDISR_EL2 = 0xE609;; +let _ARM64_SYSREG_VSESR_EL2 = 0xE293;; +let _ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108;; +let _ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109;; +let _ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A;; +let _ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B;; +let _ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110;; +let _ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111;; +let _ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112;; +let _ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113;; +let _ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118;; +let _ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119;; +let _ARM64_SYSREG_VSTCR_EL2 = 0xE132;; +let _ARM64_SYSREG_VSTTBR_EL2 = 0xE130;; +let _ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720;; +let _ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722;; +let _ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721;; +let _ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728;; +let _ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A;; +let _ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729;; +let _ARM64_SYSREG_SDER32_EL2 = 0xE099;; +let _ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5;; +let _ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6;; +let _ARM64_SYSREG_ERXTS_EL1 = 0xC2AF;; +let _ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA;; +let _ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB;; +let _ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4;; +let _ARM64_SYSREG_MPAM0_EL1 = 0xC529;; +let _ARM64_SYSREG_MPAM1_EL1 = 0xC528;; +let _ARM64_SYSREG_MPAM2_EL2 = 0xE528;; +let _ARM64_SYSREG_MPAM3_EL3 = 0xF528;; +let _ARM64_SYSREG_MPAM1_EL12 = 0xED28;; +let _ARM64_SYSREG_MPAMHCR_EL2 = 0xE520;; +let _ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521;; +let _ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530;; +let _ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531;; +let _ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532;; +let _ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533;; +let _ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534;; +let _ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535;; +let _ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536;; +let _ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537;; +let _ARM64_SYSREG_MPAMIDR_EL1 = 0xC524;; +let _ARM64_SYSREG_AMCR_EL0 = 0xDE90;; +let _ARM64_SYSREG_AMCFGR_EL0 = 0xDE91;; +let _ARM64_SYSREG_AMCGCR_EL0 = 0xDE92;; +let _ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93;; +let _ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94;; +let _ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95;; +let _ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0;; +let _ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1;; +let _ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2;; +let _ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3;; +let _ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0;; +let _ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1;; +let _ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2;; +let _ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3;; +let _ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98;; +let _ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99;; +let _ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0;; +let _ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1;; +let _ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2;; +let _ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3;; +let _ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4;; +let _ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5;; +let _ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6;; +let _ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7;; +let _ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8;; +let _ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9;; +let _ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA;; +let _ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB;; +let _ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC;; +let _ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED;; +let _ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE;; +let _ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF;; +let _ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0;; +let _ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1;; +let _ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2;; +let _ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3;; +let _ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4;; +let _ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5;; +let _ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6;; +let _ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7;; +let _ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8;; +let _ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9;; +let _ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA;; +let _ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB;; +let _ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC;; +let _ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD;; +let _ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE;; +let _ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF;; +let _ARM64_SYSREG_TRFCR_EL1 = 0xC091;; +let _ARM64_SYSREG_TRFCR_EL2 = 0xE091;; +let _ARM64_SYSREG_TRFCR_EL12 = 0xE891;; +let _ARM64_SYSREG_DIT = 0xDA15;; +let _ARM64_SYSREG_VNCR_EL2 = 0xE110;; +let _ARM64_SYSREG_ZCR_EL1 = 0xC090;; +let _ARM64_SYSREG_ZCR_EL2 = 0xE090;; +let _ARM64_SYSREG_ZCR_EL3 = 0xF090;; +let _ARM64_SYSREG_ZCR_EL12 = 0xE890;; +let _ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90;; let _ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;; let _ARM64_SYSREG_OSLAR_EL1 = 0x8084;; let _ARM64_SYSREG_PMSWINC_EL0 = 0xdce4;; @@ -144,23 +789,25 @@ let _ARM64_PSTATE_INVALID = 0;; let _ARM64_PSTATE_SPSEL = 0x05;; let _ARM64_PSTATE_DAIFSET = 0x1e;; let _ARM64_PSTATE_DAIFCLR = 0x1f;; +let _ARM64_PSTATE_PAN = 0x4;; +let _ARM64_PSTATE_UAO = 0x3;; +let _ARM64_PSTATE_DIT = 0x1a;; let _ARM64_VAS_INVALID = 0;; -let _ARM64_VAS_8B = 1;; -let _ARM64_VAS_16B = 2;; -let _ARM64_VAS_4H = 3;; -let _ARM64_VAS_8H = 4;; -let _ARM64_VAS_2S = 5;; -let _ARM64_VAS_4S = 6;; -let _ARM64_VAS_1D = 7;; -let _ARM64_VAS_2D = 8;; -let _ARM64_VAS_1Q = 9;; - -let _ARM64_VESS_INVALID = 0;; -let _ARM64_VESS_B = 1;; -let _ARM64_VESS_H = 2;; -let _ARM64_VESS_S = 3;; -let _ARM64_VESS_D = 4;; +let _ARM64_VAS_16B = 1;; +let _ARM64_VAS_8B = 2;; +let _ARM64_VAS_4B = 3;; +let _ARM64_VAS_1B = 4;; +let _ARM64_VAS_8H = 5;; +let _ARM64_VAS_4H = 6;; +let _ARM64_VAS_2H = 7;; +let _ARM64_VAS_1H = 8;; +let _ARM64_VAS_4S = 9;; +let _ARM64_VAS_2S = 10;; +let _ARM64_VAS_1S = 11;; +let _ARM64_VAS_2D = 12;; +let _ARM64_VAS_1D = 13;; +let _ARM64_VAS_1Q = 14;; let _ARM64_BARRIER_INVALID = 0;; let _ARM64_BARRIER_OSHLD = 0x1;; @@ -190,50 +837,98 @@ let _ARM64_OP_PREFETCH = 69;; let _ARM64_OP_BARRIER = 70;; let _ARM64_TLBI_INVALID = 0;; -let _ARM64_TLBI_VMALLE1IS = 1;; -let _ARM64_TLBI_VAE1IS = 2;; -let _ARM64_TLBI_ASIDE1IS = 3;; -let _ARM64_TLBI_VAAE1IS = 4;; -let _ARM64_TLBI_VALE1IS = 5;; -let _ARM64_TLBI_VAALE1IS = 6;; -let _ARM64_TLBI_ALLE2IS = 7;; -let _ARM64_TLBI_VAE2IS = 8;; -let _ARM64_TLBI_ALLE1IS = 9;; -let _ARM64_TLBI_VALE2IS = 10;; -let _ARM64_TLBI_VMALLS12E1IS = 11;; -let _ARM64_TLBI_ALLE3IS = 12;; -let _ARM64_TLBI_VAE3IS = 13;; +let _ARM64_TLBI_IPAS2E1IS = 1;; +let _ARM64_TLBI_IPAS2LE1IS = 2;; +let _ARM64_TLBI_VMALLE1IS = 3;; +let _ARM64_TLBI_ALLE2IS = 4;; +let _ARM64_TLBI_ALLE3IS = 5;; +let _ARM64_TLBI_VAE1IS = 6;; +let _ARM64_TLBI_VAE2IS = 7;; +let _ARM64_TLBI_VAE3IS = 8;; +let _ARM64_TLBI_ASIDE1IS = 9;; +let _ARM64_TLBI_VAAE1IS = 10;; +let _ARM64_TLBI_ALLE1IS = 11;; +let _ARM64_TLBI_VALE1IS = 12;; +let _ARM64_TLBI_VALE2IS = 13;; let _ARM64_TLBI_VALE3IS = 14;; -let _ARM64_TLBI_IPAS2E1IS = 15;; -let _ARM64_TLBI_IPAS2LE1IS = 16;; +let _ARM64_TLBI_VMALLS12E1IS = 15;; +let _ARM64_TLBI_VAALE1IS = 16;; let _ARM64_TLBI_IPAS2E1 = 17;; let _ARM64_TLBI_IPAS2LE1 = 18;; let _ARM64_TLBI_VMALLE1 = 19;; -let _ARM64_TLBI_VAE1 = 20;; -let _ARM64_TLBI_ASIDE1 = 21;; -let _ARM64_TLBI_VAAE1 = 22;; -let _ARM64_TLBI_VALE1 = 23;; -let _ARM64_TLBI_VAALE1 = 24;; -let _ARM64_TLBI_ALLE2 = 25;; -let _ARM64_TLBI_VAE2 = 26;; +let _ARM64_TLBI_ALLE2 = 20;; +let _ARM64_TLBI_ALLE3 = 21;; +let _ARM64_TLBI_VAE1 = 22;; +let _ARM64_TLBI_VAE2 = 23;; +let _ARM64_TLBI_VAE3 = 24;; +let _ARM64_TLBI_ASIDE1 = 25;; +let _ARM64_TLBI_VAAE1 = 26;; let _ARM64_TLBI_ALLE1 = 27;; -let _ARM64_TLBI_VALE2 = 28;; -let _ARM64_TLBI_VMALLS12E1 = 29;; -let _ARM64_TLBI_ALLE3 = 30;; -let _ARM64_TLBI_VAE3 = 31;; -let _ARM64_TLBI_VALE3 = 32;; -let _ARM64_AT_S1E1R = 33;; -let _ARM64_AT_S1E1W = 34;; -let _ARM64_AT_S1E0R = 35;; -let _ARM64_AT_S1E0W = 36;; -let _ARM64_AT_S1E2R = 37;; -let _ARM64_AT_S1E2W = 38;; -let _ARM64_AT_S12E1R = 39;; -let _ARM64_AT_S12E1W = 40;; -let _ARM64_AT_S12E0R = 41;; -let _ARM64_AT_S12E0W = 42;; -let _ARM64_AT_S1E3R = 43;; -let _ARM64_AT_S1E3W = 44;; +let _ARM64_TLBI_VALE1 = 28;; +let _ARM64_TLBI_VALE2 = 29;; +let _ARM64_TLBI_VALE3 = 30;; +let _ARM64_TLBI_VMALLS12E1 = 31;; +let _ARM64_TLBI_VAALE1 = 32;; +let _ARM64_TLBI_VMALLE1OS = 33;; +let _ARM64_TLBI_VAE1OS = 34;; +let _ARM64_TLBI_ASIDE1OS = 35;; +let _ARM64_TLBI_VAAE1OS = 36;; +let _ARM64_TLBI_VALE1OS = 37;; +let _ARM64_TLBI_VAALE1OS = 38;; +let _ARM64_TLBI_IPAS2E1OS = 39;; +let _ARM64_TLBI_IPAS2LE1OS = 40;; +let _ARM64_TLBI_VAE2OS = 41;; +let _ARM64_TLBI_VALE2OS = 42;; +let _ARM64_TLBI_VMALLS12E1OS = 43;; +let _ARM64_TLBI_VAE3OS = 44;; +let _ARM64_TLBI_VALE3OS = 45;; +let _ARM64_TLBI_ALLE2OS = 46;; +let _ARM64_TLBI_ALLE1OS = 47;; +let _ARM64_TLBI_ALLE3OS = 48;; +let _ARM64_TLBI_RVAE1 = 49;; +let _ARM64_TLBI_RVAAE1 = 50;; +let _ARM64_TLBI_RVALE1 = 51;; +let _ARM64_TLBI_RVAALE1 = 52;; +let _ARM64_TLBI_RVAE1IS = 53;; +let _ARM64_TLBI_RVAAE1IS = 54;; +let _ARM64_TLBI_RVALE1IS = 55;; +let _ARM64_TLBI_RVAALE1IS = 56;; +let _ARM64_TLBI_RVAE1OS = 57;; +let _ARM64_TLBI_RVAAE1OS = 58;; +let _ARM64_TLBI_RVALE1OS = 59;; +let _ARM64_TLBI_RVAALE1OS = 60;; +let _ARM64_TLBI_RIPAS2E1IS = 61;; +let _ARM64_TLBI_RIPAS2LE1IS = 62;; +let _ARM64_TLBI_RIPAS2E1 = 63;; +let _ARM64_TLBI_RIPAS2LE1 = 64;; +let _ARM64_TLBI_RIPAS2E1OS = 65;; +let _ARM64_TLBI_RIPAS2LE1OS = 66;; +let _ARM64_TLBI_RVAE2 = 67;; +let _ARM64_TLBI_RVALE2 = 68;; +let _ARM64_TLBI_RVAE2IS = 69;; +let _ARM64_TLBI_RVALE2IS = 70;; +let _ARM64_TLBI_RVAE2OS = 71;; +let _ARM64_TLBI_RVALE2OS = 72;; +let _ARM64_TLBI_RVAE3 = 73;; +let _ARM64_TLBI_RVALE3 = 74;; +let _ARM64_TLBI_RVAE3IS = 75;; +let _ARM64_TLBI_RVALE3IS = 76;; +let _ARM64_TLBI_RVAE3OS = 77;; +let _ARM64_TLBI_RVALE3OS = 78;; +let _ARM64_AT_S1E1R = 79;; +let _ARM64_AT_S1E2R = 80;; +let _ARM64_AT_S1E3R = 81;; +let _ARM64_AT_S1E1W = 82;; +let _ARM64_AT_S1E2W = 83;; +let _ARM64_AT_S1E3W = 84;; +let _ARM64_AT_S1E0R = 85;; +let _ARM64_AT_S1E0W = 86;; +let _ARM64_AT_S12E1R = 87;; +let _ARM64_AT_S12E1W = 88;; +let _ARM64_AT_S12E0R = 89;; +let _ARM64_AT_S12E0W = 90;; +let _ARM64_AT_S1E1RP = 91;; +let _ARM64_AT_S1E1WP = 92;; let _ARM64_DC_INVALID = 0;; let _ARM64_DC_ZVA = 1;; @@ -244,6 +939,7 @@ let _ARM64_DC_CSW = 5;; let _ARM64_DC_CVAU = 6;; let _ARM64_DC_CIVAC = 7;; let _ARM64_DC_CISW = 8;; +let _ARM64_DC_CVAP = 9;; let _ARM64_IC_INVALID = 0;; let _ARM64_IC_IALLUIS = 1;; @@ -271,726 +967,1271 @@ let _ARM64_PRFM_PSTL3KEEP = 0x14+1;; let _ARM64_PRFM_PSTL3STRM = 0x15+1;; let _ARM64_REG_INVALID = 0;; -let _ARM64_REG_X29 = 1;; -let _ARM64_REG_X30 = 2;; -let _ARM64_REG_NZCV = 3;; -let _ARM64_REG_SP = 4;; -let _ARM64_REG_WSP = 5;; -let _ARM64_REG_WZR = 6;; -let _ARM64_REG_XZR = 7;; -let _ARM64_REG_B0 = 8;; -let _ARM64_REG_B1 = 9;; -let _ARM64_REG_B2 = 10;; -let _ARM64_REG_B3 = 11;; -let _ARM64_REG_B4 = 12;; -let _ARM64_REG_B5 = 13;; -let _ARM64_REG_B6 = 14;; -let _ARM64_REG_B7 = 15;; -let _ARM64_REG_B8 = 16;; -let _ARM64_REG_B9 = 17;; -let _ARM64_REG_B10 = 18;; -let _ARM64_REG_B11 = 19;; -let _ARM64_REG_B12 = 20;; -let _ARM64_REG_B13 = 21;; -let _ARM64_REG_B14 = 22;; -let _ARM64_REG_B15 = 23;; -let _ARM64_REG_B16 = 24;; -let _ARM64_REG_B17 = 25;; -let _ARM64_REG_B18 = 26;; -let _ARM64_REG_B19 = 27;; -let _ARM64_REG_B20 = 28;; -let _ARM64_REG_B21 = 29;; -let _ARM64_REG_B22 = 30;; -let _ARM64_REG_B23 = 31;; -let _ARM64_REG_B24 = 32;; -let _ARM64_REG_B25 = 33;; -let _ARM64_REG_B26 = 34;; -let _ARM64_REG_B27 = 35;; -let _ARM64_REG_B28 = 36;; -let _ARM64_REG_B29 = 37;; -let _ARM64_REG_B30 = 38;; -let _ARM64_REG_B31 = 39;; -let _ARM64_REG_D0 = 40;; -let _ARM64_REG_D1 = 41;; -let _ARM64_REG_D2 = 42;; -let _ARM64_REG_D3 = 43;; -let _ARM64_REG_D4 = 44;; -let _ARM64_REG_D5 = 45;; -let _ARM64_REG_D6 = 46;; -let _ARM64_REG_D7 = 47;; -let _ARM64_REG_D8 = 48;; -let _ARM64_REG_D9 = 49;; -let _ARM64_REG_D10 = 50;; -let _ARM64_REG_D11 = 51;; -let _ARM64_REG_D12 = 52;; -let _ARM64_REG_D13 = 53;; -let _ARM64_REG_D14 = 54;; -let _ARM64_REG_D15 = 55;; -let _ARM64_REG_D16 = 56;; -let _ARM64_REG_D17 = 57;; -let _ARM64_REG_D18 = 58;; -let _ARM64_REG_D19 = 59;; -let _ARM64_REG_D20 = 60;; -let _ARM64_REG_D21 = 61;; -let _ARM64_REG_D22 = 62;; -let _ARM64_REG_D23 = 63;; -let _ARM64_REG_D24 = 64;; -let _ARM64_REG_D25 = 65;; -let _ARM64_REG_D26 = 66;; -let _ARM64_REG_D27 = 67;; -let _ARM64_REG_D28 = 68;; -let _ARM64_REG_D29 = 69;; -let _ARM64_REG_D30 = 70;; -let _ARM64_REG_D31 = 71;; -let _ARM64_REG_H0 = 72;; -let _ARM64_REG_H1 = 73;; -let _ARM64_REG_H2 = 74;; -let _ARM64_REG_H3 = 75;; -let _ARM64_REG_H4 = 76;; -let _ARM64_REG_H5 = 77;; -let _ARM64_REG_H6 = 78;; -let _ARM64_REG_H7 = 79;; -let _ARM64_REG_H8 = 80;; -let _ARM64_REG_H9 = 81;; -let _ARM64_REG_H10 = 82;; -let _ARM64_REG_H11 = 83;; -let _ARM64_REG_H12 = 84;; -let _ARM64_REG_H13 = 85;; -let _ARM64_REG_H14 = 86;; -let _ARM64_REG_H15 = 87;; -let _ARM64_REG_H16 = 88;; -let _ARM64_REG_H17 = 89;; -let _ARM64_REG_H18 = 90;; -let _ARM64_REG_H19 = 91;; -let _ARM64_REG_H20 = 92;; -let _ARM64_REG_H21 = 93;; -let _ARM64_REG_H22 = 94;; -let _ARM64_REG_H23 = 95;; -let _ARM64_REG_H24 = 96;; -let _ARM64_REG_H25 = 97;; -let _ARM64_REG_H26 = 98;; -let _ARM64_REG_H27 = 99;; -let _ARM64_REG_H28 = 100;; -let _ARM64_REG_H29 = 101;; -let _ARM64_REG_H30 = 102;; -let _ARM64_REG_H31 = 103;; -let _ARM64_REG_Q0 = 104;; -let _ARM64_REG_Q1 = 105;; -let _ARM64_REG_Q2 = 106;; -let _ARM64_REG_Q3 = 107;; -let _ARM64_REG_Q4 = 108;; -let _ARM64_REG_Q5 = 109;; -let _ARM64_REG_Q6 = 110;; -let _ARM64_REG_Q7 = 111;; -let _ARM64_REG_Q8 = 112;; -let _ARM64_REG_Q9 = 113;; -let _ARM64_REG_Q10 = 114;; -let _ARM64_REG_Q11 = 115;; -let _ARM64_REG_Q12 = 116;; -let _ARM64_REG_Q13 = 117;; -let _ARM64_REG_Q14 = 118;; -let _ARM64_REG_Q15 = 119;; -let _ARM64_REG_Q16 = 120;; -let _ARM64_REG_Q17 = 121;; -let _ARM64_REG_Q18 = 122;; -let _ARM64_REG_Q19 = 123;; -let _ARM64_REG_Q20 = 124;; -let _ARM64_REG_Q21 = 125;; -let _ARM64_REG_Q22 = 126;; -let _ARM64_REG_Q23 = 127;; -let _ARM64_REG_Q24 = 128;; -let _ARM64_REG_Q25 = 129;; -let _ARM64_REG_Q26 = 130;; -let _ARM64_REG_Q27 = 131;; -let _ARM64_REG_Q28 = 132;; -let _ARM64_REG_Q29 = 133;; -let _ARM64_REG_Q30 = 134;; -let _ARM64_REG_Q31 = 135;; -let _ARM64_REG_S0 = 136;; -let _ARM64_REG_S1 = 137;; -let _ARM64_REG_S2 = 138;; -let _ARM64_REG_S3 = 139;; -let _ARM64_REG_S4 = 140;; -let _ARM64_REG_S5 = 141;; -let _ARM64_REG_S6 = 142;; -let _ARM64_REG_S7 = 143;; -let _ARM64_REG_S8 = 144;; -let _ARM64_REG_S9 = 145;; -let _ARM64_REG_S10 = 146;; -let _ARM64_REG_S11 = 147;; -let _ARM64_REG_S12 = 148;; -let _ARM64_REG_S13 = 149;; -let _ARM64_REG_S14 = 150;; -let _ARM64_REG_S15 = 151;; -let _ARM64_REG_S16 = 152;; -let _ARM64_REG_S17 = 153;; -let _ARM64_REG_S18 = 154;; -let _ARM64_REG_S19 = 155;; -let _ARM64_REG_S20 = 156;; -let _ARM64_REG_S21 = 157;; -let _ARM64_REG_S22 = 158;; -let _ARM64_REG_S23 = 159;; -let _ARM64_REG_S24 = 160;; -let _ARM64_REG_S25 = 161;; -let _ARM64_REG_S26 = 162;; -let _ARM64_REG_S27 = 163;; -let _ARM64_REG_S28 = 164;; -let _ARM64_REG_S29 = 165;; -let _ARM64_REG_S30 = 166;; -let _ARM64_REG_S31 = 167;; -let _ARM64_REG_W0 = 168;; -let _ARM64_REG_W1 = 169;; -let _ARM64_REG_W2 = 170;; -let _ARM64_REG_W3 = 171;; -let _ARM64_REG_W4 = 172;; -let _ARM64_REG_W5 = 173;; -let _ARM64_REG_W6 = 174;; -let _ARM64_REG_W7 = 175;; -let _ARM64_REG_W8 = 176;; -let _ARM64_REG_W9 = 177;; -let _ARM64_REG_W10 = 178;; -let _ARM64_REG_W11 = 179;; -let _ARM64_REG_W12 = 180;; -let _ARM64_REG_W13 = 181;; -let _ARM64_REG_W14 = 182;; -let _ARM64_REG_W15 = 183;; -let _ARM64_REG_W16 = 184;; -let _ARM64_REG_W17 = 185;; -let _ARM64_REG_W18 = 186;; -let _ARM64_REG_W19 = 187;; -let _ARM64_REG_W20 = 188;; -let _ARM64_REG_W21 = 189;; -let _ARM64_REG_W22 = 190;; -let _ARM64_REG_W23 = 191;; -let _ARM64_REG_W24 = 192;; -let _ARM64_REG_W25 = 193;; -let _ARM64_REG_W26 = 194;; -let _ARM64_REG_W27 = 195;; -let _ARM64_REG_W28 = 196;; -let _ARM64_REG_W29 = 197;; -let _ARM64_REG_W30 = 198;; -let _ARM64_REG_X0 = 199;; -let _ARM64_REG_X1 = 200;; -let _ARM64_REG_X2 = 201;; -let _ARM64_REG_X3 = 202;; -let _ARM64_REG_X4 = 203;; -let _ARM64_REG_X5 = 204;; -let _ARM64_REG_X6 = 205;; -let _ARM64_REG_X7 = 206;; -let _ARM64_REG_X8 = 207;; -let _ARM64_REG_X9 = 208;; -let _ARM64_REG_X10 = 209;; -let _ARM64_REG_X11 = 210;; -let _ARM64_REG_X12 = 211;; -let _ARM64_REG_X13 = 212;; -let _ARM64_REG_X14 = 213;; -let _ARM64_REG_X15 = 214;; -let _ARM64_REG_X16 = 215;; -let _ARM64_REG_X17 = 216;; -let _ARM64_REG_X18 = 217;; -let _ARM64_REG_X19 = 218;; -let _ARM64_REG_X20 = 219;; -let _ARM64_REG_X21 = 220;; -let _ARM64_REG_X22 = 221;; -let _ARM64_REG_X23 = 222;; -let _ARM64_REG_X24 = 223;; -let _ARM64_REG_X25 = 224;; -let _ARM64_REG_X26 = 225;; -let _ARM64_REG_X27 = 226;; -let _ARM64_REG_X28 = 227;; -let _ARM64_REG_V0 = 228;; -let _ARM64_REG_V1 = 229;; -let _ARM64_REG_V2 = 230;; -let _ARM64_REG_V3 = 231;; -let _ARM64_REG_V4 = 232;; -let _ARM64_REG_V5 = 233;; -let _ARM64_REG_V6 = 234;; -let _ARM64_REG_V7 = 235;; -let _ARM64_REG_V8 = 236;; -let _ARM64_REG_V9 = 237;; -let _ARM64_REG_V10 = 238;; -let _ARM64_REG_V11 = 239;; -let _ARM64_REG_V12 = 240;; -let _ARM64_REG_V13 = 241;; -let _ARM64_REG_V14 = 242;; -let _ARM64_REG_V15 = 243;; -let _ARM64_REG_V16 = 244;; -let _ARM64_REG_V17 = 245;; -let _ARM64_REG_V18 = 246;; -let _ARM64_REG_V19 = 247;; -let _ARM64_REG_V20 = 248;; -let _ARM64_REG_V21 = 249;; -let _ARM64_REG_V22 = 250;; -let _ARM64_REG_V23 = 251;; -let _ARM64_REG_V24 = 252;; -let _ARM64_REG_V25 = 253;; -let _ARM64_REG_V26 = 254;; -let _ARM64_REG_V27 = 255;; -let _ARM64_REG_V28 = 256;; -let _ARM64_REG_V29 = 257;; -let _ARM64_REG_V30 = 258;; -let _ARM64_REG_V31 = 259;; -let _ARM64_REG_ENDING = 260;; +let _ARM64_REG_FFR = 1;; +let _ARM64_REG_FP = 2;; +let _ARM64_REG_LR = 3;; +let _ARM64_REG_NZCV = 4;; +let _ARM64_REG_SP = 5;; +let _ARM64_REG_WSP = 6;; +let _ARM64_REG_WZR = 7;; +let _ARM64_REG_XZR = 8;; +let _ARM64_REG_B0 = 9;; +let _ARM64_REG_B1 = 10;; +let _ARM64_REG_B2 = 11;; +let _ARM64_REG_B3 = 12;; +let _ARM64_REG_B4 = 13;; +let _ARM64_REG_B5 = 14;; +let _ARM64_REG_B6 = 15;; +let _ARM64_REG_B7 = 16;; +let _ARM64_REG_B8 = 17;; +let _ARM64_REG_B9 = 18;; +let _ARM64_REG_B10 = 19;; +let _ARM64_REG_B11 = 20;; +let _ARM64_REG_B12 = 21;; +let _ARM64_REG_B13 = 22;; +let _ARM64_REG_B14 = 23;; +let _ARM64_REG_B15 = 24;; +let _ARM64_REG_B16 = 25;; +let _ARM64_REG_B17 = 26;; +let _ARM64_REG_B18 = 27;; +let _ARM64_REG_B19 = 28;; +let _ARM64_REG_B20 = 29;; +let _ARM64_REG_B21 = 30;; +let _ARM64_REG_B22 = 31;; +let _ARM64_REG_B23 = 32;; +let _ARM64_REG_B24 = 33;; +let _ARM64_REG_B25 = 34;; +let _ARM64_REG_B26 = 35;; +let _ARM64_REG_B27 = 36;; +let _ARM64_REG_B28 = 37;; +let _ARM64_REG_B29 = 38;; +let _ARM64_REG_B30 = 39;; +let _ARM64_REG_B31 = 40;; +let _ARM64_REG_D0 = 41;; +let _ARM64_REG_D1 = 42;; +let _ARM64_REG_D2 = 43;; +let _ARM64_REG_D3 = 44;; +let _ARM64_REG_D4 = 45;; +let _ARM64_REG_D5 = 46;; +let _ARM64_REG_D6 = 47;; +let _ARM64_REG_D7 = 48;; +let _ARM64_REG_D8 = 49;; +let _ARM64_REG_D9 = 50;; +let _ARM64_REG_D10 = 51;; +let _ARM64_REG_D11 = 52;; +let _ARM64_REG_D12 = 53;; +let _ARM64_REG_D13 = 54;; +let _ARM64_REG_D14 = 55;; +let _ARM64_REG_D15 = 56;; +let _ARM64_REG_D16 = 57;; +let _ARM64_REG_D17 = 58;; +let _ARM64_REG_D18 = 59;; +let _ARM64_REG_D19 = 60;; +let _ARM64_REG_D20 = 61;; +let _ARM64_REG_D21 = 62;; +let _ARM64_REG_D22 = 63;; +let _ARM64_REG_D23 = 64;; +let _ARM64_REG_D24 = 65;; +let _ARM64_REG_D25 = 66;; +let _ARM64_REG_D26 = 67;; +let _ARM64_REG_D27 = 68;; +let _ARM64_REG_D28 = 69;; +let _ARM64_REG_D29 = 70;; +let _ARM64_REG_D30 = 71;; +let _ARM64_REG_D31 = 72;; +let _ARM64_REG_H0 = 73;; +let _ARM64_REG_H1 = 74;; +let _ARM64_REG_H2 = 75;; +let _ARM64_REG_H3 = 76;; +let _ARM64_REG_H4 = 77;; +let _ARM64_REG_H5 = 78;; +let _ARM64_REG_H6 = 79;; +let _ARM64_REG_H7 = 80;; +let _ARM64_REG_H8 = 81;; +let _ARM64_REG_H9 = 82;; +let _ARM64_REG_H10 = 83;; +let _ARM64_REG_H11 = 84;; +let _ARM64_REG_H12 = 85;; +let _ARM64_REG_H13 = 86;; +let _ARM64_REG_H14 = 87;; +let _ARM64_REG_H15 = 88;; +let _ARM64_REG_H16 = 89;; +let _ARM64_REG_H17 = 90;; +let _ARM64_REG_H18 = 91;; +let _ARM64_REG_H19 = 92;; +let _ARM64_REG_H20 = 93;; +let _ARM64_REG_H21 = 94;; +let _ARM64_REG_H22 = 95;; +let _ARM64_REG_H23 = 96;; +let _ARM64_REG_H24 = 97;; +let _ARM64_REG_H25 = 98;; +let _ARM64_REG_H26 = 99;; +let _ARM64_REG_H27 = 100;; +let _ARM64_REG_H28 = 101;; +let _ARM64_REG_H29 = 102;; +let _ARM64_REG_H30 = 103;; +let _ARM64_REG_H31 = 104;; +let _ARM64_REG_P0 = 105;; +let _ARM64_REG_P1 = 106;; +let _ARM64_REG_P2 = 107;; +let _ARM64_REG_P3 = 108;; +let _ARM64_REG_P4 = 109;; +let _ARM64_REG_P5 = 110;; +let _ARM64_REG_P6 = 111;; +let _ARM64_REG_P7 = 112;; +let _ARM64_REG_P8 = 113;; +let _ARM64_REG_P9 = 114;; +let _ARM64_REG_P10 = 115;; +let _ARM64_REG_P11 = 116;; +let _ARM64_REG_P12 = 117;; +let _ARM64_REG_P13 = 118;; +let _ARM64_REG_P14 = 119;; +let _ARM64_REG_P15 = 120;; +let _ARM64_REG_Q0 = 121;; +let _ARM64_REG_Q1 = 122;; +let _ARM64_REG_Q2 = 123;; +let _ARM64_REG_Q3 = 124;; +let _ARM64_REG_Q4 = 125;; +let _ARM64_REG_Q5 = 126;; +let _ARM64_REG_Q6 = 127;; +let _ARM64_REG_Q7 = 128;; +let _ARM64_REG_Q8 = 129;; +let _ARM64_REG_Q9 = 130;; +let _ARM64_REG_Q10 = 131;; +let _ARM64_REG_Q11 = 132;; +let _ARM64_REG_Q12 = 133;; +let _ARM64_REG_Q13 = 134;; +let _ARM64_REG_Q14 = 135;; +let _ARM64_REG_Q15 = 136;; +let _ARM64_REG_Q16 = 137;; +let _ARM64_REG_Q17 = 138;; +let _ARM64_REG_Q18 = 139;; +let _ARM64_REG_Q19 = 140;; +let _ARM64_REG_Q20 = 141;; +let _ARM64_REG_Q21 = 142;; +let _ARM64_REG_Q22 = 143;; +let _ARM64_REG_Q23 = 144;; +let _ARM64_REG_Q24 = 145;; +let _ARM64_REG_Q25 = 146;; +let _ARM64_REG_Q26 = 147;; +let _ARM64_REG_Q27 = 148;; +let _ARM64_REG_Q28 = 149;; +let _ARM64_REG_Q29 = 150;; +let _ARM64_REG_Q30 = 151;; +let _ARM64_REG_Q31 = 152;; +let _ARM64_REG_S0 = 153;; +let _ARM64_REG_S1 = 154;; +let _ARM64_REG_S2 = 155;; +let _ARM64_REG_S3 = 156;; +let _ARM64_REG_S4 = 157;; +let _ARM64_REG_S5 = 158;; +let _ARM64_REG_S6 = 159;; +let _ARM64_REG_S7 = 160;; +let _ARM64_REG_S8 = 161;; +let _ARM64_REG_S9 = 162;; +let _ARM64_REG_S10 = 163;; +let _ARM64_REG_S11 = 164;; +let _ARM64_REG_S12 = 165;; +let _ARM64_REG_S13 = 166;; +let _ARM64_REG_S14 = 167;; +let _ARM64_REG_S15 = 168;; +let _ARM64_REG_S16 = 169;; +let _ARM64_REG_S17 = 170;; +let _ARM64_REG_S18 = 171;; +let _ARM64_REG_S19 = 172;; +let _ARM64_REG_S20 = 173;; +let _ARM64_REG_S21 = 174;; +let _ARM64_REG_S22 = 175;; +let _ARM64_REG_S23 = 176;; +let _ARM64_REG_S24 = 177;; +let _ARM64_REG_S25 = 178;; +let _ARM64_REG_S26 = 179;; +let _ARM64_REG_S27 = 180;; +let _ARM64_REG_S28 = 181;; +let _ARM64_REG_S29 = 182;; +let _ARM64_REG_S30 = 183;; +let _ARM64_REG_S31 = 184;; +let _ARM64_REG_W0 = 185;; +let _ARM64_REG_W1 = 186;; +let _ARM64_REG_W2 = 187;; +let _ARM64_REG_W3 = 188;; +let _ARM64_REG_W4 = 189;; +let _ARM64_REG_W5 = 190;; +let _ARM64_REG_W6 = 191;; +let _ARM64_REG_W7 = 192;; +let _ARM64_REG_W8 = 193;; +let _ARM64_REG_W9 = 194;; +let _ARM64_REG_W10 = 195;; +let _ARM64_REG_W11 = 196;; +let _ARM64_REG_W12 = 197;; +let _ARM64_REG_W13 = 198;; +let _ARM64_REG_W14 = 199;; +let _ARM64_REG_W15 = 200;; +let _ARM64_REG_W16 = 201;; +let _ARM64_REG_W17 = 202;; +let _ARM64_REG_W18 = 203;; +let _ARM64_REG_W19 = 204;; +let _ARM64_REG_W20 = 205;; +let _ARM64_REG_W21 = 206;; +let _ARM64_REG_W22 = 207;; +let _ARM64_REG_W23 = 208;; +let _ARM64_REG_W24 = 209;; +let _ARM64_REG_W25 = 210;; +let _ARM64_REG_W26 = 211;; +let _ARM64_REG_W27 = 212;; +let _ARM64_REG_W28 = 213;; +let _ARM64_REG_W29 = 214;; +let _ARM64_REG_W30 = 215;; +let _ARM64_REG_X0 = 216;; +let _ARM64_REG_X1 = 217;; +let _ARM64_REG_X2 = 218;; +let _ARM64_REG_X3 = 219;; +let _ARM64_REG_X4 = 220;; +let _ARM64_REG_X5 = 221;; +let _ARM64_REG_X6 = 222;; +let _ARM64_REG_X7 = 223;; +let _ARM64_REG_X8 = 224;; +let _ARM64_REG_X9 = 225;; +let _ARM64_REG_X10 = 226;; +let _ARM64_REG_X11 = 227;; +let _ARM64_REG_X12 = 228;; +let _ARM64_REG_X13 = 229;; +let _ARM64_REG_X14 = 230;; +let _ARM64_REG_X15 = 231;; +let _ARM64_REG_X16 = 232;; +let _ARM64_REG_X17 = 233;; +let _ARM64_REG_X18 = 234;; +let _ARM64_REG_X19 = 235;; +let _ARM64_REG_X20 = 236;; +let _ARM64_REG_X21 = 237;; +let _ARM64_REG_X22 = 238;; +let _ARM64_REG_X23 = 239;; +let _ARM64_REG_X24 = 240;; +let _ARM64_REG_X25 = 241;; +let _ARM64_REG_X26 = 242;; +let _ARM64_REG_X27 = 243;; +let _ARM64_REG_X28 = 244;; +let _ARM64_REG_Z0 = 245;; +let _ARM64_REG_Z1 = 246;; +let _ARM64_REG_Z2 = 247;; +let _ARM64_REG_Z3 = 248;; +let _ARM64_REG_Z4 = 249;; +let _ARM64_REG_Z5 = 250;; +let _ARM64_REG_Z6 = 251;; +let _ARM64_REG_Z7 = 252;; +let _ARM64_REG_Z8 = 253;; +let _ARM64_REG_Z9 = 254;; +let _ARM64_REG_Z10 = 255;; +let _ARM64_REG_Z11 = 256;; +let _ARM64_REG_Z12 = 257;; +let _ARM64_REG_Z13 = 258;; +let _ARM64_REG_Z14 = 259;; +let _ARM64_REG_Z15 = 260;; +let _ARM64_REG_Z16 = 261;; +let _ARM64_REG_Z17 = 262;; +let _ARM64_REG_Z18 = 263;; +let _ARM64_REG_Z19 = 264;; +let _ARM64_REG_Z20 = 265;; +let _ARM64_REG_Z21 = 266;; +let _ARM64_REG_Z22 = 267;; +let _ARM64_REG_Z23 = 268;; +let _ARM64_REG_Z24 = 269;; +let _ARM64_REG_Z25 = 270;; +let _ARM64_REG_Z26 = 271;; +let _ARM64_REG_Z27 = 272;; +let _ARM64_REG_Z28 = 273;; +let _ARM64_REG_Z29 = 274;; +let _ARM64_REG_Z30 = 275;; +let _ARM64_REG_Z31 = 276;; +let _ARM64_REG_V0 = 277;; +let _ARM64_REG_V1 = 278;; +let _ARM64_REG_V2 = 279;; +let _ARM64_REG_V3 = 280;; +let _ARM64_REG_V4 = 281;; +let _ARM64_REG_V5 = 282;; +let _ARM64_REG_V6 = 283;; +let _ARM64_REG_V7 = 284;; +let _ARM64_REG_V8 = 285;; +let _ARM64_REG_V9 = 286;; +let _ARM64_REG_V10 = 287;; +let _ARM64_REG_V11 = 288;; +let _ARM64_REG_V12 = 289;; +let _ARM64_REG_V13 = 290;; +let _ARM64_REG_V14 = 291;; +let _ARM64_REG_V15 = 292;; +let _ARM64_REG_V16 = 293;; +let _ARM64_REG_V17 = 294;; +let _ARM64_REG_V18 = 295;; +let _ARM64_REG_V19 = 296;; +let _ARM64_REG_V20 = 297;; +let _ARM64_REG_V21 = 298;; +let _ARM64_REG_V22 = 299;; +let _ARM64_REG_V23 = 300;; +let _ARM64_REG_V24 = 301;; +let _ARM64_REG_V25 = 302;; +let _ARM64_REG_V26 = 303;; +let _ARM64_REG_V27 = 304;; +let _ARM64_REG_V28 = 305;; +let _ARM64_REG_V29 = 306;; +let _ARM64_REG_V30 = 307;; +let _ARM64_REG_V31 = 308;; +let _ARM64_REG_ENDING = 309;; let _ARM64_REG_IP0 = _ARM64_REG_X16;; let _ARM64_REG_IP1 = _ARM64_REG_X17;; -let _ARM64_REG_FP = _ARM64_REG_X29;; -let _ARM64_REG_LR = _ARM64_REG_X30;; +let _ARM64_REG_X29 = _ARM64_REG_FP;; +let _ARM64_REG_X30 = _ARM64_REG_LR;; let _ARM64_INS_INVALID = 0;; let _ARM64_INS_ABS = 1;; let _ARM64_INS_ADC = 2;; -let _ARM64_INS_ADDHN = 3;; -let _ARM64_INS_ADDHN2 = 4;; -let _ARM64_INS_ADDP = 5;; -let _ARM64_INS_ADD = 6;; -let _ARM64_INS_ADDV = 7;; -let _ARM64_INS_ADR = 8;; -let _ARM64_INS_ADRP = 9;; -let _ARM64_INS_AESD = 10;; -let _ARM64_INS_AESE = 11;; -let _ARM64_INS_AESIMC = 12;; -let _ARM64_INS_AESMC = 13;; -let _ARM64_INS_AND = 14;; -let _ARM64_INS_ASR = 15;; -let _ARM64_INS_B = 16;; -let _ARM64_INS_BFM = 17;; -let _ARM64_INS_BIC = 18;; -let _ARM64_INS_BIF = 19;; -let _ARM64_INS_BIT = 20;; -let _ARM64_INS_BL = 21;; -let _ARM64_INS_BLR = 22;; -let _ARM64_INS_BR = 23;; -let _ARM64_INS_BRK = 24;; -let _ARM64_INS_BSL = 25;; -let _ARM64_INS_CBNZ = 26;; -let _ARM64_INS_CBZ = 27;; -let _ARM64_INS_CCMN = 28;; -let _ARM64_INS_CCMP = 29;; -let _ARM64_INS_CLREX = 30;; -let _ARM64_INS_CLS = 31;; -let _ARM64_INS_CLZ = 32;; -let _ARM64_INS_CMEQ = 33;; -let _ARM64_INS_CMGE = 34;; -let _ARM64_INS_CMGT = 35;; -let _ARM64_INS_CMHI = 36;; -let _ARM64_INS_CMHS = 37;; -let _ARM64_INS_CMLE = 38;; -let _ARM64_INS_CMLT = 39;; -let _ARM64_INS_CMTST = 40;; -let _ARM64_INS_CNT = 41;; -let _ARM64_INS_MOV = 42;; -let _ARM64_INS_CRC32B = 43;; -let _ARM64_INS_CRC32CB = 44;; -let _ARM64_INS_CRC32CH = 45;; -let _ARM64_INS_CRC32CW = 46;; -let _ARM64_INS_CRC32CX = 47;; -let _ARM64_INS_CRC32H = 48;; -let _ARM64_INS_CRC32W = 49;; -let _ARM64_INS_CRC32X = 50;; -let _ARM64_INS_CSEL = 51;; -let _ARM64_INS_CSINC = 52;; -let _ARM64_INS_CSINV = 53;; -let _ARM64_INS_CSNEG = 54;; -let _ARM64_INS_DCPS1 = 55;; -let _ARM64_INS_DCPS2 = 56;; -let _ARM64_INS_DCPS3 = 57;; -let _ARM64_INS_DMB = 58;; -let _ARM64_INS_DRPS = 59;; -let _ARM64_INS_DSB = 60;; -let _ARM64_INS_DUP = 61;; -let _ARM64_INS_EON = 62;; -let _ARM64_INS_EOR = 63;; -let _ARM64_INS_ERET = 64;; -let _ARM64_INS_EXTR = 65;; -let _ARM64_INS_EXT = 66;; -let _ARM64_INS_FABD = 67;; -let _ARM64_INS_FABS = 68;; -let _ARM64_INS_FACGE = 69;; -let _ARM64_INS_FACGT = 70;; -let _ARM64_INS_FADD = 71;; -let _ARM64_INS_FADDP = 72;; -let _ARM64_INS_FCCMP = 73;; -let _ARM64_INS_FCCMPE = 74;; -let _ARM64_INS_FCMEQ = 75;; -let _ARM64_INS_FCMGE = 76;; -let _ARM64_INS_FCMGT = 77;; -let _ARM64_INS_FCMLE = 78;; -let _ARM64_INS_FCMLT = 79;; -let _ARM64_INS_FCMP = 80;; -let _ARM64_INS_FCMPE = 81;; -let _ARM64_INS_FCSEL = 82;; -let _ARM64_INS_FCVTAS = 83;; -let _ARM64_INS_FCVTAU = 84;; -let _ARM64_INS_FCVT = 85;; -let _ARM64_INS_FCVTL = 86;; -let _ARM64_INS_FCVTL2 = 87;; -let _ARM64_INS_FCVTMS = 88;; -let _ARM64_INS_FCVTMU = 89;; -let _ARM64_INS_FCVTNS = 90;; -let _ARM64_INS_FCVTNU = 91;; -let _ARM64_INS_FCVTN = 92;; -let _ARM64_INS_FCVTN2 = 93;; -let _ARM64_INS_FCVTPS = 94;; -let _ARM64_INS_FCVTPU = 95;; -let _ARM64_INS_FCVTXN = 96;; -let _ARM64_INS_FCVTXN2 = 97;; -let _ARM64_INS_FCVTZS = 98;; -let _ARM64_INS_FCVTZU = 99;; -let _ARM64_INS_FDIV = 100;; -let _ARM64_INS_FMADD = 101;; -let _ARM64_INS_FMAX = 102;; -let _ARM64_INS_FMAXNM = 103;; -let _ARM64_INS_FMAXNMP = 104;; -let _ARM64_INS_FMAXNMV = 105;; -let _ARM64_INS_FMAXP = 106;; -let _ARM64_INS_FMAXV = 107;; -let _ARM64_INS_FMIN = 108;; -let _ARM64_INS_FMINNM = 109;; -let _ARM64_INS_FMINNMP = 110;; -let _ARM64_INS_FMINNMV = 111;; -let _ARM64_INS_FMINP = 112;; -let _ARM64_INS_FMINV = 113;; -let _ARM64_INS_FMLA = 114;; -let _ARM64_INS_FMLS = 115;; -let _ARM64_INS_FMOV = 116;; -let _ARM64_INS_FMSUB = 117;; -let _ARM64_INS_FMUL = 118;; -let _ARM64_INS_FMULX = 119;; -let _ARM64_INS_FNEG = 120;; -let _ARM64_INS_FNMADD = 121;; -let _ARM64_INS_FNMSUB = 122;; -let _ARM64_INS_FNMUL = 123;; -let _ARM64_INS_FRECPE = 124;; -let _ARM64_INS_FRECPS = 125;; -let _ARM64_INS_FRECPX = 126;; -let _ARM64_INS_FRINTA = 127;; -let _ARM64_INS_FRINTI = 128;; -let _ARM64_INS_FRINTM = 129;; -let _ARM64_INS_FRINTN = 130;; -let _ARM64_INS_FRINTP = 131;; -let _ARM64_INS_FRINTX = 132;; -let _ARM64_INS_FRINTZ = 133;; -let _ARM64_INS_FRSQRTE = 134;; -let _ARM64_INS_FRSQRTS = 135;; -let _ARM64_INS_FSQRT = 136;; -let _ARM64_INS_FSUB = 137;; -let _ARM64_INS_HINT = 138;; -let _ARM64_INS_HLT = 139;; -let _ARM64_INS_HVC = 140;; -let _ARM64_INS_INS = 141;; -let _ARM64_INS_ISB = 142;; -let _ARM64_INS_LD1 = 143;; -let _ARM64_INS_LD1R = 144;; -let _ARM64_INS_LD2R = 145;; -let _ARM64_INS_LD2 = 146;; -let _ARM64_INS_LD3R = 147;; -let _ARM64_INS_LD3 = 148;; -let _ARM64_INS_LD4 = 149;; -let _ARM64_INS_LD4R = 150;; -let _ARM64_INS_LDARB = 151;; -let _ARM64_INS_LDARH = 152;; -let _ARM64_INS_LDAR = 153;; -let _ARM64_INS_LDAXP = 154;; -let _ARM64_INS_LDAXRB = 155;; -let _ARM64_INS_LDAXRH = 156;; -let _ARM64_INS_LDAXR = 157;; -let _ARM64_INS_LDNP = 158;; -let _ARM64_INS_LDP = 159;; -let _ARM64_INS_LDPSW = 160;; -let _ARM64_INS_LDRB = 161;; -let _ARM64_INS_LDR = 162;; -let _ARM64_INS_LDRH = 163;; -let _ARM64_INS_LDRSB = 164;; -let _ARM64_INS_LDRSH = 165;; -let _ARM64_INS_LDRSW = 166;; -let _ARM64_INS_LDTRB = 167;; -let _ARM64_INS_LDTRH = 168;; -let _ARM64_INS_LDTRSB = 169;; -let _ARM64_INS_LDTRSH = 170;; -let _ARM64_INS_LDTRSW = 171;; -let _ARM64_INS_LDTR = 172;; -let _ARM64_INS_LDURB = 173;; -let _ARM64_INS_LDUR = 174;; -let _ARM64_INS_LDURH = 175;; -let _ARM64_INS_LDURSB = 176;; -let _ARM64_INS_LDURSH = 177;; -let _ARM64_INS_LDURSW = 178;; -let _ARM64_INS_LDXP = 179;; -let _ARM64_INS_LDXRB = 180;; -let _ARM64_INS_LDXRH = 181;; -let _ARM64_INS_LDXR = 182;; -let _ARM64_INS_LSL = 183;; -let _ARM64_INS_LSR = 184;; -let _ARM64_INS_MADD = 185;; -let _ARM64_INS_MLA = 186;; -let _ARM64_INS_MLS = 187;; -let _ARM64_INS_MOVI = 188;; -let _ARM64_INS_MOVK = 189;; -let _ARM64_INS_MOVN = 190;; -let _ARM64_INS_MOVZ = 191;; -let _ARM64_INS_MRS = 192;; -let _ARM64_INS_MSR = 193;; -let _ARM64_INS_MSUB = 194;; -let _ARM64_INS_MUL = 195;; -let _ARM64_INS_MVNI = 196;; -let _ARM64_INS_NEG = 197;; -let _ARM64_INS_NOT = 198;; -let _ARM64_INS_ORN = 199;; -let _ARM64_INS_ORR = 200;; -let _ARM64_INS_PMULL2 = 201;; -let _ARM64_INS_PMULL = 202;; -let _ARM64_INS_PMUL = 203;; -let _ARM64_INS_PRFM = 204;; -let _ARM64_INS_PRFUM = 205;; -let _ARM64_INS_RADDHN = 206;; -let _ARM64_INS_RADDHN2 = 207;; -let _ARM64_INS_RBIT = 208;; -let _ARM64_INS_RET = 209;; -let _ARM64_INS_REV16 = 210;; -let _ARM64_INS_REV32 = 211;; -let _ARM64_INS_REV64 = 212;; -let _ARM64_INS_REV = 213;; -let _ARM64_INS_ROR = 214;; -let _ARM64_INS_RSHRN2 = 215;; -let _ARM64_INS_RSHRN = 216;; -let _ARM64_INS_RSUBHN = 217;; -let _ARM64_INS_RSUBHN2 = 218;; -let _ARM64_INS_SABAL2 = 219;; -let _ARM64_INS_SABAL = 220;; -let _ARM64_INS_SABA = 221;; -let _ARM64_INS_SABDL2 = 222;; -let _ARM64_INS_SABDL = 223;; -let _ARM64_INS_SABD = 224;; -let _ARM64_INS_SADALP = 225;; -let _ARM64_INS_SADDLP = 226;; -let _ARM64_INS_SADDLV = 227;; -let _ARM64_INS_SADDL2 = 228;; -let _ARM64_INS_SADDL = 229;; -let _ARM64_INS_SADDW2 = 230;; -let _ARM64_INS_SADDW = 231;; -let _ARM64_INS_SBC = 232;; -let _ARM64_INS_SBFM = 233;; -let _ARM64_INS_SCVTF = 234;; -let _ARM64_INS_SDIV = 235;; -let _ARM64_INS_SHA1C = 236;; -let _ARM64_INS_SHA1H = 237;; -let _ARM64_INS_SHA1M = 238;; -let _ARM64_INS_SHA1P = 239;; -let _ARM64_INS_SHA1SU0 = 240;; -let _ARM64_INS_SHA1SU1 = 241;; -let _ARM64_INS_SHA256H2 = 242;; -let _ARM64_INS_SHA256H = 243;; -let _ARM64_INS_SHA256SU0 = 244;; -let _ARM64_INS_SHA256SU1 = 245;; -let _ARM64_INS_SHADD = 246;; -let _ARM64_INS_SHLL2 = 247;; -let _ARM64_INS_SHLL = 248;; -let _ARM64_INS_SHL = 249;; -let _ARM64_INS_SHRN2 = 250;; -let _ARM64_INS_SHRN = 251;; -let _ARM64_INS_SHSUB = 252;; -let _ARM64_INS_SLI = 253;; -let _ARM64_INS_SMADDL = 254;; -let _ARM64_INS_SMAXP = 255;; -let _ARM64_INS_SMAXV = 256;; -let _ARM64_INS_SMAX = 257;; -let _ARM64_INS_SMC = 258;; -let _ARM64_INS_SMINP = 259;; -let _ARM64_INS_SMINV = 260;; -let _ARM64_INS_SMIN = 261;; -let _ARM64_INS_SMLAL2 = 262;; -let _ARM64_INS_SMLAL = 263;; -let _ARM64_INS_SMLSL2 = 264;; -let _ARM64_INS_SMLSL = 265;; -let _ARM64_INS_SMOV = 266;; -let _ARM64_INS_SMSUBL = 267;; -let _ARM64_INS_SMULH = 268;; -let _ARM64_INS_SMULL2 = 269;; -let _ARM64_INS_SMULL = 270;; -let _ARM64_INS_SQABS = 271;; -let _ARM64_INS_SQADD = 272;; -let _ARM64_INS_SQDMLAL = 273;; -let _ARM64_INS_SQDMLAL2 = 274;; -let _ARM64_INS_SQDMLSL = 275;; -let _ARM64_INS_SQDMLSL2 = 276;; -let _ARM64_INS_SQDMULH = 277;; -let _ARM64_INS_SQDMULL = 278;; -let _ARM64_INS_SQDMULL2 = 279;; -let _ARM64_INS_SQNEG = 280;; -let _ARM64_INS_SQRDMULH = 281;; -let _ARM64_INS_SQRSHL = 282;; -let _ARM64_INS_SQRSHRN = 283;; -let _ARM64_INS_SQRSHRN2 = 284;; -let _ARM64_INS_SQRSHRUN = 285;; -let _ARM64_INS_SQRSHRUN2 = 286;; -let _ARM64_INS_SQSHLU = 287;; -let _ARM64_INS_SQSHL = 288;; -let _ARM64_INS_SQSHRN = 289;; -let _ARM64_INS_SQSHRN2 = 290;; -let _ARM64_INS_SQSHRUN = 291;; -let _ARM64_INS_SQSHRUN2 = 292;; -let _ARM64_INS_SQSUB = 293;; -let _ARM64_INS_SQXTN2 = 294;; -let _ARM64_INS_SQXTN = 295;; -let _ARM64_INS_SQXTUN2 = 296;; -let _ARM64_INS_SQXTUN = 297;; -let _ARM64_INS_SRHADD = 298;; -let _ARM64_INS_SRI = 299;; -let _ARM64_INS_SRSHL = 300;; -let _ARM64_INS_SRSHR = 301;; -let _ARM64_INS_SRSRA = 302;; -let _ARM64_INS_SSHLL2 = 303;; -let _ARM64_INS_SSHLL = 304;; -let _ARM64_INS_SSHL = 305;; -let _ARM64_INS_SSHR = 306;; -let _ARM64_INS_SSRA = 307;; -let _ARM64_INS_SSUBL2 = 308;; -let _ARM64_INS_SSUBL = 309;; -let _ARM64_INS_SSUBW2 = 310;; -let _ARM64_INS_SSUBW = 311;; -let _ARM64_INS_ST1 = 312;; -let _ARM64_INS_ST2 = 313;; -let _ARM64_INS_ST3 = 314;; -let _ARM64_INS_ST4 = 315;; -let _ARM64_INS_STLRB = 316;; -let _ARM64_INS_STLRH = 317;; -let _ARM64_INS_STLR = 318;; -let _ARM64_INS_STLXP = 319;; -let _ARM64_INS_STLXRB = 320;; -let _ARM64_INS_STLXRH = 321;; -let _ARM64_INS_STLXR = 322;; -let _ARM64_INS_STNP = 323;; -let _ARM64_INS_STP = 324;; -let _ARM64_INS_STRB = 325;; -let _ARM64_INS_STR = 326;; -let _ARM64_INS_STRH = 327;; -let _ARM64_INS_STTRB = 328;; -let _ARM64_INS_STTRH = 329;; -let _ARM64_INS_STTR = 330;; -let _ARM64_INS_STURB = 331;; -let _ARM64_INS_STUR = 332;; -let _ARM64_INS_STURH = 333;; -let _ARM64_INS_STXP = 334;; -let _ARM64_INS_STXRB = 335;; -let _ARM64_INS_STXRH = 336;; -let _ARM64_INS_STXR = 337;; -let _ARM64_INS_SUBHN = 338;; -let _ARM64_INS_SUBHN2 = 339;; -let _ARM64_INS_SUB = 340;; -let _ARM64_INS_SUQADD = 341;; -let _ARM64_INS_SVC = 342;; -let _ARM64_INS_SYSL = 343;; -let _ARM64_INS_SYS = 344;; -let _ARM64_INS_TBL = 345;; -let _ARM64_INS_TBNZ = 346;; -let _ARM64_INS_TBX = 347;; -let _ARM64_INS_TBZ = 348;; -let _ARM64_INS_TRN1 = 349;; -let _ARM64_INS_TRN2 = 350;; -let _ARM64_INS_UABAL2 = 351;; -let _ARM64_INS_UABAL = 352;; -let _ARM64_INS_UABA = 353;; -let _ARM64_INS_UABDL2 = 354;; -let _ARM64_INS_UABDL = 355;; -let _ARM64_INS_UABD = 356;; -let _ARM64_INS_UADALP = 357;; -let _ARM64_INS_UADDLP = 358;; -let _ARM64_INS_UADDLV = 359;; -let _ARM64_INS_UADDL2 = 360;; -let _ARM64_INS_UADDL = 361;; -let _ARM64_INS_UADDW2 = 362;; -let _ARM64_INS_UADDW = 363;; -let _ARM64_INS_UBFM = 364;; -let _ARM64_INS_UCVTF = 365;; -let _ARM64_INS_UDIV = 366;; -let _ARM64_INS_UHADD = 367;; -let _ARM64_INS_UHSUB = 368;; -let _ARM64_INS_UMADDL = 369;; -let _ARM64_INS_UMAXP = 370;; -let _ARM64_INS_UMAXV = 371;; -let _ARM64_INS_UMAX = 372;; -let _ARM64_INS_UMINP = 373;; -let _ARM64_INS_UMINV = 374;; -let _ARM64_INS_UMIN = 375;; -let _ARM64_INS_UMLAL2 = 376;; -let _ARM64_INS_UMLAL = 377;; -let _ARM64_INS_UMLSL2 = 378;; -let _ARM64_INS_UMLSL = 379;; -let _ARM64_INS_UMOV = 380;; -let _ARM64_INS_UMSUBL = 381;; -let _ARM64_INS_UMULH = 382;; -let _ARM64_INS_UMULL2 = 383;; -let _ARM64_INS_UMULL = 384;; -let _ARM64_INS_UQADD = 385;; -let _ARM64_INS_UQRSHL = 386;; -let _ARM64_INS_UQRSHRN = 387;; -let _ARM64_INS_UQRSHRN2 = 388;; -let _ARM64_INS_UQSHL = 389;; -let _ARM64_INS_UQSHRN = 390;; -let _ARM64_INS_UQSHRN2 = 391;; -let _ARM64_INS_UQSUB = 392;; -let _ARM64_INS_UQXTN2 = 393;; -let _ARM64_INS_UQXTN = 394;; -let _ARM64_INS_URECPE = 395;; -let _ARM64_INS_URHADD = 396;; -let _ARM64_INS_URSHL = 397;; -let _ARM64_INS_URSHR = 398;; -let _ARM64_INS_URSQRTE = 399;; -let _ARM64_INS_URSRA = 400;; -let _ARM64_INS_USHLL2 = 401;; -let _ARM64_INS_USHLL = 402;; -let _ARM64_INS_USHL = 403;; -let _ARM64_INS_USHR = 404;; -let _ARM64_INS_USQADD = 405;; -let _ARM64_INS_USRA = 406;; -let _ARM64_INS_USUBL2 = 407;; -let _ARM64_INS_USUBL = 408;; -let _ARM64_INS_USUBW2 = 409;; -let _ARM64_INS_USUBW = 410;; -let _ARM64_INS_UZP1 = 411;; -let _ARM64_INS_UZP2 = 412;; -let _ARM64_INS_XTN2 = 413;; -let _ARM64_INS_XTN = 414;; -let _ARM64_INS_ZIP1 = 415;; -let _ARM64_INS_ZIP2 = 416;; -let _ARM64_INS_MNEG = 417;; -let _ARM64_INS_UMNEGL = 418;; -let _ARM64_INS_SMNEGL = 419;; -let _ARM64_INS_NOP = 420;; -let _ARM64_INS_YIELD = 421;; -let _ARM64_INS_WFE = 422;; -let _ARM64_INS_WFI = 423;; -let _ARM64_INS_SEV = 424;; -let _ARM64_INS_SEVL = 425;; -let _ARM64_INS_NGC = 426;; -let _ARM64_INS_SBFIZ = 427;; -let _ARM64_INS_UBFIZ = 428;; -let _ARM64_INS_SBFX = 429;; -let _ARM64_INS_UBFX = 430;; -let _ARM64_INS_BFI = 431;; -let _ARM64_INS_BFXIL = 432;; -let _ARM64_INS_CMN = 433;; -let _ARM64_INS_MVN = 434;; -let _ARM64_INS_TST = 435;; -let _ARM64_INS_CSET = 436;; -let _ARM64_INS_CINC = 437;; -let _ARM64_INS_CSETM = 438;; -let _ARM64_INS_CINV = 439;; -let _ARM64_INS_CNEG = 440;; -let _ARM64_INS_SXTB = 441;; -let _ARM64_INS_SXTH = 442;; -let _ARM64_INS_SXTW = 443;; -let _ARM64_INS_CMP = 444;; -let _ARM64_INS_UXTB = 445;; -let _ARM64_INS_UXTH = 446;; -let _ARM64_INS_UXTW = 447;; -let _ARM64_INS_IC = 448;; -let _ARM64_INS_DC = 449;; -let _ARM64_INS_AT = 450;; -let _ARM64_INS_TLBI = 451;; -let _ARM64_INS_NEGS = 452;; -let _ARM64_INS_NGCS = 453;; -let _ARM64_INS_ENDING = 454;; +let _ARM64_INS_ADCS = 3;; +let _ARM64_INS_ADD = 4;; +let _ARM64_INS_ADDHN = 5;; +let _ARM64_INS_ADDHN2 = 6;; +let _ARM64_INS_ADDP = 7;; +let _ARM64_INS_ADDPL = 8;; +let _ARM64_INS_ADDS = 9;; +let _ARM64_INS_ADDV = 10;; +let _ARM64_INS_ADDVL = 11;; +let _ARM64_INS_ADR = 12;; +let _ARM64_INS_ADRP = 13;; +let _ARM64_INS_AESD = 14;; +let _ARM64_INS_AESE = 15;; +let _ARM64_INS_AESIMC = 16;; +let _ARM64_INS_AESMC = 17;; +let _ARM64_INS_AND = 18;; +let _ARM64_INS_ANDS = 19;; +let _ARM64_INS_ANDV = 20;; +let _ARM64_INS_ASR = 21;; +let _ARM64_INS_ASRD = 22;; +let _ARM64_INS_ASRR = 23;; +let _ARM64_INS_ASRV = 24;; +let _ARM64_INS_AUTDA = 25;; +let _ARM64_INS_AUTDB = 26;; +let _ARM64_INS_AUTDZA = 27;; +let _ARM64_INS_AUTDZB = 28;; +let _ARM64_INS_AUTIA = 29;; +let _ARM64_INS_AUTIA1716 = 30;; +let _ARM64_INS_AUTIASP = 31;; +let _ARM64_INS_AUTIAZ = 32;; +let _ARM64_INS_AUTIB = 33;; +let _ARM64_INS_AUTIB1716 = 34;; +let _ARM64_INS_AUTIBSP = 35;; +let _ARM64_INS_AUTIBZ = 36;; +let _ARM64_INS_AUTIZA = 37;; +let _ARM64_INS_AUTIZB = 38;; +let _ARM64_INS_B = 39;; +let _ARM64_INS_BCAX = 40;; +let _ARM64_INS_BFM = 41;; +let _ARM64_INS_BIC = 42;; +let _ARM64_INS_BICS = 43;; +let _ARM64_INS_BIF = 44;; +let _ARM64_INS_BIT = 45;; +let _ARM64_INS_BL = 46;; +let _ARM64_INS_BLR = 47;; +let _ARM64_INS_BLRAA = 48;; +let _ARM64_INS_BLRAAZ = 49;; +let _ARM64_INS_BLRAB = 50;; +let _ARM64_INS_BLRABZ = 51;; +let _ARM64_INS_BR = 52;; +let _ARM64_INS_BRAA = 53;; +let _ARM64_INS_BRAAZ = 54;; +let _ARM64_INS_BRAB = 55;; +let _ARM64_INS_BRABZ = 56;; +let _ARM64_INS_BRK = 57;; +let _ARM64_INS_BRKA = 58;; +let _ARM64_INS_BRKAS = 59;; +let _ARM64_INS_BRKB = 60;; +let _ARM64_INS_BRKBS = 61;; +let _ARM64_INS_BRKN = 62;; +let _ARM64_INS_BRKNS = 63;; +let _ARM64_INS_BRKPA = 64;; +let _ARM64_INS_BRKPAS = 65;; +let _ARM64_INS_BRKPB = 66;; +let _ARM64_INS_BRKPBS = 67;; +let _ARM64_INS_BSL = 68;; +let _ARM64_INS_CAS = 69;; +let _ARM64_INS_CASA = 70;; +let _ARM64_INS_CASAB = 71;; +let _ARM64_INS_CASAH = 72;; +let _ARM64_INS_CASAL = 73;; +let _ARM64_INS_CASALB = 74;; +let _ARM64_INS_CASALH = 75;; +let _ARM64_INS_CASB = 76;; +let _ARM64_INS_CASH = 77;; +let _ARM64_INS_CASL = 78;; +let _ARM64_INS_CASLB = 79;; +let _ARM64_INS_CASLH = 80;; +let _ARM64_INS_CASP = 81;; +let _ARM64_INS_CASPA = 82;; +let _ARM64_INS_CASPAL = 83;; +let _ARM64_INS_CASPL = 84;; +let _ARM64_INS_CBNZ = 85;; +let _ARM64_INS_CBZ = 86;; +let _ARM64_INS_CCMN = 87;; +let _ARM64_INS_CCMP = 88;; +let _ARM64_INS_CFINV = 89;; +let _ARM64_INS_CINC = 90;; +let _ARM64_INS_CINV = 91;; +let _ARM64_INS_CLASTA = 92;; +let _ARM64_INS_CLASTB = 93;; +let _ARM64_INS_CLREX = 94;; +let _ARM64_INS_CLS = 95;; +let _ARM64_INS_CLZ = 96;; +let _ARM64_INS_CMEQ = 97;; +let _ARM64_INS_CMGE = 98;; +let _ARM64_INS_CMGT = 99;; +let _ARM64_INS_CMHI = 100;; +let _ARM64_INS_CMHS = 101;; +let _ARM64_INS_CMLE = 102;; +let _ARM64_INS_CMLO = 103;; +let _ARM64_INS_CMLS = 104;; +let _ARM64_INS_CMLT = 105;; +let _ARM64_INS_CMN = 106;; +let _ARM64_INS_CMP = 107;; +let _ARM64_INS_CMPEQ = 108;; +let _ARM64_INS_CMPGE = 109;; +let _ARM64_INS_CMPGT = 110;; +let _ARM64_INS_CMPHI = 111;; +let _ARM64_INS_CMPHS = 112;; +let _ARM64_INS_CMPLE = 113;; +let _ARM64_INS_CMPLO = 114;; +let _ARM64_INS_CMPLS = 115;; +let _ARM64_INS_CMPLT = 116;; +let _ARM64_INS_CMPNE = 117;; +let _ARM64_INS_CMTST = 118;; +let _ARM64_INS_CNEG = 119;; +let _ARM64_INS_CNOT = 120;; +let _ARM64_INS_CNT = 121;; +let _ARM64_INS_CNTB = 122;; +let _ARM64_INS_CNTD = 123;; +let _ARM64_INS_CNTH = 124;; +let _ARM64_INS_CNTP = 125;; +let _ARM64_INS_CNTW = 126;; +let _ARM64_INS_COMPACT = 127;; +let _ARM64_INS_CPY = 128;; +let _ARM64_INS_CRC32B = 129;; +let _ARM64_INS_CRC32CB = 130;; +let _ARM64_INS_CRC32CH = 131;; +let _ARM64_INS_CRC32CW = 132;; +let _ARM64_INS_CRC32CX = 133;; +let _ARM64_INS_CRC32H = 134;; +let _ARM64_INS_CRC32W = 135;; +let _ARM64_INS_CRC32X = 136;; +let _ARM64_INS_CSDB = 137;; +let _ARM64_INS_CSEL = 138;; +let _ARM64_INS_CSET = 139;; +let _ARM64_INS_CSETM = 140;; +let _ARM64_INS_CSINC = 141;; +let _ARM64_INS_CSINV = 142;; +let _ARM64_INS_CSNEG = 143;; +let _ARM64_INS_CTERMEQ = 144;; +let _ARM64_INS_CTERMNE = 145;; +let _ARM64_INS_DCPS1 = 146;; +let _ARM64_INS_DCPS2 = 147;; +let _ARM64_INS_DCPS3 = 148;; +let _ARM64_INS_DECB = 149;; +let _ARM64_INS_DECD = 150;; +let _ARM64_INS_DECH = 151;; +let _ARM64_INS_DECP = 152;; +let _ARM64_INS_DECW = 153;; +let _ARM64_INS_DMB = 154;; +let _ARM64_INS_DRPS = 155;; +let _ARM64_INS_DSB = 156;; +let _ARM64_INS_DUP = 157;; +let _ARM64_INS_DUPM = 158;; +let _ARM64_INS_EON = 159;; +let _ARM64_INS_EOR = 160;; +let _ARM64_INS_EOR3 = 161;; +let _ARM64_INS_EORS = 162;; +let _ARM64_INS_EORV = 163;; +let _ARM64_INS_ERET = 164;; +let _ARM64_INS_ERETAA = 165;; +let _ARM64_INS_ERETAB = 166;; +let _ARM64_INS_ESB = 167;; +let _ARM64_INS_EXT = 168;; +let _ARM64_INS_EXTR = 169;; +let _ARM64_INS_FABD = 170;; +let _ARM64_INS_FABS = 171;; +let _ARM64_INS_FACGE = 172;; +let _ARM64_INS_FACGT = 173;; +let _ARM64_INS_FACLE = 174;; +let _ARM64_INS_FACLT = 175;; +let _ARM64_INS_FADD = 176;; +let _ARM64_INS_FADDA = 177;; +let _ARM64_INS_FADDP = 178;; +let _ARM64_INS_FADDV = 179;; +let _ARM64_INS_FCADD = 180;; +let _ARM64_INS_FCCMP = 181;; +let _ARM64_INS_FCCMPE = 182;; +let _ARM64_INS_FCMEQ = 183;; +let _ARM64_INS_FCMGE = 184;; +let _ARM64_INS_FCMGT = 185;; +let _ARM64_INS_FCMLA = 186;; +let _ARM64_INS_FCMLE = 187;; +let _ARM64_INS_FCMLT = 188;; +let _ARM64_INS_FCMNE = 189;; +let _ARM64_INS_FCMP = 190;; +let _ARM64_INS_FCMPE = 191;; +let _ARM64_INS_FCMUO = 192;; +let _ARM64_INS_FCPY = 193;; +let _ARM64_INS_FCSEL = 194;; +let _ARM64_INS_FCVT = 195;; +let _ARM64_INS_FCVTAS = 196;; +let _ARM64_INS_FCVTAU = 197;; +let _ARM64_INS_FCVTL = 198;; +let _ARM64_INS_FCVTL2 = 199;; +let _ARM64_INS_FCVTMS = 200;; +let _ARM64_INS_FCVTMU = 201;; +let _ARM64_INS_FCVTN = 202;; +let _ARM64_INS_FCVTN2 = 203;; +let _ARM64_INS_FCVTNS = 204;; +let _ARM64_INS_FCVTNU = 205;; +let _ARM64_INS_FCVTPS = 206;; +let _ARM64_INS_FCVTPU = 207;; +let _ARM64_INS_FCVTXN = 208;; +let _ARM64_INS_FCVTXN2 = 209;; +let _ARM64_INS_FCVTZS = 210;; +let _ARM64_INS_FCVTZU = 211;; +let _ARM64_INS_FDIV = 212;; +let _ARM64_INS_FDIVR = 213;; +let _ARM64_INS_FDUP = 214;; +let _ARM64_INS_FEXPA = 215;; +let _ARM64_INS_FJCVTZS = 216;; +let _ARM64_INS_FMAD = 217;; +let _ARM64_INS_FMADD = 218;; +let _ARM64_INS_FMAX = 219;; +let _ARM64_INS_FMAXNM = 220;; +let _ARM64_INS_FMAXNMP = 221;; +let _ARM64_INS_FMAXNMV = 222;; +let _ARM64_INS_FMAXP = 223;; +let _ARM64_INS_FMAXV = 224;; +let _ARM64_INS_FMIN = 225;; +let _ARM64_INS_FMINNM = 226;; +let _ARM64_INS_FMINNMP = 227;; +let _ARM64_INS_FMINNMV = 228;; +let _ARM64_INS_FMINP = 229;; +let _ARM64_INS_FMINV = 230;; +let _ARM64_INS_FMLA = 231;; +let _ARM64_INS_FMLS = 232;; +let _ARM64_INS_FMOV = 233;; +let _ARM64_INS_FMSB = 234;; +let _ARM64_INS_FMSUB = 235;; +let _ARM64_INS_FMUL = 236;; +let _ARM64_INS_FMULX = 237;; +let _ARM64_INS_FNEG = 238;; +let _ARM64_INS_FNMAD = 239;; +let _ARM64_INS_FNMADD = 240;; +let _ARM64_INS_FNMLA = 241;; +let _ARM64_INS_FNMLS = 242;; +let _ARM64_INS_FNMSB = 243;; +let _ARM64_INS_FNMSUB = 244;; +let _ARM64_INS_FNMUL = 245;; +let _ARM64_INS_FRECPE = 246;; +let _ARM64_INS_FRECPS = 247;; +let _ARM64_INS_FRECPX = 248;; +let _ARM64_INS_FRINTA = 249;; +let _ARM64_INS_FRINTI = 250;; +let _ARM64_INS_FRINTM = 251;; +let _ARM64_INS_FRINTN = 252;; +let _ARM64_INS_FRINTP = 253;; +let _ARM64_INS_FRINTX = 254;; +let _ARM64_INS_FRINTZ = 255;; +let _ARM64_INS_FRSQRTE = 256;; +let _ARM64_INS_FRSQRTS = 257;; +let _ARM64_INS_FSCALE = 258;; +let _ARM64_INS_FSQRT = 259;; +let _ARM64_INS_FSUB = 260;; +let _ARM64_INS_FSUBR = 261;; +let _ARM64_INS_FTMAD = 262;; +let _ARM64_INS_FTSMUL = 263;; +let _ARM64_INS_FTSSEL = 264;; +let _ARM64_INS_HINT = 265;; +let _ARM64_INS_HLT = 266;; +let _ARM64_INS_HVC = 267;; +let _ARM64_INS_INCB = 268;; +let _ARM64_INS_INCD = 269;; +let _ARM64_INS_INCH = 270;; +let _ARM64_INS_INCP = 271;; +let _ARM64_INS_INCW = 272;; +let _ARM64_INS_INDEX = 273;; +let _ARM64_INS_INS = 274;; +let _ARM64_INS_INSR = 275;; +let _ARM64_INS_ISB = 276;; +let _ARM64_INS_LASTA = 277;; +let _ARM64_INS_LASTB = 278;; +let _ARM64_INS_LD1 = 279;; +let _ARM64_INS_LD1B = 280;; +let _ARM64_INS_LD1D = 281;; +let _ARM64_INS_LD1H = 282;; +let _ARM64_INS_LD1R = 283;; +let _ARM64_INS_LD1RB = 284;; +let _ARM64_INS_LD1RD = 285;; +let _ARM64_INS_LD1RH = 286;; +let _ARM64_INS_LD1RQB = 287;; +let _ARM64_INS_LD1RQD = 288;; +let _ARM64_INS_LD1RQH = 289;; +let _ARM64_INS_LD1RQW = 290;; +let _ARM64_INS_LD1RSB = 291;; +let _ARM64_INS_LD1RSH = 292;; +let _ARM64_INS_LD1RSW = 293;; +let _ARM64_INS_LD1RW = 294;; +let _ARM64_INS_LD1SB = 295;; +let _ARM64_INS_LD1SH = 296;; +let _ARM64_INS_LD1SW = 297;; +let _ARM64_INS_LD1W = 298;; +let _ARM64_INS_LD2 = 299;; +let _ARM64_INS_LD2B = 300;; +let _ARM64_INS_LD2D = 301;; +let _ARM64_INS_LD2H = 302;; +let _ARM64_INS_LD2R = 303;; +let _ARM64_INS_LD2W = 304;; +let _ARM64_INS_LD3 = 305;; +let _ARM64_INS_LD3B = 306;; +let _ARM64_INS_LD3D = 307;; +let _ARM64_INS_LD3H = 308;; +let _ARM64_INS_LD3R = 309;; +let _ARM64_INS_LD3W = 310;; +let _ARM64_INS_LD4 = 311;; +let _ARM64_INS_LD4B = 312;; +let _ARM64_INS_LD4D = 313;; +let _ARM64_INS_LD4H = 314;; +let _ARM64_INS_LD4R = 315;; +let _ARM64_INS_LD4W = 316;; +let _ARM64_INS_LDADD = 317;; +let _ARM64_INS_LDADDA = 318;; +let _ARM64_INS_LDADDAB = 319;; +let _ARM64_INS_LDADDAH = 320;; +let _ARM64_INS_LDADDAL = 321;; +let _ARM64_INS_LDADDALB = 322;; +let _ARM64_INS_LDADDALH = 323;; +let _ARM64_INS_LDADDB = 324;; +let _ARM64_INS_LDADDH = 325;; +let _ARM64_INS_LDADDL = 326;; +let _ARM64_INS_LDADDLB = 327;; +let _ARM64_INS_LDADDLH = 328;; +let _ARM64_INS_LDAPR = 329;; +let _ARM64_INS_LDAPRB = 330;; +let _ARM64_INS_LDAPRH = 331;; +let _ARM64_INS_LDAPUR = 332;; +let _ARM64_INS_LDAPURB = 333;; +let _ARM64_INS_LDAPURH = 334;; +let _ARM64_INS_LDAPURSB = 335;; +let _ARM64_INS_LDAPURSH = 336;; +let _ARM64_INS_LDAPURSW = 337;; +let _ARM64_INS_LDAR = 338;; +let _ARM64_INS_LDARB = 339;; +let _ARM64_INS_LDARH = 340;; +let _ARM64_INS_LDAXP = 341;; +let _ARM64_INS_LDAXR = 342;; +let _ARM64_INS_LDAXRB = 343;; +let _ARM64_INS_LDAXRH = 344;; +let _ARM64_INS_LDCLR = 345;; +let _ARM64_INS_LDCLRA = 346;; +let _ARM64_INS_LDCLRAB = 347;; +let _ARM64_INS_LDCLRAH = 348;; +let _ARM64_INS_LDCLRAL = 349;; +let _ARM64_INS_LDCLRALB = 350;; +let _ARM64_INS_LDCLRALH = 351;; +let _ARM64_INS_LDCLRB = 352;; +let _ARM64_INS_LDCLRH = 353;; +let _ARM64_INS_LDCLRL = 354;; +let _ARM64_INS_LDCLRLB = 355;; +let _ARM64_INS_LDCLRLH = 356;; +let _ARM64_INS_LDEOR = 357;; +let _ARM64_INS_LDEORA = 358;; +let _ARM64_INS_LDEORAB = 359;; +let _ARM64_INS_LDEORAH = 360;; +let _ARM64_INS_LDEORAL = 361;; +let _ARM64_INS_LDEORALB = 362;; +let _ARM64_INS_LDEORALH = 363;; +let _ARM64_INS_LDEORB = 364;; +let _ARM64_INS_LDEORH = 365;; +let _ARM64_INS_LDEORL = 366;; +let _ARM64_INS_LDEORLB = 367;; +let _ARM64_INS_LDEORLH = 368;; +let _ARM64_INS_LDFF1B = 369;; +let _ARM64_INS_LDFF1D = 370;; +let _ARM64_INS_LDFF1H = 371;; +let _ARM64_INS_LDFF1SB = 372;; +let _ARM64_INS_LDFF1SH = 373;; +let _ARM64_INS_LDFF1SW = 374;; +let _ARM64_INS_LDFF1W = 375;; +let _ARM64_INS_LDLAR = 376;; +let _ARM64_INS_LDLARB = 377;; +let _ARM64_INS_LDLARH = 378;; +let _ARM64_INS_LDNF1B = 379;; +let _ARM64_INS_LDNF1D = 380;; +let _ARM64_INS_LDNF1H = 381;; +let _ARM64_INS_LDNF1SB = 382;; +let _ARM64_INS_LDNF1SH = 383;; +let _ARM64_INS_LDNF1SW = 384;; +let _ARM64_INS_LDNF1W = 385;; +let _ARM64_INS_LDNP = 386;; +let _ARM64_INS_LDNT1B = 387;; +let _ARM64_INS_LDNT1D = 388;; +let _ARM64_INS_LDNT1H = 389;; +let _ARM64_INS_LDNT1W = 390;; +let _ARM64_INS_LDP = 391;; +let _ARM64_INS_LDPSW = 392;; +let _ARM64_INS_LDR = 393;; +let _ARM64_INS_LDRAA = 394;; +let _ARM64_INS_LDRAB = 395;; +let _ARM64_INS_LDRB = 396;; +let _ARM64_INS_LDRH = 397;; +let _ARM64_INS_LDRSB = 398;; +let _ARM64_INS_LDRSH = 399;; +let _ARM64_INS_LDRSW = 400;; +let _ARM64_INS_LDSET = 401;; +let _ARM64_INS_LDSETA = 402;; +let _ARM64_INS_LDSETAB = 403;; +let _ARM64_INS_LDSETAH = 404;; +let _ARM64_INS_LDSETAL = 405;; +let _ARM64_INS_LDSETALB = 406;; +let _ARM64_INS_LDSETALH = 407;; +let _ARM64_INS_LDSETB = 408;; +let _ARM64_INS_LDSETH = 409;; +let _ARM64_INS_LDSETL = 410;; +let _ARM64_INS_LDSETLB = 411;; +let _ARM64_INS_LDSETLH = 412;; +let _ARM64_INS_LDSMAX = 413;; +let _ARM64_INS_LDSMAXA = 414;; +let _ARM64_INS_LDSMAXAB = 415;; +let _ARM64_INS_LDSMAXAH = 416;; +let _ARM64_INS_LDSMAXAL = 417;; +let _ARM64_INS_LDSMAXALB = 418;; +let _ARM64_INS_LDSMAXALH = 419;; +let _ARM64_INS_LDSMAXB = 420;; +let _ARM64_INS_LDSMAXH = 421;; +let _ARM64_INS_LDSMAXL = 422;; +let _ARM64_INS_LDSMAXLB = 423;; +let _ARM64_INS_LDSMAXLH = 424;; +let _ARM64_INS_LDSMIN = 425;; +let _ARM64_INS_LDSMINA = 426;; +let _ARM64_INS_LDSMINAB = 427;; +let _ARM64_INS_LDSMINAH = 428;; +let _ARM64_INS_LDSMINAL = 429;; +let _ARM64_INS_LDSMINALB = 430;; +let _ARM64_INS_LDSMINALH = 431;; +let _ARM64_INS_LDSMINB = 432;; +let _ARM64_INS_LDSMINH = 433;; +let _ARM64_INS_LDSMINL = 434;; +let _ARM64_INS_LDSMINLB = 435;; +let _ARM64_INS_LDSMINLH = 436;; +let _ARM64_INS_LDTR = 437;; +let _ARM64_INS_LDTRB = 438;; +let _ARM64_INS_LDTRH = 439;; +let _ARM64_INS_LDTRSB = 440;; +let _ARM64_INS_LDTRSH = 441;; +let _ARM64_INS_LDTRSW = 442;; +let _ARM64_INS_LDUMAX = 443;; +let _ARM64_INS_LDUMAXA = 444;; +let _ARM64_INS_LDUMAXAB = 445;; +let _ARM64_INS_LDUMAXAH = 446;; +let _ARM64_INS_LDUMAXAL = 447;; +let _ARM64_INS_LDUMAXALB = 448;; +let _ARM64_INS_LDUMAXALH = 449;; +let _ARM64_INS_LDUMAXB = 450;; +let _ARM64_INS_LDUMAXH = 451;; +let _ARM64_INS_LDUMAXL = 452;; +let _ARM64_INS_LDUMAXLB = 453;; +let _ARM64_INS_LDUMAXLH = 454;; +let _ARM64_INS_LDUMIN = 455;; +let _ARM64_INS_LDUMINA = 456;; +let _ARM64_INS_LDUMINAB = 457;; +let _ARM64_INS_LDUMINAH = 458;; +let _ARM64_INS_LDUMINAL = 459;; +let _ARM64_INS_LDUMINALB = 460;; +let _ARM64_INS_LDUMINALH = 461;; +let _ARM64_INS_LDUMINB = 462;; +let _ARM64_INS_LDUMINH = 463;; +let _ARM64_INS_LDUMINL = 464;; +let _ARM64_INS_LDUMINLB = 465;; +let _ARM64_INS_LDUMINLH = 466;; +let _ARM64_INS_LDUR = 467;; +let _ARM64_INS_LDURB = 468;; +let _ARM64_INS_LDURH = 469;; +let _ARM64_INS_LDURSB = 470;; +let _ARM64_INS_LDURSH = 471;; +let _ARM64_INS_LDURSW = 472;; +let _ARM64_INS_LDXP = 473;; +let _ARM64_INS_LDXR = 474;; +let _ARM64_INS_LDXRB = 475;; +let _ARM64_INS_LDXRH = 476;; +let _ARM64_INS_LSL = 477;; +let _ARM64_INS_LSLR = 478;; +let _ARM64_INS_LSLV = 479;; +let _ARM64_INS_LSR = 480;; +let _ARM64_INS_LSRR = 481;; +let _ARM64_INS_LSRV = 482;; +let _ARM64_INS_MAD = 483;; +let _ARM64_INS_MADD = 484;; +let _ARM64_INS_MLA = 485;; +let _ARM64_INS_MLS = 486;; +let _ARM64_INS_MNEG = 487;; +let _ARM64_INS_MOV = 488;; +let _ARM64_INS_MOVI = 489;; +let _ARM64_INS_MOVK = 490;; +let _ARM64_INS_MOVN = 491;; +let _ARM64_INS_MOVPRFX = 492;; +let _ARM64_INS_MOVS = 493;; +let _ARM64_INS_MOVZ = 494;; +let _ARM64_INS_MRS = 495;; +let _ARM64_INS_MSB = 496;; +let _ARM64_INS_MSR = 497;; +let _ARM64_INS_MSUB = 498;; +let _ARM64_INS_MUL = 499;; +let _ARM64_INS_MVN = 500;; +let _ARM64_INS_MVNI = 501;; +let _ARM64_INS_NAND = 502;; +let _ARM64_INS_NANDS = 503;; +let _ARM64_INS_NEG = 504;; +let _ARM64_INS_NEGS = 505;; +let _ARM64_INS_NGC = 506;; +let _ARM64_INS_NGCS = 507;; +let _ARM64_INS_NOP = 508;; +let _ARM64_INS_NOR = 509;; +let _ARM64_INS_NORS = 510;; +let _ARM64_INS_NOT = 511;; +let _ARM64_INS_NOTS = 512;; +let _ARM64_INS_ORN = 513;; +let _ARM64_INS_ORNS = 514;; +let _ARM64_INS_ORR = 515;; +let _ARM64_INS_ORRS = 516;; +let _ARM64_INS_ORV = 517;; +let _ARM64_INS_PACDA = 518;; +let _ARM64_INS_PACDB = 519;; +let _ARM64_INS_PACDZA = 520;; +let _ARM64_INS_PACDZB = 521;; +let _ARM64_INS_PACGA = 522;; +let _ARM64_INS_PACIA = 523;; +let _ARM64_INS_PACIA1716 = 524;; +let _ARM64_INS_PACIASP = 525;; +let _ARM64_INS_PACIAZ = 526;; +let _ARM64_INS_PACIB = 527;; +let _ARM64_INS_PACIB1716 = 528;; +let _ARM64_INS_PACIBSP = 529;; +let _ARM64_INS_PACIBZ = 530;; +let _ARM64_INS_PACIZA = 531;; +let _ARM64_INS_PACIZB = 532;; +let _ARM64_INS_PFALSE = 533;; +let _ARM64_INS_PFIRST = 534;; +let _ARM64_INS_PMUL = 535;; +let _ARM64_INS_PMULL = 536;; +let _ARM64_INS_PMULL2 = 537;; +let _ARM64_INS_PNEXT = 538;; +let _ARM64_INS_PRFB = 539;; +let _ARM64_INS_PRFD = 540;; +let _ARM64_INS_PRFH = 541;; +let _ARM64_INS_PRFM = 542;; +let _ARM64_INS_PRFUM = 543;; +let _ARM64_INS_PRFW = 544;; +let _ARM64_INS_PSB = 545;; +let _ARM64_INS_PTEST = 546;; +let _ARM64_INS_PTRUE = 547;; +let _ARM64_INS_PTRUES = 548;; +let _ARM64_INS_PUNPKHI = 549;; +let _ARM64_INS_PUNPKLO = 550;; +let _ARM64_INS_RADDHN = 551;; +let _ARM64_INS_RADDHN2 = 552;; +let _ARM64_INS_RAX1 = 553;; +let _ARM64_INS_RBIT = 554;; +let _ARM64_INS_RDFFR = 555;; +let _ARM64_INS_RDFFRS = 556;; +let _ARM64_INS_RDVL = 557;; +let _ARM64_INS_RET = 558;; +let _ARM64_INS_RETAA = 559;; +let _ARM64_INS_RETAB = 560;; +let _ARM64_INS_REV = 561;; +let _ARM64_INS_REV16 = 562;; +let _ARM64_INS_REV32 = 563;; +let _ARM64_INS_REV64 = 564;; +let _ARM64_INS_REVB = 565;; +let _ARM64_INS_REVH = 566;; +let _ARM64_INS_REVW = 567;; +let _ARM64_INS_RMIF = 568;; +let _ARM64_INS_ROR = 569;; +let _ARM64_INS_RORV = 570;; +let _ARM64_INS_RSHRN = 571;; +let _ARM64_INS_RSHRN2 = 572;; +let _ARM64_INS_RSUBHN = 573;; +let _ARM64_INS_RSUBHN2 = 574;; +let _ARM64_INS_SABA = 575;; +let _ARM64_INS_SABAL = 576;; +let _ARM64_INS_SABAL2 = 577;; +let _ARM64_INS_SABD = 578;; +let _ARM64_INS_SABDL = 579;; +let _ARM64_INS_SABDL2 = 580;; +let _ARM64_INS_SADALP = 581;; +let _ARM64_INS_SADDL = 582;; +let _ARM64_INS_SADDL2 = 583;; +let _ARM64_INS_SADDLP = 584;; +let _ARM64_INS_SADDLV = 585;; +let _ARM64_INS_SADDV = 586;; +let _ARM64_INS_SADDW = 587;; +let _ARM64_INS_SADDW2 = 588;; +let _ARM64_INS_SBC = 589;; +let _ARM64_INS_SBCS = 590;; +let _ARM64_INS_SBFM = 591;; +let _ARM64_INS_SCVTF = 592;; +let _ARM64_INS_SDIV = 593;; +let _ARM64_INS_SDIVR = 594;; +let _ARM64_INS_SDOT = 595;; +let _ARM64_INS_SEL = 596;; +let _ARM64_INS_SETF16 = 597;; +let _ARM64_INS_SETF8 = 598;; +let _ARM64_INS_SETFFR = 599;; +let _ARM64_INS_SEV = 600;; +let _ARM64_INS_SEVL = 601;; +let _ARM64_INS_SHA1C = 602;; +let _ARM64_INS_SHA1H = 603;; +let _ARM64_INS_SHA1M = 604;; +let _ARM64_INS_SHA1P = 605;; +let _ARM64_INS_SHA1SU0 = 606;; +let _ARM64_INS_SHA1SU1 = 607;; +let _ARM64_INS_SHA256H = 608;; +let _ARM64_INS_SHA256H2 = 609;; +let _ARM64_INS_SHA256SU0 = 610;; +let _ARM64_INS_SHA256SU1 = 611;; +let _ARM64_INS_SHA512H = 612;; +let _ARM64_INS_SHA512H2 = 613;; +let _ARM64_INS_SHA512SU0 = 614;; +let _ARM64_INS_SHA512SU1 = 615;; +let _ARM64_INS_SHADD = 616;; +let _ARM64_INS_SHL = 617;; +let _ARM64_INS_SHLL = 618;; +let _ARM64_INS_SHLL2 = 619;; +let _ARM64_INS_SHRN = 620;; +let _ARM64_INS_SHRN2 = 621;; +let _ARM64_INS_SHSUB = 622;; +let _ARM64_INS_SLI = 623;; +let _ARM64_INS_SM3PARTW1 = 624;; +let _ARM64_INS_SM3PARTW2 = 625;; +let _ARM64_INS_SM3SS1 = 626;; +let _ARM64_INS_SM3TT1A = 627;; +let _ARM64_INS_SM3TT1B = 628;; +let _ARM64_INS_SM3TT2A = 629;; +let _ARM64_INS_SM3TT2B = 630;; +let _ARM64_INS_SM4E = 631;; +let _ARM64_INS_SM4EKEY = 632;; +let _ARM64_INS_SMADDL = 633;; +let _ARM64_INS_SMAX = 634;; +let _ARM64_INS_SMAXP = 635;; +let _ARM64_INS_SMAXV = 636;; +let _ARM64_INS_SMC = 637;; +let _ARM64_INS_SMIN = 638;; +let _ARM64_INS_SMINP = 639;; +let _ARM64_INS_SMINV = 640;; +let _ARM64_INS_SMLAL = 641;; +let _ARM64_INS_SMLAL2 = 642;; +let _ARM64_INS_SMLSL = 643;; +let _ARM64_INS_SMLSL2 = 644;; +let _ARM64_INS_SMNEGL = 645;; +let _ARM64_INS_SMOV = 646;; +let _ARM64_INS_SMSUBL = 647;; +let _ARM64_INS_SMULH = 648;; +let _ARM64_INS_SMULL = 649;; +let _ARM64_INS_SMULL2 = 650;; +let _ARM64_INS_SPLICE = 651;; +let _ARM64_INS_SQABS = 652;; +let _ARM64_INS_SQADD = 653;; +let _ARM64_INS_SQDECB = 654;; +let _ARM64_INS_SQDECD = 655;; +let _ARM64_INS_SQDECH = 656;; +let _ARM64_INS_SQDECP = 657;; +let _ARM64_INS_SQDECW = 658;; +let _ARM64_INS_SQDMLAL = 659;; +let _ARM64_INS_SQDMLAL2 = 660;; +let _ARM64_INS_SQDMLSL = 661;; +let _ARM64_INS_SQDMLSL2 = 662;; +let _ARM64_INS_SQDMULH = 663;; +let _ARM64_INS_SQDMULL = 664;; +let _ARM64_INS_SQDMULL2 = 665;; +let _ARM64_INS_SQINCB = 666;; +let _ARM64_INS_SQINCD = 667;; +let _ARM64_INS_SQINCH = 668;; +let _ARM64_INS_SQINCP = 669;; +let _ARM64_INS_SQINCW = 670;; +let _ARM64_INS_SQNEG = 671;; +let _ARM64_INS_SQRDMLAH = 672;; +let _ARM64_INS_SQRDMLSH = 673;; +let _ARM64_INS_SQRDMULH = 674;; +let _ARM64_INS_SQRSHL = 675;; +let _ARM64_INS_SQRSHRN = 676;; +let _ARM64_INS_SQRSHRN2 = 677;; +let _ARM64_INS_SQRSHRUN = 678;; +let _ARM64_INS_SQRSHRUN2 = 679;; +let _ARM64_INS_SQSHL = 680;; +let _ARM64_INS_SQSHLU = 681;; +let _ARM64_INS_SQSHRN = 682;; +let _ARM64_INS_SQSHRN2 = 683;; +let _ARM64_INS_SQSHRUN = 684;; +let _ARM64_INS_SQSHRUN2 = 685;; +let _ARM64_INS_SQSUB = 686;; +let _ARM64_INS_SQXTN = 687;; +let _ARM64_INS_SQXTN2 = 688;; +let _ARM64_INS_SQXTUN = 689;; +let _ARM64_INS_SQXTUN2 = 690;; +let _ARM64_INS_SRHADD = 691;; +let _ARM64_INS_SRI = 692;; +let _ARM64_INS_SRSHL = 693;; +let _ARM64_INS_SRSHR = 694;; +let _ARM64_INS_SRSRA = 695;; +let _ARM64_INS_SSHL = 696;; +let _ARM64_INS_SSHLL = 697;; +let _ARM64_INS_SSHLL2 = 698;; +let _ARM64_INS_SSHR = 699;; +let _ARM64_INS_SSRA = 700;; +let _ARM64_INS_SSUBL = 701;; +let _ARM64_INS_SSUBL2 = 702;; +let _ARM64_INS_SSUBW = 703;; +let _ARM64_INS_SSUBW2 = 704;; +let _ARM64_INS_ST1 = 705;; +let _ARM64_INS_ST1B = 706;; +let _ARM64_INS_ST1D = 707;; +let _ARM64_INS_ST1H = 708;; +let _ARM64_INS_ST1W = 709;; +let _ARM64_INS_ST2 = 710;; +let _ARM64_INS_ST2B = 711;; +let _ARM64_INS_ST2D = 712;; +let _ARM64_INS_ST2H = 713;; +let _ARM64_INS_ST2W = 714;; +let _ARM64_INS_ST3 = 715;; +let _ARM64_INS_ST3B = 716;; +let _ARM64_INS_ST3D = 717;; +let _ARM64_INS_ST3H = 718;; +let _ARM64_INS_ST3W = 719;; +let _ARM64_INS_ST4 = 720;; +let _ARM64_INS_ST4B = 721;; +let _ARM64_INS_ST4D = 722;; +let _ARM64_INS_ST4H = 723;; +let _ARM64_INS_ST4W = 724;; +let _ARM64_INS_STADD = 725;; +let _ARM64_INS_STADDB = 726;; +let _ARM64_INS_STADDH = 727;; +let _ARM64_INS_STADDL = 728;; +let _ARM64_INS_STADDLB = 729;; +let _ARM64_INS_STADDLH = 730;; +let _ARM64_INS_STCLR = 731;; +let _ARM64_INS_STCLRB = 732;; +let _ARM64_INS_STCLRH = 733;; +let _ARM64_INS_STCLRL = 734;; +let _ARM64_INS_STCLRLB = 735;; +let _ARM64_INS_STCLRLH = 736;; +let _ARM64_INS_STEOR = 737;; +let _ARM64_INS_STEORB = 738;; +let _ARM64_INS_STEORH = 739;; +let _ARM64_INS_STEORL = 740;; +let _ARM64_INS_STEORLB = 741;; +let _ARM64_INS_STEORLH = 742;; +let _ARM64_INS_STLLR = 743;; +let _ARM64_INS_STLLRB = 744;; +let _ARM64_INS_STLLRH = 745;; +let _ARM64_INS_STLR = 746;; +let _ARM64_INS_STLRB = 747;; +let _ARM64_INS_STLRH = 748;; +let _ARM64_INS_STLUR = 749;; +let _ARM64_INS_STLURB = 750;; +let _ARM64_INS_STLURH = 751;; +let _ARM64_INS_STLXP = 752;; +let _ARM64_INS_STLXR = 753;; +let _ARM64_INS_STLXRB = 754;; +let _ARM64_INS_STLXRH = 755;; +let _ARM64_INS_STNP = 756;; +let _ARM64_INS_STNT1B = 757;; +let _ARM64_INS_STNT1D = 758;; +let _ARM64_INS_STNT1H = 759;; +let _ARM64_INS_STNT1W = 760;; +let _ARM64_INS_STP = 761;; +let _ARM64_INS_STR = 762;; +let _ARM64_INS_STRB = 763;; +let _ARM64_INS_STRH = 764;; +let _ARM64_INS_STSET = 765;; +let _ARM64_INS_STSETB = 766;; +let _ARM64_INS_STSETH = 767;; +let _ARM64_INS_STSETL = 768;; +let _ARM64_INS_STSETLB = 769;; +let _ARM64_INS_STSETLH = 770;; +let _ARM64_INS_STSMAX = 771;; +let _ARM64_INS_STSMAXB = 772;; +let _ARM64_INS_STSMAXH = 773;; +let _ARM64_INS_STSMAXL = 774;; +let _ARM64_INS_STSMAXLB = 775;; +let _ARM64_INS_STSMAXLH = 776;; +let _ARM64_INS_STSMIN = 777;; +let _ARM64_INS_STSMINB = 778;; +let _ARM64_INS_STSMINH = 779;; +let _ARM64_INS_STSMINL = 780;; +let _ARM64_INS_STSMINLB = 781;; +let _ARM64_INS_STSMINLH = 782;; +let _ARM64_INS_STTR = 783;; +let _ARM64_INS_STTRB = 784;; +let _ARM64_INS_STTRH = 785;; +let _ARM64_INS_STUMAX = 786;; +let _ARM64_INS_STUMAXB = 787;; +let _ARM64_INS_STUMAXH = 788;; +let _ARM64_INS_STUMAXL = 789;; +let _ARM64_INS_STUMAXLB = 790;; +let _ARM64_INS_STUMAXLH = 791;; +let _ARM64_INS_STUMIN = 792;; +let _ARM64_INS_STUMINB = 793;; +let _ARM64_INS_STUMINH = 794;; +let _ARM64_INS_STUMINL = 795;; +let _ARM64_INS_STUMINLB = 796;; +let _ARM64_INS_STUMINLH = 797;; +let _ARM64_INS_STUR = 798;; +let _ARM64_INS_STURB = 799;; +let _ARM64_INS_STURH = 800;; +let _ARM64_INS_STXP = 801;; +let _ARM64_INS_STXR = 802;; +let _ARM64_INS_STXRB = 803;; +let _ARM64_INS_STXRH = 804;; +let _ARM64_INS_SUB = 805;; +let _ARM64_INS_SUBHN = 806;; +let _ARM64_INS_SUBHN2 = 807;; +let _ARM64_INS_SUBR = 808;; +let _ARM64_INS_SUBS = 809;; +let _ARM64_INS_SUNPKHI = 810;; +let _ARM64_INS_SUNPKLO = 811;; +let _ARM64_INS_SUQADD = 812;; +let _ARM64_INS_SVC = 813;; +let _ARM64_INS_SWP = 814;; +let _ARM64_INS_SWPA = 815;; +let _ARM64_INS_SWPAB = 816;; +let _ARM64_INS_SWPAH = 817;; +let _ARM64_INS_SWPAL = 818;; +let _ARM64_INS_SWPALB = 819;; +let _ARM64_INS_SWPALH = 820;; +let _ARM64_INS_SWPB = 821;; +let _ARM64_INS_SWPH = 822;; +let _ARM64_INS_SWPL = 823;; +let _ARM64_INS_SWPLB = 824;; +let _ARM64_INS_SWPLH = 825;; +let _ARM64_INS_SXTB = 826;; +let _ARM64_INS_SXTH = 827;; +let _ARM64_INS_SXTL = 828;; +let _ARM64_INS_SXTL2 = 829;; +let _ARM64_INS_SXTW = 830;; +let _ARM64_INS_SYS = 831;; +let _ARM64_INS_SYSL = 832;; +let _ARM64_INS_TBL = 833;; +let _ARM64_INS_TBNZ = 834;; +let _ARM64_INS_TBX = 835;; +let _ARM64_INS_TBZ = 836;; +let _ARM64_INS_TRN1 = 837;; +let _ARM64_INS_TRN2 = 838;; +let _ARM64_INS_TSB = 839;; +let _ARM64_INS_TST = 840;; +let _ARM64_INS_UABA = 841;; +let _ARM64_INS_UABAL = 842;; +let _ARM64_INS_UABAL2 = 843;; +let _ARM64_INS_UABD = 844;; +let _ARM64_INS_UABDL = 845;; +let _ARM64_INS_UABDL2 = 846;; +let _ARM64_INS_UADALP = 847;; +let _ARM64_INS_UADDL = 848;; +let _ARM64_INS_UADDL2 = 849;; +let _ARM64_INS_UADDLP = 850;; +let _ARM64_INS_UADDLV = 851;; +let _ARM64_INS_UADDV = 852;; +let _ARM64_INS_UADDW = 853;; +let _ARM64_INS_UADDW2 = 854;; +let _ARM64_INS_UBFM = 855;; +let _ARM64_INS_UCVTF = 856;; +let _ARM64_INS_UDIV = 857;; +let _ARM64_INS_UDIVR = 858;; +let _ARM64_INS_UDOT = 859;; +let _ARM64_INS_UHADD = 860;; +let _ARM64_INS_UHSUB = 861;; +let _ARM64_INS_UMADDL = 862;; +let _ARM64_INS_UMAX = 863;; +let _ARM64_INS_UMAXP = 864;; +let _ARM64_INS_UMAXV = 865;; +let _ARM64_INS_UMIN = 866;; +let _ARM64_INS_UMINP = 867;; +let _ARM64_INS_UMINV = 868;; +let _ARM64_INS_UMLAL = 869;; +let _ARM64_INS_UMLAL2 = 870;; +let _ARM64_INS_UMLSL = 871;; +let _ARM64_INS_UMLSL2 = 872;; +let _ARM64_INS_UMNEGL = 873;; +let _ARM64_INS_UMOV = 874;; +let _ARM64_INS_UMSUBL = 875;; +let _ARM64_INS_UMULH = 876;; +let _ARM64_INS_UMULL = 877;; +let _ARM64_INS_UMULL2 = 878;; +let _ARM64_INS_UQADD = 879;; +let _ARM64_INS_UQDECB = 880;; +let _ARM64_INS_UQDECD = 881;; +let _ARM64_INS_UQDECH = 882;; +let _ARM64_INS_UQDECP = 883;; +let _ARM64_INS_UQDECW = 884;; +let _ARM64_INS_UQINCB = 885;; +let _ARM64_INS_UQINCD = 886;; +let _ARM64_INS_UQINCH = 887;; +let _ARM64_INS_UQINCP = 888;; +let _ARM64_INS_UQINCW = 889;; +let _ARM64_INS_UQRSHL = 890;; +let _ARM64_INS_UQRSHRN = 891;; +let _ARM64_INS_UQRSHRN2 = 892;; +let _ARM64_INS_UQSHL = 893;; +let _ARM64_INS_UQSHRN = 894;; +let _ARM64_INS_UQSHRN2 = 895;; +let _ARM64_INS_UQSUB = 896;; +let _ARM64_INS_UQXTN = 897;; +let _ARM64_INS_UQXTN2 = 898;; +let _ARM64_INS_URECPE = 899;; +let _ARM64_INS_URHADD = 900;; +let _ARM64_INS_URSHL = 901;; +let _ARM64_INS_URSHR = 902;; +let _ARM64_INS_URSQRTE = 903;; +let _ARM64_INS_URSRA = 904;; +let _ARM64_INS_USHL = 905;; +let _ARM64_INS_USHLL = 906;; +let _ARM64_INS_USHLL2 = 907;; +let _ARM64_INS_USHR = 908;; +let _ARM64_INS_USQADD = 909;; +let _ARM64_INS_USRA = 910;; +let _ARM64_INS_USUBL = 911;; +let _ARM64_INS_USUBL2 = 912;; +let _ARM64_INS_USUBW = 913;; +let _ARM64_INS_USUBW2 = 914;; +let _ARM64_INS_UUNPKHI = 915;; +let _ARM64_INS_UUNPKLO = 916;; +let _ARM64_INS_UXTB = 917;; +let _ARM64_INS_UXTH = 918;; +let _ARM64_INS_UXTL = 919;; +let _ARM64_INS_UXTL2 = 920;; +let _ARM64_INS_UXTW = 921;; +let _ARM64_INS_UZP1 = 922;; +let _ARM64_INS_UZP2 = 923;; +let _ARM64_INS_WFE = 924;; +let _ARM64_INS_WFI = 925;; +let _ARM64_INS_WHILELE = 926;; +let _ARM64_INS_WHILELO = 927;; +let _ARM64_INS_WHILELS = 928;; +let _ARM64_INS_WHILELT = 929;; +let _ARM64_INS_WRFFR = 930;; +let _ARM64_INS_XAR = 931;; +let _ARM64_INS_XPACD = 932;; +let _ARM64_INS_XPACI = 933;; +let _ARM64_INS_XPACLRI = 934;; +let _ARM64_INS_XTN = 935;; +let _ARM64_INS_XTN2 = 936;; +let _ARM64_INS_YIELD = 937;; +let _ARM64_INS_ZIP1 = 938;; +let _ARM64_INS_ZIP2 = 939;; +let _ARM64_INS_SBFIZ = 940;; +let _ARM64_INS_UBFIZ = 941;; +let _ARM64_INS_SBFX = 942;; +let _ARM64_INS_UBFX = 943;; +let _ARM64_INS_BFI = 944;; +let _ARM64_INS_BFXIL = 945;; +let _ARM64_INS_IC = 946;; +let _ARM64_INS_DC = 947;; +let _ARM64_INS_AT = 948;; +let _ARM64_INS_TLBI = 949;; +let _ARM64_INS_ENDING = 950;; let _ARM64_GRP_INVALID = 0;; let _ARM64_GRP_JUMP = 1;; @@ -1003,4 +2244,17 @@ let _ARM64_GRP_CRYPTO = 128;; let _ARM64_GRP_FPARMV8 = 129;; let _ARM64_GRP_NEON = 130;; let _ARM64_GRP_CRC = 131;; -let _ARM64_GRP_ENDING = 132;; +let _ARM64_GRP_AES = 132;; +let _ARM64_GRP_DOTPROD = 133;; +let _ARM64_GRP_FULLFP16 = 134;; +let _ARM64_GRP_LSE = 135;; +let _ARM64_GRP_RCPC = 136;; +let _ARM64_GRP_RDM = 137;; +let _ARM64_GRP_SHA2 = 138;; +let _ARM64_GRP_SHA3 = 139;; +let _ARM64_GRP_SM4 = 140;; +let _ARM64_GRP_SVE = 141;; +let _ARM64_GRP_V8_1A = 142;; +let _ARM64_GRP_V8_3A = 143;; +let _ARM64_GRP_V8_4A = 144;; +let _ARM64_GRP_ENDING = 145;; diff --git a/bindings/ocaml/ocaml.c b/bindings/ocaml/ocaml.c index ac95ad26a..c74d5e60d 100644 --- a/bindings/ocaml/ocaml.c +++ b/bindings/ocaml/ocaml.c @@ -122,7 +122,7 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t if (lcount > 0) { array = caml_alloc(lcount, 0); for (i = 0; i < lcount; i++) { - tmp2 = caml_alloc(6, 0); + tmp2 = caml_alloc(5, 0); switch(insn[j-1].detail->arm.operands[i].type) { case ARM_OP_REG: case ARM_OP_SYSREG: @@ -253,10 +253,9 @@ CAMLprim value _cs_disasm(cs_arch arch, csh handle, const uint8_t * code, size_t Store_field(tmp2, 0, Val_int(insn[j-1].detail->arm64.operands[i].vector_index)); Store_field(tmp2, 1, Val_int(insn[j-1].detail->arm64.operands[i].vas)); - Store_field(tmp2, 2, Val_int(insn[j-1].detail->arm64.operands[i].vess)); - Store_field(tmp2, 3, tmp3); - Store_field(tmp2, 4, Val_int(insn[j-1].detail->arm64.operands[i].ext)); - Store_field(tmp2, 5, tmp); + Store_field(tmp2, 2, tmp3); + Store_field(tmp2, 3, Val_int(insn[j-1].detail->arm64.operands[i].ext)); + Store_field(tmp2, 4, tmp); Store_field(array, i, tmp2); } diff --git a/bindings/python/capstone/arm64.py b/bindings/python/capstone/arm64.py index 1d4efc309..ffd2469fe 100644 --- a/bindings/python/capstone/arm64.py +++ b/bindings/python/capstone/arm64.py @@ -34,7 +34,6 @@ class Arm64Op(ctypes.Structure): _fields_ = ( ('vector_index', ctypes.c_int), ('vas', ctypes.c_int), - ('vess', ctypes.c_int), ('shift', Arm64OpShift), ('ext', ctypes.c_uint), ('type', ctypes.c_uint), diff --git a/bindings/python/capstone/arm64_const.py b/bindings/python/capstone/arm64_const.py index c5efab662..43d7f3df6 100644 --- a/bindings/python/capstone/arm64_const.py +++ b/bindings/python/capstone/arm64_const.py @@ -39,95 +39,740 @@ ARM64_SYSREG_INVALID = 0 ARM64_SYSREG_MDCCSR_EL0 = 0x9808 ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828 ARM64_SYSREG_MDRAR_EL1 = 0x8080 -ARM64_SYSREG_OSLSR_EL1 = 0x808c -ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6 -ARM64_SYSREG_PMCEID0_EL0 = 0xdce6 -ARM64_SYSREG_PMCEID1_EL0 = 0xdce7 -ARM64_SYSREG_MIDR_EL1 = 0xc000 -ARM64_SYSREG_CCSIDR_EL1 = 0xc800 -ARM64_SYSREG_CLIDR_EL1 = 0xc801 -ARM64_SYSREG_CTR_EL0 = 0xd801 -ARM64_SYSREG_MPIDR_EL1 = 0xc005 -ARM64_SYSREG_REVIDR_EL1 = 0xc006 -ARM64_SYSREG_AIDR_EL1 = 0xc807 -ARM64_SYSREG_DCZID_EL0 = 0xd807 -ARM64_SYSREG_ID_PFR0_EL1 = 0xc008 -ARM64_SYSREG_ID_PFR1_EL1 = 0xc009 -ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a -ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b -ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c -ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d -ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e -ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f -ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010 -ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011 -ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012 -ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013 -ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014 -ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015 -ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020 -ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021 -ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028 -ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029 -ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c -ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d -ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030 -ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031 -ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038 -ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039 -ARM64_SYSREG_MVFR0_EL1 = 0xc018 -ARM64_SYSREG_MVFR1_EL1 = 0xc019 -ARM64_SYSREG_MVFR2_EL1 = 0xc01a -ARM64_SYSREG_RVBAR_EL1 = 0xc601 -ARM64_SYSREG_RVBAR_EL2 = 0xe601 -ARM64_SYSREG_RVBAR_EL3 = 0xf601 -ARM64_SYSREG_ISR_EL1 = 0xc608 -ARM64_SYSREG_CNTPCT_EL0 = 0xdf01 -ARM64_SYSREG_CNTVCT_EL0 = 0xdf02 +ARM64_SYSREG_OSLSR_EL1 = 0x808C +ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6 +ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6 +ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7 +ARM64_SYSREG_MIDR_EL1 = 0xC000 +ARM64_SYSREG_CCSIDR_EL1 = 0xC800 +ARM64_SYSREG_CCSIDR2_EL1 = 0xC802 +ARM64_SYSREG_CLIDR_EL1 = 0xC801 +ARM64_SYSREG_CTR_EL0 = 0xD801 +ARM64_SYSREG_MPIDR_EL1 = 0xC005 +ARM64_SYSREG_REVIDR_EL1 = 0xC006 +ARM64_SYSREG_AIDR_EL1 = 0xC807 +ARM64_SYSREG_DCZID_EL0 = 0xD807 +ARM64_SYSREG_ID_PFR0_EL1 = 0xC008 +ARM64_SYSREG_ID_PFR1_EL1 = 0xC009 +ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A +ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B +ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C +ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D +ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E +ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F +ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010 +ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011 +ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012 +ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013 +ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014 +ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015 +ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017 +ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020 +ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021 +ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028 +ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029 +ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C +ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D +ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030 +ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031 +ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038 +ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039 +ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A +ARM64_SYSREG_MVFR0_EL1 = 0xC018 +ARM64_SYSREG_MVFR1_EL1 = 0xC019 +ARM64_SYSREG_MVFR2_EL1 = 0xC01A +ARM64_SYSREG_RVBAR_EL1 = 0xC601 +ARM64_SYSREG_RVBAR_EL2 = 0xE601 +ARM64_SYSREG_RVBAR_EL3 = 0xF601 +ARM64_SYSREG_ISR_EL1 = 0xC608 +ARM64_SYSREG_CNTPCT_EL0 = 0xDF01 +ARM64_SYSREG_CNTVCT_EL0 = 0xDF02 +ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016 ARM64_SYSREG_TRCSTATR = 0x8818 ARM64_SYSREG_TRCIDR8 = 0x8806 -ARM64_SYSREG_TRCIDR9 = 0x880e +ARM64_SYSREG_TRCIDR9 = 0x880E ARM64_SYSREG_TRCIDR10 = 0x8816 -ARM64_SYSREG_TRCIDR11 = 0x881e +ARM64_SYSREG_TRCIDR11 = 0x881E ARM64_SYSREG_TRCIDR12 = 0x8826 -ARM64_SYSREG_TRCIDR13 = 0x882e +ARM64_SYSREG_TRCIDR13 = 0x882E ARM64_SYSREG_TRCIDR0 = 0x8847 -ARM64_SYSREG_TRCIDR1 = 0x884f +ARM64_SYSREG_TRCIDR1 = 0x884F ARM64_SYSREG_TRCIDR2 = 0x8857 -ARM64_SYSREG_TRCIDR3 = 0x885f +ARM64_SYSREG_TRCIDR3 = 0x885F ARM64_SYSREG_TRCIDR4 = 0x8867 -ARM64_SYSREG_TRCIDR5 = 0x886f +ARM64_SYSREG_TRCIDR5 = 0x886F ARM64_SYSREG_TRCIDR6 = 0x8877 -ARM64_SYSREG_TRCIDR7 = 0x887f -ARM64_SYSREG_TRCOSLSR = 0x888c -ARM64_SYSREG_TRCPDSR = 0x88ac -ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6 -ARM64_SYSREG_TRCDEVAFF1 = 0x8bde -ARM64_SYSREG_TRCLSR = 0x8bee -ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6 -ARM64_SYSREG_TRCDEVARCH = 0x8bfe -ARM64_SYSREG_TRCDEVID = 0x8b97 -ARM64_SYSREG_TRCDEVTYPE = 0x8b9f -ARM64_SYSREG_TRCPIDR4 = 0x8ba7 -ARM64_SYSREG_TRCPIDR5 = 0x8baf -ARM64_SYSREG_TRCPIDR6 = 0x8bb7 -ARM64_SYSREG_TRCPIDR7 = 0x8bbf -ARM64_SYSREG_TRCPIDR0 = 0x8bc7 -ARM64_SYSREG_TRCPIDR1 = 0x8bcf -ARM64_SYSREG_TRCPIDR2 = 0x8bd7 -ARM64_SYSREG_TRCPIDR3 = 0x8bdf -ARM64_SYSREG_TRCCIDR0 = 0x8be7 -ARM64_SYSREG_TRCCIDR1 = 0x8bef -ARM64_SYSREG_TRCCIDR2 = 0x8bf7 -ARM64_SYSREG_TRCCIDR3 = 0x8bff -ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660 -ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640 -ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662 -ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642 -ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b -ARM64_SYSREG_ICH_VTR_EL2 = 0xe659 -ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b -ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d +ARM64_SYSREG_TRCIDR7 = 0x887F +ARM64_SYSREG_TRCOSLSR = 0x888C +ARM64_SYSREG_TRCPDSR = 0x88AC +ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6 +ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE +ARM64_SYSREG_TRCLSR = 0x8BEE +ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6 +ARM64_SYSREG_TRCDEVARCH = 0x8BFE +ARM64_SYSREG_TRCDEVID = 0x8B97 +ARM64_SYSREG_TRCDEVTYPE = 0x8B9F +ARM64_SYSREG_TRCPIDR4 = 0x8BA7 +ARM64_SYSREG_TRCPIDR5 = 0x8BAF +ARM64_SYSREG_TRCPIDR6 = 0x8BB7 +ARM64_SYSREG_TRCPIDR7 = 0x8BBF +ARM64_SYSREG_TRCPIDR0 = 0x8BC7 +ARM64_SYSREG_TRCPIDR1 = 0x8BCF +ARM64_SYSREG_TRCPIDR2 = 0x8BD7 +ARM64_SYSREG_TRCPIDR3 = 0x8BDF +ARM64_SYSREG_TRCCIDR0 = 0x8BE7 +ARM64_SYSREG_TRCCIDR1 = 0x8BEF +ARM64_SYSREG_TRCCIDR2 = 0x8BF7 +ARM64_SYSREG_TRCCIDR3 = 0x8BFF +ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660 +ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640 +ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662 +ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642 +ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B +ARM64_SYSREG_ICH_VTR_EL2 = 0xE659 +ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B +ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D +ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024 +ARM64_SYSREG_LORID_EL1 = 0xC527 +ARM64_SYSREG_ERRIDR_EL1 = 0xC298 +ARM64_SYSREG_ERXFR_EL1 = 0xC2A0 +ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828 +ARM64_SYSREG_OSLAR_EL1 = 0x8084 +ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4 +ARM64_SYSREG_TRCOSLAR = 0x8884 +ARM64_SYSREG_TRCLAR = 0x8BE6 +ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661 +ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641 +ARM64_SYSREG_ICC_DIR_EL1 = 0xC659 +ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D +ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E +ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F +ARM64_SYSREG_OSDTRRX_EL1 = 0x8002 +ARM64_SYSREG_OSDTRTX_EL1 = 0x801A +ARM64_SYSREG_TEECR32_EL1 = 0x9000 +ARM64_SYSREG_MDCCINT_EL1 = 0x8010 +ARM64_SYSREG_MDSCR_EL1 = 0x8012 +ARM64_SYSREG_DBGDTR_EL0 = 0x9820 +ARM64_SYSREG_OSECCR_EL1 = 0x8032 +ARM64_SYSREG_DBGVCR32_EL2 = 0xA038 +ARM64_SYSREG_DBGBVR0_EL1 = 0x8004 +ARM64_SYSREG_DBGBVR1_EL1 = 0x800C +ARM64_SYSREG_DBGBVR2_EL1 = 0x8014 +ARM64_SYSREG_DBGBVR3_EL1 = 0x801C +ARM64_SYSREG_DBGBVR4_EL1 = 0x8024 +ARM64_SYSREG_DBGBVR5_EL1 = 0x802C +ARM64_SYSREG_DBGBVR6_EL1 = 0x8034 +ARM64_SYSREG_DBGBVR7_EL1 = 0x803C +ARM64_SYSREG_DBGBVR8_EL1 = 0x8044 +ARM64_SYSREG_DBGBVR9_EL1 = 0x804C +ARM64_SYSREG_DBGBVR10_EL1 = 0x8054 +ARM64_SYSREG_DBGBVR11_EL1 = 0x805C +ARM64_SYSREG_DBGBVR12_EL1 = 0x8064 +ARM64_SYSREG_DBGBVR13_EL1 = 0x806C +ARM64_SYSREG_DBGBVR14_EL1 = 0x8074 +ARM64_SYSREG_DBGBVR15_EL1 = 0x807C +ARM64_SYSREG_DBGBCR0_EL1 = 0x8005 +ARM64_SYSREG_DBGBCR1_EL1 = 0x800D +ARM64_SYSREG_DBGBCR2_EL1 = 0x8015 +ARM64_SYSREG_DBGBCR3_EL1 = 0x801D +ARM64_SYSREG_DBGBCR4_EL1 = 0x8025 +ARM64_SYSREG_DBGBCR5_EL1 = 0x802D +ARM64_SYSREG_DBGBCR6_EL1 = 0x8035 +ARM64_SYSREG_DBGBCR7_EL1 = 0x803D +ARM64_SYSREG_DBGBCR8_EL1 = 0x8045 +ARM64_SYSREG_DBGBCR9_EL1 = 0x804D +ARM64_SYSREG_DBGBCR10_EL1 = 0x8055 +ARM64_SYSREG_DBGBCR11_EL1 = 0x805D +ARM64_SYSREG_DBGBCR12_EL1 = 0x8065 +ARM64_SYSREG_DBGBCR13_EL1 = 0x806D +ARM64_SYSREG_DBGBCR14_EL1 = 0x8075 +ARM64_SYSREG_DBGBCR15_EL1 = 0x807D +ARM64_SYSREG_DBGWVR0_EL1 = 0x8006 +ARM64_SYSREG_DBGWVR1_EL1 = 0x800E +ARM64_SYSREG_DBGWVR2_EL1 = 0x8016 +ARM64_SYSREG_DBGWVR3_EL1 = 0x801E +ARM64_SYSREG_DBGWVR4_EL1 = 0x8026 +ARM64_SYSREG_DBGWVR5_EL1 = 0x802E +ARM64_SYSREG_DBGWVR6_EL1 = 0x8036 +ARM64_SYSREG_DBGWVR7_EL1 = 0x803E +ARM64_SYSREG_DBGWVR8_EL1 = 0x8046 +ARM64_SYSREG_DBGWVR9_EL1 = 0x804E +ARM64_SYSREG_DBGWVR10_EL1 = 0x8056 +ARM64_SYSREG_DBGWVR11_EL1 = 0x805E +ARM64_SYSREG_DBGWVR12_EL1 = 0x8066 +ARM64_SYSREG_DBGWVR13_EL1 = 0x806E +ARM64_SYSREG_DBGWVR14_EL1 = 0x8076 +ARM64_SYSREG_DBGWVR15_EL1 = 0x807E +ARM64_SYSREG_DBGWCR0_EL1 = 0x8007 +ARM64_SYSREG_DBGWCR1_EL1 = 0x800F +ARM64_SYSREG_DBGWCR2_EL1 = 0x8017 +ARM64_SYSREG_DBGWCR3_EL1 = 0x801F +ARM64_SYSREG_DBGWCR4_EL1 = 0x8027 +ARM64_SYSREG_DBGWCR5_EL1 = 0x802F +ARM64_SYSREG_DBGWCR6_EL1 = 0x8037 +ARM64_SYSREG_DBGWCR7_EL1 = 0x803F +ARM64_SYSREG_DBGWCR8_EL1 = 0x8047 +ARM64_SYSREG_DBGWCR9_EL1 = 0x804F +ARM64_SYSREG_DBGWCR10_EL1 = 0x8057 +ARM64_SYSREG_DBGWCR11_EL1 = 0x805F +ARM64_SYSREG_DBGWCR12_EL1 = 0x8067 +ARM64_SYSREG_DBGWCR13_EL1 = 0x806F +ARM64_SYSREG_DBGWCR14_EL1 = 0x8077 +ARM64_SYSREG_DBGWCR15_EL1 = 0x807F +ARM64_SYSREG_TEEHBR32_EL1 = 0x9080 +ARM64_SYSREG_OSDLR_EL1 = 0x809C +ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4 +ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6 +ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE +ARM64_SYSREG_CSSELR_EL1 = 0xD000 +ARM64_SYSREG_VPIDR_EL2 = 0xE000 +ARM64_SYSREG_VMPIDR_EL2 = 0xE005 +ARM64_SYSREG_CPACR_EL1 = 0xC082 +ARM64_SYSREG_SCTLR_EL1 = 0xC080 +ARM64_SYSREG_SCTLR_EL2 = 0xE080 +ARM64_SYSREG_SCTLR_EL3 = 0xF080 +ARM64_SYSREG_ACTLR_EL1 = 0xC081 +ARM64_SYSREG_ACTLR_EL2 = 0xE081 +ARM64_SYSREG_ACTLR_EL3 = 0xF081 +ARM64_SYSREG_HCR_EL2 = 0xE088 +ARM64_SYSREG_SCR_EL3 = 0xF088 +ARM64_SYSREG_MDCR_EL2 = 0xE089 +ARM64_SYSREG_SDER32_EL3 = 0xF089 +ARM64_SYSREG_CPTR_EL2 = 0xE08A +ARM64_SYSREG_CPTR_EL3 = 0xF08A +ARM64_SYSREG_HSTR_EL2 = 0xE08B +ARM64_SYSREG_HACR_EL2 = 0xE08F +ARM64_SYSREG_MDCR_EL3 = 0xF099 +ARM64_SYSREG_TTBR0_EL1 = 0xC100 +ARM64_SYSREG_TTBR0_EL2 = 0xE100 +ARM64_SYSREG_TTBR0_EL3 = 0xF100 +ARM64_SYSREG_TTBR1_EL1 = 0xC101 +ARM64_SYSREG_TCR_EL1 = 0xC102 +ARM64_SYSREG_TCR_EL2 = 0xE102 +ARM64_SYSREG_TCR_EL3 = 0xF102 +ARM64_SYSREG_VTTBR_EL2 = 0xE108 +ARM64_SYSREG_VTCR_EL2 = 0xE10A +ARM64_SYSREG_DACR32_EL2 = 0xE180 +ARM64_SYSREG_SPSR_EL1 = 0xC200 +ARM64_SYSREG_SPSR_EL2 = 0xE200 +ARM64_SYSREG_SPSR_EL3 = 0xF200 +ARM64_SYSREG_ELR_EL1 = 0xC201 +ARM64_SYSREG_ELR_EL2 = 0xE201 +ARM64_SYSREG_ELR_EL3 = 0xF201 +ARM64_SYSREG_SP_EL0 = 0xC208 +ARM64_SYSREG_SP_EL1 = 0xE208 +ARM64_SYSREG_SP_EL2 = 0xF208 +ARM64_SYSREG_SPSEL = 0xC210 +ARM64_SYSREG_NZCV = 0xDA10 +ARM64_SYSREG_DAIF = 0xDA11 +ARM64_SYSREG_CURRENTEL = 0xC212 +ARM64_SYSREG_SPSR_IRQ = 0xE218 +ARM64_SYSREG_SPSR_ABT = 0xE219 +ARM64_SYSREG_SPSR_UND = 0xE21A +ARM64_SYSREG_SPSR_FIQ = 0xE21B +ARM64_SYSREG_FPCR = 0xDA20 +ARM64_SYSREG_FPSR = 0xDA21 +ARM64_SYSREG_DSPSR_EL0 = 0xDA28 +ARM64_SYSREG_DLR_EL0 = 0xDA29 +ARM64_SYSREG_IFSR32_EL2 = 0xE281 +ARM64_SYSREG_AFSR0_EL1 = 0xC288 +ARM64_SYSREG_AFSR0_EL2 = 0xE288 +ARM64_SYSREG_AFSR0_EL3 = 0xF288 +ARM64_SYSREG_AFSR1_EL1 = 0xC289 +ARM64_SYSREG_AFSR1_EL2 = 0xE289 +ARM64_SYSREG_AFSR1_EL3 = 0xF289 +ARM64_SYSREG_ESR_EL1 = 0xC290 +ARM64_SYSREG_ESR_EL2 = 0xE290 +ARM64_SYSREG_ESR_EL3 = 0xF290 +ARM64_SYSREG_FPEXC32_EL2 = 0xE298 +ARM64_SYSREG_FAR_EL1 = 0xC300 +ARM64_SYSREG_FAR_EL2 = 0xE300 +ARM64_SYSREG_FAR_EL3 = 0xF300 +ARM64_SYSREG_HPFAR_EL2 = 0xE304 +ARM64_SYSREG_PAR_EL1 = 0xC3A0 +ARM64_SYSREG_PMCR_EL0 = 0xDCE0 +ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1 +ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2 +ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3 +ARM64_SYSREG_PMSELR_EL0 = 0xDCE5 +ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8 +ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9 +ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA +ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0 +ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1 +ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2 +ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3 +ARM64_SYSREG_MAIR_EL1 = 0xC510 +ARM64_SYSREG_MAIR_EL2 = 0xE510 +ARM64_SYSREG_MAIR_EL3 = 0xF510 +ARM64_SYSREG_AMAIR_EL1 = 0xC518 +ARM64_SYSREG_AMAIR_EL2 = 0xE518 +ARM64_SYSREG_AMAIR_EL3 = 0xF518 +ARM64_SYSREG_VBAR_EL1 = 0xC600 +ARM64_SYSREG_VBAR_EL2 = 0xE600 +ARM64_SYSREG_VBAR_EL3 = 0xF600 +ARM64_SYSREG_RMR_EL1 = 0xC602 +ARM64_SYSREG_RMR_EL2 = 0xE602 +ARM64_SYSREG_RMR_EL3 = 0xF602 +ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681 +ARM64_SYSREG_TPIDR_EL0 = 0xDE82 +ARM64_SYSREG_TPIDR_EL2 = 0xE682 +ARM64_SYSREG_TPIDR_EL3 = 0xF682 +ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83 +ARM64_SYSREG_TPIDR_EL1 = 0xC684 +ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00 +ARM64_SYSREG_CNTVOFF_EL2 = 0xE703 +ARM64_SYSREG_CNTKCTL_EL1 = 0xC708 +ARM64_SYSREG_CNTHCTL_EL2 = 0xE708 +ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10 +ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710 +ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10 +ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11 +ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711 +ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11 +ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12 +ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712 +ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12 +ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18 +ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19 +ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A +ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40 +ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41 +ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42 +ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43 +ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44 +ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45 +ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46 +ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47 +ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48 +ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49 +ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A +ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B +ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C +ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D +ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E +ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F +ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50 +ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51 +ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52 +ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53 +ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54 +ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55 +ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56 +ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57 +ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58 +ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59 +ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A +ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B +ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C +ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D +ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E +ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F +ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60 +ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61 +ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62 +ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63 +ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64 +ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65 +ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66 +ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67 +ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68 +ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69 +ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A +ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B +ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C +ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D +ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E +ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F +ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70 +ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71 +ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72 +ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73 +ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74 +ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75 +ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76 +ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77 +ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78 +ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79 +ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A +ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B +ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C +ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D +ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E +ARM64_SYSREG_TRCPRGCTLR = 0x8808 +ARM64_SYSREG_TRCPROCSELR = 0x8810 +ARM64_SYSREG_TRCCONFIGR = 0x8820 +ARM64_SYSREG_TRCAUXCTLR = 0x8830 +ARM64_SYSREG_TRCEVENTCTL0R = 0x8840 +ARM64_SYSREG_TRCEVENTCTL1R = 0x8848 +ARM64_SYSREG_TRCSTALLCTLR = 0x8858 +ARM64_SYSREG_TRCTSCTLR = 0x8860 +ARM64_SYSREG_TRCSYNCPR = 0x8868 +ARM64_SYSREG_TRCCCCTLR = 0x8870 +ARM64_SYSREG_TRCBBCTLR = 0x8878 +ARM64_SYSREG_TRCTRACEIDR = 0x8801 +ARM64_SYSREG_TRCQCTLR = 0x8809 +ARM64_SYSREG_TRCVICTLR = 0x8802 +ARM64_SYSREG_TRCVIIECTLR = 0x880A +ARM64_SYSREG_TRCVISSCTLR = 0x8812 +ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A +ARM64_SYSREG_TRCVDCTLR = 0x8842 +ARM64_SYSREG_TRCVDSACCTLR = 0x884A +ARM64_SYSREG_TRCVDARCCTLR = 0x8852 +ARM64_SYSREG_TRCSEQEVR0 = 0x8804 +ARM64_SYSREG_TRCSEQEVR1 = 0x880C +ARM64_SYSREG_TRCSEQEVR2 = 0x8814 +ARM64_SYSREG_TRCSEQRSTEVR = 0x8834 +ARM64_SYSREG_TRCSEQSTR = 0x883C +ARM64_SYSREG_TRCEXTINSELR = 0x8844 +ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805 +ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D +ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815 +ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D +ARM64_SYSREG_TRCCNTCTLR0 = 0x8825 +ARM64_SYSREG_TRCCNTCTLR1 = 0x882D +ARM64_SYSREG_TRCCNTCTLR2 = 0x8835 +ARM64_SYSREG_TRCCNTCTLR3 = 0x883D +ARM64_SYSREG_TRCCNTVR0 = 0x8845 +ARM64_SYSREG_TRCCNTVR1 = 0x884D +ARM64_SYSREG_TRCCNTVR2 = 0x8855 +ARM64_SYSREG_TRCCNTVR3 = 0x885D +ARM64_SYSREG_TRCIMSPEC0 = 0x8807 +ARM64_SYSREG_TRCIMSPEC1 = 0x880F +ARM64_SYSREG_TRCIMSPEC2 = 0x8817 +ARM64_SYSREG_TRCIMSPEC3 = 0x881F +ARM64_SYSREG_TRCIMSPEC4 = 0x8827 +ARM64_SYSREG_TRCIMSPEC5 = 0x882F +ARM64_SYSREG_TRCIMSPEC6 = 0x8837 +ARM64_SYSREG_TRCIMSPEC7 = 0x883F +ARM64_SYSREG_TRCRSCTLR2 = 0x8890 +ARM64_SYSREG_TRCRSCTLR3 = 0x8898 +ARM64_SYSREG_TRCRSCTLR4 = 0x88A0 +ARM64_SYSREG_TRCRSCTLR5 = 0x88A8 +ARM64_SYSREG_TRCRSCTLR6 = 0x88B0 +ARM64_SYSREG_TRCRSCTLR7 = 0x88B8 +ARM64_SYSREG_TRCRSCTLR8 = 0x88C0 +ARM64_SYSREG_TRCRSCTLR9 = 0x88C8 +ARM64_SYSREG_TRCRSCTLR10 = 0x88D0 +ARM64_SYSREG_TRCRSCTLR11 = 0x88D8 +ARM64_SYSREG_TRCRSCTLR12 = 0x88E0 +ARM64_SYSREG_TRCRSCTLR13 = 0x88E8 +ARM64_SYSREG_TRCRSCTLR14 = 0x88F0 +ARM64_SYSREG_TRCRSCTLR15 = 0x88F8 +ARM64_SYSREG_TRCRSCTLR16 = 0x8881 +ARM64_SYSREG_TRCRSCTLR17 = 0x8889 +ARM64_SYSREG_TRCRSCTLR18 = 0x8891 +ARM64_SYSREG_TRCRSCTLR19 = 0x8899 +ARM64_SYSREG_TRCRSCTLR20 = 0x88A1 +ARM64_SYSREG_TRCRSCTLR21 = 0x88A9 +ARM64_SYSREG_TRCRSCTLR22 = 0x88B1 +ARM64_SYSREG_TRCRSCTLR23 = 0x88B9 +ARM64_SYSREG_TRCRSCTLR24 = 0x88C1 +ARM64_SYSREG_TRCRSCTLR25 = 0x88C9 +ARM64_SYSREG_TRCRSCTLR26 = 0x88D1 +ARM64_SYSREG_TRCRSCTLR27 = 0x88D9 +ARM64_SYSREG_TRCRSCTLR28 = 0x88E1 +ARM64_SYSREG_TRCRSCTLR29 = 0x88E9 +ARM64_SYSREG_TRCRSCTLR30 = 0x88F1 +ARM64_SYSREG_TRCRSCTLR31 = 0x88F9 +ARM64_SYSREG_TRCSSCCR0 = 0x8882 +ARM64_SYSREG_TRCSSCCR1 = 0x888A +ARM64_SYSREG_TRCSSCCR2 = 0x8892 +ARM64_SYSREG_TRCSSCCR3 = 0x889A +ARM64_SYSREG_TRCSSCCR4 = 0x88A2 +ARM64_SYSREG_TRCSSCCR5 = 0x88AA +ARM64_SYSREG_TRCSSCCR6 = 0x88B2 +ARM64_SYSREG_TRCSSCCR7 = 0x88BA +ARM64_SYSREG_TRCSSCSR0 = 0x88C2 +ARM64_SYSREG_TRCSSCSR1 = 0x88CA +ARM64_SYSREG_TRCSSCSR2 = 0x88D2 +ARM64_SYSREG_TRCSSCSR3 = 0x88DA +ARM64_SYSREG_TRCSSCSR4 = 0x88E2 +ARM64_SYSREG_TRCSSCSR5 = 0x88EA +ARM64_SYSREG_TRCSSCSR6 = 0x88F2 +ARM64_SYSREG_TRCSSCSR7 = 0x88FA +ARM64_SYSREG_TRCSSPCICR0 = 0x8883 +ARM64_SYSREG_TRCSSPCICR1 = 0x888B +ARM64_SYSREG_TRCSSPCICR2 = 0x8893 +ARM64_SYSREG_TRCSSPCICR3 = 0x889B +ARM64_SYSREG_TRCSSPCICR4 = 0x88A3 +ARM64_SYSREG_TRCSSPCICR5 = 0x88AB +ARM64_SYSREG_TRCSSPCICR6 = 0x88B3 +ARM64_SYSREG_TRCSSPCICR7 = 0x88BB +ARM64_SYSREG_TRCPDCR = 0x88A4 +ARM64_SYSREG_TRCACVR0 = 0x8900 +ARM64_SYSREG_TRCACVR1 = 0x8910 +ARM64_SYSREG_TRCACVR2 = 0x8920 +ARM64_SYSREG_TRCACVR3 = 0x8930 +ARM64_SYSREG_TRCACVR4 = 0x8940 +ARM64_SYSREG_TRCACVR5 = 0x8950 +ARM64_SYSREG_TRCACVR6 = 0x8960 +ARM64_SYSREG_TRCACVR7 = 0x8970 +ARM64_SYSREG_TRCACVR8 = 0x8901 +ARM64_SYSREG_TRCACVR9 = 0x8911 +ARM64_SYSREG_TRCACVR10 = 0x8921 +ARM64_SYSREG_TRCACVR11 = 0x8931 +ARM64_SYSREG_TRCACVR12 = 0x8941 +ARM64_SYSREG_TRCACVR13 = 0x8951 +ARM64_SYSREG_TRCACVR14 = 0x8961 +ARM64_SYSREG_TRCACVR15 = 0x8971 +ARM64_SYSREG_TRCACATR0 = 0x8902 +ARM64_SYSREG_TRCACATR1 = 0x8912 +ARM64_SYSREG_TRCACATR2 = 0x8922 +ARM64_SYSREG_TRCACATR3 = 0x8932 +ARM64_SYSREG_TRCACATR4 = 0x8942 +ARM64_SYSREG_TRCACATR5 = 0x8952 +ARM64_SYSREG_TRCACATR6 = 0x8962 +ARM64_SYSREG_TRCACATR7 = 0x8972 +ARM64_SYSREG_TRCACATR8 = 0x8903 +ARM64_SYSREG_TRCACATR9 = 0x8913 +ARM64_SYSREG_TRCACATR10 = 0x8923 +ARM64_SYSREG_TRCACATR11 = 0x8933 +ARM64_SYSREG_TRCACATR12 = 0x8943 +ARM64_SYSREG_TRCACATR13 = 0x8953 +ARM64_SYSREG_TRCACATR14 = 0x8963 +ARM64_SYSREG_TRCACATR15 = 0x8973 +ARM64_SYSREG_TRCDVCVR0 = 0x8904 +ARM64_SYSREG_TRCDVCVR1 = 0x8924 +ARM64_SYSREG_TRCDVCVR2 = 0x8944 +ARM64_SYSREG_TRCDVCVR3 = 0x8964 +ARM64_SYSREG_TRCDVCVR4 = 0x8905 +ARM64_SYSREG_TRCDVCVR5 = 0x8925 +ARM64_SYSREG_TRCDVCVR6 = 0x8945 +ARM64_SYSREG_TRCDVCVR7 = 0x8965 +ARM64_SYSREG_TRCDVCMR0 = 0x8906 +ARM64_SYSREG_TRCDVCMR1 = 0x8926 +ARM64_SYSREG_TRCDVCMR2 = 0x8946 +ARM64_SYSREG_TRCDVCMR3 = 0x8966 +ARM64_SYSREG_TRCDVCMR4 = 0x8907 +ARM64_SYSREG_TRCDVCMR5 = 0x8927 +ARM64_SYSREG_TRCDVCMR6 = 0x8947 +ARM64_SYSREG_TRCDVCMR7 = 0x8967 +ARM64_SYSREG_TRCCIDCVR0 = 0x8980 +ARM64_SYSREG_TRCCIDCVR1 = 0x8990 +ARM64_SYSREG_TRCCIDCVR2 = 0x89A0 +ARM64_SYSREG_TRCCIDCVR3 = 0x89B0 +ARM64_SYSREG_TRCCIDCVR4 = 0x89C0 +ARM64_SYSREG_TRCCIDCVR5 = 0x89D0 +ARM64_SYSREG_TRCCIDCVR6 = 0x89E0 +ARM64_SYSREG_TRCCIDCVR7 = 0x89F0 +ARM64_SYSREG_TRCVMIDCVR0 = 0x8981 +ARM64_SYSREG_TRCVMIDCVR1 = 0x8991 +ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1 +ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1 +ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1 +ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1 +ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1 +ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1 +ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982 +ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A +ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992 +ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A +ARM64_SYSREG_TRCITCTRL = 0x8B84 +ARM64_SYSREG_TRCCLAIMSET = 0x8BC6 +ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE +ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663 +ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643 +ARM64_SYSREG_ICC_PMR_EL1 = 0xC230 +ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664 +ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664 +ARM64_SYSREG_ICC_SRE_EL1 = 0xC665 +ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D +ARM64_SYSREG_ICC_SRE_EL3 = 0xF665 +ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666 +ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667 +ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667 +ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668 +ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644 +ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645 +ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646 +ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647 +ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648 +ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649 +ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A +ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B +ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640 +ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641 +ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642 +ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643 +ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648 +ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649 +ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A +ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B +ARM64_SYSREG_ICH_HCR_EL2 = 0xE658 +ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A +ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F +ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C +ARM64_SYSREG_ICH_LR0_EL2 = 0xE660 +ARM64_SYSREG_ICH_LR1_EL2 = 0xE661 +ARM64_SYSREG_ICH_LR2_EL2 = 0xE662 +ARM64_SYSREG_ICH_LR3_EL2 = 0xE663 +ARM64_SYSREG_ICH_LR4_EL2 = 0xE664 +ARM64_SYSREG_ICH_LR5_EL2 = 0xE665 +ARM64_SYSREG_ICH_LR6_EL2 = 0xE666 +ARM64_SYSREG_ICH_LR7_EL2 = 0xE667 +ARM64_SYSREG_ICH_LR8_EL2 = 0xE668 +ARM64_SYSREG_ICH_LR9_EL2 = 0xE669 +ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A +ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B +ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C +ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D +ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E +ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F +ARM64_SYSREG_PAN = 0xC213 +ARM64_SYSREG_LORSA_EL1 = 0xC520 +ARM64_SYSREG_LOREA_EL1 = 0xC521 +ARM64_SYSREG_LORN_EL1 = 0xC522 +ARM64_SYSREG_LORC_EL1 = 0xC523 +ARM64_SYSREG_TTBR1_EL2 = 0xE101 +ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681 +ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718 +ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A +ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719 +ARM64_SYSREG_SCTLR_EL12 = 0xE880 +ARM64_SYSREG_CPACR_EL12 = 0xE882 +ARM64_SYSREG_TTBR0_EL12 = 0xE900 +ARM64_SYSREG_TTBR1_EL12 = 0xE901 +ARM64_SYSREG_TCR_EL12 = 0xE902 +ARM64_SYSREG_AFSR0_EL12 = 0xEA88 +ARM64_SYSREG_AFSR1_EL12 = 0xEA89 +ARM64_SYSREG_ESR_EL12 = 0xEA90 +ARM64_SYSREG_FAR_EL12 = 0xEB00 +ARM64_SYSREG_MAIR_EL12 = 0xED10 +ARM64_SYSREG_AMAIR_EL12 = 0xED18 +ARM64_SYSREG_VBAR_EL12 = 0xEE00 +ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81 +ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08 +ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10 +ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11 +ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12 +ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18 +ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19 +ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A +ARM64_SYSREG_SPSR_EL12 = 0xEA00 +ARM64_SYSREG_ELR_EL12 = 0xEA01 +ARM64_SYSREG_UAO = 0xC214 +ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0 +ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1 +ARM64_SYSREG_PMBSR_EL1 = 0xC4D3 +ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7 +ARM64_SYSREG_PMSCR_EL2 = 0xE4C8 +ARM64_SYSREG_PMSCR_EL12 = 0xECC8 +ARM64_SYSREG_PMSCR_EL1 = 0xC4C8 +ARM64_SYSREG_PMSICR_EL1 = 0xC4CA +ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB +ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC +ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD +ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE +ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF +ARM64_SYSREG_ERRSELR_EL1 = 0xC299 +ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1 +ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2 +ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3 +ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8 +ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9 +ARM64_SYSREG_DISR_EL1 = 0xC609 +ARM64_SYSREG_VDISR_EL2 = 0xE609 +ARM64_SYSREG_VSESR_EL2 = 0xE293 +ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108 +ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109 +ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A +ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B +ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110 +ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111 +ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112 +ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113 +ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118 +ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119 +ARM64_SYSREG_VSTCR_EL2 = 0xE132 +ARM64_SYSREG_VSTTBR_EL2 = 0xE130 +ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720 +ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722 +ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721 +ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728 +ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A +ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729 +ARM64_SYSREG_SDER32_EL2 = 0xE099 +ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5 +ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6 +ARM64_SYSREG_ERXTS_EL1 = 0xC2AF +ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA +ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB +ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4 +ARM64_SYSREG_MPAM0_EL1 = 0xC529 +ARM64_SYSREG_MPAM1_EL1 = 0xC528 +ARM64_SYSREG_MPAM2_EL2 = 0xE528 +ARM64_SYSREG_MPAM3_EL3 = 0xF528 +ARM64_SYSREG_MPAM1_EL12 = 0xED28 +ARM64_SYSREG_MPAMHCR_EL2 = 0xE520 +ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521 +ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530 +ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531 +ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532 +ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533 +ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534 +ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535 +ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536 +ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537 +ARM64_SYSREG_MPAMIDR_EL1 = 0xC524 +ARM64_SYSREG_AMCR_EL0 = 0xDE90 +ARM64_SYSREG_AMCFGR_EL0 = 0xDE91 +ARM64_SYSREG_AMCGCR_EL0 = 0xDE92 +ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93 +ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94 +ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95 +ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0 +ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1 +ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2 +ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3 +ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0 +ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1 +ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2 +ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3 +ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98 +ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99 +ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0 +ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1 +ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2 +ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3 +ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4 +ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5 +ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6 +ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7 +ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8 +ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9 +ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA +ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB +ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC +ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED +ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE +ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF +ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0 +ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1 +ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2 +ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3 +ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4 +ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5 +ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6 +ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7 +ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8 +ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9 +ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA +ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB +ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC +ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD +ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE +ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF +ARM64_SYSREG_TRFCR_EL1 = 0xC091 +ARM64_SYSREG_TRFCR_EL2 = 0xE091 +ARM64_SYSREG_TRFCR_EL12 = 0xE891 +ARM64_SYSREG_DIT = 0xDA15 +ARM64_SYSREG_VNCR_EL2 = 0xE110 +ARM64_SYSREG_ZCR_EL1 = 0xC090 +ARM64_SYSREG_ZCR_EL2 = 0xE090 +ARM64_SYSREG_ZCR_EL3 = 0xF090 +ARM64_SYSREG_ZCR_EL12 = 0xE890 +ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90 ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828 ARM64_SYSREG_OSLAR_EL1 = 0x8084 ARM64_SYSREG_PMSWINC_EL0 = 0xdce4 @@ -144,23 +789,25 @@ ARM64_PSTATE_INVALID = 0 ARM64_PSTATE_SPSEL = 0x05 ARM64_PSTATE_DAIFSET = 0x1e ARM64_PSTATE_DAIFCLR = 0x1f +ARM64_PSTATE_PAN = 0x4 +ARM64_PSTATE_UAO = 0x3 +ARM64_PSTATE_DIT = 0x1a ARM64_VAS_INVALID = 0 -ARM64_VAS_8B = 1 -ARM64_VAS_16B = 2 -ARM64_VAS_4H = 3 -ARM64_VAS_8H = 4 -ARM64_VAS_2S = 5 -ARM64_VAS_4S = 6 -ARM64_VAS_1D = 7 -ARM64_VAS_2D = 8 -ARM64_VAS_1Q = 9 - -ARM64_VESS_INVALID = 0 -ARM64_VESS_B = 1 -ARM64_VESS_H = 2 -ARM64_VESS_S = 3 -ARM64_VESS_D = 4 +ARM64_VAS_16B = 1 +ARM64_VAS_8B = 2 +ARM64_VAS_4B = 3 +ARM64_VAS_1B = 4 +ARM64_VAS_8H = 5 +ARM64_VAS_4H = 6 +ARM64_VAS_2H = 7 +ARM64_VAS_1H = 8 +ARM64_VAS_4S = 9 +ARM64_VAS_2S = 10 +ARM64_VAS_1S = 11 +ARM64_VAS_2D = 12 +ARM64_VAS_1D = 13 +ARM64_VAS_1Q = 14 ARM64_BARRIER_INVALID = 0 ARM64_BARRIER_OSHLD = 0x1 @@ -190,50 +837,98 @@ ARM64_OP_PREFETCH = 69 ARM64_OP_BARRIER = 70 ARM64_TLBI_INVALID = 0 -ARM64_TLBI_VMALLE1IS = 1 -ARM64_TLBI_VAE1IS = 2 -ARM64_TLBI_ASIDE1IS = 3 -ARM64_TLBI_VAAE1IS = 4 -ARM64_TLBI_VALE1IS = 5 -ARM64_TLBI_VAALE1IS = 6 -ARM64_TLBI_ALLE2IS = 7 -ARM64_TLBI_VAE2IS = 8 -ARM64_TLBI_ALLE1IS = 9 -ARM64_TLBI_VALE2IS = 10 -ARM64_TLBI_VMALLS12E1IS = 11 -ARM64_TLBI_ALLE3IS = 12 -ARM64_TLBI_VAE3IS = 13 +ARM64_TLBI_IPAS2E1IS = 1 +ARM64_TLBI_IPAS2LE1IS = 2 +ARM64_TLBI_VMALLE1IS = 3 +ARM64_TLBI_ALLE2IS = 4 +ARM64_TLBI_ALLE3IS = 5 +ARM64_TLBI_VAE1IS = 6 +ARM64_TLBI_VAE2IS = 7 +ARM64_TLBI_VAE3IS = 8 +ARM64_TLBI_ASIDE1IS = 9 +ARM64_TLBI_VAAE1IS = 10 +ARM64_TLBI_ALLE1IS = 11 +ARM64_TLBI_VALE1IS = 12 +ARM64_TLBI_VALE2IS = 13 ARM64_TLBI_VALE3IS = 14 -ARM64_TLBI_IPAS2E1IS = 15 -ARM64_TLBI_IPAS2LE1IS = 16 +ARM64_TLBI_VMALLS12E1IS = 15 +ARM64_TLBI_VAALE1IS = 16 ARM64_TLBI_IPAS2E1 = 17 ARM64_TLBI_IPAS2LE1 = 18 ARM64_TLBI_VMALLE1 = 19 -ARM64_TLBI_VAE1 = 20 -ARM64_TLBI_ASIDE1 = 21 -ARM64_TLBI_VAAE1 = 22 -ARM64_TLBI_VALE1 = 23 -ARM64_TLBI_VAALE1 = 24 -ARM64_TLBI_ALLE2 = 25 -ARM64_TLBI_VAE2 = 26 +ARM64_TLBI_ALLE2 = 20 +ARM64_TLBI_ALLE3 = 21 +ARM64_TLBI_VAE1 = 22 +ARM64_TLBI_VAE2 = 23 +ARM64_TLBI_VAE3 = 24 +ARM64_TLBI_ASIDE1 = 25 +ARM64_TLBI_VAAE1 = 26 ARM64_TLBI_ALLE1 = 27 -ARM64_TLBI_VALE2 = 28 -ARM64_TLBI_VMALLS12E1 = 29 -ARM64_TLBI_ALLE3 = 30 -ARM64_TLBI_VAE3 = 31 -ARM64_TLBI_VALE3 = 32 -ARM64_AT_S1E1R = 33 -ARM64_AT_S1E1W = 34 -ARM64_AT_S1E0R = 35 -ARM64_AT_S1E0W = 36 -ARM64_AT_S1E2R = 37 -ARM64_AT_S1E2W = 38 -ARM64_AT_S12E1R = 39 -ARM64_AT_S12E1W = 40 -ARM64_AT_S12E0R = 41 -ARM64_AT_S12E0W = 42 -ARM64_AT_S1E3R = 43 -ARM64_AT_S1E3W = 44 +ARM64_TLBI_VALE1 = 28 +ARM64_TLBI_VALE2 = 29 +ARM64_TLBI_VALE3 = 30 +ARM64_TLBI_VMALLS12E1 = 31 +ARM64_TLBI_VAALE1 = 32 +ARM64_TLBI_VMALLE1OS = 33 +ARM64_TLBI_VAE1OS = 34 +ARM64_TLBI_ASIDE1OS = 35 +ARM64_TLBI_VAAE1OS = 36 +ARM64_TLBI_VALE1OS = 37 +ARM64_TLBI_VAALE1OS = 38 +ARM64_TLBI_IPAS2E1OS = 39 +ARM64_TLBI_IPAS2LE1OS = 40 +ARM64_TLBI_VAE2OS = 41 +ARM64_TLBI_VALE2OS = 42 +ARM64_TLBI_VMALLS12E1OS = 43 +ARM64_TLBI_VAE3OS = 44 +ARM64_TLBI_VALE3OS = 45 +ARM64_TLBI_ALLE2OS = 46 +ARM64_TLBI_ALLE1OS = 47 +ARM64_TLBI_ALLE3OS = 48 +ARM64_TLBI_RVAE1 = 49 +ARM64_TLBI_RVAAE1 = 50 +ARM64_TLBI_RVALE1 = 51 +ARM64_TLBI_RVAALE1 = 52 +ARM64_TLBI_RVAE1IS = 53 +ARM64_TLBI_RVAAE1IS = 54 +ARM64_TLBI_RVALE1IS = 55 +ARM64_TLBI_RVAALE1IS = 56 +ARM64_TLBI_RVAE1OS = 57 +ARM64_TLBI_RVAAE1OS = 58 +ARM64_TLBI_RVALE1OS = 59 +ARM64_TLBI_RVAALE1OS = 60 +ARM64_TLBI_RIPAS2E1IS = 61 +ARM64_TLBI_RIPAS2LE1IS = 62 +ARM64_TLBI_RIPAS2E1 = 63 +ARM64_TLBI_RIPAS2LE1 = 64 +ARM64_TLBI_RIPAS2E1OS = 65 +ARM64_TLBI_RIPAS2LE1OS = 66 +ARM64_TLBI_RVAE2 = 67 +ARM64_TLBI_RVALE2 = 68 +ARM64_TLBI_RVAE2IS = 69 +ARM64_TLBI_RVALE2IS = 70 +ARM64_TLBI_RVAE2OS = 71 +ARM64_TLBI_RVALE2OS = 72 +ARM64_TLBI_RVAE3 = 73 +ARM64_TLBI_RVALE3 = 74 +ARM64_TLBI_RVAE3IS = 75 +ARM64_TLBI_RVALE3IS = 76 +ARM64_TLBI_RVAE3OS = 77 +ARM64_TLBI_RVALE3OS = 78 +ARM64_AT_S1E1R = 79 +ARM64_AT_S1E2R = 80 +ARM64_AT_S1E3R = 81 +ARM64_AT_S1E1W = 82 +ARM64_AT_S1E2W = 83 +ARM64_AT_S1E3W = 84 +ARM64_AT_S1E0R = 85 +ARM64_AT_S1E0W = 86 +ARM64_AT_S12E1R = 87 +ARM64_AT_S12E1W = 88 +ARM64_AT_S12E0R = 89 +ARM64_AT_S12E0W = 90 +ARM64_AT_S1E1RP = 91 +ARM64_AT_S1E1WP = 92 ARM64_DC_INVALID = 0 ARM64_DC_ZVA = 1 @@ -244,6 +939,7 @@ ARM64_DC_CSW = 5 ARM64_DC_CVAU = 6 ARM64_DC_CIVAC = 7 ARM64_DC_CISW = 8 +ARM64_DC_CVAP = 9 ARM64_IC_INVALID = 0 ARM64_IC_IALLUIS = 1 @@ -271,726 +967,1271 @@ ARM64_PRFM_PSTL3KEEP = 0x14+1 ARM64_PRFM_PSTL3STRM = 0x15+1 ARM64_REG_INVALID = 0 -ARM64_REG_X29 = 1 -ARM64_REG_X30 = 2 -ARM64_REG_NZCV = 3 -ARM64_REG_SP = 4 -ARM64_REG_WSP = 5 -ARM64_REG_WZR = 6 -ARM64_REG_XZR = 7 -ARM64_REG_B0 = 8 -ARM64_REG_B1 = 9 -ARM64_REG_B2 = 10 -ARM64_REG_B3 = 11 -ARM64_REG_B4 = 12 -ARM64_REG_B5 = 13 -ARM64_REG_B6 = 14 -ARM64_REG_B7 = 15 -ARM64_REG_B8 = 16 -ARM64_REG_B9 = 17 -ARM64_REG_B10 = 18 -ARM64_REG_B11 = 19 -ARM64_REG_B12 = 20 -ARM64_REG_B13 = 21 -ARM64_REG_B14 = 22 -ARM64_REG_B15 = 23 -ARM64_REG_B16 = 24 -ARM64_REG_B17 = 25 -ARM64_REG_B18 = 26 -ARM64_REG_B19 = 27 -ARM64_REG_B20 = 28 -ARM64_REG_B21 = 29 -ARM64_REG_B22 = 30 -ARM64_REG_B23 = 31 -ARM64_REG_B24 = 32 -ARM64_REG_B25 = 33 -ARM64_REG_B26 = 34 -ARM64_REG_B27 = 35 -ARM64_REG_B28 = 36 -ARM64_REG_B29 = 37 -ARM64_REG_B30 = 38 -ARM64_REG_B31 = 39 -ARM64_REG_D0 = 40 -ARM64_REG_D1 = 41 -ARM64_REG_D2 = 42 -ARM64_REG_D3 = 43 -ARM64_REG_D4 = 44 -ARM64_REG_D5 = 45 -ARM64_REG_D6 = 46 -ARM64_REG_D7 = 47 -ARM64_REG_D8 = 48 -ARM64_REG_D9 = 49 -ARM64_REG_D10 = 50 -ARM64_REG_D11 = 51 -ARM64_REG_D12 = 52 -ARM64_REG_D13 = 53 -ARM64_REG_D14 = 54 -ARM64_REG_D15 = 55 -ARM64_REG_D16 = 56 -ARM64_REG_D17 = 57 -ARM64_REG_D18 = 58 -ARM64_REG_D19 = 59 -ARM64_REG_D20 = 60 -ARM64_REG_D21 = 61 -ARM64_REG_D22 = 62 -ARM64_REG_D23 = 63 -ARM64_REG_D24 = 64 -ARM64_REG_D25 = 65 -ARM64_REG_D26 = 66 -ARM64_REG_D27 = 67 -ARM64_REG_D28 = 68 -ARM64_REG_D29 = 69 -ARM64_REG_D30 = 70 -ARM64_REG_D31 = 71 -ARM64_REG_H0 = 72 -ARM64_REG_H1 = 73 -ARM64_REG_H2 = 74 -ARM64_REG_H3 = 75 -ARM64_REG_H4 = 76 -ARM64_REG_H5 = 77 -ARM64_REG_H6 = 78 -ARM64_REG_H7 = 79 -ARM64_REG_H8 = 80 -ARM64_REG_H9 = 81 -ARM64_REG_H10 = 82 -ARM64_REG_H11 = 83 -ARM64_REG_H12 = 84 -ARM64_REG_H13 = 85 -ARM64_REG_H14 = 86 -ARM64_REG_H15 = 87 -ARM64_REG_H16 = 88 -ARM64_REG_H17 = 89 -ARM64_REG_H18 = 90 -ARM64_REG_H19 = 91 -ARM64_REG_H20 = 92 -ARM64_REG_H21 = 93 -ARM64_REG_H22 = 94 -ARM64_REG_H23 = 95 -ARM64_REG_H24 = 96 -ARM64_REG_H25 = 97 -ARM64_REG_H26 = 98 -ARM64_REG_H27 = 99 -ARM64_REG_H28 = 100 -ARM64_REG_H29 = 101 -ARM64_REG_H30 = 102 -ARM64_REG_H31 = 103 -ARM64_REG_Q0 = 104 -ARM64_REG_Q1 = 105 -ARM64_REG_Q2 = 106 -ARM64_REG_Q3 = 107 -ARM64_REG_Q4 = 108 -ARM64_REG_Q5 = 109 -ARM64_REG_Q6 = 110 -ARM64_REG_Q7 = 111 -ARM64_REG_Q8 = 112 -ARM64_REG_Q9 = 113 -ARM64_REG_Q10 = 114 -ARM64_REG_Q11 = 115 -ARM64_REG_Q12 = 116 -ARM64_REG_Q13 = 117 -ARM64_REG_Q14 = 118 -ARM64_REG_Q15 = 119 -ARM64_REG_Q16 = 120 -ARM64_REG_Q17 = 121 -ARM64_REG_Q18 = 122 -ARM64_REG_Q19 = 123 -ARM64_REG_Q20 = 124 -ARM64_REG_Q21 = 125 -ARM64_REG_Q22 = 126 -ARM64_REG_Q23 = 127 -ARM64_REG_Q24 = 128 -ARM64_REG_Q25 = 129 -ARM64_REG_Q26 = 130 -ARM64_REG_Q27 = 131 -ARM64_REG_Q28 = 132 -ARM64_REG_Q29 = 133 -ARM64_REG_Q30 = 134 -ARM64_REG_Q31 = 135 -ARM64_REG_S0 = 136 -ARM64_REG_S1 = 137 -ARM64_REG_S2 = 138 -ARM64_REG_S3 = 139 -ARM64_REG_S4 = 140 -ARM64_REG_S5 = 141 -ARM64_REG_S6 = 142 -ARM64_REG_S7 = 143 -ARM64_REG_S8 = 144 -ARM64_REG_S9 = 145 -ARM64_REG_S10 = 146 -ARM64_REG_S11 = 147 -ARM64_REG_S12 = 148 -ARM64_REG_S13 = 149 -ARM64_REG_S14 = 150 -ARM64_REG_S15 = 151 -ARM64_REG_S16 = 152 -ARM64_REG_S17 = 153 -ARM64_REG_S18 = 154 -ARM64_REG_S19 = 155 -ARM64_REG_S20 = 156 -ARM64_REG_S21 = 157 -ARM64_REG_S22 = 158 -ARM64_REG_S23 = 159 -ARM64_REG_S24 = 160 -ARM64_REG_S25 = 161 -ARM64_REG_S26 = 162 -ARM64_REG_S27 = 163 -ARM64_REG_S28 = 164 -ARM64_REG_S29 = 165 -ARM64_REG_S30 = 166 -ARM64_REG_S31 = 167 -ARM64_REG_W0 = 168 -ARM64_REG_W1 = 169 -ARM64_REG_W2 = 170 -ARM64_REG_W3 = 171 -ARM64_REG_W4 = 172 -ARM64_REG_W5 = 173 -ARM64_REG_W6 = 174 -ARM64_REG_W7 = 175 -ARM64_REG_W8 = 176 -ARM64_REG_W9 = 177 -ARM64_REG_W10 = 178 -ARM64_REG_W11 = 179 -ARM64_REG_W12 = 180 -ARM64_REG_W13 = 181 -ARM64_REG_W14 = 182 -ARM64_REG_W15 = 183 -ARM64_REG_W16 = 184 -ARM64_REG_W17 = 185 -ARM64_REG_W18 = 186 -ARM64_REG_W19 = 187 -ARM64_REG_W20 = 188 -ARM64_REG_W21 = 189 -ARM64_REG_W22 = 190 -ARM64_REG_W23 = 191 -ARM64_REG_W24 = 192 -ARM64_REG_W25 = 193 -ARM64_REG_W26 = 194 -ARM64_REG_W27 = 195 -ARM64_REG_W28 = 196 -ARM64_REG_W29 = 197 -ARM64_REG_W30 = 198 -ARM64_REG_X0 = 199 -ARM64_REG_X1 = 200 -ARM64_REG_X2 = 201 -ARM64_REG_X3 = 202 -ARM64_REG_X4 = 203 -ARM64_REG_X5 = 204 -ARM64_REG_X6 = 205 -ARM64_REG_X7 = 206 -ARM64_REG_X8 = 207 -ARM64_REG_X9 = 208 -ARM64_REG_X10 = 209 -ARM64_REG_X11 = 210 -ARM64_REG_X12 = 211 -ARM64_REG_X13 = 212 -ARM64_REG_X14 = 213 -ARM64_REG_X15 = 214 -ARM64_REG_X16 = 215 -ARM64_REG_X17 = 216 -ARM64_REG_X18 = 217 -ARM64_REG_X19 = 218 -ARM64_REG_X20 = 219 -ARM64_REG_X21 = 220 -ARM64_REG_X22 = 221 -ARM64_REG_X23 = 222 -ARM64_REG_X24 = 223 -ARM64_REG_X25 = 224 -ARM64_REG_X26 = 225 -ARM64_REG_X27 = 226 -ARM64_REG_X28 = 227 -ARM64_REG_V0 = 228 -ARM64_REG_V1 = 229 -ARM64_REG_V2 = 230 -ARM64_REG_V3 = 231 -ARM64_REG_V4 = 232 -ARM64_REG_V5 = 233 -ARM64_REG_V6 = 234 -ARM64_REG_V7 = 235 -ARM64_REG_V8 = 236 -ARM64_REG_V9 = 237 -ARM64_REG_V10 = 238 -ARM64_REG_V11 = 239 -ARM64_REG_V12 = 240 -ARM64_REG_V13 = 241 -ARM64_REG_V14 = 242 -ARM64_REG_V15 = 243 -ARM64_REG_V16 = 244 -ARM64_REG_V17 = 245 -ARM64_REG_V18 = 246 -ARM64_REG_V19 = 247 -ARM64_REG_V20 = 248 -ARM64_REG_V21 = 249 -ARM64_REG_V22 = 250 -ARM64_REG_V23 = 251 -ARM64_REG_V24 = 252 -ARM64_REG_V25 = 253 -ARM64_REG_V26 = 254 -ARM64_REG_V27 = 255 -ARM64_REG_V28 = 256 -ARM64_REG_V29 = 257 -ARM64_REG_V30 = 258 -ARM64_REG_V31 = 259 -ARM64_REG_ENDING = 260 +ARM64_REG_FFR = 1 +ARM64_REG_FP = 2 +ARM64_REG_LR = 3 +ARM64_REG_NZCV = 4 +ARM64_REG_SP = 5 +ARM64_REG_WSP = 6 +ARM64_REG_WZR = 7 +ARM64_REG_XZR = 8 +ARM64_REG_B0 = 9 +ARM64_REG_B1 = 10 +ARM64_REG_B2 = 11 +ARM64_REG_B3 = 12 +ARM64_REG_B4 = 13 +ARM64_REG_B5 = 14 +ARM64_REG_B6 = 15 +ARM64_REG_B7 = 16 +ARM64_REG_B8 = 17 +ARM64_REG_B9 = 18 +ARM64_REG_B10 = 19 +ARM64_REG_B11 = 20 +ARM64_REG_B12 = 21 +ARM64_REG_B13 = 22 +ARM64_REG_B14 = 23 +ARM64_REG_B15 = 24 +ARM64_REG_B16 = 25 +ARM64_REG_B17 = 26 +ARM64_REG_B18 = 27 +ARM64_REG_B19 = 28 +ARM64_REG_B20 = 29 +ARM64_REG_B21 = 30 +ARM64_REG_B22 = 31 +ARM64_REG_B23 = 32 +ARM64_REG_B24 = 33 +ARM64_REG_B25 = 34 +ARM64_REG_B26 = 35 +ARM64_REG_B27 = 36 +ARM64_REG_B28 = 37 +ARM64_REG_B29 = 38 +ARM64_REG_B30 = 39 +ARM64_REG_B31 = 40 +ARM64_REG_D0 = 41 +ARM64_REG_D1 = 42 +ARM64_REG_D2 = 43 +ARM64_REG_D3 = 44 +ARM64_REG_D4 = 45 +ARM64_REG_D5 = 46 +ARM64_REG_D6 = 47 +ARM64_REG_D7 = 48 +ARM64_REG_D8 = 49 +ARM64_REG_D9 = 50 +ARM64_REG_D10 = 51 +ARM64_REG_D11 = 52 +ARM64_REG_D12 = 53 +ARM64_REG_D13 = 54 +ARM64_REG_D14 = 55 +ARM64_REG_D15 = 56 +ARM64_REG_D16 = 57 +ARM64_REG_D17 = 58 +ARM64_REG_D18 = 59 +ARM64_REG_D19 = 60 +ARM64_REG_D20 = 61 +ARM64_REG_D21 = 62 +ARM64_REG_D22 = 63 +ARM64_REG_D23 = 64 +ARM64_REG_D24 = 65 +ARM64_REG_D25 = 66 +ARM64_REG_D26 = 67 +ARM64_REG_D27 = 68 +ARM64_REG_D28 = 69 +ARM64_REG_D29 = 70 +ARM64_REG_D30 = 71 +ARM64_REG_D31 = 72 +ARM64_REG_H0 = 73 +ARM64_REG_H1 = 74 +ARM64_REG_H2 = 75 +ARM64_REG_H3 = 76 +ARM64_REG_H4 = 77 +ARM64_REG_H5 = 78 +ARM64_REG_H6 = 79 +ARM64_REG_H7 = 80 +ARM64_REG_H8 = 81 +ARM64_REG_H9 = 82 +ARM64_REG_H10 = 83 +ARM64_REG_H11 = 84 +ARM64_REG_H12 = 85 +ARM64_REG_H13 = 86 +ARM64_REG_H14 = 87 +ARM64_REG_H15 = 88 +ARM64_REG_H16 = 89 +ARM64_REG_H17 = 90 +ARM64_REG_H18 = 91 +ARM64_REG_H19 = 92 +ARM64_REG_H20 = 93 +ARM64_REG_H21 = 94 +ARM64_REG_H22 = 95 +ARM64_REG_H23 = 96 +ARM64_REG_H24 = 97 +ARM64_REG_H25 = 98 +ARM64_REG_H26 = 99 +ARM64_REG_H27 = 100 +ARM64_REG_H28 = 101 +ARM64_REG_H29 = 102 +ARM64_REG_H30 = 103 +ARM64_REG_H31 = 104 +ARM64_REG_P0 = 105 +ARM64_REG_P1 = 106 +ARM64_REG_P2 = 107 +ARM64_REG_P3 = 108 +ARM64_REG_P4 = 109 +ARM64_REG_P5 = 110 +ARM64_REG_P6 = 111 +ARM64_REG_P7 = 112 +ARM64_REG_P8 = 113 +ARM64_REG_P9 = 114 +ARM64_REG_P10 = 115 +ARM64_REG_P11 = 116 +ARM64_REG_P12 = 117 +ARM64_REG_P13 = 118 +ARM64_REG_P14 = 119 +ARM64_REG_P15 = 120 +ARM64_REG_Q0 = 121 +ARM64_REG_Q1 = 122 +ARM64_REG_Q2 = 123 +ARM64_REG_Q3 = 124 +ARM64_REG_Q4 = 125 +ARM64_REG_Q5 = 126 +ARM64_REG_Q6 = 127 +ARM64_REG_Q7 = 128 +ARM64_REG_Q8 = 129 +ARM64_REG_Q9 = 130 +ARM64_REG_Q10 = 131 +ARM64_REG_Q11 = 132 +ARM64_REG_Q12 = 133 +ARM64_REG_Q13 = 134 +ARM64_REG_Q14 = 135 +ARM64_REG_Q15 = 136 +ARM64_REG_Q16 = 137 +ARM64_REG_Q17 = 138 +ARM64_REG_Q18 = 139 +ARM64_REG_Q19 = 140 +ARM64_REG_Q20 = 141 +ARM64_REG_Q21 = 142 +ARM64_REG_Q22 = 143 +ARM64_REG_Q23 = 144 +ARM64_REG_Q24 = 145 +ARM64_REG_Q25 = 146 +ARM64_REG_Q26 = 147 +ARM64_REG_Q27 = 148 +ARM64_REG_Q28 = 149 +ARM64_REG_Q29 = 150 +ARM64_REG_Q30 = 151 +ARM64_REG_Q31 = 152 +ARM64_REG_S0 = 153 +ARM64_REG_S1 = 154 +ARM64_REG_S2 = 155 +ARM64_REG_S3 = 156 +ARM64_REG_S4 = 157 +ARM64_REG_S5 = 158 +ARM64_REG_S6 = 159 +ARM64_REG_S7 = 160 +ARM64_REG_S8 = 161 +ARM64_REG_S9 = 162 +ARM64_REG_S10 = 163 +ARM64_REG_S11 = 164 +ARM64_REG_S12 = 165 +ARM64_REG_S13 = 166 +ARM64_REG_S14 = 167 +ARM64_REG_S15 = 168 +ARM64_REG_S16 = 169 +ARM64_REG_S17 = 170 +ARM64_REG_S18 = 171 +ARM64_REG_S19 = 172 +ARM64_REG_S20 = 173 +ARM64_REG_S21 = 174 +ARM64_REG_S22 = 175 +ARM64_REG_S23 = 176 +ARM64_REG_S24 = 177 +ARM64_REG_S25 = 178 +ARM64_REG_S26 = 179 +ARM64_REG_S27 = 180 +ARM64_REG_S28 = 181 +ARM64_REG_S29 = 182 +ARM64_REG_S30 = 183 +ARM64_REG_S31 = 184 +ARM64_REG_W0 = 185 +ARM64_REG_W1 = 186 +ARM64_REG_W2 = 187 +ARM64_REG_W3 = 188 +ARM64_REG_W4 = 189 +ARM64_REG_W5 = 190 +ARM64_REG_W6 = 191 +ARM64_REG_W7 = 192 +ARM64_REG_W8 = 193 +ARM64_REG_W9 = 194 +ARM64_REG_W10 = 195 +ARM64_REG_W11 = 196 +ARM64_REG_W12 = 197 +ARM64_REG_W13 = 198 +ARM64_REG_W14 = 199 +ARM64_REG_W15 = 200 +ARM64_REG_W16 = 201 +ARM64_REG_W17 = 202 +ARM64_REG_W18 = 203 +ARM64_REG_W19 = 204 +ARM64_REG_W20 = 205 +ARM64_REG_W21 = 206 +ARM64_REG_W22 = 207 +ARM64_REG_W23 = 208 +ARM64_REG_W24 = 209 +ARM64_REG_W25 = 210 +ARM64_REG_W26 = 211 +ARM64_REG_W27 = 212 +ARM64_REG_W28 = 213 +ARM64_REG_W29 = 214 +ARM64_REG_W30 = 215 +ARM64_REG_X0 = 216 +ARM64_REG_X1 = 217 +ARM64_REG_X2 = 218 +ARM64_REG_X3 = 219 +ARM64_REG_X4 = 220 +ARM64_REG_X5 = 221 +ARM64_REG_X6 = 222 +ARM64_REG_X7 = 223 +ARM64_REG_X8 = 224 +ARM64_REG_X9 = 225 +ARM64_REG_X10 = 226 +ARM64_REG_X11 = 227 +ARM64_REG_X12 = 228 +ARM64_REG_X13 = 229 +ARM64_REG_X14 = 230 +ARM64_REG_X15 = 231 +ARM64_REG_X16 = 232 +ARM64_REG_X17 = 233 +ARM64_REG_X18 = 234 +ARM64_REG_X19 = 235 +ARM64_REG_X20 = 236 +ARM64_REG_X21 = 237 +ARM64_REG_X22 = 238 +ARM64_REG_X23 = 239 +ARM64_REG_X24 = 240 +ARM64_REG_X25 = 241 +ARM64_REG_X26 = 242 +ARM64_REG_X27 = 243 +ARM64_REG_X28 = 244 +ARM64_REG_Z0 = 245 +ARM64_REG_Z1 = 246 +ARM64_REG_Z2 = 247 +ARM64_REG_Z3 = 248 +ARM64_REG_Z4 = 249 +ARM64_REG_Z5 = 250 +ARM64_REG_Z6 = 251 +ARM64_REG_Z7 = 252 +ARM64_REG_Z8 = 253 +ARM64_REG_Z9 = 254 +ARM64_REG_Z10 = 255 +ARM64_REG_Z11 = 256 +ARM64_REG_Z12 = 257 +ARM64_REG_Z13 = 258 +ARM64_REG_Z14 = 259 +ARM64_REG_Z15 = 260 +ARM64_REG_Z16 = 261 +ARM64_REG_Z17 = 262 +ARM64_REG_Z18 = 263 +ARM64_REG_Z19 = 264 +ARM64_REG_Z20 = 265 +ARM64_REG_Z21 = 266 +ARM64_REG_Z22 = 267 +ARM64_REG_Z23 = 268 +ARM64_REG_Z24 = 269 +ARM64_REG_Z25 = 270 +ARM64_REG_Z26 = 271 +ARM64_REG_Z27 = 272 +ARM64_REG_Z28 = 273 +ARM64_REG_Z29 = 274 +ARM64_REG_Z30 = 275 +ARM64_REG_Z31 = 276 +ARM64_REG_V0 = 277 +ARM64_REG_V1 = 278 +ARM64_REG_V2 = 279 +ARM64_REG_V3 = 280 +ARM64_REG_V4 = 281 +ARM64_REG_V5 = 282 +ARM64_REG_V6 = 283 +ARM64_REG_V7 = 284 +ARM64_REG_V8 = 285 +ARM64_REG_V9 = 286 +ARM64_REG_V10 = 287 +ARM64_REG_V11 = 288 +ARM64_REG_V12 = 289 +ARM64_REG_V13 = 290 +ARM64_REG_V14 = 291 +ARM64_REG_V15 = 292 +ARM64_REG_V16 = 293 +ARM64_REG_V17 = 294 +ARM64_REG_V18 = 295 +ARM64_REG_V19 = 296 +ARM64_REG_V20 = 297 +ARM64_REG_V21 = 298 +ARM64_REG_V22 = 299 +ARM64_REG_V23 = 300 +ARM64_REG_V24 = 301 +ARM64_REG_V25 = 302 +ARM64_REG_V26 = 303 +ARM64_REG_V27 = 304 +ARM64_REG_V28 = 305 +ARM64_REG_V29 = 306 +ARM64_REG_V30 = 307 +ARM64_REG_V31 = 308 +ARM64_REG_ENDING = 309 ARM64_REG_IP0 = ARM64_REG_X16 ARM64_REG_IP1 = ARM64_REG_X17 -ARM64_REG_FP = ARM64_REG_X29 -ARM64_REG_LR = ARM64_REG_X30 +ARM64_REG_X29 = ARM64_REG_FP +ARM64_REG_X30 = ARM64_REG_LR ARM64_INS_INVALID = 0 ARM64_INS_ABS = 1 ARM64_INS_ADC = 2 -ARM64_INS_ADDHN = 3 -ARM64_INS_ADDHN2 = 4 -ARM64_INS_ADDP = 5 -ARM64_INS_ADD = 6 -ARM64_INS_ADDV = 7 -ARM64_INS_ADR = 8 -ARM64_INS_ADRP = 9 -ARM64_INS_AESD = 10 -ARM64_INS_AESE = 11 -ARM64_INS_AESIMC = 12 -ARM64_INS_AESMC = 13 -ARM64_INS_AND = 14 -ARM64_INS_ASR = 15 -ARM64_INS_B = 16 -ARM64_INS_BFM = 17 -ARM64_INS_BIC = 18 -ARM64_INS_BIF = 19 -ARM64_INS_BIT = 20 -ARM64_INS_BL = 21 -ARM64_INS_BLR = 22 -ARM64_INS_BR = 23 -ARM64_INS_BRK = 24 -ARM64_INS_BSL = 25 -ARM64_INS_CBNZ = 26 -ARM64_INS_CBZ = 27 -ARM64_INS_CCMN = 28 -ARM64_INS_CCMP = 29 -ARM64_INS_CLREX = 30 -ARM64_INS_CLS = 31 -ARM64_INS_CLZ = 32 -ARM64_INS_CMEQ = 33 -ARM64_INS_CMGE = 34 -ARM64_INS_CMGT = 35 -ARM64_INS_CMHI = 36 -ARM64_INS_CMHS = 37 -ARM64_INS_CMLE = 38 -ARM64_INS_CMLT = 39 -ARM64_INS_CMTST = 40 -ARM64_INS_CNT = 41 -ARM64_INS_MOV = 42 -ARM64_INS_CRC32B = 43 -ARM64_INS_CRC32CB = 44 -ARM64_INS_CRC32CH = 45 -ARM64_INS_CRC32CW = 46 -ARM64_INS_CRC32CX = 47 -ARM64_INS_CRC32H = 48 -ARM64_INS_CRC32W = 49 -ARM64_INS_CRC32X = 50 -ARM64_INS_CSEL = 51 -ARM64_INS_CSINC = 52 -ARM64_INS_CSINV = 53 -ARM64_INS_CSNEG = 54 -ARM64_INS_DCPS1 = 55 -ARM64_INS_DCPS2 = 56 -ARM64_INS_DCPS3 = 57 -ARM64_INS_DMB = 58 -ARM64_INS_DRPS = 59 -ARM64_INS_DSB = 60 -ARM64_INS_DUP = 61 -ARM64_INS_EON = 62 -ARM64_INS_EOR = 63 -ARM64_INS_ERET = 64 -ARM64_INS_EXTR = 65 -ARM64_INS_EXT = 66 -ARM64_INS_FABD = 67 -ARM64_INS_FABS = 68 -ARM64_INS_FACGE = 69 -ARM64_INS_FACGT = 70 -ARM64_INS_FADD = 71 -ARM64_INS_FADDP = 72 -ARM64_INS_FCCMP = 73 -ARM64_INS_FCCMPE = 74 -ARM64_INS_FCMEQ = 75 -ARM64_INS_FCMGE = 76 -ARM64_INS_FCMGT = 77 -ARM64_INS_FCMLE = 78 -ARM64_INS_FCMLT = 79 -ARM64_INS_FCMP = 80 -ARM64_INS_FCMPE = 81 -ARM64_INS_FCSEL = 82 -ARM64_INS_FCVTAS = 83 -ARM64_INS_FCVTAU = 84 -ARM64_INS_FCVT = 85 -ARM64_INS_FCVTL = 86 -ARM64_INS_FCVTL2 = 87 -ARM64_INS_FCVTMS = 88 -ARM64_INS_FCVTMU = 89 -ARM64_INS_FCVTNS = 90 -ARM64_INS_FCVTNU = 91 -ARM64_INS_FCVTN = 92 -ARM64_INS_FCVTN2 = 93 -ARM64_INS_FCVTPS = 94 -ARM64_INS_FCVTPU = 95 -ARM64_INS_FCVTXN = 96 -ARM64_INS_FCVTXN2 = 97 -ARM64_INS_FCVTZS = 98 -ARM64_INS_FCVTZU = 99 -ARM64_INS_FDIV = 100 -ARM64_INS_FMADD = 101 -ARM64_INS_FMAX = 102 -ARM64_INS_FMAXNM = 103 -ARM64_INS_FMAXNMP = 104 -ARM64_INS_FMAXNMV = 105 -ARM64_INS_FMAXP = 106 -ARM64_INS_FMAXV = 107 -ARM64_INS_FMIN = 108 -ARM64_INS_FMINNM = 109 -ARM64_INS_FMINNMP = 110 -ARM64_INS_FMINNMV = 111 -ARM64_INS_FMINP = 112 -ARM64_INS_FMINV = 113 -ARM64_INS_FMLA = 114 -ARM64_INS_FMLS = 115 -ARM64_INS_FMOV = 116 -ARM64_INS_FMSUB = 117 -ARM64_INS_FMUL = 118 -ARM64_INS_FMULX = 119 -ARM64_INS_FNEG = 120 -ARM64_INS_FNMADD = 121 -ARM64_INS_FNMSUB = 122 -ARM64_INS_FNMUL = 123 -ARM64_INS_FRECPE = 124 -ARM64_INS_FRECPS = 125 -ARM64_INS_FRECPX = 126 -ARM64_INS_FRINTA = 127 -ARM64_INS_FRINTI = 128 -ARM64_INS_FRINTM = 129 -ARM64_INS_FRINTN = 130 -ARM64_INS_FRINTP = 131 -ARM64_INS_FRINTX = 132 -ARM64_INS_FRINTZ = 133 -ARM64_INS_FRSQRTE = 134 -ARM64_INS_FRSQRTS = 135 -ARM64_INS_FSQRT = 136 -ARM64_INS_FSUB = 137 -ARM64_INS_HINT = 138 -ARM64_INS_HLT = 139 -ARM64_INS_HVC = 140 -ARM64_INS_INS = 141 -ARM64_INS_ISB = 142 -ARM64_INS_LD1 = 143 -ARM64_INS_LD1R = 144 -ARM64_INS_LD2R = 145 -ARM64_INS_LD2 = 146 -ARM64_INS_LD3R = 147 -ARM64_INS_LD3 = 148 -ARM64_INS_LD4 = 149 -ARM64_INS_LD4R = 150 -ARM64_INS_LDARB = 151 -ARM64_INS_LDARH = 152 -ARM64_INS_LDAR = 153 -ARM64_INS_LDAXP = 154 -ARM64_INS_LDAXRB = 155 -ARM64_INS_LDAXRH = 156 -ARM64_INS_LDAXR = 157 -ARM64_INS_LDNP = 158 -ARM64_INS_LDP = 159 -ARM64_INS_LDPSW = 160 -ARM64_INS_LDRB = 161 -ARM64_INS_LDR = 162 -ARM64_INS_LDRH = 163 -ARM64_INS_LDRSB = 164 -ARM64_INS_LDRSH = 165 -ARM64_INS_LDRSW = 166 -ARM64_INS_LDTRB = 167 -ARM64_INS_LDTRH = 168 -ARM64_INS_LDTRSB = 169 -ARM64_INS_LDTRSH = 170 -ARM64_INS_LDTRSW = 171 -ARM64_INS_LDTR = 172 -ARM64_INS_LDURB = 173 -ARM64_INS_LDUR = 174 -ARM64_INS_LDURH = 175 -ARM64_INS_LDURSB = 176 -ARM64_INS_LDURSH = 177 -ARM64_INS_LDURSW = 178 -ARM64_INS_LDXP = 179 -ARM64_INS_LDXRB = 180 -ARM64_INS_LDXRH = 181 -ARM64_INS_LDXR = 182 -ARM64_INS_LSL = 183 -ARM64_INS_LSR = 184 -ARM64_INS_MADD = 185 -ARM64_INS_MLA = 186 -ARM64_INS_MLS = 187 -ARM64_INS_MOVI = 188 -ARM64_INS_MOVK = 189 -ARM64_INS_MOVN = 190 -ARM64_INS_MOVZ = 191 -ARM64_INS_MRS = 192 -ARM64_INS_MSR = 193 -ARM64_INS_MSUB = 194 -ARM64_INS_MUL = 195 -ARM64_INS_MVNI = 196 -ARM64_INS_NEG = 197 -ARM64_INS_NOT = 198 -ARM64_INS_ORN = 199 -ARM64_INS_ORR = 200 -ARM64_INS_PMULL2 = 201 -ARM64_INS_PMULL = 202 -ARM64_INS_PMUL = 203 -ARM64_INS_PRFM = 204 -ARM64_INS_PRFUM = 205 -ARM64_INS_RADDHN = 206 -ARM64_INS_RADDHN2 = 207 -ARM64_INS_RBIT = 208 -ARM64_INS_RET = 209 -ARM64_INS_REV16 = 210 -ARM64_INS_REV32 = 211 -ARM64_INS_REV64 = 212 -ARM64_INS_REV = 213 -ARM64_INS_ROR = 214 -ARM64_INS_RSHRN2 = 215 -ARM64_INS_RSHRN = 216 -ARM64_INS_RSUBHN = 217 -ARM64_INS_RSUBHN2 = 218 -ARM64_INS_SABAL2 = 219 -ARM64_INS_SABAL = 220 -ARM64_INS_SABA = 221 -ARM64_INS_SABDL2 = 222 -ARM64_INS_SABDL = 223 -ARM64_INS_SABD = 224 -ARM64_INS_SADALP = 225 -ARM64_INS_SADDLP = 226 -ARM64_INS_SADDLV = 227 -ARM64_INS_SADDL2 = 228 -ARM64_INS_SADDL = 229 -ARM64_INS_SADDW2 = 230 -ARM64_INS_SADDW = 231 -ARM64_INS_SBC = 232 -ARM64_INS_SBFM = 233 -ARM64_INS_SCVTF = 234 -ARM64_INS_SDIV = 235 -ARM64_INS_SHA1C = 236 -ARM64_INS_SHA1H = 237 -ARM64_INS_SHA1M = 238 -ARM64_INS_SHA1P = 239 -ARM64_INS_SHA1SU0 = 240 -ARM64_INS_SHA1SU1 = 241 -ARM64_INS_SHA256H2 = 242 -ARM64_INS_SHA256H = 243 -ARM64_INS_SHA256SU0 = 244 -ARM64_INS_SHA256SU1 = 245 -ARM64_INS_SHADD = 246 -ARM64_INS_SHLL2 = 247 -ARM64_INS_SHLL = 248 -ARM64_INS_SHL = 249 -ARM64_INS_SHRN2 = 250 -ARM64_INS_SHRN = 251 -ARM64_INS_SHSUB = 252 -ARM64_INS_SLI = 253 -ARM64_INS_SMADDL = 254 -ARM64_INS_SMAXP = 255 -ARM64_INS_SMAXV = 256 -ARM64_INS_SMAX = 257 -ARM64_INS_SMC = 258 -ARM64_INS_SMINP = 259 -ARM64_INS_SMINV = 260 -ARM64_INS_SMIN = 261 -ARM64_INS_SMLAL2 = 262 -ARM64_INS_SMLAL = 263 -ARM64_INS_SMLSL2 = 264 -ARM64_INS_SMLSL = 265 -ARM64_INS_SMOV = 266 -ARM64_INS_SMSUBL = 267 -ARM64_INS_SMULH = 268 -ARM64_INS_SMULL2 = 269 -ARM64_INS_SMULL = 270 -ARM64_INS_SQABS = 271 -ARM64_INS_SQADD = 272 -ARM64_INS_SQDMLAL = 273 -ARM64_INS_SQDMLAL2 = 274 -ARM64_INS_SQDMLSL = 275 -ARM64_INS_SQDMLSL2 = 276 -ARM64_INS_SQDMULH = 277 -ARM64_INS_SQDMULL = 278 -ARM64_INS_SQDMULL2 = 279 -ARM64_INS_SQNEG = 280 -ARM64_INS_SQRDMULH = 281 -ARM64_INS_SQRSHL = 282 -ARM64_INS_SQRSHRN = 283 -ARM64_INS_SQRSHRN2 = 284 -ARM64_INS_SQRSHRUN = 285 -ARM64_INS_SQRSHRUN2 = 286 -ARM64_INS_SQSHLU = 287 -ARM64_INS_SQSHL = 288 -ARM64_INS_SQSHRN = 289 -ARM64_INS_SQSHRN2 = 290 -ARM64_INS_SQSHRUN = 291 -ARM64_INS_SQSHRUN2 = 292 -ARM64_INS_SQSUB = 293 -ARM64_INS_SQXTN2 = 294 -ARM64_INS_SQXTN = 295 -ARM64_INS_SQXTUN2 = 296 -ARM64_INS_SQXTUN = 297 -ARM64_INS_SRHADD = 298 -ARM64_INS_SRI = 299 -ARM64_INS_SRSHL = 300 -ARM64_INS_SRSHR = 301 -ARM64_INS_SRSRA = 302 -ARM64_INS_SSHLL2 = 303 -ARM64_INS_SSHLL = 304 -ARM64_INS_SSHL = 305 -ARM64_INS_SSHR = 306 -ARM64_INS_SSRA = 307 -ARM64_INS_SSUBL2 = 308 -ARM64_INS_SSUBL = 309 -ARM64_INS_SSUBW2 = 310 -ARM64_INS_SSUBW = 311 -ARM64_INS_ST1 = 312 -ARM64_INS_ST2 = 313 -ARM64_INS_ST3 = 314 -ARM64_INS_ST4 = 315 -ARM64_INS_STLRB = 316 -ARM64_INS_STLRH = 317 -ARM64_INS_STLR = 318 -ARM64_INS_STLXP = 319 -ARM64_INS_STLXRB = 320 -ARM64_INS_STLXRH = 321 -ARM64_INS_STLXR = 322 -ARM64_INS_STNP = 323 -ARM64_INS_STP = 324 -ARM64_INS_STRB = 325 -ARM64_INS_STR = 326 -ARM64_INS_STRH = 327 -ARM64_INS_STTRB = 328 -ARM64_INS_STTRH = 329 -ARM64_INS_STTR = 330 -ARM64_INS_STURB = 331 -ARM64_INS_STUR = 332 -ARM64_INS_STURH = 333 -ARM64_INS_STXP = 334 -ARM64_INS_STXRB = 335 -ARM64_INS_STXRH = 336 -ARM64_INS_STXR = 337 -ARM64_INS_SUBHN = 338 -ARM64_INS_SUBHN2 = 339 -ARM64_INS_SUB = 340 -ARM64_INS_SUQADD = 341 -ARM64_INS_SVC = 342 -ARM64_INS_SYSL = 343 -ARM64_INS_SYS = 344 -ARM64_INS_TBL = 345 -ARM64_INS_TBNZ = 346 -ARM64_INS_TBX = 347 -ARM64_INS_TBZ = 348 -ARM64_INS_TRN1 = 349 -ARM64_INS_TRN2 = 350 -ARM64_INS_UABAL2 = 351 -ARM64_INS_UABAL = 352 -ARM64_INS_UABA = 353 -ARM64_INS_UABDL2 = 354 -ARM64_INS_UABDL = 355 -ARM64_INS_UABD = 356 -ARM64_INS_UADALP = 357 -ARM64_INS_UADDLP = 358 -ARM64_INS_UADDLV = 359 -ARM64_INS_UADDL2 = 360 -ARM64_INS_UADDL = 361 -ARM64_INS_UADDW2 = 362 -ARM64_INS_UADDW = 363 -ARM64_INS_UBFM = 364 -ARM64_INS_UCVTF = 365 -ARM64_INS_UDIV = 366 -ARM64_INS_UHADD = 367 -ARM64_INS_UHSUB = 368 -ARM64_INS_UMADDL = 369 -ARM64_INS_UMAXP = 370 -ARM64_INS_UMAXV = 371 -ARM64_INS_UMAX = 372 -ARM64_INS_UMINP = 373 -ARM64_INS_UMINV = 374 -ARM64_INS_UMIN = 375 -ARM64_INS_UMLAL2 = 376 -ARM64_INS_UMLAL = 377 -ARM64_INS_UMLSL2 = 378 -ARM64_INS_UMLSL = 379 -ARM64_INS_UMOV = 380 -ARM64_INS_UMSUBL = 381 -ARM64_INS_UMULH = 382 -ARM64_INS_UMULL2 = 383 -ARM64_INS_UMULL = 384 -ARM64_INS_UQADD = 385 -ARM64_INS_UQRSHL = 386 -ARM64_INS_UQRSHRN = 387 -ARM64_INS_UQRSHRN2 = 388 -ARM64_INS_UQSHL = 389 -ARM64_INS_UQSHRN = 390 -ARM64_INS_UQSHRN2 = 391 -ARM64_INS_UQSUB = 392 -ARM64_INS_UQXTN2 = 393 -ARM64_INS_UQXTN = 394 -ARM64_INS_URECPE = 395 -ARM64_INS_URHADD = 396 -ARM64_INS_URSHL = 397 -ARM64_INS_URSHR = 398 -ARM64_INS_URSQRTE = 399 -ARM64_INS_URSRA = 400 -ARM64_INS_USHLL2 = 401 -ARM64_INS_USHLL = 402 -ARM64_INS_USHL = 403 -ARM64_INS_USHR = 404 -ARM64_INS_USQADD = 405 -ARM64_INS_USRA = 406 -ARM64_INS_USUBL2 = 407 -ARM64_INS_USUBL = 408 -ARM64_INS_USUBW2 = 409 -ARM64_INS_USUBW = 410 -ARM64_INS_UZP1 = 411 -ARM64_INS_UZP2 = 412 -ARM64_INS_XTN2 = 413 -ARM64_INS_XTN = 414 -ARM64_INS_ZIP1 = 415 -ARM64_INS_ZIP2 = 416 -ARM64_INS_MNEG = 417 -ARM64_INS_UMNEGL = 418 -ARM64_INS_SMNEGL = 419 -ARM64_INS_NOP = 420 -ARM64_INS_YIELD = 421 -ARM64_INS_WFE = 422 -ARM64_INS_WFI = 423 -ARM64_INS_SEV = 424 -ARM64_INS_SEVL = 425 -ARM64_INS_NGC = 426 -ARM64_INS_SBFIZ = 427 -ARM64_INS_UBFIZ = 428 -ARM64_INS_SBFX = 429 -ARM64_INS_UBFX = 430 -ARM64_INS_BFI = 431 -ARM64_INS_BFXIL = 432 -ARM64_INS_CMN = 433 -ARM64_INS_MVN = 434 -ARM64_INS_TST = 435 -ARM64_INS_CSET = 436 -ARM64_INS_CINC = 437 -ARM64_INS_CSETM = 438 -ARM64_INS_CINV = 439 -ARM64_INS_CNEG = 440 -ARM64_INS_SXTB = 441 -ARM64_INS_SXTH = 442 -ARM64_INS_SXTW = 443 -ARM64_INS_CMP = 444 -ARM64_INS_UXTB = 445 -ARM64_INS_UXTH = 446 -ARM64_INS_UXTW = 447 -ARM64_INS_IC = 448 -ARM64_INS_DC = 449 -ARM64_INS_AT = 450 -ARM64_INS_TLBI = 451 -ARM64_INS_NEGS = 452 -ARM64_INS_NGCS = 453 -ARM64_INS_ENDING = 454 +ARM64_INS_ADCS = 3 +ARM64_INS_ADD = 4 +ARM64_INS_ADDHN = 5 +ARM64_INS_ADDHN2 = 6 +ARM64_INS_ADDP = 7 +ARM64_INS_ADDPL = 8 +ARM64_INS_ADDS = 9 +ARM64_INS_ADDV = 10 +ARM64_INS_ADDVL = 11 +ARM64_INS_ADR = 12 +ARM64_INS_ADRP = 13 +ARM64_INS_AESD = 14 +ARM64_INS_AESE = 15 +ARM64_INS_AESIMC = 16 +ARM64_INS_AESMC = 17 +ARM64_INS_AND = 18 +ARM64_INS_ANDS = 19 +ARM64_INS_ANDV = 20 +ARM64_INS_ASR = 21 +ARM64_INS_ASRD = 22 +ARM64_INS_ASRR = 23 +ARM64_INS_ASRV = 24 +ARM64_INS_AUTDA = 25 +ARM64_INS_AUTDB = 26 +ARM64_INS_AUTDZA = 27 +ARM64_INS_AUTDZB = 28 +ARM64_INS_AUTIA = 29 +ARM64_INS_AUTIA1716 = 30 +ARM64_INS_AUTIASP = 31 +ARM64_INS_AUTIAZ = 32 +ARM64_INS_AUTIB = 33 +ARM64_INS_AUTIB1716 = 34 +ARM64_INS_AUTIBSP = 35 +ARM64_INS_AUTIBZ = 36 +ARM64_INS_AUTIZA = 37 +ARM64_INS_AUTIZB = 38 +ARM64_INS_B = 39 +ARM64_INS_BCAX = 40 +ARM64_INS_BFM = 41 +ARM64_INS_BIC = 42 +ARM64_INS_BICS = 43 +ARM64_INS_BIF = 44 +ARM64_INS_BIT = 45 +ARM64_INS_BL = 46 +ARM64_INS_BLR = 47 +ARM64_INS_BLRAA = 48 +ARM64_INS_BLRAAZ = 49 +ARM64_INS_BLRAB = 50 +ARM64_INS_BLRABZ = 51 +ARM64_INS_BR = 52 +ARM64_INS_BRAA = 53 +ARM64_INS_BRAAZ = 54 +ARM64_INS_BRAB = 55 +ARM64_INS_BRABZ = 56 +ARM64_INS_BRK = 57 +ARM64_INS_BRKA = 58 +ARM64_INS_BRKAS = 59 +ARM64_INS_BRKB = 60 +ARM64_INS_BRKBS = 61 +ARM64_INS_BRKN = 62 +ARM64_INS_BRKNS = 63 +ARM64_INS_BRKPA = 64 +ARM64_INS_BRKPAS = 65 +ARM64_INS_BRKPB = 66 +ARM64_INS_BRKPBS = 67 +ARM64_INS_BSL = 68 +ARM64_INS_CAS = 69 +ARM64_INS_CASA = 70 +ARM64_INS_CASAB = 71 +ARM64_INS_CASAH = 72 +ARM64_INS_CASAL = 73 +ARM64_INS_CASALB = 74 +ARM64_INS_CASALH = 75 +ARM64_INS_CASB = 76 +ARM64_INS_CASH = 77 +ARM64_INS_CASL = 78 +ARM64_INS_CASLB = 79 +ARM64_INS_CASLH = 80 +ARM64_INS_CASP = 81 +ARM64_INS_CASPA = 82 +ARM64_INS_CASPAL = 83 +ARM64_INS_CASPL = 84 +ARM64_INS_CBNZ = 85 +ARM64_INS_CBZ = 86 +ARM64_INS_CCMN = 87 +ARM64_INS_CCMP = 88 +ARM64_INS_CFINV = 89 +ARM64_INS_CINC = 90 +ARM64_INS_CINV = 91 +ARM64_INS_CLASTA = 92 +ARM64_INS_CLASTB = 93 +ARM64_INS_CLREX = 94 +ARM64_INS_CLS = 95 +ARM64_INS_CLZ = 96 +ARM64_INS_CMEQ = 97 +ARM64_INS_CMGE = 98 +ARM64_INS_CMGT = 99 +ARM64_INS_CMHI = 100 +ARM64_INS_CMHS = 101 +ARM64_INS_CMLE = 102 +ARM64_INS_CMLO = 103 +ARM64_INS_CMLS = 104 +ARM64_INS_CMLT = 105 +ARM64_INS_CMN = 106 +ARM64_INS_CMP = 107 +ARM64_INS_CMPEQ = 108 +ARM64_INS_CMPGE = 109 +ARM64_INS_CMPGT = 110 +ARM64_INS_CMPHI = 111 +ARM64_INS_CMPHS = 112 +ARM64_INS_CMPLE = 113 +ARM64_INS_CMPLO = 114 +ARM64_INS_CMPLS = 115 +ARM64_INS_CMPLT = 116 +ARM64_INS_CMPNE = 117 +ARM64_INS_CMTST = 118 +ARM64_INS_CNEG = 119 +ARM64_INS_CNOT = 120 +ARM64_INS_CNT = 121 +ARM64_INS_CNTB = 122 +ARM64_INS_CNTD = 123 +ARM64_INS_CNTH = 124 +ARM64_INS_CNTP = 125 +ARM64_INS_CNTW = 126 +ARM64_INS_COMPACT = 127 +ARM64_INS_CPY = 128 +ARM64_INS_CRC32B = 129 +ARM64_INS_CRC32CB = 130 +ARM64_INS_CRC32CH = 131 +ARM64_INS_CRC32CW = 132 +ARM64_INS_CRC32CX = 133 +ARM64_INS_CRC32H = 134 +ARM64_INS_CRC32W = 135 +ARM64_INS_CRC32X = 136 +ARM64_INS_CSDB = 137 +ARM64_INS_CSEL = 138 +ARM64_INS_CSET = 139 +ARM64_INS_CSETM = 140 +ARM64_INS_CSINC = 141 +ARM64_INS_CSINV = 142 +ARM64_INS_CSNEG = 143 +ARM64_INS_CTERMEQ = 144 +ARM64_INS_CTERMNE = 145 +ARM64_INS_DCPS1 = 146 +ARM64_INS_DCPS2 = 147 +ARM64_INS_DCPS3 = 148 +ARM64_INS_DECB = 149 +ARM64_INS_DECD = 150 +ARM64_INS_DECH = 151 +ARM64_INS_DECP = 152 +ARM64_INS_DECW = 153 +ARM64_INS_DMB = 154 +ARM64_INS_DRPS = 155 +ARM64_INS_DSB = 156 +ARM64_INS_DUP = 157 +ARM64_INS_DUPM = 158 +ARM64_INS_EON = 159 +ARM64_INS_EOR = 160 +ARM64_INS_EOR3 = 161 +ARM64_INS_EORS = 162 +ARM64_INS_EORV = 163 +ARM64_INS_ERET = 164 +ARM64_INS_ERETAA = 165 +ARM64_INS_ERETAB = 166 +ARM64_INS_ESB = 167 +ARM64_INS_EXT = 168 +ARM64_INS_EXTR = 169 +ARM64_INS_FABD = 170 +ARM64_INS_FABS = 171 +ARM64_INS_FACGE = 172 +ARM64_INS_FACGT = 173 +ARM64_INS_FACLE = 174 +ARM64_INS_FACLT = 175 +ARM64_INS_FADD = 176 +ARM64_INS_FADDA = 177 +ARM64_INS_FADDP = 178 +ARM64_INS_FADDV = 179 +ARM64_INS_FCADD = 180 +ARM64_INS_FCCMP = 181 +ARM64_INS_FCCMPE = 182 +ARM64_INS_FCMEQ = 183 +ARM64_INS_FCMGE = 184 +ARM64_INS_FCMGT = 185 +ARM64_INS_FCMLA = 186 +ARM64_INS_FCMLE = 187 +ARM64_INS_FCMLT = 188 +ARM64_INS_FCMNE = 189 +ARM64_INS_FCMP = 190 +ARM64_INS_FCMPE = 191 +ARM64_INS_FCMUO = 192 +ARM64_INS_FCPY = 193 +ARM64_INS_FCSEL = 194 +ARM64_INS_FCVT = 195 +ARM64_INS_FCVTAS = 196 +ARM64_INS_FCVTAU = 197 +ARM64_INS_FCVTL = 198 +ARM64_INS_FCVTL2 = 199 +ARM64_INS_FCVTMS = 200 +ARM64_INS_FCVTMU = 201 +ARM64_INS_FCVTN = 202 +ARM64_INS_FCVTN2 = 203 +ARM64_INS_FCVTNS = 204 +ARM64_INS_FCVTNU = 205 +ARM64_INS_FCVTPS = 206 +ARM64_INS_FCVTPU = 207 +ARM64_INS_FCVTXN = 208 +ARM64_INS_FCVTXN2 = 209 +ARM64_INS_FCVTZS = 210 +ARM64_INS_FCVTZU = 211 +ARM64_INS_FDIV = 212 +ARM64_INS_FDIVR = 213 +ARM64_INS_FDUP = 214 +ARM64_INS_FEXPA = 215 +ARM64_INS_FJCVTZS = 216 +ARM64_INS_FMAD = 217 +ARM64_INS_FMADD = 218 +ARM64_INS_FMAX = 219 +ARM64_INS_FMAXNM = 220 +ARM64_INS_FMAXNMP = 221 +ARM64_INS_FMAXNMV = 222 +ARM64_INS_FMAXP = 223 +ARM64_INS_FMAXV = 224 +ARM64_INS_FMIN = 225 +ARM64_INS_FMINNM = 226 +ARM64_INS_FMINNMP = 227 +ARM64_INS_FMINNMV = 228 +ARM64_INS_FMINP = 229 +ARM64_INS_FMINV = 230 +ARM64_INS_FMLA = 231 +ARM64_INS_FMLS = 232 +ARM64_INS_FMOV = 233 +ARM64_INS_FMSB = 234 +ARM64_INS_FMSUB = 235 +ARM64_INS_FMUL = 236 +ARM64_INS_FMULX = 237 +ARM64_INS_FNEG = 238 +ARM64_INS_FNMAD = 239 +ARM64_INS_FNMADD = 240 +ARM64_INS_FNMLA = 241 +ARM64_INS_FNMLS = 242 +ARM64_INS_FNMSB = 243 +ARM64_INS_FNMSUB = 244 +ARM64_INS_FNMUL = 245 +ARM64_INS_FRECPE = 246 +ARM64_INS_FRECPS = 247 +ARM64_INS_FRECPX = 248 +ARM64_INS_FRINTA = 249 +ARM64_INS_FRINTI = 250 +ARM64_INS_FRINTM = 251 +ARM64_INS_FRINTN = 252 +ARM64_INS_FRINTP = 253 +ARM64_INS_FRINTX = 254 +ARM64_INS_FRINTZ = 255 +ARM64_INS_FRSQRTE = 256 +ARM64_INS_FRSQRTS = 257 +ARM64_INS_FSCALE = 258 +ARM64_INS_FSQRT = 259 +ARM64_INS_FSUB = 260 +ARM64_INS_FSUBR = 261 +ARM64_INS_FTMAD = 262 +ARM64_INS_FTSMUL = 263 +ARM64_INS_FTSSEL = 264 +ARM64_INS_HINT = 265 +ARM64_INS_HLT = 266 +ARM64_INS_HVC = 267 +ARM64_INS_INCB = 268 +ARM64_INS_INCD = 269 +ARM64_INS_INCH = 270 +ARM64_INS_INCP = 271 +ARM64_INS_INCW = 272 +ARM64_INS_INDEX = 273 +ARM64_INS_INS = 274 +ARM64_INS_INSR = 275 +ARM64_INS_ISB = 276 +ARM64_INS_LASTA = 277 +ARM64_INS_LASTB = 278 +ARM64_INS_LD1 = 279 +ARM64_INS_LD1B = 280 +ARM64_INS_LD1D = 281 +ARM64_INS_LD1H = 282 +ARM64_INS_LD1R = 283 +ARM64_INS_LD1RB = 284 +ARM64_INS_LD1RD = 285 +ARM64_INS_LD1RH = 286 +ARM64_INS_LD1RQB = 287 +ARM64_INS_LD1RQD = 288 +ARM64_INS_LD1RQH = 289 +ARM64_INS_LD1RQW = 290 +ARM64_INS_LD1RSB = 291 +ARM64_INS_LD1RSH = 292 +ARM64_INS_LD1RSW = 293 +ARM64_INS_LD1RW = 294 +ARM64_INS_LD1SB = 295 +ARM64_INS_LD1SH = 296 +ARM64_INS_LD1SW = 297 +ARM64_INS_LD1W = 298 +ARM64_INS_LD2 = 299 +ARM64_INS_LD2B = 300 +ARM64_INS_LD2D = 301 +ARM64_INS_LD2H = 302 +ARM64_INS_LD2R = 303 +ARM64_INS_LD2W = 304 +ARM64_INS_LD3 = 305 +ARM64_INS_LD3B = 306 +ARM64_INS_LD3D = 307 +ARM64_INS_LD3H = 308 +ARM64_INS_LD3R = 309 +ARM64_INS_LD3W = 310 +ARM64_INS_LD4 = 311 +ARM64_INS_LD4B = 312 +ARM64_INS_LD4D = 313 +ARM64_INS_LD4H = 314 +ARM64_INS_LD4R = 315 +ARM64_INS_LD4W = 316 +ARM64_INS_LDADD = 317 +ARM64_INS_LDADDA = 318 +ARM64_INS_LDADDAB = 319 +ARM64_INS_LDADDAH = 320 +ARM64_INS_LDADDAL = 321 +ARM64_INS_LDADDALB = 322 +ARM64_INS_LDADDALH = 323 +ARM64_INS_LDADDB = 324 +ARM64_INS_LDADDH = 325 +ARM64_INS_LDADDL = 326 +ARM64_INS_LDADDLB = 327 +ARM64_INS_LDADDLH = 328 +ARM64_INS_LDAPR = 329 +ARM64_INS_LDAPRB = 330 +ARM64_INS_LDAPRH = 331 +ARM64_INS_LDAPUR = 332 +ARM64_INS_LDAPURB = 333 +ARM64_INS_LDAPURH = 334 +ARM64_INS_LDAPURSB = 335 +ARM64_INS_LDAPURSH = 336 +ARM64_INS_LDAPURSW = 337 +ARM64_INS_LDAR = 338 +ARM64_INS_LDARB = 339 +ARM64_INS_LDARH = 340 +ARM64_INS_LDAXP = 341 +ARM64_INS_LDAXR = 342 +ARM64_INS_LDAXRB = 343 +ARM64_INS_LDAXRH = 344 +ARM64_INS_LDCLR = 345 +ARM64_INS_LDCLRA = 346 +ARM64_INS_LDCLRAB = 347 +ARM64_INS_LDCLRAH = 348 +ARM64_INS_LDCLRAL = 349 +ARM64_INS_LDCLRALB = 350 +ARM64_INS_LDCLRALH = 351 +ARM64_INS_LDCLRB = 352 +ARM64_INS_LDCLRH = 353 +ARM64_INS_LDCLRL = 354 +ARM64_INS_LDCLRLB = 355 +ARM64_INS_LDCLRLH = 356 +ARM64_INS_LDEOR = 357 +ARM64_INS_LDEORA = 358 +ARM64_INS_LDEORAB = 359 +ARM64_INS_LDEORAH = 360 +ARM64_INS_LDEORAL = 361 +ARM64_INS_LDEORALB = 362 +ARM64_INS_LDEORALH = 363 +ARM64_INS_LDEORB = 364 +ARM64_INS_LDEORH = 365 +ARM64_INS_LDEORL = 366 +ARM64_INS_LDEORLB = 367 +ARM64_INS_LDEORLH = 368 +ARM64_INS_LDFF1B = 369 +ARM64_INS_LDFF1D = 370 +ARM64_INS_LDFF1H = 371 +ARM64_INS_LDFF1SB = 372 +ARM64_INS_LDFF1SH = 373 +ARM64_INS_LDFF1SW = 374 +ARM64_INS_LDFF1W = 375 +ARM64_INS_LDLAR = 376 +ARM64_INS_LDLARB = 377 +ARM64_INS_LDLARH = 378 +ARM64_INS_LDNF1B = 379 +ARM64_INS_LDNF1D = 380 +ARM64_INS_LDNF1H = 381 +ARM64_INS_LDNF1SB = 382 +ARM64_INS_LDNF1SH = 383 +ARM64_INS_LDNF1SW = 384 +ARM64_INS_LDNF1W = 385 +ARM64_INS_LDNP = 386 +ARM64_INS_LDNT1B = 387 +ARM64_INS_LDNT1D = 388 +ARM64_INS_LDNT1H = 389 +ARM64_INS_LDNT1W = 390 +ARM64_INS_LDP = 391 +ARM64_INS_LDPSW = 392 +ARM64_INS_LDR = 393 +ARM64_INS_LDRAA = 394 +ARM64_INS_LDRAB = 395 +ARM64_INS_LDRB = 396 +ARM64_INS_LDRH = 397 +ARM64_INS_LDRSB = 398 +ARM64_INS_LDRSH = 399 +ARM64_INS_LDRSW = 400 +ARM64_INS_LDSET = 401 +ARM64_INS_LDSETA = 402 +ARM64_INS_LDSETAB = 403 +ARM64_INS_LDSETAH = 404 +ARM64_INS_LDSETAL = 405 +ARM64_INS_LDSETALB = 406 +ARM64_INS_LDSETALH = 407 +ARM64_INS_LDSETB = 408 +ARM64_INS_LDSETH = 409 +ARM64_INS_LDSETL = 410 +ARM64_INS_LDSETLB = 411 +ARM64_INS_LDSETLH = 412 +ARM64_INS_LDSMAX = 413 +ARM64_INS_LDSMAXA = 414 +ARM64_INS_LDSMAXAB = 415 +ARM64_INS_LDSMAXAH = 416 +ARM64_INS_LDSMAXAL = 417 +ARM64_INS_LDSMAXALB = 418 +ARM64_INS_LDSMAXALH = 419 +ARM64_INS_LDSMAXB = 420 +ARM64_INS_LDSMAXH = 421 +ARM64_INS_LDSMAXL = 422 +ARM64_INS_LDSMAXLB = 423 +ARM64_INS_LDSMAXLH = 424 +ARM64_INS_LDSMIN = 425 +ARM64_INS_LDSMINA = 426 +ARM64_INS_LDSMINAB = 427 +ARM64_INS_LDSMINAH = 428 +ARM64_INS_LDSMINAL = 429 +ARM64_INS_LDSMINALB = 430 +ARM64_INS_LDSMINALH = 431 +ARM64_INS_LDSMINB = 432 +ARM64_INS_LDSMINH = 433 +ARM64_INS_LDSMINL = 434 +ARM64_INS_LDSMINLB = 435 +ARM64_INS_LDSMINLH = 436 +ARM64_INS_LDTR = 437 +ARM64_INS_LDTRB = 438 +ARM64_INS_LDTRH = 439 +ARM64_INS_LDTRSB = 440 +ARM64_INS_LDTRSH = 441 +ARM64_INS_LDTRSW = 442 +ARM64_INS_LDUMAX = 443 +ARM64_INS_LDUMAXA = 444 +ARM64_INS_LDUMAXAB = 445 +ARM64_INS_LDUMAXAH = 446 +ARM64_INS_LDUMAXAL = 447 +ARM64_INS_LDUMAXALB = 448 +ARM64_INS_LDUMAXALH = 449 +ARM64_INS_LDUMAXB = 450 +ARM64_INS_LDUMAXH = 451 +ARM64_INS_LDUMAXL = 452 +ARM64_INS_LDUMAXLB = 453 +ARM64_INS_LDUMAXLH = 454 +ARM64_INS_LDUMIN = 455 +ARM64_INS_LDUMINA = 456 +ARM64_INS_LDUMINAB = 457 +ARM64_INS_LDUMINAH = 458 +ARM64_INS_LDUMINAL = 459 +ARM64_INS_LDUMINALB = 460 +ARM64_INS_LDUMINALH = 461 +ARM64_INS_LDUMINB = 462 +ARM64_INS_LDUMINH = 463 +ARM64_INS_LDUMINL = 464 +ARM64_INS_LDUMINLB = 465 +ARM64_INS_LDUMINLH = 466 +ARM64_INS_LDUR = 467 +ARM64_INS_LDURB = 468 +ARM64_INS_LDURH = 469 +ARM64_INS_LDURSB = 470 +ARM64_INS_LDURSH = 471 +ARM64_INS_LDURSW = 472 +ARM64_INS_LDXP = 473 +ARM64_INS_LDXR = 474 +ARM64_INS_LDXRB = 475 +ARM64_INS_LDXRH = 476 +ARM64_INS_LSL = 477 +ARM64_INS_LSLR = 478 +ARM64_INS_LSLV = 479 +ARM64_INS_LSR = 480 +ARM64_INS_LSRR = 481 +ARM64_INS_LSRV = 482 +ARM64_INS_MAD = 483 +ARM64_INS_MADD = 484 +ARM64_INS_MLA = 485 +ARM64_INS_MLS = 486 +ARM64_INS_MNEG = 487 +ARM64_INS_MOV = 488 +ARM64_INS_MOVI = 489 +ARM64_INS_MOVK = 490 +ARM64_INS_MOVN = 491 +ARM64_INS_MOVPRFX = 492 +ARM64_INS_MOVS = 493 +ARM64_INS_MOVZ = 494 +ARM64_INS_MRS = 495 +ARM64_INS_MSB = 496 +ARM64_INS_MSR = 497 +ARM64_INS_MSUB = 498 +ARM64_INS_MUL = 499 +ARM64_INS_MVN = 500 +ARM64_INS_MVNI = 501 +ARM64_INS_NAND = 502 +ARM64_INS_NANDS = 503 +ARM64_INS_NEG = 504 +ARM64_INS_NEGS = 505 +ARM64_INS_NGC = 506 +ARM64_INS_NGCS = 507 +ARM64_INS_NOP = 508 +ARM64_INS_NOR = 509 +ARM64_INS_NORS = 510 +ARM64_INS_NOT = 511 +ARM64_INS_NOTS = 512 +ARM64_INS_ORN = 513 +ARM64_INS_ORNS = 514 +ARM64_INS_ORR = 515 +ARM64_INS_ORRS = 516 +ARM64_INS_ORV = 517 +ARM64_INS_PACDA = 518 +ARM64_INS_PACDB = 519 +ARM64_INS_PACDZA = 520 +ARM64_INS_PACDZB = 521 +ARM64_INS_PACGA = 522 +ARM64_INS_PACIA = 523 +ARM64_INS_PACIA1716 = 524 +ARM64_INS_PACIASP = 525 +ARM64_INS_PACIAZ = 526 +ARM64_INS_PACIB = 527 +ARM64_INS_PACIB1716 = 528 +ARM64_INS_PACIBSP = 529 +ARM64_INS_PACIBZ = 530 +ARM64_INS_PACIZA = 531 +ARM64_INS_PACIZB = 532 +ARM64_INS_PFALSE = 533 +ARM64_INS_PFIRST = 534 +ARM64_INS_PMUL = 535 +ARM64_INS_PMULL = 536 +ARM64_INS_PMULL2 = 537 +ARM64_INS_PNEXT = 538 +ARM64_INS_PRFB = 539 +ARM64_INS_PRFD = 540 +ARM64_INS_PRFH = 541 +ARM64_INS_PRFM = 542 +ARM64_INS_PRFUM = 543 +ARM64_INS_PRFW = 544 +ARM64_INS_PSB = 545 +ARM64_INS_PTEST = 546 +ARM64_INS_PTRUE = 547 +ARM64_INS_PTRUES = 548 +ARM64_INS_PUNPKHI = 549 +ARM64_INS_PUNPKLO = 550 +ARM64_INS_RADDHN = 551 +ARM64_INS_RADDHN2 = 552 +ARM64_INS_RAX1 = 553 +ARM64_INS_RBIT = 554 +ARM64_INS_RDFFR = 555 +ARM64_INS_RDFFRS = 556 +ARM64_INS_RDVL = 557 +ARM64_INS_RET = 558 +ARM64_INS_RETAA = 559 +ARM64_INS_RETAB = 560 +ARM64_INS_REV = 561 +ARM64_INS_REV16 = 562 +ARM64_INS_REV32 = 563 +ARM64_INS_REV64 = 564 +ARM64_INS_REVB = 565 +ARM64_INS_REVH = 566 +ARM64_INS_REVW = 567 +ARM64_INS_RMIF = 568 +ARM64_INS_ROR = 569 +ARM64_INS_RORV = 570 +ARM64_INS_RSHRN = 571 +ARM64_INS_RSHRN2 = 572 +ARM64_INS_RSUBHN = 573 +ARM64_INS_RSUBHN2 = 574 +ARM64_INS_SABA = 575 +ARM64_INS_SABAL = 576 +ARM64_INS_SABAL2 = 577 +ARM64_INS_SABD = 578 +ARM64_INS_SABDL = 579 +ARM64_INS_SABDL2 = 580 +ARM64_INS_SADALP = 581 +ARM64_INS_SADDL = 582 +ARM64_INS_SADDL2 = 583 +ARM64_INS_SADDLP = 584 +ARM64_INS_SADDLV = 585 +ARM64_INS_SADDV = 586 +ARM64_INS_SADDW = 587 +ARM64_INS_SADDW2 = 588 +ARM64_INS_SBC = 589 +ARM64_INS_SBCS = 590 +ARM64_INS_SBFM = 591 +ARM64_INS_SCVTF = 592 +ARM64_INS_SDIV = 593 +ARM64_INS_SDIVR = 594 +ARM64_INS_SDOT = 595 +ARM64_INS_SEL = 596 +ARM64_INS_SETF16 = 597 +ARM64_INS_SETF8 = 598 +ARM64_INS_SETFFR = 599 +ARM64_INS_SEV = 600 +ARM64_INS_SEVL = 601 +ARM64_INS_SHA1C = 602 +ARM64_INS_SHA1H = 603 +ARM64_INS_SHA1M = 604 +ARM64_INS_SHA1P = 605 +ARM64_INS_SHA1SU0 = 606 +ARM64_INS_SHA1SU1 = 607 +ARM64_INS_SHA256H = 608 +ARM64_INS_SHA256H2 = 609 +ARM64_INS_SHA256SU0 = 610 +ARM64_INS_SHA256SU1 = 611 +ARM64_INS_SHA512H = 612 +ARM64_INS_SHA512H2 = 613 +ARM64_INS_SHA512SU0 = 614 +ARM64_INS_SHA512SU1 = 615 +ARM64_INS_SHADD = 616 +ARM64_INS_SHL = 617 +ARM64_INS_SHLL = 618 +ARM64_INS_SHLL2 = 619 +ARM64_INS_SHRN = 620 +ARM64_INS_SHRN2 = 621 +ARM64_INS_SHSUB = 622 +ARM64_INS_SLI = 623 +ARM64_INS_SM3PARTW1 = 624 +ARM64_INS_SM3PARTW2 = 625 +ARM64_INS_SM3SS1 = 626 +ARM64_INS_SM3TT1A = 627 +ARM64_INS_SM3TT1B = 628 +ARM64_INS_SM3TT2A = 629 +ARM64_INS_SM3TT2B = 630 +ARM64_INS_SM4E = 631 +ARM64_INS_SM4EKEY = 632 +ARM64_INS_SMADDL = 633 +ARM64_INS_SMAX = 634 +ARM64_INS_SMAXP = 635 +ARM64_INS_SMAXV = 636 +ARM64_INS_SMC = 637 +ARM64_INS_SMIN = 638 +ARM64_INS_SMINP = 639 +ARM64_INS_SMINV = 640 +ARM64_INS_SMLAL = 641 +ARM64_INS_SMLAL2 = 642 +ARM64_INS_SMLSL = 643 +ARM64_INS_SMLSL2 = 644 +ARM64_INS_SMNEGL = 645 +ARM64_INS_SMOV = 646 +ARM64_INS_SMSUBL = 647 +ARM64_INS_SMULH = 648 +ARM64_INS_SMULL = 649 +ARM64_INS_SMULL2 = 650 +ARM64_INS_SPLICE = 651 +ARM64_INS_SQABS = 652 +ARM64_INS_SQADD = 653 +ARM64_INS_SQDECB = 654 +ARM64_INS_SQDECD = 655 +ARM64_INS_SQDECH = 656 +ARM64_INS_SQDECP = 657 +ARM64_INS_SQDECW = 658 +ARM64_INS_SQDMLAL = 659 +ARM64_INS_SQDMLAL2 = 660 +ARM64_INS_SQDMLSL = 661 +ARM64_INS_SQDMLSL2 = 662 +ARM64_INS_SQDMULH = 663 +ARM64_INS_SQDMULL = 664 +ARM64_INS_SQDMULL2 = 665 +ARM64_INS_SQINCB = 666 +ARM64_INS_SQINCD = 667 +ARM64_INS_SQINCH = 668 +ARM64_INS_SQINCP = 669 +ARM64_INS_SQINCW = 670 +ARM64_INS_SQNEG = 671 +ARM64_INS_SQRDMLAH = 672 +ARM64_INS_SQRDMLSH = 673 +ARM64_INS_SQRDMULH = 674 +ARM64_INS_SQRSHL = 675 +ARM64_INS_SQRSHRN = 676 +ARM64_INS_SQRSHRN2 = 677 +ARM64_INS_SQRSHRUN = 678 +ARM64_INS_SQRSHRUN2 = 679 +ARM64_INS_SQSHL = 680 +ARM64_INS_SQSHLU = 681 +ARM64_INS_SQSHRN = 682 +ARM64_INS_SQSHRN2 = 683 +ARM64_INS_SQSHRUN = 684 +ARM64_INS_SQSHRUN2 = 685 +ARM64_INS_SQSUB = 686 +ARM64_INS_SQXTN = 687 +ARM64_INS_SQXTN2 = 688 +ARM64_INS_SQXTUN = 689 +ARM64_INS_SQXTUN2 = 690 +ARM64_INS_SRHADD = 691 +ARM64_INS_SRI = 692 +ARM64_INS_SRSHL = 693 +ARM64_INS_SRSHR = 694 +ARM64_INS_SRSRA = 695 +ARM64_INS_SSHL = 696 +ARM64_INS_SSHLL = 697 +ARM64_INS_SSHLL2 = 698 +ARM64_INS_SSHR = 699 +ARM64_INS_SSRA = 700 +ARM64_INS_SSUBL = 701 +ARM64_INS_SSUBL2 = 702 +ARM64_INS_SSUBW = 703 +ARM64_INS_SSUBW2 = 704 +ARM64_INS_ST1 = 705 +ARM64_INS_ST1B = 706 +ARM64_INS_ST1D = 707 +ARM64_INS_ST1H = 708 +ARM64_INS_ST1W = 709 +ARM64_INS_ST2 = 710 +ARM64_INS_ST2B = 711 +ARM64_INS_ST2D = 712 +ARM64_INS_ST2H = 713 +ARM64_INS_ST2W = 714 +ARM64_INS_ST3 = 715 +ARM64_INS_ST3B = 716 +ARM64_INS_ST3D = 717 +ARM64_INS_ST3H = 718 +ARM64_INS_ST3W = 719 +ARM64_INS_ST4 = 720 +ARM64_INS_ST4B = 721 +ARM64_INS_ST4D = 722 +ARM64_INS_ST4H = 723 +ARM64_INS_ST4W = 724 +ARM64_INS_STADD = 725 +ARM64_INS_STADDB = 726 +ARM64_INS_STADDH = 727 +ARM64_INS_STADDL = 728 +ARM64_INS_STADDLB = 729 +ARM64_INS_STADDLH = 730 +ARM64_INS_STCLR = 731 +ARM64_INS_STCLRB = 732 +ARM64_INS_STCLRH = 733 +ARM64_INS_STCLRL = 734 +ARM64_INS_STCLRLB = 735 +ARM64_INS_STCLRLH = 736 +ARM64_INS_STEOR = 737 +ARM64_INS_STEORB = 738 +ARM64_INS_STEORH = 739 +ARM64_INS_STEORL = 740 +ARM64_INS_STEORLB = 741 +ARM64_INS_STEORLH = 742 +ARM64_INS_STLLR = 743 +ARM64_INS_STLLRB = 744 +ARM64_INS_STLLRH = 745 +ARM64_INS_STLR = 746 +ARM64_INS_STLRB = 747 +ARM64_INS_STLRH = 748 +ARM64_INS_STLUR = 749 +ARM64_INS_STLURB = 750 +ARM64_INS_STLURH = 751 +ARM64_INS_STLXP = 752 +ARM64_INS_STLXR = 753 +ARM64_INS_STLXRB = 754 +ARM64_INS_STLXRH = 755 +ARM64_INS_STNP = 756 +ARM64_INS_STNT1B = 757 +ARM64_INS_STNT1D = 758 +ARM64_INS_STNT1H = 759 +ARM64_INS_STNT1W = 760 +ARM64_INS_STP = 761 +ARM64_INS_STR = 762 +ARM64_INS_STRB = 763 +ARM64_INS_STRH = 764 +ARM64_INS_STSET = 765 +ARM64_INS_STSETB = 766 +ARM64_INS_STSETH = 767 +ARM64_INS_STSETL = 768 +ARM64_INS_STSETLB = 769 +ARM64_INS_STSETLH = 770 +ARM64_INS_STSMAX = 771 +ARM64_INS_STSMAXB = 772 +ARM64_INS_STSMAXH = 773 +ARM64_INS_STSMAXL = 774 +ARM64_INS_STSMAXLB = 775 +ARM64_INS_STSMAXLH = 776 +ARM64_INS_STSMIN = 777 +ARM64_INS_STSMINB = 778 +ARM64_INS_STSMINH = 779 +ARM64_INS_STSMINL = 780 +ARM64_INS_STSMINLB = 781 +ARM64_INS_STSMINLH = 782 +ARM64_INS_STTR = 783 +ARM64_INS_STTRB = 784 +ARM64_INS_STTRH = 785 +ARM64_INS_STUMAX = 786 +ARM64_INS_STUMAXB = 787 +ARM64_INS_STUMAXH = 788 +ARM64_INS_STUMAXL = 789 +ARM64_INS_STUMAXLB = 790 +ARM64_INS_STUMAXLH = 791 +ARM64_INS_STUMIN = 792 +ARM64_INS_STUMINB = 793 +ARM64_INS_STUMINH = 794 +ARM64_INS_STUMINL = 795 +ARM64_INS_STUMINLB = 796 +ARM64_INS_STUMINLH = 797 +ARM64_INS_STUR = 798 +ARM64_INS_STURB = 799 +ARM64_INS_STURH = 800 +ARM64_INS_STXP = 801 +ARM64_INS_STXR = 802 +ARM64_INS_STXRB = 803 +ARM64_INS_STXRH = 804 +ARM64_INS_SUB = 805 +ARM64_INS_SUBHN = 806 +ARM64_INS_SUBHN2 = 807 +ARM64_INS_SUBR = 808 +ARM64_INS_SUBS = 809 +ARM64_INS_SUNPKHI = 810 +ARM64_INS_SUNPKLO = 811 +ARM64_INS_SUQADD = 812 +ARM64_INS_SVC = 813 +ARM64_INS_SWP = 814 +ARM64_INS_SWPA = 815 +ARM64_INS_SWPAB = 816 +ARM64_INS_SWPAH = 817 +ARM64_INS_SWPAL = 818 +ARM64_INS_SWPALB = 819 +ARM64_INS_SWPALH = 820 +ARM64_INS_SWPB = 821 +ARM64_INS_SWPH = 822 +ARM64_INS_SWPL = 823 +ARM64_INS_SWPLB = 824 +ARM64_INS_SWPLH = 825 +ARM64_INS_SXTB = 826 +ARM64_INS_SXTH = 827 +ARM64_INS_SXTL = 828 +ARM64_INS_SXTL2 = 829 +ARM64_INS_SXTW = 830 +ARM64_INS_SYS = 831 +ARM64_INS_SYSL = 832 +ARM64_INS_TBL = 833 +ARM64_INS_TBNZ = 834 +ARM64_INS_TBX = 835 +ARM64_INS_TBZ = 836 +ARM64_INS_TRN1 = 837 +ARM64_INS_TRN2 = 838 +ARM64_INS_TSB = 839 +ARM64_INS_TST = 840 +ARM64_INS_UABA = 841 +ARM64_INS_UABAL = 842 +ARM64_INS_UABAL2 = 843 +ARM64_INS_UABD = 844 +ARM64_INS_UABDL = 845 +ARM64_INS_UABDL2 = 846 +ARM64_INS_UADALP = 847 +ARM64_INS_UADDL = 848 +ARM64_INS_UADDL2 = 849 +ARM64_INS_UADDLP = 850 +ARM64_INS_UADDLV = 851 +ARM64_INS_UADDV = 852 +ARM64_INS_UADDW = 853 +ARM64_INS_UADDW2 = 854 +ARM64_INS_UBFM = 855 +ARM64_INS_UCVTF = 856 +ARM64_INS_UDIV = 857 +ARM64_INS_UDIVR = 858 +ARM64_INS_UDOT = 859 +ARM64_INS_UHADD = 860 +ARM64_INS_UHSUB = 861 +ARM64_INS_UMADDL = 862 +ARM64_INS_UMAX = 863 +ARM64_INS_UMAXP = 864 +ARM64_INS_UMAXV = 865 +ARM64_INS_UMIN = 866 +ARM64_INS_UMINP = 867 +ARM64_INS_UMINV = 868 +ARM64_INS_UMLAL = 869 +ARM64_INS_UMLAL2 = 870 +ARM64_INS_UMLSL = 871 +ARM64_INS_UMLSL2 = 872 +ARM64_INS_UMNEGL = 873 +ARM64_INS_UMOV = 874 +ARM64_INS_UMSUBL = 875 +ARM64_INS_UMULH = 876 +ARM64_INS_UMULL = 877 +ARM64_INS_UMULL2 = 878 +ARM64_INS_UQADD = 879 +ARM64_INS_UQDECB = 880 +ARM64_INS_UQDECD = 881 +ARM64_INS_UQDECH = 882 +ARM64_INS_UQDECP = 883 +ARM64_INS_UQDECW = 884 +ARM64_INS_UQINCB = 885 +ARM64_INS_UQINCD = 886 +ARM64_INS_UQINCH = 887 +ARM64_INS_UQINCP = 888 +ARM64_INS_UQINCW = 889 +ARM64_INS_UQRSHL = 890 +ARM64_INS_UQRSHRN = 891 +ARM64_INS_UQRSHRN2 = 892 +ARM64_INS_UQSHL = 893 +ARM64_INS_UQSHRN = 894 +ARM64_INS_UQSHRN2 = 895 +ARM64_INS_UQSUB = 896 +ARM64_INS_UQXTN = 897 +ARM64_INS_UQXTN2 = 898 +ARM64_INS_URECPE = 899 +ARM64_INS_URHADD = 900 +ARM64_INS_URSHL = 901 +ARM64_INS_URSHR = 902 +ARM64_INS_URSQRTE = 903 +ARM64_INS_URSRA = 904 +ARM64_INS_USHL = 905 +ARM64_INS_USHLL = 906 +ARM64_INS_USHLL2 = 907 +ARM64_INS_USHR = 908 +ARM64_INS_USQADD = 909 +ARM64_INS_USRA = 910 +ARM64_INS_USUBL = 911 +ARM64_INS_USUBL2 = 912 +ARM64_INS_USUBW = 913 +ARM64_INS_USUBW2 = 914 +ARM64_INS_UUNPKHI = 915 +ARM64_INS_UUNPKLO = 916 +ARM64_INS_UXTB = 917 +ARM64_INS_UXTH = 918 +ARM64_INS_UXTL = 919 +ARM64_INS_UXTL2 = 920 +ARM64_INS_UXTW = 921 +ARM64_INS_UZP1 = 922 +ARM64_INS_UZP2 = 923 +ARM64_INS_WFE = 924 +ARM64_INS_WFI = 925 +ARM64_INS_WHILELE = 926 +ARM64_INS_WHILELO = 927 +ARM64_INS_WHILELS = 928 +ARM64_INS_WHILELT = 929 +ARM64_INS_WRFFR = 930 +ARM64_INS_XAR = 931 +ARM64_INS_XPACD = 932 +ARM64_INS_XPACI = 933 +ARM64_INS_XPACLRI = 934 +ARM64_INS_XTN = 935 +ARM64_INS_XTN2 = 936 +ARM64_INS_YIELD = 937 +ARM64_INS_ZIP1 = 938 +ARM64_INS_ZIP2 = 939 +ARM64_INS_SBFIZ = 940 +ARM64_INS_UBFIZ = 941 +ARM64_INS_SBFX = 942 +ARM64_INS_UBFX = 943 +ARM64_INS_BFI = 944 +ARM64_INS_BFXIL = 945 +ARM64_INS_IC = 946 +ARM64_INS_DC = 947 +ARM64_INS_AT = 948 +ARM64_INS_TLBI = 949 +ARM64_INS_ENDING = 950 ARM64_GRP_INVALID = 0 ARM64_GRP_JUMP = 1 @@ -1003,4 +2244,17 @@ ARM64_GRP_CRYPTO = 128 ARM64_GRP_FPARMV8 = 129 ARM64_GRP_NEON = 130 ARM64_GRP_CRC = 131 -ARM64_GRP_ENDING = 132 +ARM64_GRP_AES = 132 +ARM64_GRP_DOTPROD = 133 +ARM64_GRP_FULLFP16 = 134 +ARM64_GRP_LSE = 135 +ARM64_GRP_RCPC = 136 +ARM64_GRP_RDM = 137 +ARM64_GRP_SHA2 = 138 +ARM64_GRP_SHA3 = 139 +ARM64_GRP_SM4 = 140 +ARM64_GRP_SVE = 141 +ARM64_GRP_V8_1A = 142 +ARM64_GRP_V8_3A = 143 +ARM64_GRP_V8_4A = 144 +ARM64_GRP_ENDING = 145 diff --git a/bindings/python/test_arm64.py b/bindings/python/test_arm64.py index f6c7a422d..6addbaeb3 100755 --- a/bindings/python/test_arm64.py +++ b/bindings/python/test_arm64.py @@ -69,9 +69,6 @@ def print_insn_detail(insn): if i.vas != ARM64_VAS_INVALID: print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas) - if i.vess != ARM64_VESS_INVALID: - print("\t\t\tVector Element Size Specifier: %u" % i.vess) - if i.vector_index != -1: print("\t\t\tVector Index: %u" % i.vector_index) diff --git a/cstool/cstool_arm64.c b/cstool/cstool_arm64.c index 61eeba7fa..a01fcfbe6 100644 --- a/cstool/cstool_arm64.c +++ b/cstool/cstool_arm64.c @@ -102,9 +102,6 @@ void print_insn_detail_arm64(csh handle, cs_insn *ins) if (op->vas != ARM64_VAS_INVALID) printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas); - if (op->vess != ARM64_VESS_INVALID) - printf("\t\t\tVector Element Size Specifier: %u\n", op->vess); - if (op->vector_index != -1) printf("\t\t\tVector Index: %u\n", op->vector_index); } diff --git a/include/capstone/arm64.h b/include/capstone/arm64.h index 156586bea..908d21873 100644 --- a/include/capstone/arm64.h +++ b/include/capstone/arm64.h @@ -56,112 +56,754 @@ typedef enum arm64_cc { ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional) ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional) - //< Note the NV exists purely to disassemble 0b1111. Execution - //< is "always". + //< Note the NV exists purely to disassemble 0b1111. Execution is "always". } arm64_cc; /// System registers typedef enum arm64_sysreg { // System registers for MRS ARM64_SYSREG_INVALID = 0, - ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 - ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 - ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 - ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 - ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 - ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 - ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 - ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 - ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 - ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 - ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001 - ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 - ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 - ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 - ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 - ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 - ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 - ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 - ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 - ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 - ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 - ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 - ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 - ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 - ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 - ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 - ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 - ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 - ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 - ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 - ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 - ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 - ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 - ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 - ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 - ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 - ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 - ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 - ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 - ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 - ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 - ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 - ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 - ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 - ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 - ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000 - ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 - ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 - // Trace registers - ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000 - ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110 - ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110 - ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110 - ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110 - ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110 - ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110 - ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111 - ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111 - ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111 - ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111 - ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111 - ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111 - ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111 - ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111 - ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100 - ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100 - ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 - ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 - ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110 - ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 - ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 - ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111 - ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 - ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 - ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 - ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 - ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 - ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 - ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 - ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 - ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 - ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 - ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 - ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 - ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 - - // GICv3 registers - ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 - ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 - ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 - ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 - ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 - ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 - ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 - ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101 + ARM64_SYSREG_MDCCSR_EL0 = 0x9808, + ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, + ARM64_SYSREG_MDRAR_EL1 = 0x8080, + ARM64_SYSREG_OSLSR_EL1 = 0x808C, + ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83F6, + ARM64_SYSREG_PMCEID0_EL0 = 0xDCE6, + ARM64_SYSREG_PMCEID1_EL0 = 0xDCE7, + ARM64_SYSREG_MIDR_EL1 = 0xC000, + ARM64_SYSREG_CCSIDR_EL1 = 0xC800, + ARM64_SYSREG_CCSIDR2_EL1 = 0xC802, + ARM64_SYSREG_CLIDR_EL1 = 0xC801, + ARM64_SYSREG_CTR_EL0 = 0xD801, + ARM64_SYSREG_MPIDR_EL1 = 0xC005, + ARM64_SYSREG_REVIDR_EL1 = 0xC006, + ARM64_SYSREG_AIDR_EL1 = 0xC807, + ARM64_SYSREG_DCZID_EL0 = 0xD807, + ARM64_SYSREG_ID_PFR0_EL1 = 0xC008, + ARM64_SYSREG_ID_PFR1_EL1 = 0xC009, + ARM64_SYSREG_ID_DFR0_EL1 = 0xC00A, + ARM64_SYSREG_ID_AFR0_EL1 = 0xC00B, + ARM64_SYSREG_ID_MMFR0_EL1 = 0xC00C, + ARM64_SYSREG_ID_MMFR1_EL1 = 0xC00D, + ARM64_SYSREG_ID_MMFR2_EL1 = 0xC00E, + ARM64_SYSREG_ID_MMFR3_EL1 = 0xC00F, + ARM64_SYSREG_ID_ISAR0_EL1 = 0xC010, + ARM64_SYSREG_ID_ISAR1_EL1 = 0xC011, + ARM64_SYSREG_ID_ISAR2_EL1 = 0xC012, + ARM64_SYSREG_ID_ISAR3_EL1 = 0xC013, + ARM64_SYSREG_ID_ISAR4_EL1 = 0xC014, + ARM64_SYSREG_ID_ISAR5_EL1 = 0xC015, + ARM64_SYSREG_ID_ISAR6_EL1 = 0xC017, + ARM64_SYSREG_ID_AA64PFR0_EL1 = 0xC020, + ARM64_SYSREG_ID_AA64PFR1_EL1 = 0xC021, + ARM64_SYSREG_ID_AA64DFR0_EL1 = 0xC028, + ARM64_SYSREG_ID_AA64DFR1_EL1 = 0xC029, + ARM64_SYSREG_ID_AA64AFR0_EL1 = 0xC02C, + ARM64_SYSREG_ID_AA64AFR1_EL1 = 0xC02D, + ARM64_SYSREG_ID_AA64ISAR0_EL1 = 0xC030, + ARM64_SYSREG_ID_AA64ISAR1_EL1 = 0xC031, + ARM64_SYSREG_ID_AA64MMFR0_EL1 = 0xC038, + ARM64_SYSREG_ID_AA64MMFR1_EL1 = 0xC039, + ARM64_SYSREG_ID_AA64MMFR2_EL1 = 0xC03A, + ARM64_SYSREG_MVFR0_EL1 = 0xC018, + ARM64_SYSREG_MVFR1_EL1 = 0xC019, + ARM64_SYSREG_MVFR2_EL1 = 0xC01A, + ARM64_SYSREG_RVBAR_EL1 = 0xC601, + ARM64_SYSREG_RVBAR_EL2 = 0xE601, + ARM64_SYSREG_RVBAR_EL3 = 0xF601, + ARM64_SYSREG_ISR_EL1 = 0xC608, + ARM64_SYSREG_CNTPCT_EL0 = 0xDF01, + ARM64_SYSREG_CNTVCT_EL0 = 0xDF02, + ARM64_SYSREG_ID_MMFR4_EL1 = 0xC016, + ARM64_SYSREG_TRCSTATR = 0x8818, + ARM64_SYSREG_TRCIDR8 = 0x8806, + ARM64_SYSREG_TRCIDR9 = 0x880E, + ARM64_SYSREG_TRCIDR10 = 0x8816, + ARM64_SYSREG_TRCIDR11 = 0x881E, + ARM64_SYSREG_TRCIDR12 = 0x8826, + ARM64_SYSREG_TRCIDR13 = 0x882E, + ARM64_SYSREG_TRCIDR0 = 0x8847, + ARM64_SYSREG_TRCIDR1 = 0x884F, + ARM64_SYSREG_TRCIDR2 = 0x8857, + ARM64_SYSREG_TRCIDR3 = 0x885F, + ARM64_SYSREG_TRCIDR4 = 0x8867, + ARM64_SYSREG_TRCIDR5 = 0x886F, + ARM64_SYSREG_TRCIDR6 = 0x8877, + ARM64_SYSREG_TRCIDR7 = 0x887F, + ARM64_SYSREG_TRCOSLSR = 0x888C, + ARM64_SYSREG_TRCPDSR = 0x88AC, + ARM64_SYSREG_TRCDEVAFF0 = 0x8BD6, + ARM64_SYSREG_TRCDEVAFF1 = 0x8BDE, + ARM64_SYSREG_TRCLSR = 0x8BEE, + ARM64_SYSREG_TRCAUTHSTATUS = 0x8BF6, + ARM64_SYSREG_TRCDEVARCH = 0x8BFE, + ARM64_SYSREG_TRCDEVID = 0x8B97, + ARM64_SYSREG_TRCDEVTYPE = 0x8B9F, + ARM64_SYSREG_TRCPIDR4 = 0x8BA7, + ARM64_SYSREG_TRCPIDR5 = 0x8BAF, + ARM64_SYSREG_TRCPIDR6 = 0x8BB7, + ARM64_SYSREG_TRCPIDR7 = 0x8BBF, + ARM64_SYSREG_TRCPIDR0 = 0x8BC7, + ARM64_SYSREG_TRCPIDR1 = 0x8BCF, + ARM64_SYSREG_TRCPIDR2 = 0x8BD7, + ARM64_SYSREG_TRCPIDR3 = 0x8BDF, + ARM64_SYSREG_TRCCIDR0 = 0x8BE7, + ARM64_SYSREG_TRCCIDR1 = 0x8BEF, + ARM64_SYSREG_TRCCIDR2 = 0x8BF7, + ARM64_SYSREG_TRCCIDR3 = 0x8BFF, + ARM64_SYSREG_ICC_IAR1_EL1 = 0xC660, + ARM64_SYSREG_ICC_IAR0_EL1 = 0xC640, + ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xC662, + ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xC642, + ARM64_SYSREG_ICC_RPR_EL1 = 0xC65B, + ARM64_SYSREG_ICH_VTR_EL2 = 0xE659, + ARM64_SYSREG_ICH_EISR_EL2 = 0xE65B, + ARM64_SYSREG_ICH_ELRSR_EL2 = 0xE65D, + ARM64_SYSREG_ID_AA64ZFR0_EL1 = 0xC024, + ARM64_SYSREG_LORID_EL1 = 0xC527, + ARM64_SYSREG_ERRIDR_EL1 = 0xC298, + ARM64_SYSREG_ERXFR_EL1 = 0xC2A0, + ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, + ARM64_SYSREG_OSLAR_EL1 = 0x8084, + ARM64_SYSREG_PMSWINC_EL0 = 0xDCE4, + ARM64_SYSREG_TRCOSLAR = 0x8884, + ARM64_SYSREG_TRCLAR = 0x8BE6, + ARM64_SYSREG_ICC_EOIR1_EL1 = 0xC661, + ARM64_SYSREG_ICC_EOIR0_EL1 = 0xC641, + ARM64_SYSREG_ICC_DIR_EL1 = 0xC659, + ARM64_SYSREG_ICC_SGI1R_EL1 = 0xC65D, + ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xC65E, + ARM64_SYSREG_ICC_SGI0R_EL1 = 0xC65F, + ARM64_SYSREG_OSDTRRX_EL1 = 0x8002, + ARM64_SYSREG_OSDTRTX_EL1 = 0x801A, + ARM64_SYSREG_TEECR32_EL1 = 0x9000, + ARM64_SYSREG_MDCCINT_EL1 = 0x8010, + ARM64_SYSREG_MDSCR_EL1 = 0x8012, + ARM64_SYSREG_DBGDTR_EL0 = 0x9820, + ARM64_SYSREG_OSECCR_EL1 = 0x8032, + ARM64_SYSREG_DBGVCR32_EL2 = 0xA038, + ARM64_SYSREG_DBGBVR0_EL1 = 0x8004, + ARM64_SYSREG_DBGBVR1_EL1 = 0x800C, + ARM64_SYSREG_DBGBVR2_EL1 = 0x8014, + ARM64_SYSREG_DBGBVR3_EL1 = 0x801C, + ARM64_SYSREG_DBGBVR4_EL1 = 0x8024, + ARM64_SYSREG_DBGBVR5_EL1 = 0x802C, + ARM64_SYSREG_DBGBVR6_EL1 = 0x8034, + ARM64_SYSREG_DBGBVR7_EL1 = 0x803C, + ARM64_SYSREG_DBGBVR8_EL1 = 0x8044, + ARM64_SYSREG_DBGBVR9_EL1 = 0x804C, + ARM64_SYSREG_DBGBVR10_EL1 = 0x8054, + ARM64_SYSREG_DBGBVR11_EL1 = 0x805C, + ARM64_SYSREG_DBGBVR12_EL1 = 0x8064, + ARM64_SYSREG_DBGBVR13_EL1 = 0x806C, + ARM64_SYSREG_DBGBVR14_EL1 = 0x8074, + ARM64_SYSREG_DBGBVR15_EL1 = 0x807C, + ARM64_SYSREG_DBGBCR0_EL1 = 0x8005, + ARM64_SYSREG_DBGBCR1_EL1 = 0x800D, + ARM64_SYSREG_DBGBCR2_EL1 = 0x8015, + ARM64_SYSREG_DBGBCR3_EL1 = 0x801D, + ARM64_SYSREG_DBGBCR4_EL1 = 0x8025, + ARM64_SYSREG_DBGBCR5_EL1 = 0x802D, + ARM64_SYSREG_DBGBCR6_EL1 = 0x8035, + ARM64_SYSREG_DBGBCR7_EL1 = 0x803D, + ARM64_SYSREG_DBGBCR8_EL1 = 0x8045, + ARM64_SYSREG_DBGBCR9_EL1 = 0x804D, + ARM64_SYSREG_DBGBCR10_EL1 = 0x8055, + ARM64_SYSREG_DBGBCR11_EL1 = 0x805D, + ARM64_SYSREG_DBGBCR12_EL1 = 0x8065, + ARM64_SYSREG_DBGBCR13_EL1 = 0x806D, + ARM64_SYSREG_DBGBCR14_EL1 = 0x8075, + ARM64_SYSREG_DBGBCR15_EL1 = 0x807D, + ARM64_SYSREG_DBGWVR0_EL1 = 0x8006, + ARM64_SYSREG_DBGWVR1_EL1 = 0x800E, + ARM64_SYSREG_DBGWVR2_EL1 = 0x8016, + ARM64_SYSREG_DBGWVR3_EL1 = 0x801E, + ARM64_SYSREG_DBGWVR4_EL1 = 0x8026, + ARM64_SYSREG_DBGWVR5_EL1 = 0x802E, + ARM64_SYSREG_DBGWVR6_EL1 = 0x8036, + ARM64_SYSREG_DBGWVR7_EL1 = 0x803E, + ARM64_SYSREG_DBGWVR8_EL1 = 0x8046, + ARM64_SYSREG_DBGWVR9_EL1 = 0x804E, + ARM64_SYSREG_DBGWVR10_EL1 = 0x8056, + ARM64_SYSREG_DBGWVR11_EL1 = 0x805E, + ARM64_SYSREG_DBGWVR12_EL1 = 0x8066, + ARM64_SYSREG_DBGWVR13_EL1 = 0x806E, + ARM64_SYSREG_DBGWVR14_EL1 = 0x8076, + ARM64_SYSREG_DBGWVR15_EL1 = 0x807E, + ARM64_SYSREG_DBGWCR0_EL1 = 0x8007, + ARM64_SYSREG_DBGWCR1_EL1 = 0x800F, + ARM64_SYSREG_DBGWCR2_EL1 = 0x8017, + ARM64_SYSREG_DBGWCR3_EL1 = 0x801F, + ARM64_SYSREG_DBGWCR4_EL1 = 0x8027, + ARM64_SYSREG_DBGWCR5_EL1 = 0x802F, + ARM64_SYSREG_DBGWCR6_EL1 = 0x8037, + ARM64_SYSREG_DBGWCR7_EL1 = 0x803F, + ARM64_SYSREG_DBGWCR8_EL1 = 0x8047, + ARM64_SYSREG_DBGWCR9_EL1 = 0x804F, + ARM64_SYSREG_DBGWCR10_EL1 = 0x8057, + ARM64_SYSREG_DBGWCR11_EL1 = 0x805F, + ARM64_SYSREG_DBGWCR12_EL1 = 0x8067, + ARM64_SYSREG_DBGWCR13_EL1 = 0x806F, + ARM64_SYSREG_DBGWCR14_EL1 = 0x8077, + ARM64_SYSREG_DBGWCR15_EL1 = 0x807F, + ARM64_SYSREG_TEEHBR32_EL1 = 0x9080, + ARM64_SYSREG_OSDLR_EL1 = 0x809C, + ARM64_SYSREG_DBGPRCR_EL1 = 0x80A4, + ARM64_SYSREG_DBGCLAIMSET_EL1 = 0x83C6, + ARM64_SYSREG_DBGCLAIMCLR_EL1 = 0x83CE, + ARM64_SYSREG_CSSELR_EL1 = 0xD000, + ARM64_SYSREG_VPIDR_EL2 = 0xE000, + ARM64_SYSREG_VMPIDR_EL2 = 0xE005, + ARM64_SYSREG_CPACR_EL1 = 0xC082, + ARM64_SYSREG_SCTLR_EL1 = 0xC080, + ARM64_SYSREG_SCTLR_EL2 = 0xE080, + ARM64_SYSREG_SCTLR_EL3 = 0xF080, + ARM64_SYSREG_ACTLR_EL1 = 0xC081, + ARM64_SYSREG_ACTLR_EL2 = 0xE081, + ARM64_SYSREG_ACTLR_EL3 = 0xF081, + ARM64_SYSREG_HCR_EL2 = 0xE088, + ARM64_SYSREG_SCR_EL3 = 0xF088, + ARM64_SYSREG_MDCR_EL2 = 0xE089, + ARM64_SYSREG_SDER32_EL3 = 0xF089, + ARM64_SYSREG_CPTR_EL2 = 0xE08A, + ARM64_SYSREG_CPTR_EL3 = 0xF08A, + ARM64_SYSREG_HSTR_EL2 = 0xE08B, + ARM64_SYSREG_HACR_EL2 = 0xE08F, + ARM64_SYSREG_MDCR_EL3 = 0xF099, + ARM64_SYSREG_TTBR0_EL1 = 0xC100, + ARM64_SYSREG_TTBR0_EL2 = 0xE100, + ARM64_SYSREG_TTBR0_EL3 = 0xF100, + ARM64_SYSREG_TTBR1_EL1 = 0xC101, + ARM64_SYSREG_TCR_EL1 = 0xC102, + ARM64_SYSREG_TCR_EL2 = 0xE102, + ARM64_SYSREG_TCR_EL3 = 0xF102, + ARM64_SYSREG_VTTBR_EL2 = 0xE108, + ARM64_SYSREG_VTCR_EL2 = 0xE10A, + ARM64_SYSREG_DACR32_EL2 = 0xE180, + ARM64_SYSREG_SPSR_EL1 = 0xC200, + ARM64_SYSREG_SPSR_EL2 = 0xE200, + ARM64_SYSREG_SPSR_EL3 = 0xF200, + ARM64_SYSREG_ELR_EL1 = 0xC201, + ARM64_SYSREG_ELR_EL2 = 0xE201, + ARM64_SYSREG_ELR_EL3 = 0xF201, + ARM64_SYSREG_SP_EL0 = 0xC208, + ARM64_SYSREG_SP_EL1 = 0xE208, + ARM64_SYSREG_SP_EL2 = 0xF208, + ARM64_SYSREG_SPSEL = 0xC210, + ARM64_SYSREG_NZCV = 0xDA10, + ARM64_SYSREG_DAIF = 0xDA11, + ARM64_SYSREG_CURRENTEL = 0xC212, + ARM64_SYSREG_SPSR_IRQ = 0xE218, + ARM64_SYSREG_SPSR_ABT = 0xE219, + ARM64_SYSREG_SPSR_UND = 0xE21A, + ARM64_SYSREG_SPSR_FIQ = 0xE21B, + ARM64_SYSREG_FPCR = 0xDA20, + ARM64_SYSREG_FPSR = 0xDA21, + ARM64_SYSREG_DSPSR_EL0 = 0xDA28, + ARM64_SYSREG_DLR_EL0 = 0xDA29, + ARM64_SYSREG_IFSR32_EL2 = 0xE281, + ARM64_SYSREG_AFSR0_EL1 = 0xC288, + ARM64_SYSREG_AFSR0_EL2 = 0xE288, + ARM64_SYSREG_AFSR0_EL3 = 0xF288, + ARM64_SYSREG_AFSR1_EL1 = 0xC289, + ARM64_SYSREG_AFSR1_EL2 = 0xE289, + ARM64_SYSREG_AFSR1_EL3 = 0xF289, + ARM64_SYSREG_ESR_EL1 = 0xC290, + ARM64_SYSREG_ESR_EL2 = 0xE290, + ARM64_SYSREG_ESR_EL3 = 0xF290, + ARM64_SYSREG_FPEXC32_EL2 = 0xE298, + ARM64_SYSREG_FAR_EL1 = 0xC300, + ARM64_SYSREG_FAR_EL2 = 0xE300, + ARM64_SYSREG_FAR_EL3 = 0xF300, + ARM64_SYSREG_HPFAR_EL2 = 0xE304, + ARM64_SYSREG_PAR_EL1 = 0xC3A0, + ARM64_SYSREG_PMCR_EL0 = 0xDCE0, + ARM64_SYSREG_PMCNTENSET_EL0 = 0xDCE1, + ARM64_SYSREG_PMCNTENCLR_EL0 = 0xDCE2, + ARM64_SYSREG_PMOVSCLR_EL0 = 0xDCE3, + ARM64_SYSREG_PMSELR_EL0 = 0xDCE5, + ARM64_SYSREG_PMCCNTR_EL0 = 0xDCE8, + ARM64_SYSREG_PMXEVTYPER_EL0 = 0xDCE9, + ARM64_SYSREG_PMXEVCNTR_EL0 = 0xDCEA, + ARM64_SYSREG_PMUSERENR_EL0 = 0xDCF0, + ARM64_SYSREG_PMINTENSET_EL1 = 0xC4F1, + ARM64_SYSREG_PMINTENCLR_EL1 = 0xC4F2, + ARM64_SYSREG_PMOVSSET_EL0 = 0xDCF3, + ARM64_SYSREG_MAIR_EL1 = 0xC510, + ARM64_SYSREG_MAIR_EL2 = 0xE510, + ARM64_SYSREG_MAIR_EL3 = 0xF510, + ARM64_SYSREG_AMAIR_EL1 = 0xC518, + ARM64_SYSREG_AMAIR_EL2 = 0xE518, + ARM64_SYSREG_AMAIR_EL3 = 0xF518, + ARM64_SYSREG_VBAR_EL1 = 0xC600, + ARM64_SYSREG_VBAR_EL2 = 0xE600, + ARM64_SYSREG_VBAR_EL3 = 0xF600, + ARM64_SYSREG_RMR_EL1 = 0xC602, + ARM64_SYSREG_RMR_EL2 = 0xE602, + ARM64_SYSREG_RMR_EL3 = 0xF602, + ARM64_SYSREG_CONTEXTIDR_EL1 = 0xC681, + ARM64_SYSREG_TPIDR_EL0 = 0xDE82, + ARM64_SYSREG_TPIDR_EL2 = 0xE682, + ARM64_SYSREG_TPIDR_EL3 = 0xF682, + ARM64_SYSREG_TPIDRRO_EL0 = 0xDE83, + ARM64_SYSREG_TPIDR_EL1 = 0xC684, + ARM64_SYSREG_CNTFRQ_EL0 = 0xDF00, + ARM64_SYSREG_CNTVOFF_EL2 = 0xE703, + ARM64_SYSREG_CNTKCTL_EL1 = 0xC708, + ARM64_SYSREG_CNTHCTL_EL2 = 0xE708, + ARM64_SYSREG_CNTP_TVAL_EL0 = 0xDF10, + ARM64_SYSREG_CNTHP_TVAL_EL2 = 0xE710, + ARM64_SYSREG_CNTPS_TVAL_EL1 = 0xFF10, + ARM64_SYSREG_CNTP_CTL_EL0 = 0xDF11, + ARM64_SYSREG_CNTHP_CTL_EL2 = 0xE711, + ARM64_SYSREG_CNTPS_CTL_EL1 = 0xFF11, + ARM64_SYSREG_CNTP_CVAL_EL0 = 0xDF12, + ARM64_SYSREG_CNTHP_CVAL_EL2 = 0xE712, + ARM64_SYSREG_CNTPS_CVAL_EL1 = 0xFF12, + ARM64_SYSREG_CNTV_TVAL_EL0 = 0xDF18, + ARM64_SYSREG_CNTV_CTL_EL0 = 0xDF19, + ARM64_SYSREG_CNTV_CVAL_EL0 = 0xDF1A, + ARM64_SYSREG_PMEVCNTR0_EL0 = 0xDF40, + ARM64_SYSREG_PMEVCNTR1_EL0 = 0xDF41, + ARM64_SYSREG_PMEVCNTR2_EL0 = 0xDF42, + ARM64_SYSREG_PMEVCNTR3_EL0 = 0xDF43, + ARM64_SYSREG_PMEVCNTR4_EL0 = 0xDF44, + ARM64_SYSREG_PMEVCNTR5_EL0 = 0xDF45, + ARM64_SYSREG_PMEVCNTR6_EL0 = 0xDF46, + ARM64_SYSREG_PMEVCNTR7_EL0 = 0xDF47, + ARM64_SYSREG_PMEVCNTR8_EL0 = 0xDF48, + ARM64_SYSREG_PMEVCNTR9_EL0 = 0xDF49, + ARM64_SYSREG_PMEVCNTR10_EL0 = 0xDF4A, + ARM64_SYSREG_PMEVCNTR11_EL0 = 0xDF4B, + ARM64_SYSREG_PMEVCNTR12_EL0 = 0xDF4C, + ARM64_SYSREG_PMEVCNTR13_EL0 = 0xDF4D, + ARM64_SYSREG_PMEVCNTR14_EL0 = 0xDF4E, + ARM64_SYSREG_PMEVCNTR15_EL0 = 0xDF4F, + ARM64_SYSREG_PMEVCNTR16_EL0 = 0xDF50, + ARM64_SYSREG_PMEVCNTR17_EL0 = 0xDF51, + ARM64_SYSREG_PMEVCNTR18_EL0 = 0xDF52, + ARM64_SYSREG_PMEVCNTR19_EL0 = 0xDF53, + ARM64_SYSREG_PMEVCNTR20_EL0 = 0xDF54, + ARM64_SYSREG_PMEVCNTR21_EL0 = 0xDF55, + ARM64_SYSREG_PMEVCNTR22_EL0 = 0xDF56, + ARM64_SYSREG_PMEVCNTR23_EL0 = 0xDF57, + ARM64_SYSREG_PMEVCNTR24_EL0 = 0xDF58, + ARM64_SYSREG_PMEVCNTR25_EL0 = 0xDF59, + ARM64_SYSREG_PMEVCNTR26_EL0 = 0xDF5A, + ARM64_SYSREG_PMEVCNTR27_EL0 = 0xDF5B, + ARM64_SYSREG_PMEVCNTR28_EL0 = 0xDF5C, + ARM64_SYSREG_PMEVCNTR29_EL0 = 0xDF5D, + ARM64_SYSREG_PMEVCNTR30_EL0 = 0xDF5E, + ARM64_SYSREG_PMCCFILTR_EL0 = 0xDF7F, + ARM64_SYSREG_PMEVTYPER0_EL0 = 0xDF60, + ARM64_SYSREG_PMEVTYPER1_EL0 = 0xDF61, + ARM64_SYSREG_PMEVTYPER2_EL0 = 0xDF62, + ARM64_SYSREG_PMEVTYPER3_EL0 = 0xDF63, + ARM64_SYSREG_PMEVTYPER4_EL0 = 0xDF64, + ARM64_SYSREG_PMEVTYPER5_EL0 = 0xDF65, + ARM64_SYSREG_PMEVTYPER6_EL0 = 0xDF66, + ARM64_SYSREG_PMEVTYPER7_EL0 = 0xDF67, + ARM64_SYSREG_PMEVTYPER8_EL0 = 0xDF68, + ARM64_SYSREG_PMEVTYPER9_EL0 = 0xDF69, + ARM64_SYSREG_PMEVTYPER10_EL0 = 0xDF6A, + ARM64_SYSREG_PMEVTYPER11_EL0 = 0xDF6B, + ARM64_SYSREG_PMEVTYPER12_EL0 = 0xDF6C, + ARM64_SYSREG_PMEVTYPER13_EL0 = 0xDF6D, + ARM64_SYSREG_PMEVTYPER14_EL0 = 0xDF6E, + ARM64_SYSREG_PMEVTYPER15_EL0 = 0xDF6F, + ARM64_SYSREG_PMEVTYPER16_EL0 = 0xDF70, + ARM64_SYSREG_PMEVTYPER17_EL0 = 0xDF71, + ARM64_SYSREG_PMEVTYPER18_EL0 = 0xDF72, + ARM64_SYSREG_PMEVTYPER19_EL0 = 0xDF73, + ARM64_SYSREG_PMEVTYPER20_EL0 = 0xDF74, + ARM64_SYSREG_PMEVTYPER21_EL0 = 0xDF75, + ARM64_SYSREG_PMEVTYPER22_EL0 = 0xDF76, + ARM64_SYSREG_PMEVTYPER23_EL0 = 0xDF77, + ARM64_SYSREG_PMEVTYPER24_EL0 = 0xDF78, + ARM64_SYSREG_PMEVTYPER25_EL0 = 0xDF79, + ARM64_SYSREG_PMEVTYPER26_EL0 = 0xDF7A, + ARM64_SYSREG_PMEVTYPER27_EL0 = 0xDF7B, + ARM64_SYSREG_PMEVTYPER28_EL0 = 0xDF7C, + ARM64_SYSREG_PMEVTYPER29_EL0 = 0xDF7D, + ARM64_SYSREG_PMEVTYPER30_EL0 = 0xDF7E, + ARM64_SYSREG_TRCPRGCTLR = 0x8808, + ARM64_SYSREG_TRCPROCSELR = 0x8810, + ARM64_SYSREG_TRCCONFIGR = 0x8820, + ARM64_SYSREG_TRCAUXCTLR = 0x8830, + ARM64_SYSREG_TRCEVENTCTL0R = 0x8840, + ARM64_SYSREG_TRCEVENTCTL1R = 0x8848, + ARM64_SYSREG_TRCSTALLCTLR = 0x8858, + ARM64_SYSREG_TRCTSCTLR = 0x8860, + ARM64_SYSREG_TRCSYNCPR = 0x8868, + ARM64_SYSREG_TRCCCCTLR = 0x8870, + ARM64_SYSREG_TRCBBCTLR = 0x8878, + ARM64_SYSREG_TRCTRACEIDR = 0x8801, + ARM64_SYSREG_TRCQCTLR = 0x8809, + ARM64_SYSREG_TRCVICTLR = 0x8802, + ARM64_SYSREG_TRCVIIECTLR = 0x880A, + ARM64_SYSREG_TRCVISSCTLR = 0x8812, + ARM64_SYSREG_TRCVIPCSSCTLR = 0x881A, + ARM64_SYSREG_TRCVDCTLR = 0x8842, + ARM64_SYSREG_TRCVDSACCTLR = 0x884A, + ARM64_SYSREG_TRCVDARCCTLR = 0x8852, + ARM64_SYSREG_TRCSEQEVR0 = 0x8804, + ARM64_SYSREG_TRCSEQEVR1 = 0x880C, + ARM64_SYSREG_TRCSEQEVR2 = 0x8814, + ARM64_SYSREG_TRCSEQRSTEVR = 0x8834, + ARM64_SYSREG_TRCSEQSTR = 0x883C, + ARM64_SYSREG_TRCEXTINSELR = 0x8844, + ARM64_SYSREG_TRCCNTRLDVR0 = 0x8805, + ARM64_SYSREG_TRCCNTRLDVR1 = 0x880D, + ARM64_SYSREG_TRCCNTRLDVR2 = 0x8815, + ARM64_SYSREG_TRCCNTRLDVR3 = 0x881D, + ARM64_SYSREG_TRCCNTCTLR0 = 0x8825, + ARM64_SYSREG_TRCCNTCTLR1 = 0x882D, + ARM64_SYSREG_TRCCNTCTLR2 = 0x8835, + ARM64_SYSREG_TRCCNTCTLR3 = 0x883D, + ARM64_SYSREG_TRCCNTVR0 = 0x8845, + ARM64_SYSREG_TRCCNTVR1 = 0x884D, + ARM64_SYSREG_TRCCNTVR2 = 0x8855, + ARM64_SYSREG_TRCCNTVR3 = 0x885D, + ARM64_SYSREG_TRCIMSPEC0 = 0x8807, + ARM64_SYSREG_TRCIMSPEC1 = 0x880F, + ARM64_SYSREG_TRCIMSPEC2 = 0x8817, + ARM64_SYSREG_TRCIMSPEC3 = 0x881F, + ARM64_SYSREG_TRCIMSPEC4 = 0x8827, + ARM64_SYSREG_TRCIMSPEC5 = 0x882F, + ARM64_SYSREG_TRCIMSPEC6 = 0x8837, + ARM64_SYSREG_TRCIMSPEC7 = 0x883F, + ARM64_SYSREG_TRCRSCTLR2 = 0x8890, + ARM64_SYSREG_TRCRSCTLR3 = 0x8898, + ARM64_SYSREG_TRCRSCTLR4 = 0x88A0, + ARM64_SYSREG_TRCRSCTLR5 = 0x88A8, + ARM64_SYSREG_TRCRSCTLR6 = 0x88B0, + ARM64_SYSREG_TRCRSCTLR7 = 0x88B8, + ARM64_SYSREG_TRCRSCTLR8 = 0x88C0, + ARM64_SYSREG_TRCRSCTLR9 = 0x88C8, + ARM64_SYSREG_TRCRSCTLR10 = 0x88D0, + ARM64_SYSREG_TRCRSCTLR11 = 0x88D8, + ARM64_SYSREG_TRCRSCTLR12 = 0x88E0, + ARM64_SYSREG_TRCRSCTLR13 = 0x88E8, + ARM64_SYSREG_TRCRSCTLR14 = 0x88F0, + ARM64_SYSREG_TRCRSCTLR15 = 0x88F8, + ARM64_SYSREG_TRCRSCTLR16 = 0x8881, + ARM64_SYSREG_TRCRSCTLR17 = 0x8889, + ARM64_SYSREG_TRCRSCTLR18 = 0x8891, + ARM64_SYSREG_TRCRSCTLR19 = 0x8899, + ARM64_SYSREG_TRCRSCTLR20 = 0x88A1, + ARM64_SYSREG_TRCRSCTLR21 = 0x88A9, + ARM64_SYSREG_TRCRSCTLR22 = 0x88B1, + ARM64_SYSREG_TRCRSCTLR23 = 0x88B9, + ARM64_SYSREG_TRCRSCTLR24 = 0x88C1, + ARM64_SYSREG_TRCRSCTLR25 = 0x88C9, + ARM64_SYSREG_TRCRSCTLR26 = 0x88D1, + ARM64_SYSREG_TRCRSCTLR27 = 0x88D9, + ARM64_SYSREG_TRCRSCTLR28 = 0x88E1, + ARM64_SYSREG_TRCRSCTLR29 = 0x88E9, + ARM64_SYSREG_TRCRSCTLR30 = 0x88F1, + ARM64_SYSREG_TRCRSCTLR31 = 0x88F9, + ARM64_SYSREG_TRCSSCCR0 = 0x8882, + ARM64_SYSREG_TRCSSCCR1 = 0x888A, + ARM64_SYSREG_TRCSSCCR2 = 0x8892, + ARM64_SYSREG_TRCSSCCR3 = 0x889A, + ARM64_SYSREG_TRCSSCCR4 = 0x88A2, + ARM64_SYSREG_TRCSSCCR5 = 0x88AA, + ARM64_SYSREG_TRCSSCCR6 = 0x88B2, + ARM64_SYSREG_TRCSSCCR7 = 0x88BA, + ARM64_SYSREG_TRCSSCSR0 = 0x88C2, + ARM64_SYSREG_TRCSSCSR1 = 0x88CA, + ARM64_SYSREG_TRCSSCSR2 = 0x88D2, + ARM64_SYSREG_TRCSSCSR3 = 0x88DA, + ARM64_SYSREG_TRCSSCSR4 = 0x88E2, + ARM64_SYSREG_TRCSSCSR5 = 0x88EA, + ARM64_SYSREG_TRCSSCSR6 = 0x88F2, + ARM64_SYSREG_TRCSSCSR7 = 0x88FA, + ARM64_SYSREG_TRCSSPCICR0 = 0x8883, + ARM64_SYSREG_TRCSSPCICR1 = 0x888B, + ARM64_SYSREG_TRCSSPCICR2 = 0x8893, + ARM64_SYSREG_TRCSSPCICR3 = 0x889B, + ARM64_SYSREG_TRCSSPCICR4 = 0x88A3, + ARM64_SYSREG_TRCSSPCICR5 = 0x88AB, + ARM64_SYSREG_TRCSSPCICR6 = 0x88B3, + ARM64_SYSREG_TRCSSPCICR7 = 0x88BB, + ARM64_SYSREG_TRCPDCR = 0x88A4, + ARM64_SYSREG_TRCACVR0 = 0x8900, + ARM64_SYSREG_TRCACVR1 = 0x8910, + ARM64_SYSREG_TRCACVR2 = 0x8920, + ARM64_SYSREG_TRCACVR3 = 0x8930, + ARM64_SYSREG_TRCACVR4 = 0x8940, + ARM64_SYSREG_TRCACVR5 = 0x8950, + ARM64_SYSREG_TRCACVR6 = 0x8960, + ARM64_SYSREG_TRCACVR7 = 0x8970, + ARM64_SYSREG_TRCACVR8 = 0x8901, + ARM64_SYSREG_TRCACVR9 = 0x8911, + ARM64_SYSREG_TRCACVR10 = 0x8921, + ARM64_SYSREG_TRCACVR11 = 0x8931, + ARM64_SYSREG_TRCACVR12 = 0x8941, + ARM64_SYSREG_TRCACVR13 = 0x8951, + ARM64_SYSREG_TRCACVR14 = 0x8961, + ARM64_SYSREG_TRCACVR15 = 0x8971, + ARM64_SYSREG_TRCACATR0 = 0x8902, + ARM64_SYSREG_TRCACATR1 = 0x8912, + ARM64_SYSREG_TRCACATR2 = 0x8922, + ARM64_SYSREG_TRCACATR3 = 0x8932, + ARM64_SYSREG_TRCACATR4 = 0x8942, + ARM64_SYSREG_TRCACATR5 = 0x8952, + ARM64_SYSREG_TRCACATR6 = 0x8962, + ARM64_SYSREG_TRCACATR7 = 0x8972, + ARM64_SYSREG_TRCACATR8 = 0x8903, + ARM64_SYSREG_TRCACATR9 = 0x8913, + ARM64_SYSREG_TRCACATR10 = 0x8923, + ARM64_SYSREG_TRCACATR11 = 0x8933, + ARM64_SYSREG_TRCACATR12 = 0x8943, + ARM64_SYSREG_TRCACATR13 = 0x8953, + ARM64_SYSREG_TRCACATR14 = 0x8963, + ARM64_SYSREG_TRCACATR15 = 0x8973, + ARM64_SYSREG_TRCDVCVR0 = 0x8904, + ARM64_SYSREG_TRCDVCVR1 = 0x8924, + ARM64_SYSREG_TRCDVCVR2 = 0x8944, + ARM64_SYSREG_TRCDVCVR3 = 0x8964, + ARM64_SYSREG_TRCDVCVR4 = 0x8905, + ARM64_SYSREG_TRCDVCVR5 = 0x8925, + ARM64_SYSREG_TRCDVCVR6 = 0x8945, + ARM64_SYSREG_TRCDVCVR7 = 0x8965, + ARM64_SYSREG_TRCDVCMR0 = 0x8906, + ARM64_SYSREG_TRCDVCMR1 = 0x8926, + ARM64_SYSREG_TRCDVCMR2 = 0x8946, + ARM64_SYSREG_TRCDVCMR3 = 0x8966, + ARM64_SYSREG_TRCDVCMR4 = 0x8907, + ARM64_SYSREG_TRCDVCMR5 = 0x8927, + ARM64_SYSREG_TRCDVCMR6 = 0x8947, + ARM64_SYSREG_TRCDVCMR7 = 0x8967, + ARM64_SYSREG_TRCCIDCVR0 = 0x8980, + ARM64_SYSREG_TRCCIDCVR1 = 0x8990, + ARM64_SYSREG_TRCCIDCVR2 = 0x89A0, + ARM64_SYSREG_TRCCIDCVR3 = 0x89B0, + ARM64_SYSREG_TRCCIDCVR4 = 0x89C0, + ARM64_SYSREG_TRCCIDCVR5 = 0x89D0, + ARM64_SYSREG_TRCCIDCVR6 = 0x89E0, + ARM64_SYSREG_TRCCIDCVR7 = 0x89F0, + ARM64_SYSREG_TRCVMIDCVR0 = 0x8981, + ARM64_SYSREG_TRCVMIDCVR1 = 0x8991, + ARM64_SYSREG_TRCVMIDCVR2 = 0x89A1, + ARM64_SYSREG_TRCVMIDCVR3 = 0x89B1, + ARM64_SYSREG_TRCVMIDCVR4 = 0x89C1, + ARM64_SYSREG_TRCVMIDCVR5 = 0x89D1, + ARM64_SYSREG_TRCVMIDCVR6 = 0x89E1, + ARM64_SYSREG_TRCVMIDCVR7 = 0x89F1, + ARM64_SYSREG_TRCCIDCCTLR0 = 0x8982, + ARM64_SYSREG_TRCCIDCCTLR1 = 0x898A, + ARM64_SYSREG_TRCVMIDCCTLR0 = 0x8992, + ARM64_SYSREG_TRCVMIDCCTLR1 = 0x899A, + ARM64_SYSREG_TRCITCTRL = 0x8B84, + ARM64_SYSREG_TRCCLAIMSET = 0x8BC6, + ARM64_SYSREG_TRCCLAIMCLR = 0x8BCE, + ARM64_SYSREG_ICC_BPR1_EL1 = 0xC663, + ARM64_SYSREG_ICC_BPR0_EL1 = 0xC643, + ARM64_SYSREG_ICC_PMR_EL1 = 0xC230, + ARM64_SYSREG_ICC_CTLR_EL1 = 0xC664, + ARM64_SYSREG_ICC_CTLR_EL3 = 0xF664, + ARM64_SYSREG_ICC_SRE_EL1 = 0xC665, + ARM64_SYSREG_ICC_SRE_EL2 = 0xE64D, + ARM64_SYSREG_ICC_SRE_EL3 = 0xF665, + ARM64_SYSREG_ICC_IGRPEN0_EL1 = 0xC666, + ARM64_SYSREG_ICC_IGRPEN1_EL1 = 0xC667, + ARM64_SYSREG_ICC_IGRPEN1_EL3 = 0xF667, + ARM64_SYSREG_ICC_SEIEN_EL1 = 0xC668, + ARM64_SYSREG_ICC_AP0R0_EL1 = 0xC644, + ARM64_SYSREG_ICC_AP0R1_EL1 = 0xC645, + ARM64_SYSREG_ICC_AP0R2_EL1 = 0xC646, + ARM64_SYSREG_ICC_AP0R3_EL1 = 0xC647, + ARM64_SYSREG_ICC_AP1R0_EL1 = 0xC648, + ARM64_SYSREG_ICC_AP1R1_EL1 = 0xC649, + ARM64_SYSREG_ICC_AP1R2_EL1 = 0xC64A, + ARM64_SYSREG_ICC_AP1R3_EL1 = 0xC64B, + ARM64_SYSREG_ICH_AP0R0_EL2 = 0xE640, + ARM64_SYSREG_ICH_AP0R1_EL2 = 0xE641, + ARM64_SYSREG_ICH_AP0R2_EL2 = 0xE642, + ARM64_SYSREG_ICH_AP0R3_EL2 = 0xE643, + ARM64_SYSREG_ICH_AP1R0_EL2 = 0xE648, + ARM64_SYSREG_ICH_AP1R1_EL2 = 0xE649, + ARM64_SYSREG_ICH_AP1R2_EL2 = 0xE64A, + ARM64_SYSREG_ICH_AP1R3_EL2 = 0xE64B, + ARM64_SYSREG_ICH_HCR_EL2 = 0xE658, + ARM64_SYSREG_ICH_MISR_EL2 = 0xE65A, + ARM64_SYSREG_ICH_VMCR_EL2 = 0xE65F, + ARM64_SYSREG_ICH_VSEIR_EL2 = 0xE64C, + ARM64_SYSREG_ICH_LR0_EL2 = 0xE660, + ARM64_SYSREG_ICH_LR1_EL2 = 0xE661, + ARM64_SYSREG_ICH_LR2_EL2 = 0xE662, + ARM64_SYSREG_ICH_LR3_EL2 = 0xE663, + ARM64_SYSREG_ICH_LR4_EL2 = 0xE664, + ARM64_SYSREG_ICH_LR5_EL2 = 0xE665, + ARM64_SYSREG_ICH_LR6_EL2 = 0xE666, + ARM64_SYSREG_ICH_LR7_EL2 = 0xE667, + ARM64_SYSREG_ICH_LR8_EL2 = 0xE668, + ARM64_SYSREG_ICH_LR9_EL2 = 0xE669, + ARM64_SYSREG_ICH_LR10_EL2 = 0xE66A, + ARM64_SYSREG_ICH_LR11_EL2 = 0xE66B, + ARM64_SYSREG_ICH_LR12_EL2 = 0xE66C, + ARM64_SYSREG_ICH_LR13_EL2 = 0xE66D, + ARM64_SYSREG_ICH_LR14_EL2 = 0xE66E, + ARM64_SYSREG_ICH_LR15_EL2 = 0xE66F, + ARM64_SYSREG_PAN = 0xC213, + ARM64_SYSREG_LORSA_EL1 = 0xC520, + ARM64_SYSREG_LOREA_EL1 = 0xC521, + ARM64_SYSREG_LORN_EL1 = 0xC522, + ARM64_SYSREG_LORC_EL1 = 0xC523, + ARM64_SYSREG_TTBR1_EL2 = 0xE101, + ARM64_SYSREG_CONTEXTIDR_EL2 = 0xE681, + ARM64_SYSREG_CNTHV_TVAL_EL2 = 0xE718, + ARM64_SYSREG_CNTHV_CVAL_EL2 = 0xE71A, + ARM64_SYSREG_CNTHV_CTL_EL2 = 0xE719, + ARM64_SYSREG_SCTLR_EL12 = 0xE880, + ARM64_SYSREG_CPACR_EL12 = 0xE882, + ARM64_SYSREG_TTBR0_EL12 = 0xE900, + ARM64_SYSREG_TTBR1_EL12 = 0xE901, + ARM64_SYSREG_TCR_EL12 = 0xE902, + ARM64_SYSREG_AFSR0_EL12 = 0xEA88, + ARM64_SYSREG_AFSR1_EL12 = 0xEA89, + ARM64_SYSREG_ESR_EL12 = 0xEA90, + ARM64_SYSREG_FAR_EL12 = 0xEB00, + ARM64_SYSREG_MAIR_EL12 = 0xED10, + ARM64_SYSREG_AMAIR_EL12 = 0xED18, + ARM64_SYSREG_VBAR_EL12 = 0xEE00, + ARM64_SYSREG_CONTEXTIDR_EL12 = 0xEE81, + ARM64_SYSREG_CNTKCTL_EL12 = 0xEF08, + ARM64_SYSREG_CNTP_TVAL_EL02 = 0xEF10, + ARM64_SYSREG_CNTP_CTL_EL02 = 0xEF11, + ARM64_SYSREG_CNTP_CVAL_EL02 = 0xEF12, + ARM64_SYSREG_CNTV_TVAL_EL02 = 0xEF18, + ARM64_SYSREG_CNTV_CTL_EL02 = 0xEF19, + ARM64_SYSREG_CNTV_CVAL_EL02 = 0xEF1A, + ARM64_SYSREG_SPSR_EL12 = 0xEA00, + ARM64_SYSREG_ELR_EL12 = 0xEA01, + ARM64_SYSREG_UAO = 0xC214, + ARM64_SYSREG_PMBLIMITR_EL1 = 0xC4D0, + ARM64_SYSREG_PMBPTR_EL1 = 0xC4D1, + ARM64_SYSREG_PMBSR_EL1 = 0xC4D3, + ARM64_SYSREG_PMBIDR_EL1 = 0xC4D7, + ARM64_SYSREG_PMSCR_EL2 = 0xE4C8, + ARM64_SYSREG_PMSCR_EL12 = 0xECC8, + ARM64_SYSREG_PMSCR_EL1 = 0xC4C8, + ARM64_SYSREG_PMSICR_EL1 = 0xC4CA, + ARM64_SYSREG_PMSIRR_EL1 = 0xC4CB, + ARM64_SYSREG_PMSFCR_EL1 = 0xC4CC, + ARM64_SYSREG_PMSEVFR_EL1 = 0xC4CD, + ARM64_SYSREG_PMSLATFR_EL1 = 0xC4CE, + ARM64_SYSREG_PMSIDR_EL1 = 0xC4CF, + ARM64_SYSREG_ERRSELR_EL1 = 0xC299, + ARM64_SYSREG_ERXCTLR_EL1 = 0xC2A1, + ARM64_SYSREG_ERXSTATUS_EL1 = 0xC2A2, + ARM64_SYSREG_ERXADDR_EL1 = 0xC2A3, + ARM64_SYSREG_ERXMISC0_EL1 = 0xC2A8, + ARM64_SYSREG_ERXMISC1_EL1 = 0xC2A9, + ARM64_SYSREG_DISR_EL1 = 0xC609, + ARM64_SYSREG_VDISR_EL2 = 0xE609, + ARM64_SYSREG_VSESR_EL2 = 0xE293, + ARM64_SYSREG_APIAKEYLO_EL1 = 0xC108, + ARM64_SYSREG_APIAKEYHI_EL1 = 0xC109, + ARM64_SYSREG_APIBKEYLO_EL1 = 0xC10A, + ARM64_SYSREG_APIBKEYHI_EL1 = 0xC10B, + ARM64_SYSREG_APDAKEYLO_EL1 = 0xC110, + ARM64_SYSREG_APDAKEYHI_EL1 = 0xC111, + ARM64_SYSREG_APDBKEYLO_EL1 = 0xC112, + ARM64_SYSREG_APDBKEYHI_EL1 = 0xC113, + ARM64_SYSREG_APGAKEYLO_EL1 = 0xC118, + ARM64_SYSREG_APGAKEYHI_EL1 = 0xC119, + ARM64_SYSREG_VSTCR_EL2 = 0xE132, + ARM64_SYSREG_VSTTBR_EL2 = 0xE130, + ARM64_SYSREG_CNTHVS_TVAL_EL2 = 0xE720, + ARM64_SYSREG_CNTHVS_CVAL_EL2 = 0xE722, + ARM64_SYSREG_CNTHVS_CTL_EL2 = 0xE721, + ARM64_SYSREG_CNTHPS_TVAL_EL2 = 0xE728, + ARM64_SYSREG_CNTHPS_CVAL_EL2 = 0xE72A, + ARM64_SYSREG_CNTHPS_CTL_EL2 = 0xE729, + ARM64_SYSREG_SDER32_EL2 = 0xE099, + ARM64_SYSREG_ERXPFGCTL_EL1 = 0xC2A5, + ARM64_SYSREG_ERXPFGCDN_EL1 = 0xC2A6, + ARM64_SYSREG_ERXTS_EL1 = 0xC2AF, + ARM64_SYSREG_ERXMISC2_EL1 = 0xC2AA, + ARM64_SYSREG_ERXMISC3_EL1 = 0xC2AB, + ARM64_SYSREG_ERXPFGF_EL1 = 0xC2A4, + ARM64_SYSREG_MPAM0_EL1 = 0xC529, + ARM64_SYSREG_MPAM1_EL1 = 0xC528, + ARM64_SYSREG_MPAM2_EL2 = 0xE528, + ARM64_SYSREG_MPAM3_EL3 = 0xF528, + ARM64_SYSREG_MPAM1_EL12 = 0xED28, + ARM64_SYSREG_MPAMHCR_EL2 = 0xE520, + ARM64_SYSREG_MPAMVPMV_EL2 = 0xE521, + ARM64_SYSREG_MPAMVPM0_EL2 = 0xE530, + ARM64_SYSREG_MPAMVPM1_EL2 = 0xE531, + ARM64_SYSREG_MPAMVPM2_EL2 = 0xE532, + ARM64_SYSREG_MPAMVPM3_EL2 = 0xE533, + ARM64_SYSREG_MPAMVPM4_EL2 = 0xE534, + ARM64_SYSREG_MPAMVPM5_EL2 = 0xE535, + ARM64_SYSREG_MPAMVPM6_EL2 = 0xE536, + ARM64_SYSREG_MPAMVPM7_EL2 = 0xE537, + ARM64_SYSREG_MPAMIDR_EL1 = 0xC524, + ARM64_SYSREG_AMCR_EL0 = 0xDE90, + ARM64_SYSREG_AMCFGR_EL0 = 0xDE91, + ARM64_SYSREG_AMCGCR_EL0 = 0xDE92, + ARM64_SYSREG_AMUSERENR_EL0 = 0xDE93, + ARM64_SYSREG_AMCNTENCLR0_EL0 = 0xDE94, + ARM64_SYSREG_AMCNTENSET0_EL0 = 0xDE95, + ARM64_SYSREG_AMEVCNTR00_EL0 = 0xDEA0, + ARM64_SYSREG_AMEVCNTR01_EL0 = 0xDEA1, + ARM64_SYSREG_AMEVCNTR02_EL0 = 0xDEA2, + ARM64_SYSREG_AMEVCNTR03_EL0 = 0xDEA3, + ARM64_SYSREG_AMEVTYPER00_EL0 = 0xDEB0, + ARM64_SYSREG_AMEVTYPER01_EL0 = 0xDEB1, + ARM64_SYSREG_AMEVTYPER02_EL0 = 0xDEB2, + ARM64_SYSREG_AMEVTYPER03_EL0 = 0xDEB3, + ARM64_SYSREG_AMCNTENCLR1_EL0 = 0xDE98, + ARM64_SYSREG_AMCNTENSET1_EL0 = 0xDE99, + ARM64_SYSREG_AMEVCNTR10_EL0 = 0xDEE0, + ARM64_SYSREG_AMEVCNTR11_EL0 = 0xDEE1, + ARM64_SYSREG_AMEVCNTR12_EL0 = 0xDEE2, + ARM64_SYSREG_AMEVCNTR13_EL0 = 0xDEE3, + ARM64_SYSREG_AMEVCNTR14_EL0 = 0xDEE4, + ARM64_SYSREG_AMEVCNTR15_EL0 = 0xDEE5, + ARM64_SYSREG_AMEVCNTR16_EL0 = 0xDEE6, + ARM64_SYSREG_AMEVCNTR17_EL0 = 0xDEE7, + ARM64_SYSREG_AMEVCNTR18_EL0 = 0xDEE8, + ARM64_SYSREG_AMEVCNTR19_EL0 = 0xDEE9, + ARM64_SYSREG_AMEVCNTR110_EL0 = 0xDEEA, + ARM64_SYSREG_AMEVCNTR111_EL0 = 0xDEEB, + ARM64_SYSREG_AMEVCNTR112_EL0 = 0xDEEC, + ARM64_SYSREG_AMEVCNTR113_EL0 = 0xDEED, + ARM64_SYSREG_AMEVCNTR114_EL0 = 0xDEEE, + ARM64_SYSREG_AMEVCNTR115_EL0 = 0xDEEF, + ARM64_SYSREG_AMEVTYPER10_EL0 = 0xDEF0, + ARM64_SYSREG_AMEVTYPER11_EL0 = 0xDEF1, + ARM64_SYSREG_AMEVTYPER12_EL0 = 0xDEF2, + ARM64_SYSREG_AMEVTYPER13_EL0 = 0xDEF3, + ARM64_SYSREG_AMEVTYPER14_EL0 = 0xDEF4, + ARM64_SYSREG_AMEVTYPER15_EL0 = 0xDEF5, + ARM64_SYSREG_AMEVTYPER16_EL0 = 0xDEF6, + ARM64_SYSREG_AMEVTYPER17_EL0 = 0xDEF7, + ARM64_SYSREG_AMEVTYPER18_EL0 = 0xDEF8, + ARM64_SYSREG_AMEVTYPER19_EL0 = 0xDEF9, + ARM64_SYSREG_AMEVTYPER110_EL0 = 0xDEFA, + ARM64_SYSREG_AMEVTYPER111_EL0 = 0xDEFB, + ARM64_SYSREG_AMEVTYPER112_EL0 = 0xDEFC, + ARM64_SYSREG_AMEVTYPER113_EL0 = 0xDEFD, + ARM64_SYSREG_AMEVTYPER114_EL0 = 0xDEFE, + ARM64_SYSREG_AMEVTYPER115_EL0 = 0xDEFF, + ARM64_SYSREG_TRFCR_EL1 = 0xC091, + ARM64_SYSREG_TRFCR_EL2 = 0xE091, + ARM64_SYSREG_TRFCR_EL12 = 0xE891, + ARM64_SYSREG_DIT = 0xDA15, + ARM64_SYSREG_VNCR_EL2 = 0xE110, + ARM64_SYSREG_ZCR_EL1 = 0xC090, + ARM64_SYSREG_ZCR_EL2 = 0xE090, + ARM64_SYSREG_ZCR_EL3 = 0xF090, + ARM64_SYSREG_ZCR_EL12 = 0xE890, + ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90, } arm64_sysreg; +#if 0 typedef enum arm64_msr_reg { // System registers for MSR ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 @@ -180,38 +822,38 @@ typedef enum arm64_msr_reg { ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111 } arm64_msr_reg; +#endif /// System PState Field (MSR instruction) typedef enum arm64_pstate { ARM64_PSTATE_INVALID = 0, ARM64_PSTATE_SPSEL = 0x05, ARM64_PSTATE_DAIFSET = 0x1e, - ARM64_PSTATE_DAIFCLR = 0x1f + ARM64_PSTATE_DAIFCLR = 0x1f, + ARM64_PSTATE_PAN = 0x4, + ARM64_PSTATE_UAO = 0x3, + ARM64_PSTATE_DIT = 0x1a, } arm64_pstate; /// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn) typedef enum arm64_vas { ARM64_VAS_INVALID = 0, - ARM64_VAS_8B, ARM64_VAS_16B, - ARM64_VAS_4H, + ARM64_VAS_8B, + ARM64_VAS_4B, + ARM64_VAS_1B, ARM64_VAS_8H, - ARM64_VAS_2S, + ARM64_VAS_4H, + ARM64_VAS_2H, + ARM64_VAS_1H, ARM64_VAS_4S, - ARM64_VAS_1D, + ARM64_VAS_2S, + ARM64_VAS_1S, ARM64_VAS_2D, + ARM64_VAS_1D, ARM64_VAS_1Q, } arm64_vas; -/// Vector element size specifier -typedef enum arm64_vess { - ARM64_VESS_INVALID = 0, - ARM64_VESS_B, - ARM64_VESS_H, - ARM64_VESS_S, - ARM64_VESS_D, -} arm64_vess; - /// Memory barrier operands typedef enum arm64_barrier_op { ARM64_BARRIER_INVALID = 0, @@ -248,54 +890,103 @@ typedef enum arm64_op_type { /// TLBI operations typedef enum arm64_tlbi_op { ARM64_TLBI_INVALID = 0, - ARM64_TLBI_VMALLE1IS, - ARM64_TLBI_VAE1IS, - ARM64_TLBI_ASIDE1IS, - ARM64_TLBI_VAAE1IS, - ARM64_TLBI_VALE1IS, - ARM64_TLBI_VAALE1IS, - ARM64_TLBI_ALLE2IS, - ARM64_TLBI_VAE2IS, - ARM64_TLBI_ALLE1IS, - ARM64_TLBI_VALE2IS, - ARM64_TLBI_VMALLS12E1IS, - ARM64_TLBI_ALLE3IS, - ARM64_TLBI_VAE3IS, - ARM64_TLBI_VALE3IS, + ARM64_TLBI_IPAS2E1IS, ARM64_TLBI_IPAS2LE1IS, + ARM64_TLBI_VMALLE1IS, + ARM64_TLBI_ALLE2IS, + ARM64_TLBI_ALLE3IS, + ARM64_TLBI_VAE1IS, + ARM64_TLBI_VAE2IS, + ARM64_TLBI_VAE3IS, + ARM64_TLBI_ASIDE1IS, + ARM64_TLBI_VAAE1IS, + ARM64_TLBI_ALLE1IS, + ARM64_TLBI_VALE1IS, + ARM64_TLBI_VALE2IS, + ARM64_TLBI_VALE3IS, + ARM64_TLBI_VMALLS12E1IS, + ARM64_TLBI_VAALE1IS, ARM64_TLBI_IPAS2E1, ARM64_TLBI_IPAS2LE1, ARM64_TLBI_VMALLE1, + ARM64_TLBI_ALLE2, + ARM64_TLBI_ALLE3, ARM64_TLBI_VAE1, + ARM64_TLBI_VAE2, + ARM64_TLBI_VAE3, ARM64_TLBI_ASIDE1, ARM64_TLBI_VAAE1, - ARM64_TLBI_VALE1, - ARM64_TLBI_VAALE1, - ARM64_TLBI_ALLE2, - ARM64_TLBI_VAE2, ARM64_TLBI_ALLE1, + ARM64_TLBI_VALE1, ARM64_TLBI_VALE2, - ARM64_TLBI_VMALLS12E1, - ARM64_TLBI_ALLE3, - ARM64_TLBI_VAE3, ARM64_TLBI_VALE3, + ARM64_TLBI_VMALLS12E1, + ARM64_TLBI_VAALE1, + ARM64_TLBI_VMALLE1OS, + ARM64_TLBI_VAE1OS, + ARM64_TLBI_ASIDE1OS, + ARM64_TLBI_VAAE1OS, + ARM64_TLBI_VALE1OS, + ARM64_TLBI_VAALE1OS, + ARM64_TLBI_IPAS2E1OS, + ARM64_TLBI_IPAS2LE1OS, + ARM64_TLBI_VAE2OS, + ARM64_TLBI_VALE2OS, + ARM64_TLBI_VMALLS12E1OS, + ARM64_TLBI_VAE3OS, + ARM64_TLBI_VALE3OS, + ARM64_TLBI_ALLE2OS, + ARM64_TLBI_ALLE1OS, + ARM64_TLBI_ALLE3OS, + ARM64_TLBI_RVAE1, + ARM64_TLBI_RVAAE1, + ARM64_TLBI_RVALE1, + ARM64_TLBI_RVAALE1, + ARM64_TLBI_RVAE1IS, + ARM64_TLBI_RVAAE1IS, + ARM64_TLBI_RVALE1IS, + ARM64_TLBI_RVAALE1IS, + ARM64_TLBI_RVAE1OS, + ARM64_TLBI_RVAAE1OS, + ARM64_TLBI_RVALE1OS, + ARM64_TLBI_RVAALE1OS, + ARM64_TLBI_RIPAS2E1IS, + ARM64_TLBI_RIPAS2LE1IS, + ARM64_TLBI_RIPAS2E1, + ARM64_TLBI_RIPAS2LE1, + ARM64_TLBI_RIPAS2E1OS, + ARM64_TLBI_RIPAS2LE1OS, + ARM64_TLBI_RVAE2, + ARM64_TLBI_RVALE2, + ARM64_TLBI_RVAE2IS, + ARM64_TLBI_RVALE2IS, + ARM64_TLBI_RVAE2OS, + ARM64_TLBI_RVALE2OS, + ARM64_TLBI_RVAE3, + ARM64_TLBI_RVALE3, + ARM64_TLBI_RVAE3IS, + ARM64_TLBI_RVALE3IS, + ARM64_TLBI_RVAE3OS, + ARM64_TLBI_RVALE3OS, } arm64_tlbi_op; /// AT operations typedef enum arm64_at_op { ARM64_AT_S1E1R, + ARM64_AT_S1E2R, + ARM64_AT_S1E3R, ARM64_AT_S1E1W, + ARM64_AT_S1E2W, + ARM64_AT_S1E3W, ARM64_AT_S1E0R, ARM64_AT_S1E0W, - ARM64_AT_S1E2R, - ARM64_AT_S1E2W, ARM64_AT_S12E1R, ARM64_AT_S12E1W, ARM64_AT_S12E0R, ARM64_AT_S12E0W, - ARM64_AT_S1E3R, - ARM64_AT_S1E3W, + ARM64_AT_S1E1RP, + ARM64_AT_S1E1WP, } arm64_at_op; /// DC operations @@ -309,6 +1000,7 @@ typedef enum arm64_dc_op { ARM64_DC_CVAU, ARM64_DC_CIVAC, ARM64_DC_CISW, + ARM64_DC_CVAP, } arm64_dc_op; /// IC operations @@ -342,238 +1034,315 @@ typedef enum arm64_prefetch_op { ARM64_PRFM_PSTL3STRM = 0x15 + 1, } arm64_prefetch_op; +#if 0 +static const SVEPREDPAT SVEPREDPATsList[] = { + { "pow2", 0x0 }, // 0 + { "vl1", 0x1 }, // 1 + { "vl2", 0x2 }, // 2 + { "vl3", 0x3 }, // 3 + { "vl4", 0x4 }, // 4 + { "vl5", 0x5 }, // 5 + { "vl6", 0x6 }, // 6 + { "vl7", 0x7 }, // 7 + { "vl8", 0x8 }, // 8 + { "vl16", 0x9 }, // 9 + { "vl32", 0xa }, // 10 + { "vl64", 0xb }, // 11 + { "vl128", 0xc }, // 12 + { "vl256", 0xd }, // 13 + { "mul4", 0x1d }, // 14 + { "mul3", 0x1e }, // 15 + { "all", 0x1f }, // 16 +}; + +static const ExactFPImm ExactFPImmsList[] = { + { "zero", 0x0, "0.0" }, // 0 + { "half", 0x1, "0.5" }, // 1 + { "one", 0x2, "1.0" }, // 2 + { "two", 0x3, "2.0" }, // 3 +}; +#endif /// ARM64 registers typedef enum arm64_reg { ARM64_REG_INVALID = 0, - ARM64_REG_X29, - ARM64_REG_X30, - ARM64_REG_NZCV, - ARM64_REG_SP, - ARM64_REG_WSP, - ARM64_REG_WZR, - ARM64_REG_XZR, - ARM64_REG_B0, - ARM64_REG_B1, - ARM64_REG_B2, - ARM64_REG_B3, - ARM64_REG_B4, - ARM64_REG_B5, - ARM64_REG_B6, - ARM64_REG_B7, - ARM64_REG_B8, - ARM64_REG_B9, - ARM64_REG_B10, - ARM64_REG_B11, - ARM64_REG_B12, - ARM64_REG_B13, - ARM64_REG_B14, - ARM64_REG_B15, - ARM64_REG_B16, - ARM64_REG_B17, - ARM64_REG_B18, - ARM64_REG_B19, - ARM64_REG_B20, - ARM64_REG_B21, - ARM64_REG_B22, - ARM64_REG_B23, - ARM64_REG_B24, - ARM64_REG_B25, - ARM64_REG_B26, - ARM64_REG_B27, - ARM64_REG_B28, - ARM64_REG_B29, - ARM64_REG_B30, - ARM64_REG_B31, - ARM64_REG_D0, - ARM64_REG_D1, - ARM64_REG_D2, - ARM64_REG_D3, - ARM64_REG_D4, - ARM64_REG_D5, - ARM64_REG_D6, - ARM64_REG_D7, - ARM64_REG_D8, - ARM64_REG_D9, - ARM64_REG_D10, - ARM64_REG_D11, - ARM64_REG_D12, - ARM64_REG_D13, - ARM64_REG_D14, - ARM64_REG_D15, - ARM64_REG_D16, - ARM64_REG_D17, - ARM64_REG_D18, - ARM64_REG_D19, - ARM64_REG_D20, - ARM64_REG_D21, - ARM64_REG_D22, - ARM64_REG_D23, - ARM64_REG_D24, - ARM64_REG_D25, - ARM64_REG_D26, - ARM64_REG_D27, - ARM64_REG_D28, - ARM64_REG_D29, - ARM64_REG_D30, - ARM64_REG_D31, - ARM64_REG_H0, - ARM64_REG_H1, - ARM64_REG_H2, - ARM64_REG_H3, - ARM64_REG_H4, - ARM64_REG_H5, - ARM64_REG_H6, - ARM64_REG_H7, - ARM64_REG_H8, - ARM64_REG_H9, - ARM64_REG_H10, - ARM64_REG_H11, - ARM64_REG_H12, - ARM64_REG_H13, - ARM64_REG_H14, - ARM64_REG_H15, - ARM64_REG_H16, - ARM64_REG_H17, - ARM64_REG_H18, - ARM64_REG_H19, - ARM64_REG_H20, - ARM64_REG_H21, - ARM64_REG_H22, - ARM64_REG_H23, - ARM64_REG_H24, - ARM64_REG_H25, - ARM64_REG_H26, - ARM64_REG_H27, - ARM64_REG_H28, - ARM64_REG_H29, - ARM64_REG_H30, - ARM64_REG_H31, - ARM64_REG_Q0, - ARM64_REG_Q1, - ARM64_REG_Q2, - ARM64_REG_Q3, - ARM64_REG_Q4, - ARM64_REG_Q5, - ARM64_REG_Q6, - ARM64_REG_Q7, - ARM64_REG_Q8, - ARM64_REG_Q9, - ARM64_REG_Q10, - ARM64_REG_Q11, - ARM64_REG_Q12, - ARM64_REG_Q13, - ARM64_REG_Q14, - ARM64_REG_Q15, - ARM64_REG_Q16, - ARM64_REG_Q17, - ARM64_REG_Q18, - ARM64_REG_Q19, - ARM64_REG_Q20, - ARM64_REG_Q21, - ARM64_REG_Q22, - ARM64_REG_Q23, - ARM64_REG_Q24, - ARM64_REG_Q25, - ARM64_REG_Q26, - ARM64_REG_Q27, - ARM64_REG_Q28, - ARM64_REG_Q29, - ARM64_REG_Q30, - ARM64_REG_Q31, - ARM64_REG_S0, - ARM64_REG_S1, - ARM64_REG_S2, - ARM64_REG_S3, - ARM64_REG_S4, - ARM64_REG_S5, - ARM64_REG_S6, - ARM64_REG_S7, - ARM64_REG_S8, - ARM64_REG_S9, - ARM64_REG_S10, - ARM64_REG_S11, - ARM64_REG_S12, - ARM64_REG_S13, - ARM64_REG_S14, - ARM64_REG_S15, - ARM64_REG_S16, - ARM64_REG_S17, - ARM64_REG_S18, - ARM64_REG_S19, - ARM64_REG_S20, - ARM64_REG_S21, - ARM64_REG_S22, - ARM64_REG_S23, - ARM64_REG_S24, - ARM64_REG_S25, - ARM64_REG_S26, - ARM64_REG_S27, - ARM64_REG_S28, - ARM64_REG_S29, - ARM64_REG_S30, - ARM64_REG_S31, - ARM64_REG_W0, - ARM64_REG_W1, - ARM64_REG_W2, - ARM64_REG_W3, - ARM64_REG_W4, - ARM64_REG_W5, - ARM64_REG_W6, - ARM64_REG_W7, - ARM64_REG_W8, - ARM64_REG_W9, - ARM64_REG_W10, - ARM64_REG_W11, - ARM64_REG_W12, - ARM64_REG_W13, - ARM64_REG_W14, - ARM64_REG_W15, - ARM64_REG_W16, - ARM64_REG_W17, - ARM64_REG_W18, - ARM64_REG_W19, - ARM64_REG_W20, - ARM64_REG_W21, - ARM64_REG_W22, - ARM64_REG_W23, - ARM64_REG_W24, - ARM64_REG_W25, - ARM64_REG_W26, - ARM64_REG_W27, - ARM64_REG_W28, - ARM64_REG_W29, - ARM64_REG_W30, - ARM64_REG_X0, - ARM64_REG_X1, - ARM64_REG_X2, - ARM64_REG_X3, - ARM64_REG_X4, - ARM64_REG_X5, - ARM64_REG_X6, - ARM64_REG_X7, - ARM64_REG_X8, - ARM64_REG_X9, - ARM64_REG_X10, - ARM64_REG_X11, - ARM64_REG_X12, - ARM64_REG_X13, - ARM64_REG_X14, - ARM64_REG_X15, - ARM64_REG_X16, - ARM64_REG_X17, - ARM64_REG_X18, - ARM64_REG_X19, - ARM64_REG_X20, - ARM64_REG_X21, - ARM64_REG_X22, - ARM64_REG_X23, - ARM64_REG_X24, - ARM64_REG_X25, - ARM64_REG_X26, - ARM64_REG_X27, - ARM64_REG_X28, + ARM64_REG_FFR = 1, + ARM64_REG_FP = 2, + ARM64_REG_LR = 3, + ARM64_REG_NZCV = 4, + ARM64_REG_SP = 5, + ARM64_REG_WSP = 6, + ARM64_REG_WZR = 7, + ARM64_REG_XZR = 8, + ARM64_REG_B0 = 9, + ARM64_REG_B1 = 10, + ARM64_REG_B2 = 11, + ARM64_REG_B3 = 12, + ARM64_REG_B4 = 13, + ARM64_REG_B5 = 14, + ARM64_REG_B6 = 15, + ARM64_REG_B7 = 16, + ARM64_REG_B8 = 17, + ARM64_REG_B9 = 18, + ARM64_REG_B10 = 19, + ARM64_REG_B11 = 20, + ARM64_REG_B12 = 21, + ARM64_REG_B13 = 22, + ARM64_REG_B14 = 23, + ARM64_REG_B15 = 24, + ARM64_REG_B16 = 25, + ARM64_REG_B17 = 26, + ARM64_REG_B18 = 27, + ARM64_REG_B19 = 28, + ARM64_REG_B20 = 29, + ARM64_REG_B21 = 30, + ARM64_REG_B22 = 31, + ARM64_REG_B23 = 32, + ARM64_REG_B24 = 33, + ARM64_REG_B25 = 34, + ARM64_REG_B26 = 35, + ARM64_REG_B27 = 36, + ARM64_REG_B28 = 37, + ARM64_REG_B29 = 38, + ARM64_REG_B30 = 39, + ARM64_REG_B31 = 40, + ARM64_REG_D0 = 41, + ARM64_REG_D1 = 42, + ARM64_REG_D2 = 43, + ARM64_REG_D3 = 44, + ARM64_REG_D4 = 45, + ARM64_REG_D5 = 46, + ARM64_REG_D6 = 47, + ARM64_REG_D7 = 48, + ARM64_REG_D8 = 49, + ARM64_REG_D9 = 50, + ARM64_REG_D10 = 51, + ARM64_REG_D11 = 52, + ARM64_REG_D12 = 53, + ARM64_REG_D13 = 54, + ARM64_REG_D14 = 55, + ARM64_REG_D15 = 56, + ARM64_REG_D16 = 57, + ARM64_REG_D17 = 58, + ARM64_REG_D18 = 59, + ARM64_REG_D19 = 60, + ARM64_REG_D20 = 61, + ARM64_REG_D21 = 62, + ARM64_REG_D22 = 63, + ARM64_REG_D23 = 64, + ARM64_REG_D24 = 65, + ARM64_REG_D25 = 66, + ARM64_REG_D26 = 67, + ARM64_REG_D27 = 68, + ARM64_REG_D28 = 69, + ARM64_REG_D29 = 70, + ARM64_REG_D30 = 71, + ARM64_REG_D31 = 72, + ARM64_REG_H0 = 73, + ARM64_REG_H1 = 74, + ARM64_REG_H2 = 75, + ARM64_REG_H3 = 76, + ARM64_REG_H4 = 77, + ARM64_REG_H5 = 78, + ARM64_REG_H6 = 79, + ARM64_REG_H7 = 80, + ARM64_REG_H8 = 81, + ARM64_REG_H9 = 82, + ARM64_REG_H10 = 83, + ARM64_REG_H11 = 84, + ARM64_REG_H12 = 85, + ARM64_REG_H13 = 86, + ARM64_REG_H14 = 87, + ARM64_REG_H15 = 88, + ARM64_REG_H16 = 89, + ARM64_REG_H17 = 90, + ARM64_REG_H18 = 91, + ARM64_REG_H19 = 92, + ARM64_REG_H20 = 93, + ARM64_REG_H21 = 94, + ARM64_REG_H22 = 95, + ARM64_REG_H23 = 96, + ARM64_REG_H24 = 97, + ARM64_REG_H25 = 98, + ARM64_REG_H26 = 99, + ARM64_REG_H27 = 100, + ARM64_REG_H28 = 101, + ARM64_REG_H29 = 102, + ARM64_REG_H30 = 103, + ARM64_REG_H31 = 104, + ARM64_REG_P0 = 105, + ARM64_REG_P1 = 106, + ARM64_REG_P2 = 107, + ARM64_REG_P3 = 108, + ARM64_REG_P4 = 109, + ARM64_REG_P5 = 110, + ARM64_REG_P6 = 111, + ARM64_REG_P7 = 112, + ARM64_REG_P8 = 113, + ARM64_REG_P9 = 114, + ARM64_REG_P10 = 115, + ARM64_REG_P11 = 116, + ARM64_REG_P12 = 117, + ARM64_REG_P13 = 118, + ARM64_REG_P14 = 119, + ARM64_REG_P15 = 120, + ARM64_REG_Q0 = 121, + ARM64_REG_Q1 = 122, + ARM64_REG_Q2 = 123, + ARM64_REG_Q3 = 124, + ARM64_REG_Q4 = 125, + ARM64_REG_Q5 = 126, + ARM64_REG_Q6 = 127, + ARM64_REG_Q7 = 128, + ARM64_REG_Q8 = 129, + ARM64_REG_Q9 = 130, + ARM64_REG_Q10 = 131, + ARM64_REG_Q11 = 132, + ARM64_REG_Q12 = 133, + ARM64_REG_Q13 = 134, + ARM64_REG_Q14 = 135, + ARM64_REG_Q15 = 136, + ARM64_REG_Q16 = 137, + ARM64_REG_Q17 = 138, + ARM64_REG_Q18 = 139, + ARM64_REG_Q19 = 140, + ARM64_REG_Q20 = 141, + ARM64_REG_Q21 = 142, + ARM64_REG_Q22 = 143, + ARM64_REG_Q23 = 144, + ARM64_REG_Q24 = 145, + ARM64_REG_Q25 = 146, + ARM64_REG_Q26 = 147, + ARM64_REG_Q27 = 148, + ARM64_REG_Q28 = 149, + ARM64_REG_Q29 = 150, + ARM64_REG_Q30 = 151, + ARM64_REG_Q31 = 152, + ARM64_REG_S0 = 153, + ARM64_REG_S1 = 154, + ARM64_REG_S2 = 155, + ARM64_REG_S3 = 156, + ARM64_REG_S4 = 157, + ARM64_REG_S5 = 158, + ARM64_REG_S6 = 159, + ARM64_REG_S7 = 160, + ARM64_REG_S8 = 161, + ARM64_REG_S9 = 162, + ARM64_REG_S10 = 163, + ARM64_REG_S11 = 164, + ARM64_REG_S12 = 165, + ARM64_REG_S13 = 166, + ARM64_REG_S14 = 167, + ARM64_REG_S15 = 168, + ARM64_REG_S16 = 169, + ARM64_REG_S17 = 170, + ARM64_REG_S18 = 171, + ARM64_REG_S19 = 172, + ARM64_REG_S20 = 173, + ARM64_REG_S21 = 174, + ARM64_REG_S22 = 175, + ARM64_REG_S23 = 176, + ARM64_REG_S24 = 177, + ARM64_REG_S25 = 178, + ARM64_REG_S26 = 179, + ARM64_REG_S27 = 180, + ARM64_REG_S28 = 181, + ARM64_REG_S29 = 182, + ARM64_REG_S30 = 183, + ARM64_REG_S31 = 184, + ARM64_REG_W0 = 185, + ARM64_REG_W1 = 186, + ARM64_REG_W2 = 187, + ARM64_REG_W3 = 188, + ARM64_REG_W4 = 189, + ARM64_REG_W5 = 190, + ARM64_REG_W6 = 191, + ARM64_REG_W7 = 192, + ARM64_REG_W8 = 193, + ARM64_REG_W9 = 194, + ARM64_REG_W10 = 195, + ARM64_REG_W11 = 196, + ARM64_REG_W12 = 197, + ARM64_REG_W13 = 198, + ARM64_REG_W14 = 199, + ARM64_REG_W15 = 200, + ARM64_REG_W16 = 201, + ARM64_REG_W17 = 202, + ARM64_REG_W18 = 203, + ARM64_REG_W19 = 204, + ARM64_REG_W20 = 205, + ARM64_REG_W21 = 206, + ARM64_REG_W22 = 207, + ARM64_REG_W23 = 208, + ARM64_REG_W24 = 209, + ARM64_REG_W25 = 210, + ARM64_REG_W26 = 211, + ARM64_REG_W27 = 212, + ARM64_REG_W28 = 213, + ARM64_REG_W29 = 214, + ARM64_REG_W30 = 215, + ARM64_REG_X0 = 216, + ARM64_REG_X1 = 217, + ARM64_REG_X2 = 218, + ARM64_REG_X3 = 219, + ARM64_REG_X4 = 220, + ARM64_REG_X5 = 221, + ARM64_REG_X6 = 222, + ARM64_REG_X7 = 223, + ARM64_REG_X8 = 224, + ARM64_REG_X9 = 225, + ARM64_REG_X10 = 226, + ARM64_REG_X11 = 227, + ARM64_REG_X12 = 228, + ARM64_REG_X13 = 229, + ARM64_REG_X14 = 230, + ARM64_REG_X15 = 231, + ARM64_REG_X16 = 232, + ARM64_REG_X17 = 233, + ARM64_REG_X18 = 234, + ARM64_REG_X19 = 235, + ARM64_REG_X20 = 236, + ARM64_REG_X21 = 237, + ARM64_REG_X22 = 238, + ARM64_REG_X23 = 239, + ARM64_REG_X24 = 240, + ARM64_REG_X25 = 241, + ARM64_REG_X26 = 242, + ARM64_REG_X27 = 243, + ARM64_REG_X28 = 244, + ARM64_REG_Z0 = 245, + ARM64_REG_Z1 = 246, + ARM64_REG_Z2 = 247, + ARM64_REG_Z3 = 248, + ARM64_REG_Z4 = 249, + ARM64_REG_Z5 = 250, + ARM64_REG_Z6 = 251, + ARM64_REG_Z7 = 252, + ARM64_REG_Z8 = 253, + ARM64_REG_Z9 = 254, + ARM64_REG_Z10 = 255, + ARM64_REG_Z11 = 256, + ARM64_REG_Z12 = 257, + ARM64_REG_Z13 = 258, + ARM64_REG_Z14 = 259, + ARM64_REG_Z15 = 260, + ARM64_REG_Z16 = 261, + ARM64_REG_Z17 = 262, + ARM64_REG_Z18 = 263, + ARM64_REG_Z19 = 264, + ARM64_REG_Z20 = 265, + ARM64_REG_Z21 = 266, + ARM64_REG_Z22 = 267, + ARM64_REG_Z23 = 268, + ARM64_REG_Z24 = 269, + ARM64_REG_Z25 = 270, + ARM64_REG_Z26 = 271, + ARM64_REG_Z27 = 272, + ARM64_REG_Z28 = 273, + ARM64_REG_Z29 = 274, + ARM64_REG_Z30 = 275, + ARM64_REG_Z31 = 276, ARM64_REG_V0, ARM64_REG_V1, @@ -611,11 +1380,10 @@ typedef enum arm64_reg { ARM64_REG_ENDING, // <-- mark the end of the list of registers // alias registers - ARM64_REG_IP0 = ARM64_REG_X16, ARM64_REG_IP1 = ARM64_REG_X17, - ARM64_REG_FP = ARM64_REG_X29, - ARM64_REG_LR = ARM64_REG_X30, + ARM64_REG_X29 = ARM64_REG_FP, + ARM64_REG_X30 = ARM64_REG_LR, } arm64_reg; /// Instruction's operand referring to memory @@ -630,7 +1398,6 @@ typedef struct arm64_op_mem { typedef struct cs_arm64_op { int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant) arm64_vas vas; ///< Vector Arrangement Specifier - arm64_vess vess; ///< Vector Element Size Specifier struct { arm64_shifter type; ///< shifter type of this operand unsigned int value; ///< shifter value of this operand @@ -671,147 +1438,30 @@ typedef struct cs_arm64 { typedef enum arm64_insn { ARM64_INS_INVALID = 0, - ARM64_INS_ABS_ZPmZ_B, - ARM64_INS_ABS_ZPmZ_D, - ARM64_INS_ABS_ZPmZ_H, - ARM64_INS_ABS_ZPmZ_S, - ARM64_INS_ABSv16i8, - ARM64_INS_ABSv1i64, - ARM64_INS_ABSv2i32, - ARM64_INS_ABSv2i64, - ARM64_INS_ABSv4i16, - ARM64_INS_ABSv4i32, - ARM64_INS_ABSv8i16, - ARM64_INS_ABSv8i8, - ARM64_INS_ADCSWr, - ARM64_INS_ADCSXr, - ARM64_INS_ADCWr, - ARM64_INS_ADCXr, - ARM64_INS_ADDHNv2i64_v2i32, - ARM64_INS_ADDHNv2i64_v4i32, - ARM64_INS_ADDHNv4i32_v4i16, - ARM64_INS_ADDHNv4i32_v8i16, - ARM64_INS_ADDHNv8i16_v16i8, - ARM64_INS_ADDHNv8i16_v8i8, - ARM64_INS_ADDPL_XXI, - ARM64_INS_ADDPv16i8, - ARM64_INS_ADDPv2i32, - ARM64_INS_ADDPv2i64, - ARM64_INS_ADDPv2i64p, - ARM64_INS_ADDPv4i16, - ARM64_INS_ADDPv4i32, - ARM64_INS_ADDPv8i16, - ARM64_INS_ADDPv8i8, - ARM64_INS_ADDSWri, - ARM64_INS_ADDSWrs, - ARM64_INS_ADDSWrx, - ARM64_INS_ADDSXri, - ARM64_INS_ADDSXrs, - ARM64_INS_ADDSXrx, - ARM64_INS_ADDSXrx64, - ARM64_INS_ADDVL_XXI, - ARM64_INS_ADDVv16i8v, - ARM64_INS_ADDVv4i16v, - ARM64_INS_ADDVv4i32v, - ARM64_INS_ADDVv8i16v, - ARM64_INS_ADDVv8i8v, - ARM64_INS_ADDWri, - ARM64_INS_ADDWrs, - ARM64_INS_ADDWrx, - ARM64_INS_ADDXri, - ARM64_INS_ADDXrs, - ARM64_INS_ADDXrx, - ARM64_INS_ADDXrx64, - ARM64_INS_ADD_ZI_B, - ARM64_INS_ADD_ZI_D, - ARM64_INS_ADD_ZI_H, - ARM64_INS_ADD_ZI_S, - ARM64_INS_ADD_ZPmZ_B, - ARM64_INS_ADD_ZPmZ_D, - ARM64_INS_ADD_ZPmZ_H, - ARM64_INS_ADD_ZPmZ_S, - ARM64_INS_ADD_ZZZ_B, - ARM64_INS_ADD_ZZZ_D, - ARM64_INS_ADD_ZZZ_H, - ARM64_INS_ADD_ZZZ_S, - ARM64_INS_ADDv16i8, - ARM64_INS_ADDv1i64, - ARM64_INS_ADDv2i32, - ARM64_INS_ADDv2i64, - ARM64_INS_ADDv4i16, - ARM64_INS_ADDv4i32, - ARM64_INS_ADDv8i16, - ARM64_INS_ADDv8i8, - ARM64_INS_ADR_LSL_ZZZ_D_0, - ARM64_INS_ADR_LSL_ZZZ_D_1, - ARM64_INS_ADR_LSL_ZZZ_D_2, - ARM64_INS_ADR_LSL_ZZZ_D_3, - ARM64_INS_ADR_LSL_ZZZ_S_0, - ARM64_INS_ADR_LSL_ZZZ_S_1, - ARM64_INS_ADR_LSL_ZZZ_S_2, - ARM64_INS_ADR_LSL_ZZZ_S_3, - ARM64_INS_ADR_SXTW_ZZZ_D_0, - ARM64_INS_ADR_SXTW_ZZZ_D_1, - ARM64_INS_ADR_SXTW_ZZZ_D_2, - ARM64_INS_ADR_SXTW_ZZZ_D_3, - ARM64_INS_ADR_UXTW_ZZZ_D_0, - ARM64_INS_ADR_UXTW_ZZZ_D_1, - ARM64_INS_ADR_UXTW_ZZZ_D_2, - ARM64_INS_ADR_UXTW_ZZZ_D_3, - ARM64_INS_AESDrr, - ARM64_INS_AESErr, - ARM64_INS_AESIMCrr, - ARM64_INS_AESMCrr, - ARM64_INS_ANDSWri, - ARM64_INS_ANDSWrs, - ARM64_INS_ANDSXri, - ARM64_INS_ANDSXrs, - ARM64_INS_ANDS_PPzPP, - ARM64_INS_ANDV_VPZ_B, - ARM64_INS_ANDV_VPZ_D, - ARM64_INS_ANDV_VPZ_H, - ARM64_INS_ANDV_VPZ_S, - ARM64_INS_ANDWri, - ARM64_INS_ANDWrs, - ARM64_INS_ANDXri, - ARM64_INS_ANDXrs, - ARM64_INS_AND_PPzPP, - ARM64_INS_AND_ZI, - ARM64_INS_AND_ZPmZ_B, - ARM64_INS_AND_ZPmZ_D, - ARM64_INS_AND_ZPmZ_H, - ARM64_INS_AND_ZPmZ_S, - ARM64_INS_AND_ZZZ, - ARM64_INS_ANDv16i8, - ARM64_INS_ANDv8i8, - ARM64_INS_ASRD_ZPmI_B, - ARM64_INS_ASRD_ZPmI_D, - ARM64_INS_ASRD_ZPmI_H, - ARM64_INS_ASRD_ZPmI_S, - ARM64_INS_ASRR_ZPmZ_B, - ARM64_INS_ASRR_ZPmZ_D, - ARM64_INS_ASRR_ZPmZ_H, - ARM64_INS_ASRR_ZPmZ_S, - ARM64_INS_ASRVWr, - ARM64_INS_ASRVXr, - ARM64_INS_ASR_WIDE_ZPmZ_B, - ARM64_INS_ASR_WIDE_ZPmZ_H, - ARM64_INS_ASR_WIDE_ZPmZ_S, - ARM64_INS_ASR_WIDE_ZZZ_B, - ARM64_INS_ASR_WIDE_ZZZ_H, - ARM64_INS_ASR_WIDE_ZZZ_S, - ARM64_INS_ASR_ZPmI_B, - ARM64_INS_ASR_ZPmI_D, - ARM64_INS_ASR_ZPmI_H, - ARM64_INS_ASR_ZPmI_S, - ARM64_INS_ASR_ZPmZ_B, - ARM64_INS_ASR_ZPmZ_D, - ARM64_INS_ASR_ZPmZ_H, - ARM64_INS_ASR_ZPmZ_S, - ARM64_INS_ASR_ZZI_B, - ARM64_INS_ASR_ZZI_D, - ARM64_INS_ASR_ZZI_H, - ARM64_INS_ASR_ZZI_S, + ARM64_INS_ABS, + ARM64_INS_ADC, + ARM64_INS_ADCS, + ARM64_INS_ADD, + ARM64_INS_ADDHN, + ARM64_INS_ADDHN2, + ARM64_INS_ADDP, + ARM64_INS_ADDPL, + ARM64_INS_ADDS, + ARM64_INS_ADDV, + ARM64_INS_ADDVL, + ARM64_INS_ADR, + ARM64_INS_ADRP, + ARM64_INS_AESD, + ARM64_INS_AESE, + ARM64_INS_AESIMC, + ARM64_INS_AESMC, + ARM64_INS_AND, + ARM64_INS_ANDS, + ARM64_INS_ANDV, + ARM64_INS_ASR, + ARM64_INS_ASRD, + ARM64_INS_ASRR, + ARM64_INS_ASRV, ARM64_INS_AUTDA, ARM64_INS_AUTDB, ARM64_INS_AUTDZA, @@ -826,2312 +1476,485 @@ typedef enum arm64_insn { ARM64_INS_AUTIBZ, ARM64_INS_AUTIZA, ARM64_INS_AUTIZB, + ARM64_INS_B, ARM64_INS_BCAX, - ARM64_INS_BFMWri, - ARM64_INS_BFMXri, - ARM64_INS_BICSWrs, - ARM64_INS_BICSXrs, - ARM64_INS_BICS_PPzPP, - ARM64_INS_BICWrs, - ARM64_INS_BICXrs, - ARM64_INS_BIC_PPzPP, - ARM64_INS_BIC_ZPmZ_B, - ARM64_INS_BIC_ZPmZ_D, - ARM64_INS_BIC_ZPmZ_H, - ARM64_INS_BIC_ZPmZ_S, - ARM64_INS_BIC_ZZZ, - ARM64_INS_BICv16i8, - ARM64_INS_BICv2i32, - ARM64_INS_BICv4i16, - ARM64_INS_BICv4i32, - ARM64_INS_BICv8i16, - ARM64_INS_BICv8i8, - ARM64_INS_BIFv16i8, - ARM64_INS_BIFv8i8, - ARM64_INS_BITv16i8, - ARM64_INS_BITv8i8, + ARM64_INS_BFM, + ARM64_INS_BIC, + ARM64_INS_BICS, + ARM64_INS_BIF, + ARM64_INS_BIT, + ARM64_INS_BL, + ARM64_INS_BLR, ARM64_INS_BLRAA, ARM64_INS_BLRAAZ, ARM64_INS_BLRAB, ARM64_INS_BLRABZ, + ARM64_INS_BR, ARM64_INS_BRAA, ARM64_INS_BRAAZ, ARM64_INS_BRAB, ARM64_INS_BRABZ, - ARM64_INS_BRKAS_PPzP, - ARM64_INS_BRKA_PPmP, - ARM64_INS_BRKA_PPzP, - ARM64_INS_BRKBS_PPzP, - ARM64_INS_BRKB_PPmP, - ARM64_INS_BRKB_PPzP, - ARM64_INS_BRKNS_PPzP, - ARM64_INS_BRKN_PPzP, - ARM64_INS_BRKPAS_PPzPP, - ARM64_INS_BRKPA_PPzPP, - ARM64_INS_BRKPBS_PPzPP, - ARM64_INS_BRKPB_PPzPP, - ARM64_INS_BSLv16i8, - ARM64_INS_BSLv8i8, - ARM64_INS_Bcc, + ARM64_INS_BRK, + ARM64_INS_BRKA, + ARM64_INS_BRKAS, + ARM64_INS_BRKB, + ARM64_INS_BRKBS, + ARM64_INS_BRKN, + ARM64_INS_BRKNS, + ARM64_INS_BRKPA, + ARM64_INS_BRKPAS, + ARM64_INS_BRKPB, + ARM64_INS_BRKPBS, + ARM64_INS_BSL, + ARM64_INS_CAS, + ARM64_INS_CASA, ARM64_INS_CASAB, ARM64_INS_CASAH, + ARM64_INS_CASAL, ARM64_INS_CASALB, ARM64_INS_CASALH, - ARM64_INS_CASALW, - ARM64_INS_CASALX, - ARM64_INS_CASAW, - ARM64_INS_CASAX, ARM64_INS_CASB, ARM64_INS_CASH, + ARM64_INS_CASL, ARM64_INS_CASLB, ARM64_INS_CASLH, - ARM64_INS_CASLW, - ARM64_INS_CASLX, - ARM64_INS_CASPALW, - ARM64_INS_CASPALX, - ARM64_INS_CASPAW, - ARM64_INS_CASPAX, - ARM64_INS_CASPLW, - ARM64_INS_CASPLX, - ARM64_INS_CASPW, - ARM64_INS_CASPX, - ARM64_INS_CASW, - ARM64_INS_CASX, - ARM64_INS_CBNZW, - ARM64_INS_CBNZX, - ARM64_INS_CBZW, - ARM64_INS_CBZX, - ARM64_INS_CCMNWi, - ARM64_INS_CCMNWr, - ARM64_INS_CCMNXi, - ARM64_INS_CCMNXr, - ARM64_INS_CCMPWi, - ARM64_INS_CCMPWr, - ARM64_INS_CCMPXi, - ARM64_INS_CCMPXr, + ARM64_INS_CASP, + ARM64_INS_CASPA, + ARM64_INS_CASPAL, + ARM64_INS_CASPL, + ARM64_INS_CBNZ, + ARM64_INS_CBZ, + ARM64_INS_CCMN, + ARM64_INS_CCMP, ARM64_INS_CFINV, - ARM64_INS_CLASTA_RPZ_B, - ARM64_INS_CLASTA_RPZ_D, - ARM64_INS_CLASTA_RPZ_H, - ARM64_INS_CLASTA_RPZ_S, - ARM64_INS_CLASTA_VPZ_B, - ARM64_INS_CLASTA_VPZ_D, - ARM64_INS_CLASTA_VPZ_H, - ARM64_INS_CLASTA_VPZ_S, - ARM64_INS_CLASTA_ZPZ_B, - ARM64_INS_CLASTA_ZPZ_D, - ARM64_INS_CLASTA_ZPZ_H, - ARM64_INS_CLASTA_ZPZ_S, - ARM64_INS_CLASTB_RPZ_B, - ARM64_INS_CLASTB_RPZ_D, - ARM64_INS_CLASTB_RPZ_H, - ARM64_INS_CLASTB_RPZ_S, - ARM64_INS_CLASTB_VPZ_B, - ARM64_INS_CLASTB_VPZ_D, - ARM64_INS_CLASTB_VPZ_H, - ARM64_INS_CLASTB_VPZ_S, - ARM64_INS_CLASTB_ZPZ_B, - ARM64_INS_CLASTB_ZPZ_D, - ARM64_INS_CLASTB_ZPZ_H, - ARM64_INS_CLASTB_ZPZ_S, - ARM64_INS_CLSWr, - ARM64_INS_CLSXr, - ARM64_INS_CLS_ZPmZ_B, - ARM64_INS_CLS_ZPmZ_D, - ARM64_INS_CLS_ZPmZ_H, - ARM64_INS_CLS_ZPmZ_S, - ARM64_INS_CLSv16i8, - ARM64_INS_CLSv2i32, - ARM64_INS_CLSv4i16, - ARM64_INS_CLSv4i32, - ARM64_INS_CLSv8i16, - ARM64_INS_CLSv8i8, - ARM64_INS_CLZWr, - ARM64_INS_CLZXr, - ARM64_INS_CLZ_ZPmZ_B, - ARM64_INS_CLZ_ZPmZ_D, - ARM64_INS_CLZ_ZPmZ_H, - ARM64_INS_CLZ_ZPmZ_S, - ARM64_INS_CLZv16i8, - ARM64_INS_CLZv2i32, - ARM64_INS_CLZv4i16, - ARM64_INS_CLZv4i32, - ARM64_INS_CLZv8i16, - ARM64_INS_CLZv8i8, - ARM64_INS_CMEQv16i8, - ARM64_INS_CMEQv16i8rz, - ARM64_INS_CMEQv1i64, - ARM64_INS_CMEQv1i64rz, - ARM64_INS_CMEQv2i32, - ARM64_INS_CMEQv2i32rz, - ARM64_INS_CMEQv2i64, - ARM64_INS_CMEQv2i64rz, - ARM64_INS_CMEQv4i16, - ARM64_INS_CMEQv4i16rz, - ARM64_INS_CMEQv4i32, - ARM64_INS_CMEQv4i32rz, - ARM64_INS_CMEQv8i16, - ARM64_INS_CMEQv8i16rz, - ARM64_INS_CMEQv8i8, - ARM64_INS_CMEQv8i8rz, - ARM64_INS_CMGEv16i8, - ARM64_INS_CMGEv16i8rz, - ARM64_INS_CMGEv1i64, - ARM64_INS_CMGEv1i64rz, - ARM64_INS_CMGEv2i32, - ARM64_INS_CMGEv2i32rz, - ARM64_INS_CMGEv2i64, - ARM64_INS_CMGEv2i64rz, - ARM64_INS_CMGEv4i16, - ARM64_INS_CMGEv4i16rz, - ARM64_INS_CMGEv4i32, - ARM64_INS_CMGEv4i32rz, - ARM64_INS_CMGEv8i16, - ARM64_INS_CMGEv8i16rz, - ARM64_INS_CMGEv8i8, - ARM64_INS_CMGEv8i8rz, - ARM64_INS_CMGTv16i8, - ARM64_INS_CMGTv16i8rz, - ARM64_INS_CMGTv1i64, - ARM64_INS_CMGTv1i64rz, - ARM64_INS_CMGTv2i32, - ARM64_INS_CMGTv2i32rz, - ARM64_INS_CMGTv2i64, - ARM64_INS_CMGTv2i64rz, - ARM64_INS_CMGTv4i16, - ARM64_INS_CMGTv4i16rz, - ARM64_INS_CMGTv4i32, - ARM64_INS_CMGTv4i32rz, - ARM64_INS_CMGTv8i16, - ARM64_INS_CMGTv8i16rz, - ARM64_INS_CMGTv8i8, - ARM64_INS_CMGTv8i8rz, - ARM64_INS_CMHIv16i8, - ARM64_INS_CMHIv1i64, - ARM64_INS_CMHIv2i32, - ARM64_INS_CMHIv2i64, - ARM64_INS_CMHIv4i16, - ARM64_INS_CMHIv4i32, - ARM64_INS_CMHIv8i16, - ARM64_INS_CMHIv8i8, - ARM64_INS_CMHSv16i8, - ARM64_INS_CMHSv1i64, - ARM64_INS_CMHSv2i32, - ARM64_INS_CMHSv2i64, - ARM64_INS_CMHSv4i16, - ARM64_INS_CMHSv4i32, - ARM64_INS_CMHSv8i16, - ARM64_INS_CMHSv8i8, - ARM64_INS_CMLEv16i8rz, - ARM64_INS_CMLEv1i64rz, - ARM64_INS_CMLEv2i32rz, - ARM64_INS_CMLEv2i64rz, - ARM64_INS_CMLEv4i16rz, - ARM64_INS_CMLEv4i32rz, - ARM64_INS_CMLEv8i16rz, - ARM64_INS_CMLEv8i8rz, - ARM64_INS_CMLTv16i8rz, - ARM64_INS_CMLTv1i64rz, - ARM64_INS_CMLTv2i32rz, - ARM64_INS_CMLTv2i64rz, - ARM64_INS_CMLTv4i16rz, - ARM64_INS_CMLTv4i32rz, - ARM64_INS_CMLTv8i16rz, - ARM64_INS_CMLTv8i8rz, - ARM64_INS_CMPEQ_PPzZI_B, - ARM64_INS_CMPEQ_PPzZI_D, - ARM64_INS_CMPEQ_PPzZI_H, - ARM64_INS_CMPEQ_PPzZI_S, - ARM64_INS_CMPEQ_PPzZZ_B, - ARM64_INS_CMPEQ_PPzZZ_D, - ARM64_INS_CMPEQ_PPzZZ_H, - ARM64_INS_CMPEQ_PPzZZ_S, - ARM64_INS_CMPEQ_WIDE_PPzZZ_B, - ARM64_INS_CMPEQ_WIDE_PPzZZ_H, - ARM64_INS_CMPEQ_WIDE_PPzZZ_S, - ARM64_INS_CMPGE_PPzZI_B, - ARM64_INS_CMPGE_PPzZI_D, - ARM64_INS_CMPGE_PPzZI_H, - ARM64_INS_CMPGE_PPzZI_S, - ARM64_INS_CMPGE_PPzZZ_B, - ARM64_INS_CMPGE_PPzZZ_D, - ARM64_INS_CMPGE_PPzZZ_H, - ARM64_INS_CMPGE_PPzZZ_S, - ARM64_INS_CMPGE_WIDE_PPzZZ_B, - ARM64_INS_CMPGE_WIDE_PPzZZ_H, - ARM64_INS_CMPGE_WIDE_PPzZZ_S, - ARM64_INS_CMPGT_PPzZI_B, - ARM64_INS_CMPGT_PPzZI_D, - ARM64_INS_CMPGT_PPzZI_H, - ARM64_INS_CMPGT_PPzZI_S, - ARM64_INS_CMPGT_PPzZZ_B, - ARM64_INS_CMPGT_PPzZZ_D, - ARM64_INS_CMPGT_PPzZZ_H, - ARM64_INS_CMPGT_PPzZZ_S, - ARM64_INS_CMPGT_WIDE_PPzZZ_B, - ARM64_INS_CMPGT_WIDE_PPzZZ_H, - ARM64_INS_CMPGT_WIDE_PPzZZ_S, - ARM64_INS_CMPHI_PPzZI_B, - ARM64_INS_CMPHI_PPzZI_D, - ARM64_INS_CMPHI_PPzZI_H, - ARM64_INS_CMPHI_PPzZI_S, - ARM64_INS_CMPHI_PPzZZ_B, - ARM64_INS_CMPHI_PPzZZ_D, - ARM64_INS_CMPHI_PPzZZ_H, - ARM64_INS_CMPHI_PPzZZ_S, - ARM64_INS_CMPHI_WIDE_PPzZZ_B, - ARM64_INS_CMPHI_WIDE_PPzZZ_H, - ARM64_INS_CMPHI_WIDE_PPzZZ_S, - ARM64_INS_CMPHS_PPzZI_B, - ARM64_INS_CMPHS_PPzZI_D, - ARM64_INS_CMPHS_PPzZI_H, - ARM64_INS_CMPHS_PPzZI_S, - ARM64_INS_CMPHS_PPzZZ_B, - ARM64_INS_CMPHS_PPzZZ_D, - ARM64_INS_CMPHS_PPzZZ_H, - ARM64_INS_CMPHS_PPzZZ_S, - ARM64_INS_CMPHS_WIDE_PPzZZ_B, - ARM64_INS_CMPHS_WIDE_PPzZZ_H, - ARM64_INS_CMPHS_WIDE_PPzZZ_S, - ARM64_INS_CMPLE_PPzZI_B, - ARM64_INS_CMPLE_PPzZI_D, - ARM64_INS_CMPLE_PPzZI_H, - ARM64_INS_CMPLE_PPzZI_S, - ARM64_INS_CMPLE_WIDE_PPzZZ_B, - ARM64_INS_CMPLE_WIDE_PPzZZ_H, - ARM64_INS_CMPLE_WIDE_PPzZZ_S, - ARM64_INS_CMPLO_PPzZI_B, - ARM64_INS_CMPLO_PPzZI_D, - ARM64_INS_CMPLO_PPzZI_H, - ARM64_INS_CMPLO_PPzZI_S, - ARM64_INS_CMPLO_WIDE_PPzZZ_B, - ARM64_INS_CMPLO_WIDE_PPzZZ_H, - ARM64_INS_CMPLO_WIDE_PPzZZ_S, - ARM64_INS_CMPLS_PPzZI_B, - ARM64_INS_CMPLS_PPzZI_D, - ARM64_INS_CMPLS_PPzZI_H, - ARM64_INS_CMPLS_PPzZI_S, - ARM64_INS_CMPLS_WIDE_PPzZZ_B, - ARM64_INS_CMPLS_WIDE_PPzZZ_H, - ARM64_INS_CMPLS_WIDE_PPzZZ_S, - ARM64_INS_CMPLT_PPzZI_B, - ARM64_INS_CMPLT_PPzZI_D, - ARM64_INS_CMPLT_PPzZI_H, - ARM64_INS_CMPLT_PPzZI_S, - ARM64_INS_CMPLT_WIDE_PPzZZ_B, - ARM64_INS_CMPLT_WIDE_PPzZZ_H, - ARM64_INS_CMPLT_WIDE_PPzZZ_S, - ARM64_INS_CMPNE_PPzZI_B, - ARM64_INS_CMPNE_PPzZI_D, - ARM64_INS_CMPNE_PPzZI_H, - ARM64_INS_CMPNE_PPzZI_S, - ARM64_INS_CMPNE_PPzZZ_B, - ARM64_INS_CMPNE_PPzZZ_D, - ARM64_INS_CMPNE_PPzZZ_H, - ARM64_INS_CMPNE_PPzZZ_S, - ARM64_INS_CMPNE_WIDE_PPzZZ_B, - ARM64_INS_CMPNE_WIDE_PPzZZ_H, - ARM64_INS_CMPNE_WIDE_PPzZZ_S, - ARM64_INS_CMTSTv16i8, - ARM64_INS_CMTSTv1i64, - ARM64_INS_CMTSTv2i32, - ARM64_INS_CMTSTv2i64, - ARM64_INS_CMTSTv4i16, - ARM64_INS_CMTSTv4i32, - ARM64_INS_CMTSTv8i16, - ARM64_INS_CMTSTv8i8, - ARM64_INS_CNOT_ZPmZ_B, - ARM64_INS_CNOT_ZPmZ_D, - ARM64_INS_CNOT_ZPmZ_H, - ARM64_INS_CNOT_ZPmZ_S, - ARM64_INS_CNTB_XPiI, - ARM64_INS_CNTD_XPiI, - ARM64_INS_CNTH_XPiI, - ARM64_INS_CNTP_XPP_B, - ARM64_INS_CNTP_XPP_D, - ARM64_INS_CNTP_XPP_H, - ARM64_INS_CNTP_XPP_S, - ARM64_INS_CNTW_XPiI, - ARM64_INS_CNT_ZPmZ_B, - ARM64_INS_CNT_ZPmZ_D, - ARM64_INS_CNT_ZPmZ_H, - ARM64_INS_CNT_ZPmZ_S, - ARM64_INS_CNTv16i8, - ARM64_INS_CNTv8i8, - ARM64_INS_COMPACT_ZPZ_D, - ARM64_INS_COMPACT_ZPZ_S, - ARM64_INS_CPY_ZPmI_B, - ARM64_INS_CPY_ZPmI_D, - ARM64_INS_CPY_ZPmI_H, - ARM64_INS_CPY_ZPmI_S, - ARM64_INS_CPY_ZPmR_B, - ARM64_INS_CPY_ZPmR_D, - ARM64_INS_CPY_ZPmR_H, - ARM64_INS_CPY_ZPmR_S, - ARM64_INS_CPY_ZPmV_B, - ARM64_INS_CPY_ZPmV_D, - ARM64_INS_CPY_ZPmV_H, - ARM64_INS_CPY_ZPmV_S, - ARM64_INS_CPY_ZPzI_B, - ARM64_INS_CPY_ZPzI_D, - ARM64_INS_CPY_ZPzI_H, - ARM64_INS_CPY_ZPzI_S, - ARM64_INS_CPYi16, - ARM64_INS_CPYi32, - ARM64_INS_CPYi64, - ARM64_INS_CPYi8, - ARM64_INS_CRC32Brr, - ARM64_INS_CRC32CBrr, - ARM64_INS_CRC32CHrr, - ARM64_INS_CRC32CWrr, - ARM64_INS_CRC32CXrr, - ARM64_INS_CRC32Hrr, - ARM64_INS_CRC32Wrr, - ARM64_INS_CRC32Xrr, - ARM64_INS_CSELWr, - ARM64_INS_CSELXr, - ARM64_INS_CSINCWr, - ARM64_INS_CSINCXr, - ARM64_INS_CSINVWr, - ARM64_INS_CSINVXr, - ARM64_INS_CSNEGWr, - ARM64_INS_CSNEGXr, - ARM64_INS_CTERMEQ_WW, - ARM64_INS_CTERMEQ_XX, - ARM64_INS_CTERMNE_WW, - ARM64_INS_CTERMNE_XX, - ARM64_INS_DECB_XPiI, - ARM64_INS_DECD_XPiI, - ARM64_INS_DECD_ZPiI, - ARM64_INS_DECH_XPiI, - ARM64_INS_DECH_ZPiI, - ARM64_INS_DECP_XP_B, - ARM64_INS_DECP_XP_D, - ARM64_INS_DECP_XP_H, - ARM64_INS_DECP_XP_S, - ARM64_INS_DECP_ZP_D, - ARM64_INS_DECP_ZP_H, - ARM64_INS_DECP_ZP_S, - ARM64_INS_DECW_XPiI, - ARM64_INS_DECW_ZPiI, - ARM64_INS_DUPM_ZI, - ARM64_INS_DUP_ZI_B, - ARM64_INS_DUP_ZI_D, - ARM64_INS_DUP_ZI_H, - ARM64_INS_DUP_ZI_S, - ARM64_INS_DUP_ZR_B, - ARM64_INS_DUP_ZR_D, - ARM64_INS_DUP_ZR_H, - ARM64_INS_DUP_ZR_S, - ARM64_INS_DUP_ZZI_B, - ARM64_INS_DUP_ZZI_D, - ARM64_INS_DUP_ZZI_H, - ARM64_INS_DUP_ZZI_Q, - ARM64_INS_DUP_ZZI_S, - ARM64_INS_DUPv16i8gpr, - ARM64_INS_DUPv16i8lane, - ARM64_INS_DUPv2i32gpr, - ARM64_INS_DUPv2i32lane, - ARM64_INS_DUPv2i64gpr, - ARM64_INS_DUPv2i64lane, - ARM64_INS_DUPv4i16gpr, - ARM64_INS_DUPv4i16lane, - ARM64_INS_DUPv4i32gpr, - ARM64_INS_DUPv4i32lane, - ARM64_INS_DUPv8i16gpr, - ARM64_INS_DUPv8i16lane, - ARM64_INS_DUPv8i8gpr, - ARM64_INS_DUPv8i8lane, - ARM64_INS_EONWrs, - ARM64_INS_EONXrs, + ARM64_INS_CINC, + ARM64_INS_CINV, + ARM64_INS_CLASTA, + ARM64_INS_CLASTB, + ARM64_INS_CLREX, + ARM64_INS_CLS, + ARM64_INS_CLZ, + ARM64_INS_CMEQ, + ARM64_INS_CMGE, + ARM64_INS_CMGT, + ARM64_INS_CMHI, + ARM64_INS_CMHS, + ARM64_INS_CMLE, + ARM64_INS_CMLO, + ARM64_INS_CMLS, + ARM64_INS_CMLT, + ARM64_INS_CMN, + ARM64_INS_CMP, + ARM64_INS_CMPEQ, + ARM64_INS_CMPGE, + ARM64_INS_CMPGT, + ARM64_INS_CMPHI, + ARM64_INS_CMPHS, + ARM64_INS_CMPLE, + ARM64_INS_CMPLO, + ARM64_INS_CMPLS, + ARM64_INS_CMPLT, + ARM64_INS_CMPNE, + ARM64_INS_CMTST, + ARM64_INS_CNEG, + ARM64_INS_CNOT, + ARM64_INS_CNT, + ARM64_INS_CNTB, + ARM64_INS_CNTD, + ARM64_INS_CNTH, + ARM64_INS_CNTP, + ARM64_INS_CNTW, + ARM64_INS_COMPACT, + ARM64_INS_CPY, + ARM64_INS_CRC32B, + ARM64_INS_CRC32CB, + ARM64_INS_CRC32CH, + ARM64_INS_CRC32CW, + ARM64_INS_CRC32CX, + ARM64_INS_CRC32H, + ARM64_INS_CRC32W, + ARM64_INS_CRC32X, + ARM64_INS_CSDB, + ARM64_INS_CSEL, + ARM64_INS_CSET, + ARM64_INS_CSETM, + ARM64_INS_CSINC, + ARM64_INS_CSINV, + ARM64_INS_CSNEG, + ARM64_INS_CTERMEQ, + ARM64_INS_CTERMNE, + ARM64_INS_DCPS1, + ARM64_INS_DCPS2, + ARM64_INS_DCPS3, + ARM64_INS_DECB, + ARM64_INS_DECD, + ARM64_INS_DECH, + ARM64_INS_DECP, + ARM64_INS_DECW, + ARM64_INS_DMB, + ARM64_INS_DRPS, + ARM64_INS_DSB, + ARM64_INS_DUP, + ARM64_INS_DUPM, + ARM64_INS_EON, + ARM64_INS_EOR, ARM64_INS_EOR3, - ARM64_INS_EORS_PPzPP, - ARM64_INS_EORV_VPZ_B, - ARM64_INS_EORV_VPZ_D, - ARM64_INS_EORV_VPZ_H, - ARM64_INS_EORV_VPZ_S, - ARM64_INS_EORWri, - ARM64_INS_EORWrs, - ARM64_INS_EORXri, - ARM64_INS_EORXrs, - ARM64_INS_EOR_PPzPP, - ARM64_INS_EOR_ZI, - ARM64_INS_EOR_ZPmZ_B, - ARM64_INS_EOR_ZPmZ_D, - ARM64_INS_EOR_ZPmZ_H, - ARM64_INS_EOR_ZPmZ_S, - ARM64_INS_EOR_ZZZ, - ARM64_INS_EORv16i8, - ARM64_INS_EORv8i8, + ARM64_INS_EORS, + ARM64_INS_EORV, + ARM64_INS_ERET, ARM64_INS_ERETAA, ARM64_INS_ERETAB, - ARM64_INS_EXTRWrri, - ARM64_INS_EXTRXrri, - ARM64_INS_EXT_ZZI, - ARM64_INS_EXTv16i8, - ARM64_INS_EXTv8i8, - ARM64_INS_FABD16, - ARM64_INS_FABD32, - ARM64_INS_FABD64, - ARM64_INS_FABD_ZPmZ_D, - ARM64_INS_FABD_ZPmZ_H, - ARM64_INS_FABD_ZPmZ_S, - ARM64_INS_FABDv2f32, - ARM64_INS_FABDv2f64, - ARM64_INS_FABDv4f16, - ARM64_INS_FABDv4f32, - ARM64_INS_FABDv8f16, - ARM64_INS_FABSDr, - ARM64_INS_FABSHr, - ARM64_INS_FABSSr, - ARM64_INS_FABS_ZPmZ_D, - ARM64_INS_FABS_ZPmZ_H, - ARM64_INS_FABS_ZPmZ_S, - ARM64_INS_FABSv2f32, - ARM64_INS_FABSv2f64, - ARM64_INS_FABSv4f16, - ARM64_INS_FABSv4f32, - ARM64_INS_FABSv8f16, - ARM64_INS_FACGE16, - ARM64_INS_FACGE32, - ARM64_INS_FACGE64, - ARM64_INS_FACGE_PPzZZ_D, - ARM64_INS_FACGE_PPzZZ_H, - ARM64_INS_FACGE_PPzZZ_S, - ARM64_INS_FACGEv2f32, - ARM64_INS_FACGEv2f64, - ARM64_INS_FACGEv4f16, - ARM64_INS_FACGEv4f32, - ARM64_INS_FACGEv8f16, - ARM64_INS_FACGT16, - ARM64_INS_FACGT32, - ARM64_INS_FACGT64, - ARM64_INS_FACGT_PPzZZ_D, - ARM64_INS_FACGT_PPzZZ_H, - ARM64_INS_FACGT_PPzZZ_S, - ARM64_INS_FACGTv2f32, - ARM64_INS_FACGTv2f64, - ARM64_INS_FACGTv4f16, - ARM64_INS_FACGTv4f32, - ARM64_INS_FACGTv8f16, - ARM64_INS_FADDA_VPZ_D, - ARM64_INS_FADDA_VPZ_H, - ARM64_INS_FADDA_VPZ_S, - ARM64_INS_FADDDrr, - ARM64_INS_FADDHrr, - ARM64_INS_FADDPv2f32, - ARM64_INS_FADDPv2f64, - ARM64_INS_FADDPv2i16p, - ARM64_INS_FADDPv2i32p, - ARM64_INS_FADDPv2i64p, - ARM64_INS_FADDPv4f16, - ARM64_INS_FADDPv4f32, - ARM64_INS_FADDPv8f16, - ARM64_INS_FADDSrr, - ARM64_INS_FADDV_VPZ_D, - ARM64_INS_FADDV_VPZ_H, - ARM64_INS_FADDV_VPZ_S, - ARM64_INS_FADD_ZPmI_D, - ARM64_INS_FADD_ZPmI_H, - ARM64_INS_FADD_ZPmI_S, - ARM64_INS_FADD_ZPmZ_D, - ARM64_INS_FADD_ZPmZ_H, - ARM64_INS_FADD_ZPmZ_S, - ARM64_INS_FADD_ZZZ_D, - ARM64_INS_FADD_ZZZ_H, - ARM64_INS_FADD_ZZZ_S, - ARM64_INS_FADDv2f32, - ARM64_INS_FADDv2f64, - ARM64_INS_FADDv4f16, - ARM64_INS_FADDv4f32, - ARM64_INS_FADDv8f16, - ARM64_INS_FCADD_ZPmZ_D, - ARM64_INS_FCADD_ZPmZ_H, - ARM64_INS_FCADD_ZPmZ_S, - ARM64_INS_FCADDv2f32, - ARM64_INS_FCADDv2f64, - ARM64_INS_FCADDv4f16, - ARM64_INS_FCADDv4f32, - ARM64_INS_FCADDv8f16, - ARM64_INS_FCCMPDrr, - ARM64_INS_FCCMPEDrr, - ARM64_INS_FCCMPEHrr, - ARM64_INS_FCCMPESrr, - ARM64_INS_FCCMPHrr, - ARM64_INS_FCCMPSrr, - ARM64_INS_FCMEQ16, - ARM64_INS_FCMEQ32, - ARM64_INS_FCMEQ64, - ARM64_INS_FCMEQ_PPzZ0_D, - ARM64_INS_FCMEQ_PPzZ0_H, - ARM64_INS_FCMEQ_PPzZ0_S, - ARM64_INS_FCMEQ_PPzZZ_D, - ARM64_INS_FCMEQ_PPzZZ_H, - ARM64_INS_FCMEQ_PPzZZ_S, - ARM64_INS_FCMEQv1i16rz, - ARM64_INS_FCMEQv1i32rz, - ARM64_INS_FCMEQv1i64rz, - ARM64_INS_FCMEQv2f32, - ARM64_INS_FCMEQv2f64, - ARM64_INS_FCMEQv2i32rz, - ARM64_INS_FCMEQv2i64rz, - ARM64_INS_FCMEQv4f16, - ARM64_INS_FCMEQv4f32, - ARM64_INS_FCMEQv4i16rz, - ARM64_INS_FCMEQv4i32rz, - ARM64_INS_FCMEQv8f16, - ARM64_INS_FCMEQv8i16rz, - ARM64_INS_FCMGE16, - ARM64_INS_FCMGE32, - ARM64_INS_FCMGE64, - ARM64_INS_FCMGE_PPzZ0_D, - ARM64_INS_FCMGE_PPzZ0_H, - ARM64_INS_FCMGE_PPzZ0_S, - ARM64_INS_FCMGE_PPzZZ_D, - ARM64_INS_FCMGE_PPzZZ_H, - ARM64_INS_FCMGE_PPzZZ_S, - ARM64_INS_FCMGEv1i16rz, - ARM64_INS_FCMGEv1i32rz, - ARM64_INS_FCMGEv1i64rz, - ARM64_INS_FCMGEv2f32, - ARM64_INS_FCMGEv2f64, - ARM64_INS_FCMGEv2i32rz, - ARM64_INS_FCMGEv2i64rz, - ARM64_INS_FCMGEv4f16, - ARM64_INS_FCMGEv4f32, - ARM64_INS_FCMGEv4i16rz, - ARM64_INS_FCMGEv4i32rz, - ARM64_INS_FCMGEv8f16, - ARM64_INS_FCMGEv8i16rz, - ARM64_INS_FCMGT16, - ARM64_INS_FCMGT32, - ARM64_INS_FCMGT64, - ARM64_INS_FCMGT_PPzZ0_D, - ARM64_INS_FCMGT_PPzZ0_H, - ARM64_INS_FCMGT_PPzZ0_S, - ARM64_INS_FCMGT_PPzZZ_D, - ARM64_INS_FCMGT_PPzZZ_H, - ARM64_INS_FCMGT_PPzZZ_S, - ARM64_INS_FCMGTv1i16rz, - ARM64_INS_FCMGTv1i32rz, - ARM64_INS_FCMGTv1i64rz, - ARM64_INS_FCMGTv2f32, - ARM64_INS_FCMGTv2f64, - ARM64_INS_FCMGTv2i32rz, - ARM64_INS_FCMGTv2i64rz, - ARM64_INS_FCMGTv4f16, - ARM64_INS_FCMGTv4f32, - ARM64_INS_FCMGTv4i16rz, - ARM64_INS_FCMGTv4i32rz, - ARM64_INS_FCMGTv8f16, - ARM64_INS_FCMGTv8i16rz, - ARM64_INS_FCMLA_ZPmZZ_D, - ARM64_INS_FCMLA_ZPmZZ_H, - ARM64_INS_FCMLA_ZPmZZ_S, - ARM64_INS_FCMLA_ZZZI_H, - ARM64_INS_FCMLA_ZZZI_S, - ARM64_INS_FCMLAv2f32, - ARM64_INS_FCMLAv2f64, - ARM64_INS_FCMLAv4f16, - ARM64_INS_FCMLAv4f16_indexed, - ARM64_INS_FCMLAv4f32, - ARM64_INS_FCMLAv4f32_indexed, - ARM64_INS_FCMLAv8f16, - ARM64_INS_FCMLAv8f16_indexed, - ARM64_INS_FCMLE_PPzZ0_D, - ARM64_INS_FCMLE_PPzZ0_H, - ARM64_INS_FCMLE_PPzZ0_S, - ARM64_INS_FCMLEv1i16rz, - ARM64_INS_FCMLEv1i32rz, - ARM64_INS_FCMLEv1i64rz, - ARM64_INS_FCMLEv2i32rz, - ARM64_INS_FCMLEv2i64rz, - ARM64_INS_FCMLEv4i16rz, - ARM64_INS_FCMLEv4i32rz, - ARM64_INS_FCMLEv8i16rz, - ARM64_INS_FCMLT_PPzZ0_D, - ARM64_INS_FCMLT_PPzZ0_H, - ARM64_INS_FCMLT_PPzZ0_S, - ARM64_INS_FCMLTv1i16rz, - ARM64_INS_FCMLTv1i32rz, - ARM64_INS_FCMLTv1i64rz, - ARM64_INS_FCMLTv2i32rz, - ARM64_INS_FCMLTv2i64rz, - ARM64_INS_FCMLTv4i16rz, - ARM64_INS_FCMLTv4i32rz, - ARM64_INS_FCMLTv8i16rz, - ARM64_INS_FCMNE_PPzZ0_D, - ARM64_INS_FCMNE_PPzZ0_H, - ARM64_INS_FCMNE_PPzZ0_S, - ARM64_INS_FCMNE_PPzZZ_D, - ARM64_INS_FCMNE_PPzZZ_H, - ARM64_INS_FCMNE_PPzZZ_S, - ARM64_INS_FCMPDri, - ARM64_INS_FCMPDrr, - ARM64_INS_FCMPEDri, - ARM64_INS_FCMPEDrr, - ARM64_INS_FCMPEHri, - ARM64_INS_FCMPEHrr, - ARM64_INS_FCMPESri, - ARM64_INS_FCMPESrr, - ARM64_INS_FCMPHri, - ARM64_INS_FCMPHrr, - ARM64_INS_FCMPSri, - ARM64_INS_FCMPSrr, - ARM64_INS_FCMUO_PPzZZ_D, - ARM64_INS_FCMUO_PPzZZ_H, - ARM64_INS_FCMUO_PPzZZ_S, - ARM64_INS_FCPY_ZPmI_D, - ARM64_INS_FCPY_ZPmI_H, - ARM64_INS_FCPY_ZPmI_S, - ARM64_INS_FCSELDrrr, - ARM64_INS_FCSELHrrr, - ARM64_INS_FCSELSrrr, - ARM64_INS_FCVTASUWDr, - ARM64_INS_FCVTASUWHr, - ARM64_INS_FCVTASUWSr, - ARM64_INS_FCVTASUXDr, - ARM64_INS_FCVTASUXHr, - ARM64_INS_FCVTASUXSr, - ARM64_INS_FCVTASv1f16, - ARM64_INS_FCVTASv1i32, - ARM64_INS_FCVTASv1i64, - ARM64_INS_FCVTASv2f32, - ARM64_INS_FCVTASv2f64, - ARM64_INS_FCVTASv4f16, - ARM64_INS_FCVTASv4f32, - ARM64_INS_FCVTASv8f16, - ARM64_INS_FCVTAUUWDr, - ARM64_INS_FCVTAUUWHr, - ARM64_INS_FCVTAUUWSr, - ARM64_INS_FCVTAUUXDr, - ARM64_INS_FCVTAUUXHr, - ARM64_INS_FCVTAUUXSr, - ARM64_INS_FCVTAUv1f16, - ARM64_INS_FCVTAUv1i32, - ARM64_INS_FCVTAUv1i64, - ARM64_INS_FCVTAUv2f32, - ARM64_INS_FCVTAUv2f64, - ARM64_INS_FCVTAUv4f16, - ARM64_INS_FCVTAUv4f32, - ARM64_INS_FCVTAUv8f16, - ARM64_INS_FCVTDHr, - ARM64_INS_FCVTDSr, - ARM64_INS_FCVTHDr, - ARM64_INS_FCVTHSr, - ARM64_INS_FCVTLv2i32, - ARM64_INS_FCVTLv4i16, - ARM64_INS_FCVTLv4i32, - ARM64_INS_FCVTLv8i16, - ARM64_INS_FCVTMSUWDr, - ARM64_INS_FCVTMSUWHr, - ARM64_INS_FCVTMSUWSr, - ARM64_INS_FCVTMSUXDr, - ARM64_INS_FCVTMSUXHr, - ARM64_INS_FCVTMSUXSr, - ARM64_INS_FCVTMSv1f16, - ARM64_INS_FCVTMSv1i32, - ARM64_INS_FCVTMSv1i64, - ARM64_INS_FCVTMSv2f32, - ARM64_INS_FCVTMSv2f64, - ARM64_INS_FCVTMSv4f16, - ARM64_INS_FCVTMSv4f32, - ARM64_INS_FCVTMSv8f16, - ARM64_INS_FCVTMUUWDr, - ARM64_INS_FCVTMUUWHr, - ARM64_INS_FCVTMUUWSr, - ARM64_INS_FCVTMUUXDr, - ARM64_INS_FCVTMUUXHr, - ARM64_INS_FCVTMUUXSr, - ARM64_INS_FCVTMUv1f16, - ARM64_INS_FCVTMUv1i32, - ARM64_INS_FCVTMUv1i64, - ARM64_INS_FCVTMUv2f32, - ARM64_INS_FCVTMUv2f64, - ARM64_INS_FCVTMUv4f16, - ARM64_INS_FCVTMUv4f32, - ARM64_INS_FCVTMUv8f16, - ARM64_INS_FCVTNSUWDr, - ARM64_INS_FCVTNSUWHr, - ARM64_INS_FCVTNSUWSr, - ARM64_INS_FCVTNSUXDr, - ARM64_INS_FCVTNSUXHr, - ARM64_INS_FCVTNSUXSr, - ARM64_INS_FCVTNSv1f16, - ARM64_INS_FCVTNSv1i32, - ARM64_INS_FCVTNSv1i64, - ARM64_INS_FCVTNSv2f32, - ARM64_INS_FCVTNSv2f64, - ARM64_INS_FCVTNSv4f16, - ARM64_INS_FCVTNSv4f32, - ARM64_INS_FCVTNSv8f16, - ARM64_INS_FCVTNUUWDr, - ARM64_INS_FCVTNUUWHr, - ARM64_INS_FCVTNUUWSr, - ARM64_INS_FCVTNUUXDr, - ARM64_INS_FCVTNUUXHr, - ARM64_INS_FCVTNUUXSr, - ARM64_INS_FCVTNUv1f16, - ARM64_INS_FCVTNUv1i32, - ARM64_INS_FCVTNUv1i64, - ARM64_INS_FCVTNUv2f32, - ARM64_INS_FCVTNUv2f64, - ARM64_INS_FCVTNUv4f16, - ARM64_INS_FCVTNUv4f32, - ARM64_INS_FCVTNUv8f16, - ARM64_INS_FCVTNv2i32, - ARM64_INS_FCVTNv4i16, - ARM64_INS_FCVTNv4i32, - ARM64_INS_FCVTNv8i16, - ARM64_INS_FCVTPSUWDr, - ARM64_INS_FCVTPSUWHr, - ARM64_INS_FCVTPSUWSr, - ARM64_INS_FCVTPSUXDr, - ARM64_INS_FCVTPSUXHr, - ARM64_INS_FCVTPSUXSr, - ARM64_INS_FCVTPSv1f16, - ARM64_INS_FCVTPSv1i32, - ARM64_INS_FCVTPSv1i64, - ARM64_INS_FCVTPSv2f32, - ARM64_INS_FCVTPSv2f64, - ARM64_INS_FCVTPSv4f16, - ARM64_INS_FCVTPSv4f32, - ARM64_INS_FCVTPSv8f16, - ARM64_INS_FCVTPUUWDr, - ARM64_INS_FCVTPUUWHr, - ARM64_INS_FCVTPUUWSr, - ARM64_INS_FCVTPUUXDr, - ARM64_INS_FCVTPUUXHr, - ARM64_INS_FCVTPUUXSr, - ARM64_INS_FCVTPUv1f16, - ARM64_INS_FCVTPUv1i32, - ARM64_INS_FCVTPUv1i64, - ARM64_INS_FCVTPUv2f32, - ARM64_INS_FCVTPUv2f64, - ARM64_INS_FCVTPUv4f16, - ARM64_INS_FCVTPUv4f32, - ARM64_INS_FCVTPUv8f16, - ARM64_INS_FCVTSDr, - ARM64_INS_FCVTSHr, - ARM64_INS_FCVTXNv1i64, - ARM64_INS_FCVTXNv2f32, - ARM64_INS_FCVTXNv4f32, - ARM64_INS_FCVTZSSWDri, - ARM64_INS_FCVTZSSWHri, - ARM64_INS_FCVTZSSWSri, - ARM64_INS_FCVTZSSXDri, - ARM64_INS_FCVTZSSXHri, - ARM64_INS_FCVTZSSXSri, - ARM64_INS_FCVTZSUWDr, - ARM64_INS_FCVTZSUWHr, - ARM64_INS_FCVTZSUWSr, - ARM64_INS_FCVTZSUXDr, - ARM64_INS_FCVTZSUXHr, - ARM64_INS_FCVTZSUXSr, - ARM64_INS_FCVTZS_ZPmZ_DtoD, - ARM64_INS_FCVTZS_ZPmZ_DtoS, - ARM64_INS_FCVTZS_ZPmZ_HtoD, - ARM64_INS_FCVTZS_ZPmZ_HtoH, - ARM64_INS_FCVTZS_ZPmZ_HtoS, - ARM64_INS_FCVTZS_ZPmZ_StoD, - ARM64_INS_FCVTZS_ZPmZ_StoS, - ARM64_INS_FCVTZSd, - ARM64_INS_FCVTZSh, - ARM64_INS_FCVTZSs, - ARM64_INS_FCVTZSv1f16, - ARM64_INS_FCVTZSv1i32, - ARM64_INS_FCVTZSv1i64, - ARM64_INS_FCVTZSv2f32, - ARM64_INS_FCVTZSv2f64, - ARM64_INS_FCVTZSv2i32_shift, - ARM64_INS_FCVTZSv2i64_shift, - ARM64_INS_FCVTZSv4f16, - ARM64_INS_FCVTZSv4f32, - ARM64_INS_FCVTZSv4i16_shift, - ARM64_INS_FCVTZSv4i32_shift, - ARM64_INS_FCVTZSv8f16, - ARM64_INS_FCVTZSv8i16_shift, - ARM64_INS_FCVTZUSWDri, - ARM64_INS_FCVTZUSWHri, - ARM64_INS_FCVTZUSWSri, - ARM64_INS_FCVTZUSXDri, - ARM64_INS_FCVTZUSXHri, - ARM64_INS_FCVTZUSXSri, - ARM64_INS_FCVTZUUWDr, - ARM64_INS_FCVTZUUWHr, - ARM64_INS_FCVTZUUWSr, - ARM64_INS_FCVTZUUXDr, - ARM64_INS_FCVTZUUXHr, - ARM64_INS_FCVTZUUXSr, - ARM64_INS_FCVTZU_ZPmZ_DtoD, - ARM64_INS_FCVTZU_ZPmZ_DtoS, - ARM64_INS_FCVTZU_ZPmZ_HtoD, - ARM64_INS_FCVTZU_ZPmZ_HtoH, - ARM64_INS_FCVTZU_ZPmZ_HtoS, - ARM64_INS_FCVTZU_ZPmZ_StoD, - ARM64_INS_FCVTZU_ZPmZ_StoS, - ARM64_INS_FCVTZUd, - ARM64_INS_FCVTZUh, - ARM64_INS_FCVTZUs, - ARM64_INS_FCVTZUv1f16, - ARM64_INS_FCVTZUv1i32, - ARM64_INS_FCVTZUv1i64, - ARM64_INS_FCVTZUv2f32, - ARM64_INS_FCVTZUv2f64, - ARM64_INS_FCVTZUv2i32_shift, - ARM64_INS_FCVTZUv2i64_shift, - ARM64_INS_FCVTZUv4f16, - ARM64_INS_FCVTZUv4f32, - ARM64_INS_FCVTZUv4i16_shift, - ARM64_INS_FCVTZUv4i32_shift, - ARM64_INS_FCVTZUv8f16, - ARM64_INS_FCVTZUv8i16_shift, - ARM64_INS_FCVT_ZPmZ_DtoH, - ARM64_INS_FCVT_ZPmZ_DtoS, - ARM64_INS_FCVT_ZPmZ_HtoD, - ARM64_INS_FCVT_ZPmZ_HtoS, - ARM64_INS_FCVT_ZPmZ_StoD, - ARM64_INS_FCVT_ZPmZ_StoH, - ARM64_INS_FDIVDrr, - ARM64_INS_FDIVHrr, - ARM64_INS_FDIVR_ZPmZ_D, - ARM64_INS_FDIVR_ZPmZ_H, - ARM64_INS_FDIVR_ZPmZ_S, - ARM64_INS_FDIVSrr, - ARM64_INS_FDIV_ZPmZ_D, - ARM64_INS_FDIV_ZPmZ_H, - ARM64_INS_FDIV_ZPmZ_S, - ARM64_INS_FDIVv2f32, - ARM64_INS_FDIVv2f64, - ARM64_INS_FDIVv4f16, - ARM64_INS_FDIVv4f32, - ARM64_INS_FDIVv8f16, - ARM64_INS_FDUP_ZI_D, - ARM64_INS_FDUP_ZI_H, - ARM64_INS_FDUP_ZI_S, - ARM64_INS_FEXPA_ZZ_D, - ARM64_INS_FEXPA_ZZ_H, - ARM64_INS_FEXPA_ZZ_S, + ARM64_INS_ESB, + ARM64_INS_EXT, + ARM64_INS_EXTR, + ARM64_INS_FABD, + ARM64_INS_FABS, + ARM64_INS_FACGE, + ARM64_INS_FACGT, + ARM64_INS_FACLE, + ARM64_INS_FACLT, + ARM64_INS_FADD, + ARM64_INS_FADDA, + ARM64_INS_FADDP, + ARM64_INS_FADDV, + ARM64_INS_FCADD, + ARM64_INS_FCCMP, + ARM64_INS_FCCMPE, + ARM64_INS_FCMEQ, + ARM64_INS_FCMGE, + ARM64_INS_FCMGT, + ARM64_INS_FCMLA, + ARM64_INS_FCMLE, + ARM64_INS_FCMLT, + ARM64_INS_FCMNE, + ARM64_INS_FCMP, + ARM64_INS_FCMPE, + ARM64_INS_FCMUO, + ARM64_INS_FCPY, + ARM64_INS_FCSEL, + ARM64_INS_FCVT, + ARM64_INS_FCVTAS, + ARM64_INS_FCVTAU, + ARM64_INS_FCVTL, + ARM64_INS_FCVTL2, + ARM64_INS_FCVTMS, + ARM64_INS_FCVTMU, + ARM64_INS_FCVTN, + ARM64_INS_FCVTN2, + ARM64_INS_FCVTNS, + ARM64_INS_FCVTNU, + ARM64_INS_FCVTPS, + ARM64_INS_FCVTPU, + ARM64_INS_FCVTXN, + ARM64_INS_FCVTXN2, + ARM64_INS_FCVTZS, + ARM64_INS_FCVTZU, + ARM64_INS_FDIV, + ARM64_INS_FDIVR, + ARM64_INS_FDUP, + ARM64_INS_FEXPA, ARM64_INS_FJCVTZS, - ARM64_INS_FMADDDrrr, - ARM64_INS_FMADDHrrr, - ARM64_INS_FMADDSrrr, - ARM64_INS_FMAD_ZPmZZ_D, - ARM64_INS_FMAD_ZPmZZ_H, - ARM64_INS_FMAD_ZPmZZ_S, - ARM64_INS_FMAXDrr, - ARM64_INS_FMAXHrr, - ARM64_INS_FMAXNMDrr, - ARM64_INS_FMAXNMHrr, - ARM64_INS_FMAXNMPv2f32, - ARM64_INS_FMAXNMPv2f64, - ARM64_INS_FMAXNMPv2i16p, - ARM64_INS_FMAXNMPv2i32p, - ARM64_INS_FMAXNMPv2i64p, - ARM64_INS_FMAXNMPv4f16, - ARM64_INS_FMAXNMPv4f32, - ARM64_INS_FMAXNMPv8f16, - ARM64_INS_FMAXNMSrr, - ARM64_INS_FMAXNMV_VPZ_D, - ARM64_INS_FMAXNMV_VPZ_H, - ARM64_INS_FMAXNMV_VPZ_S, - ARM64_INS_FMAXNMVv4i16v, - ARM64_INS_FMAXNMVv4i32v, - ARM64_INS_FMAXNMVv8i16v, - ARM64_INS_FMAXNM_ZPmI_D, - ARM64_INS_FMAXNM_ZPmI_H, - ARM64_INS_FMAXNM_ZPmI_S, - ARM64_INS_FMAXNM_ZPmZ_D, - ARM64_INS_FMAXNM_ZPmZ_H, - ARM64_INS_FMAXNM_ZPmZ_S, - ARM64_INS_FMAXNMv2f32, - ARM64_INS_FMAXNMv2f64, - ARM64_INS_FMAXNMv4f16, - ARM64_INS_FMAXNMv4f32, - ARM64_INS_FMAXNMv8f16, - ARM64_INS_FMAXPv2f32, - ARM64_INS_FMAXPv2f64, - ARM64_INS_FMAXPv2i16p, - ARM64_INS_FMAXPv2i32p, - ARM64_INS_FMAXPv2i64p, - ARM64_INS_FMAXPv4f16, - ARM64_INS_FMAXPv4f32, - ARM64_INS_FMAXPv8f16, - ARM64_INS_FMAXSrr, - ARM64_INS_FMAXV_VPZ_D, - ARM64_INS_FMAXV_VPZ_H, - ARM64_INS_FMAXV_VPZ_S, - ARM64_INS_FMAXVv4i16v, - ARM64_INS_FMAXVv4i32v, - ARM64_INS_FMAXVv8i16v, - ARM64_INS_FMAX_ZPmI_D, - ARM64_INS_FMAX_ZPmI_H, - ARM64_INS_FMAX_ZPmI_S, - ARM64_INS_FMAX_ZPmZ_D, - ARM64_INS_FMAX_ZPmZ_H, - ARM64_INS_FMAX_ZPmZ_S, - ARM64_INS_FMAXv2f32, - ARM64_INS_FMAXv2f64, - ARM64_INS_FMAXv4f16, - ARM64_INS_FMAXv4f32, - ARM64_INS_FMAXv8f16, - ARM64_INS_FMINDrr, - ARM64_INS_FMINHrr, - ARM64_INS_FMINNMDrr, - ARM64_INS_FMINNMHrr, - ARM64_INS_FMINNMPv2f32, - ARM64_INS_FMINNMPv2f64, - ARM64_INS_FMINNMPv2i16p, - ARM64_INS_FMINNMPv2i32p, - ARM64_INS_FMINNMPv2i64p, - ARM64_INS_FMINNMPv4f16, - ARM64_INS_FMINNMPv4f32, - ARM64_INS_FMINNMPv8f16, - ARM64_INS_FMINNMSrr, - ARM64_INS_FMINNMV_VPZ_D, - ARM64_INS_FMINNMV_VPZ_H, - ARM64_INS_FMINNMV_VPZ_S, - ARM64_INS_FMINNMVv4i16v, - ARM64_INS_FMINNMVv4i32v, - ARM64_INS_FMINNMVv8i16v, - ARM64_INS_FMINNM_ZPmI_D, - ARM64_INS_FMINNM_ZPmI_H, - ARM64_INS_FMINNM_ZPmI_S, - ARM64_INS_FMINNM_ZPmZ_D, - ARM64_INS_FMINNM_ZPmZ_H, - ARM64_INS_FMINNM_ZPmZ_S, - ARM64_INS_FMINNMv2f32, - ARM64_INS_FMINNMv2f64, - ARM64_INS_FMINNMv4f16, - ARM64_INS_FMINNMv4f32, - ARM64_INS_FMINNMv8f16, - ARM64_INS_FMINPv2f32, - ARM64_INS_FMINPv2f64, - ARM64_INS_FMINPv2i16p, - ARM64_INS_FMINPv2i32p, - ARM64_INS_FMINPv2i64p, - ARM64_INS_FMINPv4f16, - ARM64_INS_FMINPv4f32, - ARM64_INS_FMINPv8f16, - ARM64_INS_FMINSrr, - ARM64_INS_FMINV_VPZ_D, - ARM64_INS_FMINV_VPZ_H, - ARM64_INS_FMINV_VPZ_S, - ARM64_INS_FMINVv4i16v, - ARM64_INS_FMINVv4i32v, - ARM64_INS_FMINVv8i16v, - ARM64_INS_FMIN_ZPmI_D, - ARM64_INS_FMIN_ZPmI_H, - ARM64_INS_FMIN_ZPmI_S, - ARM64_INS_FMIN_ZPmZ_D, - ARM64_INS_FMIN_ZPmZ_H, - ARM64_INS_FMIN_ZPmZ_S, - ARM64_INS_FMINv2f32, - ARM64_INS_FMINv2f64, - ARM64_INS_FMINv4f16, - ARM64_INS_FMINv4f32, - ARM64_INS_FMINv8f16, - ARM64_INS_FMLA_ZPmZZ_D, - ARM64_INS_FMLA_ZPmZZ_H, - ARM64_INS_FMLA_ZPmZZ_S, - ARM64_INS_FMLA_ZZZI_D, - ARM64_INS_FMLA_ZZZI_H, - ARM64_INS_FMLA_ZZZI_S, - ARM64_INS_FMLAv1i16_indexed, - ARM64_INS_FMLAv1i32_indexed, - ARM64_INS_FMLAv1i64_indexed, - ARM64_INS_FMLAv2f32, - ARM64_INS_FMLAv2f64, - ARM64_INS_FMLAv2i32_indexed, - ARM64_INS_FMLAv2i64_indexed, - ARM64_INS_FMLAv4f16, - ARM64_INS_FMLAv4f32, - ARM64_INS_FMLAv4i16_indexed, - ARM64_INS_FMLAv4i32_indexed, - ARM64_INS_FMLAv8f16, - ARM64_INS_FMLAv8i16_indexed, - ARM64_INS_FMLS_ZPmZZ_D, - ARM64_INS_FMLS_ZPmZZ_H, - ARM64_INS_FMLS_ZPmZZ_S, - ARM64_INS_FMLS_ZZZI_D, - ARM64_INS_FMLS_ZZZI_H, - ARM64_INS_FMLS_ZZZI_S, - ARM64_INS_FMLSv1i16_indexed, - ARM64_INS_FMLSv1i32_indexed, - ARM64_INS_FMLSv1i64_indexed, - ARM64_INS_FMLSv2f32, - ARM64_INS_FMLSv2f64, - ARM64_INS_FMLSv2i32_indexed, - ARM64_INS_FMLSv2i64_indexed, - ARM64_INS_FMLSv4f16, - ARM64_INS_FMLSv4f32, - ARM64_INS_FMLSv4i16_indexed, - ARM64_INS_FMLSv4i32_indexed, - ARM64_INS_FMLSv8f16, - ARM64_INS_FMLSv8i16_indexed, - ARM64_INS_FMOVDXHighr, - ARM64_INS_FMOVDXr, - ARM64_INS_FMOVDi, - ARM64_INS_FMOVDr, - ARM64_INS_FMOVHWr, - ARM64_INS_FMOVHXr, - ARM64_INS_FMOVHi, - ARM64_INS_FMOVHr, - ARM64_INS_FMOVSWr, - ARM64_INS_FMOVSi, - ARM64_INS_FMOVSr, - ARM64_INS_FMOVWHr, - ARM64_INS_FMOVWSr, - ARM64_INS_FMOVXDHighr, - ARM64_INS_FMOVXDr, - ARM64_INS_FMOVXHr, - ARM64_INS_FMOVv2f32_ns, - ARM64_INS_FMOVv2f64_ns, - ARM64_INS_FMOVv4f16_ns, - ARM64_INS_FMOVv4f32_ns, - ARM64_INS_FMOVv8f16_ns, - ARM64_INS_FMSB_ZPmZZ_D, - ARM64_INS_FMSB_ZPmZZ_H, - ARM64_INS_FMSB_ZPmZZ_S, - ARM64_INS_FMSUBDrrr, - ARM64_INS_FMSUBHrrr, - ARM64_INS_FMSUBSrrr, - ARM64_INS_FMULDrr, - ARM64_INS_FMULHrr, - ARM64_INS_FMULSrr, - ARM64_INS_FMULX16, - ARM64_INS_FMULX32, - ARM64_INS_FMULX64, - ARM64_INS_FMULX_ZPmZ_D, - ARM64_INS_FMULX_ZPmZ_H, - ARM64_INS_FMULX_ZPmZ_S, - ARM64_INS_FMULXv1i16_indexed, - ARM64_INS_FMULXv1i32_indexed, - ARM64_INS_FMULXv1i64_indexed, - ARM64_INS_FMULXv2f32, - ARM64_INS_FMULXv2f64, - ARM64_INS_FMULXv2i32_indexed, - ARM64_INS_FMULXv2i64_indexed, - ARM64_INS_FMULXv4f16, - ARM64_INS_FMULXv4f32, - ARM64_INS_FMULXv4i16_indexed, - ARM64_INS_FMULXv4i32_indexed, - ARM64_INS_FMULXv8f16, - ARM64_INS_FMULXv8i16_indexed, - ARM64_INS_FMUL_ZPmI_D, - ARM64_INS_FMUL_ZPmI_H, - ARM64_INS_FMUL_ZPmI_S, - ARM64_INS_FMUL_ZPmZ_D, - ARM64_INS_FMUL_ZPmZ_H, - ARM64_INS_FMUL_ZPmZ_S, - ARM64_INS_FMUL_ZZZI_D, - ARM64_INS_FMUL_ZZZI_H, - ARM64_INS_FMUL_ZZZI_S, - ARM64_INS_FMUL_ZZZ_D, - ARM64_INS_FMUL_ZZZ_H, - ARM64_INS_FMUL_ZZZ_S, - ARM64_INS_FMULv1i16_indexed, - ARM64_INS_FMULv1i32_indexed, - ARM64_INS_FMULv1i64_indexed, - ARM64_INS_FMULv2f32, - ARM64_INS_FMULv2f64, - ARM64_INS_FMULv2i32_indexed, - ARM64_INS_FMULv2i64_indexed, - ARM64_INS_FMULv4f16, - ARM64_INS_FMULv4f32, - ARM64_INS_FMULv4i16_indexed, - ARM64_INS_FMULv4i32_indexed, - ARM64_INS_FMULv8f16, - ARM64_INS_FMULv8i16_indexed, - ARM64_INS_FNEGDr, - ARM64_INS_FNEGHr, - ARM64_INS_FNEGSr, - ARM64_INS_FNEG_ZPmZ_D, - ARM64_INS_FNEG_ZPmZ_H, - ARM64_INS_FNEG_ZPmZ_S, - ARM64_INS_FNEGv2f32, - ARM64_INS_FNEGv2f64, - ARM64_INS_FNEGv4f16, - ARM64_INS_FNEGv4f32, - ARM64_INS_FNEGv8f16, - ARM64_INS_FNMADDDrrr, - ARM64_INS_FNMADDHrrr, - ARM64_INS_FNMADDSrrr, - ARM64_INS_FNMAD_ZPmZZ_D, - ARM64_INS_FNMAD_ZPmZZ_H, - ARM64_INS_FNMAD_ZPmZZ_S, - ARM64_INS_FNMLA_ZPmZZ_D, - ARM64_INS_FNMLA_ZPmZZ_H, - ARM64_INS_FNMLA_ZPmZZ_S, - ARM64_INS_FNMLS_ZPmZZ_D, - ARM64_INS_FNMLS_ZPmZZ_H, - ARM64_INS_FNMLS_ZPmZZ_S, - ARM64_INS_FNMSB_ZPmZZ_D, - ARM64_INS_FNMSB_ZPmZZ_H, - ARM64_INS_FNMSB_ZPmZZ_S, - ARM64_INS_FNMSUBDrrr, - ARM64_INS_FNMSUBHrrr, - ARM64_INS_FNMSUBSrrr, - ARM64_INS_FNMULDrr, - ARM64_INS_FNMULHrr, - ARM64_INS_FNMULSrr, - ARM64_INS_FRECPE_ZZ_D, - ARM64_INS_FRECPE_ZZ_H, - ARM64_INS_FRECPE_ZZ_S, - ARM64_INS_FRECPEv1f16, - ARM64_INS_FRECPEv1i32, - ARM64_INS_FRECPEv1i64, - ARM64_INS_FRECPEv2f32, - ARM64_INS_FRECPEv2f64, - ARM64_INS_FRECPEv4f16, - ARM64_INS_FRECPEv4f32, - ARM64_INS_FRECPEv8f16, - ARM64_INS_FRECPS16, - ARM64_INS_FRECPS32, - ARM64_INS_FRECPS64, - ARM64_INS_FRECPS_ZZZ_D, - ARM64_INS_FRECPS_ZZZ_H, - ARM64_INS_FRECPS_ZZZ_S, - ARM64_INS_FRECPSv2f32, - ARM64_INS_FRECPSv2f64, - ARM64_INS_FRECPSv4f16, - ARM64_INS_FRECPSv4f32, - ARM64_INS_FRECPSv8f16, - ARM64_INS_FRECPX_ZPmZ_D, - ARM64_INS_FRECPX_ZPmZ_H, - ARM64_INS_FRECPX_ZPmZ_S, - ARM64_INS_FRECPXv1f16, - ARM64_INS_FRECPXv1i32, - ARM64_INS_FRECPXv1i64, - ARM64_INS_FRINTADr, - ARM64_INS_FRINTAHr, - ARM64_INS_FRINTASr, - ARM64_INS_FRINTA_ZPmZ_D, - ARM64_INS_FRINTA_ZPmZ_H, - ARM64_INS_FRINTA_ZPmZ_S, - ARM64_INS_FRINTAv2f32, - ARM64_INS_FRINTAv2f64, - ARM64_INS_FRINTAv4f16, - ARM64_INS_FRINTAv4f32, - ARM64_INS_FRINTAv8f16, - ARM64_INS_FRINTIDr, - ARM64_INS_FRINTIHr, - ARM64_INS_FRINTISr, - ARM64_INS_FRINTI_ZPmZ_D, - ARM64_INS_FRINTI_ZPmZ_H, - ARM64_INS_FRINTI_ZPmZ_S, - ARM64_INS_FRINTIv2f32, - ARM64_INS_FRINTIv2f64, - ARM64_INS_FRINTIv4f16, - ARM64_INS_FRINTIv4f32, - ARM64_INS_FRINTIv8f16, - ARM64_INS_FRINTMDr, - ARM64_INS_FRINTMHr, - ARM64_INS_FRINTMSr, - ARM64_INS_FRINTM_ZPmZ_D, - ARM64_INS_FRINTM_ZPmZ_H, - ARM64_INS_FRINTM_ZPmZ_S, - ARM64_INS_FRINTMv2f32, - ARM64_INS_FRINTMv2f64, - ARM64_INS_FRINTMv4f16, - ARM64_INS_FRINTMv4f32, - ARM64_INS_FRINTMv8f16, - ARM64_INS_FRINTNDr, - ARM64_INS_FRINTNHr, - ARM64_INS_FRINTNSr, - ARM64_INS_FRINTN_ZPmZ_D, - ARM64_INS_FRINTN_ZPmZ_H, - ARM64_INS_FRINTN_ZPmZ_S, - ARM64_INS_FRINTNv2f32, - ARM64_INS_FRINTNv2f64, - ARM64_INS_FRINTNv4f16, - ARM64_INS_FRINTNv4f32, - ARM64_INS_FRINTNv8f16, - ARM64_INS_FRINTPDr, - ARM64_INS_FRINTPHr, - ARM64_INS_FRINTPSr, - ARM64_INS_FRINTP_ZPmZ_D, - ARM64_INS_FRINTP_ZPmZ_H, - ARM64_INS_FRINTP_ZPmZ_S, - ARM64_INS_FRINTPv2f32, - ARM64_INS_FRINTPv2f64, - ARM64_INS_FRINTPv4f16, - ARM64_INS_FRINTPv4f32, - ARM64_INS_FRINTPv8f16, - ARM64_INS_FRINTXDr, - ARM64_INS_FRINTXHr, - ARM64_INS_FRINTXSr, - ARM64_INS_FRINTX_ZPmZ_D, - ARM64_INS_FRINTX_ZPmZ_H, - ARM64_INS_FRINTX_ZPmZ_S, - ARM64_INS_FRINTXv2f32, - ARM64_INS_FRINTXv2f64, - ARM64_INS_FRINTXv4f16, - ARM64_INS_FRINTXv4f32, - ARM64_INS_FRINTXv8f16, - ARM64_INS_FRINTZDr, - ARM64_INS_FRINTZHr, - ARM64_INS_FRINTZSr, - ARM64_INS_FRINTZ_ZPmZ_D, - ARM64_INS_FRINTZ_ZPmZ_H, - ARM64_INS_FRINTZ_ZPmZ_S, - ARM64_INS_FRINTZv2f32, - ARM64_INS_FRINTZv2f64, - ARM64_INS_FRINTZv4f16, - ARM64_INS_FRINTZv4f32, - ARM64_INS_FRINTZv8f16, - ARM64_INS_FRSQRTE_ZZ_D, - ARM64_INS_FRSQRTE_ZZ_H, - ARM64_INS_FRSQRTE_ZZ_S, - ARM64_INS_FRSQRTEv1f16, - ARM64_INS_FRSQRTEv1i32, - ARM64_INS_FRSQRTEv1i64, - ARM64_INS_FRSQRTEv2f32, - ARM64_INS_FRSQRTEv2f64, - ARM64_INS_FRSQRTEv4f16, - ARM64_INS_FRSQRTEv4f32, - ARM64_INS_FRSQRTEv8f16, - ARM64_INS_FRSQRTS16, - ARM64_INS_FRSQRTS32, - ARM64_INS_FRSQRTS64, - ARM64_INS_FRSQRTS_ZZZ_D, - ARM64_INS_FRSQRTS_ZZZ_H, - ARM64_INS_FRSQRTS_ZZZ_S, - ARM64_INS_FRSQRTSv2f32, - ARM64_INS_FRSQRTSv2f64, - ARM64_INS_FRSQRTSv4f16, - ARM64_INS_FRSQRTSv4f32, - ARM64_INS_FRSQRTSv8f16, - ARM64_INS_FSCALE_ZPmZ_D, - ARM64_INS_FSCALE_ZPmZ_H, - ARM64_INS_FSCALE_ZPmZ_S, - ARM64_INS_FSQRTDr, - ARM64_INS_FSQRTHr, - ARM64_INS_FSQRTSr, - ARM64_INS_FSQRT_ZPmZ_D, - ARM64_INS_FSQRT_ZPmZ_H, - ARM64_INS_FSQRT_ZPmZ_S, - ARM64_INS_FSQRTv2f32, - ARM64_INS_FSQRTv2f64, - ARM64_INS_FSQRTv4f16, - ARM64_INS_FSQRTv4f32, - ARM64_INS_FSQRTv8f16, - ARM64_INS_FSUBDrr, - ARM64_INS_FSUBHrr, - ARM64_INS_FSUBR_ZPmI_D, - ARM64_INS_FSUBR_ZPmI_H, - ARM64_INS_FSUBR_ZPmI_S, - ARM64_INS_FSUBR_ZPmZ_D, - ARM64_INS_FSUBR_ZPmZ_H, - ARM64_INS_FSUBR_ZPmZ_S, - ARM64_INS_FSUBSrr, - ARM64_INS_FSUB_ZPmI_D, - ARM64_INS_FSUB_ZPmI_H, - ARM64_INS_FSUB_ZPmI_S, - ARM64_INS_FSUB_ZPmZ_D, - ARM64_INS_FSUB_ZPmZ_H, - ARM64_INS_FSUB_ZPmZ_S, - ARM64_INS_FSUB_ZZZ_D, - ARM64_INS_FSUB_ZZZ_H, - ARM64_INS_FSUB_ZZZ_S, - ARM64_INS_FSUBv2f32, - ARM64_INS_FSUBv2f64, - ARM64_INS_FSUBv4f16, - ARM64_INS_FSUBv4f32, - ARM64_INS_FSUBv8f16, - ARM64_INS_FTMAD_ZZI_D, - ARM64_INS_FTMAD_ZZI_H, - ARM64_INS_FTMAD_ZZI_S, - ARM64_INS_FTSMUL_ZZZ_D, - ARM64_INS_FTSMUL_ZZZ_H, - ARM64_INS_FTSMUL_ZZZ_S, - ARM64_INS_FTSSEL_ZZZ_D, - ARM64_INS_FTSSEL_ZZZ_H, - ARM64_INS_FTSSEL_ZZZ_S, - ARM64_INS_GLD1B_D_IMM_REAL, - ARM64_INS_GLD1B_D_REAL, - ARM64_INS_GLD1B_D_SXTW_REAL, - ARM64_INS_GLD1B_D_UXTW_REAL, - ARM64_INS_GLD1B_S_IMM_REAL, - ARM64_INS_GLD1B_S_SXTW_REAL, - ARM64_INS_GLD1B_S_UXTW_REAL, - ARM64_INS_GLD1D_IMM_REAL, - ARM64_INS_GLD1D_REAL, - ARM64_INS_GLD1D_SCALED_REAL, - ARM64_INS_GLD1D_SXTW_REAL, - ARM64_INS_GLD1D_SXTW_SCALED_REAL, - ARM64_INS_GLD1D_UXTW_REAL, - ARM64_INS_GLD1D_UXTW_SCALED_REAL, - ARM64_INS_GLD1H_D_IMM_REAL, - ARM64_INS_GLD1H_D_REAL, - ARM64_INS_GLD1H_D_SCALED_REAL, - ARM64_INS_GLD1H_D_SXTW_REAL, - ARM64_INS_GLD1H_D_SXTW_SCALED_REAL, - ARM64_INS_GLD1H_D_UXTW_REAL, - ARM64_INS_GLD1H_D_UXTW_SCALED_REAL, - ARM64_INS_GLD1H_S_IMM_REAL, - ARM64_INS_GLD1H_S_SXTW_REAL, - ARM64_INS_GLD1H_S_SXTW_SCALED_REAL, - ARM64_INS_GLD1H_S_UXTW_REAL, - ARM64_INS_GLD1H_S_UXTW_SCALED_REAL, - ARM64_INS_GLD1SB_D_IMM_REAL, - ARM64_INS_GLD1SB_D_REAL, - ARM64_INS_GLD1SB_D_SXTW_REAL, - ARM64_INS_GLD1SB_D_UXTW_REAL, - ARM64_INS_GLD1SB_S_IMM_REAL, - ARM64_INS_GLD1SB_S_SXTW_REAL, - ARM64_INS_GLD1SB_S_UXTW_REAL, - ARM64_INS_GLD1SH_D_IMM_REAL, - ARM64_INS_GLD1SH_D_REAL, - ARM64_INS_GLD1SH_D_SCALED_REAL, - ARM64_INS_GLD1SH_D_SXTW_REAL, - ARM64_INS_GLD1SH_D_SXTW_SCALED_REAL, - ARM64_INS_GLD1SH_D_UXTW_REAL, - ARM64_INS_GLD1SH_D_UXTW_SCALED_REAL, - ARM64_INS_GLD1SH_S_IMM_REAL, - ARM64_INS_GLD1SH_S_SXTW_REAL, - ARM64_INS_GLD1SH_S_SXTW_SCALED_REAL, - ARM64_INS_GLD1SH_S_UXTW_REAL, - ARM64_INS_GLD1SH_S_UXTW_SCALED_REAL, - ARM64_INS_GLD1SW_D_IMM_REAL, - ARM64_INS_GLD1SW_D_REAL, - ARM64_INS_GLD1SW_D_SCALED_REAL, - ARM64_INS_GLD1SW_D_SXTW_REAL, - ARM64_INS_GLD1SW_D_SXTW_SCALED_REAL, - ARM64_INS_GLD1SW_D_UXTW_REAL, - ARM64_INS_GLD1SW_D_UXTW_SCALED_REAL, - ARM64_INS_GLD1W_D_IMM_REAL, - ARM64_INS_GLD1W_D_REAL, - ARM64_INS_GLD1W_D_SCALED_REAL, - ARM64_INS_GLD1W_D_SXTW_REAL, - ARM64_INS_GLD1W_D_SXTW_SCALED_REAL, - ARM64_INS_GLD1W_D_UXTW_REAL, - ARM64_INS_GLD1W_D_UXTW_SCALED_REAL, - ARM64_INS_GLD1W_IMM_REAL, - ARM64_INS_GLD1W_SXTW_REAL, - ARM64_INS_GLD1W_SXTW_SCALED_REAL, - ARM64_INS_GLD1W_UXTW_REAL, - ARM64_INS_GLD1W_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1B_D_IMM_REAL, - ARM64_INS_GLDFF1B_D_REAL, - ARM64_INS_GLDFF1B_D_SXTW_REAL, - ARM64_INS_GLDFF1B_D_UXTW_REAL, - ARM64_INS_GLDFF1B_S_IMM_REAL, - ARM64_INS_GLDFF1B_S_SXTW_REAL, - ARM64_INS_GLDFF1B_S_UXTW_REAL, - ARM64_INS_GLDFF1D_IMM_REAL, - ARM64_INS_GLDFF1D_REAL, - ARM64_INS_GLDFF1D_SCALED_REAL, - ARM64_INS_GLDFF1D_SXTW_REAL, - ARM64_INS_GLDFF1D_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1D_UXTW_REAL, - ARM64_INS_GLDFF1D_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1H_D_IMM_REAL, - ARM64_INS_GLDFF1H_D_REAL, - ARM64_INS_GLDFF1H_D_SCALED_REAL, - ARM64_INS_GLDFF1H_D_SXTW_REAL, - ARM64_INS_GLDFF1H_D_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1H_D_UXTW_REAL, - ARM64_INS_GLDFF1H_D_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1H_S_IMM_REAL, - ARM64_INS_GLDFF1H_S_SXTW_REAL, - ARM64_INS_GLDFF1H_S_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1H_S_UXTW_REAL, - ARM64_INS_GLDFF1H_S_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1SB_D_IMM_REAL, - ARM64_INS_GLDFF1SB_D_REAL, - ARM64_INS_GLDFF1SB_D_SXTW_REAL, - ARM64_INS_GLDFF1SB_D_UXTW_REAL, - ARM64_INS_GLDFF1SB_S_IMM_REAL, - ARM64_INS_GLDFF1SB_S_SXTW_REAL, - ARM64_INS_GLDFF1SB_S_UXTW_REAL, - ARM64_INS_GLDFF1SH_D_IMM_REAL, - ARM64_INS_GLDFF1SH_D_REAL, - ARM64_INS_GLDFF1SH_D_SCALED_REAL, - ARM64_INS_GLDFF1SH_D_SXTW_REAL, - ARM64_INS_GLDFF1SH_D_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1SH_D_UXTW_REAL, - ARM64_INS_GLDFF1SH_D_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1SH_S_IMM_REAL, - ARM64_INS_GLDFF1SH_S_SXTW_REAL, - ARM64_INS_GLDFF1SH_S_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1SH_S_UXTW_REAL, - ARM64_INS_GLDFF1SH_S_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1SW_D_IMM_REAL, - ARM64_INS_GLDFF1SW_D_REAL, - ARM64_INS_GLDFF1SW_D_SCALED_REAL, - ARM64_INS_GLDFF1SW_D_SXTW_REAL, - ARM64_INS_GLDFF1SW_D_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1SW_D_UXTW_REAL, - ARM64_INS_GLDFF1SW_D_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1W_D_IMM_REAL, - ARM64_INS_GLDFF1W_D_REAL, - ARM64_INS_GLDFF1W_D_SCALED_REAL, - ARM64_INS_GLDFF1W_D_SXTW_REAL, - ARM64_INS_GLDFF1W_D_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1W_D_UXTW_REAL, - ARM64_INS_GLDFF1W_D_UXTW_SCALED_REAL, - ARM64_INS_GLDFF1W_IMM_REAL, - ARM64_INS_GLDFF1W_SXTW_REAL, - ARM64_INS_GLDFF1W_SXTW_SCALED_REAL, - ARM64_INS_GLDFF1W_UXTW_REAL, - ARM64_INS_GLDFF1W_UXTW_SCALED_REAL, - ARM64_INS_INCB_XPiI, - ARM64_INS_INCD_XPiI, - ARM64_INS_INCD_ZPiI, - ARM64_INS_INCH_XPiI, - ARM64_INS_INCH_ZPiI, - ARM64_INS_INCP_XP_B, - ARM64_INS_INCP_XP_D, - ARM64_INS_INCP_XP_H, - ARM64_INS_INCP_XP_S, - ARM64_INS_INCP_ZP_D, - ARM64_INS_INCP_ZP_H, - ARM64_INS_INCP_ZP_S, - ARM64_INS_INCW_XPiI, - ARM64_INS_INCW_ZPiI, - ARM64_INS_INDEX_II_B, - ARM64_INS_INDEX_II_D, - ARM64_INS_INDEX_II_H, - ARM64_INS_INDEX_II_S, - ARM64_INS_INDEX_IR_B, - ARM64_INS_INDEX_IR_D, - ARM64_INS_INDEX_IR_H, - ARM64_INS_INDEX_IR_S, - ARM64_INS_INDEX_RI_B, - ARM64_INS_INDEX_RI_D, - ARM64_INS_INDEX_RI_H, - ARM64_INS_INDEX_RI_S, - ARM64_INS_INDEX_RR_B, - ARM64_INS_INDEX_RR_D, - ARM64_INS_INDEX_RR_H, - ARM64_INS_INDEX_RR_S, - ARM64_INS_INSR_ZR_B, - ARM64_INS_INSR_ZR_D, - ARM64_INS_INSR_ZR_H, - ARM64_INS_INSR_ZR_S, - ARM64_INS_INSR_ZV_B, - ARM64_INS_INSR_ZV_D, - ARM64_INS_INSR_ZV_H, - ARM64_INS_INSR_ZV_S, - ARM64_INS_INSvi16gpr, - ARM64_INS_INSvi16lane, - ARM64_INS_INSvi32gpr, - ARM64_INS_INSvi32lane, - ARM64_INS_INSvi64gpr, - ARM64_INS_INSvi64lane, - ARM64_INS_INSvi8gpr, - ARM64_INS_INSvi8lane, - ARM64_INS_LASTA_RPZ_B, - ARM64_INS_LASTA_RPZ_D, - ARM64_INS_LASTA_RPZ_H, - ARM64_INS_LASTA_RPZ_S, - ARM64_INS_LASTA_VPZ_B, - ARM64_INS_LASTA_VPZ_D, - ARM64_INS_LASTA_VPZ_H, - ARM64_INS_LASTA_VPZ_S, - ARM64_INS_LASTB_RPZ_B, - ARM64_INS_LASTB_RPZ_D, - ARM64_INS_LASTB_RPZ_H, - ARM64_INS_LASTB_RPZ_S, - ARM64_INS_LASTB_VPZ_B, - ARM64_INS_LASTB_VPZ_D, - ARM64_INS_LASTB_VPZ_H, - ARM64_INS_LASTB_VPZ_S, + ARM64_INS_FMAD, + ARM64_INS_FMADD, + ARM64_INS_FMAX, + ARM64_INS_FMAXNM, + ARM64_INS_FMAXNMP, + ARM64_INS_FMAXNMV, + ARM64_INS_FMAXP, + ARM64_INS_FMAXV, + ARM64_INS_FMIN, + ARM64_INS_FMINNM, + ARM64_INS_FMINNMP, + ARM64_INS_FMINNMV, + ARM64_INS_FMINP, + ARM64_INS_FMINV, + ARM64_INS_FMLA, + ARM64_INS_FMLS, + ARM64_INS_FMOV, + ARM64_INS_FMSB, + ARM64_INS_FMSUB, + ARM64_INS_FMUL, + ARM64_INS_FMULX, + ARM64_INS_FNEG, + ARM64_INS_FNMAD, + ARM64_INS_FNMADD, + ARM64_INS_FNMLA, + ARM64_INS_FNMLS, + ARM64_INS_FNMSB, + ARM64_INS_FNMSUB, + ARM64_INS_FNMUL, + ARM64_INS_FRECPE, + ARM64_INS_FRECPS, + ARM64_INS_FRECPX, + ARM64_INS_FRINTA, + ARM64_INS_FRINTI, + ARM64_INS_FRINTM, + ARM64_INS_FRINTN, + ARM64_INS_FRINTP, + ARM64_INS_FRINTX, + ARM64_INS_FRINTZ, + ARM64_INS_FRSQRTE, + ARM64_INS_FRSQRTS, + ARM64_INS_FSCALE, + ARM64_INS_FSQRT, + ARM64_INS_FSUB, + ARM64_INS_FSUBR, + ARM64_INS_FTMAD, + ARM64_INS_FTSMUL, + ARM64_INS_FTSSEL, + ARM64_INS_HINT, + ARM64_INS_HLT, + ARM64_INS_HVC, + ARM64_INS_INCB, + ARM64_INS_INCD, + ARM64_INS_INCH, + ARM64_INS_INCP, + ARM64_INS_INCW, + ARM64_INS_INDEX, + ARM64_INS_INS, + ARM64_INS_INSR, + ARM64_INS_ISB, + ARM64_INS_LASTA, + ARM64_INS_LASTB, + ARM64_INS_LD1, ARM64_INS_LD1B, - ARM64_INS_LD1B_D, - ARM64_INS_LD1B_D_IMM_REAL, - ARM64_INS_LD1B_H, - ARM64_INS_LD1B_H_IMM_REAL, - ARM64_INS_LD1B_IMM_REAL, - ARM64_INS_LD1B_S, - ARM64_INS_LD1B_S_IMM_REAL, ARM64_INS_LD1D, - ARM64_INS_LD1D_IMM_REAL, - ARM64_INS_LD1Fourv16b, - ARM64_INS_LD1Fourv16b_POST, - ARM64_INS_LD1Fourv1d, - ARM64_INS_LD1Fourv1d_POST, - ARM64_INS_LD1Fourv2d, - ARM64_INS_LD1Fourv2d_POST, - ARM64_INS_LD1Fourv2s, - ARM64_INS_LD1Fourv2s_POST, - ARM64_INS_LD1Fourv4h, - ARM64_INS_LD1Fourv4h_POST, - ARM64_INS_LD1Fourv4s, - ARM64_INS_LD1Fourv4s_POST, - ARM64_INS_LD1Fourv8b, - ARM64_INS_LD1Fourv8b_POST, - ARM64_INS_LD1Fourv8h, - ARM64_INS_LD1Fourv8h_POST, ARM64_INS_LD1H, - ARM64_INS_LD1H_D, - ARM64_INS_LD1H_D_IMM_REAL, - ARM64_INS_LD1H_IMM_REAL, - ARM64_INS_LD1H_S, - ARM64_INS_LD1H_S_IMM_REAL, - ARM64_INS_LD1Onev16b, - ARM64_INS_LD1Onev16b_POST, - ARM64_INS_LD1Onev1d, - ARM64_INS_LD1Onev1d_POST, - ARM64_INS_LD1Onev2d, - ARM64_INS_LD1Onev2d_POST, - ARM64_INS_LD1Onev2s, - ARM64_INS_LD1Onev2s_POST, - ARM64_INS_LD1Onev4h, - ARM64_INS_LD1Onev4h_POST, - ARM64_INS_LD1Onev4s, - ARM64_INS_LD1Onev4s_POST, - ARM64_INS_LD1Onev8b, - ARM64_INS_LD1Onev8b_POST, - ARM64_INS_LD1Onev8h, - ARM64_INS_LD1Onev8h_POST, - ARM64_INS_LD1RB_D_IMM, - ARM64_INS_LD1RB_H_IMM, - ARM64_INS_LD1RB_IMM, - ARM64_INS_LD1RB_S_IMM, - ARM64_INS_LD1RD_IMM, - ARM64_INS_LD1RH_D_IMM, - ARM64_INS_LD1RH_IMM, - ARM64_INS_LD1RH_S_IMM, - ARM64_INS_LD1RQ_B, - ARM64_INS_LD1RQ_B_IMM, - ARM64_INS_LD1RQ_D, - ARM64_INS_LD1RQ_D_IMM, - ARM64_INS_LD1RQ_H, - ARM64_INS_LD1RQ_H_IMM, - ARM64_INS_LD1RQ_W, - ARM64_INS_LD1RQ_W_IMM, - ARM64_INS_LD1RSB_D_IMM, - ARM64_INS_LD1RSB_H_IMM, - ARM64_INS_LD1RSB_S_IMM, - ARM64_INS_LD1RSH_D_IMM, - ARM64_INS_LD1RSH_S_IMM, - ARM64_INS_LD1RSW_IMM, - ARM64_INS_LD1RW_D_IMM, - ARM64_INS_LD1RW_IMM, - ARM64_INS_LD1Rv16b, - ARM64_INS_LD1Rv16b_POST, - ARM64_INS_LD1Rv1d, - ARM64_INS_LD1Rv1d_POST, - ARM64_INS_LD1Rv2d, - ARM64_INS_LD1Rv2d_POST, - ARM64_INS_LD1Rv2s, - ARM64_INS_LD1Rv2s_POST, - ARM64_INS_LD1Rv4h, - ARM64_INS_LD1Rv4h_POST, - ARM64_INS_LD1Rv4s, - ARM64_INS_LD1Rv4s_POST, - ARM64_INS_LD1Rv8b, - ARM64_INS_LD1Rv8b_POST, - ARM64_INS_LD1Rv8h, - ARM64_INS_LD1Rv8h_POST, - ARM64_INS_LD1SB_D, - ARM64_INS_LD1SB_D_IMM_REAL, - ARM64_INS_LD1SB_H, - ARM64_INS_LD1SB_H_IMM_REAL, - ARM64_INS_LD1SB_S, - ARM64_INS_LD1SB_S_IMM_REAL, - ARM64_INS_LD1SH_D, - ARM64_INS_LD1SH_D_IMM_REAL, - ARM64_INS_LD1SH_S, - ARM64_INS_LD1SH_S_IMM_REAL, - ARM64_INS_LD1SW_D, - ARM64_INS_LD1SW_D_IMM_REAL, - ARM64_INS_LD1Threev16b, - ARM64_INS_LD1Threev16b_POST, - ARM64_INS_LD1Threev1d, - ARM64_INS_LD1Threev1d_POST, - ARM64_INS_LD1Threev2d, - ARM64_INS_LD1Threev2d_POST, - ARM64_INS_LD1Threev2s, - ARM64_INS_LD1Threev2s_POST, - ARM64_INS_LD1Threev4h, - ARM64_INS_LD1Threev4h_POST, - ARM64_INS_LD1Threev4s, - ARM64_INS_LD1Threev4s_POST, - ARM64_INS_LD1Threev8b, - ARM64_INS_LD1Threev8b_POST, - ARM64_INS_LD1Threev8h, - ARM64_INS_LD1Threev8h_POST, - ARM64_INS_LD1Twov16b, - ARM64_INS_LD1Twov16b_POST, - ARM64_INS_LD1Twov1d, - ARM64_INS_LD1Twov1d_POST, - ARM64_INS_LD1Twov2d, - ARM64_INS_LD1Twov2d_POST, - ARM64_INS_LD1Twov2s, - ARM64_INS_LD1Twov2s_POST, - ARM64_INS_LD1Twov4h, - ARM64_INS_LD1Twov4h_POST, - ARM64_INS_LD1Twov4s, - ARM64_INS_LD1Twov4s_POST, - ARM64_INS_LD1Twov8b, - ARM64_INS_LD1Twov8b_POST, - ARM64_INS_LD1Twov8h, - ARM64_INS_LD1Twov8h_POST, + ARM64_INS_LD1R, + ARM64_INS_LD1RB, + ARM64_INS_LD1RD, + ARM64_INS_LD1RH, + ARM64_INS_LD1RQB, + ARM64_INS_LD1RQD, + ARM64_INS_LD1RQH, + ARM64_INS_LD1RQW, + ARM64_INS_LD1RSB, + ARM64_INS_LD1RSH, + ARM64_INS_LD1RSW, + ARM64_INS_LD1RW, + ARM64_INS_LD1SB, + ARM64_INS_LD1SH, + ARM64_INS_LD1SW, ARM64_INS_LD1W, - ARM64_INS_LD1W_D, - ARM64_INS_LD1W_D_IMM_REAL, - ARM64_INS_LD1W_IMM_REAL, - ARM64_INS_LD1i16, - ARM64_INS_LD1i16_POST, - ARM64_INS_LD1i32, - ARM64_INS_LD1i32_POST, - ARM64_INS_LD1i64, - ARM64_INS_LD1i64_POST, - ARM64_INS_LD1i8, - ARM64_INS_LD1i8_POST, + ARM64_INS_LD2, ARM64_INS_LD2B, - ARM64_INS_LD2B_IMM, ARM64_INS_LD2D, - ARM64_INS_LD2D_IMM, ARM64_INS_LD2H, - ARM64_INS_LD2H_IMM, - ARM64_INS_LD2Rv16b, - ARM64_INS_LD2Rv16b_POST, - ARM64_INS_LD2Rv1d, - ARM64_INS_LD2Rv1d_POST, - ARM64_INS_LD2Rv2d, - ARM64_INS_LD2Rv2d_POST, - ARM64_INS_LD2Rv2s, - ARM64_INS_LD2Rv2s_POST, - ARM64_INS_LD2Rv4h, - ARM64_INS_LD2Rv4h_POST, - ARM64_INS_LD2Rv4s, - ARM64_INS_LD2Rv4s_POST, - ARM64_INS_LD2Rv8b, - ARM64_INS_LD2Rv8b_POST, - ARM64_INS_LD2Rv8h, - ARM64_INS_LD2Rv8h_POST, - ARM64_INS_LD2Twov16b, - ARM64_INS_LD2Twov16b_POST, - ARM64_INS_LD2Twov2d, - ARM64_INS_LD2Twov2d_POST, - ARM64_INS_LD2Twov2s, - ARM64_INS_LD2Twov2s_POST, - ARM64_INS_LD2Twov4h, - ARM64_INS_LD2Twov4h_POST, - ARM64_INS_LD2Twov4s, - ARM64_INS_LD2Twov4s_POST, - ARM64_INS_LD2Twov8b, - ARM64_INS_LD2Twov8b_POST, - ARM64_INS_LD2Twov8h, - ARM64_INS_LD2Twov8h_POST, + ARM64_INS_LD2R, ARM64_INS_LD2W, - ARM64_INS_LD2W_IMM, - ARM64_INS_LD2i16, - ARM64_INS_LD2i16_POST, - ARM64_INS_LD2i32, - ARM64_INS_LD2i32_POST, - ARM64_INS_LD2i64, - ARM64_INS_LD2i64_POST, - ARM64_INS_LD2i8, - ARM64_INS_LD2i8_POST, + ARM64_INS_LD3, ARM64_INS_LD3B, - ARM64_INS_LD3B_IMM, ARM64_INS_LD3D, - ARM64_INS_LD3D_IMM, ARM64_INS_LD3H, - ARM64_INS_LD3H_IMM, - ARM64_INS_LD3Rv16b, - ARM64_INS_LD3Rv16b_POST, - ARM64_INS_LD3Rv1d, - ARM64_INS_LD3Rv1d_POST, - ARM64_INS_LD3Rv2d, - ARM64_INS_LD3Rv2d_POST, - ARM64_INS_LD3Rv2s, - ARM64_INS_LD3Rv2s_POST, - ARM64_INS_LD3Rv4h, - ARM64_INS_LD3Rv4h_POST, - ARM64_INS_LD3Rv4s, - ARM64_INS_LD3Rv4s_POST, - ARM64_INS_LD3Rv8b, - ARM64_INS_LD3Rv8b_POST, - ARM64_INS_LD3Rv8h, - ARM64_INS_LD3Rv8h_POST, - ARM64_INS_LD3Threev16b, - ARM64_INS_LD3Threev16b_POST, - ARM64_INS_LD3Threev2d, - ARM64_INS_LD3Threev2d_POST, - ARM64_INS_LD3Threev2s, - ARM64_INS_LD3Threev2s_POST, - ARM64_INS_LD3Threev4h, - ARM64_INS_LD3Threev4h_POST, - ARM64_INS_LD3Threev4s, - ARM64_INS_LD3Threev4s_POST, - ARM64_INS_LD3Threev8b, - ARM64_INS_LD3Threev8b_POST, - ARM64_INS_LD3Threev8h, - ARM64_INS_LD3Threev8h_POST, + ARM64_INS_LD3R, ARM64_INS_LD3W, - ARM64_INS_LD3W_IMM, - ARM64_INS_LD3i16, - ARM64_INS_LD3i16_POST, - ARM64_INS_LD3i32, - ARM64_INS_LD3i32_POST, - ARM64_INS_LD3i64, - ARM64_INS_LD3i64_POST, - ARM64_INS_LD3i8, - ARM64_INS_LD3i8_POST, + ARM64_INS_LD4, ARM64_INS_LD4B, - ARM64_INS_LD4B_IMM, ARM64_INS_LD4D, - ARM64_INS_LD4D_IMM, - ARM64_INS_LD4Fourv16b, - ARM64_INS_LD4Fourv16b_POST, - ARM64_INS_LD4Fourv2d, - ARM64_INS_LD4Fourv2d_POST, - ARM64_INS_LD4Fourv2s, - ARM64_INS_LD4Fourv2s_POST, - ARM64_INS_LD4Fourv4h, - ARM64_INS_LD4Fourv4h_POST, - ARM64_INS_LD4Fourv4s, - ARM64_INS_LD4Fourv4s_POST, - ARM64_INS_LD4Fourv8b, - ARM64_INS_LD4Fourv8b_POST, - ARM64_INS_LD4Fourv8h, - ARM64_INS_LD4Fourv8h_POST, ARM64_INS_LD4H, - ARM64_INS_LD4H_IMM, - ARM64_INS_LD4Rv16b, - ARM64_INS_LD4Rv16b_POST, - ARM64_INS_LD4Rv1d, - ARM64_INS_LD4Rv1d_POST, - ARM64_INS_LD4Rv2d, - ARM64_INS_LD4Rv2d_POST, - ARM64_INS_LD4Rv2s, - ARM64_INS_LD4Rv2s_POST, - ARM64_INS_LD4Rv4h, - ARM64_INS_LD4Rv4h_POST, - ARM64_INS_LD4Rv4s, - ARM64_INS_LD4Rv4s_POST, - ARM64_INS_LD4Rv8b, - ARM64_INS_LD4Rv8b_POST, - ARM64_INS_LD4Rv8h, - ARM64_INS_LD4Rv8h_POST, + ARM64_INS_LD4R, ARM64_INS_LD4W, - ARM64_INS_LD4W_IMM, - ARM64_INS_LD4i16, - ARM64_INS_LD4i16_POST, - ARM64_INS_LD4i32, - ARM64_INS_LD4i32_POST, - ARM64_INS_LD4i64, - ARM64_INS_LD4i64_POST, - ARM64_INS_LD4i8, - ARM64_INS_LD4i8_POST, + ARM64_INS_LDADD, + ARM64_INS_LDADDA, ARM64_INS_LDADDAB, ARM64_INS_LDADDAH, + ARM64_INS_LDADDAL, ARM64_INS_LDADDALB, ARM64_INS_LDADDALH, - ARM64_INS_LDADDALW, - ARM64_INS_LDADDALX, - ARM64_INS_LDADDAW, - ARM64_INS_LDADDAX, ARM64_INS_LDADDB, ARM64_INS_LDADDH, + ARM64_INS_LDADDL, ARM64_INS_LDADDLB, ARM64_INS_LDADDLH, - ARM64_INS_LDADDLW, - ARM64_INS_LDADDLX, - ARM64_INS_LDADDW, - ARM64_INS_LDADDX, + ARM64_INS_LDAPR, ARM64_INS_LDAPRB, ARM64_INS_LDAPRH, - ARM64_INS_LDAPRW, - ARM64_INS_LDAPRX, - ARM64_INS_LDAPURBi, - ARM64_INS_LDAPURHi, - ARM64_INS_LDAPURSBWi, - ARM64_INS_LDAPURSBXi, - ARM64_INS_LDAPURSHWi, - ARM64_INS_LDAPURSHXi, - ARM64_INS_LDAPURSWi, - ARM64_INS_LDAPURXi, - ARM64_INS_LDAPURi, - ARM64_INS_LDARW, - ARM64_INS_LDARX, - ARM64_INS_LDAXPW, - ARM64_INS_LDAXPX, - ARM64_INS_LDAXRW, - ARM64_INS_LDAXRX, + ARM64_INS_LDAPUR, + ARM64_INS_LDAPURB, + ARM64_INS_LDAPURH, + ARM64_INS_LDAPURSB, + ARM64_INS_LDAPURSH, + ARM64_INS_LDAPURSW, + ARM64_INS_LDAR, + ARM64_INS_LDARB, + ARM64_INS_LDARH, + ARM64_INS_LDAXP, + ARM64_INS_LDAXR, + ARM64_INS_LDAXRB, + ARM64_INS_LDAXRH, + ARM64_INS_LDCLR, + ARM64_INS_LDCLRA, ARM64_INS_LDCLRAB, ARM64_INS_LDCLRAH, + ARM64_INS_LDCLRAL, ARM64_INS_LDCLRALB, ARM64_INS_LDCLRALH, - ARM64_INS_LDCLRALW, - ARM64_INS_LDCLRALX, - ARM64_INS_LDCLRAW, - ARM64_INS_LDCLRAX, ARM64_INS_LDCLRB, ARM64_INS_LDCLRH, + ARM64_INS_LDCLRL, ARM64_INS_LDCLRLB, ARM64_INS_LDCLRLH, - ARM64_INS_LDCLRLW, - ARM64_INS_LDCLRLX, - ARM64_INS_LDCLRW, - ARM64_INS_LDCLRX, + ARM64_INS_LDEOR, + ARM64_INS_LDEORA, ARM64_INS_LDEORAB, ARM64_INS_LDEORAH, + ARM64_INS_LDEORAL, ARM64_INS_LDEORALB, ARM64_INS_LDEORALH, - ARM64_INS_LDEORALW, - ARM64_INS_LDEORALX, - ARM64_INS_LDEORAW, - ARM64_INS_LDEORAX, ARM64_INS_LDEORB, ARM64_INS_LDEORH, + ARM64_INS_LDEORL, ARM64_INS_LDEORLB, ARM64_INS_LDEORLH, - ARM64_INS_LDEORLW, - ARM64_INS_LDEORLX, - ARM64_INS_LDEORW, - ARM64_INS_LDEORX, - ARM64_INS_LDFF1B_D_REAL, - ARM64_INS_LDFF1B_H_REAL, - ARM64_INS_LDFF1B_REAL, - ARM64_INS_LDFF1B_S_REAL, - ARM64_INS_LDFF1D_REAL, - ARM64_INS_LDFF1H_D_REAL, - ARM64_INS_LDFF1H_REAL, - ARM64_INS_LDFF1H_S_REAL, - ARM64_INS_LDFF1SB_D_REAL, - ARM64_INS_LDFF1SB_H_REAL, - ARM64_INS_LDFF1SB_S_REAL, - ARM64_INS_LDFF1SH_D_REAL, - ARM64_INS_LDFF1SH_S_REAL, - ARM64_INS_LDFF1SW_D_REAL, - ARM64_INS_LDFF1W_D_REAL, - ARM64_INS_LDFF1W_REAL, + ARM64_INS_LDFF1B, + ARM64_INS_LDFF1D, + ARM64_INS_LDFF1H, + ARM64_INS_LDFF1SB, + ARM64_INS_LDFF1SH, + ARM64_INS_LDFF1SW, + ARM64_INS_LDFF1W, + ARM64_INS_LDLAR, ARM64_INS_LDLARB, ARM64_INS_LDLARH, - ARM64_INS_LDLARW, - ARM64_INS_LDLARX, - ARM64_INS_LDNF1B_D_IMM_REAL, - ARM64_INS_LDNF1B_H_IMM_REAL, - ARM64_INS_LDNF1B_IMM_REAL, - ARM64_INS_LDNF1B_S_IMM_REAL, - ARM64_INS_LDNF1D_IMM_REAL, - ARM64_INS_LDNF1H_D_IMM_REAL, - ARM64_INS_LDNF1H_IMM_REAL, - ARM64_INS_LDNF1H_S_IMM_REAL, - ARM64_INS_LDNF1SB_D_IMM_REAL, - ARM64_INS_LDNF1SB_H_IMM_REAL, - ARM64_INS_LDNF1SB_S_IMM_REAL, - ARM64_INS_LDNF1SH_D_IMM_REAL, - ARM64_INS_LDNF1SH_S_IMM_REAL, - ARM64_INS_LDNF1SW_D_IMM_REAL, - ARM64_INS_LDNF1W_D_IMM_REAL, - ARM64_INS_LDNF1W_IMM_REAL, - ARM64_INS_LDNPDi, - ARM64_INS_LDNPQi, - ARM64_INS_LDNPSi, - ARM64_INS_LDNPWi, - ARM64_INS_LDNPXi, - ARM64_INS_LDNT1B_ZRI, - ARM64_INS_LDNT1B_ZRR, - ARM64_INS_LDNT1D_ZRI, - ARM64_INS_LDNT1D_ZRR, - ARM64_INS_LDNT1H_ZRI, - ARM64_INS_LDNT1H_ZRR, - ARM64_INS_LDNT1W_ZRI, - ARM64_INS_LDNT1W_ZRR, - ARM64_INS_LDPDi, - ARM64_INS_LDPDpost, - ARM64_INS_LDPDpre, - ARM64_INS_LDPQi, - ARM64_INS_LDPQpost, - ARM64_INS_LDPQpre, - ARM64_INS_LDPSWi, - ARM64_INS_LDPSWpost, - ARM64_INS_LDPSWpre, - ARM64_INS_LDPSi, - ARM64_INS_LDPSpost, - ARM64_INS_LDPSpre, - ARM64_INS_LDPWi, - ARM64_INS_LDPWpost, - ARM64_INS_LDPWpre, - ARM64_INS_LDPXi, - ARM64_INS_LDPXpost, - ARM64_INS_LDPXpre, - ARM64_INS_LDRAAindexed, - ARM64_INS_LDRAAwriteback, - ARM64_INS_LDRABindexed, - ARM64_INS_LDRABwriteback, - ARM64_INS_LDRBBpost, - ARM64_INS_LDRBBpre, - ARM64_INS_LDRBBroW, - ARM64_INS_LDRBBroX, - ARM64_INS_LDRBBui, - ARM64_INS_LDRBpost, - ARM64_INS_LDRBpre, - ARM64_INS_LDRBroW, - ARM64_INS_LDRBroX, - ARM64_INS_LDRBui, - ARM64_INS_LDRDl, - ARM64_INS_LDRDpost, - ARM64_INS_LDRDpre, - ARM64_INS_LDRDroW, - ARM64_INS_LDRDroX, - ARM64_INS_LDRDui, - ARM64_INS_LDRHHpost, - ARM64_INS_LDRHHpre, - ARM64_INS_LDRHHroW, - ARM64_INS_LDRHHroX, - ARM64_INS_LDRHHui, - ARM64_INS_LDRHpost, - ARM64_INS_LDRHpre, - ARM64_INS_LDRHroW, - ARM64_INS_LDRHroX, - ARM64_INS_LDRHui, - ARM64_INS_LDRQl, - ARM64_INS_LDRQpost, - ARM64_INS_LDRQpre, - ARM64_INS_LDRQroW, - ARM64_INS_LDRQroX, - ARM64_INS_LDRQui, - ARM64_INS_LDRSBWpost, - ARM64_INS_LDRSBWpre, - ARM64_INS_LDRSBWroW, - ARM64_INS_LDRSBWroX, - ARM64_INS_LDRSBWui, - ARM64_INS_LDRSBXpost, - ARM64_INS_LDRSBXpre, - ARM64_INS_LDRSBXroW, - ARM64_INS_LDRSBXroX, - ARM64_INS_LDRSBXui, - ARM64_INS_LDRSHWpost, - ARM64_INS_LDRSHWpre, - ARM64_INS_LDRSHWroW, - ARM64_INS_LDRSHWroX, - ARM64_INS_LDRSHWui, - ARM64_INS_LDRSHXpost, - ARM64_INS_LDRSHXpre, - ARM64_INS_LDRSHXroW, - ARM64_INS_LDRSHXroX, - ARM64_INS_LDRSHXui, - ARM64_INS_LDRSWl, - ARM64_INS_LDRSWpost, - ARM64_INS_LDRSWpre, - ARM64_INS_LDRSWroW, - ARM64_INS_LDRSWroX, - ARM64_INS_LDRSWui, - ARM64_INS_LDRSl, - ARM64_INS_LDRSpost, - ARM64_INS_LDRSpre, - ARM64_INS_LDRSroW, - ARM64_INS_LDRSroX, - ARM64_INS_LDRSui, - ARM64_INS_LDRWl, - ARM64_INS_LDRWpost, - ARM64_INS_LDRWpre, - ARM64_INS_LDRWroW, - ARM64_INS_LDRWroX, - ARM64_INS_LDRWui, - ARM64_INS_LDRXl, - ARM64_INS_LDRXpost, - ARM64_INS_LDRXpre, - ARM64_INS_LDRXroW, - ARM64_INS_LDRXroX, - ARM64_INS_LDRXui, - ARM64_INS_LDR_PXI, - ARM64_INS_LDR_ZXI, + ARM64_INS_LDNF1B, + ARM64_INS_LDNF1D, + ARM64_INS_LDNF1H, + ARM64_INS_LDNF1SB, + ARM64_INS_LDNF1SH, + ARM64_INS_LDNF1SW, + ARM64_INS_LDNF1W, + ARM64_INS_LDNP, + ARM64_INS_LDNT1B, + ARM64_INS_LDNT1D, + ARM64_INS_LDNT1H, + ARM64_INS_LDNT1W, + ARM64_INS_LDP, + ARM64_INS_LDPSW, + ARM64_INS_LDR, + ARM64_INS_LDRAA, + ARM64_INS_LDRAB, + ARM64_INS_LDRB, + ARM64_INS_LDRH, + ARM64_INS_LDRSB, + ARM64_INS_LDRSH, + ARM64_INS_LDRSW, + ARM64_INS_LDSET, + ARM64_INS_LDSETA, ARM64_INS_LDSETAB, ARM64_INS_LDSETAH, + ARM64_INS_LDSETAL, ARM64_INS_LDSETALB, ARM64_INS_LDSETALH, - ARM64_INS_LDSETALW, - ARM64_INS_LDSETALX, - ARM64_INS_LDSETAW, - ARM64_INS_LDSETAX, ARM64_INS_LDSETB, ARM64_INS_LDSETH, + ARM64_INS_LDSETL, ARM64_INS_LDSETLB, ARM64_INS_LDSETLH, - ARM64_INS_LDSETLW, - ARM64_INS_LDSETLX, - ARM64_INS_LDSETW, - ARM64_INS_LDSETX, + ARM64_INS_LDSMAX, + ARM64_INS_LDSMAXA, ARM64_INS_LDSMAXAB, ARM64_INS_LDSMAXAH, + ARM64_INS_LDSMAXAL, ARM64_INS_LDSMAXALB, ARM64_INS_LDSMAXALH, - ARM64_INS_LDSMAXALW, - ARM64_INS_LDSMAXALX, - ARM64_INS_LDSMAXAW, - ARM64_INS_LDSMAXAX, ARM64_INS_LDSMAXB, ARM64_INS_LDSMAXH, + ARM64_INS_LDSMAXL, ARM64_INS_LDSMAXLB, ARM64_INS_LDSMAXLH, - ARM64_INS_LDSMAXLW, - ARM64_INS_LDSMAXLX, - ARM64_INS_LDSMAXW, - ARM64_INS_LDSMAXX, + ARM64_INS_LDSMIN, + ARM64_INS_LDSMINA, ARM64_INS_LDSMINAB, ARM64_INS_LDSMINAH, + ARM64_INS_LDSMINAL, ARM64_INS_LDSMINALB, ARM64_INS_LDSMINALH, - ARM64_INS_LDSMINALW, - ARM64_INS_LDSMINALX, - ARM64_INS_LDSMINAW, - ARM64_INS_LDSMINAX, ARM64_INS_LDSMINB, ARM64_INS_LDSMINH, + ARM64_INS_LDSMINL, ARM64_INS_LDSMINLB, ARM64_INS_LDSMINLH, - ARM64_INS_LDSMINLW, - ARM64_INS_LDSMINLX, - ARM64_INS_LDSMINW, - ARM64_INS_LDSMINX, - ARM64_INS_LDTRBi, - ARM64_INS_LDTRHi, - ARM64_INS_LDTRSBWi, - ARM64_INS_LDTRSBXi, - ARM64_INS_LDTRSHWi, - ARM64_INS_LDTRSHXi, - ARM64_INS_LDTRSWi, - ARM64_INS_LDTRWi, - ARM64_INS_LDTRXi, + ARM64_INS_LDTR, + ARM64_INS_LDTRB, + ARM64_INS_LDTRH, + ARM64_INS_LDTRSB, + ARM64_INS_LDTRSH, + ARM64_INS_LDTRSW, + ARM64_INS_LDUMAX, + ARM64_INS_LDUMAXA, ARM64_INS_LDUMAXAB, ARM64_INS_LDUMAXAH, + ARM64_INS_LDUMAXAL, ARM64_INS_LDUMAXALB, ARM64_INS_LDUMAXALH, - ARM64_INS_LDUMAXALW, - ARM64_INS_LDUMAXALX, - ARM64_INS_LDUMAXAW, - ARM64_INS_LDUMAXAX, ARM64_INS_LDUMAXB, ARM64_INS_LDUMAXH, + ARM64_INS_LDUMAXL, ARM64_INS_LDUMAXLB, ARM64_INS_LDUMAXLH, - ARM64_INS_LDUMAXLW, - ARM64_INS_LDUMAXLX, - ARM64_INS_LDUMAXW, - ARM64_INS_LDUMAXX, + ARM64_INS_LDUMIN, + ARM64_INS_LDUMINA, ARM64_INS_LDUMINAB, ARM64_INS_LDUMINAH, + ARM64_INS_LDUMINAL, ARM64_INS_LDUMINALB, ARM64_INS_LDUMINALH, - ARM64_INS_LDUMINALW, - ARM64_INS_LDUMINALX, - ARM64_INS_LDUMINAW, - ARM64_INS_LDUMINAX, ARM64_INS_LDUMINB, ARM64_INS_LDUMINH, + ARM64_INS_LDUMINL, ARM64_INS_LDUMINLB, ARM64_INS_LDUMINLH, - ARM64_INS_LDUMINLW, - ARM64_INS_LDUMINLX, - ARM64_INS_LDUMINW, - ARM64_INS_LDUMINX, - ARM64_INS_LDURBBi, - ARM64_INS_LDURBi, - ARM64_INS_LDURDi, - ARM64_INS_LDURHHi, - ARM64_INS_LDURHi, - ARM64_INS_LDURQi, - ARM64_INS_LDURSBWi, - ARM64_INS_LDURSBXi, - ARM64_INS_LDURSHWi, - ARM64_INS_LDURSHXi, - ARM64_INS_LDURSWi, - ARM64_INS_LDURSi, - ARM64_INS_LDURWi, - ARM64_INS_LDURXi, - ARM64_INS_LDXPW, - ARM64_INS_LDXPX, - ARM64_INS_LDXRW, - ARM64_INS_LDXRX, - ARM64_INS_LSLR_ZPmZ_B, - ARM64_INS_LSLR_ZPmZ_D, - ARM64_INS_LSLR_ZPmZ_H, - ARM64_INS_LSLR_ZPmZ_S, - ARM64_INS_LSLVWr, - ARM64_INS_LSLVXr, - ARM64_INS_LSL_WIDE_ZPmZ_B, - ARM64_INS_LSL_WIDE_ZPmZ_H, - ARM64_INS_LSL_WIDE_ZPmZ_S, - ARM64_INS_LSL_WIDE_ZZZ_B, - ARM64_INS_LSL_WIDE_ZZZ_H, - ARM64_INS_LSL_WIDE_ZZZ_S, - ARM64_INS_LSL_ZPmI_B, - ARM64_INS_LSL_ZPmI_D, - ARM64_INS_LSL_ZPmI_H, - ARM64_INS_LSL_ZPmI_S, - ARM64_INS_LSL_ZPmZ_B, - ARM64_INS_LSL_ZPmZ_D, - ARM64_INS_LSL_ZPmZ_H, - ARM64_INS_LSL_ZPmZ_S, - ARM64_INS_LSL_ZZI_B, - ARM64_INS_LSL_ZZI_D, - ARM64_INS_LSL_ZZI_H, - ARM64_INS_LSL_ZZI_S, - ARM64_INS_LSRR_ZPmZ_B, - ARM64_INS_LSRR_ZPmZ_D, - ARM64_INS_LSRR_ZPmZ_H, - ARM64_INS_LSRR_ZPmZ_S, - ARM64_INS_LSRVWr, - ARM64_INS_LSRVXr, - ARM64_INS_LSR_WIDE_ZPmZ_B, - ARM64_INS_LSR_WIDE_ZPmZ_H, - ARM64_INS_LSR_WIDE_ZPmZ_S, - ARM64_INS_LSR_WIDE_ZZZ_B, - ARM64_INS_LSR_WIDE_ZZZ_H, - ARM64_INS_LSR_WIDE_ZZZ_S, - ARM64_INS_LSR_ZPmI_B, - ARM64_INS_LSR_ZPmI_D, - ARM64_INS_LSR_ZPmI_H, - ARM64_INS_LSR_ZPmI_S, - ARM64_INS_LSR_ZPmZ_B, - ARM64_INS_LSR_ZPmZ_D, - ARM64_INS_LSR_ZPmZ_H, - ARM64_INS_LSR_ZPmZ_S, - ARM64_INS_LSR_ZZI_B, - ARM64_INS_LSR_ZZI_D, - ARM64_INS_LSR_ZZI_H, - ARM64_INS_LSR_ZZI_S, - ARM64_INS_MADDWrrr, - ARM64_INS_MADDXrrr, - ARM64_INS_MAD_ZPmZZ_B, - ARM64_INS_MAD_ZPmZZ_D, - ARM64_INS_MAD_ZPmZZ_H, - ARM64_INS_MAD_ZPmZZ_S, - ARM64_INS_MLA_ZPmZZ_B, - ARM64_INS_MLA_ZPmZZ_D, - ARM64_INS_MLA_ZPmZZ_H, - ARM64_INS_MLA_ZPmZZ_S, - ARM64_INS_MLAv16i8, - ARM64_INS_MLAv2i32, - ARM64_INS_MLAv2i32_indexed, - ARM64_INS_MLAv4i16, - ARM64_INS_MLAv4i16_indexed, - ARM64_INS_MLAv4i32, - ARM64_INS_MLAv4i32_indexed, - ARM64_INS_MLAv8i16, - ARM64_INS_MLAv8i16_indexed, - ARM64_INS_MLAv8i8, - ARM64_INS_MLS_ZPmZZ_B, - ARM64_INS_MLS_ZPmZZ_D, - ARM64_INS_MLS_ZPmZZ_H, - ARM64_INS_MLS_ZPmZZ_S, - ARM64_INS_MLSv16i8, - ARM64_INS_MLSv2i32, - ARM64_INS_MLSv2i32_indexed, - ARM64_INS_MLSv4i16, - ARM64_INS_MLSv4i16_indexed, - ARM64_INS_MLSv4i32, - ARM64_INS_MLSv4i32_indexed, - ARM64_INS_MLSv8i16, - ARM64_INS_MLSv8i16_indexed, - ARM64_INS_MLSv8i8, - ARM64_INS_MOVID, - ARM64_INS_MOVIv16b_ns, - ARM64_INS_MOVIv2d_ns, - ARM64_INS_MOVIv2i32, - ARM64_INS_MOVIv2s_msl, - ARM64_INS_MOVIv4i16, - ARM64_INS_MOVIv4i32, - ARM64_INS_MOVIv4s_msl, - ARM64_INS_MOVIv8b_ns, - ARM64_INS_MOVIv8i16, - ARM64_INS_MOVKWi, - ARM64_INS_MOVKXi, - ARM64_INS_MOVNWi, - ARM64_INS_MOVNXi, - ARM64_INS_MOVPRFX_ZPmZ_B, - ARM64_INS_MOVPRFX_ZPmZ_D, - ARM64_INS_MOVPRFX_ZPmZ_H, - ARM64_INS_MOVPRFX_ZPmZ_S, - ARM64_INS_MOVPRFX_ZPzZ_B, - ARM64_INS_MOVPRFX_ZPzZ_D, - ARM64_INS_MOVPRFX_ZPzZ_H, - ARM64_INS_MOVPRFX_ZPzZ_S, - ARM64_INS_MOVPRFX_ZZ, - ARM64_INS_MOVZWi, - ARM64_INS_MOVZXi, - ARM64_INS_MSB_ZPmZZ_B, - ARM64_INS_MSB_ZPmZZ_D, - ARM64_INS_MSB_ZPmZZ_H, - ARM64_INS_MSB_ZPmZZ_S, - ARM64_INS_MSRpstateImm1, - ARM64_INS_MSRpstateImm4, - ARM64_INS_MSUBWrrr, - ARM64_INS_MSUBXrrr, - ARM64_INS_MUL_ZI_B, - ARM64_INS_MUL_ZI_D, - ARM64_INS_MUL_ZI_H, - ARM64_INS_MUL_ZI_S, - ARM64_INS_MUL_ZPmZ_B, - ARM64_INS_MUL_ZPmZ_D, - ARM64_INS_MUL_ZPmZ_H, - ARM64_INS_MUL_ZPmZ_S, - ARM64_INS_MULv16i8, - ARM64_INS_MULv2i32, - ARM64_INS_MULv2i32_indexed, - ARM64_INS_MULv4i16, - ARM64_INS_MULv4i16_indexed, - ARM64_INS_MULv4i32, - ARM64_INS_MULv4i32_indexed, - ARM64_INS_MULv8i16, - ARM64_INS_MULv8i16_indexed, - ARM64_INS_MULv8i8, - ARM64_INS_MVNIv2i32, - ARM64_INS_MVNIv2s_msl, - ARM64_INS_MVNIv4i16, - ARM64_INS_MVNIv4i32, - ARM64_INS_MVNIv4s_msl, - ARM64_INS_MVNIv8i16, - ARM64_INS_NANDS_PPzPP, - ARM64_INS_NAND_PPzPP, - ARM64_INS_NEG_ZPmZ_B, - ARM64_INS_NEG_ZPmZ_D, - ARM64_INS_NEG_ZPmZ_H, - ARM64_INS_NEG_ZPmZ_S, - ARM64_INS_NEGv16i8, - ARM64_INS_NEGv1i64, - ARM64_INS_NEGv2i32, - ARM64_INS_NEGv2i64, - ARM64_INS_NEGv4i16, - ARM64_INS_NEGv4i32, - ARM64_INS_NEGv8i16, - ARM64_INS_NEGv8i8, - ARM64_INS_NORS_PPzPP, - ARM64_INS_NOR_PPzPP, - ARM64_INS_NOT_ZPmZ_B, - ARM64_INS_NOT_ZPmZ_D, - ARM64_INS_NOT_ZPmZ_H, - ARM64_INS_NOT_ZPmZ_S, - ARM64_INS_NOTv16i8, - ARM64_INS_NOTv8i8, - ARM64_INS_ORNS_PPzPP, - ARM64_INS_ORNWrs, - ARM64_INS_ORNXrs, - ARM64_INS_ORN_PPzPP, - ARM64_INS_ORNv16i8, - ARM64_INS_ORNv8i8, - ARM64_INS_ORRS_PPzPP, - ARM64_INS_ORRWri, - ARM64_INS_ORRWrs, - ARM64_INS_ORRXri, - ARM64_INS_ORRXrs, - ARM64_INS_ORR_PPzPP, - ARM64_INS_ORR_ZI, - ARM64_INS_ORR_ZPmZ_B, - ARM64_INS_ORR_ZPmZ_D, - ARM64_INS_ORR_ZPmZ_H, - ARM64_INS_ORR_ZPmZ_S, - ARM64_INS_ORR_ZZZ, - ARM64_INS_ORRv16i8, - ARM64_INS_ORRv2i32, - ARM64_INS_ORRv4i16, - ARM64_INS_ORRv4i32, - ARM64_INS_ORRv8i16, - ARM64_INS_ORRv8i8, - ARM64_INS_ORV_VPZ_B, - ARM64_INS_ORV_VPZ_D, - ARM64_INS_ORV_VPZ_H, - ARM64_INS_ORV_VPZ_S, + ARM64_INS_LDUR, + ARM64_INS_LDURB, + ARM64_INS_LDURH, + ARM64_INS_LDURSB, + ARM64_INS_LDURSH, + ARM64_INS_LDURSW, + ARM64_INS_LDXP, + ARM64_INS_LDXR, + ARM64_INS_LDXRB, + ARM64_INS_LDXRH, + ARM64_INS_LSL, + ARM64_INS_LSLR, + ARM64_INS_LSLV, + ARM64_INS_LSR, + ARM64_INS_LSRR, + ARM64_INS_LSRV, + ARM64_INS_MAD, + ARM64_INS_MADD, + ARM64_INS_MLA, + ARM64_INS_MLS, + ARM64_INS_MNEG, + ARM64_INS_MOV, + ARM64_INS_MOVI, + ARM64_INS_MOVK, + ARM64_INS_MOVN, + ARM64_INS_MOVPRFX, + ARM64_INS_MOVS, + ARM64_INS_MOVZ, + ARM64_INS_MRS, + ARM64_INS_MSB, + ARM64_INS_MSR, + ARM64_INS_MSUB, + ARM64_INS_MUL, + ARM64_INS_MVN, + ARM64_INS_MVNI, + ARM64_INS_NAND, + ARM64_INS_NANDS, + ARM64_INS_NEG, + ARM64_INS_NEGS, + ARM64_INS_NGC, + ARM64_INS_NGCS, + ARM64_INS_NOP, + ARM64_INS_NOR, + ARM64_INS_NORS, + ARM64_INS_NOT, + ARM64_INS_NOTS, + ARM64_INS_ORN, + ARM64_INS_ORNS, + ARM64_INS_ORR, + ARM64_INS_ORRS, + ARM64_INS_ORV, ARM64_INS_PACDA, ARM64_INS_PACDB, ARM64_INS_PACDZA, @@ -3148,312 +1971,96 @@ typedef enum arm64_insn { ARM64_INS_PACIZA, ARM64_INS_PACIZB, ARM64_INS_PFALSE, - ARM64_INS_PMULLv16i8, - ARM64_INS_PMULLv1i64, - ARM64_INS_PMULLv2i64, - ARM64_INS_PMULLv8i8, - ARM64_INS_PMULv16i8, - ARM64_INS_PMULv8i8, - ARM64_INS_PNEXT_B, - ARM64_INS_PNEXT_D, - ARM64_INS_PNEXT_H, - ARM64_INS_PNEXT_S, - ARM64_INS_PRFB_D_PZI, - ARM64_INS_PRFB_D_SCALED, - ARM64_INS_PRFB_D_SXTW_SCALED, - ARM64_INS_PRFB_D_UXTW_SCALED, - ARM64_INS_PRFB_PRI, - ARM64_INS_PRFB_PRR, - ARM64_INS_PRFB_S_PZI, - ARM64_INS_PRFB_S_SXTW_SCALED, - ARM64_INS_PRFB_S_UXTW_SCALED, - ARM64_INS_PRFD_D_PZI, - ARM64_INS_PRFD_D_SCALED, - ARM64_INS_PRFD_D_SXTW_SCALED, - ARM64_INS_PRFD_D_UXTW_SCALED, - ARM64_INS_PRFD_PRI, - ARM64_INS_PRFD_PRR, - ARM64_INS_PRFD_S_PZI, - ARM64_INS_PRFD_S_SXTW_SCALED, - ARM64_INS_PRFD_S_UXTW_SCALED, - ARM64_INS_PRFH_D_PZI, - ARM64_INS_PRFH_D_SCALED, - ARM64_INS_PRFH_D_SXTW_SCALED, - ARM64_INS_PRFH_D_UXTW_SCALED, - ARM64_INS_PRFH_PRI, - ARM64_INS_PRFH_PRR, - ARM64_INS_PRFH_S_PZI, - ARM64_INS_PRFH_S_SXTW_SCALED, - ARM64_INS_PRFH_S_UXTW_SCALED, - ARM64_INS_PRFMl, - ARM64_INS_PRFMroW, - ARM64_INS_PRFMroX, - ARM64_INS_PRFMui, - ARM64_INS_PRFS_PRR, - ARM64_INS_PRFUMi, - ARM64_INS_PRFW_D_PZI, - ARM64_INS_PRFW_D_SCALED, - ARM64_INS_PRFW_D_SXTW_SCALED, - ARM64_INS_PRFW_D_UXTW_SCALED, - ARM64_INS_PRFW_PRI, - ARM64_INS_PRFW_S_PZI, - ARM64_INS_PRFW_S_SXTW_SCALED, - ARM64_INS_PRFW_S_UXTW_SCALED, - ARM64_INS_PTEST_PP, - ARM64_INS_PTRUES_B, - ARM64_INS_PTRUES_D, - ARM64_INS_PTRUES_H, - ARM64_INS_PTRUES_S, - ARM64_INS_PTRUE_B, - ARM64_INS_PTRUE_D, - ARM64_INS_PTRUE_H, - ARM64_INS_PTRUE_S, - ARM64_INS_PUNPKHI_PP, - ARM64_INS_PUNPKLO_PP, - ARM64_INS_RADDHNv2i64_v2i32, - ARM64_INS_RADDHNv2i64_v4i32, - ARM64_INS_RADDHNv4i32_v4i16, - ARM64_INS_RADDHNv4i32_v8i16, - ARM64_INS_RADDHNv8i16_v16i8, - ARM64_INS_RADDHNv8i16_v8i8, + ARM64_INS_PFIRST, + ARM64_INS_PMUL, + ARM64_INS_PMULL, + ARM64_INS_PMULL2, + ARM64_INS_PNEXT, + ARM64_INS_PRFB, + ARM64_INS_PRFD, + ARM64_INS_PRFH, + ARM64_INS_PRFM, + ARM64_INS_PRFUM, + ARM64_INS_PRFW, + ARM64_INS_PSB, + ARM64_INS_PTEST, + ARM64_INS_PTRUE, + ARM64_INS_PTRUES, + ARM64_INS_PUNPKHI, + ARM64_INS_PUNPKLO, + ARM64_INS_RADDHN, + ARM64_INS_RADDHN2, ARM64_INS_RAX1, - ARM64_INS_RBITWr, - ARM64_INS_RBITXr, - ARM64_INS_RBIT_ZPmZ_B, - ARM64_INS_RBIT_ZPmZ_D, - ARM64_INS_RBIT_ZPmZ_H, - ARM64_INS_RBIT_ZPmZ_S, - ARM64_INS_RBITv16i8, - ARM64_INS_RBITv8i8, - ARM64_INS_RDFFRS_PPz, - ARM64_INS_RDFFR_P, - ARM64_INS_RDFFR_PPz, - ARM64_INS_RDVLI_XI, + ARM64_INS_RBIT, + ARM64_INS_RDFFR, + ARM64_INS_RDFFRS, + ARM64_INS_RDVL, + ARM64_INS_RET, ARM64_INS_RETAA, ARM64_INS_RETAB, - ARM64_INS_REV16Wr, - ARM64_INS_REV16Xr, - ARM64_INS_REV16v16i8, - ARM64_INS_REV16v8i8, - ARM64_INS_REV32Xr, - ARM64_INS_REV32v16i8, - ARM64_INS_REV32v4i16, - ARM64_INS_REV32v8i16, - ARM64_INS_REV32v8i8, - ARM64_INS_REV64v16i8, - ARM64_INS_REV64v2i32, - ARM64_INS_REV64v4i16, - ARM64_INS_REV64v4i32, - ARM64_INS_REV64v8i16, - ARM64_INS_REV64v8i8, - ARM64_INS_REVB_ZPmZ_D, - ARM64_INS_REVB_ZPmZ_H, - ARM64_INS_REVB_ZPmZ_S, - ARM64_INS_REVH_ZPmZ_D, - ARM64_INS_REVH_ZPmZ_S, - ARM64_INS_REVW_ZPmZ_D, - ARM64_INS_REVWr, - ARM64_INS_REVXr, - ARM64_INS_REV_PP_B, - ARM64_INS_REV_PP_D, - ARM64_INS_REV_PP_H, - ARM64_INS_REV_PP_S, - ARM64_INS_REV_ZZ_B, - ARM64_INS_REV_ZZ_D, - ARM64_INS_REV_ZZ_H, - ARM64_INS_REV_ZZ_S, + ARM64_INS_REV, + ARM64_INS_REV16, + ARM64_INS_REV32, + ARM64_INS_REV64, + ARM64_INS_REVB, + ARM64_INS_REVH, + ARM64_INS_REVW, ARM64_INS_RMIF, - ARM64_INS_RORVWr, - ARM64_INS_RORVXr, - ARM64_INS_RSHRNv16i8_shift, - ARM64_INS_RSHRNv2i32_shift, - ARM64_INS_RSHRNv4i16_shift, - ARM64_INS_RSHRNv4i32_shift, - ARM64_INS_RSHRNv8i16_shift, - ARM64_INS_RSHRNv8i8_shift, - ARM64_INS_RSUBHNv2i64_v2i32, - ARM64_INS_RSUBHNv2i64_v4i32, - ARM64_INS_RSUBHNv4i32_v4i16, - ARM64_INS_RSUBHNv4i32_v8i16, - ARM64_INS_RSUBHNv8i16_v16i8, - ARM64_INS_RSUBHNv8i16_v8i8, - ARM64_INS_SABALv16i8_v8i16, - ARM64_INS_SABALv2i32_v2i64, - ARM64_INS_SABALv4i16_v4i32, - ARM64_INS_SABALv4i32_v2i64, - ARM64_INS_SABALv8i16_v4i32, - ARM64_INS_SABALv8i8_v8i16, - ARM64_INS_SABAv16i8, - ARM64_INS_SABAv2i32, - ARM64_INS_SABAv4i16, - ARM64_INS_SABAv4i32, - ARM64_INS_SABAv8i16, - ARM64_INS_SABAv8i8, - ARM64_INS_SABDLv16i8_v8i16, - ARM64_INS_SABDLv2i32_v2i64, - ARM64_INS_SABDLv4i16_v4i32, - ARM64_INS_SABDLv4i32_v2i64, - ARM64_INS_SABDLv8i16_v4i32, - ARM64_INS_SABDLv8i8_v8i16, - ARM64_INS_SABD_ZPmZ_B, - ARM64_INS_SABD_ZPmZ_D, - ARM64_INS_SABD_ZPmZ_H, - ARM64_INS_SABD_ZPmZ_S, - ARM64_INS_SABDv16i8, - ARM64_INS_SABDv2i32, - ARM64_INS_SABDv4i16, - ARM64_INS_SABDv4i32, - ARM64_INS_SABDv8i16, - ARM64_INS_SABDv8i8, - ARM64_INS_SADALPv16i8_v8i16, - ARM64_INS_SADALPv2i32_v1i64, - ARM64_INS_SADALPv4i16_v2i32, - ARM64_INS_SADALPv4i32_v2i64, - ARM64_INS_SADALPv8i16_v4i32, - ARM64_INS_SADALPv8i8_v4i16, - ARM64_INS_SADDLPv16i8_v8i16, - ARM64_INS_SADDLPv2i32_v1i64, - ARM64_INS_SADDLPv4i16_v2i32, - ARM64_INS_SADDLPv4i32_v2i64, - ARM64_INS_SADDLPv8i16_v4i32, - ARM64_INS_SADDLPv8i8_v4i16, - ARM64_INS_SADDLVv16i8v, - ARM64_INS_SADDLVv4i16v, - ARM64_INS_SADDLVv4i32v, - ARM64_INS_SADDLVv8i16v, - ARM64_INS_SADDLVv8i8v, - ARM64_INS_SADDLv16i8_v8i16, - ARM64_INS_SADDLv2i32_v2i64, - ARM64_INS_SADDLv4i16_v4i32, - ARM64_INS_SADDLv4i32_v2i64, - ARM64_INS_SADDLv8i16_v4i32, - ARM64_INS_SADDLv8i8_v8i16, - ARM64_INS_SADDV_VPZ_B, - ARM64_INS_SADDV_VPZ_H, - ARM64_INS_SADDV_VPZ_S, - ARM64_INS_SADDWv16i8_v8i16, - ARM64_INS_SADDWv2i32_v2i64, - ARM64_INS_SADDWv4i16_v4i32, - ARM64_INS_SADDWv4i32_v2i64, - ARM64_INS_SADDWv8i16_v4i32, - ARM64_INS_SADDWv8i8_v8i16, - ARM64_INS_SBCSWr, - ARM64_INS_SBCSXr, - ARM64_INS_SBCWr, - ARM64_INS_SBCXr, - ARM64_INS_SBFMWri, - ARM64_INS_SBFMXri, - ARM64_INS_SCVTFSWDri, - ARM64_INS_SCVTFSWHri, - ARM64_INS_SCVTFSWSri, - ARM64_INS_SCVTFSXDri, - ARM64_INS_SCVTFSXHri, - ARM64_INS_SCVTFSXSri, - ARM64_INS_SCVTFUWDri, - ARM64_INS_SCVTFUWHri, - ARM64_INS_SCVTFUWSri, - ARM64_INS_SCVTFUXDri, - ARM64_INS_SCVTFUXHri, - ARM64_INS_SCVTFUXSri, - ARM64_INS_SCVTF_ZPmZ_DtoD, - ARM64_INS_SCVTF_ZPmZ_DtoH, - ARM64_INS_SCVTF_ZPmZ_DtoS, - ARM64_INS_SCVTF_ZPmZ_HtoH, - ARM64_INS_SCVTF_ZPmZ_StoD, - ARM64_INS_SCVTF_ZPmZ_StoH, - ARM64_INS_SCVTF_ZPmZ_StoS, - ARM64_INS_SCVTFd, - ARM64_INS_SCVTFh, - ARM64_INS_SCVTFs, - ARM64_INS_SCVTFv1i16, - ARM64_INS_SCVTFv1i32, - ARM64_INS_SCVTFv1i64, - ARM64_INS_SCVTFv2f32, - ARM64_INS_SCVTFv2f64, - ARM64_INS_SCVTFv2i32_shift, - ARM64_INS_SCVTFv2i64_shift, - ARM64_INS_SCVTFv4f16, - ARM64_INS_SCVTFv4f32, - ARM64_INS_SCVTFv4i16_shift, - ARM64_INS_SCVTFv4i32_shift, - ARM64_INS_SCVTFv8f16, - ARM64_INS_SCVTFv8i16_shift, - ARM64_INS_SDIVR_ZPmZ_D, - ARM64_INS_SDIVR_ZPmZ_S, - ARM64_INS_SDIVWr, - ARM64_INS_SDIVXr, - ARM64_INS_SDIV_ZPmZ_D, - ARM64_INS_SDIV_ZPmZ_S, - ARM64_INS_SDOT_ZZZI_D, - ARM64_INS_SDOT_ZZZI_S, - ARM64_INS_SDOT_ZZZ_D, - ARM64_INS_SDOT_ZZZ_S, - ARM64_INS_SDOTlanev16i8, - ARM64_INS_SDOTlanev8i8, - ARM64_INS_SDOTv16i8, - ARM64_INS_SDOTv8i8, - ARM64_INS_SEL_PPPP, - ARM64_INS_SEL_ZPZZ_B, - ARM64_INS_SEL_ZPZZ_D, - ARM64_INS_SEL_ZPZZ_H, - ARM64_INS_SEL_ZPZZ_S, + ARM64_INS_ROR, + ARM64_INS_RORV, + ARM64_INS_RSHRN, + ARM64_INS_RSHRN2, + ARM64_INS_RSUBHN, + ARM64_INS_RSUBHN2, + ARM64_INS_SABA, + ARM64_INS_SABAL, + ARM64_INS_SABAL2, + ARM64_INS_SABD, + ARM64_INS_SABDL, + ARM64_INS_SABDL2, + ARM64_INS_SADALP, + ARM64_INS_SADDL, + ARM64_INS_SADDL2, + ARM64_INS_SADDLP, + ARM64_INS_SADDLV, + ARM64_INS_SADDV, + ARM64_INS_SADDW, + ARM64_INS_SADDW2, + ARM64_INS_SBC, + ARM64_INS_SBCS, + ARM64_INS_SBFM, + ARM64_INS_SCVTF, + ARM64_INS_SDIV, + ARM64_INS_SDIVR, + ARM64_INS_SDOT, + ARM64_INS_SEL, ARM64_INS_SETF16, ARM64_INS_SETF8, ARM64_INS_SETFFR, - ARM64_INS_SHA1Crrr, - ARM64_INS_SHA1Hrr, - ARM64_INS_SHA1Mrrr, - ARM64_INS_SHA1Prrr, - ARM64_INS_SHA1SU0rrr, - ARM64_INS_SHA1SU1rr, - ARM64_INS_SHA256H2rrr, - ARM64_INS_SHA256Hrrr, - ARM64_INS_SHA256SU0rr, - ARM64_INS_SHA256SU1rrr, + ARM64_INS_SEV, + ARM64_INS_SEVL, + ARM64_INS_SHA1C, + ARM64_INS_SHA1H, + ARM64_INS_SHA1M, + ARM64_INS_SHA1P, + ARM64_INS_SHA1SU0, + ARM64_INS_SHA1SU1, + ARM64_INS_SHA256H, + ARM64_INS_SHA256H2, + ARM64_INS_SHA256SU0, + ARM64_INS_SHA256SU1, ARM64_INS_SHA512H, ARM64_INS_SHA512H2, ARM64_INS_SHA512SU0, ARM64_INS_SHA512SU1, - ARM64_INS_SHADDv16i8, - ARM64_INS_SHADDv2i32, - ARM64_INS_SHADDv4i16, - ARM64_INS_SHADDv4i32, - ARM64_INS_SHADDv8i16, - ARM64_INS_SHADDv8i8, - ARM64_INS_SHLLv16i8, - ARM64_INS_SHLLv2i32, - ARM64_INS_SHLLv4i16, - ARM64_INS_SHLLv4i32, - ARM64_INS_SHLLv8i16, - ARM64_INS_SHLLv8i8, - ARM64_INS_SHLd, - ARM64_INS_SHLv16i8_shift, - ARM64_INS_SHLv2i32_shift, - ARM64_INS_SHLv2i64_shift, - ARM64_INS_SHLv4i16_shift, - ARM64_INS_SHLv4i32_shift, - ARM64_INS_SHLv8i16_shift, - ARM64_INS_SHLv8i8_shift, - ARM64_INS_SHRNv16i8_shift, - ARM64_INS_SHRNv2i32_shift, - ARM64_INS_SHRNv4i16_shift, - ARM64_INS_SHRNv4i32_shift, - ARM64_INS_SHRNv8i16_shift, - ARM64_INS_SHRNv8i8_shift, - ARM64_INS_SHSUBv16i8, - ARM64_INS_SHSUBv2i32, - ARM64_INS_SHSUBv4i16, - ARM64_INS_SHSUBv4i32, - ARM64_INS_SHSUBv8i16, - ARM64_INS_SHSUBv8i8, - ARM64_INS_SLId, - ARM64_INS_SLIv16i8_shift, - ARM64_INS_SLIv2i32_shift, - ARM64_INS_SLIv2i64_shift, - ARM64_INS_SLIv4i16_shift, - ARM64_INS_SLIv4i32_shift, - ARM64_INS_SLIv8i16_shift, - ARM64_INS_SLIv8i8_shift, + ARM64_INS_SHADD, + ARM64_INS_SHL, + ARM64_INS_SHLL, + ARM64_INS_SHLL2, + ARM64_INS_SHRN, + ARM64_INS_SHRN2, + ARM64_INS_SHSUB, + ARM64_INS_SLI, ARM64_INS_SM3PARTW1, ARM64_INS_SM3PARTW2, ARM64_INS_SM3SS1, @@ -3462,1515 +2069,326 @@ typedef enum arm64_insn { ARM64_INS_SM3TT2A, ARM64_INS_SM3TT2B, ARM64_INS_SM4E, - ARM64_INS_SM4ENCKEY, - ARM64_INS_SMADDLrrr, - ARM64_INS_SMAXPv16i8, - ARM64_INS_SMAXPv2i32, - ARM64_INS_SMAXPv4i16, - ARM64_INS_SMAXPv4i32, - ARM64_INS_SMAXPv8i16, - ARM64_INS_SMAXPv8i8, - ARM64_INS_SMAXV_VPZ_B, - ARM64_INS_SMAXV_VPZ_D, - ARM64_INS_SMAXV_VPZ_H, - ARM64_INS_SMAXV_VPZ_S, - ARM64_INS_SMAXVv16i8v, - ARM64_INS_SMAXVv4i16v, - ARM64_INS_SMAXVv4i32v, - ARM64_INS_SMAXVv8i16v, - ARM64_INS_SMAXVv8i8v, - ARM64_INS_SMAX_ZI_B, - ARM64_INS_SMAX_ZI_D, - ARM64_INS_SMAX_ZI_H, - ARM64_INS_SMAX_ZI_S, - ARM64_INS_SMAX_ZPmZ_B, - ARM64_INS_SMAX_ZPmZ_D, - ARM64_INS_SMAX_ZPmZ_H, - ARM64_INS_SMAX_ZPmZ_S, - ARM64_INS_SMAXv16i8, - ARM64_INS_SMAXv2i32, - ARM64_INS_SMAXv4i16, - ARM64_INS_SMAXv4i32, - ARM64_INS_SMAXv8i16, - ARM64_INS_SMAXv8i8, - ARM64_INS_SMINPv16i8, - ARM64_INS_SMINPv2i32, - ARM64_INS_SMINPv4i16, - ARM64_INS_SMINPv4i32, - ARM64_INS_SMINPv8i16, - ARM64_INS_SMINPv8i8, - ARM64_INS_SMINV_VPZ_B, - ARM64_INS_SMINV_VPZ_D, - ARM64_INS_SMINV_VPZ_H, - ARM64_INS_SMINV_VPZ_S, - ARM64_INS_SMINVv16i8v, - ARM64_INS_SMINVv4i16v, - ARM64_INS_SMINVv4i32v, - ARM64_INS_SMINVv8i16v, - ARM64_INS_SMINVv8i8v, - ARM64_INS_SMIN_ZI_B, - ARM64_INS_SMIN_ZI_D, - ARM64_INS_SMIN_ZI_H, - ARM64_INS_SMIN_ZI_S, - ARM64_INS_SMIN_ZPmZ_B, - ARM64_INS_SMIN_ZPmZ_D, - ARM64_INS_SMIN_ZPmZ_H, - ARM64_INS_SMIN_ZPmZ_S, - ARM64_INS_SMINv16i8, - ARM64_INS_SMINv2i32, - ARM64_INS_SMINv4i16, - ARM64_INS_SMINv4i32, - ARM64_INS_SMINv8i16, - ARM64_INS_SMINv8i8, - ARM64_INS_SMLALv16i8_v8i16, - ARM64_INS_SMLALv2i32_indexed, - ARM64_INS_SMLALv2i32_v2i64, - ARM64_INS_SMLALv4i16_indexed, - ARM64_INS_SMLALv4i16_v4i32, - ARM64_INS_SMLALv4i32_indexed, - ARM64_INS_SMLALv4i32_v2i64, - ARM64_INS_SMLALv8i16_indexed, - ARM64_INS_SMLALv8i16_v4i32, - ARM64_INS_SMLALv8i8_v8i16, - ARM64_INS_SMLSLv16i8_v8i16, - ARM64_INS_SMLSLv2i32_indexed, - ARM64_INS_SMLSLv2i32_v2i64, - ARM64_INS_SMLSLv4i16_indexed, - ARM64_INS_SMLSLv4i16_v4i32, - ARM64_INS_SMLSLv4i32_indexed, - ARM64_INS_SMLSLv4i32_v2i64, - ARM64_INS_SMLSLv8i16_indexed, - ARM64_INS_SMLSLv8i16_v4i32, - ARM64_INS_SMLSLv8i8_v8i16, - ARM64_INS_SMOVvi16to32, - ARM64_INS_SMOVvi16to64, - ARM64_INS_SMOVvi32to64, - ARM64_INS_SMOVvi8to32, - ARM64_INS_SMOVvi8to64, - ARM64_INS_SMSUBLrrr, - ARM64_INS_SMULH_ZPmZ_B, - ARM64_INS_SMULH_ZPmZ_D, - ARM64_INS_SMULH_ZPmZ_H, - ARM64_INS_SMULH_ZPmZ_S, - ARM64_INS_SMULHrr, - ARM64_INS_SMULLv16i8_v8i16, - ARM64_INS_SMULLv2i32_indexed, - ARM64_INS_SMULLv2i32_v2i64, - ARM64_INS_SMULLv4i16_indexed, - ARM64_INS_SMULLv4i16_v4i32, - ARM64_INS_SMULLv4i32_indexed, - ARM64_INS_SMULLv4i32_v2i64, - ARM64_INS_SMULLv8i16_indexed, - ARM64_INS_SMULLv8i16_v4i32, - ARM64_INS_SMULLv8i8_v8i16, - ARM64_INS_SPLICE_ZPZ_B, - ARM64_INS_SPLICE_ZPZ_D, - ARM64_INS_SPLICE_ZPZ_H, - ARM64_INS_SPLICE_ZPZ_S, - ARM64_INS_SQABSv16i8, - ARM64_INS_SQABSv1i16, - ARM64_INS_SQABSv1i32, - ARM64_INS_SQABSv1i64, - ARM64_INS_SQABSv1i8, - ARM64_INS_SQABSv2i32, - ARM64_INS_SQABSv2i64, - ARM64_INS_SQABSv4i16, - ARM64_INS_SQABSv4i32, - ARM64_INS_SQABSv8i16, - ARM64_INS_SQABSv8i8, - ARM64_INS_SQADD_ZI_B, - ARM64_INS_SQADD_ZI_D, - ARM64_INS_SQADD_ZI_H, - ARM64_INS_SQADD_ZI_S, - ARM64_INS_SQADD_ZZZ_B, - ARM64_INS_SQADD_ZZZ_D, - ARM64_INS_SQADD_ZZZ_H, - ARM64_INS_SQADD_ZZZ_S, - ARM64_INS_SQADDv16i8, - ARM64_INS_SQADDv1i16, - ARM64_INS_SQADDv1i32, - ARM64_INS_SQADDv1i64, - ARM64_INS_SQADDv1i8, - ARM64_INS_SQADDv2i32, - ARM64_INS_SQADDv2i64, - ARM64_INS_SQADDv4i16, - ARM64_INS_SQADDv4i32, - ARM64_INS_SQADDv8i16, - ARM64_INS_SQADDv8i8, - ARM64_INS_SQDECB_XPiI, - ARM64_INS_SQDECB_XPiWdI, - ARM64_INS_SQDECD_XPiI, - ARM64_INS_SQDECD_XPiWdI, - ARM64_INS_SQDECD_ZPiI, - ARM64_INS_SQDECH_XPiI, - ARM64_INS_SQDECH_XPiWdI, - ARM64_INS_SQDECH_ZPiI, - ARM64_INS_SQDECP_XPWd_B, - ARM64_INS_SQDECP_XPWd_D, - ARM64_INS_SQDECP_XPWd_H, - ARM64_INS_SQDECP_XPWd_S, - ARM64_INS_SQDECP_XP_B, - ARM64_INS_SQDECP_XP_D, - ARM64_INS_SQDECP_XP_H, - ARM64_INS_SQDECP_XP_S, - ARM64_INS_SQDECP_ZP_D, - ARM64_INS_SQDECP_ZP_H, - ARM64_INS_SQDECP_ZP_S, - ARM64_INS_SQDECW_XPiI, - ARM64_INS_SQDECW_XPiWdI, - ARM64_INS_SQDECW_ZPiI, - ARM64_INS_SQDMLALi16, - ARM64_INS_SQDMLALi32, - ARM64_INS_SQDMLALv1i32_indexed, - ARM64_INS_SQDMLALv1i64_indexed, - ARM64_INS_SQDMLALv2i32_indexed, - ARM64_INS_SQDMLALv2i32_v2i64, - ARM64_INS_SQDMLALv4i16_indexed, - ARM64_INS_SQDMLALv4i16_v4i32, - ARM64_INS_SQDMLALv4i32_indexed, - ARM64_INS_SQDMLALv4i32_v2i64, - ARM64_INS_SQDMLALv8i16_indexed, - ARM64_INS_SQDMLALv8i16_v4i32, - ARM64_INS_SQDMLSLi16, - ARM64_INS_SQDMLSLi32, - ARM64_INS_SQDMLSLv1i32_indexed, - ARM64_INS_SQDMLSLv1i64_indexed, - ARM64_INS_SQDMLSLv2i32_indexed, - ARM64_INS_SQDMLSLv2i32_v2i64, - ARM64_INS_SQDMLSLv4i16_indexed, - ARM64_INS_SQDMLSLv4i16_v4i32, - ARM64_INS_SQDMLSLv4i32_indexed, - ARM64_INS_SQDMLSLv4i32_v2i64, - ARM64_INS_SQDMLSLv8i16_indexed, - ARM64_INS_SQDMLSLv8i16_v4i32, - ARM64_INS_SQDMULHv1i16, - ARM64_INS_SQDMULHv1i16_indexed, - ARM64_INS_SQDMULHv1i32, - ARM64_INS_SQDMULHv1i32_indexed, - ARM64_INS_SQDMULHv2i32, - ARM64_INS_SQDMULHv2i32_indexed, - ARM64_INS_SQDMULHv4i16, - ARM64_INS_SQDMULHv4i16_indexed, - ARM64_INS_SQDMULHv4i32, - ARM64_INS_SQDMULHv4i32_indexed, - ARM64_INS_SQDMULHv8i16, - ARM64_INS_SQDMULHv8i16_indexed, - ARM64_INS_SQDMULLi16, - ARM64_INS_SQDMULLi32, - ARM64_INS_SQDMULLv1i32_indexed, - ARM64_INS_SQDMULLv1i64_indexed, - ARM64_INS_SQDMULLv2i32_indexed, - ARM64_INS_SQDMULLv2i32_v2i64, - ARM64_INS_SQDMULLv4i16_indexed, - ARM64_INS_SQDMULLv4i16_v4i32, - ARM64_INS_SQDMULLv4i32_indexed, - ARM64_INS_SQDMULLv4i32_v2i64, - ARM64_INS_SQDMULLv8i16_indexed, - ARM64_INS_SQDMULLv8i16_v4i32, - ARM64_INS_SQINCB_XPiI, - ARM64_INS_SQINCB_XPiWdI, - ARM64_INS_SQINCD_XPiI, - ARM64_INS_SQINCD_XPiWdI, - ARM64_INS_SQINCD_ZPiI, - ARM64_INS_SQINCH_XPiI, - ARM64_INS_SQINCH_XPiWdI, - ARM64_INS_SQINCH_ZPiI, - ARM64_INS_SQINCP_XPWd_B, - ARM64_INS_SQINCP_XPWd_D, - ARM64_INS_SQINCP_XPWd_H, - ARM64_INS_SQINCP_XPWd_S, - ARM64_INS_SQINCP_XP_B, - ARM64_INS_SQINCP_XP_D, - ARM64_INS_SQINCP_XP_H, - ARM64_INS_SQINCP_XP_S, - ARM64_INS_SQINCP_ZP_D, - ARM64_INS_SQINCP_ZP_H, - ARM64_INS_SQINCP_ZP_S, - ARM64_INS_SQINCW_XPiI, - ARM64_INS_SQINCW_XPiWdI, - ARM64_INS_SQINCW_ZPiI, - ARM64_INS_SQNEGv16i8, - ARM64_INS_SQNEGv1i16, - ARM64_INS_SQNEGv1i32, - ARM64_INS_SQNEGv1i64, - ARM64_INS_SQNEGv1i8, - ARM64_INS_SQNEGv2i32, - ARM64_INS_SQNEGv2i64, - ARM64_INS_SQNEGv4i16, - ARM64_INS_SQNEGv4i32, - ARM64_INS_SQNEGv8i16, - ARM64_INS_SQNEGv8i8, - ARM64_INS_SQRDMLAHi16_indexed, - ARM64_INS_SQRDMLAHi32_indexed, - ARM64_INS_SQRDMLAHv1i16, - ARM64_INS_SQRDMLAHv1i32, - ARM64_INS_SQRDMLAHv2i32, - ARM64_INS_SQRDMLAHv2i32_indexed, - ARM64_INS_SQRDMLAHv4i16, - ARM64_INS_SQRDMLAHv4i16_indexed, - ARM64_INS_SQRDMLAHv4i32, - ARM64_INS_SQRDMLAHv4i32_indexed, - ARM64_INS_SQRDMLAHv8i16, - ARM64_INS_SQRDMLAHv8i16_indexed, - ARM64_INS_SQRDMLSHi16_indexed, - ARM64_INS_SQRDMLSHi32_indexed, - ARM64_INS_SQRDMLSHv1i16, - ARM64_INS_SQRDMLSHv1i32, - ARM64_INS_SQRDMLSHv2i32, - ARM64_INS_SQRDMLSHv2i32_indexed, - ARM64_INS_SQRDMLSHv4i16, - ARM64_INS_SQRDMLSHv4i16_indexed, - ARM64_INS_SQRDMLSHv4i32, - ARM64_INS_SQRDMLSHv4i32_indexed, - ARM64_INS_SQRDMLSHv8i16, - ARM64_INS_SQRDMLSHv8i16_indexed, - ARM64_INS_SQRDMULHv1i16, - ARM64_INS_SQRDMULHv1i16_indexed, - ARM64_INS_SQRDMULHv1i32, - ARM64_INS_SQRDMULHv1i32_indexed, - ARM64_INS_SQRDMULHv2i32, - ARM64_INS_SQRDMULHv2i32_indexed, - ARM64_INS_SQRDMULHv4i16, - ARM64_INS_SQRDMULHv4i16_indexed, - ARM64_INS_SQRDMULHv4i32, - ARM64_INS_SQRDMULHv4i32_indexed, - ARM64_INS_SQRDMULHv8i16, - ARM64_INS_SQRDMULHv8i16_indexed, - ARM64_INS_SQRSHLv16i8, - ARM64_INS_SQRSHLv1i16, - ARM64_INS_SQRSHLv1i32, - ARM64_INS_SQRSHLv1i64, - ARM64_INS_SQRSHLv1i8, - ARM64_INS_SQRSHLv2i32, - ARM64_INS_SQRSHLv2i64, - ARM64_INS_SQRSHLv4i16, - ARM64_INS_SQRSHLv4i32, - ARM64_INS_SQRSHLv8i16, - ARM64_INS_SQRSHLv8i8, - ARM64_INS_SQRSHRNb, - ARM64_INS_SQRSHRNh, - ARM64_INS_SQRSHRNs, - ARM64_INS_SQRSHRNv16i8_shift, - ARM64_INS_SQRSHRNv2i32_shift, - ARM64_INS_SQRSHRNv4i16_shift, - ARM64_INS_SQRSHRNv4i32_shift, - ARM64_INS_SQRSHRNv8i16_shift, - ARM64_INS_SQRSHRNv8i8_shift, - ARM64_INS_SQRSHRUNb, - ARM64_INS_SQRSHRUNh, - ARM64_INS_SQRSHRUNs, - ARM64_INS_SQRSHRUNv16i8_shift, - ARM64_INS_SQRSHRUNv2i32_shift, - ARM64_INS_SQRSHRUNv4i16_shift, - ARM64_INS_SQRSHRUNv4i32_shift, - ARM64_INS_SQRSHRUNv8i16_shift, - ARM64_INS_SQRSHRUNv8i8_shift, - ARM64_INS_SQSHLUb, - ARM64_INS_SQSHLUd, - ARM64_INS_SQSHLUh, - ARM64_INS_SQSHLUs, - ARM64_INS_SQSHLUv16i8_shift, - ARM64_INS_SQSHLUv2i32_shift, - ARM64_INS_SQSHLUv2i64_shift, - ARM64_INS_SQSHLUv4i16_shift, - ARM64_INS_SQSHLUv4i32_shift, - ARM64_INS_SQSHLUv8i16_shift, - ARM64_INS_SQSHLUv8i8_shift, - ARM64_INS_SQSHLb, - ARM64_INS_SQSHLd, - ARM64_INS_SQSHLh, - ARM64_INS_SQSHLs, - ARM64_INS_SQSHLv16i8, - ARM64_INS_SQSHLv16i8_shift, - ARM64_INS_SQSHLv1i16, - ARM64_INS_SQSHLv1i32, - ARM64_INS_SQSHLv1i64, - ARM64_INS_SQSHLv1i8, - ARM64_INS_SQSHLv2i32, - ARM64_INS_SQSHLv2i32_shift, - ARM64_INS_SQSHLv2i64, - ARM64_INS_SQSHLv2i64_shift, - ARM64_INS_SQSHLv4i16, - ARM64_INS_SQSHLv4i16_shift, - ARM64_INS_SQSHLv4i32, - ARM64_INS_SQSHLv4i32_shift, - ARM64_INS_SQSHLv8i16, - ARM64_INS_SQSHLv8i16_shift, - ARM64_INS_SQSHLv8i8, - ARM64_INS_SQSHLv8i8_shift, - ARM64_INS_SQSHRNb, - ARM64_INS_SQSHRNh, - ARM64_INS_SQSHRNs, - ARM64_INS_SQSHRNv16i8_shift, - ARM64_INS_SQSHRNv2i32_shift, - ARM64_INS_SQSHRNv4i16_shift, - ARM64_INS_SQSHRNv4i32_shift, - ARM64_INS_SQSHRNv8i16_shift, - ARM64_INS_SQSHRNv8i8_shift, - ARM64_INS_SQSHRUNb, - ARM64_INS_SQSHRUNh, - ARM64_INS_SQSHRUNs, - ARM64_INS_SQSHRUNv16i8_shift, - ARM64_INS_SQSHRUNv2i32_shift, - ARM64_INS_SQSHRUNv4i16_shift, - ARM64_INS_SQSHRUNv4i32_shift, - ARM64_INS_SQSHRUNv8i16_shift, - ARM64_INS_SQSHRUNv8i8_shift, - ARM64_INS_SQSUB_ZI_B, - ARM64_INS_SQSUB_ZI_D, - ARM64_INS_SQSUB_ZI_H, - ARM64_INS_SQSUB_ZI_S, - ARM64_INS_SQSUB_ZZZ_B, - ARM64_INS_SQSUB_ZZZ_D, - ARM64_INS_SQSUB_ZZZ_H, - ARM64_INS_SQSUB_ZZZ_S, - ARM64_INS_SQSUBv16i8, - ARM64_INS_SQSUBv1i16, - ARM64_INS_SQSUBv1i32, - ARM64_INS_SQSUBv1i64, - ARM64_INS_SQSUBv1i8, - ARM64_INS_SQSUBv2i32, - ARM64_INS_SQSUBv2i64, - ARM64_INS_SQSUBv4i16, - ARM64_INS_SQSUBv4i32, - ARM64_INS_SQSUBv8i16, - ARM64_INS_SQSUBv8i8, - ARM64_INS_SQXTNv16i8, - ARM64_INS_SQXTNv1i16, - ARM64_INS_SQXTNv1i32, - ARM64_INS_SQXTNv1i8, - ARM64_INS_SQXTNv2i32, - ARM64_INS_SQXTNv4i16, - ARM64_INS_SQXTNv4i32, - ARM64_INS_SQXTNv8i16, - ARM64_INS_SQXTNv8i8, - ARM64_INS_SQXTUNv16i8, - ARM64_INS_SQXTUNv1i16, - ARM64_INS_SQXTUNv1i32, - ARM64_INS_SQXTUNv1i8, - ARM64_INS_SQXTUNv2i32, - ARM64_INS_SQXTUNv4i16, - ARM64_INS_SQXTUNv4i32, - ARM64_INS_SQXTUNv8i16, - ARM64_INS_SQXTUNv8i8, - ARM64_INS_SRHADDv16i8, - ARM64_INS_SRHADDv2i32, - ARM64_INS_SRHADDv4i16, - ARM64_INS_SRHADDv4i32, - ARM64_INS_SRHADDv8i16, - ARM64_INS_SRHADDv8i8, - ARM64_INS_SRId, - ARM64_INS_SRIv16i8_shift, - ARM64_INS_SRIv2i32_shift, - ARM64_INS_SRIv2i64_shift, - ARM64_INS_SRIv4i16_shift, - ARM64_INS_SRIv4i32_shift, - ARM64_INS_SRIv8i16_shift, - ARM64_INS_SRIv8i8_shift, - ARM64_INS_SRSHLv16i8, - ARM64_INS_SRSHLv1i64, - ARM64_INS_SRSHLv2i32, - ARM64_INS_SRSHLv2i64, - ARM64_INS_SRSHLv4i16, - ARM64_INS_SRSHLv4i32, - ARM64_INS_SRSHLv8i16, - ARM64_INS_SRSHLv8i8, - ARM64_INS_SRSHRd, - ARM64_INS_SRSHRv16i8_shift, - ARM64_INS_SRSHRv2i32_shift, - ARM64_INS_SRSHRv2i64_shift, - ARM64_INS_SRSHRv4i16_shift, - ARM64_INS_SRSHRv4i32_shift, - ARM64_INS_SRSHRv8i16_shift, - ARM64_INS_SRSHRv8i8_shift, - ARM64_INS_SRSRAd, - ARM64_INS_SRSRAv16i8_shift, - ARM64_INS_SRSRAv2i32_shift, - ARM64_INS_SRSRAv2i64_shift, - ARM64_INS_SRSRAv4i16_shift, - ARM64_INS_SRSRAv4i32_shift, - ARM64_INS_SRSRAv8i16_shift, - ARM64_INS_SRSRAv8i8_shift, - ARM64_INS_SSHLLv16i8_shift, - ARM64_INS_SSHLLv2i32_shift, - ARM64_INS_SSHLLv4i16_shift, - ARM64_INS_SSHLLv4i32_shift, - ARM64_INS_SSHLLv8i16_shift, - ARM64_INS_SSHLLv8i8_shift, - ARM64_INS_SSHLv16i8, - ARM64_INS_SSHLv1i64, - ARM64_INS_SSHLv2i32, - ARM64_INS_SSHLv2i64, - ARM64_INS_SSHLv4i16, - ARM64_INS_SSHLv4i32, - ARM64_INS_SSHLv8i16, - ARM64_INS_SSHLv8i8, - ARM64_INS_SSHRd, - ARM64_INS_SSHRv16i8_shift, - ARM64_INS_SSHRv2i32_shift, - ARM64_INS_SSHRv2i64_shift, - ARM64_INS_SSHRv4i16_shift, - ARM64_INS_SSHRv4i32_shift, - ARM64_INS_SSHRv8i16_shift, - ARM64_INS_SSHRv8i8_shift, - ARM64_INS_SSRAd, - ARM64_INS_SSRAv16i8_shift, - ARM64_INS_SSRAv2i32_shift, - ARM64_INS_SSRAv2i64_shift, - ARM64_INS_SSRAv4i16_shift, - ARM64_INS_SSRAv4i32_shift, - ARM64_INS_SSRAv8i16_shift, - ARM64_INS_SSRAv8i8_shift, - ARM64_INS_SST1B_D, - ARM64_INS_SST1B_D_IMM, - ARM64_INS_SST1B_D_SXTW, - ARM64_INS_SST1B_D_UXTW, - ARM64_INS_SST1B_S_IMM, - ARM64_INS_SST1B_S_SXTW, - ARM64_INS_SST1B_S_UXTW, - ARM64_INS_SST1D, - ARM64_INS_SST1D_IMM, - ARM64_INS_SST1D_SCALED, - ARM64_INS_SST1D_SXTW, - ARM64_INS_SST1D_SXTW_SCALED, - ARM64_INS_SST1D_UXTW, - ARM64_INS_SST1D_UXTW_SCALED, - ARM64_INS_SST1H_D, - ARM64_INS_SST1H_D_IMM, - ARM64_INS_SST1H_D_SCALED, - ARM64_INS_SST1H_D_SXTW, - ARM64_INS_SST1H_D_SXTW_SCALED, - ARM64_INS_SST1H_D_UXTW, - ARM64_INS_SST1H_D_UXTW_SCALED, - ARM64_INS_SST1H_S_IMM, - ARM64_INS_SST1H_S_SXTW, - ARM64_INS_SST1H_S_SXTW_SCALED, - ARM64_INS_SST1H_S_UXTW, - ARM64_INS_SST1H_S_UXTW_SCALED, - ARM64_INS_SST1W_D, - ARM64_INS_SST1W_D_IMM, - ARM64_INS_SST1W_D_SCALED, - ARM64_INS_SST1W_D_SXTW, - ARM64_INS_SST1W_D_SXTW_SCALED, - ARM64_INS_SST1W_D_UXTW, - ARM64_INS_SST1W_D_UXTW_SCALED, - ARM64_INS_SST1W_IMM, - ARM64_INS_SST1W_SXTW, - ARM64_INS_SST1W_SXTW_SCALED, - ARM64_INS_SST1W_UXTW, - ARM64_INS_SST1W_UXTW_SCALED, - ARM64_INS_SSUBLv16i8_v8i16, - ARM64_INS_SSUBLv2i32_v2i64, - ARM64_INS_SSUBLv4i16_v4i32, - ARM64_INS_SSUBLv4i32_v2i64, - ARM64_INS_SSUBLv8i16_v4i32, - ARM64_INS_SSUBLv8i8_v8i16, - ARM64_INS_SSUBWv16i8_v8i16, - ARM64_INS_SSUBWv2i32_v2i64, - ARM64_INS_SSUBWv4i16_v4i32, - ARM64_INS_SSUBWv4i32_v2i64, - ARM64_INS_SSUBWv8i16_v4i32, - ARM64_INS_SSUBWv8i8_v8i16, + ARM64_INS_SM4EKEY, + ARM64_INS_SMADDL, + ARM64_INS_SMAX, + ARM64_INS_SMAXP, + ARM64_INS_SMAXV, + ARM64_INS_SMC, + ARM64_INS_SMIN, + ARM64_INS_SMINP, + ARM64_INS_SMINV, + ARM64_INS_SMLAL, + ARM64_INS_SMLAL2, + ARM64_INS_SMLSL, + ARM64_INS_SMLSL2, + ARM64_INS_SMNEGL, + ARM64_INS_SMOV, + ARM64_INS_SMSUBL, + ARM64_INS_SMULH, + ARM64_INS_SMULL, + ARM64_INS_SMULL2, + ARM64_INS_SPLICE, + ARM64_INS_SQABS, + ARM64_INS_SQADD, + ARM64_INS_SQDECB, + ARM64_INS_SQDECD, + ARM64_INS_SQDECH, + ARM64_INS_SQDECP, + ARM64_INS_SQDECW, + ARM64_INS_SQDMLAL, + ARM64_INS_SQDMLAL2, + ARM64_INS_SQDMLSL, + ARM64_INS_SQDMLSL2, + ARM64_INS_SQDMULH, + ARM64_INS_SQDMULL, + ARM64_INS_SQDMULL2, + ARM64_INS_SQINCB, + ARM64_INS_SQINCD, + ARM64_INS_SQINCH, + ARM64_INS_SQINCP, + ARM64_INS_SQINCW, + ARM64_INS_SQNEG, + ARM64_INS_SQRDMLAH, + ARM64_INS_SQRDMLSH, + ARM64_INS_SQRDMULH, + ARM64_INS_SQRSHL, + ARM64_INS_SQRSHRN, + ARM64_INS_SQRSHRN2, + ARM64_INS_SQRSHRUN, + ARM64_INS_SQRSHRUN2, + ARM64_INS_SQSHL, + ARM64_INS_SQSHLU, + ARM64_INS_SQSHRN, + ARM64_INS_SQSHRN2, + ARM64_INS_SQSHRUN, + ARM64_INS_SQSHRUN2, + ARM64_INS_SQSUB, + ARM64_INS_SQXTN, + ARM64_INS_SQXTN2, + ARM64_INS_SQXTUN, + ARM64_INS_SQXTUN2, + ARM64_INS_SRHADD, + ARM64_INS_SRI, + ARM64_INS_SRSHL, + ARM64_INS_SRSHR, + ARM64_INS_SRSRA, + ARM64_INS_SSHL, + ARM64_INS_SSHLL, + ARM64_INS_SSHLL2, + ARM64_INS_SSHR, + ARM64_INS_SSRA, + ARM64_INS_SSUBL, + ARM64_INS_SSUBL2, + ARM64_INS_SSUBW, + ARM64_INS_SSUBW2, + ARM64_INS_ST1, ARM64_INS_ST1B, - ARM64_INS_ST1B_D, - ARM64_INS_ST1B_D_IMM, - ARM64_INS_ST1B_H, - ARM64_INS_ST1B_H_IMM, - ARM64_INS_ST1B_IMM, - ARM64_INS_ST1B_S, - ARM64_INS_ST1B_S_IMM, ARM64_INS_ST1D, - ARM64_INS_ST1D_IMM, - ARM64_INS_ST1Fourv16b, - ARM64_INS_ST1Fourv16b_POST, - ARM64_INS_ST1Fourv1d, - ARM64_INS_ST1Fourv1d_POST, - ARM64_INS_ST1Fourv2d, - ARM64_INS_ST1Fourv2d_POST, - ARM64_INS_ST1Fourv2s, - ARM64_INS_ST1Fourv2s_POST, - ARM64_INS_ST1Fourv4h, - ARM64_INS_ST1Fourv4h_POST, - ARM64_INS_ST1Fourv4s, - ARM64_INS_ST1Fourv4s_POST, - ARM64_INS_ST1Fourv8b, - ARM64_INS_ST1Fourv8b_POST, - ARM64_INS_ST1Fourv8h, - ARM64_INS_ST1Fourv8h_POST, ARM64_INS_ST1H, - ARM64_INS_ST1H_D, - ARM64_INS_ST1H_D_IMM, - ARM64_INS_ST1H_IMM, - ARM64_INS_ST1H_S, - ARM64_INS_ST1H_S_IMM, - ARM64_INS_ST1Onev16b, - ARM64_INS_ST1Onev16b_POST, - ARM64_INS_ST1Onev1d, - ARM64_INS_ST1Onev1d_POST, - ARM64_INS_ST1Onev2d, - ARM64_INS_ST1Onev2d_POST, - ARM64_INS_ST1Onev2s, - ARM64_INS_ST1Onev2s_POST, - ARM64_INS_ST1Onev4h, - ARM64_INS_ST1Onev4h_POST, - ARM64_INS_ST1Onev4s, - ARM64_INS_ST1Onev4s_POST, - ARM64_INS_ST1Onev8b, - ARM64_INS_ST1Onev8b_POST, - ARM64_INS_ST1Onev8h, - ARM64_INS_ST1Onev8h_POST, - ARM64_INS_ST1Threev16b, - ARM64_INS_ST1Threev16b_POST, - ARM64_INS_ST1Threev1d, - ARM64_INS_ST1Threev1d_POST, - ARM64_INS_ST1Threev2d, - ARM64_INS_ST1Threev2d_POST, - ARM64_INS_ST1Threev2s, - ARM64_INS_ST1Threev2s_POST, - ARM64_INS_ST1Threev4h, - ARM64_INS_ST1Threev4h_POST, - ARM64_INS_ST1Threev4s, - ARM64_INS_ST1Threev4s_POST, - ARM64_INS_ST1Threev8b, - ARM64_INS_ST1Threev8b_POST, - ARM64_INS_ST1Threev8h, - ARM64_INS_ST1Threev8h_POST, - ARM64_INS_ST1Twov16b, - ARM64_INS_ST1Twov16b_POST, - ARM64_INS_ST1Twov1d, - ARM64_INS_ST1Twov1d_POST, - ARM64_INS_ST1Twov2d, - ARM64_INS_ST1Twov2d_POST, - ARM64_INS_ST1Twov2s, - ARM64_INS_ST1Twov2s_POST, - ARM64_INS_ST1Twov4h, - ARM64_INS_ST1Twov4h_POST, - ARM64_INS_ST1Twov4s, - ARM64_INS_ST1Twov4s_POST, - ARM64_INS_ST1Twov8b, - ARM64_INS_ST1Twov8b_POST, - ARM64_INS_ST1Twov8h, - ARM64_INS_ST1Twov8h_POST, ARM64_INS_ST1W, - ARM64_INS_ST1W_D, - ARM64_INS_ST1W_D_IMM, - ARM64_INS_ST1W_IMM, - ARM64_INS_ST1i16, - ARM64_INS_ST1i16_POST, - ARM64_INS_ST1i32, - ARM64_INS_ST1i32_POST, - ARM64_INS_ST1i64, - ARM64_INS_ST1i64_POST, - ARM64_INS_ST1i8, - ARM64_INS_ST1i8_POST, + ARM64_INS_ST2, ARM64_INS_ST2B, - ARM64_INS_ST2B_IMM, ARM64_INS_ST2D, - ARM64_INS_ST2D_IMM, ARM64_INS_ST2H, - ARM64_INS_ST2H_IMM, - ARM64_INS_ST2Twov16b, - ARM64_INS_ST2Twov16b_POST, - ARM64_INS_ST2Twov2d, - ARM64_INS_ST2Twov2d_POST, - ARM64_INS_ST2Twov2s, - ARM64_INS_ST2Twov2s_POST, - ARM64_INS_ST2Twov4h, - ARM64_INS_ST2Twov4h_POST, - ARM64_INS_ST2Twov4s, - ARM64_INS_ST2Twov4s_POST, - ARM64_INS_ST2Twov8b, - ARM64_INS_ST2Twov8b_POST, - ARM64_INS_ST2Twov8h, - ARM64_INS_ST2Twov8h_POST, ARM64_INS_ST2W, - ARM64_INS_ST2W_IMM, - ARM64_INS_ST2i16, - ARM64_INS_ST2i16_POST, - ARM64_INS_ST2i32, - ARM64_INS_ST2i32_POST, - ARM64_INS_ST2i64, - ARM64_INS_ST2i64_POST, - ARM64_INS_ST2i8, - ARM64_INS_ST2i8_POST, + ARM64_INS_ST3, ARM64_INS_ST3B, - ARM64_INS_ST3B_IMM, ARM64_INS_ST3D, - ARM64_INS_ST3D_IMM, ARM64_INS_ST3H, - ARM64_INS_ST3H_IMM, - ARM64_INS_ST3Threev16b, - ARM64_INS_ST3Threev16b_POST, - ARM64_INS_ST3Threev2d, - ARM64_INS_ST3Threev2d_POST, - ARM64_INS_ST3Threev2s, - ARM64_INS_ST3Threev2s_POST, - ARM64_INS_ST3Threev4h, - ARM64_INS_ST3Threev4h_POST, - ARM64_INS_ST3Threev4s, - ARM64_INS_ST3Threev4s_POST, - ARM64_INS_ST3Threev8b, - ARM64_INS_ST3Threev8b_POST, - ARM64_INS_ST3Threev8h, - ARM64_INS_ST3Threev8h_POST, ARM64_INS_ST3W, - ARM64_INS_ST3W_IMM, - ARM64_INS_ST3i16, - ARM64_INS_ST3i16_POST, - ARM64_INS_ST3i32, - ARM64_INS_ST3i32_POST, - ARM64_INS_ST3i64, - ARM64_INS_ST3i64_POST, - ARM64_INS_ST3i8, - ARM64_INS_ST3i8_POST, + ARM64_INS_ST4, ARM64_INS_ST4B, - ARM64_INS_ST4B_IMM, ARM64_INS_ST4D, - ARM64_INS_ST4D_IMM, - ARM64_INS_ST4Fourv16b, - ARM64_INS_ST4Fourv16b_POST, - ARM64_INS_ST4Fourv2d, - ARM64_INS_ST4Fourv2d_POST, - ARM64_INS_ST4Fourv2s, - ARM64_INS_ST4Fourv2s_POST, - ARM64_INS_ST4Fourv4h, - ARM64_INS_ST4Fourv4h_POST, - ARM64_INS_ST4Fourv4s, - ARM64_INS_ST4Fourv4s_POST, - ARM64_INS_ST4Fourv8b, - ARM64_INS_ST4Fourv8b_POST, - ARM64_INS_ST4Fourv8h, - ARM64_INS_ST4Fourv8h_POST, ARM64_INS_ST4H, - ARM64_INS_ST4H_IMM, ARM64_INS_ST4W, - ARM64_INS_ST4W_IMM, - ARM64_INS_ST4i16, - ARM64_INS_ST4i16_POST, - ARM64_INS_ST4i32, - ARM64_INS_ST4i32_POST, - ARM64_INS_ST4i64, - ARM64_INS_ST4i64_POST, - ARM64_INS_ST4i8, - ARM64_INS_ST4i8_POST, + ARM64_INS_STADD, + ARM64_INS_STADDB, + ARM64_INS_STADDH, + ARM64_INS_STADDL, + ARM64_INS_STADDLB, + ARM64_INS_STADDLH, + ARM64_INS_STCLR, + ARM64_INS_STCLRB, + ARM64_INS_STCLRH, + ARM64_INS_STCLRL, + ARM64_INS_STCLRLB, + ARM64_INS_STCLRLH, + ARM64_INS_STEOR, + ARM64_INS_STEORB, + ARM64_INS_STEORH, + ARM64_INS_STEORL, + ARM64_INS_STEORLB, + ARM64_INS_STEORLH, + ARM64_INS_STLLR, ARM64_INS_STLLRB, ARM64_INS_STLLRH, - ARM64_INS_STLLRW, - ARM64_INS_STLLRX, - ARM64_INS_STLRW, - ARM64_INS_STLRX, - ARM64_INS_STLURBi, - ARM64_INS_STLURHi, - ARM64_INS_STLURWi, - ARM64_INS_STLURXi, - ARM64_INS_STLXPW, - ARM64_INS_STLXPX, - ARM64_INS_STLXRW, - ARM64_INS_STLXRX, - ARM64_INS_STNPDi, - ARM64_INS_STNPQi, - ARM64_INS_STNPSi, - ARM64_INS_STNPWi, - ARM64_INS_STNPXi, - ARM64_INS_STNT1B_ZRI, - ARM64_INS_STNT1B_ZRR, - ARM64_INS_STNT1D_ZRI, - ARM64_INS_STNT1D_ZRR, - ARM64_INS_STNT1H_ZRI, - ARM64_INS_STNT1H_ZRR, - ARM64_INS_STNT1W_ZRI, - ARM64_INS_STNT1W_ZRR, - ARM64_INS_STPDi, - ARM64_INS_STPDpost, - ARM64_INS_STPDpre, - ARM64_INS_STPQi, - ARM64_INS_STPQpost, - ARM64_INS_STPQpre, - ARM64_INS_STPSi, - ARM64_INS_STPSpost, - ARM64_INS_STPSpre, - ARM64_INS_STPWi, - ARM64_INS_STPWpost, - ARM64_INS_STPWpre, - ARM64_INS_STPXi, - ARM64_INS_STPXpost, - ARM64_INS_STPXpre, - ARM64_INS_STRBBpost, - ARM64_INS_STRBBpre, - ARM64_INS_STRBBroW, - ARM64_INS_STRBBroX, - ARM64_INS_STRBBui, - ARM64_INS_STRBpost, - ARM64_INS_STRBpre, - ARM64_INS_STRBroW, - ARM64_INS_STRBroX, - ARM64_INS_STRBui, - ARM64_INS_STRDpost, - ARM64_INS_STRDpre, - ARM64_INS_STRDroW, - ARM64_INS_STRDroX, - ARM64_INS_STRDui, - ARM64_INS_STRHHpost, - ARM64_INS_STRHHpre, - ARM64_INS_STRHHroW, - ARM64_INS_STRHHroX, - ARM64_INS_STRHHui, - ARM64_INS_STRHpost, - ARM64_INS_STRHpre, - ARM64_INS_STRHroW, - ARM64_INS_STRHroX, - ARM64_INS_STRHui, - ARM64_INS_STRQpost, - ARM64_INS_STRQpre, - ARM64_INS_STRQroW, - ARM64_INS_STRQroX, - ARM64_INS_STRQui, - ARM64_INS_STRSpost, - ARM64_INS_STRSpre, - ARM64_INS_STRSroW, - ARM64_INS_STRSroX, - ARM64_INS_STRSui, - ARM64_INS_STRWpost, - ARM64_INS_STRWpre, - ARM64_INS_STRWroW, - ARM64_INS_STRWroX, - ARM64_INS_STRWui, - ARM64_INS_STRXpost, - ARM64_INS_STRXpre, - ARM64_INS_STRXroW, - ARM64_INS_STRXroX, - ARM64_INS_STRXui, - ARM64_INS_STR_PXI, - ARM64_INS_STR_ZXI, - ARM64_INS_STTRBi, - ARM64_INS_STTRHi, - ARM64_INS_STTRWi, - ARM64_INS_STTRXi, - ARM64_INS_STURBBi, - ARM64_INS_STURBi, - ARM64_INS_STURDi, - ARM64_INS_STURHHi, - ARM64_INS_STURHi, - ARM64_INS_STURQi, - ARM64_INS_STURSi, - ARM64_INS_STURWi, - ARM64_INS_STURXi, - ARM64_INS_STXPW, - ARM64_INS_STXPX, - ARM64_INS_STXRW, - ARM64_INS_STXRX, - ARM64_INS_SUBHNv2i64_v2i32, - ARM64_INS_SUBHNv2i64_v4i32, - ARM64_INS_SUBHNv4i32_v4i16, - ARM64_INS_SUBHNv4i32_v8i16, - ARM64_INS_SUBHNv8i16_v16i8, - ARM64_INS_SUBHNv8i16_v8i8, - ARM64_INS_SUBR_ZI_B, - ARM64_INS_SUBR_ZI_D, - ARM64_INS_SUBR_ZI_H, - ARM64_INS_SUBR_ZI_S, - ARM64_INS_SUBR_ZPmZ_B, - ARM64_INS_SUBR_ZPmZ_D, - ARM64_INS_SUBR_ZPmZ_H, - ARM64_INS_SUBR_ZPmZ_S, - ARM64_INS_SUBSWri, - ARM64_INS_SUBSWrs, - ARM64_INS_SUBSWrx, - ARM64_INS_SUBSXri, - ARM64_INS_SUBSXrs, - ARM64_INS_SUBSXrx, - ARM64_INS_SUBSXrx64, - ARM64_INS_SUBWri, - ARM64_INS_SUBWrs, - ARM64_INS_SUBWrx, - ARM64_INS_SUBXri, - ARM64_INS_SUBXrs, - ARM64_INS_SUBXrx, - ARM64_INS_SUBXrx64, - ARM64_INS_SUB_ZI_B, - ARM64_INS_SUB_ZI_D, - ARM64_INS_SUB_ZI_H, - ARM64_INS_SUB_ZI_S, - ARM64_INS_SUB_ZPmZ_B, - ARM64_INS_SUB_ZPmZ_D, - ARM64_INS_SUB_ZPmZ_H, - ARM64_INS_SUB_ZPmZ_S, - ARM64_INS_SUB_ZZZ_B, - ARM64_INS_SUB_ZZZ_D, - ARM64_INS_SUB_ZZZ_H, - ARM64_INS_SUB_ZZZ_S, - ARM64_INS_SUBv16i8, - ARM64_INS_SUBv1i64, - ARM64_INS_SUBv2i32, - ARM64_INS_SUBv2i64, - ARM64_INS_SUBv4i16, - ARM64_INS_SUBv4i32, - ARM64_INS_SUBv8i16, - ARM64_INS_SUBv8i8, - ARM64_INS_SUNPKHI_ZZ_D, - ARM64_INS_SUNPKHI_ZZ_H, - ARM64_INS_SUNPKHI_ZZ_S, - ARM64_INS_SUNPKLO_ZZ_D, - ARM64_INS_SUNPKLO_ZZ_H, - ARM64_INS_SUNPKLO_ZZ_S, - ARM64_INS_SUQADDv16i8, - ARM64_INS_SUQADDv1i16, - ARM64_INS_SUQADDv1i32, - ARM64_INS_SUQADDv1i64, - ARM64_INS_SUQADDv1i8, - ARM64_INS_SUQADDv2i32, - ARM64_INS_SUQADDv2i64, - ARM64_INS_SUQADDv4i16, - ARM64_INS_SUQADDv4i32, - ARM64_INS_SUQADDv8i16, - ARM64_INS_SUQADDv8i8, + ARM64_INS_STLR, + ARM64_INS_STLRB, + ARM64_INS_STLRH, + ARM64_INS_STLUR, + ARM64_INS_STLURB, + ARM64_INS_STLURH, + ARM64_INS_STLXP, + ARM64_INS_STLXR, + ARM64_INS_STLXRB, + ARM64_INS_STLXRH, + ARM64_INS_STNP, + ARM64_INS_STNT1B, + ARM64_INS_STNT1D, + ARM64_INS_STNT1H, + ARM64_INS_STNT1W, + ARM64_INS_STP, + ARM64_INS_STR, + ARM64_INS_STRB, + ARM64_INS_STRH, + ARM64_INS_STSET, + ARM64_INS_STSETB, + ARM64_INS_STSETH, + ARM64_INS_STSETL, + ARM64_INS_STSETLB, + ARM64_INS_STSETLH, + ARM64_INS_STSMAX, + ARM64_INS_STSMAXB, + ARM64_INS_STSMAXH, + ARM64_INS_STSMAXL, + ARM64_INS_STSMAXLB, + ARM64_INS_STSMAXLH, + ARM64_INS_STSMIN, + ARM64_INS_STSMINB, + ARM64_INS_STSMINH, + ARM64_INS_STSMINL, + ARM64_INS_STSMINLB, + ARM64_INS_STSMINLH, + ARM64_INS_STTR, + ARM64_INS_STTRB, + ARM64_INS_STTRH, + ARM64_INS_STUMAX, + ARM64_INS_STUMAXB, + ARM64_INS_STUMAXH, + ARM64_INS_STUMAXL, + ARM64_INS_STUMAXLB, + ARM64_INS_STUMAXLH, + ARM64_INS_STUMIN, + ARM64_INS_STUMINB, + ARM64_INS_STUMINH, + ARM64_INS_STUMINL, + ARM64_INS_STUMINLB, + ARM64_INS_STUMINLH, + ARM64_INS_STUR, + ARM64_INS_STURB, + ARM64_INS_STURH, + ARM64_INS_STXP, + ARM64_INS_STXR, + ARM64_INS_STXRB, + ARM64_INS_STXRH, + ARM64_INS_SUB, + ARM64_INS_SUBHN, + ARM64_INS_SUBHN2, + ARM64_INS_SUBR, + ARM64_INS_SUBS, + ARM64_INS_SUNPKHI, + ARM64_INS_SUNPKLO, + ARM64_INS_SUQADD, + ARM64_INS_SVC, + ARM64_INS_SWP, + ARM64_INS_SWPA, ARM64_INS_SWPAB, ARM64_INS_SWPAH, + ARM64_INS_SWPAL, ARM64_INS_SWPALB, ARM64_INS_SWPALH, - ARM64_INS_SWPALW, - ARM64_INS_SWPALX, - ARM64_INS_SWPAW, - ARM64_INS_SWPAX, ARM64_INS_SWPB, ARM64_INS_SWPH, + ARM64_INS_SWPL, ARM64_INS_SWPLB, ARM64_INS_SWPLH, - ARM64_INS_SWPLW, - ARM64_INS_SWPLX, - ARM64_INS_SWPW, - ARM64_INS_SWPX, - ARM64_INS_SXTB_ZPmZ_D, - ARM64_INS_SXTB_ZPmZ_H, - ARM64_INS_SXTB_ZPmZ_S, - ARM64_INS_SXTH_ZPmZ_D, - ARM64_INS_SXTH_ZPmZ_S, - ARM64_INS_SXTW_ZPmZ_D, - ARM64_INS_SYSLxt, - ARM64_INS_SYSxt, - ARM64_INS_TBL_ZZZ_B, - ARM64_INS_TBL_ZZZ_D, - ARM64_INS_TBL_ZZZ_H, - ARM64_INS_TBL_ZZZ_S, - ARM64_INS_TBLv16i8Four, - ARM64_INS_TBLv16i8One, - ARM64_INS_TBLv16i8Three, - ARM64_INS_TBLv16i8Two, - ARM64_INS_TBLv8i8Four, - ARM64_INS_TBLv8i8One, - ARM64_INS_TBLv8i8Three, - ARM64_INS_TBLv8i8Two, - ARM64_INS_TBNZW, - ARM64_INS_TBNZX, - ARM64_INS_TBXv16i8Four, - ARM64_INS_TBXv16i8One, - ARM64_INS_TBXv16i8Three, - ARM64_INS_TBXv16i8Two, - ARM64_INS_TBXv8i8Four, - ARM64_INS_TBXv8i8One, - ARM64_INS_TBXv8i8Three, - ARM64_INS_TBXv8i8Two, - ARM64_INS_TBZW, - ARM64_INS_TBZX, - ARM64_INS_TRN1_PPP_B, - ARM64_INS_TRN1_PPP_D, - ARM64_INS_TRN1_PPP_H, - ARM64_INS_TRN1_PPP_S, - ARM64_INS_TRN1_ZZZ_B, - ARM64_INS_TRN1_ZZZ_D, - ARM64_INS_TRN1_ZZZ_H, - ARM64_INS_TRN1_ZZZ_S, - ARM64_INS_TRN1v16i8, - ARM64_INS_TRN1v2i32, - ARM64_INS_TRN1v2i64, - ARM64_INS_TRN1v4i16, - ARM64_INS_TRN1v4i32, - ARM64_INS_TRN1v8i16, - ARM64_INS_TRN1v8i8, - ARM64_INS_TRN2_PPP_B, - ARM64_INS_TRN2_PPP_D, - ARM64_INS_TRN2_PPP_H, - ARM64_INS_TRN2_PPP_S, - ARM64_INS_TRN2_ZZZ_B, - ARM64_INS_TRN2_ZZZ_D, - ARM64_INS_TRN2_ZZZ_H, - ARM64_INS_TRN2_ZZZ_S, - ARM64_INS_TRN2v16i8, - ARM64_INS_TRN2v2i32, - ARM64_INS_TRN2v2i64, - ARM64_INS_TRN2v4i16, - ARM64_INS_TRN2v4i32, - ARM64_INS_TRN2v8i16, - ARM64_INS_TRN2v8i8, + ARM64_INS_SXTB, + ARM64_INS_SXTH, + ARM64_INS_SXTL, + ARM64_INS_SXTL2, + ARM64_INS_SXTW, + ARM64_INS_SYS, + ARM64_INS_SYSL, + ARM64_INS_TBL, + ARM64_INS_TBNZ, + ARM64_INS_TBX, + ARM64_INS_TBZ, + ARM64_INS_TRN1, + ARM64_INS_TRN2, ARM64_INS_TSB, - ARM64_INS_UABALv16i8_v8i16, - ARM64_INS_UABALv2i32_v2i64, - ARM64_INS_UABALv4i16_v4i32, - ARM64_INS_UABALv4i32_v2i64, - ARM64_INS_UABALv8i16_v4i32, - ARM64_INS_UABALv8i8_v8i16, - ARM64_INS_UABAv16i8, - ARM64_INS_UABAv2i32, - ARM64_INS_UABAv4i16, - ARM64_INS_UABAv4i32, - ARM64_INS_UABAv8i16, - ARM64_INS_UABAv8i8, - ARM64_INS_UABDLv16i8_v8i16, - ARM64_INS_UABDLv2i32_v2i64, - ARM64_INS_UABDLv4i16_v4i32, - ARM64_INS_UABDLv4i32_v2i64, - ARM64_INS_UABDLv8i16_v4i32, - ARM64_INS_UABDLv8i8_v8i16, - ARM64_INS_UABD_ZPmZ_B, - ARM64_INS_UABD_ZPmZ_D, - ARM64_INS_UABD_ZPmZ_H, - ARM64_INS_UABD_ZPmZ_S, - ARM64_INS_UABDv16i8, - ARM64_INS_UABDv2i32, - ARM64_INS_UABDv4i16, - ARM64_INS_UABDv4i32, - ARM64_INS_UABDv8i16, - ARM64_INS_UABDv8i8, - ARM64_INS_UADALPv16i8_v8i16, - ARM64_INS_UADALPv2i32_v1i64, - ARM64_INS_UADALPv4i16_v2i32, - ARM64_INS_UADALPv4i32_v2i64, - ARM64_INS_UADALPv8i16_v4i32, - ARM64_INS_UADALPv8i8_v4i16, - ARM64_INS_UADDLPv16i8_v8i16, - ARM64_INS_UADDLPv2i32_v1i64, - ARM64_INS_UADDLPv4i16_v2i32, - ARM64_INS_UADDLPv4i32_v2i64, - ARM64_INS_UADDLPv8i16_v4i32, - ARM64_INS_UADDLPv8i8_v4i16, - ARM64_INS_UADDLVv16i8v, - ARM64_INS_UADDLVv4i16v, - ARM64_INS_UADDLVv4i32v, - ARM64_INS_UADDLVv8i16v, - ARM64_INS_UADDLVv8i8v, - ARM64_INS_UADDLv16i8_v8i16, - ARM64_INS_UADDLv2i32_v2i64, - ARM64_INS_UADDLv4i16_v4i32, - ARM64_INS_UADDLv4i32_v2i64, - ARM64_INS_UADDLv8i16_v4i32, - ARM64_INS_UADDLv8i8_v8i16, - ARM64_INS_UADDV_VPZ_B, - ARM64_INS_UADDV_VPZ_D, - ARM64_INS_UADDV_VPZ_H, - ARM64_INS_UADDV_VPZ_S, - ARM64_INS_UADDWv16i8_v8i16, - ARM64_INS_UADDWv2i32_v2i64, - ARM64_INS_UADDWv4i16_v4i32, - ARM64_INS_UADDWv4i32_v2i64, - ARM64_INS_UADDWv8i16_v4i32, - ARM64_INS_UADDWv8i8_v8i16, - ARM64_INS_UBFMWri, - ARM64_INS_UBFMXri, - ARM64_INS_UCVTFSWDri, - ARM64_INS_UCVTFSWHri, - ARM64_INS_UCVTFSWSri, - ARM64_INS_UCVTFSXDri, - ARM64_INS_UCVTFSXHri, - ARM64_INS_UCVTFSXSri, - ARM64_INS_UCVTFUWDri, - ARM64_INS_UCVTFUWHri, - ARM64_INS_UCVTFUWSri, - ARM64_INS_UCVTFUXDri, - ARM64_INS_UCVTFUXHri, - ARM64_INS_UCVTFUXSri, - ARM64_INS_UCVTF_ZPmZ_DtoD, - ARM64_INS_UCVTF_ZPmZ_DtoH, - ARM64_INS_UCVTF_ZPmZ_DtoS, - ARM64_INS_UCVTF_ZPmZ_HtoH, - ARM64_INS_UCVTF_ZPmZ_StoD, - ARM64_INS_UCVTF_ZPmZ_StoH, - ARM64_INS_UCVTF_ZPmZ_StoS, - ARM64_INS_UCVTFd, - ARM64_INS_UCVTFh, - ARM64_INS_UCVTFs, - ARM64_INS_UCVTFv1i16, - ARM64_INS_UCVTFv1i32, - ARM64_INS_UCVTFv1i64, - ARM64_INS_UCVTFv2f32, - ARM64_INS_UCVTFv2f64, - ARM64_INS_UCVTFv2i32_shift, - ARM64_INS_UCVTFv2i64_shift, - ARM64_INS_UCVTFv4f16, - ARM64_INS_UCVTFv4f32, - ARM64_INS_UCVTFv4i16_shift, - ARM64_INS_UCVTFv4i32_shift, - ARM64_INS_UCVTFv8f16, - ARM64_INS_UCVTFv8i16_shift, - ARM64_INS_UDIVR_ZPmZ_D, - ARM64_INS_UDIVR_ZPmZ_S, - ARM64_INS_UDIVWr, - ARM64_INS_UDIVXr, - ARM64_INS_UDIV_ZPmZ_D, - ARM64_INS_UDIV_ZPmZ_S, - ARM64_INS_UDOT_ZZZI_D, - ARM64_INS_UDOT_ZZZI_S, - ARM64_INS_UDOT_ZZZ_D, - ARM64_INS_UDOT_ZZZ_S, - ARM64_INS_UDOTlanev16i8, - ARM64_INS_UDOTlanev8i8, - ARM64_INS_UDOTv16i8, - ARM64_INS_UDOTv8i8, - ARM64_INS_UHADDv16i8, - ARM64_INS_UHADDv2i32, - ARM64_INS_UHADDv4i16, - ARM64_INS_UHADDv4i32, - ARM64_INS_UHADDv8i16, - ARM64_INS_UHADDv8i8, - ARM64_INS_UHSUBv16i8, - ARM64_INS_UHSUBv2i32, - ARM64_INS_UHSUBv4i16, - ARM64_INS_UHSUBv4i32, - ARM64_INS_UHSUBv8i16, - ARM64_INS_UHSUBv8i8, - ARM64_INS_UMADDLrrr, - ARM64_INS_UMAXPv16i8, - ARM64_INS_UMAXPv2i32, - ARM64_INS_UMAXPv4i16, - ARM64_INS_UMAXPv4i32, - ARM64_INS_UMAXPv8i16, - ARM64_INS_UMAXPv8i8, - ARM64_INS_UMAXV_VPZ_B, - ARM64_INS_UMAXV_VPZ_D, - ARM64_INS_UMAXV_VPZ_H, - ARM64_INS_UMAXV_VPZ_S, - ARM64_INS_UMAXVv16i8v, - ARM64_INS_UMAXVv4i16v, - ARM64_INS_UMAXVv4i32v, - ARM64_INS_UMAXVv8i16v, - ARM64_INS_UMAXVv8i8v, - ARM64_INS_UMAX_ZI_B, - ARM64_INS_UMAX_ZI_D, - ARM64_INS_UMAX_ZI_H, - ARM64_INS_UMAX_ZI_S, - ARM64_INS_UMAX_ZPmZ_B, - ARM64_INS_UMAX_ZPmZ_D, - ARM64_INS_UMAX_ZPmZ_H, - ARM64_INS_UMAX_ZPmZ_S, - ARM64_INS_UMAXv16i8, - ARM64_INS_UMAXv2i32, - ARM64_INS_UMAXv4i16, - ARM64_INS_UMAXv4i32, - ARM64_INS_UMAXv8i16, - ARM64_INS_UMAXv8i8, - ARM64_INS_UMINPv16i8, - ARM64_INS_UMINPv2i32, - ARM64_INS_UMINPv4i16, - ARM64_INS_UMINPv4i32, - ARM64_INS_UMINPv8i16, - ARM64_INS_UMINPv8i8, - ARM64_INS_UMINV_VPZ_B, - ARM64_INS_UMINV_VPZ_D, - ARM64_INS_UMINV_VPZ_H, - ARM64_INS_UMINV_VPZ_S, - ARM64_INS_UMINVv16i8v, - ARM64_INS_UMINVv4i16v, - ARM64_INS_UMINVv4i32v, - ARM64_INS_UMINVv8i16v, - ARM64_INS_UMINVv8i8v, - ARM64_INS_UMIN_ZI_B, - ARM64_INS_UMIN_ZI_D, - ARM64_INS_UMIN_ZI_H, - ARM64_INS_UMIN_ZI_S, - ARM64_INS_UMIN_ZPmZ_B, - ARM64_INS_UMIN_ZPmZ_D, - ARM64_INS_UMIN_ZPmZ_H, - ARM64_INS_UMIN_ZPmZ_S, - ARM64_INS_UMINv16i8, - ARM64_INS_UMINv2i32, - ARM64_INS_UMINv4i16, - ARM64_INS_UMINv4i32, - ARM64_INS_UMINv8i16, - ARM64_INS_UMINv8i8, - ARM64_INS_UMLALv16i8_v8i16, - ARM64_INS_UMLALv2i32_indexed, - ARM64_INS_UMLALv2i32_v2i64, - ARM64_INS_UMLALv4i16_indexed, - ARM64_INS_UMLALv4i16_v4i32, - ARM64_INS_UMLALv4i32_indexed, - ARM64_INS_UMLALv4i32_v2i64, - ARM64_INS_UMLALv8i16_indexed, - ARM64_INS_UMLALv8i16_v4i32, - ARM64_INS_UMLALv8i8_v8i16, - ARM64_INS_UMLSLv16i8_v8i16, - ARM64_INS_UMLSLv2i32_indexed, - ARM64_INS_UMLSLv2i32_v2i64, - ARM64_INS_UMLSLv4i16_indexed, - ARM64_INS_UMLSLv4i16_v4i32, - ARM64_INS_UMLSLv4i32_indexed, - ARM64_INS_UMLSLv4i32_v2i64, - ARM64_INS_UMLSLv8i16_indexed, - ARM64_INS_UMLSLv8i16_v4i32, - ARM64_INS_UMLSLv8i8_v8i16, - ARM64_INS_UMOVvi16, - ARM64_INS_UMOVvi32, - ARM64_INS_UMOVvi64, - ARM64_INS_UMOVvi8, - ARM64_INS_UMSUBLrrr, - ARM64_INS_UMULH_ZPmZ_B, - ARM64_INS_UMULH_ZPmZ_D, - ARM64_INS_UMULH_ZPmZ_H, - ARM64_INS_UMULH_ZPmZ_S, - ARM64_INS_UMULHrr, - ARM64_INS_UMULLv16i8_v8i16, - ARM64_INS_UMULLv2i32_indexed, - ARM64_INS_UMULLv2i32_v2i64, - ARM64_INS_UMULLv4i16_indexed, - ARM64_INS_UMULLv4i16_v4i32, - ARM64_INS_UMULLv4i32_indexed, - ARM64_INS_UMULLv4i32_v2i64, - ARM64_INS_UMULLv8i16_indexed, - ARM64_INS_UMULLv8i16_v4i32, - ARM64_INS_UMULLv8i8_v8i16, - ARM64_INS_UQADD_ZI_B, - ARM64_INS_UQADD_ZI_D, - ARM64_INS_UQADD_ZI_H, - ARM64_INS_UQADD_ZI_S, - ARM64_INS_UQADD_ZZZ_B, - ARM64_INS_UQADD_ZZZ_D, - ARM64_INS_UQADD_ZZZ_H, - ARM64_INS_UQADD_ZZZ_S, - ARM64_INS_UQADDv16i8, - ARM64_INS_UQADDv1i16, - ARM64_INS_UQADDv1i32, - ARM64_INS_UQADDv1i64, - ARM64_INS_UQADDv1i8, - ARM64_INS_UQADDv2i32, - ARM64_INS_UQADDv2i64, - ARM64_INS_UQADDv4i16, - ARM64_INS_UQADDv4i32, - ARM64_INS_UQADDv8i16, - ARM64_INS_UQADDv8i8, - ARM64_INS_UQDECB_WPiI, - ARM64_INS_UQDECB_XPiI, - ARM64_INS_UQDECD_WPiI, - ARM64_INS_UQDECD_XPiI, - ARM64_INS_UQDECD_ZPiI, - ARM64_INS_UQDECH_WPiI, - ARM64_INS_UQDECH_XPiI, - ARM64_INS_UQDECH_ZPiI, - ARM64_INS_UQDECP_WP_B, - ARM64_INS_UQDECP_WP_D, - ARM64_INS_UQDECP_WP_H, - ARM64_INS_UQDECP_WP_S, - ARM64_INS_UQDECP_XP_B, - ARM64_INS_UQDECP_XP_D, - ARM64_INS_UQDECP_XP_H, - ARM64_INS_UQDECP_XP_S, - ARM64_INS_UQDECP_ZP_D, - ARM64_INS_UQDECP_ZP_H, - ARM64_INS_UQDECP_ZP_S, - ARM64_INS_UQDECW_WPiI, - ARM64_INS_UQDECW_XPiI, - ARM64_INS_UQDECW_ZPiI, - ARM64_INS_UQINCB_WPiI, - ARM64_INS_UQINCB_XPiI, - ARM64_INS_UQINCD_WPiI, - ARM64_INS_UQINCD_XPiI, - ARM64_INS_UQINCD_ZPiI, - ARM64_INS_UQINCH_WPiI, - ARM64_INS_UQINCH_XPiI, - ARM64_INS_UQINCH_ZPiI, - ARM64_INS_UQINCP_WP_B, - ARM64_INS_UQINCP_WP_D, - ARM64_INS_UQINCP_WP_H, - ARM64_INS_UQINCP_WP_S, - ARM64_INS_UQINCP_XP_B, - ARM64_INS_UQINCP_XP_D, - ARM64_INS_UQINCP_XP_H, - ARM64_INS_UQINCP_XP_S, - ARM64_INS_UQINCP_ZP_D, - ARM64_INS_UQINCP_ZP_H, - ARM64_INS_UQINCP_ZP_S, - ARM64_INS_UQINCW_WPiI, - ARM64_INS_UQINCW_XPiI, - ARM64_INS_UQINCW_ZPiI, - ARM64_INS_UQRSHLv16i8, - ARM64_INS_UQRSHLv1i16, - ARM64_INS_UQRSHLv1i32, - ARM64_INS_UQRSHLv1i64, - ARM64_INS_UQRSHLv1i8, - ARM64_INS_UQRSHLv2i32, - ARM64_INS_UQRSHLv2i64, - ARM64_INS_UQRSHLv4i16, - ARM64_INS_UQRSHLv4i32, - ARM64_INS_UQRSHLv8i16, - ARM64_INS_UQRSHLv8i8, - ARM64_INS_UQRSHRNb, - ARM64_INS_UQRSHRNh, - ARM64_INS_UQRSHRNs, - ARM64_INS_UQRSHRNv16i8_shift, - ARM64_INS_UQRSHRNv2i32_shift, - ARM64_INS_UQRSHRNv4i16_shift, - ARM64_INS_UQRSHRNv4i32_shift, - ARM64_INS_UQRSHRNv8i16_shift, - ARM64_INS_UQRSHRNv8i8_shift, - ARM64_INS_UQSHLb, - ARM64_INS_UQSHLd, - ARM64_INS_UQSHLh, - ARM64_INS_UQSHLs, - ARM64_INS_UQSHLv16i8, - ARM64_INS_UQSHLv16i8_shift, - ARM64_INS_UQSHLv1i16, - ARM64_INS_UQSHLv1i32, - ARM64_INS_UQSHLv1i64, - ARM64_INS_UQSHLv1i8, - ARM64_INS_UQSHLv2i32, - ARM64_INS_UQSHLv2i32_shift, - ARM64_INS_UQSHLv2i64, - ARM64_INS_UQSHLv2i64_shift, - ARM64_INS_UQSHLv4i16, - ARM64_INS_UQSHLv4i16_shift, - ARM64_INS_UQSHLv4i32, - ARM64_INS_UQSHLv4i32_shift, - ARM64_INS_UQSHLv8i16, - ARM64_INS_UQSHLv8i16_shift, - ARM64_INS_UQSHLv8i8, - ARM64_INS_UQSHLv8i8_shift, - ARM64_INS_UQSHRNb, - ARM64_INS_UQSHRNh, - ARM64_INS_UQSHRNs, - ARM64_INS_UQSHRNv16i8_shift, - ARM64_INS_UQSHRNv2i32_shift, - ARM64_INS_UQSHRNv4i16_shift, - ARM64_INS_UQSHRNv4i32_shift, - ARM64_INS_UQSHRNv8i16_shift, - ARM64_INS_UQSHRNv8i8_shift, - ARM64_INS_UQSUB_ZI_B, - ARM64_INS_UQSUB_ZI_D, - ARM64_INS_UQSUB_ZI_H, - ARM64_INS_UQSUB_ZI_S, - ARM64_INS_UQSUB_ZZZ_B, - ARM64_INS_UQSUB_ZZZ_D, - ARM64_INS_UQSUB_ZZZ_H, - ARM64_INS_UQSUB_ZZZ_S, - ARM64_INS_UQSUBv16i8, - ARM64_INS_UQSUBv1i16, - ARM64_INS_UQSUBv1i32, - ARM64_INS_UQSUBv1i64, - ARM64_INS_UQSUBv1i8, - ARM64_INS_UQSUBv2i32, - ARM64_INS_UQSUBv2i64, - ARM64_INS_UQSUBv4i16, - ARM64_INS_UQSUBv4i32, - ARM64_INS_UQSUBv8i16, - ARM64_INS_UQSUBv8i8, - ARM64_INS_UQXTNv16i8, - ARM64_INS_UQXTNv1i16, - ARM64_INS_UQXTNv1i32, - ARM64_INS_UQXTNv1i8, - ARM64_INS_UQXTNv2i32, - ARM64_INS_UQXTNv4i16, - ARM64_INS_UQXTNv4i32, - ARM64_INS_UQXTNv8i16, - ARM64_INS_UQXTNv8i8, - ARM64_INS_URECPEv2i32, - ARM64_INS_URECPEv4i32, - ARM64_INS_URHADDv16i8, - ARM64_INS_URHADDv2i32, - ARM64_INS_URHADDv4i16, - ARM64_INS_URHADDv4i32, - ARM64_INS_URHADDv8i16, - ARM64_INS_URHADDv8i8, - ARM64_INS_URSHLv16i8, - ARM64_INS_URSHLv1i64, - ARM64_INS_URSHLv2i32, - ARM64_INS_URSHLv2i64, - ARM64_INS_URSHLv4i16, - ARM64_INS_URSHLv4i32, - ARM64_INS_URSHLv8i16, - ARM64_INS_URSHLv8i8, - ARM64_INS_URSHRd, - ARM64_INS_URSHRv16i8_shift, - ARM64_INS_URSHRv2i32_shift, - ARM64_INS_URSHRv2i64_shift, - ARM64_INS_URSHRv4i16_shift, - ARM64_INS_URSHRv4i32_shift, - ARM64_INS_URSHRv8i16_shift, - ARM64_INS_URSHRv8i8_shift, - ARM64_INS_URSQRTEv2i32, - ARM64_INS_URSQRTEv4i32, - ARM64_INS_URSRAd, - ARM64_INS_URSRAv16i8_shift, - ARM64_INS_URSRAv2i32_shift, - ARM64_INS_URSRAv2i64_shift, - ARM64_INS_URSRAv4i16_shift, - ARM64_INS_URSRAv4i32_shift, - ARM64_INS_URSRAv8i16_shift, - ARM64_INS_URSRAv8i8_shift, - ARM64_INS_USHLLv16i8_shift, - ARM64_INS_USHLLv2i32_shift, - ARM64_INS_USHLLv4i16_shift, - ARM64_INS_USHLLv4i32_shift, - ARM64_INS_USHLLv8i16_shift, - ARM64_INS_USHLLv8i8_shift, - ARM64_INS_USHLv16i8, - ARM64_INS_USHLv1i64, - ARM64_INS_USHLv2i32, - ARM64_INS_USHLv2i64, - ARM64_INS_USHLv4i16, - ARM64_INS_USHLv4i32, - ARM64_INS_USHLv8i16, - ARM64_INS_USHLv8i8, - ARM64_INS_USHRd, - ARM64_INS_USHRv16i8_shift, - ARM64_INS_USHRv2i32_shift, - ARM64_INS_USHRv2i64_shift, - ARM64_INS_USHRv4i16_shift, - ARM64_INS_USHRv4i32_shift, - ARM64_INS_USHRv8i16_shift, - ARM64_INS_USHRv8i8_shift, - ARM64_INS_USQADDv16i8, - ARM64_INS_USQADDv1i16, - ARM64_INS_USQADDv1i32, - ARM64_INS_USQADDv1i64, - ARM64_INS_USQADDv1i8, - ARM64_INS_USQADDv2i32, - ARM64_INS_USQADDv2i64, - ARM64_INS_USQADDv4i16, - ARM64_INS_USQADDv4i32, - ARM64_INS_USQADDv8i16, - ARM64_INS_USQADDv8i8, - ARM64_INS_USRAd, - ARM64_INS_USRAv16i8_shift, - ARM64_INS_USRAv2i32_shift, - ARM64_INS_USRAv2i64_shift, - ARM64_INS_USRAv4i16_shift, - ARM64_INS_USRAv4i32_shift, - ARM64_INS_USRAv8i16_shift, - ARM64_INS_USRAv8i8_shift, - ARM64_INS_USUBLv16i8_v8i16, - ARM64_INS_USUBLv2i32_v2i64, - ARM64_INS_USUBLv4i16_v4i32, - ARM64_INS_USUBLv4i32_v2i64, - ARM64_INS_USUBLv8i16_v4i32, - ARM64_INS_USUBLv8i8_v8i16, - ARM64_INS_USUBWv16i8_v8i16, - ARM64_INS_USUBWv2i32_v2i64, - ARM64_INS_USUBWv4i16_v4i32, - ARM64_INS_USUBWv4i32_v2i64, - ARM64_INS_USUBWv8i16_v4i32, - ARM64_INS_USUBWv8i8_v8i16, - ARM64_INS_UUNPKHI_ZZ_D, - ARM64_INS_UUNPKHI_ZZ_H, - ARM64_INS_UUNPKHI_ZZ_S, - ARM64_INS_UUNPKLO_ZZ_D, - ARM64_INS_UUNPKLO_ZZ_H, - ARM64_INS_UUNPKLO_ZZ_S, - ARM64_INS_UXTB_ZPmZ_D, - ARM64_INS_UXTB_ZPmZ_H, - ARM64_INS_UXTB_ZPmZ_S, - ARM64_INS_UXTH_ZPmZ_D, - ARM64_INS_UXTH_ZPmZ_S, - ARM64_INS_UXTW_ZPmZ_D, - ARM64_INS_UZP1_PPP_B, - ARM64_INS_UZP1_PPP_D, - ARM64_INS_UZP1_PPP_H, - ARM64_INS_UZP1_PPP_S, - ARM64_INS_UZP1_ZZZ_B, - ARM64_INS_UZP1_ZZZ_D, - ARM64_INS_UZP1_ZZZ_H, - ARM64_INS_UZP1_ZZZ_S, - ARM64_INS_UZP1v16i8, - ARM64_INS_UZP1v2i32, - ARM64_INS_UZP1v2i64, - ARM64_INS_UZP1v4i16, - ARM64_INS_UZP1v4i32, - ARM64_INS_UZP1v8i16, - ARM64_INS_UZP1v8i8, - ARM64_INS_UZP2_PPP_B, - ARM64_INS_UZP2_PPP_D, - ARM64_INS_UZP2_PPP_H, - ARM64_INS_UZP2_PPP_S, - ARM64_INS_UZP2_ZZZ_B, - ARM64_INS_UZP2_ZZZ_D, - ARM64_INS_UZP2_ZZZ_H, - ARM64_INS_UZP2_ZZZ_S, - ARM64_INS_UZP2v16i8, - ARM64_INS_UZP2v2i32, - ARM64_INS_UZP2v2i64, - ARM64_INS_UZP2v4i16, - ARM64_INS_UZP2v4i32, - ARM64_INS_UZP2v8i16, - ARM64_INS_UZP2v8i8, - ARM64_INS_WHILELE_PWW_B, - ARM64_INS_WHILELE_PWW_D, - ARM64_INS_WHILELE_PWW_H, - ARM64_INS_WHILELE_PWW_S, - ARM64_INS_WHILELE_PXX_B, - ARM64_INS_WHILELE_PXX_D, - ARM64_INS_WHILELE_PXX_H, - ARM64_INS_WHILELE_PXX_S, - ARM64_INS_WHILELO_PWW_B, - ARM64_INS_WHILELO_PWW_D, - ARM64_INS_WHILELO_PWW_H, - ARM64_INS_WHILELO_PWW_S, - ARM64_INS_WHILELO_PXX_B, - ARM64_INS_WHILELO_PXX_D, - ARM64_INS_WHILELO_PXX_H, - ARM64_INS_WHILELO_PXX_S, - ARM64_INS_WHILELS_PWW_B, - ARM64_INS_WHILELS_PWW_D, - ARM64_INS_WHILELS_PWW_H, - ARM64_INS_WHILELS_PWW_S, - ARM64_INS_WHILELS_PXX_B, - ARM64_INS_WHILELS_PXX_D, - ARM64_INS_WHILELS_PXX_H, - ARM64_INS_WHILELS_PXX_S, - ARM64_INS_WHILELT_PWW_B, - ARM64_INS_WHILELT_PWW_D, - ARM64_INS_WHILELT_PWW_H, - ARM64_INS_WHILELT_PWW_S, - ARM64_INS_WHILELT_PXX_B, - ARM64_INS_WHILELT_PXX_D, - ARM64_INS_WHILELT_PXX_H, - ARM64_INS_WHILELT_PXX_S, + ARM64_INS_TST, + ARM64_INS_UABA, + ARM64_INS_UABAL, + ARM64_INS_UABAL2, + ARM64_INS_UABD, + ARM64_INS_UABDL, + ARM64_INS_UABDL2, + ARM64_INS_UADALP, + ARM64_INS_UADDL, + ARM64_INS_UADDL2, + ARM64_INS_UADDLP, + ARM64_INS_UADDLV, + ARM64_INS_UADDV, + ARM64_INS_UADDW, + ARM64_INS_UADDW2, + ARM64_INS_UBFM, + ARM64_INS_UCVTF, + ARM64_INS_UDIV, + ARM64_INS_UDIVR, + ARM64_INS_UDOT, + ARM64_INS_UHADD, + ARM64_INS_UHSUB, + ARM64_INS_UMADDL, + ARM64_INS_UMAX, + ARM64_INS_UMAXP, + ARM64_INS_UMAXV, + ARM64_INS_UMIN, + ARM64_INS_UMINP, + ARM64_INS_UMINV, + ARM64_INS_UMLAL, + ARM64_INS_UMLAL2, + ARM64_INS_UMLSL, + ARM64_INS_UMLSL2, + ARM64_INS_UMNEGL, + ARM64_INS_UMOV, + ARM64_INS_UMSUBL, + ARM64_INS_UMULH, + ARM64_INS_UMULL, + ARM64_INS_UMULL2, + ARM64_INS_UQADD, + ARM64_INS_UQDECB, + ARM64_INS_UQDECD, + ARM64_INS_UQDECH, + ARM64_INS_UQDECP, + ARM64_INS_UQDECW, + ARM64_INS_UQINCB, + ARM64_INS_UQINCD, + ARM64_INS_UQINCH, + ARM64_INS_UQINCP, + ARM64_INS_UQINCW, + ARM64_INS_UQRSHL, + ARM64_INS_UQRSHRN, + ARM64_INS_UQRSHRN2, + ARM64_INS_UQSHL, + ARM64_INS_UQSHRN, + ARM64_INS_UQSHRN2, + ARM64_INS_UQSUB, + ARM64_INS_UQXTN, + ARM64_INS_UQXTN2, + ARM64_INS_URECPE, + ARM64_INS_URHADD, + ARM64_INS_URSHL, + ARM64_INS_URSHR, + ARM64_INS_URSQRTE, + ARM64_INS_URSRA, + ARM64_INS_USHL, + ARM64_INS_USHLL, + ARM64_INS_USHLL2, + ARM64_INS_USHR, + ARM64_INS_USQADD, + ARM64_INS_USRA, + ARM64_INS_USUBL, + ARM64_INS_USUBL2, + ARM64_INS_USUBW, + ARM64_INS_USUBW2, + ARM64_INS_UUNPKHI, + ARM64_INS_UUNPKLO, + ARM64_INS_UXTB, + ARM64_INS_UXTH, + ARM64_INS_UXTL, + ARM64_INS_UXTL2, + ARM64_INS_UXTW, + ARM64_INS_UZP1, + ARM64_INS_UZP2, + ARM64_INS_WFE, + ARM64_INS_WFI, + ARM64_INS_WHILELE, + ARM64_INS_WHILELO, + ARM64_INS_WHILELS, + ARM64_INS_WHILELT, ARM64_INS_WRFFR, ARM64_INS_XAR, ARM64_INS_XPACD, ARM64_INS_XPACI, ARM64_INS_XPACLRI, - ARM64_INS_XTNv16i8, - ARM64_INS_XTNv2i32, - ARM64_INS_XTNv4i16, - ARM64_INS_XTNv4i32, - ARM64_INS_XTNv8i16, - ARM64_INS_XTNv8i8, - ARM64_INS_ZIP1_PPP_B, - ARM64_INS_ZIP1_PPP_D, - ARM64_INS_ZIP1_PPP_H, - ARM64_INS_ZIP1_PPP_S, - ARM64_INS_ZIP1_ZZZ_B, - ARM64_INS_ZIP1_ZZZ_D, - ARM64_INS_ZIP1_ZZZ_H, - ARM64_INS_ZIP1_ZZZ_S, - ARM64_INS_ZIP1v16i8, - ARM64_INS_ZIP1v2i32, - ARM64_INS_ZIP1v2i64, - ARM64_INS_ZIP1v4i16, - ARM64_INS_ZIP1v4i32, - ARM64_INS_ZIP1v8i16, - ARM64_INS_ZIP1v8i8, - ARM64_INS_ZIP2_PPP_B, - ARM64_INS_ZIP2_PPP_D, - ARM64_INS_ZIP2_PPP_H, - ARM64_INS_ZIP2_PPP_S, - ARM64_INS_ZIP2_ZZZ_B, - ARM64_INS_ZIP2_ZZZ_D, - ARM64_INS_ZIP2_ZZZ_H, - ARM64_INS_ZIP2_ZZZ_S, - ARM64_INS_ZIP2v16i8, - ARM64_INS_ZIP2v2i32, - ARM64_INS_ZIP2v2i64, - ARM64_INS_ZIP2v4i16, - ARM64_INS_ZIP2v4i32, - ARM64_INS_ZIP2v8i16, - ARM64_INS_ZIP2v8i8, - ARM64_INS_anonymous_1349, + ARM64_INS_XTN, + ARM64_INS_XTN2, + ARM64_INS_YIELD, + ARM64_INS_ZIP1, + ARM64_INS_ZIP2, + + // alias insn + ARM64_INS_SBFIZ, + ARM64_INS_UBFIZ, + ARM64_INS_SBFX, + ARM64_INS_UBFX, + ARM64_INS_BFI, + ARM64_INS_BFXIL, + ARM64_INS_IC, + ARM64_INS_DC, + ARM64_INS_AT, + ARM64_INS_TLBI, ARM64_INS_ENDING, // <-- mark the end of the list of insn } arm64_insn; @@ -4993,24 +2411,19 @@ typedef enum arm64_insn_group { ARM64_GRP_FPARMV8, ARM64_GRP_NEON, ARM64_GRP_CRC, - - // new - ARM64_GRP_HASAES, - ARM64_GRP_HASCRC, - ARM64_GRP_HASDOTPROD, - ARM64_GRP_HASFPARMV8, - ARM64_GRP_HASFULLFP16, - ARM64_GRP_HASLSE, - ARM64_GRP_HASNEON, - ARM64_GRP_HASRCPC, - ARM64_GRP_HASRDM, - ARM64_GRP_HASSHA2, - ARM64_GRP_HASSHA3, - ARM64_GRP_HASSM4, - ARM64_GRP_HASSVE, - ARM64_GRP_HASV8_1A, - ARM64_GRP_HASV8_3A, - ARM64_GRP_HASV8_4A, + ARM64_GRP_AES, + ARM64_GRP_DOTPROD, + ARM64_GRP_FULLFP16, + ARM64_GRP_LSE, + ARM64_GRP_RCPC, + ARM64_GRP_RDM, + ARM64_GRP_SHA2, + ARM64_GRP_SHA3, + ARM64_GRP_SM4, + ARM64_GRP_SVE, + ARM64_GRP_V8_1A, + ARM64_GRP_V8_3A, + ARM64_GRP_V8_4A, ARM64_GRP_ENDING, // <-- mark the end of the list of groups } arm64_insn_group; @@ -5019,4 +2432,4 @@ typedef enum arm64_insn_group { } #endif -#endif \ No newline at end of file +#endif diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs index 73cbdf5e7..d428a4ba8 100644 --- a/suite/cstest/issues.cs +++ b/suite/cstest/issues.cs @@ -1,3 +1,19 @@ +!# issue 1452 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL +0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; Vector Arrangement Specifier: 0xb + +!# issue 1452 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL +0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; Vector Arrangement Specifier: 0xd + +!# issue 1452 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL +0x20,0x3c,0x03,0x0e == umov w0, v1.b[1] ; Vector Arrangement Specifier: 0x4 + +!# issue 1452 +!# CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL +0x20,0x3c,0x06,0x0e == umov w0, v1.h[1] ; Vector Arrangement Specifier: 0x8 + !# issue x86 BND register (OSS-fuzz #13467) !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0f,0x1a,0x1a == bndldx bnd3, [edx] ; operands[0].type: REG = bnd3 diff --git a/suite/cstest/src/arm64_detail.c b/suite/cstest/src/arm64_detail.c index 266659fa7..e45ba4f6b 100644 --- a/suite/cstest/src/arm64_detail.c +++ b/suite/cstest/src/arm64_detail.c @@ -33,7 +33,7 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg)); break; case ARM64_OP_IMM: - add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm); + add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64, i, op->imm); break; case ARM64_OP_FP: #if defined(_KERNEL_MODE) @@ -75,7 +75,7 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier); break; } - + access = op->access; switch(access) { default: @@ -90,9 +90,11 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) add_str(&result, " ; operands[%u].access: READ | WRITE", i); break; } - - if (op->shift.type != ARM64_SFT_INVALID && op->shift.value) - add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value); + + if (op->shift.type != ARM64_SFT_INVALID && + op->shift.value) + add_str(&result, " ; Shift: type = %u, value = %u", + op->shift.type, op->shift.value); if (op->ext != ARM64_EXT_INVALID) add_str(&result, " ; Ext: %u", op->ext); @@ -100,9 +102,6 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) if (op->vas != ARM64_VAS_INVALID) add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas); - if (op->vess != ARM64_VESS_INVALID) - add_str(&result, " ; Vector Element Size Specifier: %u", op->vess); - if (op->vector_index != -1) add_str(&result, " ; Vector Index: %u", op->vector_index); } @@ -116,14 +115,17 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins) if (arm64->cc) add_str(&result, " ; Code-condition: %u", arm64->cc); - if (!cs_regs_access(*handle, ins, regs_read, ®s_read_count, regs_write, ®s_write_count)) { + // Print out all registers accessed by this instruction (either implicit or explicit) + if (!cs_regs_access(*handle, ins, + regs_read, ®s_read_count, + regs_write, ®s_write_count)) { if (regs_read_count) { add_str(&result, " ; Registers read:"); for(i = 0; i < regs_read_count; i++) { add_str(&result, " %s", cs_reg_name(*handle, regs_read[i])); } } - + if (regs_write_count) { add_str(&result, " ; Registers modified:"); for(i = 0; i < regs_write_count; i++) { diff --git a/tests/test_arm64.c b/tests/test_arm64.c index 33d4f7df3..46e0a35c4 100644 --- a/tests/test_arm64.c +++ b/tests/test_arm64.c @@ -123,9 +123,6 @@ static void print_insn_detail(cs_insn *ins) if (op->vas != ARM64_VAS_INVALID) printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas); - if (op->vess != ARM64_VESS_INVALID) - printf("\t\t\tVector Element Size Specifier: %u\n", op->vess); - if (op->vector_index != -1) printf("\t\t\tVector Index: %u\n", op->vector_index); } diff --git a/utils.c b/utils.c index 2a89e2bee..194e070b1 100644 --- a/utils.c +++ b/utils.c @@ -137,3 +137,33 @@ bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id) return false; } +// binary search for encoding in IndexType array +// return -1 if not found, or index if found +unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding) +{ + // binary searching since the index is sorted in encoding order + size_t left, right, m; + + right = size - 1; + + if (encoding < index[0].encoding || encoding > index[right].encoding) + // not found + return -1; + + left = 0; + + while(left <= right) { + m = (left + right) / 2; + if (encoding == index[m].encoding) { + return m; + } + + if (encoding < index[m].encoding) + right = m - 1; + else + left = m + 1; + } + + // not found + return -1; +} diff --git a/utils.h b/utils.h index 2c45b8698..520e0b419 100644 --- a/utils.h +++ b/utils.h @@ -68,5 +68,14 @@ bool arr_exist8(unsigned char *arr, unsigned char max, unsigned int id); bool arr_exist(uint16_t *arr, unsigned char max, unsigned int id); +struct IndexType { + uint16_t encoding; + unsigned index; +}; + +// binary search for encoding in IndexType array +// return -1 if not found, or index if found +unsigned int binsearch_IndexTypeEncoding(const struct IndexType *index, size_t size, uint16_t encoding); + #endif