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https://github.com/capstone-engine/capstone
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8a6fca85e4
* Branch targets are a separate addressing mode Branch targets are relative displacements that identify code locations. These are neither .w nor .l nor immediates. This change removes the immediate #s before branch target addresses in disassembly, and represents the actual branch instructions more accurately in the cs_m68k_op datastructure. M68K Python bindings have also been updated. * m68k_inst.pc handles better; print target for PC relative offsets Previous changes to branch operations relied on m68k_inst.pc pointing to (start of instruction + 2). This was not the case - it pointed to the end of the current instruction. This change makes it so that m68k_inst.pc points to (start of instruction), which is simple to work with. It also changes printing of PC relative offsets to print the absolute target address, which is consistent with how most 68000 assemblers & disassemblers behave.
120 lines
4.3 KiB
Python
Executable file
120 lines
4.3 KiB
Python
Executable file
#!/usr/bin/env python
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# Capstone Python bindings, by Nicolas PLANEL <nplanel@gmail.com>
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from __future__ import print_function
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from capstone import *
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from capstone.m68k import *
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from xprint import to_hex, to_x
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M68K_CODE = b"\x4c\x00\x54\x04\x48\xe7\xe0\x30\x4c\xdf\x0c\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4e\xb9\x00\x00\x00\x12\x4e\x75"
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all_tests = (
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(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K"),
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)
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s_addressing_modes = {
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0: "<invalid mode>",
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1: "Register Direct - Data",
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2: "Register Direct - Address",
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3: "Register Indirect - Address",
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4: "Register Indirect - Address with Postincrement",
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5: "Register Indirect - Address with Predecrement",
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6: "Register Indirect - Address with Displacement",
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7: "Address Register Indirect With Index - 8-bit displacement",
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8: "Address Register Indirect With Index - Base displacement",
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9: "Memory indirect - Postindex",
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10: "Memory indirect - Preindex",
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11: "Program Counter Indirect - with Displacement",
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12: "Program Counter Indirect with Index - with 8-Bit Displacement",
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13: "Program Counter Indirect with Index - with Base Displacement",
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14: "Program Counter Memory Indirect - Postindexed",
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15: "Program Counter Memory Indirect - Preindexed",
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16: "Absolute Data Addressing - Short",
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17: "Absolute Data Addressing - Long",
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18: "Immediate value",
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19: "Branch Displacement",
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}
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def print_read_write_regs(insn):
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for m in insn.regs_read:
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print("\treading from reg: %s" % insn.reg_name(m))
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for m in insn.regs_write:
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print("\twriting to reg: %s" % insn.reg_name(m))
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def print_insn_detail(insn):
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if len(insn.operands) > 0:
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print("\top_count: %u" % (len(insn.operands)))
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print("\tgroups_count: %u" % len(insn.groups))
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print_read_write_regs(insn)
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for i, op in enumerate(insn.operands):
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if op.type == M68K_OP_REG:
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print("\t\toperands[%u].type: REG = %s" % (i, insn.reg_name(op.reg)))
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elif op.type == M68K_OP_IMM:
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print("\t\toperands[%u].type: IMM = 0x%x" % (i, op.imm & 0xffffffff))
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elif op.type == M68K_OP_MEM:
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print("\t\toperands[%u].type: MEM" % (i))
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if op.mem.base_reg != M68K_REG_INVALID:
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print("\t\t\toperands[%u].mem.base: REG = %s" % (i, insn.reg_name(op.mem.base_reg)))
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if op.mem.index_reg != M68K_REG_INVALID:
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print("\t\t\toperands[%u].mem.index: REG = %s" % (i, insn.reg_name(op.mem.index_reg)))
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mem_index_str = "w"
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if op.mem.index_size > 0:
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mem_index_str = "l"
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print("\t\t\toperands[%u].mem.index: size = %s" % (i, mem_index_str))
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if op.mem.disp != 0:
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print("\t\t\toperands[%u].mem.disp: 0x%x" % (i, op.mem.disp))
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if op.mem.scale != 0:
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print("\t\t\toperands[%u].mem.scale: %d" % (i, op.mem.scale))
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print("\t\taddress mode: %s" % (s_addressing_modes[op.address_mode]))
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elif op.type == M68K_OP_FP_SINGLE:
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print("\t\toperands[%u].type: FP_SINGLE" % i)
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print("\t\toperands[%u].simm: %f", i, op.simm)
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elif op.type == M68K_OP_FP_DOUBLE:
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print("\t\toperands[%u].type: FP_DOUBLE" % i)
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print("\t\toperands[%u].dimm: %lf", i, op.dimm)
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elif op.type == M68K_OP_BR_DISP:
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print("\t\toperands[%u].br_disp.disp: 0x%x" % (i, op.br_disp.disp))
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print("\t\toperands[%u].br_disp.disp_size: %d" % (i, op.br_disp.disp_size))
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print()
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# ## Test class Cs
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def test_class():
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address = 0x01000
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for (arch, mode, code, comment) in all_tests:
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print("*" * 16)
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print("Platform: %s" % comment)
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print("Code: %s " % to_hex(code))
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print("Disasm:")
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try:
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md = Cs(arch, mode)
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md.detail = True
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last_address = 0
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for insn in md.disasm(code, address):
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last_address = insn.address + insn.size
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print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
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print_insn_detail(insn)
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print("0x%x:\n" % (last_address))
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except CsError as e:
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print("ERROR: %s" % e.__str__())
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if __name__ == '__main__':
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test_class()
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