Exact

Exact Union RegExp

مصطفي محمود كمال الدين ec6428f92d Refactoring the RISCV architecture to Auto-Sync on LLVM (#2756) ... - Updated to LLVM-18 - Operands have now read/write access information - Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...) - Changed register names * FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F` and `RISCV_REG_F<n>_D` for n in `0..31` - Added register names * Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples * `RISCV_REG_V21` * `RISCV_REG_V9_V10` * `RISCV_REG_V3_V4_V5` * etc... up to 8-register combinations * Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31` - Changed instruction names * Instructions ending in `_AQ_RL` now end in `_AQRL` - Added instruction names: massive amount, see `include/capstone/riscv.h` - Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type` * `dimm` is used for instructions with FP immediates * `csr` is used for instructions with CSR systrem registes - Added ISA flags to turn ISA extensions on and off		2026-02-01 11:53:24 +00:00
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unit_test.h	Refactoring the RISCV architecture to Auto-Sync on LLVM (#2756)	2026-02-01 11:53:24 +00:00