mirror of
https://github.com/capstone-engine/capstone
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22b4d0eb41
* Added new M680X target. Supports M6800/1/2/3/9, HD6301 * M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT * M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec > k cpu type, no default. * M680X: Add python bindings. Added python tests. * M680X: Added cpu types to usage message. * cstool: Avoid segfault for invalid <arch+mode>. * Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched. * M680X: Update CMake/make for m680x support. Update .gitignore. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Reduce compiler warnings. * M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). * M680X: Add ocaml bindings and tests. * M680X: Add java bindings and tests. * M680X: Added tests for all indexed addressing modes. C/Python/Ocaml * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Naming, use page1 for PAGE1 instructions (without prefix). * M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml. * M680X: Added access property to cs_m680x_op. * M680X: Added operand size. * M680X: Remove compiler warnings. * M680X: Added READ/WRITE access property per operator. * M680X: Make reg_inherent_hdlr independent of CPU type. * M680X: Add HD6309 support + bug fixes * M680X: Remove errors and warning. * M680X: Add Bcc/LBcc to group BRAREL (relative branch). * M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN. * M680X: Remove LBRN from group BRAREL. * M680X: Refactored cpu_type initialization for better readability. * M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX. * M680X: Remove typo in cstool.c * M680X: Some format improvements in changed_regs. * M680X: Remove insn id string list from tests (C/python/java/ocaml). * M680X: SEXW, set access of reg. D to WRITE. * M680X: Sort changed_regs in increasing m680x_insn order. * M680X: Add M68HC11 support + Reduced from two to one INDEXED operand. * M680X: cstool, also write '(in mnemonic)' for second reg. operand. * M680X: Add BRN/LBRN to group JUMP and BRAREL. * M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access. * M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED. * M680X: Rename some instruction handlers. * M680X: Add M68HC05 support. * M680X: Dont print prefix '<' for direct addr. mode. * M680X: Add M68HC08 support + resorted tables + bug fixes. * M680X: Add Freescale HCS08 support. * M680X: Changed group names, avoid spaces. * M680X: Refactoring, rename addessing mode handlers. * M680X: indexed addr. mode, changed pre/post inc-/decrement representation. * M680X: Rename some M6809/HD6309 specific functions. * M680X: Add CPU12 (68HC12/HCS12) support. * M680X: Correctly display illegal instruction as FCB . * M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg. * M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing. * M680X: Better support for changing insn id within handler for addessing mode. * M680X: Remove warnings. * M680X: In set_changed_regs_read_write_counts use own access_mode. * M680X: Split cpu specific tables into separate *.inc files. * M680X: Remove warnings. * M680X: Removed address_mode. Addressing mode is available in operand.type * M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg. * M680X: Remove register TMP1. It is first visible in CPU12X. * M680X: Performance improvement + bug fixes. * M680X: Performance improvement, make cpu_tables const static. * M680X: Simplify operand decoding by using two handlers. * M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings. * M680X: Format with astyle. * M680X: Update documentation. * M680X: Corrected author for m680x specific files. * M680X: Make max. number of architectures single source.
108 lines
5.8 KiB
Python
Executable file
108 lines
5.8 KiB
Python
Executable file
#!/usr/bin/env python
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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from __future__ import print_function
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from capstone import *
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X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
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X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
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X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
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ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
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ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
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THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
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THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88"
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THUMB_MCLASS = b"\xef\xf3\x02\x80"
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ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
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MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
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MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
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MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
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MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
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ARM64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
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PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
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PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
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SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
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SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
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SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
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XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
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M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
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M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
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all_tests = (
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(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
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(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
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(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
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(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
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(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
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(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
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(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
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(CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None),
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(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
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(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
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(CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
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(CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
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(CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K (68040)", None),
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(CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
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)
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def print_detail(insn):
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print("0x%x:\t%s\t%s // insn-ID: %u, insn-mnem: %s" \
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% (insn.address, insn.mnemonic, insn.op_str, insn.id, \
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insn.insn_name()))
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# "data" instruction generated by SKIPDATA option has no detail
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if insn.id == 0:
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return
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if len(insn.regs_read) > 0:
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print("\tImplicit registers read: ", end=''),
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for m in insn.regs_read:
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print("%s " % insn.reg_name(m), end=''),
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print()
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if len(insn.regs_write) > 0:
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print("\tImplicit registers modified: ", end=''),
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for m in insn.regs_write:
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print("%s " % insn.reg_name(m), end=''),
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print()
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if len(insn.groups) > 0:
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print("\tThis instruction belongs to groups: ", end=''),
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for m in insn.groups:
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print("%s " % insn.group_name(m), end=''),
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print()
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# ## Test class Cs
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def test_class():
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for (arch, mode, code, comment, syntax) in all_tests:
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print('*' * 40)
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print("Platform: %s" % comment)
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print("Disasm:")
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try:
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md = Cs(arch, mode)
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md.detail = True
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if syntax is not None:
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md.syntax = syntax
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for insn in md.disasm(code, 0x1000):
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print_detail(insn)
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print()
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except CsError as e:
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print("ERROR: %s" % e)
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if __name__ == '__main__':
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test_class()
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