mirror of
https://github.com/capstone-engine/capstone
synced 2026-08-11 16:26:07 -04:00
104f693c11
* Add auto-sync updater. * Update Capstone core with auto-sync changes. * Update ARM via auto-sync. * Make changes to arch modules which are introduced by auto-sync. * Update tests for ARM. * Fix build warnings for make * Remove meson.build * Print shift amount in decimal * Patch non LLVM register alias. * Change type of immediate operand to unsiged (due to: #771) * Replace all occurances of a register with its alias. * Fix printing of signed imms * Print rotate amount in decimal * CHange imm type to int64_t to match LLVM imm type. * Fix search for register names, by completing string first. * Print ModImm operands always in decimal * Use number format of previous capstone version. * Correct implicit writes and update_flags according to SBit. * Add missing test for RegImmShift * Reverse incorrect comparision. * Set shift information for move instructions. * Set mem access for all memory operands * Set subtracted flag if offset is negative. * Add flag for post-index memory operands. * Add detail op for BX_RET and MOVPCLR * Use instruction post_index operand. * Add VPOP and VPUSH as unique CS IDs. * Add shifting info for MOVsr. * Add TODOs. * Add in LLVM hardcoded operands to detail. * Move detail editing from InstPrinter to Mapping * Formatting * Add removed check. * Add writeback register and constraints to RFEI instructions. * Translate shift immediate * Print negative immediates * Remove duplicate invalid entry * Add CS groups to instructions * Fix write attriutes of stores. * Add missing names of added instructions * Fix LLVM bug * Add more post_index flags * http -> https * Make generated functions static * Remove tab prefix for alias instructions. * Set ValidateMCOperand to NULL. * Fix AddrMode3Operand operands * Allow getting system and banked register name via API * Add writeback to STC/LDC instructions. * Fix (hopefully) last case where disp is negative and subtracted = true * Remove accidentially introduced regressions
68 lines
3.3 KiB
C#
68 lines
3.3 KiB
C#
# CS_ARCH_ARM, CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS, None
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0x9d,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [sp]
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0x90,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]
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0xb0,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r0]!
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0x9b,0xfc,0x00,0x1e = vld20.8 {q0, q1}, [r11]
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0xb0,0xfc,0x00,0xbe = vld20.8 {q5, q6}, [r0]!
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0x90,0xfc,0x20,0x1e = vld21.8 {q0, q1}, [r0]
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0xb0,0xfc,0x20,0x7e = vld21.8 {q3, q4}, [r0]!
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0x90,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]
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0xb0,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r0]!
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0x9b,0xfc,0x80,0x1e = vld20.16 {q0, q1}, [r11]
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0xb0,0xfc,0x80,0xbe = vld20.16 {q5, q6}, [r0]!
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0x90,0xfc,0xa0,0x1e = vld21.16 {q0, q1}, [r0]
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0xb0,0xfc,0xa0,0x7e = vld21.16 {q3, q4}, [r0]!
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0x90,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]
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0xb0,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r0]!
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0x9b,0xfc,0x00,0x1f = vld20.32 {q0, q1}, [r11]
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0xb0,0xfc,0x00,0xbf = vld20.32 {q5, q6}, [r0]!
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0x90,0xfc,0x20,0x1f = vld21.32 {q0, q1}, [r0]
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0xb0,0xfc,0x20,0x7f = vld21.32 {q3, q4}, [r0]!
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0x80,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]
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0xa0,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r0]!
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0x8b,0xfc,0x00,0x1e = vst20.8 {q0, q1}, [r11]
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0xa0,0xfc,0x00,0xbe = vst20.8 {q5, q6}, [r0]!
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0x80,0xfc,0x20,0x1e = vst21.8 {q0, q1}, [r0]
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0xa0,0xfc,0x20,0x7e = vst21.8 {q3, q4}, [r0]!
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0x80,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]
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0xa0,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r0]!
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0x8b,0xfc,0x80,0x1e = vst20.16 {q0, q1}, [r11]
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0xa0,0xfc,0x80,0xbe = vst20.16 {q5, q6}, [r0]!
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0x80,0xfc,0xa0,0x1e = vst21.16 {q0, q1}, [r0]
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0xa0,0xfc,0xa0,0x7e = vst21.16 {q3, q4}, [r0]!
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0x80,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]
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0xa0,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r0]!
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0x8b,0xfc,0x00,0x1f = vst20.32 {q0, q1}, [r11]
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0xa0,0xfc,0x00,0xbf = vst20.32 {q5, q6}, [r0]!
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0x80,0xfc,0x20,0x1f = vst21.32 {q0, q1}, [r0]
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0xa0,0xfc,0x20,0x7f = vst21.32 {q3, q4}, [r0]!
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0x90,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r0]!
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0x9b,0xfc,0x01,0x1e = vld40.8 {q0, q1, q2, q3}, [r11]
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0xb0,0xfc,0x01,0x7e = vld40.8 {q3, q4, q5, q6}, [r0]!
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0x90,0xfc,0x21,0x1e = vld41.8 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x21,0x9e = vld41.8 {q4, q5, q6, q7}, [r0]!
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0x90,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x41,0x1e = vld42.8 {q0, q1, q2, q3}, [r0]!
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0x90,0xfc,0x61,0x1e = vld43.8 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x61,0x9e = vld43.8 {q4, q5, q6, q7}, [r0]!
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0x90,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r0]!
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0x9b,0xfc,0x81,0x1e = vld40.16 {q0, q1, q2, q3}, [r11]
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0xb0,0xfc,0x81,0x7e = vld40.16 {q3, q4, q5, q6}, [r0]!
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0x90,0xfc,0xa1,0x1e = vld41.16 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0xa1,0x9e = vld41.16 {q4, q5, q6, q7}, [r0]!
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0x90,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0xc1,0x1e = vld42.16 {q0, q1, q2, q3}, [r0]!
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0x90,0xfc,0xe1,0x1e = vld43.16 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0xe1,0x9e = vld43.16 {q4, q5, q6, q7}, [r0]!
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0x90,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r0]!
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0x9b,0xfc,0x01,0x1f = vld40.32 {q0, q1, q2, q3}, [r11]
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0xb0,0xfc,0x01,0x7f = vld40.32 {q3, q4, q5, q6}, [r0]!
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0x90,0xfc,0x21,0x1f = vld41.32 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x21,0x9f = vld41.32 {q4, q5, q6, q7}, [r0]!
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0x90,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x41,0x1f = vld42.32 {q0, q1, q2, q3}, [r0]!
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0x90,0xfc,0x61,0x1f = vld43.32 {q0, q1, q2, q3}, [r0]
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0xb0,0xfc,0x61,0x9f = vld43.32 {q4, q5, q6, q7}, [r0]!
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