mirror of
https://github.com/capstone-engine/capstone
synced 2026-08-11 16:26:07 -04:00
190 lines
8.2 KiB
Python
Executable file
190 lines
8.2 KiB
Python
Executable file
#!/usr/bin/env python
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# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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from __future__ import print_function
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from capstone import *
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from capstone.arm import *
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from xprint import to_hex, to_x_32
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ARM_CODE = b"\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
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ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
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THUMB_CODE = b"\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
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THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
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THUMB_MCLASS = b"\xef\xf3\x02\x80"
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ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
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all_tests = (
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "Thumb", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, ARM_CODE2, "Thumb-mixed", None),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2 & register named with numbers", CS_OPT_SYNTAX_NOREGNAME),
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(CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
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(CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
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)
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def print_insn_detail(insn):
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# print address, mnemonic and operands
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print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
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# "data" instruction generated by SKIPDATA option has no detail
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if insn.id == 0:
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return
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if len(insn.operands) > 0:
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print("\top_count: %u" % len(insn.operands))
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c = 0
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for i in insn.operands:
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if i.type == ARM_OP_REG:
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print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
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elif i.type == ARM_OP_IMM:
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print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
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elif i.type == ARM_OP_FP:
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print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
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elif i.type == ARM_OP_PRED:
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print("\t\toperands[%u].type: PRED = %d" % (c, i.pred))
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elif i.type == ARM_OP_CIMM:
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print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
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elif i.type == ARM_OP_PIMM:
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print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm))
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elif i.type == ARM_OP_SETEND:
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if i.setend == ARM_SETEND_BE:
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print("\t\toperands[%u].type: SETEND = be" % c)
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else:
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print("\t\toperands[%u].type: SETEND = le" % c)
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elif i.type == ARM_OP_MEM:
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print("\t\toperands[%u].type: MEM" % c)
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if i.mem.base != 0:
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print("\t\t\toperands[%u].mem.base: REG = %s" \
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% (c, insn.reg_name(i.mem.base)))
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if i.mem.index != 0:
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print("\t\t\toperands[%u].mem.index: REG = %s" \
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% (c, insn.reg_name(i.mem.index)))
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if i.mem.scale != 1:
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print("\t\t\toperands[%u].mem.scale: %u" \
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% (c, i.mem.scale))
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if i.mem.disp != 0:
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print("\t\t\toperands[%u].mem.disp: 0x%s" \
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% (c, to_x_32(i.mem.disp)))
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if i.mem.lshift != 0:
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print("\t\t\toperands[%u].mem.lshift: 0x%s" \
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% (c, to_x_32(i.mem.lshift)))
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elif i.type == ARM_OP_SYSM:
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print("\t\toperands[%u].type: SYSM = 0x%x" % (c, i.sysop.sysm))
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print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
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elif i.type == ARM_OP_SYSREG:
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print("\t\toperands[%u].type: SYSREG = %s" % (c, insn.reg_name(i.sysop.reg.mclasssysreg)))
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print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
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elif i.type == ARM_OP_BANKEDREG:
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print("\t\toperands[%u].type: BANKEDREG = %u" % (c, i.sysop.reg.bankedreg))
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if i.sysop.msr_mask != 2 ** (ctypes.sizeof(ctypes.c_uint8) * 8) - 1:
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print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
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elif i.type in [ARM_OP_SPSR, ARM_OP_CPSR]:
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print("\t\toperands[%u].type: %sPSR = " % (c, "S" if i.type == ARM_OP_SPSR else "C"), end="")
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field = i.sysop.psr_bits
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if (field & ARM_FIELD_SPSR_F) > 0 or (field & ARM_FIELD_CPSR_F) > 0:
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print("f", end="")
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if (field & ARM_FIELD_SPSR_S) > 0 or (field & ARM_FIELD_CPSR_S) > 0:
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print("s", end="")
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if (field & ARM_FIELD_SPSR_X) > 0 or (field & ARM_FIELD_CPSR_X) > 0:
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print("x", end="")
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if (field & ARM_FIELD_SPSR_C) > 0 or (field & ARM_FIELD_CPSR_C) > 0:
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print("c", end="")
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print()
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print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
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else:
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print("\t\toperands[%u].type: UNKNOWN = %u" % (c, i.type))
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if i.neon_lane != -1:
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print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane))
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if i.access == CS_AC_READ:
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print("\t\toperands[%u].access: READ" % (c))
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elif i.access == CS_AC_WRITE:
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print("\t\toperands[%u].access: WRITE" % (c))
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elif i.access == CS_AC_READ | CS_AC_WRITE:
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print("\t\toperands[%u].access: READ | WRITE" % (c))
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if i.shift.type != ARM_SFT_INVALID and i.shift.value:
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if i.shift.type < ARM_SFT_ASR_REG:
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# shift with constant value
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print("\t\t\tShift: %u = %u" \
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% (i.shift.type, i.shift.value))
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else:
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# shift with register
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print("\t\t\tShift: %u = %s" \
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% (i.shift.type, insn.reg_name(i.shift.value)))
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if i.vector_index != -1:
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print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index))
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if i.subtracted:
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print("\t\t\toperands[%u].subtracted = True" %c)
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c += 1
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if not insn.cc in [ARMCC_AL, ARMCC_UNDEF]:
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print("\tCode condition: %u" % insn.cc)
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if insn.vcc != ARMVCC_None:
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print("\tVector code condition: %u" % insn.vcc)
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if insn.update_flags:
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print("\tUpdate-flags: True")
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if insn.writeback:
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if insn.post_index:
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print("\tWrite-back: Post")
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else:
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print("\tWrite-back: Pre")
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if insn.cps_mode:
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print("\tCPSI-mode: %u" %(insn.cps_mode))
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if insn.cps_flag:
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print("\tCPSI-flag: %u" %(insn.cps_flag))
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if insn.vector_data:
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print("\tVector-data: %u" %(insn.vector_data))
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if insn.vector_size:
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print("\tVector-size: %u" %(insn.vector_size))
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if insn.usermode:
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print("\tUser-mode: True")
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if insn.mem_barrier:
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print("\tMemory-barrier: %u" %(insn.mem_barrier))
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if insn.pred_mask:
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print("\tPredicate Mask: 0x%x" %(insn.pred_mask))
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(regs_read, regs_write) = insn.regs_access()
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if len(regs_read) > 0:
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print("\tRegisters read:", end="")
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for r in regs_read:
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print(" %s" %(insn.reg_name(r)), end="")
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print("")
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if len(regs_write) > 0:
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print("\tRegisters modified:", end="")
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for r in regs_write:
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print(" %s" %(insn.reg_name(r)), end="")
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print("")
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# ## Test class Cs
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def test_class():
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for (arch, mode, code, comment, syntax) in all_tests:
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print("*" * 16)
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print("Platform: %s" % comment)
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print("Code: %s" % to_hex(code))
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print("Disasm:")
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try:
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md = Cs(arch, mode)
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if syntax is not None:
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md.syntax = syntax
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md.detail = True
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for insn in md.disasm(code, 0x80001000):
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print_insn_detail(insn)
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print ()
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print("0x%x:\n" % (insn.address + insn.size))
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except CsError as e:
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print("ERROR: %s" % e)
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if __name__ == '__main__':
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test_class()
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