NAME=ands (opcode) triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0
wx 022012e0
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=ands (opcode) triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=5
aer cpsr=0x40000000
wx 022012e0
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=ands triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0
wa ands r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=ands triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=5
aer cpsr=0x40000000
wa ands r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=and (no s flag) does not trigger zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0x00000000
wa and r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=and (no s flag) does not trigger zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=5
aer cpsr=0x40000000
wa and r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=orrs triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0
wa orrs r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=orrs triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=5
aer cpsr=0x40000000
wa orrs r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=orrs (opcode) triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0
wx 022092e1
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=orrs (opcode) triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=5
aer cpsr=0x40000000
wx 022092e1
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=orr (no s flag) does not trigger zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0x00000000
wa orr r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=orr (no s flag) does not trigger zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=5
aer cpsr=0x40000000
wa orr r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=adds triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0
wa adds r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=adds triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer r1=5
aer cpsr=0x40000000
wa adds r1,r2 
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=add (no s flag) does not trigger zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=0
aer cpsr=0
wa add r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=add (no s flag) does not trigger zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer r1=5
aer cpsr=0x40000000
wa add r1, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=eors (opcode) triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=1
aer cpsr=0
wx 022032e0
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=eors (opcode) triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer r1=5
aer cpsr=0x40000000
wx 021031e0
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=eors triggers zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=1
aer cpsr=0
wa eors r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=eors triggers zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer r1=5
aer cpsr=0x40000000
wa eors r1,r2 
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=eor (no s flag) does not trigger zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=1
aer cpsr=0
wa eor r2, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=eor (no s flag) does not trigger zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer r1=5
aer cpsr=0x40000000
wa eor r1, r2
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=subs triggers zf and cf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=1
aer cpsr=0
wa subs r2, r2, 1
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x60000000
EOF
RUN

NAME=subs triggers cf and zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer cpsr=0x40000000
wa subs r2, r2, 1
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x20000000
EOF
RUN

NAME=sub (no s flag) does not trigger zf
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=1
aer cpsr=0
wa sub r2, r2, 1
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x00000000
EOF
RUN

NAME=sub (no s flag) does not trigger zf off
FILE=-
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aer r2=2
aer cpsr=0x40000000
wa sub r2, r2, 1
aes
aer?cpsr
EOF
EXPECT=<<EOF
0x40000000
EOF
RUN

NAME=cmp neq unchanged zf
FILE=malloc://0x200
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aei
aeim
aer sp=0x00108000
.aer*
wa cmp r1, 16
aes
?v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x80000000
EOF
RUN

NAME=cmp neq changed zf
FILE=malloc://0x200
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aei
aeim
aer sp=0x00108000
aer cpsr=0xffffffff
.aer*
wa cmp r1, 16
aes
?v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x80000000
EOF
RUN

NAME=cmp eq unchanged zf
FILE=malloc://0x200
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aei
aeim
aer sp=0x00108000
aer r1=0x10
aer cpsr=0x40000000
.aer*
wa cmp r1, 16
aes
?v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x60000000
EOF
RUN

NAME=cmp eq changed zf
FILE=malloc://0x200
CMDS=<<EOF
e esil.debug=true
e asm.arch=arm
e asm.bits=32
aei
aeim
aer sp=0x00108000
aer cpsr=0xffffffff
.aer*
wa cmp r1, 16
aes
?v cpsr & 0xf0000000
EOF
EXPECT=<<EOF
0x80000000
EOF
RUN

NAME=tst nz
FILE=-
CMDS=<<EOF
e asm.bytes=true
e asm.arch=arm
e asm.bits=32
wx 050010e3 0100a003
pd 2
ao 2~esil
aei
ar r0=4
2aes
ar?r0
EOF
EXPECT=<<EOF
            0x00000000      050010e3       tst   r0, 5
            0x00000004      0100a003       moveq r0, 1
esilcost: 0
esil: 0,5,r0,&,==,$z,zf,:=,31,$s,nf,:=
esilcost: 0
esil: zf,?{,1,r0,=,}
0x00000004
EOF
RUN

NAME=ldr r0, [r1, 7]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar > /dev/null
ar r0=0
ar r1=1
wx 070091e5
wx aaaaaaaabbbbbbbb44332211@4
aes
ar r0
EOF
EXPECT=<<EOF
0xbbbbbbbb
EOF
RUN

NAME=ldr r0, [r0, 7]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar > /dev/null
ar r0=0
wx 070090e5
wx aaaaaaaabbbbbbbb44332211@4
aes
ar r0
EOF
EXPECT=<<EOF
0xbbbbbbaa
EOF
RUN

NAME=ldr r0, [r0, r1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar > /dev/null
ar r0=4
ar r1=2
wx 010090e7
wx aaaaaaaabbbbbbbb44332211@4
aes
ar r0
EOF
EXPECT=<<EOF
0xbbbbaaaa
EOF
RUN

NAME=ldr r2, [r3, r1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r3=4
ar r1=2
wx 012093e7aabbccddeeff
aes
ar r2
EOF
EXPECT=<<EOF
0xffeeddcc
EOF
RUN

NAME=ldrb r1, [r3, r2, lsl 2]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r3=4
ar r2=1
wx 0211d3e7
wx aabbccdd @ 8
aes
ar r1
EOF
EXPECT=<<EOF
0x000000aa
EOF
RUN

NAME=str r2, [r3, 4]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=0
wx 042083e5aabbccddeeff
aes
p8 4 @4
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000000
EOF
RUN

NAME=str r2, [r3, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=0
wx 052083e5aabbccddeeff
aes
p8 4 @5
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000000
EOF
RUN

NAME=str r2, [r3, r1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=4
ar r1=2
wx 012083e7aabbccddeeff
aes
p8 4 @6
ar r2
ar r3
ar r1
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000004
0x00000002
EOF
RUN

NAME=str r2, [r3, r1]; ldr r2, [r3, r1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=8
ar r1=4
wx 012083e7012093e7aabbccddeeff11223344
aes
aes
ar r2
ar r3
ar r1
EOF
EXPECT=<<EOF
0xdeadbeef
0x00000008
0x00000004
EOF
RUN

NAME=str r1, [r2, r3, lsl 1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx 831082e7aabbccddeeff
aes
p8 4 @8
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000004
0x00000002
EOF
RUN

NAME=str r1, [r2, r3, lsr 1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx a31082e7aabbccddeeff
aes
p8 4 @5
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000004
0x00000002
EOF
RUN

NAME=str r1, [r2, r3, asr 1]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx c31082e7aabbccddeeff
aes
p8 4 @5
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000004
0x00000002
EOF
RUN

NAME=str r1, [r2, r3, ror 23]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=1
wx e31c82e7aabbccddeeff
aes
p8 4 @0x84
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000004
0x00000001
EOF
RUN

NAME=str r2, [r3], 5
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=0
wx 052083e4aabbccddeeff
aes
p8 4 @0
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
EOF
RUN

NAME=str r2, [r3], r1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=4
ar r1=2
wx 012083e6aabbccddeeff
aes
p8 4 @4
ar r2
ar r3
ar r1
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000006
0x00000002
EOF
RUN

NAME=str r1, [r2], r3, lsl 1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx 831082e6aabbccddeeff
aes
p8 4 @4
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000008
0x00000002
EOF
RUN

NAME=str r1, [r2], r3, lsr 1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx a31082e6aabbccddeeff
aes
p8 4 @4
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
0x00000002
EOF
RUN

NAME=str r1, [r2], r3, asr 1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx c31082e6aabbccddeeff
aes
p8 4 @4
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
0x00000002
EOF
RUN

NAME=str r1, [r2], r3, ror 23
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=1
wx e31c82e6aabbccddeeff
aes
p8 4 @4
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000084
0x00000001
EOF
RUN

NAME=str r2, [r3, 5]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=0
wx 0520a3e5aabbccddeeff
aes
p8 4 @5
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
EOF
RUN

NAME=str r2, [r3, -5]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=10
wx 052023e5aabbccddeeff
aes
p8 4 @5
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
EOF
RUN

NAME=str r2, [r3, r1]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=4
ar r1=2
wx 0120a3e7aabbccddeeff
aes
p8 4 @6
ar r2
ar r3
ar r1
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000006
0x00000002
EOF
RUN

NAME=str r2, [r3, r1]! (negative r1)
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r2=0xdeadbeef
ar r3=8
ar r1=-2
wx 0120a3e7aabbccddeeff
aes
p8 4 @6
ar r2
ar r3
ar r1
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000006
0xfffffffe
EOF
RUN

NAME=str r1, [r2, r3, lsl 1]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx 8310a2e7aabbccddeeff
aes
p8 4 @8
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000008
0x00000002
EOF
RUN

NAME=str r1, [r2, r3, lsr 1]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx a310a2e7aabbccddeeff
aes
p8 4 @5
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
0x00000002
EOF
RUN

NAME=str r1, [r2, r3, asr 1]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=2
wx c310a2e7aabbccddeeff
aes
p8 4 @5
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000005
0x00000002
EOF
RUN

NAME=str r1, [r2, r3, ror 23]!
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xdeadbeef
ar r2=4
ar r3=1
wx e31ca2e7aabbccddeeff
aes
p8 4 @0x84
ar r1
ar r2
ar r3
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000084
0x00000001
EOF
RUN

NAME=streq r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508605aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=streq r5, [r6, 5] zf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508605aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strne r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508615aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strne r5, [r6, 5] zf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508615aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strhs r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508625aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strhs r5, [r6, 5] cf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508625aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strlo r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508635aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strlo r5, [r6, 5] cf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508635aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strmi r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508645aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strmi r5, [r6, 5] nf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508645aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strpl r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508655aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strpl r5, [r6, 5] nf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508655aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strvs r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508665aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strvs r5, [r6, 5] vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508665aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strvc r5, [r6, 5]
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508675aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strvc r5, [r6, 5] vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508675aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strhi r5, [r6, 5] cf==0, zf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=0
ar zf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508685aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strhi r5, [r6, 5] cf==0, zf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=0
ar zf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508685aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strhi r5, [r6, 5] cf==1, zf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=1
ar zf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508685aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strhi r5, [r6, 5] zf==0 cf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=1
ar zf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508685aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strls r5, [r6, 5] zf==1 cf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=0
ar zf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508695aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strls r5, [r6, 5] cf==0, zf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=0
ar zf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508695aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strls r5, [r6, 5] cf==1, zf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=1
ar zf=0
ar r5=0xdeadbeef
ar r6=1
wx 05508695aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strls r5, [r6, 5] cf==1, zf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar cf=1
ar zf=1
ar r5=0xdeadbeef
ar r6=1
wx 05508695aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strge r5, [r6, 5] nf==1, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=1
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086a5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strge r5, [r6, 5] nf==0, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086a5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strge r5, [r6, 5] nf==1 vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=1
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086a5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strge r5, [r6, 5] nf==0 vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=0
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086a5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strlt r5, [r6, 5] nf==1 vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=1
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086b5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strlt r5, [r6, 5] nf==0 vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086b5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strlt r5, [r6, 5] nf==0, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=0
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086b5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strlt r5, [r6, 5] nf==1, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar nf=1
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086b5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==1 nf==1, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=1
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==1 nf==0, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==1 nf==0, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=0
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==0 nf==0, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==0 nf==1, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=1
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==0 nf==0, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=0
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strgt r5, [r6, 5] zf==0 nf==1, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=1
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086c5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==1 nf==1, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=1
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==1 nf==0, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=0
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==0 nf==0, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=0
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
ccddeeff
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==0 nf==0, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==0 nf==0, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=0
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==1 nf==1, vf==0
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=1
ar vf=0
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=strle r5, [r6, 5] zf==1 nf==0, vf==1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar zf=1
ar nf=0
ar vf=1
ar r5=0xdeadbeef
ar r6=1
wx 055086d5aabbccddeeff
aes
p8 4 @6
ar r5
ar r6
EOF
EXPECT=<<EOF
efbeadde
0xdeadbeef
0x00000001
EOF
RUN

NAME=add reg
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=1
ar r2=2
wv 0xe0810002
aes
ar r0
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=add reg in place
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r0=1
ar r1=2
wv 0xe0800001
aes
ar r0
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=add reg shifted
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=1
ar r2=4
wv 0xe08100a2
aes
ar r0
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=add reg asr
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=2
ar r2=-1
wv 0xe08100c2
aes
ar r0
EOF
EXPECT=<<EOF
0x00000001
EOF
RUN

NAME=add imm
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=1
wv 0xe2810002
aes
ar r0
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=add imm rotated
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=2
wv 0xe2810104
aes
ar r0
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=sub imm rotated
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xa
wv 0xe2410104
aes
ar r0
EOF
EXPECT=<<EOF
0x00000009
EOF
RUN

NAME=mul reg
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xa
ar r2=0x2
wv 0xe0000291
aes
ar r0
EOF
EXPECT=<<EOF
0x00000014
EOF
RUN

NAME=and imm rotated
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xf
wv 0xe2010104
aes
ar r0
EOF
EXPECT=<<EOF
0x00000001
EOF
RUN

NAME=orr imm rotated
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0x2
wv 0xe3810104
aes
ar r0
EOF
EXPECT=<<EOF
0x00000003
EOF
RUN

NAME=eor imm rotated
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xf
wv 0xe2210104
aes
ar r0
EOF
EXPECT=<<EOF
0x0000000e
EOF
RUN

NAME=lsr reg
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xa
ar r2=0x2
wv 0xe1a00231
aes
ar r0
EOF
EXPECT=<<EOF
0x00000002
EOF
RUN

NAME=lsl reg
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0xa
ar r2=0x2
wv 0xe1a00211
aes
ar r0
EOF
EXPECT=<<EOF
0x00000028
EOF
RUN

NAME=lsl reg same destination and source
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
aer r3=0xffffffaa
wx 0331a0e1
aes
ar r3
ar cpsr
EOF
EXPECT=<<EOF
0xfffffea8
0x00000000
EOF
RUN

NAME=add pc op1
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wv 0xe28f0002
aes
ar r0
EOF
EXPECT=<<EOF
0x0000000a
EOF
RUN

NAME=add pc op2
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
ar r1=0x2
wv 0xe081000f
aes
ar r0
EOF
EXPECT=<<EOF
0x0000000a
EOF
RUN

NAME=pc points to next instruction
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0f00a0e1 # mov r0, pc
aes
aer r0
EOF
EXPECT=<<EOF
0x00000004
EOF
RUN

NAME=lr correct after bl
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 000000eb # bl 8
aes
aer lr
aer pc
EOF
EXPECT=<<EOF
0x00000004
0x00000008
EOF
RUN

NAME=r0 correct after stmia post-increment
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0600a0e8 # stm r0!, {r1, r2}
aes
aer r0
aer pc
EOF
EXPECT=<<EOF
0x00000008
0x00000004
EOF
RUN

NAME=r0 correct after stmia no increment
FILE=malloc://0x200
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 060080e8 # stm r0, {r1, r2}
aes
aer r0
aer pc
EOF
EXPECT=<<EOF
0x00000000
0x00000004
EOF
RUN

NAME=stmib no writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a0080e9 # stmib r0, {r1, r3}
aer r0=8
aer r1=9
aer r3=10
aes
aer r0
p8 12 @8
EOF
EXPECT=<<EOF
0x00000008
00000000090000000a000000
EOF
RUN

NAME=stmda writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a0020e8 # stmda r0!, {r1, r3}
aer r0=16
aer r1=9
aer r3=10
aes
aer r0
p8 12 @8
EOF
EXPECT=<<EOF
0x00000008
00000000090000000a000000
EOF
RUN

NAME=stmdb no writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a0000e9 # stmdb r0, {r1, r3}
aer r0=16
aer r1=9
aer r3=10
aes
aer r0
p8 12 @8
EOF
EXPECT=<<EOF
0x00000010
090000000a00000000000000
EOF
RUN

NAME=r0 and mem correct after vstmia
FILE=malloc://0x200
CMDS=<<EOF
e esil.verbose=2
e asm.arch=arm
e asm.bits=32
wx 041b80ec # vstmia r0, {d1, d2}
ar r0=0x100
ar d1=0x01c00df0fecadec0
ar d2=0xaaaaaaaaaaaaaaaa
aes
aer r0
aer pc
p8 16 @0x100
EOF
EXPECT=<<EOF
0x00000100
0x00000004
c0decafef00dc001aaaaaaaaaaaaaaaa
EOF
RUN

NAME=r0 and mem correct after vstmia writeback
FILE=malloc://0x200
CMDS=<<EOF
e esil.verbose=2
e asm.arch=arm
e asm.bits=32
wx 041ba0ec # vstmia r0!, {d1, d2}
ar r0=0x100
ar d1=0x01c00df0fecadec0
ar d2=0xaaaaaaaaaaaaaaaa
aes
aer r0
aer pc
p8 16 @0x100
EOF
EXPECT=<<EOF
0x00000110
0x00000004
c0decafef00dc001aaaaaaaaaaaaaaaa
EOF
RUN


NAME=r0 and mem correct after vstmdb
FILE=malloc://0x200
CMDS=<<EOF
e esil.verbose=2
e asm.arch=arm
e asm.bits=32
wx 041b20ed # vstmdb r0!, {d1, d2}
ar r0=0x110
ar d1=0x01c00df0fecadec0
ar d2=0xaaaaaaaaaaaaaaaa
aes
aer r0
aer pc
p8 16 @0x100
EOF
EXPECT=<<EOF
0x00000100
0x00000004
c0decafef00dc001aaaaaaaaaaaaaaaa
EOF
RUN

NAME=ldmda no writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a0010e8 # ldmda r0, {r1, r3}
wx 01234567 @8
wx 890abcde @12
aer r0=12
aes
aer r0
aer r1
aer r3
EOF
EXPECT=<<EOF
0x0000000c
0x67452301
0xdebc0a89
EOF
RUN

NAME=ldmdb writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a0030e9 # ldmdb r0!, {r1, r3}
wx 01234567 @8
wx 890abcde @12
aer r0=16
aes
aer r0
aer r1
aer r3
EOF
EXPECT=<<EOF
0x00000008
0x67452301
0xdebc0a89
EOF
RUN

NAME=ldm no writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a0090e8 # ldm r0, {r1, r3}
wx 01234567 @8
wx 890abcde @12
aer r0=8
aes
aer r0
aer r1
aer r3
EOF
EXPECT=<<EOF
0x00000008
0x67452301
0xdebc0a89
EOF
RUN

NAME=ldmib writeback
FILE=-
CMDS=<<EOF
e asm.arch=arm
e asm.bits=32
wx 0a00b0e9 # ldmib r0!, {r1, r3}
wx 01234567 @8
wx 890abcde @12
aer r0=4
aes
aer r0
aer r1
aer r3
EOF
EXPECT=<<EOF
0x0000000c
0x67452301
0xdebc0a89
EOF
RUN

NAME=regs correct after vldmia
FILE=malloc://0x200
CMDS=<<EOF
e esil.verbose=2
e asm.arch=arm
e asm.bits=32
wx 080b93ec # vldmia r3, {d0-d3}
wx c0decafef00dc001aaaaaaaaaaaaaaaa @0x100
ar r3=0x100
aes
aer r3
aer pc
aer d0
aer d1
EOF
EXPECT=<<EOF
0x00000100
0x00000004
0x1c00df0fecadec0
0xaaaaaaaaaaaaaaaa
EOF
RUN

NAME=regs correct after vldmia writeback
FILE=malloc://0x200
CMDS=<<EOF
e esil.verbose=2
e asm.arch=arm
e asm.bits=32
wx 080bb4ec # vldmia r4!, {d0-d3}
wx c0decafef00dc001aaaaaaaaaaaaaaaa @0x100
ar r4=0x100
aes
aer r4
aer pc
aer d0
aer d1
EOF
EXPECT=<<EOF
0x00000120
0x00000004
0x1c00df0fecadec0
0xaaaaaaaaaaaaaaaa
EOF
RUN

NAME=regs correct after vldmdb
FILE=malloc://0x200
CMDS=<<EOF
e esil.verbose=2
e asm.arch=arm
e asm.bits=32
wx 080b35ed # vldmdb r5!, {d0-d3}
wx c0decafef00dc001aaaaaaaaaaaaaaaa @0x100
ar r5=0x120
aes
aer r5
aer pc
aer d0
aer d1
EOF
EXPECT=<<EOF
0x00000100
0x00000004
0x1c00df0fecadec0
0xaaaaaaaaaaaaaaaa
EOF
RUN
