#ifndef HEXAGON_INSN_H
#define HEXAGON_INSN_H

enum HEX_INS {
	HEX_INS_UNKNOWN,
	HEX_INS_IMMEXT,
	HEX_INS_RD___ADD__RS___S16_,
	HEX_INS_RD___ADD__RS__RT_,
	HEX_INS_RD___ADD__RS__RT___SAT,
	HEX_INS_RD___AND__RS___S10_,
	HEX_INS_RD___OR__RS___S10_,
	HEX_INS_RD___AND__RS__RT_,
	HEX_INS_RD___OR__RS__RT_,
	HEX_INS_RD___XOR__RS__RT_,
	HEX_INS_RD___AND__RT___RS_,
	HEX_INS_RD___OR__RT___RS_,
	HEX_INS_NOP,
	HEX_INS_RD___SUB___S10__RS_,
	HEX_INS_RD___SUB__RT__RS_,
	HEX_INS_RD___SUB__RT__RS___SAT,
	HEX_INS_RD___SXTB__RS_,
	HEX_INS_RD___SXTH__RS_,
	HEX_INS_RX_L____U16,
	HEX_INS_RX_H____U16,
	HEX_INS_RD____S16,
	HEX_INS_RD___RS,
	HEX_INS_RD___VADDH__RS__RT_,
	HEX_INS_RD___VADDH__RS__RT___SAT,
	HEX_INS_RD___VADDUH__RS__RT___SAT,
	HEX_INS_RD___VAVGH__RS__RT_,
	HEX_INS_RD___VAVGH__RS__RT___RND,
	HEX_INS_RD___VNAVGH__RT__RS_,
	HEX_INS_RD___VSUBH__RT__RS_,
	HEX_INS_RD___VSUBH__RT__RS___SAT,
	HEX_INS_RD___VSUBUH__RT__RS___SAT,
	HEX_INS_RD___ZXTH__RS_,
	HEX_INS_RDD___COMBINE__RS___S8_,
	HEX_INS_RDD___COMBINE___S8__RS_,
	HEX_INS_RDD___COMBINE___S8___S8_,
	HEX_INS_RDD___COMBINE___S8___U6_,
	HEX_INS_RD___COMBINE__RT_H__RS_H_,
	HEX_INS_RD___COMBINE__RT_H__RS_L_,
	HEX_INS_RD___COMBINE__RT_L__RS_H_,
	HEX_INS_RD___COMBINE__RT_L__RS_L_,
	HEX_INS_RDD___COMBINE__RS__RT_,
	HEX_INS_RD___MUX__PU__RS___S8_,
	HEX_INS_RD___MUX__PU___S8__RS_,
	HEX_INS_RD___MUX__PU___S8___S8_,
	HEX_INS_RD___MUX__PU__RS__RT_,
	HEX_INS_RD___ASLH__RS_,
	HEX_INS_RD___ASRH__RS_,
	HEX_INS_RDD___PACKHL__RS__RT_,
	HEX_INS_IF__PU__RD___ADD__RS___S8_,
	HEX_INS_IF__PU_NEW__RD___ADD__RS___S8_,
	HEX_INS_IF__NOT_PU_RD___ADD__RS___S8_,
	HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS___S8_,
	HEX_INS_IF__PU__RD___ADD__RS__RT_,
	HEX_INS_IF__NOT_PU_RD___ADD__RS__RT_,
	HEX_INS_IF__PU_NEW__RD___ADD__RS__RT_,
	HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS__RT_,
	HEX_INS_IF__PU__RD___ASLH__RS_,
	HEX_INS_IF__PU_NEW__RD___ASLH__RS_,
	HEX_INS_IF__NOT_PU_RD___ASLH__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___ASLH__RS_,
	HEX_INS_IF__PU__RD___ASRH__RS_,
	HEX_INS_IF__PU_NEW__RD___ASRH__RS_,
	HEX_INS_IF__NOT_PU_RD___ASRH__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___ASRH__RS_,
	HEX_INS_IF__PU__RDD___COMBINE__RS__RT_,
	HEX_INS_IF__NOT_PU_RDD___COMBINE__RS__RT_,
	HEX_INS_IF__PU_NEW__RDD___COMBINE__RS__RT_,
	HEX_INS_IF__NOT_PU_NEW_RDD___COMBINE__RS__RT_,
	HEX_INS_IF__PU__RD___AND__RS__RT_,
	HEX_INS_IF__NOT_PU_RD___AND__RS__RT_,
	HEX_INS_IF__PU_NEW__RD___AND__RS__RT_,
	HEX_INS_IF__NOT_PU_NEW_RD___AND__RS__RT_,
	HEX_INS_IF__PU__RD___OR__RS__RT_,
	HEX_INS_IF__NOT_PU_RD___OR__RS__RT_,
	HEX_INS_IF__PU_NEW__RD___OR__RS__RT_,
	HEX_INS_IF__NOT_PU_NEW_RD___OR__RS__RT_,
	HEX_INS_IF__PU__RD___XOR__RS__RT_,
	HEX_INS_IF__NOT_PU_RD___XOR__RS__RT_,
	HEX_INS_IF__PU_NEW__RD___XOR__RS__RT_,
	HEX_INS_IF__NOT_PU_NEW_RD___XOR__RS__RT_,
	HEX_INS_IF__PU__RD___SUB__RT__RS_,
	HEX_INS_IF__NOT_PU_RD___SUB__RT__RS_,
	HEX_INS_IF__PU_NEW__RD___SUB__RT__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___SUB__RT__RS_,
	HEX_INS_IF__PU__RD___SXTB__RS_,
	HEX_INS_IF__PU_NEW__RD___SXTB__RS_,
	HEX_INS_IF__NOT_PU_RD___SXTB__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___SXTB__RS_,
	HEX_INS_IF__PU__RD___SXTH__RS_,
	HEX_INS_IF__PU_NEW__RD___SXTH__RS_,
	HEX_INS_IF__NOT_PU_RD___SXTH__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___SXTH__RS_,
	HEX_INS_IF__PU__RD____S12,
	HEX_INS_IF__PU_NEW__RD____S12,
	HEX_INS_IF__NOT_PU_RD____S12,
	HEX_INS_IF__NOT_PU_NEW_RD____S12,
	HEX_INS_IF__PU__RD___ZXTB__RS_,
	HEX_INS_IF__PU_NEW__RD___ZXTB__RS_,
	HEX_INS_IF__NOT_PU_RD___ZXTB__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___ZXTB__RS_,
	HEX_INS_IF__PU__RD___ZXTH__RS_,
	HEX_INS_IF__PU_NEW__RD___ZXTH__RS_,
	HEX_INS_IF__NOT_PU_RD___ZXTH__RS_,
	HEX_INS_IF__NOT_PU_NEW_RD___ZXTH__RS_,
	HEX_INS_PD___CMP_EQ__RS___S10_,
	HEX_INS_PD____NOT_CMP_EQ__RS___S10_,
	HEX_INS_PD___CMP_GT__RS___S10_,
	HEX_INS_PD____NOT_CMP_GT__RS___S10_,
	HEX_INS_PD___CMP_GTU__RS___U9_,
	HEX_INS_PD____NOT_CMP_GTU__RS___U9_,
	HEX_INS_PD___CMP_EQ__RS__RT_,
	HEX_INS_PD____NOT_CMP_EQ__RS__RT_,
	HEX_INS_PD___CMP_GT__RS__RT_,
	HEX_INS_PD____NOT_CMP_GT__RS__RT_,
	HEX_INS_PD___CMP_GTU__RS__RT_,
	HEX_INS_PD____NOT_CMP_GTU__RS__RT_,
	HEX_INS_RD___CMP_EQ__RS___S8_,
	HEX_INS_RD____NOT_CMP_EQ__RS___S8_,
	HEX_INS_RD___CMP_EQ__RS__RT_,
	HEX_INS_RD____NOT_CMP_EQ__RS__RT_,
	HEX_INS_PD___FASTCORNER9__PS__PT_,
	HEX_INS_PD____NOT_FASTCORNER9__PS__PT_,
	HEX_INS_PD___ANY8__PS_,
	HEX_INS_PD___ALL8__PS_,
	HEX_INS_LOOP0___R7_2__RS_,
	HEX_INS_LOOP1___R7_2__RS_,
	HEX_INS_LOOP0___R7_2___U10_,
	HEX_INS_LOOP1___R7_2___U10_,
	HEX_INS_RD___ADD__PC___U6_,
	HEX_INS_P3___SP1LOOP0___R7_2__RS_,
	HEX_INS_P3___SP2LOOP0___R7_2__RS_,
	HEX_INS_P3___SP3LOOP0___R7_2__RS_,
	HEX_INS_P3___SP1LOOP0___R7_2___U10_,
	HEX_INS_P3___SP2LOOP0___R7_2___U10_,
	HEX_INS_P3___SP3LOOP0___R7_2___U10_,
	HEX_INS_PD___AND__PT__PS_,
	HEX_INS_PD___AND__PS__AND__PT__PU__,
	HEX_INS_PD___OR__PT__PS_,
	HEX_INS_PD___AND__PS__OR__PT__PU__,
	HEX_INS_PD___XOR__PS__PT_,
	HEX_INS_PD___OR__PS__AND__PT__PU__,
	HEX_INS_PD___AND__PT___NOT_PS_,
	HEX_INS_PD___OR__PS__OR__PT__PU__,
	HEX_INS_PD___AND__PS__AND__PT___NOT_PU__,
	HEX_INS_PD___AND__PS__OR__PT___NOT_PU__,
	HEX_INS_PD___NOT__PS_,
	HEX_INS_PD___OR__PS__AND__PT___NOT_PU__,
	HEX_INS_PD___OR__PT___NOT_PS_,
	HEX_INS_PD___OR__PS__OR__PT___NOT_PU__,
	HEX_INS_CD___RS,
	HEX_INS_CDD___RSS,
	HEX_INS_RDD___CSS,
	HEX_INS_RD___CS,
	HEX_INS_CALLR_RS,
	HEX_INS_IF__PU__CALLR_RS,
	HEX_INS_IF__NOT_PU_CALLR_RS,
	HEX_INS_HINTJR__RS_,
	HEX_INS_JUMPR_RS,
	HEX_INS_IF__PU__JUMPR_NT_RS,
	HEX_INS_IF__PU_NEW__JUMPR_NT_RS,
	HEX_INS_IF__PU__JUMPR_T_RS,
	HEX_INS_IF__PU_NEW__JUMPR_T_RS,
	HEX_INS_IF__NOT_PU_JUMPR_NT_RS,
	HEX_INS_IF__NOT_PU_NEW_JUMPR_NT_RS,
	HEX_INS_IF__NOT_PU_JUMPR_T_RS,
	HEX_INS_IF__NOT_PU_NEW_JUMPR_T_RS,
	HEX_INS_CALL__R22_2,
	HEX_INS_IF__PU__CALL__R15_2,
	HEX_INS_IF__NOT_PU_CALL__R15_2,
	HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_NT__R9_2,
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	HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2,
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	HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2,
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	HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_NT__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_T__R9_2,
	HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2,
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	HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2,
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	HEX_INS_IF__RS_GT_EQ___0__JUMP_NT__R13_2,
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	HEX_INS_IF__RS__EQ___0__JUMP_NT__R13_2,
	HEX_INS_IF__RS__EQ___0__JUMP_T__R13_2,
	HEX_INS_IF__RS_LT_EQ___0__JUMP_NT__R13_2,
	HEX_INS_IF__RS_LT_EQ___0__JUMP_T__R13_2,
	HEX_INS_MULT_RD____U6___JUMP__R9_2,
	HEX_INS_MULT_RD___RS___JUMP__R9_2,
	HEX_INS_RDD___MEMD__RS___RT_____U2_,
	HEX_INS_RDD___MEMD__GP____U16_3_,
	HEX_INS_RDD___MEMD__RS____S11_3_,
	HEX_INS_RDD___MEMD__RX_____S4_3_CIRC__MU__,
	HEX_INS_RDD___MEMD__RX____I_CIRC__MU__,
	HEX_INS_RDD___MEMD__RE____U6_,
	HEX_INS_RDD___MEMD__RX_____S4_3_,
	HEX_INS_RDD___MEMD__RT_____U2____U6_,
	HEX_INS_RDD___MEMD__RX____MU_,
	HEX_INS_RDD___MEMD__RX____MU_BREV_,
	HEX_INS_IF__PV__RDD___MEMD__RS___RT_____U2_,
	HEX_INS_IF__NOT_PV_RDD___MEMD__RS___RT_____U2_,
	HEX_INS_IF__PV_NEW__RDD___MEMD__RS___RT_____U2_,
	HEX_INS_IF__NOT_PV_NEW_RDD___MEMD__RS___RT_____U2_,
	HEX_INS_IF__PT__RDD___MEMD__RS____U6_3_,
	HEX_INS_IF__PT_NEW__RDD___MEMD__RS____U6_3_,
	HEX_INS_IF__NOT_PT_RDD___MEMD__RS____U6_3_,
	HEX_INS_IF__NOT_PT_NEW_RDD___MEMD__RS____U6_3_,
	HEX_INS_IF__PT__RDD___MEMD__RX_____S4_3_,
	HEX_INS_IF__NOT_PT_RDD___MEMD__RX_____S4_3_,
	HEX_INS_IF__PT_NEW__RDD___MEMD__RX_____S4_3_,
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	HEX_INS_IF__PT__RDD___MEMD___U6_,
	HEX_INS_IF__NOT_PT_RDD___MEMD___U6_,
	HEX_INS_IF__PT_NEW__RDD___MEMD___U6_,
	HEX_INS_IF__NOT_PT_NEW_RDD___MEMD___U6_,
	HEX_INS_RD___MEMB__RS___RT_____U2_,
	HEX_INS_RD___MEMB__GP____U16_0_,
	HEX_INS_RD___MEMB__RS____S11_0_,
	HEX_INS_RD___MEMB__RX_____S4_0_CIRC__MU__,
	HEX_INS_RD___MEMB__RX____I_CIRC__MU__,
	HEX_INS_RD___MEMB__RE____U6_,
	HEX_INS_RD___MEMB__RX_____S4_0_,
	HEX_INS_RD___MEMB__RT_____U2____U6_,
	HEX_INS_RD___MEMB__RX____MU_,
	HEX_INS_RD___MEMB__RX____MU_BREV_,
	HEX_INS_IF__PV__RD___MEMB__RS___RT_____U2_,
	HEX_INS_IF__NOT_PV_RD___MEMB__RS___RT_____U2_,
	HEX_INS_IF__PV_NEW__RD___MEMB__RS___RT_____U2_,
	HEX_INS_IF__NOT_PV_NEW_RD___MEMB__RS___RT_____U2_,
	HEX_INS_IF__PT__RD___MEMB__RS____U6_0_,
	HEX_INS_IF__PT_NEW__RD___MEMB__RS____U6_0_,
	HEX_INS_IF__NOT_PT_RD___MEMB__RS____U6_0_,
	HEX_INS_IF__NOT_PT_NEW_RD___MEMB__RS____U6_0_,
	HEX_INS_IF__PT__RD___MEMB__RX_____S4_0_,
	HEX_INS_IF__NOT_PT_RD___MEMB__RX_____S4_0_,
	HEX_INS_IF__PT_NEW__RD___MEMB__RX_____S4_0_,
	HEX_INS_IF__NOT_PT_NEW_RD___MEMB__RX_____S4_0_,
	HEX_INS_IF__PT__RD___MEMB___U6_,
	HEX_INS_IF__NOT_PT_RD___MEMB___U6_,
	HEX_INS_IF__PT_NEW__RD___MEMB___U6_,
	HEX_INS_IF__NOT_PT_NEW_RD___MEMB___U6_,
	HEX_INS_RYY___MEMB_FIFO__RS____S11_0_,
	HEX_INS_RYY___MEMB_FIFO__RX_____S4_0_CIRC__MU__,
	HEX_INS_RYY___MEMB_FIFO__RX____I_CIRC__MU__,
	HEX_INS_RYY___MEMB_FIFO__RE____U6_,
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	HEX_INS_DUPLEX_RD___RS___DEALLOCFRAME,
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	HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__JUMPR_NT_LR,
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	HEX_INS_DUPLEX_RD___RS___IF__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__JUMPR_NT_LR,
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	HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOCFRAME,
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	HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2____RT,
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	HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0____RT,
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	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMD__SP____S6_3____RTT,
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	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2____RT,
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	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__JUMPR_LR,
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	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__JUMPR_NT_LR,
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	HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOCFRAME,
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	HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___AND__RS___1____JUMPR_LR,
	HEX_INS_DUPLEX_RD___AND__RS___1____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___AND__RS___1____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___AND__RS___255____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___AND__RS___255____JUMPR_LR,
	HEX_INS_DUPLEX_RD___AND__RS___255____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___AND__RS___255____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___AND__RU___1____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RD___AND__RU___1____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___AND__RU___1____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RD___AND__RU___255____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RD___AND__RU___255____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___AND__RU___255____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTB__RS____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___SXTB__RS____JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTB__RS____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___SXTB__RS____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___SXTB__RU____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RD___SXTH__RS____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___SXTH__RS____JUMPR_LR,
	HEX_INS_DUPLEX_RD___SXTH__RS____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___SXTH__RS____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___SXTH__RU____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RD___ZXTH__RS____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOCFRAME,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RD___ZXTH__RS____JUMPR_LR,
	HEX_INS_DUPLEX_RD___ZXTH__RS____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RD___ZXTH__RS____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RD___ZXTH__RU____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0___U2____JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___1___U2____JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___2___U2____JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE___3___U2____JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____JUMPR_LR,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOCFRAME,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____JUMPR_LR,
	HEX_INS_DUPLEX_RE_____1___RD_____1,
	HEX_INS_DUPLEX_RE_____1___RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE_____1___RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE_____1___RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE_____1___RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE_____1___RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE_____1___RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE_____1___RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE_____1___RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE_____1___IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE_____1___IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE_____1___IF__P0__RD____0,
	HEX_INS_DUPLEX_RE_____1___IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE____U6___RD_____1,
	HEX_INS_DUPLEX_RE____U6___RD____U6,
	HEX_INS_DUPLEX_RE____U6___RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RE____U6___RD___ADD__RS___1_,
	HEX_INS_DUPLEX_RE____U6___RD___ADD__SP___U6_2_,
	HEX_INS_DUPLEX_RE____U6___RD___AND__RS___1_,
	HEX_INS_DUPLEX_RE____U6___RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE____U6___RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE____U6___RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE____U6___RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE____U6___RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE____U6___RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE____U6___RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE____U6___RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE____U6___RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE____U6___IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE____U6___IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE____U6___IF__P0__RD____0,
	HEX_INS_DUPLEX_RE____U6___IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE____U6___RD___RS,
	HEX_INS_DUPLEX_RE____U6___RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE____U6___RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE____U6___RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___RS___RD_____1,
	HEX_INS_DUPLEX_RE___RS___RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___RS___RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___RS___IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___RS___IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___RS___IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___RS___IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___RU___RD___RS,
	HEX_INS_DUPLEX_RE___RU___RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RE___RU___RD___ADD__RS___1_,
	HEX_INS_DUPLEX_RE___RU___RD___AND__RS___1_,
	HEX_INS_DUPLEX_RE___RU___RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___RU___RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___RU___RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___RU___RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___RU___RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___RU___RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___RU___RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___RU___RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE___RU___RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___RU___RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___RU___RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RD_____1,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RD_____1,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS___1_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___1_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD_____1,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS___1_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__SP___U6_2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___1_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___RS,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___AND__RS___1____RD_____1,
	HEX_INS_DUPLEX_RE___AND__RS___1____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___1____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___AND__RS___1____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___1____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___1____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___1____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___255____RD_____1,
	HEX_INS_DUPLEX_RE___AND__RS___255____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___AND__RS___255____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___AND__RS___255____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___255____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___255____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___AND__RS___255____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___AND__RS___1_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___AND__RU___1____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___AND__RU___255____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___MEMB__RS____U3_0____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___MEMB__RS____U3_0____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___MEMB__RU____U3_0____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___MEMH__RS____U3_1____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___MEMH__RS____U3_1____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMUB__RS____U4_0____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___MEMUB__RS____U4_0____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMUH__RS____U3_1____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___MEMUH__RS____U3_1____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___MEMUH__RU____U3_1____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___MEMUH__RU____U3_1____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMW__RS____U4_2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___MEMW__RS____U4_2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___MEMW__SP____U5_2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___MEMW__SP____U5_2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___SXTB__RS____RD_____1,
	HEX_INS_DUPLEX_RE___SXTB__RS____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___SXTB__RS____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___SXTB__RS____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___SXTB__RS____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___SXTB__RS____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___SXTB__RS____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___SXTB__RU____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___SXTH__RS____RD_____1,
	HEX_INS_DUPLEX_RE___SXTH__RS____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___SXTH__RS____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___SXTH__RS____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___SXTH__RS____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___SXTH__RS____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___SXTH__RS____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___SXTH__RS_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___SXTH__RU____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RD_____1,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RE___ZXTH__RS____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RE___ZXTH__RS____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ZXTH__RS____IF__P0__RD____0,
	HEX_INS_DUPLEX_RE___ZXTH__RS____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RE___ZXTH__RU____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RS____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RS____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_REE___COMBINE___0__RU____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_REE___COMBINE__RS___0____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_REE___COMBINE__RS___0____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_REE___COMBINE__RU___0____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_REE___MEMD__SP____U5_3____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RD_____1,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOCFRAME,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RX___ADD__RS__RX____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RX___ADD__RU__RX____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD_____1,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD____U6,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__RS____1_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__RS___1_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__SP___U6_2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___AND__RS___1_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___AND__RS___255_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___RS,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___SXTB__RS_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___SXTH__RS_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ZXTH__RS_,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOCFRAME,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RX___ADD__RX___S7____JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RD_____1,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOCFRAME,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__RD____0,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____JUMPR_LR,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_RX___ADD__RX__RS____MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_RX___ADD__RX__RU____P0___CMP_EQ__RS___U2_,
	HEX_INS_DUPLEX_RY___ADD__RU__RY____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RY___ADD__RU__RY____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RX___S7_,
	HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_RY___ADD__RY__RU____RX___ADD__RS__RX_,
	HEX_INS_DUPLEX_RY___ADD__RY__RU____RX___ADD__RX__RS_,
	HEX_INS_DUPLEX_DEALLOCFRAME___IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_DEALLOCFRAME___IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_DEALLOCFRAME___IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_DEALLOCFRAME___IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_DEALLOCFRAME___JUMPR_LR,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOCFRAME,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___JUMPR_LR,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_IF___NOT__P0__RE____0___IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOCFRAME,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___JUMPR_LR,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF___NOT__P0_NEW__RD____0,
	HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF__P0__RD____0,
	HEX_INS_DUPLEX_IF__P0__RD____0___ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOCFRAME,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF__P0__RD____0___JUMPR_LR,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0____RT,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMD__SP____S6_3____RTT,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMH__RS____U3_1____RT,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2_____0,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2_____1,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2____RT,
	HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__SP____U5_2____RT,
	HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMB__RS____U3_0_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMH__RS____U3_1_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMUB__RS____U4_0_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMUH__RS____U3_1_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMW__RS____U4_2_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMW__SP____U5_2_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___0___U2_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___0__RS_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___1___U2_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___2___U2_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___3___U2_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE__RS___0_,
	HEX_INS_DUPLEX_IF__P0__RE____0___RDD___MEMD__SP____U5_3_,
	HEX_INS_DUPLEX_IF__P0__RE____0___IF___NOT__P0__RD____0,
	HEX_INS_DUPLEX_IF__P0__RE____0___IF__P0__RD____0,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___ALLOCFRAME___U5_3_,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOCFRAME,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__JUMPR_LR,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__JUMPR_NT_LR,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___JUMPR_LR,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0_____0,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0_____1,
	HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0____RT,
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};

#endif
