2019-12-08 15:31:14 +01:00
|
|
|
NAME=basic integer arith
|
|
|
|
|
FILE=malloc://0x200
|
2020-04-05 20:56:06 +08:00
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2020-04-05 20:56:06 +08:00
|
|
|
wx 22a0060c7330828030729022c2012b3242a0080c354065c04065d0
|
|
|
|
|
aecu 0x0000001b
|
|
|
|
|
ar~a2,a3,a4,a5,a6,a7,a8
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
a2 = 0x00000007
|
|
|
|
|
a3 = 0x00000009
|
|
|
|
|
a4 = 0x00000008
|
|
|
|
|
a5 = 0x00000003
|
|
|
|
|
a6 = 0xfffffffe
|
|
|
|
|
a7 = 0x00000013
|
|
|
|
|
a8 = 0x0000000d
|
|
|
|
|
EOF
|
|
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=load/store imm
|
|
|
|
|
FILE=malloc://0x200
|
2020-04-05 20:56:06 +08:00
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2020-04-05 20:56:06 +08:00
|
|
|
wx 22a05032a0bb42afff52a0cc7cf6326200425202524208722200829202921202a20208
|
|
|
|
|
aecu 0x00000023
|
|
|
|
|
ar~a2,a3,a4,a5,a6,a7,a8,a9,a10
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
a2 = 0x00000050
|
|
|
|
|
a3 = 0x000000bb
|
|
|
|
|
a4 = 0xffffffff
|
|
|
|
|
a5 = 0x000000cc
|
|
|
|
|
a6 = 0xffffffff
|
|
|
|
|
a7 = 0x000000bb
|
|
|
|
|
a8 = 0xffffffff
|
|
|
|
|
a9 = 0x0000ffff
|
|
|
|
|
a10 = 0x000000cc
|
|
|
|
|
EOF
|
|
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=load relative
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
2026-02-19 23:13:18 +08:00
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
|
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx ddccbbaa @ 0
|
|
|
|
|
s 0x14
|
|
|
|
|
wx 21fbff31faff41f9ff51f8fff8ff
|
|
|
|
|
aei
|
|
|
|
|
aeip
|
|
|
|
|
4aes
|
|
|
|
|
ar~a2,a3,a4,a5
|
|
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
a2 = 0xaabbccdd
|
|
|
|
|
a3 = 0xaabbccdd
|
|
|
|
|
a4 = 0xaabbccdd
|
|
|
|
|
a5 = 0xaabbccdd
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=call0 ABI
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx c5000022a020c00200000000000000008000000000000000000000000000000002a030c00000
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
|
|
|
|
ar~^a0
|
2019-12-08 15:31:14 +01:00
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
ar~a2
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
|
|
|
|
ar~^a0
|
2019-12-08 15:31:14 +01:00
|
|
|
aes
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
|
|
|
|
ar~^a0
|
2019-12-08 15:31:14 +01:00
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
pc = 0x00000010
|
|
|
|
|
a0 = 0x00000003
|
|
|
|
|
a2 = 0x00000020
|
|
|
|
|
pc = 0x00000020
|
|
|
|
|
a0 = 0x00000009
|
|
|
|
|
pc = 0x00000030
|
|
|
|
|
a0 = 0x00000026
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=branch compare imm
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx 22a002e6320526320200000086fdff
|
|
|
|
|
aes
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
pc = 0x0000000c
|
|
|
|
|
pc = 0x00000006
|
|
|
|
|
pc = 0x00000009
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=branch compare single
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx 22a002d6920000000000000000000000060000
|
|
|
|
|
aes
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
pc = 0x00000010
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=branch compare
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx 22a00232a00327130627a30300000000060000
|
|
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
pc = 0x00000010
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=branch check mask
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx 00000fff34120fff000000000000000021fcff31fcff2743060000000000000006ffff
|
|
|
|
|
s 0x10
|
|
|
|
|
aeip
|
|
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
pc = 0x00000020
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=branch check bit imm
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
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2019-12-08 15:31:14 +01:00
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wx 0000004000000000000000000000000021fcffe7f2090000000000000000000006ffff
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s 0x10
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aeip
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aes
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aes
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librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
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ar~^pc
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2019-12-08 15:31:14 +01:00
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EOF
|
2020-04-05 20:56:06 +08:00
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EXPECT=<<EOF
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|
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pc = 0x00000020
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EOF
|
2019-12-08 15:31:14 +01:00
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RUN
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NAME=branch check bit
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FILE=malloc://0x200
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CMDS=<<EOF
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e asm.arch=xtensa
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e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
wx 0000000400000000000000000000000021fcff32a01a37d2060000000000000006ffff
|
|
|
|
|
s 0x10
|
|
|
|
|
aeip
|
|
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
aes
|
librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities.
- **Instruction Set Additions**:
- **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8
- **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa
- **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez
- **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src
- **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex
- **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw
- **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s
- **Testing and Patches**:
- Implement asm tests for all
- **Miscellaneous Improvements**:
- Update Capstone and fix ARM architecture support for building.
2024-12-26 01:55:38 +08:00
|
|
|
ar~^pc
|
2019-12-08 15:31:14 +01:00
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
pc = 0x00000020
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=extract unsigned imm
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2019-12-08 15:31:14 +01:00
|
|
|
e asm.esil=1
|
|
|
|
|
wx ddccbbaa00000000000000000000000021fcff2038f4
|
|
|
|
|
s 0x10
|
|
|
|
|
aeip
|
|
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
ar~a3
|
|
|
|
|
EOF
|
2020-04-05 20:56:06 +08:00
|
|
|
EXPECT=<<EOF
|
|
|
|
|
a3 = 0x0000bbcc
|
|
|
|
|
EOF
|
2019-12-08 15:31:14 +01:00
|
|
|
RUN
|
2020-09-03 06:33:23 +03:00
|
|
|
|
|
|
|
|
NAME=movi.n: extract unsigned imm
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2020-09-03 06:33:23 +03:00
|
|
|
e asm.esil=1
|
|
|
|
|
wx 4ce87cdb
|
|
|
|
|
s 0x0
|
|
|
|
|
aeip
|
|
|
|
|
aes
|
|
|
|
|
ar~a8
|
|
|
|
|
EOF
|
|
|
|
|
EXPECT=<<EOF
|
|
|
|
|
a8 = 0x0000004e
|
|
|
|
|
EOF
|
|
|
|
|
RUN
|
|
|
|
|
|
|
|
|
|
NAME=movi.n: extract signed imm
|
|
|
|
|
FILE=malloc://0x200
|
|
|
|
|
CMDS=<<EOF
|
|
|
|
|
e asm.arch=xtensa
|
|
|
|
|
e asm.bits=32
|
2026-02-19 23:13:18 +08:00
|
|
|
e cfg.bigendian=false
|
2020-09-03 06:33:23 +03:00
|
|
|
e asm.esil=1
|
|
|
|
|
wx 4ce87cdb
|
|
|
|
|
s 0x0
|
|
|
|
|
aeip
|
|
|
|
|
aes
|
|
|
|
|
aes
|
|
|
|
|
ar~a11
|
|
|
|
|
EOF
|
|
|
|
|
EXPECT=<<EOF
|
|
|
|
|
a11 = 0xfffffffd
|
|
|
|
|
EOF
|
|
|
|
|
RUN
|