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librz/arch/tms320/c5x: classify BSAR as a right shift in analysis
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Browse source 
BSAR (Barrel Shift ACC Right) was grouped with the left-shift ops and
reported RZ_ANALYSIS_OP_TYPE_SHL. It shifts the accumulator right (1..16
bits, sign-extended under SXM), so it belongs with the SHR group next to
RORB/SFRB. The decode (shift code + 1) was already correct and continues
to match the reference disassembler bit-for-bit.
This commit is contained in:
Anton Kochkov 2026-06-30 17:06:38 +00:00 • committed by NOT XVilka
parent ad462e7ede
commit 38c3bed6c9
2 changed files with 3 additions and 1 deletions
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2
librz/arch/isa/tms320/c5x/c5x.c
View file

@ -153,10 +153,10 @@ RZ_IPI ut32 c5x_op_type(ut16 id) {
return RZ_ANALYSIS_OP_TYPE_MOV;
case C5X_INS_ROLB:
case C5X_INS_SFLB:
case C5X_INS_BSAR:
return RZ_ANALYSIS_OP_TYPE_SHL;
case C5X_INS_RORB:
case C5X_INS_SFRB:
case C5X_INS_BSAR:
return RZ_ANALYSIS_OP_TYPE_SHR;
case C5X_INS_ZAP:
case C5X_INS_ZPR:

2
test/db/asm/tms320_c5x_16
View file

@ -92,6 +92,8 @@ d "calld 0x50, *" 7e800050 0x0 (seq (set sp (- (var sp) (bv 16 0x1))) (storew 0
d "rptz #0x7" bec50007 0x0 nop
d "rptb 0x40" bec60040 0x0 nop
d "bsar #0x4" bfe3
d "bsar #0x1" bfe0
d "bsar #0x10" bfef
d "lst #0x0, 0x9" 0e09
d "sst #0x1, 0x10" 8f10
d "tblr 0x9" a609 0x0 (storew 0 (* (cast 24 false (| (<< (& (var dp) (bv 16 0x1ff)) (bv 16 0x7) false) (bv 16 0x9))) (bv 24 0x2)) (loadw 0 16 (* (cast 24 false (cast 16 false (var acc))) (bv 24 0x2))))