mirror of
https://github.com/rizinorg/rizin
synced 2026-08-22 20:26:16 -04:00
librz/bin: add corefile support for Linux MIPS 32/64 (#5355)
This commit is contained in:
Giovanni
GitHub
parent
bc30c934fc
commit
46009de0fa
5 changed files with 305 additions and 124 deletions
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@ -931,42 +931,80 @@ static char *mips_get_reg_profile(RzAnalysis *analysis) {
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"=A3 a3\n"
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"=R0 v0\n"
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"=R1 v1\n"
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"gpr zero .32 ? 0\n"
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"gpr at .32 4 0\n"
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"gpr v0 .32 8 0\n"
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"gpr v1 .32 12 0\n"
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"gpr a0 .32 16 0\n"
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"gpr a1 .32 20 0\n"
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"gpr a2 .32 24 0\n"
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"gpr a3 .32 28 0\n"
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"gpr t0 .32 32 0\n"
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"gpr t1 .32 36 0\n"
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"gpr t2 .32 40 0\n"
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"gpr t3 .32 44 0\n"
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"gpr t4 .32 48 0\n"
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"gpr t5 .32 52 0\n"
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"gpr t6 .32 56 0\n"
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"gpr t7 .32 60 0\n"
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"gpr s0 .32 64 0\n"
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"gpr s1 .32 68 0\n"
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"gpr s2 .32 72 0\n"
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"gpr s3 .32 76 0\n"
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"gpr s4 .32 80 0\n"
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"gpr s5 .32 84 0\n"
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"gpr s6 .32 88 0\n"
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"gpr s7 .32 92 0\n"
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"gpr t8 .32 96 0\n"
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"gpr t9 .32 100 0\n"
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"gpr k0 .32 104 0\n"
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"gpr k1 .32 108 0\n"
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"gpr gp .32 112 0\n"
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"gpr sp .32 116 0\n"
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"gpr fp .32 120 0\n"
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"gpr ra .32 124 0\n"
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"gpr pc .32 128 0\n"
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"gpr hi .32 132 0\n"
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"gpr lo .32 136 0\n"
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"gpr t .32 140 0\n";
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"gpr zero .32 ? 0\n"
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"gpr at .32 4 0\n"
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"gpr v0 .32 8 0\n"
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"gpr v1 .32 12 0\n"
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"gpr a0 .32 16 0\n"
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"gpr a1 .32 20 0\n"
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"gpr a2 .32 24 0\n"
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"gpr a3 .32 28 0\n"
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"gpr t0 .32 32 0\n"
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"gpr t1 .32 36 0\n"
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"gpr t2 .32 40 0\n"
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"gpr t3 .32 44 0\n"
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"gpr t4 .32 48 0\n"
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"gpr t5 .32 52 0\n"
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"gpr t6 .32 56 0\n"
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"gpr t7 .32 60 0\n"
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"gpr s0 .32 64 0\n"
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"gpr s1 .32 68 0\n"
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"gpr s2 .32 72 0\n"
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"gpr s3 .32 76 0\n"
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"gpr s4 .32 80 0\n"
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"gpr s5 .32 84 0\n"
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"gpr s6 .32 88 0\n"
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"gpr s7 .32 92 0\n"
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"gpr t8 .32 96 0\n"
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"gpr t9 .32 100 0\n"
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"gpr k0 .32 104 0\n"
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"gpr k1 .32 108 0\n"
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"gpr gp .32 112 0\n"
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"gpr sp .32 116 0\n"
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"gpr fp .32 120 0\n"
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"gpr ra .32 124 0\n"
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"gpr lo .32 128 0\n"
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"gpr hi .32 132 0\n"
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"gpr pc .32 136 0\n"
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"gpr badvaddr .32 140 0\n"
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"gpr status .32 144 0\n"
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"gpr cause .32 148 0\n"
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"fpu f0 .32 152 0\n"
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"fpu f1 .32 156 0\n"
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"fpu f2 .32 160 0\n"
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"fpu f3 .32 164 0\n"
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"fpu f4 .32 168 0\n"
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"fpu f5 .32 172 0\n"
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"fpu f6 .32 176 0\n"
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"fpu f7 .32 180 0\n"
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"fpu f8 .32 184 0\n"
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"fpu f9 .32 188 0\n"
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"fpu f10 .32 192 0\n"
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"fpu f11 .32 196 0\n"
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"fpu f12 .32 200 0\n"
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"fpu f13 .32 204 0\n"
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"fpu f14 .32 208 0\n"
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"fpu f15 .32 212 0\n"
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"fpu f16 .32 216 0\n"
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"fpu f17 .32 220 0\n"
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"fpu f18 .32 224 0\n"
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"fpu f19 .32 228 0\n"
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"fpu f20 .32 232 0\n"
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"fpu f21 .32 236 0\n"
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"fpu f22 .32 240 0\n"
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"fpu f23 .32 244 0\n"
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"fpu f24 .32 248 0\n"
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"fpu f25 .32 252 0\n"
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"fpu f26 .32 256 0\n"
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"fpu f27 .32 260 0\n"
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"fpu f28 .32 264 0\n"
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"fpu f29 .32 268 0\n"
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"fpu f30 .32 272 0\n"
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"fpu f31 .32 276 0\n"
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"fpu fcsr .32 280 0\n"
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"fpu fir .32 284 0\n"
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"fpu restart .32 288 0\n"
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"gpr t .32 292 0\n";
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break;
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case 64:
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p =
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@ -980,42 +1018,80 @@ static char *mips_get_reg_profile(RzAnalysis *analysis) {
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"=SN v0\n"
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"=R0 v0\n"
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"=R1 v1\n"
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"gpr zero .64 ? 0\n"
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"gpr at .64 8 0\n"
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"gpr v0 .64 16 0\n"
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"gpr v1 .64 24 0\n"
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"gpr a0 .64 32 0\n"
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"gpr a1 .64 40 0\n"
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"gpr a2 .64 48 0\n"
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"gpr a3 .64 56 0\n"
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"gpr t0 .64 64 0\n"
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"gpr t1 .64 72 0\n"
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"gpr t2 .64 80 0\n"
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"gpr t3 .64 88 0\n"
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"gpr t4 .64 96 0\n"
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"gpr t5 .64 104 0\n"
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"gpr t6 .64 112 0\n"
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"gpr t7 .64 120 0\n"
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"gpr s0 .64 128 0\n"
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"gpr s1 .64 136 0\n"
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"gpr s2 .64 144 0\n"
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"gpr s3 .64 152 0\n"
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"gpr s4 .64 160 0\n"
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"gpr s5 .64 168 0\n"
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"gpr s6 .64 176 0\n"
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"gpr s7 .64 184 0\n"
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"gpr t8 .64 192 0\n"
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"gpr t9 .64 200 0\n"
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"gpr k0 .64 208 0\n"
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"gpr k1 .64 216 0\n"
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"gpr gp .64 224 0\n"
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"gpr sp .64 232 0\n"
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"gpr fp .64 240 0\n"
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"gpr ra .64 248 0\n"
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"gpr pc .64 256 0\n"
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"gpr hi .64 264 0\n"
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"gpr lo .64 272 0\n"
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"gpr t .64 280 0\n";
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"gpr zero .64 ? 0\n"
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"gpr at .64 8 0\n"
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"gpr v0 .64 16 0\n"
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"gpr v1 .64 24 0\n"
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"gpr a0 .64 32 0\n"
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"gpr a1 .64 40 0\n"
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"gpr a2 .64 48 0\n"
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"gpr a3 .64 56 0\n"
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"gpr t0 .64 64 0\n"
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"gpr t1 .64 72 0\n"
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"gpr t2 .64 80 0\n"
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"gpr t3 .64 88 0\n"
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"gpr t4 .64 96 0\n"
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"gpr t5 .64 104 0\n"
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"gpr t6 .64 112 0\n"
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"gpr t7 .64 120 0\n"
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"gpr s0 .64 128 0\n"
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"gpr s1 .64 136 0\n"
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"gpr s2 .64 144 0\n"
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"gpr s3 .64 152 0\n"
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"gpr s4 .64 160 0\n"
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"gpr s5 .64 168 0\n"
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"gpr s6 .64 176 0\n"
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"gpr s7 .64 184 0\n"
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"gpr t8 .64 192 0\n"
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"gpr t9 .64 200 0\n"
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"gpr k0 .64 208 0\n"
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"gpr k1 .64 216 0\n"
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"gpr gp .64 224 0\n"
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"gpr sp .64 232 0\n"
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"gpr fp .64 240 0\n"
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"gpr ra .64 248 0\n"
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"gpr lo .64 256 0\n"
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"gpr hi .64 264 0\n"
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"gpr pc .64 272 0\n"
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"gpr badvaddr .64 280 0\n"
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"gpr status .64 288 0\n"
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"gpr cause .64 296 0\n"
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"fpu f0 .64 304 0\n"
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"fpu f1 .64 312 0\n"
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"fpu f2 .64 320 0\n"
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"fpu f3 .64 328 0\n"
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"fpu f4 .64 336 0\n"
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"fpu f5 .64 344 0\n"
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"fpu f6 .64 352 0\n"
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"fpu f7 .64 360 0\n"
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"fpu f8 .64 368 0\n"
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"fpu f9 .64 376 0\n"
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"fpu f10 .64 384 0\n"
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"fpu f11 .64 392 0\n"
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"fpu f12 .64 400 0\n"
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"fpu f13 .64 408 0\n"
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"fpu f14 .64 416 0\n"
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"fpu f15 .64 424 0\n"
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"fpu f16 .64 432 0\n"
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"fpu f17 .64 440 0\n"
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"fpu f18 .64 448 0\n"
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"fpu f19 .64 456 0\n"
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"fpu f20 .64 464 0\n"
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"fpu f21 .64 472 0\n"
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"fpu f22 .64 480 0\n"
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"fpu f23 .64 488 0\n"
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"fpu f24 .64 496 0\n"
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"fpu f25 .64 504 0\n"
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"fpu f26 .64 512 0\n"
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"fpu f27 .64 520 0\n"
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"fpu f28 .64 528 0\n"
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"fpu f29 .64 536 0\n"
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"fpu f30 .64 544 0\n"
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"fpu f31 .64 552 0\n"
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"fpu fcsr .32 560 0\n" // 32 bit long
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"fpu fir .32 564 0\n" // 32 bit long
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"fpu restart .64 568 0\n"
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"gpr t .64 576 0\n";
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break;
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}
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return rz_str_dup(p);
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@ -8,6 +8,8 @@
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#define ROUND_UP_4(x) ((x) + (4 - 1)) / 4 * 4
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#define FP_LAYOUT 0x10
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#define X86 0
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#define X86_64 1
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#define ARM 2
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@ -21,9 +23,14 @@
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// They are only for registers and store no other information.
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#define OPENBSD_SPARC_V9 7
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#define OPENBSD_SPARC_V9_FP (FP_LAYOUT | OPENBSD_SPARC_V9)
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// MIPS related constants.
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// The size of the pr status depends on the ABI
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#define MIPS_32 8
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#define MIPS_64 9
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#define MIPS_FP32 (FP_LAYOUT | MIPS_32)
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#define MIPS_FP64 (FP_LAYOUT | MIPS_64)
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// Floating point register layout.
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#define FP_LAYOUT 0x10
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#define ARCH_LEN (FP_LAYOUT | 0xf)
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#define ARCH_LEN (FP_LAYOUT | 0xf)
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// See elf.c::elfcore_grok_solaris_note_impl() of binutil's bfd
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// https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elf.c;h=6ef603010918f14eda69f0d0dc1637b4d51e8157;hb=HEAD#l11777
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@ -93,6 +100,16 @@
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#define SPARC32_PR_STATUS_REG_OFFSET_SP (4 * 14)
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#define SPARC64_PR_STATUS_REG_OFFSET_SP (8 * 14)
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// MIPS number of registers.
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#define MIPS_N_GPR_REGS 45
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#define MIPS_N_FP_REGS 33
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#define MIPS32_REGS_SIZE (4 * MIPS_N_GPR_REGS) // int32
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#define MIPS64_REGS_SIZE (8 * MIPS_N_GPR_REGS) // int64
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#define MIPS_FP32_REGS_SIZE (4 * MIPS_N_FP_REGS) // float32
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#define MIPS_FP64_REGS_SIZE (8 * MIPS_N_FP_REGS) // float64
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#define MIPS_GPR32_STATUS_OFFSET (96)
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#define MIPS_GPR64_STATUS_OFFSET (112)
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static RzBinElfPrStatusLayout prstatus_layouts[ARCH_LEN] = {
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[X86] = { 160, 0x48, 32, 0x3c },
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[X86_64] = { 216, 0x70, 64, 0x98 },
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@ -104,9 +121,15 @@ static RzBinElfPrStatusLayout prstatus_layouts[ARCH_LEN] = {
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[SPARC_V9] = { SPARC64_REGS_SIZE, SPARC64_PR_STATUS_REG_OFFSET, 64, SPARC64_PR_STATUS_REG_OFFSET_SP },
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[OPENBSD_SPARC_V9] = { SPARC64_REGS_SIZE, SPARC64_OPENBSD_REG_OFFSET, 64, SPARC64_PR_STATUS_REG_OFFSET_SP },
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[MIPS_32] = { MIPS32_REGS_SIZE, MIPS_GPR32_STATUS_OFFSET, 0, 0 },
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[MIPS_64] = { MIPS64_REGS_SIZE, MIPS_GPR64_STATUS_OFFSET, 0, 0 },
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[SPARC32_FP] = { SPARC32_FPREGS_SIZE, SPARC32_FPREG_OFFSET, 0, 0 },
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[SPARC64_FP] = { SPARC64_FPREGS_SIZE, SPARC32_FPREG_OFFSET, 0, 0 },
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[OPENBSD_SPARC_V9_FP] = { SPARC64_OPENBSD_FPREGS_SIZE, SPARC64_OPENBSD_FPREG_OFFSET, 0, 0 },
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[MIPS_FP32] = { MIPS_FP32_REGS_SIZE, 4, 0, 0 },
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[MIPS_FP64] = { MIPS_FP64_REGS_SIZE, 8, 0, 0 },
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};
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static bool parse_register_note(ELFOBJ *bin, RzVector /*<RzBinElfNote>*/ *notes, Elf_(Nhdr) * note_segment_header, ut64 offset, size_t n_type) {
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@ -310,6 +333,14 @@ static void note_segment_free(void *e, RZ_UNUSED void *user) {
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rz_vector_fini(ptr);
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}
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static const size_t elf_get_prstatus_layout_mips(const ELFOBJ *bin, bool is_fp) {
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size_t fp = is_fp ? FP_LAYOUT : 0;
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if (bin->ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
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return fp | MIPS_64;
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}
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return fp | MIPS_32;
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}
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RZ_BORROW RzBinElfPrStatusLayout *Elf_(rz_bin_elf_get_prstatus_layout)(RZ_NONNULL ELFOBJ *bin) {
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rz_return_val_if_fail(bin, NULL);
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@ -328,6 +359,12 @@ RZ_BORROW RzBinElfPrStatusLayout *Elf_(rz_bin_elf_get_prstatus_layout)(RZ_NONNUL
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return prstatus_layouts + SPARC_V8PLUS;
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case EM_SPARCV9:
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return prstatus_layouts + SPARC_V9;
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case EM_MIPS:
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/* fall-thru */
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case EM_MIPS_RS3_LE:
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/* fall-thru */
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case EM_MIPS_X:
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return prstatus_layouts + elf_get_prstatus_layout_mips(bin, false);
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}
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return NULL;
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@ -352,6 +389,18 @@ RZ_BORROW RzBinElfPrStatusLayout *Elf_(rz_bin_elf_get_regset_layout)(RZ_NONNULL
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switch (bin->ehdr.e_machine) {
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default:
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return NULL;
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case EM_MIPS:
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/* fall-thru */
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case EM_MIPS_RS3_LE:
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/* fall-thru */
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case EM_MIPS_X:
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if (n_type == NT_FPREGSET) {
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off = elf_get_prstatus_layout_mips(bin, true);
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} else {
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rz_warn_if_reached();
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return NULL;
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}
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break;
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case EM_SPARC:
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if (n_type == NT_FPREGSET) {
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off = FP_LAYOUT | SPARC;
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@ -101,9 +101,12 @@ gp = 0x00000000
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sp = 0x00000000
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fp = 0x00000000
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ra = 0x00000000
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pc = 0x00000000
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hi = 0x00000000
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lo = 0x00000000
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hi = 0x00000000
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pc = 0x00000000
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badvaddr = 0x00000000
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status = 0x00000000
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cause = 0x00000000
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t = 0x00000000
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EOF
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RUN
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@ -145,9 +148,12 @@ gp = 0x0000000000000000
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sp = 0x0000000000000000
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fp = 0x0000000000000000
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ra = 0x0000000000000000
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pc = 0x0000000000000000
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hi = 0x0000000000000000
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lo = 0x0000000000000000
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hi = 0x0000000000000000
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pc = 0x0000000000000000
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badvaddr = 0x0000000000000000
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status = 0x0000000000000000
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cause = 0x0000000000000000
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t = 0x0000000000000000
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EOF
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RUN
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@ -821,52 +821,6 @@ EXPECT=<<EOF
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EOF
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RUN
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NAME=mips regs
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FILE==
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CMDS=<<EOF
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e asm.arch=mips
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ar
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EOF
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EXPECT=<<EOF
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zero = 0x00000000
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at = 0x00000000
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v0 = 0x00000000
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v1 = 0x00000000
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a0 = 0x00000000
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a1 = 0x00000000
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a2 = 0x00000000
|
||||
a3 = 0x00000000
|
||||
t0 = 0x00000000
|
||||
t1 = 0x00000000
|
||||
t2 = 0x00000000
|
||||
t3 = 0x00000000
|
||||
t4 = 0x00000000
|
||||
t5 = 0x00000000
|
||||
t6 = 0x00000000
|
||||
t7 = 0x00000000
|
||||
s0 = 0x00000000
|
||||
s1 = 0x00000000
|
||||
s2 = 0x00000000
|
||||
s3 = 0x00000000
|
||||
s4 = 0x00000000
|
||||
s5 = 0x00000000
|
||||
s6 = 0x00000000
|
||||
s7 = 0x00000000
|
||||
t8 = 0x00000000
|
||||
t9 = 0x00000000
|
||||
k0 = 0x00000000
|
||||
k1 = 0x00000000
|
||||
gp = 0x00000000
|
||||
sp = 0x00000000
|
||||
fp = 0x00000000
|
||||
ra = 0x00000000
|
||||
pc = 0x00000000
|
||||
hi = 0x00000000
|
||||
lo = 0x00000000
|
||||
t = 0x00000000
|
||||
EOF
|
||||
RUN
|
||||
|
||||
NAME=mips sp/bp tracking
|
||||
FILE=bins/elf/vars-mips-bp
|
||||
ARGS=-e bin.dbginfo=0
|
||||
|
|
|
|||
|
|
@ -505,3 +505,99 @@ fsr = 0x0000000000000000
|
|||
EOF
|
||||
EXPECT_ERR=
|
||||
RUN
|
||||
|
||||
NAME=core regs linux mipsel
|
||||
FILE=bins/elf/core/core-linux-mips32el-bin-ls
|
||||
CMDS=<<EOF
|
||||
ar
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
zero = 0x00000000
|
||||
at = 0x824dd370
|
||||
v0 = 0xffffffff
|
||||
v1 = 0xffffffff
|
||||
a0 = 0x555922d0
|
||||
a1 = 0x55592350
|
||||
a2 = 0xffffffff
|
||||
a3 = 0x00000000
|
||||
t0 = 0x00000000
|
||||
t1 = 0x8214ad88
|
||||
t2 = 0x8242de00
|
||||
t3 = 0xffffffff
|
||||
t4 = 0x00000000
|
||||
t5 = 0x77f68e20
|
||||
t6 = 0x00000000
|
||||
t7 = 0x77f68e20
|
||||
s0 = 0x555922d0
|
||||
s1 = 0x55592190
|
||||
s2 = 0x00000000
|
||||
s3 = 0x7fffcbac
|
||||
s4 = 0x7fffcbb0
|
||||
s5 = 0xffffffff
|
||||
s6 = 0x77ffbf04
|
||||
s7 = 0x00000000
|
||||
t8 = 0x00000000
|
||||
t9 = 0x77e33978
|
||||
k0 = 0x55592190
|
||||
k1 = 0x00000000
|
||||
gp = 0x77fb8050
|
||||
sp = 0x7fffcb90
|
||||
fp = 0x00000000
|
||||
ra = 0x77f7ef54
|
||||
lo = 0x0000000c
|
||||
hi = 0x00000008
|
||||
pc = 0x77e33978
|
||||
badvaddr = 0x77dff180
|
||||
status = 0x0000a413
|
||||
cause = 0x10800024
|
||||
t = 0x00000000
|
||||
EOF
|
||||
RUN
|
||||
|
||||
NAME=core regs linux mips64el
|
||||
FILE=bins/elf/core/core-linux-mips64le-bin-ls
|
||||
CMDS=<<EOF
|
||||
ar
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
zero = 0x0000000000000000
|
||||
at = 0xffffffff82588dac
|
||||
v0 = 0xffffffffffffffff
|
||||
v1 = 0xffffffffffffffff
|
||||
a0 = 0x000000aaaaae2480
|
||||
a1 = 0xffffffffffffffff
|
||||
a2 = 0x0000000000000400
|
||||
a3 = 0x0000000000000000
|
||||
t0 = 0xfefefefefefefeff
|
||||
t1 = 0x0000000000000001
|
||||
t2 = 0x7373737373737373
|
||||
t3 = 0xffffffffffffffff
|
||||
t4 = 0x0000000000000000
|
||||
t5 = 0xffffffff84080018
|
||||
t6 = 0xffffffff824d85f0
|
||||
t7 = 0x0000000074786509
|
||||
s0 = 0x000000aaaaae2480
|
||||
s1 = 0x000000aaaaae22a0
|
||||
s2 = 0x0000000000000000
|
||||
s3 = 0x000000ffffffca10
|
||||
s4 = 0x000000ffffffca08
|
||||
s5 = 0xffffffffffffffff
|
||||
s6 = 0x000000fff7ffae68
|
||||
s7 = 0x0000000000000000
|
||||
t8 = 0x0000000000000012
|
||||
t9 = 0x000000fff7e1d010
|
||||
k0 = 0x000000aaaaae22a0
|
||||
k1 = 0x0000000000000000
|
||||
gp = 0x000000fff7fb8060
|
||||
sp = 0x000000ffffffca00
|
||||
fp = 0x0000000000000000
|
||||
ra = 0x000000fff7f80938
|
||||
lo = 0x0000000000000007
|
||||
hi = 0x0000000000000000
|
||||
pc = 0x000000fff7e1d010
|
||||
badvaddr = 0x000000fff7f55c28
|
||||
status = 0x000000000000a4f3
|
||||
cause = 0x0000000010800024
|
||||
t = 0x0000000000000000
|
||||
EOF
|
||||
RUN
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue