diff --git a/librz/arch/isa/xtensa/xtensa.h b/librz/arch/isa/xtensa/xtensa.h index 5d4e399e9c..1f1e00e7fc 100644 --- a/librz/arch/isa/xtensa/xtensa.h +++ b/librz/arch/isa/xtensa/xtensa.h @@ -8,6 +8,14 @@ #include "asm_private.h" #include "analysis_private.h" +#if CS_API_MAJOR >= 6 && CS_VERSION_PRE_RELEASE < CS_VERSION_ALPHA11 +// After Alpha10 the CS_MODE_XTENSA_ESP32S3 mode was added and some +// instructions no longer decode without it. +// For <= Alpha10 the instructions also decode with CS_MODE_XTENSA_ESP32S2. +// Hence this redefinition. +#define CS_MODE_XTENSA_ESP32S3 CS_MODE_XTENSA_ESP32S2 +#endif + typedef struct { const char *cpu; cs_mode mode; @@ -16,6 +24,7 @@ typedef struct { static const XtensaCPUMode xtensa_cpu_modes[] = { { .cpu = "esp32", .mode = CS_MODE_XTENSA_ESP32 }, { .cpu = "esp32s2", .mode = CS_MODE_XTENSA_ESP32S2 }, + { .cpu = "esp32s3", .mode = CS_MODE_XTENSA_ESP32S3 }, { .cpu = "esp8266", .mode = CS_MODE_XTENSA_ESP8266 }, }; diff --git a/librz/arch/p/analysis/analysis_alpha_cs.c b/librz/arch/p/analysis/analysis_alpha_cs.c index b479385d45..7f4ec072f1 100644 --- a/librz/arch/p/analysis/analysis_alpha_cs.c +++ b/librz/arch/p/analysis/analysis_alpha_cs.c @@ -13,6 +13,31 @@ #define RZ_ALPHA_INS(name) ALPHA_INS_##name +// Stupid me forgot to request that all enums must be upper case +// in the initial Capstone Alpha PR - Yes, I know. +// This can be removed once Capstone v5 support is dropped. +#if (CS_API_MAJOR >= 6) && (CS_VERSION_PRE_RELEASE >= CS_VERSION_ALPHA10) +#define ALPHA_INS_CMPTEQsSU ALPHA_INS_CMPTEQSSU +#define ALPHA_INS_CMPTLEsSU ALPHA_INS_CMPTLESSU +#define ALPHA_INS_CMPTLTsSU ALPHA_INS_CMPTLTSSU +#define ALPHA_INS_CMPTUNsSU ALPHA_INS_CMPTUNSSU +#define ALPHA_INS_CVTQSsSUI ALPHA_INS_CVTQSSSUI +#define ALPHA_INS_CVTQTsSUI ALPHA_INS_CVTQTSSUI +#define ALPHA_INS_CVTSTsS ALPHA_INS_CVTSTSS +#define ALPHA_INS_CVTTQsSVC ALPHA_INS_CVTTQSSVC +#define ALPHA_INS_CVTTSsSUI ALPHA_INS_CVTTSSSUI +#define ALPHA_INS_DIVSsSU ALPHA_INS_DIVSSSU +#define ALPHA_INS_DIVTsSU ALPHA_INS_DIVTSSU +#define ALPHA_INS_MULSsSU ALPHA_INS_MULSSSU +#define ALPHA_INS_MULTsSU ALPHA_INS_MULTSSU +#define ALPHA_INS_SQRTSsSU ALPHA_INS_SQRTSSSU +#define ALPHA_INS_SQRTTsSU ALPHA_INS_SQRTTSSU +#define ALPHA_INS_SUBSsSU ALPHA_INS_SUBSSSU +#define ALPHA_INS_SUBTsSU ALPHA_INS_SUBTSSU +#define ALPHA_INS_ADDSsSU ALPHA_INS_ADDSSSU +#define ALPHA_INS_ADDTsSU ALPHA_INS_ADDTSSU +#endif + static char *get_reg_profile(RzAnalysis *_) { const char *p = "=PC r31\n" @@ -276,8 +301,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) { case RZ_ALPHA_INS(ADDL): case RZ_ALPHA_INS(ADDQ): - case RZ_ALPHA_INS(ADDSsSU): - case RZ_ALPHA_INS(ADDTsSU): case RZ_ALPHA_INS(AND): case RZ_ALPHA_INS(BIC): case RZ_ALPHA_INS(BIS): @@ -293,10 +316,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) { case RZ_ALPHA_INS(CMPEQ): case RZ_ALPHA_INS(CMPLE): case RZ_ALPHA_INS(CMPLT): - case RZ_ALPHA_INS(CMPTEQsSU): - case RZ_ALPHA_INS(CMPTLEsSU): - case RZ_ALPHA_INS(CMPTLTsSU): - case RZ_ALPHA_INS(CMPTUNsSU): case RZ_ALPHA_INS(CMPULE): case RZ_ALPHA_INS(CMPULT): case RZ_ALPHA_INS(COND_BRANCH): @@ -306,13 +325,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) { case RZ_ALPHA_INS(CTLZ): case RZ_ALPHA_INS(CTPOP): case RZ_ALPHA_INS(CTTZ): - case RZ_ALPHA_INS(CVTQSsSUI): - case RZ_ALPHA_INS(CVTQTsSUI): - case RZ_ALPHA_INS(CVTSTsS): - case RZ_ALPHA_INS(CVTTQsSVC): - case RZ_ALPHA_INS(CVTTSsSUI): - case RZ_ALPHA_INS(DIVSsSU): - case RZ_ALPHA_INS(DIVTsSU): case RZ_ALPHA_INS(ECB): case RZ_ALPHA_INS(EQV): case RZ_ALPHA_INS(EXCB): @@ -358,8 +370,6 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) { case RZ_ALPHA_INS(MSKWL): case RZ_ALPHA_INS(MULL): case RZ_ALPHA_INS(MULQ): - case RZ_ALPHA_INS(MULSsSU): - case RZ_ALPHA_INS(MULTsSU): case RZ_ALPHA_INS(ORNOT): case RZ_ALPHA_INS(RC): case RZ_ALPHA_INS(RPCC): @@ -375,22 +385,37 @@ static void alpha_op_set_type(RzAsmAlphaContext *ctx, RzAnalysisOp *op) { case RZ_ALPHA_INS(SEXTB): case RZ_ALPHA_INS(SEXTW): case RZ_ALPHA_INS(SLL): - case RZ_ALPHA_INS(SQRTSsSU): - case RZ_ALPHA_INS(SQRTTsSU): case RZ_ALPHA_INS(SRA): case RZ_ALPHA_INS(SRL): case RZ_ALPHA_INS(STS): case RZ_ALPHA_INS(STT): case RZ_ALPHA_INS(SUBL): case RZ_ALPHA_INS(SUBQ): - case RZ_ALPHA_INS(SUBSsSU): - case RZ_ALPHA_INS(SUBTsSU): case RZ_ALPHA_INS(TRAPB): case RZ_ALPHA_INS(UMULH): case RZ_ALPHA_INS(WH64): case RZ_ALPHA_INS(WH64EN): case RZ_ALPHA_INS(WMB): case RZ_ALPHA_INS(ZAPNOT): + case RZ_ALPHA_INS(CMPTEQsSU): + case RZ_ALPHA_INS(CMPTLEsSU): + case RZ_ALPHA_INS(CMPTLTsSU): + case RZ_ALPHA_INS(CMPTUNsSU): + case RZ_ALPHA_INS(CVTQSsSUI): + case RZ_ALPHA_INS(CVTQTsSUI): + case RZ_ALPHA_INS(CVTSTsS): + case RZ_ALPHA_INS(CVTTQsSVC): + case RZ_ALPHA_INS(CVTTSsSUI): + case RZ_ALPHA_INS(DIVSsSU): + case RZ_ALPHA_INS(DIVTsSU): + case RZ_ALPHA_INS(MULSsSU): + case RZ_ALPHA_INS(MULTsSU): + case RZ_ALPHA_INS(SQRTSsSU): + case RZ_ALPHA_INS(SQRTTsSU): + case RZ_ALPHA_INS(SUBSsSU): + case RZ_ALPHA_INS(SUBTsSU): + case RZ_ALPHA_INS(ADDSsSU): + case RZ_ALPHA_INS(ADDTsSU): break; } } diff --git a/librz/arch/p/asm/asm_xtensa_cs.c b/librz/arch/p/asm/asm_xtensa_cs.c index 41abdd7cc5..0e94234b99 100644 --- a/librz/arch/p/asm/asm_xtensa_cs.c +++ b/librz/arch/p/asm/asm_xtensa_cs.c @@ -34,6 +34,7 @@ static char **xtensa_cpu_descriptions() { static char *cpu_desc[] = { "esp32", "Xtensa microcontroller with Wi-Fi and Bluetooth capabilities", "esp32s2", "Xtensa microcontroller with Wi-Fi and USB OTG support", + "esp32s3", "Xtensa microcontroller with Wi-Fi, USB OTG support, and HIFI3", "esp8266", "Xtensa microcontroller with Wi-Fi support", NULL }; @@ -46,7 +47,7 @@ RzAsmPlugin rz_asm_plugin_xtensa_cs = { .desc = "Tensilica Xtensa Capstone-based disassembler", .author = "billow", .arch = "xtensa", - .cpus = "esp32,esp32s2,esp8266", + .cpus = "esp32,esp32s2,esp32s3,esp8266", .bits = 32, .endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG, .disassemble = asm_xtensa_disassemble, diff --git a/librz/core/cconfig.c b/librz/core/cconfig.c index 73f23c0716..1c9dbb5230 100644 --- a/librz/core/cconfig.c +++ b/librz/core/cconfig.c @@ -114,9 +114,11 @@ static void update_asmbits_options(RzCore *core, RzConfigNode *node) { int bits = rz_asm_get_plugin_bits(core->rasm); rz_set_s_clear(node->options); + char b[32] = { 0 }; for (int i = 1; i <= bits; i <<= 1) { if (i & bits) { - SETOPTIONS(node, rz_str_newf("%d", i), NULL); + rz_strf(b, "%d", i); + SETOPTIONS(node, b, NULL); } } } diff --git a/librz/main/rz-asm.c b/librz/main/rz-asm.c index 249f46bb68..63a909b11c 100644 --- a/librz/main/rz-asm.c +++ b/librz/main/rz-asm.c @@ -736,11 +736,12 @@ RZ_API int rz_main_rz_asm(int argc, const char *argv[]) { rz_analysis_set_big_endian(as->analysis, canbebig); } if (whatsop) { - const char *s = rz_asm_describe(as->a, opt.argv[opt.ind]); + char *s = rz_asm_describe(as->a, opt.argv[opt.ind]); ret = 1; if (s) { printf("%s\n", s); ret = 0; + free(s); } goto beach; } diff --git a/meson.build b/meson.build index 64893c0b89..02031d1ffe 100644 --- a/meson.build +++ b/meson.build @@ -215,22 +215,6 @@ else add_project_arguments(['-DUSE_SYS_CAPSTONE'], language: 'c') endif -has_capstone_alpha_uppercase_insns = cc.compiles(''' -#include -#include -int main(void) { - alpha_insn insn = ALPHA_INS_INVALID; - return insn == ALPHA_INS_INVALID; -} -''', - dependencies: capstone_check_deps, - include_directories: capstone_check_includes, - name: 'Capstone has uppercase Alpha instruction IDs' -) -if has_capstone_alpha_uppercase_insns - add_project_arguments(['-DRZ_CAPSTONE_ALPHA_INSNS_UPPERCASE'], language: 'c') -endif - has_capstone_m68k_cpu32 = cc.compiles(''' #include int main(void) { diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap index cd5adda549..a49e6945f2 100644 --- a/subprojects/capstone-next.wrap +++ b/subprojects/capstone-next.wrap @@ -1,6 +1,6 @@ [wrap-git] url = https://github.com/capstone-engine/capstone.git -revision = ae11e4232cb1f0df4847bf2d66825b9f1cb119a2 +revision = 6fb5a1717604d171637012dc87baef93773f8f5a directory = capstone-next patch_directory = capstone-next depth = 1 diff --git a/subprojects/capstone-v6.wrap b/subprojects/capstone-v6.wrap index 5397cc6efe..15a029704c 100644 --- a/subprojects/capstone-v6.wrap +++ b/subprojects/capstone-v6.wrap @@ -1,6 +1,6 @@ [wrap-file] -source_url = https://github.com/capstone-engine/capstone/releases/download/6.0.0-Alpha9/capstone-6.0.0-Alpha9.tar.xz -source_filename = capstone-6.0.0-Alpha9.tar.xz -source_hash = 4c8e4f98827236d43be41b91f3faa7cc70f2f0699b97356a60b6a9d492540ed7 -directory = capstone-6.0.0-Alpha9 -patch_directory = capstone-6.0.0-alpha9 +source_url = https://github.com/capstone-engine/capstone/releases/download/6.0.0-Alpha10/capstone-6.0.0-Alpha10.tar.xz +source_filename = capstone-6.0.0-Alpha10.tar.xz +source_hash = 3eabbad2c6e6b6904c78c72110527e5c560a245421fcc2dfbb135aa292a95e94 +directory = capstone-6.0.0-Alpha10 +patch_directory = capstone-6.0.0-alpha10 diff --git a/subprojects/packagefiles/capstone-6.0.0-alpha9/meson.build b/subprojects/packagefiles/capstone-6.0.0-alpha10/meson.build similarity index 100% rename from subprojects/packagefiles/capstone-6.0.0-alpha9/meson.build rename to subprojects/packagefiles/capstone-6.0.0-alpha10/meson.build diff --git a/subprojects/rzspp/p/spp.h b/subprojects/rzspp/p/spp.h index 3d3425fc6c..aa969dddbe 100644 --- a/subprojects/rzspp/p/spp.h +++ b/subprojects/rzspp/p/spp.h @@ -80,6 +80,7 @@ static TAG_CALLBACK(spp_get) { var = spp_var_get (buf); if (var) { out_printf (out, "%s", var); + free(var); } return 0; } @@ -230,6 +231,7 @@ static TAG_CALLBACK(spp_ifeq) { else state->echo[state->ifl + 1] = 0; //fprintf(stderr, "IFEQ(%s)(%s)=%d\n", buf, value, echo[ifl]); } + free(value); return 1; } diff --git a/test/README.md b/test/README.md index 65d0bd3972..2d97773c8d 100644 --- a/test/README.md +++ b/test/README.md @@ -98,6 +98,20 @@ a "nop" 90 # Assembly is correct dB "nopppp" 90 # Disassembly test is broken ``` +#### Select bits and cpu + +Some instructions are only valid for a certain ISA version. +For that `rz-test` is setup with the correct architecture, bits, and cpu model from the file name. + +The possible formats are: + +1. `` + Example: `arm` +2. _ + Example: `arm_32` +3. __ + Example: `arm_cortex_32` + #### Multiple instructions in a single test Some instructions change if they appear together with another instructions. diff --git a/test/db/asm/xtensa b/test/db/asm/xtensa index 10120d7b17..79eaca3d25 100644 --- a/test/db/asm/xtensa +++ b/test/db/asm/xtensa @@ -227,26 +227,6 @@ d "rsil a1, 0xf" 106f00 0x0 (seq (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ d "rsqrt0.s f1, f2" a012fa 0x0 nop d "rsr a1, litbase" 100503 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase)) d "rsync" 102000 0x0 nop -d "rur.accx_0 a0" 0000e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0)) -d "rur.accx_0 a1" 0010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0)) -d "rur.accx_1 a1" 1010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_1)) -d "rur.qacc_h_0 a1" 2010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_0)) -d "rur.qacc_h_1 a1" 3010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_1)) -d "rur.qacc_h_2 a1" 4010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_2)) -d "rur.qacc_h_3 a1" 5010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_3)) -d "rur.qacc_h_4 a1" 6010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_4)) -d "rur.qacc_l_0 a1" 7010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_0)) -d "rur.qacc_l_1 a1" 8010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_1)) -d "rur.qacc_l_2 a1" 9010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_2)) -d "rur.qacc_l_3 a1" a010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_3)) -d "rur.qacc_l_4 a1" b010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_4)) -d "rur.gpio_out a1" c010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var gpio_out)) -d "rur.sar_byte a1" d010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar_byte)) -d "rur.fft_bit_width a1" e010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var fft_bit_width)) -d "rur.ua_state_0 a1" f010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_0)) -d "rur.ua_state_1 a1" 0011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_1)) -d "rur.ua_state_2 a1" 1011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_2)) -d "rur.ua_state_3 a1" 2011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_3)) d "s8i a1, a2, 0xff" 1242ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0xff))) (store 0 (var vAddr) (cast 8 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) d "s16i a1, a2, 0x1fe" 1252ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x1fe))) (storew 0 (var vAddr) (cast 16 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))) d "s32c1i a1, a2, 0x3fc" 12e2ff 0x0 (seq (set vAddr (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x3fc))) (set mem (loadw 0 32 (var vAddr))) (branch (== (var mem) (var scompare1)) (storew 0 (var vAddr) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) nop) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var mem))) @@ -298,21 +278,6 @@ d "wsr a1, br" 100413 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var wi d "wsr a1, litbase" 100513 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var litbase)) d "wsr a1, scompare1" 100c13 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var scompare1)) d "witlb a1, a2" 106250 0x0 nop -d "wur.accx_1 a1" 1001f3 0x0 (set accx_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_h_0 a1" 1002f3 0x0 (set qacc_h_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_h_1 a1" 1003f3 0x0 (set qacc_h_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_h_2 a1" 1004f3 0x0 (set qacc_h_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_h_3 a1" 1005f3 0x0 (set qacc_h_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_h_4 a1" 1006f3 0x0 (set qacc_h_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_l_0 a1" 1007f3 0x0 (set qacc_l_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_l_1 a1" 1008f3 0x0 (set qacc_l_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_l_2 a1" 1009f3 0x0 (set qacc_l_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_l_3 a1" 100af3 0x0 (set qacc_l_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.qacc_l_4 a1" 100bf3 0x0 (set qacc_l_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.gpio_out a1" 100cf3 0x0 (set gpio_out (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.sar_byte a1" 100df3 0x0 (set sar_byte (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.fft_bit_width a1" 100ef3 0x0 (set fft_bit_width (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) -d "wur.ua_state_0 a1" 100ff3 0x0 (set ua_state_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) d "xsr a1, lend" 100161 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lend)) (set lend (var t0))) d "xsr a1, lcount" 100261 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var lcount)) (set lcount (var t0))) d "xsr a1, sar" 100361 0x0 (seq (set t0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar)) (set sar (var t0))) diff --git a/test/db/asm/xtensa_esp32s3_32 b/test/db/asm/xtensa_esp32s3_32 new file mode 100644 index 0000000000..2d24f145b3 --- /dev/null +++ b/test/db/asm/xtensa_esp32s3_32 @@ -0,0 +1,35 @@ +d "rur.accx_0 a0" 0000e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0)) +d "rur.accx_0 a1" 0010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_0)) +d "rur.accx_1 a1" 1010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var accx_1)) +d "rur.qacc_h_0 a1" 2010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_0)) +d "rur.qacc_h_1 a1" 3010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_1)) +d "rur.qacc_h_2 a1" 4010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_2)) +d "rur.qacc_h_3 a1" 5010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_3)) +d "rur.qacc_h_4 a1" 6010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_h_4)) +d "rur.qacc_l_0 a1" 7010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_0)) +d "rur.qacc_l_1 a1" 8010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_1)) +d "rur.qacc_l_2 a1" 9010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_2)) +d "rur.qacc_l_3 a1" a010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_3)) +d "rur.qacc_l_4 a1" b010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var qacc_l_4)) +d "rur.gpio_out a1" c010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var gpio_out)) +d "rur.sar_byte a1" d010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var sar_byte)) +d "rur.fft_bit_width a1" e010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var fft_bit_width)) +d "rur.ua_state_0 a1" f010e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_0)) +d "rur.ua_state_1 a1" 0011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_1)) +d "rur.ua_state_2 a1" 1011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_2)) +d "rur.ua_state_3 a1" 2011e3 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (var ua_state_3)) +d "wur.accx_1 a1" 1001f3 0x0 (set accx_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_0 a1" 1002f3 0x0 (set qacc_h_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_1 a1" 1003f3 0x0 (set qacc_h_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_2 a1" 1004f3 0x0 (set qacc_h_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_3 a1" 1005f3 0x0 (set qacc_h_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_h_4 a1" 1006f3 0x0 (set qacc_h_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_0 a1" 1007f3 0x0 (set qacc_l_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_1 a1" 1008f3 0x0 (set qacc_l_1 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_2 a1" 1009f3 0x0 (set qacc_l_2 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_3 a1" 100af3 0x0 (set qacc_l_3 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.qacc_l_4 a1" 100bf3 0x0 (set qacc_l_4 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.gpio_out a1" 100cf3 0x0 (set gpio_out (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.sar_byte a1" 100df3 0x0 (set sar_byte (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.fft_bit_width a1" 100ef3 0x0 (set fft_bit_width (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) +d "wur.ua_state_0 a1" 100ff3 0x0 (set ua_state_0 (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) diff --git a/test/db/cmd/cmd_aL b/test/db/cmd/cmd_aL index 0937f28838..41357942f1 100644 --- a/test/db/cmd/cmd_aL +++ b/test/db/cmd/cmd_aL @@ -124,6 +124,7 @@ noptr64 Special MIPS configuration to disable support for 64-bit pointer nofloat Special MIPS configuration to disable support for floating-points esp32 Xtensa microcontroller with Wi-Fi and Bluetooth capabilities esp32s2 Xtensa microcontroller with Wi-Fi and USB OTG support +esp32s3 Xtensa microcontroller with Wi-Fi, USB OTG support, and HIFI3 esp8266 Xtensa microcontroller with Wi-Fi support v8 ARMv8 version cortexm ARM Cortex-M family diff --git a/test/db/tools/rz_asm b/test/db/tools/rz_asm index bc13031186..0e500c9a1d 100644 --- a/test/db/tools/rz_asm +++ b/test/db/tools/rz_asm @@ -546,6 +546,7 @@ ARGS=-m xtensa EXPECT=<