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https://github.com/rizinorg/rizin
synced 2026-08-22 20:26:16 -04:00
librz/bin/coff: scale addresses on word-addressed TI targets
The C54x and C28x address 16-bit words, so their loadable section sizes and every address in the file count words. Rizin's address space is byte-based, so reading those unscaled mapped only half of each loadable section and placed every symbol at half its true offset: _main in the c54x emulateme object landed mid-instruction instead of on its prologue. Scale section VAs, loadable section sizes and symbol addresses by the target's address unit. Debug sections are byte streams even on these targets and keep a scale of one, matching the loadable mask already used for mapping. The C55x addresses program memory by byte and is left alone; the ids were checked against the objects in rizin-testbins by comparing each section's declared size against its extent in the file. Branch and call targets on the C54x count program words too, and reached analysis and RzIL unscaled. That went unnoticed while the sections were half-mapped: the emulateme RzIL test ran from a mid-instruction address whose decode happened to lift, so it pinned values produced by garbage. Scale those as well and drive the test the way its C55x sibling does, decrypting seckrit with the real key. With the sections fully mapped, analysis now finds every routine the c54x fixtures declare, so the function counts change.
This commit is contained in:
Anton Kochkov
NOT XVilka
parent
f82d6e2104
commit
fee84c7f5c
8 changed files with 96 additions and 56 deletions
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@ -116,6 +116,9 @@ static RzILOpPure *c54x_ea(const C55Operand *m) {
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}
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// Byte address of the current stack top: SP is a 16-bit word pointer.
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// Program addresses count 16-bit words; the VM runs in the byte address space.
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#define C54X_WORD_BYTES 2
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static RzILOpPure *c54x_sp_ea(void) {
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return MUL(UNSIGNED(24, VARG("sp")), UN(24, C54X_WORD_BYTES));
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}
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@ -1152,7 +1155,7 @@ RZ_IPI RzILOpEffect *c54x_lift(const C55Insn *insn, ut64 pc) {
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if (!pred) {
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return NULL;
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}
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return BRANCH(pred, JMP(UN(24, (ut32)op[0]->imm)), NOP());
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return BRANCH(pred, JMP(UN(24, (ut32)op[0]->imm * C54X_WORD_BYTES)), NOP());
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}
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// conditional return
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@ -1185,7 +1188,7 @@ RZ_IPI RzILOpEffect *c54x_lift(const C55Insn *insn, ut64 pc) {
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}
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// Test the AR before its post-modify, which happens regardless of branch.
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RzILOpEffect *grab = SETL("take", BOOL_TO_BV(INV(IS_ZERO(VARG(ar))), 1));
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RzILOpEffect *br = BRANCH(NON_ZERO(VARL("take")), JMP(UN(24, (ut32)op[0]->imm)), NOP());
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RzILOpEffect *br = BRANCH(NON_ZERO(VARL("take")), JMP(UN(24, (ut32)op[0]->imm * C54X_WORD_BYTES)), NOP());
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RzILOpEffect *post = c55_post_effect(a, op[1]);
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return post ? SEQ3(grab, post, br) : SEQ2(grab, br);
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}
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@ -500,7 +500,10 @@ static ut64 c55_branch_target(const C55Insn *insn, ut64 pc) {
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if (o->abs_target) {
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// Absolute target: the operand is the destination address
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// itself (24-bit program space), not a pc-relative offset.
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return v & 0xffffff;
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// The C54x counts program words here, so scale the target
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// into the byte address space the analysis works in.
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ut64 target = v & 0xffffff;
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return insn->arch == C55_ARCH_C54X ? target * 2 : target;
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}
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st64 soff = o->reltarget_unsigned
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? (st64)v
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@ -124,6 +124,30 @@ RZ_API bool rz_coff_supported_arch(RzBuffer *b) {
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return coff_guess_endianness(b, &big_endian);
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}
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/**
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* \brief Bytes per target address unit of \p obj.
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* \param obj COFF object
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* \return 1 for byte-addressed targets, 2 for the 16-bit word-addressed TI DSPs
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*
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* The C54x and C28x address 16-bit words, so their loadable section
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* sizes and every address in the file count words, not bytes. Rizin's address
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* space is byte-based, so those have to be scaled to line up with the section
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* data. Debug sections are byte streams even on these targets and are excluded
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* by the caller.
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*/
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RZ_API ut32 rz_coff_addr_scale(RZ_NONNULL struct rz_bin_coff_obj *obj) {
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rz_return_val_if_fail(obj, 1);
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switch (obj->target_id) {
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case COFF_FILE_TARGET_TI_TMS320C5400:
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case COFF_FILE_TARGET_TI_TMS320C2800:
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return 2;
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default:
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// The C55x addresses program memory by byte, so its objects need no
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// scaling despite being a fixed-point DSP.
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return 1;
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}
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}
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RZ_API ut64 rz_coff_perms_from_section_flags(ut32 flags) {
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ut32 r = 0;
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if (flags & COFF_SCN_MEM_READ) {
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@ -375,11 +399,15 @@ static bool bin_coff_init_scn_va(struct rz_bin_coff_obj *obj) {
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CoffScnHdr *scn_hdr;
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rz_vector_enumerate (obj->scn_hdrs, scn_hdr, i) {
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if (is_exec) {
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obj->scn_va[i] = scn_hdr->s_vaddr;
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obj->scn_va[i] = (ut64)scn_hdr->s_vaddr * rz_coff_addr_scale(obj);
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continue;
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}
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obj->scn_va[i] = va;
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va += scn_hdr->s_size ? scn_hdr->s_size : 16;
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// Advance by the mapped byte length so the synthetic bases cannot
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// overlap once a word-counted section is scaled.
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const ut32 loadable = COFF_SCN_CNT_CODE | COFF_SCN_CNT_INIT_DATA | COFF_SCN_CNT_UNIN_DATA;
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const ut32 scale = (scn_hdr->s_flags & loadable) ? rz_coff_addr_scale(obj) : 1;
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va += scn_hdr->s_size ? (ut64)scn_hdr->s_size * scale : 16;
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va = RZ_ROUND(va, 16ULL);
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}
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return true;
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@ -37,6 +37,7 @@ struct rz_bin_coff_obj {
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};
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RZ_API bool rz_coff_supported_arch(RzBuffer *b);
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RZ_API ut32 rz_coff_addr_scale(RZ_NONNULL struct rz_bin_coff_obj *obj);
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RZ_API ut64 rz_coff_perms_from_section_flags(ut32 flags);
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RZ_API struct rz_bin_coff_obj *rz_bin_coff_new_buf(RzBuffer *buf);
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RZ_API void rz_bin_coff_free(struct rz_bin_coff_obj *obj);
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@ -82,8 +82,9 @@ static bool coff_fill_bin_symbol(RzBin *rbin, struct rz_bin_coff_obj *bin, size_
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if ((bin->hdr.f_flags & COFF_FLAGS_TI_F_EXEC) != 0) {
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const ut32 loadable = COFF_SCN_CNT_CODE | COFF_SCN_CNT_INIT_DATA | COFF_SCN_CNT_UNIN_DATA;
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if (sc_hdr->s_flags & loadable) {
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ptr->vaddr = s->n_value;
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ptr->paddr = sc_hdr->s_scnptr + (s->n_value - sc_hdr->s_vaddr);
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const ut32 scale = rz_coff_addr_scale(bin);
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ptr->vaddr = (ut64)s->n_value * scale;
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ptr->paddr = sc_hdr->s_scnptr + (ut64)(s->n_value - sc_hdr->s_vaddr) * scale;
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} else {
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// Symbol belongs to a non-loadable section (DWARF/debug, build
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// attributes, .pinit). Its n_value is not an address in the
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@ -97,9 +98,11 @@ static bool coff_fill_bin_symbol(RzBin *rbin, struct rz_bin_coff_obj *bin, size_
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ptr->paddr = sc_hdr->s_scnptr + s->n_value;
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}
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} else {
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ptr->paddr = sc_hdr->s_scnptr + s->n_value;
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const ut32 loadable = COFF_SCN_CNT_CODE | COFF_SCN_CNT_INIT_DATA | COFF_SCN_CNT_UNIN_DATA;
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const ut32 scale = (sc_hdr->s_flags & loadable) ? rz_coff_addr_scale(bin) : 1;
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ptr->paddr = sc_hdr->s_scnptr + (ut64)s->n_value * scale;
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if (bin->scn_va) {
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ptr->vaddr = bin->scn_va[s->n_scnum - 1] + s->n_value;
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ptr->vaddr = bin->scn_va[s->n_scnum - 1] + (ut64)s->n_value * scale;
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}
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}
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}
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@ -300,8 +303,11 @@ static RzPVector /*<RzBinMap *>*/ *coff_maps(RzBinFile *bf) {
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return ret;
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}
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ptr->name = rz_coff_symbol_name(obj, (const ut8 *)hdr->s_name);
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ptr->psize = hdr->s_size;
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ptr->vsize = hdr->s_size;
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// Only loadable sections are counted in target address units; debug
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// sections are byte streams even on a word-addressed target.
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const ut32 scale = (hdr->s_flags & loadable) ? rz_coff_addr_scale(obj) : 1;
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ptr->psize = (ut64)hdr->s_size * scale;
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ptr->vsize = (ut64)hdr->s_size * scale;
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ptr->paddr = hdr->s_scnptr;
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if (obj->scn_va) {
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ptr->vaddr = obj->scn_va[i];
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@ -355,8 +361,10 @@ static RzPVector /*<RzBinSection *>*/ *coff_sections(RzBinFile *bf) {
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if (strstr(ptr->name, "data")) {
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ptr->is_data = true;
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}
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ptr->size = scn_hdr->s_size;
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ptr->vsize = scn_hdr->s_size;
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const ut32 loadable = COFF_SCN_CNT_CODE | COFF_SCN_CNT_INIT_DATA | COFF_SCN_CNT_UNIN_DATA;
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const ut32 scale = (scn_hdr->s_flags & loadable) ? rz_coff_addr_scale(obj) : 1;
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ptr->size = (ut64)scn_hdr->s_size * scale;
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ptr->vsize = (ut64)scn_hdr->s_size * scale;
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ptr->paddr = scn_hdr->s_scnptr;
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ptr->flags = scn_hdr->s_flags;
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if (obj->scn_va) {
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@ -141,22 +141,22 @@ EXPECT=<<EOF
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type: nop
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size: 2
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type: jmp
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jump: 0x00000100
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jump: 0x00000200
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type: jmp
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jump: 0x00000100
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jump: 0x00000200
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type: call
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jump: 0x00000100
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jump: 0x00000200
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fail: 0x00000004
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stackptr: 2
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type: cjmp
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jump: 0x00000120
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jump: 0x00000240
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fail: 0x00000004
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type: ccall
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jump: 0x00000120
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jump: 0x00000240
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fail: 0x00000004
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stackptr: 2
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type: cjmp
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jump: 0x00000120
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jump: 0x00000240
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fail: 0x00000004
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type: ujmp
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fail: 0x00000002
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@ -248,7 +248,7 @@ direction: exec
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stackop: inc
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stackptr: 2
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type: call
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jump: 0x00000100
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jump: 0x00000200
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direction: exec
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EOF
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RUN
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@ -322,7 +322,7 @@ val: 0x00001234
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val: 0x00001234
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val: 0x0000000f
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type: jmp
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jump: 0x00002010
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jump: 0x00004020
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EOF
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RUN
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@ -391,7 +391,7 @@ arch tms320
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cpu c54x
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bintype coff
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endian LE
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12
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13
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1
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EOF
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RUN
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@ -407,7 +407,7 @@ EOF
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EXPECT=<<EOF
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arch tms320
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cpu c54x
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8
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9
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EOF
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RUN
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@ -1,8 +1,8 @@
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d "nop" 95f4 0x0 nop
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d "b 0x100" 73f00001 0x0 (jmp (bv 24 0x100))
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d "bd 0x100" 73f20001 0x0 (jmp (bv 24 0x100))
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d "call 0x100" 74f00001 0x0 (jmp (bv 24 0x100))
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d "calld 0x100" 74f20001 0x0 (jmp (bv 24 0x100))
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d "b 0x100" 73f00001 0x0 (jmp (bv 24 0x200))
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d "bd 0x100" 73f20001 0x0 (jmp (bv 24 0x200))
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d "call 0x100" 74f00001 0x0 (jmp (bv 24 0x200))
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d "calld 0x100" 74f20001 0x0 (jmp (bv 24 0x200))
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d "ret" 00fc 0x0 (seq (set sp (+ (var sp) (bv 16 0x1))) (jmp (cast 24 false (loadw 0 16 (* (cast 24 false (var sp)) (bv 24 0x2))))))
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d "retd" 00fe 0x0 (seq (set sp (+ (var sp) (bv 16 0x1))) (jmp (cast 24 false (loadw 0 16 (* (cast 24 false (var sp)) (bv 24 0x2))))))
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d "rete" ebf4 0x0 (seq (set ret_addr (loadw 0 24 (* (cast 24 false (var sp)) (bv 24 0x2)))) (set sp (+ (var sp) (bv 16 0x2))) (jmp (var ret_addr)))
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@ -13,10 +13,10 @@ d "bacc a" e2f4 0x0 (jmp (cast 24 false (var a)))
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d "baccd a" e2f6 0x0 (jmp (cast 24 false (var a)))
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d "cala a" e3f4 0x0 (jmp (cast 24 false (var a)))
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d "calad a" e3f6 0x0 (jmp (cast 24 false (var a)))
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d "fb 0x2" 80f80200 0x0 (jmp (bv 24 0x2))
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d "fbd 0x2" 80fa0200 0x0 (jmp (bv 24 0x2))
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d "fcall 0xf" 80f90f00 0x0 (jmp (bv 24 0xf))
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d "fcalld 0xf" 80fb0f00 0x0 (jmp (bv 24 0xf))
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d "fb 0x2" 80f80200 0x0 (jmp (bv 24 0x4))
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d "fbd 0x2" 80fa0200 0x0 (jmp (bv 24 0x4))
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d "fcall 0xf" 80f90f00 0x0 (jmp (bv 24 0x1e))
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d "fcalld 0xf" 80fb0f00 0x0 (jmp (bv 24 0x1e))
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d "fret" e4f4 0x0 (seq (set ret_addr (loadw 0 24 (* (cast 24 false (var sp)) (bv 24 0x2)))) (set sp (+ (var sp) (bv 16 0x2))) (jmp (var ret_addr)))
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d "fretd" e4f6 0x0 (seq (set ret_addr (loadw 0 24 (* (cast 24 false (var sp)) (bv 24 0x2)))) (set sp (+ (var sp) (bv 16 0x2))) (jmp (var ret_addr)))
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d "frete" e5f4 0x0 (seq (set ret_addr (loadw 0 24 (* (cast 24 false (var sp)) (bv 24 0x2)))) (set sp (+ (var sp) (bv 16 0x2))) (jmp (var ret_addr)))
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@ -89,13 +89,13 @@ d "frame #-2" feee 0x0 (set sp (+ (var sp) (bv 16 0xfffe)))
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d "frame #10" 0aee 0x0 (set sp (+ (var sp) (bv 16 0xa)))
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d "bitf *ar1, #0x1234" 81613412 0x0 (set st0 (| (& (var st0) (bv 16 0xefff)) (ite (! (is_zero (& (loadw 0 16 (* (cast 24 false (var ar1)) (bv 24 0x2))) (bv 16 0x1234)))) (bv 16 0x1000) (bv 16 0x0))))
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d "cmpm *ar1, #0x1234" 81603412 0x0 (set st0 (| (& (var st0) (bv 16 0xefff)) (ite (== (loadw 0 16 (* (cast 24 false (var ar1)) (bv 24 0x2))) (bv 16 0x1234)) (bv 16 0x1000) (bv 16 0x0))))
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d "bc 0x100, agt" 46f80001 0x0 (branch (! (sle (var a) (bv 40 0x0))) (jmp (bv 24 0x100)) nop)
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d "bc 0x100, aeq" 45f80001 0x0 (branch (is_zero (var a)) (jmp (bv 24 0x100)) nop)
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d "cc 0x200, bneq" 4cf90002 0x0 (branch (! (is_zero (var b))) (jmp (bv 24 0x200)) nop)
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d "bcd 0x100, agt" 46fa0001 0x0 (branch (! (sle (var a) (bv 40 0x0))) (jmp (bv 24 0x100)) nop)
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d "ccd 0x200, bneq" 4cfb0002 0x0 (branch (! (is_zero (var b))) (jmp (bv 24 0x200)) nop)
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d "banz 0x100, *ar1-" 896c0001 0x0 (seq (set take (ite (! (is_zero (var ar1))) (bv 1 0x1) (bv 1 0x0))) (set ar1 (- (var ar1) (bv 16 0x1))) (branch (! (is_zero (var take))) (jmp (bv 24 0x100)) nop))
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d "banzd 0x100, *ar1-" 896e0001 0x0 (seq (set take (ite (! (is_zero (var ar1))) (bv 1 0x1) (bv 1 0x0))) (set ar1 (- (var ar1) (bv 16 0x1))) (branch (! (is_zero (var take))) (jmp (bv 24 0x100)) nop))
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d "bc 0x100, agt" 46f80001 0x0 (branch (! (sle (var a) (bv 40 0x0))) (jmp (bv 24 0x200)) nop)
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d "bc 0x100, aeq" 45f80001 0x0 (branch (is_zero (var a)) (jmp (bv 24 0x200)) nop)
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d "cc 0x200, bneq" 4cf90002 0x0 (branch (! (is_zero (var b))) (jmp (bv 24 0x400)) nop)
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d "bcd 0x100, agt" 46fa0001 0x0 (branch (! (sle (var a) (bv 40 0x0))) (jmp (bv 24 0x200)) nop)
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d "ccd 0x200, bneq" 4cfb0002 0x0 (branch (! (is_zero (var b))) (jmp (bv 24 0x400)) nop)
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d "banz 0x100, *ar1-" 896c0001 0x0 (seq (set take (ite (! (is_zero (var ar1))) (bv 1 0x1) (bv 1 0x0))) (set ar1 (- (var ar1) (bv 16 0x1))) (branch (! (is_zero (var take))) (jmp (bv 24 0x200)) nop))
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d "banzd 0x100, *ar1-" 896e0001 0x0 (seq (set take (ite (! (is_zero (var ar1))) (bv 1 0x1) (bv 1 0x0))) (set ar1 (- (var ar1) (bv 16 0x1))) (branch (! (is_zero (var take))) (jmp (bv 24 0x200)) nop))
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d "stl a, *ar1(0xc)" e1800c00 0x0 (storew 0 (* (+ (cast 24 false (var ar1)) (bv 24 0xc)) (bv 24 0x2)) (cast 16 false (var a)))
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d "ld *ar1(0x1), a" e1100100 0x0 (set a (cast 40 (msb (loadw 0 16 (* (+ (cast 24 false (var ar1)) (bv 24 0x1)) (bv 24 0x2)))) (loadw 0 16 (* (+ (cast 24 false (var ar1)) (bv 24 0x1)) (bv 24 0x2)))))
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d "ldm ar1, a" 1148 0x0 (set a (cast 40 false (var ar1)))
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@ -260,7 +260,7 @@ d "rc bgeq" 4afc 0x0 (branch (|| (! (sle (var b) (bv 40 0x0))) (== (var b) (bv 4
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d "xc 1, aeq" 45fd
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d "xc 2, aeq" 45ff
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d "xc 1, tc, c" 3cfd
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d "bc 0x1234, tc, c" 3cf83412 0x0 (branch (&& (! (is_zero (& (var st0) (bv 16 0x1000)))) (! (is_zero (& (var st0) (bv 16 0x800))))) (jmp (bv 24 0x1234)) nop)
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d "bc 0x1234, tc, c" 3cf83412 0x0 (branch (&& (! (is_zero (& (var st0) (bv 16 0x1000)))) (! (is_zero (& (var st0) (bv 16 0x800))))) (jmp (bv 24 0x2468)) nop)
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d "ldm imr, a" 0048 0x0 (set a (cast 40 false (var imr)))
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d "ldm al, a" 0848
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d "ldm ah, a" 0948
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||||
|
|
|
|||
|
|
@ -347,29 +347,26 @@ ar4 = 0x30
|
|||
EOF
|
||||
RUN
|
||||
|
||||
NAME=C54x RzIL VM: emulateme _decrypt writes hex digits to the UART buffer
|
||||
# Key at word 0x280 (byte 0x500) in A, encrypted seckrit at _seckrit; the stack
|
||||
# is kept clear of .text, which the linker places at byte 0x100.
|
||||
NAME=C54x RzIL VM: emulateme _decrypt decrypts seckrit to "Hello from RzIL!"
|
||||
FILE=bins/tms320/emulateme_nostd.ccsv5.c54x.ticoff2.dbg.coff
|
||||
CMDS=<<EOF
|
||||
e io.cache=true
|
||||
wx 30003100320033003400350036003700380039006100620063006400650066 @ 0x900
|
||||
wx 0006 @ 0x9a4
|
||||
wx 00000000 @ 0x9a8
|
||||
s 0xec
|
||||
wx 510053004d0077005800140051005f0045006c0017007f006e0078007f001c000000 @ 0x9ac
|
||||
wx 41006e00790043006f006c006f007500720059006f0075004c0069006b006500 @ 0x500
|
||||
s 0x1d8
|
||||
aezi
|
||||
aezv a 0x5a
|
||||
aezv b 0x5
|
||||
aezv sp 0x100
|
||||
aezsu 0x136
|
||||
p8 4 @ 0xc00
|
||||
p8 2 @ 0x9aa
|
||||
aezv sp 0x800
|
||||
aezv a 0x280
|
||||
aezsu 0x270
|
||||
p8 32 @ 0x9ac
|
||||
ar a
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
a = 0x5a
|
||||
b = 0x5
|
||||
sp = 0x100
|
||||
35006100
|
||||
0200
|
||||
a = 0x0000000002
|
||||
sp = 0x800
|
||||
a = 0x280
|
||||
480065006c006c006f002000660072006f006d00200052007a0049004c002100
|
||||
a = 0x0000000001
|
||||
EOF
|
||||
RUN
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue