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19b1783c88
The `RzFloat` changes fix or improve: - binary80 explicit-integer-bit, pseudo-value, infinity, and NaN handling; - binary16 conversions; - gradual underflow and directed rounding; - overflow, underflow, invalid-operation, and inexact exception reporting; - exception propagation through nested conversions and arithmetic operations; - binary80 fused multiply-add rounding, including reduced-precision and double-rounding edge cases; - thread-local SoftFloat state, preventing rounding state from leaking between threads. The `RzIL` changes add scoped binary80 precision support through `RzFloatRPrecision` and `FWITH_RPREC`. The supported precisions are 32, 64, and 80. Precision scopes restore the previous thread-local SoftFloat state after successful evaluation and evaluation failures. Runtime rounding modes are represented explicitly by dedicated pure opcodes: - `FCONVERT_WITH_RMODE` - `FROUND_WITH_RMODE` - `FSQRT_WITH_RMODE` - `FADD_WITH_RMODE` - `FSUB_WITH_RMODE` - `FMUL_WITH_RMODE` - `FDIV_WITH_RMODE` - `FMOD_WITH_RMODE` Their rounding-mode operand is a 32-bit IL bitvector whose values correspond to `RzFloatRMode`: RNE, RNA, RTP, RTN, and RTZ. Invalid operand widths are rejected by validation, while invalid runtime values cause evaluation to fail with an error. Dedicated opcodes keep runtime-controlled floating-point expressions compact. This is useful for architectures whose rounding mode is selected from register state and avoids the expression duplication caused by expanding every operation into nested `ITE` branches. The new operations are supported by: - construction, duplication, and destruction; - type and operand validation; - VM evaluation; - plain, Unicode, and JSON exporters; - graph output and opcode stringification. `FEXCEPT` now emits a VM event only when the queried exception is present, while preserving exceptions raised by nested conversions and arithmetic operations. |
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