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https://github.com/rizinorg/rizin
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148b54a9fc
Add the real TMS320C5x (C50/C51/C53) object encoding. The C5x is source-compatible with the C2x but encodes instructions differently, so it cannot reuse the C2x decode table: a dedicated C5x decode front-end fills the shared C55 instruction representation, carrying the C2x ids for shared-semantics instructions (so the common consumers apply unchanged) and new C5x-only ids for the C5x additions (ACCB ops, parallel-logic, memory-mapped register access, conditional execute/call/return, block moves, ...). Wired into the tms320 asm and analysis plugins under cpu "c5x", with the C5x mnemonic and op-type tables and register profile. Includes disassembly and opcode classification tests. |
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| .. | ||
| rz | ||
| rz_ar | ||
| rz_asm | ||
| rz_ax | ||
| rz_bin | ||
| rz_diff | ||
| rz_find | ||
| rz_gg | ||
| rz_hash | ||
| rz_run | ||
| rz_sign | ||
| rz_test | ||