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https://github.com/rizinorg/rizin
synced 2026-08-22 20:26:16 -04:00
79bec39195
Lift the TMS320C2x instruction set to RzIL: the 32-bit accumulator and product paths, the auxiliary-register file with all indirect addressing modes, the status bits (carry, overflow, OVM saturation, SXM sign extension, product-mode shifts, TC), and the load/store, multiply, accumulate, shift, logical and control-flow instructions. Wired into the analysis plugin's il_config under cpu "c2x". The asm tests now assert the lifted RzIL for every instruction, with execution tests covering the IL VM end to end.
178 lines
3.1 KiB
Text
178 lines
3.1 KiB
Text
# TMS320C2x / TMS320C5x legacy binaries -- RzIL VM execution tests.
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# Binaries assembled from src/*.asm with the Python tms320c2x assembler and
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# cross-checked against the Python emulator; stepped here in Rizin's RzIL VM.
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# io.cache gives the program writable data memory beyond the raw file image.
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NAME=c2x RzIL VM: arithmetic + load/store legacy binary
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FILE=bins/tms320/c2x_legacy/01_arithmetic.bin
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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aezi
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aezs 40
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ar acc
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ar t
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ar p
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ar dp
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ar arp
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ar ar2
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EOF
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EXPECT=<<EOF
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acc = 0x00000033
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t = 0x0006
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p = 0x0000002a
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dp = 0x0004
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arp = 0x0002
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ar2 = 0x0211
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EOF
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RUN
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NAME=c2x RzIL VM: logic + shift/rotate legacy binary
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FILE=bins/tms320/c2x_legacy/02_logic_shifts.bin
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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aezi
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aezs 34
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ar acc
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ar t
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ar p
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ar dp
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ar arp
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ar ar2
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EOF
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EXPECT=<<EOF
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acc = 0x00000030
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t = 0x0004
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p = 0x00000000
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dp = 0x0004
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arp = 0x0000
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ar2 = 0x0000
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EOF
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RUN
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NAME=c2x RzIL VM: branches + CALL/RET legacy binary
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FILE=bins/tms320/c2x_legacy/03_branches_calls.bin
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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aezi
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aezv sp 0x100
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aezs 23
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ar acc
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ar t
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ar p
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ar dp
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ar arp
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ar ar2
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EOF
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EXPECT=<<EOF
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sp = 0x100
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acc = 0x000000aa
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t = 0x0000
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p = 0x00000000
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dp = 0x0004
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arp = 0x0000
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ar2 = 0x0000
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EOF
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RUN
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NAME=c2x RzIL VM: FIR dot-product (MAC chain) legacy binary
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FILE=bins/tms320/c2x_legacy/04_fir_filter.bin
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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aezi
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aezs 57
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ar acc
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ar t
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ar p
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ar dp
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ar arp
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ar ar2
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EOF
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EXPECT=<<EOF
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acc = 0x000000c8
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t = 0x0002
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p = 0x00000002
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dp = 0x0006
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arp = 0x0002
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ar2 = 0x0310
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EOF
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RUN
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NAME=c2x RzIL VM: status save/restore + data move legacy binary
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FILE=bins/tms320/c2x_legacy/05_status_data.bin
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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aezi
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aezs 27
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ar acc
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ar t
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ar p
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ar dp
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ar arp
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ar ar2
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EOF
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EXPECT=<<EOF
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acc = 0x0000005a
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t = 0x0000
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p = 0x00000000
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dp = 0x0006
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arp = 0x0000
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ar2 = 0x0000
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EOF
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RUN
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NAME=c2x RzIL VM: mixed full program legacy binary
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FILE=bins/tms320/c2x_legacy/10_full_program.bin
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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aezi
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aezs 48
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ar acc
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ar t
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ar p
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ar dp
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ar arp
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ar ar2
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EOF
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EXPECT=<<EOF
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acc = 0x0000005a
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t = 0x0064
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p = 0x00004e20
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dp = 0x0006
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arp = 0x0004
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ar2 = 0x0306
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EOF
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RUN
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NAME=c2x RzIL VM: emulateme complex exerciser (loops, MAC, XOR buffer, call/stack, fold)
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FILE=malloc://0x800
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ARGS=-a tms320 -b 16 -e asm.cpu=c2x -e analysis.cpu=c2x
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CMDS=<<EOF
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e io.cache=true
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wx c806d10003005589ca0360a0ca0160a0ca0460a0ca0160a0ca0560a0ca0960a0ca0260a0ca0660a0d1000300d4000007ca006010558920a000106010558cfb90001ad1000300d4000007ca00601155893c8038a0ce15558cfb90002768126011d1000300d2000318d4000007558920a0d006005a558a60a0558cfb9000362010fe80004e60132011d00400ffce18d0050100d00600556014ff80004cce1cce1dce18ce26
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aezi
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aezv sp 0x100
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aezsu 0x98
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p8 10 @ 0x620
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p8 16 @ 0x630
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ar acc
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ar p
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ar t
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ar arp
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EOF
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EXPECT=<<EOF
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sp = 0x100
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001f00ad0000003e010f
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0059005b005e005b005f00530058005c
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acc = 0x0000010f
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p = 0x00000024
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t = 0x0006
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arp = 0x0004
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EOF
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RUN
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