mirror of
https://github.com/rizinorg/rizin
synced 2026-08-22 20:26:16 -04:00
7f55442dc2
* Refactor of bflt to guess arch & fix m68k code * Fix endianness issues * Always cleanup at the end on travis ci
1276 lines
16 KiB
Text
1276 lines
16 KiB
Text
NAME=AVR: aeso on call
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FILE=malloc://1024
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CMDS=<<EOF
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e asm.arch=avr
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e cfg.bigendian=false
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e asm.bits=8
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wx 0xf8 0x94 0x08 0xe0 0x0e 0xbf 0x0f 0xe5 0x0d 0xbf 0x0e 0x94 0x08 0x00 0x88 0x95 0x08 0x95
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aei
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aeim 0x00000100 0xffff avr_ram
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6aeso
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ar pc
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ar pc = 0
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7aes
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ar pc
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EOF
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EXPECT=<<EOF
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pc = 0x0000000e
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pc = 0x0000000e
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EOF
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RUN
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# des tests are checked against Microchip's AVR Simulator emulating ATxmega128A1
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NAME=AVR: des encrypt
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FILE=malloc://1024
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CMDS=<<EOF
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(regs ;ar 8~:0..16) # show regs r0-r15
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e asm.arch=avr
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e cfg.bigendian=false
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wx 0b941b942b943b944b945b946b947b948b949b94ab94bb94cb94db94eb94fb94
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ar r0 = 0x41
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ar r1 = 0x20
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ar r2 = 0x52
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ar r3 = 0x69
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ar r4 = 0x76
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ar r5 = 0x61
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ar r6 = 0x6c
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ar r7 = 0x20
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ar r8 = 0x41
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ar r9 = 0x70
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ar r10 = 0x70
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ar r11 = 0x65
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ar r12 = 0x61
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ar r13 = 0x72
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ar r14 = 0x73
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ar r15 = 0x21
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.(regs)
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aei
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echo -- round 0; aes; .(regs)
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echo -- round 1; aes; .(regs)
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echo -- round 2; aes; .(regs)
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echo -- round 3; aes; .(regs)
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echo -- round 4; aes; .(regs)
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echo -- round 5; aes; .(regs)
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echo -- round 6; aes; .(regs)
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echo -- round 7; aes; .(regs)
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echo -- round 8; aes; .(regs)
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echo -- round 9; aes; .(regs)
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echo -- round 10; aes; .(regs)
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echo -- round 11; aes; .(regs)
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echo -- round 12; aes; .(regs)
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echo -- round 13; aes; .(regs)
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echo -- round 14; aes; .(regs)
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echo -- round 15; aes; .(regs)
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ar pcl
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EOF
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EXPECT=<<EOF
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r0 = 0x41
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r1 = 0x20
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r2 = 0x52
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r3 = 0x69
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r4 = 0x76
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r5 = 0x61
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r6 = 0x6c
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r7 = 0x20
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r8 = 0x41
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r9 = 0x70
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r10 = 0x70
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r11 = 0x65
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r12 = 0x61
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r13 = 0x72
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r14 = 0x73
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r15 = 0x21
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-- round 0
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r0 = 0x00
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r1 = 0x18
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r2 = 0xa9
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r3 = 0xbc
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r4 = 0x1b
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r5 = 0x10
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r6 = 0x36
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r7 = 0x1a
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r8 = 0x71
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r9 = 0x70
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r10 = 0x64
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r11 = 0x61
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r12 = 0x73
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r13 = 0x72
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r14 = 0x21
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r15 = 0x81
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-- round 1
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r0 = 0x22
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r1 = 0x04
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r2 = 0x7e
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r3 = 0x7c
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r4 = 0x8d
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r5 = 0x80
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r6 = 0x91
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r7 = 0x25
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r8 = 0x71
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r9 = 0x64
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r10 = 0x60
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r11 = 0x63
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r12 = 0x73
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r13 = 0x20
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r14 = 0x81
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r15 = 0xe9
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-- round 2
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r0 = 0x91
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r1 = 0x00
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r2 = 0x3d
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r3 = 0xb4
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r4 = 0xe6
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r5 = 0x60
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r6 = 0xc8
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r7 = 0x98
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r8 = 0x61
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r9 = 0x62
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r10 = 0x62
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r11 = 0x21
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r12 = 0x81
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r13 = 0xe8
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r14 = 0xe9
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r15 = 0xc3
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-- round 3
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r0 = 0x62
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r1 = 0x22
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r2 = 0x1c
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r3 = 0x5a
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r4 = 0xf1
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r5 = 0x3a
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r6 = 0x46
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r7 = 0x4e
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r8 = 0x63
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r9 = 0x20
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r10 = 0x80
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r11 = 0xe9
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r12 = 0xe9
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r13 = 0xc2
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r14 = 0xc1
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r15 = 0xd1
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-- round 4
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r0 = 0x3b
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r1 = 0x91
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r2 = 0x26
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r3 = 0x85
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r4 = 0xf0
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r5 = 0x35
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r6 = 0x03
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r7 = 0x8d
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r8 = 0x81
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r9 = 0xe8
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r10 = 0xe8
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r11 = 0xc3
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r12 = 0xc1
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r13 = 0xd0
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r14 = 0xd1
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r15 = 0x41
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-- round 5
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r0 = 0x9d
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r1 = 0x6a
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r2 = 0x19
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r3 = 0xea
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r4 = 0x72
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r5 = 0xba
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r6 = 0x89
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r7 = 0x6e
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r8 = 0xe9
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r9 = 0xc2
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r10 = 0xd0
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r11 = 0xd1
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r12 = 0xd1
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r13 = 0x40
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r14 = 0x01
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r15 = 0xcd
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-- round 6
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r0 = 0x64
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r1 = 0xb5
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r2 = 0x2e
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r3 = 0xff
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r4 = 0x9b
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r5 = 0x5f
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r6 = 0xc4
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r7 = 0x15
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r8 = 0xd1
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r9 = 0xd0
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r10 = 0xd0
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r11 = 0x51
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r12 = 0x01
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r13 = 0xcc
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r14 = 0xcd
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r15 = 0x91
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-- round 7
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r0 = 0xba
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r1 = 0x5a
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r2 = 0x97
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r3 = 0x5f
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r4 = 0xef
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r5 = 0x8f
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r6 = 0xe2
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r7 = 0x08
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r8 = 0xd1
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r9 = 0x50
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r10 = 0x10
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r11 = 0xdd
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r12 = 0xcd
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r13 = 0x90
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r14 = 0xa1
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r15 = 0xa1
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-- round 8
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r0 = 0x7f
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r1 = 0x2d
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r2 = 0xe9
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r3 = 0x2f
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r4 = 0xdf
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r5 = 0xcd
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r6 = 0xf3
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r7 = 0x26
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r8 = 0x51
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r9 = 0x10
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r10 = 0xdc
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r11 = 0xdd
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r12 = 0x91
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r13 = 0xa0
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r14 = 0xa1
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r15 = 0xa1
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-- round 9
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r0 = 0x3f
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r1 = 0x96
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r2 = 0xdc
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r3 = 0x1f
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r4 = 0x6f
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r5 = 0x66
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r6 = 0x51
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r7 = 0x39
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r8 = 0xdd
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r9 = 0xdc
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r10 = 0x80
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r11 = 0xa1
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r12 = 0xa1
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r13 = 0xa0
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r14 = 0xa9
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r15 = 0x21
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-- round 10
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r0 = 0xbf
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r1 = 0xc9
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r2 = 0x4e
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r3 = 0xad
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r4 = 0x95
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r5 = 0x99
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r6 = 0x2a
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r7 = 0x94
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r8 = 0x81
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r9 = 0xa0
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r10 = 0xb0
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r11 = 0xb1
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r12 = 0xa9
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r13 = 0x20
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r14 = 0xa7
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r15 = 0xa7
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-- round 11
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r0 = 0x7f
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r1 = 0xc6
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r2 = 0xaf
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r3 = 0xfe
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r4 = 0x4a
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r5 = 0xee
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r6 = 0xbd
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r7 = 0x40
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r8 = 0xb1
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r9 = 0xb0
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r10 = 0xb8
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r11 = 0x31
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r12 = 0xa7
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r13 = 0xa6
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r14 = 0x01
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r15 = 0x41
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-- round 12
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r0 = 0x3d
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r1 = 0xc3
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r2 = 0x57
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r3 = 0x55
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r4 = 0x8d
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r5 = 0x7d
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r6 = 0x54
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r7 = 0xaa
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r8 = 0xb9
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r9 = 0x30
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r10 = 0xb6
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r11 = 0xb7
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r12 = 0x01
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r13 = 0x40
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r14 = 0x61
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r15 = 0x61
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-- round 13
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r0 = 0x1e
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r1 = 0x61
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r2 = 0xa1
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r3 = 0x08
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r4 = 0xc4
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r5 = 0xb6
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r6 = 0x28
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r7 = 0x75
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r8 = 0xb7
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r9 = 0xb6
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r10 = 0x10
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r11 = 0x41
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r12 = 0x61
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r13 = 0x60
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r14 = 0x65
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r15 = 0x61
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-- round 14
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r0 = 0xa5
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r1 = 0xba
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r2 = 0x72
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r3 = 0x06
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r4 = 0x60
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r5 = 0x7b
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r6 = 0xb4
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r7 = 0xb8
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r8 = 0x11
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r9 = 0x40
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r10 = 0x70
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r11 = 0x71
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r12 = 0x65
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r13 = 0x60
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r14 = 0x73
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r15 = 0x73
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-- round 15
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r0 = 0xf5
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r1 = 0xfe
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r2 = 0x27
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r3 = 0x16
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r4 = 0x61
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r5 = 0x3f
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r6 = 0xf5
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r7 = 0xbc
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r8 = 0x41
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r9 = 0x70
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r10 = 0x70
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r11 = 0x65
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r12 = 0x61
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r13 = 0x72
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r14 = 0x73
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r15 = 0x21
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pcl = 0x0020
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EOF
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RUN
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NAME=AVR: des decrypt
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FILE=malloc://1024
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CMDS=<<EOF
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(regs ;ar 8~:0..16) # show regs r0-r15
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e asm.arch=avr
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e cfg.bigendian=false
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wx 58940b941b942b943b944b945b946b947b948b949b94ab94bb94cb94db94eb94fb94
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ar r0 = 0xf5
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ar r1 = 0xfe
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ar r2 = 0x27
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ar r3 = 0x16
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ar r4 = 0x61
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ar r5 = 0x3f
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ar r6 = 0xf5
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ar r7 = 0xbc
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ar r8 = 0x41
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ar r9 = 0x70
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ar r10 = 0x70
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ar r11 = 0x65
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ar r12 = 0x61
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ar r13 = 0x72
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ar r14 = 0x73
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ar r15 = 0x21
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.(regs)
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aei
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aes
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echo decrypt?; ar hf
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echo -- round 0; aes; .(regs)
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echo -- round 1; aes; .(regs)
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echo -- round 2; aes; .(regs)
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echo -- round 3; aes; .(regs)
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echo -- round 4; aes; .(regs)
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echo -- round 5; aes; .(regs)
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echo -- round 6; aes; .(regs)
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echo -- round 7; aes; .(regs)
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echo -- round 8; aes; .(regs)
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echo -- round 9; aes; .(regs)
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echo -- round 10; aes; .(regs)
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echo -- round 11; aes; .(regs)
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echo -- round 12; aes; .(regs)
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echo -- round 13; aes; .(regs)
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echo -- round 14; aes; .(regs)
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echo -- round 15; aes; .(regs)
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ar pcl
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EOF
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EXPECT=<<EOF
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r0 = 0xf5
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r1 = 0xfe
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r2 = 0x27
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r3 = 0x16
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r4 = 0x61
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r5 = 0x3f
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r6 = 0xf5
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r7 = 0xbc
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r8 = 0x41
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r9 = 0x70
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r10 = 0x70
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r11 = 0x65
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r12 = 0x61
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r13 = 0x72
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r14 = 0x73
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r15 = 0x21
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decrypt?
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hf = 0x1
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-- round 0
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r0 = 0x5a
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r1 = 0x75
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r2 = 0xb1
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r3 = 0x09
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r4 = 0x90
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r5 = 0xb7
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r6 = 0x78
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r7 = 0x74
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r8 = 0x11
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r9 = 0x40
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r10 = 0x70
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r11 = 0x71
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r12 = 0x65
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r13 = 0x60
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r14 = 0x73
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r15 = 0x73
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-- round 1
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r0 = 0x2d
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r1 = 0x92
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r2 = 0x52
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r3 = 0x04
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r4 = 0xc8
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r5 = 0x79
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r6 = 0x14
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r7 = 0xba
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r8 = 0xb7
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r9 = 0xb6
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r10 = 0x10
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r11 = 0x41
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r12 = 0x61
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r13 = 0x60
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r14 = 0x65
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r15 = 0x61
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-- round 2
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r0 = 0x3e
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r1 = 0xc3
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r2 = 0xab
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r3 = 0xaa
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r4 = 0x4e
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r5 = 0xbe
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r6 = 0xa8
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r7 = 0x55
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r8 = 0xb9
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r9 = 0x30
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r10 = 0xb6
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r11 = 0xb7
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r12 = 0x01
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r13 = 0x40
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r14 = 0x61
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r15 = 0x61
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-- round 3
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r0 = 0xbf
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r1 = 0xc9
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r2 = 0x5f
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r3 = 0xfd
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r4 = 0x85
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r5 = 0xdd
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r6 = 0x7e
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r7 = 0x80
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r8 = 0xb1
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r9 = 0xb0
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r10 = 0xb8
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r11 = 0x31
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r12 = 0xa7
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r13 = 0xa6
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r14 = 0x01
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r15 = 0x41
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-- round 4
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r0 = 0x7f
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r1 = 0xc6
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r2 = 0x8d
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r3 = 0x5e
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r4 = 0x6a
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r5 = 0x66
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r6 = 0x15
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r7 = 0x68
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r8 = 0x81
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r9 = 0xa0
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r10 = 0xb0
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r11 = 0xb1
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r12 = 0xa9
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r13 = 0x20
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r14 = 0xa7
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r15 = 0xa7
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-- round 5
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r0 = 0x3f
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r1 = 0x69
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r2 = 0xec
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r3 = 0x2f
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r4 = 0x9f
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r5 = 0x99
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r6 = 0xa2
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r7 = 0x36
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r8 = 0xdd
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r9 = 0xdc
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r10 = 0x80
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r11 = 0xa1
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r12 = 0xa1
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r13 = 0xa0
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r14 = 0xa9
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r15 = 0x21
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-- round 6
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r0 = 0xbf
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r1 = 0x1e
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r2 = 0xd6
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r3 = 0x1f
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r4 = 0xef
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r5 = 0xce
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r6 = 0xf3
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r7 = 0x19
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r8 = 0x51
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r9 = 0x10
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r10 = 0xdc
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r11 = 0xdd
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r12 = 0x91
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r13 = 0xa0
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r14 = 0xa1
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r15 = 0xa1
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-- round 7
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r0 = 0x75
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r1 = 0xa5
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r2 = 0x6b
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r3 = 0xaf
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r4 = 0xdf
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r5 = 0x4f
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r6 = 0xd1
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r7 = 0x04
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r8 = 0xd1
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r9 = 0x50
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r10 = 0x10
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r11 = 0xdd
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r12 = 0xcd
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r13 = 0x90
|
|
r14 = 0xa1
|
|
r15 = 0xa1
|
|
-- round 8
|
|
r0 = 0x98
|
|
r1 = 0x7a
|
|
r2 = 0x1d
|
|
r3 = 0xff
|
|
r4 = 0x67
|
|
r5 = 0xaf
|
|
r6 = 0xc8
|
|
r7 = 0x2a
|
|
r8 = 0xd1
|
|
r9 = 0xd0
|
|
r10 = 0xd0
|
|
r11 = 0x51
|
|
r12 = 0x01
|
|
r13 = 0xcc
|
|
r14 = 0xcd
|
|
r15 = 0x91
|
|
-- round 9
|
|
r0 = 0x6e
|
|
r1 = 0x95
|
|
r2 = 0x26
|
|
r3 = 0xd5
|
|
r4 = 0xb1
|
|
r5 = 0x75
|
|
r6 = 0x46
|
|
r7 = 0x9d
|
|
r8 = 0xe9
|
|
r9 = 0xc2
|
|
r10 = 0xd0
|
|
r11 = 0xd1
|
|
r12 = 0xd1
|
|
r13 = 0x40
|
|
r14 = 0x01
|
|
r15 = 0xcd
|
|
-- round 10
|
|
r0 = 0x37
|
|
r1 = 0x62
|
|
r2 = 0x19
|
|
r3 = 0x4a
|
|
r4 = 0xf0
|
|
r5 = 0x3a
|
|
r6 = 0x03
|
|
r7 = 0x4e
|
|
r8 = 0x81
|
|
r9 = 0xe8
|
|
r10 = 0xe8
|
|
r11 = 0xc3
|
|
r12 = 0xc1
|
|
r13 = 0xd0
|
|
r14 = 0xd1
|
|
r15 = 0x41
|
|
-- round 11
|
|
r0 = 0x91
|
|
r1 = 0x11
|
|
r2 = 0x2c
|
|
r3 = 0xa5
|
|
r4 = 0xf2
|
|
r5 = 0x35
|
|
r6 = 0x89
|
|
r7 = 0x8d
|
|
r8 = 0x63
|
|
r9 = 0x20
|
|
r10 = 0x80
|
|
r11 = 0xe9
|
|
r12 = 0xe9
|
|
r13 = 0xc2
|
|
r14 = 0xc1
|
|
r15 = 0xd1
|
|
-- round 12
|
|
r0 = 0x62
|
|
r1 = 0x00
|
|
r2 = 0x3e
|
|
r3 = 0x78
|
|
r4 = 0xd9
|
|
r5 = 0x90
|
|
r6 = 0xc4
|
|
r7 = 0x64
|
|
r8 = 0x61
|
|
r9 = 0x62
|
|
r10 = 0x62
|
|
r11 = 0x21
|
|
r12 = 0x81
|
|
r13 = 0xe8
|
|
r14 = 0xe9
|
|
r15 = 0xc3
|
|
-- round 13
|
|
r0 = 0x11
|
|
r1 = 0x08
|
|
r2 = 0xbd
|
|
r3 = 0xbc
|
|
r4 = 0x4e
|
|
r5 = 0x40
|
|
r6 = 0x62
|
|
r7 = 0x1a
|
|
r8 = 0x71
|
|
r9 = 0x64
|
|
r10 = 0x60
|
|
r11 = 0x63
|
|
r12 = 0x73
|
|
r13 = 0x20
|
|
r14 = 0x81
|
|
r15 = 0xe9
|
|
-- round 14
|
|
r0 = 0x00
|
|
r1 = 0x24
|
|
r2 = 0x56
|
|
r3 = 0x7c
|
|
r4 = 0x27
|
|
r5 = 0x20
|
|
r6 = 0x39
|
|
r7 = 0x25
|
|
r8 = 0x71
|
|
r9 = 0x70
|
|
r10 = 0x64
|
|
r11 = 0x61
|
|
r12 = 0x73
|
|
r13 = 0x72
|
|
r14 = 0x21
|
|
r15 = 0x81
|
|
-- round 15
|
|
r0 = 0x41
|
|
r1 = 0x20
|
|
r2 = 0x52
|
|
r3 = 0x69
|
|
r4 = 0x76
|
|
r5 = 0x61
|
|
r6 = 0x6c
|
|
r7 = 0x20
|
|
r8 = 0x41
|
|
r9 = 0x70
|
|
r10 = 0x70
|
|
r11 = 0x65
|
|
r12 = 0x61
|
|
r13 = 0x72
|
|
r14 = 0x73
|
|
r15 = 0x21
|
|
pcl = 0x0022
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: mul
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
wx 019f
|
|
aei
|
|
(mul x y; echo ======== ${x} * ${y} ========; ar r16 = ${x}; ar r17 = ${y}; ar pc = 0; aes; echo r0; ar r0; echo r1; ar r1; echo r16; ar r16; echo r17; ar r17; echo sreg; ar sreg)
|
|
.(mul 42 13)
|
|
.(mul 0xff 0xff)
|
|
.(mul 0 42)
|
|
.(mul 0x10 0x80)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 42 * 13 ========
|
|
r0
|
|
r0 = 0x22
|
|
r1
|
|
r1 = 0x02
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x0d
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff * 0xff ========
|
|
r0
|
|
r0 = 0x01
|
|
r1
|
|
r1 = 0xfe
|
|
r16
|
|
r16 = 0xff
|
|
r17
|
|
r17 = 0xff
|
|
sreg
|
|
sreg = 0x01
|
|
======== 0 * 42 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x00
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x10 * 0x80 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x08
|
|
r16
|
|
r16 = 0x10
|
|
r17
|
|
r17 = 0x80
|
|
sreg
|
|
sreg = 0x00
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: muls
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
wx 0102
|
|
aei
|
|
(muls x y; echo ======== ${x} * ${y} ========; ar r16 = ${x}; ar r17 = ${y}; ar pc = 0; aes; echo r0; ar r0; echo r1; ar r1; echo r16; ar r16; echo r17; ar r17; echo sreg; ar sreg)
|
|
.(muls 42 13)
|
|
.(muls 0xff 0xff)
|
|
.(muls 0 42)
|
|
.(muls 0x10 0x80)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 42 * 13 ========
|
|
r0
|
|
r0 = 0x22
|
|
r1
|
|
r1 = 0x02
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x0d
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff * 0xff ========
|
|
r0
|
|
r0 = 0x01
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0xff
|
|
r17
|
|
r17 = 0xff
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0 * 42 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x00
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x10 * 0x80 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0xf8
|
|
r16
|
|
r16 = 0x10
|
|
r17
|
|
r17 = 0x80
|
|
sreg
|
|
sreg = 0x01
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: mulsu
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
wx 0103
|
|
aei
|
|
(mulsu x y; echo ======== ${x} * ${y} ========; ar r16 = ${x}; ar r17 = ${y}; ar pc = 0; aes; echo r0; ar r0; echo r1; ar r1; echo r16; ar r16; echo r17; ar r17; echo sreg; ar sreg)
|
|
.(mulsu 42 13)
|
|
.(mulsu 0xff 0xff)
|
|
.(mulsu 0 42)
|
|
.(mulsu 0x10 0x80)
|
|
.(mulsu 13 42)
|
|
.(mulsu 42 0)
|
|
.(mulsu 0x80 0x10)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 42 * 13 ========
|
|
r0
|
|
r0 = 0x22
|
|
r1
|
|
r1 = 0x02
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x0d
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff * 0xff ========
|
|
r0
|
|
r0 = 0x01
|
|
r1
|
|
r1 = 0xff
|
|
r16
|
|
r16 = 0xff
|
|
r17
|
|
r17 = 0xff
|
|
sreg
|
|
sreg = 0x01
|
|
======== 0 * 42 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x00
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x10 * 0x80 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x08
|
|
r16
|
|
r16 = 0x10
|
|
r17
|
|
r17 = 0x80
|
|
sreg
|
|
sreg = 0x00
|
|
======== 13 * 42 ========
|
|
r0
|
|
r0 = 0x22
|
|
r1
|
|
r1 = 0x02
|
|
r16
|
|
r16 = 0x0d
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x00
|
|
======== 42 * 0 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x00
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x80 * 0x10 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0xf8
|
|
r16
|
|
r16 = 0x80
|
|
r17
|
|
r17 = 0x10
|
|
sreg
|
|
sreg = 0x01
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: fmul
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
wx 0903
|
|
aei
|
|
(fmul x y; echo ======== ${x} * ${y} ========; ar r16 = ${x}; ar r17 = ${y}; ar pc = 0; aes; echo r0; ar r0; echo r1; ar r1; echo r16; ar r16; echo r17; ar r17; echo sreg; ar sreg)
|
|
.(fmul 42 13)
|
|
.(fmul 0xff 0xff)
|
|
.(fmul 0 42)
|
|
.(fmul 0x10 0x80)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 42 * 13 ========
|
|
r0
|
|
r0 = 0x44
|
|
r1
|
|
r1 = 0x04
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x0d
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff * 0xff ========
|
|
r0
|
|
r0 = 0x02
|
|
r1
|
|
r1 = 0xfc
|
|
r16
|
|
r16 = 0xff
|
|
r17
|
|
r17 = 0xff
|
|
sreg
|
|
sreg = 0x01
|
|
======== 0 * 42 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x00
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x10 * 0x80 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x10
|
|
r16
|
|
r16 = 0x10
|
|
r17
|
|
r17 = 0x80
|
|
sreg
|
|
sreg = 0x00
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: fmuls
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
wx 8103
|
|
aei
|
|
(fmuls x y; echo ======== ${x} * ${y} ========; ar r16 = ${x}; ar r17 = ${y}; ar pc = 0; aes; echo r0; ar r0; echo r1; ar r1; echo r16; ar r16; echo r17; ar r17; echo sreg; ar sreg)
|
|
.(fmuls 42 13)
|
|
.(fmuls 0xff 0xff)
|
|
.(fmuls 0 42)
|
|
.(fmuls 0x10 0x80)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 42 * 13 ========
|
|
r0
|
|
r0 = 0x44
|
|
r1
|
|
r1 = 0x04
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x0d
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff * 0xff ========
|
|
r0
|
|
r0 = 0x02
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0xff
|
|
r17
|
|
r17 = 0xff
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0 * 42 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x00
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x10 * 0x80 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0xf0
|
|
r16
|
|
r16 = 0x10
|
|
r17
|
|
r17 = 0x80
|
|
sreg
|
|
sreg = 0x01
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: fmulsu
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
wx 8903
|
|
aei
|
|
(fmulsu x y; echo ======== ${x} * ${y} ========; ar r16 = ${x}; ar r17 = ${y}; ar pc = 0; aes; echo r0; ar r0; echo r1; ar r1; echo r16; ar r16; echo r17; ar r17; echo sreg; ar sreg)
|
|
.(fmulsu 42 13)
|
|
.(fmulsu 0xff 0xff)
|
|
.(fmulsu 0 42)
|
|
.(fmulsu 0x10 0x80)
|
|
.(fmulsu 13 42)
|
|
.(fmulsu 42 0)
|
|
.(fmulsu 0x80 0x10)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 42 * 13 ========
|
|
r0
|
|
r0 = 0x44
|
|
r1
|
|
r1 = 0x04
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x0d
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff * 0xff ========
|
|
r0
|
|
r0 = 0x02
|
|
r1
|
|
r1 = 0xfe
|
|
r16
|
|
r16 = 0xff
|
|
r17
|
|
r17 = 0xff
|
|
sreg
|
|
sreg = 0x01
|
|
======== 0 * 42 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x00
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x10 * 0x80 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x10
|
|
r16
|
|
r16 = 0x10
|
|
r17
|
|
r17 = 0x80
|
|
sreg
|
|
sreg = 0x00
|
|
======== 13 * 42 ========
|
|
r0
|
|
r0 = 0x44
|
|
r1
|
|
r1 = 0x04
|
|
r16
|
|
r16 = 0x0d
|
|
r17
|
|
r17 = 0x2a
|
|
sreg
|
|
sreg = 0x00
|
|
======== 42 * 0 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0x00
|
|
r16
|
|
r16 = 0x2a
|
|
r17
|
|
r17 = 0x00
|
|
sreg
|
|
sreg = 0x02
|
|
======== 0x80 * 0x10 ========
|
|
r0
|
|
r0 = 0x00
|
|
r1
|
|
r1 = 0xf0
|
|
r16
|
|
r16 = 0x80
|
|
r17
|
|
r17 = 0x10
|
|
sreg
|
|
sreg = 0x01
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: adiw
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
aei
|
|
(adiw h l x; echo ======== ${h}:${l} + ${x} ========; wa "adiw r27:r26, ${x}"; pi 1; ar r27 = ${h}; ar r26 = ${l}; ar pc = 0; aes; echo r26; ar r26; echo r27; ar r27; echo sreg; ar sreg)
|
|
.(adiw 0xca 0xfe 0x3f)
|
|
.(adiw 0x0a 0xfe 0x3f)
|
|
.(adiw 0xff 0xff 0x01)
|
|
.(adiw 0x77 0x7e 0x03)
|
|
.(adiw 0x7f 0xfe 0x03)
|
|
.(adiw 0x80 0x00 0x01)
|
|
.(adiw 0x00 0x00 0x00)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 0xca:0xfe + 0x3f ========
|
|
adiw r27:r26, 0x3f
|
|
r26
|
|
r26 = 0x3d
|
|
r27
|
|
r27 = 0xcb
|
|
sreg
|
|
sreg = 0x14
|
|
======== 0x0a:0xfe + 0x3f ========
|
|
adiw r27:r26, 0x3f
|
|
r26
|
|
r26 = 0x3d
|
|
r27
|
|
r27 = 0x0b
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0xff:0xff + 0x01 ========
|
|
adiw r27:r26, 0x01
|
|
r26
|
|
r26 = 0x00
|
|
r27
|
|
r27 = 0x00
|
|
sreg
|
|
sreg = 0x03
|
|
======== 0x77:0x7e + 0x03 ========
|
|
adiw r27:r26, 0x03
|
|
r26
|
|
r26 = 0x81
|
|
r27
|
|
r27 = 0x77
|
|
sreg
|
|
sreg = 0x00
|
|
======== 0x7f:0xfe + 0x03 ========
|
|
adiw r27:r26, 0x03
|
|
r26
|
|
r26 = 0x01
|
|
r27
|
|
r27 = 0x80
|
|
sreg
|
|
sreg = 0x0c
|
|
======== 0x80:0x00 + 0x01 ========
|
|
adiw r27:r26, 0x01
|
|
r26
|
|
r26 = 0x01
|
|
r27
|
|
r27 = 0x80
|
|
sreg
|
|
sreg = 0x14
|
|
======== 0x00:0x00 + 0x00 ========
|
|
adiw r27:r26, 0x00
|
|
r26
|
|
r26 = 0x00
|
|
r27
|
|
r27 = 0x00
|
|
sreg
|
|
sreg = 0x02
|
|
EOF
|
|
RUN
|
|
|
|
NAME=AVR: sbiw
|
|
FILE=malloc://1024
|
|
CMDS=<<EOF
|
|
e asm.arch=avr
|
|
e cfg.bigendian=false
|
|
aei
|
|
(sbiw h l x; echo ======== ${h}:${l} - ${x} ========; wa "sbiw r27:r26, ${x}"; pi 1; ar r27 = ${h}; ar r26 = ${l}; ar pc = 0; aes; echo r26; ar r26; echo r27; ar r27; echo sreg; ar sreg)
|
|
.(sbiw 0xca 0x21 0x3f)
|
|
.(sbiw 0x00 0x10 0x3f)
|
|
.(sbiw 0x80 0x00 0x01)
|
|
.(sbiw 0x80 0x05 0x01)
|
|
.(sbiw 0x00 0x02 0x03)
|
|
.(sbiw 0x00 0x12 0x12)
|
|
EOF
|
|
EXPECT=<<EOF
|
|
======== 0xca:0x21 - 0x3f ========
|
|
sbiw r27:r26, 0x3f
|
|
r26
|
|
r26 = 0xe2
|
|
r27
|
|
r27 = 0xc9
|
|
sreg
|
|
sreg = 0x14
|
|
======== 0x00:0x10 - 0x3f ========
|
|
sbiw r27:r26, 0x3f
|
|
r26
|
|
r26 = 0xd1
|
|
r27
|
|
r27 = 0xff
|
|
sreg
|
|
sreg = 0x15
|
|
======== 0x80:0x00 - 0x01 ========
|
|
sbiw r27:r26, 0x01
|
|
r26
|
|
r26 = 0xff
|
|
r27
|
|
r27 = 0x7f
|
|
sreg
|
|
sreg = 0x18
|
|
======== 0x80:0x05 - 0x01 ========
|
|
sbiw r27:r26, 0x01
|
|
r26
|
|
r26 = 0x04
|
|
r27
|
|
r27 = 0x80
|
|
sreg
|
|
sreg = 0x14
|
|
======== 0x00:0x02 - 0x03 ========
|
|
sbiw r27:r26, 0x03
|
|
r26
|
|
r26 = 0xff
|
|
r27
|
|
r27 = 0xff
|
|
sreg
|
|
sreg = 0x15
|
|
======== 0x00:0x12 - 0x12 ========
|
|
sbiw r27:r26, 0x12
|
|
r26
|
|
r26 = 0x00
|
|
r27
|
|
r27 = 0x00
|
|
sreg
|
|
sreg = 0x02
|
|
EOF
|
|
RUN
|