diff --git a/src/ciphers/aes/aes_desc.c b/src/ciphers/aes/aes_desc.c
index 2ff913e8..d4f3aeed 100644
--- a/src/ciphers/aes/aes_desc.c
+++ b/src/ciphers/aes/aes_desc.c
@@ -48,36 +48,42 @@ const struct ltc_cipher_descriptor aes_enc_desc =
 
 #endif
 
-/* Code partially borrowed from https://software.intel.com/content/www/us/en/develop/articles/intel-sha-extensions.html */
 #if defined(LTC_AES_NI)
+
+#if !defined (LTC_S_X86_CPUID)
+#define LTC_S_X86_CPUID
+static LTC_INLINE void s_x86_cpuid(int* regs, int leaf)
+{
+#if defined _MSC_VER
+   __cpuid(regs, leaf);
+#else
+   int a, b, c, d;
+
+   a = leaf;
+   b = c = d = 0;
+   asm volatile ("cpuid"
+       :"=a"(a), "=b"(b), "=c"(c), "=d"(d)
+       :"a"(a), "c"(c)
+   );
+   regs[0] = a;
+   regs[1] = b;
+   regs[2] = c;
+   regs[3] = d;
+#endif
+}
+#endif /* LTC_S_X86_CPUID */
+
 static LTC_INLINE int s_aesni_is_supported(void)
 {
    static int initialized = 0, is_supported = 0;
 
    if (initialized == 0) {
-      int a, b, c, d;
-
       /* Look for CPUID.1.0.ECX[19] (SSE4.1) and CPUID.1.0.ECX[25] (AES-NI)
        * EAX = 1, ECX = 0
        */
-      a = 1;
-      c = 0;
-
-#if defined(_MSC_VER) && !defined(__clang__)
-      int arr[4];
-      __cpuidex(arr, a, c);
-      a = arr[0];
-      b = arr[1];
-      c = arr[2];
-      d = arr[3];
-#else
-      __asm__ volatile ("cpuid"
-           :"=a"(a), "=b"(b), "=c"(c), "=d"(d)
-           :"a"(a), "c"(c)
-          );
-#endif
-
-      is_supported = ((c >> 19) & 1) && ((c >> 25) & 1);
+      int regs[4];
+      s_x86_cpuid(regs, 1);
+      is_supported = ((regs[2] >> 19) & 1) && ((regs[2] >> 25) & 1);
       initialized = 1;
    }
 
diff --git a/src/encauth/gcm/gcm_gf_mult.c b/src/encauth/gcm/gcm_gf_mult.c
index b19259e4..39ce9de1 100644
--- a/src/encauth/gcm/gcm_gf_mult.c
+++ b/src/encauth/gcm/gcm_gf_mult.c
@@ -21,27 +21,38 @@
 #include <smmintrin.h>
 #include <emmintrin.h>
 
+#if !defined (LTC_S_X86_CPUID)
+#define LTC_S_X86_CPUID
+static LTC_INLINE void s_x86_cpuid(int* regs, int leaf)
+{
+#if defined _MSC_VER
+   __cpuid(regs, leaf);
+#else
+   int a, b, c, d;
+
+   a = leaf;
+   b = c = d = 0;
+   asm volatile ("cpuid"
+       :"=a"(a), "=b"(b), "=c"(c), "=d"(d)
+       :"a"(a), "c"(c)
+   );
+   regs[0] = a;
+   regs[1] = b;
+   regs[2] = c;
+   regs[3] = d;
+#endif
+}
+#endif /* LTC_S_X86_CPUID */
+
 static LTC_INLINE int s_pclmul_is_supported(void)
 {
    static int initialized = 0, is_supported = 0;
 
    if (initialized == 0) {
-      /* Test CPUID.1.0.ECX[1]
-       * EAX = 1, ECX = 0 */
-#if defined(_MSC_VER)
-      int cpuInfo[4];
-      __cpuid(cpuInfo, 1);
-      is_supported = ((cpuInfo[2] >> 1) & 1);
-#else
-      int a = 1 , b, c = 0, d;
-
-      asm volatile ("cpuid"
-           :"=a"(a), "=b"(b), "=c"(c), "=d"(d)
-           :"a"(a), "c"(c)
-          );
-
-      is_supported = ((c >> 1) & 1);
-#endif
+      int regs[4];
+      s_x86_cpuid(regs, 1);
+      /* Test CPUID.1.0.ECX[1] (PCLMUL) and CPUID.1.0.ECX[9] (SSSE3) */
+      is_supported = ((regs[2] >> 1) & 1) && ((regs[2] >> 9) & 1);
       initialized = 1;
    }