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https://github.com/brazilofmux/tinymux
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6f60f6b934
Decoder (dbt_decoder.h) and interpreter (dbt_interp.cpp) for the RV64IMD instruction set — the execution foundation for the JIT compiler. D-only (no single-precision F); ECALL dispatches through a caller-provided callback for future EngineAPI integration. Standalone test harness (dbt_test.cpp): 20 tests, 40 assertions covering integer, W-suffix, shift, multiply, branch, load/store, FP arithmetic, FP conversion, and loop execution. Design doc updated: RV64 decision locked, ~/riscv as reference only, file locations in mux/modules/engine/. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
198 lines
6 KiB
C++
198 lines
6 KiB
C++
/*! \file dbt_decoder.h
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* \brief RV64IMD instruction decoder.
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*
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* Inline decoder for the RISC-V RV64IMD instruction set:
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* I — Base integer (64-bit)
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* M — Multiply/divide
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* D — Double-precision floating point
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*
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* Reference: ~/riscv/dbt/decoder.h (RV32IMFD version).
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* Key difference: 64-bit register width, W-suffix instructions,
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* 6-bit shift amounts, LD/SD/LWU, FCVT.L.D/FCVT.D.L, FMV.X.D/FMV.D.X.
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*/
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#ifndef DBT_DECODER_H
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#define DBT_DECODER_H
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#include <cstdint>
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// Opcodes (bits [6:0])
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//
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constexpr uint8_t OP_LUI = 0x37;
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constexpr uint8_t OP_AUIPC = 0x17;
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constexpr uint8_t OP_JAL = 0x6F;
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constexpr uint8_t OP_JALR = 0x67;
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constexpr uint8_t OP_BRANCH = 0x63;
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constexpr uint8_t OP_LOAD = 0x03;
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constexpr uint8_t OP_STORE = 0x23;
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constexpr uint8_t OP_IMM = 0x13;
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constexpr uint8_t OP_REG = 0x33;
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constexpr uint8_t OP_IMM32 = 0x1B; // RV64: ADDIW, SLLIW, SRLIW, SRAIW
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constexpr uint8_t OP_REG32 = 0x3B; // RV64: ADDW, SUBW, SLLW, SRLW, SRAW, M*W
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constexpr uint8_t OP_FENCE = 0x0F;
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constexpr uint8_t OP_SYSTEM = 0x73;
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// RV64D opcodes
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//
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constexpr uint8_t OP_FP_LOAD = 0x07; // FLD (funct3=3)
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constexpr uint8_t OP_FP_STORE = 0x27; // FSD (funct3=3)
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constexpr uint8_t OP_FMADD = 0x43;
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constexpr uint8_t OP_FMSUB = 0x47;
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constexpr uint8_t OP_FNMSUB = 0x4B;
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constexpr uint8_t OP_FNMADD = 0x4F;
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constexpr uint8_t OP_FP = 0x53; // arithmetic, compare, convert, move
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// Branch funct3
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//
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constexpr uint8_t BR_BEQ = 0;
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constexpr uint8_t BR_BNE = 1;
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constexpr uint8_t BR_BLT = 4;
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constexpr uint8_t BR_BGE = 5;
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constexpr uint8_t BR_BLTU = 6;
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constexpr uint8_t BR_BGEU = 7;
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// Load funct3
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//
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constexpr uint8_t LD_LB = 0;
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constexpr uint8_t LD_LH = 1;
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constexpr uint8_t LD_LW = 2;
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constexpr uint8_t LD_LD = 3; // RV64: load doubleword
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constexpr uint8_t LD_LBU = 4;
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constexpr uint8_t LD_LHU = 5;
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constexpr uint8_t LD_LWU = 6; // RV64: load word unsigned
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// Store funct3
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//
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constexpr uint8_t ST_SB = 0;
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constexpr uint8_t ST_SH = 1;
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constexpr uint8_t ST_SW = 2;
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constexpr uint8_t ST_SD = 3; // RV64: store doubleword
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// ALU immediate funct3
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//
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constexpr uint8_t ALU_ADDI = 0;
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constexpr uint8_t ALU_SLTI = 2;
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constexpr uint8_t ALU_SLTIU = 3;
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constexpr uint8_t ALU_XORI = 4;
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constexpr uint8_t ALU_ORI = 6;
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constexpr uint8_t ALU_ANDI = 7;
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constexpr uint8_t ALU_SLLI = 1;
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constexpr uint8_t ALU_SRLI = 5; // also SRAI when funct6=0x10
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// ALU register funct3 (+ funct7 for disambiguation)
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//
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constexpr uint8_t ALU_ADD = 0; // SUB when funct7=0x20, MUL when funct7=0x01
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constexpr uint8_t ALU_SLL = 1; // MULH when funct7=0x01
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constexpr uint8_t ALU_SLT = 2; // MULHSU when funct7=0x01
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constexpr uint8_t ALU_SLTU = 3; // MULHU when funct7=0x01
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constexpr uint8_t ALU_XOR = 4; // DIV when funct7=0x01
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constexpr uint8_t ALU_SRL = 5; // SRA when funct7=0x20, DIVU when funct7=0x01
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constexpr uint8_t ALU_OR = 6; // REM when funct7=0x01
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constexpr uint8_t ALU_AND = 7; // REMU when funct7=0x01
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// FP funct5 (funct7 >> 2)
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//
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constexpr uint8_t FP_FADD = 0x00;
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constexpr uint8_t FP_FSUB = 0x01;
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constexpr uint8_t FP_FMUL = 0x02;
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constexpr uint8_t FP_FDIV = 0x03;
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constexpr uint8_t FP_FSQRT = 0x0B;
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constexpr uint8_t FP_FSGNJ = 0x04;
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constexpr uint8_t FP_FMINMAX = 0x05;
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constexpr uint8_t FP_FCMP = 0x14;
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constexpr uint8_t FP_FCVTW = 0x18; // FCVT.W.D, FCVT.WU.D, FCVT.L.D, FCVT.LU.D
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constexpr uint8_t FP_FCVTDW = 0x1A; // FCVT.D.W, FCVT.D.WU, FCVT.D.L, FCVT.D.LU
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constexpr uint8_t FP_FCLASS = 0x1C; // FCLASS.D, FMV.X.D
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constexpr uint8_t FP_FMVDX = 0x1E; // FMV.D.X
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// FP format (funct7 & 3): 1 = double
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//
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constexpr uint8_t FP_FMT_D = 1;
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// Decoded instruction
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//
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struct rv64_insn_t {
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uint8_t opcode; // bits [6:0]
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uint8_t rd; // destination register
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uint8_t rs1; // source register 1
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uint8_t rs2; // source register 2
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uint8_t rs3; // source register 3 (R4-type: FMA) = funct7[6:2]
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uint8_t funct3; // function code (bits [14:12])
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uint8_t funct7; // function code (bits [31:25])
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int32_t imm; // decoded immediate (sign-extended to 32-bit;
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// widen to int64_t when applied to 64-bit regs)
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};
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// Decode a 32-bit RV64IMD instruction word.
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// Returns the instruction length (always 4).
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//
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static inline int rv64_decode(uint32_t word, rv64_insn_t *insn) {
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insn->opcode = word & 0x7F;
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insn->rd = (word >> 7) & 0x1F;
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insn->funct3 = (word >> 12) & 0x07;
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insn->rs1 = (word >> 15) & 0x1F;
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insn->rs2 = (word >> 20) & 0x1F;
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insn->rs3 = (word >> 27) & 0x1F;
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insn->funct7 = (word >> 25) & 0x7F;
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// Decode immediate based on instruction format.
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//
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switch (insn->opcode) {
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case OP_LUI:
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case OP_AUIPC:
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// U-type: imm[31:12]
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//
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insn->imm = static_cast<int32_t>(word & 0xFFFFF000);
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break;
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case OP_JAL:
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// J-type: imm[20|10:1|11|19:12]
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//
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insn->imm = static_cast<int32_t>(
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((word >> 31) ? 0xFFF00000 : 0) |
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(word & 0x000FF000) |
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((word >> 9) & 0x00000800) |
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((word >> 20) & 0x000007FE)
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);
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break;
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case OP_BRANCH:
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// B-type: imm[12|10:5|4:1|11]
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//
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insn->imm = static_cast<int32_t>(
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((word >> 31) ? 0xFFFFF000 : 0) |
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((word << 4) & 0x00000800) |
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((word >> 20) & 0x000007E0) |
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((word >> 7) & 0x0000001E)
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);
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break;
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case OP_STORE:
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case OP_FP_STORE:
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// S-type: imm[11:5|4:0]
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//
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insn->imm = static_cast<int32_t>(
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((word >> 31) ? 0xFFFFF000 : 0) |
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((word >> 20) & 0xFE0) |
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((word >> 7) & 0x1F)
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);
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break;
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case OP_FMADD: case OP_FMSUB: case OP_FNMSUB: case OP_FNMADD:
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case OP_FP:
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// R/R4-type: no immediate
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//
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insn->imm = 0;
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break;
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default:
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// I-type: imm[11:0] (covers LOAD, FP_LOAD, IMM, IMM32, JALR, SYSTEM)
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//
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insn->imm = static_cast<int32_t>(word) >> 20;
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break;
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}
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return 4;
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}
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#endif // DBT_DECODER_H
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