Polled NS16550A receive primitives. uart_rx_byte spins on LSR.DR
(bit 0) until a byte arrives, then reads RBR. uart_rx_available
returns 1/0 of the same DR bit, non-blocking.
Both stay as the polled fall-back even after uart_isr lands; the
IRQ-driven ring-buffer path will become the production hot path
on the C6, the polled forms keep working on qemu-virt where qemu
does not model the PLIC for our IRQ wiring.
Loop forwards each byte to uart_tx_byte. ra/s0/s1 saved in a 16-byte
frame; s0 holds the buffer cursor and s1 the remaining count, both
across the inner call. Empty-buffer case exits at the loop head with
one branch.
Static checks: aligned prologue, sw of ra+s0+s1, lbu a0,0(s0) +
addi s0,1 + addi s1,-1 in the loop, beqz s1 head exit, restored
epilogue + ret.
Polled NS16550A TX: spin on LSR.THRE (offset 5, bit 5 = 0x20), then
write a0 to THR (offset 0). Leaf, no spill, single ret.
Pulls UART0_BASE / UART0_LSR_THRE from src/include/regs.S so the
qemu-virt and (future) C6 builds share the same source. Static
checks confirm: lui t0, 0x10000 (UART0_BASE), lbu/andi/beqz poll
loop, sb a0,0(t0), and ABI compliance (no s* writes, a0 not
clobbered).
Single `ret` on qemu-virt — qemu's NS16550A model self-initialises.
Body is target-conditional via .ifdef; the C6 arm has a .error so a
build for that target fails loudly until the real register sequence
(peripheral clock, divisor, 8N1, RX IRQ enable) is written.
Static checks: function exists, body is exactly one ret, no
callee-saved writes.
