mirror of
https://github.com/ratspeak/C6-Reticulum-ASM
synced 2026-08-12 18:07:18 -04:00
c338223429
- TARGET_C6 register block + linker script (load into 0x4086c410, the same upper-half HP_SRAM bootloader region esp-idf uses; loading to 0x40800000 collides with ROM flash-loader scratch and silently aborts the segment copy with "Calculated 0xef stored 0xff"). - USB-Serial/JTAG as the early-bring-up uart_* backend (ADR-0010 refines ADR-0004; the C6's mask ROM provides the CDC-ACM stack so we just push bytes to a 1-byte FIFO with WR_DONE flush). - TARGET_C6 paths in clock_init / clock_now_ticks / clock_delay_us / uart_init / uart_tx_byte / uart_rx_byte / uart_rx_available. - clock_init disables TG0 / LP / Super watchdogs (key 0x50D83AA1) so the polling main loop survives. - Makefile image/flash/monitor targets default DIO @ 40 MHz (QIO @ 80 MHz hangs on the Feather's factory flash configuration). - Hardware demo passed end-to-end: KISS-framed Reticulum packet over USB-C produces kiss.rx_frame + packet.parsed; short payload produces rejected; SHA-256 KAT trigger emits FIPS 180-4 §B.1 vector ba7816bf...20015ad. - qemu-virt suite still 124/124 green.
103 lines
4.2 KiB
Text
103 lines
4.2 KiB
Text
/* Linker script for the Adafruit ESP32-C6 Feather (RV32IMAC).
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*
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* Memory layout (per ESP32-C6 TRM r1.4 Ch 4 "System and Memory" + the
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* esp-idf bootloader linker script's documented ROM scratch map):
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* 0x4080_0000 - 0x4086_C410 HP_SRAM low half — used by the mask-ROM
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* during SPI flash boot (download-mode
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* shared buffers, flash-read scratch,
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* segment-loader workspace). Loading our
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* image here corrupts the ROM's working
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* memory while the load is in progress —
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* empirically this triggers a checksum
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* failure with calculated == seed (0xef),
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* meaning the XOR walk over our segment
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* data never completes.
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* 0x4086_C410 - 0x4087_C610 HP_SRAM upper half — esp-idf's own
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* second-stage bootloader lives here
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* (bootloader.ld:bootloader_iram_seg_start
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* etc.). Safe for OUR second-stage image
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* because the ROM has finished its boot
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* work by the time we land here.
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* 0x4087_C610 - 0x4087_E610 ROM PRO-CPU stack (in use throughout)
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* 0x4087_E610 - 0x4088_0000 ROM .bss/.data (in use throughout)
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* 0x6000_0000 + High-peripheral block (UART, USJ, SYSTIMER…)
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* Flash (XIP) 0x4200_0000 — not used this milestone;
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* everything lives in HP_SRAM.
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*
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* We load the entire image into the upper HP_SRAM bootloader region
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* starting at 0x4086_C410 — same address esp-idf's own bootloader uses,
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* which is the most thoroughly-tested ROM hand-off path. Total budget
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* is 0x4087_C610 - 0x4086_C410 = 64 KiB for .text + .rodata + .data +
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* .bss + .stack; a 16 KiB stack leaves 48 KiB for code/data, which
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* accommodates the current ~30 KiB image with room to grow before the
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* crypto KAT bridge starts pushing the .text size.
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*
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* LMA == VMA throughout (the ROM loader copies each PT_LOAD segment
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* into HP_SRAM at the documented load address); _init_data's copy loop
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* still runs but every iteration is a no-op, matching the qemu-virt
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* path. Stack grows down from __stack_top (top of the reserved 16 KiB
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* region); tools/check_stack.py asserts worst-case depth fits.
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*/
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OUTPUT_ARCH("riscv")
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OUTPUT_FORMAT("elf32-littleriscv")
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ENTRY(_reset)
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/* 0x4086_C410 + 64 KiB = 0x4087_C410 — keeps us 0x200 bytes below the
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* ROM stack at 0x4087_C610. */
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MEMORY
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{
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HPSRAM (rwx) : ORIGIN = 0x4086C410, LENGTH = 64K
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}
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SECTIONS
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{
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. = ORIGIN(HPSRAM);
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.text : ALIGN(4) {
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__text_start = .;
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KEEP(*(.text._reset)) /* reset vector first */
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*(.text*)
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__text_end = .;
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} > HPSRAM
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.rodata : ALIGN(4) {
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*(.rodata*)
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} > HPSRAM
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.data : ALIGN(4) {
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__data_start = .;
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*(.data*)
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__data_end = .;
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} > HPSRAM
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/* On the C6 the ROM loader installs each segment at its LMA in SRAM,
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so LMA == VMA and _init_data's copy loop is a per-word no-op (same
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as qemu-virt). The contract is preserved for the day .data lives
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in flash and needs an actual XIP-to-SRAM copy. */
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__data_load_start = LOADADDR(.data);
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/* GP convention: gp points 0x800 above the start of small data so
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gp-relative loads can reach ±2 KiB on either side. We have no .sdata
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yet, so anchor it at the .data start; consumed by `la gp,
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__global_pointer$` in _reset. */
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PROVIDE(__global_pointer$ = __data_start + 0x800);
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.bss : ALIGN(4) {
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__bss_start = .;
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end = .;
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} > HPSRAM
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/* Stack at the top of the loaded image, grows down. STACK_SIZE comes
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from src/include/config.S (16 KiB). We intentionally place .stack
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right after .bss rather than at HPSRAM end so unused HP_SRAM stays
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free for future BSS growth without re-flashing the linker script. */
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. = ALIGN(16);
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__stack_bottom = .;
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. += 0x4000;
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__stack_top = .;
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__image_end = .;
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}
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