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drivers: SKY72310: apply clang-format

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Signed-off-by: Silvano Seva <silseva@fastwebnet.it>
This commit is contained in:
Silvano Seva 2026-04-26 08:46:33 +02:00
parent c28110a5a7
commit dc82283bd0
3 changed files with 17 additions and 17 deletions
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21
platform/drivers/baseband/SKY72310.c
View file

@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: Copyright 2020-2026 OpenRTX Contributors
*
*
* SPDX-License-Identifier: GPL-3.0-or-later
*/
@ -28,7 +28,6 @@ static inline void writeReg(const struct sky73210 *dev, const uint16_t value)
spi_release(dev->spi);
}
void SKY73210_init(const struct sky73210 *dev)
{
gpioPin_setMode(&dev->cs, OUTPUT);
@ -42,7 +41,7 @@ void SKY73210_init(const struct sky73210 *dev)
void SKY73210_terminate(const struct sky73210 *dev)
{
(void) dev;
(void)dev;
}
void SKY73210_setFrequency(const struct sky73210 *dev, const uint32_t freq,
@ -52,8 +51,8 @@ void SKY73210_setFrequency(const struct sky73210 *dev, const uint32_t freq,
if (clkDiv > 32)
clkDiv = 32;
float clk = ((float) dev->refClk) / ((float) clkDiv);
float K = ((float) freq) / clk;
float clk = ((float)dev->refClk) / ((float)clkDiv);
float K = ((float)freq) / clk;
float Ndiv = floor(K) - 32.0;
float Ndnd = round(262144 * (K - Ndiv - 32.0));
@ -62,15 +61,15 @@ void SKY73210_setFrequency(const struct sky73210 *dev, const uint32_t freq,
* When converting from float to uint32_t we have to cast the value to a
* signed 18-bit one and increment the divider by one if dividend is negative.
*/
uint32_t dnd = ((uint32_t) Ndnd) & 0x03FFFF;
if(dnd & 0x20000)
uint32_t dnd = ((uint32_t)Ndnd) & 0x03FFFF;
if (dnd & 0x20000)
Ndiv += 1;
uint16_t dndMsb = dnd >> 8;
uint16_t dndLsb = dnd & 0x00FF;
writeReg(dev, (uint16_t) Ndiv); // Divider register
writeReg(dev, 0x2000 | dndLsb); // Dividend LSB register
writeReg(dev, 0x1000 | dndMsb); // Dividend MSB register
writeReg(dev, 0x5000 | ((uint16_t)clkDiv - 1)); // Reference clock divider
writeReg(dev, (uint16_t)Ndiv); // Divider register
writeReg(dev, 0x2000 | dndLsb); // Dividend LSB register
writeReg(dev, 0x1000 | dndMsb); // Dividend MSB register
writeReg(dev, 0x5000 | ((uint16_t)clkDiv - 1)); // Reference clock divider
}

11
platform/drivers/baseband/SKY72310.h
View file

@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: Copyright 2020-2026 OpenRTX Contributors
*
*
* SPDX-License-Identifier: GPL-3.0-or-later
*/
@ -19,11 +19,10 @@ extern "C" {
/**
* SKY73210 device data.
*/
struct sky73210
{
const struct spiDevice *spi; ///< SPI bus device driver
const struct gpioPin cs; ///< Chip select gpio
const uint32_t refClk; ///< Reference clock frequency, in Hz
struct sky73210 {
const struct spiDevice *spi; ///< SPI bus device driver
const struct gpioPin cs; ///< Chip select gpio
const uint32_t refClk; ///< Reference clock frequency, in Hz
};
/**

2
scripts/clang_format.sh
View file

@ -86,6 +86,8 @@ platform/drivers/audio/file_source.c
platform/drivers/audio/MAX9814.h
platform/drivers/baseband/MCP4551.h
platform/drivers/baseband/SA8x8.h
platform/drivers/baseband/SKY72310.c
platform/drivers/baseband/SKY72310.h
platform/drivers/chSelector/chSelector.h
platform/drivers/display/SH110x_Mod17.h
platform/drivers/display/SSD1306_Mod17.h