sovereign-rf/hackrf
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

si5351c: API: distinguish between PLL IDs and PLL masks.

Browse source 
We're going to want a type that just identifies one PLL, and is
consistent with how the PLLs are numbered in register settings.

The current si5351c_pll_t is a bitmask which allows referring to
both PLLs. Let's make that a different type, and name things more
clearly when using it.
This commit is contained in:
Martin Ling 2026-05-03 09:19:45 +01:00
parent d00dae3835
commit 098b9dd9f2
3 changed files with 20 additions and 15 deletions
Download patch file Download diff file Expand all files Collapse all files

4
firmware/common/clock_gen.c
View file

@ -113,7 +113,7 @@ void clock_gen_init(void)
si5351c_configure_clock_control(&si5351c);
si5351c_change_input(&si5351c, SI5351C_INPUT_XTAL);
// soft reset
si5351c_reset_pll(&si5351c, SI5351C_PLL_BOTH);
si5351c_reset_plls(&si5351c, SI5351C_PLL_MASK_BOTH);
si5351c_enable_clock_outputs(&si5351c);
}
@ -412,7 +412,7 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
}
/* Reset PLL to synchronize output clock phase. */
si5351c_reset_pll(&si5351c, SI5351C_PLL_A);
si5351c_reset_plls(&si5351c, SI5351C_PLL_MASK_A);
}
#endif

16
firmware/common/si5351c.c
View file

@ -91,7 +91,7 @@ void si5351c_disable_all_outputs(si5351c_driver_t* const drv)
}
/* Disable all CLKx outputs using selected PLL. */
void si5351c_disable_pll_outputs(si5351c_driver_t* const drv, si5351c_pll_t pll)
void si5351c_disable_pll_outputs(si5351c_driver_t* const drv, si5351c_pll_mask_t mask)
{
/*
* Bitmask defines outputs using PLL B. Other outputs are assumed to
@ -102,10 +102,10 @@ void si5351c_disable_pll_outputs(si5351c_driver_t* const drv, si5351c_pll_t pll)
pllb_outputs = 0x30;
}
if (pll & SI5351C_PLL_A) {
if (mask & SI5351C_PLL_MASK_A) {
outputs_disabled |= ~pllb_outputs;
}
if (pll & SI5351C_PLL_B) {
if (mask & SI5351C_PLL_MASK_B) {
outputs_disabled |= pllb_outputs;
}
uint8_t data[] = {3, outputs_disabled};
@ -189,18 +189,18 @@ void si5351c_configure_pll_multisynth(
si5351c_write(drv, data, sizeof(data));
}
void si5351c_reset_pll(si5351c_driver_t* const drv, si5351c_pll_t pll)
void si5351c_reset_plls(si5351c_driver_t* const drv, si5351c_pll_mask_t mask)
{
uint8_t value = 0;
if (pll & SI5351C_PLL_A) {
if (mask & SI5351C_PLL_MASK_A) {
value |= 0x20;
}
if (pll & SI5351C_PLL_B) {
if (mask & SI5351C_PLL_MASK_B) {
value |= 0x80;
}
si5351c_disable_pll_outputs(drv, pll);
si5351c_disable_pll_outputs(drv, mask);
uint8_t data[] = {177, value};
si5351c_write(drv, data, sizeof(data));
delay_us_at_mhz(2000, 204);
@ -442,7 +442,7 @@ void si5351c_change_input(si5351c_driver_t* const drv, si5351c_input_t input)
si5351c_configure_pll_multisynth(drv, input);
active_input = input;
input_initialized = true;
si5351c_reset_pll(drv, SI5351C_PLL_BOTH);
si5351c_reset_plls(drv, SI5351C_PLL_MASK_BOTH);
}
bool si5351c_clkin_signal_valid(si5351c_driver_t* const drv)

15
firmware/common/si5351c.h
View file

@ -57,12 +57,17 @@ extern "C" {
#define SI5351C_REVID 0x03
typedef enum {
SI5351C_PLL_A = 1,
SI5351C_PLL_B = 2,
SI5351C_PLL_BOTH = 3,
SI5351C_PLL_A = 0,
SI5351C_PLL_B = 1,
} si5351c_pll_t;
#define SI5351C_CLK_PLL_SRC(x) ((x & SI5351C_PLL_B) << 4)
#define SI5351C_CLK_PLL_SRC(x) ((x & SI5351C_PLL_B) << 5)
typedef enum {
SI5351C_PLL_MASK_A = 1,
SI5351C_PLL_MASK_B = 2,
SI5351C_PLL_MASK_BOTH = 3,
} si5351c_pll_mask_t;
typedef enum {
SI5351C_INPUT_XTAL = 0,
@ -83,7 +88,7 @@ void si5351c_configure_inputs(si5351c_driver_t* const drv, const si5351c_input_t
void si5351c_configure_pll_multisynth(
si5351c_driver_t* const drv,
const si5351c_input_t input);
void si5351c_reset_pll(si5351c_driver_t* const drv, si5351c_pll_t pll);
void si5351c_reset_plls(si5351c_driver_t* const drv, si5351c_pll_mask_t mask);
void si5351c_configure_multisynth(
si5351c_driver_t* const drv,
const uint_fast8_t ms_number,