Universalize: si5351.c
Co-authored-by: Antoine van Gelder <antoine@greatscottgadgets.com>
This commit is contained in:
Martin Ling
parent
c913e81ed6
commit
cfd729597c
1 changed files with 64 additions and 55 deletions
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@ -23,7 +23,7 @@
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#include <stdbool.h>
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#include <stddef.h>
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#if defined(HACKRF_ONE)
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#if defined(HACKRF_ONE) || defined(UNIVERSAL)
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#include <libopencm3/lpc43xx/scu.h>
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#endif
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@ -32,7 +32,7 @@
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#include "platform_detect.h"
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#include "selftest.h"
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#include "si5351c.h"
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#if defined(HACKRF_ONE)
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#if defined(HACKRF_ONE) || defined(UNIVERSAL)
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#include "gpio.h"
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#include "platform_gpio.h"
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#include "platform_scu.h"
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@ -235,6 +235,7 @@ void si5351c_configure_multisynth(
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void si5351c_configure_clock_control(si5351c_driver_t* const drv)
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{
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uint8_t clkout_ctrl;
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board_id_t board_id = detected_platform();
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if (clkout_enabled) {
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clkout_ctrl = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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@ -269,7 +270,8 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv)
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SI5351C_CLK_POWERDOWN |
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SI5351C_CLK_INT_MODE /* not connected, but: PLL B int mode */
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};
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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if (board_id == BOARD_ID_HACKRF1_R9) {
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#if defined(HACKRF_ONE) || defined(UNIVERSAL)
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data[1] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_6MA);
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@ -280,37 +282,41 @@ void si5351c_configure_clock_control(si5351c_driver_t* const drv)
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data[4] = SI5351C_CLK_POWERDOWN;
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data[5] = SI5351C_CLK_POWERDOWN;
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data[6] = SI5351C_CLK_POWERDOWN;
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#endif
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}
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#ifdef PRALINE
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/* CLK0: AFE_CLK */
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data[1] = SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA);
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/* CLK1: SCT_CLK and FPGA_CLK */
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data[2] = SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA);
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/* CLK3: CLKOUT */
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clkout_ctrl = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_B) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA);
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/* CLK4: XCVR_CLK */
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data[5] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_B) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) | SI5351C_CLK_INV;
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data[6] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_B) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA);
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if ((detected_revision() & ~BOARD_REV_GSG) < BOARD_REV_PRALINE_R1_1) {
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/* CLK2: FPGA_CLK (not shared with SCT_CLK on older boards) */
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data[3] = SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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if (board_id == BOARD_ID_PRALINE) {
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#if defined(PRALINE) || defined(UNIVERSAL)
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/* CLK0: AFE_CLK */
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data[1] = SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA);
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/* CLK1: SCT_CLK and FPGA_CLK */
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data[2] = SI5351C_CLK_FRAC_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA);
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} else {
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/* CLK2: MCU_CLK */
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data[3] = SI5351C_CLK_POWERDOWN;
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}
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/* CLK3: CLKOUT */
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clkout_ctrl = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_B) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_8MA);
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/* CLK4: XCVR_CLK */
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data[5] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_B) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA) | SI5351C_CLK_INV;
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data[6] = SI5351C_CLK_INT_MODE | SI5351C_CLK_PLL_SRC(SI5351C_PLL_B) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_4MA);
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if ((detected_revision() & ~BOARD_REV_GSG) < BOARD_REV_PRALINE_R1_1) {
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/* CLK2: FPGA_CLK (not shared with SCT_CLK on older boards) */
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data[3] = SI5351C_CLK_FRAC_MODE |
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SI5351C_CLK_PLL_SRC(SI5351C_PLL_A) |
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SI5351C_CLK_SRC(SI5351C_CLK_SRC_MULTISYNTH_SELF) |
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SI5351C_CLK_IDRV(SI5351C_CLK_IDRV_2MA);
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} else {
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/* CLK2: MCU_CLK */
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data[3] = SI5351C_CLK_POWERDOWN;
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}
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#endif
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}
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si5351c_write(drv, data, sizeof(data));
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}
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@ -325,30 +331,34 @@ void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
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/* 7: Clock to CPU is deactivated as it is not used and creates noise */
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/* 3: External clock output is deactivated by default */
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#ifndef PRALINE
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uint8_t value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_ENABLE(2) | SI5351C_CLK_ENABLE(4) | SI5351C_CLK_ENABLE(5) |
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SI5351C_CLK_DISABLE(6) | SI5351C_CLK_DISABLE(7);
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#else
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uint8_t value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_ENABLE(4) | SI5351C_CLK_ENABLE(5) | SI5351C_CLK_DISABLE(6) |
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SI5351C_CLK_DISABLE(7);
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if ((detected_revision() & ~BOARD_REV_GSG) < BOARD_REV_PRALINE_R1_1) {
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/* CLK2: FPGA_CLK (not shared with SCT_CLK on older boards) */
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value |= SI5351C_CLK_ENABLE(2);
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} else {
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value |= SI5351C_CLK_DISABLE(2);
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}
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#endif
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board_id_t board_id = detected_platform();
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uint8_t clkout = 3;
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uint8_t value;
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/* HackRF One r9 has only three clock generator outputs. */
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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clkout = 2;
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if (board_id == BOARD_ID_PRALINE) {
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value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_DISABLE(3) | SI5351C_CLK_DISABLE(4) |
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SI5351C_CLK_DISABLE(5) | SI5351C_CLK_DISABLE(6) |
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SI5351C_CLK_ENABLE(4) | SI5351C_CLK_ENABLE(5) |
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SI5351C_CLK_DISABLE(6) | SI5351C_CLK_DISABLE(7);
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if ((detected_revision() & ~BOARD_REV_GSG) < BOARD_REV_PRALINE_R1_1) {
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/* CLK2: FPGA_CLK (not shared with SCT_CLK on older boards) */
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value |= SI5351C_CLK_ENABLE(2);
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} else {
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value |= SI5351C_CLK_DISABLE(2);
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}
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} else {
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value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_ENABLE(2) | SI5351C_CLK_ENABLE(4) |
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SI5351C_CLK_ENABLE(5) | SI5351C_CLK_DISABLE(6) |
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SI5351C_CLK_DISABLE(7);
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/* HackRF One r9 has only three clock generator outputs. */
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if (board_id == BOARD_ID_HACKRF1_R9) {
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clkout = 2;
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value = SI5351C_CLK_ENABLE(0) | SI5351C_CLK_ENABLE(1) |
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SI5351C_CLK_DISABLE(3) | SI5351C_CLK_DISABLE(4) |
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SI5351C_CLK_DISABLE(5) | SI5351C_CLK_DISABLE(6) |
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SI5351C_CLK_DISABLE(7);
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}
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}
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value |= (clkout_enabled) ? SI5351C_CLK_ENABLE(clkout) :
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@ -357,16 +367,16 @@ void si5351c_enable_clock_outputs(si5351c_driver_t* const drv)
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si5351c_write(drv, data, sizeof(data));
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outputs_disabled = value;
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#if defined(HACKRF_ONE)
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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#if defined(HACKRF_ONE) || defined(UNIVERSAL)
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const platform_gpio_t* gpio = platform_gpio();
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if (clkout_enabled) {
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gpio_set(gpio->h1r9_clkout_en);
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} else {
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gpio_clear(gpio->h1r9_clkout_en);
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}
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}
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#endif
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}
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}
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void si5351c_set_int_mode(
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@ -466,8 +476,8 @@ void si5351c_init(si5351c_driver_t* const drv)
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selftest.report.pass = false;
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}
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#if defined(HACKRF_ONE)
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if (detected_platform() == BOARD_ID_HACKRF1_R9) {
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#if defined(HACKRF_ONE) || defined(UNIVERSAL)
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const platform_gpio_t* gpio = platform_gpio();
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const platform_scu_t* scu = platform_scu();
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@ -485,9 +495,8 @@ void si5351c_init(si5351c_driver_t* const drv)
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scu_pinmux(scu->H1R9_MCU_CLK_EN, SCU_GPIO_FAST | SCU_CONF_FUNCTION0);
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gpio_clear(gpio->h1r9_mcu_clk_en);
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gpio_output(gpio->h1r9_mcu_clk_en);
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}
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#endif
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(void) drv;
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}
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}
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/*
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