Enable TX interpolation

Add phase offset to FPGA_CLK/SCT_CLK
In order to support higher DAC sample rates on Praline with interpolation, it is necessary to adjust the phase of FPGA_CLK with respect to AFE_CLK.
2026-03-10 21:34:48 -04:00 · 2026-03-10 18:16:07 -04:00
241 changed files with 5500 additions and 10488 deletions
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@ -17,127 +17,70 @@ jobs:
  host:
    strategy:
      matrix:
-        os: ['macos', 'ubuntu', 'windows']
-        cmake: ['3.10.0', '3.21.7', '4.2.6', 'latest']
-        compiler: ['gcc', 'msvc']
+        sys:
+          - {os: 'macos', shell: 'bash'}
+          - {os: 'ubuntu', shell: 'bash'}
+          - {os: 'windows', shell: 'pwsh'}
+          - {os: 'windows', shell: 'msys2'}
+        cmake: ['3.10.0', '3.16.0', '3.21.0', '4.0.0', 'latest']
        exclude:
-          # MSVC only runs on Windows.
-          - os: 'macos'
-            compiler: 'msvc'
-          - os: 'ubuntu'
-            compiler: 'msvc'
-          # We can't use the oldest CMake versions on Windows.
-          - os: 'windows'
+          # GitHub runners use Visual Studio 2022. Support added in CMake 3.21.
+          - sys: {os: 'windows', shell: 'pwsh'}
            cmake: '3.10.0'
-          # The in-between CMake versions aren't so intersting with GCC.
-          - compiler: 'gcc'
-            cmake: '3.21.7'
-          - compiler: 'gcc'
-            cmake: '4.2.6'
+          - sys: {os: 'windows', shell: 'pwsh'}
+            cmake: '3.16.0'
+          # MSYS2 always supplies the latest cmake.
+          - sys: {os: 'windows', shell: 'msys2'}
+            cmake: '3.10.0'
+          - sys: {os: 'windows', shell: 'msys2'}
+            cmake: '3.16.0'
+          - sys: {os: 'windows', shell: 'msys2'}
+            cmake: '3.21.0'
+          - sys: {os: 'windows', shell: 'msys2'}
+            cmake: '4.0.0'
        include:
-          # Shell selection
-          - os: 'macos'
-            shell: 'bash'
-          - os: 'ubuntu'
-            shell: 'bash'
-          - os: 'windows'
-            compiler: 'msvc'
-            shell: 'pwsh'
-          - os: 'windows'
-            compiler: 'gcc'
-            shell: 'msys2'
-          # MSVC version selection
-          - cmake: '3.21.7'
-            msvc: '17.14'
-          - cmake: '4.2.6'
-            msvc: 'latest'
-          - cmake: 'latest'
-            msvc: 'latest'
-          # CMake generator selection
-          - os: 'macos'
-            generator: 'Unix Makefiles'
-          - os: 'ubuntu'
-            generator: 'Unix Makefiles'
-          - compiler: 'msvc'
-            cmake: '3.21.7'
-            generator: 'Visual Studio 17 2022'
-          - compiler: 'msvc'
-            cmake: '4.2.6'
-            generator: 'Visual Studio 18 2026'
-          - compiler: 'msvc'
-            cmake: 'latest'
-            generator: 'Visual Studio 18 2026'
-          - os: 'windows'
-            compiler: 'gcc'
-            generator: 'MSYS Makefiles'
-          # Additional CMake arguments
-          - os: 'windows'
-            compiler: 'msvc'
+          - sys: {os: 'windows', shell: 'pwsh'}
            cmake_args: >-
              -DPKG_CONFIG_EXECUTABLE=C:/vcpkg/installed/x64-windows/tools/pkgconf/pkgconf.exe
              -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake
              --install-prefix=$env:GITHUB_WORKSPACE/install
-          - os: 'windows'
-            compiler: 'gcc'
+          - sys: {os: 'windows', shell: 'msys2'}
            cmake_args: >-
              --install-prefix=/usr/local
-          # CMake 3.10 uses --build with --target install
-          - cmake: '3.10.0'
-            install_cmd: --build
-            install_args: --target install
-          # Later versions just use --install
-          - cmake: '3.21.7'
-            install_cmd: --install
-          - cmake: '4.2.6'
-            install_cmd: --install
-          - cmake: 'latest'
-            install_cmd: --install
-          # We need sudo on MacOS and Ubuntu only
-          - os: macos
-            sudo: sudo
-          - os: ubuntu
-            sudo: sudo
-

      # Don't cancel all builds when one fails
      fail-fast: false
-    runs-on: ${{ matrix.os }}-latest
+    runs-on: ${{ matrix.sys.os }}-latest

    defaults:
      run:
-        shell: '${{ matrix.shell }} {0}'
+        shell: '${{ matrix.sys.shell }} {0}'

    steps:
-    - uses: actions/checkout@v6
+    - uses: actions/checkout@v4

    - name: Setup cmake
-      uses: lukka/get-cmake@latest
+      uses: jwlawson/actions-setup-cmake@v2
      with:
-        cmakeVersion: ${{ matrix.cmake }}
-      if: matrix.shell != 'msys2'
-
-    - name: Install MSVC (Windows)
-      uses: k3DW/setup-msvc@v1
-      with:
-        vs-version: ${{ matrix.msvc }}
-      if: matrix.compiler == 'msvc' && matrix.msvc != 'latest'
+        cmake-version: ${{ matrix.cmake }}
+      if: matrix.sys.shell != 'msys2'

    - name: Install dependencies (macOS)
      run: brew install fftw
-      if: matrix.os == 'macos'
+      if: matrix.sys.os == 'macos'

    - name: Install dependencies (Ubuntu)
      run: |
        sudo apt update
        sudo apt install libfftw3-dev libusb-1.0-0-dev
-      if: matrix.os == 'ubuntu'
+      if: matrix.sys.os == 'ubuntu'

    - name: Install dependencies (Windows)
      run: vcpkg install --triplet=x64-windows libusb fftw3 pthreads pkgconf
-      if: matrix.os == 'windows' && matrix.shell != 'msys2'
+      if: matrix.sys.os == 'windows' && matrix.sys.shell != 'msys2'

    - name: Setup MSYS (Windows)
-      if: matrix.os == 'windows' && matrix.shell == 'msys2'
+      if: matrix.sys.os == 'windows' && matrix.sys.shell == 'msys2'
      uses: msys2/setup-msys2@v2
      with:
        msystem: UCRT64
@ -155,7 +98,7 @@ jobs:
      run: |
        cmake -E make_directory host/build
        cd host/build
-        cmake .. -G "${{ matrix.generator }}" -DCMAKE_BUILD_TYPE=Release ${{matrix.cmake_args}}
+        cmake .. -DCMAKE_BUILD_TYPE=Release ${{matrix.cmake_args}}
        cmake --build . --config Release

    # Build libhackrf ONLY
@ -164,12 +107,22 @@ jobs:
      run: |
        cmake -E make_directory host/libhackrf/build
        cd host/libhackrf/build
-        cmake .. -G "${{ matrix.generator }}" -DCMAKE_BUILD_TYPE=Release ${{ matrix.cmake_args }}
+        cmake .. -DCMAKE_BUILD_TYPE=Release ${{ matrix.cmake_args }}
        cmake --build . --config Release

    - name: Install (libhackrf)
      run: |
-        ${{ matrix.sudo }} cmake ${{ matrix.install_cmd }} host/libhackrf/build ${{ matrix.install_args }} --config Release
+        sudo cmake --install host/libhackrf/build --config Release
+      if: matrix.sys.os != 'windows' && matrix.cmake != '3.10.0'
+
+    - name: Install (libhackrf, CMake 3.10)
+      run: |
+        sudo cmake --build host/libhackrf/build --target install --config Release
+      if: matrix.sys.os != 'windows' && matrix.cmake == '3.10.0'
+
+    - name: Install (libhackrf, Windows)
+      run: cmake --install host/libhackrf/build --config Release
+      if: matrix.sys.os == 'windows'

    # Build hackrf-tools ONLY

@ -177,12 +130,22 @@ jobs:
      run: |
        cmake -E make_directory host/hackrf-tools/build
        cd host/hackrf-tools/build
-        cmake .. -G "${{ matrix.generator }}" -DCMAKE_BUILD_TYPE=Release ${{ matrix.cmake_args }}
+        cmake .. -DCMAKE_BUILD_TYPE=Release ${{ matrix.cmake_args }}
        cmake --build . --config Release

    - name: Install (hackrf-tools)
      run: |
-        ${{ matrix.sudo }} cmake ${{ matrix.install_cmd }} host/hackrf-tools/build ${{ matrix.install_args }}
+        sudo cmake --install host/hackrf-tools/build --config Release
+      if: matrix.sys.os != 'windows' && matrix.cmake != '3.10.0'
+
+    - name: Install (hackrf-tools, CMake 3.10)
+      run: |
+        sudo cmake --build host/hackrf-tools/build --target install --config Release
+      if: matrix.sys.os != 'windows' && matrix.cmake == '3.10.0'
+
+    - name: Install (hackrf-tools, Windows)
+      run: cmake --install host/hackrf-tools/build --config Release
+      if: matrix.sys.os == 'windows'

    # Publish the contents of install/bin (which should be the combination libhackrf and host-tools) for Windows
    - name: Publish Artifacts (Windows)
@ -190,40 +153,31 @@ jobs:
      with:
        name: hackrf-tools-windows
        path: ${{github.workspace}}/install/bin
-      if: matrix.os == 'windows' && matrix.cmake == 'latest' && matrix.shell == 'pwsh'
+      if: matrix.sys.os == 'windows' && matrix.cmake == 'latest' && matrix.sys.shell == 'pwsh'

  firmware:
    strategy:
      matrix:
        os: ['macos', 'ubuntu', 'windows']
-        board: ['HACKRF_ONE', 'JAWBREAKER', 'RAD1O', 'PRALINE', 'UNIVERSAL']
-        cmake: ['3.12.0', 'latest']
+        board: ['HACKRF_ONE', 'JAWBREAKER', 'RAD1O', 'PRALINE']
+        cmake: ['3.10.0', 'latest']
        exclude:
          - os: 'windows'
-            cmake: '3.12.0'
-          # GitHub doesn't give us many macOS runners, so don't build for every board.
-          # We just need to know that building firmware works on macOS. Use PRALINE
-          # since that's the most complicated one due to FPGA bitstreams.
-          - os: 'macos'
-            board: 'HACKRF_ONE'
-          - os: 'macos'
-            board: 'JAWBREAKER'
-          - os: 'macos'
-            board: 'RAD1O'
+            cmake: '3.10.0'

      # Don't cancel all builds when one fails
      fail-fast: false
    runs-on: ${{ matrix.os }}-latest

    steps:
-    - uses: actions/checkout@v6
+    - uses: actions/checkout@v4
      with:
        submodules: true

    - name: Setup cmake
-      uses: lukka/get-cmake@latest
+      uses: jwlawson/actions-setup-cmake@v2
      with:
-        cmakeVersion: ${{ matrix.cmake }}
+        cmake-version: ${{ matrix.cmake }}
      if: matrix.os != 'windows'

    - name: Install Arm GNU Toolchain
--- a/.github/workflows/clang-format-check.yml
+++ b/.github/workflows/clang-format-check.yml
@ -16,7 +16,7 @@ jobs:
          - check: 'firmware/hackrf_usb'
            exclude: ''
    steps:
-    - uses: actions/checkout@v6
+    - uses: actions/checkout@v4
    - name: Run clang-format-action
      uses: jidicula/clang-format-action@v4.6.2
      with:
--- a/.github/workflows/includes-check.yml
+++ b/.github/workflows/includes-check.yml
@ -1,96 +0,0 @@
-name: Check includes
-on: [push, pull_request]
-
-defaults:
-  run:
-    shell: bash
-
-jobs:
-  includes-check:
-    runs-on: ubuntu-latest
-    container:
-      image: "debian:13"
-      options: --user 0
-    strategy:
-      matrix:
-        board: ['HACKRF_ONE', 'JAWBREAKER', 'RAD1O', 'PRALINE', 'UNIVERSAL']
-        cmake: ['3.12.0', 'latest']
-
-      # Don't cancel all builds when one fails
-      fail-fast: false
-
-    steps:
-
-    - name: Make it work on debian
-      run: |
-        apt update
-        apt install -y git python3 python3-pip python3-venv nodejs unzip
-        # actions/checkout insists on putting the checkout in the
-        # working directory rather than ${{ github.workspace }}.
-        #
-        # This may just be because the 'runner' user does not exist
-        # in the docker image at startup.
-        #
-        # also see: https://github.com/actions/runner/issues/878
-        useradd -ms /bin/bash runner
-        ln -s /__w /home/runner/work
-
-    - name: Checkout repository
-      uses: actions/checkout@v6
-      with:
-        submodules: true
-
-    - name: Setup cmake
-      uses: lukka/get-cmake@latest
-      with:
-        cmakeVersion: ${{ matrix.cmake }}
-
-    - name: Install Arm GNU Toolchain
-      uses: carlosperate/arm-none-eabi-gcc-action@v1
-
-    - name: Install dependencies
-      run: |
-        python3 -m venv environment && source environment/bin/activate
-        python3 -m pip install PyYAML
-        apt install -y iwyu
-        iwyu --version
-
-    - name: Build libopencm3
-      working-directory: ${{github.workspace}}/firmware/libopencm3/
-      run: |
-        source ../../environment/bin/activate
-        make
-
-    - name: Create Build Environment
-      run: cmake -E make_directory ${{github.workspace}}/firmware/build
-
-    - name: Configure CMake
-      working-directory: ${{github.workspace}}/firmware/build
-      run: cmake ${{github.workspace}}/firmware/ -DCMAKE_BUILD_TYPE=Release -DBOARD=${{ matrix.board }} -DCHECK_INCLUDES=1
-
-    - name: Build
-      working-directory: ${{github.workspace}}/firmware/build
-      run: |
-        source ../../environment/bin/activate
-        output="$(cmake --build . --config Release 2>&1)"
-        while IFS= read -r line
-        do
-            if [[ "${line}" == "Warning: include-what-you-use"* ]]; then
-                exit_code=1
-                dump=1
-                echo
-            elif [[ "${line}" == "---" ]]; then
-                dump=0
-                echo
-            fi
-            if [[ ${dump} == "1" ]]; then
-                echo "${line}"
-            fi
-        done <<< ${output}
-        if [[ ${exit_code} == "1" ]]; then
-            echo "Includes check failed for board target: ${{ matrix.board }}"
-        else
-            echo "Includes check succeeded for board target: ${{ matrix.board }}"
-        fi
-        echo $(include-what-you-use --version)
-        exit ${exit_code}
--- a/367
+++ b/367
@ -1,123 +1,275 @@
 import org.jenkinsci.plugins.workflow.steps.FlowInterruptedException

-def docker_args = '''--group-add=20 --group-add=46 --device-cgroup-rule="c 189:* rmw" \
-                    --device-cgroup-rule="c 166:* rmw" -v /dev/bus/usb:/dev/bus/usb \
-                    -v /tmp/req_pipe:/tmp/req_pipe -v /tmp/res_pipe:/tmp/res_pipe'''
-
-def h1_test = '''python3 ci-scripts/hackrf_test.py --ci --log log \
-                    --hostdir host/build/hackrf-tools/src/ \
-                    --fwupdate firmware/hackrf_usb/build/ \
-                    --tester 0000000000000000325866e629a25623 \
-                    --eut RunningFromRAM --unattended --rev r4'''
-
-def hpro_test = '''python3 ci-scripts/hackrf_pro_test.py --ci --log log \
-                    --hostdir host/build/hackrf-tools/src \
-                    --fwupdate firmware/hackrf_usb/build \
-                    --tester 0000000000000000a06063c82338145f \
-                    --eut RunningFromRAM -p --rev r1.2'''
-
 pipeline {
    agent any
    stages {
        stage('Build Docker Image') {
-            options {
-                timeout(time: 20, unit: 'MINUTES')
-            }
            steps {
                sh 'docker build -t hackrf https://github.com/greatscottgadgets/hackrf.git'
            }
        }
-        stage('Test HackRF One with BOARD=HACKRF_ONE') {
+        stage('Test HackRF One') {
            agent {
                docker {
                    image 'hackrf'
                    reuseNode true
-                    args docker_args
+                    args '''--group-add=20 --group-add=46 --device-cgroup-rule="c 189:* rmw" \
+                            --device-cgroup-rule="c 166:* rmw" -v /dev/bus/usb:/dev/bus/usb \
+                            -v /tmp/req_pipe:/tmp/req_pipe -v /tmp/res_pipe:/tmp/res_pipe'''
                }
            }
-            options {
-                timeout(time: 20, unit: 'MINUTES')
-            }
            steps {
-                runCommand("Install Host Tools", './ci-scripts/install_host.sh', 3, 1, 'MINUTES')
-                runCommand("Build HackRF One Firmware", './ci-scripts/build_firmware.sh HACKRF_ONE', 3, 1, 'MINUTES')
-                lock('HIL_hubs') {
-                    script {
-                        allOff()
-                        runTest("Check Host", 'h1_eut', './ci-scripts/test_host.sh')
-                        runTest("HackRF One HIL Test", 'h1_tester h1_eut', h1_test)
-                        runTest("SGPIO Debug Test", 'h1_eut', 'python3 ci-scripts/test_sgpio_debug.py')
+                sh './ci-scripts/install_host.sh'
+                sh './ci-scripts/build_h1_firmware.sh'
+                script {
+                    try {
+                        // Allow 20 seconds for the USB hub port power server to respond
+                        timeout(time: 20, unit: 'SECONDS') {
+                            sh 'hubs all off'
+                        }
+                    } catch (FlowInterruptedException err) {
+                        // Check if the cause was specifically an exceeded timeout
+                        def cause = err.getCauses().get(0)
+                        if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                            echo "USB hub port power server command timeout reached."
+                            throw err // Re-throw the exception to fail the build
+                        } else {
+                            echo "Build interrupted for another reason."
+                            throw err // Re-throw the exception to fail the build
+                        }
+                    } catch (Exception err) {
+                        echo "An unrelated error occurred: ${err.getMessage()}"
+                        throw err
                    }
                }
+                retry(3) {
+                    script {
+                        try {
+                            // Allow 20 seconds for the USB hub port power server to respond
+                            timeout(time: 20, unit: 'SECONDS') {
+                                sh 'hubs h1_eut reset'
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "USB hub port power server command timeout reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
+                    }
+                    sh 'sleep 1s'
+                    sh './ci-scripts/test_host.sh'
+                }
+                retry(3) {
+                    script {
+                        try {
+                            // Allow 20 seconds for the USB hub port power server to respond
+                            timeout(time: 20, unit: 'SECONDS') {
+                                sh 'hubs h1_tester h1_eut reset'
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "USB hub port power server command timeout reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
+                    }
+                    sh 'sleep 1s'
+                    script {
+                        try {
+                            // Allow 5 minutes for the test to run
+                            timeout(time: 5, unit: 'MINUTES') {
+                                sh '''python3 ci-scripts/hackrf_test.py --ci --log log \
+                                    --hostdir host/build/hackrf-tools/src/ \
+                                    --fwupdate firmware/hackrf_usb/build/ \
+                                    --tester 0000000000000000325866e629a25623 \
+                                    --eut RunningFromRAM --unattended --rev r4'''
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "HackRF One Test timeout limit reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
+                    }
+                    script {
+                        try {
+                            // Allow 20 seconds for the USB hub port power server to respond
+                            timeout(time: 20, unit: 'SECONDS') {
+                                sh 'hubs all off'
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "USB hub port power server command timeout reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
+                    }
+                }
+                retry(3) {
+                    script {
+                        try {
+                            // Allow 20 seconds for the USB hub port power server to respond
+                            timeout(time: 20, unit: 'SECONDS') {
+                                sh 'hubs h1_eut reset'
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "USB hub port power server command timeout reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
+                    }
+                    sh 'sleep 1s'
+                    sh 'python3 ci-scripts/test_sgpio_debug.py'
+                }
            }
        }
-        stage('Test HackRF One with BOARD=UNIVERSAL') {
+        stage('Test HackRF Pro') {
            agent {
                docker {
                    image 'hackrf'
                    reuseNode true
-                    args docker_args
+                    args '''--group-add=20 --group-add=46 --device-cgroup-rule="c 189:* rmw" \
+                    --device-cgroup-rule="c 166:* rmw" -v /dev/bus/usb:/dev/bus/usb \
+                    -v /tmp/req_pipe:/tmp/req_pipe -v /tmp/res_pipe:/tmp/res_pipe'''
                }
            }
-            options {
-                timeout(time: 20, unit: 'MINUTES')
-            }
            steps {
-                runCommand("Install Host Tools", './ci-scripts/install_host.sh', 3, 1, 'MINUTES')
-                runCommand("Build Universal Firmware", './ci-scripts/build_firmware.sh UNIVERSAL', 3, 1, 'MINUTES')
-                lock('HIL_hubs') {
-                    script {
-                        allOff()
-                        runTest("Check Host", 'h1_eut', './ci-scripts/test_host.sh')
-                        runTest("HackRF One HIL Test", 'h1_tester h1_eut', h1_test)
-                        runTest("SGPIO Debug Test", 'h1_eut', 'python3 ci-scripts/test_sgpio_debug.py')
+                sh './ci-scripts/install_host.sh'
+                sh './ci-scripts/build_hpro_firmware.sh'
+                script {
+                    try {
+                        // Allow 20 seconds for the USB hub port power server to respond
+                        timeout(time: 20, unit: 'SECONDS') {
+                            sh 'hubs all off'
+                        }
+                    } catch (FlowInterruptedException err) {
+                        // Check if the cause was specifically an exceeded timeout
+                        def cause = err.getCauses().get(0)
+                        if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                            echo "USB hub port power server command timeout reached."
+                            throw err // Re-throw the exception to fail the build
+                        } else {
+                            echo "Build interrupted for another reason."
+                            throw err // Re-throw the exception to fail the build
+                        }
+                    } catch (Exception err) {
+                        echo "An unrelated error occurred: ${err.getMessage()}"
+                        throw err
                    }
                }
-
-            }
-        }
-        stage('Test HackRF Pro with BOARD=PRALINE') {
-            agent {
-                docker {
-                    image 'hackrf'
-                    reuseNode true
-                    args "$docker_args"
-                }
-            }
-            options {
-                timeout(time: 20, unit: 'MINUTES')
-            }
-            steps {
-                runCommand("Install Host Tools", './ci-scripts/install_host.sh', 3, 1, 'MINUTES')
-                runCommand("Build Praline Firmware", './ci-scripts/build_firmware.sh PRALINE', 3, 1, 'MINUTES')
-                lock('HIL_hubs') {
+                retry(3) {
                    script {
-                        allOff()
-                        runTest("Check Host", 'hpro_eut', './ci-scripts/test_host.sh')
-                        runTest("HackRF Pro HIL Test", 'hpro_tester hpro_eut', hpro_test)
+                        try {
+                            // Allow 20 seconds for the USB hub port power server to respond
+                            timeout(time: 20, unit: 'SECONDS') {
+                                sh 'hubs hpro_eut reset'
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "USB hub port power server command timeout reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
                    }
+                    sh 'sleep 1s'
+                    sh './ci-scripts/test_host.sh'
                }
-            }
-        }
-        stage('Test HackRF Pro with BOARD=UNIVERSAL') {
-            agent {
-                docker {
-                    image 'hackrf'
-                    reuseNode true
-                    args "$docker_args"
-                }
-            }
-            options {
-                timeout(time: 20, unit: 'MINUTES')
-            }
-            steps {
-                runCommand("Install Host Tools", './ci-scripts/install_host.sh', 3, 1, 'MINUTES')
-                runCommand("Build Universal Firmware", './ci-scripts/build_firmware.sh UNIVERSAL', 3, 1, 'MINUTES')
-                lock('HIL_hubs') {
+                retry(3) {
                    script {
-                        allOff()
-                        runTest("Check Host", 'hpro_eut', './ci-scripts/test_host.sh')
-                        runTest("HackRF Pro HIL Test", 'hpro_tester hpro_eut', hpro_test)
+                        try {
+                            // Allow 10 seconds for the USB hub port power server to respond
+                            timeout(time: 20, unit: 'SECONDS') {
+                                sh 'hubs hpro_tester hpro_eut reset'
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "USB hub port power server command timeout reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
+                    }
+                    sh 'sleep 1s'
+                    script {
+                        try {
+                            // Allow 5 minutes for the test to run
+                            timeout(time: 5, unit: 'MINUTES') {
+                                sh '''python3 ci-scripts/hackrf_pro_test.py --ci --log log \
+                                    --hostdir host/build/hackrf-tools/src \
+                                    --fwupdate firmware/hackrf_usb/build \
+                                    --tester 0000000000000000a06063c82338145f \
+                                    --eut RunningFromRAM -p --rev r1.2'''
+                            }
+                        } catch (FlowInterruptedException err) {
+                            // Check if the cause was specifically an exceeded timeout
+                            def cause = err.getCauses().get(0)
+                            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
+                                echo "HackRF Pro Test timeout limit reached."
+                                throw err // Re-throw the exception to fail the build
+                            } else {
+                                echo "Build interrupted for another reason."
+                                throw err // Re-throw the exception to fail the build
+                            }
+                        } catch (Exception err) {
+                            echo "An unrelated error occurred: ${err.getMessage()}"
+                            throw err
+                        }
                    }
                }
            }
@ -132,46 +284,3 @@ pipeline {
        }
    }
 }
-
-def allOff() {
-    // Allow up to 3 retries, 20 seconds each, for the USB hub port power server to respond appropriately
-    runCommand('USB hub port power server command', "hubs all off", 3, 20, 'SECONDS')
-}
-
-def reset(devices) {
-    // Allow up to 3 retries, 20 seconds each, for the USB hub port power server to respond appropriately
-    runCommand('USB hub port power server command', "hubs ${devices} reset", 3, 20, 'SECONDS')
-}
-
-def runCommand(title, cmd, retries, time, unit) {
-    retry(retries) {
-        try {
-            timeout(time: time, unit: unit) {
-                sh "${cmd}"
-            }
-        } catch (FlowInterruptedException err) {
-            // Check if the cause was specifically an exceeded timeout
-            def cause = err.getCauses().get(0)
-            if (cause instanceof org.jenkinsci.plugins.workflow.steps.TimeoutStepExecution.ExceededTimeout) {
-                echo "${title} timeout reached."
-                throw err // Re-throw the exception to fail the build
-            } else {
-                echo "Build interrupted for another reason."
-                throw err // Re-throw the exception to fail the build
-            }
-        } catch (Exception err) {
-            echo "An unrelated error occurred: ${err.getMessage()}"
-            throw err
-        }
-    }
-}
-
-def runTest(title, devices, cmd) {
-    retry(3) {
-        // reset() retains it's own internal retries
-        reset(devices)
-        sh 'sleep 1s'
-        // run the test with 0 internal retries and 3 external retries to ensure resets between runs
-        runCommand(title, cmd, 0, 5, 'MINUTES')
-    }
-}
--- a/ci-scripts/build_h1_firmware.sh
+++ b/ci-scripts/build_h1_firmware.sh
@ -3,7 +3,6 @@ set -e
 git submodule init
 git submodule update
 cd firmware/hackrf_usb
-rm -rf build
-cmake -DBOARD=$1 -B build
+cmake -B build
 cmake --build build
 cd ../..
--- a/ci-scripts/build_hpro_firmware.sh
+++ b/ci-scripts/build_hpro_firmware.sh
@ -0,0 +1,8 @@
+#!/bin/bash
+set -e
+git submodule init
+git submodule update
+cd firmware/hackrf_usb
+cmake -DBOARD=PRALINE -B build
+cmake --build build
+cd ../..
--- a/ci-scripts/hackrf_pro_test.py
+++ b/ci-scripts/hackrf_pro_test.py
@ -663,6 +663,9 @@ class HackRF:
            self.rf_test_cases = praline_r110_rf_test_cases

    def clkin(self):
+        if self.name == "EUT" and self.id == "5":
+            debug = subprocess.run([self.bin_dir + "/hackrf_debug", "-d", self.serial,
+                                    "-C", "0"])
        command = subprocess.run([self.bin_dir + "/hackrf_clock", "-i", "-d",
            self.serial], capture_output=True, encoding="utf-8",
            timeout=TIMEOUT)
@ -716,7 +719,8 @@ class HackRF:
                log(receive.stdout + receive.stderr)
                fail(220 + self.unit_number)

-            # confirm that PLL A locked to new source
+            # confirm that PLL locked to new source
+            expected_value = "0x01" if (enable and self.partner.revision != "r9") else "0x51"
            timeout = time.time() + 1
            while time.time() < timeout:
                debug = subprocess.run([self.partner.bin_dir + "/hackrf_debug", "-d",
@ -726,17 +730,9 @@ class HackRF:
                if debug.returncode != 0:
                    log(debug.stderr)
                    fail(230 + self.unit_number)
-                output = str(debug.stdout).split()
-                try:
-                    val = int(output[3], 0)
-                except:
-                    log(debug.stderr)
-                    log(traceback.format_exc())
-                    fail(230 + self.unit_number)
-                # Check LOL_A
-                if not (val >> 5) & 1:
+                if expected_value in debug.stdout:
                    break
-            if (val >> 5) & 1:
+            if expected_value not in debug.stdout:
                fail(232 + self.unit_number)
            time.sleep(0.1)
        else:
@ -1410,11 +1406,11 @@ def program(bin_dir, fw_dir, serial, unattended=False):
    if spiflash.returncode != 0:
        log(spiflash.stdout + spiflash.stderr)
        fail(70)
-    time.sleep(3)

    then = time.time()
    device_found = False
    while time.time() < (then + 5):
+        time.sleep(1)
        flash_info = subprocess.run([bin_dir + "/hackrf_info"], capture_output=True,
            timeout=TIMEOUT)
        if serial == "RunningFromRAM" and not unattended:
@ -1430,7 +1426,7 @@ def program(bin_dir, fw_dir, serial, unattended=False):
        if serial in flash_info.stdout.decode('utf-8', errors='ignore'):
            device_found = True
            break
-        time.sleep(1)
+        time.sleep(0.1)
    if not device_found:
        fail(75)

--- a/ci-scripts/hackrf_test.py
+++ b/ci-scripts/hackrf_test.py
@ -595,7 +595,8 @@ class HackRF:
                log(receive.stdout + receive.stderr)
                fail(220 + self.unit_number)

-            # confirm that PLL A locked to new source
+            # confirm that PLL locked to new source
+            expected_value = "0x01" if (enable and self.partner.revision != "r9") else "0x51"
            timeout = time.time() + 1
            while time.time() < timeout:
                debug = subprocess.run([self.partner.bin_dir + "hackrf_debug", "-d",
@ -605,17 +606,9 @@ class HackRF:
                if debug.returncode != 0:
                    log(debug.stderr)
                    fail(230 + self.unit_number)
-                output = str(debug.stdout).split()
-                try:
-                    val = int(output[3], 0)
-                except:
-                    log(debug.stderr)
-                    log(traceback.format_exc())
-                    fail(230 + self.unit_number)
-                # Check LOL_A
-                if not (val >> 5) & 1:
+                if expected_value in debug.stdout:
                    break
-            if (val >> 5) & 1:
+            if expected_value not in debug.stdout:
                fail(232 + self.unit_number)
            time.sleep(0.1)
        else:
@ -1358,7 +1351,7 @@ def main():
            eut.clkout_connected = True
            tester.clkout_connected = True

-        if count > 0 and not args.fwupdate:
+        if count > 0 and not args.fw_update:
            eut.activate_leds(False)

        eut.test_serial()
--- a/docs/images/gateware-basic-block-diagram.png
+++ b/docs/images/gateware-basic-block-diagram.png
--- a/docs/images/gateware-basic-block-diagram.svg
+++ b/docs/images/gateware-basic-block-diagram.svg
--- a/docs/images/gateware-ext-prec-rx-dsp-chain.png
+++ b/docs/images/gateware-ext-prec-rx-dsp-chain.png
--- a/docs/images/gateware-ext-prec-rx-dsp-chain.svg
+++ b/docs/images/gateware-ext-prec-rx-dsp-chain.svg
--- a/docs/images/gateware-ext-prec-tx-dsp-chain.png
+++ b/docs/images/gateware-ext-prec-tx-dsp-chain.png
--- a/docs/images/gateware-ext-prec-tx-dsp-chain.svg
+++ b/docs/images/gateware-ext-prec-tx-dsp-chain.svg
--- a/docs/images/gateware-halfprec-dsp-chain.png
+++ b/docs/images/gateware-halfprec-dsp-chain.png
--- a/docs/images/gateware-halfprec-dsp-chain.svg
+++ b/docs/images/gateware-halfprec-dsp-chain.svg
--- a/docs/images/gateware-rx-only-basic-block-diagram.png
+++ b/docs/images/gateware-rx-only-basic-block-diagram.png
--- a/docs/images/gateware-rx-only-basic-block-diagram.svg
+++ b/docs/images/gateware-rx-only-basic-block-diagram.svg
--- a/docs/images/gateware-standard-dsp-chain.png
+++ b/docs/images/gateware-standard-dsp-chain.png
--- a/docs/images/gateware-standard-dsp-chain.svg
+++ b/docs/images/gateware-standard-dsp-chain.svg
--- a/docs/images/gateware-tx-only-basic-block-diagram.png
+++ b/docs/images/gateware-tx-only-basic-block-diagram.png
--- a/docs/images/gateware-tx-only-basic-block-diagram.svg
+++ b/docs/images/gateware-tx-only-basic-block-diagram.svg
--- a/docs/source/external_clock_interface.rst
+++ b/docs/source/external_clock_interface.rst
@ -9,18 +9,12 @@ HackRF Pro

 HackRF Pro has two configurable SMA ports, P1 and P2. By default, P1 is configured as CLKIN and P2 as CLKOUT. The default behaviour of these signals is as described for HackRF One below.

-A second CLKIN signal is available on header P22 pin 2. Unlike HackRF One, HackRF Pro's P22_CLKIN is a separate signal from P1_CLKIN. To enable P22_CLKIN instead of P1_CLKIN use ``hackrf_clock -c p22``.
-
-Various internal signals can be connected to P1 or P2 instead of the default CLKIN and CLKOUT signals. Use ``hackrf_clock -1`` or ``hackrf_clock -2`` to select a different signal.
-
 HackRF One
 ~~~~~~~~~~

-HackRF One produces a 10 MHz clock signal on the CLKOUT SMA port. The signal is a 3.3 V, 10 MHz square wave intended for a high impedance load.
+HackRF One produces a 10 MHz clock signal on CLKOUT. The signal is a 3.3 V, 10 MHz square wave intended for a high impedance load.

-The CLKIN SMA port on HackRF One is a high impedance input that expects 3.3 V square wave at 10 MHz. Do not exceed 3.3 V or drop below 0 V on this input. Do not connect a clock signal at a frequency other than 10 MHz (unless you modify the firmware to support this). You may directly connect the CLKOUT port of one HackRF One to the CLKIN port of another HackRF.
-
-The CLKIN signal is also connected to header P22 pin 2. Unlike HackRF Pro, HackRF One has only one CLKIN signal shared between P22 pin 2 and the CLKIN port. Do not connect input signals to both CLKIN and P22 pin 2 simultaneously.
+The CLKIN port on HackRF One is a high impedance input that expects 3.3 V square wave at 10 MHz. Do not exceed 3.3 V or drop below 0 V on this input. Do not connect a clock signal at a frequency other than 10 MHz (unless you modify the firmware to support this). You may directly connect the CLKOUT port of one HackRF One to the CLKIN port of another HackRF One.

 HackRF One uses CLKIN instead of the internal crystal when a clock signal is detected on CLKIN. The switch to or from CLKIN only happens when a transmit or receive operation begins.

--- a/docs/source/gateware.rst
+++ b/docs/source/gateware.rst
@ -1,118 +0,0 @@
-================================================
-Gateware
-================================================
-
-One of the significant hardware changes in :ref:`HackRF Pro <hackrf_pro>` is the replacement of the CPLD with a FPGA. While the older CPLD primarily provided glue logic between the MCU and RF front end, the FPGA in HackRF Pro introduces more logic and DSP capability. This enables offloading digital signal processing tasks from the MCU.
-
-FPGAs are highly flexible devices whose behavior is defined by *gateware*: hardware descriptions that configure the internal logic fabric. HackRF Pro gateware is written in `Amaranth HDL <https://amaranth-lang.org/>`__, a Python-based hardware description language.
-
-The specific FPGA device used in HackRF Pro is the Lattice iCE40UP5K, which features 
-5280 LUT4s and 8 dedicated DSP (multiply-accumulate) blocks. We rely on the `open-source iCE40 FPGA toolchain <https://github.com/YosysHQ/icestorm>`__ to build the required bitstreams that are bundled in the firmware.
-
-All gateware source code lives under `firmware/fpga/` in the HackRF repository. Top-level designs reside in `firmware/fpga/top/` and are the primary entry points for different operational modes.
-
-By default, a standard gateware configuration is loaded at boot. However, the firmware can dynamically reconfigure the FPGA at runtime to switch between different gateware variants.
-
-
-Standard gateware
-~~~~~~~~~~~~~~~~~
-
-The standard gateware is used by default when the firmware has not requested an alternative bitstream.
-
-The standard gateware provides a balanced configuration optimized for general-purpose operation. It implements configurable digital signal processing paths for the reception and transmission paths, capable of (limited) frequency translation and supporting a wide range of sample rates.
-
-Block diagram
-^^^^^^^^^^^^^
-
-.. image:: ../images/gateware-basic-block-diagram.png
-        :align: center
-
-.. image:: ../images/gateware-standard-dsp-chain.png
-        :align: center
-        :width: 75%
-
-Features
-^^^^^^^^
-* 8-bit I, 8-bit Q data format
-* Receiver signal chain:
-    * Optional DC offset removal (DC blocker)
-    * Configurable fs/4 shifter (quarter sample rate): bypass, shift up or shift down
-    * Configurable decimation rates: 1x, 2x, 4x, 8x, 16x, 32x
-* Transmitter signal chain:
-    * Configurable interpolation rates: 1x, 2x, 4x, 8x, 16x, 32x
-* SPI control interface for register configuration
-* Double data rate (DDR) interface to RF transceiver
-* Interface to MCU (SGPIO)
-
-
-Half-precision gateware
-~~~~~~~~~~~~~~~~~~~~~~~
-
-The half-precision gateware reduces sample width to 4 bits per I/Q component, enabling higher throughput within the constraints of the USB interface (up to 40 Msps).
-
-This configuration is intended for applications where bandwidth is more critical than dynamic range, such as wideband spectrum monitoring.
-
-Block diagram
-^^^^^^^^^^^^^
-
-.. image:: ../images/gateware-basic-block-diagram.png
-        :align: center
-
-.. image:: ../images/gateware-halfprec-dsp-chain.png
-        :align: center
-        :width: 75%
-
-Features
-^^^^^^^^
-* 4-bit I, 4-bit Q data format
-* Receiver signal chain:
-    * Optional DC offset removal (DC blocker)
-    * Round to 4-bit I/Q
-* Transmitter signal chain:
-    * Extend width to 8-bit I/Q
-* SPI control interface for register configuration
-* Double data rate (DDR) interface to RF transceiver
-* Interface to MCU (SGPIO)
-
-Extended-precision gateware (RX and TX)
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The extended-precision gateware increases internal signal processing precision and output sample width to improve signal quality. The main drawback is that the minimum decimation or interpolation factor is 16x. Due to increased logic requirements, this gateware is split in two top-level designs (RX and TX).
-
-Samples are 16-bit I/Q, while the effective number of bits (ENOB) depends on the selected configuration and typically ranges between 9 and 11 bits.
-
-The increased dynamic range of the output makes it particularly useful for weak and/or narrowband signals.
-
-Block diagram (RX)
-^^^^^^^^^^^^^^^^^^
-
-.. image:: ../images/gateware-rx-only-basic-block-diagram.png
-        :align: center
-
-.. image:: ../images/gateware-ext-prec-rx-dsp-chain.png
-        :align: center
-        :width: 75%
-
-Block diagram (TX)
-^^^^^^^^^^^^^^^^^^
-
-.. image:: ../images/gateware-tx-only-basic-block-diagram.png
-        :align: center
-
-.. image:: ../images/gateware-ext-prec-tx-dsp-chain.png
-        :align: center
-        :width: 75%
-
-Features
-^^^^^^^^
-* 16-bit I, 16-bit Q data format
-* Receiver signal chain (RX extended-precision gateware):
-    * Optional DC offset removal (DC blocker)
-    * Configurable mixer (in fs/128 steps)
-    * Configurable decimation rates: 16x, 32x, 64x, 128x
-* Transmitter signal chain (TX extended-precision gateware):
-    * Configurable interpolation rates: 16x, 32x, 64x, 128x
-* SPI control interface for register configuration
-* Double data rate (DDR) interface to RF transceiver
-* Interface to MCU (SGPIO)
-
--- a/docs/source/hackrf_pro.rst
+++ b/docs/source/hackrf_pro.rst
@ -2,8 +2,6 @@
 HackRF Pro
 ================================================

-.. _hackrf_pro:
-
 .. image:: ../images/hackrf-pro-preliminary-photo.jpg
  :alt: HackRF Pro

--- a/docs/source/index.rst
+++ b/docs/source/index.rst
@ -57,13 +57,6 @@ Welcome to HackRF's documentation!
   setting_gain
   virtual_machines

-
-.. toctree::
-   :maxdepth: 2
-   :caption: Gateware
-
-   gateware
-
 .. toctree::
   :maxdepth: 2
   :caption: Opera Cake Documentation
--- a/docs/source/software_support.rst
+++ b/docs/source/software_support.rst
@ -43,11 +43,6 @@ Software That Has Direct Support For HackRF

    * `https://xakcop.com/aprs-sdr <https://xakcop.com/aprs-sdr/>`__

-* SigDigger (Windows/Linux/macOS)
-
-    * `https://github.com/BatchDrake/SigDigger <https://github.com/BatchDrake/SigDigger>`__
-    * Supports HackRF through SoapySDR / SoapyHackRF
-


 Software That Can Use Data From HackRF
@ -79,4 +74,4 @@ Troubleshooting Recommendations

 Many of these tools require libhackrf and at times HackRF Tools. It may help you to have updated libhackrf and HackRF Tools when troubleshooting these applications. 

-It is also strongly suggested, and usually required, that your HackRF Tools and HackRF firmware match. 
+It is also strongly suggested, and usually required, that your HackRF Tools and HackRF firmware match. 
--- a/firmware/CMakeLists.txt
+++ b/firmware/CMakeLists.txt
@ -20,17 +20,10 @@

 # Top directory CMake project for HackRF firmware

-option(CHECK_INCLUDES
-	   "Check firmware sources for unused includes and transitive dependencies. (Requires iwyu)" OFF)
-
-cmake_minimum_required(VERSION 3.12.0)
+cmake_minimum_required(VERSION 3.10.0)
 set(CMAKE_TOOLCHAIN_FILE toolchain-arm-cortex-m.cmake)

 project (hackrf_firmware_all C)

-if(CHECK_INCLUDES)
-	include(include-what-you-use.cmake)
-endif()
-
 add_subdirectory(blinky)
 add_subdirectory(hackrf_usb)
--- a/firmware/blinky/blinky.c
+++ b/firmware/blinky/blinky.c
@ -19,16 +19,14 @@
 * Boston, MA 02110-1301, USA.
 */

-#include "delay.h"
-#include "leds.h"
-#include "pins.h"
+#include "hackrf_core.h"
 #include "platform_detect.h"
-#include "power.h"
+#include "delay.h"

 int main(void)
 {
 	detect_hardware_platform();
-	pins_setup();
+	pin_setup();

 #ifndef PRALINE
 	/* enable 1V8 power supply so that the 1V8 LED lights up */
@ -39,19 +37,19 @@ int main(void)
 #endif

 	/* Blink LED1/2/3 on the board. */
-	while (1)
+	while (1) 
 	{
 		led_on(LED1);
 		led_on(LED2);
 		led_on(LED3);

-		delay_ms(150);
-
+		delay(2000000);
+		
 		led_off(LED1);
 		led_off(LED2);
 		led_off(LED3);
-
-		delay_ms(150);
+		
+		delay(2000000);
 	}

 	return 0;
--- a/firmware/common/LPC4320_M4_memory.ld
+++ b/firmware/common/LPC4320_M4_memory.ld
@ -26,8 +26,7 @@ MEMORY
 {
 	/* rom is really the shadow region that points to SPI flash or elsewhere */
 	rom (rx)  : ORIGIN = 0x00000000, LENGTH =  1M
-	ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH =  64K
-	ram_usb (rw) : ORIGIN = 0x10010000, LENGTH = 32K
+	ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH =  96K
 	ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH =  32K
 	ram_sleep (rwx) : ORIGIN = 0x10088000, LENGTH = 8K
 }
--- a/firmware/common/LPC4330_M4_memory.ld
+++ b/firmware/common/LPC4330_M4_memory.ld
@ -26,8 +26,7 @@ MEMORY
 {
 	/* rom is really the shadow region that points to SPI flash or elsewhere */
 	rom (rx)  : ORIGIN = 0x00000000, LENGTH =  128K
-	ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH =  96K
-	ram_usb(rw) : ORIGIN = 0x10018000, LENGTH = 32K
+	ram_local1 (rwx) : ORIGIN = 0x10000000, LENGTH =  128K
 	ram_local2 (rwx) : ORIGIN = 0x10080000, LENGTH =  64K
 	ram_sleep (rwx) : ORIGIN = 0x10090000, LENGTH = 8K
 }
--- a/firmware/common/LPC43xx_M4_memory.ld
+++ b/firmware/common/LPC43xx_M4_memory.ld
@ -35,12 +35,11 @@ MEMORY
 	 * to get performance benefit of having two USB buffers addressable
 	 * simultaneously (on two different buses of the AHB multilayer matrix)
 	 */
-	ram_samp (rwx)     : ORIGIN = 0x20008000, LENGTH = 32K
+	ram_usb (rwx)     : ORIGIN = 0x20008000, LENGTH = 32K
 }

+usb_bulk_buffer = ORIGIN(ram_usb);
 lz4_in_buf = ORIGIN(ram_lz4_in);
 lz4_out_buf = ORIGIN(ram_lz4_out);
-usb_samp_buffer = ORIGIN(ram_samp);
-usb_bulk_buffer = ORIGIN(ram_usb);
 m0_state = ORIGIN(ram_shared);
 PROVIDE(__ram_m0_start__ = ORIGIN(ram_m0));
--- a/firmware/common/adc.c
+++ b/firmware/common/adc.c
@ -19,13 +19,10 @@
 * Boston, MA 02110-1301, USA.
 */

-#include <stdbool.h>
-
+#include "adc.h"
 #include <libopencm3/lpc43xx/adc.h>
 #include <libopencm3/lpc43xx/scu.h>

-#include "adc.h"
-
 uint16_t adc_read(uint8_t pin)
 {
 	bool alt_pin = (pin & 0x80);
--- a/firmware/common/adc.h
+++ b/firmware/common/adc.h
@ -19,9 +19,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __ADC_H__
+#define __ADC_H__

 #include <stdint.h>

 uint16_t adc_read(uint8_t pin);
 void adc_off(void);
+
+#endif // __ADC_H__
--- a/firmware/common/bitband.h
+++ b/firmware/common/bitband.h
@ -20,7 +20,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __BITBAND_H__
+#define __BITBAND_H__

 #include <stdint.h>

@ -36,3 +37,5 @@ void peripheral_bitband_clear(
 uint32_t peripheral_bitband_get(
 	volatile void* const peripheral_address,
 	const uint_fast8_t bit_number);
+
+#endif //__BITBAND_H__
--- a/firmware/common/clock_io.c
+++ b/firmware/common/clock_io.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2026 Great Scott Gadgets
+ * Copyright 2022 Great Scott Gadgets
 *
 * This file is part of HackRF.
 *
@ -19,27 +19,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#include "clock_io.h"
-
-#include <stdbool.h>
-#include <stdint.h>
-
+#include "gpdma.h"
 #include <libopencm3/lpc43xx/timer.h>
 #include <libopencm3/lpc43xx/scu.h>
 #include <libopencm3/lpc43xx/gima.h>
-#include <libopencm3/lpc43xx/gpdma.h>
 #include <libopencm3/lpc43xx/creg.h>
-
-#include "gpdma.h"
-#include "gpio.h"
-#include "platform_detect.h"
-#ifdef IS_NOT_PRALINE
-	#include "sgpio.h"
-#endif
-#ifdef IS_PRALINE
-	#include "fpga.h"
-	#include "platform_gpio.h"
-#endif
+#include <stdint.h>

 #define CLOCK_CYCLES_1_MS     (204000)
 #define MEASUREMENT_WINDOW_MS (50)
@ -124,47 +109,4 @@ void clkin_detect_init(void)
 uint32_t clkin_frequency(void)
 {
 	return TIMER2_CR3 * (1000 / MEASUREMENT_WINDOW_MS);
-}
-
-void trigger_enable(const bool enable)
-{
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		gpio_write(sgpio_config.gpio_trigger_enable, enable);
-	}
-#endif
-#ifdef IS_PRALINE
-	if (IS_PRALINE) {
-		fpga_set_trigger_enable(&fpga, enable);
-	}
-#endif
-}
-
-#ifdef IS_PRALINE
-void clkin_ctrl_set(const clkin_signal_t signal)
-{
-	gpio_write(platform_gpio()->clkin_ctrl, signal & 1);
-}
-
-void p1_ctrl_set(const p1_ctrl_signal_t signal)
-{
-	const platform_gpio_t* gpio = platform_gpio();
-
-	gpio_write(gpio->p1_ctrl0, signal & 1);
-	gpio_write(gpio->p1_ctrl1, (signal >> 1) & 1);
-	gpio_write(gpio->p1_ctrl2, (signal >> 2) & 1);
-}
-
-void p2_ctrl_set(const p2_ctrl_signal_t signal)
-{
-	const platform_gpio_t* gpio = platform_gpio();
-
-	gpio_write(gpio->p2_ctrl0, signal & 1);
-	gpio_write(gpio->p2_ctrl1, (signal >> 1) & 1);
-}
-
-void pps_out_set(const uint8_t value)
-{
-	gpio_write(platform_gpio()->pps_out, value & 1);
-}
-#endif
+};
--- a/firmware/common/da7219.h
+++ b/firmware/common/da7219.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2022 Great Scott Gadgets
 *
 * This file is part of HackRF.
 *
@ -19,10 +19,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __CLKIN_H__
+#define __CLKIN_H__

-#include <stdbool.h>
+#include <stdint.h>

-#define DA7219_ADDRESS 0x1A
+void clkin_detect_init(void);
+uint32_t clkin_frequency(void);

-bool da7219_detect(void);
+#endif //__CLKIN_H__
--- a/firmware/common/clock_gen.c
+++ b/firmware/common/clock_gen.c
@ -1,420 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#include "clock_gen.h"
-
-#include <stdint.h>
-
-#include "hackrf_ui.h"
-#include "platform_detect.h"
-#include "sgpio.h"
-#include "si5351c.h"
-#if defined(IS_HACKRF_ONE) || defined(IS_PRALINE)
-	#include "delay.h"
-	#include "portapack.h"
-#endif
-
-void clock_gen_init(void)
-{
-	si5351c_init(&si5351c);
-	si5351c_disable_all_outputs(&si5351c);
-	si5351c_disable_oeb_pin_control(&si5351c);
-	si5351c_power_down_all_clocks(&si5351c);
-	si5351c_set_crystal_configuration(&si5351c);
-	si5351c_enable_xo_and_ms_fanout(&si5351c);
-
-	/*
-	 * Clocks on HackRF One r9:
-	 *   CLK0 -> MAX5864/CPLD/SGPIO (sample clocks)
-	 *   CLK1 -> RFFC5072/MAX2839
-	 *   CLK2 -> External Clock Output/LPC43xx (power down at boot)
-	 *
-	 * Clocks on other platforms:
-	 *   CLK0 -> MAX5864/CPLD
-	 *   CLK1 -> CPLD
-	 *   CLK2 -> SGPIO
-	 *   CLK3 -> External Clock Output (power down at boot)
-	 *   CLK4 -> RFFC5072 (MAX2837 on rad1o)
-	 *   CLK5 -> MAX2837 (MAX2871 on rad1o)
-	 *   CLK6 -> none
-	 *   CLK7 -> LPC43xx (uses a 12MHz crystal by default)
-	 *
-	 * Clocks on Praline:
-	 *   CLK0 -> AFE_CLK (MAX5864/FPGA)
-	 *   CLK1 -> SCT_CLK
-	 *   CLK2 -> MCU_CLK (uses a 12MHz crystal by default)
-	 *   CLK3 -> External Clock Output (power down at boot)
-	 *   CLK4 -> XCVR_CLK (MAX2837)
-	 *   CLK5 -> MIX_CLK (RFFC5072)
-	 *   CLK6 -> AUX_CLK1
-	 *   CLK7 -> AUX_CLK2
-	 */
-
-#ifdef IS_H1_R9
-	if (IS_H1_R9) {
-		/* MS0/CLK0 is the reference for both RFFC5071 and MAX2839. */
-		si5351c_configure_multisynth(
-			&si5351c,
-			0,
-			20 * 128 - 512,
-			0,
-			1,
-			0); /* 800/20 = 40MHz */
-	}
-#endif
-#ifdef IS_NOT_H1_R9
-	if (IS_NOT_H1_R9) {
-		/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
-		si5351c_configure_multisynth(
-			&si5351c,
-			4,
-			20 * 128 - 512,
-			0,
-			1,
-			0); /* 800/20 = 40MHz */
-		/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
-		si5351c_configure_multisynth(
-			&si5351c,
-			5,
-			20 * 128 - 512,
-			0,
-			1,
-			0); /* 800/20 = 40MHz */
-	}
-#endif
-
-	/* MS6/CLK6 is unused. */
-	/* MS7/CLK7 is unused. */
-
-	/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
-	sample_rate_set(SR_FP_MHZ(10), true);
-
-	si5351c_configure_clock_control(&si5351c);
-	si5351c_change_input(&si5351c, SI5351C_INPUT_XTAL);
-	// soft reset
-	si5351c_reset_plls(&si5351c, SI5351C_PLL_MASK_BOTH);
-	si5351c_enable_clock_outputs(&si5351c);
-}
-
-void clock_gen_shutdown(void)
-{
-	si5351c_disable_all_outputs(&si5351c);
-	si5351c_disable_oeb_pin_control(&si5351c);
-	si5351c_power_down_all_clocks(&si5351c);
-}
-
-clock_source_t activate_best_clock_source(void)
-{
-#ifdef IS_EXPANSION_COMPATIBLE
-	if (IS_EXPANSION_COMPATIBLE) {
-		/* Ensure PortaPack reference oscillator is off while checking for external clock input. */
-		if (portapack_present()) {
-			portapack_reference_oscillator(false);
-		}
-	}
-#endif
-
-	clock_source_t source = CLOCK_SOURCE_HACKRF;
-
-	/* Check for external clock input. */
-	if (si5351c_clkin_signal_valid(&si5351c)) {
-		source = CLOCK_SOURCE_EXTERNAL;
-	} else {
-#ifdef IS_EXPANSION_COMPATIBLE
-		if (IS_EXPANSION_COMPATIBLE) {
-			/* Enable PortaPack reference oscillator (if present), and check for valid clock. */
-			if (portapack_present()) {
-				portapack_reference_oscillator(true);
-				delay_ms(18); // for oscillator to enable.
-				if (si5351c_clkin_signal_valid(&si5351c)) {
-					source = CLOCK_SOURCE_PORTAPACK;
-				} else {
-					portapack_reference_oscillator(false);
-				}
-			}
-		}
-#endif
-		/* No external or PortaPack clock was found. Use HackRF Si5351C crystal. */
-	}
-
-	si5351c_input_t input = (source == CLOCK_SOURCE_HACKRF) ? SI5351C_INPUT_XTAL :
-								  SI5351C_INPUT_CLKIN;
-	si5351c_change_input(&si5351c, input);
-
-	hackrf_ui()->set_clock_source(source);
-
-	return source;
-}
-
-/*
- * Closest fraction to m/d with denominator <= max_den.
- * Returns result in *r / *s with gcd(*r, *s) == 1 and 0 < *s <= max_den.
- * Straight port from CPython's fractions, and better documented there.
- */
-void limit_denominator(
-	uint64_t m,
-	uint64_t d,
-	const uint64_t max_den,
-	uint64_t* r,
-	uint64_t* s)
-{
-	if (d <= max_den) {
-		*r = m;
-		*s = d;
-		return;
-	}
-
-	uint64_t p0 = 0, q0 = 1, p1 = 1, q1 = 0;
-	uint64_t n = m, orig_d = d;
-	uint64_t tmp;
-
-	while (1) {
-		uint64_t a = n / d;
-		uint64_t q2 = q0 + a * q1;
-
-		if (q2 > max_den)
-			break;
-
-		tmp = p0 + a * p1;
-		p0 = p1;
-		q0 = q1;
-		p1 = tmp;
-		q1 = q2;
-
-		tmp = n - a * d;
-		n = d;
-		d = tmp;
-		if (d == 0)
-			break;
-	}
-
-	uint64_t k = (max_den - q0) / q1;
-
-	/* Return closer candidate. */
-	if (2 * d * (q0 + k * q1) <= orig_d) {
-		*r = p1;
-		*s = q1;
-	} else {
-		*r = p0 + k * p1;
-		*s = q0 + k * q1;
-	}
-}
-
-/*
- * Configure clock generator to produce sample clock in units of 1/(2**36) Hz.
- * Can be called with program=false for a dry run that returns the resultant
- * frequency without actually configuring the clock generator.
- *
- * The clock generator output frequency is:
- *
- * fs = 128 * vco / (512 + p1 + p2/p3))
- *
- * where p1, p2, and p3 are register values.
- *
- * For more information see:
- * https://www.pa3fwm.nl/technotes/tn42a-si5351-programming.html
- */
-fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
-{
-	const uint64_t vco_hz = 800 * 1000ULL * 1000ULL;
-	uint64_t p1, p2, p3;
-	uint64_t n, d, q1, q2, q3, r1, r2;
-	fp_28_36_t resultant_rate;
-
-	/*
-	 * First double the sample rate so that we can produce a clock at twice
-	 * the intended sample rate. The 2x clock is sometimes used directly,
-	 * and it is divided by two in an output divider to produce the actual
-	 * AFE clock.
-	 */
-	fp_28_36_t rate = sample_rate * 2;
-
-	/*
-	 * Computes p1 = (N << 36) / rate - 512, where N = 128 * vco_hz.
-	 *
-	 * Full numerator (N << 36) is 73 bits, so we split the division:
-	 *
-	 *   (N << 36) / rate = ((N << 27) / rate) << 9
-	 *                    + (((N << 27) % rate) << 9) / rate
-	 *
-	 * IMPORTANT: Assumes sample rate is in [200e3 << 36, 43.6e6 << 36].
-	 */
-	const uint64_t A = (128 * vco_hz) << 27;
-
-	q1 = A / rate;
-	r1 = A % rate;
-
-	// Remaining 9 bits with long division.
-	q2 = 0;
-	r2 = r1;
-	for (int j = 0; j < 9; j++) {
-		uint64_t msb = r2 >> 63;
-		r2 <<= 1;
-		q2 <<= 1;
-		if (msb || r2 >= rate) {
-			r2 -= rate;
-			q2 |= 1;
-		}
-	}
-
-	p1 = (q1 << 9) + q2 - 512;
-
-	if (r2) {
-		/* Use the remainder for the fractional part. */
-		n = r2;
-		d = rate;
-
-		/* Reduce fraction. */
-		const uint64_t p3_max = 0xfffff;
-		limit_denominator(n, d, p3_max, &p2, &p3);
-
-		/* Roll over to next p1 to enable integer mode. */
-		if (p2 >= p3) {
-			p1++;
-			p2 = 0;
-		}
-	} else {
-		p2 = 0;
-	}
-
-	/* Maximum: (128 * 2048) - 512 */
-	if (p1 > 0x3fe00) {
-		p1 = 0x3fe00;
-		p2 = 0;
-	}
-
-	if (p2 == 0) {
-		/* Use unity denominator for integer mode. */
-		p3 = 1;
-		n = (128 * vco_hz) << 18;
-		d = (p1 + 512);
-		q1 = n / d;
-		r1 = n % d;
-		q2 = ((r1 << 18) + (d / 2)) / d;
-		resultant_rate = (q1 << 18) + q2;
-	} else {
-		n = p3 * vco_hz * 128;
-		d = p3 * (p1 + 512) + p2;
-		q1 = n / d;
-		r1 = n % d;
-		q2 = (r1 << 18) / d;
-		r2 = (r1 << 18) % d;
-		q3 = ((r2 << 18) + (d / 2)) / d;
-		resultant_rate = (q1 << 36) + (q2 << 18) + q3;
-	}
-
-	/* Return MCU sample rate, not AFE clock rate. */
-	resultant_rate = (resultant_rate + 1) / 2;
-
-	if (!program) {
-		return resultant_rate;
-	}
-
-	bool streaming = sgpio_cpld_stream_is_enabled(&sgpio_config);
-
-	if (streaming) {
-		sgpio_cpld_stream_disable(&sgpio_config);
-	}
-
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		/* Integer mode can be enabled if p1 is even and p2 is zero. */
-		if (p1 & 0x1 || p2) {
-			si5351c_set_int_mode(&si5351c, 0, 0);
-		} else {
-			si5351c_set_int_mode(&si5351c, 0, 1);
-		}
-
-	#ifdef IS_H1_R9
-		if (IS_H1_R9) {
-			/*
-			 * On HackRF One r9 all sample clocks are externally derived
-			 * from MS1/CLK1 operating at twice the sample rate.
-			 */
-			si5351c_configure_multisynth(&si5351c, 1, p1, p2, p3, 0);
-		}
-	#endif
-	#ifdef IS_NOT_H1_R9
-		if (IS_NOT_H1_R9) {
-			/*
-			 * On other platforms the clock generator produces three
-			 * different sample clocks, all derived from multisynth 0.
-			 */
-			/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
-			si5351c_configure_multisynth(&si5351c, 0, p1, p2, p3, 1);
-
-			/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
-			si5351c_configure_multisynth(
-				&si5351c,
-				1,
-				0,
-				0,
-				0,
-				0); //p1 doesn't matter
-
-			/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
-			si5351c_configure_multisynth(
-				&si5351c,
-				2,
-				0,
-				0,
-				0,
-				0); //p1 doesn't matter
-		}
-	#endif
-	}
-#endif
-#ifdef IS_PRALINE
-	if (IS_PRALINE) {
-		/* MS0/CLK0 is the source for the MAX5864 (AFE_CLK). */
-		si5351c_configure_multisynth(&si5351c, 0, p1, p2, p3, 1);
-
-		/* MS1/CLK1 is the source for the FPGA (FPGA_CLK and SCT_CLK). */
-		si5351c_configure_multisynth(&si5351c, 1, p1, p2, p3, 1);
-
-		/* Delay FPGA_CLK relative to AFE_CLK. */
-		uint8_t phase_offset = 0;
-		if (p1 < 2100) {
-			phase_offset = (p1 >> 4) - 6;
-		}
-		si5351c_set_phase(&si5351c, 1, phase_offset);
-
-		if ((detected_revision() & ~BOARD_REV_GSG) < BOARD_REV_PRALINE_R1_1) {
-			/*
-			 * On older boards FPGA_CLK is on CLK2 while SCT_CLK is on
-			 * CLK1. We configure both so that behavior is consistent with
-			 * newer boards that use CLK1 for both FPGA_CLK and SCT_CLK.
-			 */
-			si5351c_configure_multisynth(&si5351c, 2, p1, p2, p3, 1);
-			si5351c_set_phase(&si5351c, 2, phase_offset);
-		}
-
-		/* Reset PLL to synchronize output clock phase. */
-		si5351c_reset_plls(&si5351c, SI5351C_PLL_MASK_A);
-	}
-#endif
-
-	if (streaming) {
-		sgpio_cpld_stream_enable(&sgpio_config);
-	}
-
-	return resultant_rate;
-}
--- a/firmware/common/clock_gen.h
+++ b/firmware/common/clock_gen.h
@ -1,47 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdbool.h>
-
-#include "fixed_point.h"
-
-typedef enum {
-	CLOCK_SOURCE_HACKRF = 0,
-	CLOCK_SOURCE_EXTERNAL = 1,
-	CLOCK_SOURCE_PORTAPACK = 2,
-} clock_source_t;
-
-void clock_gen_init(void);
-void clock_gen_shutdown(void);
-
-clock_source_t activate_best_clock_source(void);
-
-fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program);
-
-#ifdef __cplusplus
-}
-#endif
--- a/firmware/common/clock_io.h
+++ b/firmware/common/clock_io.h
@ -1,60 +0,0 @@
-/*
- * Copyright 2022-2026 Great Scott Gadgets
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#pragma once
-
-#include <stdbool.h>
-#include <stdint.h>
-
-void clkin_detect_init(void);
-uint32_t clkin_frequency(void);
-
-void trigger_enable(const bool enable);
-
-#ifdef IS_PRALINE
-typedef enum {
-	CLKIN_SIGNAL_P1 = 0,
-	CLKIN_SIGNAL_P22 = 1,
-} clkin_signal_t;
-
-typedef enum {
-	P1_SIGNAL_TRIGGER_IN = 0,
-	P1_SIGNAL_AUX_CLK1 = 1,
-	P1_SIGNAL_CLKIN = 2,
-	P1_SIGNAL_TRIGGER_OUT = 3,
-	P1_SIGNAL_P22_CLKIN = 4,
-	P1_SIGNAL_P2_5 = 5,
-	P1_SIGNAL_NC = 6,
-	P1_SIGNAL_AUX_CLK2 = 7,
-} p1_ctrl_signal_t;
-
-typedef enum {
-	P2_SIGNAL_CLK3 = 0,
-	P2_SIGNAL_TRIGGER_IN = 2,
-	P2_SIGNAL_TRIGGER_OUT = 3,
-} p2_ctrl_signal_t;
-
-void clkin_ctrl_set(const clkin_signal_t value);
-void p1_ctrl_set(const p1_ctrl_signal_t signal);
-void p2_ctrl_set(const p2_ctrl_signal_t signal);
-
-void pps_out_set(const uint8_t value);
-#endif
--- a/firmware/common/cpld_jtag.c
+++ b/firmware/common/cpld_jtag.c
@ -20,51 +20,17 @@
 */

 #include "cpld_jtag.h"
+#include "hackrf_core.h"
+#include "xapp058/micro.h"
+#include <libopencm3/lpc43xx/scu.h>
+#include <stdint.h>

-#include "platform_detect.h"
-#include "platform_gpio.h"
-#ifdef IS_NOT_PRALINE
-	#include <stdbool.h>
-	#include <stdint.h>
-	#include "xapp058/micro.h"
-	#include "cpld_xc2c.h"
-#endif
-
-#ifdef IS_NOT_PRALINE
+#ifndef PRALINE
 static refill_buffer_cb refill_buffer;
 static uint32_t xsvf_buffer_len, xsvf_pos;
 static unsigned char* xsvf_buffer;
 #endif

-/* Driver instance. */
-jtag_gpio_t jtag_gpio_cpld = {};
-
-jtag_t jtag_cpld = {
-	.gpio = &jtag_gpio_cpld,
-};
-
-void cpld_jtag_pin_setup(void)
-{
-	const platform_gpio_t* gpio = platform_gpio();
-
-	jtag_gpio_cpld.gpio_tck = gpio->cpld_tck;
-
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		jtag_gpio_cpld.gpio_tms = gpio->cpld_tms;
-		jtag_gpio_cpld.gpio_tdi = gpio->cpld_tdi;
-		jtag_gpio_cpld.gpio_tdo = gpio->cpld_tdo;
-	}
-#endif
-
-#ifdef IS_EXPANSION_COMPATIBLE
-	if (IS_EXPANSION_COMPATIBLE) {
-		jtag_gpio_cpld.gpio_pp_tms = gpio->cpld_pp_tms;
-		jtag_gpio_cpld.gpio_pp_tdo = gpio->cpld_pp_tdo;
-	}
-#endif
-}
-
 void cpld_jtag_take(jtag_t* const jtag)
 {
 	const jtag_gpio_t* const gpio = jtag->gpio;
@ -72,37 +38,25 @@ void cpld_jtag_take(jtag_t* const jtag)
 	/* Set initial GPIO state to the voltages of the internal or external pull-ups/downs,
 	 * to avoid any glitches.
 	 */
-#ifdef IS_EXPANSION_COMPATIBLE
-	if (IS_EXPANSION_COMPATIBLE) {
-		gpio_set(gpio->gpio_pp_tms);
-	}
+#if (defined HACKRF_ONE || defined PRALINE)
+	gpio_set(gpio->gpio_pp_tms);
 #endif
-
 	gpio_clear(gpio->gpio_tck);
-
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		gpio_set(gpio->gpio_tms);
-		gpio_set(gpio->gpio_tdi);
-	}
+#ifndef PRALINE
+	gpio_set(gpio->gpio_tms);
+	gpio_set(gpio->gpio_tdi);
 #endif

-#ifdef IS_EXPANSION_COMPATIBLE
-	if (IS_EXPANSION_COMPATIBLE) {
-		/* Do not drive PortaPack-specific TMS pin initially, just to be cautious. */
-		gpio_input(gpio->gpio_pp_tms);
-		gpio_input(gpio->gpio_pp_tdo);
-	}
+#if (defined HACKRF_ONE || defined PRALINE)
+	/* Do not drive PortaPack-specific TMS pin initially, just to be cautious. */
+	gpio_input(gpio->gpio_pp_tms);
+	gpio_input(gpio->gpio_pp_tdo);
 #endif
-
 	gpio_output(gpio->gpio_tck);
-
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		gpio_output(gpio->gpio_tms);
-		gpio_output(gpio->gpio_tdi);
-		gpio_input(gpio->gpio_tdo);
-	}
+#ifndef PRALINE
+	gpio_output(gpio->gpio_tms);
+	gpio_output(gpio->gpio_tdi);
+	gpio_input(gpio->gpio_tdo);
 #endif
 }

@ -113,26 +67,20 @@ void cpld_jtag_release(jtag_t* const jtag)
 	/* Make all pins inputs when JTAG interface not active.
 	 * Let the pull-ups/downs do the work.
 	 */
-#ifdef IS_EXPANSION_COMPATIBLE
-	if (IS_EXPANSION_COMPATIBLE) {
-		/* Do not drive PortaPack-specific pins, initially, just to be cautious. */
-		gpio_input(gpio->gpio_pp_tms);
-		gpio_input(gpio->gpio_pp_tdo);
-	}
+#if (defined HACKRF_ONE || defined PRALINE)
+	/* Do not drive PortaPack-specific pins, initially, just to be cautious. */
+	gpio_input(gpio->gpio_pp_tms);
+	gpio_input(gpio->gpio_pp_tdo);
 #endif
-
 	gpio_input(gpio->gpio_tck);
-
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		gpio_input(gpio->gpio_tms);
-		gpio_input(gpio->gpio_tdi);
-		gpio_input(gpio->gpio_tdo);
-	}
+#ifndef PRALINE
+	gpio_input(gpio->gpio_tms);
+	gpio_input(gpio->gpio_tdi);
+	gpio_input(gpio->gpio_tdo);
 #endif
 }

-#ifdef IS_NOT_PRALINE
+#ifndef PRALINE
 /* return 0 if success else return error code see xsvfExecute() */
 int cpld_jtag_program(
 	jtag_t* const jtag,
@ -163,16 +111,4 @@ unsigned char cpld_jtag_get_next_byte(void)
 	xsvf_pos++;
 	return byte;
 }
-
-bool cpld_jtag_sram_load(jtag_t* const jtag)
-{
-	cpld_jtag_take(jtag);
-	cpld_xc2c64a_jtag_sram_write(jtag, &cpld_hackrf_program_sram);
-	const bool success = cpld_xc2c64a_jtag_sram_verify(
-		jtag,
-		&cpld_hackrf_program_sram,
-		&cpld_hackrf_verify);
-	cpld_jtag_release(jtag);
-	return success;
-}
-#endif
+#endif
--- a/firmware/common/cpld_jtag.h
+++ b/firmware/common/cpld_jtag.h
@ -19,33 +19,32 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __CPLD_JTAG_H__
+#define __CPLD_JTAG_H__

-#include <stdbool.h>
 #include <stdint.h>

 #include "gpio.h"

-typedef struct {
+typedef struct jtag_gpio_t {
 	gpio_t gpio_tck;
-#ifdef IS_NOT_PRALINE
+#ifndef PRALINE
 	gpio_t gpio_tms;
 	gpio_t gpio_tdi;
 	gpio_t gpio_tdo;
 #endif
-#ifdef IS_EXPANSION_COMPATIBLE
+#if (defined HACKRF_ONE || defined PRALINE)
 	gpio_t gpio_pp_tms;
 	gpio_t gpio_pp_tdo;
 #endif
 } jtag_gpio_t;

-typedef struct {
+typedef struct jtag_t {
 	jtag_gpio_t* const gpio;
 } jtag_t;

 typedef void (*refill_buffer_cb)(void);

-void cpld_jtag_pin_setup(void);
 void cpld_jtag_take(jtag_t* const jtag);
 void cpld_jtag_release(jtag_t* const jtag);

@ -60,8 +59,5 @@ int cpld_jtag_program(
 	unsigned char* const buffer,
 	refill_buffer_cb refill);
 unsigned char cpld_jtag_get_next_byte(void);
-bool cpld_jtag_sram_load(jtag_t* const jtag);

-/* Driver instance. */
-extern jtag_gpio_t jtag_gpio_cpld;
-extern jtag_t jtag_cpld;
+#endif //__CPLD_JTAG_H__
--- a/firmware/common/cpld_xc2c.c
+++ b/firmware/common/cpld_xc2c.c
@ -22,10 +22,10 @@

 #include "cpld_xc2c.h"

-#include <string.h>
-
 #include "crc.h"
-#include "gpio.h"
+
+#include <stddef.h>
+#include <string.h>

 // clang-format off
 typedef enum {
--- a/firmware/common/cpld_xc2c.h
+++ b/firmware/common/cpld_xc2c.h
@ -20,10 +20,11 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __CPLD_XC2C_H__
+#define __CPLD_XC2C_H__

-#include <stdbool.h>
 #include <stdint.h>
+#include <stdbool.h>

 #include "cpld_jtag.h"

@ -68,3 +69,5 @@ bool cpld_xc2c64a_jtag_sram_verify(
 extern const cpld_xc2c64a_program_t cpld_hackrf_program_sram;
 extern const cpld_xc2c64a_verify_t cpld_hackrf_verify;
 extern const cpld_xc2c64a_row_addresses_t cpld_hackrf_row_addresses;
+
+#endif /*__CPLD_XC2C_H__*/
--- a/firmware/common/cpu_clock.c
+++ b/firmware/common/cpu_clock.c
@ -1,262 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#include "cpu_clock.h"
-
-#include <stdint.h>
-
-#include <libopencm3/lpc43xx/cgu.h>
-#if defined(IS_JAWBREAKER) || defined(IS_HACKRF_ONE) || defined(IS_PRALINE)
-	#include <libopencm3/lpc43xx/ccu.h>
-#endif
-
-#include "delay.h"
-#include "i2c_bus.h"
-#include "i2c_lpc.h"
-#include "si5351c.h"
-
-/* We start with the CPU clock at 96MHz */
-unsigned int cpu_clock_mhz = 96;
-
-/*
-Configure PLL1 (Main MCU Clock) to max speed (204MHz).
-Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1.
-This function shall be called after cpu_clock_init().
-*/
-static void cpu_clock_pll1_max_speed(void)
-{
-	uint32_t reg_val;
-
-	/* This function implements the sequence recommended in:
-	 * UM10503 Rev 2.4 (Aug 2018), section 13.2.1.1, page 167. */
-
-	/* 1. Select the IRC as BASE_M4_CLK source. */
-	reg_val = CGU_BASE_M4_CLK;
-	reg_val &= ~CGU_BASE_M4_CLK_CLK_SEL_MASK;
-	reg_val |= CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_IRC) | CGU_BASE_M4_CLK_AUTOBLOCK(1);
-	CGU_BASE_M4_CLK = reg_val;
-
-	/* CPU is now at 12MHz */
-	cpu_clock_mhz = 12;
-
-	/* 2. Enable the crystal oscillator. */
-	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
-
-	/* 3. Wait 250us. */
-	delay_us(250);
-
-	/* 4. Set the AUTOBLOCK bit. */
-	CGU_PLL1_CTRL |= CGU_PLL1_CTRL_AUTOBLOCK(1);
-
-	/* 5. Reconfigure PLL1 to produce the final output frequency, with the
-	 *    crystal oscillator as clock source. */
-	reg_val = CGU_PLL1_CTRL;
-	// clang-format off
-	reg_val &= ~( CGU_PLL1_CTRL_CLK_SEL_MASK |
-	              CGU_PLL1_CTRL_PD_MASK |
-	              CGU_PLL1_CTRL_FBSEL_MASK |
-	              CGU_PLL1_CTRL_BYPASS_MASK |
-	              CGU_PLL1_CTRL_DIRECT_MASK |
-	              CGU_PLL1_CTRL_PSEL_MASK |
-	              CGU_PLL1_CTRL_MSEL_MASK |
-	              CGU_PLL1_CTRL_NSEL_MASK );
-	/* Set PLL1 up to 12MHz * 17 = 204MHz.
-	 * Direct mode: FCLKOUT = FCCO = M*(FCLKIN/N) */
-	reg_val |= CGU_PLL1_CTRL_CLK_SEL(CGU_SRC_XTAL) |
-	           CGU_PLL1_CTRL_PSEL(0) |
-	           CGU_PLL1_CTRL_NSEL(0) |
-	           CGU_PLL1_CTRL_MSEL(16) |
-	           CGU_PLL1_CTRL_FBSEL(0) |
-	           CGU_PLL1_CTRL_DIRECT(1);
-	// clang-format on
-	CGU_PLL1_CTRL = reg_val;
-
-	/* 6. Wait for PLL1 to lock. */
-	while (!(CGU_PLL1_STAT & CGU_PLL1_STAT_LOCK_MASK)) {}
-
-	/* 7. Set the PLL1 P-divider to divide by 2 (DIRECT=0, PSEL=0). */
-	CGU_PLL1_CTRL &= ~CGU_PLL1_CTRL_DIRECT_MASK;
-
-	/* 8. Select PLL1 as BASE_M4_CLK source. */
-	reg_val = CGU_BASE_M4_CLK;
-	reg_val &= ~CGU_BASE_M4_CLK_CLK_SEL_MASK;
-	reg_val |= CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1);
-	CGU_BASE_M4_CLK = reg_val;
-
-	/* CPU is now at 102MHz */
-	cpu_clock_mhz = 102;
-
-	/* 9. Wait 50us. */
-	delay_us(50);
-
-	/* 10. Set the PLL1 P-divider to direct output mode (DIRECT=1). */
-	CGU_PLL1_CTRL |= CGU_PLL1_CTRL_DIRECT_MASK;
-
-	/* CPU is now at 204MHz */
-	cpu_clock_mhz = 204;
-}
-
-/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
-Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
-void cpu_clock_init(void)
-{
-	/* use IRC as clock source for APB1 (including I2C0) */
-	CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
-
-	/* use IRC as clock source for APB3 */
-	CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
-
-	//FIXME disable I2C
-	/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
-	i2c_bus_start(si5351c.bus, &i2c_config_fast_clock);
-
-	/*
-	 * 12MHz clock is entering LPC XTAL1/OSC input now.
-	 * On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
-	 * Set up PLL1 to run from XTAL1 input.
-	 */
-
-	//FIXME a lot of the details here should be in a CGU driver
-
-	/* set xtal oscillator to low frequency mode */
-	CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
-
-	cpu_clock_pll1_max_speed();
-
-	/* use XTAL_OSC as clock source for APB1 */
-	CGU_BASE_APB1_CLK =
-		CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
-
-	/* use XTAL_OSC as clock source for APB3 */
-	CGU_BASE_APB3_CLK =
-		CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
-
-	/* use XTAL_OSC as clock source for PLL0USB */
-	CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1) | CGU_PLL0USB_CTRL_AUTOBLOCK(1) |
-		CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
-	while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK) {}
-
-	/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
-	/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
-	CGU_PLL0USB_MDIV = 0x06167FFA;
-	CGU_PLL0USB_NP_DIV = 0x00302062;
-	CGU_PLL0USB_CTRL |=
-		(CGU_PLL0USB_CTRL_PD(1) | CGU_PLL0USB_CTRL_DIRECTI(1) |
-		 CGU_PLL0USB_CTRL_DIRECTO(1) | CGU_PLL0USB_CTRL_CLKEN(1));
-
-	/* power on PLL0USB and wait until stable */
-	CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
-	while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK)) {}
-
-	/* use PLL0USB as clock source for USB0 */
-	CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1) |
-		CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
-
-	/* Switch peripheral clock over to use PLL1 (204MHz) */
-	CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1) |
-		CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	/* Switch APB1 clock over to use PLL1 (204MHz) */
-	CGU_BASE_APB1_CLK =
-		CGU_BASE_APB1_CLK_AUTOBLOCK(1) | CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	/* Switch APB3 clock over to use PLL1 (204MHz) */
-	CGU_BASE_APB3_CLK =
-		CGU_BASE_APB3_CLK_AUTOBLOCK(1) | CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	CGU_BASE_SSP0_CLK =
-		CGU_BASE_SSP0_CLK_AUTOBLOCK(1) | CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-	CGU_BASE_SSP1_CLK =
-		CGU_BASE_SSP1_CLK_AUTOBLOCK(1) | CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
-
-#ifdef IS_NOT_RAD1O
-	if (IS_NOT_RAD1O) {
-		/* Disable unused clocks */
-		/* Start with PLLs */
-		CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);
-
-		/* Dividers */
-		CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1);
-		CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1);
-		CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
-		CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
-		CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
-
-		/* Base clocks */
-		CGU_BASE_SPIFI_CLK =
-			CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */
-		CGU_BASE_USB1_CLK =
-			CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */
-		CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
-		CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
-		CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
-		CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
-		CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
-		CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
-		CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
-		CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
-		CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
-		CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
-		CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
-		CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
-		CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
-
-		/* Disable unused peripheral clocks */
-		CCU1_CLK_APB1_CAN1_CFG = 0;
-		CCU1_CLK_APB1_I2S_CFG = 0;
-		CCU1_CLK_APB1_MOTOCONPWM_CFG = 0;
-		//CCU1_CLK_APB3_ADC0_CFG = 0;
-		CCU1_CLK_APB3_ADC1_CFG = 0;
-		CCU1_CLK_APB3_CAN0_CFG = 0;
-		CCU1_CLK_APB3_DAC_CFG = 0;
-		//CCU1_CLK_M4_DMA_CFG = 0;
-		CCU1_CLK_M4_EMC_CFG = 0;
-		CCU1_CLK_M4_EMCDIV_CFG = 0;
-		CCU1_CLK_M4_ETHERNET_CFG = 0;
-		CCU1_CLK_M4_LCD_CFG = 0;
-		CCU1_CLK_M4_QEI_CFG = 0;
-		CCU1_CLK_M4_RITIMER_CFG = 0;
-		// CCU1_CLK_M4_SCT_CFG = 0;
-		CCU1_CLK_M4_SDIO_CFG = 0;
-		CCU1_CLK_M4_SPIFI_CFG = 0;
-		CCU1_CLK_M4_TIMER0_CFG = 0;
-		//CCU1_CLK_M4_TIMER1_CFG = 0;
-		//CCU1_CLK_M4_TIMER2_CFG = 0;
-		CCU1_CLK_M4_TIMER3_CFG = 0;
-		CCU1_CLK_M4_UART1_CFG = 0;
-		CCU1_CLK_M4_USART0_CFG = 0;
-		CCU1_CLK_M4_USART2_CFG = 0;
-		CCU1_CLK_M4_USART3_CFG = 0;
-		CCU1_CLK_M4_USB1_CFG = 0;
-		CCU1_CLK_M4_VADC_CFG = 0;
-		// CCU1_CLK_SPIFI_CFG = 0;
-		// CCU1_CLK_USB1_CFG = 0;
-		// CCU1_CLK_VADC_CFG = 0;
-		// CCU2_CLK_APB0_UART1_CFG = 0;
-		// CCU2_CLK_APB0_USART0_CFG = 0;
-		// CCU2_CLK_APB2_USART2_CFG = 0;
-		// CCU2_CLK_APB2_USART3_CFG = 0;
-		// CCU2_CLK_APLL_CFG = 0;
-		// CCU2_CLK_SDIO_CFG = 0;
-	}
-#endif
-}
--- a/firmware/common/cpu_clock.h
+++ b/firmware/common/cpu_clock.h
@ -1,35 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void cpu_clock_init(void);
-
-// Current clock speed in MHz, updated on clock changes.
-extern unsigned int cpu_clock_mhz;
-
-#ifdef __cplusplus
-}
-#endif
--- a/firmware/common/crc.h
+++ b/firmware/common/crc.h
@ -20,10 +20,11 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __CRC_H__
+#define __CRC_H__

-#include <stddef.h>
 #include <stdint.h>
+#include <stddef.h>

 typedef struct {
 	uint32_t remainder;
@ -34,3 +35,5 @@ typedef struct {
 void crc32_init(crc32_t* const crc);
 void crc32_update(crc32_t* const crc, const uint8_t* const data, const size_t byte_count);
 uint32_t crc32_digest(const crc32_t* const crc);
+
+#endif //__CRC_H__
--- a/firmware/common/da7219.c
+++ b/firmware/common/da7219.c
@ -1,46 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#include <stdint.h>
-
-#include "da7219.h"
-#include "i2c_bus.h"
-#include "i2c_lpc.h"
-
-#define DA7219_REG_CHIP_ID1 0x81
-#define DA7219_REG_CHIP_ID2 0x82
-
-i2c_bus_t* const da7219_bus = &i2c0;
-
-uint8_t da7219_read_reg(i2c_bus_t* const bus, uint8_t reg)
-{
-	const uint8_t data_tx[] = {reg};
-	uint8_t data_rx[] = {0x00};
-	i2c_bus_transfer(bus, DA7219_ADDRESS, data_tx, 1, data_rx, 1);
-	return data_rx[0];
-}
-
-bool da7219_detect(void)
-{
-	uint8_t chip_id1 = da7219_read_reg(da7219_bus, DA7219_REG_CHIP_ID1);
-	uint8_t chip_id2 = da7219_read_reg(da7219_bus, DA7219_REG_CHIP_ID2);
-	return (chip_id1 == 0x23) && (chip_id2 == 0x93);
-}
--- a/firmware/common/delay.c
+++ b/firmware/common/delay.c
@ -21,9 +21,16 @@

 #include "delay.h"

-#include "cpu_clock.h"
+void delay(uint32_t duration)
+{
+	uint32_t i;

-static void delay_us_at_mhz(uint32_t us, uint32_t mhz)
+	for (i = 0; i < duration; i++) {
+		__asm__("nop");
+	}
+}
+
+void delay_us_at_mhz(uint32_t us, uint32_t mhz)
 {
 #if defined(LPC43XX_M4)
 	// The loop below takes 3 cycles per iteration.
@ -45,13 +52,3 @@ static void delay_us_at_mhz(uint32_t us, uint32_t mhz)
 	#error "No delay loop implementation"
 #endif
 }
-
-void delay_us(uint32_t us)
-{
-	delay_us_at_mhz(us, cpu_clock_mhz);
-}
-
-void delay_ms(uint32_t ms)
-{
-	delay_us_at_mhz(ms * 1000, cpu_clock_mhz);
-}
--- a/firmware/common/delay.h
+++ b/firmware/common/delay.h
@ -19,7 +19,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __DELAY_H
+#define __DELAY_H

 #ifdef __cplusplus
 extern "C" {
@ -27,9 +28,7 @@ extern "C" {

 #include <stdint.h>

-void delay_us(uint32_t us);
-void delay_ms(uint32_t ms);
+void delay(uint32_t duration);
+void delay_us_at_mhz(uint32_t us, uint32_t mhz);

-#ifdef __cplusplus
-}
-#endif
+#endif /* __DELAY_H */
--- a/firmware/common/fault_handler.c
+++ b/firmware/common/fault_handler.c
@ -21,10 +21,10 @@
 * Boston, MA 02110-1301, USA.
 */

-#include "fault_handler.h"
-
 #include <stdint.h>

+#include "fault_handler.h"
+
 typedef struct {
 	uint32_t r0;
 	uint32_t r1;
--- a/firmware/common/fault_handler.h
+++ b/firmware/common/fault_handler.h
@ -20,7 +20,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __FAULT_HANDLER__
+#define __FAULT_HANDLER__

 #include <stdint.h>

@ -29,7 +30,9 @@
 // TODO: Move all this to a Cortex-M(?) include file, since these
 // structures are supposedly the same between processors (to an
 // undetermined extent).
-typedef struct {
+typedef struct armv7m_scb_t armv7m_scb_t;
+
+struct armv7m_scb_t {
 	volatile const uint32_t CPUID;
 	volatile uint32_t ICSR;
 	volatile uint32_t VTOR;
@ -61,10 +64,12 @@ typedef struct {
 	volatile const uint32_t ID_ISAR4;
 	volatile const uint32_t __reserved_0x74_0x87[5];
 	volatile uint32_t CPACR;
-} __attribute__((packed)) armv7m_scb_t;
+} __attribute__((packed));

 static armv7m_scb_t* const SCB = (armv7m_scb_t*) SCB_BASE;

 #define SCB_HFSR_DEBUGEVT (1 << 31)
 #define SCB_HFSR_FORCED   (1 << 30)
 #define SCB_HFSR_VECTTBL  (1 << 1)
+
+#endif //__FAULT_HANDLER__
--- a/firmware/common/firmware_info.c
+++ b/firmware/common/firmware_info.c
@ -21,6 +21,11 @@

 #include "firmware_info.h"
 #include "platform_detect.h"
+#include "gpio_lpc.h"
+#include "hackrf_core.h"
+
+#include <libopencm3/lpc43xx/scu.h>
+#include <libopencm3/lpc43xx/adc.h>

 #ifdef JAWBREAKER
 	#define SUPPORTED_PLATFORM PLATFORM_JAWBREAKER
@ -30,9 +35,6 @@
 	#define SUPPORTED_PLATFORM PLATFORM_RAD1O
 #elif PRALINE
 	#define SUPPORTED_PLATFORM PLATFORM_PRALINE
-#elif UNIVERSAL
-	#define SUPPORTED_PLATFORM \
-		(PLATFORM_PRALINE | PLATFORM_HACKRF1_OG | PLATFORM_HACKRF1_R9)
 #else
 	#define SUPPORTED_PLATFORM 0
 #endif
--- a/firmware/common/firmware_info.h
+++ b/firmware/common/firmware_info.h
@ -19,7 +19,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef FIRMWARE_INFO_H
+#define FIRMWARE_INFO_H

 #include <stdint.h>

@ -32,3 +33,5 @@ struct firmware_info_t {
 } __attribute__((packed, aligned(1)));

 extern const struct firmware_info_t firmware_info;
+
+#endif
--- a/firmware/common/fixed_point.h
+++ b/firmware/common/fixed_point.h
@ -19,9 +19,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
-
-#include <stdint.h>
+#ifndef __FIXED_POINT_H__
+#define __FIXED_POINT_H__

 /* 40.24 fixed-point */
 typedef uint64_t fp_40_24_t;
@ -29,45 +28,7 @@ typedef uint64_t fp_40_24_t;
 /* one million in 40.24 fixed-point */
 #define FP_ONE_MHZ ((1000ULL * 1000ULL) << 24)

-/* one thousand in 40.24 fixed-point */
-#define FP_ONE_KHZ ((1000ULL) << 24)
-
 /* one in 40.24 fixed-point */
 #define FP_ONE_HZ (1 << 24)

-#define FP_MHZ(mhz) (mhz##ULL * FP_ONE_MHZ)
-#define FP_KHZ(khz) (khz##ULL * FP_ONE_KHZ)
-#define FP_HZ(hz)   (hz##ULL * FP_ONE_HZ)
-
-/* 28.36 fixed-point */
-typedef uint64_t fp_28_36_t;
-
-/* one million in 28.36 fixed-point */
-#define SR_FP_ONE_MHZ ((1000ULL * 1000ULL) << 36)
-
-/* one thousand in 28.36 fixed-point */
-#define SR_FP_ONE_KHZ (1000ULL << 36)
-
-/* one in 28.36 fixed-point */
-#define SR_FP_ONE_HZ (1ULL << 36)
-
-#define SR_FP_MHZ(mhz) (mhz##ULL * SR_FP_ONE_MHZ)
-#define SR_FP_KHZ(khz) (khz##ULL * SR_FP_ONE_KHZ)
-#define SR_FP_HZ(hz)   (hz##ULL * SR_FP_ONE_HZ)
-
-/* 1.63 fixed point */
-typedef uint64_t fp_1_63_t;
-
-#define FRAC_ONE (1ULL << 63)
-
-/* one hundredth in 1.63 fixed point */
-#define FRAC_ONE_PERCENT (FRAC_ONE / (100ULL))
-
-/* one thousandth in 1.63 fixed point */
-#define FRAC_ONE_PERMILLE (FRAC_ONE / (1000ULL))
-
-/* one millionth in 1.63 fixed point */
-#define FRAC_ONE_PPM (FRAC_ONE / (1000000ULL))
-
-/* one billionth in 1.63 fixed point */
-#define FRAC_ONE_PPB (FRAC_ONE / (1000000000ULL))
+#endif /*__FIXED_POINT_H__*/
--- a/firmware/common/fpga.c
+++ b/firmware/common/fpga.c
@ -19,24 +19,19 @@
 * Boston, MA 02110-1301, USA.
 */

+#include <stdbool.h>
+#include "hackrf_core.h"
+#include "ice40_spi.h"
 #include "fpga.h"
 #include "fpga_regs.def"

-#include <stdbool.h>
-
-#include "ice40_spi.h"
-
-/* Driver instance. */
-fpga_driver_t fpga = {
-	.bus = &ice40,
-};
-
 /* Set up all registers according to the loaded bitstream's defaults. */
 void fpga_init(fpga_driver_t* const drv)
 {
 	// Standard bitstream default register values.
 	set_FPGA_STANDARD_CTRL_DC_BLOCK(drv, true);
-	set_FPGA_STANDARD_RX_PSTEP(drv, 0);
+	set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_EN(drv, false);
+	set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_UP(drv, false);
 	set_FPGA_STANDARD_CTRL_PRBS(drv, false);
 	set_FPGA_STANDARD_CTRL_TRIGGER_EN(drv, false);
 	set_FPGA_STANDARD_TX_CTRL(drv, 0);
@ -56,7 +51,9 @@ void fpga_setup(fpga_driver_t* const drv)
 uint8_t fpga_reg_read(fpga_driver_t* const drv, uint8_t r)
 {
 	uint8_t v;
+	ssp1_set_mode_ice40();
 	v = ice40_spi_read(drv->bus, r);
+	ssp1_set_mode_max283x();
 	drv->regs[r] = v;
 	return v;
 }
@ -64,7 +61,9 @@ uint8_t fpga_reg_read(fpga_driver_t* const drv, uint8_t r)
 void fpga_reg_write(fpga_driver_t* const drv, uint8_t r, uint8_t v)
 {
 	drv->regs[r] = v;
+	ssp1_set_mode_ice40();
 	ice40_spi_write(drv->bus, r, v);
+	ssp1_set_mode_max283x();
 	FPGA_REG_SET_CLEAN(drv, r);
 }

@ -106,7 +105,8 @@ void fpga_set_rx_quarter_shift_mode(
 	fpga_driver_t* const drv,
 	const fpga_quarter_shift_mode_t mode)
 {
-	set_FPGA_STANDARD_RX_PSTEP(drv, (mode & 0b11) << 6);
+	set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_EN(drv, (mode >> 0) & 0b1);
+	set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_UP(drv, (mode >> 1) & 0b1);
 	fpga_regs_commit(drv);
 }

--- a/firmware/common/fpga.h
+++ b/firmware/common/fpga.h
@ -19,15 +19,14 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __FPGA_H
+#define __FPGA_H

 #include <stdbool.h>
-#include <stdint.h>
-
 #include "ice40_spi.h"

-/* Up to 7 registers, each containing up to 8 bits of data */
-#define FPGA_NUM_REGS            7
+/* Up to 6 registers, each containing up to 8 bits of data */
+#define FPGA_NUM_REGS            6
 #define FPGA_DATA_REGS_MAX_VALUE 255

 typedef enum {
@ -36,23 +35,13 @@ typedef enum {
 	FPGA_QUARTER_SHIFT_MODE_DOWN = 0b01,
 } fpga_quarter_shift_mode_t;

-typedef struct {
+struct fpga_driver_t;
+typedef struct fpga_driver_t fpga_driver_t;
+
+struct fpga_driver_t {
 	ice40_spi_driver_t* bus;
 	uint8_t regs[FPGA_NUM_REGS];
 	uint8_t regs_dirty;
-} fpga_driver_t;
-
-struct fpga_loader_t {
-	/* Start address added as an offset to all read() calls. */
-	uint32_t start_addr;
-	/* Any one-off setup needed before calling read(). May be NULL. */
-	void (*setup)(void);
-	/* Read data from the specified address. */
-	void (*read)(uint32_t addr, uint32_t len, uint8_t* const data);
-	/* Buffer to use for compressed data (4096 bytes). */
-	uint8_t* in_buffer;
-	/* Buffer to use for decompressed data (4096 bytes). */
-	uint8_t* out_buffer;
 };

 /* Initialize the loaded bitstream's registers to their default values. */
@ -86,10 +75,9 @@ void fpga_set_prbs_enable(fpga_driver_t* const drv, const bool enable);
 void fpga_set_tx_nco_enable(fpga_driver_t* const drv, const bool enable);
 void fpga_set_tx_nco_pstep(fpga_driver_t* const drv, const uint8_t phase_increment);

-bool fpga_image_load(struct fpga_loader_t* loader, unsigned int index);
+bool fpga_image_load(unsigned int index);
 bool fpga_spi_selftest(void);
 bool fpga_sgpio_selftest(void);
 bool fpga_if_xcvr_selftest(void);

-/* Driver instance. */
-extern fpga_driver_t fpga;
+#endif // __FPGA_H
--- a/firmware/common/fpga_image.c
+++ b/firmware/common/fpga_image.c
@ -19,34 +19,33 @@
 * Boston, MA 02110-1301, USA.
 */

-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "fpga.h"
-#include "ice40_spi.h"
+#include "hackrf_core.h"
 #include "lz4_blk.h"
+#include "lz4_buf.h"
 #include "selftest.h"

+// FPGA bitstreams blob.
+extern uint32_t _binary_fpga_bin_start;
+extern uint32_t _binary_fpga_bin_end;
+extern uint32_t _binary_fpga_bin_size;
+
 struct fpga_image_read_ctx {
-	struct fpga_loader_t* loader;
 	uint32_t addr;
 	size_t next_block_sz;
 	uint8_t init_flag;
 };

-static size_t fpga_image_read_block_cb(void* _ctx)
+static size_t fpga_image_read_block_cb(void* _ctx, uint8_t* out_buffer)
 {
 	// Assume out_buffer is 4KB
 	struct fpga_image_read_ctx* ctx = _ctx;
-	struct fpga_loader_t* loader = ctx->loader;
 	size_t block_sz = ctx->next_block_sz;

 	uint8_t block_sz_buf[2];

 	// first iteration: read first block size
 	if (ctx->init_flag == 0) {
-		loader->read(ctx->addr, 2, block_sz_buf);
+		w25q80bv_read(&spi_flash, ctx->addr, 2, block_sz_buf);
 		block_sz = block_sz_buf[0] | block_sz_buf[1] << 8;
 		ctx->addr += 2;
 		ctx->init_flag = 1;
@ -57,43 +56,51 @@ static size_t fpga_image_read_block_cb(void* _ctx)
 		return 0;

 	// Read compressed block (and the next block size) from flash.
-	loader->read(ctx->addr, block_sz, loader->in_buffer);
+	w25q80bv_read(&spi_flash, ctx->addr, block_sz, lz4_in_buf);
 	ctx->addr += block_sz;
-	loader->read(ctx->addr, 2, block_sz_buf);
+	w25q80bv_read(&spi_flash, ctx->addr, 2, block_sz_buf);
 	ctx->next_block_sz = block_sz_buf[0] | block_sz_buf[1] << 8;
 	ctx->addr += 2;

 	// Decompress block.
-	return lz4_blk_decompress(loader->in_buffer, loader->out_buffer, block_sz);
+	return lz4_blk_decompress(lz4_in_buf, out_buffer, block_sz);
 }

-bool fpga_image_load(struct fpga_loader_t* loader, unsigned int index)
+bool fpga_image_load(unsigned int index)
 {
+#if defined(DFU_MODE) || defined(RAM_MODE)
+	selftest.fpga_image_load = SKIPPED;
+	selftest.report.pass = false;
+	return false;
+#endif
+
 	// TODO: do SPI setup and read number of bitstreams once!
-	if (loader->setup != NULL)
-		loader->setup();
+
+	// Prepare for SPI flash access.
+	spi_bus_start(spi_flash.bus, &ssp_config_w25q80bv);
+	w25q80bv_setup(&spi_flash);

 	// Read number of bitstreams from flash.
 	// Check the bitstream exists, and extract its offset.
-	uint32_t addr = loader->start_addr;
+	uint32_t addr = (uint32_t) &_binary_fpga_bin_start;
 	uint32_t num_bitstreams, bitstream_offset;
-	loader->read(addr, 4, (uint8_t*) &num_bitstreams);
+	w25q80bv_read(&spi_flash, addr, 4, (uint8_t*) &num_bitstreams);
 	if (index >= num_bitstreams)
 		return false;
-	loader->read(addr + 4 * (index + 1), 4, (uint8_t*) &bitstream_offset);
+	w25q80bv_read(&spi_flash, addr + 4 * (index + 1), 4, (uint8_t*) &bitstream_offset);

 	// A callback function is used by the FPGA programmer
 	// to obtain consecutive gateware chunks.
 	ice40_spi_target_init(&ice40);
+	ssp1_set_mode_ice40();
 	struct fpga_image_read_ctx fpga_image_ctx = {
-		.loader = loader,
-		.addr = loader->start_addr + bitstream_offset,
+		.addr = (uint32_t) &_binary_fpga_bin_start + bitstream_offset,
 	};
 	const bool success = ice40_spi_syscfg_program(
 		&ice40,
-		loader->out_buffer,
 		fpga_image_read_block_cb,
 		&fpga_image_ctx);
+	ssp1_set_mode_max283x();

 	// Update selftest result.
 	selftest.fpga_image_load = success ? PASSED : FAILED;
--- a/firmware/common/fpga_regs.def
+++ b/firmware/common/fpga_regs.def
@ -1,7 +1,7 @@
 /* -*- mode: c -*-
 *
 * Copyright 2012 Michael Ossmann
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
 *
 * This file is part of HackRF.
 *
@ -21,7 +21,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __FPGA_REGS_DEF
+#define __FPGA_REGS_DEF

 #define FPGA_REG_SET_CLEAN(_d, _r) (_d->regs_dirty &= ~(1UL<<_r))
 #define FPGA_REG_SET_DIRTY(_d, _r) (_d->regs_dirty |= (1UL<<_r))
@ -52,21 +53,22 @@ const uint8_t n = r;
 /* REG 01 (1): CTRL */
 __MREG__(FPGA_STANDARD_CTRL, 1, 0, 8)
 __MREG__(FPGA_STANDARD_CTRL_DC_BLOCK, 1, 0, 1)
+__MREG__(FPGA_STANDARD_CTRL_QUARTER_SHIFT_EN, 1, 1, 1)
+__MREG__(FPGA_STANDARD_CTRL_QUARTER_SHIFT_UP, 1, 2, 1)
 __MREG__(FPGA_STANDARD_CTRL_PRBS, 1, 6, 1)
 __MREG__(FPGA_STANDARD_CTRL_TRIGGER_EN, 1, 7, 1)

 /* REG 02 (2): RX_DECIM */
 __MREG__(FPGA_STANDARD_RX_DECIM, 2, 0, 3)

-/* REG 03 (3): RX_PSTEP */
-__MREG__(FPGA_STANDARD_RX_PSTEP, 3, 0, 8)
+/* REG 03 (3): TX_CTRL */
+__MREG__(FPGA_STANDARD_TX_CTRL, 3, 0, 1)
+__MREG__(FPGA_STANDARD_TX_CTRL_NCO_EN, 3, 0, 1)

-/* REG 04 (4): TX_CTRL */
-__MREG__(FPGA_STANDARD_TX_CTRL, 4, 0, 1)
-__MREG__(FPGA_STANDARD_TX_CTRL_NCO_EN, 4, 0, 1)
+/* REG 04 (4): TX_INTRP */
+__MREG__(FPGA_STANDARD_TX_INTRP, 4, 0, 3)

-/* REG 05 (5): TX_INTRP */
-__MREG__(FPGA_STANDARD_TX_INTRP, 5, 0, 3)
+/* REG 05 (5): TX_PSTEP */
+__MREG__(FPGA_STANDARD_TX_PSTEP, 5, 0, 8)

-/* REG 06 (6): TX_PSTEP */
-__MREG__(FPGA_STANDARD_TX_PSTEP, 6, 0, 8)
+#endif // __FPGA_REGS_DEF
--- a/firmware/common/fpga_selftest.c
+++ b/firmware/common/fpga_selftest.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
 *
 * This file is part of HackRF.
 *
@ -19,25 +19,16 @@
 * Boston, MA 02110-1301, USA.
 */

-#include <stdbool.h>
-#include <stddef.h>
-#include <stdint.h>
-
-#include "clock_gen.h"
-#include "delay.h"
-#include "fixed_point.h"
-#include "fpga.h"
-#include "ice40_spi.h"
+#include "hackrf_core.h"
 #include "m0_state.h"
-#include "max283x.h"
-#include "rf_path.h"
-#include "selftest.h"
-#include "sgpio.h"
 #include "streaming.h"
+#include "selftest.h"
+#include "fpga.h"
+#include "delay.h"

 // USB buffer used during selftests.
-#define USB_SAMP_BUFFER_SIZE 0x8000
-extern uint8_t usb_samp_buffer[USB_SAMP_BUFFER_SIZE];
+#define USB_BULK_BUFFER_SIZE 0x8000
+extern uint8_t usb_bulk_buffer[USB_BULK_BUFFER_SIZE];

 static int rx_samples(const unsigned int num_samples, uint32_t max_cycles)
 {
@ -69,10 +60,12 @@ bool fpga_spi_selftest(void)
 	}

 	// Test writing a register and reading it back.
-	uint8_t reg = 6;
+	uint8_t reg = 5;
 	uint8_t write_value = 0xA5;
+	ssp1_set_mode_ice40();
 	ice40_spi_write(&ice40, reg, write_value);
 	uint8_t read_value = ice40_spi_read(&ice40, reg);
+	ssp1_set_mode_max283x();

 	// Update selftest result.
 	selftest.fpga_spi = (read_value == write_value) ? PASSED : FAILED;
@ -112,10 +105,10 @@ bool fpga_sgpio_selftest(void)
 	fpga_set_prbs_enable(&fpga, false);

 	// Generate sequence from first value and compare.
-	bool seq_in_sync = (usb_samp_buffer[0] != 0);
-	uint8_t seq = lfsr_advance(usb_samp_buffer[0]);
+	bool seq_in_sync = (usb_bulk_buffer[0] != 0);
+	uint8_t seq = lfsr_advance(usb_bulk_buffer[0]);
 	for (int i = 1; i < 512; ++i) {
-		if (usb_samp_buffer[i] != seq) {
+		if (usb_bulk_buffer[i] != seq) {
 			seq_in_sync = false;
 			break;
 		}
@ -186,64 +179,64 @@ bool fpga_if_xcvr_selftest(void)
 		return false;
 	}

-	const size_t num_samples = USB_SAMP_BUFFER_SIZE / 2;
+	const size_t num_samples = USB_BULK_BUFFER_SIZE / 2;

 	// Set common RX path and gateware settings for the measurements.
 	fpga_set_tx_nco_pstep(&fpga, 64);    // NCO phase increment
 	fpga_set_tx_nco_enable(&fpga, true); // TX enable
 	rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_RX_CALIBRATION);
-	max283x_set_lna_gain(&max283x, 16);
-	max283x_set_vga_gain(&max283x, 36);
-	max283x_set_frequency(&max283x, FP_MHZ(2500), true);
+	max2831_set_lna_gain(&max283x, 16);
+	max2831_set_vga_gain(&max283x, 36);
+	max2831_set_frequency(&max283x, 2500000000);

 	// Capture 1: 4 Msps, tone at 0.5 MHz, narrowband filter OFF
-	sample_rate_set(SR_FP_MHZ(4), true);
-	delay_ms(1);
+	sample_rate_set(4ULL * FP_ONE_MHZ, true);
+	delay_us_at_mhz(1000, 204);
 	if (rx_samples(num_samples, 2000000) == -1) {
 		timeout = true;
 	}
 	measure_tone(
-		(int8_t*) usb_samp_buffer,
+		(int8_t*) usb_bulk_buffer,
 		num_samples,
 		&selftest.xcvr_measurements[0]);

 	// Capture 2: 4 Msps, tone at 0.5 MHz, narrowband filter ON
 	narrowband_filter_set(1);
-	delay_ms(1);
+	delay_us_at_mhz(1000, 204);
 	if (rx_samples(num_samples, 2000000) == -1) {
 		timeout = true;
 	}
 	measure_tone(
-		(int8_t*) usb_samp_buffer,
+		(int8_t*) usb_bulk_buffer,
 		num_samples,
 		&selftest.xcvr_measurements[1]);

 	// Capture 3: 20 Msps, tone at 5 MHz, narrowband filter OFF
 	fpga_set_tx_nco_pstep(&fpga, 255);
-	sample_rate_set(SR_FP_MHZ(20), true);
+	sample_rate_set(20ULL * FP_ONE_MHZ, true);
 	narrowband_filter_set(0);
-	delay_ms(1);
+	delay_us_at_mhz(1000, 204);
 	if (rx_samples(num_samples, 2000000) == -1) {
 		timeout = true;
 	}
 	measure_tone(
-		(int8_t*) usb_samp_buffer,
+		(int8_t*) usb_bulk_buffer,
 		num_samples,
 		&selftest.xcvr_measurements[2]);

 	// Capture 4: 20 Msps, tone at 5 MHz, narrowband filter ON
 	narrowband_filter_set(1);
-	delay_ms(1);
+	delay_us_at_mhz(1000, 204);
 	if (rx_samples(num_samples, 2000000) == -1) {
 		timeout = true;
 	}
 	measure_tone(
-		(int8_t*) usb_samp_buffer,
+		(int8_t*) usb_bulk_buffer,
 		num_samples,
 		&selftest.xcvr_measurements[3]);

 	// Restore default settings.
-	sample_rate_set(SR_FP_MHZ(10), true);
+	sample_rate_set(10ULL * FP_ONE_MHZ, true);
 	rf_path_set_direction(&rf_path, RF_PATH_DIRECTION_OFF);
 	narrowband_filter_set(0);
 	fpga_init(&fpga);
--- a/firmware/common/gpdma.c
+++ b/firmware/common/gpdma.c
@ -20,7 +20,7 @@
 * Boston, MA 02110-1301, USA.
 */

-#include "gpdma.h"
+#include <gpdma.h>

 #include <libopencm3/lpc43xx/gpdma.h>

--- a/firmware/common/gpdma.h
+++ b/firmware/common/gpdma.h
@ -20,7 +20,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __GPDMA_H__
+#define __GPDMA_H__

 #include <stddef.h>
 #include <stdint.h>
@ -39,3 +40,5 @@ void gpdma_lli_enable_interrupt(gpdma_lli_t* const lli);

 void gpdma_lli_create_loop(gpdma_lli_t* const lli, const size_t lli_count);
 void gpdma_lli_create_oneshot(gpdma_lli_t* const lli, const size_t lli_count);
+
+#endif /*__GPDMA_H__*/
--- a/firmware/common/gpio.h
+++ b/firmware/common/gpio.h
@ -20,7 +20,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __GPIO_H__
+#define __GPIO_H__

 #include <stdbool.h>

@ -34,3 +35,5 @@ void gpio_output(gpio_t gpio);
 void gpio_input(gpio_t gpio);
 void gpio_write(gpio_t gpio, const bool value);
 bool gpio_read(gpio_t gpio);
+
+#endif /*__GPIO_H__*/
--- a/firmware/common/gpio_lpc.c
+++ b/firmware/common/gpio_lpc.c
@ -22,11 +22,8 @@

 #include "gpio_lpc.h"

-#include <stdbool.h>
 #include <stddef.h>

-#include "gpio.h"
-
 void gpio_init(void)
 {
 	for (size_t i = 0; i < 8; i++) {
--- a/firmware/common/gpio_lpc.h
+++ b/firmware/common/gpio_lpc.h
@ -20,16 +20,19 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __GPIO_LPC_H__
+#define __GPIO_LPC_H__

 #include <stdint.h>

+#include "gpio.h"
+
 /* NOTE: libopencm3 constants and functions not used here due to naming
 * conflicts. I'd recommend changes to libopencm3 design to separate
 * register #defines and API declarations into separate header files.
 */

-typedef struct {
+typedef struct gpio_port {
 	volatile uint32_t dir; /* +0x000 */
 	uint32_t _reserved0[31];
 	volatile uint32_t mask; /* +0x080 */
@ -68,3 +71,5 @@ struct gpio {
 	.gpio_w = GPIO_LPC_W(_port_num, _pin_num), \
 }
 // clang-format on
+
+#endif /*__GPIO_LPC_H__*/
--- a/firmware/common/hackrf_core.c
+++ b/firmware/common/hackrf_core.c
--- a/firmware/common/hackrf_core.h
+++ b/firmware/common/hackrf_core.h
@ -0,0 +1,498 @@
+/*
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012 Benjamin Vernoux <titanmkd@gmail.com>
+ * Copyright 2012 Jared Boone <jared@sharebrained.com>
+ *
+ * This file is part of HackRF.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.  If not, write to
+ * the Free Software Foundation, Inc., 51 Franklin Street,
+ * Boston, MA 02110-1301, USA.
+ */
+
+#ifndef __HACKRF_CORE_H
+#define __HACKRF_CORE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "si5351c.h"
+#include "spi_ssp.h"
+
+#include "max2831.h"
+#include "max283x.h"
+#include "max5864.h"
+#include "mixer.h"
+#include "w25q80bv.h"
+#include "sgpio.h"
+#include "radio.h"
+#include "rf_path.h"
+#include "cpld_jtag.h"
+#include "ice40_spi.h"
+#include "fpga.h"
+#include "fixed_point.h"
+
+/*
+ * SCU PinMux
+ */
+
+/* GPIO Output PinMux */
+#define SCU_PINMUX_LED1 (P4_1)  /* GPIO2[1] on P4_1 */
+#define SCU_PINMUX_LED2 (P4_2)  /* GPIO2[2] on P4_2 */
+#define SCU_PINMUX_LED3 (P6_12) /* GPIO2[8] on P6_12 */
+#ifdef RAD1O
+	#define SCU_PINMUX_LED4 (PB_6) /* GPIO5[26] on PB_6 */
+#endif
+#ifdef PRALINE
+	#define SCU_PINMUX_LED4 (P8_6) /* GPIO4[6] on P8_6 */
+#endif
+
+#define SCU_PINMUX_EN1V8 (P6_10) /* GPIO3[6] on P6_10 */
+#define SCU_PINMUX_EN1V2 (P8_7)  /* GPIO4[7] on P8_7 */
+#ifdef PRALINE
+	#define SCU_PINMUX_EN3V3_AUX_N (P6_7)  /* GPIO5[15] on P6_7 */
+	#define SCU_PINMUX_EN3V3_OC_N  (P6_11) /* GPIO3[7] on P6_11 */
+#endif
+
+/* GPIO Input PinMux */
+#define SCU_PINMUX_BOOT0 (P1_1) /* GPIO0[8] on P1_1 */
+#define SCU_PINMUX_BOOT1 (P1_2) /* GPIO0[9] on P1_2 */
+#ifndef HACKRF_ONE
+	#define SCU_PINMUX_BOOT2 (P2_8) /* GPIO5[7] on P2_8 */
+	#define SCU_PINMUX_BOOT3 (P2_9) /* GPIO1[10] on P2_9 */
+#endif
+#define SCU_PINMUX_PP_LCD_TE  (P2_3)  /* GPIO5[3] on P2_3 */
+#define SCU_PINMUX_PP_LCD_RDX (P2_4)  /* GPIO5[4] on P2_4 */
+#define SCU_PINMUX_PP_UNUSED  (P2_8)  /* GPIO5[7] on P2_8 */
+#define SCU_PINMUX_PP_LCD_WRX (P2_9)  /* GPIO1[10] on P2_9 */
+#define SCU_PINMUX_PP_DIR     (P2_13) /* GPIO1[13] on P2_13 */
+
+/* USB peripheral */
+#ifdef JAWBREAKER
+	#define SCU_PINMUX_USB_LED0 (P6_8)
+	#define SCU_PINMUX_USB_LED1 (P6_7)
+#endif
+
+/* SSP1 Peripheral PinMux */
+#define SCU_SSP1_CIPO (P1_3)  /* P1_3 */
+#define SCU_SSP1_COPI (P1_4)  /* P1_4 */
+#define SCU_SSP1_SCK  (P1_19) /* P1_19 */
+#define SCU_SSP1_CS   (P1_20) /* P1_20 */
+
+/* CPLD JTAG interface */
+#ifdef PRALINE
+	#define SCU_PINMUX_FPGA_CRESET (P5_2)  /* GPIO2[11] on P5_2 */
+	#define SCU_PINMUX_FPGA_CDONE  (P4_10) /* GPIO5[14] */
+	#define SCU_PINMUX_FPGA_SPI_CS (P5_1)  /* GPIO2[10] */
+#endif
+#define SCU_PINMUX_CPLD_TDO (P9_5) /* GPIO5[18] */
+#define SCU_PINMUX_CPLD_TCK (P6_1) /* GPIO3[ 0] */
+#if (defined HACKRF_ONE || defined RAD1O || defined PRALINE)
+	#define SCU_PINMUX_CPLD_TMS (P6_5) /* GPIO3[ 4] */
+	#define SCU_PINMUX_CPLD_TDI (P6_2) /* GPIO3[ 1] */
+#else
+	#define SCU_PINMUX_CPLD_TMS (P6_2) /* GPIO3[ 1] */
+	#define SCU_PINMUX_CPLD_TDI (P6_5) /* GPIO3[ 4] */
+#endif
+
+/* CPLD SGPIO interface */
+#ifdef PRALINE
+	#define SCU_PINMUX_SGPIO0  (P0_0)
+	#define SCU_PINMUX_SGPIO1  (P0_1)
+	#define SCU_PINMUX_SGPIO2  (P1_15)
+	#define SCU_PINMUX_SGPIO3  (P1_16)
+	#define SCU_PINMUX_SGPIO4  (P9_4)
+	#define SCU_PINMUX_SGPIO5  (P6_6)
+	#define SCU_PINMUX_SGPIO6  (P2_2)
+	#define SCU_PINMUX_SGPIO7  (P1_0)
+	#define SCU_PINMUX_SGPIO8  (P8_0)
+	#define SCU_PINMUX_SGPIO9  (P9_3)
+	#define SCU_PINMUX_SGPIO10 (P8_2)
+	#define SCU_PINMUX_SGPIO11 (P1_17)
+	#define SCU_PINMUX_SGPIO12 (P1_18)
+	#define SCU_PINMUX_SGPIO14 (P1_18)
+	#define SCU_PINMUX_SGPIO15 (P1_18)
+
+	#define SCU_PINMUX_SGPIO0_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
+	#define SCU_PINMUX_SGPIO1_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
+	#define SCU_PINMUX_SGPIO2_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO3_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO4_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO5_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO6_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_PINMUX_SGPIO7_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO8_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_PINMUX_SGPIO9_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO10_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_PINMUX_SGPIO11_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO12_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_PINMUX_SGPIO14_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_PINMUX_SGPIO15_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+
+#else
+	#define SCU_PINMUX_SGPIO0 (P0_0)
+	#define SCU_PINMUX_SGPIO1 (P0_1)
+	#define SCU_PINMUX_SGPIO2 (P1_15)
+	#define SCU_PINMUX_SGPIO3 (P1_16)
+	#define SCU_PINMUX_SGPIO4 (P6_3)
+	#define SCU_PINMUX_SGPIO5 (P6_6)
+	#define SCU_PINMUX_SGPIO6 (P2_2)
+	#define SCU_PINMUX_SGPIO7 (P1_0)
+	#if (defined JAWBREAKER || defined HACKRF_ONE || defined RAD1O)
+		#define SCU_PINMUX_SGPIO8 (P9_6)
+	#endif
+	#define SCU_PINMUX_SGPIO9  (P4_3)
+	#define SCU_PINMUX_SGPIO10 (P1_14)
+	#define SCU_PINMUX_SGPIO11 (P1_17)
+	#define SCU_PINMUX_SGPIO12 (P1_18)
+	#define SCU_PINMUX_SGPIO14 (P4_9)
+	#define SCU_PINMUX_SGPIO15 (P4_10)
+
+	#define SCU_PINMUX_SGPIO0_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
+	#define SCU_PINMUX_SGPIO1_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION3)
+	#define SCU_PINMUX_SGPIO2_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO3_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO4_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO5_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION2)
+	#define SCU_PINMUX_SGPIO6_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_PINMUX_SGPIO7_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO8_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO9_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION7)
+	#define SCU_PINMUX_SGPIO10_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO11_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION6)
+	#define SCU_PINMUX_SGPIO12_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_PINMUX_SGPIO14_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_PINMUX_SGPIO15_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+
+#endif
+#define SCU_TRIGGER_EN (P4_8) /* GPIO5[12] on P4_8 */
+
+/* MAX2837 GPIO (XCVR_CTL) PinMux */
+#ifdef RAD1O
+	#define SCU_XCVR_RXHP (P8_1) /* GPIO[] on P8_1 */
+	#define SCU_XCVR_B6   (P8_2) /* GPIO[] on P8_2 */
+	#define SCU_XCVR_B7   (P9_3) /* GPIO[] on P8_3 */
+#endif
+
+#ifdef PRALINE
+	#define SCU_XCVR_ENABLE   (PE_1)  /* GPIO7[1] on PE_1 */
+	#define SCU_XCVR_RXENABLE (PE_2)  /* GPIO7[2] on PE_2 */
+	#define SCU_XCVR_CS       (PD_14) /* GPIO6[28] on PD_14 */
+	#define SCU_XCVR_RXHP     (PD_15) /* GPIO6[29] on PD_15 */
+	#define SCU_XCVR_LD       (P9_6)  /* GPIO4[11] on P9_6 */
+
+	#define SCU_XCVR_ENABLE_PINCFG   (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_XCVR_RXENABLE_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_XCVR_CS_PINCFG       (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_XCVR_RXHP_PINCFG     (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_XCVR_LD_PINCFG                                               \
+		(SCU_GPIO_FAST | SCU_CONF_FUNCTION0 | SCU_CONF_EPD_EN_PULLDOWN | \
+		 SCU_CONF_EPUN_DIS_PULLUP)
+#else
+	#define SCU_XCVR_ENABLE   (P4_6)  /* GPIO2[6] on P4_6 */
+	#define SCU_XCVR_RXENABLE (P4_5)  /* GPIO2[5] on P4_5 */
+	#define SCU_XCVR_TXENABLE (P4_4)  /* GPIO2[4] on P4_4 */
+	#define SCU_XCVR_CS       (P1_20) /* GPIO0[15] on P1_20 */
+
+	#define SCU_XCVR_ENABLE_PINCFG   (SCU_GPIO_FAST)
+	#define SCU_XCVR_RXENABLE_PINCFG (SCU_GPIO_FAST)
+	#define SCU_XCVR_TXENABLE_PINCFG (SCU_GPIO_FAST)
+	#define SCU_XCVR_CS_PINCFG       (SCU_GPIO_FAST)
+#endif
+
+/* MAX5864 SPI chip select (AD_CS) GPIO PinMux */
+#ifdef PRALINE
+	#define SCU_AD_CS        (PD_16) /* GPIO6[30] on PD_16 */
+	#define SCU_AD_CS_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+#else
+	#define SCU_AD_CS        (P5_7) /* GPIO2[7] on P5_7 */
+	#define SCU_AD_CS_PINCFG (SCU_GPIO_FAST)
+#endif
+
+/* RFFC5071 GPIO serial interface PinMux */
+#if (defined JAWBREAKER || defined HACKRF_ONE)
+	#define SCU_MIXER_ENX    (P5_4) /* GPIO2[13] on P5_4 */
+	#define SCU_MIXER_SCLK   (P2_6) /* GPIO5[6] on P2_6 */
+	#define SCU_MIXER_SDATA  (P6_4) /* GPIO3[3] on P6_4 */
+	#define SCU_MIXER_RESETX (P5_5) /* GPIO2[14] on P5_5 */
+
+	#define SCU_MIXER_SCLK_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_MIXER_SDATA_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+#endif
+#ifdef PRALINE
+	#define SCU_MIXER_ENX    (P5_4)  /* GPIO2[13] on P5_4 */
+	#define SCU_MIXER_SCLK   (P9_5)  /* GPIO5[18] on P9_5 */
+	#define SCU_MIXER_SDATA  (P9_2)  /* GPIO4[14] on P9_2 */
+	#define SCU_MIXER_RESETX (P5_5)  /* GPIO2[14] on P5_5 */
+	#define SCU_MIXER_LD     (PD_11) /* GPIO6[25] on PD_11 */
+
+	#define SCU_MIXER_SCLK_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_MIXER_SDATA_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_MIXER_LD_PINCFG    (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+#endif
+#ifdef RAD1O
+	#define SCU_VCO_CE        (P5_4) /* GPIO2[13] on P5_4 */
+	#define SCU_VCO_SCLK      (P2_6) /* GPIO5[6] on P2_6 */
+	#define SCU_VCO_SDATA     (P6_4) /* GPIO3[3] on P6_4 */
+	#define SCU_VCO_LE        (P5_5) /* GPIO2[14] on P5_5 */
+	#define SCU_VCO_MUX       (PB_5) /* GPIO5[25] on PB_5 */
+	#define SCU_MIXER_EN      (P6_8) /* GPIO5[16] on P6_8 */
+	#define SCU_SYNT_RFOUT_EN (P6_9) /* GPIO3[5] on P6_9 */
+#endif
+
+/* RF LDO control */
+#ifdef JAWBREAKER
+	#define SCU_RF_LDO_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
+#endif
+
+/* RF supply (VAA) control */
+#ifdef HACKRF_ONE
+	#define SCU_NO_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
+#endif
+#ifdef PRALINE
+	#define SCU_NO_VAA_ENABLE (P8_1) /* GPIO4[1] on P8_1 */
+#endif
+#ifdef RAD1O
+	#define SCU_VAA_ENABLE (P5_0) /* GPIO2[9] on P5_0 */
+#endif
+
+/* SPI flash */
+#define SCU_SSP0_CIPO  (P3_6)
+#define SCU_SSP0_COPI  (P3_7)
+#define SCU_SSP0_SCK   (P3_3)
+#define SCU_SSP0_CS    (P3_8) /* GPIO5[11] on P3_8 */
+#define SCU_FLASH_HOLD (P3_4) /* GPIO1[14] on P3_4 */
+#define SCU_FLASH_WP   (P3_5) /* GPIO1[15] on P3_5 */
+
+/* RF switch control */
+#ifdef HACKRF_ONE
+	#define SCU_HP            (P4_0)  /* GPIO2[0] on P4_0 */
+	#define SCU_LP            (P5_1)  /* GPIO2[10] on P5_1 */
+	#define SCU_TX_MIX_BP     (P5_2)  /* GPIO2[11] on P5_2 */
+	#define SCU_NO_MIX_BYPASS (P1_7)  /* GPIO1[0] on P1_7 */
+	#define SCU_RX_MIX_BP     (P5_3)  /* GPIO2[12] on P5_3 */
+	#define SCU_TX_AMP        (P5_6)  /* GPIO2[15] on P5_6 */
+	#define SCU_TX            (P6_7)  /* GPIO5[15] on P6_7 */
+	#define SCU_MIX_BYPASS    (P6_8)  /* GPIO5[16] on P6_8 */
+	#define SCU_RX            (P2_5)  /* GPIO5[5] on P2_5 */
+	#define SCU_NO_TX_AMP_PWR (P6_9)  /* GPIO3[5] on P6_9 */
+	#define SCU_AMP_BYPASS    (P2_10) /* GPIO0[14] on P2_10 */
+	#define SCU_RX_AMP        (P2_11) /* GPIO1[11] on P2_11 */
+	#define SCU_NO_RX_AMP_PWR (P2_12) /* GPIO1[12] on P2_12 */
+#endif
+#ifdef RAD1O
+	#define SCU_BY_AMP          (P1_7)  /* GPIO1[0] on P1_7 */
+	#define SCU_BY_AMP_N        (P2_5)  /* GPIO5[5] on P2_5 */
+	#define SCU_TX_RX           (P2_10) /* GPIO0[14] on P2_10 */
+	#define SCU_TX_RX_N         (P2_11) /* GPIO1[11] on P2_11 */
+	#define SCU_BY_MIX          (P2_12) /* GPIO1[12] on P2_12 */
+	#define SCU_BY_MIX_N        (P5_1)  /* GPIO2[10] on P5_1 */
+	#define SCU_LOW_HIGH_FILT   (P5_2)  /* GPIO2[11] on P5_2 */
+	#define SCU_LOW_HIGH_FILT_N (P5_3)  /* GPIO2[12] on P5_3 */
+	#define SCU_TX_AMP          (P5_6)  /* GPIO2[15] on P5_6 */
+	#define SCU_RX_LNA          (P6_7)  /* GPIO5[15] on P6_7 */
+#endif
+#ifdef PRALINE
+	#define SCU_TX_EN         (P6_5)  /* GPIO3[4] on P6_5 */
+	#define SCU_MIX_EN_N      (P6_3)  /* GPIO3[2] on P6_3 */
+	#define SCU_MIX_EN_N_R1_0 (P2_6)  /* GPIO5[6] on P2_6 */
+	#define SCU_LPF_EN        (PA_1)  /* GPIO4[8] on PA_1 */
+	#define SCU_RF_AMP_EN     (PA_2)  /* GPIO4[9] on PA_2 */
+	#define SCU_ANT_BIAS_EN_N (P2_12) /* GPIO1[12] on P2_12 */
+	#define SCU_ANT_BIAS_OC_N (P2_11) /* GPIO1[11] on P2_11 */
+#endif
+
+#ifdef PRALINE
+	#define SCU_P2_CTRL0    (PE_3)  /* GPIO7[3] on PE_3 */
+	#define SCU_P2_CTRL1    (PE_4)  /* GPIO7[4] on PE_4 */
+	#define SCU_P1_CTRL0    (P2_10) /* GPIO0[14] on P2_10 */
+	#define SCU_P1_CTRL1    (P6_8)  /* GPIO5[16] on P6_8 */
+	#define SCU_P1_CTRL2    (P6_9)  /* GPIO3[5] on P6_9 */
+	#define SCU_CLKIN_CTRL  (P1_20) /* GPIO0[15] on P1_20 */
+	#define SCU_AA_EN       (P1_14) /* GPIO1[7] on P1_14 */
+	#define SCU_TRIGGER_IN  (PD_12) /* GPIO6[26] on PD_12 */
+	#define SCU_TRIGGER_OUT (P2_6)  /* GPIO5[6] on P2_6 */
+	#define SCU_PPS_OUT     (P2_5)  /* GPIO5[5] on P2_5 */
+
+	#define SCU_P2_CTRL0_PINCFG    (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_P2_CTRL1_PINCFG    (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_P1_CTRL0_PINCFG    (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_P1_CTRL1_PINCFG    (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_P1_CTRL2_PINCFG    (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_CLKIN_CTRL_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_AA_EN_PINCFG       (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)
+	#define SCU_TRIGGER_IN_PINCFG  (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_TRIGGER_OUT_PINCFG (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+	#define SCU_PPS_OUT_PINCFG     (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)
+
+#endif
+
+#define SCU_PINMUX_PP_D0 (P7_0) /* GPIO3[8] */
+#define SCU_PINMUX_PP_D1 (P7_1) /* GPIO3[9] */
+#define SCU_PINMUX_PP_D2 (P7_2) /* GPIO3[10] */
+#define SCU_PINMUX_PP_D3 (P7_3) /* GPIO3[11] */
+#define SCU_PINMUX_PP_D4 (P7_4) /* GPIO3[12] */
+#define SCU_PINMUX_PP_D5 (P7_5) /* GPIO3[13] */
+#define SCU_PINMUX_PP_D6 (P7_6) /* GPIO3[14] */
+#define SCU_PINMUX_PP_D7 (P7_7) /* GPIO3[15] */
+/* TODO add other Pins */
+#define SCU_PINMUX_GPIO3_8  (P7_0) /* GPIO3[8] */
+#define SCU_PINMUX_GPIO3_9  (P7_1) /* GPIO3[9] */
+#define SCU_PINMUX_GPIO3_10 (P7_2) /* GPIO3[10] */
+#define SCU_PINMUX_GPIO3_11 (P7_3) /* GPIO3[11] */
+#define SCU_PINMUX_GPIO3_12 (P7_4) /* GPIO3[12] */
+#define SCU_PINMUX_GPIO3_13 (P7_5) /* GPIO3[13] */
+#define SCU_PINMUX_GPIO3_14 (P7_6) /* GPIO3[14] */
+#define SCU_PINMUX_GPIO3_15 (P7_7) /* GPIO3[15] */
+
+#define SCU_PINMUX_PP_TDO   (P1_5)  /* GPIO1[8] */
+#define SCU_PINMUX_SD_POW   (P1_5)  /* GPIO1[8] */
+#define SCU_PINMUX_SD_CMD   (P1_6)  /* GPIO1[9] */
+#define SCU_PINMUX_PP_TMS   (P1_8)  /* GPIO1[1] */
+#define SCU_PINMUX_SD_VOLT0 (P1_8)  /* GPIO1[1] */
+#define SCU_PINMUX_SD_DAT0  (P1_9)  /* GPIO1[2] */
+#define SCU_PINMUX_SD_DAT1  (P1_10) /* GPIO1[3] */
+#define SCU_PINMUX_SD_DAT2  (P1_11) /* GPIO1[4] */
+#define SCU_PINMUX_SD_DAT3  (P1_12) /* GPIO1[5] */
+#define SCU_PINMUX_SD_CD    (P1_13) /* GPIO1[6] */
+
+#define SCU_PINMUX_PP_IO_STBX (P2_0) /* GPIO5[0] */
+#define SCU_PINMUX_PP_ADDR    (P2_1) /* GPIO5[1] */
+#define SCU_PINMUX_U0_TXD     (P2_0) /* GPIO5[0] */
+#define SCU_PINMUX_U0_RXD     (P2_1) /* GPIO5[1] */
+
+#define SCU_PINMUX_ISP (P2_7) /* GPIO0[7] */
+
+#define SCU_PINMUX_GP_CLKIN (P4_7)
+
+/* HackRF One r9 */
+#define SCU_H1R9_CLKIN_EN   (P6_7)  /* GPIO5[15] on P6_7 */
+#define SCU_H1R9_CLKOUT_EN  (P1_2)  /* GPIO0[9] on P1_2 (has boot pull-down) */
+#define SCU_H1R9_MCU_CLK_EN (P1_1)  /* GPIO0[8] on P1_1 (has boot pull-up) */
+#define SCU_H1R9_RX         (P2_7)  /* GPIO0[7] on P4_4 (has boot pull-up) */
+#define SCU_H1R9_NO_ANT_PWR (P4_4)  /* GPIO2[4] on P4_4 */
+#define SCU_H1R9_EN1V8      (P5_0)  /* GPIO2[9] on P5_0 */
+#define SCU_H1R9_NO_VAA_EN  (P6_10) /* GPIO3[6] on P6_10 */
+#define SCU_H1R9_TRIGGER_EN (P2_5)  /* GPIO5[5] on P2_5 */
+
+/* TODO: Hide these configurations */
+extern si5351c_driver_t clock_gen;
+extern const ssp_config_t ssp_config_w25q80bv;
+extern const ssp_config_t ssp_config_max283x;
+extern const ssp_config_t ssp_config_max5864;
+
+#ifndef PRALINE
+extern max283x_driver_t max283x;
+#else
+extern max2831_driver_t max283x;
+extern ice40_spi_driver_t ice40;
+extern fpga_driver_t fpga;
+
+#endif
+extern max5864_driver_t max5864;
+extern mixer_driver_t mixer;
+extern w25q80bv_driver_t spi_flash;
+extern sgpio_config_t sgpio_config;
+extern radio_t radio;
+extern rf_path_t rf_path;
+extern jtag_t jtag_cpld;
+extern i2c_bus_t i2c0;
+
+void cpu_clock_init(void);
+void clock_gen_init(void);
+void clock_gen_shutdown(void);
+void ssp1_set_mode_max283x(void);
+void ssp1_set_mode_max5864(void);
+#ifdef PRALINE
+void ssp1_set_mode_max2831(void);
+void ssp1_set_mode_ice40(void);
+#endif
+
+void pin_shutdown(void);
+void pin_setup(void);
+
+#ifdef PRALINE
+void enable_1v2_power(void);
+void disable_1v2_power(void);
+void enable_3v3aux_power(void);
+void disable_3v3aux_power(void);
+#else
+void enable_1v8_power(void);
+void disable_1v8_power(void);
+#endif
+
+fp_40_24_t sample_rate_set(const fp_40_24_t sample_rate, const bool program);
+
+clock_source_t activate_best_clock_source(void);
+
+#if (defined HACKRF_ONE || defined RAD1O || defined PRALINE)
+void enable_rf_power(void);
+void disable_rf_power(void);
+#endif
+
+typedef enum {
+	LED1 = 0,
+	LED2 = 1,
+	LED3 = 2,
+	LED4 = 3,
+} led_t;
+
+void led_on(const led_t led);
+void led_off(const led_t led);
+void led_toggle(const led_t led);
+void set_leds(const uint8_t state);
+
+void trigger_enable(const bool enable);
+
+void halt_and_flash(const uint32_t duration);
+
+#ifdef PRALINE
+typedef enum {
+	P1_SIGNAL_TRIGGER_IN = 0,
+	P1_SIGNAL_AUX_CLK1 = 1,
+	P1_SIGNAL_CLKIN = 2,
+	P1_SIGNAL_TRIGGER_OUT = 3,
+	P1_SIGNAL_P22_CLKIN = 4,
+	P1_SIGNAL_P2_5 = 5,
+	P1_SIGNAL_NC = 6,
+	P1_SIGNAL_AUX_CLK2 = 7,
+} p1_ctrl_signal_t;
+
+typedef enum {
+	P2_SIGNAL_CLK3 = 0,
+	P2_SIGNAL_TRIGGER_IN = 2,
+	P2_SIGNAL_TRIGGER_OUT = 3,
+} p2_ctrl_signal_t;
+
+typedef enum {
+	CLKIN_SIGNAL_P1 = 0,
+	CLKIN_SIGNAL_P22 = 1,
+} clkin_signal_t;
+
+void p1_ctrl_set(const p1_ctrl_signal_t signal);
+void p2_ctrl_set(const p2_ctrl_signal_t signal);
+void narrowband_filter_set(const uint8_t value);
+void clkin_ctrl_set(const clkin_signal_t value);
+void pps_out_set(const uint8_t value);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HACKRF_CORE_H */
--- a/firmware/common/hackrf_ui.c
+++ b/firmware/common/hackrf_ui.c
@ -20,16 +20,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#include <stddef.h>
-
 #include "hackrf_ui.h"
-#include "transceiver_mode.h"
-#ifdef IS_EXPANSION_COMPATIBLE
-	#include "ui_portapack.h"
-#endif
-#ifdef IS_RAD1O
-	#include "ui_rad1o.h"
-#endif
+
+#include "ui_portapack.h"
+#include "ui_rad1o.h"
+
+#include <stddef.h>

 #define UNUSED(x) (void) (x)

@ -82,18 +78,14 @@ const hackrf_ui_t* hackrf_ui(void)
 {
 	/* Detect on first use. If no UI hardware is detected, use a stub function table. */
 	if (ui == NULL && ui_enabled) {
-#ifdef IS_EXPANSION_COMPATIBLE
-		if (IS_EXPANSION_COMPATIBLE) {
-			if (portapack_hackrf_ui_init) {
-				ui = portapack_hackrf_ui_init();
-			}
+#if (defined HACKRF_ONE || defined PRALINE)
+		if (portapack_hackrf_ui_init) {
+			ui = portapack_hackrf_ui_init();
 		}
 #endif
-#ifdef IS_RAD1O
-		if (IS_RAD1O) {
-			if (rad1o_ui_setup) {
-				ui = rad1o_ui_setup();
-			}
+#ifdef RAD1O
+		if (rad1o_ui_setup) {
+			ui = rad1o_ui_setup();
 		}
 #endif
 	}
--- a/firmware/common/hackrf_ui.h
+++ b/firmware/common/hackrf_ui.h
@ -20,15 +20,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef HACKRF_UI_H
+#define HACKRF_UI_H

-#include <stdbool.h>
+#include <hackrf_core.h>
 #include <stdint.h>

-#include "clock_gen.h"
-#include "rf_path.h"
-#include "transceiver_mode.h"
-
 typedef void (*hackrf_ui_init_fn)(void);
 typedef void (*hackrf_ui_deinit_fn)(void);
 typedef void (*hackrf_ui_set_frequency_fn)(uint64_t frequency);
@ -71,3 +68,5 @@ typedef struct {
 */
 const hackrf_ui_t* hackrf_ui(void);
 void hackrf_ui_set_enable(bool);
+
+#endif
--- a/firmware/common/i2c_bus.h
+++ b/firmware/common/i2c_bus.h
@ -20,23 +20,27 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __I2C_BUS_H__
+#define __I2C_BUS_H__

-#include <stddef.h>
 #include <stdint.h>
+#include <stddef.h>

-typedef struct _i2c_bus_t {
+struct i2c_bus_t;
+typedef struct i2c_bus_t i2c_bus_t;
+
+struct i2c_bus_t {
 	void* const obj;
-	void (*start)(struct _i2c_bus_t* const bus, const void* const config);
-	void (*stop)(struct _i2c_bus_t* const bus);
+	void (*start)(i2c_bus_t* const bus, const void* const config);
+	void (*stop)(i2c_bus_t* const bus);
 	void (*transfer)(
-		struct _i2c_bus_t* const bus,
+		i2c_bus_t* const bus,
 		const uint_fast8_t peripheral_address,
 		const uint8_t* const tx,
 		const size_t tx_count,
 		uint8_t* const rx,
 		const size_t rx_count);
-} i2c_bus_t;
+};

 void i2c_bus_start(i2c_bus_t* const bus, const void* const config);
 void i2c_bus_stop(i2c_bus_t* const bus);
@ -47,3 +51,5 @@ void i2c_bus_transfer(
 	const size_t tx_count,
 	uint8_t* const rx,
 	const size_t rx_count);
+
+#endif /*__I2C_BUS_H__*/
--- a/firmware/common/i2c_lpc.c
+++ b/firmware/common/i2c_lpc.c
@ -23,28 +23,6 @@
 #include "i2c_lpc.h"

 #include <libopencm3/lpc43xx/i2c.h>
-#include <libopencm3/lpc43xx/memorymap.h>
-
-#include "cpu_clock.h"
-
-/* Driver instances. */
-i2c_bus_t i2c0 = {
-	.obj = (void*) I2C0_BASE,
-	.start = i2c_lpc_start,
-	.stop = i2c_lpc_stop,
-	.transfer = i2c_lpc_transfer,
-};
-
-i2c_bus_t i2c1 = {
-	.obj = (void*) I2C1_BASE,
-	.start = i2c_lpc_start,
-	.stop = i2c_lpc_stop,
-	.transfer = i2c_lpc_transfer,
-};
-
-const i2c_lpc_config_t i2c_config_fast_clock = {
-	.clock_khz = 400,
-};

 /* FIXME return i2c0 status from each function */

@ -53,9 +31,7 @@ void i2c_lpc_start(i2c_bus_t* const bus, const void* const _config)
 	const i2c_lpc_config_t* const config = _config;

 	const uint32_t port = (uint32_t) bus->obj;
-	const uint16_t duty_cycle_count =
-		(cpu_clock_mhz * (2000 / config->clock_khz)) / 4;
-	i2c_init(port, duty_cycle_count);
+	i2c_init(port, config->duty_cycle_count);
 }

 void i2c_lpc_stop(i2c_bus_t* const bus)
--- a/firmware/common/i2c_lpc.h
+++ b/firmware/common/i2c_lpc.h
@ -20,16 +20,17 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __I2C_LPC_H__
+#define __I2C_LPC_H__

-#include <stdbool.h>
-#include <stddef.h>
 #include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>

 #include "i2c_bus.h"

-typedef struct {
-	const uint16_t clock_khz;
+typedef struct i2c_lpc_config_t {
+	const uint16_t duty_cycle_count;
 } i2c_lpc_config_t;

 void i2c_lpc_start(i2c_bus_t* const bus, const void* const config);
@ -43,7 +44,4 @@ void i2c_lpc_transfer(
 	const size_t count_rx);
 bool i2c_probe(i2c_bus_t* const bus, const uint_fast8_t device_address);

-/* Driver instances. */
-extern const i2c_lpc_config_t i2c_config_fast_clock;
-extern i2c_bus_t i2c0;
-extern i2c_bus_t i2c1;
+#endif /*__I2C_LPC_H__*/
--- a/firmware/common/ice40_spi.c
+++ b/firmware/common/ice40_spi.c
@ -21,44 +21,20 @@

 #include "ice40_spi.h"

-#include <libopencm3/lpc43xx/memorymap.h>
 #include <libopencm3/lpc43xx/scu.h>
-#include <libopencm3/lpc43xx/ssp.h>
-
+#include "hackrf_core.h"
+#include "lz4_buf.h"
 #include "delay.h"
-#include "platform_gpio.h"
-#include "platform_scu.h"
-
-/* Driver instance. */
-ssp_config_t ssp_config_ice40_fpga = {
-	.data_bits = SSP_DATA_8BITS,
-	.spi_mode = SSP_CPOL_1_CPHA_1,
-	.serial_clock_rate = 21,
-	.clock_prescale_rate = 2,
-};
-
-ice40_spi_driver_t ice40 = {
-	.bus = &spi_bus_ssp1,
-};

 void ice40_spi_target_init(ice40_spi_driver_t* const drv)
 {
-	const platform_gpio_t* gpio = platform_gpio();
-	const platform_scu_t* scu = platform_scu();
-
-	/* Configure drivers and driver pins */
-	ssp_config_ice40_fpga.gpio_select = gpio->fpga_cfg_spi_cs;
-	ice40.gpio_select = gpio->fpga_cfg_spi_cs;
-	ice40.gpio_creset = gpio->fpga_cfg_creset;
-	ice40.gpio_cdone = gpio->fpga_cfg_cdone;
-
 	/* Configure SSP1 Peripheral and relevant FPGA pins. */
-	scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
-	scu_pinmux(scu->PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
-	scu_pinmux(scu->PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
-	scu_pinmux(scu->PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	scu_pinmux(SCU_PINMUX_FPGA_CRESET, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);
+	scu_pinmux(SCU_PINMUX_FPGA_CDONE, SCU_GPIO_PUP | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_PINMUX_FPGA_SPI_CS, SCU_GPIO_NOPULL | SCU_CONF_FUNCTION0);

 	/* Configure GPIOs as inputs or outputs as needed. */
 	gpio_clear(drv->gpio_creset);
@ -70,14 +46,14 @@ void ice40_spi_target_init(ice40_spi_driver_t* const drv)
 uint8_t ice40_spi_read(ice40_spi_driver_t* const drv, uint8_t r)
 {
 	uint8_t value[3] = {r & 0x7F, 0, 0};
-	spi_bus_transfer(drv->bus, &ssp_config_ice40_fpga, value, 3);
+	spi_bus_transfer(drv->bus, value, 3);
 	return value[2];
 }

 void ice40_spi_write(ice40_spi_driver_t* const drv, uint8_t r, uint16_t v)
 {
 	uint8_t value[3] = {(r & 0x7F) | 0x80, v, 0};
-	spi_bus_transfer(drv->bus, &ssp_config_ice40_fpga, value, 3);
+	spi_bus_transfer(drv->bus, value, 3);
 }

 static void spi_ssp1_wait_for_tx_fifo_not_full(void)
@ -106,25 +82,22 @@ static uint32_t spi_ssp1_transfer_word(const uint32_t data)

 bool ice40_spi_syscfg_program(
 	ice40_spi_driver_t* const drv,
-	uint8_t* buf,
-	size_t (*read_block_cb)(void* ctx),
+	size_t (*read_block_cb)(void* ctx, uint8_t* buffer),
 	void* read_ctx)
 {
-	spi_bus_start(drv->bus, &ssp_config_ice40_fpga);
-
 	// Drive CRESET_B = 0, SPI_SS = 0, SPI_SCK = 1.
 	gpio_clear(drv->gpio_creset);
 	gpio_clear(drv->gpio_select);

 	// Wait a minimum of 200 ns.
-	delay_us(1);
+	delay_us_at_mhz(1, 204 / 4); // 250 ns.

 	// Release CRESET_B or drive CRESET_B = 1.
 	gpio_set(drv->gpio_creset);

 	// Wait a minimum of 1200 μs to clear internal configuration memory.
 	// Testing showed us that we need to wait longer. Let's wait 1800 μs.
-	delay_us(1800);
+	delay_us_at_mhz(1800, 204);

 	// Set SPI_SS = 1, Send 8 dummy clocks.
 	gpio_set(drv->gpio_select);
@ -134,11 +107,11 @@ bool ice40_spi_syscfg_program(
 	// first, on falling edge of SPI_SCK.
 	gpio_clear(drv->gpio_select);
 	for (;;) {
-		size_t read_sz = read_block_cb(read_ctx);
+		size_t read_sz = read_block_cb(read_ctx, lz4_out_buf);
 		if (read_sz == 0)
 			break;
 		for (size_t j = 0; j < read_sz; j++) {
-			spi_ssp1_transfer_word(buf[j]);
+			spi_ssp1_transfer_word(lz4_out_buf[j]);
 		}
 	}

--- a/firmware/common/ice40_spi.h
+++ b/firmware/common/ice40_spi.h
@ -19,32 +19,30 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __ICE40_SPI_H
+#define __ICE40_SPI_H

-#include <stdbool.h>
 #include <stdint.h>
 #include <stdlib.h>
-
 #include "gpio.h"
 #include "spi_bus.h"
-#include "spi_ssp.h"

-typedef struct {
+struct ice40_spi_driver_t;
+typedef struct ice40_spi_driver_t ice40_spi_driver_t;
+
+struct ice40_spi_driver_t {
 	spi_bus_t* const bus;
 	gpio_t gpio_select;
 	gpio_t gpio_creset;
 	gpio_t gpio_cdone;
-} ice40_spi_driver_t;
+};

 void ice40_spi_target_init(ice40_spi_driver_t* const drv);
 uint8_t ice40_spi_read(ice40_spi_driver_t* const drv, uint8_t r);
 void ice40_spi_write(ice40_spi_driver_t* const drv, uint8_t r, uint16_t v);
 bool ice40_spi_syscfg_program(
 	ice40_spi_driver_t* const drv,
-	uint8_t* buf,
-	size_t (*read_block_cb)(void* ctx),
+	size_t (*read_block_cb)(void* ctx, uint8_t* buffer),
 	void* read_ctx);

-/* Driver instance. */
-extern ssp_config_t ssp_config_ice40_fpga;
-extern ice40_spi_driver_t ice40;
+#endif // __ICE40_SPI_H
--- a/firmware/common/leds.c
+++ b/firmware/common/leds.c
@ -1,100 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#include "leds.h"
-
-#include <stdint.h>
-
-#include "delay.h"
-#include "gpio.h"
-#include "platform_detect.h"
-#include "platform_gpio.h"
-
-void led_on(const led_t led)
-{
-#ifdef IS_PRALINE
-	if (IS_PRALINE) {
-		gpio_clear(platform_gpio()->led[led]);
-	}
-#endif
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		gpio_set(platform_gpio()->led[led]);
-	}
-#endif
-}
-
-void led_off(const led_t led)
-{
-#ifdef IS_PRALINE
-	if (IS_PRALINE) {
-		gpio_set(platform_gpio()->led[led]);
-	}
-#endif
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		gpio_clear(platform_gpio()->led[led]);
-	}
-#endif
-}
-
-void led_toggle(const led_t led)
-{
-	gpio_toggle(platform_gpio()->led[led]);
-}
-
-void set_leds(const uint8_t state)
-{
-	int num_leds = 3;
-#ifdef IS_FOUR_LEDS
-	if (IS_FOUR_LEDS) {
-		num_leds = 4;
-	}
-#endif
-
-	for (int i = 0; i < num_leds; i++) {
-#ifdef IS_PRALINE
-		if (IS_PRALINE) {
-			gpio_write(platform_gpio()->led[i], ((state >> i) & 1) == 0);
-		}
-#endif
-#ifdef IS_NOT_PRALINE
-		if (IS_NOT_PRALINE) {
-			gpio_write(platform_gpio()->led[i], ((state >> i) & 1) == 1);
-		}
-#endif
-	}
-}
-
-void halt_and_flash(const uint32_t period_ms)
-{
-	/* blink LED1, LED2, and LED3 */
-	while (1) {
-		led_on(LED1);
-		led_on(LED2);
-		led_on(LED3);
-		delay_ms(period_ms / 2);
-		led_off(LED1);
-		led_off(LED2);
-		led_off(LED3);
-		delay_ms(period_ms / 2);
-	}
-}
--- a/firmware/common/leds.h
+++ b/firmware/common/leds.h
@ -1,46 +0,0 @@
-/*
- * Copyright 2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
-
-#pragma once
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-typedef enum {
-	LED1 = 0,
-	LED2 = 1,
-	LED3 = 2,
-	LED4 = 3,
-} led_t;
-
-void led_on(const led_t led);
-void led_off(const led_t led);
-void led_toggle(const led_t led);
-void set_leds(const uint8_t state);
-
-void halt_and_flash(const uint32_t duration);
-
-#ifdef __cplusplus
-}
-#endif
--- a/firmware/common/locking.h
+++ b/firmware/common/locking.h
@ -19,7 +19,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __LOCKING_H__
+#define __LOCKING_H__

 #include <stdint.h>

@ -50,3 +51,5 @@ static inline uint32_t store_exclusive(uint32_t val, volatile uint32_t* addr)
 	return 0;
 }
 #endif
+
+#endif /* __LOCKING_H__ */
--- a/firmware/common/lz4_blk.h
+++ b/firmware/common/lz4_blk.h
@ -19,9 +19,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __LZ4_BLK_H
+#define __LZ4_BLK_H

 #include <stdint.h>
 #include <stdlib.h>

 int lz4_blk_decompress(const uint8_t* src, uint8_t* dst, size_t length);
+
+#endif
--- a/firmware/common/lz4_buf.h
+++ b/firmware/common/lz4_buf.h
@ -19,7 +19,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __LZ4_BUF_H
+#define __LZ4_BUF_H

 #include <stdint.h>

@ -30,3 +31,5 @@

 extern uint8_t lz4_in_buf[LZ4_BUFFER_SIZE];
 extern uint8_t lz4_out_buf[LZ4_BUFFER_SIZE];
+
+#endif /*__LZ4_BUF_H */
--- a/firmware/common/m0_state.c
+++ b/firmware/common/m0_state.c
@ -20,8 +20,8 @@
 */

 #include "m0_state.h"
-
 #include <libopencm3/lpc43xx/sgpio.h>
+#include <stddef.h>

 void m0_set_mode(enum m0_mode mode)
 {
--- a/firmware/common/m0_state.h
+++ b/firmware/common/m0_state.h
@ -19,7 +19,8 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __M0_STATE_H__
+#define __M0_STATE_H__

 #include <stdint.h>

@ -59,3 +60,5 @@ enum m0_error {
 extern volatile struct m0_state m0_state;

 void m0_set_mode(enum m0_mode mode);
+
+#endif /*__M0_STATE_H__*/
--- a/firmware/common/max2831.c
+++ b/firmware/common/max2831.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
 *
 * This file is part of HackRF.
 *
@ -27,18 +27,14 @@
 * pirate commands to do the same thing.
 */

-#include "max2831.h"
-
-#include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
-#include "fixed_point.h"
+#include "max2831.h"
 #include "max2831_regs.def" // private register def macros
 #include "selftest.h"
 #include "adc.h"

 #define MIN(x, y) ((x) < (y) ? (x) : (y))
-#define MAX(x, y) ((x) > (y) ? (x) : (y))

 /* Default register values. */
 static const uint16_t max2831_regs_default[MAX2831_NUM_REGS] = {
@ -109,7 +105,7 @@ static void max2831_write(max2831_driver_t* const drv, uint8_t r, uint16_t v)
 {
 	uint32_t word = (((uint32_t) v & 0x3fff) << 4) | (r & 0xf);
 	uint16_t values[2] = {word >> 9, word & 0x1ff};
-	spi_bus_transfer(drv->bus, drv->config, values, 2);
+	spi_bus_transfer(drv->bus, values, 2);
 }

 uint16_t max2831_reg_read(max2831_driver_t* const drv, uint8_t r)
@ -226,40 +222,36 @@ void max2831_stop(max2831_driver_t* const drv)
 	max2831_set_mode(drv, MAX2831_MODE_SHUTDOWN);
 }

-/* Assume 40 MHz reference clock with R divider of 2. */
-#define PFD_FREQ_HZ (20ULL * (1000ULL * 1000ULL))
-
-#define MIN_FREQ FP_MHZ(2000)
-#define MAX_FREQ FP_MHZ(3000)
-
-fp_40_24_t max2831_set_frequency(
-	max2831_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program)
+void max2831_set_frequency(max2831_driver_t* const drv, uint32_t freq)
 {
-	uint64_t div;
+	uint32_t div_frac;
+	uint32_t div_int;
+	uint32_t div_rem;
+	uint32_t div_cmp;
+	int i;

-	freq = MIN(freq, MAX_FREQ);
-	freq = MAX(freq, MIN_FREQ);
-
-	freq += ((PFD_FREQ_HZ * FP_ONE_HZ) >> 21); /* round to nearest frequency */
-	div = freq / PFD_FREQ_HZ;
-
-	/*
-	 * Shift from 40.24 fixed-point to 44.20 to match 20-bit fractional
-	 * divider.
-	 */
-	div = div >> 4;
-
-	if (program) {
-		//set_MAX2831_SYN_REF_DIV(drv, MAX2831_SYN_REF_DIV_2);
-		set_MAX2831_SYN_INT(drv, (div >> 20) & 0xff);
-		set_MAX2831_SYN_FRAC_HI(drv, (div >> 6) & 0x3fff);
-		set_MAX2831_SYN_FRAC_LO(drv, div & 0x3f);
-		max2831_regs_commit(drv);
+	/* ASSUME 40MHz PLL. Ratio = F*R/40,000,000. */
+	/* TODO: fixed to R=2. Check if it's worth exploring R=1. */
+	freq += (20000000 >> 21); /* round to nearest frequency */
+	div_int = freq / 20000000;
+	div_rem = freq % 20000000;
+	div_frac = 0;
+	div_cmp = 20000000;
+	for (i = 0; i < 20; i++) {
+		div_frac <<= 1;
+		div_rem <<= 1;
+		if (div_rem >= div_cmp) {
+			div_frac |= 0x1;
+			div_rem -= div_cmp;
+		}
 	}

-	return PFD_FREQ_HZ * (div << 4);
+	/* Write order matters? */
+	//set_MAX2831_SYN_REF_DIV(drv, MAX2831_SYN_REF_DIV_2);
+	set_MAX2831_SYN_INT(drv, div_int);
+	set_MAX2831_SYN_FRAC_HI(drv, (div_frac >> 6) & 0x3fff);
+	set_MAX2831_SYN_FRAC_LO(drv, div_frac & 0x3f);
+	max2831_regs_commit(drv);
 }

 typedef struct {
--- a/firmware/common/max2831.h
+++ b/firmware/common/max2831.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
 *
 * This file is part of HackRF.
 *
@ -19,12 +19,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __MAX2831_H
+#define __MAX2831_H

-#include <stdbool.h>
 #include <stdint.h>
+#include <stdbool.h>

-#include "fixed_point.h"
 #include "gpio.h"
 #include "spi_bus.h"

@ -37,8 +37,8 @@ typedef enum {
 	MAX2831_MODE_STANDBY,
 	MAX2831_MODE_TX,
 	MAX2831_MODE_RX,
-	MAX2831_MODE_RX_CALIBRATION,
 	MAX2831_MODE_TX_CALIBRATION,
+	MAX2831_MODE_RX_CALIBRATION,
 } max2831_mode_t;

 typedef enum {
@ -48,22 +48,22 @@ typedef enum {
 	MAX2831_RX_HPF_600_KHZ = 3,
 } max2831_rx_hpf_freq_t;

-typedef struct _max2831_driver_t {
+struct max2831_driver_t;
+typedef struct max2831_driver_t max2831_driver_t;
+
+struct max2831_driver_t {
 	spi_bus_t* bus;
-	void* config;
 	gpio_t gpio_enable;
 	gpio_t gpio_rxtx;
 	gpio_t gpio_rxhp;
 	gpio_t gpio_ld;
-	void (*target_init)(struct _max2831_driver_t* const drv);
-	void (*set_mode)(
-		struct _max2831_driver_t* const drv,
-		const max2831_mode_t new_mode);
+	void (*target_init)(max2831_driver_t* const drv);
+	void (*set_mode)(max2831_driver_t* const drv, const max2831_mode_t new_mode);
 	max2831_mode_t mode;
 	uint16_t regs[MAX2831_NUM_REGS];
 	uint16_t regs_dirty;
 	uint32_t desired_lpf_bw;
-} max2831_driver_t;
+};

 /* Initialize chip. */
 extern void max2831_setup(max2831_driver_t* const drv);
@ -88,11 +88,9 @@ void max2831_set_mode(max2831_driver_t* const drv, const max2831_mode_t new_mode
 extern void max2831_start(max2831_driver_t* const drv);
 extern void max2831_stop(max2831_driver_t* const drv);

-/* Set frequency in 1/(2**24) Hz */
-extern fp_40_24_t max2831_set_frequency(
-	max2831_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program);
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+extern void max2831_set_frequency(max2831_driver_t* const drv, uint32_t freq);
 uint32_t max2831_set_lpf_bandwidth(
 	max2831_driver_t* const drv,
 	const max2831_mode_t mode,
@ -110,3 +108,5 @@ extern void max2831_tx(max2831_driver_t* const drv);
 extern void max2831_rx(max2831_driver_t* const drv);
 extern void max2831_tx_calibration(max2831_driver_t* const drv);
 extern void max2831_rx_calibration(max2831_driver_t* const drv);
+
+#endif // __MAX2831_H
--- a/firmware/common/max2831_regs.def
+++ b/firmware/common/max2831_regs.def
@ -1,27 +1,7 @@
-/* -*- mode: c -*-
- *
- * Copyright 2012 Michael Ossmann
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
+/* -*- mode: c -*- */

-#pragma once
+#ifndef __MAX2831_REGS_DEF
+#define __MAX2831_REGS_DEF

 /* Generate static inline accessors that operate on the global
 * regs. Done this way to (1) allow defs to be scraped out and used
@ -148,3 +128,5 @@ __MREG__(MAX2831_RXIQ_VCM,15,10,2)  // RX I/Q output common mode
 #define MAX2831_RXIQ_VCM_1_2  1  // 1.2V
 #define MAX2831_RXIQ_VCM_1_3  2  // 1.3V
 #define MAX2831_RXIQ_VCM_1_45 3  // 1.45V
+
+#endif // __MAX2831_REGS_DEF
--- a/firmware/common/max2831_target.c
+++ b/firmware/common/max2831_target.c
@ -22,19 +22,15 @@
 #include "max2831_target.h"

 #include <libopencm3/lpc43xx/scu.h>
-
-#include "gpio.h"
-#include "platform_scu.h"
+#include "hackrf_core.h"

 void max2831_target_init(max2831_driver_t* const drv)
 {
-	const platform_scu_t* scu = platform_scu();
-
 	/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
-	scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));

-	scu_pinmux(scu->XCVR_CS, scu->XCVR_CS_PINCFG);
+	scu_pinmux(SCU_XCVR_CS, SCU_XCVR_CS_PINCFG);

 	/*
 	 * Configure XCVR_CTL GPIO pins.
@ -43,10 +39,10 @@ void max2831_target_init(max2831_driver_t* const drv)
 	 * MAX2837 which had a separate TXENABLE. On MAX2831 a single RXTX pin
 	 * switches between RX (high) and TX (low) modes.
 	 */
-	scu_pinmux(scu->XCVR_ENABLE, scu->XCVR_ENABLE_PINCFG);
-	scu_pinmux(scu->XCVR_RXENABLE, scu->XCVR_RXENABLE_PINCFG);
-	scu_pinmux(scu->XCVR_RXHP, scu->XCVR_RXHP_PINCFG);
-	scu_pinmux(scu->XCVR_LD, scu->XCVR_LD_PINCFG);
+	scu_pinmux(SCU_XCVR_ENABLE, SCU_XCVR_ENABLE_PINCFG);
+	scu_pinmux(SCU_XCVR_RXENABLE, SCU_XCVR_RXENABLE_PINCFG);
+	scu_pinmux(SCU_XCVR_RXHP, SCU_XCVR_RXHP_PINCFG);
+	scu_pinmux(SCU_XCVR_LD, SCU_XCVR_LD_PINCFG);

 	/* Set GPIO pins as outputs. */
 	gpio_output(drv->gpio_enable);
--- a/firmware/common/max2831_target.h
+++ b/firmware/common/max2831_target.h
@ -19,9 +19,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __MAX2831_TARGET_H
+#define __MAX2831_TARGET_H

 #include "max2831.h"

 void max2831_target_init(max2831_driver_t* const drv);
 void max2831_target_set_mode(max2831_driver_t* const drv, const max2831_mode_t new_mode);
+
+#endif // __MAX2831_TARGET_H
--- a/firmware/common/max2837.c
+++ b/firmware/common/max2837.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 * Copyright 2012 Will Code <willcode4@gmail.com>
 * Copyright 2014 Jared Boone <jared@sharebrained.com>
 *
@ -29,18 +29,12 @@
 * pirate commands to do the same thing.
 */

-#include "max2837.h"
-
-#include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
-#include "fixed_point.h"
+#include "max2837.h"
 #include "max2837_regs.def" // private register def macros
 #include "selftest.h"

-#define MIN(x, y) ((x) < (y) ? (x) : (y))
-#define MAX(x, y) ((x) > (y) ? (x) : (y))
-
 /* Default register values. */
 static const uint16_t max2837_regs_default[MAX2837_NUM_REGS] = {
 	0x150, /* 0 */
@ -156,14 +150,14 @@ void max2837_setup(max2837_driver_t* const drv)
 static uint16_t max2837_read(max2837_driver_t* const drv, uint8_t r)
 {
 	uint16_t value = (1 << 15) | (r << 10);
-	spi_bus_transfer(drv->bus, drv->config, &value, 1);
+	spi_bus_transfer(drv->bus, &value, 1);
 	return value & 0x3ff;
 }

 static void max2837_write(max2837_driver_t* const drv, uint8_t r, uint16_t v)
 {
 	uint16_t value = (r << 10) | (v & 0x3ff);
-	spi_bus_transfer(drv->bus, drv->config, &value, 1);
+	spi_bus_transfer(drv->bus, &value, 1);
 }

 uint16_t max2837_reg_read(max2837_driver_t* const drv, uint8_t r)
@ -234,32 +228,24 @@ void max2837_stop(max2837_driver_t* const drv)
 	max2837_set_mode(drv, MAX2837_MODE_SHUTDOWN);
 }

-/* Assume 40 MHz reference clock with R divider of 1. */
-#define PFD_FREQ_HZ (40ULL * (1000ULL * 1000ULL))
-
-#define MIN_FREQ FP_MHZ(2000)
-#define MAX_FREQ FP_MHZ(3000)
-
-fp_40_24_t max2837_set_frequency(
-	max2837_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program)
+void max2837_set_frequency(max2837_driver_t* const drv, uint32_t freq)
 {
 	uint8_t band;
 	uint8_t lna_band;
-	uint64_t div;
-
-	freq = MIN(freq, MAX_FREQ);
-	freq = MAX(freq, MIN_FREQ);
+	uint32_t div_frac;
+	uint32_t div_int;
+	uint32_t div_rem;
+	uint32_t div_cmp;
+	int i;

 	/* Select band. Allow tuning outside specified bands. */
-	if (freq < FP_MHZ(2400)) {
+	if (freq < 2400000000U) {
 		band = MAX2837_LOGEN_BSW_2_3;
 		lna_band = MAX2837_LNAband_2_4;
-	} else if (freq < FP_MHZ(2500)) {
+	} else if (freq < 2500000000U) {
 		band = MAX2837_LOGEN_BSW_2_4;
 		lna_band = MAX2837_LNAband_2_4;
-	} else if (freq < FP_MHZ(2600)) {
+	} else if (freq < 2600000000U) {
 		band = MAX2837_LOGEN_BSW_2_5;
 		lna_band = MAX2837_LNAband_2_6;
 	} else {
@ -267,34 +253,35 @@ fp_40_24_t max2837_set_frequency(
 		lna_band = MAX2837_LNAband_2_6;
 	}

-	fp_40_24_t vco = (freq * 4) / 3;
-
-	vco += ((PFD_FREQ_HZ * FP_ONE_HZ) >> 21); /* round to nearest frequency */
-	div = vco / PFD_FREQ_HZ;
-
-	/*
-	 * Shift from 40.24 fixed-point to 44.20 to match 20-bit fractional
-	 * divider.
-	 */
-	div = div >> 4;
-
-	if (program) {
-		/* Band settings */
-		set_MAX2837_LOGEN_BSW(drv, band);
-		set_MAX2837_LNAband(drv, lna_band);
-
-		/*
-		 * Write order matters here, so commit INT and FRAC_HI before
-		 * committing FRAC_LO, which is the trigger for VCO auto-select.
-		 */
-		set_MAX2837_SYN_INT(drv, (div >> 20) & 0xff);
-		set_MAX2837_SYN_FRAC_HI(drv, (div >> 10) & 0x3ff);
-		max2837_regs_commit(drv);
-		set_MAX2837_SYN_FRAC_LO(drv, div & 0x3ff);
-		max2837_regs_commit(drv);
+	/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
+	freq += (30000000 >> 21); /* round to nearest frequency */
+	div_int = freq / 30000000;
+	div_rem = freq % 30000000;
+	div_frac = 0;
+	div_cmp = 30000000;
+	for (i = 0; i < 20; i++) {
+		div_frac <<= 1;
+		div_rem <<= 1;
+		if (div_rem >= div_cmp) {
+			div_frac |= 0x1;
+			div_rem -= div_cmp;
+		}
 	}

-	return ((PFD_FREQ_HZ * 3) / 4) * (div << 4);
+	/* Band settings */
+	set_MAX2837_LOGEN_BSW(drv, band);
+	set_MAX2837_LNAband(drv, lna_band);
+
+	/* Write order matters here, so commit INT and FRAC_HI before
+	 * committing FRAC_LO, which is the trigger for VCO
+	 * auto-select. TODO - it's cleaner this way, but it would be
+	 * faster to explicitly commit the registers explicitly so the
+	 * dirty bits aren't scanned twice. */
+	set_MAX2837_SYN_INT(drv, div_int);
+	set_MAX2837_SYN_FRAC_HI(drv, (div_frac >> 10) & 0x3ff);
+	max2837_regs_commit(drv);
+	set_MAX2837_SYN_FRAC_LO(drv, div_frac & 0x3ff);
+	max2837_regs_commit(drv);
 }

 typedef struct {
--- a/firmware/common/max2837.h
+++ b/firmware/common/max2837.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 * Copyright 2012 Will Code <willcode4@gmail.com>
 * Copyright 2014 Jared Boone <jared@sharebrained.com>
 *
@ -21,12 +21,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __MAX2837_H
+#define __MAX2837_H

-#include <stdbool.h>
 #include <stdint.h>
+#include <stdbool.h>

-#include "fixed_point.h"
 #include "gpio.h"
 #include "spi_bus.h"

@ -41,20 +41,20 @@ typedef enum {
 	MAX2837_MODE_RX
 } max2837_mode_t;

-typedef struct _max2837_driver_t {
+struct max2837_driver_t;
+typedef struct max2837_driver_t max2837_driver_t;
+
+struct max2837_driver_t {
 	spi_bus_t* bus;
-	void* config;
 	gpio_t gpio_enable;
 	gpio_t gpio_rx_enable;
 	gpio_t gpio_tx_enable;
-	void (*target_init)(struct _max2837_driver_t* const drv);
-	void (*set_mode)(
-		struct _max2837_driver_t* const drv,
-		const max2837_mode_t new_mode);
+	void (*target_init)(max2837_driver_t* const drv);
+	void (*set_mode)(max2837_driver_t* const drv, const max2837_mode_t new_mode);
 	max2837_mode_t mode;
 	uint16_t regs[MAX2837_NUM_REGS];
 	uint32_t regs_dirty;
-} max2837_driver_t;
+};

 /* Initialize chip. */
 extern void max2837_setup(max2837_driver_t* const drv);
@ -79,11 +79,9 @@ void max2837_set_mode(max2837_driver_t* const drv, const max2837_mode_t new_mode
 extern void max2837_start(max2837_driver_t* const drv);
 extern void max2837_stop(max2837_driver_t* const drv);

-/* Set frequency in 1/(2**24) Hz. */
-extern fp_40_24_t max2837_set_frequency(
-	max2837_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program);
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+extern void max2837_set_frequency(max2837_driver_t* const drv, uint32_t freq);
 uint32_t max2837_set_lpf_bandwidth(
 	max2837_driver_t* const drv,
 	const uint32_t bandwidth_hz);
@ -93,3 +91,5 @@ bool max2837_set_txvga_gain(max2837_driver_t* const drv, const uint32_t gain_db)

 extern void max2837_tx(max2837_driver_t* const drv);
 extern void max2837_rx(max2837_driver_t* const drv);
+
+#endif // __MAX2837_H
--- a/firmware/common/max2837_regs.def
+++ b/firmware/common/max2837_regs.def
@ -1,26 +1,7 @@
-/* -*- mode: c -*-  *
- * Copyright 2012 Michael Ossmann
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
+/* -*- mode: c -*- */

-#pragma once
+#ifndef __MAX2837_REGS_DEF
+#define __MAX2837_REGS_DEF

 /* Generate static inline accessors that operate on the global
 * regs. Done this way to (1) allow defs to be scraped out and used
@ -423,3 +404,5 @@ __MREG__(MAX2837_FUSE_RTH,30,9,1)
 // 0 -> 992/0uA correction, 15 -> 0/992uA correction ... if TX_DCCORR_SPI_EN
 __MREG__(MAX2837_TX_DCCORR_I,31,4,5)
 __MREG__(MAX2837_TX_DCCORR_Q,31,9,5)
+
+#endif // __MAX2837_REGS_DEF
--- a/firmware/common/max2837_target.c
+++ b/firmware/common/max2837_target.c
@ -24,25 +24,21 @@
 #include "max2837_target.h"

 #include <libopencm3/lpc43xx/scu.h>
-
-#include "gpio.h"
-#include "platform_scu.h"
+#include "hackrf_core.h"

 void max2837_target_init(max2837_driver_t* const drv)
 {
-	const platform_scu_t* scu = platform_scu();
-
 	/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
-	scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));

-	scu_pinmux(scu->XCVR_CS, scu->XCVR_CS_PINCFG);
+	scu_pinmux(SCU_XCVR_CS, SCU_XCVR_CS_PINCFG);

 	/* Configure XCVR_CTL GPIO pins. */
-	scu_pinmux(scu->XCVR_ENABLE, scu->XCVR_ENABLE_PINCFG);
-	scu_pinmux(scu->XCVR_RXENABLE, scu->XCVR_RXENABLE_PINCFG);
-	scu_pinmux(scu->XCVR_TXENABLE, scu->XCVR_TXENABLE_PINCFG);
+	scu_pinmux(SCU_XCVR_ENABLE, SCU_XCVR_ENABLE_PINCFG);
+	scu_pinmux(SCU_XCVR_RXENABLE, SCU_XCVR_RXENABLE_PINCFG);
+	scu_pinmux(SCU_XCVR_TXENABLE, SCU_XCVR_TXENABLE_PINCFG);

 	/* Set GPIO pins as outputs. */
 	gpio_output(drv->gpio_enable);
--- a/firmware/common/max2837_target.h
+++ b/firmware/common/max2837_target.h
@ -21,9 +21,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __MAX2837_TARGET_H
+#define __MAX2837_TARGET_H

 #include "max2837.h"

 void max2837_target_init(max2837_driver_t* const drv);
 void max2837_target_set_mode(max2837_driver_t* const drv, const max2837_mode_t new_mode);
+
+#endif // __MAX2837_TARGET_H
--- a/firmware/common/max2839.c
+++ b/firmware/common/max2839.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 * Copyright 2012 Will Code <willcode4@gmail.com>
 * Copyright 2014 Jared Boone <jared@sharebrained.com>
 *
@ -29,18 +29,12 @@
 * pirate commands to do the same thing.
 */

-#include "max2839.h"
-
-#include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
-#include "fixed_point.h"
+#include "max2839.h"
 #include "max2839_regs.def" // private register def macros
 #include "selftest.h"

-#define MIN(x, y) ((x) < (y) ? (x) : (y))
-#define MAX(x, y) ((x) > (y) ? (x) : (y))
-
 static uint8_t requested_lna_gain = 0;
 static uint8_t requested_vga_gain = 0;

@ -164,14 +158,14 @@ void max2839_setup(max2839_driver_t* const drv)
 static uint16_t max2839_read(max2839_driver_t* const drv, uint8_t r)
 {
 	uint16_t value = (1 << 15) | (r << 10);
-	spi_bus_transfer(drv->bus, drv->config, &value, 1);
+	spi_bus_transfer(drv->bus, &value, 1);
 	return value & 0x3ff;
 }

 static void max2839_write(max2839_driver_t* const drv, uint8_t r, uint16_t v)
 {
 	uint16_t value = (r << 10) | (v & 0x3ff);
-	spi_bus_transfer(drv->bus, drv->config, &value, 1);
+	spi_bus_transfer(drv->bus, &value, 1);
 }

 uint16_t max2839_reg_read(max2839_driver_t* const drv, uint8_t r)
@ -245,61 +239,54 @@ void max2839_stop(max2839_driver_t* const drv)
 	max2839_set_mode(drv, MAX2839_MODE_SHUTDOWN);
 }

-/* Assume 40 MHz reference clock with R divider of 1. */
-#define PFD_FREQ_HZ (40ULL * (1000ULL * 1000ULL))
-
-#define MIN_FREQ FP_MHZ(2000)
-#define MAX_FREQ FP_MHZ(3000)
-
-fp_40_24_t max2839_set_frequency(
-	max2839_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program)
+void max2839_set_frequency(max2839_driver_t* const drv, uint32_t freq)
 {
 	uint8_t band;
-	uint64_t div;
-
-	freq = MIN(freq, MAX_FREQ);
-	freq = MAX(freq, MIN_FREQ);
+	uint32_t div_frac;
+	uint32_t div_int;
+	uint32_t div_rem;
+	uint32_t div_cmp;
+	int i;

 	/* Select band. Allow tuning outside specified bands. */
-	if (freq < FP_MHZ(2400)) {
+	if (freq < 2400000000U) {
 		band = MAX2839_LOGEN_BSW_2_3;
-	} else if (freq < FP_MHZ(2500)) {
+	} else if (freq < 2500000000U) {
 		band = MAX2839_LOGEN_BSW_2_4;
-	} else if (freq < FP_MHZ(2600)) {
+	} else if (freq < 2600000000U) {
 		band = MAX2839_LOGEN_BSW_2_5;
 	} else {
 		band = MAX2839_LOGEN_BSW_2_6;
 	}

-	fp_40_24_t vco = (freq * 4) / 3;
-
-	vco += ((PFD_FREQ_HZ * FP_ONE_HZ) >> 21); /* round to nearest frequency */
-	div = vco / PFD_FREQ_HZ;
-
-	/*
-	 * Shift from 40.24 fixed-point to 44.20 to match 20-bit fractional
-	 * divider.
-	 */
-	div = div >> 4;
-
-	if (program) {
-		/* Band settings */
-		set_MAX2839_LOGEN_BSW(drv, band);
-
-		/*
-		 * Write order matters here, so commit INT and FRAC_HI before
-		 * committing FRAC_LO, which is the trigger for VCO auto-select.
-		 */
-		set_MAX2839_SYN_INT(drv, (div >> 20) & 0xff);
-		set_MAX2839_SYN_FRAC_HI(drv, (div >> 10) & 0x3ff);
-		max2839_regs_commit(drv);
-		set_MAX2839_SYN_FRAC_LO(drv, div & 0x3ff);
-		max2839_regs_commit(drv);
+	/* ASSUME 40MHz PLL. Ratio = F*(4/3)/40,000,000 = F/30,000,000 */
+	freq += (30000000 >> 21); /* round to nearest frequency */
+	div_int = freq / 30000000;
+	div_rem = freq % 30000000;
+	div_frac = 0;
+	div_cmp = 30000000;
+	for (i = 0; i < 20; i++) {
+		div_frac <<= 1;
+		div_rem <<= 1;
+		if (div_rem >= div_cmp) {
+			div_frac |= 0x1;
+			div_rem -= div_cmp;
+		}
 	}

-	return ((PFD_FREQ_HZ * 3) / 4) * (div << 4);
+	/* Band settings */
+	set_MAX2839_LOGEN_BSW(drv, band);
+
+	/* Write order matters here, so commit INT and FRAC_HI before
+	 * committing FRAC_LO, which is the trigger for VCO
+	 * auto-select. TODO - it's cleaner this way, but it would be
+	 * faster to explicitly commit the registers explicitly so the
+	 * dirty bits aren't scanned twice. */
+	set_MAX2839_SYN_INT(drv, div_int);
+	set_MAX2839_SYN_FRAC_HI(drv, (div_frac >> 10) & 0x3ff);
+	max2839_regs_commit(drv);
+	set_MAX2839_SYN_FRAC_LO(drv, div_frac & 0x3ff);
+	max2839_regs_commit(drv);
 }

 typedef struct {
--- a/firmware/common/max2839.h
+++ b/firmware/common/max2839.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 * Copyright 2012 Will Code <willcode4@gmail.com>
 * Copyright 2014 Jared Boone <jared@sharebrained.com>
 *
@ -21,12 +21,12 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __MAX2839_H
+#define __MAX2839_H

-#include <stdbool.h>
 #include <stdint.h>
+#include <stdbool.h>

-#include "fixed_point.h"
 #include "gpio.h"
 #include "spi_bus.h"

@ -44,19 +44,19 @@ typedef enum {
 	MAX2839_MODE_CLKOUT,
 } max2839_mode_t;

-typedef struct _max2839_driver_t {
+struct max2839_driver_t;
+typedef struct max2839_driver_t max2839_driver_t;
+
+struct max2839_driver_t {
 	spi_bus_t* bus;
-	void* config;
 	gpio_t gpio_enable;
 	gpio_t gpio_rxtx;
-	void (*target_init)(struct _max2839_driver_t* const drv);
-	void (*set_mode)(
-		struct _max2839_driver_t* const drv,
-		const max2839_mode_t new_mode);
+	void (*target_init)(max2839_driver_t* const drv);
+	void (*set_mode)(max2839_driver_t* const drv, const max2839_mode_t new_mode);
 	max2839_mode_t mode;
 	uint16_t regs[MAX2839_NUM_REGS];
 	uint32_t regs_dirty;
-} max2839_driver_t;
+};

 /* Initialize chip. */
 extern void max2839_setup(max2839_driver_t* const drv);
@ -81,11 +81,9 @@ void max2839_set_mode(max2839_driver_t* const drv, const max2839_mode_t new_mode
 extern void max2839_start(max2839_driver_t* const drv);
 extern void max2839_stop(max2839_driver_t* const drv);

-/* Set frequency in 1/(2**24) Hz. */
-extern fp_40_24_t max2839_set_frequency(
-	max2839_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program);
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+extern void max2839_set_frequency(max2839_driver_t* const drv, uint32_t freq);
 uint32_t max2839_set_lpf_bandwidth(
 	max2839_driver_t* const drv,
 	const uint32_t bandwidth_hz);
@ -95,3 +93,5 @@ bool max2839_set_txvga_gain(max2839_driver_t* const drv, const uint32_t gain_db)

 extern void max2839_tx(max2839_driver_t* const drv);
 extern void max2839_rx(max2839_driver_t* const drv);
+
+#endif // __MAX2839_H
--- a/firmware/common/max2839_regs.def
+++ b/firmware/common/max2839_regs.def
@ -1,26 +1,7 @@
-/* -*- mode: c -*-  *
- * Copyright 2012 Michael Ossmann
- * Copyright 2025-2026 Great Scott Gadgets <info@greatscottgadgets.com>
- *
- * This file is part of HackRF.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.  If not, write to
- * the Free Software Foundation, Inc., 51 Franklin Street,
- * Boston, MA 02110-1301, USA.
- */
+/* -*- mode: c -*- */

-#pragma once
+#ifndef __MAX2839_REGS_DEF
+#define __MAX2839_REGS_DEF

 /* Generate static inline accessors that operate on the global
 * regs. Done this way to (1) allow defs to be scraped out and used
@ -274,3 +255,5 @@ __MREG__(MAX2839_PA_DAC_Voltage_Mode_Output_Select,30,9,1)
 __MREG__(MAX2839_TX_DC_Offset_Correction_QChannel,31,5,6)
 __MREG__(MAX2839_RESERVED_31_8,31,8,3)
 __MREG__(MAX2839_PA_DAC_Clk_Divide_Ratio,31,9,1)
+
+#endif // __MAX2839_REGS_DEF
--- a/firmware/common/max2839_target.c
+++ b/firmware/common/max2839_target.c
@ -24,20 +24,16 @@
 #include "max2839_target.h"

 #include <libopencm3/lpc43xx/scu.h>
-
-#include "gpio.h"
-#include "platform_scu.h"
+#include "hackrf_core.h"

 void max2839_target_init(max2839_driver_t* const drv)
 {
-	const platform_scu_t* scu = platform_scu();
-
 	/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
-	scu_pinmux(scu->SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
-	scu_pinmux(scu->SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+	scu_pinmux(SCU_SSP1_CIPO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_COPI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+	scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));

-	scu_pinmux(scu->XCVR_CS, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);

 	/*
 	 * Configure XCVR_CTL GPIO pins.
@ -46,8 +42,8 @@ void max2839_target_init(max2839_driver_t* const drv)
 	 * MAX2837 which had a separate TXENABLE. On MAX2839 a single RXTX pin
 	 * switches between RX (high) and TX (low) modes.
 	 */
-	scu_pinmux(scu->XCVR_ENABLE, SCU_GPIO_FAST);
-	scu_pinmux(scu->XCVR_RXENABLE, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_ENABLE, SCU_GPIO_FAST);
+	scu_pinmux(SCU_XCVR_RXENABLE, SCU_GPIO_FAST);

 	/* Set GPIO pins as outputs. */
 	gpio_output(drv->gpio_enable);
--- a/firmware/common/max2839_target.h
+++ b/firmware/common/max2839_target.h
@ -21,7 +21,12 @@
 * Boston, MA 02110-1301, USA.
 */

+#ifndef __MAX2839_TARGET_H
+#define __MAX2839_TARGET_H
+
 #include "max2839.h"

 void max2839_target_init(max2839_driver_t* const drv);
 void max2839_target_set_mode(max2839_driver_t* const drv, const max2839_mode_t new_mode);
+
+#endif // __MAX2839_TARGET_H
--- a/firmware/common/max283x.c
+++ b/firmware/common/max283x.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 * Copyright 2012 Will Code <willcode4@gmail.com>
 * Copyright 2014 Jared Boone <jared@sharebrained.com>
 *
@ -23,201 +23,89 @@

 #include "max283x.h"

-#include <stdbool.h>
-#include <string.h>
+#include "gpio.h"
+#include "gpio_lpc.h"
+#include "max2837.h"
+#include "max2837_target.h"
+#include "max2839.h"
+#include "max2839_target.h"
+#include "spi_bus.h"

-#include <libopencm3/lpc43xx/ssp.h>
-
-#include "fixed_point.h"
-#include "platform_detect.h"
-#include "platform_gpio.h"
-
-#ifdef IS_PRALINE
-	#include "max2831_target.h"
-#endif
-#ifdef IS_NOT_PRALINE
-	#include "max2837_target.h"
-#endif
-#ifdef IS_H1_R9
-	#include "max2839_target.h"
+extern spi_bus_t spi_bus_ssp1;
+#ifdef PRALINE
+static struct gpio gpio_max2837_enable = GPIO(6, 29);
+static struct gpio gpio_max2837_rx_enable = GPIO(3, 3);
+static struct gpio gpio_max2837_tx_enable = GPIO(3, 2);
+#else
+static struct gpio gpio_max2837_enable = GPIO(2, 6);
+static struct gpio gpio_max2837_rx_enable = GPIO(2, 5);
+static struct gpio gpio_max2837_tx_enable = GPIO(2, 4);
 #endif

-/* Driver instance. */
-ssp_config_t ssp_config_max283x = {
-	/* FIXME speed up once everything is working reliably */
-	/*
-	// Freq About 0.0498MHz / 49.8KHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
-	const uint8_t serial_clock_rate = 32;
-	const uint8_t clock_prescale_rate = 128;
-	*/
-	// Freq About 4.857MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=204MHz
-	.serial_clock_rate = 21,
-	.clock_prescale_rate = 2,
-};
-
-max283x_driver_t max283x = {};
-
-#ifdef IS_PRALINE
-max2831_driver_t max2831 = {
-	.bus = &spi_bus_ssp1,
-	.config = &ssp_config_max283x,
-	.target_init = max2831_target_init,
-	.set_mode = max2831_target_set_mode,
-};
-#endif
-
-#ifdef IS_NOT_PRALINE
 max2837_driver_t max2837 = {
 	.bus = &spi_bus_ssp1,
-	.config = &ssp_config_max283x,
+	.gpio_enable = &gpio_max2837_enable,
+	.gpio_rx_enable = &gpio_max2837_rx_enable,
+	.gpio_tx_enable = &gpio_max2837_tx_enable,
 	.target_init = max2837_target_init,
 	.set_mode = max2837_target_set_mode,
 };
-#endif

-#ifdef IS_HACKRF_ONE
 max2839_driver_t max2839 = {
 	.bus = &spi_bus_ssp1,
-	.config = &ssp_config_max283x,
+	.gpio_enable = &gpio_max2837_enable,
+	.gpio_rxtx = &gpio_max2837_rx_enable,
 	.target_init = max2839_target_init,
 	.set_mode = max2839_target_set_mode,
 };
-#endif

 /* Initialize chip. */
-void max283x_setup(max283x_driver_t* const drv)
+void max283x_setup(max283x_driver_t* const drv, max283x_variant_t type)
 {
-	const platform_gpio_t* gpio = platform_gpio();
+	drv->type = type;
+	switch (type) {
+	case MAX2837_VARIANT:
+		memcpy(&drv->drv.max2837, &max2837, sizeof(max2837));
+		max2837_setup(&drv->drv.max2837);
+		break;

-	/* MAX283x GPIO PinMux */
-	ssp_config_max283x.gpio_select = gpio->max283x_select;
-#ifdef IS_PRALINE
-	if (IS_PRALINE) {
-		ssp_config_max283x.data_bits = SSP_DATA_9BITS;
-		drv->type = MAX2831_VARIANT;
-		max2831.gpio_enable = gpio->max283x_enable;
-		max2831.gpio_rxtx = gpio->max283x_rx_enable;
-		max2831.gpio_rxhp = gpio->max2831_rxhp;
-		max2831.gpio_ld = gpio->max2831_ld;
-		memcpy(&drv->drv.max2831, &max2831, sizeof(max2831));
-		max2831_setup(&drv->drv.max2831);
+	case MAX2839_VARIANT:
+		memcpy(&drv->drv.max2839, &max2839, sizeof(max2839));
+		max2839_setup(&drv->drv.max2839);
+		break;
 	}
-#endif
-#ifdef IS_NOT_PRALINE
-	if (IS_NOT_PRALINE) {
-		ssp_config_max283x.data_bits = SSP_DATA_16BITS;
-	#ifdef IS_H1_R9
-		if (IS_H1_R9) {
-			drv->type = MAX2839_VARIANT;
-			max2839.gpio_enable = gpio->max283x_enable;
-			max2839.gpio_rxtx = gpio->max283x_rx_enable;
-			memcpy(&drv->drv.max2839, &max2839, sizeof(max2839));
-			max2839_setup(&drv->drv.max2839);
-		}
-	#endif
-	#ifdef IS_NOT_H1_R9
-		if (IS_NOT_H1_R9) {
-			drv->type = MAX2837_VARIANT;
-			max2837.gpio_enable = gpio->max283x_enable;
-			max2837.gpio_rx_enable = gpio->max283x_rx_enable;
-			max2837.gpio_tx_enable = gpio->max283x_tx_enable;
-			memcpy(&drv->drv.max2837, &max2837, sizeof(max2837));
-			max2837_setup(&drv->drv.max2837);
-		}
-	#endif
-	}
-#endif
-}
-
-/* Macros to simplify dispatch of variant-specific operations. */
-
-/* clang-format off */
-
-#if UNIVERSAL
-	// UNIVERSAL: all variants
-	#define DISPATCH(_drv, _max2831, _max2837, _max2839) \
-		if (_drv->type == MAX2831_VARIANT) { \
-			_max2831; \
-		} else if (_drv->type == MAX2837_VARIANT) { \
-			_max2837; \
-		} else { \
-			_max2839; \
-		}
-#elif HACKRF_ONE
-	// HACKRF_ONE: MAX2837 and MAX2839 only
-	#define DISPATCH(_drv, _max2831, _max2837, _max2839) \
-		if (_drv->type == MAX2837_VARIANT) { \
-			_max2837; \
-		} else { \
-			_max2839; \
-		}
-#elif PRALINE
-	// PRALINE: MAX2831 only
-	#define DISPATCH(_drv, _max2831, _max2837, _max2839) \
-		(void) drv; \
-		_max2831
-#else
-	// JAWBREAKER, RAD1O: MAX2837 only
-	#define DISPATCH(_drv, _max2831, _max2837, _max2839) \
-		(void) drv; \
-		_max2837
-#endif
-
-#define CALL(_drv, _func, ...) \
-	DISPATCH(drv, \
-		max2831_ ## _func(&_drv->drv.max2831, ##__VA_ARGS__), \
-		max2837_ ## _func(&_drv->drv.max2837, ##__VA_ARGS__), \
-		max2839_ ## _func(&_drv->drv.max2839, ##__VA_ARGS__) \
-	); \
-
-#define RESULT(_drv, _type, _func, ...) ({ \
-	_type _result; \
-	DISPATCH(drv, \
-		_result = max2831_ ## _func(&_drv->drv.max2831, ##__VA_ARGS__), \
-		_result = max2837_ ## _func(&_drv->drv.max2837, ##__VA_ARGS__), \
-		_result = max2839_ ## _func(&_drv->drv.max2839, ##__VA_ARGS__) \
-	); \
-	_result; \
-})
-
-#define CONSTANT(_drv, _type, _name) ({\
-	_type value; \
-	DISPATCH(drv, \
-		value = MAX2831_ ## _name, \
-		value = MAX2837_ ## _name, \
-		value = MAX2839_ ## _name \
-	); \
-	value; \
-})
-
-#define PRALINE_ONLY(_drv, _max2831) DISPATCH(_drv, _max2831, , )
-
-/* clang-format on */
-
-/* Returns the number of registers supported by the driver. */
-uint16_t max283x_num_regs(max283x_driver_t* const drv)
-{
-	return CONSTANT(drv, uint16_t, NUM_REGS);
-}
-
-/* Returns the maximum data register value supported by the driver. */
-uint16_t max283x_data_regs_max_value(max283x_driver_t* const drv)
-{
-	return CONSTANT(drv, uint16_t, DATA_REGS_MAX_VALUE);
 }

 /* Read a register via SPI. Save a copy to memory and return
 * value. Mark clean. */
 uint16_t max283x_reg_read(max283x_driver_t* const drv, uint8_t r)
 {
-	return RESULT(drv, uint16_t, reg_read, r);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		return max2837_reg_read(&drv->drv.max2837, r);
+		break;
+
+	case MAX2839_VARIANT:
+		return max2839_reg_read(&drv->drv.max2839, r);
+		break;
+	}
+
+	return 0;
 }

 /* Write value to register via SPI and save a copy to memory. Mark
 * clean. */
 void max283x_reg_write(max283x_driver_t* const drv, uint8_t r, uint16_t v)
 {
-	CALL(drv, reg_write, r, v);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_reg_write(&drv->drv.max2837, r, v);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_reg_write(&drv->drv.max2839, r, v);
+		break;
+	}
 }

 /* Write all dirty registers via SPI from memory. Mark all clean. Some
@ -225,107 +113,174 @@ void max283x_reg_write(max283x_driver_t* const drv, uint8_t r, uint16_t v)
 * provided routines for those operations. */
 void max283x_regs_commit(max283x_driver_t* const drv)
 {
-	CALL(drv, regs_commit);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_regs_commit(&drv->drv.max2837);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_regs_commit(&drv->drv.max2839);
+		break;
+	}
 }

 void max283x_set_mode(max283x_driver_t* const drv, const max283x_mode_t new_mode)
 {
-	DISPATCH(
-		drv,
-		max2831_set_mode(&drv->drv.max2831, (max2831_mode_t) new_mode),
-		max2837_set_mode(&drv->drv.max2837, (max2837_mode_t) new_mode),
-		max2839_set_mode(&drv->drv.max2839, (max2839_mode_t) new_mode));
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_set_mode(&drv->drv.max2837, (max2837_mode_t) new_mode);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_set_mode(&drv->drv.max2839, (max2839_mode_t) new_mode);
+		break;
+	}
 }

 max283x_mode_t max283x_mode(max283x_driver_t* const drv)
 {
-	DISPATCH(
-		drv,
-		return (max283x_mode_t) max2831_mode(&drv->drv.max2831),
-		return (max283x_mode_t) max2837_mode(&drv->drv.max2837),
-		return (max283x_mode_t) max2839_mode(&drv->drv.max2839));
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		return (max283x_mode_t) max2837_mode(&drv->drv.max2837);
+		break;
+
+	case MAX2839_VARIANT:
+		return (max283x_mode_t) max2839_mode(&drv->drv.max2839);
+		break;
+	}
+
+	return 0;
 }

+//max283x_mode_t max283x_mode(max283x_driver_t* const drv);
+//void max283x_set_mode(max283x_driver_t* const drv, const max283x_mode_t new_mode);
+
 /* Turn on/off all chip functions. Does not control oscillator and CLKOUT */
 void max283x_start(max283x_driver_t* const drv)
 {
-	CALL(drv, start);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_start(&drv->drv.max2837);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_start(&drv->drv.max2839);
+		break;
+	}
 }

 void max283x_stop(max283x_driver_t* const drv)
 {
-	CALL(drv, stop);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_stop(&drv->drv.max2837);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_stop(&drv->drv.max2839);
+		break;
+	}
 }

-/* Set frequency in 1/(2**24) Hz. */
-fp_40_24_t max283x_set_frequency(
-	max283x_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program)
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+void max283x_set_frequency(max283x_driver_t* const drv, uint32_t freq)
 {
-	return RESULT(drv, fp_40_24_t, set_frequency, freq, program);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_set_frequency(&drv->drv.max2837, freq);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_set_frequency(&drv->drv.max2839, freq);
+		break;
+	}
 }

 uint32_t max283x_set_lpf_bandwidth(
 	max283x_driver_t* const drv,
-	const max283x_mode_t mode,
 	const uint32_t bandwidth_hz)
 {
-	(void) mode;
-	DISPATCH(
-		drv,
-		return max2831_set_lpf_bandwidth(
-			&drv->drv.max2831,
-			(max2831_mode_t) mode,
-			bandwidth_hz),
-		return max2837_set_lpf_bandwidth(&drv->drv.max2837, bandwidth_hz),
-		return max2839_set_lpf_bandwidth(&drv->drv.max2839, bandwidth_hz));
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		return max2837_set_lpf_bandwidth(&drv->drv.max2837, bandwidth_hz);
+		break;
+
+	case MAX2839_VARIANT:
+		return max2839_set_lpf_bandwidth(&drv->drv.max2839, bandwidth_hz);
+		break;
+	}
+
+	return 0;
 }

 bool max283x_set_lna_gain(max283x_driver_t* const drv, const uint32_t gain_db)
 {
-	return RESULT(drv, bool, set_lna_gain, gain_db);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		return max2837_set_lna_gain(&drv->drv.max2837, gain_db);
+		break;
+
+	case MAX2839_VARIANT:
+		return max2839_set_lna_gain(&drv->drv.max2839, gain_db);
+		break;
+	}
+
+	return false;
 }

 bool max283x_set_vga_gain(max283x_driver_t* const drv, const uint32_t gain_db)
 {
-	return RESULT(drv, bool, set_vga_gain, gain_db);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		return max2837_set_vga_gain(&drv->drv.max2837, gain_db);
+		break;
+
+	case MAX2839_VARIANT:
+		return max2839_set_vga_gain(&drv->drv.max2839, gain_db);
+		break;
+	}
+
+	return false;
 }

 bool max283x_set_txvga_gain(max283x_driver_t* const drv, const uint32_t gain_db)
 {
-	return RESULT(drv, bool, set_txvga_gain, gain_db);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		return max2837_set_txvga_gain(&drv->drv.max2837, gain_db);
+		break;
+
+	case MAX2839_VARIANT:
+		return max2839_set_txvga_gain(&drv->drv.max2839, gain_db);
+		break;
+	}
+
+	return false;
 }

 void max283x_tx(max283x_driver_t* const drv)
 {
-	CALL(drv, tx);
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_tx(&drv->drv.max2837);
+		break;
+
+	case MAX2839_VARIANT:
+		max2839_tx(&drv->drv.max2839);
+		break;
+	}
 }

 void max283x_rx(max283x_driver_t* const drv)
 {
-	CALL(drv, rx);
-}
+	switch (drv->type) {
+	case MAX2837_VARIANT:
+		max2837_rx(&drv->drv.max2837);
+		break;

-/* Set MAX2831 receiver high-pass filter corner frequency in Hz */
-void max283x_set_rx_hpf_frequency(
-	max283x_driver_t* const drv,
-	const max283x_rx_hpf_freq_t freq)
-{
-	(void) freq;
-	PRALINE_ONLY(
-		drv,
-		max2831_set_rx_hpf_frequency(
-			&drv->drv.max2831,
-			(max2831_rx_hpf_freq_t) freq));
-}
-
-void max283x_tx_calibration(max283x_driver_t* const drv)
-{
-	PRALINE_ONLY(drv, max2831_tx_calibration(&drv->drv.max2831));
-}
-
-void max283x_rx_calibration(max283x_driver_t* const drv)
-{
-	PRALINE_ONLY(drv, max2831_rx_calibration(&drv->drv.max2831));
+	case MAX2839_VARIANT:
+		max2839_rx(&drv->drv.max2839);
+		break;
+	}
 }
--- a/firmware/common/max283x.h
+++ b/firmware/common/max283x.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2012-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2012-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 * Copyright 2012 Will Code <willcode4@gmail.com>
 * Copyright 2014 Jared Boone <jared@sharebrained.com>
 *
@ -21,23 +21,20 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef __MAX283x_H
+#define __MAX283x_H

-#include <stdbool.h>
 #include <stdint.h>
+#include <stdbool.h>
+#include <string.h>

-#include "fixed_point.h"
-#include "spi_ssp.h"
-
-#ifdef IS_PRALINE
-	#include "max2831.h"
-#endif
-#ifdef IS_NOT_PRALINE
-	#include "max2837.h"
-#endif
-#ifdef IS_H1_R9
-	#include "max2839.h"
-#endif
+#include "gpio.h"
+#include "gpio_lpc.h"
+#include "max2837.h"
+#include "max2837_target.h"
+#include "max2839.h"
+#include "max2839_target.h"
+#include "spi_bus.h"

 typedef enum {
 	MAX283x_MODE_SHUTDOWN,
@ -50,48 +47,21 @@ typedef enum {
 } max283x_mode_t;

 typedef enum {
-	MAX283x_RX_HPF_100_HZ = 0,
-	MAX283x_RX_HPF_4_KHZ = 1,
-	MAX283x_RX_HPF_30_KHZ = 2,
-	MAX283x_RX_HPF_600_KHZ = 3,
-} max283x_rx_hpf_freq_t;
-
-typedef enum {
-#ifdef IS_PRALINE
-	MAX2831_VARIANT,
-#endif
-#ifdef IS_NOT_PRALINE
 	MAX2837_VARIANT,
-#endif
-#ifdef IS_H1_R9
 	MAX2839_VARIANT,
-#endif
 } max283x_variant_t;

 typedef struct {
 	max283x_variant_t type;

 	union {
-#ifdef IS_PRALINE
-		max2831_driver_t max2831;
-#endif
-#ifdef IS_NOT_PRALINE
 		max2837_driver_t max2837;
-#endif
-#ifdef IS_H1_R9
 		max2839_driver_t max2839;
-#endif
 	} drv;
 } max283x_driver_t;

 /* Initialize chip. */
-void max283x_setup(max283x_driver_t* const drv);
-
-/* Returns the number of registers supported by the driver. */
-uint16_t max283x_num_regs(max283x_driver_t* const drv);
-
-/* Returns the maximum data register value supported by the driver. */
-uint16_t max283x_data_regs_max_value(max283x_driver_t* const drv);
+void max283x_setup(max283x_driver_t* const drv, max283x_variant_t type);

 /* Read a register via SPI. Save a copy to memory and return
 * value. Mark clean. */
@ -113,14 +83,11 @@ void max283x_set_mode(max283x_driver_t* const drv, const max283x_mode_t new_mode
 void max283x_start(max283x_driver_t* const drv);
 void max283x_stop(max283x_driver_t* const drv);

-/* Set frequency in 1/(2**24) Hz. */
-fp_40_24_t max283x_set_frequency(
-	max283x_driver_t* const drv,
-	fp_40_24_t freq,
-	bool program);
+/* Set frequency in Hz. Frequency setting is a multi-step function
+ * where order of register writes matters. */
+void max283x_set_frequency(max283x_driver_t* const drv, uint32_t freq);
 uint32_t max283x_set_lpf_bandwidth(
 	max283x_driver_t* const drv,
-	const max283x_mode_t mode,
 	const uint32_t bandwidth_hz);

 bool max283x_set_lna_gain(max283x_driver_t* const drv, const uint32_t gain_db);
@ -131,15 +98,4 @@ bool max283x_set_txvga_gain(max283x_driver_t* const drv, const uint32_t gain_db)
 void max283x_tx(max283x_driver_t* const drv);
 void max283x_rx(max283x_driver_t* const drv);

-/* Set MAX2831 receiver high-pass filter corner frequency in Hz */
-void max283x_set_rx_hpf_frequency(
-	max283x_driver_t* const drv,
-	const max283x_rx_hpf_freq_t freq);
-
-/* Perform MAX2831 TX and RX calibration. */
-void max283x_tx_calibration(max283x_driver_t* const drv);
-void max283x_rx_calibration(max283x_driver_t* const drv);
-
-/* Driver instance. */
-extern ssp_config_t ssp_config_max283x;
-extern max283x_driver_t max283x;
+#endif // __MAX283x_H
--- a/firmware/common/max2871.c
+++ b/firmware/common/max2871.c
@ -1,5 +1,5 @@
 /*
- * Copyright 2015-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2015-2022 Great Scott Gadgets <info@greatscottgadgets.com>
 *
 * This file is part of HackRF.
 *
@ -20,15 +20,7 @@
 */

 #include "max2871.h"
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <libopencm3/lpc43xx/scu.h>
-
-#include "fixed_point.h"
 #include "max2871_regs.h"
-#include "platform_scu.h"
 #include "selftest.h"

 #if (defined DEBUG)
@ -36,10 +28,13 @@
 	#define LOG printf
 #else
 	#define LOG(x, ...)
+	#include <libopencm3/lpc43xx/ssp.h>
+	#include <libopencm3/lpc43xx/scu.h>
+	#include "hackrf_core.h"
 #endif

-#define MIN(x, y) ((x) < (y) ? (x) : (y))
-#define MAX(x, y) ((x) > (y) ? (x) : (y))
+#include <stdint.h>
+#include <string.h>

 static uint32_t max2871_spi_read(max2871_driver_t* const drv);
 static void max2871_spi_write(max2871_driver_t* const drv, uint8_t r, uint32_t v);
@ -48,16 +43,14 @@ static void delay_ms(int ms);

 void max2871_setup(max2871_driver_t* const drv)
 {
-	const platform_scu_t* scu = platform_scu();
-
 	/* Configure GPIO pins. */
-	scu_pinmux(scu->VCO_CE, SCU_GPIO_FAST);
-	scu_pinmux(scu->VCO_SCLK, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
-	/* Only used for the debug pin config: scu_pinmux(scu->VCO_SCLK, SCU_GPIO_FAST); */
-	scu_pinmux(scu->VCO_SDATA, SCU_GPIO_FAST);
-	scu_pinmux(scu->VCO_LE, SCU_GPIO_FAST);
-	scu_pinmux(scu->VCO_MUX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
-	scu_pinmux(scu->SYNT_RFOUT_EN, SCU_GPIO_FAST);
+	scu_pinmux(SCU_VCO_CE, SCU_GPIO_FAST);
+	scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
+	/* Only used for the debug pin config: scu_pinmux(SCU_VCO_SCLK, SCU_GPIO_FAST); */
+	scu_pinmux(SCU_VCO_SDATA, SCU_GPIO_FAST);
+	scu_pinmux(SCU_VCO_LE, SCU_GPIO_FAST);
+	scu_pinmux(SCU_VCO_MUX, SCU_GPIO_FAST | SCU_CONF_FUNCTION4);
+	scu_pinmux(SCU_SYNT_RFOUT_EN, SCU_GPIO_FAST);

 	/* Set GPIO pins as outputs. */
 	gpio_output(drv->gpio_vco_ce);
@ -137,7 +130,7 @@ void max2871_setup(max2871_driver_t* const drv)

 	max2871_write_registers(drv);

-	max2871_set_frequency(drv, FP_MHZ(3500), true);
+	max2871_set_frequency(drv, 3500);
 }

 static void delay_ms(int ms)
@ -233,16 +226,9 @@ static void max2871_write_registers(max2871_driver_t* const drv)
 	}
 }

-#define MIN_LO FP_MHZ(40)
-#define MAX_LO FP_MHZ(6000)
-
-/* Set frequency in 1/(2**24) Hz, rounded to nearest 40 MHz. */
-fp_40_24_t max2871_set_frequency(max2871_driver_t* const drv, fp_40_24_t lo, bool program)
+/* Set frequency (MHz). */
+uint64_t max2871_set_frequency(max2871_driver_t* const drv, uint16_t mhz)
 {
-	lo = MIN(lo, MAX_LO);
-	lo = MAX(lo, MIN_LO);
-
-	uint16_t mhz = lo / FP_ONE_MHZ;
 	int n = mhz / 40;
 	int diva = 0;

@ -251,21 +237,19 @@ fp_40_24_t max2871_set_frequency(max2871_driver_t* const drv, fp_40_24_t lo, boo
 		diva += 1;
 	}

-	if (program) {
-		max2871_set_RFA_EN(0);
-		max2871_write_registers(drv);
+	max2871_set_RFA_EN(0);
+	max2871_write_registers(drv);

-		max2871_set_N(n);
-		max2871_set_DIVA(diva);
-		max2871_write_registers(drv);
+	max2871_set_N(n);
+	max2871_set_DIVA(diva);
+	max2871_write_registers(drv);

-		while (max2871_spi_read(drv) & MAX2871_VASA) {}
+	while (max2871_spi_read(drv) & MAX2871_VASA) {}

-		max2871_set_RFA_EN(1);
-		max2871_write_registers(drv);
-	}
+	max2871_set_RFA_EN(1);
+	max2871_write_registers(drv);

-	return (mhz / 40) * FP_MHZ(40);
+	return (mhz / 40) * 40 * 1000000;
 }

 void max2871_enable(max2871_driver_t* const drv)
--- a/firmware/common/max2871.h
+++ b/firmware/common/max2871.h
@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2026 Great Scott Gadgets <info@greatscottgadgets.com>
+ * Copyright 2017 Great Scott Gadgets <info@greatscottgadgets.com>
 *
 * This file is part of HackRF.
 *
@ -19,13 +19,13 @@
 * Boston, MA 02110-1301, USA.
 */

-#pragma once
+#ifndef MAX2871_H
+#define MAX2871_H

-#include <stdbool.h>
-
-#include "fixed_point.h"
 #include "gpio.h"

+#include <stdint.h>
+
 typedef struct {
 	gpio_t gpio_vco_ce;
 	gpio_t gpio_vco_sclk;
@ -36,9 +36,7 @@ typedef struct {
 } max2871_driver_t;

 extern void max2871_setup(max2871_driver_t* const drv);
-extern fp_40_24_t max2871_set_frequency(
-	max2871_driver_t* const drv,
-	fp_40_24_t lo,
-	bool program);
+extern uint64_t max2871_set_frequency(max2871_driver_t* const drv, uint16_t mhz);
 extern void max2871_enable(max2871_driver_t* const drv);
 extern void max2871_disable(max2871_driver_t* const drv);
+#endif
--- a/Show more
+++ b/Show more
Author	SHA1	Message	Date
Michael Ossmann	d2e4990563	Enable TX interpolation Some checks failed Build / firmware (JAWBREAKER, latest, ubuntu) (push) Failing after 8s Details Build / firmware (PRALINE, 3.10.0, ubuntu) (push) Failing after 6s Details Build / firmware (PRALINE, latest, ubuntu) (push) Failing after 7s Details Build / firmware (RAD1O, 3.10.0, ubuntu) (push) Failing after 10s Details Build / firmware (RAD1O, latest, ubuntu) (push) Failing after 13s Details Check code style / clang-format (push) Failing after 14s Details Check code style / clang-format-1 (push) Failing after 12s Details Check code style / clang-format-2 (push) Failing after 10s Details Check code style / clang-format-3 (push) Failing after 11s Details Build / host (4.0.0, -DPKG_CONFIG_EXECUTABLE=C:/vcpkg/installed/x64-windows/tools/pkgconf/pkgconf.exe -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake --install-prefix=$env:GITHUB_WORKSPACE/install, map[os:windows shell:pwsh]) (push) Has been cancelled Details Build / host (4.0.0, map[os:macos shell:bash]) (push) Has been cancelled Details Build / host (latest, --install-prefix=/usr/local, map[os:windows shell:msys2]) (push) Has been cancelled Details Build / host (latest, -DPKG_CONFIG_EXECUTABLE=C:/vcpkg/installed/x64-windows/tools/pkgconf/pkgconf.exe -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake --install-prefix=$env:GITHUB_WORKSPACE/install, map[os:windows shell:pwsh]) (push) Has been cancelled Details Build / host (latest, map[os:macos shell:bash]) (push) Has been cancelled Details Build / firmware (HACKRF_ONE, 3.10.0, macos) (push) Has been cancelled Details Build / firmware (HACKRF_ONE, latest, macos) (push) Has been cancelled Details Build / firmware (HACKRF_ONE, latest, windows) (push) Has been cancelled Details Build / firmware (JAWBREAKER, 3.10.0, macos) (push) Has been cancelled Details Build / firmware (JAWBREAKER, latest, macos) (push) Has been cancelled Details Build / firmware (JAWBREAKER, latest, windows) (push) Has been cancelled Details Build / firmware (PRALINE, 3.10.0, macos) (push) Has been cancelled Details Build / firmware (PRALINE, latest, macos) (push) Has been cancelled Details Build / firmware (PRALINE, latest, windows) (push) Has been cancelled Details Build / firmware (RAD1O, 3.10.0, macos) (push) Has been cancelled Details Build / firmware (RAD1O, latest, macos) (push) Has been cancelled Details Build / firmware (RAD1O, latest, windows) (push) Has been cancelled Details Build / host (3.10.0, map[os:macos shell:bash]) (push) Has been cancelled Details Build / host (3.16.0, map[os:macos shell:bash]) (push) Has been cancelled Details Build / host (3.21.0, -DPKG_CONFIG_EXECUTABLE=C:/vcpkg/installed/x64-windows/tools/pkgconf/pkgconf.exe -DCMAKE_TOOLCHAIN_FILE=C:/vcpkg/scripts/buildsystems/vcpkg.cmake --install-prefix=$env:GITHUB_WORKSPACE/install, map[os:windows shell:pwsh]) (push) Has been cancelled Details Build / host (3.21.0, map[os:macos shell:bash]) (push) Has been cancelled Details	2026-03-10 21:34:48 -04:00
Michael Ossmann	880a055e44	Add phase offset to FPGA_CLK/SCT_CLK In order to support higher DAC sample rates on Praline with interpolation, it is necessary to adjust the phase of FPGA_CLK with respect to AFE_CLK.	2026-03-10 18:16:07 -04:00