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x86: improve matching diagnostics when %st is involved
Diagnosing operand size vs operand type mismatches doesn't work very well when GPRs and FPRs are in the same register class, distinguished just by size. Introduce a separate RegFP class.
This commit is contained in:
Jan Beulich
parent
a7148a799b
commit
101b4bb8f4
8 changed files with 7476 additions and 7440 deletions
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@ -2497,8 +2497,8 @@ operand_type_check (i386_operand_type t, enum operand_type c)
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return 0;
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}
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/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
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between operand GIVEN and opeand WANTED for instruction template T. */
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/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit size
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between operand GIVEN and operand WANTED for instruction template T. */
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static INLINE int
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match_operand_size (const insn_template *t, unsigned int wanted,
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@ -2518,13 +2518,22 @@ match_operand_size (const insn_template *t, unsigned int wanted,
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|| (intel_syntax
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&& flag_code != CODE_64BIT
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&& (t->operand_types[wanted].bitfield.class == Reg
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|| t->opcode_modifier.isstring))))
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|| (i.types[given].bitfield.tbyte
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&& !t->operand_types[wanted].bitfield.tbyte));
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|| t->opcode_modifier.isstring)))));
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}
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/* Return 1 if there is no conflict in 80bit size
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between operand GIVEN and operand WANTED for instruction template T. */
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static INLINE int
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match_fp_size (const insn_template *t, unsigned int wanted,
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unsigned int given)
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{
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return !i.types[given].bitfield.tbyte
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|| t->operand_types[wanted].bitfield.tbyte;
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}
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/* Return 1 if there is no conflict in SIMD register between operand
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GIVEN and opeand WANTED for instruction template T. */
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GIVEN and operand WANTED for instruction template T. */
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static INLINE int
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match_simd_size (const insn_template *t, unsigned int wanted,
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@ -2541,13 +2550,15 @@ match_simd_size (const insn_template *t, unsigned int wanted,
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}
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/* Return 1 if there is no conflict in any size between operand GIVEN
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and opeand WANTED for instruction template T. */
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and operand WANTED for instruction template T. */
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static INLINE int
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match_mem_size (const insn_template *t, unsigned int wanted,
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unsigned int given)
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{
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return (match_operand_size (t, wanted, given)
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&& (!i.types[given].bitfield.tbyte
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|| t->operand_types[wanted].bitfield.tbyte)
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&& !((i.types[given].bitfield.unspecified
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&& !i.broadcast.type
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&& !i.broadcast.bytes
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@ -2610,14 +2621,23 @@ operand_size_match (const insn_template *t)
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&& (t->operand_types[j].bitfield.byte
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|| t->operand_types[j].bitfield.word
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|| t->operand_types[j].bitfield.dword
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|| t->operand_types[j].bitfield.qword
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|| t->operand_types[j].bitfield.tbyte)))
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|| t->operand_types[j].bitfield.qword)))
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&& !match_operand_size (t, j, j))
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{
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match = 0;
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break;
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}
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if (i.types[j].bitfield.class == RegFP
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&& (t->operand_types[j].bitfield.class == RegFP
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|| (t->operand_types[j].bitfield.instance == Accum
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&& t->operand_types[j].bitfield.tbyte))
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&& !match_fp_size (t, j, j))
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{
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match = 0;
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break;
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}
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if (i.types[j].bitfield.class == RegSIMD
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&& (t->operand_types[j].bitfield.class == RegSIMD
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|| (t->operand_types[j].bitfield.instance == Accum
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@ -2667,6 +2687,13 @@ operand_size_match (const insn_template *t)
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&& !match_operand_size (t, j, given))
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return match;
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if (i.types[given].bitfield.class == RegFP
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&& (t->operand_types[j].bitfield.class == RegFP
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|| (t->operand_types[j].bitfield.instance == Accum
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&& t->operand_types[j].bitfield.tbyte))
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&& !match_fp_size (t, j, given))
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return match;
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/* No need to check for Accum here: There are no such templates with D
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set. */
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if (i.types[given].bitfield.class == RegSIMD
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@ -3602,14 +3629,14 @@ md_begin (void)
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if (regtab->reg_type.bitfield.instance == Accum)
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reg_eax = regtab;
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}
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else if (regtab->reg_type.bitfield.tbyte)
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{
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/* There's no point inserting st(<N>) in the hash table, as
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parentheses aren't included in register_chars[] anyway. */
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if (regtab->reg_type.bitfield.instance != Accum)
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continue;
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reg_st0 = regtab;
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}
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break;
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case RegFP:
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/* There's no point inserting st(<N>) in the hash table, as
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parentheses aren't included in register_chars[] anyway. */
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if (regtab->reg_type.bitfield.instance != Accum)
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continue;
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reg_st0 = regtab;
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break;
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case SReg:
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@ -3744,6 +3771,7 @@ pi (const char *line, i386_insn *x)
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pt (x->types[j]);
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fprintf (stdout, "\n");
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if (x->types[j].bitfield.class == Reg
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|| x->types[j].bitfield.class == RegFP
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|| x->types[j].bitfield.class == RegMMX
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|| x->types[j].bitfield.class == RegSIMD
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|| x->types[j].bitfield.class == RegMask
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@ -3852,7 +3880,7 @@ const type_names[] =
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{ { .bitfield = { .class = RegCR } }, "control reg" },
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{ { .bitfield = { .class = RegTR } }, "test reg" },
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{ { .bitfield = { .class = RegDR } }, "debug reg" },
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{ { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" },
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{ { .bitfield = { .class = RegFP, .tbyte = 1 } }, "FReg" },
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{ { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" },
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{ { .bitfield = { .class = SReg } }, "SReg" },
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{ { .bitfield = { .class = RegMMX } }, "rMMX" },
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@ -4,7 +4,10 @@
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.*: Error: operand type mismatch for .bsf.
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.*: Error: operand type mismatch for .bswap.
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.*: Error: operand type mismatch for .bswap.
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.*: Error: operand type mismatch for .bswap.
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.*: Error: operand type mismatch for .fcomi.
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.*: Error: operand type mismatch for .fcomi.
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.*: Error: operand type mismatch for .in.
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.*: Error: operand type mismatch for .in.
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.*: Error: operand type mismatch for .movntdqa.
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.*: Error: operand type mismatch for .movntdq.
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@ -6,9 +6,12 @@
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blendvps %eax, %xmm1, %xmm2
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blendvps %st, %xmm1, %xmm2
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bsf %eax, (%eax)
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bswap %st
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bswap %mm0
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bswapl %xmm0
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fcomi %st(1), %eax
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fcomi %st(1), %xmm0
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inl $0, %st
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inl $0, %xmm0
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movntdqa %xmm0, (%eax)
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movntdq (%eax), %xmm0
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@ -540,6 +540,7 @@ static const struct {
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} operand_classes[] = {
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CLASS (Reg),
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CLASS (SReg),
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CLASS (RegFP),
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CLASS (RegCR),
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CLASS (RegDR),
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CLASS (RegTR),
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@ -863,8 +863,9 @@ typedef struct i386_opcode_modifier
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enum operand_class
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{
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ClassNone,
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Reg, /* GPRs and FP regs, distinguished by operand size */
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Reg, /* GPRs, distinguished by operand size */
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SReg, /* Segment register */
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RegFP, /* FP regs */
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RegCR, /* Control register */
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RegDR, /* Debug register */
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RegTR, /* Test register */
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@ -44,7 +44,7 @@
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#define InOutPortReg RegD|Word
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#define FloatAcc Acc|Tbyte
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#define FloatReg Class=Reg|Tbyte
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#define FloatReg Class=RegFP|Tbyte
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#define SReg Class=SReg
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@ -367,14 +367,14 @@ eip, Dword, RegRex64, RegIP, 8, Dw2Inval
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riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
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eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
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// fp regs. No need for an explicit st(0) here.
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st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
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st(1), Class=Reg|Tbyte, 0, 1, 12, 34
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st(2), Class=Reg|Tbyte, 0, 2, 13, 35
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st(3), Class=Reg|Tbyte, 0, 3, 14, 36
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st(4), Class=Reg|Tbyte, 0, 4, 15, 37
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st(5), Class=Reg|Tbyte, 0, 5, 16, 38
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st(6), Class=Reg|Tbyte, 0, 6, 17, 39
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st(7), Class=Reg|Tbyte, 0, 7, 18, 40
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st, Class=RegFP|Instance=Accum|Tbyte, 0, 0, 11, 33
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st(1), Class=RegFP|Tbyte, 0, 1, 12, 34
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st(2), Class=RegFP|Tbyte, 0, 2, 13, 35
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st(3), Class=RegFP|Tbyte, 0, 3, 14, 36
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st(4), Class=RegFP|Tbyte, 0, 4, 15, 37
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st(5), Class=RegFP|Tbyte, 0, 5, 16, 38
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st(6), Class=RegFP|Tbyte, 0, 6, 17, 39
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st(7), Class=RegFP|Tbyte, 0, 7, 18, 40
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// Pseudo-register names only used in .cfi_* directives
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eflags, 0, 0, 0, 9, 49
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rflags, 0, 0, 0, Dw2Inval, 49
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14824
opcodes/i386-tbl.h
14824
opcodes/i386-tbl.h
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