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Add AMD znver6 processor support
In --help option, adds znver6 to the list of CPUs under -march.
Please find the ISA descriptions for AVX512_BMM instructions below.
AVX512 Bit Manipulation Instructions
====================================
The AVX512BMM instructions include Bit Matrix Multiply and Bit Reversal
operations.
CPUID
-----
Support is indicated by the new CPUID 8000_0021, EAX bit 23, labeled AVX512_BMM.
Encoding
--------
VBMACOR16x16x16
EVEX.256.NP.MAP6.W0 80 /r VBMACOR16x16x16 ymm1, ymm2, ymm3/m256
EVEX.512.NP.MAP6.W0 80 /r VBMACOR16x16x16 zmm1, zmm2, zmm3/m512
VBMACXOR16x16x16
EVEX.256.NP.MAP6.W1 80 /r VBMACXOR16x16x16 ymm1, ymm2, ymm3/m256
EVEX.512.NP.MAP6.W1 80 /r VBMACXOR16x16x16 zmm1, zmm2, zmm3/m512
DESCRIPTION
-----------
256 BIT VERSIONS
----------------
16x16 non-transposed fused BMM-accumulate (BMAC) with OR/XOR reduction.
A ymm register holds a 16x16 bit matrix. The third source matrix for
accumulation is in ymm1.
512 BIT VERSIONS
----------------
2 parallel 16x16 non-transposed fused BMM-accumulate (BMAC) with OR/XOR
reduction.
Each 256-bit chunk of a zmm register holds a 16x16 bit matrix. The third source
matrices for accumulation are in zmm1.
VBITREVB
--------
EVEX.128.NP.MAP6.W0 81 /r VBITREVB xmm1{k1}{z}, xmm2/m128
EVEX.256.NP.MAP6.W0 81 /r VBITREVB ymm1{k1}{z}, ymm2/m256
EVEX.512.NP.MAP6.W0 81 /r VBITREVB zmm1{k1}{z}, zmm2/m512
DESCRIPTION
-----------
Bit reversal within a byte boundary. Only applied to input bytes where the
corresponding mask bit is set; otherwise, bytes are left untouched or zeroed out
if zero masking is indicated.
gas/ChangeLog:
* NEWS: Add znver6 ARCH.
* config/tc-i386.c: Add znver6 ARCH, avx512_bmm SUBARCH.
* doc/c-i386.texi: Likewise.
* testsuite/gas/i386/i386.exp: Add znver6 test cases.
* testsuite/gas/i386/x86-64.exp: Add znver6 test cases.
* testsuite/gas/i386/arch-16-znver6.d: New test.
* testsuite/gas/i386/arch-16.d: New test.
* testsuite/gas/i386/arch-16.s: New test.
* testsuite/gas/i386/avx512_bmm.d: New test.
* testsuite/gas/i386/avx512_bmm.s: New test.
* testsuite/gas/i386/avx512_bmm_vl-inval.l: New test.
* testsuite/gas/i386/avx512_bmm_vl-inval.s: New test.
* testsuite/gas/i386/avx512_bmm_vl.d: New test.
* testsuite/gas/i386/avx512_bmm_vl.s: New test.
* testsuite/gas/i386/x86-64-arch-6-znver6.d: New test.
* testsuite/gas/i386/x86-64-arch-6.d: New test.
* testsuite/gas/i386/x86-64-arch-6.s: New test.
* testsuite/gas/i386/x86-64-avx512_bmm-bad.d: New test.
* testsuite/gas/i386/x86-64-avx512_bmm-bad.s: New test.
* testsuite/gas/i386/x86-64-avx512_bmm.d: New test.
* testsuite/gas/i386/x86-64-avx512_bmm.s: New test.
* testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l: New test.
* testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s: New test.
* testsuite/gas/i386/x86-64-avx512_bmm_vl.d: New test.
* testsuite/gas/i386/x86-64-avx512_bmm_vl.s: New test.
opcodes/ChangeLog:
* i386-dis-evex-len.h: Likewise.
* i386-dis-evex-w.h: Likewise.
* i386-dis-evex.h: Likewise.
* i386-dis.c: Add EVEX_W_MAP6_80, EVEX_W_MAP6_81,
EVEX_LEN_MAP6_80_W_0, EVEX_LEN_MAP6_80_W_1.
* i386-gen.c: Likewise.
* i386-init.h: Re-generated.
* i386-mnem.h: Re-generated.
* i386-opc.h (enum i386_cpu): Add CpuAVX512_BMM.
(i386_cpu_flags): Add cpuvavx512_bmm.
* i386-opc.tbl: Add vbmacor16x16x16, vbmacxor16x16x16, vbitrevb.
* i386-tbl.h: Re-generated.
This commit is contained in:
Umesh Kalvakuntla
Jan Beulich
parent
4c1e38095b
commit
2abac9c95c
35 changed files with 4136 additions and 3688 deletions
2
gas/NEWS
2
gas/NEWS
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@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for AMD Zen6 processor.
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* Emit an SFrame FRE with zero offsets to convey an undefined return address
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in the SFrame stack trace format.
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@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
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ARCH (znver3, ZNVER, ZNVER3, false),
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ARCH (znver4, ZNVER, ZNVER4, false),
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ARCH (znver5, ZNVER, ZNVER5, false),
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ARCH (znver6, ZNVER, ZNVER6, false),
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ARCH (btver1, BT, BTVER1, false),
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ARCH (btver2, BT, BTVER2, false),
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@ -1214,6 +1215,7 @@ static const arch_entry cpu_arch[] =
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VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset),
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VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT,
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ANY_AVX512_VP2INTERSECT, reset),
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VECARCH (avx512_bmm, AVX512_BMM, ANY_AVX512_BMM, reset),
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SUBARCH (tdx, TDX, TDX, false),
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SUBARCH (enqcmd, ENQCMD, ENQCMD, false),
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SUBARCH (serialize, SERIALIZE, SERIALIZE, false),
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@ -126,6 +126,7 @@ processor names are recognized:
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@code{znver3},
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@code{znver4},
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@code{znver5},
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@code{znver6},
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@code{btver1},
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@code{btver2},
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@code{generic32} and
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@ -198,6 +199,7 @@ accept various extension mnemonics. For example,
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@code{avx512_bf16},
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@code{avx_vnni},
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@code{avx512_fp16},
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@code{avx512_bmm},
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@code{prefetchi},
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@code{avx_ifma},
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@code{avx_vnni_int8},
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@ -1695,9 +1697,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
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@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
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@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
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@item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2}
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@item @samp{generic32}
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@item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
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@item @samp{znver4} @tab @samp{znver5} @tab @samp{znver6} @tab @samp{btver1}
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@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
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@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
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@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
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@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
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@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
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@ -1714,9 +1716,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
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@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
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@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
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@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{.avx10.1}
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@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
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@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
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@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{avx512_bmm}
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@item @samp{.avx10.1} @tab @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite}
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@item @samp{.ibt} @tab @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
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@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
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@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
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@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
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16
gas/testsuite/gas/i386/arch-16-znver6.d
Normal file
16
gas/testsuite/gas/i386/arch-16-znver6.d
Normal file
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@ -0,0 +1,16 @@
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#source: arch-16.s
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#as: -march=znver6
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#objdump: -dw
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#name: i386 arch 16 (znver6)
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.*: +file format .*
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Disassembly of section \.text:
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[0-9a-f]+ <\.text>:
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[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
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[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
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[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2
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[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
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[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
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#pass
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14
gas/testsuite/gas/i386/arch-16.d
Normal file
14
gas/testsuite/gas/i386/arch-16.d
Normal file
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@ -0,0 +1,14 @@
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#objdump: -dw
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#name: i386 arch 6
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.*: +file format .*
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Disassembly of section \.text:
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[0-9a-f]+ <\.text>:
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[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
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[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
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[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2
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[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
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[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
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#pass
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8
gas/testsuite/gas/i386/arch-16.s
Normal file
8
gas/testsuite/gas/i386/arch-16.s
Normal file
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@ -0,0 +1,8 @@
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# Test -march=
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.text
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vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM
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vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT
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vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA
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vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8
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vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16
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23
gas/testsuite/gas/i386/avx512_bmm.d
Normal file
23
gas/testsuite/gas/i386/avx512_bmm.d
Normal file
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@ -0,0 +1,23 @@
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#objdump: -dw
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#name: i386 AVX512_BMM insns
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.*: +file format .*
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Disassembly of section \.text:
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[0-9a-f]+ <bmm>:
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[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
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[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
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[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrevb %zmm1,%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrevb %zmm1,%zmm2\{%k1\}\{z\}
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[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
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[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrevb 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
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[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 52 80[\s]*vbitrevb -0x2000\(%edx\),%zmm2\{%k1\}\{z\}
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#pass
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21
gas/testsuite/gas/i386/avx512_bmm.s
Normal file
21
gas/testsuite/gas/i386/avx512_bmm.s
Normal file
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@ -0,0 +1,21 @@
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# Check 32bit AVX512_BMM instructions
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.text
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bmm:
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.arch .noavx512vl
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vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
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vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
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vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
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vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
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vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
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vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
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vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
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vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
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vbitrevb %zmm1, %zmm2 # AVX512_BMM
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vbitrevb %zmm1, %zmm2{%k1}{z} # AVX512_BMM
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vbitrevb -123456(%esp,%esi,8), %zmm2 # AVX512_BMM
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vbitrevb -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM
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vbitrevb 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM
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vbitrevb -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8
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3
gas/testsuite/gas/i386/avx512_bmm_vl-inval.l
Normal file
3
gas/testsuite/gas/i386/avx512_bmm_vl-inval.l
Normal file
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@ -0,0 +1,3 @@
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.* Assembler messages:
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.*:5: Error: operand .* `vbmacor16x16x16'
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.*:6: Error: operand .* `vbmacxor16x16x16'
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6
gas/testsuite/gas/i386/avx512_bmm_vl-inval.s
Normal file
6
gas/testsuite/gas/i386/avx512_bmm_vl-inval.s
Normal file
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@ -0,0 +1,6 @@
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# Check illegal 32bit AVX512_BMM,AVX512VL instructions
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.text
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_start:
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vbmacor16x16x16 %xmm1, %xmm2, %xmm3
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vbmacxor16x16x16 %xmm1, %xmm2, %xmm3
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29
gas/testsuite/gas/i386/avx512_bmm_vl.d
Normal file
29
gas/testsuite/gas/i386/avx512_bmm_vl.d
Normal file
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@ -0,0 +1,29 @@
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#objdump: -dw
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#name: i386 AVX512_BMM,AVX512VL insns
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.*: +file format .*
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Disassembly of section \.text:
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[0-9a-f]+ <bmm>:
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[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
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[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
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[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
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[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
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[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
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[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
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[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
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[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
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[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrevb %xmm1,%xmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrevb %xmm1,%xmm2\{%k1\}\{z\}
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[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2
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[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrevb 0x800\(%edx\),%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 52 80[\s]*vbitrevb -0x800\(%edx\),%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrevb %ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrevb %ymm1,%ymm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrevb 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 50 80[\s]*vbitrevb -0x1000\(%eax\),%ymm2\{%k1\}\{z\}
|
||||
#pass
|
||||
26
gas/testsuite/gas/i386/avx512_bmm_vl.s
Normal file
26
gas/testsuite/gas/i386/avx512_bmm_vl.s
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Check 32bit AVX512_BMM,AVX512VL instructions
|
||||
|
||||
.text
|
||||
bmm:
|
||||
vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
|
||||
vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
|
||||
|
||||
vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
|
||||
vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
|
||||
|
||||
vbitrevb %xmm1, %xmm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb %xmm1, %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %xmm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
|
||||
vbitrevb %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb %ymm1, %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
|
||||
|
|
@ -215,6 +215,7 @@ if [gas_32_check] then {
|
|||
run_dump_test "arch-14-znver3"
|
||||
run_dump_test "arch-14-znver4"
|
||||
run_dump_test "arch-15-znver5"
|
||||
run_dump_test "arch-16-znver6"
|
||||
run_dump_test "arch-10-btver1"
|
||||
run_dump_test "arch-10-btver2"
|
||||
run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
|
||||
|
|
@ -229,6 +230,7 @@ if [gas_32_check] then {
|
|||
run_dump_test "arch-14"
|
||||
run_dump_test "arch-14-1"
|
||||
run_dump_test "arch-15"
|
||||
run_dump_test "arch-16"
|
||||
run_list_test "arch-dflt" "-march=generic32 -al"
|
||||
run_list_test "arch-stk" "-march=generic32 -al"
|
||||
run_dump_test "8087"
|
||||
|
|
@ -477,6 +479,9 @@ if [gas_32_check] then {
|
|||
run_dump_test "avx512vnni-intel"
|
||||
run_dump_test "avx512vnni_vl"
|
||||
run_dump_test "avx512vnni_vl-intel"
|
||||
run_dump_test "avx512_bmm"
|
||||
run_dump_test "avx512_bmm_vl"
|
||||
run_list_test "avx512_bmm_vl-inval"
|
||||
run_dump_test "avx512bitalg"
|
||||
run_dump_test "avx512bitalg-intel"
|
||||
run_dump_test "avx512bitalg_vl"
|
||||
|
|
|
|||
16
gas/testsuite/gas/i386/x86-64-arch-6-znver6.d
Normal file
16
gas/testsuite/gas/i386/x86-64-arch-6-znver6.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#source: x86-64-arch-6.s
|
||||
#as: -march=znver6
|
||||
#objdump: -dw
|
||||
#name: x86-64 arch 6 (znver6)
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
[0-9a-f]+ <\.text>:
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
|
||||
[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
|
||||
[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2
|
||||
[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
|
||||
[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
|
||||
#pass
|
||||
14
gas/testsuite/gas/i386/x86-64-arch-6.d
Normal file
14
gas/testsuite/gas/i386/x86-64-arch-6.d
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 arch 6
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
[0-9a-f]+ <\.text>:
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
|
||||
[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
|
||||
[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2
|
||||
[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
|
||||
[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
|
||||
#pass
|
||||
8
gas/testsuite/gas/i386/x86-64-arch-6.s
Normal file
8
gas/testsuite/gas/i386/x86-64-arch-6.s
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Test -march=
|
||||
.text
|
||||
|
||||
vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM
|
||||
vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT
|
||||
vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA
|
||||
vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8
|
||||
vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16
|
||||
14
gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.d
Normal file
14
gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.d
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#objdump: -dw
|
||||
#name: x86_64 AVX512_BMM BAD insns
|
||||
#source: x86-64-avx512_bmm-bad.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
[0-9a-f]+ <\.text>:
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 6c 08 80[\s]*\(bad\)
|
||||
[\s]*[a-f0-9]+:[\s]*c7[\s]*\(bad\)
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 ec 08 80[\s]*\(bad\)
|
||||
[\s]*[a-f0-9]+:[\s]*c7[\s]*.*
|
||||
#pass
|
||||
8
gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.s
Normal file
8
gas/testsuite/gas/i386/x86-64-avx512_bmm-bad.s
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# Check Illegal 64-bit AVX512_BMM instructions
|
||||
|
||||
.text
|
||||
#vbmacor16x16x16 %xmm7, %xmm2, %xmm0 set EVEX.L'L = 0 (illegal value).
|
||||
.insn EVEX.128.NP.M6.W0 0x80, %xmm7, %xmm2, %xmm0
|
||||
|
||||
#vbmacxor16x16x16 %xmm7, %xmm2, %xmm0 set EVEX.L'L = 0 (illegal value).
|
||||
.insn EVEX.128.NP.M6.W1 0x80, %xmm7, %xmm2, %xmm0
|
||||
23
gas/testsuite/gas/i386/x86-64-avx512_bmm.d
Normal file
23
gas/testsuite/gas/i386/x86-64-avx512_bmm.d
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 AVX512_BMM insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
[0-9a-f]+ <bmm>:
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrevb %zmm1,%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrevb %zmm1,%zmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrevb 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 52 80[\s]*vbitrevb -0x2000\(%edx\),%zmm2\{%k1\}\{z\}
|
||||
#pass
|
||||
21
gas/testsuite/gas/i386/x86-64-avx512_bmm.s
Normal file
21
gas/testsuite/gas/i386/x86-64-avx512_bmm.s
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# Check 64bit AVX512_BMM instructions
|
||||
|
||||
.text
|
||||
bmm:
|
||||
.arch .noavx512vl
|
||||
vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
|
||||
vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
|
||||
vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
|
||||
vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
|
||||
|
||||
vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
|
||||
vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
|
||||
vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
|
||||
vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
|
||||
|
||||
vbitrevb %zmm1, %zmm2 # AVX512_BMM
|
||||
vbitrevb %zmm1, %zmm2{%k1}{z} # AVX512_BMM
|
||||
vbitrevb -123456(%esp,%esi,8), %zmm2 # AVX512_BMM
|
||||
vbitrevb -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM
|
||||
vbitrevb 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM
|
||||
vbitrevb -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8
|
||||
3
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l
Normal file
3
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.l
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
.* Assembler messages:
|
||||
.*:5: Error: operand .* `vbmacor16x16x16'
|
||||
.*:6: Error: operand .* `vbmacxor16x16x16'
|
||||
6
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s
Normal file
6
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl-inval.s
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
# Check illegal 64bit AVX512_BMM,AVX512VL instructions
|
||||
|
||||
.text
|
||||
_start:
|
||||
vbmacor16x16x16 %xmm1, %xmm2, %xmm3
|
||||
vbmacxor16x16x16 %xmm1, %xmm2, %xmm3
|
||||
29
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.d
Normal file
29
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.d
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
#objdump: -dw
|
||||
#name: x86-64 AVX512_BMM,AVX512VL insns
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
[0-9a-f]+ <bmm>:
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrevb %xmm1,%xmm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrevb %xmm1,%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrevb 0x800\(%edx\),%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 52 80[\s]*vbitrevb -0x800\(%edx\),%xmm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrevb %ymm1,%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrevb %ymm1,%ymm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrevb -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrevb 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
|
||||
[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 50 80[\s]*vbitrevb -0x1000\(%eax\),%ymm2\{%k1\}\{z\}
|
||||
#pass
|
||||
26
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.s
Normal file
26
gas/testsuite/gas/i386/x86-64-avx512_bmm_vl.s
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Check 64bit AVX512_BMM,AVX512VL instructions
|
||||
|
||||
.text
|
||||
bmm:
|
||||
vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
|
||||
vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
|
||||
|
||||
vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM,AVX512VL
|
||||
vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM,AVX512VL Disp8
|
||||
|
||||
vbitrevb %xmm1, %xmm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb %xmm1, %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %xmm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
|
||||
vbitrevb %ymm1, %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb %ymm1, %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %ymm2 # AVX512_BMM,AVX512VL
|
||||
vbitrevb -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL
|
||||
vbitrevb -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM,AVX512VL Disp8
|
||||
|
|
@ -182,6 +182,7 @@ run_dump_test "x86-64-arch-4"
|
|||
run_dump_test "x86-64-arch-4-1"
|
||||
run_dump_test "rmpquery"
|
||||
run_dump_test "x86-64-arch-5"
|
||||
run_dump_test "x86-64-arch-6"
|
||||
run_dump_test "x86-64-arch-2-lzcnt"
|
||||
run_dump_test "x86-64-arch-2-prefetchw"
|
||||
run_dump_test "x86-64-arch-2-bdver1"
|
||||
|
|
@ -193,6 +194,7 @@ run_dump_test "x86-64-arch-3-znver2"
|
|||
run_dump_test "x86-64-arch-4-znver3"
|
||||
run_dump_test "x86-64-arch-4-znver4"
|
||||
run_dump_test "x86-64-arch-5-znver5"
|
||||
run_dump_test "x86-64-arch-6-znver6"
|
||||
run_dump_test "x86-64-arch-2-btver1"
|
||||
run_dump_test "x86-64-arch-2-btver2"
|
||||
run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
|
||||
|
|
@ -442,6 +444,10 @@ run_dump_test "x86-64-avx512vnni"
|
|||
run_dump_test "x86-64-avx512vnni-intel"
|
||||
run_dump_test "x86-64-avx512vnni_vl"
|
||||
run_dump_test "x86-64-avx512vnni_vl-intel"
|
||||
run_dump_test "x86-64-avx512_bmm"
|
||||
run_dump_test "x86-64-avx512_bmm_vl"
|
||||
run_list_test "x86-64-avx512_bmm_vl-inval"
|
||||
run_dump_test "x86-64-avx512_bmm-bad"
|
||||
run_dump_test "x86-64-avx512bitalg"
|
||||
run_dump_test "x86-64-avx512bitalg-intel"
|
||||
run_dump_test "x86-64-avx512bitalg_vl"
|
||||
|
|
|
|||
|
|
@ -193,4 +193,18 @@ static const struct dis386 evex_len_table[][3] = {
|
|||
{
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_7E_L_0) },
|
||||
},
|
||||
|
||||
/* EVEX_LEN_MAP6_80_W_0 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vbmacor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
|
||||
{ "vbmacor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
|
||||
},
|
||||
|
||||
/* EVEX_LEN_MAP6_80_W_1 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
|
||||
{ "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
|
||||
},
|
||||
};
|
||||
|
|
|
|||
|
|
@ -524,3 +524,13 @@
|
|||
{
|
||||
{ "vmovw", { EXwS, XMScalar }, 0 },
|
||||
},
|
||||
/* EVEX_W_MAP6_80 */
|
||||
{
|
||||
{ EVEX_LEN_TABLE (EVEX_LEN_MAP6_80_W_0) },
|
||||
{ EVEX_LEN_TABLE (EVEX_LEN_MAP6_80_W_1) },
|
||||
},
|
||||
/* EVEX_W_MAP6_81 */
|
||||
{
|
||||
{ "vbitrevb", { XM, EXx }, NO_PREFIX },
|
||||
{ Bad_Opcode }
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1601,8 +1601,8 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 80 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (EVEX_W_MAP6_80) },
|
||||
{ VEX_W_TABLE (EVEX_W_MAP6_81) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
|
|
|||
|
|
@ -1606,6 +1606,8 @@ enum
|
|||
|
||||
EVEX_LEN_MAP5_6E,
|
||||
EVEX_LEN_MAP5_7E,
|
||||
EVEX_LEN_MAP6_80_W_0,
|
||||
EVEX_LEN_MAP6_80_W_1,
|
||||
};
|
||||
|
||||
enum
|
||||
|
|
@ -1859,6 +1861,8 @@ enum
|
|||
EVEX_W_MAP5_6E_P_1,
|
||||
EVEX_W_MAP5_7A_P_3,
|
||||
EVEX_W_MAP5_7E_P_1,
|
||||
EVEX_W_MAP6_80,
|
||||
EVEX_W_MAP6_81,
|
||||
};
|
||||
|
||||
typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
|
||||
|
|
|
|||
|
|
@ -98,6 +98,8 @@ static const dependency isa_dependencies[] =
|
|||
"ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
|
||||
{ "ZNVER5",
|
||||
"ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" },
|
||||
{ "ZNVER6",
|
||||
"ZNVER5|AVX512_BMM|AVX_NE_CONVERT|AVX_IFMA|AVX_VNNI_INT8|AVX512_FP16" },
|
||||
{ "BTVER1",
|
||||
"GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
|
||||
{ "BTVER2",
|
||||
|
|
@ -208,6 +210,8 @@ static const dependency isa_dependencies[] =
|
|||
"AVX512BW" },
|
||||
{ "AVX512_VP2INTERSECT",
|
||||
"AVX512F" },
|
||||
{ "AVX512_BMM",
|
||||
"AVX512BW" },
|
||||
{ "AVX512_BF16",
|
||||
"AVX512BW" },
|
||||
{ "AVX512_FP16",
|
||||
|
|
@ -427,6 +431,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (AVX512_BITALG),
|
||||
BITFIELD (AVX512_BF16),
|
||||
BITFIELD (AVX512_VP2INTERSECT),
|
||||
BITFIELD (AVX512_BMM),
|
||||
BITFIELD (TDX),
|
||||
BITFIELD (AVX_VNNI),
|
||||
BITFIELD (AVX512_FP16),
|
||||
|
|
|
|||
1179
opcodes/i386-init.h
1179
opcodes/i386-init.h
File diff suppressed because it is too large
Load diff
4187
opcodes/i386-mnem.h
4187
opcodes/i386-mnem.h
File diff suppressed because it is too large
Load diff
|
|
@ -205,6 +205,8 @@ enum i386_cpu
|
|||
CpuAVX512_BF16,
|
||||
/* Intel AVX-512 VP2INTERSECT Instructions support required. */
|
||||
CpuAVX512_VP2INTERSECT,
|
||||
/* AMD AVX-512 BMM Instructions support required. */
|
||||
CpuAVX512_BMM,
|
||||
/* TDX Instructions support required. */
|
||||
CpuTDX,
|
||||
/* Intel AVX VNNI Instructions support required. */
|
||||
|
|
@ -503,6 +505,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuavx512_bitalg:1;
|
||||
unsigned int cpuavx512_bf16:1;
|
||||
unsigned int cpuavx512_vp2intersect:1;
|
||||
unsigned int cpuavx512_bmm:1;
|
||||
unsigned int cputdx:1;
|
||||
unsigned int cpuavx_vnni:1;
|
||||
unsigned int cpuavx512_fp16:1;
|
||||
|
|
|
|||
|
|
@ -3151,6 +3151,14 @@ vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSu
|
|||
|
||||
// AVX-NE-CONVERT instructions end.
|
||||
|
||||
// AVX512-BMM instructions.
|
||||
|
||||
vbmacor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW0|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
|
||||
vbmacxor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW1|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
|
||||
vbitrevb, 0x81, AVX512_BMM, Modrm|EVexDYN|VexW0|Masking|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
|
||||
|
||||
// AVX512-BMM instructions end.
|
||||
|
||||
// ENQCMD instructions.
|
||||
|
||||
enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
|
|
|||
2067
opcodes/i386-tbl.h
2067
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue