diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index d44bc6dc6a4..305ac2981ce 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -40,7 +40,6 @@ static inline void insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...) { uint32_t num; - enum aarch64_field_kind kind; va_list va; va_start (va, mask); @@ -48,9 +47,9 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...) assert (num <= 5); while (num--) { - kind = va_arg (va, enum aarch64_field_kind); - insert_field (kind, code, value, mask); - value >>= aarch64_fields[kind].width; + aarch64_field field = va_arg (va, aarch64_field); + insert_field (field, code, value, mask); + value >>= field.width; } va_end (va); } @@ -63,14 +62,13 @@ insert_all_fields_after (const aarch64_operand *self, unsigned int start, aarch64_insn *code, aarch64_insn value) { unsigned int i; - enum aarch64_field_kind kind; for (i = ARRAY_SIZE (self->fields); i-- > start; ) - if (self->fields[i] != FLD_NIL) + if (self->fields[i].width != 0) { - kind = self->fields[i]; - insert_field (kind, code, value, 0); - value >>= aarch64_fields[kind].width; + aarch64_field field = self->fields[i]; + insert_field (field, code, value, 0); + value >>= field.width; } } @@ -349,7 +347,7 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, } insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q); gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); - insert_field_2 (&field, code, opcodeh2, 0); + insert_field (field, code, opcodeh2, 0); return true; } @@ -500,7 +498,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, amount >>= 4; gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ } - insert_field_2 (&field, code, amount, 0); + insert_field (field, code, amount, 0); return true; } @@ -753,7 +751,7 @@ aarch64_ins_addr_simm (const aarch64_operand *self, insert_field (FLD_Rn, code, info->addr.base_regno, 0); /* simm (imm9 or imm7) */ imm = info->addr.offset.imm; - if (self->fields[0] == FLD_imm7 + if (self->fields[0].width == 7 || info->qualifier == AARCH64_OPND_QLF_imm_tag) /* scaled immediate in ld/st pair instructions.. */ imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier)); @@ -1868,7 +1866,7 @@ encode_asimd_fcvt (aarch64_inst *inst) || qualifier == AARCH64_OPND_QLF_V_2D); value = (qualifier == AARCH64_OPND_QLF_V_4S) ? 0 : 1; gen_sub_field (FLD_size, 0, 1, &field); - insert_field_2 (&field, &inst->value, value, 0); + insert_field (field, &inst->value, value, 0); } /* Encode size[0], i.e. bit 22, for @@ -1881,7 +1879,7 @@ encode_asisd_fcvtxn (aarch64_inst *inst) aarch64_field field = AARCH64_FIELD_NIL; assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_S_S); gen_sub_field (FLD_size, 0, 1, &field); - insert_field_2 (&field, &inst->value, val, 0); + insert_field (field, &inst->value, val, 0); } /* Encode the 'opc' field for e.g. FCVT
, . */ @@ -1899,7 +1897,7 @@ encode_fcvt (aarch64_inst *inst) case AARCH64_OPND_QLF_S_H: val = 3; break; default: abort (); } - insert_field_2 (&field, &inst->value, val, 0); + insert_field (field, &inst->value, val, 0); return; } @@ -1998,7 +1996,7 @@ static void encode_sizeq (aarch64_inst *inst) { aarch64_insn sizeq; - enum aarch64_field_kind kind; + aarch64_field field; int idx; /* Get the index of the operand whose information we are going to use @@ -2015,10 +2013,10 @@ encode_sizeq (aarch64_inst *inst) || inst->opcode->iclass == asisdlsep || inst->opcode->iclass == asisdlso || inst->opcode->iclass == asisdlsop) - kind = FLD_vldst_size; + field = FLD_vldst_size; else - kind = FLD_size; - insert_field (kind, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask); + field = FLD_size; + insert_field (field, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask); } /* Opcodes that have fields shared by multiple operands are usually flagged @@ -2131,7 +2129,7 @@ do_special_encoding (struct aarch64_inst *inst) num = (int) value >> 1; assert (num >= 0 && num <= 3); gen_sub_field (FLD_imm5, 0, num + 1, &field); - insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask); + insert_field (field, &inst->value, 1 << num, inst->opcode->mask); } if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs) @@ -2173,7 +2171,7 @@ do_special_encoding (struct aarch64_inst *inst) == AARCH64_OPND_CLASS_INT_REG); gen_sub_field (FLD_opc, 0, 1, &field); qualifier = inst->operands[0].qualifier; - insert_field_2 (&field, &inst->value, + insert_field (field, &inst->value, 1 - aarch64_get_qualifier_standard_value (qualifier), 0); } /* Miscellaneous encoding as the last step. */ diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 3505a7d911d..d73975fe783 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -162,7 +162,6 @@ aarch64_insn extract_fields (aarch64_insn code, aarch64_insn mask, ...) { uint32_t num; - enum aarch64_field_kind kind; va_list va; va_start (va, mask); @@ -171,9 +170,9 @@ extract_fields (aarch64_insn code, aarch64_insn mask, ...) aarch64_insn value = 0x0; while (num--) { - kind = va_arg (va, enum aarch64_field_kind); - value <<= aarch64_fields[kind].width; - value |= extract_field (kind, code, mask); + aarch64_field field = va_arg (va, aarch64_field); + value <<= field.width; + value |= extract_field (field, code, mask); } va_end (va); return value; @@ -188,15 +187,14 @@ extract_all_fields_after (const aarch64_operand *self, unsigned int start, { aarch64_insn value; unsigned int i; - enum aarch64_field_kind kind; value = 0; for (i = start; - i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) + i < ARRAY_SIZE (self->fields) && self->fields[i].width != 0; ++i) { - kind = self->fields[i]; - value <<= aarch64_fields[kind].width; - value |= extract_field (kind, code, 0); + aarch64_field field = self->fields[i]; + value <<= field.width; + value |= extract_field (field, code, 0); } return value; } @@ -607,7 +605,7 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, /* Decode the index, opcode<2:1> and size. */ gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); - opcodeh2 = extract_field_2 (&field, code, 0); + opcodeh2 = extract_field (field, code, 0); QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size); switch (opcodeh2) { @@ -855,13 +853,13 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, default: return false; } /* 00: 0; 01: 8; 10:16; 11:24. */ - info->shifter.amount = extract_field_2 (&field, code, 0) << 3; + info->shifter.amount = extract_field (field, code, 0) << 3; break; case AARCH64_OPND_QLF_MSL: /* shift ones */ info->shifter.kind = AARCH64_MOD_MSL; gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ - info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; + info->shifter.amount = extract_field (field, code, 0) ? 16 : 8; break; default: return false; @@ -1250,8 +1248,8 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, /* simm (imm9 or imm7) */ imm = extract_field (self->fields[0], code, 0); info->addr.offset.imm - = sign_extend (imm, aarch64_fields[self->fields[0]].width - 1); - if (self->fields[0] == FLD_imm7 + = sign_extend (imm, self->fields[0].width - 1); + if (self->fields[0].width == 7 || info->qualifier == AARCH64_OPND_QLF_imm_tag) /* scaled immediate in ld/st pair instructions. */ info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); @@ -2563,7 +2561,7 @@ decode_sizeq (aarch64_inst *inst) int idx; aarch64_insn code; aarch64_insn value, mask; - enum aarch64_field_kind fld_sz; + aarch64_field fld_sz; enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; if (inst->opcode->iclass == asisdlse @@ -2632,7 +2630,7 @@ decode_asimd_fcvt (aarch64_inst *inst) enum aarch64_opnd_qualifier qualifier; gen_sub_field (FLD_size, 0, 1, &field); - value = extract_field_2 (&field, inst->value, 0); + value = extract_field (field, inst->value, 0); qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S : AARCH64_OPND_QLF_V_2D; switch (inst->opcode->op) @@ -2662,7 +2660,7 @@ decode_asisd_fcvtxn (aarch64_inst *inst) { aarch64_field field = AARCH64_FIELD_NIL; gen_sub_field (FLD_size, 0, 1, &field); - if (!extract_field_2 (&field, inst->value, 0)) + if (!extract_field (field, inst->value, 0)) return 0; inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S; return 1; @@ -2677,7 +2675,7 @@ decode_fcvt (aarch64_inst *inst) const aarch64_field field = AARCH64_FIELD (15, 2); /* opc dstsize */ - value = extract_field_2 (&field, inst->value, 0); + value = extract_field (field, inst->value, 0); switch (value) { case 0: qualifier = AARCH64_OPND_QLF_S_S; break; @@ -2957,7 +2955,7 @@ do_special_decoding (aarch64_inst *inst) assert (aarch64_get_operand_class (inst->opcode->operands[0]) == AARCH64_OPND_CLASS_INT_REG); gen_sub_field (FLD_opc, 0, 1, &field); - value = extract_field_2 (&field, inst->value, 0); + value = extract_field (field, inst->value, 0); inst->operands[0].qualifier = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; } diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c index d989c557523..c10b84d323e 100644 --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -998,14 +998,14 @@ typedef struct operand operand; static operand operands[] = { - {"NIL", "0", "0", "", "0", "{0}", "", 0, 0, 0}, + {"NIL", "0", "0", "", "0", "{}", "", 0, 0, 0}, #define F(...) #__VA_ARGS__ #define X(a,b,c,d,e,f,g) \ {#a, #b, #c, d, #e, "{"f"}", g, 0, 0, 0}, #define Y(a,b,d,e,f,g) \ {#a, "ins_"#b, "ext_"#b, d, #e, "{"f"}", g, 0, 0, 0}, AARCH64_OPERANDS - {"NIL", "0", "0", "", "0", "{0}", "DUMMY", 0, 0, 0}, + {"NIL", "0", "0", "", "0", "{}", "DUMMY", 0, 0, 0}, }; #undef F diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 8d99101fb1c..5b869d1ddbb 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -25,7 +25,7 @@ const struct aarch64_operand aarch64_operands[] = { - {AARCH64_OPND_CLASS_NIL, "", 0, {0}, ""}, + {AARCH64_OPND_CLASS_NIL, "", 0, {}, ""}, {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"}, @@ -377,7 +377,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SYSTEM, "GIC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, {AARCH64_OPND_CLASS_SYSTEM, "GICR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, {AARCH64_OPND_CLASS_SYSTEM, "GSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller Synchronization Barrier"}, - {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {}, "DUMMY"}, }; /* Indexed by an enum aarch64_op enumerator, the value is the diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index e651efb341c..41f38053275 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -217,231 +217,6 @@ aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode) significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])]; } -/* Instruction bit-fields. -+ Keep synced with 'enum aarch64_field_kind'. */ -const aarch64_field aarch64_fields[] = -{ - AARCH64_FIELD_NIL, /* NIL. */ - AARCH64_FIELD_CONST (0, 1), /* CONST_0. */ - AARCH64_FIELD_CONST (0, 2), /* CONST_00. */ - AARCH64_FIELD_CONST (1, 2), /* CONST_01. */ - AARCH64_FIELD_CONST (1, 1), /* CONST_1. */ - AARCH64_FIELD ( 8, 4), /* CRm: in the system instructions. */ - AARCH64_FIELD (10, 2), /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */ - AARCH64_FIELD (12, 4), /* CRn: in the system instructions. */ - AARCH64_FIELD (10, 8), /* CSSC_imm8. */ - AARCH64_FIELD (11, 1), /* H: in advsimd scalar x indexed element instructions. */ - AARCH64_FIELD (21, 1), /* L: in advsimd scalar x indexed element instructions. */ - AARCH64_FIELD ( 0, 5), /* LSE128_Rt: Shared input+output operand register. */ - AARCH64_FIELD (16, 5), /* LSE128_Rt2: Shared input+output operand register 2. */ - AARCH64_FIELD (20, 1), /* M: in advsimd scalar x indexed element instructions. */ - AARCH64_FIELD (22, 1), /* N: in logical (immediate) instructions. */ - AARCH64_FIELD (30, 1), /* Q: in most AdvSIMD instructions. */ - AARCH64_FIELD (10, 5), /* Ra: in fp instructions. */ - AARCH64_FIELD ( 0, 5), /* Rd: in many integer instructions. */ - AARCH64_FIELD (16, 5), /* Rm: in ld/st reg offset and some integer inst. */ - AARCH64_FIELD ( 5, 5), /* Rn: in many integer instructions. */ - AARCH64_FIELD (16, 5), /* Rs: in load/store exclusive instructions. */ - AARCH64_FIELD ( 0, 5), /* Rt: in load/store instructions. */ - AARCH64_FIELD (10, 5), /* Rt2: in load/store pair instructions. */ - AARCH64_FIELD (12, 1), /* S: in load/store reg offset instructions. */ - AARCH64_FIELD (12, 2), /* SM3_imm2: Indexed element SM3 2 bits index immediate. */ - AARCH64_FIELD ( 1, 3), /* SME_Pdx2: predicate register, multiple of 2, [3:1]. */ - AARCH64_FIELD (13, 3), /* SME_Pm: second source scalable predicate register P0-P7. */ - AARCH64_FIELD ( 0, 3), /* SME_PNd3: PN0-PN7, bits [2:0]. */ - AARCH64_FIELD ( 5, 3), /* SME_PNn3: PN0-PN7, bits [7:5]. */ - AARCH64_FIELD (16, 1), /* SME_Q: Q class bit, bit 16. */ - AARCH64_FIELD (16, 2), /* SME_Rm: index base register W12-W15 [17:16]. */ - AARCH64_FIELD (13, 2), /* SME_Rv: vector select register W12-W15, bits [14:13]. */ - AARCH64_FIELD (15, 1), /* SME_V: (horizontal / vertical tiles), bit 15. */ - AARCH64_FIELD (10, 1), /* SME_VL_10: VLx2 or VLx4, bit [10]. */ - AARCH64_FIELD (13, 1), /* SME_VL_13: VLx2 or VLx4, bit [13]. */ - AARCH64_FIELD ( 0, 1), /* SME_ZAda_1b: tile ZA0-ZA1. */ - AARCH64_FIELD ( 0, 2), /* SME_ZAda_2b: tile ZA0-ZA3. */ - AARCH64_FIELD ( 0, 3), /* SME_ZAda_3b: tile ZA0-ZA7. */ - AARCH64_FIELD ( 1, 4), /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ - AARCH64_FIELD ( 2, 3), /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */ - AARCH64_FIELD (16, 4), /* SME_Zm: Z0-Z15, bits [19:16]. */ - AARCH64_FIELD (17, 3), /* SME_Zm17_3: Z0-Z15/Z16-Z31, multiple of 2, bits [19:17]. */ - AARCH64_FIELD (17, 4), /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */ - AARCH64_FIELD (18, 3), /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */ - AARCH64_FIELD ( 6, 4), /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */ - AARCH64_FIELD ( 7, 3), /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */ - AARCH64_FIELD ( 6, 3), /* SME_Zn6_3: Z0-Z15/Z16-Z31, multiple of 2, bits [8:6]. */ - AARCH64_FIELD ( 4, 1), /* SME_ZtT: upper bit of Zt, bit [4]. */ - AARCH64_FIELD ( 0, 3), /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */ - AARCH64_FIELD ( 0, 2), /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */ - AARCH64_FIELD (23, 1), /* SME_i1: immediate field, bit 23. */ - AARCH64_FIELD (12, 2), /* SME_size_12: bits [13:12]. */ - AARCH64_FIELD (22, 2), /* SME_size_22: size<1>, size<0> class field, [23:22]. */ - AARCH64_FIELD (23, 1), /* SME_sz_23: bit [23]. */ - AARCH64_FIELD (22, 1), /* SME_tszh: immediate and qualifier field, bit 22. */ - AARCH64_FIELD (18, 3), /* SME_tszl: immediate and qualifier field, bits [20:18]. */ - AARCH64_FIELD (0, 8), /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ - AARCH64_FIELD ( 4, 1), /* SVE_M_4: Merge/zero select, bit 4. */ - AARCH64_FIELD (14, 1), /* SVE_M_14: Merge/zero select, bit 14. */ - AARCH64_FIELD (16, 1), /* SVE_M_16: Merge/zero select, bit 16. */ - AARCH64_FIELD (17, 1), /* SVE_N: SVE equivalent of N. */ - AARCH64_FIELD ( 0, 4), /* SVE_Pd: p0-p15, bits [3,0]. */ - AARCH64_FIELD (10, 3), /* SVE_Pg3: p0-p7, bits [12,10]. */ - AARCH64_FIELD ( 5, 4), /* SVE_Pg4_5: p0-p15, bits [8,5]. */ - AARCH64_FIELD (10, 4), /* SVE_Pg4_10: p0-p15, bits [13,10]. */ - AARCH64_FIELD (16, 4), /* SVE_Pg4_16: p0-p15, bits [19,16]. */ - AARCH64_FIELD (16, 4), /* SVE_Pm: p0-p15, bits [19,16]. */ - AARCH64_FIELD ( 5, 4), /* SVE_Pn: p0-p15, bits [8,5]. */ - AARCH64_FIELD ( 0, 4), /* SVE_Pt: p0-p15, bits [3,0]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Rm: SVE alternative position for Rm. */ - AARCH64_FIELD (16, 5), /* SVE_Rn: SVE alternative position for Rn. */ - AARCH64_FIELD ( 0, 5), /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Za_5: SVE vector register, bits [9,5]. */ - AARCH64_FIELD (16, 5), /* SVE_Za_16: SVE vector register, bits [20,16]. */ - AARCH64_FIELD ( 0, 5), /* SVE_Zd: SVE vector register. bits [4,0]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Zm_5: SVE vector register, bits [9,5]. */ - AARCH64_FIELD (16, 5), /* SVE_Zm_16: SVE vector register, bits [20,16]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Zn: SVE vector register, bits [9,5]. */ - AARCH64_FIELD ( 0, 5), /* SVE_Zt: SVE vector register, bits [4,0]. */ - AARCH64_FIELD ( 5, 1), /* SVE_i1: single-bit immediate. */ - AARCH64_FIELD (23, 1), /* SVE_i1_23: single-bit immediate. */ - AARCH64_FIELD (22, 2), /* SVE_i2: 2-bit index, bits [23,22]. */ - AARCH64_FIELD (20, 1), /* SVE_i2h: high bit of 2bit immediate, bits. */ - AARCH64_FIELD (22, 1), /* SVE_i3h: high bit of 3-bit immediate. */ - AARCH64_FIELD (19, 2), /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */ - AARCH64_FIELD (22, 2), /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ - AARCH64_FIELD (11, 1), /* SVE_i3l: low bit of 3-bit immediate. */ - AARCH64_FIELD (12, 1), /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ - AARCH64_FIELD (10, 2), /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */ - AARCH64_FIELD (16, 3), /* SVE_imm3: 3-bit immediate field. */ - AARCH64_FIELD (16, 4), /* SVE_imm4: 4-bit immediate field. */ - AARCH64_FIELD ( 5, 5), /* SVE_imm5: 5-bit immediate field. */ - AARCH64_FIELD (16, 5), /* SVE_imm5b: secondary 5-bit immediate field. */ - AARCH64_FIELD (16, 6), /* SVE_imm6: 6-bit immediate field. */ - AARCH64_FIELD (14, 7), /* SVE_imm7: 7-bit immediate field. */ - AARCH64_FIELD ( 5, 8), /* SVE_imm8: 8-bit immediate field. */ - AARCH64_FIELD ( 5, 9), /* SVE_imm9: 9-bit immediate field. */ - AARCH64_FIELD (11, 6), /* SVE_immr: SVE equivalent of immr. */ - AARCH64_FIELD ( 5, 6), /* SVE_imms: SVE equivalent of imms. */ - AARCH64_FIELD (10, 2), /* SVE_msz: 2-bit shift amount for ADR. */ - AARCH64_FIELD ( 5, 5), /* SVE_pattern: vector pattern enumeration. */ - AARCH64_FIELD ( 0, 4), /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */ - AARCH64_FIELD (16, 1), /* SVE_rot1: 1-bit rotation amount. */ - AARCH64_FIELD (10, 2), /* SVE_rot2: 2-bit rotation amount. */ - AARCH64_FIELD (10, 1), /* SVE_rot3: 1-bit rotation amount at bit 10. */ - AARCH64_FIELD (17, 2), /* SVE_size: 2-bit element size, bits [18,17]. */ - AARCH64_FIELD (22, 1), /* SVE_sz: 1-bit element size select. */ - AARCH64_FIELD (30, 1), /* SVE_sz2: 1-bit element size select. */ - AARCH64_FIELD (17, 1), /* SVE_sz3: 1-bit element size select. */ - AARCH64_FIELD (14, 1), /* SVE_sz4: 1-bit element size select. */ - AARCH64_FIELD (16, 4), /* SVE_tsz: triangular size select. */ - AARCH64_FIELD (22, 2), /* SVE_tszh: triangular size select high, bits [23,22]. */ - AARCH64_FIELD ( 8, 2), /* SVE_tszl_8: triangular size select low, bits [9,8]. */ - AARCH64_FIELD (19, 2), /* SVE_tszl_19: triangular size select low, bits [20,19]. */ - AARCH64_FIELD (14, 1), /* SVE_xs_14: UXTW/SXTW select (bit 14). */ - AARCH64_FIELD (22, 1), /* SVE_xs_22: UXTW/SXTW select (bit 22). */ - AARCH64_FIELD (22, 1), /* S_imm10: in LDRAA and LDRAB instructions. */ - AARCH64_FIELD (16, 3), /* abc: a:b:c bits in AdvSIMD modified immediate. */ - AARCH64_FIELD (13, 3), /* asisdlso_opcode: opcode in advsimd ld/st single element. */ - AARCH64_FIELD (19, 5), /* b40: in the test bit and branch instructions. */ - AARCH64_FIELD (31, 1), /* b5: in the test bit and branch instructions. */ - AARCH64_FIELD (12, 4), /* cmode: in advsimd modified immediate instructions. */ - AARCH64_FIELD (12, 4), /* cond: condition flags as a source operand. */ - AARCH64_FIELD ( 0, 4), /* cond2: condition in truly conditional-executed inst. */ - AARCH64_FIELD ( 5, 5), /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ - AARCH64_FIELD (21, 2), /* hw: in move wide constant instructions. */ - AARCH64_FIELD ( 0, 1), /* imm1_0: general immediate in bits [0]. */ - AARCH64_FIELD ( 2, 1), /* imm1_2: general immediate in bits [2]. */ - AARCH64_FIELD ( 3, 1), /* imm1_3: general immediate in bits [3]. */ - AARCH64_FIELD ( 8, 1), /* imm1_8: general immediate in bits [8]. */ - AARCH64_FIELD (10, 1), /* imm1_10: general immediate in bits [10]. */ - AARCH64_FIELD (14, 1), /* imm1_14: general immediate in bits [14]. */ - AARCH64_FIELD (15, 1), /* imm1_15: general immediate in bits [15]. */ - AARCH64_FIELD (16, 1), /* imm1_16: general immediate in bits [16]. */ - AARCH64_FIELD (22, 1), /* imm1_22: general immediate in bits [22]. */ - AARCH64_FIELD ( 0, 2), /* imm2_0: general immediate in bits [1:0]. */ - AARCH64_FIELD ( 1, 2), /* imm2_1: general immediate in bits [2:1]. */ - AARCH64_FIELD ( 2, 2), /* imm2_2: general immediate in bits [3:2]. */ - AARCH64_FIELD ( 4, 2), /* imm2_4: general immediate in bits [5:4]. */ - AARCH64_FIELD ( 8, 2), /* imm2_8: general immediate in bits [9:8]. */ - AARCH64_FIELD (10, 2), /* imm2_10: 2-bit immediate, bits [11:10] */ - AARCH64_FIELD (12, 2), /* imm2_12: 2-bit immediate, bits [13:12] */ - AARCH64_FIELD (13, 2), /* imm2_13: 2-bit immediate, bits [14:13] */ - AARCH64_FIELD (15, 2), /* imm2_15: 2-bit immediate, bits [16:15] */ - AARCH64_FIELD (16, 2), /* imm2_16: 2-bit immediate, bits [17:16] */ - AARCH64_FIELD (19, 2), /* imm2_19: 2-bit immediate, bits [20:19] */ - AARCH64_FIELD ( 0, 3), /* imm3_0: general immediate in bits [2:0]. */ - AARCH64_FIELD ( 5, 3), /* imm3_5: general immediate in bits [7:5]. */ - AARCH64_FIELD (10, 3), /* imm3_10: in add/sub extended reg instructions. */ - AARCH64_FIELD (12, 3), /* imm3_12: general immediate in bits [14:12]. */ - AARCH64_FIELD (14, 3), /* imm3_14: general immediate in bits [16:14]. */ - AARCH64_FIELD (15, 3), /* imm3_15: general immediate in bits [17:15]. */ - AARCH64_FIELD (19, 3), /* imm3_19: general immediate in bits [21:19]. */ - AARCH64_FIELD ( 0, 4), /* imm4_0: in rmif instructions. */ - AARCH64_FIELD ( 5, 4), /* imm4_5: in SME instructions. */ - AARCH64_FIELD (10, 4), /* imm4_10: in adddg/subg instructions. */ - AARCH64_FIELD (11, 4), /* imm4_11: in advsimd ext and advsimd ins instructions. */ - AARCH64_FIELD (14, 4), /* imm4_14: general immediate in bits [17:14]. */ - AARCH64_FIELD (16, 5), /* imm5: in conditional compare (immediate) instructions. */ - AARCH64_FIELD (10, 6), /* imm6_10: in add/sub reg shifted instructions. */ - AARCH64_FIELD (15, 6), /* imm6_15: in rmif instructions. */ - AARCH64_FIELD (15, 7), /* imm7: in load/store pair pre/post index instructions. */ - AARCH64_FIELD (13, 8), /* imm8: in floating-point scalar move immediate inst. */ - AARCH64_FIELD (12, 9), /* imm9: in load/store pre/post index instructions. */ - AARCH64_FIELD ( 5, 9), /* imm9_5: in CB (immediate). */ - AARCH64_FIELD (10,12), /* imm12: in ld/st unsigned imm or add/sub shifted inst. */ - AARCH64_FIELD ( 5,14), /* imm14: in test bit and branch instructions. */ - AARCH64_FIELD ( 0,16), /* imm16_0: in udf instruction. */ - AARCH64_FIELD ( 5,16), /* imm16_5: in exception instructions. */ - AARCH64_FIELD (17, 1), /* imm17_1: in 1 bit element index. */ - AARCH64_FIELD (17, 2), /* imm17_2: in 2 bits element index. */ - AARCH64_FIELD ( 5,19), /* imm19: e.g. in CBZ. */ - AARCH64_FIELD ( 0,26), /* imm26: in unconditional branch instructions. */ - AARCH64_FIELD (16, 3), /* immb: in advsimd shift by immediate instructions. */ - AARCH64_FIELD (19, 4), /* immh: in advsimd shift by immediate instructions. */ - AARCH64_FIELD ( 5,19), /* immhi: e.g. in ADRP. */ - AARCH64_FIELD (29, 2), /* immlo: e.g. in ADRP. */ - AARCH64_FIELD (16, 6), /* immr: in bitfield and logical immediate instructions. */ - AARCH64_FIELD (10, 6), /* imms: in bitfield and logical immediate instructions. */ - AARCH64_FIELD (11, 1), /* index: in ld/st inst deciding the pre/post-index. */ - AARCH64_FIELD (24, 1), /* index2: in ld/st pair inst deciding the pre/post-index. */ - AARCH64_FIELD (30, 2), /* ldst_size: size field in ld/st reg offset inst. */ - AARCH64_FIELD (13, 2), /* len: in advsimd tbl/tbx instructions. */ - AARCH64_FIELD (30, 1), /* lse_sz: in LSE extension atomic instructions. */ - AARCH64_FIELD ( 0, 4), /* nzcv: flag bit specifier, encoded in the "nzcv" field. */ - AARCH64_FIELD (29, 1), /* op: in AdvSIMD modified immediate instructions. */ - AARCH64_FIELD (19, 2), /* op0: in the system instructions. */ - AARCH64_FIELD (16, 3), /* op1: in the system instructions. */ - AARCH64_FIELD ( 5, 3), /* op2: in the system instructions. */ - AARCH64_FIELD (22, 2), /* opc: in load/store reg offset instructions. */ - AARCH64_FIELD (23, 1), /* opc1: in load/store reg offset instructions. */ - AARCH64_FIELD (12, 4), /* opcode: in advsimd load/store instructions. */ - AARCH64_FIELD (13, 3), /* option: in ld/st reg offset + add/sub extended reg inst. */ - AARCH64_FIELD (11, 2), /* rotate1: FCMLA immediate rotate. */ - AARCH64_FIELD (13, 2), /* rotate2: Indexed element FCMLA immediate rotate. */ - AARCH64_FIELD (12, 1), /* rotate3: FCADD immediate rotate. */ - AARCH64_FIELD (10, 6), /* scale: in the fixed-point scalar to fp converting inst. */ - AARCH64_FIELD (31, 1), /* sf: in integer data processing instructions. */ - AARCH64_FIELD (22, 2), /* shift: in add/sub reg/imm shifted instructions. */ - AARCH64_FIELD (22, 2), /* size: in most AdvSIMD and floating-point instructions. */ - AARCH64_FIELD (22, 1), /* sz: 1-bit element size select. */ - AARCH64_FIELD (22, 2), /* type: floating point type field in fp data inst. */ - AARCH64_FIELD (10, 2), /* vldst_size: size field in the AdvSIMD load/store inst. */ - AARCH64_FIELD ( 5, 3), /* off3: immediate offset used to calculate slice number in a ZA tile. */ - AARCH64_FIELD ( 5, 2), /* off2: immediate offset used to calculate slice number in a ZA tile. */ - AARCH64_FIELD ( 7, 1), /* ZAn_1: name of the 1bit encoded ZA tile. */ - AARCH64_FIELD ( 5, 1), /* ol: immediate offset used to calculate slice number in a ZA tile. */ - AARCH64_FIELD ( 6, 2), /* ZAn_2: name of the 2bit encoded ZA tile. */ - AARCH64_FIELD ( 5, 3), /* ZAn_3: name of the 3bit encoded ZA tile. */ - AARCH64_FIELD ( 6, 1), /* ZAn: name of the bit encoded ZA tile. */ - AARCH64_FIELD (12, 4), /* opc2: in rcpc3 ld/st inst deciding the pre/post-index. */ - AARCH64_FIELD (30, 2), /* rcpc3_size: in rcpc3 ld/st, field controls Rt/Rt2 width. */ - AARCH64_FIELD ( 5, 1), /* FLD_brbop: used in BRB to mean IALL or INJ. */ - AARCH64_FIELD ( 8, 1), /* ZA8_1: name of the 1 bit encoded ZA tile ZA0-ZA1. */ - AARCH64_FIELD ( 7, 2), /* ZA7_2: name of the 2 bits encoded ZA tile ZA0-ZA3. */ - AARCH64_FIELD ( 6, 3), /* ZA6_3: name of the 3 bits encoded ZA tile ZA0-ZA7. */ - AARCH64_FIELD ( 5, 4), /* ZA5_4: name of the 4 bits encoded ZA tile ZA0-ZA15. */ -}; - enum aarch64_operand_class aarch64_get_operand_class (enum aarch64_opnd type) { diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 9be0275391c..3a7085a3def 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -24,232 +24,6 @@ #include #include "opcode/aarch64.h" -/* Instruction fields. - Keep this sorted alphanumerically and synced with the fields array - in aarch64-opc.c. */ -enum aarch64_field_kind -{ - FLD_NIL, - FLD_CONST_0, - FLD_CONST_00, - FLD_CONST_01, - FLD_CONST_1, - FLD_CRm, - FLD_CRm_dsb_nxs, - FLD_CRn, - FLD_CSSC_imm8, - FLD_H, - FLD_L, - FLD_LSE128_Rt, - FLD_LSE128_Rt2, - FLD_M, - FLD_N, - FLD_Q, - FLD_Ra, - FLD_Rd, - FLD_Rm, - FLD_Rn, - FLD_Rs, - FLD_Rt, - FLD_Rt2, - FLD_S, - FLD_SM3_imm2, - FLD_SME_Pdx2, - FLD_SME_Pm, - FLD_SME_PNd3, - FLD_SME_PNn3, - FLD_SME_Q, - FLD_SME_Rm, - FLD_SME_Rv, - FLD_SME_V, - FLD_SME_VL_10, - FLD_SME_VL_13, - FLD_SME_ZAda_1b, - FLD_SME_ZAda_2b, - FLD_SME_ZAda_3b, - FLD_SME_Zdn2, - FLD_SME_Zdn4, - FLD_SME_Zm, - FLD_SME_Zm17_3, - FLD_SME_Zm2, - FLD_SME_Zm4, - FLD_SME_Zn2, - FLD_SME_Zn4, - FLD_SME_Zn6_3, - FLD_SME_ZtT, - FLD_SME_Zt3, - FLD_SME_Zt2, - FLD_SME_i1, - FLD_SME_size_12, - FLD_SME_size_22, - FLD_SME_sz_23, - FLD_SME_tszh, - FLD_SME_tszl, - FLD_SME_zero_mask, - FLD_SVE_M_4, - FLD_SVE_M_14, - FLD_SVE_M_16, - FLD_SVE_N, - FLD_SVE_Pd, - FLD_SVE_Pg3, - FLD_SVE_Pg4_5, - FLD_SVE_Pg4_10, - FLD_SVE_Pg4_16, - FLD_SVE_Pm, - FLD_SVE_Pn, - FLD_SVE_Pt, - FLD_SVE_Rm, - FLD_SVE_Rn, - FLD_SVE_Vd, - FLD_SVE_Vm, - FLD_SVE_Vn, - FLD_SVE_Za_5, - FLD_SVE_Za_16, - FLD_SVE_Zd, - FLD_SVE_Zm_5, - FLD_SVE_Zm_16, - FLD_SVE_Zn, - FLD_SVE_Zt, - FLD_SVE_i1, - FLD_SVE_i1_23, - FLD_SVE_i2, - FLD_SVE_i2h, - FLD_SVE_i3h, - FLD_SVE_i3h2, - FLD_SVE_i3h3, - FLD_SVE_i3l, - FLD_SVE_i3l2, - FLD_SVE_i4l2, - FLD_SVE_imm3, - FLD_SVE_imm4, - FLD_SVE_imm5, - FLD_SVE_imm5b, - FLD_SVE_imm6, - FLD_SVE_imm7, - FLD_SVE_imm8, - FLD_SVE_imm9, - FLD_SVE_immr, - FLD_SVE_imms, - FLD_SVE_msz, - FLD_SVE_pattern, - FLD_SVE_prfop, - FLD_SVE_rot1, - FLD_SVE_rot2, - FLD_SVE_rot3, - FLD_SVE_size, - FLD_SVE_sz, - FLD_SVE_sz2, - FLD_SVE_sz3, - FLD_SVE_sz4, - FLD_SVE_tsz, - FLD_SVE_tszh, - FLD_SVE_tszl_8, - FLD_SVE_tszl_19, - FLD_SVE_xs_14, - FLD_SVE_xs_22, - FLD_S_imm10, - FLD_abc, - FLD_asisdlso_opcode, - FLD_b40, - FLD_b5, - FLD_cmode, - FLD_cond, - FLD_cond2, - FLD_defgh, - FLD_hw, - FLD_imm1_0, - FLD_imm1_2, - FLD_imm1_3, - FLD_imm1_8, - FLD_imm1_10, - FLD_imm1_14, - FLD_imm1_15, - FLD_imm1_16, - FLD_imm1_22, - FLD_imm2_0, - FLD_imm2_1, - FLD_imm2_2, - FLD_imm2_4, - FLD_imm2_8, - FLD_imm2_10, - FLD_imm2_12, - FLD_imm2_13, - FLD_imm2_15, - FLD_imm2_16, - FLD_imm2_19, - FLD_imm3_0, - FLD_imm3_5, - FLD_imm3_10, - FLD_imm3_12, - FLD_imm3_14, - FLD_imm3_15, - FLD_imm3_19, - FLD_imm4_0, - FLD_imm4_5, - FLD_imm4_10, - FLD_imm4_11, - FLD_imm4_14, - FLD_imm5, - FLD_imm6_10, - FLD_imm6_15, - FLD_imm7, - FLD_imm8, - FLD_imm9, - FLD_imm9_5, - FLD_imm12, - FLD_imm14, - FLD_imm16_0, - FLD_imm16_5, - FLD_imm17_1, - FLD_imm17_2, - FLD_imm19, - FLD_imm26, - FLD_immb, - FLD_immh, - FLD_immhi, - FLD_immlo, - FLD_immr, - FLD_imms, - FLD_index, - FLD_index2, - FLD_ldst_size, - FLD_len, - FLD_lse_sz, - FLD_nzcv, - FLD_op, - FLD_op0, - FLD_op1, - FLD_op2, - FLD_opc, - FLD_opc1, - FLD_opcode, - FLD_option, - FLD_rotate1, - FLD_rotate2, - FLD_rotate3, - FLD_scale, - FLD_sf, - FLD_shift, - FLD_size, - FLD_sz, - FLD_type, - FLD_vldst_size, - FLD_off3, - FLD_off2, - FLD_ZAn_1, - FLD_ol, - FLD_ZAn_2, - FLD_ZAn_3, - FLD_ZAn, - FLD_opc2, - FLD_rcpc3_size, - FLD_brbop, - FLD_ZA8_1, - FLD_ZA7_2, - FLD_ZA6_3, - FLD_ZA5_4, -}; - /* Field description. If is_const is false, this identifies a bitfield in an instruction encoding @@ -281,11 +55,233 @@ struct aarch64_field typedef struct aarch64_field aarch64_field; -#define AARCH64_FIELD(lsb, width) {width, lsb, false} -#define AARCH64_FIELD_CONST(val, width) {width, val, true} -#define AARCH64_FIELD_NIL {0, 0, false} +#define AARCH64_FIELD(lsb, width) ((aarch64_field) {width, lsb, false}) +#define AARCH64_FIELD_CONST(val, width) ((aarch64_field) {width, val, true}) +#define AARCH64_FIELD_NIL ((aarch64_field) {0, 0, false}) + +#define FLD_CONST_0 AARCH64_FIELD_CONST (0, 1) +#define FLD_CONST_00 AARCH64_FIELD_CONST (0, 2) +#define FLD_CONST_01 AARCH64_FIELD_CONST (1, 2) +#define FLD_CONST_1 AARCH64_FIELD_CONST (1, 1) + +/* Instruction fields. These defines are included to reduce the initial diff + size, but the indirection should eventually be eliminated. */ +#define FLD_NIL AARCH64_FIELD( 0, 0) +#define FLD_CRm AARCH64_FIELD( 8, 4) +#define FLD_CRm_dsb_nxs AARCH64_FIELD(10, 2) +#define FLD_CRn AARCH64_FIELD(12, 4) +#define FLD_CSSC_imm8 AARCH64_FIELD(10, 8) +#define FLD_H AARCH64_FIELD(11, 1) +#define FLD_L AARCH64_FIELD(21, 1) +#define FLD_LSE128_Rt AARCH64_FIELD( 0, 5) +#define FLD_LSE128_Rt2 AARCH64_FIELD(16, 5) +#define FLD_M AARCH64_FIELD(20, 1) +#define FLD_N AARCH64_FIELD(22, 1) +#define FLD_Q AARCH64_FIELD(30, 1) +#define FLD_Ra AARCH64_FIELD(10, 5) +#define FLD_Rd AARCH64_FIELD( 0, 5) +#define FLD_Rm AARCH64_FIELD(16, 5) +#define FLD_Rn AARCH64_FIELD( 5, 5) +#define FLD_Rs AARCH64_FIELD(16, 5) +#define FLD_Rt AARCH64_FIELD( 0, 5) +#define FLD_Rt2 AARCH64_FIELD(10, 5) +#define FLD_S AARCH64_FIELD(12, 1) +#define FLD_SM3_imm2 AARCH64_FIELD(12, 2) +#define FLD_SME_Pdx2 AARCH64_FIELD( 1, 3) +#define FLD_SME_Pm AARCH64_FIELD(13, 3) +#define FLD_SME_PNd3 AARCH64_FIELD( 0, 3) +#define FLD_SME_PNn3 AARCH64_FIELD( 5, 3) +#define FLD_SME_Q AARCH64_FIELD(16, 1) +#define FLD_SME_Rm AARCH64_FIELD(16, 2) +#define FLD_SME_Rv AARCH64_FIELD(13, 2) +#define FLD_SME_V AARCH64_FIELD(15, 1) +#define FLD_SME_VL_10 AARCH64_FIELD(10, 1) +#define FLD_SME_VL_13 AARCH64_FIELD(13, 1) +#define FLD_SME_ZAda_1b AARCH64_FIELD( 0, 1) +#define FLD_SME_ZAda_2b AARCH64_FIELD( 0, 2) +#define FLD_SME_ZAda_3b AARCH64_FIELD( 0, 3) +#define FLD_SME_Zdn2 AARCH64_FIELD( 1, 4) +#define FLD_SME_Zdn4 AARCH64_FIELD( 2, 3) +#define FLD_SME_Zm AARCH64_FIELD(16, 4) +#define FLD_SME_Zm17_3 AARCH64_FIELD(17, 3) +#define FLD_SME_Zm2 AARCH64_FIELD(17, 4) +#define FLD_SME_Zm4 AARCH64_FIELD(18, 3) +#define FLD_SME_Zn2 AARCH64_FIELD( 6, 4) +#define FLD_SME_Zn4 AARCH64_FIELD( 7, 3) +#define FLD_SME_Zn6_3 AARCH64_FIELD( 6, 3) +#define FLD_SME_ZtT AARCH64_FIELD( 4, 1) +#define FLD_SME_Zt3 AARCH64_FIELD( 0, 3) +#define FLD_SME_Zt2 AARCH64_FIELD( 0, 2) +#define FLD_SME_i1 AARCH64_FIELD(23, 1) +#define FLD_SME_size_12 AARCH64_FIELD(12, 2) +#define FLD_SME_size_22 AARCH64_FIELD(22, 2) +#define FLD_SME_sz_23 AARCH64_FIELD(23, 1) +#define FLD_SME_tszh AARCH64_FIELD(22, 1) +#define FLD_SME_tszl AARCH64_FIELD(18, 3) +#define FLD_SME_zero_mask AARCH64_FIELD(0, 8) +#define FLD_SVE_M_4 AARCH64_FIELD( 4, 1) +#define FLD_SVE_M_14 AARCH64_FIELD(14, 1) +#define FLD_SVE_M_16 AARCH64_FIELD(16, 1) +#define FLD_SVE_N AARCH64_FIELD(17, 1) +#define FLD_SVE_Pd AARCH64_FIELD( 0, 4) +#define FLD_SVE_Pg3 AARCH64_FIELD(10, 3) +#define FLD_SVE_Pg4_5 AARCH64_FIELD( 5, 4) +#define FLD_SVE_Pg4_10 AARCH64_FIELD(10, 4) +#define FLD_SVE_Pg4_16 AARCH64_FIELD(16, 4) +#define FLD_SVE_Pm AARCH64_FIELD(16, 4) +#define FLD_SVE_Pn AARCH64_FIELD( 5, 4) +#define FLD_SVE_Pt AARCH64_FIELD( 0, 4) +#define FLD_SVE_Rm AARCH64_FIELD( 5, 5) +#define FLD_SVE_Rn AARCH64_FIELD(16, 5) +#define FLD_SVE_Vd AARCH64_FIELD( 0, 5) +#define FLD_SVE_Vm AARCH64_FIELD( 5, 5) +#define FLD_SVE_Vn AARCH64_FIELD( 5, 5) +#define FLD_SVE_Za_5 AARCH64_FIELD( 5, 5) +#define FLD_SVE_Za_16 AARCH64_FIELD(16, 5) +#define FLD_SVE_Zd AARCH64_FIELD( 0, 5) +#define FLD_SVE_Zm_5 AARCH64_FIELD( 5, 5) +#define FLD_SVE_Zm_16 AARCH64_FIELD(16, 5) +#define FLD_SVE_Zn AARCH64_FIELD( 5, 5) +#define FLD_SVE_Zt AARCH64_FIELD( 0, 5) +#define FLD_SVE_i1 AARCH64_FIELD( 5, 1) +#define FLD_SVE_i1_23 AARCH64_FIELD(23, 1) +#define FLD_SVE_i2 AARCH64_FIELD(22, 2) +#define FLD_SVE_i2h AARCH64_FIELD(20, 1) +#define FLD_SVE_i3h AARCH64_FIELD(22, 1) +#define FLD_SVE_i3h2 AARCH64_FIELD(19, 2) +#define FLD_SVE_i3h3 AARCH64_FIELD(22, 2) +#define FLD_SVE_i3l AARCH64_FIELD(11, 1) +#define FLD_SVE_i3l2 AARCH64_FIELD(12, 1) +#define FLD_SVE_i4l2 AARCH64_FIELD(10, 2) +#define FLD_SVE_imm3 AARCH64_FIELD(16, 3) +#define FLD_SVE_imm4 AARCH64_FIELD(16, 4) +#define FLD_SVE_imm5 AARCH64_FIELD( 5, 5) +#define FLD_SVE_imm5b AARCH64_FIELD(16, 5) +#define FLD_SVE_imm6 AARCH64_FIELD(16, 6) +#define FLD_SVE_imm7 AARCH64_FIELD(14, 7) +#define FLD_SVE_imm8 AARCH64_FIELD( 5, 8) +#define FLD_SVE_imm9 AARCH64_FIELD( 5, 9) +#define FLD_SVE_immr AARCH64_FIELD(11, 6) +#define FLD_SVE_imms AARCH64_FIELD( 5, 6) +#define FLD_SVE_msz AARCH64_FIELD(10, 2) +#define FLD_SVE_pattern AARCH64_FIELD( 5, 5) +#define FLD_SVE_prfop AARCH64_FIELD( 0, 4) +#define FLD_SVE_rot1 AARCH64_FIELD(16, 1) +#define FLD_SVE_rot2 AARCH64_FIELD(10, 2) +#define FLD_SVE_rot3 AARCH64_FIELD(10, 1) +#define FLD_SVE_size AARCH64_FIELD(17, 2) +#define FLD_SVE_sz AARCH64_FIELD(22, 1) +#define FLD_SVE_sz2 AARCH64_FIELD(30, 1) +#define FLD_SVE_sz3 AARCH64_FIELD(17, 1) +#define FLD_SVE_sz4 AARCH64_FIELD(14, 1) +#define FLD_SVE_tsz AARCH64_FIELD(16, 4) +#define FLD_SVE_tszh AARCH64_FIELD(22, 2) +#define FLD_SVE_tszl_8 AARCH64_FIELD( 8, 2) +#define FLD_SVE_tszl_19 AARCH64_FIELD(19, 2) +#define FLD_SVE_xs_14 AARCH64_FIELD(14, 1) +#define FLD_SVE_xs_22 AARCH64_FIELD(22, 1) +#define FLD_S_imm10 AARCH64_FIELD(22, 1) +#define FLD_abc AARCH64_FIELD(16, 3) +#define FLD_asisdlso_opcode AARCH64_FIELD(13, 3) +#define FLD_b40 AARCH64_FIELD(19, 5) +#define FLD_b5 AARCH64_FIELD(31, 1) +#define FLD_cmode AARCH64_FIELD(12, 4) +#define FLD_cond AARCH64_FIELD(12, 4) +#define FLD_cond2 AARCH64_FIELD( 0, 4) +#define FLD_defgh AARCH64_FIELD( 5, 5) +#define FLD_hw AARCH64_FIELD(21, 2) +#define FLD_imm1_0 AARCH64_FIELD( 0, 1) +#define FLD_imm1_2 AARCH64_FIELD( 2, 1) +#define FLD_imm1_3 AARCH64_FIELD( 3, 1) +#define FLD_imm1_8 AARCH64_FIELD( 8, 1) +#define FLD_imm1_10 AARCH64_FIELD(10, 1) +#define FLD_imm1_14 AARCH64_FIELD(14, 1) +#define FLD_imm1_15 AARCH64_FIELD(15, 1) +#define FLD_imm1_16 AARCH64_FIELD(16, 1) +#define FLD_imm1_22 AARCH64_FIELD(22, 1) +#define FLD_imm2_0 AARCH64_FIELD( 0, 2) +#define FLD_imm2_1 AARCH64_FIELD( 1, 2) +#define FLD_imm2_2 AARCH64_FIELD( 2, 2) +#define FLD_imm2_4 AARCH64_FIELD( 4, 2) +#define FLD_imm2_8 AARCH64_FIELD( 8, 2) +#define FLD_imm2_10 AARCH64_FIELD(10, 2) +#define FLD_imm2_12 AARCH64_FIELD(12, 2) +#define FLD_imm2_13 AARCH64_FIELD(13, 2) +#define FLD_imm2_15 AARCH64_FIELD(15, 2) +#define FLD_imm2_16 AARCH64_FIELD(16, 2) +#define FLD_imm2_19 AARCH64_FIELD(19, 2) +#define FLD_imm3_0 AARCH64_FIELD( 0, 3) +#define FLD_imm3_5 AARCH64_FIELD( 5, 3) +#define FLD_imm3_10 AARCH64_FIELD(10, 3) +#define FLD_imm3_12 AARCH64_FIELD(12, 3) +#define FLD_imm3_14 AARCH64_FIELD(14, 3) +#define FLD_imm3_15 AARCH64_FIELD(15, 3) +#define FLD_imm3_19 AARCH64_FIELD(19, 3) +#define FLD_imm4_0 AARCH64_FIELD( 0, 4) +#define FLD_imm4_5 AARCH64_FIELD( 5, 4) +#define FLD_imm4_10 AARCH64_FIELD(10, 4) +#define FLD_imm4_11 AARCH64_FIELD(11, 4) +#define FLD_imm4_14 AARCH64_FIELD(14, 4) +#define FLD_imm5 AARCH64_FIELD(16, 5) +#define FLD_imm6_10 AARCH64_FIELD(10, 6) +#define FLD_imm6_15 AARCH64_FIELD(15, 6) +#define FLD_imm7 AARCH64_FIELD(15, 7) +#define FLD_imm8 AARCH64_FIELD(13, 8) +#define FLD_imm9 AARCH64_FIELD(12, 9) +#define FLD_imm9_5 AARCH64_FIELD( 5, 9) +#define FLD_imm12 AARCH64_FIELD(10, 12) +#define FLD_imm14 AARCH64_FIELD( 5, 14) +#define FLD_imm16_0 AARCH64_FIELD( 0, 16) +#define FLD_imm16_5 AARCH64_FIELD( 5, 16) +#define FLD_imm17_1 AARCH64_FIELD(17, 1) +#define FLD_imm17_2 AARCH64_FIELD(17, 2) +#define FLD_imm19 AARCH64_FIELD( 5, 19) +#define FLD_imm26 AARCH64_FIELD( 0, 26) +#define FLD_immb AARCH64_FIELD(16, 3) +#define FLD_immh AARCH64_FIELD(19, 4) +#define FLD_immhi AARCH64_FIELD( 5, 19) +#define FLD_immlo AARCH64_FIELD(29, 2) +#define FLD_immr AARCH64_FIELD(16, 6) +#define FLD_imms AARCH64_FIELD(10, 6) +#define FLD_index AARCH64_FIELD(11, 1) +#define FLD_index2 AARCH64_FIELD(24, 1) +#define FLD_ldst_size AARCH64_FIELD(30, 2) +#define FLD_len AARCH64_FIELD(13, 2) +#define FLD_lse_sz AARCH64_FIELD(30, 1) +#define FLD_nzcv AARCH64_FIELD( 0, 4) +#define FLD_op AARCH64_FIELD(29, 1) +#define FLD_op0 AARCH64_FIELD(19, 2) +#define FLD_op1 AARCH64_FIELD(16, 3) +#define FLD_op2 AARCH64_FIELD( 5, 3) +#define FLD_opc AARCH64_FIELD(22, 2) +#define FLD_opc1 AARCH64_FIELD(23, 1) +#define FLD_opcode AARCH64_FIELD(12, 4) +#define FLD_option AARCH64_FIELD(13, 3) +#define FLD_rotate1 AARCH64_FIELD(11, 2) +#define FLD_rotate2 AARCH64_FIELD(13, 2) +#define FLD_rotate3 AARCH64_FIELD(12, 1) +#define FLD_scale AARCH64_FIELD(10, 6) +#define FLD_sf AARCH64_FIELD(31, 1) +#define FLD_shift AARCH64_FIELD(22, 2) +#define FLD_size AARCH64_FIELD(22, 2) +#define FLD_sz AARCH64_FIELD(22, 1) +#define FLD_type AARCH64_FIELD(22, 2) +#define FLD_vldst_size AARCH64_FIELD(10, 2) +#define FLD_off3 AARCH64_FIELD( 5, 3) +#define FLD_off2 AARCH64_FIELD( 5, 2) +#define FLD_ZAn_1 AARCH64_FIELD( 7, 1) +#define FLD_ol AARCH64_FIELD( 5, 1) +#define FLD_ZAn_2 AARCH64_FIELD( 6, 2) +#define FLD_ZAn_3 AARCH64_FIELD( 5, 3) +#define FLD_ZAn AARCH64_FIELD( 6, 1) +#define FLD_opc2 AARCH64_FIELD(12, 4) +#define FLD_rcpc3_size AARCH64_FIELD(30, 2) +#define FLD_brbop AARCH64_FIELD( 5, 1) +#define FLD_ZA8_1 AARCH64_FIELD( 8, 1) +#define FLD_ZA7_2 AARCH64_FIELD( 7, 2) +#define FLD_ZA6_3 AARCH64_FIELD( 6, 3) +#define FLD_ZA5_4 AARCH64_FIELD( 5, 4) -extern const aarch64_field aarch64_fields[]; /* Operand description. */ @@ -301,7 +297,7 @@ struct aarch64_operand /* The associated instruction bit-fields; no operand has more than 5 bit-fields */ - enum aarch64_field_kind fields[6]; + aarch64_field fields[6]; /* Brief description */ const char *desc; @@ -454,8 +450,8 @@ get_operand_specific_data (const aarch64_operand *operand) static inline unsigned get_operand_field_width (const aarch64_operand *operand, unsigned n) { - assert (operand->fields[n] != FLD_NIL); - return aarch64_fields[operand->fields[n]].width; + assert (operand->fields[n].width != 0); + return operand->fields[n].width; } /* Return the total width of the operand *OPERAND. */ @@ -464,8 +460,8 @@ get_operand_fields_width (const aarch64_operand *operand) { int i = 0; unsigned width = 0; - while (operand->fields[i] != FLD_NIL) - width += aarch64_fields[operand->fields[i++]].width; + while (operand->fields[i].width != 0) + width += operand->fields[i++].width; assert (width > 0 && width < 32); return width; } @@ -508,12 +504,11 @@ gen_mask (int width) /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */ static inline int -gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret) +gen_sub_field (aarch64_field field, int lsb_rel, int width, aarch64_field *ret) { - const aarch64_field *field = &aarch64_fields[kind]; - if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width) + if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field.width) return 0; - ret->num = field->num + lsb_rel; + ret->num = field.num + lsb_rel; ret->width = width; return 1; } @@ -522,19 +517,19 @@ gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_fie of the opcode. */ static inline void -insert_field_2 (const aarch64_field *field, aarch64_insn *code, - aarch64_insn value, aarch64_insn mask) +insert_field (aarch64_field field, aarch64_insn *code, + aarch64_insn value, aarch64_insn mask) { - assert (field->width < 32 && field->width >= 1 - && (field->is_const ? (field->num < 1 << field->width) - : (field->num + field->width <= 32))); - value &= gen_mask (field->width); - if (field->is_const) + assert (field.width < 32 && field.width >= 1 + && (field.is_const ? (field.num < 1 << field.width) + : (field.num + field.width <= 32))); + value &= gen_mask (field.width); + if (field.is_const) { - assert (value == field->num); + assert (value == field.num); return; } - value <<= field->num; + value <<= field.num; /* In some opcodes, field can be part of the base opcode, e.g. the size field in FADD. The following helps avoid corrupt the base opcode. */ value &= ~mask; @@ -545,40 +540,20 @@ insert_field_2 (const aarch64_field *field, aarch64_insn *code, mask of the opcode. */ static inline aarch64_insn -extract_field_2 (const aarch64_field *field, aarch64_insn code, - aarch64_insn mask) +extract_field (aarch64_field field, aarch64_insn code, + aarch64_insn mask) { aarch64_insn value; /* Check for constant field. */ - if (field->is_const) - return field->num; + if (field.is_const) + return field.num; /* Clear any bit that is a part of the base opcode. */ code &= ~mask; - value = (code >> field->num) & gen_mask (field->width); + value = (code >> field.num) & gen_mask (field.width); return value; } -/* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask - of the opcode. */ - -static inline void -insert_field (enum aarch64_field_kind kind, aarch64_insn *code, - aarch64_insn value, aarch64_insn mask) -{ - insert_field_2 (&aarch64_fields[kind], code, value, mask); -} - -/* Extract field KIND of CODE and return the value. MASK can be zero or the - base mask of the opcode. */ - -static inline aarch64_insn -extract_field (enum aarch64_field_kind kind, aarch64_insn code, - aarch64_insn mask) -{ - return extract_field_2 (&aarch64_fields[kind], code, mask); -} - extern aarch64_insn extract_fields (aarch64_insn code, aarch64_insn mask, ...);