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x86: swap operands in OUT-with-immediate template
In a number of places we assume that immediates come first in the set of operands. It is mere luck that so far OUT, having operands the other way around, wasn't negatively impacted by this. Leverage this to have a few loops start from the first non-immediate operand (or in one case to stop there). Note, however, that process_immext() inserts an immediate last, so especially all output_*() functions cannot be changed in the same way.
This commit is contained in:
Jan Beulich
parent
412164f0a9
commit
620dc0f523
3 changed files with 39 additions and 37 deletions
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@ -2589,22 +2589,23 @@ operand_size_match (const insn_template *t)
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&& t->opcode_modifier.jump != JUMP_ABSOLUTE)
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return match;
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/* Check memory and accumulator operand size. */
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for (j = 0; j < i.operands; j++)
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{
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/* Instruction templates with only sign-extended 8-bit immediate
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operand also have a second template with full-operand-size
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immediate operand under a different opcode. Don't match the
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first template if sign-extended 8-bit immediate operand should
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be excluded. */
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if (pp.no_imm8s
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&& !t->operand_types[j].bitfield.imm8
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&& t->operand_types[j].bitfield.imm8s)
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{
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match = 0;
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break;
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}
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for (j = 0; j < i.imm_operands; j++)
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/* Instruction templates with only sign-extended 8-bit immediate
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operand also have a second template with full-operand-size
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immediate operand under a different opcode. Don't match the
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first template if sign-extended 8-bit immediate operand should
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be excluded. */
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if (pp.no_imm8s
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&& !t->operand_types[j].bitfield.imm8
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&& t->operand_types[j].bitfield.imm8s)
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{
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gas_assert (!t->opcode_modifier.d);
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return 0;
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}
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/* Check memory and accumulator operand size. */
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for (; j < i.operands; j++)
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{
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if (i.types[j].bitfield.class == Reg
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&& (t->operand_types[j].bitfield.class == Reg
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|| (t->operand_types[j].bitfield.instance == Accum
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@ -2655,7 +2656,7 @@ operand_size_match (const insn_template *t)
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/* Check reverse. */
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gas_assert (i.operands >= 2);
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for (j = 0; j < i.operands; j++)
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for (j = i.imm_operands; j < i.operands; j++)
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{
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unsigned int given = i.operands - j - 1;
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@ -7129,12 +7130,14 @@ i386_assemble (char *line)
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swap_operands ();
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/* The order of the immediates should be reversed for 2-immediates EXTRQ
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and INSERTQ instructions. Also UWRMSR wants its immediate to be in the
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"canonical" place (first), despite it appearing last (in AT&T syntax, or
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because of the swapping above) in the incoming set of operands. */
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and INSERTQ instructions. Also OUT, UWRMSR, and WRMSRNS want their
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immediate to be in the "canonical" place (first), despite it appearing
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last (in AT&T syntax, or because of the swapping above) in the incoming
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set of operands. */
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if ((i.imm_operands == 2
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&& (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq))
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|| ((t->mnem_off == MN_uwrmsr || t->mnem_off == MN_wrmsrns)
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|| ((t->mnem_off == MN_out || t->mnem_off == MN_uwrmsr
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|| t->mnem_off == MN_wrmsrns)
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&& i.imm_operands && i.operands > i.imm_operands))
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swap_2_operands (0, 1);
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@ -7149,11 +7152,8 @@ i386_assemble (char *line)
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|| t->mnem_off == MN_rdmsr
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|| t->mnem_off == MN_wrmsrns)
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{
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for (j = 0; j < i.operands; j++)
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{
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if (operand_type_check(i.types[j], imm))
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i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
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}
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for (j = 0; j < i.imm_operands; j++)
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i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
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}
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else
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optimize_imm ();
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@ -8467,7 +8467,7 @@ optimize_disp (const insn_template *t)
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&& (!t->opcode_modifier.jump
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|| i.jumpabsolute || i.types[0].bitfield.baseindex))
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{
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for (op = 0; op < i.operands; ++op)
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for (op = i.imm_operands; op < i.operands; ++op)
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{
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const expressionS *exp = i.op[op].disps;
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@ -8808,7 +8808,7 @@ check_VecOperands (const insn_template *t)
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unsigned int j;
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type.bitfield.baseindex = 1;
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for (j = 0; j < i.operands; ++j)
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for (j = i.imm_operands; j < i.operands; ++j)
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{
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if (j != op
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&& !operand_type_register_match(i.types[j],
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@ -8824,7 +8824,7 @@ check_VecOperands (const insn_template *t)
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else if (t->opcode_modifier.broadcast && i.mem_operands)
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{
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/* Find memory operand. */
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for (op = 0; op < i.operands; op++)
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for (op = i.imm_operands; op < i.operands; op++)
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if (i.flags[op] & Operand_Mem)
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break;
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gas_assert (op < i.operands);
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@ -8933,7 +8933,7 @@ check_VecOperands (const insn_template *t)
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const i386_operand_type *type = NULL, *fallback = NULL;
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i.memshift = 0;
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for (op = 0; op < i.operands; op++)
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for (op = i.imm_operands; op < i.operands; op++)
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if (i.flags[op] & Operand_Mem)
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{
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if (t->opcode_modifier.evex == EVEXLIG)
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@ -8975,7 +8975,7 @@ check_VecOperands (const insn_template *t)
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i.memshift = -1;
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}
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for (op = 0; op < i.operands; op++)
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for (op = i.imm_operands; op < i.operands; op++)
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if (operand_type_check (i.types[op], disp)
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&& i.op[op].disps->X_op == O_constant)
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{
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@ -9069,7 +9069,7 @@ check_EgprOperands (const insn_template *t)
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if (!t->opcode_modifier.noegpr)
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return false;
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for (unsigned int op = 0; op < i.operands; op++)
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for (unsigned int op = i.imm_operands; op < i.operands; op++)
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{
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if (i.types[op].bitfield.class != Reg)
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continue;
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@ -9131,7 +9131,7 @@ check_APX_operands (const insn_template *t)
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static bool
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check_Rex_required (void)
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{
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for (unsigned int op = 0; op < i.operands; op++)
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for (unsigned int op = i.imm_operands; op < i.operands; op++)
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{
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if (i.types[op].bitfield.class != Reg)
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continue;
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@ -10444,7 +10444,7 @@ process_suffix (const insn_template *t)
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else
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need = flag_code == CODE_64BIT ? need_qword : need_word;
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for (op = 0; op < i.operands; op++)
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for (op = i.imm_operands; op < i.operands; op++)
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{
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if (i.types[op].bitfield.class != Reg)
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continue;
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@ -10776,7 +10776,7 @@ process_operands (void)
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unnecessary segment overrides. */
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const reg_entry *default_seg = NULL;
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for (unsigned int j = 0; j < i.operands; j++)
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for (unsigned int j = i.imm_operands; j < i.operands; j++)
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if (i.types[j].bitfield.instance != InstanceNone)
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i.reg_operands--;
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@ -275,7 +275,9 @@ in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
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in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword }
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in, 0xe4, 0, W|No_sSuf|No_qSuf|IntelSuffix, { Imm8 }
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in, 0xec, 0, W|No_sSuf|No_qSuf|IntelSuffix, { InOutPortReg }
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out, 0xe6, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 }
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// Immediates want to be first; md_assemble() takes care of swapping operands
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// accordingly.
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out, 0xe6, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
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out, 0xee, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg }
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out, 0xe6, 0, W|No_sSuf|No_qSuf|IntelSuffix, { Imm8 }
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out, 0xee, 0, W|No_sSuf|No_qSuf|IntelSuffix, { InOutPortReg }
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@ -544,9 +544,9 @@ static const insn_template i386_optab[] =
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0, 0 },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } },
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{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ MN_out, 0xee, 2, SPACE_BASE, None,
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{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
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