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RISC-V: Add Zvdota extension classes

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Zvfqwdota8f: dot product of 8-bit floating-point numbers with 32-bit accumulation.

Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8 of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew constants for vsetvli/vsetivli so that assembly code can select the alternative element formats required by these dot-product instructions.

[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
	(riscv_supported_std_z_ext): New extensions.
	(riscv_multi_subset_supports): Ditto.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
	zvfqwdota8f extensions.
	* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
	constants array for e8alt and e16alt.
	(riscv_vtype_altfmt_supported): New function.
	(my_getVsetvliExpression): Ditto.
	* testsuite/gas/riscv/march-help.l: New test.
	* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
	* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
	* testsuite/gas/riscv/zvdota.d: Ditto.
	* testsuite/gas/riscv/zvdota.s: Ditto.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New encoding.
	(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
	(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
	(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
	(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
	(DECLARE_INSN): New declarations.
	* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT): New vtype altfmt.
	(enum riscv_insn_class): New extension classes.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add altfmt support.
	* riscv-opc.c (riscv_opcodes): New instructions.
This commit is contained in:
Jiawei 2026-06-30 07:54:21 -06:00 • committed by Jeff Law
parent 4f54c79267
commit 89d59bf712
12 changed files with 162 additions and 6 deletions
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17
include/opcode/riscv-opc.h
View file

@ -2577,6 +2577,17 @@
#define MASK_VFWMACCBF16_VF 0xfc00707f
#define MATCH_VFWMACCBF16_VV 0xec001057
#define MASK_VFWMACCBF16_VV 0xfc00707f
/* Zvdota instructions. */
#define MATCH_VQWDOTAU_VV 0x98000077
#define MASK_VQWDOTAU_VV 0xfc00707f
#define MATCH_VQWDOTAS_VV 0x9c000077
#define MASK_VQWDOTAS_VV 0xfc00707f
#define MATCH_VFWDOTA_VV 0x90001077
#define MASK_VFWDOTA_VV 0xfc00707f
#define MATCH_VFQWDOTA_VV 0x98001077
#define MASK_VFQWDOTA_VV 0xfc00707f
#define MATCH_VFQWDOTA_ALT_VV 0x9c001077
#define MASK_VFQWDOTA_ALT_VV 0xfc00707f
/* Vendor-specific (CORE-V) Xcvmac instructions. */
#define MATCH_CV_MAC 0x9000302b
#define MASK_CV_MAC 0xfe00707f
@ -4902,6 +4913,12 @@ DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
/* Zvfbfwma instructions. */
DECLARE_INSN(VFWMACCBF16_VF, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
DECLARE_INSN(VFWMACCBF16_VV, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
/* Zvdota instructions. */
DECLARE_INSN(vqwdotau_vv, MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV)
DECLARE_INSN(vqwdotas_vv, MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV)
DECLARE_INSN(vfwdota_vv, MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV)
DECLARE_INSN(vfqwdota_vv, MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV)
DECLARE_INSN(vfqwdota_alt_vv, MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV)
/* Zvbb/Zvkb instructions. */
DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)

8
include/opcode/riscv.h
View file

@ -374,6 +374,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define OP_SH_VTA 6
#define OP_MASK_VMA 0x1
#define OP_SH_VMA 7
#define OP_MASK_VTYPE_ALTFMT 0x1
#define OP_SH_VTYPE_ALTFMT 8
#define OP_MASK_VWD 0x1
#define OP_SH_VWD 26
@ -560,6 +562,8 @@ enum riscv_insn_class
INSN_CLASS_ZVBC,
INSN_CLASS_ZVFBFMIN,
INSN_CLASS_ZVFBFWMA,
INSN_CLASS_ZVFQWDOTA8F,
INSN_CLASS_ZVFWDOTA16BF,
INSN_CLASS_ZVKB,
INSN_CLASS_ZVKG,
INSN_CLASS_ZVKNED,
@ -567,6 +571,9 @@ enum riscv_insn_class
INSN_CLASS_ZVKSED,
INSN_CLASS_ZVKSH,
INSN_CLASS_ZVABD,
INSN_CLASS_ZVQWDOTA8I,
INSN_CLASS_ZVQWDOTA16I,
INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I,
INSN_CLASS_ZICFISS,
INSN_CLASS_ZICFISS_AND_ZCMOP,
INSN_CLASS_ZICFILP,
@ -737,6 +744,7 @@ extern const char * const riscv_pred_succ[16];
extern const char riscv_vecr_names_numeric[NVECR][NRC];
extern const char riscv_vecm_names_numeric[NVECM][NRC];
extern const char * const riscv_vsew[8];
extern const char * const riscv_vsew_altfmt[2];
extern const char * const riscv_vlmul[8];
extern const char * const riscv_vta[2];
extern const char * const riscv_vma[2];