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aarch64: Remove unused operand SM3_IMM2

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This operand was intended to be used for the sm3tt* instructions, but
those were added with operand Em instead.
This commit is contained in:
Alice Carlotti 2026-04-29 17:10:54 +01:00
parent dfaa633605
commit 9c0b9c4d84
7 changed files with 0 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

2
gas/config/tc-aarch64.c
View file

@ -6460,7 +6460,6 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
operand->reglane.regno = default_value;
break;
@ -7050,7 +7049,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
reg_type = REG_TYPE_V;
vector_reg_index:
reg = aarch64_reg_parse (&str, reg_type, &vectype);

1
include/opcode/aarch64.h
View file

@ -987,7 +987,6 @@ enum aarch64_opnd
AARCH64_OPND_SME_ZT0_INDEX_MUL_VL,/* ZT0[<imm>], bits [13:12]. */
AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
AARCH64_OPND_MOPS_ADDR_Rs, /* [Rs]!, in bits [16, 20]. */
AARCH64_OPND_MOPS_WB_Rn, /* Rn!, in bits [5, 9]. */

1
opcodes/aarch64-asm-2.c
View file

@ -866,7 +866,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
return aarch64_ins_reglane (self, info, code, inst, errors);
case AARCH64_OPND_Em_INDEX1_14:
case AARCH64_OPND_Em_INDEX2_13:

1
opcodes/aarch64-dis-2.c
View file

@ -37851,7 +37851,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
return aarch64_ext_reglane (self, info, code, inst, errors);
case AARCH64_OPND_Em_INDEX1_14:
case AARCH64_OPND_Em_INDEX2_13:

1
opcodes/aarch64-opc-2.c
View file

@ -365,7 +365,6 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
{AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},

1
opcodes/aarch64-opc.c
View file

@ -4311,7 +4311,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
snprintf (buf, size, "%s[%s]",
style_reg (styler, "v%d.%s", opnd->reglane.regno,
aarch64_get_qualifier_name (opnd->qualifier)),

2
opcodes/aarch64-tbl.h
View file

@ -8674,8 +8674,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \
"a 16-bit unsigned immediate for TME tcancel") \
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
"an indexed SM3 vector immediate") \
/* These next two are really register fields; the [...] notation \
is just syntactic sugar. */ \
Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd), \