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RISC-V: Support Zalasr extension.
This patch supports Zalasr extension(load-acquire/store-release) instructions. https://github.com/riscv/riscv-zalasr bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): New ext. (riscv_multi_subset_supports_ext): Ditto. gas/ChangeLog: * NEWS: Support Zalasr extension. * testsuite/gas/riscv/march-help.l: New ext. * testsuite/gas/riscv/zalasr.d: New test. * testsuite/gas/riscv/zalasr.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_LBA): New match opcode. (MASK_LBA): New mask opcode. (MATCH_LHA): New match opcode. (MASK_LHA): New mask opcode. (MATCH_LWA): New match opcode. (MASK_LWA): New mask opcode. (MATCH_LDA): New match opcode. (MASK_LDA): New mask opcode. (MATCH_SBR): New match opcode. (MASK_SBR): New mask opcode. (MATCH_SHR): New match opcode. (MASK_SHR): New mask opcode. (MATCH_SWR): New match opcode. (MASK_SWR): New mask opcode. (MATCH_SDR): New match opcode. (MASK_SDR): New mask opcode. (DECLARE_INSN): New insn declare. * opcode/riscv.h (enum riscv_insn_class): New ext. opcodes/ChangeLog: * riscv-opc.c: New instructions def.
This commit is contained in:
Jiawei
Jeff Law
parent
d26861e53c
commit
db7f7dd315
8 changed files with 98 additions and 0 deletions
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@ -1220,6 +1220,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
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{"zabha", "+zaamo", check_implicit_always},
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{"zacas", "+zaamo", check_implicit_always},
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{"a", "+zaamo,+zalrsc", check_implicit_always},
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{"zalasr", "+zaamo,+zalrsc,+zabha", check_implicit_always},
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{"xsfvcp", "+zve32x", check_implicit_always},
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{"xsfvqmaccqoq", "+zve32x,+zvl256b", check_implicit_always},
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@ -1478,6 +1479,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
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{"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zalasr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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{"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
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@ -2860,6 +2862,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
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case INSN_CLASS_ZABHA_AND_ZACAS:
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return (riscv_subset_supports (rps, "zabha")
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&& riscv_subset_supports (rps, "zacas"));
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case INSN_CLASS_ZALASR:
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return riscv_subset_supports (rps, "zalasr");
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case INSN_CLASS_ZALRSC:
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return riscv_subset_supports (rps, "zalrsc");
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case INSN_CLASS_ZAWRS:
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@ -3155,6 +3159,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
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return "zabha";
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}
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return "zacas";
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case INSN_CLASS_ZALASR:
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return "zalasr";
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case INSN_CLASS_ZALRSC:
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return "zalrsc";
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case INSN_CLASS_ZAWRS:
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3
gas/NEWS
3
gas/NEWS
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@ -5,6 +5,9 @@
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ABI was adopted) are now considered obsolete. They are now deprecated
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and will be removed in a future release.
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* Add support for RISC-V standard extensions:
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zalasr v1.0
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Changes in 2.46:
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* Add support for AMD Zen6 processor.
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@ -35,6 +35,7 @@ All available -march extensions for RISC-V:
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zaamo 1.0
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zabha 1.0
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zacas 1.0
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zalasr 1.0
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zalrsc 1.0
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zawrs 1.0
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zfbfmin 1.0
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26
gas/testsuite/gas/riscv/zalasr.d
Normal file
26
gas/testsuite/gas/riscv/zalasr.d
Normal file
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@ -0,0 +1,26 @@
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#as: -march=rv64i_zalasr
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#source: zalasr.s
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#objdump: -d
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.*:[ ]+file format .*
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Disassembly of section .text:
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0+000 <target>:
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[ ]+[0-9a-f]+:[ ]+3405052f[ ]+lb.aq[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3605052f[ ]+lb.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3405152f[ ]+lh.aq[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3605152f[ ]+lh.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3405252f[ ]+lw.aq[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3605252f[ ]+lw.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3405352f[ ]+ld.aq[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3605352f[ ]+ld.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3aa5002f[ ]+sb.rl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3ea5002f[ ]+sb.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3aa5102f[ ]+sh.rl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3ea5102f[ ]+sh.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3aa5202f[ ]+sw.rl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3ea5202f[ ]+sw.aqrl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3aa5302f[ ]+sd.rl[ ]+a0,\(a0\)
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[ ]+[0-9a-f]+:[ ]+3ea5302f[ ]+sd.aqrl[ ]+a0,\(a0\)
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17
gas/testsuite/gas/riscv/zalasr.s
Normal file
17
gas/testsuite/gas/riscv/zalasr.s
Normal file
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@ -0,0 +1,17 @@
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target:
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lb.aq a0, 0(a0)
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lb.aqrl a0, 0(a0)
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lh.aq a0, 0(a0)
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lh.aqrl a0, 0(a0)
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lw.aq a0, 0(a0)
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lw.aqrl a0, 0(a0)
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ld.aq a0, 0(a0)
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ld.aqrl a0, 0(a0)
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sb.rl a0, 0(a0)
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sb.aqrl a0, 0(a0)
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sh.rl a0, 0(a0)
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sh.aqrl a0, 0(a0)
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sw.rl a0, 0(a0)
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sw.aqrl a0, 0(a0)
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sd.rl a0, 0(a0)
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sd.aqrl a0, 0(a0)
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@ -2529,6 +2529,23 @@
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#define MASK_AMOCAS_D 0xf800707f
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#define MATCH_AMOCAS_Q 0x2800402f
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#define MASK_AMOCAS_Q 0xf800707f
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/* Zalasr instructions. */
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#define MATCH_LBA 0x3000002f
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#define MASK_LBA 0xf9f0707f
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#define MATCH_LHA 0x3000102f
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#define MASK_LHA 0xf9f0707f
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#define MATCH_LWA 0x3000202f
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#define MASK_LWA 0xf9f0707f
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#define MATCH_LDA 0x3000302f
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#define MASK_LDA 0xf9f0707f
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#define MATCH_SBR 0x3800002f
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#define MASK_SBR 0xf8007fff
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#define MATCH_SHR 0x3800102f
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#define MASK_SHR 0xf8007fff
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#define MATCH_SWR 0x3800202f
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#define MASK_SWR 0xf8007fff
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#define MATCH_SDR 0x3800302f
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#define MASK_SDR 0xf8007fff
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/* Zawrs instructions. */
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#define MATCH_WRS_NTO 0x00d00073
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#define MASK_WRS_NTO 0xffffffff
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@ -4876,6 +4893,15 @@ DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S)
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/* Zcmt instructions. */
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DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
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DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
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/* Zalasr instructions. */
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DECLARE_INSN(lb_aq, MATCH_LBA, MASK_LBA)
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DECLARE_INSN(lh_aq, MATCH_LHA, MASK_LHA)
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DECLARE_INSN(lw_aq, MATCH_LWA, MASK_LWA)
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DECLARE_INSN(ld_aq, MATCH_LDA, MASK_LDA)
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DECLARE_INSN(sb_rl, MATCH_SBR, MASK_SBR)
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DECLARE_INSN(sh_rl, MATCH_SHR, MASK_SHR)
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DECLARE_INSN(sw_rl, MATCH_SWR, MASK_SWR)
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DECLARE_INSN(sd_rl, MATCH_SDR, MASK_SDR)
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/* Smctr/Ssctr instruction. */
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DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
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/* Smrnmi instruction */
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@ -509,6 +509,7 @@ enum riscv_insn_class
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INSN_CLASS_ZIMOP,
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INSN_CLASS_ZMMUL,
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INSN_CLASS_ZAAMO,
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INSN_CLASS_ZALASR,
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INSN_CLASS_ZALRSC,
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INSN_CLASS_ZAWRS,
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INSN_CLASS_F_INX,
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@ -886,6 +886,24 @@ const struct riscv_opcode riscv_opcodes[] =
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{"amocas.d.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_D|MASK_AQRL, MASK_AMOCAS_D|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_Q|MASK_AQRL, MASK_AMOCAS_Q|MASK_AQRL, match_rs2_rd_even, INSN_DREF|INSN_16_BYTE },
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/* Zalasr instruction subset. */
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{"lb.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LBA|MASK_AQ, MASK_LBA|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
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{"lb.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LBA|MASK_AQRL, MASK_LBA|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
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{"lh.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LHA|MASK_AQ, MASK_LHA|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
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{"lh.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LHA|MASK_AQRL, MASK_LHA|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
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{"lw.aq", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LWA|MASK_AQ, MASK_LWA|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"lw.aqrl", 0, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LWA|MASK_AQRL, MASK_LWA|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"ld.aq", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LDA|MASK_AQ, MASK_LDA|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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{"ld.aqrl", 64, INSN_CLASS_ZALASR, "d,0(s)", MATCH_LDA|MASK_AQRL, MASK_LDA|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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{"sb.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SBR|MASK_RL, MASK_SBR|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
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{"sb.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SBR|MASK_AQRL, MASK_SBR|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
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{"sh.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SHR|MASK_RL, MASK_SHR|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
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{"sh.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SHR|MASK_AQRL, MASK_SHR|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
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{"sw.rl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SWR|MASK_RL, MASK_SWR|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"sw.aqrl", 0, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SWR|MASK_AQRL, MASK_SWR|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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{"sd.rl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SDR|MASK_RL, MASK_SDR|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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{"sd.aqrl", 64, INSN_CLASS_ZALASR, "t,0(s)", MATCH_SDR|MASK_AQRL, MASK_SDR|MASK_AQRL, match_opcode, INSN_DREF|INSN_8_BYTE },
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/* Multiply/Divide instruction subset. */
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{"mul", 0, INSN_CLASS_ZCB_AND_ZMMUL, "Cs,Cw,Ct", MATCH_C_MUL, MASK_C_MUL, match_opcode, INSN_ALIAS },
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{"mul", 0, INSN_CLASS_ZMMUL, "d,s,t", MATCH_MUL, MASK_MUL, match_opcode, 0 },
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