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RISC-V: Support Zalasr extension.

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This patch supports Zalasr extension(load-acquire/store-release) instructions.

https://github.com/riscv/riscv-zalasr

bfd/ChangeLog:

        * elfxx-riscv.c (riscv_multi_subset_supports): New ext.
        (riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

        * NEWS: Support Zalasr extension.
        * testsuite/gas/riscv/march-help.l: New ext.
        * testsuite/gas/riscv/zalasr.d: New test.
        * testsuite/gas/riscv/zalasr.s: New test.

include/ChangeLog:

        * opcode/riscv-opc.h (MATCH_LBA): New match opcode.
        (MASK_LBA): New mask opcode.
        (MATCH_LHA): New match opcode.
        (MASK_LHA): New mask opcode.
        (MATCH_LWA): New match opcode.
        (MASK_LWA): New mask opcode.
        (MATCH_LDA): New match opcode.
        (MASK_LDA): New mask opcode.
        (MATCH_SBR): New match opcode.
        (MASK_SBR): New mask opcode.
        (MATCH_SHR): New match opcode.
        (MASK_SHR): New mask opcode.
        (MATCH_SWR): New match opcode.
        (MASK_SWR): New mask opcode.
        (MATCH_SDR): New match opcode.
        (MASK_SDR): New mask opcode.
        (DECLARE_INSN): New insn declare.
        * opcode/riscv.h (enum riscv_insn_class): New ext.

opcodes/ChangeLog:

        * riscv-opc.c: New instructions def.
This commit is contained in:
Jiawei 2026-06-22 08:13:44 -06:00 • committed by Jeff Law
parent d26861e53c
commit db7f7dd315
8 changed files with 98 additions and 0 deletions
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26
include/opcode/riscv-opc.h
View file

@ -2529,6 +2529,23 @@
#define MASK_AMOCAS_D 0xf800707f
#define MATCH_AMOCAS_Q 0x2800402f
#define MASK_AMOCAS_Q 0xf800707f
/* Zalasr instructions. */
#define MATCH_LBA 0x3000002f
#define MASK_LBA 0xf9f0707f
#define MATCH_LHA 0x3000102f
#define MASK_LHA 0xf9f0707f
#define MATCH_LWA 0x3000202f
#define MASK_LWA 0xf9f0707f
#define MATCH_LDA 0x3000302f
#define MASK_LDA 0xf9f0707f
#define MATCH_SBR 0x3800002f
#define MASK_SBR 0xf8007fff
#define MATCH_SHR 0x3800102f
#define MASK_SHR 0xf8007fff
#define MATCH_SWR 0x3800202f
#define MASK_SWR 0xf8007fff
#define MATCH_SDR 0x3800302f
#define MASK_SDR 0xf8007fff
/* Zawrs instructions. */
#define MATCH_WRS_NTO 0x00d00073
#define MASK_WRS_NTO 0xffffffff
@ -4876,6 +4893,15 @@ DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S)
/* Zcmt instructions. */
DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
/* Zalasr instructions. */
DECLARE_INSN(lb_aq, MATCH_LBA, MASK_LBA)
DECLARE_INSN(lh_aq, MATCH_LHA, MASK_LHA)
DECLARE_INSN(lw_aq, MATCH_LWA, MASK_LWA)
DECLARE_INSN(ld_aq, MATCH_LDA, MASK_LDA)
DECLARE_INSN(sb_rl, MATCH_SBR, MASK_SBR)
DECLARE_INSN(sh_rl, MATCH_SHR, MASK_SHR)
DECLARE_INSN(sw_rl, MATCH_SWR, MASK_SWR)
DECLARE_INSN(sd_rl, MATCH_SDR, MASK_SDR)
/* Smctr/Ssctr instruction. */
DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
/* Smrnmi instruction */

1
include/opcode/riscv.h
View file

@ -509,6 +509,7 @@ enum riscv_insn_class
INSN_CLASS_ZIMOP,
INSN_CLASS_ZMMUL,
INSN_CLASS_ZAAMO,
INSN_CLASS_ZALASR,
INSN_CLASS_ZALRSC,
INSN_CLASS_ZAWRS,
INSN_CLASS_F_INX,