aarch64: Add support for FEAT_SVE2p2 and FEAT_SME2p2

This commit is contained in:
Alice Carlotti 2025-06-03 20:35:34 +01:00
parent f4d1a953fe
commit e68a412e16
15 changed files with 3413 additions and 721 deletions

View file

@ -10797,6 +10797,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sme-b16b16", AARCH64_FEATURE (SME_B16B16),
AARCH64_FEATURES (2, SVE_B16B16, SME2)},
{"pops", AARCH64_FEATURE (PoPS), AARCH64_NO_FEATURES},
{"sve2p2", AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2)},
{"sme2p2", AARCH64_FEATURE (SME2p2), AARCH64_FEATURE (SME2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@ -10817,12 +10819,15 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
{AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
{AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
{AARCH64_FEATURE (SME_F8F16), AARCH64_FEATURE (SME_F16F16_F8F16)},
{AARCH64_FEATURE (SVE), AARCH64_FEATURE (SVE_SME2p2)},
{AARCH64_FEATURE (SME), AARCH64_FEATURE (SVE2p1_SME)},
{AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE2_SME2)},
{AARCH64_FEATURE (SME2), AARCH64_FEATURES (2, SVE2_SME2, SVE2p1_SME2)},
{AARCH64_FEATURE (SVE2p1), AARCH64_FEATURES (3, SVE2p1_SME, SVE2p1_SME2,
SVE2p1_SME2p1)},
{AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SVE2p1_SME2p1)},
{AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p2_SME2p2)},
{AARCH64_FEATURE (SME2p2), AARCH64_FEATURES (2, SVE_SME2p2, SVE2p2_SME2p2)},
};
static aarch64_feature_set

View file

@ -299,6 +299,8 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.
@item @code{sme2p1} @tab @code{sme2}
@tab Enable SME2.1.
@item @code{sme2p2} @tab @code{sme2p1}
@tab Enable SME2.2.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
@ -327,6 +329,8 @@ automatically cause those extensions to be disabled.
@tab Enable the SVE2 SM4 Extension.
@item @code{sve2p1} @tab @code{sve2}
@tab Enable SVE2.1.
@item @code{sve2p2} @tab @code{sve2p1}
@tab Enable SVE2.2.
@item @code{the} @tab
@tab Enable the Translation Hardening Extension.
@item @code{tme} @tab

View file

@ -10,15 +10,11 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla z0\.s,z1\.h,z2\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfmmla z0\.s, z1\.h, z2\.h
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/z,z2\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfcvt z0\.h, p1/m, z2\.s
[^ :]+:[0-9]+: Error: selected processor does not support `bfcvt z0\.h,p1/z,z2\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/m,z2\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfcvt z0\.h, p1/m, z2\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/z,z2\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfcvtnt z0\.h, p1/m, z2\.s
[^ :]+:[0-9]+: Error: selected processor does not support `bfcvtnt z0\.h,p1/z,z2\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/m,z2\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: bfcvtnt z0\.h, p1/m, z2\.s

View file

@ -280,18 +280,14 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/z,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.s, p0/m, z0\.h
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtlt z0\.s,p0/z,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtlt z32\.d,p0/m,z0\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.d,p8/m,z0\.s'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtlt z0\.d,p0/m,z32\.s'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/m,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/z,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtlt z0\.d, p0/m, z0\.s
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtlt z0\.d,p0/z,z0\.s'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtnt z0\.h,p0/m,z0\.s'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.h,p0/m,z0\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.h,p8/m,z0\.s'
@ -299,27 +295,21 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/m,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.h, p0/m, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/z,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.h, p0/m, z0\.s
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtnt z0\.h,p0/z,z0\.s'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.s,p8/m,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.s,p0/m,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtnt z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtnt z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtx z32\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtx z0\.s,p8/m,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtx z0\.s,p0/m,z32\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtx z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtx z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtx z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtx z0\.s,p0/m,z2\.d'
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtxnt z0\.s,p0/m,z0\.d'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtxnt z32\.s,p0/m,z0\.d'
@ -328,9 +318,7 @@
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/m,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtxnt z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fcvtxnt z0\.s, p0/m, z0\.d
[^ :]+:[0-9]+: Error: selected processor does not support `fcvtxnt z0\.s,p0/z,z0\.d'
[^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.b,p0/m,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: flogb z0\.h, p0/m, z0\.h
@ -343,12 +331,7 @@
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: flogb z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: flogb z0\.d, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `flogb z0\.h,p0/z,z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: flogb z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: flogb z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: flogb z0\.d, p0/m, z0\.d
[^ :]+:[0-9]+: Error: selected processor does not support `flogb z0\.h,p0/z,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `flogb z32\.h,p0/m,z0\.h'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `flogb z0\.h,p8/m,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `flogb z0\.h,p0/m,z32\.h'
@ -1302,13 +1285,7 @@
[^ :]+:[0-9]+: Info: sqabs z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sqabs z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: sqabs z0\.d, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/z,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqabs z0\.b, p0/m, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqabs z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sqabs z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: sqabs z0\.d, p0/m, z0\.d
[^ :]+:[0-9]+: Error: selected processor does not support `sqabs z0\.b,p0/z,z0\.b'
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
@ -1555,13 +1532,7 @@
[^ :]+:[0-9]+: Info: sqneg z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sqneg z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: sqneg z0\.d, p0/m, z0\.d
[^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/z,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sqneg z0\.b, p0/m, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sqneg z0\.h, p0/m, z0\.h
[^ :]+:[0-9]+: Info: sqneg z0\.s, p0/m, z0\.s
[^ :]+:[0-9]+: Info: sqneg z0\.d, p0/m, z0\.d
[^ :]+:[0-9]+: Error: selected processor does not support `sqneg z0\.b,p0/z,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z8\.h\[0\],#0'

View file

@ -0,0 +1,57 @@
#as: -march=armv8-a+sme2p2
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <\.text>:
*[0-9a-f]+: c160e800 fmul {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h
*[0-9a-f]+: c160e81e fmul {z30\.h-z31\.h}, {z0\.h-z1\.h}, z0\.h
*[0-9a-f]+: c160ebc0 fmul {z0\.h-z1\.h}, {z30\.h-z31\.h}, z0\.h
*[0-9a-f]+: c17ee800 fmul {z0\.h-z1\.h}, {z0\.h-z1\.h}, z15\.h
*[0-9a-f]+: c1a0e800 fmul {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s
*[0-9a-f]+: c1a0e81e fmul {z30\.s-z31\.s}, {z0\.s-z1\.s}, z0\.s
*[0-9a-f]+: c1a0ebc0 fmul {z0\.s-z1\.s}, {z30\.s-z31\.s}, z0\.s
*[0-9a-f]+: c1bee800 fmul {z0\.s-z1\.s}, {z0\.s-z1\.s}, z15\.s
*[0-9a-f]+: c1e0e800 fmul {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d
*[0-9a-f]+: c1e0e81e fmul {z30\.d-z31\.d}, {z0\.d-z1\.d}, z0\.d
*[0-9a-f]+: c1e0ebc0 fmul {z0\.d-z1\.d}, {z30\.d-z31\.d}, z0\.d
*[0-9a-f]+: c1fee800 fmul {z0\.d-z1\.d}, {z0\.d-z1\.d}, z15\.d
*[0-9a-f]+: c161e800 fmul {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h
*[0-9a-f]+: c161e81c fmul {z28\.h-z31\.h}, {z0\.h-z3\.h}, z0\.h
*[0-9a-f]+: c161eb80 fmul {z0\.h-z3\.h}, {z28\.h-z31\.h}, z0\.h
*[0-9a-f]+: c17fe800 fmul {z0\.h-z3\.h}, {z0\.h-z3\.h}, z15\.h
*[0-9a-f]+: c1a1e800 fmul {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s
*[0-9a-f]+: c1a1e81c fmul {z28\.s-z31\.s}, {z0\.s-z3\.s}, z0\.s
*[0-9a-f]+: c1a1eb80 fmul {z0\.s-z3\.s}, {z28\.s-z31\.s}, z0\.s
*[0-9a-f]+: c1bfe800 fmul {z0\.s-z3\.s}, {z0\.s-z3\.s}, z15\.s
*[0-9a-f]+: c1e1e800 fmul {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d
*[0-9a-f]+: c1e1e81c fmul {z28\.d-z31\.d}, {z0\.d-z3\.d}, z0\.d
*[0-9a-f]+: c1e1eb80 fmul {z0\.d-z3\.d}, {z28\.d-z31\.d}, z0\.d
*[0-9a-f]+: c1ffe800 fmul {z0\.d-z3\.d}, {z0\.d-z3\.d}, z15\.d
*[0-9a-f]+: c160e400 fmul {z0\.h-z1\.h}, {z0\.h-z1\.h}, {z0\.h-z1\.h}
*[0-9a-f]+: c160e41e fmul {z30\.h-z31\.h}, {z0\.h-z1\.h}, {z0\.h-z1\.h}
*[0-9a-f]+: c160e7c0 fmul {z0\.h-z1\.h}, {z30\.h-z31\.h}, {z0\.h-z1\.h}
*[0-9a-f]+: c17ee400 fmul {z0\.h-z1\.h}, {z0\.h-z1\.h}, {z30\.h-z31\.h}
*[0-9a-f]+: c1a0e400 fmul {z0\.s-z1\.s}, {z0\.s-z1\.s}, {z0\.s-z1\.s}
*[0-9a-f]+: c1a0e41e fmul {z30\.s-z31\.s}, {z0\.s-z1\.s}, {z0\.s-z1\.s}
*[0-9a-f]+: c1a0e7c0 fmul {z0\.s-z1\.s}, {z30\.s-z31\.s}, {z0\.s-z1\.s}
*[0-9a-f]+: c1bee400 fmul {z0\.s-z1\.s}, {z0\.s-z1\.s}, {z30\.s-z31\.s}
*[0-9a-f]+: c1e0e400 fmul {z0\.d-z1\.d}, {z0\.d-z1\.d}, {z0\.d-z1\.d}
*[0-9a-f]+: c1e0e41e fmul {z30\.d-z31\.d}, {z0\.d-z1\.d}, {z0\.d-z1\.d}
*[0-9a-f]+: c1e0e7c0 fmul {z0\.d-z1\.d}, {z30\.d-z31\.d}, {z0\.d-z1\.d}
*[0-9a-f]+: c1fee400 fmul {z0\.d-z1\.d}, {z0\.d-z1\.d}, {z30\.d-z31\.d}
*[0-9a-f]+: c161e400 fmul {z0\.h-z3\.h}, {z0\.h-z3\.h}, {z0\.h-z3\.h}
*[0-9a-f]+: c161e41c fmul {z28\.h-z31\.h}, {z0\.h-z3\.h}, {z0\.h-z3\.h}
*[0-9a-f]+: c161e780 fmul {z0\.h-z3\.h}, {z28\.h-z31\.h}, {z0\.h-z3\.h}
*[0-9a-f]+: c17de400 fmul {z0\.h-z3\.h}, {z0\.h-z3\.h}, {z28\.h-z31\.h}
*[0-9a-f]+: c1a1e400 fmul {z0\.s-z3\.s}, {z0\.s-z3\.s}, {z0\.s-z3\.s}
*[0-9a-f]+: c1a1e41c fmul {z28\.s-z31\.s}, {z0\.s-z3\.s}, {z0\.s-z3\.s}
*[0-9a-f]+: c1a1e780 fmul {z0\.s-z3\.s}, {z28\.s-z31\.s}, {z0\.s-z3\.s}
*[0-9a-f]+: c1bde400 fmul {z0\.s-z3\.s}, {z0\.s-z3\.s}, {z28\.s-z31\.s}
*[0-9a-f]+: c1e1e400 fmul {z0\.d-z3\.d}, {z0\.d-z3\.d}, {z0\.d-z3\.d}
*[0-9a-f]+: c1e1e41c fmul {z28\.d-z31\.d}, {z0\.d-z3\.d}, {z0\.d-z3\.d}
*[0-9a-f]+: c1e1e780 fmul {z0\.d-z3\.d}, {z28\.d-z31\.d}, {z0\.d-z3\.d}
*[0-9a-f]+: c1fde400 fmul {z0\.d-z3\.d}, {z0\.d-z3\.d}, {z28\.d-z31\.d}

View file

@ -0,0 +1,50 @@
fmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h
fmul {z30.h-z31.h}, {z0.h-z1.h}, z0.h
fmul {z0.h-z1.h}, {z30.h-z31.h}, z0.h
fmul {z0.h-z1.h}, {z0.h-z1.h}, z15.h
fmul {z0.s-z1.s}, {z0.s-z1.s}, z0.s
fmul {z30.s-z31.s}, {z0.s-z1.s}, z0.s
fmul {z0.s-z1.s}, {z30.s-z31.s}, z0.s
fmul {z0.s-z1.s}, {z0.s-z1.s}, z15.s
fmul {z0.d-z1.d}, {z0.d-z1.d}, z0.d
fmul {z30.d-z31.d}, {z0.d-z1.d}, z0.d
fmul {z0.d-z1.d}, {z30.d-z31.d}, z0.d
fmul {z0.d-z1.d}, {z0.d-z1.d}, z15.d
fmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h
fmul {z28.h-z31.h}, {z0.h-z3.h}, z0.h
fmul {z0.h-z3.h}, {z28.h-z31.h}, z0.h
fmul {z0.h-z3.h}, {z0.h-z3.h}, z15.h
fmul {z0.s-z3.s}, {z0.s-z3.s}, z0.s
fmul {z28.s-z31.s}, {z0.s-z3.s}, z0.s
fmul {z0.s-z3.s}, {z28.s-z31.s}, z0.s
fmul {z0.s-z3.s}, {z0.s-z3.s}, z15.s
fmul {z0.d-z3.d}, {z0.d-z3.d}, z0.d
fmul {z28.d-z31.d}, {z0.d-z3.d}, z0.d
fmul {z0.d-z3.d}, {z28.d-z31.d}, z0.d
fmul {z0.d-z3.d}, {z0.d-z3.d}, z15.d
fmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
fmul {z30.h-z31.h}, {z0.h-z1.h}, {z0.h-z1.h}
fmul {z0.h-z1.h}, {z30.h-z31.h}, {z0.h-z1.h}
fmul {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
fmul {z0.s-z1.s}, {z0.s-z1.s}, {z0.s-z1.s}
fmul {z30.s-z31.s}, {z0.s-z1.s}, {z0.s-z1.s}
fmul {z0.s-z1.s}, {z30.s-z31.s}, {z0.s-z1.s}
fmul {z0.s-z1.s}, {z0.s-z1.s}, {z30.s-z31.s}
fmul {z0.d-z1.d}, {z0.d-z1.d}, {z0.d-z1.d}
fmul {z30.d-z31.d}, {z0.d-z1.d}, {z0.d-z1.d}
fmul {z0.d-z1.d}, {z30.d-z31.d}, {z0.d-z1.d}
fmul {z0.d-z1.d}, {z0.d-z1.d}, {z30.d-z31.d}
fmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
fmul {z28.h-z31.h}, {z0.h-z3.h}, {z0.h-z3.h}
fmul {z0.h-z3.h}, {z28.h-z31.h}, {z0.h-z3.h}
fmul {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
fmul {z0.s-z3.s}, {z0.s-z3.s}, {z0.s-z3.s}
fmul {z28.s-z31.s}, {z0.s-z3.s}, {z0.s-z3.s}
fmul {z0.s-z3.s}, {z28.s-z31.s}, {z0.s-z3.s}
fmul {z0.s-z3.s}, {z0.s-z3.s}, {z28.s-z31.s}
fmul {z0.d-z3.d}, {z0.d-z3.d}, {z0.d-z3.d}
fmul {z28.d-z31.d}, {z0.d-z3.d}, {z0.d-z3.d}
fmul {z0.d-z3.d}, {z28.d-z31.d}, {z0.d-z3.d}
fmul {z0.d-z3.d}, {z0.d-z3.d}, {z28.d-z31.d}

View file

@ -0,0 +1,694 @@
#as: -march=armv8-a+sve2p2
#as: -march=armv8-a+sme2p2
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <\.text>:
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*[0-9a-f]+: 0406a01f abs z31\.b, p0/z, z0\.b
*[0-9a-f]+: 0406bc00 abs z0\.b, p7/z, z0\.b
*[0-9a-f]+: 0406a3e0 abs z0\.b, p0/z, z31\.b
*[0-9a-f]+: 0446a000 abs z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0446a01f abs z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0446bc00 abs z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0446a3e0 abs z0\.h, p0/z, z31\.h
*[0-9a-f]+: 0486a000 abs z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0486a01f abs z31\.s, p0/z, z0\.s
*[0-9a-f]+: 0486bc00 abs z0\.s, p7/z, z0\.s
*[0-9a-f]+: 0486a3e0 abs z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04c6a000 abs z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c6a01f abs z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c6bc00 abs z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c6a3e0 abs z0\.d, p0/z, z31\.d
*[0-9a-f]+: 649ac000 bfcvt z0\.h, p0/z, z0\.s
*[0-9a-f]+: 649ac01f bfcvt z31\.h, p0/z, z0\.s
*[0-9a-f]+: 649adc00 bfcvt z0\.h, p7/z, z0\.s
*[0-9a-f]+: 649ac3e0 bfcvt z0\.h, p0/z, z31\.s
*[0-9a-f]+: 6482a000 bfcvtnt z0\.h, p0/z, z0\.s
*[0-9a-f]+: 6482a01f bfcvtnt z31\.h, p0/z, z0\.s
*[0-9a-f]+: 6482bc00 bfcvtnt z0\.h, p7/z, z0\.s
*[0-9a-f]+: 6482a3e0 bfcvtnt z0\.h, p0/z, z31\.s
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*[0-9a-f]+: 0408a01f cls z31\.b, p0/z, z0\.b
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*[0-9a-f]+: 0408a3e0 cls z0\.b, p0/z, z31\.b
*[0-9a-f]+: 0448a000 cls z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0448a01f cls z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0448bc00 cls z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0448a3e0 cls z0\.h, p0/z, z31\.h
*[0-9a-f]+: 0488a000 cls z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0488a01f cls z31\.s, p0/z, z0\.s
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*[0-9a-f]+: 0409a3e0 clz z0\.b, p0/z, z31\.b
*[0-9a-f]+: 0449a000 clz z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0449a01f clz z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0449bc00 clz z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0449a3e0 clz z0\.h, p0/z, z31\.h
*[0-9a-f]+: 0489a000 clz z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0489a01f clz z31\.s, p0/z, z0\.s
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*[0-9a-f]+: 0489a3e0 clz z0\.s, p0/z, z31\.s
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*[0-9a-f]+: 04c9bc00 clz z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c9a3e0 clz z0\.d, p0/z, z31\.d
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*[0-9a-f]+: 040ba01f cnot z31\.b, p0/z, z0\.b
*[0-9a-f]+: 040bbc00 cnot z0\.b, p7/z, z0\.b
*[0-9a-f]+: 040ba3e0 cnot z0\.b, p0/z, z31\.b
*[0-9a-f]+: 044ba000 cnot z0\.h, p0/z, z0\.h
*[0-9a-f]+: 044ba01f cnot z31\.h, p0/z, z0\.h
*[0-9a-f]+: 044bbc00 cnot z0\.h, p7/z, z0\.h
*[0-9a-f]+: 044ba3e0 cnot z0\.h, p0/z, z31\.h
*[0-9a-f]+: 048ba000 cnot z0\.s, p0/z, z0\.s
*[0-9a-f]+: 048ba01f cnot z31\.s, p0/z, z0\.s
*[0-9a-f]+: 048bbc00 cnot z0\.s, p7/z, z0\.s
*[0-9a-f]+: 048ba3e0 cnot z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04cba000 cnot z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04cba01f cnot z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04cbbc00 cnot z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04cba3e0 cnot z0\.d, p0/z, z31\.d
*[0-9a-f]+: 040aa000 cnt z0\.b, p0/z, z0\.b
*[0-9a-f]+: 040aa01f cnt z31\.b, p0/z, z0\.b
*[0-9a-f]+: 040abc00 cnt z0\.b, p7/z, z0\.b
*[0-9a-f]+: 040aa3e0 cnt z0\.b, p0/z, z31\.b
*[0-9a-f]+: 044aa000 cnt z0\.h, p0/z, z0\.h
*[0-9a-f]+: 044aa01f cnt z31\.h, p0/z, z0\.h
*[0-9a-f]+: 044abc00 cnt z0\.h, p7/z, z0\.h
*[0-9a-f]+: 044aa3e0 cnt z0\.h, p0/z, z31\.h
*[0-9a-f]+: 048aa000 cnt z0\.s, p0/z, z0\.s
*[0-9a-f]+: 048aa01f cnt z31\.s, p0/z, z0\.s
*[0-9a-f]+: 048abc00 cnt z0\.s, p7/z, z0\.s
*[0-9a-f]+: 048aa3e0 cnt z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04caa000 cnt z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04caa01f cnt z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04cabc00 cnt z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04caa3e0 cnt z0\.d, p0/z, z31\.d
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*[0-9a-f]+: 0521801f compact z31\.b, p0, z0\.b
*[0-9a-f]+: 05219c00 compact z0\.b, p7, z0\.b
*[0-9a-f]+: 052183e0 compact z0\.b, p0, z31\.b
*[0-9a-f]+: 05618000 compact z0\.h, p0, z0\.h
*[0-9a-f]+: 0561801f compact z31\.h, p0, z0\.h
*[0-9a-f]+: 05619c00 compact z0\.h, p7, z0\.h
*[0-9a-f]+: 056183e0 compact z0\.h, p0, z31\.h
*[0-9a-f]+: 05a18000 compact z0\.s, p0, z0\.s
*[0-9a-f]+: 05a1801f compact z31\.s, p0, z0\.s
*[0-9a-f]+: 05a19c00 compact z0\.s, p7, z0\.s
*[0-9a-f]+: 05a183e0 compact z0\.s, p0, z31\.s
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*[0-9a-f]+: 05719c00 expand z0\.h, p7, z0\.h
*[0-9a-f]+: 057183e0 expand z0\.h, p0, z31\.h
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*[0-9a-f]+: 05b1801f expand z31\.s, p0, z0\.s
*[0-9a-f]+: 05b19c00 expand z0\.s, p7, z0\.s
*[0-9a-f]+: 05b183e0 expand z0\.s, p0, z31\.s
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*[0-9a-f]+: 05f1801f expand z31\.d, p0, z0\.d
*[0-9a-f]+: 05f19c00 expand z0\.d, p7, z0\.d
*[0-9a-f]+: 05f183e0 expand z0\.d, p0, z31\.d
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*[0-9a-f]+: 25a281e0 lastp x0, p0, p15\.s
*[0-9a-f]+: 25e28000 lastp x0, p0, p0\.d
*[0-9a-f]+: 25e2801f lastp xzr, p0, p0\.d
*[0-9a-f]+: 25e2bc00 lastp x0, p15, p0\.d
*[0-9a-f]+: 25e281e0 lastp x0, p0, p15\.d
*[0-9a-f]+: 0407a000 neg z0\.b, p0/z, z0\.b
*[0-9a-f]+: 0407a01f neg z31\.b, p0/z, z0\.b
*[0-9a-f]+: 0407bc00 neg z0\.b, p7/z, z0\.b
*[0-9a-f]+: 0407a3e0 neg z0\.b, p0/z, z31\.b
*[0-9a-f]+: 0447a000 neg z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0447a01f neg z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0447bc00 neg z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0447a3e0 neg z0\.h, p0/z, z31\.h
*[0-9a-f]+: 0487a000 neg z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0487a01f neg z31\.s, p0/z, z0\.s
*[0-9a-f]+: 0487bc00 neg z0\.s, p7/z, z0\.s
*[0-9a-f]+: 0487a3e0 neg z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04c7a000 neg z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c7a01f neg z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c7bc00 neg z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c7a3e0 neg z0\.d, p0/z, z31\.d
*[0-9a-f]+: 040ea000 not z0\.b, p0/z, z0\.b
*[0-9a-f]+: 040ea01f not z31\.b, p0/z, z0\.b
*[0-9a-f]+: 040ebc00 not z0\.b, p7/z, z0\.b
*[0-9a-f]+: 040ea3e0 not z0\.b, p0/z, z31\.b
*[0-9a-f]+: 044ea000 not z0\.h, p0/z, z0\.h
*[0-9a-f]+: 044ea01f not z31\.h, p0/z, z0\.h
*[0-9a-f]+: 044ebc00 not z0\.h, p7/z, z0\.h
*[0-9a-f]+: 044ea3e0 not z0\.h, p0/z, z31\.h
*[0-9a-f]+: 048ea000 not z0\.s, p0/z, z0\.s
*[0-9a-f]+: 048ea01f not z31\.s, p0/z, z0\.s
*[0-9a-f]+: 048ebc00 not z0\.s, p7/z, z0\.s
*[0-9a-f]+: 048ea3e0 not z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04cea000 not z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04cea01f not z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04cebc00 not z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04cea3e0 not z0\.d, p0/z, z31\.d
*[0-9a-f]+: 0527a000 rbit z0\.b, p0/z, z0\.b
*[0-9a-f]+: 0527a01f rbit z31\.b, p0/z, z0\.b
*[0-9a-f]+: 0527bc00 rbit z0\.b, p7/z, z0\.b
*[0-9a-f]+: 0527a3e0 rbit z0\.b, p0/z, z31\.b
*[0-9a-f]+: 0567a000 rbit z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0567a01f rbit z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0567bc00 rbit z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0567a3e0 rbit z0\.h, p0/z, z31\.h
*[0-9a-f]+: 05a7a000 rbit z0\.s, p0/z, z0\.s
*[0-9a-f]+: 05a7a01f rbit z31\.s, p0/z, z0\.s
*[0-9a-f]+: 05a7bc00 rbit z0\.s, p7/z, z0\.s
*[0-9a-f]+: 05a7a3e0 rbit z0\.s, p0/z, z31\.s
*[0-9a-f]+: 05e7a000 rbit z0\.d, p0/z, z0\.d
*[0-9a-f]+: 05e7a01f rbit z31\.d, p0/z, z0\.d
*[0-9a-f]+: 05e7bc00 rbit z0\.d, p7/z, z0\.d
*[0-9a-f]+: 05e7a3e0 rbit z0\.d, p0/z, z31\.d
*[0-9a-f]+: 0564a000 revb z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0564a01f revb z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0564bc00 revb z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0564a3e0 revb z0\.h, p0/z, z31\.h
*[0-9a-f]+: 05a4a000 revb z0\.s, p0/z, z0\.s
*[0-9a-f]+: 05a4a01f revb z31\.s, p0/z, z0\.s
*[0-9a-f]+: 05a4bc00 revb z0\.s, p7/z, z0\.s
*[0-9a-f]+: 05a4a3e0 revb z0\.s, p0/z, z31\.s
*[0-9a-f]+: 05e4a000 revb z0\.d, p0/z, z0\.d
*[0-9a-f]+: 05e4a01f revb z31\.d, p0/z, z0\.d
*[0-9a-f]+: 05e4bc00 revb z0\.d, p7/z, z0\.d
*[0-9a-f]+: 05e4a3e0 revb z0\.d, p0/z, z31\.d
*[0-9a-f]+: 05a5a000 revh z0\.s, p0/z, z0\.s
*[0-9a-f]+: 05a5a01f revh z31\.s, p0/z, z0\.s
*[0-9a-f]+: 05a5bc00 revh z0\.s, p7/z, z0\.s
*[0-9a-f]+: 05a5a3e0 revh z0\.s, p0/z, z31\.s
*[0-9a-f]+: 05e5a000 revh z0\.d, p0/z, z0\.d
*[0-9a-f]+: 05e5a01f revh z31\.d, p0/z, z0\.d
*[0-9a-f]+: 05e5bc00 revh z0\.d, p7/z, z0\.d
*[0-9a-f]+: 05e5a3e0 revh z0\.d, p0/z, z31\.d
*[0-9a-f]+: 05e6a000 revw z0\.d, p0/z, z0\.d
*[0-9a-f]+: 05e6a01f revw z31\.d, p0/z, z0\.d
*[0-9a-f]+: 05e6bc00 revw z0\.d, p7/z, z0\.d
*[0-9a-f]+: 05e6a3e0 revw z0\.d, p0/z, z31\.d
*[0-9a-f]+: 052ea000 revd z0\.q, p0/z, z0\.q
*[0-9a-f]+: 052ea01f revd z31\.q, p0/z, z0\.q
*[0-9a-f]+: 052ebc00 revd z0\.q, p7/z, z0\.q
*[0-9a-f]+: 052ea3e0 revd z0\.q, p0/z, z31\.q
*[0-9a-f]+: 645cc000 scvtf z0\.h, p0/z, z0\.h
*[0-9a-f]+: 645cc01f scvtf z31\.h, p0/z, z0\.h
*[0-9a-f]+: 645cdc00 scvtf z0\.h, p7/z, z0\.h
*[0-9a-f]+: 645cc3e0 scvtf z0\.h, p0/z, z31\.h
*[0-9a-f]+: 645d8000 scvtf z0\.h, p0/z, z0\.s
*[0-9a-f]+: 645d801f scvtf z31\.h, p0/z, z0\.s
*[0-9a-f]+: 645d9c00 scvtf z0\.h, p7/z, z0\.s
*[0-9a-f]+: 645d83e0 scvtf z0\.h, p0/z, z31\.s
*[0-9a-f]+: 649d8000 scvtf z0\.s, p0/z, z0\.s
*[0-9a-f]+: 649d801f scvtf z31\.s, p0/z, z0\.s
*[0-9a-f]+: 649d9c00 scvtf z0\.s, p7/z, z0\.s
*[0-9a-f]+: 649d83e0 scvtf z0\.s, p0/z, z31\.s
*[0-9a-f]+: 64dc8000 scvtf z0\.d, p0/z, z0\.s
*[0-9a-f]+: 64dc801f scvtf z31\.d, p0/z, z0\.s
*[0-9a-f]+: 64dc9c00 scvtf z0\.d, p7/z, z0\.s
*[0-9a-f]+: 64dc83e0 scvtf z0\.d, p0/z, z31\.s
*[0-9a-f]+: 645dc000 scvtf z0\.h, p0/z, z0\.d
*[0-9a-f]+: 645dc01f scvtf z31\.h, p0/z, z0\.d
*[0-9a-f]+: 645ddc00 scvtf z0\.h, p7/z, z0\.d
*[0-9a-f]+: 645dc3e0 scvtf z0\.h, p0/z, z31\.d
*[0-9a-f]+: 64dd8000 scvtf z0\.s, p0/z, z0\.d
*[0-9a-f]+: 64dd801f scvtf z31\.s, p0/z, z0\.d
*[0-9a-f]+: 64dd9c00 scvtf z0\.s, p7/z, z0\.d
*[0-9a-f]+: 64dd83e0 scvtf z0\.s, p0/z, z31\.d
*[0-9a-f]+: 64ddc000 scvtf z0\.d, p0/z, z0\.d
*[0-9a-f]+: 64ddc01f scvtf z31\.d, p0/z, z0\.d
*[0-9a-f]+: 64dddc00 scvtf z0\.d, p7/z, z0\.d
*[0-9a-f]+: 64ddc3e0 scvtf z0\.d, p0/z, z31\.d
*[0-9a-f]+: 440aa000 sqabs z0\.b, p0/z, z0\.b
*[0-9a-f]+: 440aa01f sqabs z31\.b, p0/z, z0\.b
*[0-9a-f]+: 440abc00 sqabs z0\.b, p7/z, z0\.b
*[0-9a-f]+: 440aa3e0 sqabs z0\.b, p0/z, z31\.b
*[0-9a-f]+: 444aa000 sqabs z0\.h, p0/z, z0\.h
*[0-9a-f]+: 444aa01f sqabs z31\.h, p0/z, z0\.h
*[0-9a-f]+: 444abc00 sqabs z0\.h, p7/z, z0\.h
*[0-9a-f]+: 444aa3e0 sqabs z0\.h, p0/z, z31\.h
*[0-9a-f]+: 448aa000 sqabs z0\.s, p0/z, z0\.s
*[0-9a-f]+: 448aa01f sqabs z31\.s, p0/z, z0\.s
*[0-9a-f]+: 448abc00 sqabs z0\.s, p7/z, z0\.s
*[0-9a-f]+: 448aa3e0 sqabs z0\.s, p0/z, z31\.s
*[0-9a-f]+: 44caa000 sqabs z0\.d, p0/z, z0\.d
*[0-9a-f]+: 44caa01f sqabs z31\.d, p0/z, z0\.d
*[0-9a-f]+: 44cabc00 sqabs z0\.d, p7/z, z0\.d
*[0-9a-f]+: 44caa3e0 sqabs z0\.d, p0/z, z31\.d
*[0-9a-f]+: 440ba000 sqneg z0\.b, p0/z, z0\.b
*[0-9a-f]+: 440ba01f sqneg z31\.b, p0/z, z0\.b
*[0-9a-f]+: 440bbc00 sqneg z0\.b, p7/z, z0\.b
*[0-9a-f]+: 440ba3e0 sqneg z0\.b, p0/z, z31\.b
*[0-9a-f]+: 444ba000 sqneg z0\.h, p0/z, z0\.h
*[0-9a-f]+: 444ba01f sqneg z31\.h, p0/z, z0\.h
*[0-9a-f]+: 444bbc00 sqneg z0\.h, p7/z, z0\.h
*[0-9a-f]+: 444ba3e0 sqneg z0\.h, p0/z, z31\.h
*[0-9a-f]+: 448ba000 sqneg z0\.s, p0/z, z0\.s
*[0-9a-f]+: 448ba01f sqneg z31\.s, p0/z, z0\.s
*[0-9a-f]+: 448bbc00 sqneg z0\.s, p7/z, z0\.s
*[0-9a-f]+: 448ba3e0 sqneg z0\.s, p0/z, z31\.s
*[0-9a-f]+: 44cba000 sqneg z0\.d, p0/z, z0\.d
*[0-9a-f]+: 44cba01f sqneg z31\.d, p0/z, z0\.d
*[0-9a-f]+: 44cbbc00 sqneg z0\.d, p7/z, z0\.d
*[0-9a-f]+: 44cba3e0 sqneg z0\.d, p0/z, z31\.d
*[0-9a-f]+: 0440a000 sxtb z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0440a01f sxtb z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0440bc00 sxtb z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0440a3e0 sxtb z0\.h, p0/z, z31\.h
*[0-9a-f]+: 0480a000 sxtb z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0480a01f sxtb z31\.s, p0/z, z0\.s
*[0-9a-f]+: 0480bc00 sxtb z0\.s, p7/z, z0\.s
*[0-9a-f]+: 0480a3e0 sxtb z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04c0a000 sxtb z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c0a01f sxtb z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c0bc00 sxtb z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c0a3e0 sxtb z0\.d, p0/z, z31\.d
*[0-9a-f]+: 0482a000 sxth z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0482a01f sxth z31\.s, p0/z, z0\.s
*[0-9a-f]+: 0482bc00 sxth z0\.s, p7/z, z0\.s
*[0-9a-f]+: 0482a3e0 sxth z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04c2a000 sxth z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c2a01f sxth z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c2bc00 sxth z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c2a3e0 sxth z0\.d, p0/z, z31\.d
*[0-9a-f]+: 04c4a000 sxtw z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c4a01f sxtw z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c4bc00 sxtw z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c4a3e0 sxtw z0\.d, p0/z, z31\.d
*[0-9a-f]+: 645ce000 ucvtf z0\.h, p0/z, z0\.h
*[0-9a-f]+: 645ce01f ucvtf z31\.h, p0/z, z0\.h
*[0-9a-f]+: 645cfc00 ucvtf z0\.h, p7/z, z0\.h
*[0-9a-f]+: 645ce3e0 ucvtf z0\.h, p0/z, z31\.h
*[0-9a-f]+: 645da000 ucvtf z0\.h, p0/z, z0\.s
*[0-9a-f]+: 645da01f ucvtf z31\.h, p0/z, z0\.s
*[0-9a-f]+: 645dbc00 ucvtf z0\.h, p7/z, z0\.s
*[0-9a-f]+: 645da3e0 ucvtf z0\.h, p0/z, z31\.s
*[0-9a-f]+: 649da000 ucvtf z0\.s, p0/z, z0\.s
*[0-9a-f]+: 649da01f ucvtf z31\.s, p0/z, z0\.s
*[0-9a-f]+: 649dbc00 ucvtf z0\.s, p7/z, z0\.s
*[0-9a-f]+: 649da3e0 ucvtf z0\.s, p0/z, z31\.s
*[0-9a-f]+: 64dca000 ucvtf z0\.d, p0/z, z0\.s
*[0-9a-f]+: 64dca01f ucvtf z31\.d, p0/z, z0\.s
*[0-9a-f]+: 64dcbc00 ucvtf z0\.d, p7/z, z0\.s
*[0-9a-f]+: 64dca3e0 ucvtf z0\.d, p0/z, z31\.s
*[0-9a-f]+: 645de000 ucvtf z0\.h, p0/z, z0\.d
*[0-9a-f]+: 645de01f ucvtf z31\.h, p0/z, z0\.d
*[0-9a-f]+: 645dfc00 ucvtf z0\.h, p7/z, z0\.d
*[0-9a-f]+: 645de3e0 ucvtf z0\.h, p0/z, z31\.d
*[0-9a-f]+: 64dda000 ucvtf z0\.s, p0/z, z0\.d
*[0-9a-f]+: 64dda01f ucvtf z31\.s, p0/z, z0\.d
*[0-9a-f]+: 64ddbc00 ucvtf z0\.s, p7/z, z0\.d
*[0-9a-f]+: 64dda3e0 ucvtf z0\.s, p0/z, z31\.d
*[0-9a-f]+: 64dde000 ucvtf z0\.d, p0/z, z0\.d
*[0-9a-f]+: 64dde01f ucvtf z31\.d, p0/z, z0\.d
*[0-9a-f]+: 64ddfc00 ucvtf z0\.d, p7/z, z0\.d
*[0-9a-f]+: 64dde3e0 ucvtf z0\.d, p0/z, z31\.d
*[0-9a-f]+: 4482a000 urecpe z0\.s, p0/z, z0\.s
*[0-9a-f]+: 4482a01f urecpe z31\.s, p0/z, z0\.s
*[0-9a-f]+: 4482bc00 urecpe z0\.s, p7/z, z0\.s
*[0-9a-f]+: 4482a3e0 urecpe z0\.s, p0/z, z31\.s
*[0-9a-f]+: 4483a000 ursqrte z0\.s, p0/z, z0\.s
*[0-9a-f]+: 4483a01f ursqrte z31\.s, p0/z, z0\.s
*[0-9a-f]+: 4483bc00 ursqrte z0\.s, p7/z, z0\.s
*[0-9a-f]+: 4483a3e0 ursqrte z0\.s, p0/z, z31\.s
*[0-9a-f]+: 0441a000 uxtb z0\.h, p0/z, z0\.h
*[0-9a-f]+: 0441a01f uxtb z31\.h, p0/z, z0\.h
*[0-9a-f]+: 0441bc00 uxtb z0\.h, p7/z, z0\.h
*[0-9a-f]+: 0441a3e0 uxtb z0\.h, p0/z, z31\.h
*[0-9a-f]+: 0481a000 uxtb z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0481a01f uxtb z31\.s, p0/z, z0\.s
*[0-9a-f]+: 0481bc00 uxtb z0\.s, p7/z, z0\.s
*[0-9a-f]+: 0481a3e0 uxtb z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04c1a000 uxtb z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c1a01f uxtb z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c1bc00 uxtb z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c1a3e0 uxtb z0\.d, p0/z, z31\.d
*[0-9a-f]+: 0483a000 uxth z0\.s, p0/z, z0\.s
*[0-9a-f]+: 0483a01f uxth z31\.s, p0/z, z0\.s
*[0-9a-f]+: 0483bc00 uxth z0\.s, p7/z, z0\.s
*[0-9a-f]+: 0483a3e0 uxth z0\.s, p0/z, z31\.s
*[0-9a-f]+: 04c3a000 uxth z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c3a01f uxth z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c3bc00 uxth z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c3a3e0 uxth z0\.d, p0/z, z31\.d
*[0-9a-f]+: 04c5a000 uxtw z0\.d, p0/z, z0\.d
*[0-9a-f]+: 04c5a01f uxtw z31\.d, p0/z, z0\.d
*[0-9a-f]+: 04c5bc00 uxtw z0\.d, p7/z, z0\.d
*[0-9a-f]+: 04c5a3e0 uxtw z0\.d, p0/z, z31\.d

View file

@ -0,0 +1,738 @@
abs z0.b, p0/z, z0.b
abs z31.b, p0/z, z0.b
abs z0.b, p7/z, z0.b
abs z0.b, p0/z, z31.b
abs z0.h, p0/z, z0.h
abs z31.h, p0/z, z0.h
abs z0.h, p7/z, z0.h
abs z0.h, p0/z, z31.h
abs z0.s, p0/z, z0.s
abs z31.s, p0/z, z0.s
abs z0.s, p7/z, z0.s
abs z0.s, p0/z, z31.s
abs z0.d, p0/z, z0.d
abs z31.d, p0/z, z0.d
abs z0.d, p7/z, z0.d
abs z0.d, p0/z, z31.d
bfcvt z0.h, p0/z, z0.s
bfcvt z31.h, p0/z, z0.s
bfcvt z0.h, p7/z, z0.s
bfcvt z0.h, p0/z, z31.s
bfcvtnt z0.h, p0/z, z0.s
bfcvtnt z31.h, p0/z, z0.s
bfcvtnt z0.h, p7/z, z0.s
bfcvtnt z0.h, p0/z, z31.s
cls z0.b, p0/z, z0.b
cls z31.b, p0/z, z0.b
cls z0.b, p7/z, z0.b
cls z0.b, p0/z, z31.b
cls z0.h, p0/z, z0.h
cls z31.h, p0/z, z0.h
cls z0.h, p7/z, z0.h
cls z0.h, p0/z, z31.h
cls z0.s, p0/z, z0.s
cls z31.s, p0/z, z0.s
cls z0.s, p7/z, z0.s
cls z0.s, p0/z, z31.s
cls z0.d, p0/z, z0.d
cls z31.d, p0/z, z0.d
cls z0.d, p7/z, z0.d
cls z0.d, p0/z, z31.d
clz z0.b, p0/z, z0.b
clz z31.b, p0/z, z0.b
clz z0.b, p7/z, z0.b
clz z0.b, p0/z, z31.b
clz z0.h, p0/z, z0.h
clz z31.h, p0/z, z0.h
clz z0.h, p7/z, z0.h
clz z0.h, p0/z, z31.h
clz z0.s, p0/z, z0.s
clz z31.s, p0/z, z0.s
clz z0.s, p7/z, z0.s
clz z0.s, p0/z, z31.s
clz z0.d, p0/z, z0.d
clz z31.d, p0/z, z0.d
clz z0.d, p7/z, z0.d
clz z0.d, p0/z, z31.d
cnot z0.b, p0/z, z0.b
cnot z31.b, p0/z, z0.b
cnot z0.b, p7/z, z0.b
cnot z0.b, p0/z, z31.b
cnot z0.h, p0/z, z0.h
cnot z31.h, p0/z, z0.h
cnot z0.h, p7/z, z0.h
cnot z0.h, p0/z, z31.h
cnot z0.s, p0/z, z0.s
cnot z31.s, p0/z, z0.s
cnot z0.s, p7/z, z0.s
cnot z0.s, p0/z, z31.s
cnot z0.d, p0/z, z0.d
cnot z31.d, p0/z, z0.d
cnot z0.d, p7/z, z0.d
cnot z0.d, p0/z, z31.d
cnt z0.b, p0/z, z0.b
cnt z31.b, p0/z, z0.b
cnt z0.b, p7/z, z0.b
cnt z0.b, p0/z, z31.b
cnt z0.h, p0/z, z0.h
cnt z31.h, p0/z, z0.h
cnt z0.h, p7/z, z0.h
cnt z0.h, p0/z, z31.h
cnt z0.s, p0/z, z0.s
cnt z31.s, p0/z, z0.s
cnt z0.s, p7/z, z0.s
cnt z0.s, p0/z, z31.s
cnt z0.d, p0/z, z0.d
cnt z31.d, p0/z, z0.d
cnt z0.d, p7/z, z0.d
cnt z0.d, p0/z, z31.d
// Word and doubleword forms in nonstreaming mode are part of FEAT_SVE.
compact z0.b, p0, z0.b
compact z31.b, p0, z0.b
compact z0.b, p7, z0.b
compact z0.b, p0, z31.b
compact z0.h, p0, z0.h
compact z31.h, p0, z0.h
compact z0.h, p7, z0.h
compact z0.h, p0, z31.h
compact z0.s, p0, z0.s
compact z31.s, p0, z0.s
compact z0.s, p7, z0.s
compact z0.s, p0, z31.s
compact z0.d, p0, z0.d
compact z31.d, p0, z0.d
compact z0.d, p7, z0.d
compact z0.d, p0, z31.d
expand z0.b, p0, z0.b
expand z31.b, p0, z0.b
expand z0.b, p7, z0.b
expand z0.b, p0, z31.b
expand z0.h, p0, z0.h
expand z31.h, p0, z0.h
expand z0.h, p7, z0.h
expand z0.h, p0, z31.h
expand z0.s, p0, z0.s
expand z31.s, p0, z0.s
expand z0.s, p7, z0.s
expand z0.s, p0, z31.s
expand z0.d, p0, z0.d
expand z31.d, p0, z0.d
expand z0.d, p7, z0.d
expand z0.d, p0, z31.d
fabs z0.h, p0/z, z0.h
fabs z31.h, p0/z, z0.h
fabs z0.h, p7/z, z0.h
fabs z0.h, p0/z, z31.h
fabs z0.s, p0/z, z0.s
fabs z31.s, p0/z, z0.s
fabs z0.s, p7/z, z0.s
fabs z0.s, p0/z, z31.s
fabs z0.d, p0/z, z0.d
fabs z31.d, p0/z, z0.d
fabs z0.d, p7/z, z0.d
fabs z0.d, p0/z, z31.d
fcvt z0.s, p0/z, z0.h
fcvt z31.s, p0/z, z0.h
fcvt z0.s, p7/z, z0.h
fcvt z0.s, p0/z, z31.h
fcvt z0.d, p0/z, z0.h
fcvt z31.d, p0/z, z0.h
fcvt z0.d, p7/z, z0.h
fcvt z0.d, p0/z, z31.h
fcvt z0.h, p0/z, z0.s
fcvt z31.h, p0/z, z0.s
fcvt z0.h, p7/z, z0.s
fcvt z0.h, p0/z, z31.s
fcvt z0.d, p0/z, z0.s
fcvt z31.d, p0/z, z0.s
fcvt z0.d, p7/z, z0.s
fcvt z0.d, p0/z, z31.s
fcvt z0.h, p0/z, z0.d
fcvt z31.h, p0/z, z0.d
fcvt z0.h, p7/z, z0.d
fcvt z0.h, p0/z, z31.d
fcvt z0.s, p0/z, z0.d
fcvt z31.s, p0/z, z0.d
fcvt z0.s, p7/z, z0.d
fcvt z0.s, p0/z, z31.d
fcvtlt z0.s, p0/z, z0.h
fcvtlt z31.s, p0/z, z0.h
fcvtlt z0.s, p7/z, z0.h
fcvtlt z0.s, p0/z, z31.h
fcvtlt z0.d, p0/z, z0.s
fcvtlt z31.d, p0/z, z0.s
fcvtlt z0.d, p7/z, z0.s
fcvtlt z0.d, p0/z, z31.s
fcvtnt z0.h, p0/z, z0.s
fcvtnt z31.h, p0/z, z0.s
fcvtnt z0.h, p7/z, z0.s
fcvtnt z0.h, p0/z, z31.s
fcvtnt z0.s, p0/z, z0.d
fcvtnt z31.s, p0/z, z0.d
fcvtnt z0.s, p7/z, z0.d
fcvtnt z0.s, p0/z, z31.d
fcvtx z0.s, p0/z, z0.d
fcvtx z31.s, p0/z, z0.d
fcvtx z0.s, p7/z, z0.d
fcvtx z0.s, p0/z, z31.d
fcvtxnt z0.s, p0/z, z0.d
fcvtxnt z31.s, p0/z, z0.d
fcvtxnt z0.s, p7/z, z0.d
fcvtxnt z0.s, p0/z, z31.d
fcvtzs z0.h, p0/z, z0.h
fcvtzs z31.h, p0/z, z0.h
fcvtzs z0.h, p7/z, z0.h
fcvtzs z0.h, p0/z, z31.h
fcvtzs z0.s, p0/z, z0.h
fcvtzs z31.s, p0/z, z0.h
fcvtzs z0.s, p7/z, z0.h
fcvtzs z0.s, p0/z, z31.h
fcvtzs z0.d, p0/z, z0.h
fcvtzs z31.d, p0/z, z0.h
fcvtzs z0.d, p7/z, z0.h
fcvtzs z0.d, p0/z, z31.h
fcvtzs z0.s, p0/z, z0.s
fcvtzs z31.s, p0/z, z0.s
fcvtzs z0.s, p7/z, z0.s
fcvtzs z0.s, p0/z, z31.s
fcvtzs z0.d, p0/z, z0.s
fcvtzs z31.d, p0/z, z0.s
fcvtzs z0.d, p7/z, z0.s
fcvtzs z0.d, p0/z, z31.s
fcvtzs z0.s, p0/z, z0.d
fcvtzs z31.s, p0/z, z0.d
fcvtzs z0.s, p7/z, z0.d
fcvtzs z0.s, p0/z, z31.d
fcvtzs z0.d, p0/z, z0.d
fcvtzs z31.d, p0/z, z0.d
fcvtzs z0.d, p7/z, z0.d
fcvtzs z0.d, p0/z, z31.d
fcvtzu z0.h, p0/z, z0.h
fcvtzu z31.h, p0/z, z0.h
fcvtzu z0.h, p7/z, z0.h
fcvtzu z0.h, p0/z, z31.h
fcvtzu z0.s, p0/z, z0.h
fcvtzu z31.s, p0/z, z0.h
fcvtzu z0.s, p7/z, z0.h
fcvtzu z0.s, p0/z, z31.h
fcvtzu z0.d, p0/z, z0.h
fcvtzu z31.d, p0/z, z0.h
fcvtzu z0.d, p7/z, z0.h
fcvtzu z0.d, p0/z, z31.h
fcvtzu z0.s, p0/z, z0.s
fcvtzu z31.s, p0/z, z0.s
fcvtzu z0.s, p7/z, z0.s
fcvtzu z0.s, p0/z, z31.s
fcvtzu z0.d, p0/z, z0.s
fcvtzu z31.d, p0/z, z0.s
fcvtzu z0.d, p7/z, z0.s
fcvtzu z0.d, p0/z, z31.s
fcvtzu z0.s, p0/z, z0.d
fcvtzu z31.s, p0/z, z0.d
fcvtzu z0.s, p7/z, z0.d
fcvtzu z0.s, p0/z, z31.d
fcvtzu z0.d, p0/z, z0.d
fcvtzu z31.d, p0/z, z0.d
fcvtzu z0.d, p7/z, z0.d
fcvtzu z0.d, p0/z, z31.d
firstp x0, p0, p0.b
firstp xzr, p0, p0.b
firstp x0, p15, p0.b
firstp x0, p0, p15.b
firstp x0, p0, p0.h
firstp xzr, p0, p0.h
firstp x0, p15, p0.h
firstp x0, p0, p15.h
firstp x0, p0, p0.s
firstp xzr, p0, p0.s
firstp x0, p15, p0.s
firstp x0, p0, p15.s
firstp x0, p0, p0.d
firstp xzr, p0, p0.d
firstp x0, p15, p0.d
firstp x0, p0, p15.d
flogb z0.h, p0/z, z0.h
flogb z31.h, p0/z, z0.h
flogb z0.h, p7/z, z0.h
flogb z0.h, p0/z, z31.h
flogb z0.s, p0/z, z0.s
flogb z31.s, p0/z, z0.s
flogb z0.s, p7/z, z0.s
flogb z0.s, p0/z, z31.s
flogb z0.d, p0/z, z0.d
flogb z31.d, p0/z, z0.d
flogb z0.d, p7/z, z0.d
flogb z0.d, p0/z, z31.d
fneg z0.h, p0/z, z0.h
fneg z31.h, p0/z, z0.h
fneg z0.h, p7/z, z0.h
fneg z0.h, p0/z, z31.h
fneg z0.s, p0/z, z0.s
fneg z31.s, p0/z, z0.s
fneg z0.s, p7/z, z0.s
fneg z0.s, p0/z, z31.s
fneg z0.d, p0/z, z0.d
fneg z31.d, p0/z, z0.d
fneg z0.d, p7/z, z0.d
fneg z0.d, p0/z, z31.d
frecpx z0.h, p0/z, z0.h
frecpx z31.h, p0/z, z0.h
frecpx z0.h, p7/z, z0.h
frecpx z0.h, p0/z, z31.h
frecpx z0.s, p0/z, z0.s
frecpx z31.s, p0/z, z0.s
frecpx z0.s, p7/z, z0.s
frecpx z0.s, p0/z, z31.s
frecpx z0.d, p0/z, z0.d
frecpx z31.d, p0/z, z0.d
frecpx z0.d, p7/z, z0.d
frecpx z0.d, p0/z, z31.d
frint32x z0.s, p0/m, z0.s
frint32x z31.s, p0/m, z0.s
frint32x z0.s, p7/m, z0.s
frint32x z0.s, p0/m, z31.s
frint32x z0.d, p0/m, z0.d
frint32x z31.d, p0/m, z0.d
frint32x z0.d, p7/m, z0.d
frint32x z0.d, p0/m, z31.d
frint32x z0.s, p0/z, z0.s
frint32x z31.s, p0/z, z0.s
frint32x z0.s, p7/z, z0.s
frint32x z0.s, p0/z, z31.s
frint32x z0.d, p0/z, z0.d
frint32x z31.d, p0/z, z0.d
frint32x z0.d, p7/z, z0.d
frint32x z0.d, p0/z, z31.d
frint32z z0.s, p0/m, z0.s
frint32z z31.s, p0/m, z0.s
frint32z z0.s, p7/m, z0.s
frint32z z0.s, p0/m, z31.s
frint32z z0.d, p0/m, z0.d
frint32z z31.d, p0/m, z0.d
frint32z z0.d, p7/m, z0.d
frint32z z0.d, p0/m, z31.d
frint32z z0.s, p0/z, z0.s
frint32z z31.s, p0/z, z0.s
frint32z z0.s, p7/z, z0.s
frint32z z0.s, p0/z, z31.s
frint32z z0.d, p0/z, z0.d
frint32z z31.d, p0/z, z0.d
frint32z z0.d, p7/z, z0.d
frint32z z0.d, p0/z, z31.d
frint64x z0.s, p0/m, z0.s
frint64x z31.s, p0/m, z0.s
frint64x z0.s, p7/m, z0.s
frint64x z0.s, p0/m, z31.s
frint64x z0.d, p0/m, z0.d
frint64x z31.d, p0/m, z0.d
frint64x z0.d, p7/m, z0.d
frint64x z0.d, p0/m, z31.d
frint64x z0.s, p0/z, z0.s
frint64x z31.s, p0/z, z0.s
frint64x z0.s, p7/z, z0.s
frint64x z0.s, p0/z, z31.s
frint64x z0.d, p0/z, z0.d
frint64x z31.d, p0/z, z0.d
frint64x z0.d, p7/z, z0.d
frint64x z0.d, p0/z, z31.d
frint64z z0.s, p0/m, z0.s
frint64z z31.s, p0/m, z0.s
frint64z z0.s, p7/m, z0.s
frint64z z0.s, p0/m, z31.s
frint64z z0.d, p0/m, z0.d
frint64z z31.d, p0/m, z0.d
frint64z z0.d, p7/m, z0.d
frint64z z0.d, p0/m, z31.d
frint64z z0.s, p0/z, z0.s
frint64z z31.s, p0/z, z0.s
frint64z z0.s, p7/z, z0.s
frint64z z0.s, p0/z, z31.s
frint64z z0.d, p0/z, z0.d
frint64z z31.d, p0/z, z0.d
frint64z z0.d, p7/z, z0.d
frint64z z0.d, p0/z, z31.d
frintx z0.h, p0/z, z0.h
frintx z31.h, p0/z, z0.h
frintx z0.h, p7/z, z0.h
frintx z0.h, p0/z, z31.h
frintx z0.s, p0/z, z0.s
frintx z31.s, p0/z, z0.s
frintx z0.s, p7/z, z0.s
frintx z0.s, p0/z, z31.s
frintx z0.d, p0/z, z0.d
frintx z31.d, p0/z, z0.d
frintx z0.d, p7/z, z0.d
frintx z0.d, p0/z, z31.d
frinti z0.h, p0/z, z0.h
frinti z31.h, p0/z, z0.h
frinti z0.h, p7/z, z0.h
frinti z0.h, p0/z, z31.h
frinti z0.s, p0/z, z0.s
frinti z31.s, p0/z, z0.s
frinti z0.s, p7/z, z0.s
frinti z0.s, p0/z, z31.s
frinti z0.d, p0/z, z0.d
frinti z31.d, p0/z, z0.d
frinti z0.d, p7/z, z0.d
frinti z0.d, p0/z, z31.d
frinta z0.h, p0/z, z0.h
frinta z31.h, p0/z, z0.h
frinta z0.h, p7/z, z0.h
frinta z0.h, p0/z, z31.h
frinta z0.s, p0/z, z0.s
frinta z31.s, p0/z, z0.s
frinta z0.s, p7/z, z0.s
frinta z0.s, p0/z, z31.s
frinta z0.d, p0/z, z0.d
frinta z31.d, p0/z, z0.d
frinta z0.d, p7/z, z0.d
frinta z0.d, p0/z, z31.d
frintn z0.h, p0/z, z0.h
frintn z31.h, p0/z, z0.h
frintn z0.h, p7/z, z0.h
frintn z0.h, p0/z, z31.h
frintn z0.s, p0/z, z0.s
frintn z31.s, p0/z, z0.s
frintn z0.s, p7/z, z0.s
frintn z0.s, p0/z, z31.s
frintn z0.d, p0/z, z0.d
frintn z31.d, p0/z, z0.d
frintn z0.d, p7/z, z0.d
frintn z0.d, p0/z, z31.d
frintz z0.h, p0/z, z0.h
frintz z31.h, p0/z, z0.h
frintz z0.h, p7/z, z0.h
frintz z0.h, p0/z, z31.h
frintz z0.s, p0/z, z0.s
frintz z31.s, p0/z, z0.s
frintz z0.s, p7/z, z0.s
frintz z0.s, p0/z, z31.s
frintz z0.d, p0/z, z0.d
frintz z31.d, p0/z, z0.d
frintz z0.d, p7/z, z0.d
frintz z0.d, p0/z, z31.d
frintm z0.h, p0/z, z0.h
frintm z31.h, p0/z, z0.h
frintm z0.h, p7/z, z0.h
frintm z0.h, p0/z, z31.h
frintm z0.s, p0/z, z0.s
frintm z31.s, p0/z, z0.s
frintm z0.s, p7/z, z0.s
frintm z0.s, p0/z, z31.s
frintm z0.d, p0/z, z0.d
frintm z31.d, p0/z, z0.d
frintm z0.d, p7/z, z0.d
frintm z0.d, p0/z, z31.d
frintp z0.h, p0/z, z0.h
frintp z31.h, p0/z, z0.h
frintp z0.h, p7/z, z0.h
frintp z0.h, p0/z, z31.h
frintp z0.s, p0/z, z0.s
frintp z31.s, p0/z, z0.s
frintp z0.s, p7/z, z0.s
frintp z0.s, p0/z, z31.s
frintp z0.d, p0/z, z0.d
frintp z31.d, p0/z, z0.d
frintp z0.d, p7/z, z0.d
frintp z0.d, p0/z, z31.d
fsqrt z0.h, p0/z, z0.h
fsqrt z31.h, p0/z, z0.h
fsqrt z0.h, p7/z, z0.h
fsqrt z0.h, p0/z, z31.h
fsqrt z0.s, p0/z, z0.s
fsqrt z31.s, p0/z, z0.s
fsqrt z0.s, p7/z, z0.s
fsqrt z0.s, p0/z, z31.s
fsqrt z0.d, p0/z, z0.d
fsqrt z31.d, p0/z, z0.d
fsqrt z0.d, p7/z, z0.d
fsqrt z0.d, p0/z, z31.d
lastp x0, p0, p0.b
lastp xzr, p0, p0.b
lastp x0, p15, p0.b
lastp x0, p0, p15.b
lastp x0, p0, p0.h
lastp xzr, p0, p0.h
lastp x0, p15, p0.h
lastp x0, p0, p15.h
lastp x0, p0, p0.s
lastp xzr, p0, p0.s
lastp x0, p15, p0.s
lastp x0, p0, p15.s
lastp x0, p0, p0.d
lastp xzr, p0, p0.d
lastp x0, p15, p0.d
lastp x0, p0, p15.d
neg z0.b, p0/z, z0.b
neg z31.b, p0/z, z0.b
neg z0.b, p7/z, z0.b
neg z0.b, p0/z, z31.b
neg z0.h, p0/z, z0.h
neg z31.h, p0/z, z0.h
neg z0.h, p7/z, z0.h
neg z0.h, p0/z, z31.h
neg z0.s, p0/z, z0.s
neg z31.s, p0/z, z0.s
neg z0.s, p7/z, z0.s
neg z0.s, p0/z, z31.s
neg z0.d, p0/z, z0.d
neg z31.d, p0/z, z0.d
neg z0.d, p7/z, z0.d
neg z0.d, p0/z, z31.d
not z0.b, p0/z, z0.b
not z31.b, p0/z, z0.b
not z0.b, p7/z, z0.b
not z0.b, p0/z, z31.b
not z0.h, p0/z, z0.h
not z31.h, p0/z, z0.h
not z0.h, p7/z, z0.h
not z0.h, p0/z, z31.h
not z0.s, p0/z, z0.s
not z31.s, p0/z, z0.s
not z0.s, p7/z, z0.s
not z0.s, p0/z, z31.s
not z0.d, p0/z, z0.d
not z31.d, p0/z, z0.d
not z0.d, p7/z, z0.d
not z0.d, p0/z, z31.d
rbit z0.b, p0/z, z0.b
rbit z31.b, p0/z, z0.b
rbit z0.b, p7/z, z0.b
rbit z0.b, p0/z, z31.b
rbit z0.h, p0/z, z0.h
rbit z31.h, p0/z, z0.h
rbit z0.h, p7/z, z0.h
rbit z0.h, p0/z, z31.h
rbit z0.s, p0/z, z0.s
rbit z31.s, p0/z, z0.s
rbit z0.s, p7/z, z0.s
rbit z0.s, p0/z, z31.s
rbit z0.d, p0/z, z0.d
rbit z31.d, p0/z, z0.d
rbit z0.d, p7/z, z0.d
rbit z0.d, p0/z, z31.d
revb z0.h, p0/z, z0.h
revb z31.h, p0/z, z0.h
revb z0.h, p7/z, z0.h
revb z0.h, p0/z, z31.h
revb z0.s, p0/z, z0.s
revb z31.s, p0/z, z0.s
revb z0.s, p7/z, z0.s
revb z0.s, p0/z, z31.s
revb z0.d, p0/z, z0.d
revb z31.d, p0/z, z0.d
revb z0.d, p7/z, z0.d
revb z0.d, p0/z, z31.d
revh z0.s, p0/z, z0.s
revh z31.s, p0/z, z0.s
revh z0.s, p7/z, z0.s
revh z0.s, p0/z, z31.s
revh z0.d, p0/z, z0.d
revh z31.d, p0/z, z0.d
revh z0.d, p7/z, z0.d
revh z0.d, p0/z, z31.d
revw z0.d, p0/z, z0.d
revw z31.d, p0/z, z0.d
revw z0.d, p7/z, z0.d
revw z0.d, p0/z, z31.d
revd z0.q, p0/z, z0.q
revd z31.q, p0/z, z0.q
revd z0.q, p7/z, z0.q
revd z0.q, p0/z, z31.q
scvtf z0.h, p0/z, z0.h
scvtf z31.h, p0/z, z0.h
scvtf z0.h, p7/z, z0.h
scvtf z0.h, p0/z, z31.h
scvtf z0.h, p0/z, z0.s
scvtf z31.h, p0/z, z0.s
scvtf z0.h, p7/z, z0.s
scvtf z0.h, p0/z, z31.s
scvtf z0.s, p0/z, z0.s
scvtf z31.s, p0/z, z0.s
scvtf z0.s, p7/z, z0.s
scvtf z0.s, p0/z, z31.s
scvtf z0.d, p0/z, z0.s
scvtf z31.d, p0/z, z0.s
scvtf z0.d, p7/z, z0.s
scvtf z0.d, p0/z, z31.s
scvtf z0.h, p0/z, z0.d
scvtf z31.h, p0/z, z0.d
scvtf z0.h, p7/z, z0.d
scvtf z0.h, p0/z, z31.d
scvtf z0.s, p0/z, z0.d
scvtf z31.s, p0/z, z0.d
scvtf z0.s, p7/z, z0.d
scvtf z0.s, p0/z, z31.d
scvtf z0.d, p0/z, z0.d
scvtf z31.d, p0/z, z0.d
scvtf z0.d, p7/z, z0.d
scvtf z0.d, p0/z, z31.d
sqabs z0.b, p0/z, z0.b
sqabs z31.b, p0/z, z0.b
sqabs z0.b, p7/z, z0.b
sqabs z0.b, p0/z, z31.b
sqabs z0.h, p0/z, z0.h
sqabs z31.h, p0/z, z0.h
sqabs z0.h, p7/z, z0.h
sqabs z0.h, p0/z, z31.h
sqabs z0.s, p0/z, z0.s
sqabs z31.s, p0/z, z0.s
sqabs z0.s, p7/z, z0.s
sqabs z0.s, p0/z, z31.s
sqabs z0.d, p0/z, z0.d
sqabs z31.d, p0/z, z0.d
sqabs z0.d, p7/z, z0.d
sqabs z0.d, p0/z, z31.d
sqneg z0.b, p0/z, z0.b
sqneg z31.b, p0/z, z0.b
sqneg z0.b, p7/z, z0.b
sqneg z0.b, p0/z, z31.b
sqneg z0.h, p0/z, z0.h
sqneg z31.h, p0/z, z0.h
sqneg z0.h, p7/z, z0.h
sqneg z0.h, p0/z, z31.h
sqneg z0.s, p0/z, z0.s
sqneg z31.s, p0/z, z0.s
sqneg z0.s, p7/z, z0.s
sqneg z0.s, p0/z, z31.s
sqneg z0.d, p0/z, z0.d
sqneg z31.d, p0/z, z0.d
sqneg z0.d, p7/z, z0.d
sqneg z0.d, p0/z, z31.d
sxtb z0.h, p0/z, z0.h
sxtb z31.h, p0/z, z0.h
sxtb z0.h, p7/z, z0.h
sxtb z0.h, p0/z, z31.h
sxtb z0.s, p0/z, z0.s
sxtb z31.s, p0/z, z0.s
sxtb z0.s, p7/z, z0.s
sxtb z0.s, p0/z, z31.s
sxtb z0.d, p0/z, z0.d
sxtb z31.d, p0/z, z0.d
sxtb z0.d, p7/z, z0.d
sxtb z0.d, p0/z, z31.d
sxth z0.s, p0/z, z0.s
sxth z31.s, p0/z, z0.s
sxth z0.s, p7/z, z0.s
sxth z0.s, p0/z, z31.s
sxth z0.d, p0/z, z0.d
sxth z31.d, p0/z, z0.d
sxth z0.d, p7/z, z0.d
sxth z0.d, p0/z, z31.d
sxtw z0.d, p0/z, z0.d
sxtw z31.d, p0/z, z0.d
sxtw z0.d, p7/z, z0.d
sxtw z0.d, p0/z, z31.d
ucvtf z0.h, p0/z, z0.h
ucvtf z31.h, p0/z, z0.h
ucvtf z0.h, p7/z, z0.h
ucvtf z0.h, p0/z, z31.h
ucvtf z0.h, p0/z, z0.s
ucvtf z31.h, p0/z, z0.s
ucvtf z0.h, p7/z, z0.s
ucvtf z0.h, p0/z, z31.s
ucvtf z0.s, p0/z, z0.s
ucvtf z31.s, p0/z, z0.s
ucvtf z0.s, p7/z, z0.s
ucvtf z0.s, p0/z, z31.s
ucvtf z0.d, p0/z, z0.s
ucvtf z31.d, p0/z, z0.s
ucvtf z0.d, p7/z, z0.s
ucvtf z0.d, p0/z, z31.s
ucvtf z0.h, p0/z, z0.d
ucvtf z31.h, p0/z, z0.d
ucvtf z0.h, p7/z, z0.d
ucvtf z0.h, p0/z, z31.d
ucvtf z0.s, p0/z, z0.d
ucvtf z31.s, p0/z, z0.d
ucvtf z0.s, p7/z, z0.d
ucvtf z0.s, p0/z, z31.d
ucvtf z0.d, p0/z, z0.d
ucvtf z31.d, p0/z, z0.d
ucvtf z0.d, p7/z, z0.d
ucvtf z0.d, p0/z, z31.d
urecpe z0.s, p0/z, z0.s
urecpe z31.s, p0/z, z0.s
urecpe z0.s, p7/z, z0.s
urecpe z0.s, p0/z, z31.s
ursqrte z0.s, p0/z, z0.s
ursqrte z31.s, p0/z, z0.s
ursqrte z0.s, p7/z, z0.s
ursqrte z0.s, p0/z, z31.s
uxtb z0.h, p0/z, z0.h
uxtb z31.h, p0/z, z0.h
uxtb z0.h, p7/z, z0.h
uxtb z0.h, p0/z, z31.h
uxtb z0.s, p0/z, z0.s
uxtb z31.s, p0/z, z0.s
uxtb z0.s, p7/z, z0.s
uxtb z0.s, p0/z, z31.s
uxtb z0.d, p0/z, z0.d
uxtb z31.d, p0/z, z0.d
uxtb z0.d, p7/z, z0.d
uxtb z0.d, p0/z, z31.d
uxth z0.s, p0/z, z0.s
uxth z31.s, p0/z, z0.s
uxth z0.s, p7/z, z0.s
uxth z0.s, p0/z, z31.s
uxth z0.d, p0/z, z0.d
uxth z31.d, p0/z, z0.d
uxth z0.d, p7/z, z0.d
uxth z0.d, p0/z, z31.d
uxtw z0.d, p0/z, z0.d
uxtw z31.d, p0/z, z0.d
uxtw z0.d, p7/z, z0.d
uxtw z0.d, p0/z, z31.d

View file

@ -282,6 +282,10 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE_B16B16,
/* SME non-widening BFloat16 instructions. */
AARCH64_FEATURE_SME_B16B16,
/* SVE2.2. */
AARCH64_FEATURE_SVE2p2,
/* SME2.2. */
AARCH64_FEATURE_SME2p2,
/* Armv9.1-A processors. */
AARCH64_FEATURE_V9_1A,
/* Armv9.2-A processors. */
@ -307,6 +311,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FP8DOT2_SVE,
/* +sme-f16f16 or +sme-f8f16 */
AARCH64_FEATURE_SME_F16F16_F8F16,
/* +sve or +sme2p2 */
AARCH64_FEATURE_SVE_SME2p2,
/* +sve2 or +sme2 */
AARCH64_FEATURE_SVE2_SME2,
/* +sve2p1 or +sme */
@ -315,6 +321,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE2p1_SME2,
/* +sve2p1 or +sme2p1 */
AARCH64_FEATURE_SVE2p1_SME2p1,
/* +sve2p2 or +sme2p2 */
AARCH64_FEATURE_SVE2p2_SME2p2,
AARCH64_NUM_FEATURES
};
@ -1192,13 +1200,16 @@ enum aarch64_insn_class
sve_pred_zm,
sve_shift_pred,
sve_shift_unpred,
sve_size_bh,
sve_size_bhs,
sve_size_bhsd,
sve_size_hsd,
sve_size_hsd2,
sve_size_hsd3,
sve_size_sd,
sve_size_bh,
sve_size_sd2,
sve_size_sd3,
sve_size_sd4,
sve_size_13,
sve_shift_tsz_hsd,
sve_shift_tsz_bhsd,

View file

@ -2279,11 +2279,24 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0);
break;
case sve_size_sd3:
insert_field (FLD_SVE_sz3, &inst->value, aarch64_get_variant (inst), 0);
break;
case sve_size_sd4:
insert_field (FLD_SVE_sz4, &inst->value, aarch64_get_variant (inst), 0);
break;
case sve_size_hsd2:
insert_field (FLD_SVE_size, &inst->value,
aarch64_get_variant (inst) + 1, 0);
break;
case sve_size_hsd3:
insert_field (FLD_len, &inst->value,
aarch64_get_variant (inst) + 1, 0);
break;
case sve_size_tsz_bhs:
insert_fields (&inst->value,
(1 << aarch64_get_variant (inst)),

File diff suppressed because it is too large Load diff

View file

@ -3603,6 +3603,14 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = extract_field (FLD_SVE_sz2, inst->value, 0);
break;
case sve_size_sd3:
variant = extract_field (FLD_SVE_sz3, inst->value, 0);
break;
case sve_size_sd4:
variant = extract_field (FLD_SVE_sz4, inst->value, 0);
break;
case sve_size_hsd2:
i = extract_field (FLD_SVE_size, inst->value, 0);
if (i < 1)
@ -3610,6 +3618,13 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
variant = i - 1;
break;
case sve_size_hsd3:
i = extract_field (FLD_len, inst->value, 0);
if (i < 1)
return false;
variant = i - 1;
break;
case sve_size_13:
/* Ignore low bit of this field since that is set in the opcode for
instructions of this iclass. */

View file

@ -329,6 +329,8 @@ const aarch64_field fields[] =
{ 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
{ 22, 1 }, /* SVE_sz: 1-bit element size select. */
{ 30, 1 }, /* SVE_sz2: 1-bit element size select. */
{ 17, 1 }, /* SVE_sz3: 1-bit element size select. */
{ 14, 1 }, /* SVE_sz4: 1-bit element size select. */
{ 16, 4 }, /* SVE_tsz: triangular size select. */
{ 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
{ 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */

View file

@ -133,6 +133,8 @@ enum aarch64_field_kind
FLD_SVE_size,
FLD_SVE_sz,
FLD_SVE_sz2,
FLD_SVE_sz3,
FLD_SVE_sz4,
FLD_SVE_tsz,
FLD_SVE_tszh,
FLD_SVE_tszl_8,

View file

@ -1732,6 +1732,14 @@
{ \
QLF3(S_D,P_Z,S_D), \
}
#define OP_SVE_DZH \
{ \
QLF3(S_D,P_Z,S_H), \
}
#define OP_SVE_DZS \
{ \
QLF3(S_D,P_Z,S_S), \
}
#define OP_SVE_DZU \
{ \
QLF3(S_D,P_Z,NIL), \
@ -1792,6 +1800,18 @@
{ \
QLF3(S_H,NIL,NIL), \
}
#define OP_SVE_HZD \
{ \
QLF3(S_H,P_Z,S_D), \
}
#define OP_SVE_HZH \
{ \
QLF3(S_H,P_Z,S_H), \
}
#define OP_SVE_HZS \
{ \
QLF3(S_H,P_Z,S_S), \
}
#define OP_SVE_HZU \
{ \
QLF3(S_H,P_Z,NIL), \
@ -1812,6 +1832,10 @@
{ \
QLF3(S_Q,NIL,NIL), \
}
#define OP_SVE_QZQ \
{ \
QLF3(S_Q,P_Z,S_Q), \
}
#define OP_SVE_QZU \
{ \
QLF3(S_Q,P_Z,NIL), \
@ -1899,6 +1923,14 @@
{ \
QLF3(S_S,NIL,NIL), \
}
#define OP_SVE_SZD \
{ \
QLF3(S_S,P_Z,S_D), \
}
#define OP_SVE_SZH \
{ \
QLF3(S_S,P_Z,S_H), \
}
#define OP_SVE_SZS \
{ \
QLF3(S_S,P_Z,S_S), \
@ -2171,6 +2203,11 @@
QLF4(S_S,NIL,S_S,S_S), \
QLF4(S_D,NIL,S_D,S_D), \
}
#define OP_SVE_VUV_BH \
{ \
QLF3(S_B,NIL,S_B), \
QLF3(S_H,NIL,S_H), \
}
#define OP_SVE_VUV_BHSD \
{ \
QLF3(S_B,NIL,S_B), \
@ -2404,6 +2441,13 @@
QLF4(S_S,X,X,NIL), \
QLF4(S_D,X,X,NIL), \
}
#define OP_SVE_VZV_BHSD \
{ \
QLF3(S_B,P_Z,S_B), \
QLF3(S_H,P_Z,S_H), \
QLF3(S_S,P_Z,S_S), \
QLF3(S_D,P_Z,S_D), \
}
#define OP_SVE_VZVD_BHS \
{ \
QLF4(S_B,P_Z,S_B,S_D), \
@ -2942,6 +2986,12 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2 =
AARCH64_FEATURES (2, SVE2p1_SME2, SVE);
static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
AARCH64_FEATURES (2, SVE2p1_SME2p1, SVE);
static const aarch64_feature_set aarch64_feature_sme2p2 =
AARCH64_FEATURES (2, SME2p2, SME);
static const aarch64_feature_set aarch64_feature_sve_sme2p2 =
AARCH64_FEATURES (2, SVE_SME2p2, SVE);
static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
AARCH64_FEATURES (2, SVE2p2_SME2p2, SVE);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@ -3046,6 +3096,9 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
#define SVE2p1_SME &aarch64_feature_sve2p1_sme
#define SVE2p1_SME2 &aarch64_feature_sve2p1_sme2
#define SVE2p1_SME2p1 &aarch64_feature_sve2p1_sme2p1
#define SME2p2 &aarch64_feature_sme2p2
#define SVE_SME2p2 &aarch64_feature_sve_sme2p2
#define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -3320,6 +3373,15 @@ static const aarch64_feature_set aarch64_feature_sve2p1_sme2p1 =
#define SVE2p1_SME2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE2p1_SME2p1, OPS, QUALS, \
F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define SVE_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, OP, SVE_SME2p2, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
#define SVE2p2_SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SVE2p2_SME2p2, OPS, QUALS, \
F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
#define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \
F_STRICT | FLAGS, 0, TIED, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@ -4940,7 +5002,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSN ("cnth", 0x0460e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
_SVE_INSN ("cntp", 0x25208000, 0xff3fc200, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0),
_SVE_INSN ("cntw", 0x04a0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
_SVE_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
SVE_SME2p2_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
_SVE_INSNC ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
_SVE_INSNC ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
_SVE_INSNC ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
@ -7233,6 +7295,102 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_F8F32_INSNC ("fvdotb", 0xc1d00800, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4) | F_VG_REQ, 0),
SME_F8F32_INSNC ("fvdott", 0xc1d00810, 0xfff09830, sme_misc, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2_3), OP_SVE_VVV_S_B, F_OD (4) | F_VG_REQ, 0),
/* SVE2p2 / SME2p2 instructions. */
SVE2p2_SME2p2_INSN ("abs", 0x0406a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("bfcvt", 0x649ac000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("bfcvtnt", 0x6482a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("cls", 0x0408a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("clz", 0x0409a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("cnot", 0x040ba000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("cnt", 0x040aa000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("compact", 0x05218000, 0xffbfe000, sve_size_bh, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("expand", 0x05318000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fabs", 0x040ca000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvt", 0x649aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvt", 0x64daa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvt", 0x649a8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvt", 0x64dae000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvt", 0x64da8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvt", 0x64dac000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtlt", 0x6481a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtlt", 0x64c3a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtnt", 0x6480a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtnt", 0x64c2a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtx", 0x641ac000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtxnt", 0x6402a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x645ec000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x645f8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x645fc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x649f8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x64df8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x64de8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzs", 0x64dfc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x645ee000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x645fa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x645fe000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x649fa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x64dfa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x64dea000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fcvtzu", 0x64dfe000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("firstp", 0x25218000, 0xff3fc200, sve_size_bhsd, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("flogb", 0x641e8000, 0xffff8000, sve_size_hsd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fneg", 0x040da000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frecpx", 0x641b8000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frint32x", 0x6511a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
SVE2p2_SME2p2_INSN ("frint32x", 0x641ca000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frint32z", 0x6510a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
SVE2p2_SME2p2_INSN ("frint32z", 0x641c8000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frint64x", 0x6515a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
SVE2p2_SME2p2_INSN ("frint64x", 0x641da000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frint64z", 0x6514a000, 0xfffde000, sve_size_sd3, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
SVE2p2_SME2p2_INSN ("frint64z", 0x641d8000, 0xffffa000, sve_size_sd4, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frintx", 0x6419c000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frinti", 0x6419e000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frinta", 0x64198000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frintn", 0x64188000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frintz", 0x6418e000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frintm", 0x6418c000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("frintp", 0x6418a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("fsqrt", 0x641ba000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("lastp", 0x25228000, 0xff3fc200, sve_size_bhsd, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("neg", 0x0407a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("not", 0x040ea000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("rbit", 0x0527a000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("revb", 0x0524a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("revh", 0x05a5a000, 0xffbfe000, sve_size_sd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("revw", 0x05e6a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("revd", 0x052ea000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QZQ, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x645cc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x645d8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x649d8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x64dc8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x645dc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x64dd8000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("scvtf", 0x64ddc000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("sqabs", 0x440aa000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("sqneg", 0x440ba000, 0xff3fe000, sve_size_bhsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_BHSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("sxtb", 0x0400a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("sxth", 0x0482a000, 0xffbfe000, sve_size_sd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("sxtw", 0x04c4a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x645ce000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZH, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x645da000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x649da000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x64dca000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x645de000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x64dda000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ucvtf", 0x64dde000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("urecpe", 0x4482a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("ursqrte", 0x4483a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SZS, 0, 0, 0),
SVE2p2_SME2p2_INSN ("uxtb", 0x0401a000, 0xff3fe000, sve_size_hsd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_HSD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("uxth", 0x0483a000, 0xffbfe000, sve_size_sd, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VZV_SD, 0, 0, 0),
SVE2p2_SME2p2_INSN ("uxtw", 0x04c5a000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DZD, 0, 0, 0),
/* SME2p2 instructions. */
SME2p2_INSN ("fmul", 0xc120e800, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zm_17), OP_SVE_VVV_HSD, 0, 0),
SME2p2_INSN ("fmul", 0xc121e800, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zm_17), OP_SVE_VVV_HSD, 0, 0),
SME2p2_INSN ("fmul", 0xc120e400, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 0),
SME2p2_INSN ("fmul", 0xc121e400, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 0),
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};