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Delete the ARM sub-directory of the SIM directory.

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This commit is contained in:
Nick Clifton 2025-03-25 13:30:32 +00:00
parent ea10be6e89
commit f829773772
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27 changed files with 209 additions and 24624 deletions
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3
sim/Makefile.am
View file

@ -106,9 +106,6 @@ include testsuite/local.mk
if SIM_ENABLE_ARCH_aarch64
include aarch64/local.mk
endif
if SIM_ENABLE_ARCH_arm
include arm/local.mk
endif
if SIM_ENABLE_ARCH_avr
include avr/local.mk
endif

517
sim/Makefile.in
View file

@ -118,7 +118,7 @@ noinst_PROGRAMS = $(am__EXEEXT_11) $(am__EXEEXT_12) $(am__EXEEXT_13) \
$(am__EXEEXT_32) $(am__EXEEXT_33) $(am__EXEEXT_34) \
$(am__EXEEXT_35) $(am__EXEEXT_36) $(am__EXEEXT_37) \
$(am__EXEEXT_38) $(am__EXEEXT_39) $(am__EXEEXT_40) \
$(am__EXEEXT_41) $(am__EXEEXT_42)
$(am__EXEEXT_41)
EXTRA_PROGRAMS = $(am__EXEEXT_1) testsuite/common/bits-gen$(EXEEXT) \
testsuite/common/fpu-tst$(EXEEXT) $(am__EXEEXT_2) \
$(am__EXEEXT_3) $(am__EXEEXT_4) $(am__EXEEXT_5) \
@ -138,86 +138,84 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_3 = aarch64/libsim.a
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_4 = aarch64/run
@SIM_ENABLE_ARCH_arm_TRUE@am__append_5 = arm/libsim.a
@SIM_ENABLE_ARCH_arm_TRUE@am__append_6 = arm/run
@SIM_ENABLE_ARCH_avr_TRUE@am__append_7 = avr/libsim.a
@SIM_ENABLE_ARCH_avr_TRUE@am__append_8 = avr/run
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_9 = bfin/libsim.a
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_10 = bfin/run
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_11 = bpf/libsim.a
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_12 = bpf/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/libsim.a
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/run
@SIM_ENABLE_ARCH_avr_TRUE@am__append_5 = avr/libsim.a
@SIM_ENABLE_ARCH_avr_TRUE@am__append_6 = avr/run
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_7 = bfin/libsim.a
@SIM_ENABLE_ARCH_bfin_TRUE@am__append_8 = bfin/run
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_9 = bpf/libsim.a
@SIM_ENABLE_ARCH_bpf_TRUE@am__append_10 = bpf/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_11 = cr16/libsim.a
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_12 = cr16/run
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/gencode
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/libsim.a
@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/rvdummy
@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = \
@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = $(cr16_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@am__append_17 = cris/libsim.a
@SIM_ENABLE_ARCH_cris_TRUE@am__append_18 = cris/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/rvdummy
@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/engv10.h cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/run
@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/engv10.h cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_23 = d10v/libsim.a
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_24 = d10v/run
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = erc32/libsim.a
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = erc32/run erc32/sis
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = sim-%D-install-exec-local
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = sim-erc32-uninstall-local
@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 = example-synacor/libsim.a
@SIM_ENABLE_ARCH_examples_TRUE@am__append_36 = example-synacor/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/libsim.a
@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_42 = ft32/libsim.a
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 = ft32/run
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_44 = h8300/libsim.a
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 = h8300/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/libsim.a
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/libsim.a
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = m32c/run
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 = m32c/opc2c
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_59 = \
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = $(d10v_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_29 = erc32/libsim.a
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_30 = erc32/run erc32/sis
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = sim-%D-install-exec-local
@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = sim-erc32-uninstall-local
@SIM_ENABLE_ARCH_examples_TRUE@am__append_33 = example-synacor/libsim.a
@SIM_ENABLE_ARCH_examples_TRUE@am__append_34 = example-synacor/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_35 = frv/libsim.a
@SIM_ENABLE_ARCH_frv_TRUE@am__append_36 = frv/run
@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_40 = ft32/libsim.a
@SIM_ENABLE_ARCH_ft32_TRUE@am__append_41 = ft32/run
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_42 = h8300/libsim.a
@SIM_ENABLE_ARCH_h8300_TRUE@am__append_43 = h8300/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 = iq2000/libsim.a
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = iq2000/run
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_50 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_54 = m32c/libsim.a
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 = m32c/run
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/opc2c
@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = m32r/libsim.a
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/run
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = \
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_58 = m32r/libsim.a
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 = m32r/run
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_63 = m32r/eng.h m32r/engx.h m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/libsim.a
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = m68hc11/run
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_67 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_68 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_69 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_70 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_71 = microblaze/libsim.a
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_72 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/eng.h m32r/engx.h m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 = m68hc11/libsim.a
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_64 = m68hc11/run
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/gencode
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = $(m68hc11_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_67 = mcore/libsim.a
@SIM_ENABLE_ARCH_mcore_TRUE@am__append_68 = mcore/run
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_69 = microblaze/libsim.a
@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_70 = microblaze/run
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_71 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
@ -226,7 +224,7 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_74 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_72 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
@ -240,35 +238,35 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/libsim.a
@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@am__append_74 = mips/libsim.a
@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 = mips/run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_77 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_78 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = mn10300/libsim.a
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 = \
@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 = mips/multi-include.h mips/multi-run.c
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 = mn10300/libsim.a
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_83 = mn10300/run
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@ -277,47 +275,47 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_88 = moxie/libsim.a
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 = msp430/libsim.a
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/libsim.a
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/libsim.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/defines.h ppc/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_86 = moxie/libsim.a
@SIM_ENABLE_ARCH_moxie_TRUE@am__append_87 = moxie/run
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_88 = msp430/libsim.a
@SIM_ENABLE_ARCH_msp430_TRUE@am__append_89 = msp430/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 = or1k/libsim.a
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_91 = or1k/run
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_95 = ppc/libsim.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_96 = ppc/run
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/defines.h ppc/icache.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h ppc/semantics.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h ppc/support.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h ppc/hw.h
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/defines.h \
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/defines.h \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-defines \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_IGEN_TOOLS) ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_101 = ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_102 = $(ppc_IGEN_TOOLS)
@SIM_ENABLE_ARCH_pru_TRUE@am__append_103 = pru/libsim.a
@SIM_ENABLE_ARCH_pru_TRUE@am__append_104 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_105 = riscv/libsim.a
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 = rl78/libsim.a
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_108 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 = rx/libsim.a
@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/libsim.a
@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/libigen.a
@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = $(ppc_IGEN_TOOLS)
@SIM_ENABLE_ARCH_pru_TRUE@am__append_101 = pru/libsim.a
@SIM_ENABLE_ARCH_pru_TRUE@am__append_102 = pru/run
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_103 = riscv/libsim.a
@SIM_ENABLE_ARCH_riscv_TRUE@am__append_104 = riscv/run
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_105 = rl78/libsim.a
@SIM_ENABLE_ARCH_rl78_TRUE@am__append_106 = rl78/run
@SIM_ENABLE_ARCH_rx_TRUE@am__append_107 = rx/libsim.a
@SIM_ENABLE_ARCH_rx_TRUE@am__append_108 = rx/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_109 = sh/libsim.a
@SIM_ENABLE_ARCH_sh_TRUE@am__append_110 = sh/run
@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = v850/libsim.a
@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_118 = \
@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/gencode
@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = $(sh_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_114 = v850/libsim.a
@SIM_ENABLE_ARCH_v850_TRUE@am__append_115 = v850/run
@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@ -326,7 +324,7 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
@ -366,15 +364,15 @@ am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
configure.lineno config.status.lineno
mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs
CONFIG_HEADER = config.h
CONFIG_CLEAN_FILES = aarch64/.gdbinit arm/.gdbinit avr/.gdbinit \
bfin/.gdbinit bpf/.gdbinit cr16/.gdbinit cris/.gdbinit \
d10v/.gdbinit frv/.gdbinit ft32/.gdbinit h8300/.gdbinit \
iq2000/.gdbinit lm32/.gdbinit m32c/.gdbinit m32r/.gdbinit \
m68hc11/.gdbinit mcore/.gdbinit microblaze/.gdbinit \
mips/.gdbinit mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit \
or1k/.gdbinit ppc/.gdbinit pru/.gdbinit riscv/.gdbinit \
rl78/.gdbinit rx/.gdbinit sh/.gdbinit erc32/.gdbinit \
v850/.gdbinit example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_FILES = aarch64/.gdbinit avr/.gdbinit bfin/.gdbinit \
bpf/.gdbinit cr16/.gdbinit cris/.gdbinit d10v/.gdbinit \
frv/.gdbinit ft32/.gdbinit h8300/.gdbinit iq2000/.gdbinit \
lm32/.gdbinit m32c/.gdbinit m32r/.gdbinit m68hc11/.gdbinit \
mcore/.gdbinit microblaze/.gdbinit mips/.gdbinit \
mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit or1k/.gdbinit \
ppc/.gdbinit pru/.gdbinit riscv/.gdbinit rl78/.gdbinit \
rx/.gdbinit sh/.gdbinit erc32/.gdbinit v850/.gdbinit \
example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_VPATH_FILES =
LIBRARIES = $(noinst_LIBRARIES)
ARFLAGS = cru
@ -407,22 +405,6 @@ am__objects_1 = common/callback.$(OBJEXT) common/portability.$(OBJEXT) \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/modules.$(OBJEXT)
aarch64_libsim_a_OBJECTS = $(am_aarch64_libsim_a_OBJECTS) \
$(nodist_aarch64_libsim_a_OBJECTS)
arm_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_DEPENDENCIES = arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_arm_TRUE@ %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_arm_TRUE@ %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o arm/armemu32.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/arminit.o arm/armos.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armsupp.o arm/armvirt.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/thumbemu.o arm/armcopro.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/maverick.o arm/iwmmxt.o
@SIM_ENABLE_ARCH_arm_TRUE@am_arm_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.$(OBJEXT)
arm_libsim_a_OBJECTS = $(am_arm_libsim_a_OBJECTS) \
$(nodist_arm_libsim_a_OBJECTS)
avr_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_DEPENDENCIES = avr/interp.o \
@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst \
@ -736,8 +718,8 @@ am__DEPENDENCIES_1 =
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) \
@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_71) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
@ -954,40 +936,39 @@ am__EXEEXT_9 = testsuite/common/bits32m0$(EXEEXT) \
testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_10 = cris/rvdummy$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_11 = aarch64/run$(EXEEXT)
@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_12 = arm/run$(EXEEXT)
@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_13 = avr/run$(EXEEXT)
@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_14 = bfin/run$(EXEEXT)
@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_15 = bpf/run$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_16 = cr16/run$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_17 = cris/run$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_18 = d10v/run$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_19 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_12 = avr/run$(EXEEXT)
@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_13 = bfin/run$(EXEEXT)
@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_14 = bpf/run$(EXEEXT)
@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_15 = cr16/run$(EXEEXT)
@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_16 = cris/run$(EXEEXT)
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_17 = d10v/run$(EXEEXT)
@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_18 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis$(EXEEXT)
@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_20 = \
@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_19 = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/run$(EXEEXT)
@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_21 = frv/run$(EXEEXT)
@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_22 = ft32/run$(EXEEXT)
@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_23 = h8300/run$(EXEEXT)
@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_24 = iq2000/run$(EXEEXT)
@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_25 = lm32/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_26 = m32c/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_27 = m32r/run$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_28 = m68hc11/run$(EXEEXT)
@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_29 = mcore/run$(EXEEXT)
@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_30 = \
@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_20 = frv/run$(EXEEXT)
@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_21 = ft32/run$(EXEEXT)
@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_22 = h8300/run$(EXEEXT)
@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_23 = iq2000/run$(EXEEXT)
@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_24 = lm32/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_25 = m32c/run$(EXEEXT)
@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_26 = m32r/run$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_27 = m68hc11/run$(EXEEXT)
@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_28 = mcore/run$(EXEEXT)
@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_29 = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/run$(EXEEXT)
@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_31 = mips/run$(EXEEXT)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_32 = mn10300/run$(EXEEXT)
@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_33 = moxie/run$(EXEEXT)
@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_34 = msp430/run$(EXEEXT)
@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_35 = or1k/run$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_36 = ppc/run$(EXEEXT)
@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_37 = pru/run$(EXEEXT)
@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_38 = riscv/run$(EXEEXT)
@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_39 = rl78/run$(EXEEXT)
@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_40 = rx/run$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_41 = sh/run$(EXEEXT)
@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_42 = v850/run$(EXEEXT)
@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_30 = mips/run$(EXEEXT)
@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_31 = mn10300/run$(EXEEXT)
@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_32 = moxie/run$(EXEEXT)
@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_33 = msp430/run$(EXEEXT)
@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_34 = or1k/run$(EXEEXT)
@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_35 = ppc/run$(EXEEXT)
@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_36 = pru/run$(EXEEXT)
@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_37 = riscv/run$(EXEEXT)
@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_38 = rl78/run$(EXEEXT)
@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_39 = rx/run$(EXEEXT)
@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_40 = sh/run$(EXEEXT)
@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_41 = v850/run$(EXEEXT)
PROGRAMS = $(noinst_PROGRAMS)
am_aarch64_run_OBJECTS =
aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
@ -999,10 +980,6 @@ AM_V_lt = $(am__v_lt_@AM_V@)
am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@)
am__v_lt_0 = --silent
am__v_lt_1 =
am_arm_run_OBJECTS =
arm_run_OBJECTS = $(am_arm_run_OBJECTS)
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_DEPENDENCIES = arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a $(am__DEPENDENCIES_4)
am_avr_run_OBJECTS =
avr_run_OBJECTS = $(am_avr_run_OBJECTS)
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_DEPENDENCIES = avr/nrun.o \
@ -1264,8 +1241,7 @@ am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@)
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
SOURCES = $(aarch64_libsim_a_SOURCES) \
$(nodist_aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
$(nodist_arm_libsim_a_SOURCES) $(avr_libsim_a_SOURCES) \
$(nodist_aarch64_libsim_a_SOURCES) $(avr_libsim_a_SOURCES) \
$(nodist_avr_libsim_a_SOURCES) $(bfin_libsim_a_SOURCES) \
$(nodist_bfin_libsim_a_SOURCES) $(bpf_libsim_a_SOURCES) \
$(nodist_bpf_libsim_a_SOURCES) $(common_libcommon_a_SOURCES) \
@ -1299,8 +1275,8 @@ SOURCES = $(aarch64_libsim_a_SOURCES) \
$(nodist_rx_libsim_a_SOURCES) $(sh_libsim_a_SOURCES) \
$(nodist_sh_libsim_a_SOURCES) $(v850_libsim_a_SOURCES) \
$(nodist_v850_libsim_a_SOURCES) $(aarch64_run_SOURCES) \
$(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
$(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
$(avr_run_SOURCES) $(bfin_run_SOURCES) $(bpf_run_SOURCES) \
$(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
$(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
$(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
$(erc32_run_SOURCES) erc32/sis.c \
@ -1356,12 +1332,12 @@ am__uninstall_files_from_dir = { \
|| { echo " ( cd '$$dir' && rm -f" $$files ")"; \
$(am__cd) "$$dir" && rm -f $$files; }; \
}
am__installdirs = "$(DESTDIR)$(armdocdir)" "$(DESTDIR)$(dtbdir)" \
"$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" \
"$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" \
"$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"
DATA = $(armdoc_DATA) $(dtb_DATA) $(erc32doc_DATA) $(frvdoc_DATA) \
$(or1kdoc_DATA) $(ppcdoc_DATA) $(rxdoc_DATA)
am__installdirs = "$(DESTDIR)$(dtbdir)" "$(DESTDIR)$(erc32docdir)" \
"$(DESTDIR)$(frvdocdir)" "$(DESTDIR)$(or1kdocdir)" \
"$(DESTDIR)$(ppcdocdir)" "$(DESTDIR)$(rxdocdir)" \
"$(DESTDIR)$(pkgincludedir)"
DATA = $(dtb_DATA) $(erc32doc_DATA) $(frvdoc_DATA) $(or1kdoc_DATA) \
$(ppcdoc_DATA) $(rxdoc_DATA)
am__pkginclude_HEADERS_DIST = $(srcroot)/include/sim/callback.h \
$(srcroot)/include/sim/sim.h
HEADERS = $(pkginclude_HEADERS)
@ -1574,7 +1550,6 @@ AR = @AR@
AR_FOR_BUILD = @AR_FOR_BUILD@
AS_FOR_TARGET = @AS_FOR_TARGET@
AS_FOR_TARGET_AARCH64 = @AS_FOR_TARGET_AARCH64@
AS_FOR_TARGET_ARM = @AS_FOR_TARGET_ARM@
AS_FOR_TARGET_AVR = @AS_FOR_TARGET_AVR@
AS_FOR_TARGET_BFIN = @AS_FOR_TARGET_BFIN@
AS_FOR_TARGET_BPF = @AS_FOR_TARGET_BPF@
@ -1616,7 +1591,6 @@ CCDEPMODE = @CCDEPMODE@
CC_FOR_BUILD = @CC_FOR_BUILD@
CC_FOR_TARGET = @CC_FOR_TARGET@
CC_FOR_TARGET_AARCH64 = @CC_FOR_TARGET_AARCH64@
CC_FOR_TARGET_ARM = @CC_FOR_TARGET_ARM@
CC_FOR_TARGET_AVR = @CC_FOR_TARGET_AVR@
CC_FOR_TARGET_BFIN = @CC_FOR_TARGET_BFIN@
CC_FOR_TARGET_BPF = @CC_FOR_TARGET_BPF@
@ -1678,7 +1652,6 @@ LDFLAGS = @LDFLAGS@
LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@
LD_FOR_TARGET = @LD_FOR_TARGET@
LD_FOR_TARGET_AARCH64 = @LD_FOR_TARGET_AARCH64@
LD_FOR_TARGET_ARM = @LD_FOR_TARGET_ARM@
LD_FOR_TARGET_AVR = @LD_FOR_TARGET_AVR@
LD_FOR_TARGET_BFIN = @LD_FOR_TARGET_BFIN@
LD_FOR_TARGET_BPF = @LD_FOR_TARGET_BPF@
@ -1856,41 +1829,41 @@ GNULIB_PARENT_DIR = ..
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
pkginclude_HEADERS = $(am__append_1)
EXTRA_LIBRARIES = igen/libigen.a $(am__append_101)
EXTRA_LIBRARIES = igen/libigen.a $(am__append_99)
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
$(am__append_7) $(am__append_9) $(am__append_11) \
$(am__append_13) $(am__append_19) $(am__append_25) \
$(am__append_31) $(am__append_35) $(am__append_37) \
$(am__append_42) $(am__append_44) $(am__append_46) \
$(am__append_51) $(am__append_56) $(am__append_60) \
$(am__append_65) $(am__append_69) $(am__append_71) \
$(am__append_76) $(am__append_84) $(am__append_88) \
$(am__append_90) $(am__append_92) $(am__append_97) \
$(am__append_17) $(am__append_23) $(am__append_29) \
$(am__append_33) $(am__append_35) $(am__append_40) \
$(am__append_42) $(am__append_44) $(am__append_49) \
$(am__append_54) $(am__append_58) $(am__append_63) \
$(am__append_67) $(am__append_69) $(am__append_74) \
$(am__append_82) $(am__append_86) $(am__append_88) \
$(am__append_90) $(am__append_95) $(am__append_101) \
$(am__append_103) $(am__append_105) $(am__append_107) \
$(am__append_109) $(am__append_111) $(am__append_116)
BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \
$(am__append_39) $(am__append_48) $(am__append_53) \
$(am__append_62) $(am__append_78) $(am__append_86) \
$(am__append_94) $(am__append_99) $(am__append_113) \
$(am__append_118)
$(am__append_109) $(am__append_114)
BUILT_SOURCES = $(am__append_13) $(am__append_20) $(am__append_25) \
$(am__append_37) $(am__append_46) $(am__append_51) \
$(am__append_60) $(am__append_76) $(am__append_84) \
$(am__append_92) $(am__append_97) $(am__append_111) \
$(am__append_116)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \
$(am__append_29) $(am__append_40) $(am__append_49) \
$(am__append_54) $(am__append_63) $(am__append_95)
DISTCLEANFILES = $(am__append_83)
testsuite/common/bits64m63.c $(am__append_15) $(am__append_21) \
$(am__append_27) $(am__append_38) $(am__append_47) \
$(am__append_52) $(am__append_61) $(am__append_93)
DISTCLEANFILES = $(am__append_81)
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
$(SIM_ENABLED_ARCHES:%=%/modules.c) \
$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
igen/libigen.a site-sim-config.exp testrun.log testrun.sum \
$(am__append_18) $(am__append_24) $(am__append_30) \
$(am__append_41) $(am__append_50) $(am__append_55) \
$(am__append_59) $(am__append_64) $(am__append_68) \
$(am__append_82) $(am__append_87) $(am__append_96) \
$(am__append_100) $(am__append_115) $(am__append_119)
$(am__append_16) $(am__append_22) $(am__append_28) \
$(am__append_39) $(am__append_48) $(am__append_53) \
$(am__append_57) $(am__append_62) $(am__append_66) \
$(am__append_80) $(am__append_85) $(am__append_94) \
$(am__append_98) $(am__append_113) $(am__append_117)
CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh
AM_CFLAGS = \
$(WERROR_CFLAGS) \
@ -1907,8 +1880,8 @@ AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(BUILD_WERROR_CFLAGS) $(BUILD_WARN_CFLAGS)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_INSTALL_DATA_LOCAL_DEPS =
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34)
SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_31)
SIM_UNINSTALL_LOCAL_DEPS = $(am__append_32)
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
@ -2109,30 +2082,6 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_arm_TRUE@AM_CPPFLAGS_arm = -DMODET
@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.c
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_arm_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/wrapper.o \
@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armvirt.o arm/thumbemu.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/armcopro.o arm/maverick.o arm/iwmmxt.o
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES =
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a \
@SIM_ENABLE_ARCH_arm_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
@SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.c
@ -2705,8 +2654,8 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75)
@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_71) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
@ -2778,8 +2727,8 @@ testsuite_common_CPPFLAGS = \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81)
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_77) $(am__append_78) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@ -3238,7 +3187,7 @@ all: $(BUILT_SOURCES) config.h
.SUFFIXES: .c .lo .log .o .obj .test .test$(EXEEXT) .trs
am--refresh: Makefile
@:
$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps)
$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
@ -3260,7 +3209,7 @@ Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
esac;
$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty):
$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty):
$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
$(SHELL) ./config.status --recheck
@ -3287,8 +3236,6 @@ distclean-hdr:
-rm -f config.h stamp-h1
aarch64/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
arm/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
avr/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
bfin/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
@ -3393,19 +3340,6 @@ aarch64/libsim.a: $(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_DEPENDENCIES) $
$(AM_V_at)-rm -f aarch64/libsim.a
$(AM_V_AR)$(aarch64_libsim_a_AR) aarch64/libsim.a $(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) aarch64/libsim.a
arm/$(am__dirstamp):
@$(MKDIR_P) arm
@: > arm/$(am__dirstamp)
arm/$(DEPDIR)/$(am__dirstamp):
@$(MKDIR_P) arm/$(DEPDIR)
@: > arm/$(DEPDIR)/$(am__dirstamp)
arm/modules.$(OBJEXT): arm/$(am__dirstamp) \
arm/$(DEPDIR)/$(am__dirstamp)
arm/libsim.a: $(arm_libsim_a_OBJECTS) $(arm_libsim_a_DEPENDENCIES) $(EXTRA_arm_libsim_a_DEPENDENCIES) arm/$(am__dirstamp)
$(AM_V_at)-rm -f arm/libsim.a
$(AM_V_AR)$(arm_libsim_a_AR) arm/libsim.a $(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) arm/libsim.a
avr/$(am__dirstamp):
@$(MKDIR_P) avr
@: > avr/$(am__dirstamp)
@ -3886,10 +3820,6 @@ aarch64/run$(EXEEXT): $(aarch64_run_OBJECTS) $(aarch64_run_DEPENDENCIES) $(EXTRA
@rm -f aarch64/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(aarch64_run_OBJECTS) $(aarch64_run_LDADD) $(LIBS)
arm/run$(EXEEXT): $(arm_run_OBJECTS) $(arm_run_DEPENDENCIES) $(EXTRA_arm_run_DEPENDENCIES) arm/$(am__dirstamp)
@rm -f arm/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(arm_run_OBJECTS) $(arm_run_LDADD) $(LIBS)
avr/run$(EXEEXT): $(avr_run_OBJECTS) $(avr_run_DEPENDENCIES) $(EXTRA_avr_run_DEPENDENCIES) avr/$(am__dirstamp)
@rm -f avr/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(avr_run_OBJECTS) $(avr_run_LDADD) $(LIBS)
@ -4120,7 +4050,6 @@ v850/run$(EXEEXT): $(v850_run_OBJECTS) $(v850_run_DEPENDENCIES) $(EXTRA_v850_run
mostlyclean-compile:
-rm -f *.$(OBJEXT)
-rm -f aarch64/*.$(OBJEXT)
-rm -f arm/*.$(OBJEXT)
-rm -f avr/*.$(OBJEXT)
-rm -f bfin/*.$(OBJEXT)
-rm -f bpf/*.$(OBJEXT)
@ -4159,7 +4088,6 @@ distclean-compile:
-rm -f *.tab.c
@AMDEP_TRUE@@am__include@ @am__quote@aarch64/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@arm/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@avr/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@bfin/$(DEPDIR)/modules.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@bpf/$(DEPDIR)/modules.Po@am__quote@
@ -4276,7 +4204,6 @@ mostlyclean-libtool:
clean-libtool:
-rm -rf .libs _libs
-rm -rf aarch64/.libs aarch64/_libs
-rm -rf arm/.libs arm/_libs
-rm -rf avr/.libs avr/_libs
-rm -rf bfin/.libs bfin/_libs
-rm -rf bpf/.libs bpf/_libs
@ -4312,27 +4239,6 @@ clean-libtool:
distclean-libtool:
-rm -f libtool config.lt
install-armdocDATA: $(armdoc_DATA)
@$(NORMAL_INSTALL)
@list='$(armdoc_DATA)'; test -n "$(armdocdir)" || list=; \
if test -n "$$list"; then \
echo " $(MKDIR_P) '$(DESTDIR)$(armdocdir)'"; \
$(MKDIR_P) "$(DESTDIR)$(armdocdir)" || exit 1; \
fi; \
for p in $$list; do \
if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \
echo "$$d$$p"; \
done | $(am__base_list) | \
while read files; do \
echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(armdocdir)'"; \
$(INSTALL_DATA) $$files "$(DESTDIR)$(armdocdir)" || exit $$?; \
done
uninstall-armdocDATA:
@$(NORMAL_UNINSTALL)
@list='$(armdoc_DATA)'; test -n "$(armdocdir)" || list=; \
files=`for p in $$list; do echo $$p; done | sed -e 's|^.*/||'`; \
dir='$(DESTDIR)$(armdocdir)'; $(am__uninstall_files_from_dir)
install-dtbDATA: $(dtb_DATA)
@$(NORMAL_INSTALL)
@list='$(dtb_DATA)'; test -n "$(dtbdir)" || list=; \
@ -4769,7 +4675,7 @@ check: $(BUILT_SOURCES)
$(MAKE) $(AM_MAKEFLAGS) check-am
all-am: Makefile $(LIBRARIES) $(PROGRAMS) $(DATA) $(HEADERS) config.h
installdirs:
for dir in "$(DESTDIR)$(armdocdir)" "$(DESTDIR)$(dtbdir)" "$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" "$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" "$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"; do \
for dir in "$(DESTDIR)$(dtbdir)" "$(DESTDIR)$(erc32docdir)" "$(DESTDIR)$(frvdocdir)" "$(DESTDIR)$(or1kdocdir)" "$(DESTDIR)$(ppcdocdir)" "$(DESTDIR)$(rxdocdir)" "$(DESTDIR)$(pkgincludedir)"; do \
test -z "$$dir" || $(MKDIR_P) "$$dir"; \
done
install: $(BUILT_SOURCES)
@ -4806,8 +4712,6 @@ distclean-generic:
-test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES)
-rm -f aarch64/$(DEPDIR)/$(am__dirstamp)
-rm -f aarch64/$(am__dirstamp)
-rm -f arm/$(DEPDIR)/$(am__dirstamp)
-rm -f arm/$(am__dirstamp)
-rm -f avr/$(DEPDIR)/$(am__dirstamp)
-rm -f avr/$(am__dirstamp)
-rm -f bfin/$(DEPDIR)/$(am__dirstamp)
@ -4887,7 +4791,7 @@ clean-am: clean-checkPROGRAMS clean-generic clean-libtool \
distclean: distclean-am
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
-rm -rf aarch64/$(DEPDIR) arm/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
-rm -rf aarch64/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
-rm -f Makefile
distclean-am: clean-am distclean-DEJAGNU distclean-compile \
distclean-generic distclean-hdr distclean-libtool \
@ -4905,7 +4809,7 @@ info: info-am
info-am:
install-data-am: install-armdocDATA install-data-local install-dtbDATA \
install-data-am: install-data-local install-dtbDATA \
install-erc32docDATA install-frvdocDATA install-or1kdocDATA \
install-pkgincludeHEADERS install-ppcdocDATA install-rxdocDATA
@ -4938,7 +4842,7 @@ installcheck-am:
maintainer-clean: maintainer-clean-am
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
-rm -rf $(top_srcdir)/autom4te.cache
-rm -rf aarch64/$(DEPDIR) arm/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
-rm -rf aarch64/$(DEPDIR) avr/$(DEPDIR) bfin/$(DEPDIR) bpf/$(DEPDIR) common/$(DEPDIR) cr16/$(DEPDIR) cris/$(DEPDIR) d10v/$(DEPDIR) erc32/$(DEPDIR) example-synacor/$(DEPDIR) frv/$(DEPDIR) ft32/$(DEPDIR) h8300/$(DEPDIR) igen/$(DEPDIR) iq2000/$(DEPDIR) lm32/$(DEPDIR) m32c/$(DEPDIR) m32r/$(DEPDIR) m68hc11/$(DEPDIR) mcore/$(DEPDIR) microblaze/$(DEPDIR) mips/$(DEPDIR) mn10300/$(DEPDIR) moxie/$(DEPDIR) msp430/$(DEPDIR) or1k/$(DEPDIR) ppc/$(DEPDIR) pru/$(DEPDIR) riscv/$(DEPDIR) rl78/$(DEPDIR) rx/$(DEPDIR) sh/$(DEPDIR) testsuite/common/$(DEPDIR) v850/$(DEPDIR)
-rm -f Makefile
maintainer-clean-am: distclean-am maintainer-clean-generic
@ -4955,10 +4859,10 @@ ps: ps-am
ps-am:
uninstall-am: uninstall-armdocDATA uninstall-dtbDATA \
uninstall-erc32docDATA uninstall-frvdocDATA uninstall-local \
uninstall-or1kdocDATA uninstall-pkgincludeHEADERS \
uninstall-ppcdocDATA uninstall-rxdocDATA
uninstall-am: uninstall-dtbDATA uninstall-erc32docDATA \
uninstall-frvdocDATA uninstall-local uninstall-or1kdocDATA \
uninstall-pkgincludeHEADERS uninstall-ppcdocDATA \
uninstall-rxdocDATA
.MAKE: all check check-am install install-am install-strip
@ -4969,8 +4873,8 @@ uninstall-am: uninstall-armdocDATA uninstall-dtbDATA \
distclean distclean-DEJAGNU distclean-compile \
distclean-generic distclean-hdr distclean-libtool \
distclean-tags dvi dvi-am html html-am info info-am install \
install-am install-armdocDATA install-data install-data-am \
install-data-local install-dtbDATA install-dvi install-dvi-am \
install-am install-data install-data-am install-data-local \
install-dtbDATA install-dvi install-dvi-am \
install-erc32docDATA install-exec install-exec-am \
install-exec-local install-frvdocDATA install-html \
install-html-am install-info install-info-am install-man \
@ -4980,11 +4884,10 @@ uninstall-am: uninstall-armdocDATA uninstall-dtbDATA \
installcheck-am installdirs maintainer-clean \
maintainer-clean-generic mostlyclean mostlyclean-compile \
mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
recheck tags tags-am uninstall uninstall-am \
uninstall-armdocDATA uninstall-dtbDATA uninstall-erc32docDATA \
uninstall-frvdocDATA uninstall-local uninstall-or1kdocDATA \
uninstall-pkgincludeHEADERS uninstall-ppcdocDATA \
uninstall-rxdocDATA
recheck tags tags-am uninstall uninstall-am uninstall-dtbDATA \
uninstall-erc32docDATA uninstall-frvdocDATA uninstall-local \
uninstall-or1kdocDATA uninstall-pkgincludeHEADERS \
uninstall-ppcdocDATA uninstall-rxdocDATA
.PRECIOUS: Makefile
@ -5166,12 +5069,6 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_aarch64_TRUE@-@am__include@ aarch64/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_arm_TRUE@$(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD): arm/hw-config.h
@SIM_ENABLE_ARCH_arm_TRUE@arm/modules.o: arm/modules.c
@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_arm_TRUE@-@am__include@ arm/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_avr_TRUE@$(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD): avr/hw-config.h
@SIM_ENABLE_ARCH_avr_TRUE@avr/modules.o: avr/modules.c

2018
sim/arm/ChangeLog-2021
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File diff suppressed because it is too large Load diff

27
sim/arm/README
View file

@ -1,27 +0,0 @@
This directory contains the standard release of the ARMulator from
Advanced RISC Machines, and was ftp'd from.
ftp.cl.cam.ac.uk:/arm/gnu
It likes to use TCP/IP between the simulator and the host, which is
nice, but is a pain to use under anything non-unix.
I've added created a new Makefile.in (the original in Makefile.orig)
to build a version of the simulator without the TCP/IP stuff, and a
wrapper.c to link directly into gdb and the run command.
It should be possible (barring major changes in the layout of
the armulator) to upgrade the simulator by copying all the files
out of a release into this directory and renaming the Makefile.
(Except that I changed armos.c to work more simply with our
simulator rigs)
Steve
sac@cygnus.com
Mon May 15 12:03:28 PDT 1995

26
sim/arm/arm-sim.h
View file

@ -1,26 +0,0 @@
/* Simulation code for the ARM processor.
Copyright (C) 2009-2024 Free Software Foundation, Inc.
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef ARM_SIM_H
#define ARM_SIM_H
#include "armdefs.h"
extern struct ARMul_State *state;
#endif

1429
sim/arm/armcopro.c
View file

File diff suppressed because it is too large Load diff

426
sim/arm/armdefs.h
View file

@ -1,426 +0,0 @@
/* armdefs.h -- ARMulator common definitions: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
#ifndef ARMDEFS_H
#define ARMDEFS_H
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <ansidecl.h>
#define FALSE 0
#define TRUE 1
#define LOW 0
#define HIGH 1
#define LOWHIGH 1
#define HIGHLOW 2
typedef uint32_t ARMword;
typedef int32_t ARMsword;
typedef uint64_t ARMdword;
typedef int64_t ARMsdword;
typedef struct ARMul_State ARMul_State;
typedef unsigned ARMul_CPInits (ARMul_State * state);
typedef unsigned ARMul_CPExits (ARMul_State * state);
typedef unsigned ARMul_LDCs (ARMul_State * state, unsigned type,
ARMword instr, ARMword value);
typedef unsigned ARMul_STCs (ARMul_State * state, unsigned type,
ARMword instr, ARMword * value);
typedef unsigned ARMul_MRCs (ARMul_State * state, unsigned type,
ARMword instr, ARMword * value);
typedef unsigned ARMul_MCRs (ARMul_State * state, unsigned type,
ARMword instr, ARMword value);
typedef unsigned ARMul_CDPs (ARMul_State * state, unsigned type,
ARMword instr);
typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
ARMword * value);
typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
ARMword value);
typedef double ARMdval; /* FIXME: Must be a 64-bit floating point type. */
typedef float ARMfval; /* FIXME: Must be a 32-bit floating point type. */
typedef union
{
ARMword uword[2];
ARMsword sword[2];
ARMfval fval[2];
ARMdword dword;
ARMdval dval;
} ARM_VFP_reg;
#define VFP_fval(N) (state->VFP_Reg[(N)>> 1].fval[(N) & 1])
#define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1])
#define VFP_sword(N) (state->VFP_Reg[(N)>> 1].sword[(N) & 1])
#define VFP_dval(N) (state->VFP_Reg[(N)].dval)
#define VFP_dword(N) (state->VFP_Reg[(N)].dword)
struct ARMul_State
{
ARMword Emulate; /* to start and stop emulation */
unsigned EndCondition; /* reason for stopping */
ARMword Reg[16]; /* the current register file */
ARMword RegBank[7][16]; /* all the registers */
/* 40 bit accumulator. We always keep this 64 bits wide,
and move only 40 bits out of it in an MRA insn. */
ARMdword Accumulator;
ARMword Cpsr; /* the current psr */
ARMword Spsr[7]; /* the exception psr's */
ARMword NFlag, ZFlag, CFlag, VFlag, IFFlags; /* dummy flags for speed */
ARMword SFlag;
#ifdef MODET
ARMword TFlag; /* Thumb state */
#endif
ARMword Bank; /* the current register bank */
ARMword Mode; /* the current mode */
ARMword instr, pc, temp; /* saved register state */
ARMword loaded, decoded; /* saved pipeline state */
unsigned long NumScycles, NumNcycles, NumIcycles, NumCcycles, NumFcycles; /* emulated cycles used */
unsigned long NumInstrs; /* the number of instructions executed */
unsigned NextInstr;
unsigned VectorCatch; /* caught exception mask */
unsigned CallDebug; /* set to call the debugger */
unsigned CanWatch; /* set by memory interface if its willing to suffer the
overhead of checking for watchpoints on each memory
access */
unsigned MemReadDebug, MemWriteDebug;
unsigned long StopHandle;
unsigned char *MemDataPtr; /* admin data */
unsigned char *MemInPtr; /* the Data In bus */
unsigned char *MemOutPtr; /* the Data Out bus (which you may not need */
unsigned char *MemSparePtr; /* extra space */
ARMword MemSize;
unsigned char *OSptr; /* OS Handle */
char *CommandLine; /* Command Line from ARMsd */
ARMul_CPInits *CPInit[16]; /* coprocessor initialisers */
ARMul_CPExits *CPExit[16]; /* coprocessor finalisers */
ARMul_LDCs *LDC[16]; /* LDC instruction */
ARMul_STCs *STC[16]; /* STC instruction */
ARMul_MRCs *MRC[16]; /* MRC instruction */
ARMul_MCRs *MCR[16]; /* MCR instruction */
ARMul_CDPs *CDP[16]; /* CDP instruction */
ARMul_CPReads *CPRead[16]; /* Read CP register */
ARMul_CPWrites *CPWrite[16]; /* Write CP register */
unsigned char *CPData[16]; /* Coprocessor data */
unsigned char const *CPRegWords[16]; /* map of coprocessor register sizes */
unsigned long LastTime; /* Value of last call to ARMul_Time() */
ARMword CP14R0_CCD; /* used to count 64 clock cycles with CP14 R0 bit
3 set */
unsigned EventSet; /* the number of events in the queue */
unsigned long Now; /* time to the nearest cycle */
struct EventNode **EventPtr; /* the event list */
unsigned Exception; /* enable the next four values */
unsigned Debug; /* show instructions as they are executed */
unsigned NresetSig; /* reset the processor */
unsigned NfiqSig;
unsigned NirqSig;
unsigned abortSig;
unsigned NtransSig;
unsigned bigendSig;
unsigned prog32Sig;
unsigned data32Sig;
unsigned lateabtSig;
ARMword Vector; /* synthesize aborts in cycle modes */
ARMword Aborted; /* sticky flag for aborts */
ARMword Reseted; /* sticky flag for Reset */
ARMword Inted, LastInted; /* sticky flags for interrupts */
ARMword Base; /* extra hand for base writeback */
ARMword AbortAddr; /* to keep track of Prefetch aborts */
const struct Dbg_HostosInterface *hostif;
unsigned is_v4; /* Are we emulating a v4 architecture (or higher) ? */
unsigned is_v5; /* Are we emulating a v5 architecture ? */
unsigned is_v5e; /* Are we emulating a v5e architecture ? */
unsigned is_v6; /* Are we emulating a v6 architecture ? */
unsigned is_XScale; /* Are we emulating an XScale architecture ? */
unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
unsigned verbose; /* Print various messages like the banner */
ARM_VFP_reg VFP_Reg[32]; /* Advanced SIMD registers. */
ARMword FPSCR; /* Floating Point Status Register. */
};
/***************************************************************************\
* Properties of ARM we know about *
\***************************************************************************/
/* The bitflags */
#define ARM_Fix26_Prop 0x01
#define ARM_Nexec_Prop 0x02
#define ARM_Debug_Prop 0x10
#define ARM_Isync_Prop ARM_Debug_Prop
#define ARM_Lock_Prop 0x20
#define ARM_v4_Prop 0x40
#define ARM_v5_Prop 0x80
#define ARM_v5e_Prop 0x100
#define ARM_XScale_Prop 0x200
#define ARM_ep9312_Prop 0x400
#define ARM_iWMMXt_Prop 0x800
#define ARM_v6_Prop 0x1000
/***************************************************************************\
* Macros to extract instruction fields *
\***************************************************************************/
#undef BIT /* common/sim-bits.h conflict :( */
#define BIT(n) ( (ARMword)(instr>>(n))&1) /* bit n of instruction */
#define BITS(m,n) ( (ARMword)(instr<<(31-(n))) >> ((31-(n))+(m)) ) /* bits m to n of instr */
#define TOPBITS(n) (instr >> (n)) /* bits 31 to n of instr */
/***************************************************************************\
* The hardware vector addresses *
\***************************************************************************/
#define ARMResetV 0L
#define ARMUndefinedInstrV 4L
#define ARMSWIV 8L
#define ARMPrefetchAbortV 12L
#define ARMDataAbortV 16L
#define ARMAddrExceptnV 20L
#define ARMIRQV 24L
#define ARMFIQV 28L
#define ARMErrorV 32L /* This is an offset, not an address ! */
#define ARMul_ResetV ARMResetV
#define ARMul_UndefinedInstrV ARMUndefinedInstrV
#define ARMul_SWIV ARMSWIV
#define ARMul_PrefetchAbortV ARMPrefetchAbortV
#define ARMul_DataAbortV ARMDataAbortV
#define ARMul_AddrExceptnV ARMAddrExceptnV
#define ARMul_IRQV ARMIRQV
#define ARMul_FIQV ARMFIQV
/***************************************************************************\
* Mode and Bank Constants *
\***************************************************************************/
#define USER26MODE 0L
#define FIQ26MODE 1L
#define IRQ26MODE 2L
#define SVC26MODE 3L
#define USER32MODE 16L
#define FIQ32MODE 17L
#define IRQ32MODE 18L
#define SVC32MODE 19L
#define ABORT32MODE 23L
#define UNDEF32MODE 27L
#define SYSTEMMODE 31L
#define ARM32BITMODE (state->Mode > 3)
#define ARM26BITMODE (state->Mode <= 3)
#define ARMMODE (state->Mode)
#define ARMul_MODEBITS 0x1fL
#define ARMul_MODE32BIT ARM32BITMODE
#define ARMul_MODE26BIT ARM26BITMODE
#define USERBANK 0
#define FIQBANK 1
#define IRQBANK 2
#define SVCBANK 3
#define ABORTBANK 4
#define UNDEFBANK 5
#define DUMMYBANK 6
#define SYSTEMBANK USERBANK
#define BANK_CAN_ACCESS_SPSR(bank) \
((bank) != USERBANK && (bank) != SYSTEMBANK && (bank) != DUMMYBANK)
/***************************************************************************\
* Definitons of things in the emulator *
\***************************************************************************/
extern void ARMul_EmulateInit (void);
extern ARMul_State *ARMul_NewState (void);
extern void ARMul_Reset (ARMul_State * state);
extern ARMword ARMul_DoProg (ARMul_State * state);
extern ARMword ARMul_DoInstr (ARMul_State * state);
/***************************************************************************\
* Definitons of things for event handling *
\***************************************************************************/
extern void ARMul_ScheduleEvent (ARMul_State * state, unsigned long delay,
unsigned (*func) ());
extern void ARMul_EnvokeEvent (ARMul_State * state);
extern unsigned long ARMul_Time (ARMul_State * state);
/***************************************************************************\
* Useful support routines *
\***************************************************************************/
extern ARMword ARMul_GetReg (ARMul_State * state, unsigned mode,
unsigned reg);
extern void ARMul_SetReg (ARMul_State * state, unsigned mode, unsigned reg,
ARMword value);
extern ARMword ARMul_GetPC (ARMul_State * state);
extern ARMword ARMul_GetNextPC (ARMul_State * state);
extern void ARMul_SetPC (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetR15 (ARMul_State * state);
extern void ARMul_SetR15 (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetCPSR (ARMul_State * state);
extern void ARMul_SetCPSR (ARMul_State * state, ARMword value);
extern ARMword ARMul_GetSPSR (ARMul_State * state, ARMword mode);
extern void ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value);
/***************************************************************************\
* Definitons of things to handle aborts *
\***************************************************************************/
extern void ARMul_Abort (ARMul_State * state, ARMword address);
#define ARMul_ABORTWORD 0xefffffff /* SWI -1 */
#define ARMul_PREFETCHABORT(address) if (state->AbortAddr == 1) \
state->AbortAddr = (address & ~3L)
#define ARMul_DATAABORT(address) state->abortSig = HIGH ; \
state->Aborted = ARMul_DataAbortV ;
#define ARMul_CLEARABORT state->abortSig = LOW
/***************************************************************************\
* Definitons of things in the memory interface *
\***************************************************************************/
extern unsigned ARMul_MemoryInit (ARMul_State * state,
unsigned long initmemsize);
extern void ARMul_MemoryExit (ARMul_State * state);
extern ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address,
ARMword isize);
extern ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address,
ARMword isize);
extern ARMword ARMul_ReLoadInstr (ARMul_State * state, ARMword address,
ARMword isize);
extern ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address);
extern ARMword ARMul_LoadByte (ARMul_State * state, ARMword address);
extern void ARMul_StoreWordS (ARMul_State * state, ARMword address,
ARMword data);
extern void ARMul_StoreWordN (ARMul_State * state, ARMword address,
ARMword data);
extern void ARMul_StoreHalfWord (ARMul_State * state, ARMword address,
ARMword data);
extern void ARMul_StoreByte (ARMul_State * state, ARMword address,
ARMword data);
extern ARMword ARMul_SwapWord (ARMul_State * state, ARMword address,
ARMword data);
extern ARMword ARMul_SwapByte (ARMul_State * state, ARMword address,
ARMword data);
extern void ARMul_Icycles (ARMul_State * state, unsigned number,
ARMword address);
extern void ARMul_Ccycles (ARMul_State * state, unsigned number,
ARMword address);
extern ARMword ARMul_ReadWord (ARMul_State * state, ARMword address);
extern ARMword ARMul_ReadByte (ARMul_State * state, ARMword address);
extern ARMword ARMul_SafeReadByte (ARMul_State * state, ARMword address);
extern void ARMul_WriteWord (ARMul_State * state, ARMword address,
ARMword data);
extern void ARMul_WriteByte (ARMul_State * state, ARMword address,
ARMword data);
extern void ARMul_SafeWriteByte (ARMul_State * state, ARMword address,
ARMword data);
extern ARMword ARMul_MemAccess (ARMul_State * state, ARMword, ARMword,
ARMword, ARMword, ARMword, ARMword, ARMword,
ARMword, ARMword, ARMword);
/***************************************************************************\
* Definitons of things in the co-processor interface *
\***************************************************************************/
#define ARMul_FIRST 0
#define ARMul_TRANSFER 1
#define ARMul_BUSY 2
#define ARMul_DATA 3
#define ARMul_INTERRUPT 4
#define ARMul_DONE 0
#define ARMul_CANT 1
#define ARMul_INC 3
#define ARMul_CP13_R0_FIQ 0x1
#define ARMul_CP13_R0_IRQ 0x2
#define ARMul_CP13_R8_PMUS 0x1
#define ARMul_CP14_R0_ENABLE 0x0001
#define ARMul_CP14_R0_CLKRST 0x0004
#define ARMul_CP14_R0_CCD 0x0008
#define ARMul_CP14_R0_INTEN0 0x0010
#define ARMul_CP14_R0_INTEN1 0x0020
#define ARMul_CP14_R0_INTEN2 0x0040
#define ARMul_CP14_R0_FLAG0 0x0100
#define ARMul_CP14_R0_FLAG1 0x0200
#define ARMul_CP14_R0_FLAG2 0x0400
#define ARMul_CP14_R10_MOE_IB 0x0004
#define ARMul_CP14_R10_MOE_DB 0x0008
#define ARMul_CP14_R10_MOE_BT 0x000c
#define ARMul_CP15_R1_ENDIAN 0x0080
#define ARMul_CP15_R1_ALIGN 0x0002
#define ARMul_CP15_R5_X 0x0400
#define ARMul_CP15_R5_ST_ALIGN 0x0001
#define ARMul_CP15_R5_IMPRE 0x0406
#define ARMul_CP15_R5_MMU_EXCPT 0x0400
#define ARMul_CP15_DBCON_M 0x0100
#define ARMul_CP15_DBCON_E1 0x000c
#define ARMul_CP15_DBCON_E0 0x0003
extern unsigned ARMul_CoProInit (ARMul_State * state);
extern void ARMul_CoProExit (ARMul_State * state);
extern void ARMul_CoProAttach (ARMul_State * state, unsigned number,
ARMul_CPInits * init, ARMul_CPExits * exit,
ARMul_LDCs * ldc, ARMul_STCs * stc,
ARMul_MRCs * mrc, ARMul_MCRs * mcr,
ARMul_CDPs * cdp,
ARMul_CPReads * read, ARMul_CPWrites * write);
extern void ARMul_CoProDetach (ARMul_State * state, unsigned number);
extern void XScale_check_memacc (ARMul_State * state, ARMword * address,
int store);
extern void XScale_set_fsr_far (ARMul_State * state, ARMword fsr, ARMword far);
extern int XScale_debug_moe (ARMul_State * state, int moe);
/***************************************************************************\
* Definitons of things in the host environment *
\***************************************************************************/
extern unsigned ARMul_OSInit (ARMul_State * state);
extern unsigned ARMul_OSHandleSWI (ARMul_State * state, ARMword number);
/***************************************************************************\
* Host-dependent stuff *
\***************************************************************************/
extern void ARMul_UndefInstr (ARMul_State *, ARMword);
extern void ARMul_FixCPSR (ARMul_State *, ARMword, ARMword);
extern void ARMul_FixSPSR (ARMul_State *, ARMword, ARMword);
extern void ARMul_ConsolePrint (ARMul_State *, const char *, ...)
ATTRIBUTE_PRINTF (2, 3);
extern void ARMul_SelectProcessor (ARMul_State *, unsigned);
#endif

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sim/arm/armemu.c
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sim/arm/armemu.h
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/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
#include "armdefs.h"
extern ARMword isize;
extern int trace;
extern int disas;
extern int trace_funcs;
extern void print_insn (ARMword);
/* Condition code values. */
#define EQ 0
#define NE 1
#define CS 2
#define CC 3
#define MI 4
#define PL 5
#define VS 6
#define VC 7
#define HI 8
#define LS 9
#define GE 10
#define LT 11
#define GT 12
#define LE 13
#define AL 14
#define NV 15
/* Shift Opcodes. */
#define LSL 0
#define LSR 1
#define ASR 2
#define ROR 3
/* Macros to twiddle the status flags and mode. */
#define NBIT ((unsigned)1L << 31)
#define ZBIT (1L << 30)
#define CBIT (1L << 29)
#define VBIT (1L << 28)
#define SBIT (1L << 27)
#define GE0 (1L << 16)
#define GE1 (1L << 17)
#define GE2 (1L << 18)
#define GE3 (1L << 19)
#define IBIT (1L << 7)
#define FBIT (1L << 6)
#define IFBITS (3L << 6)
#define R15IBIT (1L << 27)
#define R15FBIT (1L << 26)
#define R15IFBITS (3L << 26)
#define POS(i) ( (~(i)) >> 31 )
#define NEG(i) ( (i) >> 31 )
#ifdef MODET /* Thumb support. */
/* ??? This bit is actually in the low order bit of the PC in the hardware.
It isn't clear if the simulator needs to model that or not. */
#define TBIT (1L << 5)
#define TFLAG state->TFlag
#define SETT state->TFlag = 1
#define CLEART state->TFlag = 0
#define ASSIGNT(res) state->TFlag = res
#define INSN_SIZE (TFLAG ? 2 : 4)
#else
#define INSN_SIZE 4
#endif
#define NFLAG state->NFlag
#define SETN state->NFlag = 1
#define CLEARN state->NFlag = 0
#define ASSIGNN(res) state->NFlag = res
#define ZFLAG state->ZFlag
#define SETZ state->ZFlag = 1
#define CLEARZ state->ZFlag = 0
#define ASSIGNZ(res) state->ZFlag = res
#define CFLAG state->CFlag
#define SETC state->CFlag = 1
#define CLEARC state->CFlag = 0
#define ASSIGNC(res) state->CFlag = res
#define VFLAG state->VFlag
#define SETV state->VFlag = 1
#define CLEARV state->VFlag = 0
#define ASSIGNV(res) state->VFlag = res
#define SFLAG state->SFlag
#define SETS state->SFlag = 1
#define CLEARS state->SFlag = 0
#define ASSIGNS(res) state->SFlag = res
#define IFLAG (state->IFFlags >> 1)
#define FFLAG (state->IFFlags & 1)
#define IFFLAGS state->IFFlags
#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
#define PSR_FBITS (0xff000000L)
#define PSR_SBITS (0x00ff0000L)
#define PSR_XBITS (0x0000ff00L)
#define PSR_CBITS (0x000000ffL)
#if defined MODE32 || defined MODET
#define CCBITS (0xf8000000L)
#else
#define CCBITS (0xf0000000L)
#endif
#define INTBITS (0xc0L)
#if defined MODET && defined MODE32
#define PCBITS (0xffffffffL)
#else
#define PCBITS (0xfffffffcL)
#endif
#define MODEBITS (0x1fL)
#define R15INTBITS (3L << 26)
#if defined MODET && defined MODE32
#define R15PCBITS (0x03ffffffL)
#else
#define R15PCBITS (0x03fffffcL)
#endif
#define R15PCMODEBITS (0x03ffffffL)
#define R15MODEBITS (0x3L)
#ifdef MODE32
#define PCMASK PCBITS
#define PCWRAP(pc) (pc)
#else
#define PCMASK R15PCBITS
#define PCWRAP(pc) ((pc) & R15PCBITS)
#endif
#define PC (state->Reg[15] & PCMASK)
#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
#define R15INT (state->Reg[15] & R15INTBITS)
#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
#define R15PC (state->Reg[15] & R15PCBITS)
#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
#define R15MODE (state->Reg[15] & R15MODEBITS)
#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27))
#define EINT (IFFLAGS << 6)
#define ER15INT (IFFLAGS << 26)
#define EMODE (state->Mode)
#ifdef MODET
#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
#else
#define CPSR (ECC | EINT | EMODE)
#endif
#ifdef MODE32
#define PATCHR15
#else
#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
#endif
#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE))
#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS)
#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS)
#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS)
#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS)
#define SETR15PSR(s) \
do \
{ \
if (state->Mode == USER26MODE) \
{ \
state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \
ASSIGNN ((state->Reg[15] & NBIT) != 0); \
ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \
ASSIGNC ((state->Reg[15] & CBIT) != 0); \
ASSIGNV ((state->Reg[15] & VBIT) != 0); \
} \
else \
{ \
state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \
ARMul_R15Altered (state); \
} \
} \
while (0)
#define SETABORT(i, m, d) \
do \
{ \
int SETABORT_mode = (m); \
\
ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \
ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \
| (i) | SETABORT_mode)); \
state->Reg[14] = temp - (d); \
} \
while (0)
#ifndef MODE32
#define VECTORS 0x20
#define LEGALADDR 0x03ffffff
#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
#endif
#define INTERNALABORT(address) \
do \
{ \
if (address < VECTORS) \
state->Aborted = ARMul_DataAbortV; \
else \
state->Aborted = ARMul_AddrExceptnV; \
} \
while (0)
#ifdef MODE32
#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV)
#else
#define TAKEABORT \
do \
{ \
if (state->Aborted == ARMul_AddrExceptnV) \
ARMul_Abort (state, ARMul_AddrExceptnV); \
else \
ARMul_Abort (state, ARMul_DataAbortV); \
} \
while (0)
#endif
#define CPTAKEABORT \
do \
{ \
if (!state->Aborted) \
ARMul_Abort (state, ARMul_UndefinedInstrV); \
else if (state->Aborted == ARMul_AddrExceptnV) \
ARMul_Abort (state, ARMul_AddrExceptnV); \
else \
ARMul_Abort (state, ARMul_DataAbortV); \
} \
while (0);
/* Different ways to start the next instruction. */
#define SEQ 0
#define NONSEQ 1
#define PCINCEDSEQ 2
#define PCINCEDNONSEQ 3
#define PRIMEPIPE 4
#define RESUME 8
#define NORMALCYCLE state->NextInstr = 0
#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */
#define BUSUSEDINCPCS \
do \
{ \
if (! state->is_v4) \
{ \
/* A standard PC inc and an S cycle. */ \
state->Reg[15] += isize; \
state->NextInstr = (state->NextInstr & 0xff) | 2; \
} \
} \
while (0)
#define BUSUSEDINCPCN \
do \
{ \
if (state->is_v4) \
BUSUSEDN; \
else \
{ \
/* A standard PC inc and an N cycle. */ \
state->Reg[15] += isize; \
state->NextInstr |= 3; \
} \
} \
while (0)
#define INCPC \
do \
{ \
/* A standard PC inc. */ \
state->Reg[15] += isize; \
state->NextInstr |= 2; \
} \
while (0)
#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
/* Cycle based emulation. */
#define OUTPUTCP(i,a,b)
#define NCYCLE
#define SCYCLE
#define ICYCLE
#define CCYCLE
#define NEXTCYCLE(c)
/* Macros to extract parts of instructions. */
#define DESTReg (BITS (12, 15))
#define LHSReg (BITS (16, 19))
#define RHSReg (BITS ( 0, 3))
#define DEST (state->Reg[DESTReg])
#ifdef MODE32
#ifdef MODET
#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
#else
#define LHS (state->Reg[LHSReg])
#endif
#else
#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]))
#endif
#define MULDESTReg (BITS (16, 19))
#define MULLHSReg (BITS ( 0, 3))
#define MULRHSReg (BITS ( 8, 11))
#define MULACCReg (BITS (12, 15))
#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)])
#define DPSImmRHS temp = BITS(0,11) ; \
rhs = ARMul_ImmedTable[temp] ; \
if (temp > 255) /* There was a shift. */ \
ASSIGNC (rhs >> 31) ;
#ifdef MODE32
#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
: GetDPRegRHS (state, instr))
#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \
: GetDPSRegRHS (state, instr))
#else
#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
: GetDPRegRHS (state, instr))
#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
: GetDPSRegRHS (state, instr))
#endif
#define LSBase state->Reg[LHSReg]
#define LSImmRHS (BITS(0,11))
#ifdef MODE32
#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \
: GetLSRegRHS (state, instr))
#else
#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \
: GetLSRegRHS (state, instr))
#endif
#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \
(ARMword) ARMul_BitList[BITS (8, 15)] )
#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \
(BIT (LHSReg) && BITS (0, LHSReg - 1) == 0))
#define SWAPSRC (state->Reg[RHSReg])
#define LSCOff (BITS (0, 7) << 2)
#define CPNum BITS (8, 11)
/* Determine if access to coprocessor CP is permitted.
The XScale has a register in CP15 which controls access to CP0 - CP13. */
#define CP_ACCESS_ALLOWED(STATE, CP) \
( ((CP) >= 14) \
|| (! (STATE)->is_XScale) \
|| (read_cp15_reg (15, 0, 1) & (1 << (CP))))
/* Macro to rotate n right by b bits. */
#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b))))
/* Macros to store results of instructions. */
#define WRITEDEST(d) \
do \
{ \
if (DESTReg == 15) \
WriteR15 (state, d); \
else \
DEST = d; \
} \
while (0)
#define WRITESDEST(d) \
do \
{ \
if (DESTReg == 15) \
WriteSR15 (state, d); \
else \
{ \
DEST = d; \
ARMul_NegZero (state, d); \
} \
} \
while (0)
#define WRITEDESTB(d) \
do \
{ \
if (DESTReg == 15) \
WriteR15Load (state, d); \
else \
DEST = d; \
} \
while (0)
#define BYTETOBUS(data) ((data & 0xff) | \
((data & 0xff) << 8) | \
((data & 0xff) << 16) | \
((data & 0xff) << 24))
#define BUSTOBYTE(address, data) \
do \
{ \
if (state->bigendSig) \
temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \
else \
temp = (data >> ((address & 3) << 3)) & 0xff; \
} \
while (0)
#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb)
#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb)
#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb)
#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb)
#define POSBRANCH ((instr & 0x7fffff) << 2)
#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2)
/* Values for Emulate. */
#define STOP 0 /* stop */
#define CHANGEMODE 1 /* change mode */
#define ONCE 2 /* execute just one interation */
#define RUN 3 /* continuous execution */
/* Stuff that is shared across modes. */
extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */
extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */
extern char ARMul_BitList[]; /* Number of bits in a byte table. */
#define EVENTLISTSIZE 1024L
/* Thumb support. */
typedef enum
{
t_undefined, /* Undefined Thumb instruction. */
t_decoded, /* Instruction decoded to ARM equivalent. */
t_branch /* Thumb branch (already processed). */
}
tdstate;
#define t_resolved t_branch
/* Macros to scrutinize instructions. The dummy do loop is to keep the compiler
happy when the statement is used in an otherwise empty else statement. */
#define UNDEF_Test do { ; } while (0)
#define UNDEF_Shift do { ; } while (0)
#define UNDEF_MSRPC do { ; } while (0)
#define UNDEF_MRSPC do { ; } while (0)
#define UNDEF_MULPCDest do { ; } while (0)
#define UNDEF_MULDestEQOp1 do { ; } while (0)
#define UNDEF_LSRBPC do { ; } while (0)
#define UNDEF_LSRBaseEQOffWb do { ; } while (0)
#define UNDEF_LSRBaseEQDestWb do { ; } while (0)
#define UNDEF_LSRPCBaseWb do { ; } while (0)
#define UNDEF_LSRPCOffWb do { ; } while (0)
#define UNDEF_LSMNoRegs do { ; } while (0)
#define UNDEF_LSMPCBase do { ; } while (0)
#define UNDEF_LSMUserBankWb do { ; } while (0)
#define UNDEF_LSMBaseInListWb do { ; } while (0)
#define UNDEF_SWPPC do { ; } while (0)
#define UNDEF_CoProHS do { ; } while (0)
#define UNDEF_MCRPC do { ; } while (0)
#define UNDEF_LSCPCBaseWb do { ; } while (0)
#define UNDEF_UndefNotBounced do { ; } while (0)
#define UNDEF_ShortInt do { ; } while (0)
#define UNDEF_IllegalMode do { ; } while (0)
#define UNDEF_Prog32SigChange do { ; } while (0)
#define UNDEF_Data32SigChange do { ; } while (0)
/* Prototypes for exported functions. */
extern unsigned ARMul_NthReg (ARMword, unsigned);
extern int AddOverflow (ARMword, ARMword, ARMword);
extern int SubOverflow (ARMword, ARMword, ARMword);
extern ARMword ARMul_Emulate26 (ARMul_State *);
extern ARMword ARMul_Emulate32 (ARMul_State *);
extern unsigned IntPending (ARMul_State *);
extern void ARMul_CPSRAltered (ARMul_State *);
extern void ARMul_R15Altered (ARMul_State *);
extern ARMword ARMul_GetPC (ARMul_State *);
extern ARMword ARMul_GetNextPC (ARMul_State *);
extern ARMword ARMul_GetR15 (ARMul_State *);
extern ARMword ARMul_GetCPSR (ARMul_State *);
extern void ARMul_EnvokeEvent (ARMul_State *);
extern unsigned long ARMul_Time (ARMul_State *);
extern void ARMul_NegZero (ARMul_State *, ARMword);
extern void ARMul_SetPC (ARMul_State *, ARMword);
extern void ARMul_SetR15 (ARMul_State *, ARMword);
extern void ARMul_SetCPSR (ARMul_State *, ARMword);
extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword);
extern void ARMul_Abort26 (ARMul_State *, ARMword);
extern void ARMul_Abort32 (ARMul_State *, ARMword);
extern ARMword ARMul_MRC (ARMul_State *, ARMword);
extern void ARMul_CDP (ARMul_State *, ARMword);
extern void ARMul_LDC (ARMul_State *, ARMword, ARMword);
extern void ARMul_STC (ARMul_State *, ARMword, ARMword);
extern void ARMul_MCR (ARMul_State *, ARMword, ARMword);
extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword);
extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword);
extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword);
extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword);
extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword);
extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword);
extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword);
extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword);
extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *);
extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned);
extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword);
extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *));
/* Coprocessor support functions. */
extern unsigned ARMul_CoProInit (ARMul_State *);
extern void ARMul_CoProExit (ARMul_State *);
extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *,
ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *,
ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *);
extern void ARMul_CoProDetach (ARMul_State *, unsigned);
extern ARMword read_cp15_reg (unsigned, unsigned, unsigned);
extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword);
extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword);

18
sim/arm/armemu32.c
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@ -1,18 +0,0 @@
/* Build armemu.c with ARM32 support.
Copyright (C) 1995-2024 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <https://www.gnu.org/licenses/>. */
#define MODE32
#include "armemu.c"

1350
sim/arm/armfpe.h
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File diff suppressed because it is too large Load diff

355
sim/arm/arminit.c
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@ -1,355 +0,0 @@
/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* This must come before any other includes. */
#include "defs.h"
#include <string.h>
#include "armdefs.h"
#include "armemu.h"
#include "dbg_rdi.h"
/***************************************************************************\
* Definitions for the emulator architecture *
\***************************************************************************/
void ARMul_EmulateInit (void);
ARMul_State *ARMul_NewState (void);
void ARMul_Reset (ARMul_State * state);
ARMword ARMul_DoCycle (ARMul_State * state);
unsigned ARMul_DoCoPro (ARMul_State * state);
ARMword ARMul_DoProg (ARMul_State * state);
ARMword ARMul_DoInstr (ARMul_State * state);
void ARMul_Abort (ARMul_State * state, ARMword address);
unsigned ARMul_MultTable[32] =
{ 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9,
10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16
};
ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */
char ARMul_BitList[256]; /* number of bits in a byte table */
/* The PC pipeline value depends on whether ARM
or Thumb instructions are being executed. */
ARMword isize;
/***************************************************************************\
* Call this routine once to set up the emulator's tables. *
\***************************************************************************/
void
ARMul_EmulateInit (void)
{
unsigned long i, j;
for (i = 0; i < 4096; i++)
{ /* the values of 12 bit dp rhs's */
ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL);
}
for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */
for (j = 1; j < 256; j <<= 1)
for (i = 0; i < 256; i++)
if ((i & j) > 0)
ARMul_BitList[i]++;
for (i = 0; i < 256; i++)
ARMul_BitList[i] *= 4; /* you always need 4 times these values */
}
/***************************************************************************\
* Returns a new instantiation of the ARMulator's state *
\***************************************************************************/
ARMul_State *
ARMul_NewState (void)
{
ARMul_State *state;
unsigned i, j;
state = (ARMul_State *) malloc (sizeof (ARMul_State));
memset (state, 0, sizeof (ARMul_State));
state->Emulate = RUN;
for (i = 0; i < 16; i++)
{
state->Reg[i] = 0;
for (j = 0; j < 7; j++)
state->RegBank[j][i] = 0;
}
for (i = 0; i < 7; i++)
state->Spsr[i] = 0;
/* state->Mode = USER26MODE; */
state->Mode = USER32MODE;
state->CallDebug = FALSE;
state->Debug = FALSE;
state->VectorCatch = 0;
state->Aborted = FALSE;
state->Reseted = FALSE;
state->Inted = 3;
state->LastInted = 3;
state->MemDataPtr = NULL;
state->MemInPtr = NULL;
state->MemOutPtr = NULL;
state->MemSparePtr = NULL;
state->MemSize = 0;
state->OSptr = NULL;
state->CommandLine = NULL;
state->CP14R0_CCD = -1;
state->LastTime = 0;
state->EventSet = 0;
state->Now = 0;
state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE *
sizeof (struct EventNode
*));
for (i = 0; i < EVENTLISTSIZE; i++)
*(state->EventPtr + i) = NULL;
state->prog32Sig = HIGH;
state->data32Sig = HIGH;
state->lateabtSig = LOW;
state->bigendSig = LOW;
state->is_v4 = LOW;
state->is_v5 = LOW;
state->is_v5e = LOW;
state->is_XScale = LOW;
state->is_iWMMXt = LOW;
state->is_v6 = LOW;
ARMul_Reset (state);
return state;
}
/***************************************************************************\
Call this routine to set ARMulator to model certain processor properities
\***************************************************************************/
void
ARMul_SelectProcessor (ARMul_State * state, unsigned properties)
{
if (properties & ARM_Fix26_Prop)
{
state->prog32Sig = LOW;
state->data32Sig = LOW;
}
else
{
state->prog32Sig = HIGH;
state->data32Sig = HIGH;
}
state->lateabtSig = LOW;
state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW;
state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW;
state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW;
state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW;
state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW;
state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW;
state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW;
/* Only initialse the coprocessor support once we
know what kind of chip we are dealing with. */
ARMul_CoProInit (state);
}
/***************************************************************************\
* Call this routine to set up the initial machine state (or perform a RESET *
\***************************************************************************/
void
ARMul_Reset (ARMul_State * state)
{
state->NextInstr = 0;
if (state->prog32Sig)
{
state->Reg[15] = 0;
state->Cpsr = INTBITS | SVC32MODE;
state->Mode = SVC32MODE;
}
else
{
state->Reg[15] = R15INTBITS | SVC26MODE;
state->Cpsr = INTBITS | SVC26MODE;
state->Mode = SVC26MODE;
}
ARMul_CPSRAltered (state);
state->Bank = SVCBANK;
FLUSHPIPE;
state->EndCondition = 0;
state->Exception = FALSE;
state->NresetSig = HIGH;
state->NfiqSig = HIGH;
state->NirqSig = HIGH;
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
state->abortSig = LOW;
state->AbortAddr = 1;
state->NumInstrs = 0;
state->NumNcycles = 0;
state->NumScycles = 0;
state->NumIcycles = 0;
state->NumCcycles = 0;
state->NumFcycles = 0;
#ifdef ASIM
(void) ARMul_MemoryInit ();
ARMul_OSInit (state);
#endif
}
/***************************************************************************\
* Emulate the execution of an entire program. Start the correct emulator *
* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
* address of the last instruction that is executed. *
\***************************************************************************/
ARMword
ARMul_DoProg (ARMul_State * state)
{
ARMword pc = 0;
state->Emulate = RUN;
while (state->Emulate != STOP)
{
state->Emulate = RUN;
if (state->prog32Sig && ARMul_MODE32BIT)
pc = ARMul_Emulate32 (state);
else
pc = ARMul_Emulate26 (state);
}
return (pc);
}
/***************************************************************************\
* Emulate the execution of one instruction. Start the correct emulator *
* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
* address of the instruction that is executed. *
\***************************************************************************/
ARMword
ARMul_DoInstr (ARMul_State * state)
{
ARMword pc = 0;
state->Emulate = ONCE;
if (state->prog32Sig && ARMul_MODE32BIT)
pc = ARMul_Emulate32 (state);
else
pc = ARMul_Emulate26 (state);
return (pc);
}
/***************************************************************************\
* This routine causes an Abort to occur, including selecting the correct *
* mode, register bank, and the saving of registers. Call with the *
* appropriate vector's memory address (0,4,8 ....) *
\***************************************************************************/
void
ARMul_Abort (ARMul_State * state, ARMword vector)
{
ARMword temp;
int isize = INSN_SIZE;
int esize = (TFLAG ? 0 : 4);
int e2size = (TFLAG ? -4 : 0);
state->Aborted = FALSE;
if (state->prog32Sig)
if (ARMul_MODE26BIT)
temp = R15PC;
else
temp = state->Reg[15];
else
temp = R15PC | ECC | ER15INT | EMODE;
switch (vector)
{
case ARMul_ResetV: /* RESET */
SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0);
break;
case ARMul_UndefinedInstrV: /* Undefined Instruction */
SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize);
break;
case ARMul_SWIV: /* Software Interrupt */
SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize);
break;
case ARMul_PrefetchAbortV: /* Prefetch Abort */
state->AbortAddr = 1;
SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize);
break;
case ARMul_DataAbortV: /* Data Abort */
SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size);
break;
case ARMul_AddrExceptnV: /* Address Exception */
SETABORT (IBIT, SVC26MODE, isize);
break;
case ARMul_IRQV: /* IRQ */
if ( ! state->is_XScale
|| ! state->CPRead[13] (state, 0, & temp)
|| (temp & ARMul_CP13_R0_IRQ))
SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize);
break;
case ARMul_FIQV: /* FIQ */
if ( ! state->is_XScale
|| ! state->CPRead[13] (state, 0, & temp)
|| (temp & ARMul_CP13_R0_FIQ))
SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize);
break;
}
if (ARMul_MODE32BIT)
ARMul_SetR15 (state, vector);
else
ARMul_SetR15 (state, R15CCINTMODE | vector);
if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0)
{
/* No vector has been installed. Rather than simulating whatever
random bits might happen to be at address 0x20 onwards we elect
to stop. */
switch (vector)
{
case ARMul_ResetV: state->EndCondition = RDIError_Reset; break;
case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break;
case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break;
case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break;
case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break;
case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break;
case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break;
case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break;
default: break;
}
state->Emulate = FALSE;
}
}

873
sim/arm/armos.c
View file

@ -1,873 +0,0 @@
/* armos.c -- ARMulator OS interface: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* This file contains a model of Demon, ARM Ltd's Debug Monitor,
including all the SWI's required to support the C library. The code in
it is not really for the faint-hearted (especially the abort handling
code), but it is a complete example. Defining NOOS will disable all the
fun, and definign VAILDATE will define SWI 1 to enter SVC mode, and SWI
0x11 to halt the emulator. */
/* This must come before any other includes. */
#include "defs.h"
#include "ansidecl.h"
#include "libiberty.h"
#include <time.h>
#include <errno.h>
#include <limits.h>
#include <string.h>
#include <unistd.h> /* For SEEK_SET etc. */
#include "armdefs.h"
#include "armos.h"
#include "armemu.h"
#ifndef NOOS
#ifndef VALIDATE
/* #ifndef ASIM */
#include "armfpe.h"
/* #endif */
#endif
#endif
/* For RDIError_BreakpointReached. */
#include "dbg_rdi.h"
#include "sim/callback.h"
extern host_callback *sim_callback;
extern unsigned ARMul_OSInit (ARMul_State *);
extern unsigned ARMul_OSHandleSWI (ARMul_State *, ARMword);
#ifndef FOPEN_MAX
#define FOPEN_MAX 64
#endif
#ifndef PATH_MAX
#define PATH_MAX 1024
#endif
/* OS private Information. */
struct OSblock
{
ARMword ErrorNo;
};
/* Bit mask of enabled SWI implementations. */
unsigned int swi_mask = -1;
static ARMword softvectorcode[] =
{
/* Installed instructions:
swi tidyexception + event;
mov lr, pc;
ldmia fp, {fp, pc};
swi generateexception + event. */
0xef000090, 0xe1a0e00f, 0xe89b8800, 0xef000080, /* Reset */
0xef000091, 0xe1a0e00f, 0xe89b8800, 0xef000081, /* Undef */
0xef000092, 0xe1a0e00f, 0xe89b8800, 0xef000082, /* SWI */
0xef000093, 0xe1a0e00f, 0xe89b8800, 0xef000083, /* Prefetch abort */
0xef000094, 0xe1a0e00f, 0xe89b8800, 0xef000084, /* Data abort */
0xef000095, 0xe1a0e00f, 0xe89b8800, 0xef000085, /* Address exception */
0xef000096, 0xe1a0e00f, 0xe89b8800, 0xef000086, /* IRQ */
0xef000097, 0xe1a0e00f, 0xe89b8800, 0xef000087, /* FIQ */
0xef000098, 0xe1a0e00f, 0xe89b8800, 0xef000088, /* Error */
0xe1a0f00e /* Default handler */
};
/* Time for the Operating System to initialise itself. */
unsigned
ARMul_OSInit (ARMul_State * state)
{
#ifndef NOOS
#ifndef VALIDATE
ARMword instr, i, j;
if (state->OSptr == NULL)
{
state->OSptr = (unsigned char *) malloc (sizeof (struct OSblock));
if (state->OSptr == NULL)
{
perror ("OS Memory");
exit (15);
}
}
state->Reg[13] = ADDRSUPERSTACK; /* Set up a stack for the current mode... */
ARMul_SetReg (state, SVC32MODE, 13, ADDRSUPERSTACK);/* ...and for supervisor mode... */
ARMul_SetReg (state, ABORT32MODE, 13, ADDRSUPERSTACK);/* ...and for abort 32 mode... */
ARMul_SetReg (state, UNDEF32MODE, 13, ADDRSUPERSTACK);/* ...and for undef 32 mode... */
ARMul_SetReg (state, SYSTEMMODE, 13, ADDRSUPERSTACK);/* ...and for system mode. */
instr = 0xe59ff000 | (ADDRSOFTVECTORS - 8); /* Load pc from soft vector */
for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
/* Write hardware vectors. */
ARMul_WriteWord (state, i, instr);
SWI_vector_installed = 0;
for (i = ARMul_ResetV; i <= ARMFIQV + 4; i += 4)
{
ARMul_WriteWord (state, ADDRSOFTVECTORS + i, SOFTVECTORCODE + i * 4);
ARMul_WriteWord (state, ADDRSOFHANDLERS + 2 * i + 4L,
SOFTVECTORCODE + sizeof (softvectorcode) - 4L);
}
for (i = 0; i < sizeof (softvectorcode); i += 4)
ARMul_WriteWord (state, SOFTVECTORCODE + i, softvectorcode[i / 4]);
ARMul_ConsolePrint (state, ", Demon 1.01");
/* #ifndef ASIM */
/* Install FPE. */
for (i = 0; i < fpesize; i += 4)
/* Copy the code. */
ARMul_WriteWord (state, FPESTART + i, fpecode[i >> 2]);
/* Scan backwards from the end of the code. */
for (i = FPESTART + fpesize;; i -= 4)
{
/* When we reach the marker value, break out of
the loop, leaving i pointing at the maker. */
if ((j = ARMul_ReadWord (state, i)) == 0xffffffff)
break;
/* If necessary, reverse the error strings. */
if (state->bigendSig && j < 0x80000000)
{
/* It's part of the string so swap it. */
j = ((j >> 0x18) & 0x000000ff) |
((j >> 0x08) & 0x0000ff00) |
((j << 0x08) & 0x00ff0000) | ((j << 0x18) & 0xff000000);
ARMul_WriteWord (state, i, j);
}
}
/* Copy old illegal instr vector. */
ARMul_WriteWord (state, FPEOLDVECT, ARMul_ReadWord (state, ARMUndefinedInstrV));
/* Install new vector. */
ARMul_WriteWord (state, ARMUndefinedInstrV, FPENEWVECT (ARMul_ReadWord (state, i - 4)));
ARMul_ConsolePrint (state, ", FPE");
/* #endif ASIM */
#endif /* VALIDATE */
#endif /* NOOS */
/* Intel do not want DEMON SWI support. */
if (state->is_XScale)
swi_mask = SWI_MASK_ANGEL;
return TRUE;
}
/* These are libgloss defines, but seem to be common across all supported ARM
targets at the moment. These should get moved to the callback open_map. */
#define TARGET_O_BINARY 0
#define TARGET_O_APPEND 0x8
#define TARGET_O_CREAT 0x200
#define TARGET_O_RDONLY 0x0
#define TARGET_O_RDWR 0x2
#define TARGET_O_TRUNC 0x400
#define TARGET_O_WRONLY 0x1
static const int translate_open_mode[] =
{
TARGET_O_RDONLY, /* "r" */
TARGET_O_RDONLY + TARGET_O_BINARY, /* "rb" */
TARGET_O_RDWR, /* "r+" */
TARGET_O_RDWR + TARGET_O_BINARY, /* "r+b" */
TARGET_O_WRONLY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w" */
TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "wb" */
TARGET_O_RDWR + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+" */
TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_CREAT + TARGET_O_TRUNC, /* "w+b" */
TARGET_O_WRONLY + TARGET_O_APPEND + TARGET_O_CREAT, /* "a" */
TARGET_O_WRONLY + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT, /* "ab" */
TARGET_O_RDWR + TARGET_O_APPEND + TARGET_O_CREAT, /* "a+" */
TARGET_O_RDWR + TARGET_O_BINARY + TARGET_O_APPEND + TARGET_O_CREAT /* "a+b" */
};
static void
SWIWrite0 (ARMul_State * state, ARMword addr)
{
ARMword temp;
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
while ((temp = ARMul_SafeReadByte (state, addr++)) != 0)
{
char buffer = temp;
/* Note - we cannot just cast 'temp' to a (char *) here,
since on a big-endian host the byte value will end
up in the wrong place and a nul character will be printed. */
(void) sim_callback->write_stdout (sim_callback, & buffer, 1);
}
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
static void
WriteCommandLineTo (ARMul_State * state, ARMword addr)
{
ARMword temp;
char *cptr = state->CommandLine;
if (cptr == NULL)
cptr = "\0";
do
{
temp = (ARMword) * cptr++;
ARMul_SafeWriteByte (state, addr++, temp);
}
while (temp != 0);
}
static int
ReadFileName (ARMul_State * state, char *buf, ARMword src, size_t n)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
char *p = buf;
while (n--)
if ((*p++ = ARMul_SafeReadByte (state, src++)) == '\0')
return 0;
OSptr->ErrorNo = cb_host_to_target_errno (sim_callback, ENAMETOOLONG);
state->Reg[0] = -1;
return -1;
}
static void
SWIopen (ARMul_State * state, ARMword name, ARMword SWIflags)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
char buf[PATH_MAX];
int flags;
if (ReadFileName (state, buf, name, sizeof buf) == -1)
return;
/* Now we need to decode the Demon open mode. */
if (SWIflags >= ARRAY_SIZE (translate_open_mode))
flags = 0;
else
flags = translate_open_mode[SWIflags];
/* Filename ":tt" is special: it denotes stdin/out. */
if (strcmp (buf, ":tt") == 0)
{
if (flags == TARGET_O_RDONLY) /* opening tty "r" */
state->Reg[0] = 0; /* stdin */
else
state->Reg[0] = 1; /* stdout */
}
else
{
state->Reg[0] = sim_callback->open (sim_callback, buf, flags);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
}
static void
SWIread (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
int res;
int i;
char *local = malloc (len);
if (local == NULL)
{
sim_callback->printf_filtered
(sim_callback,
"sim: Unable to read 0x%lx bytes - out of memory\n",
(long)len);
return;
}
res = sim_callback->read (sim_callback, f, local, len);
if (res > 0)
for (i = 0; i < res; i++)
ARMul_SafeWriteByte (state, ptr + i, local[i]);
free (local);
state->Reg[0] = res == -1 ? -1 : len - res;
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
static void
SWIwrite (ARMul_State * state, ARMword f, ARMword ptr, ARMword len)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
int res;
ARMword i;
char *local = malloc (len);
if (local == NULL)
{
sim_callback->printf_filtered
(sim_callback,
"sim: Unable to write 0x%lx bytes - out of memory\n",
(long) len);
return;
}
for (i = 0; i < len; i++)
local[i] = ARMul_SafeReadByte (state, ptr + i);
res = sim_callback->write (sim_callback, f, local, len);
state->Reg[0] = res == -1 ? -1 : len - res;
free (local);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
static void
SWIflen (ARMul_State * state, ARMword fh)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
ARMword addr;
if (fh > FOPEN_MAX)
{
OSptr->ErrorNo = EBADF;
state->Reg[0] = -1L;
return;
}
addr = sim_callback->lseek (sim_callback, fh, 0, SEEK_CUR);
state->Reg[0] = sim_callback->lseek (sim_callback, fh, 0L, SEEK_END);
(void) sim_callback->lseek (sim_callback, fh, addr, SEEK_SET);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
static void
SWIremove (ARMul_State * state, ARMword path)
{
char buf[PATH_MAX];
if (ReadFileName (state, buf, path, sizeof buf) != -1)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
state->Reg[0] = sim_callback->unlink (sim_callback, buf);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
}
static void
SWIrename (ARMul_State * state, ARMword old, ARMword new)
{
char oldbuf[PATH_MAX], newbuf[PATH_MAX];
if (ReadFileName (state, oldbuf, old, sizeof oldbuf) != -1
&& ReadFileName (state, newbuf, new, sizeof newbuf) != -1)
{
struct OSblock *OSptr = (struct OSblock *) state->OSptr;
state->Reg[0] = sim_callback->rename (sim_callback, oldbuf, newbuf);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
}
/* The emulator calls this routine when a SWI instruction is encuntered.
The parameter passed is the SWI number (lower 24 bits of the instruction). */
unsigned
ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
{
struct OSblock * OSptr = (struct OSblock *) state->OSptr;
int unhandled = FALSE;
switch (number)
{
case SWI_Read:
if (swi_mask & SWI_MASK_DEMON)
SWIread (state, state->Reg[0], state->Reg[1], state->Reg[2]);
else
unhandled = TRUE;
break;
case SWI_Write:
if (swi_mask & SWI_MASK_DEMON)
SWIwrite (state, state->Reg[0], state->Reg[1], state->Reg[2]);
else
unhandled = TRUE;
break;
case SWI_Open:
if (swi_mask & SWI_MASK_DEMON)
SWIopen (state, state->Reg[0], state->Reg[1]);
else
unhandled = TRUE;
break;
case SWI_Clock:
if (swi_mask & SWI_MASK_DEMON)
{
/* Return number of centi-seconds. */
state->Reg[0] =
#ifdef CLOCKS_PER_SEC
(CLOCKS_PER_SEC >= 100)
? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
: (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
#else
/* Presume unix... clock() returns microseconds. */
(ARMword) (clock () / 10000);
#endif
OSptr->ErrorNo = errno;
}
else
unhandled = TRUE;
break;
case SWI_Time:
if (swi_mask & SWI_MASK_DEMON)
{
state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
else
unhandled = TRUE;
break;
case SWI_Close:
if (swi_mask & SWI_MASK_DEMON)
{
state->Reg[0] = sim_callback->close (sim_callback, state->Reg[0]);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
else
unhandled = TRUE;
break;
case SWI_Flen:
if (swi_mask & SWI_MASK_DEMON)
SWIflen (state, state->Reg[0]);
else
unhandled = TRUE;
break;
case SWI_Exit:
if (swi_mask & SWI_MASK_DEMON)
state->Emulate = FALSE;
else
unhandled = TRUE;
break;
case SWI_Seek:
if (swi_mask & SWI_MASK_DEMON)
{
/* We must return non-zero for failure. */
state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, state->Reg[0], state->Reg[1], SEEK_SET);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
else
unhandled = TRUE;
break;
case SWI_WriteC:
if (swi_mask & SWI_MASK_DEMON)
{
char tmp = state->Reg[0];
(void) sim_callback->write_stdout (sim_callback, &tmp, 1);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
else
unhandled = TRUE;
break;
case SWI_Write0:
if (swi_mask & SWI_MASK_DEMON)
SWIWrite0 (state, state->Reg[0]);
else
unhandled = TRUE;
break;
case SWI_GetErrno:
if (swi_mask & SWI_MASK_DEMON)
state->Reg[0] = OSptr->ErrorNo;
else
unhandled = TRUE;
break;
case SWI_GetEnv:
if (swi_mask & SWI_MASK_DEMON)
{
state->Reg[0] = ADDRCMDLINE;
if (state->MemSize)
state->Reg[1] = state->MemSize;
else
state->Reg[1] = ADDRUSERSTACK;
WriteCommandLineTo (state, state->Reg[0]);
}
else
unhandled = TRUE;
break;
case SWI_Breakpoint:
state->EndCondition = RDIError_BreakpointReached;
state->Emulate = FALSE;
break;
case SWI_Remove:
if (swi_mask & SWI_MASK_DEMON)
SWIremove (state, state->Reg[0]);
else
unhandled = TRUE;
break;
case SWI_Rename:
if (swi_mask & SWI_MASK_DEMON)
SWIrename (state, state->Reg[0], state->Reg[1]);
else
unhandled = TRUE;
break;
case SWI_IsTTY:
if (swi_mask & SWI_MASK_DEMON)
{
state->Reg[0] = sim_callback->isatty (sim_callback, state->Reg[0]);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
}
else
unhandled = TRUE;
break;
/* Handle Angel SWIs as well as Demon ones. */
case AngelSWI_ARM:
case AngelSWI_Thumb:
if (swi_mask & SWI_MASK_ANGEL)
{
ARMword addr;
ARMword temp;
/* R1 is almost always a parameter block. */
addr = state->Reg[1];
/* R0 is a reason code. */
switch (state->Reg[0])
{
case -1:
/* This can happen when a SWI is interrupted (eg receiving a
ctrl-C whilst processing SWIRead()). The SWI will complete
returning -1 in r0 to the caller. If GDB is then used to
resume the system call the reason code will now be -1. */
return TRUE;
/* Unimplemented reason codes. */
case AngelSWI_Reason_ReadC:
case AngelSWI_Reason_TmpNam:
case AngelSWI_Reason_System:
case AngelSWI_Reason_EnterSVC:
default:
state->Emulate = FALSE;
return FALSE;
case AngelSWI_Reason_Clock:
/* Return number of centi-seconds. */
state->Reg[0] =
#ifdef CLOCKS_PER_SEC
(CLOCKS_PER_SEC >= 100)
? (ARMword) (clock () / (CLOCKS_PER_SEC / 100))
: (ARMword) ((clock () * 100) / CLOCKS_PER_SEC);
#else
/* Presume unix... clock() returns microseconds. */
(ARMword) (clock () / 10000);
#endif
OSptr->ErrorNo = errno;
break;
case AngelSWI_Reason_Time:
state->Reg[0] = (ARMword) sim_callback->time (sim_callback);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case AngelSWI_Reason_WriteC:
{
char tmp = ARMul_SafeReadByte (state, addr);
(void) sim_callback->write_stdout (sim_callback, &tmp, 1);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
}
case AngelSWI_Reason_Write0:
SWIWrite0 (state, addr);
break;
case AngelSWI_Reason_Close:
state->Reg[0] = sim_callback->close (sim_callback, ARMul_ReadWord (state, addr));
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case AngelSWI_Reason_Seek:
state->Reg[0] = -1 >= sim_callback->lseek (sim_callback, ARMul_ReadWord (state, addr),
ARMul_ReadWord (state, addr + 4),
SEEK_SET);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case AngelSWI_Reason_FLen:
SWIflen (state, ARMul_ReadWord (state, addr));
break;
case AngelSWI_Reason_GetCmdLine:
WriteCommandLineTo (state, ARMul_ReadWord (state, addr));
break;
case AngelSWI_Reason_HeapInfo:
/* R1 is a pointer to a pointer. */
addr = ARMul_ReadWord (state, addr);
/* Pick up the right memory limit. */
if (state->MemSize)
temp = state->MemSize;
else
temp = ADDRUSERSTACK;
ARMul_WriteWord (state, addr, 0); /* Heap base. */
ARMul_WriteWord (state, addr + 4, temp); /* Heap limit. */
ARMul_WriteWord (state, addr + 8, temp); /* Stack base. */
ARMul_WriteWord (state, addr + 12, temp); /* Stack limit. */
break;
case AngelSWI_Reason_ReportException:
if (state->Reg[1] == ADP_Stopped_ApplicationExit)
state->Reg[0] = 0;
else
state->Reg[0] = -1;
state->Emulate = FALSE;
break;
case ADP_Stopped_ApplicationExit:
state->Reg[0] = 0;
state->Emulate = FALSE;
break;
case ADP_Stopped_RunTimeError:
state->Reg[0] = -1;
state->Emulate = FALSE;
break;
case AngelSWI_Reason_Errno:
state->Reg[0] = OSptr->ErrorNo;
break;
case AngelSWI_Reason_Open:
SWIopen (state,
ARMul_ReadWord (state, addr),
ARMul_ReadWord (state, addr + 4));
break;
case AngelSWI_Reason_Read:
SWIread (state,
ARMul_ReadWord (state, addr),
ARMul_ReadWord (state, addr + 4),
ARMul_ReadWord (state, addr + 8));
break;
case AngelSWI_Reason_Write:
SWIwrite (state,
ARMul_ReadWord (state, addr),
ARMul_ReadWord (state, addr + 4),
ARMul_ReadWord (state, addr + 8));
break;
case AngelSWI_Reason_IsTTY:
state->Reg[0] = sim_callback->isatty (sim_callback,
ARMul_ReadWord (state, addr));
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case AngelSWI_Reason_Remove:
SWIremove (state,
ARMul_ReadWord (state, addr));
break;
case AngelSWI_Reason_Rename:
SWIrename (state,
ARMul_ReadWord (state, addr),
ARMul_ReadWord (state, addr + 4));
break;
}
}
else
unhandled = TRUE;
break;
/* The following SWIs are generated by the softvectorcode[]
installed by default by the simulator. */
case 0x91: /* Undefined Instruction. */
{
ARMword addr = state->RegBank[UNDEFBANK][14] - 4;
sim_callback->printf_filtered
(sim_callback, "sim: exception: Unhandled Instruction '0x%08x' at 0x%08x. Stopping.\n",
ARMul_ReadWord (state, addr), addr);
state->EndCondition = RDIError_SoftwareInterrupt;
state->Emulate = FALSE;
return FALSE;
}
case 0x90: /* Reset. */
case 0x92: /* SWI. */
/* These two can be safely ignored. */
break;
case 0x93: /* Prefetch Abort. */
case 0x94: /* Data Abort. */
case 0x95: /* Address Exception. */
case 0x96: /* IRQ. */
case 0x97: /* FIQ. */
case 0x98: /* Error. */
unhandled = TRUE;
break;
case -1:
/* This can happen when a SWI is interrupted (eg receiving a
ctrl-C whilst processing SWIRead()). The SWI will complete
returning -1 in r0 to the caller. If GDB is then used to
resume the system call the reason code will now be -1. */
return TRUE;
case 0x180001: /* RedBoot's Syscall SWI in ARM mode. */
if (swi_mask & SWI_MASK_REDBOOT)
{
switch (state->Reg[0])
{
/* These numbers are defined in libgloss/syscall.h
but the simulator should not be dependend upon
libgloss being installed. */
case 1: /* Exit. */
state->Emulate = FALSE;
/* Copy exit code into r0. */
state->Reg[0] = state->Reg[1];
break;
case 2: /* Open. */
SWIopen (state, state->Reg[1], state->Reg[2]);
break;
case 3: /* Close. */
state->Reg[0] = sim_callback->close (sim_callback, state->Reg[1]);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case 4: /* Read. */
SWIread (state, state->Reg[1], state->Reg[2], state->Reg[3]);
break;
case 5: /* Write. */
SWIwrite (state, state->Reg[1], state->Reg[2], state->Reg[3]);
break;
case 6: /* Lseek. */
state->Reg[0] = sim_callback->lseek (sim_callback,
state->Reg[1],
state->Reg[2],
state->Reg[3]);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case 17: /* Utime. */
state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback);
OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
break;
case 7: /* Unlink. */
case 8: /* Getpid. */
case 9: /* Kill. */
case 10: /* Fstat. */
case 11: /* Sbrk. */
case 12: /* Argvlen. */
case 13: /* Argv. */
case 14: /* ChDir. */
case 15: /* Stat. */
case 16: /* Chmod. */
case 18: /* Time. */
sim_callback->printf_filtered
(sim_callback,
"sim: unhandled RedBoot syscall `%d' encountered - "
"returning ENOSYS\n",
state->Reg[0]);
state->Reg[0] = -1;
OSptr->ErrorNo = cb_host_to_target_errno
(sim_callback, ENOSYS);
break;
case 1001: /* Meminfo. */
{
ARMword totmem = state->Reg[1],
topmem = state->Reg[2];
ARMword stack = state->MemSize > 0
? state->MemSize : ADDRUSERSTACK;
if (totmem != 0)
ARMul_WriteWord (state, totmem, stack);
if (topmem != 0)
ARMul_WriteWord (state, topmem, stack);
state->Reg[0] = 0;
break;
}
default:
sim_callback->printf_filtered
(sim_callback,
"sim: unknown RedBoot syscall '%d' encountered - ignoring\n",
state->Reg[0]);
return FALSE;
}
break;
}
ATTRIBUTE_FALLTHROUGH;
default:
unhandled = TRUE;
}
if (unhandled)
{
if (SWI_vector_installed)
{
ARMword cpsr;
ARMword i_size;
cpsr = ARMul_GetCPSR (state);
i_size = INSN_SIZE;
ARMul_SetSPSR (state, SVC32MODE, cpsr);
cpsr &= ~0xbf;
cpsr |= SVC32MODE | 0x80;
ARMul_SetCPSR (state, cpsr);
state->RegBank[SVCBANK][14] = state->Reg[14] = state->Reg[15] - i_size;
state->NextInstr = RESUME;
state->Reg[15] = state->pc = ARMSWIV;
FLUSHPIPE;
}
else
{
sim_callback->printf_filtered
(sim_callback,
"sim: unknown SWI encountered - %x - ignoring\n",
number);
return FALSE;
}
}
return TRUE;
}

93
sim/arm/armos.h
View file

@ -1,93 +0,0 @@
/* armos.h -- ARMulator OS definitions: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* Define the initial layout of memory. */
#define ADDRSUPERSTACK 0x800L /* Supervisor stack space. */
#define ADDRUSERSTACK 0x80000L/* Default user stack start. */
#define ADDRSOFTVECTORS 0x840L /* Soft vectors are here. */
#define ADDRCMDLINE 0xf00L /* Command line is here after a SWI GetEnv. */
#define ADDRSOFHANDLERS 0xad0L /* Address and workspace for installed handlers. */
#define SOFTVECTORCODE 0xb80L /* Default handlers. */
/* SWI numbers. */
#define SWI_WriteC 0x0
#define SWI_Write0 0x2
#define SWI_ReadC 0x4
#define SWI_CLI 0x5
#define SWI_GetEnv 0x10
#define SWI_Exit 0x11
#define SWI_EnterOS 0x16
#define SWI_GetErrno 0x60
#define SWI_Clock 0x61
#define SWI_Time 0x63
#define SWI_Remove 0x64
#define SWI_Rename 0x65
#define SWI_Open 0x66
#define SWI_Close 0x68
#define SWI_Write 0x69
#define SWI_Read 0x6a
#define SWI_Seek 0x6b
#define SWI_Flen 0x6c
#define SWI_IsTTY 0x6e
#define SWI_TmpNam 0x6f
#define SWI_InstallHandler 0x70
#define SWI_GenerateError 0x71
#define SWI_Breakpoint 0x180000 /* See gdb's tm-arm.h */
#define AngelSWI_ARM 0x123456
#define AngelSWI_Thumb 0xAB
/* The reason codes: */
#define AngelSWI_Reason_Open 0x01
#define AngelSWI_Reason_Close 0x02
#define AngelSWI_Reason_WriteC 0x03
#define AngelSWI_Reason_Write0 0x04
#define AngelSWI_Reason_Write 0x05
#define AngelSWI_Reason_Read 0x06
#define AngelSWI_Reason_ReadC 0x07
#define AngelSWI_Reason_IsTTY 0x09
#define AngelSWI_Reason_Seek 0x0A
#define AngelSWI_Reason_FLen 0x0C
#define AngelSWI_Reason_TmpNam 0x0D
#define AngelSWI_Reason_Remove 0x0E
#define AngelSWI_Reason_Rename 0x0F
#define AngelSWI_Reason_Clock 0x10
#define AngelSWI_Reason_Time 0x11
#define AngelSWI_Reason_System 0x12
#define AngelSWI_Reason_Errno 0x13
#define AngelSWI_Reason_GetCmdLine 0x15
#define AngelSWI_Reason_HeapInfo 0x16
#define AngelSWI_Reason_EnterSVC 0x17
#define AngelSWI_Reason_ReportException 0x18
#define ADP_Stopped_ApplicationExit ((2 << 16) + 38)
#define ADP_Stopped_RunTimeError ((2 << 16) + 35)
/* Floating Point Emulator address space. */
#define FPESTART 0x2000L
#define FPEEND 0x8000L
#define FPEOLDVECT FPESTART + 0x100L + 8L * 16L + 4L /* Stack + 8 regs + fpsr. */
#define FPENEWVECT(addr) 0xea000000L + ((addr) >> 2) - 3L /* Branch from 4 to 0x2400. */
extern unsigned long fpecode[];
extern unsigned long fpesize;
extern int SWI_vector_installed;

1704
sim/arm/armsupp.c
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517
sim/arm/armvirt.c
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@ -1,517 +0,0 @@
/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
/* This file contains a complete ARMulator memory model, modelling a
"virtual memory" system. A much simpler model can be found in armfast.c,
and that model goes faster too, but has a fixed amount of memory. This
model's memory has 64K pages, allocated on demand from a 64K entry page
table. The routines PutWord and GetWord implement this. Pages are never
freed as they might be needed again. A single area of memory may be
defined to generate aborts. */
/* This must come before any other includes. */
#include "defs.h"
#include "armos.h"
#include "armdefs.h"
#include "ansidecl.h"
#ifdef VALIDATE /* for running the validate suite */
#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
#define ABORTS 1
#endif
/* #define ABORTS */
#ifdef ABORTS /* the memory system will abort */
/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
For the new test suite Abort between 8 Mbytes and 26 Mbytes */
/* #define LOWABORT 32 * 1024
#define HIGHABORT 32 * 1024 * 1024 */
#define LOWABORT 8 * 1024 * 1024
#define HIGHABORT 26 * 1024 * 1024
#endif
#undef PAGESIZE /* Cleanup system headers. */
#define NUMPAGES 64 * 1024
#define PAGESIZE 64 * 1024
#define PAGEBITS 16
#define OFFSETBITS 0xffff
int SWI_vector_installed = FALSE;
/***************************************************************************\
* Get a Word from Virtual Memory, maybe allocating the page *
\***************************************************************************/
static ARMword
GetWord (ARMul_State * state, ARMword address, int check)
{
ARMword page;
ARMword offset;
ARMword **pagetable;
ARMword *pageptr;
if (check && state->is_XScale)
XScale_check_memacc (state, &address, 0);
page = address >> PAGEBITS;
offset = (address & OFFSETBITS) >> 2;
pagetable = (ARMword **) state->MemDataPtr;
pageptr = *(pagetable + page);
if (pageptr == NULL)
{
pageptr = (ARMword *) malloc (PAGESIZE);
if (pageptr == NULL)
{
perror ("ARMulator can't allocate VM page");
exit (12);
}
*(pagetable + page) = pageptr;
}
return *(pageptr + offset);
}
/***************************************************************************\
* Put a Word into Virtual Memory, maybe allocating the page *
\***************************************************************************/
static void
PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
{
ARMword page;
ARMword offset;
ARMword **pagetable;
ARMword *pageptr;
if (check && state->is_XScale)
XScale_check_memacc (state, &address, 1);
page = address >> PAGEBITS;
offset = (address & OFFSETBITS) >> 2;
pagetable = (ARMword **) state->MemDataPtr;
pageptr = *(pagetable + page);
if (pageptr == NULL)
{
pageptr = (ARMword *) malloc (PAGESIZE);
if (pageptr == NULL)
{
perror ("ARMulator can't allocate VM page");
exit (13);
}
*(pagetable + page) = pageptr;
}
if (address == 0x8)
SWI_vector_installed = TRUE;
*(pageptr + offset) = data;
}
/***************************************************************************\
* Initialise the memory interface *
\***************************************************************************/
unsigned
ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
{
ARMword **pagetable;
unsigned page;
if (initmemsize)
state->MemSize = initmemsize;
pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES);
if (pagetable == NULL)
return FALSE;
for (page = 0; page < NUMPAGES; page++)
*(pagetable + page) = NULL;
state->MemDataPtr = (unsigned char *) pagetable;
ARMul_ConsolePrint (state, ", 4 Gb memory");
return TRUE;
}
/***************************************************************************\
* Remove the memory interface *
\***************************************************************************/
void
ARMul_MemoryExit (ARMul_State * state)
{
ARMword page;
ARMword **pagetable;
ARMword *pageptr;
pagetable = (ARMword **) state->MemDataPtr;
for (page = 0; page < NUMPAGES; page++)
{
pageptr = *(pagetable + page);
if (pageptr != NULL)
free ((char *) pageptr);
}
free ((char *) pagetable);
return;
}
/***************************************************************************\
* ReLoad Instruction *
\***************************************************************************/
ARMword
ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
{
#ifdef ABORTS
if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_PREFETCHABORT (address);
return ARMul_ABORTWORD;
}
else
{
ARMul_CLEARABORT;
}
#endif
if ((isize == 2) && (address & 0x2))
{
/* We return the next two halfwords: */
ARMword lo = GetWord (state, address, FALSE);
ARMword hi = GetWord (state, address + 4, FALSE);
if (state->bigendSig == HIGH)
return (lo << 16) | (hi >> 16);
else
return ((hi & 0xFFFF) << 16) | (lo >> 16);
}
return GetWord (state, address, TRUE);
}
/***************************************************************************\
* Load Instruction, Sequential Cycle *
\***************************************************************************/
ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
{
state->NumScycles++;
return ARMul_ReLoadInstr (state, address, isize);
}
/***************************************************************************\
* Load Instruction, Non Sequential Cycle *
\***************************************************************************/
ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
{
state->NumNcycles++;
return ARMul_ReLoadInstr (state, address, isize);
}
/***************************************************************************\
* Read Word (but don't tell anyone!) *
\***************************************************************************/
ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
{
#ifdef ABORTS
if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_DATAABORT (address);
return ARMul_ABORTWORD;
}
else
{
ARMul_CLEARABORT;
}
#endif
return GetWord (state, address, TRUE);
}
/***************************************************************************\
* Load Word, Sequential Cycle *
\***************************************************************************/
ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
{
state->NumScycles++;
return ARMul_ReadWord (state, address);
}
/***************************************************************************\
* Load Word, Non Sequential Cycle *
\***************************************************************************/
ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
{
state->NumNcycles++;
return ARMul_ReadWord (state, address);
}
/***************************************************************************\
* Load Halfword, (Non Sequential Cycle) *
\***************************************************************************/
ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
state->NumNcycles++;
temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
return (temp >> offset) & 0xffff;
}
/***************************************************************************\
* Read Byte (but don't tell anyone!) *
\***************************************************************************/
ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
return (temp >> offset & 0xffL);
}
/***************************************************************************\
* Load Byte, (Non Sequential Cycle) *
\***************************************************************************/
ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
{
state->NumNcycles++;
return ARMul_ReadByte (state, address);
}
/***************************************************************************\
* Write Word (but don't tell anyone!) *
\***************************************************************************/
void
ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
{
#ifdef ABORTS
if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_DATAABORT (address);
return;
}
else
{
ARMul_CLEARABORT;
}
#endif
PutWord (state, address, data, TRUE);
}
/***************************************************************************\
* Store Word, Sequential Cycle *
\***************************************************************************/
void
ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
{
state->NumScycles++;
ARMul_WriteWord (state, address, data);
}
/***************************************************************************\
* Store Word, Non Sequential Cycle *
\***************************************************************************/
void
ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
{
state->NumNcycles++;
ARMul_WriteWord (state, address, data);
}
/***************************************************************************\
* Store HalfWord, (Non Sequential Cycle) *
\***************************************************************************/
void
ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp, offset;
state->NumNcycles++;
#ifdef VALIDATE
if (address == TUBE)
{
if (data == 4)
state->Emulate = FALSE;
else
(void) putc ((char) data, stderr); /* Write Char */
return;
}
#endif
temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
PutWord (state, address,
(temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset),
TRUE);
}
/***************************************************************************\
* Write Byte (but don't tell anyone!) *
\***************************************************************************/
void
ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp, offset;
temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
PutWord (state, address,
(temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
TRUE);
}
/***************************************************************************\
* Store Byte, (Non Sequential Cycle) *
\***************************************************************************/
void
ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
{
state->NumNcycles++;
#ifdef VALIDATE
if (address == TUBE)
{
if (data == 4)
state->Emulate = FALSE;
else
(void) putc ((char) data, stderr); /* Write Char */
return;
}
#endif
ARMul_WriteByte (state, address, data);
}
/***************************************************************************\
* Swap Word, (Two Non Sequential Cycles) *
\***************************************************************************/
ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp;
state->NumNcycles++;
temp = ARMul_ReadWord (state, address);
state->NumNcycles++;
PutWord (state, address, data, TRUE);
return temp;
}
/***************************************************************************\
* Swap Byte, (Two Non Sequential Cycles) *
\***************************************************************************/
ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp;
temp = ARMul_LoadByte (state, address);
ARMul_StoreByte (state, address, data);
return temp;
}
/***************************************************************************\
* Count I Cycles *
\***************************************************************************/
void
ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
state->NumIcycles += number;
ARMul_CLEARABORT;
}
/***************************************************************************\
* Count C Cycles *
\***************************************************************************/
void
ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
state->NumCcycles += number;
ARMul_CLEARABORT;
}
/* Read a byte. Do not check for alignment or access errors. */
ARMword
ARMul_SafeReadByte (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
temp = GetWord (state, address, FALSE);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
return (temp >> offset & 0xffL);
}
void
ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp, offset;
temp = GetWord (state, address, FALSE);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
PutWord (state, address,
(temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
FALSE);
}

84
sim/arm/dbg_rdi.h
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/* dbg_rdi.h -- ARMulator RDI interface: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see <http://www.gnu.org/licenses/>. */
#ifndef dbg_rdi__h
#define dbg_rdi__h
/***************************************************************************\
* Error Codes *
\***************************************************************************/
#define RDIError_NoError 0
#define RDIError_Reset 1
#define RDIError_UndefinedInstruction 2
#define RDIError_SoftwareInterrupt 3
#define RDIError_PrefetchAbort 4
#define RDIError_DataAbort 5
#define RDIError_AddressException 6
#define RDIError_IRQ 7
#define RDIError_FIQ 8
#define RDIError_Error 9
#define RDIError_BranchThrough0 10
#define RDIError_NotInitialised 128
#define RDIError_UnableToInitialise 129
#define RDIError_WrongByteSex 130
#define RDIError_UnableToTerminate 131
#define RDIError_BadInstruction 132
#define RDIError_IllegalInstruction 133
#define RDIError_BadCPUStateSetting 134
#define RDIError_UnknownCoPro 135
#define RDIError_UnknownCoProState 136
#define RDIError_BadCoProState 137
#define RDIError_BadPointType 138
#define RDIError_UnimplementedType 139
#define RDIError_BadPointSize 140
#define RDIError_UnimplementedSize 141
#define RDIError_NoMorePoints 142
#define RDIError_BreakpointReached 143
#define RDIError_WatchpointAccessed 144
#define RDIError_NoSuchPoint 145
#define RDIError_ProgramFinishedInStep 146
#define RDIError_UserInterrupt 147
#define RDIError_CantSetPoint 148
#define RDIError_IncompatibleRDILevels 149
#define RDIError_CantLoadConfig 150
#define RDIError_BadConfigData 151
#define RDIError_NoSuchConfig 152
#define RDIError_BufferFull 153
#define RDIError_OutOfStore 154
#define RDIError_NotInDownload 155
#define RDIError_PointInUse 156
#define RDIError_BadImageFormat 157
#define RDIError_TargetRunning 158
#define RDIError_LittleEndian 240
#define RDIError_BigEndian 241
#define RDIError_SoftInitialiseError 242
#define RDIError_InsufficientPrivilege 253
#define RDIError_UnimplementedMessage 254
#define RDIError_UndefinedMessage 255
#endif
extern unsigned int swi_mask;
#define SWI_MASK_DEMON (1 << 0)
#define SWI_MASK_ANGEL (1 << 1)
#define SWI_MASK_REDBOOT (1 << 2)

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sim/arm/iwmmxt.c
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sim/arm/iwmmxt.h
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/* iwmmxt.h -- Intel(r) Wireless MMX(tm) technology co-processor interface.
Copyright (C) 2002-2024 Free Software Foundation, Inc.
Contributed by matthew green (mrg@redhat.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
extern unsigned IwmmxtLDC (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned IwmmxtSTC (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned IwmmxtMCR (ARMul_State *, unsigned, ARMword, ARMword);
extern unsigned IwmmxtMRC (ARMul_State *, unsigned, ARMword, ARMword *);
extern unsigned IwmmxtCDP (ARMul_State *, unsigned, ARMword);
extern int ARMul_HandleIwmmxt (ARMul_State *, ARMword);
extern int Fetch_Iwmmxt_Register (unsigned int, unsigned char *);
extern int Store_Iwmmxt_Register (unsigned int, const unsigned char *);

52
sim/arm/local.mk
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@ -1,52 +0,0 @@
## See sim/Makefile.am
##
## Copyright (C) 1995-2024 Free Software Foundation, Inc.
## Written by Cygnus Support.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 3 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program. If not, see <http://www.gnu.org/licenses/>.
AM_CPPFLAGS_%C% = -DMODET
nodist_%C%_libsim_a_SOURCES = \
%D%/modules.c
%C%_libsim_a_SOURCES = \
$(common_libcommon_a_SOURCES)
%C%_libsim_a_LIBADD = \
%D%/wrapper.o \
$(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
$(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
%D%/armemu.o \
%D%/armemu32.o %D%/arminit.o %D%/armos.o %D%/armsupp.o \
%D%/armvirt.o %D%/thumbemu.o \
%D%/armcopro.o %D%/maverick.o %D%/iwmmxt.o
$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
noinst_LIBRARIES += %D%/libsim.a
## Override wildcards that trigger common/modules.c to be (incorrectly) used.
%D%/modules.o: %D%/modules.c
%D%/%.o: common/%.c ; $(SIM_COMPILE)
-@am__include@ %D%/$(DEPDIR)/*.Po
%C%_run_SOURCES =
%C%_run_LDADD = \
%D%/nrun.o \
%D%/libsim.a \
$(SIM_COMMON_LIBS)
noinst_PROGRAMS += %D%/run
%C%docdir = $(docdir)/%C%
%C%doc_DATA = %D%/README

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sim/arm/maverick.c
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sim/arm/maverick.h
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/* maverick.h -- Cirrus/DSP co-processor interface header
Copyright (C) 2003-2024 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* Define Co-Processor instruction handlers here. */
/* Here's ARMulator's DSP definition. A few things to note:
1) it has 16 64-bit registers and 4 72-bit accumulators
2) you can only access its registers with MCR and MRC. */
struct maverick_regs
{
union
{
int i;
float f;
} upper;
union
{
int i;
float f;
} lower;
};
union maverick_acc_regs
{
long double ld; /* Acc registers are 72-bits. */
};
extern struct maverick_regs DSPregs[16];
extern union maverick_acc_regs DSPacc[4];
extern ARMword DSPsc;

25
sim/arm/sim-main.h
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/* Simulation code for the ARM processor.
Copyright (C) 2009-2024 Free Software Foundation, Inc.
This file is part of simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
#include "sim-basics.h"
#include "sim-base.h"
#endif

2623
sim/arm/thumbemu.c
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938
sim/arm/wrapper.c
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/* run front end support for arm
Copyright (C) 1995-2024 Free Software Foundation, Inc.
This file is part of ARM SIM.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
/* This file provides the interface between the simulator and
run.c and gdb (when the simulator is linked with gdb).
All simulator interaction should go through this file. */
/* This must come before any other includes. */
#include "defs.h"
#include <stdio.h>
#include <stdarg.h>
#include <stdlib.h>
#include <string.h>
#include <bfd.h>
#include <signal.h>
#include "sim/callback.h"
#include "sim/sim.h"
#include "sim-main.h"
#include "sim-options.h"
#include "armemu.h"
#include "dbg_rdi.h"
#include "ansidecl.h"
#include "sim/sim-arm.h"
#include "gdb/signals.h"
#include "libiberty.h"
#include "iwmmxt.h"
#include "maverick.h"
#include "arm-sim.h"
/* TODO: This should get pulled from the SIM_DESC. */
host_callback *sim_callback;
/* TODO: This should get merged into sim_cpu. */
struct ARMul_State *state;
/* Memory size in bytes. */
/* TODO: Memory should be converted to the common memory module. */
static int mem_size = (1 << 21);
int stop_simulator;
#include "dis-asm.h"
/* TODO: Tracing should be converted to common tracing module. */
int trace = 0;
int disas = 0;
int trace_funcs = 0;
static struct disassemble_info info;
static char opbuf[1000];
static int ATTRIBUTE_PRINTF (2, 3)
op_printf (char *buf, const char *fmt, ...)
{
int ret;
va_list ap;
va_start (ap, fmt);
ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
va_end (ap);
return ret;
}
static int ATTRIBUTE_PRINTF (3, 4)
op_styled_printf (char *buf, enum disassembler_style style,
const char *fmt, ...)
{
int ret;
va_list ap;
va_start (ap, fmt);
ret = vsprintf (opbuf + strlen (opbuf), fmt, ap);
va_end (ap);
return ret;
}
static int
sim_dis_read (bfd_vma memaddr ATTRIBUTE_UNUSED,
bfd_byte * ptr,
unsigned int length,
struct disassemble_info * info)
{
ARMword val = (ARMword) *((ARMword *) info->application_data);
while (length--)
{
* ptr ++ = val & 0xFF;
val >>= 8;
}
return 0;
}
void
print_insn (ARMword instr)
{
int size;
disassembler_ftype disassemble_fn;
opbuf[0] = 0;
info.application_data = & instr;
disassemble_fn = disassembler (bfd_arch_arm, 0, 0, NULL);
size = disassemble_fn (0, & info);
fprintf (stderr, " %*s\n", size, opbuf);
}
static void
init (void)
{
static int done;
if (!done)
{
ARMul_EmulateInit ();
state = ARMul_NewState ();
state->bigendSig = (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? HIGH : LOW);
ARMul_MemoryInit (state, mem_size);
ARMul_OSInit (state);
state->verbose = 0;
done = 1;
}
}
void
ARMul_ConsolePrint (ARMul_State * state,
const char * format,
...)
{
va_list ap;
if (state->verbose)
{
va_start (ap, format);
vprintf (format, ap);
va_end (ap);
}
}
uint64_t
sim_write (SIM_DESC sd ATTRIBUTE_UNUSED,
uint64_t addr,
const void * buffer,
uint64_t size)
{
uint64_t i;
const unsigned char * data = buffer;
init ();
for (i = 0; i < size; i++)
ARMul_SafeWriteByte (state, addr + i, data[i]);
return size;
}
uint64_t
sim_read (SIM_DESC sd ATTRIBUTE_UNUSED,
uint64_t addr,
void * buffer,
uint64_t size)
{
uint64_t i;
unsigned char * data = buffer;
init ();
for (i = 0; i < size; i++)
data[i] = ARMul_SafeReadByte (state, addr + i);
return size;
}
int
sim_stop (SIM_DESC sd ATTRIBUTE_UNUSED)
{
state->Emulate = STOP;
stop_simulator = 1;
return 1;
}
void
sim_resume (SIM_DESC sd ATTRIBUTE_UNUSED,
int step,
int siggnal ATTRIBUTE_UNUSED)
{
state->EndCondition = 0;
stop_simulator = 0;
if (step)
{
state->Reg[15] = ARMul_DoInstr (state);
if (state->EndCondition == 0)
state->EndCondition = RDIError_BreakpointReached;
}
else
{
state->NextInstr = RESUME; /* treat as PC change */
state->Reg[15] = ARMul_DoProg (state);
}
FLUSHPIPE;
}
SIM_RC
sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
struct bfd * abfd,
char * const *argv,
char * const *env)
{
int argvlen = 0;
int mach;
char * const *arg;
init ();
if (abfd != NULL)
{
ARMul_SetPC (state, bfd_get_start_address (abfd));
mach = bfd_get_mach (abfd);
}
else
{
ARMul_SetPC (state, 0); /* ??? */
mach = 0;
}
#ifdef MODET
if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
SETT;
#endif
switch (mach)
{
default:
(*sim_callback->printf_filtered)
(sim_callback,
"Unknown machine type '%d'; please update sim_create_inferior.\n",
mach);
ATTRIBUTE_FALLTHROUGH;
case 0:
/* We wouldn't set the machine type with earlier toolchains, so we
explicitly select a processor capable of supporting all ARMs in
32bit mode. */
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
break;
#if 1
case bfd_mach_arm_6T2:
case bfd_mach_arm_7:
case bfd_mach_arm_7EM:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_v6_Prop);
break;
#endif
case bfd_mach_arm_XScale:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_v6_Prop);
break;
case bfd_mach_arm_iWMMXt2:
case bfd_mach_arm_iWMMXt:
{
extern int SWI_vector_installed;
ARMword i;
if (! SWI_vector_installed)
{
/* Intialise the hardware vectors to zero. */
if (! SWI_vector_installed)
for (i = ARMul_ResetV; i <= ARMFIQV; i += 4)
ARMul_WriteWord (state, i, 0);
/* ARM_WriteWord will have detected the write to the SWI vector,
but we want SWI_vector_installed to remain at 0 so that thumb
mode breakpoints will work. */
SWI_vector_installed = 0;
}
}
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop | ARM_iWMMXt_Prop);
break;
case bfd_mach_arm_ep9312:
ARMul_SelectProcessor (state, ARM_v4_Prop | ARM_ep9312_Prop);
break;
case bfd_mach_arm_5:
if (bfd_family_coff (abfd))
{
/* This is a special case in order to support COFF based ARM toolchains.
The COFF header does not have enough room to store all the different
kinds of ARM cpu, so the XScale, v5T and v5TE architectures all default
to v5. (See coff_set_flags() in bdf/coffcode.h). So if we see a v5
machine type here, we assume it could be any of the above architectures
and so select the most feature-full. */
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop | ARM_XScale_Prop);
break;
}
ATTRIBUTE_FALLTHROUGH;
case bfd_mach_arm_5T:
ARMul_SelectProcessor (state, ARM_v5_Prop);
break;
case bfd_mach_arm_5TE:
ARMul_SelectProcessor (state, ARM_v5_Prop | ARM_v5e_Prop);
break;
case bfd_mach_arm_4:
case bfd_mach_arm_4T:
ARMul_SelectProcessor (state, ARM_v4_Prop);
break;
case bfd_mach_arm_3:
case bfd_mach_arm_3M:
ARMul_SelectProcessor (state, ARM_Lock_Prop);
break;
case bfd_mach_arm_2:
case bfd_mach_arm_2a:
ARMul_SelectProcessor (state, ARM_Fix26_Prop);
break;
}
memset (& info, 0, sizeof (info));
INIT_DISASSEMBLE_INFO (info, stdout, op_printf, op_styled_printf);
info.read_memory_func = sim_dis_read;
info.arch = bfd_get_arch (abfd);
info.mach = bfd_get_mach (abfd);
info.endian_code = BFD_ENDIAN_LITTLE;
if (info.mach == 0)
info.arch = bfd_arch_arm;
disassemble_init_for_target (& info);
if (argv != NULL)
{
/* Set up the command line by laboriously stringing together
the environment carefully picked apart by our caller. */
/* Free any old stuff. */
if (state->CommandLine != NULL)
{
free (state->CommandLine);
state->CommandLine = NULL;
}
/* See how much we need. */
for (arg = argv; *arg != NULL; arg++)
argvlen += strlen (*arg) + 1;
/* Allocate it. */
state->CommandLine = malloc (argvlen + 1);
if (state->CommandLine != NULL)
{
arg = argv;
state->CommandLine[0] = '\0';
for (arg = argv; *arg != NULL; arg++)
{
strcat (state->CommandLine, *arg);
strcat (state->CommandLine, " ");
}
}
}
if (env != NULL)
{
/* Now see if there's a MEMSIZE spec in the environment. */
while (*env)
{
if (strncmp (*env, "MEMSIZE=", sizeof ("MEMSIZE=") - 1) == 0)
{
char *end_of_num;
/* Set up memory limit. */
state->MemSize =
strtoul (*env + sizeof ("MEMSIZE=") - 1, &end_of_num, 0);
}
env++;
}
}
return SIM_RC_OK;
}
static int
frommem (struct ARMul_State *state, const unsigned char *memory)
{
if (state->bigendSig == HIGH)
return (memory[0] << 24) | (memory[1] << 16)
| (memory[2] << 8) | (memory[3] << 0);
else
return (memory[3] << 24) | (memory[2] << 16)
| (memory[1] << 8) | (memory[0] << 0);
}
static void
tomem (struct ARMul_State *state,
unsigned char *memory,
int val)
{
if (state->bigendSig == HIGH)
{
memory[0] = val >> 24;
memory[1] = val >> 16;
memory[2] = val >> 8;
memory[3] = val >> 0;
}
else
{
memory[3] = val >> 24;
memory[2] = val >> 16;
memory[1] = val >> 8;
memory[0] = val >> 0;
}
}
static int
arm_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length)
{
init ();
switch ((enum sim_arm_regs) rn)
{
case SIM_ARM_R0_REGNUM:
case SIM_ARM_R1_REGNUM:
case SIM_ARM_R2_REGNUM:
case SIM_ARM_R3_REGNUM:
case SIM_ARM_R4_REGNUM:
case SIM_ARM_R5_REGNUM:
case SIM_ARM_R6_REGNUM:
case SIM_ARM_R7_REGNUM:
case SIM_ARM_R8_REGNUM:
case SIM_ARM_R9_REGNUM:
case SIM_ARM_R10_REGNUM:
case SIM_ARM_R11_REGNUM:
case SIM_ARM_R12_REGNUM:
case SIM_ARM_R13_REGNUM:
case SIM_ARM_R14_REGNUM:
case SIM_ARM_R15_REGNUM: /* PC */
case SIM_ARM_FP0_REGNUM:
case SIM_ARM_FP1_REGNUM:
case SIM_ARM_FP2_REGNUM:
case SIM_ARM_FP3_REGNUM:
case SIM_ARM_FP4_REGNUM:
case SIM_ARM_FP5_REGNUM:
case SIM_ARM_FP6_REGNUM:
case SIM_ARM_FP7_REGNUM:
case SIM_ARM_FPS_REGNUM:
ARMul_SetReg (state, state->Mode, rn, frommem (state, buf));
break;
case SIM_ARM_PS_REGNUM:
state->Cpsr = frommem (state, buf);
ARMul_CPSRAltered (state);
break;
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
buf, sizeof (struct maverick_regs));
return sizeof (struct maverick_regs);
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
memcpy (&DSPsc, buf, sizeof DSPsc);
return sizeof DSPsc;
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, buf);
default:
return 0;
}
return length;
}
static int
arm_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length)
{
unsigned char *memory = buf;
ARMword regval;
int len = length;
init ();
switch ((enum sim_arm_regs) rn)
{
case SIM_ARM_R0_REGNUM:
case SIM_ARM_R1_REGNUM:
case SIM_ARM_R2_REGNUM:
case SIM_ARM_R3_REGNUM:
case SIM_ARM_R4_REGNUM:
case SIM_ARM_R5_REGNUM:
case SIM_ARM_R6_REGNUM:
case SIM_ARM_R7_REGNUM:
case SIM_ARM_R8_REGNUM:
case SIM_ARM_R9_REGNUM:
case SIM_ARM_R10_REGNUM:
case SIM_ARM_R11_REGNUM:
case SIM_ARM_R12_REGNUM:
case SIM_ARM_R13_REGNUM:
case SIM_ARM_R14_REGNUM:
case SIM_ARM_R15_REGNUM: /* PC */
regval = ARMul_GetReg (state, state->Mode, rn);
break;
case SIM_ARM_FP0_REGNUM:
case SIM_ARM_FP1_REGNUM:
case SIM_ARM_FP2_REGNUM:
case SIM_ARM_FP3_REGNUM:
case SIM_ARM_FP4_REGNUM:
case SIM_ARM_FP5_REGNUM:
case SIM_ARM_FP6_REGNUM:
case SIM_ARM_FP7_REGNUM:
case SIM_ARM_FPS_REGNUM:
memset (memory, 0, length);
return 0;
case SIM_ARM_PS_REGNUM:
regval = ARMul_GetCPSR (state);
break;
case SIM_ARM_MAVERIC_COP0R0_REGNUM:
case SIM_ARM_MAVERIC_COP0R1_REGNUM:
case SIM_ARM_MAVERIC_COP0R2_REGNUM:
case SIM_ARM_MAVERIC_COP0R3_REGNUM:
case SIM_ARM_MAVERIC_COP0R4_REGNUM:
case SIM_ARM_MAVERIC_COP0R5_REGNUM:
case SIM_ARM_MAVERIC_COP0R6_REGNUM:
case SIM_ARM_MAVERIC_COP0R7_REGNUM:
case SIM_ARM_MAVERIC_COP0R8_REGNUM:
case SIM_ARM_MAVERIC_COP0R9_REGNUM:
case SIM_ARM_MAVERIC_COP0R10_REGNUM:
case SIM_ARM_MAVERIC_COP0R11_REGNUM:
case SIM_ARM_MAVERIC_COP0R12_REGNUM:
case SIM_ARM_MAVERIC_COP0R13_REGNUM:
case SIM_ARM_MAVERIC_COP0R14_REGNUM:
case SIM_ARM_MAVERIC_COP0R15_REGNUM:
memcpy (memory, & DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM],
sizeof (struct maverick_regs));
return sizeof (struct maverick_regs);
case SIM_ARM_MAVERIC_DSPSC_REGNUM:
memcpy (memory, & DSPsc, sizeof DSPsc);
return sizeof DSPsc;
case SIM_ARM_IWMMXT_COP0R0_REGNUM:
case SIM_ARM_IWMMXT_COP0R1_REGNUM:
case SIM_ARM_IWMMXT_COP0R2_REGNUM:
case SIM_ARM_IWMMXT_COP0R3_REGNUM:
case SIM_ARM_IWMMXT_COP0R4_REGNUM:
case SIM_ARM_IWMMXT_COP0R5_REGNUM:
case SIM_ARM_IWMMXT_COP0R6_REGNUM:
case SIM_ARM_IWMMXT_COP0R7_REGNUM:
case SIM_ARM_IWMMXT_COP0R8_REGNUM:
case SIM_ARM_IWMMXT_COP0R9_REGNUM:
case SIM_ARM_IWMMXT_COP0R10_REGNUM:
case SIM_ARM_IWMMXT_COP0R11_REGNUM:
case SIM_ARM_IWMMXT_COP0R12_REGNUM:
case SIM_ARM_IWMMXT_COP0R13_REGNUM:
case SIM_ARM_IWMMXT_COP0R14_REGNUM:
case SIM_ARM_IWMMXT_COP0R15_REGNUM:
case SIM_ARM_IWMMXT_COP1R0_REGNUM:
case SIM_ARM_IWMMXT_COP1R1_REGNUM:
case SIM_ARM_IWMMXT_COP1R2_REGNUM:
case SIM_ARM_IWMMXT_COP1R3_REGNUM:
case SIM_ARM_IWMMXT_COP1R4_REGNUM:
case SIM_ARM_IWMMXT_COP1R5_REGNUM:
case SIM_ARM_IWMMXT_COP1R6_REGNUM:
case SIM_ARM_IWMMXT_COP1R7_REGNUM:
case SIM_ARM_IWMMXT_COP1R8_REGNUM:
case SIM_ARM_IWMMXT_COP1R9_REGNUM:
case SIM_ARM_IWMMXT_COP1R10_REGNUM:
case SIM_ARM_IWMMXT_COP1R11_REGNUM:
case SIM_ARM_IWMMXT_COP1R12_REGNUM:
case SIM_ARM_IWMMXT_COP1R13_REGNUM:
case SIM_ARM_IWMMXT_COP1R14_REGNUM:
case SIM_ARM_IWMMXT_COP1R15_REGNUM:
return Fetch_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory);
default:
return 0;
}
while (len)
{
tomem (state, memory, regval);
len -= 4;
memory += 4;
regval = 0;
}
return length;
}
typedef struct
{
char * swi_option;
unsigned int swi_mask;
} swi_options;
#define SWI_SWITCH "--swi-support"
static swi_options options[] =
{
{ "none", 0 },
{ "demon", SWI_MASK_DEMON },
{ "angel", SWI_MASK_ANGEL },
{ "redboot", SWI_MASK_REDBOOT },
{ "all", -1 },
{ "NONE", 0 },
{ "DEMON", SWI_MASK_DEMON },
{ "ANGEL", SWI_MASK_ANGEL },
{ "REDBOOT", SWI_MASK_REDBOOT },
{ "ALL", -1 }
};
static int
sim_target_parse_command_line (int argc, char ** argv)
{
int i;
for (i = 1; i < argc; i++)
{
char * ptr = argv[i];
int arg;
if ((ptr == NULL) || (* ptr != '-'))
break;
if (strcmp (ptr, "-t") == 0)
{
trace = 1;
continue;
}
if (strcmp (ptr, "-z") == 0)
{
/* Remove this option from the argv array. */
for (arg = i; arg < argc; arg ++)
{
free (argv[arg]);
argv[arg] = argv[arg + 1];
}
argc --;
i --;
trace_funcs = 1;
continue;
}
if (strcmp (ptr, "-d") == 0)
{
/* Remove this option from the argv array. */
for (arg = i; arg < argc; arg ++)
{
free (argv[arg]);
argv[arg] = argv[arg + 1];
}
argc --;
i --;
disas = 1;
continue;
}
if (strncmp (ptr, SWI_SWITCH, sizeof SWI_SWITCH - 1) != 0)
continue;
if (ptr[sizeof SWI_SWITCH - 1] == 0)
{
/* Remove this option from the argv array. */
for (arg = i; arg < argc; arg ++)
{
free (argv[arg]);
argv[arg] = argv[arg + 1];
}
argc --;
ptr = argv[i];
}
else
ptr += sizeof SWI_SWITCH;
swi_mask = 0;
while (* ptr)
{
int o;
for (o = ARRAY_SIZE (options); o--;)
if (strncmp (ptr, options[o].swi_option,
strlen (options[o].swi_option)) == 0)
{
swi_mask |= options[o].swi_mask;
ptr += strlen (options[o].swi_option);
if (* ptr == ',')
++ ptr;
break;
}
if (o < 0)
break;
}
if (* ptr != 0)
fprintf (stderr, "Ignoring swi options: %s\n", ptr);
/* Remove this option from the argv array. */
for (arg = i; arg < argc; arg ++)
{
free (argv[arg]);
argv[arg] = argv[arg + 1];
}
argc --;
i --;
}
return argc;
}
static void
sim_target_parse_arg_array (char ** argv)
{
sim_target_parse_command_line (countargv (argv), argv);
}
static sim_cia
arm_pc_get (sim_cpu *cpu)
{
return PC;
}
static void
arm_pc_set (sim_cpu *cpu, sim_cia pc)
{
ARMul_SetPC (state, pc);
}
static void
free_state (SIM_DESC sd)
{
if (STATE_MODULES (sd) != NULL)
sim_module_uninstall (sd);
sim_cpu_free_all (sd);
sim_state_free (sd);
}
SIM_DESC
sim_open (SIM_OPEN_KIND kind,
host_callback *cb,
struct bfd *abfd,
char * const *argv)
{
int i;
char **argv_copy;
SIM_DESC sd = sim_state_alloc (kind, cb);
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
/* Set default options before parsing user options. */
current_alignment = STRICT_ALIGNMENT;
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Check for/establish the a reference program image. */
if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Configure/verify the target byte order and other runtime
configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* CPU specific initialization. */
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
CPU_REG_FETCH (cpu) = arm_reg_fetch;
CPU_REG_STORE (cpu) = arm_reg_store;
CPU_PC_FETCH (cpu) = arm_pc_get;
CPU_PC_STORE (cpu) = arm_pc_set;
}
sim_callback = cb;
/* Copy over the argv contents so we can modify them. */
argv_copy = dupargv (argv);
sim_target_parse_arg_array (argv_copy);
if (argv_copy[1] != NULL)
{
/* Scan for memory-size switches. */
for (i = 0; (argv_copy[i] != NULL) && (argv_copy[i][0] != 0); i++)
if (argv_copy[i][0] == '-' && argv_copy[i][1] == 'm')
{
if (argv_copy[i][2] != '\0')
mem_size = atoi (&argv_copy[i][2]);
else if (argv_copy[i + 1] != NULL)
{
mem_size = atoi (argv_copy[i + 1]);
i++;
}
else
{
sim_callback->printf_filtered (sim_callback,
"Missing argument to -m option\n");
return NULL;
}
}
}
freeargv (argv_copy);
return sd;
}
void
sim_stop_reason (SIM_DESC sd ATTRIBUTE_UNUSED,
enum sim_stop *reason,
int *sigrc)
{
if (stop_simulator)
{
*reason = sim_stopped;
*sigrc = GDB_SIGNAL_INT;
}
else if (state->EndCondition == 0)
{
*reason = sim_exited;
*sigrc = state->Reg[0] & 255;
}
else
{
*reason = sim_stopped;
if (state->EndCondition == RDIError_BreakpointReached)
*sigrc = GDB_SIGNAL_TRAP;
else if ( state->EndCondition == RDIError_DataAbort
|| state->EndCondition == RDIError_AddressException)
*sigrc = GDB_SIGNAL_BUS;
else
*sigrc = 0;
}
}

58
sim/configure vendored
View file

@ -839,11 +839,6 @@ SIM_ENABLE_ARCH_avr_TRUE
CC_FOR_TARGET_AVR
LD_FOR_TARGET_AVR
AS_FOR_TARGET_AVR
SIM_ENABLE_ARCH_arm_FALSE
SIM_ENABLE_ARCH_arm_TRUE
CC_FOR_TARGET_ARM
LD_FOR_TARGET_ARM
AS_FOR_TARGET_ARM
SIM_ENABLE_ARCH_aarch64_FALSE
SIM_ENABLE_ARCH_aarch64_TRUE
CC_FOR_TARGET_AARCH64
@ -1067,9 +1062,6 @@ SDL_LIBS
AS_FOR_TARGET_AARCH64
LD_FOR_TARGET_AARCH64
CC_FOR_TARGET_AARCH64
AS_FOR_TARGET_ARM
LD_FOR_TARGET_ARM
CC_FOR_TARGET_ARM
AS_FOR_TARGET_AVR
LD_FOR_TARGET_AVR
CC_FOR_TARGET_AVR
@ -1900,12 +1892,6 @@ Some influential environment variables:
Linker for aarch64 tests
CC_FOR_TARGET_AARCH64
C compiler for aarch64 tests
AS_FOR_TARGET_ARM
Assembler for arm tests
LD_FOR_TARGET_ARM
Linker for arm tests
CC_FOR_TARGET_ARM
C compiler for arm tests
AS_FOR_TARGET_AVR
Assembler for avr tests
LD_FOR_TARGET_AVR
@ -12892,7 +12878,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
#line 12895 "configure"
#line 12881 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -12998,7 +12984,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
#line 13001 "configure"
#line 12987 "configure"
#include "confdefs.h"
#if HAVE_DLFCN_H
@ -15053,41 +15039,6 @@ else
SIM_ENABLE_ARCH_aarch64_FALSE=
fi
sim_enable_arch_arm=false
case "${targ}" in
all|arm*-*-*)
if test "${targ}" = "${target}"; then
SIM_PRIMARY_TARGET=arm
fi
ENABLE_SIM=yes
as_fn_append SIM_ENABLED_ARCHES " arm"
ac_config_files="$ac_config_files arm/.gdbinit:common/gdbinit.in"
sim_enable_arch_arm=true
;;
esac
if test "$SIM_PRIMARY_TARGET" = "arm"; then :
: "${AS_FOR_TARGET_ARM:=\$(AS_FOR_TARGET)}"
: "${LD_FOR_TARGET_ARM:=\$(LD_FOR_TARGET)}"
: "${CC_FOR_TARGET_ARM:=\$(CC_FOR_TARGET)}"
fi
as_fn_append SIM_TOOLCHAIN_VARS " AS_FOR_TARGET_ARM LD_FOR_TARGET_ARM CC_FOR_TARGET_ARM"
if ${sim_enable_arch_arm}; then
SIM_ENABLE_ARCH_arm_TRUE=
SIM_ENABLE_ARCH_arm_FALSE='#'
else
SIM_ENABLE_ARCH_arm_TRUE='#'
SIM_ENABLE_ARCH_arm_FALSE=
fi
sim_enable_arch_avr=false
case "${targ}" in
all|avr*-*-*)
@ -17655,10 +17606,6 @@ if test -z "${SIM_ENABLE_ARCH_aarch64_TRUE}" && test -z "${SIM_ENABLE_ARCH_aarch
as_fn_error $? "conditional \"SIM_ENABLE_ARCH_aarch64\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
if test -z "${SIM_ENABLE_ARCH_arm_TRUE}" && test -z "${SIM_ENABLE_ARCH_arm_FALSE}"; then
as_fn_error $? "conditional \"SIM_ENABLE_ARCH_arm\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
if test -z "${SIM_ENABLE_ARCH_avr_TRUE}" && test -z "${SIM_ENABLE_ARCH_avr_FALSE}"; then
as_fn_error $? "conditional \"SIM_ENABLE_ARCH_avr\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@ -18656,7 +18603,6 @@ do
"libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;;
"depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;;
"aarch64/.gdbinit") CONFIG_FILES="$CONFIG_FILES aarch64/.gdbinit:common/gdbinit.in" ;;
"arm/.gdbinit") CONFIG_FILES="$CONFIG_FILES arm/.gdbinit:common/gdbinit.in" ;;
"avr/.gdbinit") CONFIG_FILES="$CONFIG_FILES avr/.gdbinit:common/gdbinit.in" ;;
"bfin/.gdbinit") CONFIG_FILES="$CONFIG_FILES bfin/.gdbinit:common/gdbinit.in" ;;
"bpf/.gdbinit") CONFIG_FILES="$CONFIG_FILES bpf/.gdbinit:common/gdbinit.in" ;;

1
sim/configure.ac
View file

@ -96,7 +96,6 @@ if test "${enable_sim}" != no; then
do
m4_map([SIM_TARGET], [
[[aarch64*-*-*], [aarch64]],
[[arm*-*-*], [arm]],
[[avr*-*-*], [avr]],
[[bfin-*-*], [bfin]],
[[bpf-*-*], [bpf]],