PE/COFF stores symbol section numbers in a 16-bit field. Binutils used
signed 16-bit handling there, which limited normal PE objects to 32767
sections even though MSVC and Clang already accept a larger unsigned
range.
Raise the normal PE section limit to 65279, while keeping the PE/COFF
special section-number values for undefined, absolute and debug symbols
working correctly. Do this by decoding and encoding normal PE symbol
section numbers as unsigned values in the ordinary range, but preserving
the reserved PE constants explicitly.
Also add a gas test that exercises a normal PE object above the old
32767-section limit and checks that objdump reports the high section
number correctly.
bfd/ChangeLog:
* coffcode.h (COFF_DEFAULT_MAX_NSCNS): Define.
(bfd_coff_std_swap_table): Use it for the default maximum section
count.
(ticoff0_swap_table): Likewise.
(ticoff1_swap_table): Likewise.
* peXXigen.c (pe_decode_sym_section_number): New function.
(pe_encode_sym_section_number): New function.
(_bfd_XXi_swap_sym_in): Use pe_decode_sym_section_number.
(_bfd_XXi_swap_sym_out): Use pe_encode_sym_section_number.
include/ChangeLog:
* coff/pe.h (IMAGE_SYM_UNDEFINED): Define.
(IMAGE_SYM_ABSOLUTE): Define.
(IMAGE_SYM_DEBUG): Define.
(IMAGE_SYM_SECTION_MAX): Define.
gas/ChangeLog:
* testsuite/gas/pe/pe.exp: Run large-obj-normal.
* testsuite/gas/pe/large-obj-normal.s: New test.
* testsuite/gas/pe/large-obj-normal.d: New test.
Signed-off-by: Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
Commit 8bf4b69718 ("LoongArch: Fix relaxation alignment with ld -r (PR
33236)") has broken the kernel modules on Debian sid. The expectation
of the kernel is all the source files which would be linked into a
module are compiled with -mno-relax so the module should not contain
R_LARCH_ALIGN, thus the module loader rejects any module containing
R_LARCH_ALIGN.
To restore the correctness of the expectation, only insert the align
section if an input has R_LARCH_ALIGN or R_LARCH_ALIGN (i.e. bytes may
be removed from that input). Regardless of the kernel modules, it also
does not make too much sense to bloat the output with NOPs and
R_LARCH_ALIGN if no input ever contains R_LARCH_ALIGN and R_LARCH_ALIGN
anyway.
Signed-off-by: Xi Ruoyao <xry111@xry111.site>
H8/300H uses 32-bit addresses in its default advanced mode, whereas
H8/300 uses 16-bit addresses. Updates affected test cases accordingly.
bfd/
* cpu-h8300.c: Set H8/300H as the default architecture
for the H8 family.
gas/
* config/tc-h8300.c: Set H8/300H as the default architecture
for the H8 family.
* NEWS: Add info about the above change.
ld/
* configure.tgt: Set H8/300H as the default architecture
for the H8 family.
* NEWS: Add info about the above change.
* testsuite/ld-elf/elf.exp: Expect 32-bit addresses/pointers
for H8 on __patchable_function_entries tests.
Signed-off-by: Jan Dubiec <jdx@o2.pl>
Simplify R_LARCH_TLS_DTPREL32/64 relocations processing.
Return the offset to TLS block for symbol.
Change R_LARCH_TLS_DTPREL32/64 partial_inplace to false since
LoongArch uses RELA relocations.
The linker validates the arch of each input when parsing it, but never
checks the merged arch as a whole, so conflicting extensions could
silently slip through. The merge can even imply extensions that
neither input implies alone, e.g. `c' from one input and `d' from
another imply `zcd', which conflicts with `zcmp'.
After merging the input archs, add the implicit extensions to the
merged arch, then run the conflict checks on it and reject the merge
if any conflict is found. Add tests for such merges.
riscv_merge_arch_attr_info returned early on the error paths without
releasing in_subsets, out_subsets and merged_subsets, so the nodes
already added to them were leaked. The leaked nodes of in_subsets
and out_subsets also carry over into the next merge.
Route every post-parse error path through a single cleanup exit that
releases all three subset lists, and drop the now-redundant reset of
merged_subsets at entry.
PR 34131
* elf.c: Remove unnecessary casts on bfd_[zm]*alloc return value.
Do without "amt" temp var in a few cases.
(assign_section_numbers): Check for NULL return from bfd_zalloc.
(elfobj_grok_stapsdt_note_1): Likewise for bfd_alloc.
Correct sh_size and sh_entsize to use external reloc size.
loongarch32-elf +FAIL: Linkonce sections with assembler generated notes
loongarch32-elf +FAIL: ld-loongarch-elf/relax-align-ld-r
This patch avoids undefined behaviour and divide by zero exceptions in
some relocation processing. In most cases, unsigned arithmetic is
used which has defined overflow characteristics. Arithmetic right
shift, division, and modulo operations have more special cases. See
the explanation in commit 30200464e9.
* coff-alpha.c (alpha_ecoff_get_relocated_section_contents): Avoid
UB in RSHIFT reloc.
(alpha_relocate_section): Likewise.
* elf32-rl78.c (rl78_compute_complex_reloc): Avoid UB in reloc
arithmetic.
* elf32-rx.c (rx_elf_relocate_section): Likewise.
(rx_offset_for_reloc): Likewise.
The s390 32-bit target (s390-*) is deprecated and planned for removal
in a future release, along with the elf32-s390 target format. Emit an
error for this target during configure, which can be overridden using
option --enable-obsolete.
Linux Kernel 6.19 removed s390 32-bit compatibility support. [1]
Glibc 2.43 [2] and GCC 16.1 (compiler option -m31) [3] deprecated
s390 32-bit with the intent to remove it in a future release.
The s390 64-bit target (s390x-*) remains supported.
[1]: Linux kernel 6.19 commit 8e0b986c59c6 ("s390: Remove compat support"),
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8e0b986c59c6
[2]: Glibc 2.43 commit 638d437dbf9c ("Deprecate s390-linux-gnu (31bit)"),
https://sourceware.org/git/glibc.git?a=commitdiff;h=638d437dbf9c
[3]: GCC 16 commit 5886bb453a6a ("s390: Deprecate -m31"),
https://gcc.gnu.org/git/gcc.git?h=5886bb453a6a
bfd/
* config.bfd: Require --enable-obsolete to build s390 32-bit
target "s390-*".
binutils/
* NEWS: Deprecate s390 32-bit target "s390-*".
gdb/
* NEWS: Deprecate s390 32-bit target "s390-*".
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
LoongArch has the same issue as RISC-V for PR 33236 [1].
Section alignment can't be adjusted for objects generated by ld -r.
If previous sections are relaxed, the subsequent section maybe misaligned.
To fix this, add an align section and an align relocation before each
section when ld -r. And change the section alignment to 4 to disable
the default section start address calculation.
ld.lld has fixed this issue in the following two patches [2] [3].
[1] https://sourceware.org/bugzilla/show_bug.cgi?id=33236
[2] https://github.com/llvm/llvm-project/pull/151639
[3] https://github.com/llvm/llvm-project/pull/198147
When linking multiple objects, relaxation can cause alignment issues.
Input section's output_offset is updated in relaxation without considering
alignment. Update section output_offset by align_opwer.
This patch fixes some style nits:
- Fix indentations
- Using TABs for indentation
- Breaking long lines
- Remove ; after the closing } of a code block
bfd/
* cpu-avr.c: Adhere to GNU coding style.
* elf32-avr.c: Same.
* elf32-avr.h: Same.
gas/
* config/tc-avr.c: Adhere to GNU coding style.
opcodes/
* avr-dis.c: Adhere to GNU coding style.
include/
* opcode/avr.h: Adhere to GNU coding style.
The private header ('-p') import table output for pe-aarch64 (and
probably all other 64-bit arches apart from x86_64) is truncated after the
first import.
The distinction between the conditional branches here should be between
PE32 (32-bit) and PE32+ (somewhat confusingly, the 64-bit version of the
PE format).
PE file format specification [1] states under "Import Lookup Table":
"An import lookup table is an array of 32-bit numbers for PE32 or an
array of 64-bit numbers for PE32+."
[1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#import-lookup-table
2026-06-19 Jon Turney <jon.turney@dronecode.org.uk>
* peXXigen.c (pe_print_idata): Fix conditional.
I don't claim to have caught all places where reloc special functions
don't sanity check input, but this should be most of them. Hopefully
this does not expose odd reloc howto entries like the mmix one in the
previous patch.
* coff-arm.c (aoutarm_fix_pcrel_26): Sanity check reloc offset.
Remove some unnecessary casts.
(coff_thumb_pcrel_common): Likewise.
* coff-mips.c (mips_generic_reloc): Remove unnecessary casts.
(mips_refhi_reloc): Likewise.
(mips_gprel_reloc): Likewise. Use bfd_reloc_offset_in_range.
* cpu-ns32k.c (do_ns32k_reloc): Likewise.
* elf32-m68hc1x.c (m68hc11_elf_special_reloc): Likewise. Don't
abort, return notsupported instead.
* elf32-pj.c (pj_elf_reloc): Sanity check reloc offset.
* elf32-pru.c (pru_elf32_do_s10_pcrel_relocate): Update reloc
offset sanity check.
(pru_elf32_do_ldi32_relocate): Likewise.
* elf32-s390.c (s390_elf_ldisp_reloc): Use bfd_reloc_offset_in_range.
Remove unnecessary casts.
* elf32-score7.c (score_elf_got_lo16_reloc): Remove redundant old
reloc offset sanity check.
* elf32-sh.c (sh_elf_reloc): Use bfd_reloc_offset_in_range.
* elf32-v850.c (v850_elf_reloc): Likewise.
As per the PR, s12z lacked any reloc offset sanity checking, the
others all just checked that the offset started within the section
rather than checking the field was contained in the section.
Using the proper check for mmix exposed a problem in the howto table,
present since the initial mmix commit. The R_MMIX_BASE_PLUS_OFFSET
field is actually two bytes, located at the reloc address. Making it
an eight byte field is just wrong, as doing that indicates the field
is at the reloc address plus six bytes for a big-endian target.
Presumably this was done for overlow reporting, which is properly done
by appropriately setting complain_on_overflow.
* elf32-d30v.c (bfd_elf_d30v_reloc, bfd_elf_d30v_reloc_21): Use
bfd_reloc_offset_in_range
* elf32-s12z.c (opru18_reloc): Likewise.
* elf32-spu.c (spu_elf_rel9): Likewise.
* elf32-xstormy16.c (xstormy16_elf_24_reloc): Likewise.
* elf32-visium.c (visium_elf_howto_parity_reloc): Likewise.
Remove unnecessary casts too.
* elf64-s390.c (s390_elf_ldisp_reloc): Likewise.
* elfxx-sparc.c (init_insn_reloc): Likewise.
* elf64-mmix.c (mmix_elf_reloc): Likewise. Remove unnecessary
variable too.
(elf_mmix_howto_table[R_MMIX_BASE_PLUS_OFFSET]): Correct size,
bitsize and complain_on_overflow.
PE weak externals are canonicalized as undefined BFD symbols, even
when their auxiliary entry names a real fallback definition in the same
object. Archive map generation therefore skipped the public weak name,
so a strong undefined reference to that name could not extract the
archive member.
Include such PE weak externals in the archive map, but only when the
fallback is a real definition rather than the absolute-zero null symbol
used for weak declarations with no fallback. Also avoid extracting an
archive member again during repeated archive searches once the weak
external resolves through a defined fallback.
Fixes: https://gcc.gnu.org/PR124263
bfd/
* archive.c: Include coff-bfd.h.
(_bfd_compute_and_push_armap): Include PE weak externals in
the archive map when their fallback is a real definition.
* coff-bfd.c (bfd_coff_pe_weak_external_has_real_fallback): New
function.
* coff-bfd.h (bfd_coff_pe_weak_external_has_real_fallback):
Declare.
* cofflink.c (coff_link_hash_pe_weak_external_has_real_fallback):
New function.
(coff_link_check_archive_element): Avoid extracting an archive
member again for a PE weak external whose real fallback is
already defined.
When two PE COFF weak externals for the same symbol are linked (both
C_NT_WEAK with aux records), the generic linker takes no action on the
second one (NOACT: weak undef meets existing weak undef). This means
the first file's fallback alias always wins regardless of whether it
points to a real definition or to NULL.
This causes a problem when a weak declaration (fallback = NULL,
i.e. "resolve to NULL if nothing provides it") is linked before a
weak definition (fallback = actual function body). The symbol resolves
to address 0 at runtime, causing a crash when called.
Fix this by comparing the fallback targets when two weak externals
meet: if the incoming weak external's fallback resolves to a defined
symbol and the existing one does not (or points to NULL),
update the aux record to use the better fallback.
This matches the behavior of lld after:
7ca5698b4c
bfd/
* cofflink.c (coff_link_add_symbols): When two PE COFF weak
externals meet, prefer the one whose fallback alias resolves
to a defined symbol.
When linking PE-COFF objects, a weak external symbol (C_NT_WEAK with an
aux record specifying a fallback alias) may fail to resolve if a strong
undefined reference to the same symbol is encountered before the weak
definition. This causes "undefined reference" errors for symbols like
operator new or personality routines that GCC emits as weak externals
with a fallback to a default implementation.
There are two problems:
1. In coff_link_add_symbols, when the generic linker resolves a weak
undefined against an existing strong undefined (NOACT in the action
table), the COFF-specific symbol_class and aux record were not stored
because the existing hash entry already had non-null class/type from
the first (strong) object file.
2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
triggered for bfd_link_hash_undefweak symbols. When a strong undef
is seen first, the hash type stays bfd_link_hash_undefined (the
generic linker does not downgrade it), so the fallback was skipped.
Fix by extending the condition in coff_link_add_symbols to also update
symbol_class and aux when the incoming symbol is a PE weak external
with aux and the existing hash is still undefined. Also extend the
relocation handler to resolve the weak alias fallback for
bfd_link_hash_undefined symbols that carry C_NT_WEAK class and have
an aux record.
bfd/
* cofflink.c (coff_link_add_symbols): Also store symbol_class
and aux record when a PE weak external with aux meets an
existing undefined hash entry.
(_bfd_coff_generic_relocate_section): Also resolve weak alias
fallback for undefined symbols with C_NT_WEAK class and aux.
This patch supports the RISC-V Zvbdota family of batched dot-product
extensions [1].
Compared to the non-batched Zvdota family, Zvbdota computes up to eight
dot products at a time. These instructions use an EMUL=8 `vs2` vector
register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
This patch adds assembler/disassembler support for those additional
operand constraints.
The Zvbdota extension family includes the following extensions:
* Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
accumulation.
* Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
accumulation.
* Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
with 32-bit accumulation.
* Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
32-bit accumulation.
* Zvfbdota32f: batched dot product of 32-bit single-precision
floating-point numbers with 32-bit accumulation.
[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): New implies.
(riscv_supported_std_z_ext): New extensions.
(riscv_multi_subset_supports): Ditto.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
zvfqwbdota8f and zvfbdota32f extensions.
* config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
type 'q' and 'r' bits validation.
(riscv_vtype_altfmt_supported): Add Zvbdota extensions.
(my_getVsetvliExpression): Update altfmt error message.
(riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
and 'r' operand for ci immediate.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvbdota.d: New test.
* testsuite/gas/riscv/zvbdota.s: Ditto.
* testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
* testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
* testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
* testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
* testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
New encoding.
(MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
(MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
(MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
(MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
(MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (enum riscv_insn_class): New extension classes.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
for Zvbdota.
* riscv-opc.c (riscv_opcodes): New instructions.
Zvfqwdota8f: dot product of 8-bit floating-point numbers with 32-bit accumulation.
Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8 of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew constants for vsetvli/vsetivli so that assembly code can select the alternative element formats required by these dot-product instructions.
[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): New implies.
(riscv_supported_std_z_ext): New extensions.
(riscv_multi_subset_supports): Ditto.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
zvfqwdota8f extensions.
* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
constants array for e8alt and e16alt.
(riscv_vtype_altfmt_supported): New function.
(my_getVsetvliExpression): Ditto.
* testsuite/gas/riscv/march-help.l: New test.
* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
* testsuite/gas/riscv/zvdota.d: Ditto.
* testsuite/gas/riscv/zvdota.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New encoding.
(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
(DECLARE_INSN): New declarations.
* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT): New vtype altfmt.
(enum riscv_insn_class): New extension classes.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Add altfmt support.
* riscv-opc.c (riscv_opcodes): New instructions.
PE/COFF object files use 16-bit section numbers in normal symbols.
When an object grows past that limit, current BFD already rejects it with
a "too many sections" / "file too big" error.
BFD already has PE bigobj targets for the backends that support them, but
oversized PE/COFF output still requires selecting bigobj explicitly.
Teach coff_compute_section_file_positions to switch PE/COFF output to the
corresponding bigobj target when the normal section-number limit is
exceeded. This preserves the existing hard error for targets without
bigobj support, but lets supported PE targets transparently emit a valid
bigobj object instead of requiring manual selection.
bfd/
* coffcode.h (coff_compute_section_file_positions): Auto-promote
oversized PE/COFF objects to the bigobj target.
gas/
* testsuite/gas/pe/big-obj-auto.d: New test.
* testsuite/gas/pe/big-obj-auto.s: New test.
* testsuite/gas/pe/pe.exp: Run big-obj-auto.
Signed-off-by: Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
bfd/configure.host defines CP_ACP=1 on Solaris 11 as a workaround for
the lack the MS-ANSI codepage in Solaris libc iconv(3C). However, the
issue isn't restricted to some OpenSolaris build as the comment
suggests, but present on Solaris in general as can be seen in the iconv -l
output:
On both Solaris 10 and 11.4, one gets
CP1252 (1252, ANSI-1252, WINDOWS-1252),
unlike GNU iconv which lists
CP1252 MS-ANSI WINDOWS-1252
Therefore, this patch applies the patch on all Solaris versions.
Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.
2026-06-28 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
bfd:
PR binutils/11280
* configure.host (HDEFINES): Always define CP_ACP=1 on Solaris.
After the removal of all Solaris configurations but Solaris 10/11
(*-*-solaris2.1[01]), the 32-bit-only configurations can no longer be
matched. This patch removes them.
Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.
2026-06-28 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
bfd:
* config.bfd <i[3-7]86-*-solaris*>: Remove.
<sparc*-*-solaris*>: Likewise.
ld:
* configure.tgt <i[3-7]86-*-solaris*>: Remove.
<sparc*-*-solaris*>: Likewise.
