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Oleg Endo 17eb89e3c1 sim/sh: check PFSCR.PR setting for fldi0 and fldi1 insns 
On SH variants with double-precision FPU the insns fli0 and flid1 are only
defined when FPSCR.PR = 0.  The hardware does not necessarily trap but might
quietly load undefined values.  However, qemu traps in that case, so do the
same.
2026-03-17 13:49:37 +09:00
..
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
gencode.c sim/sh: check PFSCR.PR setting for fldi0 and fldi1 insns 2026-03-17 13:49:37 +09:00
interp.c Fix missing int argument warning 2025-03-07 10:32:39 +01:00
local.mk Update copyright dates to include 2026 2026-01-05 13:16:46 -07:00
sh-sim.h Update copyright dates to include 2026 2026-01-05 13:16:46 -07:00
sim-main.h Update copyright dates to include 2026 2026-01-05 13:16:46 -07:00