binutils-gdb/sim/example-synacor
Tom Tromey d01e823438 Update copyright dates to include 2025
This updates the copyright headers to include 2025.  I did this by
running gdb/copyright.py and then manually modifying a few files as
noted by the script.

Approved-By: Eli Zaretskii <eliz@gnu.org>
2025-04-08 10:54:39 -06:00
..
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
example-synacor-sim.h Update copyright dates to include 2025 2025-04-08 10:54:39 -06:00
interp.c Update copyright dates to include 2025 2025-04-08 10:54:39 -06:00
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README
README.arch-spec
sim-main.c Update copyright dates to include 2025 2025-04-08 10:54:39 -06:00
sim-main.h Update copyright dates to include 2025 2025-04-08 10:54:39 -06:00

= OVERVIEW =

The Synacor Challenge is a fun programming exercise with a number of puzzles
built into it.  You can find more details about it here:
https://challenge.synacor.com/

The first puzzle is writing an interpreter for their custom ISA.  This is a
simulator for that custom CPU.  The CPU is quite basic: it's 16-bit with only
8 registers and a limited set of instructions.  This means the port will never
grow new features.  See README.arch-spec for more details.

Implementing it here ends up being quite useful: it acts as a simple constrained
"real world" example for people who want to implement a new simulator for their
own architecture.  We demonstrate all the basic fundamentals (registers, memory,
branches, and tracing) that all ports should have.